sesto_reg_structs.h (648782B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 8 /*================================================================*/ 9 /* Automatically Generated by rdbHC.sh */ 10 /* - Do Not Edit - */ 11 /*================================================================*/ 12 #ifndef chip_reg_structs__H 13 #define chip_reg_structs__H 14 15 #ifdef BE_HOST 16 #define IS_BIG_ENDIAN (1) 17 #define IS_LITTLE_ENDIAN (0) 18 #else 19 #define IS_BIG_ENDIAN (0) 20 #define IS_LITTLE_ENDIAN (1) 21 #endif 22 23 /*-----------------------------------------------*/ 24 /* Structs for IEEE_PMA_PMD_BLK0 Bank */ 25 /*-----------------------------------------------*/ 26 typedef union { 27 uint32_t data; 28 struct { 29 #if IS_BIG_ENDIAN 30 uint32_t reserved : 16; 31 uint32_t reset : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[15] - SC */ 32 uint32_t reserved_14 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[14] - RSVD */ 33 uint32_t speed_selectionlsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[13] - WO */ 34 uint32_t reserved_12 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[12] - RSVD */ 35 uint32_t power_down : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[11] - WO */ 36 uint32_t reserved_07 : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[10:07] - RSVD */ 37 uint32_t speed_selectionmsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[06] - WO */ 38 uint32_t speed_selection : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[05:02] - WO */ 39 uint32_t pma_remote_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[01] - WO */ 40 uint32_t pma_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[00] - WO */ 41 #endif /* IS_BIG_ENDIAN */ 42 #if IS_LITTLE_ENDIAN 43 uint32_t pma_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[00] - WO */ 44 uint32_t pma_remote_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[01] - WO */ 45 uint32_t speed_selection : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[05:02] - WO */ 46 uint32_t speed_selectionmsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[06] - WO */ 47 uint32_t reserved_07 : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[10:07] - RSVD */ 48 uint32_t power_down : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[11] - WO */ 49 uint32_t reserved_12 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[12] - RSVD */ 50 uint32_t speed_selectionlsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[13] - WO */ 51 uint32_t reserved_14 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[14] - RSVD */ 52 uint32_t reset : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE[15] - SC */ 53 uint32_t reserved : 16; 54 #endif /* IS_LITTLE_ENDIAN */ 55 } fields; 56 } IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE; 57 58 typedef IEEE_PMA_PMD_BLK0_pmd_control_register_TYPE IEEE_PMA_PMD_BLK0_PMD_CONTROL_REGISTER_TYPE_T; 59 60 typedef union { 61 uint32_t data; 62 struct { 63 #if IS_BIG_ENDIAN 64 uint32_t reserved : 16; 65 uint32_t reserved_08 : 8; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[15:08] - RSVD */ 66 uint32_t fault : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[07] - RO */ 67 uint32_t reserved_03 : 4; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[06:03] - RSVD */ 68 uint32_t reserved_02 : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[02] - RSVD */ 69 uint32_t low_power_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[01] - RO */ 70 uint32_t reserved_00 : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[00] - RSVD */ 71 #endif /* IS_BIG_ENDIAN */ 72 #if IS_LITTLE_ENDIAN 73 uint32_t reserved_00 : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[00] - RSVD */ 74 uint32_t low_power_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[01] - RO */ 75 uint32_t reserved_02 : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[02] - RSVD */ 76 uint32_t reserved_03 : 4; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[06:03] - RSVD */ 77 uint32_t fault : 1; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[07] - RO */ 78 uint32_t reserved_08 : 8; /* IEEE_PMA_PMD_BLK0_status_register_TYPE[15:08] - RSVD */ 79 uint32_t reserved : 16; 80 #endif /* IS_LITTLE_ENDIAN */ 81 } fields; 82 } IEEE_PMA_PMD_BLK0_status_register_TYPE; 83 84 typedef IEEE_PMA_PMD_BLK0_status_register_TYPE IEEE_PMA_PMD_BLK0_STATUS_REGISTER_TYPE_T; 85 86 typedef union { 87 uint32_t data; 88 struct { 89 #if IS_BIG_ENDIAN 90 uint32_t reserved : 16; 91 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_TYPE[15:00] - RO */ 92 #endif /* IS_BIG_ENDIAN */ 93 #if IS_LITTLE_ENDIAN 94 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_TYPE[15:00] - RO */ 95 uint32_t reserved : 16; 96 #endif /* IS_LITTLE_ENDIAN */ 97 } fields; 98 } IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_TYPE; 99 100 typedef IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_TYPE IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_0_TYPE_T; 101 102 typedef union { 103 uint32_t data; 104 struct { 105 #if IS_BIG_ENDIAN 106 uint32_t reserved : 16; 107 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_TYPE[15:00] - RO */ 108 #endif /* IS_BIG_ENDIAN */ 109 #if IS_LITTLE_ENDIAN 110 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_TYPE[15:00] - RO */ 111 uint32_t reserved : 16; 112 #endif /* IS_LITTLE_ENDIAN */ 113 } fields; 114 } IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_TYPE; 115 116 typedef IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_TYPE IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_1_TYPE_T; 117 118 typedef union { 119 uint32_t data; 120 struct { 121 #if IS_BIG_ENDIAN 122 uint32_t reserved : 16; 123 uint32_t reserved_10 : 6; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[15:10] - RSVD */ 124 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[09] - RSVD */ 125 uint32_t fortyg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[08] - RO */ 126 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[07:05] - RSVD */ 127 uint32_t oneg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[04] - RO */ 128 uint32_t reserved_01 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[03:01] - RSVD */ 129 uint32_t teng_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[00] - RO */ 130 #endif /* IS_BIG_ENDIAN */ 131 #if IS_LITTLE_ENDIAN 132 uint32_t teng_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[00] - RO */ 133 uint32_t reserved_01 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[03:01] - RSVD */ 134 uint32_t oneg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[04] - RO */ 135 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[07:05] - RSVD */ 136 uint32_t fortyg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[08] - RO */ 137 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[09] - RSVD */ 138 uint32_t reserved_10 : 6; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE[15:10] - RSVD */ 139 uint32_t reserved : 16; 140 #endif /* IS_LITTLE_ENDIAN */ 141 } fields; 142 } IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE; 143 144 typedef IEEE_PMA_PMD_BLK0_pmd_speed_ability_TYPE IEEE_PMA_PMD_BLK0_PMD_SPEED_ABILITY_TYPE_T; 145 146 typedef union { 147 uint32_t data; 148 struct { 149 #if IS_BIG_ENDIAN 150 uint32_t reserved : 16; 151 uint32_t reserved_12 : 4; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[15:12] - RSVD */ 152 uint32_t seperate_pma_4_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[11] - RO */ 153 uint32_t seperate_pma_3_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[10] - RO */ 154 uint32_t seperate_pma_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[09] - RO */ 155 uint32_t seperate_pma_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[08] - RO */ 156 uint32_t an_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[07] - RO */ 157 uint32_t tc_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[06] - RO */ 158 uint32_t dte_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[05] - RO */ 159 uint32_t phy_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[04] - RO */ 160 uint32_t pcs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[03] - RO */ 161 uint32_t wis_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[02] - RO */ 162 uint32_t pmd_pma_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[01] - RO */ 163 uint32_t clause_22registers_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[00] - RO */ 164 #endif /* IS_BIG_ENDIAN */ 165 #if IS_LITTLE_ENDIAN 166 uint32_t clause_22registers_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[00] - RO */ 167 uint32_t pmd_pma_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[01] - RO */ 168 uint32_t wis_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[02] - RO */ 169 uint32_t pcs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[03] - RO */ 170 uint32_t phy_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[04] - RO */ 171 uint32_t dte_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[05] - RO */ 172 uint32_t tc_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[06] - RO */ 173 uint32_t an_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[07] - RO */ 174 uint32_t seperate_pma_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[08] - RO */ 175 uint32_t seperate_pma_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[09] - RO */ 176 uint32_t seperate_pma_3_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[10] - RO */ 177 uint32_t seperate_pma_4_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[11] - RO */ 178 uint32_t reserved_12 : 4; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE[15:12] - RSVD */ 179 uint32_t reserved : 16; 180 #endif /* IS_LITTLE_ENDIAN */ 181 } fields; 182 } IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE; 183 184 typedef IEEE_PMA_PMD_BLK0_devices_in_package_1_TYPE IEEE_PMA_PMD_BLK0_DEVICES_IN_PACKAGE_1_TYPE_T; 185 186 typedef union { 187 uint32_t data; 188 struct { 189 #if IS_BIG_ENDIAN 190 uint32_t reserved : 16; 191 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[15] - RO */ 192 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[14] - RO */ 193 uint32_t clause_22extension_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[13] - RO */ 194 uint32_t reserved_00 : 13; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[12:00] - RSVD */ 195 #endif /* IS_BIG_ENDIAN */ 196 #if IS_LITTLE_ENDIAN 197 uint32_t reserved_00 : 13; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[12:00] - RSVD */ 198 uint32_t clause_22extension_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[13] - RO */ 199 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[14] - RO */ 200 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE[15] - RO */ 201 uint32_t reserved : 16; 202 #endif /* IS_LITTLE_ENDIAN */ 203 } fields; 204 } IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE; 205 206 typedef IEEE_PMA_PMD_BLK0_devices_in_package_2_TYPE IEEE_PMA_PMD_BLK0_DEVICES_IN_PACKAGE_2_TYPE_T; 207 208 typedef union { 209 uint32_t data; 210 struct { 211 #if IS_BIG_ENDIAN 212 uint32_t reserved : 16; 213 uint32_t reserved_06 : 10; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_TYPE[15:06] - RSVD */ 214 uint32_t pma_typeselection : 6; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_TYPE[05:00] - WO */ 215 #endif /* IS_BIG_ENDIAN */ 216 #if IS_LITTLE_ENDIAN 217 uint32_t pma_typeselection : 6; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_TYPE[05:00] - WO */ 218 uint32_t reserved_06 : 10; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_TYPE[15:06] - RSVD */ 219 uint32_t reserved : 16; 220 #endif /* IS_LITTLE_ENDIAN */ 221 } fields; 222 } IEEE_PMA_PMD_BLK0_pmd_control_2_register_TYPE; 223 224 typedef IEEE_PMA_PMD_BLK0_pmd_control_2_register_TYPE IEEE_PMA_PMD_BLK0_PMD_CONTROL_2_REGISTER_TYPE_T; 225 226 typedef union { 227 uint32_t data; 228 struct { 229 #if IS_BIG_ENDIAN 230 uint32_t reserved : 16; 231 uint32_t device_present : 2; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[15:14] - RO */ 232 uint32_t transmit_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[13] - RO */ 233 uint32_t receive_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[12] - RO */ 234 uint32_t transmit_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[11] - LH */ 235 uint32_t receive_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[10] - LH */ 236 uint32_t extended_abilities : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[09] - RO */ 237 uint32_t pmd_transmitdisable_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[08] - RO */ 238 uint32_t tengbase_sr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[07] - RO */ 239 uint32_t tengbase_lr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[06] - RO */ 240 uint32_t tengbase_er_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[05] - RO */ 241 uint32_t tengbase_lx4_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[04] - RO */ 242 uint32_t tengbase_sw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[03] - RO */ 243 uint32_t tengbase_lw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[02] - RO */ 244 uint32_t tengbase_ew_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[01] - RO */ 245 uint32_t pma_local_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[00] - RO */ 246 #endif /* IS_BIG_ENDIAN */ 247 #if IS_LITTLE_ENDIAN 248 uint32_t pma_local_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[00] - RO */ 249 uint32_t tengbase_ew_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[01] - RO */ 250 uint32_t tengbase_lw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[02] - RO */ 251 uint32_t tengbase_sw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[03] - RO */ 252 uint32_t tengbase_lx4_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[04] - RO */ 253 uint32_t tengbase_er_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[05] - RO */ 254 uint32_t tengbase_lr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[06] - RO */ 255 uint32_t tengbase_sr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[07] - RO */ 256 uint32_t pmd_transmitdisable_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[08] - RO */ 257 uint32_t extended_abilities : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[09] - RO */ 258 uint32_t receive_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[10] - LH */ 259 uint32_t transmit_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[11] - LH */ 260 uint32_t receive_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[12] - RO */ 261 uint32_t transmit_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[13] - RO */ 262 uint32_t device_present : 2; /* IEEE_PMA_PMD_BLK0_status_register_2_TYPE[15:14] - RO */ 263 uint32_t reserved : 16; 264 #endif /* IS_LITTLE_ENDIAN */ 265 } fields; 266 } IEEE_PMA_PMD_BLK0_status_register_2_TYPE; 267 268 typedef IEEE_PMA_PMD_BLK0_status_register_2_TYPE IEEE_PMA_PMD_BLK0_STATUS_REGISTER_2_TYPE_T; 269 270 typedef union { 271 uint32_t data; 272 struct { 273 #if IS_BIG_ENDIAN 274 uint32_t reserved : 16; 275 uint32_t reserved_11 : 5; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[15:11] - RSVD */ 276 uint32_t pmd_transmitdisable_9 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[10] - WO */ 277 uint32_t pmd_transmitdisable_8 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[09] - WO */ 278 uint32_t pmd_transmitdisable_7 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[08] - WO */ 279 uint32_t pmd_transmitdisable_6 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[07] - WO */ 280 uint32_t pmd_transmitdisable_5 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[06] - WO */ 281 uint32_t pmd_transmitdisable_4 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[05] - WO */ 282 uint32_t pmd_transmitdisable_3 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[04] - WO */ 283 uint32_t pmd_transmitdisable_2 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[03] - WO */ 284 uint32_t pmd_transmitdisable_1 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[02] - WO */ 285 uint32_t pmd_transmitdisable_0 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[01] - WO */ 286 uint32_t global_pmdtransmit_disable : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[00] - WO */ 287 #endif /* IS_BIG_ENDIAN */ 288 #if IS_LITTLE_ENDIAN 289 uint32_t global_pmdtransmit_disable : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[00] - WO */ 290 uint32_t pmd_transmitdisable_0 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[01] - WO */ 291 uint32_t pmd_transmitdisable_1 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[02] - WO */ 292 uint32_t pmd_transmitdisable_2 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[03] - WO */ 293 uint32_t pmd_transmitdisable_3 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[04] - WO */ 294 uint32_t pmd_transmitdisable_4 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[05] - WO */ 295 uint32_t pmd_transmitdisable_5 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[06] - WO */ 296 uint32_t pmd_transmitdisable_6 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[07] - WO */ 297 uint32_t pmd_transmitdisable_7 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[08] - WO */ 298 uint32_t pmd_transmitdisable_8 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[09] - WO */ 299 uint32_t pmd_transmitdisable_9 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[10] - WO */ 300 uint32_t reserved_11 : 5; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE[15:11] - RSVD */ 301 uint32_t reserved : 16; 302 #endif /* IS_LITTLE_ENDIAN */ 303 } fields; 304 } IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE; 305 306 typedef IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_TYPE IEEE_PMA_PMD_BLK0_PMD_TRANSMIT_DISABLE_REGISTER_TYPE_T; 307 308 typedef union { 309 uint32_t data; 310 struct { 311 #if IS_BIG_ENDIAN 312 uint32_t reserved : 16; 313 uint32_t reserved_11 : 5; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[15:11] - RSVD */ 314 uint32_t fortygbase_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[10] - RO */ 315 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[09] - RSVD */ 316 uint32_t tenbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[08] - RO */ 317 uint32_t hundredbase_tx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[07] - RO */ 318 uint32_t gigbase_kx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[06] - RO */ 319 uint32_t gigbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[05] - RO */ 320 uint32_t tengbase_kr_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[04] - RO */ 321 uint32_t tengbase_kx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[03] - RO */ 322 uint32_t tengbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[02] - RO */ 323 uint32_t tengbase_lrm_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[01] - RO */ 324 uint32_t tengbase_cx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[00] - RO */ 325 #endif /* IS_BIG_ENDIAN */ 326 #if IS_LITTLE_ENDIAN 327 uint32_t tengbase_cx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[00] - RO */ 328 uint32_t tengbase_lrm_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[01] - RO */ 329 uint32_t tengbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[02] - RO */ 330 uint32_t tengbase_kx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[03] - RO */ 331 uint32_t tengbase_kr_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[04] - RO */ 332 uint32_t gigbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[05] - RO */ 333 uint32_t gigbase_kx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[06] - RO */ 334 uint32_t hundredbase_tx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[07] - RO */ 335 uint32_t tenbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[08] - RO */ 336 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[09] - RSVD */ 337 uint32_t fortygbase_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[10] - RO */ 338 uint32_t reserved_11 : 5; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE[15:11] - RSVD */ 339 uint32_t reserved : 16; 340 #endif /* IS_LITTLE_ENDIAN */ 341 } fields; 342 } IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE; 343 344 typedef IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_TYPE IEEE_PMA_PMD_BLK0_PMD_EXTENDED_ABILITY_REGISTER_TYPE_T; 345 346 typedef union { 347 uint32_t data; 348 struct { 349 #if IS_BIG_ENDIAN 350 uint32_t reserved : 16; 351 uint32_t pma_remote_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[15] - RO */ 352 uint32_t one_hundredgbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[14] - RO */ 353 uint32_t one_hundredgbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[13] - RO */ 354 uint32_t one_hundredgbase_kp4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[12] - RO */ 355 uint32_t one_hundredgbase_er4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[11] - RO */ 356 uint32_t one_hundredgbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[10] - RO */ 357 uint32_t one_hundredgbase_sr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[09] - RO */ 358 uint32_t one_hundredgbase_cr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[08] - RO */ 359 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[07:05] - RSVD */ 360 uint32_t fortygbase_fr_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[04] - RO */ 361 uint32_t fortygbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[03] - RO */ 362 uint32_t fortygbase_sr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[02] - RO */ 363 uint32_t fortygbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[01] - RO */ 364 uint32_t fortygbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[00] - RO */ 365 #endif /* IS_BIG_ENDIAN */ 366 #if IS_LITTLE_ENDIAN 367 uint32_t fortygbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[00] - RO */ 368 uint32_t fortygbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[01] - RO */ 369 uint32_t fortygbase_sr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[02] - RO */ 370 uint32_t fortygbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[03] - RO */ 371 uint32_t fortygbase_fr_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[04] - RO */ 372 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[07:05] - RSVD */ 373 uint32_t one_hundredgbase_cr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[08] - RO */ 374 uint32_t one_hundredgbase_sr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[09] - RO */ 375 uint32_t one_hundredgbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[10] - RO */ 376 uint32_t one_hundredgbase_er4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[11] - RO */ 377 uint32_t one_hundredgbase_kp4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[12] - RO */ 378 uint32_t one_hundredgbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[13] - RO */ 379 uint32_t one_hundredgbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[14] - RO */ 380 uint32_t pma_remote_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE[15] - RO */ 381 uint32_t reserved : 16; 382 #endif /* IS_LITTLE_ENDIAN */ 383 } fields; 384 } IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE; 385 386 typedef IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_TYPE IEEE_PMA_PMD_BLK0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_TYPE_T; 387 388 typedef union { 389 uint32_t data; 390 struct { 391 #if IS_BIG_ENDIAN 392 uint32_t reserved : 16; 393 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_TYPE[15:00] - RO */ 394 #endif /* IS_BIG_ENDIAN */ 395 #if IS_LITTLE_ENDIAN 396 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_TYPE[15:00] - RO */ 397 uint32_t reserved : 16; 398 #endif /* IS_LITTLE_ENDIAN */ 399 } fields; 400 } IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_TYPE; 401 402 typedef IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_TYPE IEEE_PMA_PMD_BLK0_PMD_OUI_ID0_REGISTER_TYPE_T; 403 404 typedef union { 405 uint32_t data; 406 struct { 407 #if IS_BIG_ENDIAN 408 uint32_t reserved : 16; 409 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_TYPE[15:00] - RO */ 410 #endif /* IS_BIG_ENDIAN */ 411 #if IS_LITTLE_ENDIAN 412 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_TYPE[15:00] - RO */ 413 uint32_t reserved : 16; 414 #endif /* IS_LITTLE_ENDIAN */ 415 } fields; 416 } IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_TYPE; 417 418 typedef IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_TYPE IEEE_PMA_PMD_BLK0_PMD_OUI_ID1_REG_TYPE_T; 419 420 421 /*-----------------------------------------------*/ 422 /* Structs for M10G_CL72_IEEE_TX Bank */ 423 /*-----------------------------------------------*/ 424 typedef union { 425 uint32_t data; 426 struct { 427 #if IS_BIG_ENDIAN 428 uint32_t reserved : 16; 429 uint32_t reserved_02 : 14; /* M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE[15:02] - RSVD */ 430 uint32_t training_enable : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE[01] - RW */ 431 uint32_t restart_training : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE[00] - SC */ 432 #endif /* IS_BIG_ENDIAN */ 433 #if IS_LITTLE_ENDIAN 434 uint32_t restart_training : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE[00] - SC */ 435 uint32_t training_enable : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE[01] - RW */ 436 uint32_t reserved_02 : 14; /* M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE[15:02] - RSVD */ 437 uint32_t reserved : 16; 438 #endif /* IS_LITTLE_ENDIAN */ 439 } fields; 440 } M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE; 441 442 typedef M10G_CL72_IEEE_TX_BASE_R_PMD_control_register_150_TYPE M10G_CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_TYPE_T; 443 444 typedef union { 445 uint32_t data; 446 struct { 447 #if IS_BIG_ENDIAN 448 uint32_t reserved : 16; 449 uint32_t reserved_04 : 12; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[15:04] - RSVD */ 450 uint32_t training_failure : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[03] - RO */ 451 uint32_t training_status : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[02] - RO */ 452 uint32_t frame_lock : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[01] - RO */ 453 uint32_t receiver_status : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[00] - RO */ 454 #endif /* IS_BIG_ENDIAN */ 455 #if IS_LITTLE_ENDIAN 456 uint32_t receiver_status : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[00] - RO */ 457 uint32_t frame_lock : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[01] - RO */ 458 uint32_t training_status : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[02] - RO */ 459 uint32_t training_failure : 1; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[03] - RO */ 460 uint32_t reserved_04 : 12; /* M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE[15:04] - RSVD */ 461 uint32_t reserved : 16; 462 #endif /* IS_LITTLE_ENDIAN */ 463 } fields; 464 } M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE; 465 466 typedef M10G_CL72_IEEE_TX_BASE_R_PMD_status_register_151_TYPE M10G_CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_TYPE_T; 467 468 typedef union { 469 uint32_t data; 470 struct { 471 #if IS_BIG_ENDIAN 472 uint32_t reserved : 16; 473 uint32_t lp_coeff_update : 16; /* M10G_CL72_IEEE_TX_BASE_R_LP_coeff_update_register_152_TYPE[15:00] - RO */ 474 #endif /* IS_BIG_ENDIAN */ 475 #if IS_LITTLE_ENDIAN 476 uint32_t lp_coeff_update : 16; /* M10G_CL72_IEEE_TX_BASE_R_LP_coeff_update_register_152_TYPE[15:00] - RO */ 477 uint32_t reserved : 16; 478 #endif /* IS_LITTLE_ENDIAN */ 479 } fields; 480 } M10G_CL72_IEEE_TX_BASE_R_LP_coeff_update_register_152_TYPE; 481 482 typedef M10G_CL72_IEEE_TX_BASE_R_LP_coeff_update_register_152_TYPE M10G_CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_TYPE_T; 483 484 typedef union { 485 uint32_t data; 486 struct { 487 #if IS_BIG_ENDIAN 488 uint32_t reserved : 16; 489 uint32_t ld_coeff_update : 16; /* M10G_CL72_IEEE_TX_BASE_R_LD_coeff_update_register_154_TYPE[15:00] - RO */ 490 #endif /* IS_BIG_ENDIAN */ 491 #if IS_LITTLE_ENDIAN 492 uint32_t ld_coeff_update : 16; /* M10G_CL72_IEEE_TX_BASE_R_LD_coeff_update_register_154_TYPE[15:00] - RO */ 493 uint32_t reserved : 16; 494 #endif /* IS_LITTLE_ENDIAN */ 495 } fields; 496 } M10G_CL72_IEEE_TX_BASE_R_LD_coeff_update_register_154_TYPE; 497 498 typedef M10G_CL72_IEEE_TX_BASE_R_LD_coeff_update_register_154_TYPE M10G_CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_TYPE_T; 499 500 typedef union { 501 uint32_t data; 502 struct { 503 #if IS_BIG_ENDIAN 504 uint32_t reserved : 16; 505 uint32_t ld_status_report : 16; /* M10G_CL72_IEEE_TX_BASE_R_LD_status_report_register_155_TYPE[15:00] - RO */ 506 #endif /* IS_BIG_ENDIAN */ 507 #if IS_LITTLE_ENDIAN 508 uint32_t ld_status_report : 16; /* M10G_CL72_IEEE_TX_BASE_R_LD_status_report_register_155_TYPE[15:00] - RO */ 509 uint32_t reserved : 16; 510 #endif /* IS_LITTLE_ENDIAN */ 511 } fields; 512 } M10G_CL72_IEEE_TX_BASE_R_LD_status_report_register_155_TYPE; 513 514 typedef M10G_CL72_IEEE_TX_BASE_R_LD_status_report_register_155_TYPE M10G_CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_TYPE_T; 515 516 517 /*-----------------------------------------------*/ 518 /* Structs for M10G_CL72_IEEE_RX Bank */ 519 /*-----------------------------------------------*/ 520 typedef union { 521 uint32_t data; 522 struct { 523 #if IS_BIG_ENDIAN 524 uint32_t reserved : 16; 525 uint32_t lp_status_report : 16; /* M10G_CL72_IEEE_RX_BASE_R_LD_status_report_register_153_TYPE[15:00] - RO */ 526 #endif /* IS_BIG_ENDIAN */ 527 #if IS_LITTLE_ENDIAN 528 uint32_t lp_status_report : 16; /* M10G_CL72_IEEE_RX_BASE_R_LD_status_report_register_153_TYPE[15:00] - RO */ 529 uint32_t reserved : 16; 530 #endif /* IS_LITTLE_ENDIAN */ 531 } fields; 532 } M10G_CL72_IEEE_RX_BASE_R_LD_status_report_register_153_TYPE; 533 534 typedef M10G_CL72_IEEE_RX_BASE_R_LD_status_report_register_153_TYPE M10G_CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_TYPE_T; 535 536 537 /*-----------------------------------------------*/ 538 /* Structs for F25G_CL93n72_IEEE_TX Bank */ 539 /*-----------------------------------------------*/ 540 typedef union { 541 uint32_t data; 542 struct { 543 #if IS_BIG_ENDIAN 544 uint32_t reserved : 16; 545 uint32_t reserved_02 : 14; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE[15:02] - RSVD */ 546 uint32_t cl93n72_ieee_training_enable : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE[01] - RW */ 547 uint32_t cl93n72_ieee_restart_training : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE[00] - SC */ 548 #endif /* IS_BIG_ENDIAN */ 549 #if IS_LITTLE_ENDIAN 550 uint32_t cl93n72_ieee_restart_training : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE[00] - SC */ 551 uint32_t cl93n72_ieee_training_enable : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE[01] - RW */ 552 uint32_t reserved_02 : 14; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE[15:02] - RSVD */ 553 uint32_t reserved : 16; 554 #endif /* IS_LITTLE_ENDIAN */ 555 } fields; 556 } F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE; 557 558 typedef F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_TYPE F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150_TYPE_T; 559 560 typedef union { 561 uint32_t data; 562 struct { 563 #if IS_BIG_ENDIAN 564 uint32_t reserved : 16; 565 uint32_t reserved_04 : 12; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[15:04] - RSVD */ 566 uint32_t cl93n72_ieee_training_failure : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[03] - RO */ 567 uint32_t cl93n72_ieee_training_status : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[02] - RO */ 568 uint32_t cl93n72_ieee_frame_lock : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[01] - RO */ 569 uint32_t cl93n72_ieee_receiver_status : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[00] - RO */ 570 #endif /* IS_BIG_ENDIAN */ 571 #if IS_LITTLE_ENDIAN 572 uint32_t cl93n72_ieee_receiver_status : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[00] - RO */ 573 uint32_t cl93n72_ieee_frame_lock : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[01] - RO */ 574 uint32_t cl93n72_ieee_training_status : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[02] - RO */ 575 uint32_t cl93n72_ieee_training_failure : 1; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[03] - RO */ 576 uint32_t reserved_04 : 12; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE[15:04] - RSVD */ 577 uint32_t reserved : 16; 578 #endif /* IS_LITTLE_ENDIAN */ 579 } fields; 580 } F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE; 581 582 typedef F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_TYPE F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151_TYPE_T; 583 584 typedef union { 585 uint32_t data; 586 struct { 587 #if IS_BIG_ENDIAN 588 uint32_t reserved : 16; 589 uint32_t cl93n72_ieee_ld_coeff_update : 16; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_TYPE[15:00] - RO */ 590 #endif /* IS_BIG_ENDIAN */ 591 #if IS_LITTLE_ENDIAN 592 uint32_t cl93n72_ieee_ld_coeff_update : 16; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_TYPE[15:00] - RO */ 593 uint32_t reserved : 16; 594 #endif /* IS_LITTLE_ENDIAN */ 595 } fields; 596 } F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_TYPE; 597 598 typedef F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_TYPE F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154_TYPE_T; 599 600 typedef union { 601 uint32_t data; 602 struct { 603 #if IS_BIG_ENDIAN 604 uint32_t reserved : 16; 605 uint32_t cl93n72_ieee_ld_status_report : 16; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_TYPE[15:00] - RO */ 606 #endif /* IS_BIG_ENDIAN */ 607 #if IS_LITTLE_ENDIAN 608 uint32_t cl93n72_ieee_ld_status_report : 16; /* F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_TYPE[15:00] - RO */ 609 uint32_t reserved : 16; 610 #endif /* IS_LITTLE_ENDIAN */ 611 } fields; 612 } F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_TYPE; 613 614 typedef F25G_CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_TYPE F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155_TYPE_T; 615 616 617 /*-----------------------------------------------*/ 618 /* Structs for F25G_CL93n72_IEEE_RX Bank */ 619 /*-----------------------------------------------*/ 620 typedef union { 621 uint32_t data; 622 struct { 623 #if IS_BIG_ENDIAN 624 uint32_t reserved : 16; 625 uint32_t cl93n72_ieee_lp_coeff_update : 16; /* F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_TYPE[15:00] - RO */ 626 #endif /* IS_BIG_ENDIAN */ 627 #if IS_LITTLE_ENDIAN 628 uint32_t cl93n72_ieee_lp_coeff_update : 16; /* F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_TYPE[15:00] - RO */ 629 uint32_t reserved : 16; 630 #endif /* IS_LITTLE_ENDIAN */ 631 } fields; 632 } F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_TYPE; 633 634 typedef F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_TYPE F25G_CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152_TYPE_T; 635 636 typedef union { 637 uint32_t data; 638 struct { 639 #if IS_BIG_ENDIAN 640 uint32_t reserved : 16; 641 uint32_t cl93n72_ieee_lp_status_report : 16; /* F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_TYPE[15:00] - RO */ 642 #endif /* IS_BIG_ENDIAN */ 643 #if IS_LITTLE_ENDIAN 644 uint32_t cl93n72_ieee_lp_status_report : 16; /* F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_TYPE[15:00] - RO */ 645 uint32_t reserved : 16; 646 #endif /* IS_LITTLE_ENDIAN */ 647 } fields; 648 } F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_TYPE; 649 650 typedef F25G_CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_TYPE F25G_CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153_TYPE_T; 651 652 653 /*-----------------------------------------------*/ 654 /* Structs for IEEE_CL91_RX Bank */ 655 /*-----------------------------------------------*/ 656 typedef union { 657 uint32_t data; 658 struct { 659 #if IS_BIG_ENDIAN 660 uint32_t reserved : 16; 661 uint32_t reserved_02 : 14; /* IEEE_CL91_RX_fec_control_TYPE[15:02] - RSVD */ 662 uint32_t fec_byp_ind_en : 1; /* IEEE_CL91_RX_fec_control_TYPE[01] - WO */ 663 uint32_t fec_byp_corr_en : 1; /* IEEE_CL91_RX_fec_control_TYPE[00] - WO */ 664 #endif /* IS_BIG_ENDIAN */ 665 #if IS_LITTLE_ENDIAN 666 uint32_t fec_byp_corr_en : 1; /* IEEE_CL91_RX_fec_control_TYPE[00] - WO */ 667 uint32_t fec_byp_ind_en : 1; /* IEEE_CL91_RX_fec_control_TYPE[01] - WO */ 668 uint32_t reserved_02 : 14; /* IEEE_CL91_RX_fec_control_TYPE[15:02] - RSVD */ 669 uint32_t reserved : 16; 670 #endif /* IS_LITTLE_ENDIAN */ 671 } fields; 672 } IEEE_CL91_RX_fec_control_TYPE; 673 674 typedef IEEE_CL91_RX_fec_control_TYPE IEEE_CL91_RX_FEC_CONTROL_TYPE_T; 675 676 typedef union { 677 uint32_t data; 678 struct { 679 #if IS_BIG_ENDIAN 680 uint32_t reserved : 16; 681 uint32_t pcs_align_status : 1; /* IEEE_CL91_RX_fec_status_TYPE[15] - RO */ 682 uint32_t fec_align_status : 1; /* IEEE_CL91_RX_fec_status_TYPE[14] - RO */ 683 uint32_t reserved_03 : 11; /* IEEE_CL91_RX_fec_status_TYPE[13:03] - RSVD */ 684 uint32_t high_ser : 1; /* IEEE_CL91_RX_fec_status_TYPE[02] - RO */ 685 uint32_t fec_byp_ind_ability : 1; /* IEEE_CL91_RX_fec_status_TYPE[01] - RO */ 686 uint32_t fec_byp_corr_ability : 1; /* IEEE_CL91_RX_fec_status_TYPE[00] - RO */ 687 #endif /* IS_BIG_ENDIAN */ 688 #if IS_LITTLE_ENDIAN 689 uint32_t fec_byp_corr_ability : 1; /* IEEE_CL91_RX_fec_status_TYPE[00] - RO */ 690 uint32_t fec_byp_ind_ability : 1; /* IEEE_CL91_RX_fec_status_TYPE[01] - RO */ 691 uint32_t high_ser : 1; /* IEEE_CL91_RX_fec_status_TYPE[02] - RO */ 692 uint32_t reserved_03 : 11; /* IEEE_CL91_RX_fec_status_TYPE[13:03] - RSVD */ 693 uint32_t fec_align_status : 1; /* IEEE_CL91_RX_fec_status_TYPE[14] - RO */ 694 uint32_t pcs_align_status : 1; /* IEEE_CL91_RX_fec_status_TYPE[15] - RO */ 695 uint32_t reserved : 16; 696 #endif /* IS_LITTLE_ENDIAN */ 697 } fields; 698 } IEEE_CL91_RX_fec_status_TYPE; 699 700 typedef IEEE_CL91_RX_fec_status_TYPE IEEE_CL91_RX_FEC_STATUS_TYPE_T; 701 702 typedef union { 703 uint32_t data; 704 struct { 705 #if IS_BIG_ENDIAN 706 uint32_t reserved : 16; 707 uint32_t fec_corr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_TYPE[15:00] - RO */ 708 #endif /* IS_BIG_ENDIAN */ 709 #if IS_LITTLE_ENDIAN 710 uint32_t fec_corr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_TYPE[15:00] - RO */ 711 uint32_t reserved : 16; 712 #endif /* IS_LITTLE_ENDIAN */ 713 } fields; 714 } IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_TYPE; 715 716 typedef IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_TYPE IEEE_CL91_RX_FEC_CORR_CW_CNT_LOWER_REG_TYPE_T; 717 718 typedef union { 719 uint32_t data; 720 struct { 721 #if IS_BIG_ENDIAN 722 uint32_t reserved : 16; 723 uint32_t fec_corr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_TYPE[15:00] - RO */ 724 #endif /* IS_BIG_ENDIAN */ 725 #if IS_LITTLE_ENDIAN 726 uint32_t fec_corr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_TYPE[15:00] - RO */ 727 uint32_t reserved : 16; 728 #endif /* IS_LITTLE_ENDIAN */ 729 } fields; 730 } IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_TYPE; 731 732 typedef IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_TYPE IEEE_CL91_RX_FEC_CORR_CW_CNT_UPPER_REG_TYPE_T; 733 734 typedef union { 735 uint32_t data; 736 struct { 737 #if IS_BIG_ENDIAN 738 uint32_t reserved : 16; 739 uint32_t fec_uncorr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_TYPE[15:00] - RO */ 740 #endif /* IS_BIG_ENDIAN */ 741 #if IS_LITTLE_ENDIAN 742 uint32_t fec_uncorr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_TYPE[15:00] - RO */ 743 uint32_t reserved : 16; 744 #endif /* IS_LITTLE_ENDIAN */ 745 } fields; 746 } IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_TYPE; 747 748 typedef IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_TYPE IEEE_CL91_RX_FEC_UNCORR_CW_CNT_LOWER_REG_TYPE_T; 749 750 typedef union { 751 uint32_t data; 752 struct { 753 #if IS_BIG_ENDIAN 754 uint32_t reserved : 16; 755 uint32_t fec_uncorr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_TYPE[15:00] - RO */ 756 #endif /* IS_BIG_ENDIAN */ 757 #if IS_LITTLE_ENDIAN 758 uint32_t fec_uncorr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_TYPE[15:00] - RO */ 759 uint32_t reserved : 16; 760 #endif /* IS_LITTLE_ENDIAN */ 761 } fields; 762 } IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_TYPE; 763 764 typedef IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_TYPE IEEE_CL91_RX_FEC_UNCORR_CW_CNT_UPPER_REG_TYPE_T; 765 766 typedef union { 767 uint32_t data; 768 struct { 769 #if IS_BIG_ENDIAN 770 uint32_t reserved : 16; 771 uint32_t reserved_08 : 8; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[15:08] - RSVD */ 772 uint32_t fec_lane_3_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[07:06] - RO */ 773 uint32_t fec_lane_2_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[05:04] - RO */ 774 uint32_t fec_lane_1_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[03:02] - RO */ 775 uint32_t fec_lane_0_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[01:00] - RO */ 776 #endif /* IS_BIG_ENDIAN */ 777 #if IS_LITTLE_ENDIAN 778 uint32_t fec_lane_0_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[01:00] - RO */ 779 uint32_t fec_lane_1_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[03:02] - RO */ 780 uint32_t fec_lane_2_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[05:04] - RO */ 781 uint32_t fec_lane_3_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[07:06] - RO */ 782 uint32_t reserved_08 : 8; /* IEEE_CL91_RX_fec_lane_mapping_TYPE[15:08] - RSVD */ 783 uint32_t reserved : 16; 784 #endif /* IS_LITTLE_ENDIAN */ 785 } fields; 786 } IEEE_CL91_RX_fec_lane_mapping_TYPE; 787 788 typedef IEEE_CL91_RX_fec_lane_mapping_TYPE IEEE_CL91_RX_FEC_LANE_MAPPING_TYPE_T; 789 790 typedef union { 791 uint32_t data; 792 struct { 793 #if IS_BIG_ENDIAN 794 uint32_t reserved : 16; 795 uint32_t fec_sym_err_cnt_ln_0_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_TYPE[15:00] - RO */ 796 #endif /* IS_BIG_ENDIAN */ 797 #if IS_LITTLE_ENDIAN 798 uint32_t fec_sym_err_cnt_ln_0_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_TYPE[15:00] - RO */ 799 uint32_t reserved : 16; 800 #endif /* IS_LITTLE_ENDIAN */ 801 } fields; 802 } IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_TYPE; 803 804 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_0_LOWER_REG_TYPE_T; 805 806 typedef union { 807 uint32_t data; 808 struct { 809 #if IS_BIG_ENDIAN 810 uint32_t reserved : 16; 811 uint32_t fec_sym_err_cnt_ln_0_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_TYPE[15:00] - RO */ 812 #endif /* IS_BIG_ENDIAN */ 813 #if IS_LITTLE_ENDIAN 814 uint32_t fec_sym_err_cnt_ln_0_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_TYPE[15:00] - RO */ 815 uint32_t reserved : 16; 816 #endif /* IS_LITTLE_ENDIAN */ 817 } fields; 818 } IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_TYPE; 819 820 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_0_UPPER_REG_TYPE_T; 821 822 typedef union { 823 uint32_t data; 824 struct { 825 #if IS_BIG_ENDIAN 826 uint32_t reserved : 16; 827 uint32_t fec_sym_err_cnt_ln_1_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_TYPE[15:00] - RO */ 828 #endif /* IS_BIG_ENDIAN */ 829 #if IS_LITTLE_ENDIAN 830 uint32_t fec_sym_err_cnt_ln_1_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_TYPE[15:00] - RO */ 831 uint32_t reserved : 16; 832 #endif /* IS_LITTLE_ENDIAN */ 833 } fields; 834 } IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_TYPE; 835 836 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_1_LOWER_REG_TYPE_T; 837 838 typedef union { 839 uint32_t data; 840 struct { 841 #if IS_BIG_ENDIAN 842 uint32_t reserved : 16; 843 uint32_t fec_sym_err_cnt_ln_1_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_TYPE[15:00] - RO */ 844 #endif /* IS_BIG_ENDIAN */ 845 #if IS_LITTLE_ENDIAN 846 uint32_t fec_sym_err_cnt_ln_1_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_TYPE[15:00] - RO */ 847 uint32_t reserved : 16; 848 #endif /* IS_LITTLE_ENDIAN */ 849 } fields; 850 } IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_TYPE; 851 852 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_1_UPPER_REG_TYPE_T; 853 854 typedef union { 855 uint32_t data; 856 struct { 857 #if IS_BIG_ENDIAN 858 uint32_t reserved : 16; 859 uint32_t fec_sym_err_cnt_ln_2_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_TYPE[15:00] - RO */ 860 #endif /* IS_BIG_ENDIAN */ 861 #if IS_LITTLE_ENDIAN 862 uint32_t fec_sym_err_cnt_ln_2_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_TYPE[15:00] - RO */ 863 uint32_t reserved : 16; 864 #endif /* IS_LITTLE_ENDIAN */ 865 } fields; 866 } IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_TYPE; 867 868 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_2_LOWER_REG_TYPE_T; 869 870 typedef union { 871 uint32_t data; 872 struct { 873 #if IS_BIG_ENDIAN 874 uint32_t reserved : 16; 875 uint32_t fec_sym_err_cnt_ln_2_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_TYPE[15:00] - RO */ 876 #endif /* IS_BIG_ENDIAN */ 877 #if IS_LITTLE_ENDIAN 878 uint32_t fec_sym_err_cnt_ln_2_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_TYPE[15:00] - RO */ 879 uint32_t reserved : 16; 880 #endif /* IS_LITTLE_ENDIAN */ 881 } fields; 882 } IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_TYPE; 883 884 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_2_UPPER_REG_TYPE_T; 885 886 typedef union { 887 uint32_t data; 888 struct { 889 #if IS_BIG_ENDIAN 890 uint32_t reserved : 16; 891 uint32_t fec_sym_err_cnt_ln_3_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_TYPE[15:00] - RO */ 892 #endif /* IS_BIG_ENDIAN */ 893 #if IS_LITTLE_ENDIAN 894 uint32_t fec_sym_err_cnt_ln_3_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_TYPE[15:00] - RO */ 895 uint32_t reserved : 16; 896 #endif /* IS_LITTLE_ENDIAN */ 897 } fields; 898 } IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_TYPE; 899 900 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_3_LOWER_REG_TYPE_T; 901 902 typedef union { 903 uint32_t data; 904 struct { 905 #if IS_BIG_ENDIAN 906 uint32_t reserved : 16; 907 uint32_t fec_sym_err_cnt_ln_3_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_TYPE[15:00] - RO */ 908 #endif /* IS_BIG_ENDIAN */ 909 #if IS_LITTLE_ENDIAN 910 uint32_t fec_sym_err_cnt_ln_3_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_TYPE[15:00] - RO */ 911 uint32_t reserved : 16; 912 #endif /* IS_LITTLE_ENDIAN */ 913 } fields; 914 } IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_TYPE; 915 916 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_TYPE IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_3_UPPER_REG_TYPE_T; 917 918 919 /*-----------------------------------------------*/ 920 /* Structs for IEEE_CL91_TX Bank */ 921 /*-----------------------------------------------*/ 922 typedef union { 923 uint32_t data; 924 struct { 925 #if IS_BIG_ENDIAN 926 uint32_t reserved : 16; 927 uint32_t bip_err_cnt_ln_0 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_0_reg_TYPE[15:00] - RO */ 928 #endif /* IS_BIG_ENDIAN */ 929 #if IS_LITTLE_ENDIAN 930 uint32_t bip_err_cnt_ln_0 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_0_reg_TYPE[15:00] - RO */ 931 uint32_t reserved : 16; 932 #endif /* IS_LITTLE_ENDIAN */ 933 } fields; 934 } IEEE_CL91_TX_bip_err_cnt_ln_0_reg_TYPE; 935 936 typedef IEEE_CL91_TX_bip_err_cnt_ln_0_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_0_REG_TYPE_T; 937 938 typedef union { 939 uint32_t data; 940 struct { 941 #if IS_BIG_ENDIAN 942 uint32_t reserved : 16; 943 uint32_t bip_err_cnt_ln_1 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_1_reg_TYPE[15:00] - RO */ 944 #endif /* IS_BIG_ENDIAN */ 945 #if IS_LITTLE_ENDIAN 946 uint32_t bip_err_cnt_ln_1 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_1_reg_TYPE[15:00] - RO */ 947 uint32_t reserved : 16; 948 #endif /* IS_LITTLE_ENDIAN */ 949 } fields; 950 } IEEE_CL91_TX_bip_err_cnt_ln_1_reg_TYPE; 951 952 typedef IEEE_CL91_TX_bip_err_cnt_ln_1_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_1_REG_TYPE_T; 953 954 typedef union { 955 uint32_t data; 956 struct { 957 #if IS_BIG_ENDIAN 958 uint32_t reserved : 16; 959 uint32_t bip_err_cnt_ln_2 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_2_reg_TYPE[15:00] - RO */ 960 #endif /* IS_BIG_ENDIAN */ 961 #if IS_LITTLE_ENDIAN 962 uint32_t bip_err_cnt_ln_2 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_2_reg_TYPE[15:00] - RO */ 963 uint32_t reserved : 16; 964 #endif /* IS_LITTLE_ENDIAN */ 965 } fields; 966 } IEEE_CL91_TX_bip_err_cnt_ln_2_reg_TYPE; 967 968 typedef IEEE_CL91_TX_bip_err_cnt_ln_2_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_2_REG_TYPE_T; 969 970 typedef union { 971 uint32_t data; 972 struct { 973 #if IS_BIG_ENDIAN 974 uint32_t reserved : 16; 975 uint32_t bip_err_cnt_ln_3 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_3_reg_TYPE[15:00] - RO */ 976 #endif /* IS_BIG_ENDIAN */ 977 #if IS_LITTLE_ENDIAN 978 uint32_t bip_err_cnt_ln_3 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_3_reg_TYPE[15:00] - RO */ 979 uint32_t reserved : 16; 980 #endif /* IS_LITTLE_ENDIAN */ 981 } fields; 982 } IEEE_CL91_TX_bip_err_cnt_ln_3_reg_TYPE; 983 984 typedef IEEE_CL91_TX_bip_err_cnt_ln_3_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_3_REG_TYPE_T; 985 986 typedef union { 987 uint32_t data; 988 struct { 989 #if IS_BIG_ENDIAN 990 uint32_t reserved : 16; 991 uint32_t bip_err_cnt_ln_4 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_4_reg_TYPE[15:00] - RO */ 992 #endif /* IS_BIG_ENDIAN */ 993 #if IS_LITTLE_ENDIAN 994 uint32_t bip_err_cnt_ln_4 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_4_reg_TYPE[15:00] - RO */ 995 uint32_t reserved : 16; 996 #endif /* IS_LITTLE_ENDIAN */ 997 } fields; 998 } IEEE_CL91_TX_bip_err_cnt_ln_4_reg_TYPE; 999 1000 typedef IEEE_CL91_TX_bip_err_cnt_ln_4_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_4_REG_TYPE_T; 1001 1002 typedef union { 1003 uint32_t data; 1004 struct { 1005 #if IS_BIG_ENDIAN 1006 uint32_t reserved : 16; 1007 uint32_t bip_err_cnt_ln_5 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_5_reg_TYPE[15:00] - RO */ 1008 #endif /* IS_BIG_ENDIAN */ 1009 #if IS_LITTLE_ENDIAN 1010 uint32_t bip_err_cnt_ln_5 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_5_reg_TYPE[15:00] - RO */ 1011 uint32_t reserved : 16; 1012 #endif /* IS_LITTLE_ENDIAN */ 1013 } fields; 1014 } IEEE_CL91_TX_bip_err_cnt_ln_5_reg_TYPE; 1015 1016 typedef IEEE_CL91_TX_bip_err_cnt_ln_5_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_5_REG_TYPE_T; 1017 1018 typedef union { 1019 uint32_t data; 1020 struct { 1021 #if IS_BIG_ENDIAN 1022 uint32_t reserved : 16; 1023 uint32_t bip_err_cnt_ln_6 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_6_reg_TYPE[15:00] - RO */ 1024 #endif /* IS_BIG_ENDIAN */ 1025 #if IS_LITTLE_ENDIAN 1026 uint32_t bip_err_cnt_ln_6 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_6_reg_TYPE[15:00] - RO */ 1027 uint32_t reserved : 16; 1028 #endif /* IS_LITTLE_ENDIAN */ 1029 } fields; 1030 } IEEE_CL91_TX_bip_err_cnt_ln_6_reg_TYPE; 1031 1032 typedef IEEE_CL91_TX_bip_err_cnt_ln_6_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_6_REG_TYPE_T; 1033 1034 typedef union { 1035 uint32_t data; 1036 struct { 1037 #if IS_BIG_ENDIAN 1038 uint32_t reserved : 16; 1039 uint32_t bip_err_cnt_ln_7 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_7_reg_TYPE[15:00] - RO */ 1040 #endif /* IS_BIG_ENDIAN */ 1041 #if IS_LITTLE_ENDIAN 1042 uint32_t bip_err_cnt_ln_7 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_7_reg_TYPE[15:00] - RO */ 1043 uint32_t reserved : 16; 1044 #endif /* IS_LITTLE_ENDIAN */ 1045 } fields; 1046 } IEEE_CL91_TX_bip_err_cnt_ln_7_reg_TYPE; 1047 1048 typedef IEEE_CL91_TX_bip_err_cnt_ln_7_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_7_REG_TYPE_T; 1049 1050 typedef union { 1051 uint32_t data; 1052 struct { 1053 #if IS_BIG_ENDIAN 1054 uint32_t reserved : 16; 1055 uint32_t bip_err_cnt_ln_8 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_8_reg_TYPE[15:00] - RO */ 1056 #endif /* IS_BIG_ENDIAN */ 1057 #if IS_LITTLE_ENDIAN 1058 uint32_t bip_err_cnt_ln_8 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_8_reg_TYPE[15:00] - RO */ 1059 uint32_t reserved : 16; 1060 #endif /* IS_LITTLE_ENDIAN */ 1061 } fields; 1062 } IEEE_CL91_TX_bip_err_cnt_ln_8_reg_TYPE; 1063 1064 typedef IEEE_CL91_TX_bip_err_cnt_ln_8_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_8_REG_TYPE_T; 1065 1066 typedef union { 1067 uint32_t data; 1068 struct { 1069 #if IS_BIG_ENDIAN 1070 uint32_t reserved : 16; 1071 uint32_t bip_err_cnt_ln_9 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_9_reg_TYPE[15:00] - RO */ 1072 #endif /* IS_BIG_ENDIAN */ 1073 #if IS_LITTLE_ENDIAN 1074 uint32_t bip_err_cnt_ln_9 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_9_reg_TYPE[15:00] - RO */ 1075 uint32_t reserved : 16; 1076 #endif /* IS_LITTLE_ENDIAN */ 1077 } fields; 1078 } IEEE_CL91_TX_bip_err_cnt_ln_9_reg_TYPE; 1079 1080 typedef IEEE_CL91_TX_bip_err_cnt_ln_9_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_9_REG_TYPE_T; 1081 1082 typedef union { 1083 uint32_t data; 1084 struct { 1085 #if IS_BIG_ENDIAN 1086 uint32_t reserved : 16; 1087 uint32_t bip_err_cnt_ln_10 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_10_reg_TYPE[15:00] - RO */ 1088 #endif /* IS_BIG_ENDIAN */ 1089 #if IS_LITTLE_ENDIAN 1090 uint32_t bip_err_cnt_ln_10 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_10_reg_TYPE[15:00] - RO */ 1091 uint32_t reserved : 16; 1092 #endif /* IS_LITTLE_ENDIAN */ 1093 } fields; 1094 } IEEE_CL91_TX_bip_err_cnt_ln_10_reg_TYPE; 1095 1096 typedef IEEE_CL91_TX_bip_err_cnt_ln_10_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_10_REG_TYPE_T; 1097 1098 typedef union { 1099 uint32_t data; 1100 struct { 1101 #if IS_BIG_ENDIAN 1102 uint32_t reserved : 16; 1103 uint32_t bip_err_cnt_ln_11 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_11_reg_TYPE[15:00] - RO */ 1104 #endif /* IS_BIG_ENDIAN */ 1105 #if IS_LITTLE_ENDIAN 1106 uint32_t bip_err_cnt_ln_11 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_11_reg_TYPE[15:00] - RO */ 1107 uint32_t reserved : 16; 1108 #endif /* IS_LITTLE_ENDIAN */ 1109 } fields; 1110 } IEEE_CL91_TX_bip_err_cnt_ln_11_reg_TYPE; 1111 1112 typedef IEEE_CL91_TX_bip_err_cnt_ln_11_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_11_REG_TYPE_T; 1113 1114 typedef union { 1115 uint32_t data; 1116 struct { 1117 #if IS_BIG_ENDIAN 1118 uint32_t reserved : 16; 1119 uint32_t bip_err_cnt_ln_12 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_12_reg_TYPE[15:00] - RO */ 1120 #endif /* IS_BIG_ENDIAN */ 1121 #if IS_LITTLE_ENDIAN 1122 uint32_t bip_err_cnt_ln_12 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_12_reg_TYPE[15:00] - RO */ 1123 uint32_t reserved : 16; 1124 #endif /* IS_LITTLE_ENDIAN */ 1125 } fields; 1126 } IEEE_CL91_TX_bip_err_cnt_ln_12_reg_TYPE; 1127 1128 typedef IEEE_CL91_TX_bip_err_cnt_ln_12_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_12_REG_TYPE_T; 1129 1130 typedef union { 1131 uint32_t data; 1132 struct { 1133 #if IS_BIG_ENDIAN 1134 uint32_t reserved : 16; 1135 uint32_t bip_err_cnt_ln_13 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_13_reg_TYPE[15:00] - RO */ 1136 #endif /* IS_BIG_ENDIAN */ 1137 #if IS_LITTLE_ENDIAN 1138 uint32_t bip_err_cnt_ln_13 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_13_reg_TYPE[15:00] - RO */ 1139 uint32_t reserved : 16; 1140 #endif /* IS_LITTLE_ENDIAN */ 1141 } fields; 1142 } IEEE_CL91_TX_bip_err_cnt_ln_13_reg_TYPE; 1143 1144 typedef IEEE_CL91_TX_bip_err_cnt_ln_13_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_13_REG_TYPE_T; 1145 1146 typedef union { 1147 uint32_t data; 1148 struct { 1149 #if IS_BIG_ENDIAN 1150 uint32_t reserved : 16; 1151 uint32_t bip_err_cnt_ln_14 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_14_reg_TYPE[15:00] - RO */ 1152 #endif /* IS_BIG_ENDIAN */ 1153 #if IS_LITTLE_ENDIAN 1154 uint32_t bip_err_cnt_ln_14 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_14_reg_TYPE[15:00] - RO */ 1155 uint32_t reserved : 16; 1156 #endif /* IS_LITTLE_ENDIAN */ 1157 } fields; 1158 } IEEE_CL91_TX_bip_err_cnt_ln_14_reg_TYPE; 1159 1160 typedef IEEE_CL91_TX_bip_err_cnt_ln_14_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_14_REG_TYPE_T; 1161 1162 typedef union { 1163 uint32_t data; 1164 struct { 1165 #if IS_BIG_ENDIAN 1166 uint32_t reserved : 16; 1167 uint32_t bip_err_cnt_ln_15 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_15_reg_TYPE[15:00] - RO */ 1168 #endif /* IS_BIG_ENDIAN */ 1169 #if IS_LITTLE_ENDIAN 1170 uint32_t bip_err_cnt_ln_15 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_15_reg_TYPE[15:00] - RO */ 1171 uint32_t reserved : 16; 1172 #endif /* IS_LITTLE_ENDIAN */ 1173 } fields; 1174 } IEEE_CL91_TX_bip_err_cnt_ln_15_reg_TYPE; 1175 1176 typedef IEEE_CL91_TX_bip_err_cnt_ln_15_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_15_REG_TYPE_T; 1177 1178 typedef union { 1179 uint32_t data; 1180 struct { 1181 #if IS_BIG_ENDIAN 1182 uint32_t reserved : 16; 1183 uint32_t bip_err_cnt_ln_16 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_16_reg_TYPE[15:00] - RO */ 1184 #endif /* IS_BIG_ENDIAN */ 1185 #if IS_LITTLE_ENDIAN 1186 uint32_t bip_err_cnt_ln_16 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_16_reg_TYPE[15:00] - RO */ 1187 uint32_t reserved : 16; 1188 #endif /* IS_LITTLE_ENDIAN */ 1189 } fields; 1190 } IEEE_CL91_TX_bip_err_cnt_ln_16_reg_TYPE; 1191 1192 typedef IEEE_CL91_TX_bip_err_cnt_ln_16_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_16_REG_TYPE_T; 1193 1194 typedef union { 1195 uint32_t data; 1196 struct { 1197 #if IS_BIG_ENDIAN 1198 uint32_t reserved : 16; 1199 uint32_t bip_err_cnt_ln_17 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_17_reg_TYPE[15:00] - RO */ 1200 #endif /* IS_BIG_ENDIAN */ 1201 #if IS_LITTLE_ENDIAN 1202 uint32_t bip_err_cnt_ln_17 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_17_reg_TYPE[15:00] - RO */ 1203 uint32_t reserved : 16; 1204 #endif /* IS_LITTLE_ENDIAN */ 1205 } fields; 1206 } IEEE_CL91_TX_bip_err_cnt_ln_17_reg_TYPE; 1207 1208 typedef IEEE_CL91_TX_bip_err_cnt_ln_17_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_17_REG_TYPE_T; 1209 1210 typedef union { 1211 uint32_t data; 1212 struct { 1213 #if IS_BIG_ENDIAN 1214 uint32_t reserved : 16; 1215 uint32_t bip_err_cnt_ln_18 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_18_reg_TYPE[15:00] - RO */ 1216 #endif /* IS_BIG_ENDIAN */ 1217 #if IS_LITTLE_ENDIAN 1218 uint32_t bip_err_cnt_ln_18 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_18_reg_TYPE[15:00] - RO */ 1219 uint32_t reserved : 16; 1220 #endif /* IS_LITTLE_ENDIAN */ 1221 } fields; 1222 } IEEE_CL91_TX_bip_err_cnt_ln_18_reg_TYPE; 1223 1224 typedef IEEE_CL91_TX_bip_err_cnt_ln_18_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_18_REG_TYPE_T; 1225 1226 typedef union { 1227 uint32_t data; 1228 struct { 1229 #if IS_BIG_ENDIAN 1230 uint32_t reserved : 16; 1231 uint32_t bip_err_cnt_ln_19 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_19_reg_TYPE[15:00] - RO */ 1232 #endif /* IS_BIG_ENDIAN */ 1233 #if IS_LITTLE_ENDIAN 1234 uint32_t bip_err_cnt_ln_19 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_19_reg_TYPE[15:00] - RO */ 1235 uint32_t reserved : 16; 1236 #endif /* IS_LITTLE_ENDIAN */ 1237 } fields; 1238 } IEEE_CL91_TX_bip_err_cnt_ln_19_reg_TYPE; 1239 1240 typedef IEEE_CL91_TX_bip_err_cnt_ln_19_reg_TYPE IEEE_CL91_TX_BIP_ERR_CNT_LN_19_REG_TYPE_T; 1241 1242 typedef union { 1243 uint32_t data; 1244 struct { 1245 #if IS_BIG_ENDIAN 1246 uint32_t reserved : 16; 1247 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_TYPE[15:05] - RSVD */ 1248 uint32_t pcs_ln_0_mapping : 5; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_TYPE[04:00] - RO */ 1249 #endif /* IS_BIG_ENDIAN */ 1250 #if IS_LITTLE_ENDIAN 1251 uint32_t pcs_ln_0_mapping : 5; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_TYPE[04:00] - RO */ 1252 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_TYPE[15:05] - RSVD */ 1253 uint32_t reserved : 16; 1254 #endif /* IS_LITTLE_ENDIAN */ 1255 } fields; 1256 } IEEE_CL91_TX_pcs_ln_0_mapping_reg_TYPE; 1257 1258 typedef IEEE_CL91_TX_pcs_ln_0_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_0_MAPPING_REG_TYPE_T; 1259 1260 typedef union { 1261 uint32_t data; 1262 struct { 1263 #if IS_BIG_ENDIAN 1264 uint32_t reserved : 16; 1265 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_TYPE[15:05] - RSVD */ 1266 uint32_t pcs_ln_1_mapping : 5; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_TYPE[04:00] - RO */ 1267 #endif /* IS_BIG_ENDIAN */ 1268 #if IS_LITTLE_ENDIAN 1269 uint32_t pcs_ln_1_mapping : 5; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_TYPE[04:00] - RO */ 1270 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_TYPE[15:05] - RSVD */ 1271 uint32_t reserved : 16; 1272 #endif /* IS_LITTLE_ENDIAN */ 1273 } fields; 1274 } IEEE_CL91_TX_pcs_ln_1_mapping_reg_TYPE; 1275 1276 typedef IEEE_CL91_TX_pcs_ln_1_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_1_MAPPING_REG_TYPE_T; 1277 1278 typedef union { 1279 uint32_t data; 1280 struct { 1281 #if IS_BIG_ENDIAN 1282 uint32_t reserved : 16; 1283 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_TYPE[15:05] - RSVD */ 1284 uint32_t pcs_ln_2_mapping : 5; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_TYPE[04:00] - RO */ 1285 #endif /* IS_BIG_ENDIAN */ 1286 #if IS_LITTLE_ENDIAN 1287 uint32_t pcs_ln_2_mapping : 5; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_TYPE[04:00] - RO */ 1288 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_TYPE[15:05] - RSVD */ 1289 uint32_t reserved : 16; 1290 #endif /* IS_LITTLE_ENDIAN */ 1291 } fields; 1292 } IEEE_CL91_TX_pcs_ln_2_mapping_reg_TYPE; 1293 1294 typedef IEEE_CL91_TX_pcs_ln_2_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_2_MAPPING_REG_TYPE_T; 1295 1296 typedef union { 1297 uint32_t data; 1298 struct { 1299 #if IS_BIG_ENDIAN 1300 uint32_t reserved : 16; 1301 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_TYPE[15:05] - RSVD */ 1302 uint32_t pcs_ln_3_mapping : 5; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_TYPE[04:00] - RO */ 1303 #endif /* IS_BIG_ENDIAN */ 1304 #if IS_LITTLE_ENDIAN 1305 uint32_t pcs_ln_3_mapping : 5; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_TYPE[04:00] - RO */ 1306 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_TYPE[15:05] - RSVD */ 1307 uint32_t reserved : 16; 1308 #endif /* IS_LITTLE_ENDIAN */ 1309 } fields; 1310 } IEEE_CL91_TX_pcs_ln_3_mapping_reg_TYPE; 1311 1312 typedef IEEE_CL91_TX_pcs_ln_3_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_3_MAPPING_REG_TYPE_T; 1313 1314 typedef union { 1315 uint32_t data; 1316 struct { 1317 #if IS_BIG_ENDIAN 1318 uint32_t reserved : 16; 1319 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_TYPE[15:05] - RSVD */ 1320 uint32_t pcs_ln_4_mapping : 5; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_TYPE[04:00] - RO */ 1321 #endif /* IS_BIG_ENDIAN */ 1322 #if IS_LITTLE_ENDIAN 1323 uint32_t pcs_ln_4_mapping : 5; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_TYPE[04:00] - RO */ 1324 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_TYPE[15:05] - RSVD */ 1325 uint32_t reserved : 16; 1326 #endif /* IS_LITTLE_ENDIAN */ 1327 } fields; 1328 } IEEE_CL91_TX_pcs_ln_4_mapping_reg_TYPE; 1329 1330 typedef IEEE_CL91_TX_pcs_ln_4_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_4_MAPPING_REG_TYPE_T; 1331 1332 typedef union { 1333 uint32_t data; 1334 struct { 1335 #if IS_BIG_ENDIAN 1336 uint32_t reserved : 16; 1337 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_TYPE[15:05] - RSVD */ 1338 uint32_t pcs_ln_5_mapping : 5; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_TYPE[04:00] - RO */ 1339 #endif /* IS_BIG_ENDIAN */ 1340 #if IS_LITTLE_ENDIAN 1341 uint32_t pcs_ln_5_mapping : 5; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_TYPE[04:00] - RO */ 1342 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_TYPE[15:05] - RSVD */ 1343 uint32_t reserved : 16; 1344 #endif /* IS_LITTLE_ENDIAN */ 1345 } fields; 1346 } IEEE_CL91_TX_pcs_ln_5_mapping_reg_TYPE; 1347 1348 typedef IEEE_CL91_TX_pcs_ln_5_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_5_MAPPING_REG_TYPE_T; 1349 1350 typedef union { 1351 uint32_t data; 1352 struct { 1353 #if IS_BIG_ENDIAN 1354 uint32_t reserved : 16; 1355 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_TYPE[15:05] - RSVD */ 1356 uint32_t pcs_ln_6_mapping : 5; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_TYPE[04:00] - RO */ 1357 #endif /* IS_BIG_ENDIAN */ 1358 #if IS_LITTLE_ENDIAN 1359 uint32_t pcs_ln_6_mapping : 5; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_TYPE[04:00] - RO */ 1360 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_TYPE[15:05] - RSVD */ 1361 uint32_t reserved : 16; 1362 #endif /* IS_LITTLE_ENDIAN */ 1363 } fields; 1364 } IEEE_CL91_TX_pcs_ln_6_mapping_reg_TYPE; 1365 1366 typedef IEEE_CL91_TX_pcs_ln_6_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_6_MAPPING_REG_TYPE_T; 1367 1368 typedef union { 1369 uint32_t data; 1370 struct { 1371 #if IS_BIG_ENDIAN 1372 uint32_t reserved : 16; 1373 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_TYPE[15:05] - RSVD */ 1374 uint32_t pcs_ln_7_mapping : 5; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_TYPE[04:00] - RO */ 1375 #endif /* IS_BIG_ENDIAN */ 1376 #if IS_LITTLE_ENDIAN 1377 uint32_t pcs_ln_7_mapping : 5; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_TYPE[04:00] - RO */ 1378 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_TYPE[15:05] - RSVD */ 1379 uint32_t reserved : 16; 1380 #endif /* IS_LITTLE_ENDIAN */ 1381 } fields; 1382 } IEEE_CL91_TX_pcs_ln_7_mapping_reg_TYPE; 1383 1384 typedef IEEE_CL91_TX_pcs_ln_7_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_7_MAPPING_REG_TYPE_T; 1385 1386 typedef union { 1387 uint32_t data; 1388 struct { 1389 #if IS_BIG_ENDIAN 1390 uint32_t reserved : 16; 1391 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_TYPE[15:05] - RSVD */ 1392 uint32_t pcs_ln_8_mapping : 5; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_TYPE[04:00] - RO */ 1393 #endif /* IS_BIG_ENDIAN */ 1394 #if IS_LITTLE_ENDIAN 1395 uint32_t pcs_ln_8_mapping : 5; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_TYPE[04:00] - RO */ 1396 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_TYPE[15:05] - RSVD */ 1397 uint32_t reserved : 16; 1398 #endif /* IS_LITTLE_ENDIAN */ 1399 } fields; 1400 } IEEE_CL91_TX_pcs_ln_8_mapping_reg_TYPE; 1401 1402 typedef IEEE_CL91_TX_pcs_ln_8_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_8_MAPPING_REG_TYPE_T; 1403 1404 typedef union { 1405 uint32_t data; 1406 struct { 1407 #if IS_BIG_ENDIAN 1408 uint32_t reserved : 16; 1409 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_TYPE[15:05] - RSVD */ 1410 uint32_t pcs_ln_9_mapping : 5; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_TYPE[04:00] - RO */ 1411 #endif /* IS_BIG_ENDIAN */ 1412 #if IS_LITTLE_ENDIAN 1413 uint32_t pcs_ln_9_mapping : 5; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_TYPE[04:00] - RO */ 1414 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_TYPE[15:05] - RSVD */ 1415 uint32_t reserved : 16; 1416 #endif /* IS_LITTLE_ENDIAN */ 1417 } fields; 1418 } IEEE_CL91_TX_pcs_ln_9_mapping_reg_TYPE; 1419 1420 typedef IEEE_CL91_TX_pcs_ln_9_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_9_MAPPING_REG_TYPE_T; 1421 1422 typedef union { 1423 uint32_t data; 1424 struct { 1425 #if IS_BIG_ENDIAN 1426 uint32_t reserved : 16; 1427 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_TYPE[15:05] - RSVD */ 1428 uint32_t pcs_ln_10_mapping : 5; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_TYPE[04:00] - RO */ 1429 #endif /* IS_BIG_ENDIAN */ 1430 #if IS_LITTLE_ENDIAN 1431 uint32_t pcs_ln_10_mapping : 5; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_TYPE[04:00] - RO */ 1432 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_TYPE[15:05] - RSVD */ 1433 uint32_t reserved : 16; 1434 #endif /* IS_LITTLE_ENDIAN */ 1435 } fields; 1436 } IEEE_CL91_TX_pcs_ln_10_mapping_reg_TYPE; 1437 1438 typedef IEEE_CL91_TX_pcs_ln_10_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_10_MAPPING_REG_TYPE_T; 1439 1440 typedef union { 1441 uint32_t data; 1442 struct { 1443 #if IS_BIG_ENDIAN 1444 uint32_t reserved : 16; 1445 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_TYPE[15:05] - RSVD */ 1446 uint32_t pcs_ln_11_mapping : 5; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_TYPE[04:00] - RO */ 1447 #endif /* IS_BIG_ENDIAN */ 1448 #if IS_LITTLE_ENDIAN 1449 uint32_t pcs_ln_11_mapping : 5; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_TYPE[04:00] - RO */ 1450 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_TYPE[15:05] - RSVD */ 1451 uint32_t reserved : 16; 1452 #endif /* IS_LITTLE_ENDIAN */ 1453 } fields; 1454 } IEEE_CL91_TX_pcs_ln_11_mapping_reg_TYPE; 1455 1456 typedef IEEE_CL91_TX_pcs_ln_11_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_11_MAPPING_REG_TYPE_T; 1457 1458 typedef union { 1459 uint32_t data; 1460 struct { 1461 #if IS_BIG_ENDIAN 1462 uint32_t reserved : 16; 1463 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_TYPE[15:05] - RSVD */ 1464 uint32_t pcs_ln_12_mapping : 5; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_TYPE[04:00] - RO */ 1465 #endif /* IS_BIG_ENDIAN */ 1466 #if IS_LITTLE_ENDIAN 1467 uint32_t pcs_ln_12_mapping : 5; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_TYPE[04:00] - RO */ 1468 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_TYPE[15:05] - RSVD */ 1469 uint32_t reserved : 16; 1470 #endif /* IS_LITTLE_ENDIAN */ 1471 } fields; 1472 } IEEE_CL91_TX_pcs_ln_12_mapping_reg_TYPE; 1473 1474 typedef IEEE_CL91_TX_pcs_ln_12_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_12_MAPPING_REG_TYPE_T; 1475 1476 typedef union { 1477 uint32_t data; 1478 struct { 1479 #if IS_BIG_ENDIAN 1480 uint32_t reserved : 16; 1481 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_TYPE[15:05] - RSVD */ 1482 uint32_t pcs_ln_13_mapping : 5; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_TYPE[04:00] - RO */ 1483 #endif /* IS_BIG_ENDIAN */ 1484 #if IS_LITTLE_ENDIAN 1485 uint32_t pcs_ln_13_mapping : 5; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_TYPE[04:00] - RO */ 1486 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_TYPE[15:05] - RSVD */ 1487 uint32_t reserved : 16; 1488 #endif /* IS_LITTLE_ENDIAN */ 1489 } fields; 1490 } IEEE_CL91_TX_pcs_ln_13_mapping_reg_TYPE; 1491 1492 typedef IEEE_CL91_TX_pcs_ln_13_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_13_MAPPING_REG_TYPE_T; 1493 1494 typedef union { 1495 uint32_t data; 1496 struct { 1497 #if IS_BIG_ENDIAN 1498 uint32_t reserved : 16; 1499 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_TYPE[15:05] - RSVD */ 1500 uint32_t pcs_ln_14_mapping : 5; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_TYPE[04:00] - RO */ 1501 #endif /* IS_BIG_ENDIAN */ 1502 #if IS_LITTLE_ENDIAN 1503 uint32_t pcs_ln_14_mapping : 5; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_TYPE[04:00] - RO */ 1504 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_TYPE[15:05] - RSVD */ 1505 uint32_t reserved : 16; 1506 #endif /* IS_LITTLE_ENDIAN */ 1507 } fields; 1508 } IEEE_CL91_TX_pcs_ln_14_mapping_reg_TYPE; 1509 1510 typedef IEEE_CL91_TX_pcs_ln_14_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_14_MAPPING_REG_TYPE_T; 1511 1512 typedef union { 1513 uint32_t data; 1514 struct { 1515 #if IS_BIG_ENDIAN 1516 uint32_t reserved : 16; 1517 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_TYPE[15:05] - RSVD */ 1518 uint32_t pcs_ln_15_mapping : 5; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_TYPE[04:00] - RO */ 1519 #endif /* IS_BIG_ENDIAN */ 1520 #if IS_LITTLE_ENDIAN 1521 uint32_t pcs_ln_15_mapping : 5; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_TYPE[04:00] - RO */ 1522 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_TYPE[15:05] - RSVD */ 1523 uint32_t reserved : 16; 1524 #endif /* IS_LITTLE_ENDIAN */ 1525 } fields; 1526 } IEEE_CL91_TX_pcs_ln_15_mapping_reg_TYPE; 1527 1528 typedef IEEE_CL91_TX_pcs_ln_15_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_15_MAPPING_REG_TYPE_T; 1529 1530 typedef union { 1531 uint32_t data; 1532 struct { 1533 #if IS_BIG_ENDIAN 1534 uint32_t reserved : 16; 1535 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_TYPE[15:05] - RSVD */ 1536 uint32_t pcs_ln_16_mapping : 5; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_TYPE[04:00] - RO */ 1537 #endif /* IS_BIG_ENDIAN */ 1538 #if IS_LITTLE_ENDIAN 1539 uint32_t pcs_ln_16_mapping : 5; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_TYPE[04:00] - RO */ 1540 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_TYPE[15:05] - RSVD */ 1541 uint32_t reserved : 16; 1542 #endif /* IS_LITTLE_ENDIAN */ 1543 } fields; 1544 } IEEE_CL91_TX_pcs_ln_16_mapping_reg_TYPE; 1545 1546 typedef IEEE_CL91_TX_pcs_ln_16_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_16_MAPPING_REG_TYPE_T; 1547 1548 typedef union { 1549 uint32_t data; 1550 struct { 1551 #if IS_BIG_ENDIAN 1552 uint32_t reserved : 16; 1553 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_TYPE[15:05] - RSVD */ 1554 uint32_t pcs_ln_17_mapping : 5; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_TYPE[04:00] - RO */ 1555 #endif /* IS_BIG_ENDIAN */ 1556 #if IS_LITTLE_ENDIAN 1557 uint32_t pcs_ln_17_mapping : 5; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_TYPE[04:00] - RO */ 1558 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_TYPE[15:05] - RSVD */ 1559 uint32_t reserved : 16; 1560 #endif /* IS_LITTLE_ENDIAN */ 1561 } fields; 1562 } IEEE_CL91_TX_pcs_ln_17_mapping_reg_TYPE; 1563 1564 typedef IEEE_CL91_TX_pcs_ln_17_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_17_MAPPING_REG_TYPE_T; 1565 1566 typedef union { 1567 uint32_t data; 1568 struct { 1569 #if IS_BIG_ENDIAN 1570 uint32_t reserved : 16; 1571 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_TYPE[15:05] - RSVD */ 1572 uint32_t pcs_ln_18_mapping : 5; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_TYPE[04:00] - RO */ 1573 #endif /* IS_BIG_ENDIAN */ 1574 #if IS_LITTLE_ENDIAN 1575 uint32_t pcs_ln_18_mapping : 5; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_TYPE[04:00] - RO */ 1576 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_TYPE[15:05] - RSVD */ 1577 uint32_t reserved : 16; 1578 #endif /* IS_LITTLE_ENDIAN */ 1579 } fields; 1580 } IEEE_CL91_TX_pcs_ln_18_mapping_reg_TYPE; 1581 1582 typedef IEEE_CL91_TX_pcs_ln_18_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_18_MAPPING_REG_TYPE_T; 1583 1584 typedef union { 1585 uint32_t data; 1586 struct { 1587 #if IS_BIG_ENDIAN 1588 uint32_t reserved : 16; 1589 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_TYPE[15:05] - RSVD */ 1590 uint32_t pcs_ln_19_mapping : 5; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_TYPE[04:00] - RO */ 1591 #endif /* IS_BIG_ENDIAN */ 1592 #if IS_LITTLE_ENDIAN 1593 uint32_t pcs_ln_19_mapping : 5; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_TYPE[04:00] - RO */ 1594 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_TYPE[15:05] - RSVD */ 1595 uint32_t reserved : 16; 1596 #endif /* IS_LITTLE_ENDIAN */ 1597 } fields; 1598 } IEEE_CL91_TX_pcs_ln_19_mapping_reg_TYPE; 1599 1600 typedef IEEE_CL91_TX_pcs_ln_19_mapping_reg_TYPE IEEE_CL91_TX_PCS_LN_19_MAPPING_REG_TYPE_T; 1601 1602 typedef union { 1603 uint32_t data; 1604 struct { 1605 #if IS_BIG_ENDIAN 1606 uint32_t reserved : 16; 1607 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_TYPE[15:08] - RSVD */ 1608 uint32_t pcs_blk_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_TYPE[07:00] - RO */ 1609 #endif /* IS_BIG_ENDIAN */ 1610 #if IS_LITTLE_ENDIAN 1611 uint32_t pcs_blk_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_TYPE[07:00] - RO */ 1612 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_TYPE[15:08] - RSVD */ 1613 uint32_t reserved : 16; 1614 #endif /* IS_LITTLE_ENDIAN */ 1615 } fields; 1616 } IEEE_CL91_TX_pcs_align_status1_reg_TYPE; 1617 1618 typedef IEEE_CL91_TX_pcs_align_status1_reg_TYPE IEEE_CL91_TX_PCS_ALIGN_STATUS1_REG_TYPE_T; 1619 1620 typedef union { 1621 uint32_t data; 1622 struct { 1623 #if IS_BIG_ENDIAN 1624 uint32_t reserved : 16; 1625 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status2_reg_TYPE[15:12] - RSVD */ 1626 uint32_t pcs_blk_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status2_reg_TYPE[11:00] - RO */ 1627 #endif /* IS_BIG_ENDIAN */ 1628 #if IS_LITTLE_ENDIAN 1629 uint32_t pcs_blk_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status2_reg_TYPE[11:00] - RO */ 1630 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status2_reg_TYPE[15:12] - RSVD */ 1631 uint32_t reserved : 16; 1632 #endif /* IS_LITTLE_ENDIAN */ 1633 } fields; 1634 } IEEE_CL91_TX_pcs_align_status2_reg_TYPE; 1635 1636 typedef IEEE_CL91_TX_pcs_align_status2_reg_TYPE IEEE_CL91_TX_PCS_ALIGN_STATUS2_REG_TYPE_T; 1637 1638 typedef union { 1639 uint32_t data; 1640 struct { 1641 #if IS_BIG_ENDIAN 1642 uint32_t reserved : 16; 1643 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_TYPE[15:08] - RSVD */ 1644 uint32_t pcs_am_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_TYPE[07:00] - RO */ 1645 #endif /* IS_BIG_ENDIAN */ 1646 #if IS_LITTLE_ENDIAN 1647 uint32_t pcs_am_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_TYPE[07:00] - RO */ 1648 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_TYPE[15:08] - RSVD */ 1649 uint32_t reserved : 16; 1650 #endif /* IS_LITTLE_ENDIAN */ 1651 } fields; 1652 } IEEE_CL91_TX_pcs_align_status3_reg_TYPE; 1653 1654 typedef IEEE_CL91_TX_pcs_align_status3_reg_TYPE IEEE_CL91_TX_PCS_ALIGN_STATUS3_REG_TYPE_T; 1655 1656 typedef union { 1657 uint32_t data; 1658 struct { 1659 #if IS_BIG_ENDIAN 1660 uint32_t reserved : 16; 1661 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status4_reg_TYPE[15:12] - RSVD */ 1662 uint32_t pcs_am_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status4_reg_TYPE[11:00] - RO */ 1663 #endif /* IS_BIG_ENDIAN */ 1664 #if IS_LITTLE_ENDIAN 1665 uint32_t pcs_am_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status4_reg_TYPE[11:00] - RO */ 1666 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status4_reg_TYPE[15:12] - RSVD */ 1667 uint32_t reserved : 16; 1668 #endif /* IS_LITTLE_ENDIAN */ 1669 } fields; 1670 } IEEE_CL91_TX_pcs_align_status4_reg_TYPE; 1671 1672 typedef IEEE_CL91_TX_pcs_align_status4_reg_TYPE IEEE_CL91_TX_PCS_ALIGN_STATUS4_REG_TYPE_T; 1673 1674 1675 /*-----------------------------------------------*/ 1676 /* Structs for DEV1_SLICE Bank */ 1677 /*-----------------------------------------------*/ 1678 typedef union { 1679 uint32_t data; 1680 struct { 1681 #if IS_BIG_ENDIAN 1682 uint32_t reserved : 16; 1683 uint32_t dev : 1; /* DEV1_SLICE_slice_TYPE[15] - WO */ 1684 uint32_t reserved_12 : 3; /* DEV1_SLICE_slice_TYPE[14:12] - RSVD */ 1685 uint32_t cast : 4; /* DEV1_SLICE_slice_TYPE[11:08] - WO */ 1686 uint32_t lane : 4; /* DEV1_SLICE_slice_TYPE[07:04] - WO */ 1687 uint32_t reserved_01 : 3; /* DEV1_SLICE_slice_TYPE[03:01] - RSVD */ 1688 uint32_t ip : 1; /* DEV1_SLICE_slice_TYPE[00] - WO */ 1689 #endif /* IS_BIG_ENDIAN */ 1690 #if IS_LITTLE_ENDIAN 1691 uint32_t ip : 1; /* DEV1_SLICE_slice_TYPE[00] - WO */ 1692 uint32_t reserved_01 : 3; /* DEV1_SLICE_slice_TYPE[03:01] - RSVD */ 1693 uint32_t lane : 4; /* DEV1_SLICE_slice_TYPE[07:04] - WO */ 1694 uint32_t cast : 4; /* DEV1_SLICE_slice_TYPE[11:08] - WO */ 1695 uint32_t reserved_12 : 3; /* DEV1_SLICE_slice_TYPE[14:12] - RSVD */ 1696 uint32_t dev : 1; /* DEV1_SLICE_slice_TYPE[15] - WO */ 1697 uint32_t reserved : 16; 1698 #endif /* IS_LITTLE_ENDIAN */ 1699 } fields; 1700 } DEV1_SLICE_slice_TYPE; 1701 1702 typedef DEV1_SLICE_slice_TYPE DEV1_SLICE_SLICE_TYPE_T; 1703 1704 1705 /*-----------------------------------------------*/ 1706 /* Structs for SES_MDICS_PMI_ARB_MASK Bank */ 1707 /*-----------------------------------------------*/ 1708 typedef union { 1709 uint32_t data; 1710 struct { 1711 #if IS_BIG_ENDIAN 1712 uint32_t reserved : 16; 1713 uint32_t data : 16; /* SES_MDICS_PMI_ARB_MASK_ctrl_TYPE[15:00] - SC */ 1714 #endif /* IS_BIG_ENDIAN */ 1715 #if IS_LITTLE_ENDIAN 1716 uint32_t data : 16; /* SES_MDICS_PMI_ARB_MASK_ctrl_TYPE[15:00] - SC */ 1717 uint32_t reserved : 16; 1718 #endif /* IS_LITTLE_ENDIAN */ 1719 } fields; 1720 } SES_MDICS_PMI_ARB_MASK_ctrl_TYPE; 1721 1722 typedef SES_MDICS_PMI_ARB_MASK_ctrl_TYPE SES_MDICS_PMI_ARB_MASK_CTRL_TYPE_T; 1723 1724 1725 /*-----------------------------------------------*/ 1726 /* Structs for SES_GEN_CNTRLS Bank */ 1727 /*-----------------------------------------------*/ 1728 typedef union { 1729 uint32_t data; 1730 struct { 1731 #if IS_BIG_ENDIAN 1732 uint32_t reserved : 16; 1733 uint32_t reserved_for_eco_07 : 9; /* SES_GEN_CNTRLS_gen_control1_TYPE[15:07] - RSVD */ 1734 uint32_t modctrl_rstb : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[06] - WO */ 1735 uint32_t reserved_05 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[05] - RSVD */ 1736 uint32_t reserved_04 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[04] - RSVD */ 1737 uint32_t reserved_03 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[03] - RSVD */ 1738 uint32_t reserved_02 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[02] - RSVD */ 1739 uint32_t reg_rstb : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[01] - WO */ 1740 uint32_t resetb : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[00] - WO */ 1741 #endif /* IS_BIG_ENDIAN */ 1742 #if IS_LITTLE_ENDIAN 1743 uint32_t resetb : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[00] - WO */ 1744 uint32_t reg_rstb : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[01] - WO */ 1745 uint32_t reserved_02 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[02] - RSVD */ 1746 uint32_t reserved_03 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[03] - RSVD */ 1747 uint32_t reserved_04 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[04] - RSVD */ 1748 uint32_t reserved_05 : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[05] - RSVD */ 1749 uint32_t modctrl_rstb : 1; /* SES_GEN_CNTRLS_gen_control1_TYPE[06] - WO */ 1750 uint32_t reserved_for_eco_07 : 9; /* SES_GEN_CNTRLS_gen_control1_TYPE[15:07] - RSVD */ 1751 uint32_t reserved : 16; 1752 #endif /* IS_LITTLE_ENDIAN */ 1753 } fields; 1754 } SES_GEN_CNTRLS_gen_control1_TYPE; 1755 1756 typedef SES_GEN_CNTRLS_gen_control1_TYPE SES_GEN_CNTRLS_GEN_CONTROL1_TYPE_T; 1757 1758 typedef union { 1759 uint32_t data; 1760 struct { 1761 #if IS_BIG_ENDIAN 1762 uint32_t reserved : 16; 1763 uint32_t reserved_for_eco_06 : 10; /* SES_GEN_CNTRLS_gen_control2_TYPE[15:06] - RSVD */ 1764 uint32_t spi_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[05] - WO */ 1765 uint32_t spi2x_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[04] - WO */ 1766 uint32_t m0_slv_ucp_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[03] - WO */ 1767 uint32_t m0_slv_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[02] - WO */ 1768 uint32_t m0_mstr_ucp_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[01] - WO */ 1769 uint32_t m0_mstr_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[00] - WO */ 1770 #endif /* IS_BIG_ENDIAN */ 1771 #if IS_LITTLE_ENDIAN 1772 uint32_t m0_mstr_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[00] - WO */ 1773 uint32_t m0_mstr_ucp_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[01] - WO */ 1774 uint32_t m0_slv_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[02] - WO */ 1775 uint32_t m0_slv_ucp_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[03] - WO */ 1776 uint32_t spi2x_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[04] - WO */ 1777 uint32_t spi_rstb : 1; /* SES_GEN_CNTRLS_gen_control2_TYPE[05] - WO */ 1778 uint32_t reserved_for_eco_06 : 10; /* SES_GEN_CNTRLS_gen_control2_TYPE[15:06] - RSVD */ 1779 uint32_t reserved : 16; 1780 #endif /* IS_LITTLE_ENDIAN */ 1781 } fields; 1782 } SES_GEN_CNTRLS_gen_control2_TYPE; 1783 1784 typedef SES_GEN_CNTRLS_gen_control2_TYPE SES_GEN_CNTRLS_GEN_CONTROL2_TYPE_T; 1785 1786 typedef union { 1787 uint32_t data; 1788 struct { 1789 #if IS_BIG_ENDIAN 1790 uint32_t reserved : 16; 1791 uint32_t reserved_for_eco_14 : 2; /* SES_GEN_CNTRLS_gen_control3_TYPE[15:14] - RSVD */ 1792 uint32_t qsfp_sel1b : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[13] - WO */ 1793 uint32_t qsfp_sel0b : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[12] - WO */ 1794 uint32_t reserved_11 : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[11] - RSVD */ 1795 uint32_t reserved_for_eco_10 : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[10] - RSVD */ 1796 uint32_t ucspi_slow : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[09] - WO */ 1797 uint32_t reserved_for_eco_01 : 8; /* SES_GEN_CNTRLS_gen_control3_TYPE[08:01] - RSVD */ 1798 uint32_t qsfp_mode : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[00] - WO */ 1799 #endif /* IS_BIG_ENDIAN */ 1800 #if IS_LITTLE_ENDIAN 1801 uint32_t qsfp_mode : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[00] - WO */ 1802 uint32_t reserved_for_eco_01 : 8; /* SES_GEN_CNTRLS_gen_control3_TYPE[08:01] - RSVD */ 1803 uint32_t ucspi_slow : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[09] - WO */ 1804 uint32_t reserved_for_eco_10 : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[10] - RSVD */ 1805 uint32_t reserved_11 : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[11] - RSVD */ 1806 uint32_t qsfp_sel0b : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[12] - WO */ 1807 uint32_t qsfp_sel1b : 1; /* SES_GEN_CNTRLS_gen_control3_TYPE[13] - WO */ 1808 uint32_t reserved_for_eco_14 : 2; /* SES_GEN_CNTRLS_gen_control3_TYPE[15:14] - RSVD */ 1809 uint32_t reserved : 16; 1810 #endif /* IS_LITTLE_ENDIAN */ 1811 } fields; 1812 } SES_GEN_CNTRLS_gen_control3_TYPE; 1813 1814 typedef SES_GEN_CNTRLS_gen_control3_TYPE SES_GEN_CNTRLS_GEN_CONTROL3_TYPE_T; 1815 1816 typedef union { 1817 uint32_t data; 1818 struct { 1819 #if IS_BIG_ENDIAN 1820 uint32_t reserved : 16; 1821 uint32_t master_code_start_ptr : 16; /* SES_GEN_CNTRLS_spi_mst_code_start_ptr_TYPE[15:00] - WO */ 1822 #endif /* IS_BIG_ENDIAN */ 1823 #if IS_LITTLE_ENDIAN 1824 uint32_t master_code_start_ptr : 16; /* SES_GEN_CNTRLS_spi_mst_code_start_ptr_TYPE[15:00] - WO */ 1825 uint32_t reserved : 16; 1826 #endif /* IS_LITTLE_ENDIAN */ 1827 } fields; 1828 } SES_GEN_CNTRLS_spi_mst_code_start_ptr_TYPE; 1829 1830 typedef SES_GEN_CNTRLS_spi_mst_code_start_ptr_TYPE SES_GEN_CNTRLS_SPI_MST_CODE_START_PTR_TYPE_T; 1831 1832 typedef union { 1833 uint32_t data; 1834 struct { 1835 #if IS_BIG_ENDIAN 1836 uint32_t reserved : 16; 1837 uint32_t slave_code_start_ptr : 16; /* SES_GEN_CNTRLS_spi_slv_code_start_ptr_TYPE[15:00] - WO */ 1838 #endif /* IS_BIG_ENDIAN */ 1839 #if IS_LITTLE_ENDIAN 1840 uint32_t slave_code_start_ptr : 16; /* SES_GEN_CNTRLS_spi_slv_code_start_ptr_TYPE[15:00] - WO */ 1841 uint32_t reserved : 16; 1842 #endif /* IS_LITTLE_ENDIAN */ 1843 } fields; 1844 } SES_GEN_CNTRLS_spi_slv_code_start_ptr_TYPE; 1845 1846 typedef SES_GEN_CNTRLS_spi_slv_code_start_ptr_TYPE SES_GEN_CNTRLS_SPI_SLV_CODE_START_PTR_TYPE_T; 1847 1848 typedef union { 1849 uint32_t data; 1850 struct { 1851 #if IS_BIG_ENDIAN 1852 uint32_t reserved : 16; 1853 uint32_t reserved_03 : 13; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[15:03] - RSVD */ 1854 uint32_t code_broadcast_en : 1; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[02] - WO */ 1855 uint32_t slave_code_download_en : 1; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[01] - WO */ 1856 uint32_t master_code_download_en : 1; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[00] - WO */ 1857 #endif /* IS_BIG_ENDIAN */ 1858 #if IS_LITTLE_ENDIAN 1859 uint32_t master_code_download_en : 1; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[00] - WO */ 1860 uint32_t slave_code_download_en : 1; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[01] - WO */ 1861 uint32_t code_broadcast_en : 1; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[02] - WO */ 1862 uint32_t reserved_03 : 13; /* SES_GEN_CNTRLS_spi_code_load_en_TYPE[15:03] - RSVD */ 1863 uint32_t reserved : 16; 1864 #endif /* IS_LITTLE_ENDIAN */ 1865 } fields; 1866 } SES_GEN_CNTRLS_spi_code_load_en_TYPE; 1867 1868 typedef SES_GEN_CNTRLS_spi_code_load_en_TYPE SES_GEN_CNTRLS_SPI_CODE_LOAD_EN_TYPE_T; 1869 1870 typedef union { 1871 uint32_t data; 1872 struct { 1873 #if IS_BIG_ENDIAN 1874 uint32_t reserved : 16; 1875 uint32_t slv_eeprom_offset : 4; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[15:12] - WO */ 1876 uint32_t reserved_11 : 1; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[11] - RSVD */ 1877 uint32_t slv_eeprom_count : 3; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[10:08] - WO */ 1878 uint32_t mst_eeprom_offset : 4; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[07:04] - WO */ 1879 uint32_t spi_master_oeb : 1; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[03] - WO */ 1880 uint32_t mst_eeprom_count : 3; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[02:00] - WO */ 1881 #endif /* IS_BIG_ENDIAN */ 1882 #if IS_LITTLE_ENDIAN 1883 uint32_t mst_eeprom_count : 3; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[02:00] - WO */ 1884 uint32_t spi_master_oeb : 1; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[03] - WO */ 1885 uint32_t mst_eeprom_offset : 4; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[07:04] - WO */ 1886 uint32_t slv_eeprom_count : 3; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[10:08] - WO */ 1887 uint32_t reserved_11 : 1; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[11] - RSVD */ 1888 uint32_t slv_eeprom_offset : 4; /* SES_GEN_CNTRLS_spi_eeprom_control_TYPE[15:12] - WO */ 1889 uint32_t reserved : 16; 1890 #endif /* IS_LITTLE_ENDIAN */ 1891 } fields; 1892 } SES_GEN_CNTRLS_spi_eeprom_control_TYPE; 1893 1894 typedef SES_GEN_CNTRLS_spi_eeprom_control_TYPE SES_GEN_CNTRLS_SPI_EEPROM_CONTROL_TYPE_T; 1895 1896 typedef union { 1897 uint32_t data; 1898 struct { 1899 #if IS_BIG_ENDIAN 1900 uint32_t reserved : 16; 1901 uint32_t global_intr_mask : 1; /* SES_GEN_CNTRLS_mscr_TYPE[15] - WO */ 1902 uint32_t reserved_03 : 12; /* SES_GEN_CNTRLS_mscr_TYPE[14:03] - RSVD */ 1903 uint32_t hresp_mask : 1; /* SES_GEN_CNTRLS_mscr_TYPE[02] - WO */ 1904 uint32_t reserved_00 : 2; /* SES_GEN_CNTRLS_mscr_TYPE[01:00] - RSVD */ 1905 #endif /* IS_BIG_ENDIAN */ 1906 #if IS_LITTLE_ENDIAN 1907 uint32_t reserved_00 : 2; /* SES_GEN_CNTRLS_mscr_TYPE[01:00] - RSVD */ 1908 uint32_t hresp_mask : 1; /* SES_GEN_CNTRLS_mscr_TYPE[02] - WO */ 1909 uint32_t reserved_03 : 12; /* SES_GEN_CNTRLS_mscr_TYPE[14:03] - RSVD */ 1910 uint32_t global_intr_mask : 1; /* SES_GEN_CNTRLS_mscr_TYPE[15] - WO */ 1911 uint32_t reserved : 16; 1912 #endif /* IS_LITTLE_ENDIAN */ 1913 } fields; 1914 } SES_GEN_CNTRLS_mscr_TYPE; 1915 1916 typedef SES_GEN_CNTRLS_mscr_TYPE SES_GEN_CNTRLS_MSCR_TYPE_T; 1917 1918 typedef union { 1919 uint32_t data; 1920 struct { 1921 #if IS_BIG_ENDIAN 1922 uint32_t reserved : 16; 1923 uint32_t msgout_val : 16; /* SES_GEN_CNTRLS_msgout_TYPE[15:00] - SC */ 1924 #endif /* IS_BIG_ENDIAN */ 1925 #if IS_LITTLE_ENDIAN 1926 uint32_t msgout_val : 16; /* SES_GEN_CNTRLS_msgout_TYPE[15:00] - SC */ 1927 uint32_t reserved : 16; 1928 #endif /* IS_LITTLE_ENDIAN */ 1929 } fields; 1930 } SES_GEN_CNTRLS_msgout_TYPE; 1931 1932 typedef SES_GEN_CNTRLS_msgout_TYPE SES_GEN_CNTRLS_MSGOUT_TYPE_T; 1933 1934 typedef union { 1935 uint32_t data; 1936 struct { 1937 #if IS_BIG_ENDIAN 1938 uint32_t reserved : 16; 1939 uint32_t msgin_val : 16; /* SES_GEN_CNTRLS_msgin_TYPE[15:00] - WO */ 1940 #endif /* IS_BIG_ENDIAN */ 1941 #if IS_LITTLE_ENDIAN 1942 uint32_t msgin_val : 16; /* SES_GEN_CNTRLS_msgin_TYPE[15:00] - WO */ 1943 uint32_t reserved : 16; 1944 #endif /* IS_LITTLE_ENDIAN */ 1945 } fields; 1946 } SES_GEN_CNTRLS_msgin_TYPE; 1947 1948 typedef SES_GEN_CNTRLS_msgin_TYPE SES_GEN_CNTRLS_MSGIN_TYPE_T; 1949 1950 typedef union { 1951 uint32_t data; 1952 struct { 1953 #if IS_BIG_ENDIAN 1954 uint32_t reserved : 16; 1955 uint32_t reserved_03 : 13; /* SES_GEN_CNTRLS_boot_TYPE[15:03] - RSVD */ 1956 uint32_t serboot_done_once : 1; /* SES_GEN_CNTRLS_boot_TYPE[02] - RO */ 1957 uint32_t serboot_busy : 1; /* SES_GEN_CNTRLS_boot_TYPE[01] - RO */ 1958 uint32_t reserved_00 : 1; /* SES_GEN_CNTRLS_boot_TYPE[00] - RSVD */ 1959 #endif /* IS_BIG_ENDIAN */ 1960 #if IS_LITTLE_ENDIAN 1961 uint32_t reserved_00 : 1; /* SES_GEN_CNTRLS_boot_TYPE[00] - RSVD */ 1962 uint32_t serboot_busy : 1; /* SES_GEN_CNTRLS_boot_TYPE[01] - RO */ 1963 uint32_t serboot_done_once : 1; /* SES_GEN_CNTRLS_boot_TYPE[02] - RO */ 1964 uint32_t reserved_03 : 13; /* SES_GEN_CNTRLS_boot_TYPE[15:03] - RSVD */ 1965 uint32_t reserved : 16; 1966 #endif /* IS_LITTLE_ENDIAN */ 1967 } fields; 1968 } SES_GEN_CNTRLS_boot_TYPE; 1969 1970 typedef SES_GEN_CNTRLS_boot_TYPE SES_GEN_CNTRLS_BOOT_TYPE_T; 1971 1972 typedef union { 1973 uint32_t data; 1974 struct { 1975 #if IS_BIG_ENDIAN 1976 uint32_t reserved : 16; 1977 uint32_t slv_msgout_val : 16; /* SES_GEN_CNTRLS_slv_msgout_TYPE[15:00] - SC */ 1978 #endif /* IS_BIG_ENDIAN */ 1979 #if IS_LITTLE_ENDIAN 1980 uint32_t slv_msgout_val : 16; /* SES_GEN_CNTRLS_slv_msgout_TYPE[15:00] - SC */ 1981 uint32_t reserved : 16; 1982 #endif /* IS_LITTLE_ENDIAN */ 1983 } fields; 1984 } SES_GEN_CNTRLS_slv_msgout_TYPE; 1985 1986 typedef SES_GEN_CNTRLS_slv_msgout_TYPE SES_GEN_CNTRLS_SLV_MSGOUT_TYPE_T; 1987 1988 typedef union { 1989 uint32_t data; 1990 struct { 1991 #if IS_BIG_ENDIAN 1992 uint32_t reserved : 16; 1993 uint32_t slv_msgin_val : 16; /* SES_GEN_CNTRLS_slv_msgin_TYPE[15:00] - WO */ 1994 #endif /* IS_BIG_ENDIAN */ 1995 #if IS_LITTLE_ENDIAN 1996 uint32_t slv_msgin_val : 16; /* SES_GEN_CNTRLS_slv_msgin_TYPE[15:00] - WO */ 1997 uint32_t reserved : 16; 1998 #endif /* IS_LITTLE_ENDIAN */ 1999 } fields; 2000 } SES_GEN_CNTRLS_slv_msgin_TYPE; 2001 2002 typedef SES_GEN_CNTRLS_slv_msgin_TYPE SES_GEN_CNTRLS_SLV_MSGIN_TYPE_T; 2003 2004 typedef union { 2005 uint32_t data; 2006 struct { 2007 #if IS_BIG_ENDIAN 2008 uint32_t reserved : 16; 2009 uint32_t phy_type : 2; /* SES_GEN_CNTRLS_gpreg11_TYPE[15:14] - WO */ 2010 uint32_t lpbk_change : 1; /* SES_GEN_CNTRLS_gpreg11_TYPE[13] - WO */ 2011 uint32_t reserved_10 : 3; /* SES_GEN_CNTRLS_gpreg11_TYPE[12:10] - RSVD */ 2012 uint32_t an_enable : 2; /* SES_GEN_CNTRLS_gpreg11_TYPE[09:08] - WO */ 2013 uint32_t dis_rptr_10g_to_20g : 4; /* SES_GEN_CNTRLS_gpreg11_TYPE[07:04] - WO */ 2014 uint32_t dis_rptr_20g_to_10g : 4; /* SES_GEN_CNTRLS_gpreg11_TYPE[03:00] - WO */ 2015 #endif /* IS_BIG_ENDIAN */ 2016 #if IS_LITTLE_ENDIAN 2017 uint32_t dis_rptr_20g_to_10g : 4; /* SES_GEN_CNTRLS_gpreg11_TYPE[03:00] - WO */ 2018 uint32_t dis_rptr_10g_to_20g : 4; /* SES_GEN_CNTRLS_gpreg11_TYPE[07:04] - WO */ 2019 uint32_t an_enable : 2; /* SES_GEN_CNTRLS_gpreg11_TYPE[09:08] - WO */ 2020 uint32_t reserved_10 : 3; /* SES_GEN_CNTRLS_gpreg11_TYPE[12:10] - RSVD */ 2021 uint32_t lpbk_change : 1; /* SES_GEN_CNTRLS_gpreg11_TYPE[13] - WO */ 2022 uint32_t phy_type : 2; /* SES_GEN_CNTRLS_gpreg11_TYPE[15:14] - WO */ 2023 uint32_t reserved : 16; 2024 #endif /* IS_LITTLE_ENDIAN */ 2025 } fields; 2026 } SES_GEN_CNTRLS_gpreg11_TYPE; 2027 2028 typedef SES_GEN_CNTRLS_gpreg11_TYPE SES_GEN_CNTRLS_GPREG11_TYPE_T; 2029 2030 typedef union { 2031 uint32_t data; 2032 struct { 2033 #if IS_BIG_ENDIAN 2034 uint32_t reserved : 16; 2035 uint32_t reserved_15 : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[15] - RSVD */ 2036 uint32_t scrambling_dis_10g : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[14] - WO */ 2037 uint32_t media_type_10g : 2; /* SES_GEN_CNTRLS_gpreg12_TYPE[13:12] - WO */ 2038 uint32_t reserved_11 : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[11] - RSVD */ 2039 uint32_t dfe_en_10g : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[10] - WO */ 2040 uint32_t tx_trng_10g_ln : 10; /* SES_GEN_CNTRLS_gpreg12_TYPE[09:00] - WO */ 2041 #endif /* IS_BIG_ENDIAN */ 2042 #if IS_LITTLE_ENDIAN 2043 uint32_t tx_trng_10g_ln : 10; /* SES_GEN_CNTRLS_gpreg12_TYPE[09:00] - WO */ 2044 uint32_t dfe_en_10g : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[10] - WO */ 2045 uint32_t reserved_11 : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[11] - RSVD */ 2046 uint32_t media_type_10g : 2; /* SES_GEN_CNTRLS_gpreg12_TYPE[13:12] - WO */ 2047 uint32_t scrambling_dis_10g : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[14] - WO */ 2048 uint32_t reserved_15 : 1; /* SES_GEN_CNTRLS_gpreg12_TYPE[15] - RSVD */ 2049 uint32_t reserved : 16; 2050 #endif /* IS_LITTLE_ENDIAN */ 2051 } fields; 2052 } SES_GEN_CNTRLS_gpreg12_TYPE; 2053 2054 typedef SES_GEN_CNTRLS_gpreg12_TYPE SES_GEN_CNTRLS_GPREG12_TYPE_T; 2055 2056 typedef union { 2057 uint32_t data; 2058 struct { 2059 #if IS_BIG_ENDIAN 2060 uint32_t reserved : 16; 2061 uint32_t reserved_15 : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[15] - RSVD */ 2062 uint32_t scrambling_dis_20g : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[14] - WO */ 2063 uint32_t media_type_20g : 2; /* SES_GEN_CNTRLS_gpreg13_TYPE[13:12] - WO */ 2064 uint32_t dfe_lp_en_20g : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[11] - WO */ 2065 uint32_t dfe_en_20g : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[10] - WO */ 2066 uint32_t reserved_04 : 6; /* SES_GEN_CNTRLS_gpreg13_TYPE[09:04] - RSVD */ 2067 uint32_t tx_trng_20g_ln : 4; /* SES_GEN_CNTRLS_gpreg13_TYPE[03:00] - WO */ 2068 #endif /* IS_BIG_ENDIAN */ 2069 #if IS_LITTLE_ENDIAN 2070 uint32_t tx_trng_20g_ln : 4; /* SES_GEN_CNTRLS_gpreg13_TYPE[03:00] - WO */ 2071 uint32_t reserved_04 : 6; /* SES_GEN_CNTRLS_gpreg13_TYPE[09:04] - RSVD */ 2072 uint32_t dfe_en_20g : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[10] - WO */ 2073 uint32_t dfe_lp_en_20g : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[11] - WO */ 2074 uint32_t media_type_20g : 2; /* SES_GEN_CNTRLS_gpreg13_TYPE[13:12] - WO */ 2075 uint32_t scrambling_dis_20g : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[14] - WO */ 2076 uint32_t reserved_15 : 1; /* SES_GEN_CNTRLS_gpreg13_TYPE[15] - RSVD */ 2077 uint32_t reserved : 16; 2078 #endif /* IS_LITTLE_ENDIAN */ 2079 } fields; 2080 } SES_GEN_CNTRLS_gpreg13_TYPE; 2081 2082 typedef SES_GEN_CNTRLS_gpreg13_TYPE SES_GEN_CNTRLS_GPREG13_TYPE_T; 2083 2084 typedef union { 2085 uint32_t data; 2086 struct { 2087 #if IS_BIG_ENDIAN 2088 uint32_t reserved : 16; 2089 uint32_t gpreg14_data : 16; /* SES_GEN_CNTRLS_gpreg14_TYPE[15:00] - WO */ 2090 #endif /* IS_BIG_ENDIAN */ 2091 #if IS_LITTLE_ENDIAN 2092 uint32_t gpreg14_data : 16; /* SES_GEN_CNTRLS_gpreg14_TYPE[15:00] - WO */ 2093 uint32_t reserved : 16; 2094 #endif /* IS_LITTLE_ENDIAN */ 2095 } fields; 2096 } SES_GEN_CNTRLS_gpreg14_TYPE; 2097 2098 typedef SES_GEN_CNTRLS_gpreg14_TYPE SES_GEN_CNTRLS_GPREG14_TYPE_T; 2099 2100 typedef union { 2101 uint32_t data; 2102 struct { 2103 #if IS_BIG_ENDIAN 2104 uint32_t reserved : 16; 2105 uint32_t gpreg15_data : 16; /* SES_GEN_CNTRLS_gpreg15_TYPE[15:00] - WO */ 2106 #endif /* IS_BIG_ENDIAN */ 2107 #if IS_LITTLE_ENDIAN 2108 uint32_t gpreg15_data : 16; /* SES_GEN_CNTRLS_gpreg15_TYPE[15:00] - WO */ 2109 uint32_t reserved : 16; 2110 #endif /* IS_LITTLE_ENDIAN */ 2111 } fields; 2112 } SES_GEN_CNTRLS_gpreg15_TYPE; 2113 2114 typedef SES_GEN_CNTRLS_gpreg15_TYPE SES_GEN_CNTRLS_GPREG15_TYPE_T; 2115 2116 typedef union { 2117 uint32_t data; 2118 struct { 2119 #if IS_BIG_ENDIAN 2120 uint32_t reserved : 16; 2121 uint32_t mst_running_chksum_val : 16; /* SES_GEN_CNTRLS_mst_running_chksum_TYPE[15:00] - WO */ 2122 #endif /* IS_BIG_ENDIAN */ 2123 #if IS_LITTLE_ENDIAN 2124 uint32_t mst_running_chksum_val : 16; /* SES_GEN_CNTRLS_mst_running_chksum_TYPE[15:00] - WO */ 2125 uint32_t reserved : 16; 2126 #endif /* IS_LITTLE_ENDIAN */ 2127 } fields; 2128 } SES_GEN_CNTRLS_mst_running_chksum_TYPE; 2129 2130 typedef SES_GEN_CNTRLS_mst_running_chksum_TYPE SES_GEN_CNTRLS_MST_RUNNING_CHKSUM_TYPE_T; 2131 2132 typedef union { 2133 uint32_t data; 2134 struct { 2135 #if IS_BIG_ENDIAN 2136 uint32_t reserved : 16; 2137 uint32_t slv_running_chksum_val : 16; /* SES_GEN_CNTRLS_slv_running_chksum_TYPE[15:00] - WO */ 2138 #endif /* IS_BIG_ENDIAN */ 2139 #if IS_LITTLE_ENDIAN 2140 uint32_t slv_running_chksum_val : 16; /* SES_GEN_CNTRLS_slv_running_chksum_TYPE[15:00] - WO */ 2141 uint32_t reserved : 16; 2142 #endif /* IS_LITTLE_ENDIAN */ 2143 } fields; 2144 } SES_GEN_CNTRLS_slv_running_chksum_TYPE; 2145 2146 typedef SES_GEN_CNTRLS_slv_running_chksum_TYPE SES_GEN_CNTRLS_SLV_RUNNING_CHKSUM_TYPE_T; 2147 2148 typedef union { 2149 uint32_t data; 2150 struct { 2151 #if IS_BIG_ENDIAN 2152 uint32_t reserved : 16; 2153 uint32_t mst_running_byte_cnt_val : 16; /* SES_GEN_CNTRLS_mst_running_byte_cnt_TYPE[15:00] - WO */ 2154 #endif /* IS_BIG_ENDIAN */ 2155 #if IS_LITTLE_ENDIAN 2156 uint32_t mst_running_byte_cnt_val : 16; /* SES_GEN_CNTRLS_mst_running_byte_cnt_TYPE[15:00] - WO */ 2157 uint32_t reserved : 16; 2158 #endif /* IS_LITTLE_ENDIAN */ 2159 } fields; 2160 } SES_GEN_CNTRLS_mst_running_byte_cnt_TYPE; 2161 2162 typedef SES_GEN_CNTRLS_mst_running_byte_cnt_TYPE SES_GEN_CNTRLS_MST_RUNNING_BYTE_CNT_TYPE_T; 2163 2164 typedef union { 2165 uint32_t data; 2166 struct { 2167 #if IS_BIG_ENDIAN 2168 uint32_t reserved : 16; 2169 uint32_t slv_running_byte_cnt_val : 16; /* SES_GEN_CNTRLS_slv_running_byte_cnt_TYPE[15:00] - WO */ 2170 #endif /* IS_BIG_ENDIAN */ 2171 #if IS_LITTLE_ENDIAN 2172 uint32_t slv_running_byte_cnt_val : 16; /* SES_GEN_CNTRLS_slv_running_byte_cnt_TYPE[15:00] - WO */ 2173 uint32_t reserved : 16; 2174 #endif /* IS_LITTLE_ENDIAN */ 2175 } fields; 2176 } SES_GEN_CNTRLS_slv_running_byte_cnt_TYPE; 2177 2178 typedef SES_GEN_CNTRLS_slv_running_byte_cnt_TYPE SES_GEN_CNTRLS_SLV_RUNNING_BYTE_CNT_TYPE_T; 2179 2180 typedef union { 2181 uint32_t data; 2182 struct { 2183 #if IS_BIG_ENDIAN 2184 uint32_t reserved : 16; 2185 uint32_t firmware_version_val : 16; /* SES_GEN_CNTRLS_firmware_version_TYPE[15:00] - WO */ 2186 #endif /* IS_BIG_ENDIAN */ 2187 #if IS_LITTLE_ENDIAN 2188 uint32_t firmware_version_val : 16; /* SES_GEN_CNTRLS_firmware_version_TYPE[15:00] - WO */ 2189 uint32_t reserved : 16; 2190 #endif /* IS_LITTLE_ENDIAN */ 2191 } fields; 2192 } SES_GEN_CNTRLS_firmware_version_TYPE; 2193 2194 typedef SES_GEN_CNTRLS_firmware_version_TYPE SES_GEN_CNTRLS_FIRMWARE_VERSION_TYPE_T; 2195 2196 typedef union { 2197 uint32_t data; 2198 struct { 2199 #if IS_BIG_ENDIAN 2200 uint32_t reserved : 16; 2201 uint32_t reserved_01 : 15; /* SES_GEN_CNTRLS_firmware_enable_TYPE[15:01] - RSVD */ 2202 uint32_t fw_enable_val : 1; /* SES_GEN_CNTRLS_firmware_enable_TYPE[00] - WO */ 2203 #endif /* IS_BIG_ENDIAN */ 2204 #if IS_LITTLE_ENDIAN 2205 uint32_t fw_enable_val : 1; /* SES_GEN_CNTRLS_firmware_enable_TYPE[00] - WO */ 2206 uint32_t reserved_01 : 15; /* SES_GEN_CNTRLS_firmware_enable_TYPE[15:01] - RSVD */ 2207 uint32_t reserved : 16; 2208 #endif /* IS_LITTLE_ENDIAN */ 2209 } fields; 2210 } SES_GEN_CNTRLS_firmware_enable_TYPE; 2211 2212 typedef SES_GEN_CNTRLS_firmware_enable_TYPE SES_GEN_CNTRLS_FIRMWARE_ENABLE_TYPE_T; 2213 2214 typedef union { 2215 uint32_t data; 2216 struct { 2217 #if IS_BIG_ENDIAN 2218 uint32_t reserved : 16; 2219 uint32_t micro_sync_0_data : 16; /* SES_GEN_CNTRLS_micro_sync_0_TYPE[15:00] - WO */ 2220 #endif /* IS_BIG_ENDIAN */ 2221 #if IS_LITTLE_ENDIAN 2222 uint32_t micro_sync_0_data : 16; /* SES_GEN_CNTRLS_micro_sync_0_TYPE[15:00] - WO */ 2223 uint32_t reserved : 16; 2224 #endif /* IS_LITTLE_ENDIAN */ 2225 } fields; 2226 } SES_GEN_CNTRLS_micro_sync_0_TYPE; 2227 2228 typedef SES_GEN_CNTRLS_micro_sync_0_TYPE SES_GEN_CNTRLS_MICRO_SYNC_0_TYPE_T; 2229 2230 typedef union { 2231 uint32_t data; 2232 struct { 2233 #if IS_BIG_ENDIAN 2234 uint32_t reserved : 16; 2235 uint32_t micro_sync_1_data : 16; /* SES_GEN_CNTRLS_micro_sync_1_TYPE[15:00] - WO */ 2236 #endif /* IS_BIG_ENDIAN */ 2237 #if IS_LITTLE_ENDIAN 2238 uint32_t micro_sync_1_data : 16; /* SES_GEN_CNTRLS_micro_sync_1_TYPE[15:00] - WO */ 2239 uint32_t reserved : 16; 2240 #endif /* IS_LITTLE_ENDIAN */ 2241 } fields; 2242 } SES_GEN_CNTRLS_micro_sync_1_TYPE; 2243 2244 typedef SES_GEN_CNTRLS_micro_sync_1_TYPE SES_GEN_CNTRLS_MICRO_SYNC_1_TYPE_T; 2245 2246 typedef union { 2247 uint32_t data; 2248 struct { 2249 #if IS_BIG_ENDIAN 2250 uint32_t reserved : 16; 2251 uint32_t micro_sync_2_data : 16; /* SES_GEN_CNTRLS_micro_sync_2_TYPE[15:00] - WO */ 2252 #endif /* IS_BIG_ENDIAN */ 2253 #if IS_LITTLE_ENDIAN 2254 uint32_t micro_sync_2_data : 16; /* SES_GEN_CNTRLS_micro_sync_2_TYPE[15:00] - WO */ 2255 uint32_t reserved : 16; 2256 #endif /* IS_LITTLE_ENDIAN */ 2257 } fields; 2258 } SES_GEN_CNTRLS_micro_sync_2_TYPE; 2259 2260 typedef SES_GEN_CNTRLS_micro_sync_2_TYPE SES_GEN_CNTRLS_MICRO_SYNC_2_TYPE_T; 2261 2262 typedef union { 2263 uint32_t data; 2264 struct { 2265 #if IS_BIG_ENDIAN 2266 uint32_t reserved : 16; 2267 uint32_t micro_sync_3_data : 16; /* SES_GEN_CNTRLS_micro_sync_3_TYPE[15:00] - WO */ 2268 #endif /* IS_BIG_ENDIAN */ 2269 #if IS_LITTLE_ENDIAN 2270 uint32_t micro_sync_3_data : 16; /* SES_GEN_CNTRLS_micro_sync_3_TYPE[15:00] - WO */ 2271 uint32_t reserved : 16; 2272 #endif /* IS_LITTLE_ENDIAN */ 2273 } fields; 2274 } SES_GEN_CNTRLS_micro_sync_3_TYPE; 2275 2276 typedef SES_GEN_CNTRLS_micro_sync_3_TYPE SES_GEN_CNTRLS_MICRO_SYNC_3_TYPE_T; 2277 2278 typedef union { 2279 uint32_t data; 2280 struct { 2281 #if IS_BIG_ENDIAN 2282 uint32_t reserved : 16; 2283 uint32_t micro_sync_4_data : 16; /* SES_GEN_CNTRLS_micro_sync_4_TYPE[15:00] - WO */ 2284 #endif /* IS_BIG_ENDIAN */ 2285 #if IS_LITTLE_ENDIAN 2286 uint32_t micro_sync_4_data : 16; /* SES_GEN_CNTRLS_micro_sync_4_TYPE[15:00] - WO */ 2287 uint32_t reserved : 16; 2288 #endif /* IS_LITTLE_ENDIAN */ 2289 } fields; 2290 } SES_GEN_CNTRLS_micro_sync_4_TYPE; 2291 2292 typedef SES_GEN_CNTRLS_micro_sync_4_TYPE SES_GEN_CNTRLS_MICRO_SYNC_4_TYPE_T; 2293 2294 typedef union { 2295 uint32_t data; 2296 struct { 2297 #if IS_BIG_ENDIAN 2298 uint32_t reserved : 16; 2299 uint32_t p1_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[15:14] - WO */ 2300 uint32_t p1_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[13] - WO */ 2301 uint32_t p1_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[12] - WO */ 2302 uint32_t p1_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[11:10] - WO */ 2303 uint32_t p1_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[09] - WO */ 2304 uint32_t p1_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[08] - WO */ 2305 uint32_t p0_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[07:06] - WO */ 2306 uint32_t p0_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[05] - WO */ 2307 uint32_t p0_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[04] - WO */ 2308 uint32_t p0_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[03:02] - WO */ 2309 uint32_t p0_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[01] - WO */ 2310 uint32_t p0_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[00] - WO */ 2311 #endif /* IS_BIG_ENDIAN */ 2312 #if IS_LITTLE_ENDIAN 2313 uint32_t p0_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[00] - WO */ 2314 uint32_t p0_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[01] - WO */ 2315 uint32_t p0_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[03:02] - WO */ 2316 uint32_t p0_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[04] - WO */ 2317 uint32_t p0_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[05] - WO */ 2318 uint32_t p0_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[07:06] - WO */ 2319 uint32_t p1_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[08] - WO */ 2320 uint32_t p1_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[09] - WO */ 2321 uint32_t p1_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[11:10] - WO */ 2322 uint32_t p1_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[12] - WO */ 2323 uint32_t p1_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[13] - WO */ 2324 uint32_t p1_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_5_TYPE[15:14] - WO */ 2325 uint32_t reserved : 16; 2326 #endif /* IS_LITTLE_ENDIAN */ 2327 } fields; 2328 } SES_GEN_CNTRLS_micro_sync_5_TYPE; 2329 2330 typedef SES_GEN_CNTRLS_micro_sync_5_TYPE SES_GEN_CNTRLS_MICRO_SYNC_5_TYPE_T; 2331 2332 typedef union { 2333 uint32_t data; 2334 struct { 2335 #if IS_BIG_ENDIAN 2336 uint32_t reserved : 16; 2337 uint32_t p3_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[15:14] - WO */ 2338 uint32_t p3_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[13] - WO */ 2339 uint32_t p3_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[12] - WO */ 2340 uint32_t p3_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[11:10] - WO */ 2341 uint32_t p3_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[09] - WO */ 2342 uint32_t p3_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[08] - WO */ 2343 uint32_t p2_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[07:06] - WO */ 2344 uint32_t p2_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[05] - WO */ 2345 uint32_t p2_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[04] - WO */ 2346 uint32_t p2_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[03:02] - WO */ 2347 uint32_t p2_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[01] - WO */ 2348 uint32_t p2_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[00] - WO */ 2349 #endif /* IS_BIG_ENDIAN */ 2350 #if IS_LITTLE_ENDIAN 2351 uint32_t p2_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[00] - WO */ 2352 uint32_t p2_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[01] - WO */ 2353 uint32_t p2_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[03:02] - WO */ 2354 uint32_t p2_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[04] - WO */ 2355 uint32_t p2_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[05] - WO */ 2356 uint32_t p2_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[07:06] - WO */ 2357 uint32_t p3_scrambling_dis : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[08] - WO */ 2358 uint32_t p3_10g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[09] - WO */ 2359 uint32_t p3_10g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[11:10] - WO */ 2360 uint32_t p3_20g_dfe_lp_mode : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[12] - WO */ 2361 uint32_t p3_20g_dfe_on : 1; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[13] - WO */ 2362 uint32_t p3_20g_media_type : 2; /* SES_GEN_CNTRLS_micro_sync_6_TYPE[15:14] - WO */ 2363 uint32_t reserved : 16; 2364 #endif /* IS_LITTLE_ENDIAN */ 2365 } fields; 2366 } SES_GEN_CNTRLS_micro_sync_6_TYPE; 2367 2368 typedef SES_GEN_CNTRLS_micro_sync_6_TYPE SES_GEN_CNTRLS_MICRO_SYNC_6_TYPE_T; 2369 2370 typedef union { 2371 uint32_t data; 2372 struct { 2373 #if IS_BIG_ENDIAN 2374 uint32_t reserved : 16; 2375 uint32_t micro_sync_7_data : 15; /* SES_GEN_CNTRLS_micro_sync_7_TYPE[15:01] - WO */ 2376 uint32_t brdcst_en : 1; /* SES_GEN_CNTRLS_micro_sync_7_TYPE[00] - WO */ 2377 #endif /* IS_BIG_ENDIAN */ 2378 #if IS_LITTLE_ENDIAN 2379 uint32_t brdcst_en : 1; /* SES_GEN_CNTRLS_micro_sync_7_TYPE[00] - WO */ 2380 uint32_t micro_sync_7_data : 15; /* SES_GEN_CNTRLS_micro_sync_7_TYPE[15:01] - WO */ 2381 uint32_t reserved : 16; 2382 #endif /* IS_LITTLE_ENDIAN */ 2383 } fields; 2384 } SES_GEN_CNTRLS_micro_sync_7_TYPE; 2385 2386 typedef SES_GEN_CNTRLS_micro_sync_7_TYPE SES_GEN_CNTRLS_MICRO_SYNC_7_TYPE_T; 2387 2388 2389 /*-----------------------------------------------*/ 2390 /* Structs for SES_MICRO_BOOT Bank */ 2391 /*-----------------------------------------------*/ 2392 typedef union { 2393 uint32_t data; 2394 struct { 2395 #if IS_BIG_ENDIAN 2396 uint32_t reserved : 16; 2397 uint32_t spi_port_used : 1; /* SES_MICRO_BOOT_boot_por_TYPE[15] - WO */ 2398 uint32_t serboot : 1; /* SES_MICRO_BOOT_boot_por_TYPE[14] - WO */ 2399 uint32_t mst_dwld_done : 1; /* SES_MICRO_BOOT_boot_por_TYPE[13] - WO */ 2400 uint32_t slv_dwld_done : 1; /* SES_MICRO_BOOT_boot_por_TYPE[12] - WO */ 2401 uint32_t reserved_11 : 1; /* SES_MICRO_BOOT_boot_por_TYPE[11] - RSVD */ 2402 uint32_t reserved_08 : 3; /* SES_MICRO_BOOT_boot_por_TYPE[10:08] - RSVD */ 2403 uint32_t gpreg : 8; /* SES_MICRO_BOOT_boot_por_TYPE[07:00] - WO */ 2404 #endif /* IS_BIG_ENDIAN */ 2405 #if IS_LITTLE_ENDIAN 2406 uint32_t gpreg : 8; /* SES_MICRO_BOOT_boot_por_TYPE[07:00] - WO */ 2407 uint32_t reserved_08 : 3; /* SES_MICRO_BOOT_boot_por_TYPE[10:08] - RSVD */ 2408 uint32_t reserved_11 : 1; /* SES_MICRO_BOOT_boot_por_TYPE[11] - RSVD */ 2409 uint32_t slv_dwld_done : 1; /* SES_MICRO_BOOT_boot_por_TYPE[12] - WO */ 2410 uint32_t mst_dwld_done : 1; /* SES_MICRO_BOOT_boot_por_TYPE[13] - WO */ 2411 uint32_t serboot : 1; /* SES_MICRO_BOOT_boot_por_TYPE[14] - WO */ 2412 uint32_t spi_port_used : 1; /* SES_MICRO_BOOT_boot_por_TYPE[15] - WO */ 2413 uint32_t reserved : 16; 2414 #endif /* IS_LITTLE_ENDIAN */ 2415 } fields; 2416 } SES_MICRO_BOOT_boot_por_TYPE; 2417 2418 typedef SES_MICRO_BOOT_boot_por_TYPE SES_MICRO_BOOT_BOOT_POR_TYPE_T; 2419 2420 2421 /*-----------------------------------------------*/ 2422 /* Structs for SES_M0ACCESS_ADDR Bank */ 2423 /*-----------------------------------------------*/ 2424 2425 typedef union { 2426 uint32_t data; 2427 struct { 2428 #if IS_BIG_ENDIAN 2429 uint32_t reserved : 16; 2430 uint32_t reserved_13 : 3; /* SES_M0ACCESS_ADDR_master_dram_mem_add_TYPE[15:13] - RSVD */ 2431 uint32_t mst_dram_mem_add : 13; /* SES_M0ACCESS_ADDR_master_dram_mem_add_TYPE[12:00] - WO */ 2432 #endif /* IS_BIG_ENDIAN */ 2433 #if IS_LITTLE_ENDIAN 2434 uint32_t mst_dram_mem_add : 13; /* SES_M0ACCESS_ADDR_master_dram_mem_add_TYPE[12:00] - WO */ 2435 uint32_t reserved_13 : 3; /* SES_M0ACCESS_ADDR_master_dram_mem_add_TYPE[15:13] - RSVD */ 2436 uint32_t reserved : 16; 2437 #endif /* IS_LITTLE_ENDIAN */ 2438 } fields; 2439 } SES_M0ACCESS_ADDR_master_dram_mem_add_TYPE; 2440 2441 typedef SES_M0ACCESS_ADDR_master_dram_mem_add_TYPE SES_M0ACCESS_ADDR_MASTER_DRAM_MEM_ADD_TYPE_T; 2442 2443 2444 /*-----------------------------------------------*/ 2445 /* Structs for SES_M0ACCESS_DATA Bank */ 2446 /*-----------------------------------------------*/ 2447 2448 typedef union { 2449 uint32_t data; 2450 struct { 2451 #if IS_BIG_ENDIAN 2452 uint32_t reserved : 16; 2453 uint32_t mst_dram_wdata : 16; /* SES_M0ACCESS_DATA_master_dram_wdata_TYPE[15:00] - WO */ 2454 #endif /* IS_BIG_ENDIAN */ 2455 #if IS_LITTLE_ENDIAN 2456 uint32_t mst_dram_wdata : 16; /* SES_M0ACCESS_DATA_master_dram_wdata_TYPE[15:00] - WO */ 2457 uint32_t reserved : 16; 2458 #endif /* IS_LITTLE_ENDIAN */ 2459 } fields; 2460 } SES_M0ACCESS_DATA_master_dram_wdata_TYPE; 2461 2462 typedef SES_M0ACCESS_DATA_master_dram_wdata_TYPE SES_M0ACCESS_DATA_MASTER_DRAM_WDATA_TYPE_T; 2463 2464 typedef union { 2465 uint32_t data; 2466 struct { 2467 #if IS_BIG_ENDIAN 2468 uint32_t reserved : 16; 2469 uint32_t mst_dram_rdata : 16; /* SES_M0ACCESS_DATA_master_dram_rdata_TYPE[15:00] - RO */ 2470 #endif /* IS_BIG_ENDIAN */ 2471 #if IS_LITTLE_ENDIAN 2472 uint32_t mst_dram_rdata : 16; /* SES_M0ACCESS_DATA_master_dram_rdata_TYPE[15:00] - RO */ 2473 uint32_t reserved : 16; 2474 #endif /* IS_LITTLE_ENDIAN */ 2475 } fields; 2476 } SES_M0ACCESS_DATA_master_dram_rdata_TYPE; 2477 2478 typedef SES_M0ACCESS_DATA_master_dram_rdata_TYPE SES_M0ACCESS_DATA_MASTER_DRAM_RDATA_TYPE_T; 2479 2480 2481 /*-----------------------------------------------*/ 2482 /* Structs for SES_CTRL Bank */ 2483 /*-----------------------------------------------*/ 2484 typedef union { 2485 uint32_t data; 2486 struct { 2487 #if IS_BIG_ENDIAN 2488 uint32_t reserved : 16; 2489 uint32_t chip_id_15_0 : 16; /* SES_CTRL_chip_id_TYPE[15:00] - RO */ 2490 #endif /* IS_BIG_ENDIAN */ 2491 #if IS_LITTLE_ENDIAN 2492 uint32_t chip_id_15_0 : 16; /* SES_CTRL_chip_id_TYPE[15:00] - RO */ 2493 uint32_t reserved : 16; 2494 #endif /* IS_LITTLE_ENDIAN */ 2495 } fields; 2496 } SES_CTRL_chip_id_TYPE; 2497 2498 typedef SES_CTRL_chip_id_TYPE SES_CTRL_CHIP_ID_TYPE_T; 2499 2500 typedef union { 2501 uint32_t data; 2502 struct { 2503 #if IS_BIG_ENDIAN 2504 uint32_t reserved : 16; 2505 uint32_t chip_id_19_16 : 4; /* SES_CTRL_chip_revision_TYPE[15:12] - RO */ 2506 uint32_t reserved_for_eco_08 : 4; /* SES_CTRL_chip_revision_TYPE[11:08] - RSVD */ 2507 uint32_t chip_rev : 8; /* SES_CTRL_chip_revision_TYPE[07:00] - RO */ 2508 #endif /* IS_BIG_ENDIAN */ 2509 #if IS_LITTLE_ENDIAN 2510 uint32_t chip_rev : 8; /* SES_CTRL_chip_revision_TYPE[07:00] - RO */ 2511 uint32_t reserved_for_eco_08 : 4; /* SES_CTRL_chip_revision_TYPE[11:08] - RSVD */ 2512 uint32_t chip_id_19_16 : 4; /* SES_CTRL_chip_revision_TYPE[15:12] - RO */ 2513 uint32_t reserved : 16; 2514 #endif /* IS_LITTLE_ENDIAN */ 2515 } fields; 2516 } SES_CTRL_chip_revision_TYPE; 2517 2518 typedef SES_CTRL_chip_revision_TYPE SES_CTRL_CHIP_REVISION_TYPE_T; 2519 2520 typedef union { 2521 uint32_t data; 2522 struct { 2523 #if IS_BIG_ENDIAN 2524 uint32_t reserved : 16; 2525 uint32_t module1_intrb_high : 1; /* SES_CTRL_m0_eisr_TYPE[15] - WO */ 2526 uint32_t module1_intrb_low : 1; /* SES_CTRL_m0_eisr_TYPE[14] - WO */ 2527 uint32_t module2_intrb_high : 1; /* SES_CTRL_m0_eisr_TYPE[13] - WO */ 2528 uint32_t module2_intrb_low : 1; /* SES_CTRL_m0_eisr_TYPE[12] - WO */ 2529 uint32_t m0_mst_sec : 1; /* SES_CTRL_m0_eisr_TYPE[11] - WO */ 2530 uint32_t m0_mst_ded : 1; /* SES_CTRL_m0_eisr_TYPE[10] - WO */ 2531 uint32_t m0_slv_sec : 1; /* SES_CTRL_m0_eisr_TYPE[09] - WO */ 2532 uint32_t m0_slv_ded : 1; /* SES_CTRL_m0_eisr_TYPE[08] - WO */ 2533 uint32_t m0_mst_msgout_intr : 1; /* SES_CTRL_m0_eisr_TYPE[07] - WO */ 2534 uint32_t m0_slv_msgout_intr : 1; /* SES_CTRL_m0_eisr_TYPE[06] - WO */ 2535 uint32_t m0_mst_misc_intr : 1; /* SES_CTRL_m0_eisr_TYPE[05] - WO */ 2536 uint32_t m0_slv_misc_intr : 1; /* SES_CTRL_m0_eisr_TYPE[04] - WO */ 2537 uint32_t reserved_03 : 1; /* SES_CTRL_m0_eisr_TYPE[03] - RSVD */ 2538 uint32_t reserved_02 : 1; /* SES_CTRL_m0_eisr_TYPE[02] - RSVD */ 2539 uint32_t reserved_01 : 1; /* SES_CTRL_m0_eisr_TYPE[01] - RSVD */ 2540 uint32_t reserved_00 : 1; /* SES_CTRL_m0_eisr_TYPE[00] - RSVD */ 2541 #endif /* IS_BIG_ENDIAN */ 2542 #if IS_LITTLE_ENDIAN 2543 uint32_t reserved_00 : 1; /* SES_CTRL_m0_eisr_TYPE[00] - RSVD */ 2544 uint32_t reserved_01 : 1; /* SES_CTRL_m0_eisr_TYPE[01] - RSVD */ 2545 uint32_t reserved_02 : 1; /* SES_CTRL_m0_eisr_TYPE[02] - RSVD */ 2546 uint32_t reserved_03 : 1; /* SES_CTRL_m0_eisr_TYPE[03] - RSVD */ 2547 uint32_t m0_slv_misc_intr : 1; /* SES_CTRL_m0_eisr_TYPE[04] - WO */ 2548 uint32_t m0_mst_misc_intr : 1; /* SES_CTRL_m0_eisr_TYPE[05] - WO */ 2549 uint32_t m0_slv_msgout_intr : 1; /* SES_CTRL_m0_eisr_TYPE[06] - WO */ 2550 uint32_t m0_mst_msgout_intr : 1; /* SES_CTRL_m0_eisr_TYPE[07] - WO */ 2551 uint32_t m0_slv_ded : 1; /* SES_CTRL_m0_eisr_TYPE[08] - WO */ 2552 uint32_t m0_slv_sec : 1; /* SES_CTRL_m0_eisr_TYPE[09] - WO */ 2553 uint32_t m0_mst_ded : 1; /* SES_CTRL_m0_eisr_TYPE[10] - WO */ 2554 uint32_t m0_mst_sec : 1; /* SES_CTRL_m0_eisr_TYPE[11] - WO */ 2555 uint32_t module2_intrb_low : 1; /* SES_CTRL_m0_eisr_TYPE[12] - WO */ 2556 uint32_t module2_intrb_high : 1; /* SES_CTRL_m0_eisr_TYPE[13] - WO */ 2557 uint32_t module1_intrb_low : 1; /* SES_CTRL_m0_eisr_TYPE[14] - WO */ 2558 uint32_t module1_intrb_high : 1; /* SES_CTRL_m0_eisr_TYPE[15] - WO */ 2559 uint32_t reserved : 16; 2560 #endif /* IS_LITTLE_ENDIAN */ 2561 } fields; 2562 } SES_CTRL_m0_eisr_TYPE; 2563 2564 typedef SES_CTRL_m0_eisr_TYPE SES_CTRL_M0_EISR_TYPE_T; 2565 2566 typedef union { 2567 uint32_t data; 2568 struct { 2569 #if IS_BIG_ENDIAN 2570 uint32_t reserved : 16; 2571 uint32_t p_module1_intrb_high : 1; /* SES_CTRL_m0_eipr_TYPE[15] - RO */ 2572 uint32_t p_module1_intrb_low : 1; /* SES_CTRL_m0_eipr_TYPE[14] - RO */ 2573 uint32_t p_module2_intrb_high : 1; /* SES_CTRL_m0_eipr_TYPE[13] - RO */ 2574 uint32_t p_module2_intrb_low : 1; /* SES_CTRL_m0_eipr_TYPE[12] - RO */ 2575 uint32_t p_m0_mst_sec : 1; /* SES_CTRL_m0_eipr_TYPE[11] - RO */ 2576 uint32_t p_m0_mst_ded : 1; /* SES_CTRL_m0_eipr_TYPE[10] - RO */ 2577 uint32_t p_m0_slv_sec : 1; /* SES_CTRL_m0_eipr_TYPE[09] - RO */ 2578 uint32_t p_m0_slv_ded : 1; /* SES_CTRL_m0_eipr_TYPE[08] - RO */ 2579 uint32_t p_m0_mst_msgout_intr : 1; /* SES_CTRL_m0_eipr_TYPE[07] - RO */ 2580 uint32_t p_m0_slv_msgout_intr : 1; /* SES_CTRL_m0_eipr_TYPE[06] - RO */ 2581 uint32_t p_m0_mst_misc_intr : 1; /* SES_CTRL_m0_eipr_TYPE[05] - RO */ 2582 uint32_t p_m0_slv_misc_intr : 1; /* SES_CTRL_m0_eipr_TYPE[04] - RO */ 2583 uint32_t reserved_03 : 1; /* SES_CTRL_m0_eipr_TYPE[03] - RSVD */ 2584 uint32_t reserved_02 : 1; /* SES_CTRL_m0_eipr_TYPE[02] - RSVD */ 2585 uint32_t reserved_01 : 1; /* SES_CTRL_m0_eipr_TYPE[01] - RSVD */ 2586 uint32_t reserved_00 : 1; /* SES_CTRL_m0_eipr_TYPE[00] - RSVD */ 2587 #endif /* IS_BIG_ENDIAN */ 2588 #if IS_LITTLE_ENDIAN 2589 uint32_t reserved_00 : 1; /* SES_CTRL_m0_eipr_TYPE[00] - RSVD */ 2590 uint32_t reserved_01 : 1; /* SES_CTRL_m0_eipr_TYPE[01] - RSVD */ 2591 uint32_t reserved_02 : 1; /* SES_CTRL_m0_eipr_TYPE[02] - RSVD */ 2592 uint32_t reserved_03 : 1; /* SES_CTRL_m0_eipr_TYPE[03] - RSVD */ 2593 uint32_t p_m0_slv_misc_intr : 1; /* SES_CTRL_m0_eipr_TYPE[04] - RO */ 2594 uint32_t p_m0_mst_misc_intr : 1; /* SES_CTRL_m0_eipr_TYPE[05] - RO */ 2595 uint32_t p_m0_slv_msgout_intr : 1; /* SES_CTRL_m0_eipr_TYPE[06] - RO */ 2596 uint32_t p_m0_mst_msgout_intr : 1; /* SES_CTRL_m0_eipr_TYPE[07] - RO */ 2597 uint32_t p_m0_slv_ded : 1; /* SES_CTRL_m0_eipr_TYPE[08] - RO */ 2598 uint32_t p_m0_slv_sec : 1; /* SES_CTRL_m0_eipr_TYPE[09] - RO */ 2599 uint32_t p_m0_mst_ded : 1; /* SES_CTRL_m0_eipr_TYPE[10] - RO */ 2600 uint32_t p_m0_mst_sec : 1; /* SES_CTRL_m0_eipr_TYPE[11] - RO */ 2601 uint32_t p_module2_intrb_low : 1; /* SES_CTRL_m0_eipr_TYPE[12] - RO */ 2602 uint32_t p_module2_intrb_high : 1; /* SES_CTRL_m0_eipr_TYPE[13] - RO */ 2603 uint32_t p_module1_intrb_low : 1; /* SES_CTRL_m0_eipr_TYPE[14] - RO */ 2604 uint32_t p_module1_intrb_high : 1; /* SES_CTRL_m0_eipr_TYPE[15] - RO */ 2605 uint32_t reserved : 16; 2606 #endif /* IS_LITTLE_ENDIAN */ 2607 } fields; 2608 } SES_CTRL_m0_eipr_TYPE; 2609 2610 typedef SES_CTRL_m0_eipr_TYPE SES_CTRL_M0_EIPR_TYPE_T; 2611 2612 typedef union { 2613 uint32_t data; 2614 struct { 2615 #if IS_BIG_ENDIAN 2616 uint32_t reserved : 16; 2617 uint32_t enable_module1_intrb_high : 1; /* SES_CTRL_m0_eier_TYPE[15] - WO */ 2618 uint32_t enable_module1_intrb_low : 1; /* SES_CTRL_m0_eier_TYPE[14] - WO */ 2619 uint32_t enable_module2_intrb_high : 1; /* SES_CTRL_m0_eier_TYPE[13] - WO */ 2620 uint32_t enable_module2_intrb_low : 1; /* SES_CTRL_m0_eier_TYPE[12] - WO */ 2621 uint32_t enable_m0_mst_sec : 1; /* SES_CTRL_m0_eier_TYPE[11] - WO */ 2622 uint32_t enable_m0_mst_ded : 1; /* SES_CTRL_m0_eier_TYPE[10] - WO */ 2623 uint32_t enable_m0_slv_sec : 1; /* SES_CTRL_m0_eier_TYPE[09] - WO */ 2624 uint32_t enable_m0_slv_ded : 1; /* SES_CTRL_m0_eier_TYPE[08] - WO */ 2625 uint32_t enable_m0_mst_msgout_intr : 1; /* SES_CTRL_m0_eier_TYPE[07] - WO */ 2626 uint32_t enable_m0_slv_msgout_intr : 1; /* SES_CTRL_m0_eier_TYPE[06] - WO */ 2627 uint32_t enable_m0_mst_misc_intr : 1; /* SES_CTRL_m0_eier_TYPE[05] - WO */ 2628 uint32_t enable_m0_slv_misc_intr : 1; /* SES_CTRL_m0_eier_TYPE[04] - WO */ 2629 uint32_t reserved_03 : 1; /* SES_CTRL_m0_eier_TYPE[03] - RSVD */ 2630 uint32_t reserved_02 : 1; /* SES_CTRL_m0_eier_TYPE[02] - RSVD */ 2631 uint32_t reserved_01 : 1; /* SES_CTRL_m0_eier_TYPE[01] - RSVD */ 2632 uint32_t reserved_00 : 1; /* SES_CTRL_m0_eier_TYPE[00] - RSVD */ 2633 #endif /* IS_BIG_ENDIAN */ 2634 #if IS_LITTLE_ENDIAN 2635 uint32_t reserved_00 : 1; /* SES_CTRL_m0_eier_TYPE[00] - RSVD */ 2636 uint32_t reserved_01 : 1; /* SES_CTRL_m0_eier_TYPE[01] - RSVD */ 2637 uint32_t reserved_02 : 1; /* SES_CTRL_m0_eier_TYPE[02] - RSVD */ 2638 uint32_t reserved_03 : 1; /* SES_CTRL_m0_eier_TYPE[03] - RSVD */ 2639 uint32_t enable_m0_slv_misc_intr : 1; /* SES_CTRL_m0_eier_TYPE[04] - WO */ 2640 uint32_t enable_m0_mst_misc_intr : 1; /* SES_CTRL_m0_eier_TYPE[05] - WO */ 2641 uint32_t enable_m0_slv_msgout_intr : 1; /* SES_CTRL_m0_eier_TYPE[06] - WO */ 2642 uint32_t enable_m0_mst_msgout_intr : 1; /* SES_CTRL_m0_eier_TYPE[07] - WO */ 2643 uint32_t enable_m0_slv_ded : 1; /* SES_CTRL_m0_eier_TYPE[08] - WO */ 2644 uint32_t enable_m0_slv_sec : 1; /* SES_CTRL_m0_eier_TYPE[09] - WO */ 2645 uint32_t enable_m0_mst_ded : 1; /* SES_CTRL_m0_eier_TYPE[10] - WO */ 2646 uint32_t enable_m0_mst_sec : 1; /* SES_CTRL_m0_eier_TYPE[11] - WO */ 2647 uint32_t enable_module2_intrb_low : 1; /* SES_CTRL_m0_eier_TYPE[12] - WO */ 2648 uint32_t enable_module2_intrb_high : 1; /* SES_CTRL_m0_eier_TYPE[13] - WO */ 2649 uint32_t enable_module1_intrb_low : 1; /* SES_CTRL_m0_eier_TYPE[14] - WO */ 2650 uint32_t enable_module1_intrb_high : 1; /* SES_CTRL_m0_eier_TYPE[15] - WO */ 2651 uint32_t reserved : 16; 2652 #endif /* IS_LITTLE_ENDIAN */ 2653 } fields; 2654 } SES_CTRL_m0_eier_TYPE; 2655 2656 typedef SES_CTRL_m0_eier_TYPE SES_CTRL_M0_EIER_TYPE_T; 2657 2658 typedef union { 2659 uint32_t data; 2660 struct { 2661 #if IS_BIG_ENDIAN 2662 uint32_t reserved : 16; 2663 uint32_t reserved_08 : 8; /* SES_CTRL_mm_eisr_TYPE[15:08] - RSVD */ 2664 uint32_t reserved_07 : 1; /* SES_CTRL_mm_eisr_TYPE[07] - RSVD */ 2665 uint32_t reserved_06 : 1; /* SES_CTRL_mm_eisr_TYPE[06] - RSVD */ 2666 uint32_t pll_10g_lock_found : 1; /* SES_CTRL_mm_eisr_TYPE[05] - WO */ 2667 uint32_t pll_10g_lock_lost : 1; /* SES_CTRL_mm_eisr_TYPE[04] - WO */ 2668 uint32_t mux_sigdet_found : 1; /* SES_CTRL_mm_eisr_TYPE[03] - WO */ 2669 uint32_t mux_sigdet_lost : 1; /* SES_CTRL_mm_eisr_TYPE[02] - WO */ 2670 uint32_t mux_pmd_lock_found : 1; /* SES_CTRL_mm_eisr_TYPE[01] - WO */ 2671 uint32_t mux_pmd_lock_lost : 1; /* SES_CTRL_mm_eisr_TYPE[00] - WO */ 2672 #endif /* IS_BIG_ENDIAN */ 2673 #if IS_LITTLE_ENDIAN 2674 uint32_t mux_pmd_lock_lost : 1; /* SES_CTRL_mm_eisr_TYPE[00] - WO */ 2675 uint32_t mux_pmd_lock_found : 1; /* SES_CTRL_mm_eisr_TYPE[01] - WO */ 2676 uint32_t mux_sigdet_lost : 1; /* SES_CTRL_mm_eisr_TYPE[02] - WO */ 2677 uint32_t mux_sigdet_found : 1; /* SES_CTRL_mm_eisr_TYPE[03] - WO */ 2678 uint32_t pll_10g_lock_lost : 1; /* SES_CTRL_mm_eisr_TYPE[04] - WO */ 2679 uint32_t pll_10g_lock_found : 1; /* SES_CTRL_mm_eisr_TYPE[05] - WO */ 2680 uint32_t reserved_06 : 1; /* SES_CTRL_mm_eisr_TYPE[06] - RSVD */ 2681 uint32_t reserved_07 : 1; /* SES_CTRL_mm_eisr_TYPE[07] - RSVD */ 2682 uint32_t reserved_08 : 8; /* SES_CTRL_mm_eisr_TYPE[15:08] - RSVD */ 2683 uint32_t reserved : 16; 2684 #endif /* IS_LITTLE_ENDIAN */ 2685 } fields; 2686 } SES_CTRL_mm_eisr_TYPE; 2687 2688 typedef SES_CTRL_mm_eisr_TYPE SES_CTRL_MM_EISR_TYPE_T; 2689 2690 typedef union { 2691 uint32_t data; 2692 struct { 2693 #if IS_BIG_ENDIAN 2694 uint32_t reserved : 16; 2695 uint32_t reserved_08 : 8; /* SES_CTRL_mm_eipr_TYPE[15:08] - RSVD */ 2696 uint32_t reserved_07 : 1; /* SES_CTRL_mm_eipr_TYPE[07] - RSVD */ 2697 uint32_t reserved_06 : 1; /* SES_CTRL_mm_eipr_TYPE[06] - RSVD */ 2698 uint32_t p_pll_10g_lock_found : 1; /* SES_CTRL_mm_eipr_TYPE[05] - RO */ 2699 uint32_t p_pll_10g_lock_lost : 1; /* SES_CTRL_mm_eipr_TYPE[04] - RO */ 2700 uint32_t p_mux_sigdet_found : 1; /* SES_CTRL_mm_eipr_TYPE[03] - RO */ 2701 uint32_t p_mux_sigdet_lost : 1; /* SES_CTRL_mm_eipr_TYPE[02] - RO */ 2702 uint32_t p_mux_pmd_lock_found : 1; /* SES_CTRL_mm_eipr_TYPE[01] - RO */ 2703 uint32_t p_mux_pmd_lock_lost : 1; /* SES_CTRL_mm_eipr_TYPE[00] - RO */ 2704 #endif /* IS_BIG_ENDIAN */ 2705 #if IS_LITTLE_ENDIAN 2706 uint32_t p_mux_pmd_lock_lost : 1; /* SES_CTRL_mm_eipr_TYPE[00] - RO */ 2707 uint32_t p_mux_pmd_lock_found : 1; /* SES_CTRL_mm_eipr_TYPE[01] - RO */ 2708 uint32_t p_mux_sigdet_lost : 1; /* SES_CTRL_mm_eipr_TYPE[02] - RO */ 2709 uint32_t p_mux_sigdet_found : 1; /* SES_CTRL_mm_eipr_TYPE[03] - RO */ 2710 uint32_t p_pll_10g_lock_lost : 1; /* SES_CTRL_mm_eipr_TYPE[04] - RO */ 2711 uint32_t p_pll_10g_lock_found : 1; /* SES_CTRL_mm_eipr_TYPE[05] - RO */ 2712 uint32_t reserved_06 : 1; /* SES_CTRL_mm_eipr_TYPE[06] - RSVD */ 2713 uint32_t reserved_07 : 1; /* SES_CTRL_mm_eipr_TYPE[07] - RSVD */ 2714 uint32_t reserved_08 : 8; /* SES_CTRL_mm_eipr_TYPE[15:08] - RSVD */ 2715 uint32_t reserved : 16; 2716 #endif /* IS_LITTLE_ENDIAN */ 2717 } fields; 2718 } SES_CTRL_mm_eipr_TYPE; 2719 2720 typedef SES_CTRL_mm_eipr_TYPE SES_CTRL_MM_EIPR_TYPE_T; 2721 2722 typedef union { 2723 uint32_t data; 2724 struct { 2725 #if IS_BIG_ENDIAN 2726 uint32_t reserved : 16; 2727 uint32_t reserved_08 : 8; /* SES_CTRL_mm_eier_TYPE[15:08] - RSVD */ 2728 uint32_t reserved_07 : 1; /* SES_CTRL_mm_eier_TYPE[07] - RSVD */ 2729 uint32_t reserved_06 : 1; /* SES_CTRL_mm_eier_TYPE[06] - RSVD */ 2730 uint32_t enable_pll_10g_lock_found : 1; /* SES_CTRL_mm_eier_TYPE[05] - WO */ 2731 uint32_t enable_pll_10g_lock_lost : 1; /* SES_CTRL_mm_eier_TYPE[04] - WO */ 2732 uint32_t enable_mux_sigdet_found : 1; /* SES_CTRL_mm_eier_TYPE[03] - WO */ 2733 uint32_t enable_mux_sigdet_lost : 1; /* SES_CTRL_mm_eier_TYPE[02] - WO */ 2734 uint32_t enable_mux_pmd_lock_found : 1; /* SES_CTRL_mm_eier_TYPE[01] - WO */ 2735 uint32_t enable_mux_pmd_lock_lost : 1; /* SES_CTRL_mm_eier_TYPE[00] - WO */ 2736 #endif /* IS_BIG_ENDIAN */ 2737 #if IS_LITTLE_ENDIAN 2738 uint32_t enable_mux_pmd_lock_lost : 1; /* SES_CTRL_mm_eier_TYPE[00] - WO */ 2739 uint32_t enable_mux_pmd_lock_found : 1; /* SES_CTRL_mm_eier_TYPE[01] - WO */ 2740 uint32_t enable_mux_sigdet_lost : 1; /* SES_CTRL_mm_eier_TYPE[02] - WO */ 2741 uint32_t enable_mux_sigdet_found : 1; /* SES_CTRL_mm_eier_TYPE[03] - WO */ 2742 uint32_t enable_pll_10g_lock_lost : 1; /* SES_CTRL_mm_eier_TYPE[04] - WO */ 2743 uint32_t enable_pll_10g_lock_found : 1; /* SES_CTRL_mm_eier_TYPE[05] - WO */ 2744 uint32_t reserved_06 : 1; /* SES_CTRL_mm_eier_TYPE[06] - RSVD */ 2745 uint32_t reserved_07 : 1; /* SES_CTRL_mm_eier_TYPE[07] - RSVD */ 2746 uint32_t reserved_08 : 8; /* SES_CTRL_mm_eier_TYPE[15:08] - RSVD */ 2747 uint32_t reserved : 16; 2748 #endif /* IS_LITTLE_ENDIAN */ 2749 } fields; 2750 } SES_CTRL_mm_eier_TYPE; 2751 2752 typedef SES_CTRL_mm_eier_TYPE SES_CTRL_MM_EIER_TYPE_T; 2753 2754 typedef union { 2755 uint32_t data; 2756 struct { 2757 #if IS_BIG_ENDIAN 2758 uint32_t reserved : 16; 2759 uint32_t reserved_08 : 8; /* SES_CTRL_df_eisr_TYPE[15:08] - RSVD */ 2760 uint32_t reserved_07 : 1; /* SES_CTRL_df_eisr_TYPE[07] - RSVD */ 2761 uint32_t reserved_06 : 1; /* SES_CTRL_df_eisr_TYPE[06] - RSVD */ 2762 uint32_t pll_25g_lock_found : 1; /* SES_CTRL_df_eisr_TYPE[05] - WO */ 2763 uint32_t pll_25g_lock_lost : 1; /* SES_CTRL_df_eisr_TYPE[04] - WO */ 2764 uint32_t demux_sigdet_found : 1; /* SES_CTRL_df_eisr_TYPE[03] - WO */ 2765 uint32_t demux_sigdet_lost : 1; /* SES_CTRL_df_eisr_TYPE[02] - WO */ 2766 uint32_t demux_pmd_lock_found : 1; /* SES_CTRL_df_eisr_TYPE[01] - WO */ 2767 uint32_t demux_pmd_lock_lost : 1; /* SES_CTRL_df_eisr_TYPE[00] - WO */ 2768 #endif /* IS_BIG_ENDIAN */ 2769 #if IS_LITTLE_ENDIAN 2770 uint32_t demux_pmd_lock_lost : 1; /* SES_CTRL_df_eisr_TYPE[00] - WO */ 2771 uint32_t demux_pmd_lock_found : 1; /* SES_CTRL_df_eisr_TYPE[01] - WO */ 2772 uint32_t demux_sigdet_lost : 1; /* SES_CTRL_df_eisr_TYPE[02] - WO */ 2773 uint32_t demux_sigdet_found : 1; /* SES_CTRL_df_eisr_TYPE[03] - WO */ 2774 uint32_t pll_25g_lock_lost : 1; /* SES_CTRL_df_eisr_TYPE[04] - WO */ 2775 uint32_t pll_25g_lock_found : 1; /* SES_CTRL_df_eisr_TYPE[05] - WO */ 2776 uint32_t reserved_06 : 1; /* SES_CTRL_df_eisr_TYPE[06] - RSVD */ 2777 uint32_t reserved_07 : 1; /* SES_CTRL_df_eisr_TYPE[07] - RSVD */ 2778 uint32_t reserved_08 : 8; /* SES_CTRL_df_eisr_TYPE[15:08] - RSVD */ 2779 uint32_t reserved : 16; 2780 #endif /* IS_LITTLE_ENDIAN */ 2781 } fields; 2782 } SES_CTRL_df_eisr_TYPE; 2783 2784 typedef SES_CTRL_df_eisr_TYPE SES_CTRL_DF_EISR_TYPE_T; 2785 2786 typedef union { 2787 uint32_t data; 2788 struct { 2789 #if IS_BIG_ENDIAN 2790 uint32_t reserved : 16; 2791 uint32_t reserved_08 : 8; /* SES_CTRL_df_eipr_TYPE[15:08] - RSVD */ 2792 uint32_t reserved_07 : 1; /* SES_CTRL_df_eipr_TYPE[07] - RSVD */ 2793 uint32_t reserved_06 : 1; /* SES_CTRL_df_eipr_TYPE[06] - RSVD */ 2794 uint32_t p_pll_25g_lock_found : 1; /* SES_CTRL_df_eipr_TYPE[05] - RO */ 2795 uint32_t p_pll_25g_lock_lost : 1; /* SES_CTRL_df_eipr_TYPE[04] - RO */ 2796 uint32_t p_demux_sigdet_found : 1; /* SES_CTRL_df_eipr_TYPE[03] - RO */ 2797 uint32_t p_demux_sigdet_lost : 1; /* SES_CTRL_df_eipr_TYPE[02] - RO */ 2798 uint32_t p_demux_pmd_lock_found : 1; /* SES_CTRL_df_eipr_TYPE[01] - RO */ 2799 uint32_t p_demux_pmd_lock_lost : 1; /* SES_CTRL_df_eipr_TYPE[00] - RO */ 2800 #endif /* IS_BIG_ENDIAN */ 2801 #if IS_LITTLE_ENDIAN 2802 uint32_t p_demux_pmd_lock_lost : 1; /* SES_CTRL_df_eipr_TYPE[00] - RO */ 2803 uint32_t p_demux_pmd_lock_found : 1; /* SES_CTRL_df_eipr_TYPE[01] - RO */ 2804 uint32_t p_demux_sigdet_lost : 1; /* SES_CTRL_df_eipr_TYPE[02] - RO */ 2805 uint32_t p_demux_sigdet_found : 1; /* SES_CTRL_df_eipr_TYPE[03] - RO */ 2806 uint32_t p_pll_25g_lock_lost : 1; /* SES_CTRL_df_eipr_TYPE[04] - RO */ 2807 uint32_t p_pll_25g_lock_found : 1; /* SES_CTRL_df_eipr_TYPE[05] - RO */ 2808 uint32_t reserved_06 : 1; /* SES_CTRL_df_eipr_TYPE[06] - RSVD */ 2809 uint32_t reserved_07 : 1; /* SES_CTRL_df_eipr_TYPE[07] - RSVD */ 2810 uint32_t reserved_08 : 8; /* SES_CTRL_df_eipr_TYPE[15:08] - RSVD */ 2811 uint32_t reserved : 16; 2812 #endif /* IS_LITTLE_ENDIAN */ 2813 } fields; 2814 } SES_CTRL_df_eipr_TYPE; 2815 2816 typedef SES_CTRL_df_eipr_TYPE SES_CTRL_DF_EIPR_TYPE_T; 2817 2818 typedef union { 2819 uint32_t data; 2820 struct { 2821 #if IS_BIG_ENDIAN 2822 uint32_t reserved : 16; 2823 uint32_t reserved_08 : 8; /* SES_CTRL_df_eier_TYPE[15:08] - RSVD */ 2824 uint32_t reserved_07 : 1; /* SES_CTRL_df_eier_TYPE[07] - RSVD */ 2825 uint32_t reserved_06 : 1; /* SES_CTRL_df_eier_TYPE[06] - RSVD */ 2826 uint32_t enable_pll_25g_lock_found : 1; /* SES_CTRL_df_eier_TYPE[05] - WO */ 2827 uint32_t enable_pll_25g_lock_lost : 1; /* SES_CTRL_df_eier_TYPE[04] - WO */ 2828 uint32_t enable_demux_sigdet_found : 1; /* SES_CTRL_df_eier_TYPE[03] - WO */ 2829 uint32_t enable_demux_sigdet_lost : 1; /* SES_CTRL_df_eier_TYPE[02] - WO */ 2830 uint32_t enable_demux_pmd_lock_found : 1; /* SES_CTRL_df_eier_TYPE[01] - WO */ 2831 uint32_t enable_demux_pmd_lock_lost : 1; /* SES_CTRL_df_eier_TYPE[00] - WO */ 2832 #endif /* IS_BIG_ENDIAN */ 2833 #if IS_LITTLE_ENDIAN 2834 uint32_t enable_demux_pmd_lock_lost : 1; /* SES_CTRL_df_eier_TYPE[00] - WO */ 2835 uint32_t enable_demux_pmd_lock_found : 1; /* SES_CTRL_df_eier_TYPE[01] - WO */ 2836 uint32_t enable_demux_sigdet_lost : 1; /* SES_CTRL_df_eier_TYPE[02] - WO */ 2837 uint32_t enable_demux_sigdet_found : 1; /* SES_CTRL_df_eier_TYPE[03] - WO */ 2838 uint32_t enable_pll_25g_lock_lost : 1; /* SES_CTRL_df_eier_TYPE[04] - WO */ 2839 uint32_t enable_pll_25g_lock_found : 1; /* SES_CTRL_df_eier_TYPE[05] - WO */ 2840 uint32_t reserved_06 : 1; /* SES_CTRL_df_eier_TYPE[06] - RSVD */ 2841 uint32_t reserved_07 : 1; /* SES_CTRL_df_eier_TYPE[07] - RSVD */ 2842 uint32_t reserved_08 : 8; /* SES_CTRL_df_eier_TYPE[15:08] - RSVD */ 2843 uint32_t reserved : 16; 2844 #endif /* IS_LITTLE_ENDIAN */ 2845 } fields; 2846 } SES_CTRL_df_eier_TYPE; 2847 2848 typedef SES_CTRL_df_eier_TYPE SES_CTRL_DF_EIER_TYPE_T; 2849 2850 typedef union { 2851 uint32_t data; 2852 struct { 2853 #if IS_BIG_ENDIAN 2854 uint32_t reserved : 16; 2855 uint32_t reserved_09 : 7; /* SES_CTRL_demux_eisr_TYPE[15:09] - RSVD */ 2856 uint32_t demux_cl73_an_complete : 1; /* SES_CTRL_demux_eisr_TYPE[08] - WO */ 2857 uint32_t demux_cl73_an_restarted : 1; /* SES_CTRL_demux_eisr_TYPE[07] - WO */ 2858 uint32_t demux_fifoerr : 1; /* SES_CTRL_demux_eisr_TYPE[06] - WO */ 2859 uint32_t demux_pcs_mon_lock_found : 1; /* SES_CTRL_demux_eisr_TYPE[05] - WO */ 2860 uint32_t demux_pcs_mon_lock_lost : 1; /* SES_CTRL_demux_eisr_TYPE[04] - WO */ 2861 uint32_t reserved_03 : 1; /* SES_CTRL_demux_eisr_TYPE[03] - RSVD */ 2862 uint32_t reserved_02 : 1; /* SES_CTRL_demux_eisr_TYPE[02] - RSVD */ 2863 uint32_t cl91_rx_fec_align_found : 1; /* SES_CTRL_demux_eisr_TYPE[01] - WO */ 2864 uint32_t cl91_rx_fec_align_lost : 1; /* SES_CTRL_demux_eisr_TYPE[00] - WO */ 2865 #endif /* IS_BIG_ENDIAN */ 2866 #if IS_LITTLE_ENDIAN 2867 uint32_t cl91_rx_fec_align_lost : 1; /* SES_CTRL_demux_eisr_TYPE[00] - WO */ 2868 uint32_t cl91_rx_fec_align_found : 1; /* SES_CTRL_demux_eisr_TYPE[01] - WO */ 2869 uint32_t reserved_02 : 1; /* SES_CTRL_demux_eisr_TYPE[02] - RSVD */ 2870 uint32_t reserved_03 : 1; /* SES_CTRL_demux_eisr_TYPE[03] - RSVD */ 2871 uint32_t demux_pcs_mon_lock_lost : 1; /* SES_CTRL_demux_eisr_TYPE[04] - WO */ 2872 uint32_t demux_pcs_mon_lock_found : 1; /* SES_CTRL_demux_eisr_TYPE[05] - WO */ 2873 uint32_t demux_fifoerr : 1; /* SES_CTRL_demux_eisr_TYPE[06] - WO */ 2874 uint32_t demux_cl73_an_restarted : 1; /* SES_CTRL_demux_eisr_TYPE[07] - WO */ 2875 uint32_t demux_cl73_an_complete : 1; /* SES_CTRL_demux_eisr_TYPE[08] - WO */ 2876 uint32_t reserved_09 : 7; /* SES_CTRL_demux_eisr_TYPE[15:09] - RSVD */ 2877 uint32_t reserved : 16; 2878 #endif /* IS_LITTLE_ENDIAN */ 2879 } fields; 2880 } SES_CTRL_demux_eisr_TYPE; 2881 2882 typedef SES_CTRL_demux_eisr_TYPE SES_CTRL_DEMUX_EISR_TYPE_T; 2883 2884 typedef union { 2885 uint32_t data; 2886 struct { 2887 #if IS_BIG_ENDIAN 2888 uint32_t reserved : 16; 2889 uint32_t reserved_09 : 7; /* SES_CTRL_demux_eipr_TYPE[15:09] - RSVD */ 2890 uint32_t p_demux_cl73_an_complete : 1; /* SES_CTRL_demux_eipr_TYPE[08] - RO */ 2891 uint32_t p_demux_cl73_an_restarted : 1; /* SES_CTRL_demux_eipr_TYPE[07] - RO */ 2892 uint32_t p_demux_fifoerr : 1; /* SES_CTRL_demux_eipr_TYPE[06] - RO */ 2893 uint32_t p_demux_pcs_mon_lock_found : 1; /* SES_CTRL_demux_eipr_TYPE[05] - RO */ 2894 uint32_t p_demux_pcs_mon_lock_lost : 1; /* SES_CTRL_demux_eipr_TYPE[04] - RO */ 2895 uint32_t reserved_03 : 1; /* SES_CTRL_demux_eipr_TYPE[03] - RSVD */ 2896 uint32_t reserved_02 : 1; /* SES_CTRL_demux_eipr_TYPE[02] - RSVD */ 2897 uint32_t p_cl91_rx_fec_align_found : 1; /* SES_CTRL_demux_eipr_TYPE[01] - RO */ 2898 uint32_t p_cl91_rx_fec_align_lost : 1; /* SES_CTRL_demux_eipr_TYPE[00] - RO */ 2899 #endif /* IS_BIG_ENDIAN */ 2900 #if IS_LITTLE_ENDIAN 2901 uint32_t p_cl91_rx_fec_align_lost : 1; /* SES_CTRL_demux_eipr_TYPE[00] - RO */ 2902 uint32_t p_cl91_rx_fec_align_found : 1; /* SES_CTRL_demux_eipr_TYPE[01] - RO */ 2903 uint32_t reserved_02 : 1; /* SES_CTRL_demux_eipr_TYPE[02] - RSVD */ 2904 uint32_t reserved_03 : 1; /* SES_CTRL_demux_eipr_TYPE[03] - RSVD */ 2905 uint32_t p_demux_pcs_mon_lock_lost : 1; /* SES_CTRL_demux_eipr_TYPE[04] - RO */ 2906 uint32_t p_demux_pcs_mon_lock_found : 1; /* SES_CTRL_demux_eipr_TYPE[05] - RO */ 2907 uint32_t p_demux_fifoerr : 1; /* SES_CTRL_demux_eipr_TYPE[06] - RO */ 2908 uint32_t p_demux_cl73_an_restarted : 1; /* SES_CTRL_demux_eipr_TYPE[07] - RO */ 2909 uint32_t p_demux_cl73_an_complete : 1; /* SES_CTRL_demux_eipr_TYPE[08] - RO */ 2910 uint32_t reserved_09 : 7; /* SES_CTRL_demux_eipr_TYPE[15:09] - RSVD */ 2911 uint32_t reserved : 16; 2912 #endif /* IS_LITTLE_ENDIAN */ 2913 } fields; 2914 } SES_CTRL_demux_eipr_TYPE; 2915 2916 typedef SES_CTRL_demux_eipr_TYPE SES_CTRL_DEMUX_EIPR_TYPE_T; 2917 2918 typedef union { 2919 uint32_t data; 2920 struct { 2921 #if IS_BIG_ENDIAN 2922 uint32_t reserved : 16; 2923 uint32_t reserved_09 : 7; /* SES_CTRL_demux_eier_TYPE[15:09] - RSVD */ 2924 uint32_t enable_demux_cl73_an_complete : 1; /* SES_CTRL_demux_eier_TYPE[08] - WO */ 2925 uint32_t enable_demux_cl73_an_restarted : 1; /* SES_CTRL_demux_eier_TYPE[07] - WO */ 2926 uint32_t enable_demux_fifoerr : 1; /* SES_CTRL_demux_eier_TYPE[06] - WO */ 2927 uint32_t enable_demux_pcs_mon_lock_found : 1; /* SES_CTRL_demux_eier_TYPE[05] - WO */ 2928 uint32_t enable_demux_pcs_mon_lock_lost : 1; /* SES_CTRL_demux_eier_TYPE[04] - WO */ 2929 uint32_t reserved_03 : 1; /* SES_CTRL_demux_eier_TYPE[03] - RSVD */ 2930 uint32_t reserved_02 : 1; /* SES_CTRL_demux_eier_TYPE[02] - RSVD */ 2931 uint32_t enable_cl91_rx_fec_align_found : 1; /* SES_CTRL_demux_eier_TYPE[01] - WO */ 2932 uint32_t enable_cl91_rx_fec_align_lost : 1; /* SES_CTRL_demux_eier_TYPE[00] - WO */ 2933 #endif /* IS_BIG_ENDIAN */ 2934 #if IS_LITTLE_ENDIAN 2935 uint32_t enable_cl91_rx_fec_align_lost : 1; /* SES_CTRL_demux_eier_TYPE[00] - WO */ 2936 uint32_t enable_cl91_rx_fec_align_found : 1; /* SES_CTRL_demux_eier_TYPE[01] - WO */ 2937 uint32_t reserved_02 : 1; /* SES_CTRL_demux_eier_TYPE[02] - RSVD */ 2938 uint32_t reserved_03 : 1; /* SES_CTRL_demux_eier_TYPE[03] - RSVD */ 2939 uint32_t enable_demux_pcs_mon_lock_lost : 1; /* SES_CTRL_demux_eier_TYPE[04] - WO */ 2940 uint32_t enable_demux_pcs_mon_lock_found : 1; /* SES_CTRL_demux_eier_TYPE[05] - WO */ 2941 uint32_t enable_demux_fifoerr : 1; /* SES_CTRL_demux_eier_TYPE[06] - WO */ 2942 uint32_t enable_demux_cl73_an_restarted : 1; /* SES_CTRL_demux_eier_TYPE[07] - WO */ 2943 uint32_t enable_demux_cl73_an_complete : 1; /* SES_CTRL_demux_eier_TYPE[08] - WO */ 2944 uint32_t reserved_09 : 7; /* SES_CTRL_demux_eier_TYPE[15:09] - RSVD */ 2945 uint32_t reserved : 16; 2946 #endif /* IS_LITTLE_ENDIAN */ 2947 } fields; 2948 } SES_CTRL_demux_eier_TYPE; 2949 2950 typedef SES_CTRL_demux_eier_TYPE SES_CTRL_DEMUX_EIER_TYPE_T; 2951 2952 typedef union { 2953 uint32_t data; 2954 struct { 2955 #if IS_BIG_ENDIAN 2956 uint32_t reserved : 16; 2957 uint32_t reserved_13 : 3; /* SES_CTRL_mux_eisr_TYPE[15:13] - RSVD */ 2958 uint32_t mux_cl73_an_complete_p1 : 1; /* SES_CTRL_mux_eisr_TYPE[12] - WO */ 2959 uint32_t mux_cl73_an_complete_p2 : 1; /* SES_CTRL_mux_eisr_TYPE[11] - WO */ 2960 uint32_t mux_cl73_an_restarted_p1 : 1; /* SES_CTRL_mux_eisr_TYPE[10] - WO */ 2961 uint32_t mux_cl73_an_restarted_p2 : 1; /* SES_CTRL_mux_eisr_TYPE[09] - WO */ 2962 uint32_t mux_cl73_an_complete : 1; /* SES_CTRL_mux_eisr_TYPE[08] - WO */ 2963 uint32_t mux_cl73_an_restarted : 1; /* SES_CTRL_mux_eisr_TYPE[07] - WO */ 2964 uint32_t mux_fifoerr : 1; /* SES_CTRL_mux_eisr_TYPE[06] - WO */ 2965 uint32_t mux_pcs_mon_lock_found : 1; /* SES_CTRL_mux_eisr_TYPE[05] - WO */ 2966 uint32_t mux_pcs_mon_lock_lost : 1; /* SES_CTRL_mux_eisr_TYPE[04] - WO */ 2967 uint32_t reserved_03 : 1; /* SES_CTRL_mux_eisr_TYPE[03] - RSVD */ 2968 uint32_t reserved_02 : 1; /* SES_CTRL_mux_eisr_TYPE[02] - RSVD */ 2969 uint32_t cl91_tx_pcs_align_found : 1; /* SES_CTRL_mux_eisr_TYPE[01] - WO */ 2970 uint32_t cl91_tx_pcs_align_lost : 1; /* SES_CTRL_mux_eisr_TYPE[00] - WO */ 2971 #endif /* IS_BIG_ENDIAN */ 2972 #if IS_LITTLE_ENDIAN 2973 uint32_t cl91_tx_pcs_align_lost : 1; /* SES_CTRL_mux_eisr_TYPE[00] - WO */ 2974 uint32_t cl91_tx_pcs_align_found : 1; /* SES_CTRL_mux_eisr_TYPE[01] - WO */ 2975 uint32_t reserved_02 : 1; /* SES_CTRL_mux_eisr_TYPE[02] - RSVD */ 2976 uint32_t reserved_03 : 1; /* SES_CTRL_mux_eisr_TYPE[03] - RSVD */ 2977 uint32_t mux_pcs_mon_lock_lost : 1; /* SES_CTRL_mux_eisr_TYPE[04] - WO */ 2978 uint32_t mux_pcs_mon_lock_found : 1; /* SES_CTRL_mux_eisr_TYPE[05] - WO */ 2979 uint32_t mux_fifoerr : 1; /* SES_CTRL_mux_eisr_TYPE[06] - WO */ 2980 uint32_t mux_cl73_an_restarted : 1; /* SES_CTRL_mux_eisr_TYPE[07] - WO */ 2981 uint32_t mux_cl73_an_complete : 1; /* SES_CTRL_mux_eisr_TYPE[08] - WO */ 2982 uint32_t mux_cl73_an_restarted_p2 : 1; /* SES_CTRL_mux_eisr_TYPE[09] - WO */ 2983 uint32_t mux_cl73_an_restarted_p1 : 1; /* SES_CTRL_mux_eisr_TYPE[10] - WO */ 2984 uint32_t mux_cl73_an_complete_p2 : 1; /* SES_CTRL_mux_eisr_TYPE[11] - WO */ 2985 uint32_t mux_cl73_an_complete_p1 : 1; /* SES_CTRL_mux_eisr_TYPE[12] - WO */ 2986 uint32_t reserved_13 : 3; /* SES_CTRL_mux_eisr_TYPE[15:13] - RSVD */ 2987 uint32_t reserved : 16; 2988 #endif /* IS_LITTLE_ENDIAN */ 2989 } fields; 2990 } SES_CTRL_mux_eisr_TYPE; 2991 2992 typedef SES_CTRL_mux_eisr_TYPE SES_CTRL_MUX_EISR_TYPE_T; 2993 2994 typedef union { 2995 uint32_t data; 2996 struct { 2997 #if IS_BIG_ENDIAN 2998 uint32_t reserved : 16; 2999 uint32_t reserved_13 : 3; /* SES_CTRL_mux_eipr_TYPE[15:13] - RSVD */ 3000 uint32_t p_mux_cl73_an_complete_p1 : 1; /* SES_CTRL_mux_eipr_TYPE[12] - RO */ 3001 uint32_t p_mux_cl73_an_complete_p2 : 1; /* SES_CTRL_mux_eipr_TYPE[11] - RO */ 3002 uint32_t p_mux_cl73_an_restarted_p1 : 1; /* SES_CTRL_mux_eipr_TYPE[10] - RO */ 3003 uint32_t p_mux_cl73_an_restarted_p2 : 1; /* SES_CTRL_mux_eipr_TYPE[09] - RO */ 3004 uint32_t p_mux_cl73_an_complete : 1; /* SES_CTRL_mux_eipr_TYPE[08] - RO */ 3005 uint32_t p_mux_cl73_an_restarted : 1; /* SES_CTRL_mux_eipr_TYPE[07] - RO */ 3006 uint32_t p_mux_fifoerr : 1; /* SES_CTRL_mux_eipr_TYPE[06] - RO */ 3007 uint32_t p_mux_pcs_mon_lock_found : 1; /* SES_CTRL_mux_eipr_TYPE[05] - RO */ 3008 uint32_t p_mux_pcs_mon_lock_lost : 1; /* SES_CTRL_mux_eipr_TYPE[04] - RO */ 3009 uint32_t reserved_03 : 1; /* SES_CTRL_mux_eipr_TYPE[03] - RSVD */ 3010 uint32_t reserved_02 : 1; /* SES_CTRL_mux_eipr_TYPE[02] - RSVD */ 3011 uint32_t p_cl91_tx_pcs_align_found : 1; /* SES_CTRL_mux_eipr_TYPE[01] - RO */ 3012 uint32_t p_cl91_tx_pcs_align_lost : 1; /* SES_CTRL_mux_eipr_TYPE[00] - RO */ 3013 #endif /* IS_BIG_ENDIAN */ 3014 #if IS_LITTLE_ENDIAN 3015 uint32_t p_cl91_tx_pcs_align_lost : 1; /* SES_CTRL_mux_eipr_TYPE[00] - RO */ 3016 uint32_t p_cl91_tx_pcs_align_found : 1; /* SES_CTRL_mux_eipr_TYPE[01] - RO */ 3017 uint32_t reserved_02 : 1; /* SES_CTRL_mux_eipr_TYPE[02] - RSVD */ 3018 uint32_t reserved_03 : 1; /* SES_CTRL_mux_eipr_TYPE[03] - RSVD */ 3019 uint32_t p_mux_pcs_mon_lock_lost : 1; /* SES_CTRL_mux_eipr_TYPE[04] - RO */ 3020 uint32_t p_mux_pcs_mon_lock_found : 1; /* SES_CTRL_mux_eipr_TYPE[05] - RO */ 3021 uint32_t p_mux_fifoerr : 1; /* SES_CTRL_mux_eipr_TYPE[06] - RO */ 3022 uint32_t p_mux_cl73_an_restarted : 1; /* SES_CTRL_mux_eipr_TYPE[07] - RO */ 3023 uint32_t p_mux_cl73_an_complete : 1; /* SES_CTRL_mux_eipr_TYPE[08] - RO */ 3024 uint32_t p_mux_cl73_an_restarted_p2 : 1; /* SES_CTRL_mux_eipr_TYPE[09] - RO */ 3025 uint32_t p_mux_cl73_an_restarted_p1 : 1; /* SES_CTRL_mux_eipr_TYPE[10] - RO */ 3026 uint32_t p_mux_cl73_an_complete_p2 : 1; /* SES_CTRL_mux_eipr_TYPE[11] - RO */ 3027 uint32_t p_mux_cl73_an_complete_p1 : 1; /* SES_CTRL_mux_eipr_TYPE[12] - RO */ 3028 uint32_t reserved_13 : 3; /* SES_CTRL_mux_eipr_TYPE[15:13] - RSVD */ 3029 uint32_t reserved : 16; 3030 #endif /* IS_LITTLE_ENDIAN */ 3031 } fields; 3032 } SES_CTRL_mux_eipr_TYPE; 3033 3034 typedef SES_CTRL_mux_eipr_TYPE SES_CTRL_MUX_EIPR_TYPE_T; 3035 3036 typedef union { 3037 uint32_t data; 3038 struct { 3039 #if IS_BIG_ENDIAN 3040 uint32_t reserved : 16; 3041 uint32_t reserved_13 : 3; /* SES_CTRL_mux_eier_TYPE[15:13] - RSVD */ 3042 uint32_t enable_mux_cl73_an_complete_p1 : 1; /* SES_CTRL_mux_eier_TYPE[12] - WO */ 3043 uint32_t enable_mux_cl73_an_complete_p2 : 1; /* SES_CTRL_mux_eier_TYPE[11] - WO */ 3044 uint32_t enable_mux_cl73_an_restarted_p1 : 1; /* SES_CTRL_mux_eier_TYPE[10] - WO */ 3045 uint32_t enable_mux_cl73_an_restarted_p2 : 1; /* SES_CTRL_mux_eier_TYPE[09] - WO */ 3046 uint32_t enable_mux_cl73_an_complete : 1; /* SES_CTRL_mux_eier_TYPE[08] - WO */ 3047 uint32_t enable_mux_cl73_an_restarted : 1; /* SES_CTRL_mux_eier_TYPE[07] - WO */ 3048 uint32_t enable_mux_fifoerr : 1; /* SES_CTRL_mux_eier_TYPE[06] - WO */ 3049 uint32_t enable_mux_pcs_mon_lock_found : 1; /* SES_CTRL_mux_eier_TYPE[05] - WO */ 3050 uint32_t enable_mux_pcs_mon_lock_lost : 1; /* SES_CTRL_mux_eier_TYPE[04] - WO */ 3051 uint32_t reserved_03 : 1; /* SES_CTRL_mux_eier_TYPE[03] - RSVD */ 3052 uint32_t reserved_02 : 1; /* SES_CTRL_mux_eier_TYPE[02] - RSVD */ 3053 uint32_t enable_cl91_tx_pcs_align_found : 1; /* SES_CTRL_mux_eier_TYPE[01] - WO */ 3054 uint32_t enable_cl91_tx_pcs_align_lost : 1; /* SES_CTRL_mux_eier_TYPE[00] - WO */ 3055 #endif /* IS_BIG_ENDIAN */ 3056 #if IS_LITTLE_ENDIAN 3057 uint32_t enable_cl91_tx_pcs_align_lost : 1; /* SES_CTRL_mux_eier_TYPE[00] - WO */ 3058 uint32_t enable_cl91_tx_pcs_align_found : 1; /* SES_CTRL_mux_eier_TYPE[01] - WO */ 3059 uint32_t reserved_02 : 1; /* SES_CTRL_mux_eier_TYPE[02] - RSVD */ 3060 uint32_t reserved_03 : 1; /* SES_CTRL_mux_eier_TYPE[03] - RSVD */ 3061 uint32_t enable_mux_pcs_mon_lock_lost : 1; /* SES_CTRL_mux_eier_TYPE[04] - WO */ 3062 uint32_t enable_mux_pcs_mon_lock_found : 1; /* SES_CTRL_mux_eier_TYPE[05] - WO */ 3063 uint32_t enable_mux_fifoerr : 1; /* SES_CTRL_mux_eier_TYPE[06] - WO */ 3064 uint32_t enable_mux_cl73_an_restarted : 1; /* SES_CTRL_mux_eier_TYPE[07] - WO */ 3065 uint32_t enable_mux_cl73_an_complete : 1; /* SES_CTRL_mux_eier_TYPE[08] - WO */ 3066 uint32_t enable_mux_cl73_an_restarted_p2 : 1; /* SES_CTRL_mux_eier_TYPE[09] - WO */ 3067 uint32_t enable_mux_cl73_an_restarted_p1 : 1; /* SES_CTRL_mux_eier_TYPE[10] - WO */ 3068 uint32_t enable_mux_cl73_an_complete_p2 : 1; /* SES_CTRL_mux_eier_TYPE[11] - WO */ 3069 uint32_t enable_mux_cl73_an_complete_p1 : 1; /* SES_CTRL_mux_eier_TYPE[12] - WO */ 3070 uint32_t reserved_13 : 3; /* SES_CTRL_mux_eier_TYPE[15:13] - RSVD */ 3071 uint32_t reserved : 16; 3072 #endif /* IS_LITTLE_ENDIAN */ 3073 } fields; 3074 } SES_CTRL_mux_eier_TYPE; 3075 3076 typedef SES_CTRL_mux_eier_TYPE SES_CTRL_MUX_EIER_TYPE_T; 3077 3078 typedef union { 3079 uint32_t data; 3080 struct { 3081 #if IS_BIG_ENDIAN 3082 uint32_t reserved : 16; 3083 uint32_t gpio_3_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[15] - WO */ 3084 uint32_t gpio_3_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[14:12] - WO */ 3085 uint32_t gpio_2_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[11] - WO */ 3086 uint32_t gpio_2_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[10:08] - WO */ 3087 uint32_t gpio_1_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[07] - WO */ 3088 uint32_t gpio_1_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[06:04] - WO */ 3089 uint32_t gpio_0_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[03] - WO */ 3090 uint32_t gpio_0_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[02:00] - WO */ 3091 #endif /* IS_BIG_ENDIAN */ 3092 #if IS_LITTLE_ENDIAN 3093 uint32_t gpio_0_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[02:00] - WO */ 3094 uint32_t gpio_0_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[03] - WO */ 3095 uint32_t gpio_1_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[06:04] - WO */ 3096 uint32_t gpio_1_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[07] - WO */ 3097 uint32_t gpio_2_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[10:08] - WO */ 3098 uint32_t gpio_2_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[11] - WO */ 3099 uint32_t gpio_3_out_sel : 3; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[14:12] - WO */ 3100 uint32_t gpio_3_val : 1; /* SES_CTRL_general_purpose_IO_ctrl0_TYPE[15] - WO */ 3101 uint32_t reserved : 16; 3102 #endif /* IS_LITTLE_ENDIAN */ 3103 } fields; 3104 } SES_CTRL_general_purpose_IO_ctrl0_TYPE; 3105 3106 typedef SES_CTRL_general_purpose_IO_ctrl0_TYPE SES_CTRL_GENERAL_PURPOSE_IO_CTRL0_TYPE_T; 3107 3108 typedef union { 3109 uint32_t data; 3110 struct { 3111 #if IS_BIG_ENDIAN 3112 uint32_t reserved : 16; 3113 uint32_t reserved_15 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[15] - RSVD */ 3114 uint32_t qsfp_gpio_sel1 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[14:12] - WO */ 3115 uint32_t en_mod_intrn_gpio_0 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[11] - WO */ 3116 uint32_t qsfp_gpio_sel0 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[10:08] - WO */ 3117 uint32_t reserved_07 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[07] - RSVD */ 3118 uint32_t reserved_04 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[06:04] - RSVD */ 3119 uint32_t reserved_03 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[03] - RSVD */ 3120 uint32_t reserved_00 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[02:00] - RSVD */ 3121 #endif /* IS_BIG_ENDIAN */ 3122 #if IS_LITTLE_ENDIAN 3123 uint32_t reserved_00 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[02:00] - RSVD */ 3124 uint32_t reserved_03 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[03] - RSVD */ 3125 uint32_t reserved_04 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[06:04] - RSVD */ 3126 uint32_t reserved_07 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[07] - RSVD */ 3127 uint32_t qsfp_gpio_sel0 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[10:08] - WO */ 3128 uint32_t en_mod_intrn_gpio_0 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[11] - WO */ 3129 uint32_t qsfp_gpio_sel1 : 3; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[14:12] - WO */ 3130 uint32_t reserved_15 : 1; /* SES_CTRL_general_purpose_IO_ctrl1_TYPE[15] - RSVD */ 3131 uint32_t reserved : 16; 3132 #endif /* IS_LITTLE_ENDIAN */ 3133 } fields; 3134 } SES_CTRL_general_purpose_IO_ctrl1_TYPE; 3135 3136 typedef SES_CTRL_general_purpose_IO_ctrl1_TYPE SES_CTRL_GENERAL_PURPOSE_IO_CTRL1_TYPE_T; 3137 3138 typedef union { 3139 uint32_t data; 3140 struct { 3141 #if IS_BIG_ENDIAN 3142 uint32_t reserved : 16; 3143 uint32_t reserved_08 : 8; /* SES_CTRL_test_pad_ctrl_TYPE[15:08] - RSVD */ 3144 uint32_t gpio_open_drain_en : 6; /* SES_CTRL_test_pad_ctrl_TYPE[07:02] - WO */ 3145 uint32_t reserved_01 : 1; /* SES_CTRL_test_pad_ctrl_TYPE[01] - RSVD */ 3146 uint32_t reserved_00 : 1; /* SES_CTRL_test_pad_ctrl_TYPE[00] - RSVD */ 3147 #endif /* IS_BIG_ENDIAN */ 3148 #if IS_LITTLE_ENDIAN 3149 uint32_t reserved_00 : 1; /* SES_CTRL_test_pad_ctrl_TYPE[00] - RSVD */ 3150 uint32_t reserved_01 : 1; /* SES_CTRL_test_pad_ctrl_TYPE[01] - RSVD */ 3151 uint32_t gpio_open_drain_en : 6; /* SES_CTRL_test_pad_ctrl_TYPE[07:02] - WO */ 3152 uint32_t reserved_08 : 8; /* SES_CTRL_test_pad_ctrl_TYPE[15:08] - RSVD */ 3153 uint32_t reserved : 16; 3154 #endif /* IS_LITTLE_ENDIAN */ 3155 } fields; 3156 } SES_CTRL_test_pad_ctrl_TYPE; 3157 3158 typedef SES_CTRL_test_pad_ctrl_TYPE SES_CTRL_TEST_PAD_CTRL_TYPE_T; 3159 3160 typedef union { 3161 uint32_t data; 3162 struct { 3163 #if IS_BIG_ENDIAN 3164 uint32_t reserved : 16; 3165 uint32_t reserved_08 : 8; /* SES_CTRL_clock_scaler_ctrl_TYPE[15:08] - RSVD */ 3166 uint32_t reserved_04 : 4; /* SES_CTRL_clock_scaler_ctrl_TYPE[07:04] - RSVD */ 3167 uint32_t reserved_03 : 1; /* SES_CTRL_clock_scaler_ctrl_TYPE[03] - RSVD */ 3168 uint32_t clock_scaler_code : 3; /* SES_CTRL_clock_scaler_ctrl_TYPE[02:00] - WO */ 3169 #endif /* IS_BIG_ENDIAN */ 3170 #if IS_LITTLE_ENDIAN 3171 uint32_t clock_scaler_code : 3; /* SES_CTRL_clock_scaler_ctrl_TYPE[02:00] - WO */ 3172 uint32_t reserved_03 : 1; /* SES_CTRL_clock_scaler_ctrl_TYPE[03] - RSVD */ 3173 uint32_t reserved_04 : 4; /* SES_CTRL_clock_scaler_ctrl_TYPE[07:04] - RSVD */ 3174 uint32_t reserved_08 : 8; /* SES_CTRL_clock_scaler_ctrl_TYPE[15:08] - RSVD */ 3175 uint32_t reserved : 16; 3176 #endif /* IS_LITTLE_ENDIAN */ 3177 } fields; 3178 } SES_CTRL_clock_scaler_ctrl_TYPE; 3179 3180 typedef SES_CTRL_clock_scaler_ctrl_TYPE SES_CTRL_CLOCK_SCALER_CTRL_TYPE_T; 3181 3182 3183 /*-----------------------------------------------*/ 3184 /* Structs for SES_MODULE_CNTRL Bank */ 3185 /*-----------------------------------------------*/ 3186 typedef union { 3187 uint32_t data; 3188 struct { 3189 #if IS_BIG_ENDIAN 3190 uint32_t reserved : 16; 3191 uint32_t i2c_en : 1; /* SES_MODULE_CNTRL_control_TYPE[15] - WO */ 3192 uint32_t i2cflush : 1; /* SES_MODULE_CNTRL_control_TYPE[14] - WO */ 3193 uint32_t sl_add_cnt : 1; /* SES_MODULE_CNTRL_control_TYPE[13] - WO */ 3194 uint32_t sl_dat_cnt : 1; /* SES_MODULE_CNTRL_control_TYPE[12] - WO */ 3195 uint32_t reserved_06 : 6; /* SES_MODULE_CNTRL_control_TYPE[11:06] - RSVD */ 3196 uint32_t slave_cmd : 1; /* SES_MODULE_CNTRL_control_TYPE[05] - WO */ 3197 uint32_t reserved_02 : 3; /* SES_MODULE_CNTRL_control_TYPE[04:02] - RSVD */ 3198 uint32_t extend_cmd : 2; /* SES_MODULE_CNTRL_control_TYPE[01:00] - WO */ 3199 #endif /* IS_BIG_ENDIAN */ 3200 #if IS_LITTLE_ENDIAN 3201 uint32_t extend_cmd : 2; /* SES_MODULE_CNTRL_control_TYPE[01:00] - WO */ 3202 uint32_t reserved_02 : 3; /* SES_MODULE_CNTRL_control_TYPE[04:02] - RSVD */ 3203 uint32_t slave_cmd : 1; /* SES_MODULE_CNTRL_control_TYPE[05] - WO */ 3204 uint32_t reserved_06 : 6; /* SES_MODULE_CNTRL_control_TYPE[11:06] - RSVD */ 3205 uint32_t sl_dat_cnt : 1; /* SES_MODULE_CNTRL_control_TYPE[12] - WO */ 3206 uint32_t sl_add_cnt : 1; /* SES_MODULE_CNTRL_control_TYPE[13] - WO */ 3207 uint32_t i2cflush : 1; /* SES_MODULE_CNTRL_control_TYPE[14] - WO */ 3208 uint32_t i2c_en : 1; /* SES_MODULE_CNTRL_control_TYPE[15] - WO */ 3209 uint32_t reserved : 16; 3210 #endif /* IS_LITTLE_ENDIAN */ 3211 } fields; 3212 } SES_MODULE_CNTRL_control_TYPE; 3213 3214 typedef SES_MODULE_CNTRL_control_TYPE SES_MODULE_CNTRL_CONTROL_TYPE_T; 3215 3216 typedef union { 3217 uint32_t data; 3218 struct { 3219 #if IS_BIG_ENDIAN 3220 uint32_t reserved : 16; 3221 uint32_t reserved_09 : 7; /* SES_MODULE_CNTRL_status_TYPE[15:09] - RSVD */ 3222 uint32_t scl_live_status : 1; /* SES_MODULE_CNTRL_status_TYPE[08] - RO */ 3223 uint32_t scl_latch_low : 1; /* SES_MODULE_CNTRL_status_TYPE[07] - RO */ 3224 uint32_t scl_latch_high : 1; /* SES_MODULE_CNTRL_status_TYPE[06] - RO */ 3225 uint32_t sda_live_status : 1; /* SES_MODULE_CNTRL_status_TYPE[05] - RO */ 3226 uint32_t sda_latch_low : 1; /* SES_MODULE_CNTRL_status_TYPE[04] - RO */ 3227 uint32_t sda_latch_high : 1; /* SES_MODULE_CNTRL_status_TYPE[03] - RO */ 3228 uint32_t i2cm_stat : 2; /* SES_MODULE_CNTRL_status_TYPE[02:01] - RO */ 3229 uint32_t xaction_done : 1; /* SES_MODULE_CNTRL_status_TYPE[00] - RO */ 3230 #endif /* IS_BIG_ENDIAN */ 3231 #if IS_LITTLE_ENDIAN 3232 uint32_t xaction_done : 1; /* SES_MODULE_CNTRL_status_TYPE[00] - RO */ 3233 uint32_t i2cm_stat : 2; /* SES_MODULE_CNTRL_status_TYPE[02:01] - RO */ 3234 uint32_t sda_latch_high : 1; /* SES_MODULE_CNTRL_status_TYPE[03] - RO */ 3235 uint32_t sda_latch_low : 1; /* SES_MODULE_CNTRL_status_TYPE[04] - RO */ 3236 uint32_t sda_live_status : 1; /* SES_MODULE_CNTRL_status_TYPE[05] - RO */ 3237 uint32_t scl_latch_high : 1; /* SES_MODULE_CNTRL_status_TYPE[06] - RO */ 3238 uint32_t scl_latch_low : 1; /* SES_MODULE_CNTRL_status_TYPE[07] - RO */ 3239 uint32_t scl_live_status : 1; /* SES_MODULE_CNTRL_status_TYPE[08] - RO */ 3240 uint32_t reserved_09 : 7; /* SES_MODULE_CNTRL_status_TYPE[15:09] - RSVD */ 3241 uint32_t reserved : 16; 3242 #endif /* IS_LITTLE_ENDIAN */ 3243 } fields; 3244 } SES_MODULE_CNTRL_status_TYPE; 3245 3246 typedef SES_MODULE_CNTRL_status_TYPE SES_MODULE_CNTRL_STATUS_TYPE_T; 3247 3248 typedef union { 3249 uint32_t data; 3250 struct { 3251 #if IS_BIG_ENDIAN 3252 uint32_t reserved : 16; 3253 uint32_t reserved_13 : 3; /* SES_MODULE_CNTRL_xfer_count_TYPE[15:13] - RSVD */ 3254 uint32_t chk_live_status : 1; /* SES_MODULE_CNTRL_xfer_count_TYPE[12] - WO */ 3255 uint32_t page_2ld : 4; /* SES_MODULE_CNTRL_xfer_count_TYPE[11:08] - WO */ 3256 uint32_t xfer_cnt : 8; /* SES_MODULE_CNTRL_xfer_count_TYPE[07:00] - WO */ 3257 #endif /* IS_BIG_ENDIAN */ 3258 #if IS_LITTLE_ENDIAN 3259 uint32_t xfer_cnt : 8; /* SES_MODULE_CNTRL_xfer_count_TYPE[07:00] - WO */ 3260 uint32_t page_2ld : 4; /* SES_MODULE_CNTRL_xfer_count_TYPE[11:08] - WO */ 3261 uint32_t chk_live_status : 1; /* SES_MODULE_CNTRL_xfer_count_TYPE[12] - WO */ 3262 uint32_t reserved_13 : 3; /* SES_MODULE_CNTRL_xfer_count_TYPE[15:13] - RSVD */ 3263 uint32_t reserved : 16; 3264 #endif /* IS_LITTLE_ENDIAN */ 3265 } fields; 3266 } SES_MODULE_CNTRL_xfer_count_TYPE; 3267 3268 typedef SES_MODULE_CNTRL_xfer_count_TYPE SES_MODULE_CNTRL_XFER_COUNT_TYPE_T; 3269 3270 typedef union { 3271 uint32_t data; 3272 struct { 3273 #if IS_BIG_ENDIAN 3274 uint32_t reserved : 16; 3275 uint32_t slave_addr : 16; /* SES_MODULE_CNTRL_address_TYPE[15:00] - WO */ 3276 #endif /* IS_BIG_ENDIAN */ 3277 #if IS_LITTLE_ENDIAN 3278 uint32_t slave_addr : 16; /* SES_MODULE_CNTRL_address_TYPE[15:00] - WO */ 3279 uint32_t reserved : 16; 3280 #endif /* IS_LITTLE_ENDIAN */ 3281 } fields; 3282 } SES_MODULE_CNTRL_address_TYPE; 3283 3284 typedef SES_MODULE_CNTRL_address_TYPE SES_MODULE_CNTRL_ADDRESS_TYPE_T; 3285 3286 typedef union { 3287 uint32_t data; 3288 struct { 3289 #if IS_BIG_ENDIAN 3290 uint32_t reserved : 16; 3291 uint32_t xfer_addr : 16; /* SES_MODULE_CNTRL_xfer_address_TYPE[15:00] - WO */ 3292 #endif /* IS_BIG_ENDIAN */ 3293 #if IS_LITTLE_ENDIAN 3294 uint32_t xfer_addr : 16; /* SES_MODULE_CNTRL_xfer_address_TYPE[15:00] - WO */ 3295 uint32_t reserved : 16; 3296 #endif /* IS_LITTLE_ENDIAN */ 3297 } fields; 3298 } SES_MODULE_CNTRL_xfer_address_TYPE; 3299 3300 typedef SES_MODULE_CNTRL_xfer_address_TYPE SES_MODULE_CNTRL_XFER_ADDRESS_TYPE_T; 3301 3302 typedef union { 3303 uint32_t data; 3304 struct { 3305 #if IS_BIG_ENDIAN 3306 uint32_t reserved : 16; 3307 uint32_t sl_dev_add : 7; /* SES_MODULE_CNTRL_dev_id_TYPE[15:09] - WO */ 3308 uint32_t i2c_speed : 1; /* SES_MODULE_CNTRL_dev_id_TYPE[08] - WO */ 3309 uint32_t slave_addr_msb : 8; /* SES_MODULE_CNTRL_dev_id_TYPE[07:00] - WO */ 3310 #endif /* IS_BIG_ENDIAN */ 3311 #if IS_LITTLE_ENDIAN 3312 uint32_t slave_addr_msb : 8; /* SES_MODULE_CNTRL_dev_id_TYPE[07:00] - WO */ 3313 uint32_t i2c_speed : 1; /* SES_MODULE_CNTRL_dev_id_TYPE[08] - WO */ 3314 uint32_t sl_dev_add : 7; /* SES_MODULE_CNTRL_dev_id_TYPE[15:09] - WO */ 3315 uint32_t reserved : 16; 3316 #endif /* IS_LITTLE_ENDIAN */ 3317 } fields; 3318 } SES_MODULE_CNTRL_dev_id_TYPE; 3319 3320 typedef SES_MODULE_CNTRL_dev_id_TYPE SES_MODULE_CNTRL_DEV_ID_TYPE_T; 3321 3322 3323 /*-----------------------------------------------*/ 3324 /* Structs for SES_PAD_CTRL Bank */ 3325 /*-----------------------------------------------*/ 3326 typedef union { 3327 uint32_t data; 3328 struct { 3329 #if IS_BIG_ENDIAN 3330 uint32_t reserved : 16; 3331 uint32_t reserved_12 : 4; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[15:12] - RSVD */ 3332 uint32_t ext_uc_rstb_out_out_frcval : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[11] - WO */ 3333 uint32_t reserved_10 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[10] - RSVD */ 3334 uint32_t ext_uc_rstb_out_ibof : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[09] - WO */ 3335 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[08] - RSVD */ 3336 uint32_t reserved_07 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[07] - RSVD */ 3337 uint32_t reserved_06 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[06] - RSVD */ 3338 uint32_t reserved_05 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[05] - RSVD */ 3339 uint32_t reserved_04 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[04] - RSVD */ 3340 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[03] - RSVD */ 3341 uint32_t reserved_02 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[02] - RSVD */ 3342 uint32_t reserved_01 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[01] - RSVD */ 3343 uint32_t reserved_00 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[00] - RSVD */ 3344 #endif /* IS_BIG_ENDIAN */ 3345 #if IS_LITTLE_ENDIAN 3346 uint32_t reserved_00 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[00] - RSVD */ 3347 uint32_t reserved_01 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[01] - RSVD */ 3348 uint32_t reserved_02 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[02] - RSVD */ 3349 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[03] - RSVD */ 3350 uint32_t reserved_04 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[04] - RSVD */ 3351 uint32_t reserved_05 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[05] - RSVD */ 3352 uint32_t reserved_06 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[06] - RSVD */ 3353 uint32_t reserved_07 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[07] - RSVD */ 3354 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[08] - RSVD */ 3355 uint32_t ext_uc_rstb_out_ibof : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[09] - WO */ 3356 uint32_t reserved_10 : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[10] - RSVD */ 3357 uint32_t ext_uc_rstb_out_out_frcval : 1; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[11] - WO */ 3358 uint32_t reserved_12 : 4; /* SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE[15:12] - RSVD */ 3359 uint32_t reserved : 16; 3360 #endif /* IS_LITTLE_ENDIAN */ 3361 } fields; 3362 } SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE; 3363 3364 typedef SES_PAD_CTRL_ext_uc_rstb_out_control_TYPE SES_PAD_CTRL_EXT_UC_RSTB_OUT_CONTROL_TYPE_T; 3365 3366 typedef union { 3367 uint32_t data; 3368 struct { 3369 #if IS_BIG_ENDIAN 3370 uint32_t reserved : 16; 3371 uint32_t mod_lopwr_dglh_cnt : 4; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[15:12] - WO */ 3372 uint32_t mod_lopwr_out_frcval : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[11] - WO */ 3373 uint32_t mod_lopwr_invert_en : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[10] - WO */ 3374 uint32_t mod_lopwr_ibof : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[09] - WO */ 3375 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[08] - RSVD */ 3376 uint32_t mod_lopwr_sel2 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[07] - WO */ 3377 uint32_t mod_lopwr_sel1 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[06] - WO */ 3378 uint32_t mod_lopwr_sel0 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[05] - WO */ 3379 uint32_t mod_lopwr_ind : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[04] - WO */ 3380 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[03] - RSVD */ 3381 uint32_t mod_lopwr_pdn : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[02] - WO */ 3382 uint32_t mod_lopwr_pup : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[01] - WO */ 3383 uint32_t mod_lopwr_oeb : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[00] - WO */ 3384 #endif /* IS_BIG_ENDIAN */ 3385 #if IS_LITTLE_ENDIAN 3386 uint32_t mod_lopwr_oeb : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[00] - WO */ 3387 uint32_t mod_lopwr_pup : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[01] - WO */ 3388 uint32_t mod_lopwr_pdn : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[02] - WO */ 3389 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[03] - RSVD */ 3390 uint32_t mod_lopwr_ind : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[04] - WO */ 3391 uint32_t mod_lopwr_sel0 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[05] - WO */ 3392 uint32_t mod_lopwr_sel1 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[06] - WO */ 3393 uint32_t mod_lopwr_sel2 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[07] - WO */ 3394 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[08] - RSVD */ 3395 uint32_t mod_lopwr_ibof : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[09] - WO */ 3396 uint32_t mod_lopwr_invert_en : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[10] - WO */ 3397 uint32_t mod_lopwr_out_frcval : 1; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[11] - WO */ 3398 uint32_t mod_lopwr_dglh_cnt : 4; /* SES_PAD_CTRL_mod_lopwr_control_TYPE[15:12] - WO */ 3399 uint32_t reserved : 16; 3400 #endif /* IS_LITTLE_ENDIAN */ 3401 } fields; 3402 } SES_PAD_CTRL_mod_lopwr_control_TYPE; 3403 3404 typedef SES_PAD_CTRL_mod_lopwr_control_TYPE SES_PAD_CTRL_MOD_LOPWR_CONTROL_TYPE_T; 3405 3406 typedef union { 3407 uint32_t data; 3408 struct { 3409 #if IS_BIG_ENDIAN 3410 uint32_t reserved : 16; 3411 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[15:03] - RSVD */ 3412 uint32_t mod_lopwr_din : 1; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[02] - RO */ 3413 uint32_t mod_lopwr_din_ll : 1; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[01] - RO */ 3414 uint32_t mod_lopwr_din_lh : 1; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[00] - RO */ 3415 #endif /* IS_BIG_ENDIAN */ 3416 #if IS_LITTLE_ENDIAN 3417 uint32_t mod_lopwr_din_lh : 1; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[00] - RO */ 3418 uint32_t mod_lopwr_din_ll : 1; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[01] - RO */ 3419 uint32_t mod_lopwr_din : 1; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[02] - RO */ 3420 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_lopwr_status_TYPE[15:03] - RSVD */ 3421 uint32_t reserved : 16; 3422 #endif /* IS_LITTLE_ENDIAN */ 3423 } fields; 3424 } SES_PAD_CTRL_mod_lopwr_status_TYPE; 3425 3426 typedef SES_PAD_CTRL_mod_lopwr_status_TYPE SES_PAD_CTRL_MOD_LOPWR_STATUS_TYPE_T; 3427 3428 typedef union { 3429 uint32_t data; 3430 struct { 3431 #if IS_BIG_ENDIAN 3432 uint32_t reserved : 16; 3433 uint32_t mod_abs_dglh_cnt : 4; /* SES_PAD_CTRL_mod_abs_control_TYPE[15:12] - WO */ 3434 uint32_t mod_abs_out_frcval : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[11] - WO */ 3435 uint32_t mod_abs_invert_en : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[10] - WO */ 3436 uint32_t mod_abs_ibof : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[09] - WO */ 3437 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[08] - RSVD */ 3438 uint32_t mod_abs_sel2 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[07] - WO */ 3439 uint32_t mod_abs_sel1 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[06] - WO */ 3440 uint32_t mod_abs_sel0 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[05] - WO */ 3441 uint32_t mod_abs_ind : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[04] - WO */ 3442 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[03] - RSVD */ 3443 uint32_t mod_abs_pdn : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[02] - WO */ 3444 uint32_t mod_abs_pup : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[01] - WO */ 3445 uint32_t mod_abs_oeb : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[00] - WO */ 3446 #endif /* IS_BIG_ENDIAN */ 3447 #if IS_LITTLE_ENDIAN 3448 uint32_t mod_abs_oeb : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[00] - WO */ 3449 uint32_t mod_abs_pup : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[01] - WO */ 3450 uint32_t mod_abs_pdn : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[02] - WO */ 3451 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[03] - RSVD */ 3452 uint32_t mod_abs_ind : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[04] - WO */ 3453 uint32_t mod_abs_sel0 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[05] - WO */ 3454 uint32_t mod_abs_sel1 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[06] - WO */ 3455 uint32_t mod_abs_sel2 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[07] - WO */ 3456 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[08] - RSVD */ 3457 uint32_t mod_abs_ibof : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[09] - WO */ 3458 uint32_t mod_abs_invert_en : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[10] - WO */ 3459 uint32_t mod_abs_out_frcval : 1; /* SES_PAD_CTRL_mod_abs_control_TYPE[11] - WO */ 3460 uint32_t mod_abs_dglh_cnt : 4; /* SES_PAD_CTRL_mod_abs_control_TYPE[15:12] - WO */ 3461 uint32_t reserved : 16; 3462 #endif /* IS_LITTLE_ENDIAN */ 3463 } fields; 3464 } SES_PAD_CTRL_mod_abs_control_TYPE; 3465 3466 typedef SES_PAD_CTRL_mod_abs_control_TYPE SES_PAD_CTRL_MOD_ABS_CONTROL_TYPE_T; 3467 3468 typedef union { 3469 uint32_t data; 3470 struct { 3471 #if IS_BIG_ENDIAN 3472 uint32_t reserved : 16; 3473 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_abs_status_TYPE[15:03] - RSVD */ 3474 uint32_t mod_abs_din : 1; /* SES_PAD_CTRL_mod_abs_status_TYPE[02] - RO */ 3475 uint32_t mod_abs_din_ll : 1; /* SES_PAD_CTRL_mod_abs_status_TYPE[01] - RO */ 3476 uint32_t mod_abs_din_lh : 1; /* SES_PAD_CTRL_mod_abs_status_TYPE[00] - RO */ 3477 #endif /* IS_BIG_ENDIAN */ 3478 #if IS_LITTLE_ENDIAN 3479 uint32_t mod_abs_din_lh : 1; /* SES_PAD_CTRL_mod_abs_status_TYPE[00] - RO */ 3480 uint32_t mod_abs_din_ll : 1; /* SES_PAD_CTRL_mod_abs_status_TYPE[01] - RO */ 3481 uint32_t mod_abs_din : 1; /* SES_PAD_CTRL_mod_abs_status_TYPE[02] - RO */ 3482 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_abs_status_TYPE[15:03] - RSVD */ 3483 uint32_t reserved : 16; 3484 #endif /* IS_LITTLE_ENDIAN */ 3485 } fields; 3486 } SES_PAD_CTRL_mod_abs_status_TYPE; 3487 3488 typedef SES_PAD_CTRL_mod_abs_status_TYPE SES_PAD_CTRL_MOD_ABS_STATUS_TYPE_T; 3489 3490 typedef union { 3491 uint32_t data; 3492 struct { 3493 #if IS_BIG_ENDIAN 3494 uint32_t reserved : 16; 3495 uint32_t mod_rstn_dglh_cnt : 4; /* SES_PAD_CTRL_mod_rstn_control_TYPE[15:12] - WO */ 3496 uint32_t mod_rstn_out_frcval : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[11] - WO */ 3497 uint32_t mod_rstn_invert_en : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[10] - WO */ 3498 uint32_t mod_rstn_ibof : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[09] - WO */ 3499 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[08] - RSVD */ 3500 uint32_t mod_rstn_sel2 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[07] - WO */ 3501 uint32_t mod_rstn_sel1 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[06] - WO */ 3502 uint32_t mod_rstn_sel0 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[05] - WO */ 3503 uint32_t mod_rstn_ind : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[04] - WO */ 3504 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[03] - RSVD */ 3505 uint32_t mod_rstn_pdn : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[02] - WO */ 3506 uint32_t mod_rstn_pup : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[01] - WO */ 3507 uint32_t mod_rstn_oeb : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[00] - WO */ 3508 #endif /* IS_BIG_ENDIAN */ 3509 #if IS_LITTLE_ENDIAN 3510 uint32_t mod_rstn_oeb : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[00] - WO */ 3511 uint32_t mod_rstn_pup : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[01] - WO */ 3512 uint32_t mod_rstn_pdn : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[02] - WO */ 3513 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[03] - RSVD */ 3514 uint32_t mod_rstn_ind : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[04] - WO */ 3515 uint32_t mod_rstn_sel0 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[05] - WO */ 3516 uint32_t mod_rstn_sel1 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[06] - WO */ 3517 uint32_t mod_rstn_sel2 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[07] - WO */ 3518 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[08] - RSVD */ 3519 uint32_t mod_rstn_ibof : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[09] - WO */ 3520 uint32_t mod_rstn_invert_en : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[10] - WO */ 3521 uint32_t mod_rstn_out_frcval : 1; /* SES_PAD_CTRL_mod_rstn_control_TYPE[11] - WO */ 3522 uint32_t mod_rstn_dglh_cnt : 4; /* SES_PAD_CTRL_mod_rstn_control_TYPE[15:12] - WO */ 3523 uint32_t reserved : 16; 3524 #endif /* IS_LITTLE_ENDIAN */ 3525 } fields; 3526 } SES_PAD_CTRL_mod_rstn_control_TYPE; 3527 3528 typedef SES_PAD_CTRL_mod_rstn_control_TYPE SES_PAD_CTRL_MOD_RSTN_CONTROL_TYPE_T; 3529 3530 typedef union { 3531 uint32_t data; 3532 struct { 3533 #if IS_BIG_ENDIAN 3534 uint32_t reserved : 16; 3535 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_rstn_status_TYPE[15:03] - RSVD */ 3536 uint32_t mod_rstn_din : 1; /* SES_PAD_CTRL_mod_rstn_status_TYPE[02] - RO */ 3537 uint32_t mod_rstn_din_ll : 1; /* SES_PAD_CTRL_mod_rstn_status_TYPE[01] - RO */ 3538 uint32_t mod_rstn_din_lh : 1; /* SES_PAD_CTRL_mod_rstn_status_TYPE[00] - RO */ 3539 #endif /* IS_BIG_ENDIAN */ 3540 #if IS_LITTLE_ENDIAN 3541 uint32_t mod_rstn_din_lh : 1; /* SES_PAD_CTRL_mod_rstn_status_TYPE[00] - RO */ 3542 uint32_t mod_rstn_din_ll : 1; /* SES_PAD_CTRL_mod_rstn_status_TYPE[01] - RO */ 3543 uint32_t mod_rstn_din : 1; /* SES_PAD_CTRL_mod_rstn_status_TYPE[02] - RO */ 3544 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_rstn_status_TYPE[15:03] - RSVD */ 3545 uint32_t reserved : 16; 3546 #endif /* IS_LITTLE_ENDIAN */ 3547 } fields; 3548 } SES_PAD_CTRL_mod_rstn_status_TYPE; 3549 3550 typedef SES_PAD_CTRL_mod_rstn_status_TYPE SES_PAD_CTRL_MOD_RSTN_STATUS_TYPE_T; 3551 3552 typedef union { 3553 uint32_t data; 3554 struct { 3555 #if IS_BIG_ENDIAN 3556 uint32_t reserved : 16; 3557 uint32_t mod_intrn_dglh_cnt : 4; /* SES_PAD_CTRL_mod_intrn_control_TYPE[15:12] - WO */ 3558 uint32_t mod_intrn_out_frcval : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[11] - WO */ 3559 uint32_t mod_intrn_invert_en : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[10] - WO */ 3560 uint32_t mod_intrn_ibof : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[09] - WO */ 3561 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[08] - RSVD */ 3562 uint32_t mod_intrn_sel2 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[07] - WO */ 3563 uint32_t mod_intrn_sel1 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[06] - WO */ 3564 uint32_t mod_intrn_sel0 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[05] - WO */ 3565 uint32_t mod_intrn_ind : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[04] - WO */ 3566 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[03] - RSVD */ 3567 uint32_t mod_intrn_pdn : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[02] - WO */ 3568 uint32_t mod_intrn_pup : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[01] - WO */ 3569 uint32_t mod_intrn_oeb : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[00] - WO */ 3570 #endif /* IS_BIG_ENDIAN */ 3571 #if IS_LITTLE_ENDIAN 3572 uint32_t mod_intrn_oeb : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[00] - WO */ 3573 uint32_t mod_intrn_pup : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[01] - WO */ 3574 uint32_t mod_intrn_pdn : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[02] - WO */ 3575 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[03] - RSVD */ 3576 uint32_t mod_intrn_ind : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[04] - WO */ 3577 uint32_t mod_intrn_sel0 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[05] - WO */ 3578 uint32_t mod_intrn_sel1 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[06] - WO */ 3579 uint32_t mod_intrn_sel2 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[07] - WO */ 3580 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[08] - RSVD */ 3581 uint32_t mod_intrn_ibof : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[09] - WO */ 3582 uint32_t mod_intrn_invert_en : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[10] - WO */ 3583 uint32_t mod_intrn_out_frcval : 1; /* SES_PAD_CTRL_mod_intrn_control_TYPE[11] - WO */ 3584 uint32_t mod_intrn_dglh_cnt : 4; /* SES_PAD_CTRL_mod_intrn_control_TYPE[15:12] - WO */ 3585 uint32_t reserved : 16; 3586 #endif /* IS_LITTLE_ENDIAN */ 3587 } fields; 3588 } SES_PAD_CTRL_mod_intrn_control_TYPE; 3589 3590 typedef SES_PAD_CTRL_mod_intrn_control_TYPE SES_PAD_CTRL_MOD_INTRN_CONTROL_TYPE_T; 3591 3592 typedef union { 3593 uint32_t data; 3594 struct { 3595 #if IS_BIG_ENDIAN 3596 uint32_t reserved : 16; 3597 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_intrn_status_TYPE[15:03] - RSVD */ 3598 uint32_t mod_intrn_din : 1; /* SES_PAD_CTRL_mod_intrn_status_TYPE[02] - RO */ 3599 uint32_t mod_intrn_din_ll : 1; /* SES_PAD_CTRL_mod_intrn_status_TYPE[01] - RO */ 3600 uint32_t mod_intrn_din_lh : 1; /* SES_PAD_CTRL_mod_intrn_status_TYPE[00] - RO */ 3601 #endif /* IS_BIG_ENDIAN */ 3602 #if IS_LITTLE_ENDIAN 3603 uint32_t mod_intrn_din_lh : 1; /* SES_PAD_CTRL_mod_intrn_status_TYPE[00] - RO */ 3604 uint32_t mod_intrn_din_ll : 1; /* SES_PAD_CTRL_mod_intrn_status_TYPE[01] - RO */ 3605 uint32_t mod_intrn_din : 1; /* SES_PAD_CTRL_mod_intrn_status_TYPE[02] - RO */ 3606 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_intrn_status_TYPE[15:03] - RSVD */ 3607 uint32_t reserved : 16; 3608 #endif /* IS_LITTLE_ENDIAN */ 3609 } fields; 3610 } SES_PAD_CTRL_mod_intrn_status_TYPE; 3611 3612 typedef SES_PAD_CTRL_mod_intrn_status_TYPE SES_PAD_CTRL_MOD_INTRN_STATUS_TYPE_T; 3613 3614 typedef union { 3615 uint32_t data; 3616 struct { 3617 #if IS_BIG_ENDIAN 3618 uint32_t reserved : 16; 3619 uint32_t mod_tx_dis_lopwr2_dglh_cnt : 4; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[15:12] - WO */ 3620 uint32_t mod_tx_dis_lopwr2_out_frcval : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[11] - WO */ 3621 uint32_t mod_tx_dis_lopwr2_invert_en : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[10] - WO */ 3622 uint32_t mod_tx_dis_lopwr2_ibof : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[09] - WO */ 3623 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[08] - RSVD */ 3624 uint32_t mod_tx_dis_lopwr2_sel2 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[07] - WO */ 3625 uint32_t mod_tx_dis_lopwr2_sel1 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[06] - WO */ 3626 uint32_t mod_tx_dis_lopwr2_sel0 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[05] - WO */ 3627 uint32_t mod_tx_dis_lopwr2_ind : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[04] - WO */ 3628 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[03] - RSVD */ 3629 uint32_t mod_tx_dis_lopwr2_pdn : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[02] - WO */ 3630 uint32_t mod_tx_dis_lopwr2_pup : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[01] - WO */ 3631 uint32_t mod_tx_dis_lopwr2_oeb : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[00] - WO */ 3632 #endif /* IS_BIG_ENDIAN */ 3633 #if IS_LITTLE_ENDIAN 3634 uint32_t mod_tx_dis_lopwr2_oeb : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[00] - WO */ 3635 uint32_t mod_tx_dis_lopwr2_pup : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[01] - WO */ 3636 uint32_t mod_tx_dis_lopwr2_pdn : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[02] - WO */ 3637 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[03] - RSVD */ 3638 uint32_t mod_tx_dis_lopwr2_ind : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[04] - WO */ 3639 uint32_t mod_tx_dis_lopwr2_sel0 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[05] - WO */ 3640 uint32_t mod_tx_dis_lopwr2_sel1 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[06] - WO */ 3641 uint32_t mod_tx_dis_lopwr2_sel2 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[07] - WO */ 3642 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[08] - RSVD */ 3643 uint32_t mod_tx_dis_lopwr2_ibof : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[09] - WO */ 3644 uint32_t mod_tx_dis_lopwr2_invert_en : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[10] - WO */ 3645 uint32_t mod_tx_dis_lopwr2_out_frcval : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[11] - WO */ 3646 uint32_t mod_tx_dis_lopwr2_dglh_cnt : 4; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE[15:12] - WO */ 3647 uint32_t reserved : 16; 3648 #endif /* IS_LITTLE_ENDIAN */ 3649 } fields; 3650 } SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE; 3651 3652 typedef SES_PAD_CTRL_mod_tx_dis_lopwr2_control_TYPE SES_PAD_CTRL_MOD_TX_DIS_LOPWR2_CONTROL_TYPE_T; 3653 3654 typedef union { 3655 uint32_t data; 3656 struct { 3657 #if IS_BIG_ENDIAN 3658 uint32_t reserved : 16; 3659 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[15:03] - RSVD */ 3660 uint32_t mod_tx_dis_lopwr2_din : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[02] - RO */ 3661 uint32_t mod_tx_dis_lopwr2_din_ll : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[01] - RO */ 3662 uint32_t mod_tx_dis_lopwr2_din_lh : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[00] - RO */ 3663 #endif /* IS_BIG_ENDIAN */ 3664 #if IS_LITTLE_ENDIAN 3665 uint32_t mod_tx_dis_lopwr2_din_lh : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[00] - RO */ 3666 uint32_t mod_tx_dis_lopwr2_din_ll : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[01] - RO */ 3667 uint32_t mod_tx_dis_lopwr2_din : 1; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[02] - RO */ 3668 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE[15:03] - RSVD */ 3669 uint32_t reserved : 16; 3670 #endif /* IS_LITTLE_ENDIAN */ 3671 } fields; 3672 } SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE; 3673 3674 typedef SES_PAD_CTRL_mod_tx_dis_lopwr2_status_TYPE SES_PAD_CTRL_MOD_TX_DIS_LOPWR2_STATUS_TYPE_T; 3675 3676 typedef union { 3677 uint32_t data; 3678 struct { 3679 #if IS_BIG_ENDIAN 3680 uint32_t reserved : 16; 3681 uint32_t mod_rx_los_abs2_dglh_cnt : 4; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[15:12] - WO */ 3682 uint32_t mod_rx_los_abs2_out_frcval : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[11] - WO */ 3683 uint32_t mod_rx_los_abs2_invert_en : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[10] - WO */ 3684 uint32_t mod_rx_los_abs2_ibof : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[09] - WO */ 3685 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[08] - RSVD */ 3686 uint32_t mod_rx_los_abs2_sel2 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[07] - WO */ 3687 uint32_t mod_rx_los_abs2_sel1 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[06] - WO */ 3688 uint32_t mod_rx_los_abs2_sel0 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[05] - WO */ 3689 uint32_t mod_rx_los_abs2_ind : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[04] - WO */ 3690 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[03] - RSVD */ 3691 uint32_t mod_rx_los_abs2_pdn : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[02] - WO */ 3692 uint32_t mod_rx_los_abs2_pup : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[01] - WO */ 3693 uint32_t mod_rx_los_abs2_oeb : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[00] - WO */ 3694 #endif /* IS_BIG_ENDIAN */ 3695 #if IS_LITTLE_ENDIAN 3696 uint32_t mod_rx_los_abs2_oeb : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[00] - WO */ 3697 uint32_t mod_rx_los_abs2_pup : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[01] - WO */ 3698 uint32_t mod_rx_los_abs2_pdn : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[02] - WO */ 3699 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[03] - RSVD */ 3700 uint32_t mod_rx_los_abs2_ind : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[04] - WO */ 3701 uint32_t mod_rx_los_abs2_sel0 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[05] - WO */ 3702 uint32_t mod_rx_los_abs2_sel1 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[06] - WO */ 3703 uint32_t mod_rx_los_abs2_sel2 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[07] - WO */ 3704 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[08] - RSVD */ 3705 uint32_t mod_rx_los_abs2_ibof : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[09] - WO */ 3706 uint32_t mod_rx_los_abs2_invert_en : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[10] - WO */ 3707 uint32_t mod_rx_los_abs2_out_frcval : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[11] - WO */ 3708 uint32_t mod_rx_los_abs2_dglh_cnt : 4; /* SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE[15:12] - WO */ 3709 uint32_t reserved : 16; 3710 #endif /* IS_LITTLE_ENDIAN */ 3711 } fields; 3712 } SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE; 3713 3714 typedef SES_PAD_CTRL_mod_rx_los_abs2_control_TYPE SES_PAD_CTRL_MOD_RX_LOS_ABS2_CONTROL_TYPE_T; 3715 3716 typedef union { 3717 uint32_t data; 3718 struct { 3719 #if IS_BIG_ENDIAN 3720 uint32_t reserved : 16; 3721 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[15:03] - RSVD */ 3722 uint32_t mod_rx_los_abs2_din : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[02] - RO */ 3723 uint32_t mod_rx_los_abs2_din_ll : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[01] - RO */ 3724 uint32_t mod_rx_los_abs2_din_lh : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[00] - RO */ 3725 #endif /* IS_BIG_ENDIAN */ 3726 #if IS_LITTLE_ENDIAN 3727 uint32_t mod_rx_los_abs2_din_lh : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[00] - RO */ 3728 uint32_t mod_rx_los_abs2_din_ll : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[01] - RO */ 3729 uint32_t mod_rx_los_abs2_din : 1; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[02] - RO */ 3730 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE[15:03] - RSVD */ 3731 uint32_t reserved : 16; 3732 #endif /* IS_LITTLE_ENDIAN */ 3733 } fields; 3734 } SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE; 3735 3736 typedef SES_PAD_CTRL_mod_rx_los_abs2_status_TYPE SES_PAD_CTRL_MOD_RX_LOS_ABS2_STATUS_TYPE_T; 3737 3738 typedef union { 3739 uint32_t data; 3740 struct { 3741 #if IS_BIG_ENDIAN 3742 uint32_t reserved : 16; 3743 uint32_t gpio_0_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_0_control_TYPE[15:12] - WO */ 3744 uint32_t gpio_0_out_frcval : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[11] - WO */ 3745 uint32_t gpio_0_invert_en : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[10] - WO */ 3746 uint32_t gpio_0_ibof : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[09] - WO */ 3747 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[08] - RSVD */ 3748 uint32_t gpio_0_sel2 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[07] - WO */ 3749 uint32_t gpio_0_sel1 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[06] - WO */ 3750 uint32_t gpio_0_sel0 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[05] - WO */ 3751 uint32_t gpio_0_ind : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[04] - WO */ 3752 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[03] - RSVD */ 3753 uint32_t gpio_0_pdn : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[02] - WO */ 3754 uint32_t gpio_0_pup : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[01] - WO */ 3755 uint32_t gpio_0_oeb : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[00] - WO */ 3756 #endif /* IS_BIG_ENDIAN */ 3757 #if IS_LITTLE_ENDIAN 3758 uint32_t gpio_0_oeb : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[00] - WO */ 3759 uint32_t gpio_0_pup : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[01] - WO */ 3760 uint32_t gpio_0_pdn : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[02] - WO */ 3761 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[03] - RSVD */ 3762 uint32_t gpio_0_ind : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[04] - WO */ 3763 uint32_t gpio_0_sel0 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[05] - WO */ 3764 uint32_t gpio_0_sel1 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[06] - WO */ 3765 uint32_t gpio_0_sel2 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[07] - WO */ 3766 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[08] - RSVD */ 3767 uint32_t gpio_0_ibof : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[09] - WO */ 3768 uint32_t gpio_0_invert_en : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[10] - WO */ 3769 uint32_t gpio_0_out_frcval : 1; /* SES_PAD_CTRL_gpio_0_control_TYPE[11] - WO */ 3770 uint32_t gpio_0_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_0_control_TYPE[15:12] - WO */ 3771 uint32_t reserved : 16; 3772 #endif /* IS_LITTLE_ENDIAN */ 3773 } fields; 3774 } SES_PAD_CTRL_gpio_0_control_TYPE; 3775 3776 typedef SES_PAD_CTRL_gpio_0_control_TYPE SES_PAD_CTRL_GPIO_0_CONTROL_TYPE_T; 3777 3778 typedef union { 3779 uint32_t data; 3780 struct { 3781 #if IS_BIG_ENDIAN 3782 uint32_t reserved : 16; 3783 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_0_status_TYPE[15:03] - RSVD */ 3784 uint32_t gpio_0_din : 1; /* SES_PAD_CTRL_gpio_0_status_TYPE[02] - RO */ 3785 uint32_t gpio_0_din_ll : 1; /* SES_PAD_CTRL_gpio_0_status_TYPE[01] - RO */ 3786 uint32_t gpio_0_din_lh : 1; /* SES_PAD_CTRL_gpio_0_status_TYPE[00] - RO */ 3787 #endif /* IS_BIG_ENDIAN */ 3788 #if IS_LITTLE_ENDIAN 3789 uint32_t gpio_0_din_lh : 1; /* SES_PAD_CTRL_gpio_0_status_TYPE[00] - RO */ 3790 uint32_t gpio_0_din_ll : 1; /* SES_PAD_CTRL_gpio_0_status_TYPE[01] - RO */ 3791 uint32_t gpio_0_din : 1; /* SES_PAD_CTRL_gpio_0_status_TYPE[02] - RO */ 3792 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_0_status_TYPE[15:03] - RSVD */ 3793 uint32_t reserved : 16; 3794 #endif /* IS_LITTLE_ENDIAN */ 3795 } fields; 3796 } SES_PAD_CTRL_gpio_0_status_TYPE; 3797 3798 typedef SES_PAD_CTRL_gpio_0_status_TYPE SES_PAD_CTRL_GPIO_0_STATUS_TYPE_T; 3799 3800 typedef union { 3801 uint32_t data; 3802 struct { 3803 #if IS_BIG_ENDIAN 3804 uint32_t reserved : 16; 3805 uint32_t gpio_1_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_1_control_TYPE[15:12] - WO */ 3806 uint32_t gpio_1_out_frcval : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[11] - WO */ 3807 uint32_t gpio_1_invert_en : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[10] - WO */ 3808 uint32_t gpio_1_ibof : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[09] - WO */ 3809 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[08] - RSVD */ 3810 uint32_t gpio_1_sel2 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[07] - WO */ 3811 uint32_t gpio_1_sel1 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[06] - WO */ 3812 uint32_t gpio_1_sel0 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[05] - WO */ 3813 uint32_t gpio_1_ind : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[04] - WO */ 3814 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[03] - RSVD */ 3815 uint32_t gpio_1_pdn : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[02] - WO */ 3816 uint32_t gpio_1_pup : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[01] - WO */ 3817 uint32_t gpio_1_oeb : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[00] - WO */ 3818 #endif /* IS_BIG_ENDIAN */ 3819 #if IS_LITTLE_ENDIAN 3820 uint32_t gpio_1_oeb : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[00] - WO */ 3821 uint32_t gpio_1_pup : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[01] - WO */ 3822 uint32_t gpio_1_pdn : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[02] - WO */ 3823 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[03] - RSVD */ 3824 uint32_t gpio_1_ind : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[04] - WO */ 3825 uint32_t gpio_1_sel0 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[05] - WO */ 3826 uint32_t gpio_1_sel1 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[06] - WO */ 3827 uint32_t gpio_1_sel2 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[07] - WO */ 3828 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[08] - RSVD */ 3829 uint32_t gpio_1_ibof : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[09] - WO */ 3830 uint32_t gpio_1_invert_en : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[10] - WO */ 3831 uint32_t gpio_1_out_frcval : 1; /* SES_PAD_CTRL_gpio_1_control_TYPE[11] - WO */ 3832 uint32_t gpio_1_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_1_control_TYPE[15:12] - WO */ 3833 uint32_t reserved : 16; 3834 #endif /* IS_LITTLE_ENDIAN */ 3835 } fields; 3836 } SES_PAD_CTRL_gpio_1_control_TYPE; 3837 3838 typedef SES_PAD_CTRL_gpio_1_control_TYPE SES_PAD_CTRL_GPIO_1_CONTROL_TYPE_T; 3839 3840 typedef union { 3841 uint32_t data; 3842 struct { 3843 #if IS_BIG_ENDIAN 3844 uint32_t reserved : 16; 3845 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_1_status_TYPE[15:03] - RSVD */ 3846 uint32_t gpio_1_din : 1; /* SES_PAD_CTRL_gpio_1_status_TYPE[02] - RO */ 3847 uint32_t gpio_1_din_ll : 1; /* SES_PAD_CTRL_gpio_1_status_TYPE[01] - RO */ 3848 uint32_t gpio_1_din_lh : 1; /* SES_PAD_CTRL_gpio_1_status_TYPE[00] - RO */ 3849 #endif /* IS_BIG_ENDIAN */ 3850 #if IS_LITTLE_ENDIAN 3851 uint32_t gpio_1_din_lh : 1; /* SES_PAD_CTRL_gpio_1_status_TYPE[00] - RO */ 3852 uint32_t gpio_1_din_ll : 1; /* SES_PAD_CTRL_gpio_1_status_TYPE[01] - RO */ 3853 uint32_t gpio_1_din : 1; /* SES_PAD_CTRL_gpio_1_status_TYPE[02] - RO */ 3854 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_1_status_TYPE[15:03] - RSVD */ 3855 uint32_t reserved : 16; 3856 #endif /* IS_LITTLE_ENDIAN */ 3857 } fields; 3858 } SES_PAD_CTRL_gpio_1_status_TYPE; 3859 3860 typedef SES_PAD_CTRL_gpio_1_status_TYPE SES_PAD_CTRL_GPIO_1_STATUS_TYPE_T; 3861 3862 typedef union { 3863 uint32_t data; 3864 struct { 3865 #if IS_BIG_ENDIAN 3866 uint32_t reserved : 16; 3867 uint32_t gpio_2_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_2_control_TYPE[15:12] - WO */ 3868 uint32_t gpio_2_out_frcval : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[11] - WO */ 3869 uint32_t gpio_2_invert_en : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[10] - WO */ 3870 uint32_t gpio_2_ibof : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[09] - WO */ 3871 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[08] - RSVD */ 3872 uint32_t gpio_2_sel2 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[07] - WO */ 3873 uint32_t gpio_2_sel1 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[06] - WO */ 3874 uint32_t gpio_2_sel0 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[05] - WO */ 3875 uint32_t gpio_2_ind : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[04] - WO */ 3876 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[03] - RSVD */ 3877 uint32_t gpio_2_pdn : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[02] - WO */ 3878 uint32_t gpio_2_pup : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[01] - WO */ 3879 uint32_t gpio_2_oeb : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[00] - WO */ 3880 #endif /* IS_BIG_ENDIAN */ 3881 #if IS_LITTLE_ENDIAN 3882 uint32_t gpio_2_oeb : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[00] - WO */ 3883 uint32_t gpio_2_pup : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[01] - WO */ 3884 uint32_t gpio_2_pdn : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[02] - WO */ 3885 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[03] - RSVD */ 3886 uint32_t gpio_2_ind : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[04] - WO */ 3887 uint32_t gpio_2_sel0 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[05] - WO */ 3888 uint32_t gpio_2_sel1 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[06] - WO */ 3889 uint32_t gpio_2_sel2 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[07] - WO */ 3890 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[08] - RSVD */ 3891 uint32_t gpio_2_ibof : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[09] - WO */ 3892 uint32_t gpio_2_invert_en : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[10] - WO */ 3893 uint32_t gpio_2_out_frcval : 1; /* SES_PAD_CTRL_gpio_2_control_TYPE[11] - WO */ 3894 uint32_t gpio_2_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_2_control_TYPE[15:12] - WO */ 3895 uint32_t reserved : 16; 3896 #endif /* IS_LITTLE_ENDIAN */ 3897 } fields; 3898 } SES_PAD_CTRL_gpio_2_control_TYPE; 3899 3900 typedef SES_PAD_CTRL_gpio_2_control_TYPE SES_PAD_CTRL_GPIO_2_CONTROL_TYPE_T; 3901 3902 typedef union { 3903 uint32_t data; 3904 struct { 3905 #if IS_BIG_ENDIAN 3906 uint32_t reserved : 16; 3907 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_2_status_TYPE[15:03] - RSVD */ 3908 uint32_t gpio_2_din : 1; /* SES_PAD_CTRL_gpio_2_status_TYPE[02] - RO */ 3909 uint32_t gpio_2_din_ll : 1; /* SES_PAD_CTRL_gpio_2_status_TYPE[01] - RO */ 3910 uint32_t gpio_2_din_lh : 1; /* SES_PAD_CTRL_gpio_2_status_TYPE[00] - RO */ 3911 #endif /* IS_BIG_ENDIAN */ 3912 #if IS_LITTLE_ENDIAN 3913 uint32_t gpio_2_din_lh : 1; /* SES_PAD_CTRL_gpio_2_status_TYPE[00] - RO */ 3914 uint32_t gpio_2_din_ll : 1; /* SES_PAD_CTRL_gpio_2_status_TYPE[01] - RO */ 3915 uint32_t gpio_2_din : 1; /* SES_PAD_CTRL_gpio_2_status_TYPE[02] - RO */ 3916 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_2_status_TYPE[15:03] - RSVD */ 3917 uint32_t reserved : 16; 3918 #endif /* IS_LITTLE_ENDIAN */ 3919 } fields; 3920 } SES_PAD_CTRL_gpio_2_status_TYPE; 3921 3922 typedef SES_PAD_CTRL_gpio_2_status_TYPE SES_PAD_CTRL_GPIO_2_STATUS_TYPE_T; 3923 3924 typedef union { 3925 uint32_t data; 3926 struct { 3927 #if IS_BIG_ENDIAN 3928 uint32_t reserved : 16; 3929 uint32_t gpio_3_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_3_control_TYPE[15:12] - WO */ 3930 uint32_t gpio_3_out_frcval : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[11] - WO */ 3931 uint32_t gpio_3_invert_en : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[10] - WO */ 3932 uint32_t gpio_3_ibof : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[09] - WO */ 3933 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[08] - RSVD */ 3934 uint32_t gpio_3_sel2 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[07] - WO */ 3935 uint32_t gpio_3_sel1 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[06] - WO */ 3936 uint32_t gpio_3_sel0 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[05] - WO */ 3937 uint32_t gpio_3_ind : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[04] - WO */ 3938 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[03] - RSVD */ 3939 uint32_t gpio_3_pdn : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[02] - WO */ 3940 uint32_t gpio_3_pup : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[01] - WO */ 3941 uint32_t gpio_3_oeb : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[00] - WO */ 3942 #endif /* IS_BIG_ENDIAN */ 3943 #if IS_LITTLE_ENDIAN 3944 uint32_t gpio_3_oeb : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[00] - WO */ 3945 uint32_t gpio_3_pup : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[01] - WO */ 3946 uint32_t gpio_3_pdn : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[02] - WO */ 3947 uint32_t reserved_03 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[03] - RSVD */ 3948 uint32_t gpio_3_ind : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[04] - WO */ 3949 uint32_t gpio_3_sel0 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[05] - WO */ 3950 uint32_t gpio_3_sel1 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[06] - WO */ 3951 uint32_t gpio_3_sel2 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[07] - WO */ 3952 uint32_t reserved_08 : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[08] - RSVD */ 3953 uint32_t gpio_3_ibof : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[09] - WO */ 3954 uint32_t gpio_3_invert_en : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[10] - WO */ 3955 uint32_t gpio_3_out_frcval : 1; /* SES_PAD_CTRL_gpio_3_control_TYPE[11] - WO */ 3956 uint32_t gpio_3_dglh_cnt : 4; /* SES_PAD_CTRL_gpio_3_control_TYPE[15:12] - WO */ 3957 uint32_t reserved : 16; 3958 #endif /* IS_LITTLE_ENDIAN */ 3959 } fields; 3960 } SES_PAD_CTRL_gpio_3_control_TYPE; 3961 3962 typedef SES_PAD_CTRL_gpio_3_control_TYPE SES_PAD_CTRL_GPIO_3_CONTROL_TYPE_T; 3963 3964 typedef union { 3965 uint32_t data; 3966 struct { 3967 #if IS_BIG_ENDIAN 3968 uint32_t reserved : 16; 3969 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_3_status_TYPE[15:03] - RSVD */ 3970 uint32_t gpio_3_din : 1; /* SES_PAD_CTRL_gpio_3_status_TYPE[02] - RO */ 3971 uint32_t gpio_3_din_ll : 1; /* SES_PAD_CTRL_gpio_3_status_TYPE[01] - RO */ 3972 uint32_t gpio_3_din_lh : 1; /* SES_PAD_CTRL_gpio_3_status_TYPE[00] - RO */ 3973 #endif /* IS_BIG_ENDIAN */ 3974 #if IS_LITTLE_ENDIAN 3975 uint32_t gpio_3_din_lh : 1; /* SES_PAD_CTRL_gpio_3_status_TYPE[00] - RO */ 3976 uint32_t gpio_3_din_ll : 1; /* SES_PAD_CTRL_gpio_3_status_TYPE[01] - RO */ 3977 uint32_t gpio_3_din : 1; /* SES_PAD_CTRL_gpio_3_status_TYPE[02] - RO */ 3978 uint32_t reserved_03 : 13; /* SES_PAD_CTRL_gpio_3_status_TYPE[15:03] - RSVD */ 3979 uint32_t reserved : 16; 3980 #endif /* IS_LITTLE_ENDIAN */ 3981 } fields; 3982 } SES_PAD_CTRL_gpio_3_status_TYPE; 3983 3984 typedef SES_PAD_CTRL_gpio_3_status_TYPE SES_PAD_CTRL_GPIO_3_STATUS_TYPE_T; 3985 3986 3987 /*-----------------------------------------------*/ 3988 /* Structs for CL91_USER_RX Bank */ 3989 /*-----------------------------------------------*/ 3990 typedef union { 3991 uint32_t data; 3992 struct { 3993 #if IS_BIG_ENDIAN 3994 uint32_t reserved : 16; 3995 uint32_t reserved_05 : 11; /* CL91_USER_RX_status_TYPE[15:05] - RSVD */ 3996 uint32_t align_status : 1; /* CL91_USER_RX_status_TYPE[04] - RO */ 3997 uint32_t amp_lock_ln : 4; /* CL91_USER_RX_status_TYPE[03:00] - RO */ 3998 #endif /* IS_BIG_ENDIAN */ 3999 #if IS_LITTLE_ENDIAN 4000 uint32_t amp_lock_ln : 4; /* CL91_USER_RX_status_TYPE[03:00] - RO */ 4001 uint32_t align_status : 1; /* CL91_USER_RX_status_TYPE[04] - RO */ 4002 uint32_t reserved_05 : 11; /* CL91_USER_RX_status_TYPE[15:05] - RSVD */ 4003 uint32_t reserved : 16; 4004 #endif /* IS_LITTLE_ENDIAN */ 4005 } fields; 4006 } CL91_USER_RX_status_TYPE; 4007 4008 typedef CL91_USER_RX_status_TYPE CL91_USER_RX_STATUS_TYPE_T; 4009 4010 typedef union { 4011 uint32_t data; 4012 struct { 4013 #if IS_BIG_ENDIAN 4014 uint32_t reserved : 16; 4015 uint32_t reserved_10 : 6; /* CL91_USER_RX_latched_status_TYPE[15:10] - RSVD */ 4016 uint32_t align_status_ll : 1; /* CL91_USER_RX_latched_status_TYPE[09] - RO */ 4017 uint32_t align_status_lh : 1; /* CL91_USER_RX_latched_status_TYPE[08] - RO */ 4018 uint32_t amp_lock_ln3_ll : 1; /* CL91_USER_RX_latched_status_TYPE[07] - RO */ 4019 uint32_t amp_lock_ln3_lh : 1; /* CL91_USER_RX_latched_status_TYPE[06] - RO */ 4020 uint32_t amp_lock_ln2_ll : 1; /* CL91_USER_RX_latched_status_TYPE[05] - RO */ 4021 uint32_t amp_lock_ln2_lh : 1; /* CL91_USER_RX_latched_status_TYPE[04] - RO */ 4022 uint32_t amp_lock_ln1_ll : 1; /* CL91_USER_RX_latched_status_TYPE[03] - RO */ 4023 uint32_t amp_lock_ln1_lh : 1; /* CL91_USER_RX_latched_status_TYPE[02] - RO */ 4024 uint32_t amp_lock_ln0_ll : 1; /* CL91_USER_RX_latched_status_TYPE[01] - RO */ 4025 uint32_t amp_lock_ln0_lh : 1; /* CL91_USER_RX_latched_status_TYPE[00] - RO */ 4026 #endif /* IS_BIG_ENDIAN */ 4027 #if IS_LITTLE_ENDIAN 4028 uint32_t amp_lock_ln0_lh : 1; /* CL91_USER_RX_latched_status_TYPE[00] - RO */ 4029 uint32_t amp_lock_ln0_ll : 1; /* CL91_USER_RX_latched_status_TYPE[01] - RO */ 4030 uint32_t amp_lock_ln1_lh : 1; /* CL91_USER_RX_latched_status_TYPE[02] - RO */ 4031 uint32_t amp_lock_ln1_ll : 1; /* CL91_USER_RX_latched_status_TYPE[03] - RO */ 4032 uint32_t amp_lock_ln2_lh : 1; /* CL91_USER_RX_latched_status_TYPE[04] - RO */ 4033 uint32_t amp_lock_ln2_ll : 1; /* CL91_USER_RX_latched_status_TYPE[05] - RO */ 4034 uint32_t amp_lock_ln3_lh : 1; /* CL91_USER_RX_latched_status_TYPE[06] - RO */ 4035 uint32_t amp_lock_ln3_ll : 1; /* CL91_USER_RX_latched_status_TYPE[07] - RO */ 4036 uint32_t align_status_lh : 1; /* CL91_USER_RX_latched_status_TYPE[08] - RO */ 4037 uint32_t align_status_ll : 1; /* CL91_USER_RX_latched_status_TYPE[09] - RO */ 4038 uint32_t reserved_10 : 6; /* CL91_USER_RX_latched_status_TYPE[15:10] - RSVD */ 4039 uint32_t reserved : 16; 4040 #endif /* IS_LITTLE_ENDIAN */ 4041 } fields; 4042 } CL91_USER_RX_latched_status_TYPE; 4043 4044 typedef CL91_USER_RX_latched_status_TYPE CL91_USER_RX_LATCHED_STATUS_TYPE_T; 4045 4046 typedef union { 4047 uint32_t data; 4048 struct { 4049 #if IS_BIG_ENDIAN 4050 uint32_t reserved : 16; 4051 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[15:13] - RSVD */ 4052 uint32_t phy_ln0_log_ln1 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[12:08] - WO */ 4053 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[07:05] - RSVD */ 4054 uint32_t phy_ln0_log_ln0 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[04:00] - WO */ 4055 #endif /* IS_BIG_ENDIAN */ 4056 #if IS_LITTLE_ENDIAN 4057 uint32_t phy_ln0_log_ln0 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[04:00] - WO */ 4058 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[07:05] - RSVD */ 4059 uint32_t phy_ln0_log_ln1 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[12:08] - WO */ 4060 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE[15:13] - RSVD */ 4061 uint32_t reserved : 16; 4062 #endif /* IS_LITTLE_ENDIAN */ 4063 } fields; 4064 } CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE; 4065 4066 typedef CL91_USER_RX_phy_ln0_mapping_ctrl1_TYPE CL91_USER_RX_PHY_LN0_MAPPING_CTRL1_TYPE_T; 4067 4068 typedef union { 4069 uint32_t data; 4070 struct { 4071 #if IS_BIG_ENDIAN 4072 uint32_t reserved : 16; 4073 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[15:13] - RSVD */ 4074 uint32_t phy_ln0_log_ln3 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[12:08] - WO */ 4075 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[07:05] - RSVD */ 4076 uint32_t phy_ln0_log_ln2 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[04:00] - WO */ 4077 #endif /* IS_BIG_ENDIAN */ 4078 #if IS_LITTLE_ENDIAN 4079 uint32_t phy_ln0_log_ln2 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[04:00] - WO */ 4080 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[07:05] - RSVD */ 4081 uint32_t phy_ln0_log_ln3 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[12:08] - WO */ 4082 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE[15:13] - RSVD */ 4083 uint32_t reserved : 16; 4084 #endif /* IS_LITTLE_ENDIAN */ 4085 } fields; 4086 } CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE; 4087 4088 typedef CL91_USER_RX_phy_ln0_mapping_ctrl2_TYPE CL91_USER_RX_PHY_LN0_MAPPING_CTRL2_TYPE_T; 4089 4090 typedef union { 4091 uint32_t data; 4092 struct { 4093 #if IS_BIG_ENDIAN 4094 uint32_t reserved : 16; 4095 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_TYPE[15:05] - RSVD */ 4096 uint32_t phy_ln0_log_ln4 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_TYPE[04:00] - WO */ 4097 #endif /* IS_BIG_ENDIAN */ 4098 #if IS_LITTLE_ENDIAN 4099 uint32_t phy_ln0_log_ln4 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_TYPE[04:00] - WO */ 4100 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_TYPE[15:05] - RSVD */ 4101 uint32_t reserved : 16; 4102 #endif /* IS_LITTLE_ENDIAN */ 4103 } fields; 4104 } CL91_USER_RX_phy_ln0_mapping_ctrl3_TYPE; 4105 4106 typedef CL91_USER_RX_phy_ln0_mapping_ctrl3_TYPE CL91_USER_RX_PHY_LN0_MAPPING_CTRL3_TYPE_T; 4107 4108 typedef union { 4109 uint32_t data; 4110 struct { 4111 #if IS_BIG_ENDIAN 4112 uint32_t reserved : 16; 4113 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[15:13] - RSVD */ 4114 uint32_t phy_ln1_log_ln1 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[12:08] - WO */ 4115 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[07:05] - RSVD */ 4116 uint32_t phy_ln1_log_ln0 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[04:00] - WO */ 4117 #endif /* IS_BIG_ENDIAN */ 4118 #if IS_LITTLE_ENDIAN 4119 uint32_t phy_ln1_log_ln0 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[04:00] - WO */ 4120 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[07:05] - RSVD */ 4121 uint32_t phy_ln1_log_ln1 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[12:08] - WO */ 4122 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE[15:13] - RSVD */ 4123 uint32_t reserved : 16; 4124 #endif /* IS_LITTLE_ENDIAN */ 4125 } fields; 4126 } CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE; 4127 4128 typedef CL91_USER_RX_phy_ln1_mapping_ctrl1_TYPE CL91_USER_RX_PHY_LN1_MAPPING_CTRL1_TYPE_T; 4129 4130 typedef union { 4131 uint32_t data; 4132 struct { 4133 #if IS_BIG_ENDIAN 4134 uint32_t reserved : 16; 4135 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[15:13] - RSVD */ 4136 uint32_t phy_ln1_log_ln3 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[12:08] - WO */ 4137 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[07:05] - RSVD */ 4138 uint32_t phy_ln1_log_ln2 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[04:00] - WO */ 4139 #endif /* IS_BIG_ENDIAN */ 4140 #if IS_LITTLE_ENDIAN 4141 uint32_t phy_ln1_log_ln2 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[04:00] - WO */ 4142 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[07:05] - RSVD */ 4143 uint32_t phy_ln1_log_ln3 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[12:08] - WO */ 4144 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE[15:13] - RSVD */ 4145 uint32_t reserved : 16; 4146 #endif /* IS_LITTLE_ENDIAN */ 4147 } fields; 4148 } CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE; 4149 4150 typedef CL91_USER_RX_phy_ln1_mapping_ctrl2_TYPE CL91_USER_RX_PHY_LN1_MAPPING_CTRL2_TYPE_T; 4151 4152 typedef union { 4153 uint32_t data; 4154 struct { 4155 #if IS_BIG_ENDIAN 4156 uint32_t reserved : 16; 4157 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_TYPE[15:05] - RSVD */ 4158 uint32_t phy_ln1_log_ln4 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_TYPE[04:00] - WO */ 4159 #endif /* IS_BIG_ENDIAN */ 4160 #if IS_LITTLE_ENDIAN 4161 uint32_t phy_ln1_log_ln4 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_TYPE[04:00] - WO */ 4162 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_TYPE[15:05] - RSVD */ 4163 uint32_t reserved : 16; 4164 #endif /* IS_LITTLE_ENDIAN */ 4165 } fields; 4166 } CL91_USER_RX_phy_ln1_mapping_ctrl3_TYPE; 4167 4168 typedef CL91_USER_RX_phy_ln1_mapping_ctrl3_TYPE CL91_USER_RX_PHY_LN1_MAPPING_CTRL3_TYPE_T; 4169 4170 typedef union { 4171 uint32_t data; 4172 struct { 4173 #if IS_BIG_ENDIAN 4174 uint32_t reserved : 16; 4175 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[15:13] - RSVD */ 4176 uint32_t phy_ln2_log_ln1 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[12:08] - WO */ 4177 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[07:05] - RSVD */ 4178 uint32_t phy_ln2_log_ln0 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[04:00] - WO */ 4179 #endif /* IS_BIG_ENDIAN */ 4180 #if IS_LITTLE_ENDIAN 4181 uint32_t phy_ln2_log_ln0 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[04:00] - WO */ 4182 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[07:05] - RSVD */ 4183 uint32_t phy_ln2_log_ln1 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[12:08] - WO */ 4184 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE[15:13] - RSVD */ 4185 uint32_t reserved : 16; 4186 #endif /* IS_LITTLE_ENDIAN */ 4187 } fields; 4188 } CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE; 4189 4190 typedef CL91_USER_RX_phy_ln2_mapping_ctrl1_TYPE CL91_USER_RX_PHY_LN2_MAPPING_CTRL1_TYPE_T; 4191 4192 typedef union { 4193 uint32_t data; 4194 struct { 4195 #if IS_BIG_ENDIAN 4196 uint32_t reserved : 16; 4197 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[15:13] - RSVD */ 4198 uint32_t phy_ln2_log_ln3 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[12:08] - WO */ 4199 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[07:05] - RSVD */ 4200 uint32_t phy_ln2_log_ln2 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[04:00] - WO */ 4201 #endif /* IS_BIG_ENDIAN */ 4202 #if IS_LITTLE_ENDIAN 4203 uint32_t phy_ln2_log_ln2 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[04:00] - WO */ 4204 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[07:05] - RSVD */ 4205 uint32_t phy_ln2_log_ln3 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[12:08] - WO */ 4206 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE[15:13] - RSVD */ 4207 uint32_t reserved : 16; 4208 #endif /* IS_LITTLE_ENDIAN */ 4209 } fields; 4210 } CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE; 4211 4212 typedef CL91_USER_RX_phy_ln2_mapping_ctrl2_TYPE CL91_USER_RX_PHY_LN2_MAPPING_CTRL2_TYPE_T; 4213 4214 typedef union { 4215 uint32_t data; 4216 struct { 4217 #if IS_BIG_ENDIAN 4218 uint32_t reserved : 16; 4219 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_TYPE[15:05] - RSVD */ 4220 uint32_t phy_ln2_log_ln4 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_TYPE[04:00] - WO */ 4221 #endif /* IS_BIG_ENDIAN */ 4222 #if IS_LITTLE_ENDIAN 4223 uint32_t phy_ln2_log_ln4 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_TYPE[04:00] - WO */ 4224 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_TYPE[15:05] - RSVD */ 4225 uint32_t reserved : 16; 4226 #endif /* IS_LITTLE_ENDIAN */ 4227 } fields; 4228 } CL91_USER_RX_phy_ln2_mapping_ctrl3_TYPE; 4229 4230 typedef CL91_USER_RX_phy_ln2_mapping_ctrl3_TYPE CL91_USER_RX_PHY_LN2_MAPPING_CTRL3_TYPE_T; 4231 4232 typedef union { 4233 uint32_t data; 4234 struct { 4235 #if IS_BIG_ENDIAN 4236 uint32_t reserved : 16; 4237 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[15:13] - RSVD */ 4238 uint32_t phy_ln3_log_ln1 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[12:08] - WO */ 4239 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[07:05] - RSVD */ 4240 uint32_t phy_ln3_log_ln0 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[04:00] - WO */ 4241 #endif /* IS_BIG_ENDIAN */ 4242 #if IS_LITTLE_ENDIAN 4243 uint32_t phy_ln3_log_ln0 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[04:00] - WO */ 4244 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[07:05] - RSVD */ 4245 uint32_t phy_ln3_log_ln1 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[12:08] - WO */ 4246 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE[15:13] - RSVD */ 4247 uint32_t reserved : 16; 4248 #endif /* IS_LITTLE_ENDIAN */ 4249 } fields; 4250 } CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE; 4251 4252 typedef CL91_USER_RX_phy_ln3_mapping_ctrl1_TYPE CL91_USER_RX_PHY_LN3_MAPPING_CTRL1_TYPE_T; 4253 4254 typedef union { 4255 uint32_t data; 4256 struct { 4257 #if IS_BIG_ENDIAN 4258 uint32_t reserved : 16; 4259 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[15:13] - RSVD */ 4260 uint32_t phy_ln3_log_ln3 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[12:08] - WO */ 4261 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[07:05] - RSVD */ 4262 uint32_t phy_ln3_log_ln2 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[04:00] - WO */ 4263 #endif /* IS_BIG_ENDIAN */ 4264 #if IS_LITTLE_ENDIAN 4265 uint32_t phy_ln3_log_ln2 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[04:00] - WO */ 4266 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[07:05] - RSVD */ 4267 uint32_t phy_ln3_log_ln3 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[12:08] - WO */ 4268 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE[15:13] - RSVD */ 4269 uint32_t reserved : 16; 4270 #endif /* IS_LITTLE_ENDIAN */ 4271 } fields; 4272 } CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE; 4273 4274 typedef CL91_USER_RX_phy_ln3_mapping_ctrl2_TYPE CL91_USER_RX_PHY_LN3_MAPPING_CTRL2_TYPE_T; 4275 4276 typedef union { 4277 uint32_t data; 4278 struct { 4279 #if IS_BIG_ENDIAN 4280 uint32_t reserved : 16; 4281 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_TYPE[15:05] - RSVD */ 4282 uint32_t phy_ln3_log_ln4 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_TYPE[04:00] - WO */ 4283 #endif /* IS_BIG_ENDIAN */ 4284 #if IS_LITTLE_ENDIAN 4285 uint32_t phy_ln3_log_ln4 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_TYPE[04:00] - WO */ 4286 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_TYPE[15:05] - RSVD */ 4287 uint32_t reserved : 16; 4288 #endif /* IS_LITTLE_ENDIAN */ 4289 } fields; 4290 } CL91_USER_RX_phy_ln3_mapping_ctrl3_TYPE; 4291 4292 typedef CL91_USER_RX_phy_ln3_mapping_ctrl3_TYPE CL91_USER_RX_PHY_LN3_MAPPING_CTRL3_TYPE_T; 4293 4294 4295 /*-----------------------------------------------*/ 4296 /* Structs for CL91_USER_TX Bank */ 4297 /*-----------------------------------------------*/ 4298 typedef union { 4299 uint32_t data; 4300 struct { 4301 #if IS_BIG_ENDIAN 4302 uint32_t reserved : 16; 4303 uint32_t reserved_for_eco_05 : 11; /* CL91_USER_TX_status1_TYPE[15:05] - RSVD */ 4304 uint32_t tx_xc_sh_err_lh : 1; /* CL91_USER_TX_status1_TYPE[04] - RO */ 4305 uint32_t all_aligned_lh : 1; /* CL91_USER_TX_status1_TYPE[03] - RO */ 4306 uint32_t all_aligned_ll : 1; /* CL91_USER_TX_status1_TYPE[02] - RO */ 4307 uint32_t all_aligned : 1; /* CL91_USER_TX_status1_TYPE[01] - RO */ 4308 uint32_t nonuniq_pcsl_found_lh : 1; /* CL91_USER_TX_status1_TYPE[00] - RO */ 4309 #endif /* IS_BIG_ENDIAN */ 4310 #if IS_LITTLE_ENDIAN 4311 uint32_t nonuniq_pcsl_found_lh : 1; /* CL91_USER_TX_status1_TYPE[00] - RO */ 4312 uint32_t all_aligned : 1; /* CL91_USER_TX_status1_TYPE[01] - RO */ 4313 uint32_t all_aligned_ll : 1; /* CL91_USER_TX_status1_TYPE[02] - RO */ 4314 uint32_t all_aligned_lh : 1; /* CL91_USER_TX_status1_TYPE[03] - RO */ 4315 uint32_t tx_xc_sh_err_lh : 1; /* CL91_USER_TX_status1_TYPE[04] - RO */ 4316 uint32_t reserved_for_eco_05 : 11; /* CL91_USER_TX_status1_TYPE[15:05] - RSVD */ 4317 uint32_t reserved : 16; 4318 #endif /* IS_LITTLE_ENDIAN */ 4319 } fields; 4320 } CL91_USER_TX_status1_TYPE; 4321 4322 typedef CL91_USER_TX_status1_TYPE CL91_USER_TX_STATUS1_TYPE_T; 4323 4324 typedef union { 4325 uint32_t data; 4326 struct { 4327 #if IS_BIG_ENDIAN 4328 uint32_t reserved : 16; 4329 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status2_TYPE[15:10] - RSVD */ 4330 uint32_t block_lock_9_0 : 10; /* CL91_USER_TX_status2_TYPE[09:00] - RO */ 4331 #endif /* IS_BIG_ENDIAN */ 4332 #if IS_LITTLE_ENDIAN 4333 uint32_t block_lock_9_0 : 10; /* CL91_USER_TX_status2_TYPE[09:00] - RO */ 4334 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status2_TYPE[15:10] - RSVD */ 4335 uint32_t reserved : 16; 4336 #endif /* IS_LITTLE_ENDIAN */ 4337 } fields; 4338 } CL91_USER_TX_status2_TYPE; 4339 4340 typedef CL91_USER_TX_status2_TYPE CL91_USER_TX_STATUS2_TYPE_T; 4341 4342 typedef union { 4343 uint32_t data; 4344 struct { 4345 #if IS_BIG_ENDIAN 4346 uint32_t reserved : 16; 4347 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status3_TYPE[15:10] - RSVD */ 4348 uint32_t block_lock_19_10 : 10; /* CL91_USER_TX_status3_TYPE[09:00] - RO */ 4349 #endif /* IS_BIG_ENDIAN */ 4350 #if IS_LITTLE_ENDIAN 4351 uint32_t block_lock_19_10 : 10; /* CL91_USER_TX_status3_TYPE[09:00] - RO */ 4352 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status3_TYPE[15:10] - RSVD */ 4353 uint32_t reserved : 16; 4354 #endif /* IS_LITTLE_ENDIAN */ 4355 } fields; 4356 } CL91_USER_TX_status3_TYPE; 4357 4358 typedef CL91_USER_TX_status3_TYPE CL91_USER_TX_STATUS3_TYPE_T; 4359 4360 typedef union { 4361 uint32_t data; 4362 struct { 4363 #if IS_BIG_ENDIAN 4364 uint32_t reserved : 16; 4365 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status4_TYPE[15:10] - RSVD */ 4366 uint32_t am_lock_9_0 : 10; /* CL91_USER_TX_status4_TYPE[09:00] - RO */ 4367 #endif /* IS_BIG_ENDIAN */ 4368 #if IS_LITTLE_ENDIAN 4369 uint32_t am_lock_9_0 : 10; /* CL91_USER_TX_status4_TYPE[09:00] - RO */ 4370 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status4_TYPE[15:10] - RSVD */ 4371 uint32_t reserved : 16; 4372 #endif /* IS_LITTLE_ENDIAN */ 4373 } fields; 4374 } CL91_USER_TX_status4_TYPE; 4375 4376 typedef CL91_USER_TX_status4_TYPE CL91_USER_TX_STATUS4_TYPE_T; 4377 4378 typedef union { 4379 uint32_t data; 4380 struct { 4381 #if IS_BIG_ENDIAN 4382 uint32_t reserved : 16; 4383 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status5_TYPE[15:10] - RSVD */ 4384 uint32_t am_lock_19_10 : 10; /* CL91_USER_TX_status5_TYPE[09:00] - RO */ 4385 #endif /* IS_BIG_ENDIAN */ 4386 #if IS_LITTLE_ENDIAN 4387 uint32_t am_lock_19_10 : 10; /* CL91_USER_TX_status5_TYPE[09:00] - RO */ 4388 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status5_TYPE[15:10] - RSVD */ 4389 uint32_t reserved : 16; 4390 #endif /* IS_LITTLE_ENDIAN */ 4391 } fields; 4392 } CL91_USER_TX_status5_TYPE; 4393 4394 typedef CL91_USER_TX_status5_TYPE CL91_USER_TX_STATUS5_TYPE_T; 4395 4396 typedef union { 4397 uint32_t data; 4398 struct { 4399 #if IS_BIG_ENDIAN 4400 uint32_t reserved : 16; 4401 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln0_status_TYPE[15:14] - RSVD */ 4402 uint32_t ln0_block_lock : 1; /* CL91_USER_TX_ln0_status_TYPE[13] - RO */ 4403 uint32_t ln0_block_lock_lh : 1; /* CL91_USER_TX_ln0_status_TYPE[12] - RO */ 4404 uint32_t ln0_block_lock_ll : 1; /* CL91_USER_TX_ln0_status_TYPE[11] - RO */ 4405 uint32_t ln0_am_lock : 1; /* CL91_USER_TX_ln0_status_TYPE[10] - RO */ 4406 uint32_t ln0_am_lock_lh : 1; /* CL91_USER_TX_ln0_status_TYPE[09] - RO */ 4407 uint32_t ln0_am_lock_ll : 1; /* CL91_USER_TX_ln0_status_TYPE[08] - RO */ 4408 uint32_t reserved_05 : 3; /* CL91_USER_TX_ln0_status_TYPE[07:05] - RSVD */ 4409 uint32_t ln0_pcsl_lane_number : 5; /* CL91_USER_TX_ln0_status_TYPE[04:00] - RO */ 4410 #endif /* IS_BIG_ENDIAN */ 4411 #if IS_LITTLE_ENDIAN 4412 uint32_t ln0_pcsl_lane_number : 5; /* CL91_USER_TX_ln0_status_TYPE[04:00] - RO */ 4413 uint32_t reserved_05 : 3; /* CL91_USER_TX_ln0_status_TYPE[07:05] - RSVD */ 4414 uint32_t ln0_am_lock_ll : 1; /* CL91_USER_TX_ln0_status_TYPE[08] - RO */ 4415 uint32_t ln0_am_lock_lh : 1; /* CL91_USER_TX_ln0_status_TYPE[09] - RO */ 4416 uint32_t ln0_am_lock : 1; /* CL91_USER_TX_ln0_status_TYPE[10] - RO */ 4417 uint32_t ln0_block_lock_ll : 1; /* CL91_USER_TX_ln0_status_TYPE[11] - RO */ 4418 uint32_t ln0_block_lock_lh : 1; /* CL91_USER_TX_ln0_status_TYPE[12] - RO */ 4419 uint32_t ln0_block_lock : 1; /* CL91_USER_TX_ln0_status_TYPE[13] - RO */ 4420 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln0_status_TYPE[15:14] - RSVD */ 4421 uint32_t reserved : 16; 4422 #endif /* IS_LITTLE_ENDIAN */ 4423 } fields; 4424 } CL91_USER_TX_ln0_status_TYPE; 4425 4426 typedef CL91_USER_TX_ln0_status_TYPE CL91_USER_TX_LN0_STATUS_TYPE_T; 4427 4428 typedef union { 4429 uint32_t data; 4430 struct { 4431 #if IS_BIG_ENDIAN 4432 uint32_t reserved : 16; 4433 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln1_status_TYPE[15:14] - RSVD */ 4434 uint32_t ln1_block_lock : 1; /* CL91_USER_TX_ln1_status_TYPE[13] - RO */ 4435 uint32_t ln1_block_lock_lh : 1; /* CL91_USER_TX_ln1_status_TYPE[12] - RO */ 4436 uint32_t ln1_block_lock_ll : 1; /* CL91_USER_TX_ln1_status_TYPE[11] - RO */ 4437 uint32_t ln1_am_lock : 1; /* CL91_USER_TX_ln1_status_TYPE[10] - RO */ 4438 uint32_t ln1_am_lock_lh : 1; /* CL91_USER_TX_ln1_status_TYPE[09] - RO */ 4439 uint32_t ln1_am_lock_ll : 1; /* CL91_USER_TX_ln1_status_TYPE[08] - RO */ 4440 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln1_status_TYPE[07:05] - RSVD */ 4441 uint32_t ln1_pcsl_lane_number : 5; /* CL91_USER_TX_ln1_status_TYPE[04:00] - RO */ 4442 #endif /* IS_BIG_ENDIAN */ 4443 #if IS_LITTLE_ENDIAN 4444 uint32_t ln1_pcsl_lane_number : 5; /* CL91_USER_TX_ln1_status_TYPE[04:00] - RO */ 4445 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln1_status_TYPE[07:05] - RSVD */ 4446 uint32_t ln1_am_lock_ll : 1; /* CL91_USER_TX_ln1_status_TYPE[08] - RO */ 4447 uint32_t ln1_am_lock_lh : 1; /* CL91_USER_TX_ln1_status_TYPE[09] - RO */ 4448 uint32_t ln1_am_lock : 1; /* CL91_USER_TX_ln1_status_TYPE[10] - RO */ 4449 uint32_t ln1_block_lock_ll : 1; /* CL91_USER_TX_ln1_status_TYPE[11] - RO */ 4450 uint32_t ln1_block_lock_lh : 1; /* CL91_USER_TX_ln1_status_TYPE[12] - RO */ 4451 uint32_t ln1_block_lock : 1; /* CL91_USER_TX_ln1_status_TYPE[13] - RO */ 4452 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln1_status_TYPE[15:14] - RSVD */ 4453 uint32_t reserved : 16; 4454 #endif /* IS_LITTLE_ENDIAN */ 4455 } fields; 4456 } CL91_USER_TX_ln1_status_TYPE; 4457 4458 typedef CL91_USER_TX_ln1_status_TYPE CL91_USER_TX_LN1_STATUS_TYPE_T; 4459 4460 typedef union { 4461 uint32_t data; 4462 struct { 4463 #if IS_BIG_ENDIAN 4464 uint32_t reserved : 16; 4465 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln2_status_TYPE[15:14] - RSVD */ 4466 uint32_t ln2_block_lock : 1; /* CL91_USER_TX_ln2_status_TYPE[13] - RO */ 4467 uint32_t ln2_block_lock_lh : 1; /* CL91_USER_TX_ln2_status_TYPE[12] - RO */ 4468 uint32_t ln2_block_lock_ll : 1; /* CL91_USER_TX_ln2_status_TYPE[11] - RO */ 4469 uint32_t ln2_am_lock : 1; /* CL91_USER_TX_ln2_status_TYPE[10] - RO */ 4470 uint32_t ln2_am_lock_lh : 1; /* CL91_USER_TX_ln2_status_TYPE[09] - RO */ 4471 uint32_t ln2_am_lock_ll : 1; /* CL91_USER_TX_ln2_status_TYPE[08] - RO */ 4472 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln2_status_TYPE[07:05] - RSVD */ 4473 uint32_t ln2_pcsl_lane_number : 5; /* CL91_USER_TX_ln2_status_TYPE[04:00] - RO */ 4474 #endif /* IS_BIG_ENDIAN */ 4475 #if IS_LITTLE_ENDIAN 4476 uint32_t ln2_pcsl_lane_number : 5; /* CL91_USER_TX_ln2_status_TYPE[04:00] - RO */ 4477 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln2_status_TYPE[07:05] - RSVD */ 4478 uint32_t ln2_am_lock_ll : 1; /* CL91_USER_TX_ln2_status_TYPE[08] - RO */ 4479 uint32_t ln2_am_lock_lh : 1; /* CL91_USER_TX_ln2_status_TYPE[09] - RO */ 4480 uint32_t ln2_am_lock : 1; /* CL91_USER_TX_ln2_status_TYPE[10] - RO */ 4481 uint32_t ln2_block_lock_ll : 1; /* CL91_USER_TX_ln2_status_TYPE[11] - RO */ 4482 uint32_t ln2_block_lock_lh : 1; /* CL91_USER_TX_ln2_status_TYPE[12] - RO */ 4483 uint32_t ln2_block_lock : 1; /* CL91_USER_TX_ln2_status_TYPE[13] - RO */ 4484 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln2_status_TYPE[15:14] - RSVD */ 4485 uint32_t reserved : 16; 4486 #endif /* IS_LITTLE_ENDIAN */ 4487 } fields; 4488 } CL91_USER_TX_ln2_status_TYPE; 4489 4490 typedef CL91_USER_TX_ln2_status_TYPE CL91_USER_TX_LN2_STATUS_TYPE_T; 4491 4492 typedef union { 4493 uint32_t data; 4494 struct { 4495 #if IS_BIG_ENDIAN 4496 uint32_t reserved : 16; 4497 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln3_status_TYPE[15:14] - RSVD */ 4498 uint32_t ln3_block_lock : 1; /* CL91_USER_TX_ln3_status_TYPE[13] - RO */ 4499 uint32_t ln3_block_lock_lh : 1; /* CL91_USER_TX_ln3_status_TYPE[12] - RO */ 4500 uint32_t ln3_block_lock_ll : 1; /* CL91_USER_TX_ln3_status_TYPE[11] - RO */ 4501 uint32_t ln3_am_lock : 1; /* CL91_USER_TX_ln3_status_TYPE[10] - RO */ 4502 uint32_t ln3_am_lock_lh : 1; /* CL91_USER_TX_ln3_status_TYPE[09] - RO */ 4503 uint32_t ln3_am_lock_ll : 1; /* CL91_USER_TX_ln3_status_TYPE[08] - RO */ 4504 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln3_status_TYPE[07:05] - RSVD */ 4505 uint32_t ln3_pcsl_lane_number : 5; /* CL91_USER_TX_ln3_status_TYPE[04:00] - RO */ 4506 #endif /* IS_BIG_ENDIAN */ 4507 #if IS_LITTLE_ENDIAN 4508 uint32_t ln3_pcsl_lane_number : 5; /* CL91_USER_TX_ln3_status_TYPE[04:00] - RO */ 4509 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln3_status_TYPE[07:05] - RSVD */ 4510 uint32_t ln3_am_lock_ll : 1; /* CL91_USER_TX_ln3_status_TYPE[08] - RO */ 4511 uint32_t ln3_am_lock_lh : 1; /* CL91_USER_TX_ln3_status_TYPE[09] - RO */ 4512 uint32_t ln3_am_lock : 1; /* CL91_USER_TX_ln3_status_TYPE[10] - RO */ 4513 uint32_t ln3_block_lock_ll : 1; /* CL91_USER_TX_ln3_status_TYPE[11] - RO */ 4514 uint32_t ln3_block_lock_lh : 1; /* CL91_USER_TX_ln3_status_TYPE[12] - RO */ 4515 uint32_t ln3_block_lock : 1; /* CL91_USER_TX_ln3_status_TYPE[13] - RO */ 4516 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln3_status_TYPE[15:14] - RSVD */ 4517 uint32_t reserved : 16; 4518 #endif /* IS_LITTLE_ENDIAN */ 4519 } fields; 4520 } CL91_USER_TX_ln3_status_TYPE; 4521 4522 typedef CL91_USER_TX_ln3_status_TYPE CL91_USER_TX_LN3_STATUS_TYPE_T; 4523 4524 typedef union { 4525 uint32_t data; 4526 struct { 4527 #if IS_BIG_ENDIAN 4528 uint32_t reserved : 16; 4529 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln4_status_TYPE[15:14] - RSVD */ 4530 uint32_t ln4_block_lock : 1; /* CL91_USER_TX_ln4_status_TYPE[13] - RO */ 4531 uint32_t ln4_block_lock_lh : 1; /* CL91_USER_TX_ln4_status_TYPE[12] - RO */ 4532 uint32_t ln4_block_lock_ll : 1; /* CL91_USER_TX_ln4_status_TYPE[11] - RO */ 4533 uint32_t ln4_am_lock : 1; /* CL91_USER_TX_ln4_status_TYPE[10] - RO */ 4534 uint32_t ln4_am_lock_lh : 1; /* CL91_USER_TX_ln4_status_TYPE[09] - RO */ 4535 uint32_t ln4_am_lock_ll : 1; /* CL91_USER_TX_ln4_status_TYPE[08] - RO */ 4536 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln4_status_TYPE[07:05] - RSVD */ 4537 uint32_t ln4_pcsl_lane_number : 5; /* CL91_USER_TX_ln4_status_TYPE[04:00] - RO */ 4538 #endif /* IS_BIG_ENDIAN */ 4539 #if IS_LITTLE_ENDIAN 4540 uint32_t ln4_pcsl_lane_number : 5; /* CL91_USER_TX_ln4_status_TYPE[04:00] - RO */ 4541 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln4_status_TYPE[07:05] - RSVD */ 4542 uint32_t ln4_am_lock_ll : 1; /* CL91_USER_TX_ln4_status_TYPE[08] - RO */ 4543 uint32_t ln4_am_lock_lh : 1; /* CL91_USER_TX_ln4_status_TYPE[09] - RO */ 4544 uint32_t ln4_am_lock : 1; /* CL91_USER_TX_ln4_status_TYPE[10] - RO */ 4545 uint32_t ln4_block_lock_ll : 1; /* CL91_USER_TX_ln4_status_TYPE[11] - RO */ 4546 uint32_t ln4_block_lock_lh : 1; /* CL91_USER_TX_ln4_status_TYPE[12] - RO */ 4547 uint32_t ln4_block_lock : 1; /* CL91_USER_TX_ln4_status_TYPE[13] - RO */ 4548 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln4_status_TYPE[15:14] - RSVD */ 4549 uint32_t reserved : 16; 4550 #endif /* IS_LITTLE_ENDIAN */ 4551 } fields; 4552 } CL91_USER_TX_ln4_status_TYPE; 4553 4554 typedef CL91_USER_TX_ln4_status_TYPE CL91_USER_TX_LN4_STATUS_TYPE_T; 4555 4556 typedef union { 4557 uint32_t data; 4558 struct { 4559 #if IS_BIG_ENDIAN 4560 uint32_t reserved : 16; 4561 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln5_status_TYPE[15:14] - RSVD */ 4562 uint32_t ln5_block_lock : 1; /* CL91_USER_TX_ln5_status_TYPE[13] - RO */ 4563 uint32_t ln5_block_lock_lh : 1; /* CL91_USER_TX_ln5_status_TYPE[12] - RO */ 4564 uint32_t ln5_block_lock_ll : 1; /* CL91_USER_TX_ln5_status_TYPE[11] - RO */ 4565 uint32_t ln5_am_lock : 1; /* CL91_USER_TX_ln5_status_TYPE[10] - RO */ 4566 uint32_t ln5_am_lock_lh : 1; /* CL91_USER_TX_ln5_status_TYPE[09] - RO */ 4567 uint32_t ln5_am_lock_ll : 1; /* CL91_USER_TX_ln5_status_TYPE[08] - RO */ 4568 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln5_status_TYPE[07:05] - RSVD */ 4569 uint32_t ln5_pcsl_lane_number : 5; /* CL91_USER_TX_ln5_status_TYPE[04:00] - RO */ 4570 #endif /* IS_BIG_ENDIAN */ 4571 #if IS_LITTLE_ENDIAN 4572 uint32_t ln5_pcsl_lane_number : 5; /* CL91_USER_TX_ln5_status_TYPE[04:00] - RO */ 4573 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln5_status_TYPE[07:05] - RSVD */ 4574 uint32_t ln5_am_lock_ll : 1; /* CL91_USER_TX_ln5_status_TYPE[08] - RO */ 4575 uint32_t ln5_am_lock_lh : 1; /* CL91_USER_TX_ln5_status_TYPE[09] - RO */ 4576 uint32_t ln5_am_lock : 1; /* CL91_USER_TX_ln5_status_TYPE[10] - RO */ 4577 uint32_t ln5_block_lock_ll : 1; /* CL91_USER_TX_ln5_status_TYPE[11] - RO */ 4578 uint32_t ln5_block_lock_lh : 1; /* CL91_USER_TX_ln5_status_TYPE[12] - RO */ 4579 uint32_t ln5_block_lock : 1; /* CL91_USER_TX_ln5_status_TYPE[13] - RO */ 4580 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln5_status_TYPE[15:14] - RSVD */ 4581 uint32_t reserved : 16; 4582 #endif /* IS_LITTLE_ENDIAN */ 4583 } fields; 4584 } CL91_USER_TX_ln5_status_TYPE; 4585 4586 typedef CL91_USER_TX_ln5_status_TYPE CL91_USER_TX_LN5_STATUS_TYPE_T; 4587 4588 typedef union { 4589 uint32_t data; 4590 struct { 4591 #if IS_BIG_ENDIAN 4592 uint32_t reserved : 16; 4593 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln6_status_TYPE[15:14] - RSVD */ 4594 uint32_t ln6_block_lock : 1; /* CL91_USER_TX_ln6_status_TYPE[13] - RO */ 4595 uint32_t ln6_block_lock_lh : 1; /* CL91_USER_TX_ln6_status_TYPE[12] - RO */ 4596 uint32_t ln6_block_lock_ll : 1; /* CL91_USER_TX_ln6_status_TYPE[11] - RO */ 4597 uint32_t ln6_am_lock : 1; /* CL91_USER_TX_ln6_status_TYPE[10] - RO */ 4598 uint32_t ln6_am_lock_lh : 1; /* CL91_USER_TX_ln6_status_TYPE[09] - RO */ 4599 uint32_t ln6_am_lock_ll : 1; /* CL91_USER_TX_ln6_status_TYPE[08] - RO */ 4600 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln6_status_TYPE[07:05] - RSVD */ 4601 uint32_t ln6_pcsl_lane_number : 5; /* CL91_USER_TX_ln6_status_TYPE[04:00] - RO */ 4602 #endif /* IS_BIG_ENDIAN */ 4603 #if IS_LITTLE_ENDIAN 4604 uint32_t ln6_pcsl_lane_number : 5; /* CL91_USER_TX_ln6_status_TYPE[04:00] - RO */ 4605 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln6_status_TYPE[07:05] - RSVD */ 4606 uint32_t ln6_am_lock_ll : 1; /* CL91_USER_TX_ln6_status_TYPE[08] - RO */ 4607 uint32_t ln6_am_lock_lh : 1; /* CL91_USER_TX_ln6_status_TYPE[09] - RO */ 4608 uint32_t ln6_am_lock : 1; /* CL91_USER_TX_ln6_status_TYPE[10] - RO */ 4609 uint32_t ln6_block_lock_ll : 1; /* CL91_USER_TX_ln6_status_TYPE[11] - RO */ 4610 uint32_t ln6_block_lock_lh : 1; /* CL91_USER_TX_ln6_status_TYPE[12] - RO */ 4611 uint32_t ln6_block_lock : 1; /* CL91_USER_TX_ln6_status_TYPE[13] - RO */ 4612 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln6_status_TYPE[15:14] - RSVD */ 4613 uint32_t reserved : 16; 4614 #endif /* IS_LITTLE_ENDIAN */ 4615 } fields; 4616 } CL91_USER_TX_ln6_status_TYPE; 4617 4618 typedef CL91_USER_TX_ln6_status_TYPE CL91_USER_TX_LN6_STATUS_TYPE_T; 4619 4620 typedef union { 4621 uint32_t data; 4622 struct { 4623 #if IS_BIG_ENDIAN 4624 uint32_t reserved : 16; 4625 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln7_status_TYPE[15:14] - RSVD */ 4626 uint32_t ln7_block_lock : 1; /* CL91_USER_TX_ln7_status_TYPE[13] - RO */ 4627 uint32_t ln7_block_lock_lh : 1; /* CL91_USER_TX_ln7_status_TYPE[12] - RO */ 4628 uint32_t ln7_block_lock_ll : 1; /* CL91_USER_TX_ln7_status_TYPE[11] - RO */ 4629 uint32_t ln7_am_lock : 1; /* CL91_USER_TX_ln7_status_TYPE[10] - RO */ 4630 uint32_t ln7_am_lock_lh : 1; /* CL91_USER_TX_ln7_status_TYPE[09] - RO */ 4631 uint32_t ln7_am_lock_ll : 1; /* CL91_USER_TX_ln7_status_TYPE[08] - RO */ 4632 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln7_status_TYPE[07:05] - RSVD */ 4633 uint32_t ln7_pcsl_lane_number : 5; /* CL91_USER_TX_ln7_status_TYPE[04:00] - RO */ 4634 #endif /* IS_BIG_ENDIAN */ 4635 #if IS_LITTLE_ENDIAN 4636 uint32_t ln7_pcsl_lane_number : 5; /* CL91_USER_TX_ln7_status_TYPE[04:00] - RO */ 4637 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln7_status_TYPE[07:05] - RSVD */ 4638 uint32_t ln7_am_lock_ll : 1; /* CL91_USER_TX_ln7_status_TYPE[08] - RO */ 4639 uint32_t ln7_am_lock_lh : 1; /* CL91_USER_TX_ln7_status_TYPE[09] - RO */ 4640 uint32_t ln7_am_lock : 1; /* CL91_USER_TX_ln7_status_TYPE[10] - RO */ 4641 uint32_t ln7_block_lock_ll : 1; /* CL91_USER_TX_ln7_status_TYPE[11] - RO */ 4642 uint32_t ln7_block_lock_lh : 1; /* CL91_USER_TX_ln7_status_TYPE[12] - RO */ 4643 uint32_t ln7_block_lock : 1; /* CL91_USER_TX_ln7_status_TYPE[13] - RO */ 4644 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln7_status_TYPE[15:14] - RSVD */ 4645 uint32_t reserved : 16; 4646 #endif /* IS_LITTLE_ENDIAN */ 4647 } fields; 4648 } CL91_USER_TX_ln7_status_TYPE; 4649 4650 typedef CL91_USER_TX_ln7_status_TYPE CL91_USER_TX_LN7_STATUS_TYPE_T; 4651 4652 typedef union { 4653 uint32_t data; 4654 struct { 4655 #if IS_BIG_ENDIAN 4656 uint32_t reserved : 16; 4657 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln8_status_TYPE[15:14] - RSVD */ 4658 uint32_t ln8_block_lock : 1; /* CL91_USER_TX_ln8_status_TYPE[13] - RO */ 4659 uint32_t ln8_block_lock_lh : 1; /* CL91_USER_TX_ln8_status_TYPE[12] - RO */ 4660 uint32_t ln8_block_lock_ll : 1; /* CL91_USER_TX_ln8_status_TYPE[11] - RO */ 4661 uint32_t ln8_am_lock : 1; /* CL91_USER_TX_ln8_status_TYPE[10] - RO */ 4662 uint32_t ln8_am_lock_lh : 1; /* CL91_USER_TX_ln8_status_TYPE[09] - RO */ 4663 uint32_t ln8_am_lock_ll : 1; /* CL91_USER_TX_ln8_status_TYPE[08] - RO */ 4664 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln8_status_TYPE[07:05] - RSVD */ 4665 uint32_t ln8_pcsl_lane_number : 5; /* CL91_USER_TX_ln8_status_TYPE[04:00] - RO */ 4666 #endif /* IS_BIG_ENDIAN */ 4667 #if IS_LITTLE_ENDIAN 4668 uint32_t ln8_pcsl_lane_number : 5; /* CL91_USER_TX_ln8_status_TYPE[04:00] - RO */ 4669 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln8_status_TYPE[07:05] - RSVD */ 4670 uint32_t ln8_am_lock_ll : 1; /* CL91_USER_TX_ln8_status_TYPE[08] - RO */ 4671 uint32_t ln8_am_lock_lh : 1; /* CL91_USER_TX_ln8_status_TYPE[09] - RO */ 4672 uint32_t ln8_am_lock : 1; /* CL91_USER_TX_ln8_status_TYPE[10] - RO */ 4673 uint32_t ln8_block_lock_ll : 1; /* CL91_USER_TX_ln8_status_TYPE[11] - RO */ 4674 uint32_t ln8_block_lock_lh : 1; /* CL91_USER_TX_ln8_status_TYPE[12] - RO */ 4675 uint32_t ln8_block_lock : 1; /* CL91_USER_TX_ln8_status_TYPE[13] - RO */ 4676 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln8_status_TYPE[15:14] - RSVD */ 4677 uint32_t reserved : 16; 4678 #endif /* IS_LITTLE_ENDIAN */ 4679 } fields; 4680 } CL91_USER_TX_ln8_status_TYPE; 4681 4682 typedef CL91_USER_TX_ln8_status_TYPE CL91_USER_TX_LN8_STATUS_TYPE_T; 4683 4684 typedef union { 4685 uint32_t data; 4686 struct { 4687 #if IS_BIG_ENDIAN 4688 uint32_t reserved : 16; 4689 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln9_status_TYPE[15:14] - RSVD */ 4690 uint32_t ln9_block_lock : 1; /* CL91_USER_TX_ln9_status_TYPE[13] - RO */ 4691 uint32_t ln9_block_lock_lh : 1; /* CL91_USER_TX_ln9_status_TYPE[12] - RO */ 4692 uint32_t ln9_block_lock_ll : 1; /* CL91_USER_TX_ln9_status_TYPE[11] - RO */ 4693 uint32_t ln9_am_lock : 1; /* CL91_USER_TX_ln9_status_TYPE[10] - RO */ 4694 uint32_t ln9_am_lock_lh : 1; /* CL91_USER_TX_ln9_status_TYPE[09] - RO */ 4695 uint32_t ln9_am_lock_ll : 1; /* CL91_USER_TX_ln9_status_TYPE[08] - RO */ 4696 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln9_status_TYPE[07:05] - RSVD */ 4697 uint32_t ln9_pcsl_lane_number : 5; /* CL91_USER_TX_ln9_status_TYPE[04:00] - RO */ 4698 #endif /* IS_BIG_ENDIAN */ 4699 #if IS_LITTLE_ENDIAN 4700 uint32_t ln9_pcsl_lane_number : 5; /* CL91_USER_TX_ln9_status_TYPE[04:00] - RO */ 4701 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln9_status_TYPE[07:05] - RSVD */ 4702 uint32_t ln9_am_lock_ll : 1; /* CL91_USER_TX_ln9_status_TYPE[08] - RO */ 4703 uint32_t ln9_am_lock_lh : 1; /* CL91_USER_TX_ln9_status_TYPE[09] - RO */ 4704 uint32_t ln9_am_lock : 1; /* CL91_USER_TX_ln9_status_TYPE[10] - RO */ 4705 uint32_t ln9_block_lock_ll : 1; /* CL91_USER_TX_ln9_status_TYPE[11] - RO */ 4706 uint32_t ln9_block_lock_lh : 1; /* CL91_USER_TX_ln9_status_TYPE[12] - RO */ 4707 uint32_t ln9_block_lock : 1; /* CL91_USER_TX_ln9_status_TYPE[13] - RO */ 4708 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln9_status_TYPE[15:14] - RSVD */ 4709 uint32_t reserved : 16; 4710 #endif /* IS_LITTLE_ENDIAN */ 4711 } fields; 4712 } CL91_USER_TX_ln9_status_TYPE; 4713 4714 typedef CL91_USER_TX_ln9_status_TYPE CL91_USER_TX_LN9_STATUS_TYPE_T; 4715 4716 typedef union { 4717 uint32_t data; 4718 struct { 4719 #if IS_BIG_ENDIAN 4720 uint32_t reserved : 16; 4721 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln10_status_TYPE[15:14] - RSVD */ 4722 uint32_t ln10_block_lock : 1; /* CL91_USER_TX_ln10_status_TYPE[13] - RO */ 4723 uint32_t ln10_block_lock_lh : 1; /* CL91_USER_TX_ln10_status_TYPE[12] - RO */ 4724 uint32_t ln10_block_lock_ll : 1; /* CL91_USER_TX_ln10_status_TYPE[11] - RO */ 4725 uint32_t ln10_am_lock : 1; /* CL91_USER_TX_ln10_status_TYPE[10] - RO */ 4726 uint32_t ln10_am_lock_lh : 1; /* CL91_USER_TX_ln10_status_TYPE[09] - RO */ 4727 uint32_t ln10_am_lock_ll : 1; /* CL91_USER_TX_ln10_status_TYPE[08] - RO */ 4728 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln10_status_TYPE[07:05] - RSVD */ 4729 uint32_t ln10_pcsl_lane_number : 5; /* CL91_USER_TX_ln10_status_TYPE[04:00] - RO */ 4730 #endif /* IS_BIG_ENDIAN */ 4731 #if IS_LITTLE_ENDIAN 4732 uint32_t ln10_pcsl_lane_number : 5; /* CL91_USER_TX_ln10_status_TYPE[04:00] - RO */ 4733 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln10_status_TYPE[07:05] - RSVD */ 4734 uint32_t ln10_am_lock_ll : 1; /* CL91_USER_TX_ln10_status_TYPE[08] - RO */ 4735 uint32_t ln10_am_lock_lh : 1; /* CL91_USER_TX_ln10_status_TYPE[09] - RO */ 4736 uint32_t ln10_am_lock : 1; /* CL91_USER_TX_ln10_status_TYPE[10] - RO */ 4737 uint32_t ln10_block_lock_ll : 1; /* CL91_USER_TX_ln10_status_TYPE[11] - RO */ 4738 uint32_t ln10_block_lock_lh : 1; /* CL91_USER_TX_ln10_status_TYPE[12] - RO */ 4739 uint32_t ln10_block_lock : 1; /* CL91_USER_TX_ln10_status_TYPE[13] - RO */ 4740 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln10_status_TYPE[15:14] - RSVD */ 4741 uint32_t reserved : 16; 4742 #endif /* IS_LITTLE_ENDIAN */ 4743 } fields; 4744 } CL91_USER_TX_ln10_status_TYPE; 4745 4746 typedef CL91_USER_TX_ln10_status_TYPE CL91_USER_TX_LN10_STATUS_TYPE_T; 4747 4748 typedef union { 4749 uint32_t data; 4750 struct { 4751 #if IS_BIG_ENDIAN 4752 uint32_t reserved : 16; 4753 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln11_status_TYPE[15:14] - RSVD */ 4754 uint32_t ln11_block_lock : 1; /* CL91_USER_TX_ln11_status_TYPE[13] - RO */ 4755 uint32_t ln11_block_lock_lh : 1; /* CL91_USER_TX_ln11_status_TYPE[12] - RO */ 4756 uint32_t ln11_block_lock_ll : 1; /* CL91_USER_TX_ln11_status_TYPE[11] - RO */ 4757 uint32_t ln11_am_lock : 1; /* CL91_USER_TX_ln11_status_TYPE[10] - RO */ 4758 uint32_t ln11_am_lock_lh : 1; /* CL91_USER_TX_ln11_status_TYPE[09] - RO */ 4759 uint32_t ln11_am_lock_ll : 1; /* CL91_USER_TX_ln11_status_TYPE[08] - RO */ 4760 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln11_status_TYPE[07:05] - RSVD */ 4761 uint32_t ln11_pcsl_lane_number : 5; /* CL91_USER_TX_ln11_status_TYPE[04:00] - RO */ 4762 #endif /* IS_BIG_ENDIAN */ 4763 #if IS_LITTLE_ENDIAN 4764 uint32_t ln11_pcsl_lane_number : 5; /* CL91_USER_TX_ln11_status_TYPE[04:00] - RO */ 4765 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln11_status_TYPE[07:05] - RSVD */ 4766 uint32_t ln11_am_lock_ll : 1; /* CL91_USER_TX_ln11_status_TYPE[08] - RO */ 4767 uint32_t ln11_am_lock_lh : 1; /* CL91_USER_TX_ln11_status_TYPE[09] - RO */ 4768 uint32_t ln11_am_lock : 1; /* CL91_USER_TX_ln11_status_TYPE[10] - RO */ 4769 uint32_t ln11_block_lock_ll : 1; /* CL91_USER_TX_ln11_status_TYPE[11] - RO */ 4770 uint32_t ln11_block_lock_lh : 1; /* CL91_USER_TX_ln11_status_TYPE[12] - RO */ 4771 uint32_t ln11_block_lock : 1; /* CL91_USER_TX_ln11_status_TYPE[13] - RO */ 4772 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln11_status_TYPE[15:14] - RSVD */ 4773 uint32_t reserved : 16; 4774 #endif /* IS_LITTLE_ENDIAN */ 4775 } fields; 4776 } CL91_USER_TX_ln11_status_TYPE; 4777 4778 typedef CL91_USER_TX_ln11_status_TYPE CL91_USER_TX_LN11_STATUS_TYPE_T; 4779 4780 typedef union { 4781 uint32_t data; 4782 struct { 4783 #if IS_BIG_ENDIAN 4784 uint32_t reserved : 16; 4785 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln12_status_TYPE[15:14] - RSVD */ 4786 uint32_t ln12_block_lock : 1; /* CL91_USER_TX_ln12_status_TYPE[13] - RO */ 4787 uint32_t ln12_block_lock_lh : 1; /* CL91_USER_TX_ln12_status_TYPE[12] - RO */ 4788 uint32_t ln12_block_lock_ll : 1; /* CL91_USER_TX_ln12_status_TYPE[11] - RO */ 4789 uint32_t ln12_am_lock : 1; /* CL91_USER_TX_ln12_status_TYPE[10] - RO */ 4790 uint32_t ln12_am_lock_lh : 1; /* CL91_USER_TX_ln12_status_TYPE[09] - RO */ 4791 uint32_t ln12_am_lock_ll : 1; /* CL91_USER_TX_ln12_status_TYPE[08] - RO */ 4792 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln12_status_TYPE[07:05] - RSVD */ 4793 uint32_t ln12_pcsl_lane_number : 5; /* CL91_USER_TX_ln12_status_TYPE[04:00] - RO */ 4794 #endif /* IS_BIG_ENDIAN */ 4795 #if IS_LITTLE_ENDIAN 4796 uint32_t ln12_pcsl_lane_number : 5; /* CL91_USER_TX_ln12_status_TYPE[04:00] - RO */ 4797 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln12_status_TYPE[07:05] - RSVD */ 4798 uint32_t ln12_am_lock_ll : 1; /* CL91_USER_TX_ln12_status_TYPE[08] - RO */ 4799 uint32_t ln12_am_lock_lh : 1; /* CL91_USER_TX_ln12_status_TYPE[09] - RO */ 4800 uint32_t ln12_am_lock : 1; /* CL91_USER_TX_ln12_status_TYPE[10] - RO */ 4801 uint32_t ln12_block_lock_ll : 1; /* CL91_USER_TX_ln12_status_TYPE[11] - RO */ 4802 uint32_t ln12_block_lock_lh : 1; /* CL91_USER_TX_ln12_status_TYPE[12] - RO */ 4803 uint32_t ln12_block_lock : 1; /* CL91_USER_TX_ln12_status_TYPE[13] - RO */ 4804 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln12_status_TYPE[15:14] - RSVD */ 4805 uint32_t reserved : 16; 4806 #endif /* IS_LITTLE_ENDIAN */ 4807 } fields; 4808 } CL91_USER_TX_ln12_status_TYPE; 4809 4810 typedef CL91_USER_TX_ln12_status_TYPE CL91_USER_TX_LN12_STATUS_TYPE_T; 4811 4812 typedef union { 4813 uint32_t data; 4814 struct { 4815 #if IS_BIG_ENDIAN 4816 uint32_t reserved : 16; 4817 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln13_status_TYPE[15:14] - RSVD */ 4818 uint32_t ln13_block_lock : 1; /* CL91_USER_TX_ln13_status_TYPE[13] - RO */ 4819 uint32_t ln13_block_lock_lh : 1; /* CL91_USER_TX_ln13_status_TYPE[12] - RO */ 4820 uint32_t ln13_block_lock_ll : 1; /* CL91_USER_TX_ln13_status_TYPE[11] - RO */ 4821 uint32_t ln13_am_lock : 1; /* CL91_USER_TX_ln13_status_TYPE[10] - RO */ 4822 uint32_t ln13_am_lock_lh : 1; /* CL91_USER_TX_ln13_status_TYPE[09] - RO */ 4823 uint32_t ln13_am_lock_ll : 1; /* CL91_USER_TX_ln13_status_TYPE[08] - RO */ 4824 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln13_status_TYPE[07:05] - RSVD */ 4825 uint32_t ln13_pcsl_lane_number : 5; /* CL91_USER_TX_ln13_status_TYPE[04:00] - RO */ 4826 #endif /* IS_BIG_ENDIAN */ 4827 #if IS_LITTLE_ENDIAN 4828 uint32_t ln13_pcsl_lane_number : 5; /* CL91_USER_TX_ln13_status_TYPE[04:00] - RO */ 4829 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln13_status_TYPE[07:05] - RSVD */ 4830 uint32_t ln13_am_lock_ll : 1; /* CL91_USER_TX_ln13_status_TYPE[08] - RO */ 4831 uint32_t ln13_am_lock_lh : 1; /* CL91_USER_TX_ln13_status_TYPE[09] - RO */ 4832 uint32_t ln13_am_lock : 1; /* CL91_USER_TX_ln13_status_TYPE[10] - RO */ 4833 uint32_t ln13_block_lock_ll : 1; /* CL91_USER_TX_ln13_status_TYPE[11] - RO */ 4834 uint32_t ln13_block_lock_lh : 1; /* CL91_USER_TX_ln13_status_TYPE[12] - RO */ 4835 uint32_t ln13_block_lock : 1; /* CL91_USER_TX_ln13_status_TYPE[13] - RO */ 4836 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln13_status_TYPE[15:14] - RSVD */ 4837 uint32_t reserved : 16; 4838 #endif /* IS_LITTLE_ENDIAN */ 4839 } fields; 4840 } CL91_USER_TX_ln13_status_TYPE; 4841 4842 typedef CL91_USER_TX_ln13_status_TYPE CL91_USER_TX_LN13_STATUS_TYPE_T; 4843 4844 typedef union { 4845 uint32_t data; 4846 struct { 4847 #if IS_BIG_ENDIAN 4848 uint32_t reserved : 16; 4849 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln14_status_TYPE[15:14] - RSVD */ 4850 uint32_t ln14_block_lock : 1; /* CL91_USER_TX_ln14_status_TYPE[13] - RO */ 4851 uint32_t ln14_block_lock_lh : 1; /* CL91_USER_TX_ln14_status_TYPE[12] - RO */ 4852 uint32_t ln14_block_lock_ll : 1; /* CL91_USER_TX_ln14_status_TYPE[11] - RO */ 4853 uint32_t ln14_am_lock : 1; /* CL91_USER_TX_ln14_status_TYPE[10] - RO */ 4854 uint32_t ln14_am_lock_lh : 1; /* CL91_USER_TX_ln14_status_TYPE[09] - RO */ 4855 uint32_t ln14_am_lock_ll : 1; /* CL91_USER_TX_ln14_status_TYPE[08] - RO */ 4856 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln14_status_TYPE[07:05] - RSVD */ 4857 uint32_t ln14_pcsl_lane_number : 5; /* CL91_USER_TX_ln14_status_TYPE[04:00] - RO */ 4858 #endif /* IS_BIG_ENDIAN */ 4859 #if IS_LITTLE_ENDIAN 4860 uint32_t ln14_pcsl_lane_number : 5; /* CL91_USER_TX_ln14_status_TYPE[04:00] - RO */ 4861 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln14_status_TYPE[07:05] - RSVD */ 4862 uint32_t ln14_am_lock_ll : 1; /* CL91_USER_TX_ln14_status_TYPE[08] - RO */ 4863 uint32_t ln14_am_lock_lh : 1; /* CL91_USER_TX_ln14_status_TYPE[09] - RO */ 4864 uint32_t ln14_am_lock : 1; /* CL91_USER_TX_ln14_status_TYPE[10] - RO */ 4865 uint32_t ln14_block_lock_ll : 1; /* CL91_USER_TX_ln14_status_TYPE[11] - RO */ 4866 uint32_t ln14_block_lock_lh : 1; /* CL91_USER_TX_ln14_status_TYPE[12] - RO */ 4867 uint32_t ln14_block_lock : 1; /* CL91_USER_TX_ln14_status_TYPE[13] - RO */ 4868 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln14_status_TYPE[15:14] - RSVD */ 4869 uint32_t reserved : 16; 4870 #endif /* IS_LITTLE_ENDIAN */ 4871 } fields; 4872 } CL91_USER_TX_ln14_status_TYPE; 4873 4874 typedef CL91_USER_TX_ln14_status_TYPE CL91_USER_TX_LN14_STATUS_TYPE_T; 4875 4876 typedef union { 4877 uint32_t data; 4878 struct { 4879 #if IS_BIG_ENDIAN 4880 uint32_t reserved : 16; 4881 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln15_status_TYPE[15:14] - RSVD */ 4882 uint32_t ln15_block_lock : 1; /* CL91_USER_TX_ln15_status_TYPE[13] - RO */ 4883 uint32_t ln15_block_lock_lh : 1; /* CL91_USER_TX_ln15_status_TYPE[12] - RO */ 4884 uint32_t ln15_block_lock_ll : 1; /* CL91_USER_TX_ln15_status_TYPE[11] - RO */ 4885 uint32_t ln15_am_lock : 1; /* CL91_USER_TX_ln15_status_TYPE[10] - RO */ 4886 uint32_t ln15_am_lock_lh : 1; /* CL91_USER_TX_ln15_status_TYPE[09] - RO */ 4887 uint32_t ln15_am_lock_ll : 1; /* CL91_USER_TX_ln15_status_TYPE[08] - RO */ 4888 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln15_status_TYPE[07:05] - RSVD */ 4889 uint32_t ln15_pcsl_lane_number : 5; /* CL91_USER_TX_ln15_status_TYPE[04:00] - RO */ 4890 #endif /* IS_BIG_ENDIAN */ 4891 #if IS_LITTLE_ENDIAN 4892 uint32_t ln15_pcsl_lane_number : 5; /* CL91_USER_TX_ln15_status_TYPE[04:00] - RO */ 4893 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln15_status_TYPE[07:05] - RSVD */ 4894 uint32_t ln15_am_lock_ll : 1; /* CL91_USER_TX_ln15_status_TYPE[08] - RO */ 4895 uint32_t ln15_am_lock_lh : 1; /* CL91_USER_TX_ln15_status_TYPE[09] - RO */ 4896 uint32_t ln15_am_lock : 1; /* CL91_USER_TX_ln15_status_TYPE[10] - RO */ 4897 uint32_t ln15_block_lock_ll : 1; /* CL91_USER_TX_ln15_status_TYPE[11] - RO */ 4898 uint32_t ln15_block_lock_lh : 1; /* CL91_USER_TX_ln15_status_TYPE[12] - RO */ 4899 uint32_t ln15_block_lock : 1; /* CL91_USER_TX_ln15_status_TYPE[13] - RO */ 4900 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln15_status_TYPE[15:14] - RSVD */ 4901 uint32_t reserved : 16; 4902 #endif /* IS_LITTLE_ENDIAN */ 4903 } fields; 4904 } CL91_USER_TX_ln15_status_TYPE; 4905 4906 typedef CL91_USER_TX_ln15_status_TYPE CL91_USER_TX_LN15_STATUS_TYPE_T; 4907 4908 typedef union { 4909 uint32_t data; 4910 struct { 4911 #if IS_BIG_ENDIAN 4912 uint32_t reserved : 16; 4913 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln16_status_TYPE[15:14] - RSVD */ 4914 uint32_t ln16_block_lock : 1; /* CL91_USER_TX_ln16_status_TYPE[13] - RO */ 4915 uint32_t ln16_block_lock_lh : 1; /* CL91_USER_TX_ln16_status_TYPE[12] - RO */ 4916 uint32_t ln16_block_lock_ll : 1; /* CL91_USER_TX_ln16_status_TYPE[11] - RO */ 4917 uint32_t ln16_am_lock : 1; /* CL91_USER_TX_ln16_status_TYPE[10] - RO */ 4918 uint32_t ln16_am_lock_lh : 1; /* CL91_USER_TX_ln16_status_TYPE[09] - RO */ 4919 uint32_t ln16_am_lock_ll : 1; /* CL91_USER_TX_ln16_status_TYPE[08] - RO */ 4920 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln16_status_TYPE[07:05] - RSVD */ 4921 uint32_t ln16_pcsl_lane_number : 5; /* CL91_USER_TX_ln16_status_TYPE[04:00] - RO */ 4922 #endif /* IS_BIG_ENDIAN */ 4923 #if IS_LITTLE_ENDIAN 4924 uint32_t ln16_pcsl_lane_number : 5; /* CL91_USER_TX_ln16_status_TYPE[04:00] - RO */ 4925 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln16_status_TYPE[07:05] - RSVD */ 4926 uint32_t ln16_am_lock_ll : 1; /* CL91_USER_TX_ln16_status_TYPE[08] - RO */ 4927 uint32_t ln16_am_lock_lh : 1; /* CL91_USER_TX_ln16_status_TYPE[09] - RO */ 4928 uint32_t ln16_am_lock : 1; /* CL91_USER_TX_ln16_status_TYPE[10] - RO */ 4929 uint32_t ln16_block_lock_ll : 1; /* CL91_USER_TX_ln16_status_TYPE[11] - RO */ 4930 uint32_t ln16_block_lock_lh : 1; /* CL91_USER_TX_ln16_status_TYPE[12] - RO */ 4931 uint32_t ln16_block_lock : 1; /* CL91_USER_TX_ln16_status_TYPE[13] - RO */ 4932 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln16_status_TYPE[15:14] - RSVD */ 4933 uint32_t reserved : 16; 4934 #endif /* IS_LITTLE_ENDIAN */ 4935 } fields; 4936 } CL91_USER_TX_ln16_status_TYPE; 4937 4938 typedef CL91_USER_TX_ln16_status_TYPE CL91_USER_TX_LN16_STATUS_TYPE_T; 4939 4940 typedef union { 4941 uint32_t data; 4942 struct { 4943 #if IS_BIG_ENDIAN 4944 uint32_t reserved : 16; 4945 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln17_status_TYPE[15:14] - RSVD */ 4946 uint32_t ln17_block_lock : 1; /* CL91_USER_TX_ln17_status_TYPE[13] - RO */ 4947 uint32_t ln17_block_lock_lh : 1; /* CL91_USER_TX_ln17_status_TYPE[12] - RO */ 4948 uint32_t ln17_block_lock_ll : 1; /* CL91_USER_TX_ln17_status_TYPE[11] - RO */ 4949 uint32_t ln17_am_lock : 1; /* CL91_USER_TX_ln17_status_TYPE[10] - RO */ 4950 uint32_t ln17_am_lock_lh : 1; /* CL91_USER_TX_ln17_status_TYPE[09] - RO */ 4951 uint32_t ln17_am_lock_ll : 1; /* CL91_USER_TX_ln17_status_TYPE[08] - RO */ 4952 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln17_status_TYPE[07:05] - RSVD */ 4953 uint32_t ln17_pcsl_lane_number : 5; /* CL91_USER_TX_ln17_status_TYPE[04:00] - RO */ 4954 #endif /* IS_BIG_ENDIAN */ 4955 #if IS_LITTLE_ENDIAN 4956 uint32_t ln17_pcsl_lane_number : 5; /* CL91_USER_TX_ln17_status_TYPE[04:00] - RO */ 4957 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln17_status_TYPE[07:05] - RSVD */ 4958 uint32_t ln17_am_lock_ll : 1; /* CL91_USER_TX_ln17_status_TYPE[08] - RO */ 4959 uint32_t ln17_am_lock_lh : 1; /* CL91_USER_TX_ln17_status_TYPE[09] - RO */ 4960 uint32_t ln17_am_lock : 1; /* CL91_USER_TX_ln17_status_TYPE[10] - RO */ 4961 uint32_t ln17_block_lock_ll : 1; /* CL91_USER_TX_ln17_status_TYPE[11] - RO */ 4962 uint32_t ln17_block_lock_lh : 1; /* CL91_USER_TX_ln17_status_TYPE[12] - RO */ 4963 uint32_t ln17_block_lock : 1; /* CL91_USER_TX_ln17_status_TYPE[13] - RO */ 4964 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln17_status_TYPE[15:14] - RSVD */ 4965 uint32_t reserved : 16; 4966 #endif /* IS_LITTLE_ENDIAN */ 4967 } fields; 4968 } CL91_USER_TX_ln17_status_TYPE; 4969 4970 typedef CL91_USER_TX_ln17_status_TYPE CL91_USER_TX_LN17_STATUS_TYPE_T; 4971 4972 typedef union { 4973 uint32_t data; 4974 struct { 4975 #if IS_BIG_ENDIAN 4976 uint32_t reserved : 16; 4977 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln18_status_TYPE[15:14] - RSVD */ 4978 uint32_t ln18_block_lock : 1; /* CL91_USER_TX_ln18_status_TYPE[13] - RO */ 4979 uint32_t ln18_block_lock_lh : 1; /* CL91_USER_TX_ln18_status_TYPE[12] - RO */ 4980 uint32_t ln18_block_lock_ll : 1; /* CL91_USER_TX_ln18_status_TYPE[11] - RO */ 4981 uint32_t ln18_am_lock : 1; /* CL91_USER_TX_ln18_status_TYPE[10] - RO */ 4982 uint32_t ln18_am_lock_lh : 1; /* CL91_USER_TX_ln18_status_TYPE[09] - RO */ 4983 uint32_t ln18_am_lock_ll : 1; /* CL91_USER_TX_ln18_status_TYPE[08] - RO */ 4984 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln18_status_TYPE[07:05] - RSVD */ 4985 uint32_t ln18_pcsl_lane_number : 5; /* CL91_USER_TX_ln18_status_TYPE[04:00] - RO */ 4986 #endif /* IS_BIG_ENDIAN */ 4987 #if IS_LITTLE_ENDIAN 4988 uint32_t ln18_pcsl_lane_number : 5; /* CL91_USER_TX_ln18_status_TYPE[04:00] - RO */ 4989 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln18_status_TYPE[07:05] - RSVD */ 4990 uint32_t ln18_am_lock_ll : 1; /* CL91_USER_TX_ln18_status_TYPE[08] - RO */ 4991 uint32_t ln18_am_lock_lh : 1; /* CL91_USER_TX_ln18_status_TYPE[09] - RO */ 4992 uint32_t ln18_am_lock : 1; /* CL91_USER_TX_ln18_status_TYPE[10] - RO */ 4993 uint32_t ln18_block_lock_ll : 1; /* CL91_USER_TX_ln18_status_TYPE[11] - RO */ 4994 uint32_t ln18_block_lock_lh : 1; /* CL91_USER_TX_ln18_status_TYPE[12] - RO */ 4995 uint32_t ln18_block_lock : 1; /* CL91_USER_TX_ln18_status_TYPE[13] - RO */ 4996 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln18_status_TYPE[15:14] - RSVD */ 4997 uint32_t reserved : 16; 4998 #endif /* IS_LITTLE_ENDIAN */ 4999 } fields; 5000 } CL91_USER_TX_ln18_status_TYPE; 5001 5002 typedef CL91_USER_TX_ln18_status_TYPE CL91_USER_TX_LN18_STATUS_TYPE_T; 5003 5004 typedef union { 5005 uint32_t data; 5006 struct { 5007 #if IS_BIG_ENDIAN 5008 uint32_t reserved : 16; 5009 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln19_status_TYPE[15:14] - RSVD */ 5010 uint32_t ln19_block_lock : 1; /* CL91_USER_TX_ln19_status_TYPE[13] - RO */ 5011 uint32_t ln19_block_lock_lh : 1; /* CL91_USER_TX_ln19_status_TYPE[12] - RO */ 5012 uint32_t ln19_block_lock_ll : 1; /* CL91_USER_TX_ln19_status_TYPE[11] - RO */ 5013 uint32_t ln19_am_lock : 1; /* CL91_USER_TX_ln19_status_TYPE[10] - RO */ 5014 uint32_t ln19_am_lock_lh : 1; /* CL91_USER_TX_ln19_status_TYPE[09] - RO */ 5015 uint32_t ln19_am_lock_ll : 1; /* CL91_USER_TX_ln19_status_TYPE[08] - RO */ 5016 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln19_status_TYPE[07:05] - RSVD */ 5017 uint32_t ln19_pcsl_lane_number : 5; /* CL91_USER_TX_ln19_status_TYPE[04:00] - RO */ 5018 #endif /* IS_BIG_ENDIAN */ 5019 #if IS_LITTLE_ENDIAN 5020 uint32_t ln19_pcsl_lane_number : 5; /* CL91_USER_TX_ln19_status_TYPE[04:00] - RO */ 5021 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln19_status_TYPE[07:05] - RSVD */ 5022 uint32_t ln19_am_lock_ll : 1; /* CL91_USER_TX_ln19_status_TYPE[08] - RO */ 5023 uint32_t ln19_am_lock_lh : 1; /* CL91_USER_TX_ln19_status_TYPE[09] - RO */ 5024 uint32_t ln19_am_lock : 1; /* CL91_USER_TX_ln19_status_TYPE[10] - RO */ 5025 uint32_t ln19_block_lock_ll : 1; /* CL91_USER_TX_ln19_status_TYPE[11] - RO */ 5026 uint32_t ln19_block_lock_lh : 1; /* CL91_USER_TX_ln19_status_TYPE[12] - RO */ 5027 uint32_t ln19_block_lock : 1; /* CL91_USER_TX_ln19_status_TYPE[13] - RO */ 5028 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln19_status_TYPE[15:14] - RSVD */ 5029 uint32_t reserved : 16; 5030 #endif /* IS_LITTLE_ENDIAN */ 5031 } fields; 5032 } CL91_USER_TX_ln19_status_TYPE; 5033 5034 typedef CL91_USER_TX_ln19_status_TYPE CL91_USER_TX_LN19_STATUS_TYPE_T; 5035 5036 5037 /*-----------------------------------------------*/ 5038 /* Structs for RX_ANA_REGS Bank */ 5039 /*-----------------------------------------------*/ 5040 typedef union { 5041 uint32_t data; 5042 struct { 5043 #if IS_BIG_ENDIAN 5044 uint32_t reserved : 16; 5045 uint32_t reserved_15 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[15] - RSVD */ 5046 uint32_t reserved_14 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[14] - RSVD */ 5047 uint32_t reserved_13 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[13] - RSVD */ 5048 uint32_t reserved_12 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[12] - RSVD */ 5049 uint32_t reserved_11 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[11] - RSVD */ 5050 uint32_t reserved_10 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[10] - RSVD */ 5051 uint32_t reserved_09 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[09] - RSVD */ 5052 uint32_t reserved_08 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[08] - RSVD */ 5053 uint32_t reserved_07 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[07] - RSVD */ 5054 uint32_t use_kr4_block_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[06] - WO */ 5055 uint32_t reserved_05 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[05] - RSVD */ 5056 uint32_t reserved_04 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[04] - RSVD */ 5057 uint32_t use_kr4_pmd_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[03] - WO */ 5058 uint32_t reserved_02 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[02] - RSVD */ 5059 uint32_t reserved_01 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[01] - RSVD */ 5060 uint32_t reserved_00 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[00] - RSVD */ 5061 #endif /* IS_BIG_ENDIAN */ 5062 #if IS_LITTLE_ENDIAN 5063 uint32_t reserved_00 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[00] - RSVD */ 5064 uint32_t reserved_01 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[01] - RSVD */ 5065 uint32_t reserved_02 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[02] - RSVD */ 5066 uint32_t use_kr4_pmd_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[03] - WO */ 5067 uint32_t reserved_04 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[04] - RSVD */ 5068 uint32_t reserved_05 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[05] - RSVD */ 5069 uint32_t use_kr4_block_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[06] - WO */ 5070 uint32_t reserved_07 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[07] - RSVD */ 5071 uint32_t reserved_08 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[08] - RSVD */ 5072 uint32_t reserved_09 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[09] - RSVD */ 5073 uint32_t reserved_10 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[10] - RSVD */ 5074 uint32_t reserved_11 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[11] - RSVD */ 5075 uint32_t reserved_12 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[12] - RSVD */ 5076 uint32_t reserved_13 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[13] - RSVD */ 5077 uint32_t reserved_14 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[14] - RSVD */ 5078 uint32_t reserved_15 : 1; /* RX_ANA_REGS_anaRxControl3_TYPE[15] - RSVD */ 5079 uint32_t reserved : 16; 5080 #endif /* IS_LITTLE_ENDIAN */ 5081 } fields; 5082 } RX_ANA_REGS_anaRxControl3_TYPE; 5083 5084 typedef RX_ANA_REGS_anaRxControl3_TYPE RX_ANA_REGS_ANARXCONTROL3_TYPE_T; 5085 5086 5087 /*-----------------------------------------------*/ 5088 /* Structs for DP Bank */ 5089 /*-----------------------------------------------*/ 5090 typedef union { 5091 uint32_t data; 5092 struct { 5093 #if IS_BIG_ENDIAN 5094 uint32_t reserved : 16; 5095 uint32_t reserved_01 : 15; /* DP_dp_control0_TYPE[15:01] - RSVD */ 5096 uint32_t datapath_rstb : 1; /* DP_dp_control0_TYPE[00] - WO */ 5097 #endif /* IS_BIG_ENDIAN */ 5098 #if IS_LITTLE_ENDIAN 5099 uint32_t datapath_rstb : 1; /* DP_dp_control0_TYPE[00] - WO */ 5100 uint32_t reserved_01 : 15; /* DP_dp_control0_TYPE[15:01] - RSVD */ 5101 uint32_t reserved : 16; 5102 #endif /* IS_LITTLE_ENDIAN */ 5103 } fields; 5104 } DP_dp_control0_TYPE; 5105 5106 typedef DP_dp_control0_TYPE DP_DP_CONTROL0_TYPE_T; 5107 5108 typedef union { 5109 uint32_t data; 5110 struct { 5111 #if IS_BIG_ENDIAN 5112 uint32_t reserved : 16; 5113 uint32_t reserved_15 : 1; /* DP_sesto_mode_ctrl0_TYPE[15] - RSVD */ 5114 uint32_t mode_falcon_line : 1; /* DP_sesto_mode_ctrl0_TYPE[14] - WO */ 5115 uint32_t mode_cl91_en : 1; /* DP_sesto_mode_ctrl0_TYPE[13] - WO */ 5116 uint32_t mode_enzo_combatible_en : 1; /* DP_sesto_mode_ctrl0_TYPE[12] - WO */ 5117 uint32_t mode_100g_gbox_en : 1; /* DP_sesto_mode_ctrl0_TYPE[11] - WO */ 5118 uint32_t mode_40g_passthru_en : 1; /* DP_sesto_mode_ctrl0_TYPE[10] - WO */ 5119 uint32_t mode_multiport1_40g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[09] - WO */ 5120 uint32_t mode_multiport1_20g_passthru : 1; /* DP_sesto_mode_ctrl0_TYPE[08] - WO */ 5121 uint32_t mode_multiport1_20g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[07] - WO */ 5122 uint32_t mode_multiport1_10g1 : 1; /* DP_sesto_mode_ctrl0_TYPE[06] - WO */ 5123 uint32_t mode_multiport1_10g2 : 1; /* DP_sesto_mode_ctrl0_TYPE[05] - WO */ 5124 uint32_t mode_multiport2_40g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[04] - WO */ 5125 uint32_t mode_multiport2_20g_passthru : 1; /* DP_sesto_mode_ctrl0_TYPE[03] - WO */ 5126 uint32_t mode_multiport2_20g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[02] - WO */ 5127 uint32_t mode_multiport2_10g1 : 1; /* DP_sesto_mode_ctrl0_TYPE[01] - WO */ 5128 uint32_t mode_multiport2_10g2 : 1; /* DP_sesto_mode_ctrl0_TYPE[00] - WO */ 5129 #endif /* IS_BIG_ENDIAN */ 5130 #if IS_LITTLE_ENDIAN 5131 uint32_t mode_multiport2_10g2 : 1; /* DP_sesto_mode_ctrl0_TYPE[00] - WO */ 5132 uint32_t mode_multiport2_10g1 : 1; /* DP_sesto_mode_ctrl0_TYPE[01] - WO */ 5133 uint32_t mode_multiport2_20g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[02] - WO */ 5134 uint32_t mode_multiport2_20g_passthru : 1; /* DP_sesto_mode_ctrl0_TYPE[03] - WO */ 5135 uint32_t mode_multiport2_40g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[04] - WO */ 5136 uint32_t mode_multiport1_10g2 : 1; /* DP_sesto_mode_ctrl0_TYPE[05] - WO */ 5137 uint32_t mode_multiport1_10g1 : 1; /* DP_sesto_mode_ctrl0_TYPE[06] - WO */ 5138 uint32_t mode_multiport1_20g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[07] - WO */ 5139 uint32_t mode_multiport1_20g_passthru : 1; /* DP_sesto_mode_ctrl0_TYPE[08] - WO */ 5140 uint32_t mode_multiport1_40g_mux : 1; /* DP_sesto_mode_ctrl0_TYPE[09] - WO */ 5141 uint32_t mode_40g_passthru_en : 1; /* DP_sesto_mode_ctrl0_TYPE[10] - WO */ 5142 uint32_t mode_100g_gbox_en : 1; /* DP_sesto_mode_ctrl0_TYPE[11] - WO */ 5143 uint32_t mode_enzo_combatible_en : 1; /* DP_sesto_mode_ctrl0_TYPE[12] - WO */ 5144 uint32_t mode_cl91_en : 1; /* DP_sesto_mode_ctrl0_TYPE[13] - WO */ 5145 uint32_t mode_falcon_line : 1; /* DP_sesto_mode_ctrl0_TYPE[14] - WO */ 5146 uint32_t reserved_15 : 1; /* DP_sesto_mode_ctrl0_TYPE[15] - RSVD */ 5147 uint32_t reserved : 16; 5148 #endif /* IS_LITTLE_ENDIAN */ 5149 } fields; 5150 } DP_sesto_mode_ctrl0_TYPE; 5151 5152 typedef DP_sesto_mode_ctrl0_TYPE DP_SESTO_MODE_CTRL0_TYPE_T; 5153 5154 typedef union { 5155 uint32_t data; 5156 struct { 5157 #if IS_BIG_ENDIAN 5158 uint32_t reserved : 16; 5159 uint32_t reserved_14 : 2; /* DP_sesto_mode_ctrl1_TYPE[15:14] - RSVD */ 5160 uint32_t udms_en1 : 1; /* DP_sesto_mode_ctrl1_TYPE[13] - WO */ 5161 uint32_t udms_en2 : 1; /* DP_sesto_mode_ctrl1_TYPE[12] - WO */ 5162 uint32_t reserved_04 : 8; /* DP_sesto_mode_ctrl1_TYPE[11:04] - RSVD */ 5163 uint32_t mode_dmept1_en : 1; /* DP_sesto_mode_ctrl1_TYPE[03] - WO */ 5164 uint32_t mode_dmept1b_en : 1; /* DP_sesto_mode_ctrl1_TYPE[02] - WO */ 5165 uint32_t mode_dmept2_en : 1; /* DP_sesto_mode_ctrl1_TYPE[01] - WO */ 5166 uint32_t mode_dmept2b_en : 1; /* DP_sesto_mode_ctrl1_TYPE[00] - WO */ 5167 #endif /* IS_BIG_ENDIAN */ 5168 #if IS_LITTLE_ENDIAN 5169 uint32_t mode_dmept2b_en : 1; /* DP_sesto_mode_ctrl1_TYPE[00] - WO */ 5170 uint32_t mode_dmept2_en : 1; /* DP_sesto_mode_ctrl1_TYPE[01] - WO */ 5171 uint32_t mode_dmept1b_en : 1; /* DP_sesto_mode_ctrl1_TYPE[02] - WO */ 5172 uint32_t mode_dmept1_en : 1; /* DP_sesto_mode_ctrl1_TYPE[03] - WO */ 5173 uint32_t reserved_04 : 8; /* DP_sesto_mode_ctrl1_TYPE[11:04] - RSVD */ 5174 uint32_t udms_en2 : 1; /* DP_sesto_mode_ctrl1_TYPE[12] - WO */ 5175 uint32_t udms_en1 : 1; /* DP_sesto_mode_ctrl1_TYPE[13] - WO */ 5176 uint32_t reserved_14 : 2; /* DP_sesto_mode_ctrl1_TYPE[15:14] - RSVD */ 5177 uint32_t reserved : 16; 5178 #endif /* IS_LITTLE_ENDIAN */ 5179 } fields; 5180 } DP_sesto_mode_ctrl1_TYPE; 5181 5182 typedef DP_sesto_mode_ctrl1_TYPE DP_SESTO_MODE_CTRL1_TYPE_T; 5183 5184 typedef union { 5185 uint32_t data; 5186 struct { 5187 #if IS_BIG_ENDIAN 5188 uint32_t reserved : 16; 5189 uint32_t demux_ilane_dp_rstb : 4; /* DP_lane_reset_control0_TYPE[15:12] - WO */ 5190 uint32_t reserved_10 : 2; /* DP_lane_reset_control0_TYPE[11:10] - RSVD */ 5191 uint32_t mux_ilane_dp_rstb : 10; /* DP_lane_reset_control0_TYPE[09:00] - WO */ 5192 #endif /* IS_BIG_ENDIAN */ 5193 #if IS_LITTLE_ENDIAN 5194 uint32_t mux_ilane_dp_rstb : 10; /* DP_lane_reset_control0_TYPE[09:00] - WO */ 5195 uint32_t reserved_10 : 2; /* DP_lane_reset_control0_TYPE[11:10] - RSVD */ 5196 uint32_t demux_ilane_dp_rstb : 4; /* DP_lane_reset_control0_TYPE[15:12] - WO */ 5197 uint32_t reserved : 16; 5198 #endif /* IS_LITTLE_ENDIAN */ 5199 } fields; 5200 } DP_lane_reset_control0_TYPE; 5201 5202 typedef DP_lane_reset_control0_TYPE DP_LANE_RESET_CONTROL0_TYPE_T; 5203 5204 typedef union { 5205 uint32_t data; 5206 struct { 5207 #if IS_BIG_ENDIAN 5208 uint32_t reserved : 16; 5209 uint32_t reserved_15 : 1; /* DP_decoded_mode_status0_TYPE[15] - RSVD */ 5210 uint32_t decoded_mode_100g_gbox : 1; /* DP_decoded_mode_status0_TYPE[14] - RO */ 5211 uint32_t decoded_mode_10g_p1 : 1; /* DP_decoded_mode_status0_TYPE[13] - RO */ 5212 uint32_t decoded_mode_10g_p2 : 1; /* DP_decoded_mode_status0_TYPE[12] - RO */ 5213 uint32_t decoded_mode_10g_p3 : 1; /* DP_decoded_mode_status0_TYPE[11] - RO */ 5214 uint32_t decoded_mode_10g_p4 : 1; /* DP_decoded_mode_status0_TYPE[10] - RO */ 5215 uint32_t decoded_mode_20g_mux_p1 : 1; /* DP_decoded_mode_status0_TYPE[09] - RO */ 5216 uint32_t decoded_mode_20g_mux_p2 : 1; /* DP_decoded_mode_status0_TYPE[08] - RO */ 5217 uint32_t decoded_mode_20g_passthru_p1 : 1; /* DP_decoded_mode_status0_TYPE[07] - RO */ 5218 uint32_t decoded_mode_20g_passthru_p2 : 1; /* DP_decoded_mode_status0_TYPE[06] - RO */ 5219 uint32_t decoded_mode_40g_mux_p1 : 1; /* DP_decoded_mode_status0_TYPE[05] - RO */ 5220 uint32_t decoded_mode_40g_mux_p2 : 1; /* DP_decoded_mode_status0_TYPE[04] - RO */ 5221 uint32_t decoded_mode_40g_passthru : 1; /* DP_decoded_mode_status0_TYPE[03] - RO */ 5222 uint32_t decoded_mode_cl91_en : 1; /* DP_decoded_mode_status0_TYPE[02] - RO */ 5223 uint32_t decoded_mode_enzo_compatible : 1; /* DP_decoded_mode_status0_TYPE[01] - RO */ 5224 uint32_t decoded_mode_falcon_line : 1; /* DP_decoded_mode_status0_TYPE[00] - RO */ 5225 #endif /* IS_BIG_ENDIAN */ 5226 #if IS_LITTLE_ENDIAN 5227 uint32_t decoded_mode_falcon_line : 1; /* DP_decoded_mode_status0_TYPE[00] - RO */ 5228 uint32_t decoded_mode_enzo_compatible : 1; /* DP_decoded_mode_status0_TYPE[01] - RO */ 5229 uint32_t decoded_mode_cl91_en : 1; /* DP_decoded_mode_status0_TYPE[02] - RO */ 5230 uint32_t decoded_mode_40g_passthru : 1; /* DP_decoded_mode_status0_TYPE[03] - RO */ 5231 uint32_t decoded_mode_40g_mux_p2 : 1; /* DP_decoded_mode_status0_TYPE[04] - RO */ 5232 uint32_t decoded_mode_40g_mux_p1 : 1; /* DP_decoded_mode_status0_TYPE[05] - RO */ 5233 uint32_t decoded_mode_20g_passthru_p2 : 1; /* DP_decoded_mode_status0_TYPE[06] - RO */ 5234 uint32_t decoded_mode_20g_passthru_p1 : 1; /* DP_decoded_mode_status0_TYPE[07] - RO */ 5235 uint32_t decoded_mode_20g_mux_p2 : 1; /* DP_decoded_mode_status0_TYPE[08] - RO */ 5236 uint32_t decoded_mode_20g_mux_p1 : 1; /* DP_decoded_mode_status0_TYPE[09] - RO */ 5237 uint32_t decoded_mode_10g_p4 : 1; /* DP_decoded_mode_status0_TYPE[10] - RO */ 5238 uint32_t decoded_mode_10g_p3 : 1; /* DP_decoded_mode_status0_TYPE[11] - RO */ 5239 uint32_t decoded_mode_10g_p2 : 1; /* DP_decoded_mode_status0_TYPE[12] - RO */ 5240 uint32_t decoded_mode_10g_p1 : 1; /* DP_decoded_mode_status0_TYPE[13] - RO */ 5241 uint32_t decoded_mode_100g_gbox : 1; /* DP_decoded_mode_status0_TYPE[14] - RO */ 5242 uint32_t reserved_15 : 1; /* DP_decoded_mode_status0_TYPE[15] - RSVD */ 5243 uint32_t reserved : 16; 5244 #endif /* IS_LITTLE_ENDIAN */ 5245 } fields; 5246 } DP_decoded_mode_status0_TYPE; 5247 5248 typedef DP_decoded_mode_status0_TYPE DP_DECODED_MODE_STATUS0_TYPE_T; 5249 5250 typedef union { 5251 uint32_t data; 5252 struct { 5253 #if IS_BIG_ENDIAN 5254 uint32_t reserved : 16; 5255 uint32_t reserved_12 : 4; /* DP_decoded_mode_status1_TYPE[15:12] - RSVD */ 5256 uint32_t decoded_dptmode_100g_gbox : 1; /* DP_decoded_mode_status1_TYPE[11] - RO */ 5257 uint32_t decoded_dptmode_10g_p1 : 1; /* DP_decoded_mode_status1_TYPE[10] - RO */ 5258 uint32_t decoded_dptmode_10g_p2 : 1; /* DP_decoded_mode_status1_TYPE[09] - RO */ 5259 uint32_t decoded_dptmode_10g_p3 : 1; /* DP_decoded_mode_status1_TYPE[08] - RO */ 5260 uint32_t decoded_dptmode_10g_p4 : 1; /* DP_decoded_mode_status1_TYPE[07] - RO */ 5261 uint32_t decoded_dptmode_20g_mux_p1 : 1; /* DP_decoded_mode_status1_TYPE[06] - RO */ 5262 uint32_t decoded_dptmode_20g_mux_p2 : 1; /* DP_decoded_mode_status1_TYPE[05] - RO */ 5263 uint32_t decoded_dptmode_20g_passthru_p1 : 1; /* DP_decoded_mode_status1_TYPE[04] - RO */ 5264 uint32_t decoded_dptmode_20g_passthru_p2 : 1; /* DP_decoded_mode_status1_TYPE[03] - RO */ 5265 uint32_t decoded_dptmode_40g_mux_p1 : 1; /* DP_decoded_mode_status1_TYPE[02] - RO */ 5266 uint32_t decoded_dptmode_40g_mux_p2 : 1; /* DP_decoded_mode_status1_TYPE[01] - RO */ 5267 uint32_t decoded_dptmode_40g_passthru : 1; /* DP_decoded_mode_status1_TYPE[00] - RO */ 5268 #endif /* IS_BIG_ENDIAN */ 5269 #if IS_LITTLE_ENDIAN 5270 uint32_t decoded_dptmode_40g_passthru : 1; /* DP_decoded_mode_status1_TYPE[00] - RO */ 5271 uint32_t decoded_dptmode_40g_mux_p2 : 1; /* DP_decoded_mode_status1_TYPE[01] - RO */ 5272 uint32_t decoded_dptmode_40g_mux_p1 : 1; /* DP_decoded_mode_status1_TYPE[02] - RO */ 5273 uint32_t decoded_dptmode_20g_passthru_p2 : 1; /* DP_decoded_mode_status1_TYPE[03] - RO */ 5274 uint32_t decoded_dptmode_20g_passthru_p1 : 1; /* DP_decoded_mode_status1_TYPE[04] - RO */ 5275 uint32_t decoded_dptmode_20g_mux_p2 : 1; /* DP_decoded_mode_status1_TYPE[05] - RO */ 5276 uint32_t decoded_dptmode_20g_mux_p1 : 1; /* DP_decoded_mode_status1_TYPE[06] - RO */ 5277 uint32_t decoded_dptmode_10g_p4 : 1; /* DP_decoded_mode_status1_TYPE[07] - RO */ 5278 uint32_t decoded_dptmode_10g_p3 : 1; /* DP_decoded_mode_status1_TYPE[08] - RO */ 5279 uint32_t decoded_dptmode_10g_p2 : 1; /* DP_decoded_mode_status1_TYPE[09] - RO */ 5280 uint32_t decoded_dptmode_10g_p1 : 1; /* DP_decoded_mode_status1_TYPE[10] - RO */ 5281 uint32_t decoded_dptmode_100g_gbox : 1; /* DP_decoded_mode_status1_TYPE[11] - RO */ 5282 uint32_t reserved_12 : 4; /* DP_decoded_mode_status1_TYPE[15:12] - RSVD */ 5283 uint32_t reserved : 16; 5284 #endif /* IS_LITTLE_ENDIAN */ 5285 } fields; 5286 } DP_decoded_mode_status1_TYPE; 5287 5288 typedef DP_decoded_mode_status1_TYPE DP_DECODED_MODE_STATUS1_TYPE_T; 5289 5290 typedef union { 5291 uint32_t data; 5292 struct { 5293 #if IS_BIG_ENDIAN 5294 uint32_t reserved : 16; 5295 uint32_t reserved_15 : 1; /* DP_demux_fec_rc_ctrl_TYPE[15] - RSVD */ 5296 uint32_t reserved_14 : 1; /* DP_demux_fec_rc_ctrl_TYPE[14] - RSVD */ 5297 uint32_t reserved_08 : 6; /* DP_demux_fec_rc_ctrl_TYPE[13:08] - RSVD */ 5298 uint32_t reserved_04 : 4; /* DP_demux_fec_rc_ctrl_TYPE[07:04] - RSVD */ 5299 uint32_t reserved_03 : 1; /* DP_demux_fec_rc_ctrl_TYPE[03] - RSVD */ 5300 uint32_t demux_fec_rc_edet : 1; /* DP_demux_fec_rc_ctrl_TYPE[02] - WO */ 5301 uint32_t demux_fec_rc_perf : 2; /* DP_demux_fec_rc_ctrl_TYPE[01:00] - WO */ 5302 #endif /* IS_BIG_ENDIAN */ 5303 #if IS_LITTLE_ENDIAN 5304 uint32_t demux_fec_rc_perf : 2; /* DP_demux_fec_rc_ctrl_TYPE[01:00] - WO */ 5305 uint32_t demux_fec_rc_edet : 1; /* DP_demux_fec_rc_ctrl_TYPE[02] - WO */ 5306 uint32_t reserved_03 : 1; /* DP_demux_fec_rc_ctrl_TYPE[03] - RSVD */ 5307 uint32_t reserved_04 : 4; /* DP_demux_fec_rc_ctrl_TYPE[07:04] - RSVD */ 5308 uint32_t reserved_08 : 6; /* DP_demux_fec_rc_ctrl_TYPE[13:08] - RSVD */ 5309 uint32_t reserved_14 : 1; /* DP_demux_fec_rc_ctrl_TYPE[14] - RSVD */ 5310 uint32_t reserved_15 : 1; /* DP_demux_fec_rc_ctrl_TYPE[15] - RSVD */ 5311 uint32_t reserved : 16; 5312 #endif /* IS_LITTLE_ENDIAN */ 5313 } fields; 5314 } DP_demux_fec_rc_ctrl_TYPE; 5315 5316 typedef DP_demux_fec_rc_ctrl_TYPE DP_DEMUX_FEC_RC_CTRL_TYPE_T; 5317 5318 typedef union { 5319 uint32_t data; 5320 struct { 5321 #if IS_BIG_ENDIAN 5322 uint32_t reserved : 16; 5323 uint32_t reserved_15 : 1; /* DP_demux_p0_fifo_ctrl_TYPE[15] - RSVD */ 5324 uint32_t reserved_14 : 1; /* DP_demux_p0_fifo_ctrl_TYPE[14] - RSVD */ 5325 uint32_t reserved_08 : 6; /* DP_demux_p0_fifo_ctrl_TYPE[13:08] - RSVD */ 5326 uint32_t reserved_04 : 4; /* DP_demux_p0_fifo_ctrl_TYPE[07:04] - RSVD */ 5327 uint32_t reserved_03 : 1; /* DP_demux_p0_fifo_ctrl_TYPE[03] - RSVD */ 5328 uint32_t demux_p0_edet : 1; /* DP_demux_p0_fifo_ctrl_TYPE[02] - WO */ 5329 uint32_t demux_p0_perf : 2; /* DP_demux_p0_fifo_ctrl_TYPE[01:00] - WO */ 5330 #endif /* IS_BIG_ENDIAN */ 5331 #if IS_LITTLE_ENDIAN 5332 uint32_t demux_p0_perf : 2; /* DP_demux_p0_fifo_ctrl_TYPE[01:00] - WO */ 5333 uint32_t demux_p0_edet : 1; /* DP_demux_p0_fifo_ctrl_TYPE[02] - WO */ 5334 uint32_t reserved_03 : 1; /* DP_demux_p0_fifo_ctrl_TYPE[03] - RSVD */ 5335 uint32_t reserved_04 : 4; /* DP_demux_p0_fifo_ctrl_TYPE[07:04] - RSVD */ 5336 uint32_t reserved_08 : 6; /* DP_demux_p0_fifo_ctrl_TYPE[13:08] - RSVD */ 5337 uint32_t reserved_14 : 1; /* DP_demux_p0_fifo_ctrl_TYPE[14] - RSVD */ 5338 uint32_t reserved_15 : 1; /* DP_demux_p0_fifo_ctrl_TYPE[15] - RSVD */ 5339 uint32_t reserved : 16; 5340 #endif /* IS_LITTLE_ENDIAN */ 5341 } fields; 5342 } DP_demux_p0_fifo_ctrl_TYPE; 5343 5344 typedef DP_demux_p0_fifo_ctrl_TYPE DP_DEMUX_P0_FIFO_CTRL_TYPE_T; 5345 5346 typedef union { 5347 uint32_t data; 5348 struct { 5349 #if IS_BIG_ENDIAN 5350 uint32_t reserved : 16; 5351 uint32_t reserved_15 : 1; /* DP_demux_p1_fifo_ctrl_TYPE[15] - RSVD */ 5352 uint32_t reserved_14 : 1; /* DP_demux_p1_fifo_ctrl_TYPE[14] - RSVD */ 5353 uint32_t reserved_08 : 6; /* DP_demux_p1_fifo_ctrl_TYPE[13:08] - RSVD */ 5354 uint32_t reserved_04 : 4; /* DP_demux_p1_fifo_ctrl_TYPE[07:04] - RSVD */ 5355 uint32_t reserved_03 : 1; /* DP_demux_p1_fifo_ctrl_TYPE[03] - RSVD */ 5356 uint32_t demux_p1_edet : 1; /* DP_demux_p1_fifo_ctrl_TYPE[02] - WO */ 5357 uint32_t demux_p1_perf : 2; /* DP_demux_p1_fifo_ctrl_TYPE[01:00] - WO */ 5358 #endif /* IS_BIG_ENDIAN */ 5359 #if IS_LITTLE_ENDIAN 5360 uint32_t demux_p1_perf : 2; /* DP_demux_p1_fifo_ctrl_TYPE[01:00] - WO */ 5361 uint32_t demux_p1_edet : 1; /* DP_demux_p1_fifo_ctrl_TYPE[02] - WO */ 5362 uint32_t reserved_03 : 1; /* DP_demux_p1_fifo_ctrl_TYPE[03] - RSVD */ 5363 uint32_t reserved_04 : 4; /* DP_demux_p1_fifo_ctrl_TYPE[07:04] - RSVD */ 5364 uint32_t reserved_08 : 6; /* DP_demux_p1_fifo_ctrl_TYPE[13:08] - RSVD */ 5365 uint32_t reserved_14 : 1; /* DP_demux_p1_fifo_ctrl_TYPE[14] - RSVD */ 5366 uint32_t reserved_15 : 1; /* DP_demux_p1_fifo_ctrl_TYPE[15] - RSVD */ 5367 uint32_t reserved : 16; 5368 #endif /* IS_LITTLE_ENDIAN */ 5369 } fields; 5370 } DP_demux_p1_fifo_ctrl_TYPE; 5371 5372 typedef DP_demux_p1_fifo_ctrl_TYPE DP_DEMUX_P1_FIFO_CTRL_TYPE_T; 5373 5374 typedef union { 5375 uint32_t data; 5376 struct { 5377 #if IS_BIG_ENDIAN 5378 uint32_t reserved : 16; 5379 uint32_t reserved_15 : 1; /* DP_demux_p2_fifo_ctrl_TYPE[15] - RSVD */ 5380 uint32_t reserved_14 : 1; /* DP_demux_p2_fifo_ctrl_TYPE[14] - RSVD */ 5381 uint32_t reserved_08 : 6; /* DP_demux_p2_fifo_ctrl_TYPE[13:08] - RSVD */ 5382 uint32_t reserved_04 : 4; /* DP_demux_p2_fifo_ctrl_TYPE[07:04] - RSVD */ 5383 uint32_t reserved_03 : 1; /* DP_demux_p2_fifo_ctrl_TYPE[03] - RSVD */ 5384 uint32_t demux_p2_edet : 1; /* DP_demux_p2_fifo_ctrl_TYPE[02] - WO */ 5385 uint32_t demux_p2_perf : 2; /* DP_demux_p2_fifo_ctrl_TYPE[01:00] - WO */ 5386 #endif /* IS_BIG_ENDIAN */ 5387 #if IS_LITTLE_ENDIAN 5388 uint32_t demux_p2_perf : 2; /* DP_demux_p2_fifo_ctrl_TYPE[01:00] - WO */ 5389 uint32_t demux_p2_edet : 1; /* DP_demux_p2_fifo_ctrl_TYPE[02] - WO */ 5390 uint32_t reserved_03 : 1; /* DP_demux_p2_fifo_ctrl_TYPE[03] - RSVD */ 5391 uint32_t reserved_04 : 4; /* DP_demux_p2_fifo_ctrl_TYPE[07:04] - RSVD */ 5392 uint32_t reserved_08 : 6; /* DP_demux_p2_fifo_ctrl_TYPE[13:08] - RSVD */ 5393 uint32_t reserved_14 : 1; /* DP_demux_p2_fifo_ctrl_TYPE[14] - RSVD */ 5394 uint32_t reserved_15 : 1; /* DP_demux_p2_fifo_ctrl_TYPE[15] - RSVD */ 5395 uint32_t reserved : 16; 5396 #endif /* IS_LITTLE_ENDIAN */ 5397 } fields; 5398 } DP_demux_p2_fifo_ctrl_TYPE; 5399 5400 typedef DP_demux_p2_fifo_ctrl_TYPE DP_DEMUX_P2_FIFO_CTRL_TYPE_T; 5401 5402 typedef union { 5403 uint32_t data; 5404 struct { 5405 #if IS_BIG_ENDIAN 5406 uint32_t reserved : 16; 5407 uint32_t reserved_15 : 1; /* DP_demux_p3_fifo_ctrl_TYPE[15] - RSVD */ 5408 uint32_t reserved_14 : 1; /* DP_demux_p3_fifo_ctrl_TYPE[14] - RSVD */ 5409 uint32_t reserved_08 : 6; /* DP_demux_p3_fifo_ctrl_TYPE[13:08] - RSVD */ 5410 uint32_t reserved_04 : 4; /* DP_demux_p3_fifo_ctrl_TYPE[07:04] - RSVD */ 5411 uint32_t reserved_03 : 1; /* DP_demux_p3_fifo_ctrl_TYPE[03] - RSVD */ 5412 uint32_t demux_p3_edet : 1; /* DP_demux_p3_fifo_ctrl_TYPE[02] - WO */ 5413 uint32_t demux_p3_perf : 2; /* DP_demux_p3_fifo_ctrl_TYPE[01:00] - WO */ 5414 #endif /* IS_BIG_ENDIAN */ 5415 #if IS_LITTLE_ENDIAN 5416 uint32_t demux_p3_perf : 2; /* DP_demux_p3_fifo_ctrl_TYPE[01:00] - WO */ 5417 uint32_t demux_p3_edet : 1; /* DP_demux_p3_fifo_ctrl_TYPE[02] - WO */ 5418 uint32_t reserved_03 : 1; /* DP_demux_p3_fifo_ctrl_TYPE[03] - RSVD */ 5419 uint32_t reserved_04 : 4; /* DP_demux_p3_fifo_ctrl_TYPE[07:04] - RSVD */ 5420 uint32_t reserved_08 : 6; /* DP_demux_p3_fifo_ctrl_TYPE[13:08] - RSVD */ 5421 uint32_t reserved_14 : 1; /* DP_demux_p3_fifo_ctrl_TYPE[14] - RSVD */ 5422 uint32_t reserved_15 : 1; /* DP_demux_p3_fifo_ctrl_TYPE[15] - RSVD */ 5423 uint32_t reserved : 16; 5424 #endif /* IS_LITTLE_ENDIAN */ 5425 } fields; 5426 } DP_demux_p3_fifo_ctrl_TYPE; 5427 5428 typedef DP_demux_p3_fifo_ctrl_TYPE DP_DEMUX_P3_FIFO_CTRL_TYPE_T; 5429 5430 typedef union { 5431 uint32_t data; 5432 struct { 5433 #if IS_BIG_ENDIAN 5434 uint32_t reserved : 16; 5435 uint32_t reserved_15 : 1; /* DP_mux_fec_rc_ctrl_TYPE[15] - RSVD */ 5436 uint32_t reserved_14 : 1; /* DP_mux_fec_rc_ctrl_TYPE[14] - RSVD */ 5437 uint32_t reserved_08 : 6; /* DP_mux_fec_rc_ctrl_TYPE[13:08] - RSVD */ 5438 uint32_t reserved_07 : 1; /* DP_mux_fec_rc_ctrl_TYPE[07] - RSVD */ 5439 uint32_t reserved_04 : 3; /* DP_mux_fec_rc_ctrl_TYPE[06:04] - RSVD */ 5440 uint32_t reserved_03 : 1; /* DP_mux_fec_rc_ctrl_TYPE[03] - RSVD */ 5441 uint32_t mux_fec_rc_edet : 1; /* DP_mux_fec_rc_ctrl_TYPE[02] - WO */ 5442 uint32_t mux_fec_rc_perf : 2; /* DP_mux_fec_rc_ctrl_TYPE[01:00] - WO */ 5443 #endif /* IS_BIG_ENDIAN */ 5444 #if IS_LITTLE_ENDIAN 5445 uint32_t mux_fec_rc_perf : 2; /* DP_mux_fec_rc_ctrl_TYPE[01:00] - WO */ 5446 uint32_t mux_fec_rc_edet : 1; /* DP_mux_fec_rc_ctrl_TYPE[02] - WO */ 5447 uint32_t reserved_03 : 1; /* DP_mux_fec_rc_ctrl_TYPE[03] - RSVD */ 5448 uint32_t reserved_04 : 3; /* DP_mux_fec_rc_ctrl_TYPE[06:04] - RSVD */ 5449 uint32_t reserved_07 : 1; /* DP_mux_fec_rc_ctrl_TYPE[07] - RSVD */ 5450 uint32_t reserved_08 : 6; /* DP_mux_fec_rc_ctrl_TYPE[13:08] - RSVD */ 5451 uint32_t reserved_14 : 1; /* DP_mux_fec_rc_ctrl_TYPE[14] - RSVD */ 5452 uint32_t reserved_15 : 1; /* DP_mux_fec_rc_ctrl_TYPE[15] - RSVD */ 5453 uint32_t reserved : 16; 5454 #endif /* IS_LITTLE_ENDIAN */ 5455 } fields; 5456 } DP_mux_fec_rc_ctrl_TYPE; 5457 5458 typedef DP_mux_fec_rc_ctrl_TYPE DP_MUX_FEC_RC_CTRL_TYPE_T; 5459 5460 typedef union { 5461 uint32_t data; 5462 struct { 5463 #if IS_BIG_ENDIAN 5464 uint32_t reserved : 16; 5465 uint32_t reserved_15 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[15] - RSVD */ 5466 uint32_t reserved_14 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[14] - RSVD */ 5467 uint32_t reserved_08 : 6; /* DP_mux_p0_fifo_ctrl_TYPE[13:08] - RSVD */ 5468 uint32_t reserved_07 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[07] - RSVD */ 5469 uint32_t reserved_04 : 3; /* DP_mux_p0_fifo_ctrl_TYPE[06:04] - RSVD */ 5470 uint32_t reserved_03 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[03] - RSVD */ 5471 uint32_t mux_p0_edet : 1; /* DP_mux_p0_fifo_ctrl_TYPE[02] - WO */ 5472 uint32_t mux_p0_perf : 2; /* DP_mux_p0_fifo_ctrl_TYPE[01:00] - WO */ 5473 #endif /* IS_BIG_ENDIAN */ 5474 #if IS_LITTLE_ENDIAN 5475 uint32_t mux_p0_perf : 2; /* DP_mux_p0_fifo_ctrl_TYPE[01:00] - WO */ 5476 uint32_t mux_p0_edet : 1; /* DP_mux_p0_fifo_ctrl_TYPE[02] - WO */ 5477 uint32_t reserved_03 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[03] - RSVD */ 5478 uint32_t reserved_04 : 3; /* DP_mux_p0_fifo_ctrl_TYPE[06:04] - RSVD */ 5479 uint32_t reserved_07 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[07] - RSVD */ 5480 uint32_t reserved_08 : 6; /* DP_mux_p0_fifo_ctrl_TYPE[13:08] - RSVD */ 5481 uint32_t reserved_14 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[14] - RSVD */ 5482 uint32_t reserved_15 : 1; /* DP_mux_p0_fifo_ctrl_TYPE[15] - RSVD */ 5483 uint32_t reserved : 16; 5484 #endif /* IS_LITTLE_ENDIAN */ 5485 } fields; 5486 } DP_mux_p0_fifo_ctrl_TYPE; 5487 5488 typedef DP_mux_p0_fifo_ctrl_TYPE DP_MUX_P0_FIFO_CTRL_TYPE_T; 5489 5490 typedef union { 5491 uint32_t data; 5492 struct { 5493 #if IS_BIG_ENDIAN 5494 uint32_t reserved : 16; 5495 uint32_t reserved_15 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[15] - RSVD */ 5496 uint32_t reserved_14 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[14] - RSVD */ 5497 uint32_t reserved_08 : 6; /* DP_mux_p1_fifo_ctrl_TYPE[13:08] - RSVD */ 5498 uint32_t reserved_07 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[07] - RSVD */ 5499 uint32_t reserved_04 : 3; /* DP_mux_p1_fifo_ctrl_TYPE[06:04] - RSVD */ 5500 uint32_t reserved_03 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[03] - RSVD */ 5501 uint32_t mux_p1_edet : 1; /* DP_mux_p1_fifo_ctrl_TYPE[02] - WO */ 5502 uint32_t mux_p1_perf : 2; /* DP_mux_p1_fifo_ctrl_TYPE[01:00] - WO */ 5503 #endif /* IS_BIG_ENDIAN */ 5504 #if IS_LITTLE_ENDIAN 5505 uint32_t mux_p1_perf : 2; /* DP_mux_p1_fifo_ctrl_TYPE[01:00] - WO */ 5506 uint32_t mux_p1_edet : 1; /* DP_mux_p1_fifo_ctrl_TYPE[02] - WO */ 5507 uint32_t reserved_03 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[03] - RSVD */ 5508 uint32_t reserved_04 : 3; /* DP_mux_p1_fifo_ctrl_TYPE[06:04] - RSVD */ 5509 uint32_t reserved_07 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[07] - RSVD */ 5510 uint32_t reserved_08 : 6; /* DP_mux_p1_fifo_ctrl_TYPE[13:08] - RSVD */ 5511 uint32_t reserved_14 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[14] - RSVD */ 5512 uint32_t reserved_15 : 1; /* DP_mux_p1_fifo_ctrl_TYPE[15] - RSVD */ 5513 uint32_t reserved : 16; 5514 #endif /* IS_LITTLE_ENDIAN */ 5515 } fields; 5516 } DP_mux_p1_fifo_ctrl_TYPE; 5517 5518 typedef DP_mux_p1_fifo_ctrl_TYPE DP_MUX_P1_FIFO_CTRL_TYPE_T; 5519 5520 typedef union { 5521 uint32_t data; 5522 struct { 5523 #if IS_BIG_ENDIAN 5524 uint32_t reserved : 16; 5525 uint32_t reserved_15 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[15] - RSVD */ 5526 uint32_t reserved_14 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[14] - RSVD */ 5527 uint32_t reserved_08 : 6; /* DP_mux_p2_fifo_ctrl_TYPE[13:08] - RSVD */ 5528 uint32_t reserved_07 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[07] - RSVD */ 5529 uint32_t reserved_04 : 3; /* DP_mux_p2_fifo_ctrl_TYPE[06:04] - RSVD */ 5530 uint32_t reserved_03 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[03] - RSVD */ 5531 uint32_t mux_p2_edet : 1; /* DP_mux_p2_fifo_ctrl_TYPE[02] - WO */ 5532 uint32_t mux_p2_perf : 2; /* DP_mux_p2_fifo_ctrl_TYPE[01:00] - WO */ 5533 #endif /* IS_BIG_ENDIAN */ 5534 #if IS_LITTLE_ENDIAN 5535 uint32_t mux_p2_perf : 2; /* DP_mux_p2_fifo_ctrl_TYPE[01:00] - WO */ 5536 uint32_t mux_p2_edet : 1; /* DP_mux_p2_fifo_ctrl_TYPE[02] - WO */ 5537 uint32_t reserved_03 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[03] - RSVD */ 5538 uint32_t reserved_04 : 3; /* DP_mux_p2_fifo_ctrl_TYPE[06:04] - RSVD */ 5539 uint32_t reserved_07 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[07] - RSVD */ 5540 uint32_t reserved_08 : 6; /* DP_mux_p2_fifo_ctrl_TYPE[13:08] - RSVD */ 5541 uint32_t reserved_14 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[14] - RSVD */ 5542 uint32_t reserved_15 : 1; /* DP_mux_p2_fifo_ctrl_TYPE[15] - RSVD */ 5543 uint32_t reserved : 16; 5544 #endif /* IS_LITTLE_ENDIAN */ 5545 } fields; 5546 } DP_mux_p2_fifo_ctrl_TYPE; 5547 5548 typedef DP_mux_p2_fifo_ctrl_TYPE DP_MUX_P2_FIFO_CTRL_TYPE_T; 5549 5550 typedef union { 5551 uint32_t data; 5552 struct { 5553 #if IS_BIG_ENDIAN 5554 uint32_t reserved : 16; 5555 uint32_t reserved_15 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[15] - RSVD */ 5556 uint32_t reserved_14 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[14] - RSVD */ 5557 uint32_t reserved_08 : 6; /* DP_mux_p3_fifo_ctrl_TYPE[13:08] - RSVD */ 5558 uint32_t reserved_07 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[07] - RSVD */ 5559 uint32_t reserved_04 : 3; /* DP_mux_p3_fifo_ctrl_TYPE[06:04] - RSVD */ 5560 uint32_t reserved_03 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[03] - RSVD */ 5561 uint32_t mux_p3_edet : 1; /* DP_mux_p3_fifo_ctrl_TYPE[02] - WO */ 5562 uint32_t mux_p3_perf : 2; /* DP_mux_p3_fifo_ctrl_TYPE[01:00] - WO */ 5563 #endif /* IS_BIG_ENDIAN */ 5564 #if IS_LITTLE_ENDIAN 5565 uint32_t mux_p3_perf : 2; /* DP_mux_p3_fifo_ctrl_TYPE[01:00] - WO */ 5566 uint32_t mux_p3_edet : 1; /* DP_mux_p3_fifo_ctrl_TYPE[02] - WO */ 5567 uint32_t reserved_03 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[03] - RSVD */ 5568 uint32_t reserved_04 : 3; /* DP_mux_p3_fifo_ctrl_TYPE[06:04] - RSVD */ 5569 uint32_t reserved_07 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[07] - RSVD */ 5570 uint32_t reserved_08 : 6; /* DP_mux_p3_fifo_ctrl_TYPE[13:08] - RSVD */ 5571 uint32_t reserved_14 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[14] - RSVD */ 5572 uint32_t reserved_15 : 1; /* DP_mux_p3_fifo_ctrl_TYPE[15] - RSVD */ 5573 uint32_t reserved : 16; 5574 #endif /* IS_LITTLE_ENDIAN */ 5575 } fields; 5576 } DP_mux_p3_fifo_ctrl_TYPE; 5577 5578 typedef DP_mux_p3_fifo_ctrl_TYPE DP_MUX_P3_FIFO_CTRL_TYPE_T; 5579 5580 typedef union { 5581 uint32_t data; 5582 struct { 5583 #if IS_BIG_ENDIAN 5584 uint32_t reserved : 16; 5585 uint32_t reserved_15 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[15] - RSVD */ 5586 uint32_t reserved_14 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[14] - RSVD */ 5587 uint32_t reserved_08 : 6; /* DP_mux_p4_fifo_ctrl_TYPE[13:08] - RSVD */ 5588 uint32_t reserved_07 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[07] - RSVD */ 5589 uint32_t reserved_04 : 3; /* DP_mux_p4_fifo_ctrl_TYPE[06:04] - RSVD */ 5590 uint32_t reserved_03 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[03] - RSVD */ 5591 uint32_t mux_p4_edet : 1; /* DP_mux_p4_fifo_ctrl_TYPE[02] - WO */ 5592 uint32_t mux_p4_perf : 2; /* DP_mux_p4_fifo_ctrl_TYPE[01:00] - WO */ 5593 #endif /* IS_BIG_ENDIAN */ 5594 #if IS_LITTLE_ENDIAN 5595 uint32_t mux_p4_perf : 2; /* DP_mux_p4_fifo_ctrl_TYPE[01:00] - WO */ 5596 uint32_t mux_p4_edet : 1; /* DP_mux_p4_fifo_ctrl_TYPE[02] - WO */ 5597 uint32_t reserved_03 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[03] - RSVD */ 5598 uint32_t reserved_04 : 3; /* DP_mux_p4_fifo_ctrl_TYPE[06:04] - RSVD */ 5599 uint32_t reserved_07 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[07] - RSVD */ 5600 uint32_t reserved_08 : 6; /* DP_mux_p4_fifo_ctrl_TYPE[13:08] - RSVD */ 5601 uint32_t reserved_14 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[14] - RSVD */ 5602 uint32_t reserved_15 : 1; /* DP_mux_p4_fifo_ctrl_TYPE[15] - RSVD */ 5603 uint32_t reserved : 16; 5604 #endif /* IS_LITTLE_ENDIAN */ 5605 } fields; 5606 } DP_mux_p4_fifo_ctrl_TYPE; 5607 5608 typedef DP_mux_p4_fifo_ctrl_TYPE DP_MUX_P4_FIFO_CTRL_TYPE_T; 5609 5610 typedef union { 5611 uint32_t data; 5612 struct { 5613 #if IS_BIG_ENDIAN 5614 uint32_t reserved : 16; 5615 uint32_t reserved_15 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[15] - RSVD */ 5616 uint32_t reserved_14 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[14] - RSVD */ 5617 uint32_t reserved_08 : 6; /* DP_mux_p5_fifo_ctrl_TYPE[13:08] - RSVD */ 5618 uint32_t reserved_07 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[07] - RSVD */ 5619 uint32_t reserved_04 : 3; /* DP_mux_p5_fifo_ctrl_TYPE[06:04] - RSVD */ 5620 uint32_t reserved_03 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[03] - RSVD */ 5621 uint32_t mux_p5_edet : 1; /* DP_mux_p5_fifo_ctrl_TYPE[02] - WO */ 5622 uint32_t mux_p5_perf : 2; /* DP_mux_p5_fifo_ctrl_TYPE[01:00] - WO */ 5623 #endif /* IS_BIG_ENDIAN */ 5624 #if IS_LITTLE_ENDIAN 5625 uint32_t mux_p5_perf : 2; /* DP_mux_p5_fifo_ctrl_TYPE[01:00] - WO */ 5626 uint32_t mux_p5_edet : 1; /* DP_mux_p5_fifo_ctrl_TYPE[02] - WO */ 5627 uint32_t reserved_03 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[03] - RSVD */ 5628 uint32_t reserved_04 : 3; /* DP_mux_p5_fifo_ctrl_TYPE[06:04] - RSVD */ 5629 uint32_t reserved_07 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[07] - RSVD */ 5630 uint32_t reserved_08 : 6; /* DP_mux_p5_fifo_ctrl_TYPE[13:08] - RSVD */ 5631 uint32_t reserved_14 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[14] - RSVD */ 5632 uint32_t reserved_15 : 1; /* DP_mux_p5_fifo_ctrl_TYPE[15] - RSVD */ 5633 uint32_t reserved : 16; 5634 #endif /* IS_LITTLE_ENDIAN */ 5635 } fields; 5636 } DP_mux_p5_fifo_ctrl_TYPE; 5637 5638 typedef DP_mux_p5_fifo_ctrl_TYPE DP_MUX_P5_FIFO_CTRL_TYPE_T; 5639 5640 typedef union { 5641 uint32_t data; 5642 struct { 5643 #if IS_BIG_ENDIAN 5644 uint32_t reserved : 16; 5645 uint32_t reserved_15 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[15] - RSVD */ 5646 uint32_t reserved_14 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[14] - RSVD */ 5647 uint32_t reserved_08 : 6; /* DP_mux_p6_fifo_ctrl_TYPE[13:08] - RSVD */ 5648 uint32_t reserved_07 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[07] - RSVD */ 5649 uint32_t reserved_04 : 3; /* DP_mux_p6_fifo_ctrl_TYPE[06:04] - RSVD */ 5650 uint32_t reserved_03 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[03] - RSVD */ 5651 uint32_t mux_p6_edet : 1; /* DP_mux_p6_fifo_ctrl_TYPE[02] - WO */ 5652 uint32_t mux_p6_perf : 2; /* DP_mux_p6_fifo_ctrl_TYPE[01:00] - WO */ 5653 #endif /* IS_BIG_ENDIAN */ 5654 #if IS_LITTLE_ENDIAN 5655 uint32_t mux_p6_perf : 2; /* DP_mux_p6_fifo_ctrl_TYPE[01:00] - WO */ 5656 uint32_t mux_p6_edet : 1; /* DP_mux_p6_fifo_ctrl_TYPE[02] - WO */ 5657 uint32_t reserved_03 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[03] - RSVD */ 5658 uint32_t reserved_04 : 3; /* DP_mux_p6_fifo_ctrl_TYPE[06:04] - RSVD */ 5659 uint32_t reserved_07 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[07] - RSVD */ 5660 uint32_t reserved_08 : 6; /* DP_mux_p6_fifo_ctrl_TYPE[13:08] - RSVD */ 5661 uint32_t reserved_14 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[14] - RSVD */ 5662 uint32_t reserved_15 : 1; /* DP_mux_p6_fifo_ctrl_TYPE[15] - RSVD */ 5663 uint32_t reserved : 16; 5664 #endif /* IS_LITTLE_ENDIAN */ 5665 } fields; 5666 } DP_mux_p6_fifo_ctrl_TYPE; 5667 5668 typedef DP_mux_p6_fifo_ctrl_TYPE DP_MUX_P6_FIFO_CTRL_TYPE_T; 5669 5670 typedef union { 5671 uint32_t data; 5672 struct { 5673 #if IS_BIG_ENDIAN 5674 uint32_t reserved : 16; 5675 uint32_t reserved_15 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[15] - RSVD */ 5676 uint32_t reserved_14 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[14] - RSVD */ 5677 uint32_t reserved_08 : 6; /* DP_mux_p7_fifo_ctrl_TYPE[13:08] - RSVD */ 5678 uint32_t reserved_07 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[07] - RSVD */ 5679 uint32_t reserved_04 : 3; /* DP_mux_p7_fifo_ctrl_TYPE[06:04] - RSVD */ 5680 uint32_t reserved_03 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[03] - RSVD */ 5681 uint32_t mux_p7_edet : 1; /* DP_mux_p7_fifo_ctrl_TYPE[02] - WO */ 5682 uint32_t mux_p7_perf : 2; /* DP_mux_p7_fifo_ctrl_TYPE[01:00] - WO */ 5683 #endif /* IS_BIG_ENDIAN */ 5684 #if IS_LITTLE_ENDIAN 5685 uint32_t mux_p7_perf : 2; /* DP_mux_p7_fifo_ctrl_TYPE[01:00] - WO */ 5686 uint32_t mux_p7_edet : 1; /* DP_mux_p7_fifo_ctrl_TYPE[02] - WO */ 5687 uint32_t reserved_03 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[03] - RSVD */ 5688 uint32_t reserved_04 : 3; /* DP_mux_p7_fifo_ctrl_TYPE[06:04] - RSVD */ 5689 uint32_t reserved_07 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[07] - RSVD */ 5690 uint32_t reserved_08 : 6; /* DP_mux_p7_fifo_ctrl_TYPE[13:08] - RSVD */ 5691 uint32_t reserved_14 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[14] - RSVD */ 5692 uint32_t reserved_15 : 1; /* DP_mux_p7_fifo_ctrl_TYPE[15] - RSVD */ 5693 uint32_t reserved : 16; 5694 #endif /* IS_LITTLE_ENDIAN */ 5695 } fields; 5696 } DP_mux_p7_fifo_ctrl_TYPE; 5697 5698 typedef DP_mux_p7_fifo_ctrl_TYPE DP_MUX_P7_FIFO_CTRL_TYPE_T; 5699 5700 typedef union { 5701 uint32_t data; 5702 struct { 5703 #if IS_BIG_ENDIAN 5704 uint32_t reserved : 16; 5705 uint32_t reserved_15 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[15] - RSVD */ 5706 uint32_t reserved_14 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[14] - RSVD */ 5707 uint32_t reserved_08 : 6; /* DP_mux_p8_fifo_ctrl_TYPE[13:08] - RSVD */ 5708 uint32_t reserved_07 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[07] - RSVD */ 5709 uint32_t reserved_04 : 3; /* DP_mux_p8_fifo_ctrl_TYPE[06:04] - RSVD */ 5710 uint32_t reserved_03 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[03] - RSVD */ 5711 uint32_t mux_p8_edet : 1; /* DP_mux_p8_fifo_ctrl_TYPE[02] - WO */ 5712 uint32_t mux_p8_perf : 2; /* DP_mux_p8_fifo_ctrl_TYPE[01:00] - WO */ 5713 #endif /* IS_BIG_ENDIAN */ 5714 #if IS_LITTLE_ENDIAN 5715 uint32_t mux_p8_perf : 2; /* DP_mux_p8_fifo_ctrl_TYPE[01:00] - WO */ 5716 uint32_t mux_p8_edet : 1; /* DP_mux_p8_fifo_ctrl_TYPE[02] - WO */ 5717 uint32_t reserved_03 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[03] - RSVD */ 5718 uint32_t reserved_04 : 3; /* DP_mux_p8_fifo_ctrl_TYPE[06:04] - RSVD */ 5719 uint32_t reserved_07 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[07] - RSVD */ 5720 uint32_t reserved_08 : 6; /* DP_mux_p8_fifo_ctrl_TYPE[13:08] - RSVD */ 5721 uint32_t reserved_14 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[14] - RSVD */ 5722 uint32_t reserved_15 : 1; /* DP_mux_p8_fifo_ctrl_TYPE[15] - RSVD */ 5723 uint32_t reserved : 16; 5724 #endif /* IS_LITTLE_ENDIAN */ 5725 } fields; 5726 } DP_mux_p8_fifo_ctrl_TYPE; 5727 5728 typedef DP_mux_p8_fifo_ctrl_TYPE DP_MUX_P8_FIFO_CTRL_TYPE_T; 5729 5730 typedef union { 5731 uint32_t data; 5732 struct { 5733 #if IS_BIG_ENDIAN 5734 uint32_t reserved : 16; 5735 uint32_t reserved_15 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[15] - RSVD */ 5736 uint32_t reserved_14 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[14] - RSVD */ 5737 uint32_t reserved_08 : 6; /* DP_mux_p9_fifo_ctrl_TYPE[13:08] - RSVD */ 5738 uint32_t reserved_07 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[07] - RSVD */ 5739 uint32_t reserved_04 : 3; /* DP_mux_p9_fifo_ctrl_TYPE[06:04] - RSVD */ 5740 uint32_t reserved_03 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[03] - RSVD */ 5741 uint32_t mux_p9_edet : 1; /* DP_mux_p9_fifo_ctrl_TYPE[02] - WO */ 5742 uint32_t mux_p9_perf : 2; /* DP_mux_p9_fifo_ctrl_TYPE[01:00] - WO */ 5743 #endif /* IS_BIG_ENDIAN */ 5744 #if IS_LITTLE_ENDIAN 5745 uint32_t mux_p9_perf : 2; /* DP_mux_p9_fifo_ctrl_TYPE[01:00] - WO */ 5746 uint32_t mux_p9_edet : 1; /* DP_mux_p9_fifo_ctrl_TYPE[02] - WO */ 5747 uint32_t reserved_03 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[03] - RSVD */ 5748 uint32_t reserved_04 : 3; /* DP_mux_p9_fifo_ctrl_TYPE[06:04] - RSVD */ 5749 uint32_t reserved_07 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[07] - RSVD */ 5750 uint32_t reserved_08 : 6; /* DP_mux_p9_fifo_ctrl_TYPE[13:08] - RSVD */ 5751 uint32_t reserved_14 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[14] - RSVD */ 5752 uint32_t reserved_15 : 1; /* DP_mux_p9_fifo_ctrl_TYPE[15] - RSVD */ 5753 uint32_t reserved : 16; 5754 #endif /* IS_LITTLE_ENDIAN */ 5755 } fields; 5756 } DP_mux_p9_fifo_ctrl_TYPE; 5757 5758 typedef DP_mux_p9_fifo_ctrl_TYPE DP_MUX_P9_FIFO_CTRL_TYPE_T; 5759 5760 typedef union { 5761 uint32_t data; 5762 struct { 5763 #if IS_BIG_ENDIAN 5764 uint32_t reserved : 16; 5765 uint32_t reserved_01 : 15; /* DP_common_fifo_ctrl_TYPE[15:01] - RSVD */ 5766 uint32_t rst_on_ferr : 1; /* DP_common_fifo_ctrl_TYPE[00] - WO */ 5767 #endif /* IS_BIG_ENDIAN */ 5768 #if IS_LITTLE_ENDIAN 5769 uint32_t rst_on_ferr : 1; /* DP_common_fifo_ctrl_TYPE[00] - WO */ 5770 uint32_t reserved_01 : 15; /* DP_common_fifo_ctrl_TYPE[15:01] - RSVD */ 5771 uint32_t reserved : 16; 5772 #endif /* IS_LITTLE_ENDIAN */ 5773 } fields; 5774 } DP_common_fifo_ctrl_TYPE; 5775 5776 typedef DP_common_fifo_ctrl_TYPE DP_COMMON_FIFO_CTRL_TYPE_T; 5777 5778 typedef union { 5779 uint32_t data; 5780 struct { 5781 #if IS_BIG_ENDIAN 5782 uint32_t reserved : 16; 5783 uint32_t reserved_10 : 6; /* DP_mux_ferr_lh_TYPE[15:10] - RSVD */ 5784 uint32_t mux_p9_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[09] - RO */ 5785 uint32_t mux_p8_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[08] - RO */ 5786 uint32_t mux_p7_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[07] - RO */ 5787 uint32_t mux_p6_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[06] - RO */ 5788 uint32_t mux_p5_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[05] - RO */ 5789 uint32_t mux_p4_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[04] - RO */ 5790 uint32_t mux_p3_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[03] - RO */ 5791 uint32_t mux_p2_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[02] - RO */ 5792 uint32_t mux_p1_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[01] - RO */ 5793 uint32_t mux_p0_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[00] - RO */ 5794 #endif /* IS_BIG_ENDIAN */ 5795 #if IS_LITTLE_ENDIAN 5796 uint32_t mux_p0_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[00] - RO */ 5797 uint32_t mux_p1_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[01] - RO */ 5798 uint32_t mux_p2_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[02] - RO */ 5799 uint32_t mux_p3_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[03] - RO */ 5800 uint32_t mux_p4_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[04] - RO */ 5801 uint32_t mux_p5_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[05] - RO */ 5802 uint32_t mux_p6_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[06] - RO */ 5803 uint32_t mux_p7_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[07] - RO */ 5804 uint32_t mux_p8_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[08] - RO */ 5805 uint32_t mux_p9_ferr_lh : 1; /* DP_mux_ferr_lh_TYPE[09] - RO */ 5806 uint32_t reserved_10 : 6; /* DP_mux_ferr_lh_TYPE[15:10] - RSVD */ 5807 uint32_t reserved : 16; 5808 #endif /* IS_LITTLE_ENDIAN */ 5809 } fields; 5810 } DP_mux_ferr_lh_TYPE; 5811 5812 typedef DP_mux_ferr_lh_TYPE DP_MUX_FERR_LH_TYPE_T; 5813 5814 typedef union { 5815 uint32_t data; 5816 struct { 5817 #if IS_BIG_ENDIAN 5818 uint32_t reserved : 16; 5819 uint32_t reserved_04 : 12; /* DP_demux_ferr_lh_TYPE[15:04] - RSVD */ 5820 uint32_t demux_p3_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[03] - RO */ 5821 uint32_t demux_p2_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[02] - RO */ 5822 uint32_t demux_p1_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[01] - RO */ 5823 uint32_t demux_p0_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[00] - RO */ 5824 #endif /* IS_BIG_ENDIAN */ 5825 #if IS_LITTLE_ENDIAN 5826 uint32_t demux_p0_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[00] - RO */ 5827 uint32_t demux_p1_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[01] - RO */ 5828 uint32_t demux_p2_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[02] - RO */ 5829 uint32_t demux_p3_ferr_lh : 1; /* DP_demux_ferr_lh_TYPE[03] - RO */ 5830 uint32_t reserved_04 : 12; /* DP_demux_ferr_lh_TYPE[15:04] - RSVD */ 5831 uint32_t reserved : 16; 5832 #endif /* IS_LITTLE_ENDIAN */ 5833 } fields; 5834 } DP_demux_ferr_lh_TYPE; 5835 5836 typedef DP_demux_ferr_lh_TYPE DP_DEMUX_FERR_LH_TYPE_T; 5837 5838 typedef union { 5839 uint32_t data; 5840 struct { 5841 #if IS_BIG_ENDIAN 5842 uint32_t reserved : 16; 5843 uint32_t reserved_04 : 12; /* DP_mux_fec_rc_ferr_lh_TYPE[15:04] - RSVD */ 5844 uint32_t mux_fec_rc_ferr_lh_3 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[03] - RO */ 5845 uint32_t mux_fec_rc_ferr_lh_2 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[02] - RO */ 5846 uint32_t mux_fec_rc_ferr_lh_1 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[01] - RO */ 5847 uint32_t mux_fec_rc_ferr_lh_0 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[00] - RO */ 5848 #endif /* IS_BIG_ENDIAN */ 5849 #if IS_LITTLE_ENDIAN 5850 uint32_t mux_fec_rc_ferr_lh_0 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[00] - RO */ 5851 uint32_t mux_fec_rc_ferr_lh_1 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[01] - RO */ 5852 uint32_t mux_fec_rc_ferr_lh_2 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[02] - RO */ 5853 uint32_t mux_fec_rc_ferr_lh_3 : 1; /* DP_mux_fec_rc_ferr_lh_TYPE[03] - RO */ 5854 uint32_t reserved_04 : 12; /* DP_mux_fec_rc_ferr_lh_TYPE[15:04] - RSVD */ 5855 uint32_t reserved : 16; 5856 #endif /* IS_LITTLE_ENDIAN */ 5857 } fields; 5858 } DP_mux_fec_rc_ferr_lh_TYPE; 5859 5860 typedef DP_mux_fec_rc_ferr_lh_TYPE DP_MUX_FEC_RC_FERR_LH_TYPE_T; 5861 5862 typedef union { 5863 uint32_t data; 5864 struct { 5865 #if IS_BIG_ENDIAN 5866 uint32_t reserved : 16; 5867 uint32_t reserved_10 : 6; /* DP_demux_fec_rc_ferr_lh_TYPE[15:10] - RSVD */ 5868 uint32_t demux_fec_rc_ferr_lh_9 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[09] - RO */ 5869 uint32_t demux_fec_rc_ferr_lh_8 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[08] - RO */ 5870 uint32_t demux_fec_rc_ferr_lh_7 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[07] - RO */ 5871 uint32_t demux_fec_rc_ferr_lh_6 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[06] - RO */ 5872 uint32_t demux_fec_rc_ferr_lh_5 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[05] - RO */ 5873 uint32_t demux_fec_rc_ferr_lh_4 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[04] - RO */ 5874 uint32_t demux_fec_rc_ferr_lh_3 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[03] - RO */ 5875 uint32_t demux_fec_rc_ferr_lh_2 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[02] - RO */ 5876 uint32_t demux_fec_rc_ferr_lh_1 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[01] - RO */ 5877 uint32_t demux_fec_rc_ferr_lh_0 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[00] - RO */ 5878 #endif /* IS_BIG_ENDIAN */ 5879 #if IS_LITTLE_ENDIAN 5880 uint32_t demux_fec_rc_ferr_lh_0 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[00] - RO */ 5881 uint32_t demux_fec_rc_ferr_lh_1 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[01] - RO */ 5882 uint32_t demux_fec_rc_ferr_lh_2 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[02] - RO */ 5883 uint32_t demux_fec_rc_ferr_lh_3 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[03] - RO */ 5884 uint32_t demux_fec_rc_ferr_lh_4 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[04] - RO */ 5885 uint32_t demux_fec_rc_ferr_lh_5 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[05] - RO */ 5886 uint32_t demux_fec_rc_ferr_lh_6 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[06] - RO */ 5887 uint32_t demux_fec_rc_ferr_lh_7 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[07] - RO */ 5888 uint32_t demux_fec_rc_ferr_lh_8 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[08] - RO */ 5889 uint32_t demux_fec_rc_ferr_lh_9 : 1; /* DP_demux_fec_rc_ferr_lh_TYPE[09] - RO */ 5890 uint32_t reserved_10 : 6; /* DP_demux_fec_rc_ferr_lh_TYPE[15:10] - RSVD */ 5891 uint32_t reserved : 16; 5892 #endif /* IS_LITTLE_ENDIAN */ 5893 } fields; 5894 } DP_demux_fec_rc_ferr_lh_TYPE; 5895 5896 typedef DP_demux_fec_rc_ferr_lh_TYPE DP_DEMUX_FEC_RC_FERR_LH_TYPE_T; 5897 5898 typedef union { 5899 uint32_t data; 5900 struct { 5901 #if IS_BIG_ENDIAN 5902 uint32_t reserved : 16; 5903 uint32_t reserved_06 : 10; /* DP_mer_an_lane_select_TYPE[15:06] - RSVD */ 5904 uint32_t mer_an_lane_sel4to7 : 2; /* DP_mer_an_lane_select_TYPE[05:04] - WO */ 5905 uint32_t reserved_02 : 2; /* DP_mer_an_lane_select_TYPE[03:02] - RSVD */ 5906 uint32_t mer_an_lane_sel0to3 : 2; /* DP_mer_an_lane_select_TYPE[01:00] - WO */ 5907 #endif /* IS_BIG_ENDIAN */ 5908 #if IS_LITTLE_ENDIAN 5909 uint32_t mer_an_lane_sel0to3 : 2; /* DP_mer_an_lane_select_TYPE[01:00] - WO */ 5910 uint32_t reserved_02 : 2; /* DP_mer_an_lane_select_TYPE[03:02] - RSVD */ 5911 uint32_t mer_an_lane_sel4to7 : 2; /* DP_mer_an_lane_select_TYPE[05:04] - WO */ 5912 uint32_t reserved_06 : 10; /* DP_mer_an_lane_select_TYPE[15:06] - RSVD */ 5913 uint32_t reserved : 16; 5914 #endif /* IS_LITTLE_ENDIAN */ 5915 } fields; 5916 } DP_mer_an_lane_select_TYPE; 5917 5918 typedef DP_mer_an_lane_select_TYPE DP_MER_AN_LANE_SELECT_TYPE_T; 5919 5920 typedef union { 5921 uint32_t data; 5922 struct { 5923 #if IS_BIG_ENDIAN 5924 uint32_t reserved : 16; 5925 uint32_t reserved_02 : 14; /* DP_fal_an_lane_select_TYPE[15:02] - RSVD */ 5926 uint32_t fal_an_lane_sel0to3 : 2; /* DP_fal_an_lane_select_TYPE[01:00] - WO */ 5927 #endif /* IS_BIG_ENDIAN */ 5928 #if IS_LITTLE_ENDIAN 5929 uint32_t fal_an_lane_sel0to3 : 2; /* DP_fal_an_lane_select_TYPE[01:00] - WO */ 5930 uint32_t reserved_02 : 14; /* DP_fal_an_lane_select_TYPE[15:02] - RSVD */ 5931 uint32_t reserved : 16; 5932 #endif /* IS_LITTLE_ENDIAN */ 5933 } fields; 5934 } DP_fal_an_lane_select_TYPE; 5935 5936 typedef DP_fal_an_lane_select_TYPE DP_FAL_AN_LANE_SELECT_TYPE_T; 5937 5938 typedef union { 5939 uint32_t data; 5940 struct { 5941 #if IS_BIG_ENDIAN 5942 uint32_t reserved : 16; 5943 uint32_t fal_ln_h_rstb : 4; /* DP_fal_mer_line_side_reset_control1_TYPE[15:12] - WO */ 5944 uint32_t mgt_datapath_rstb : 1; /* DP_fal_mer_line_side_reset_control1_TYPE[11] - WO */ 5945 uint32_t reserved_10 : 1; /* DP_fal_mer_line_side_reset_control1_TYPE[10] - RSVD */ 5946 uint32_t mer_ln_h_rstb : 10; /* DP_fal_mer_line_side_reset_control1_TYPE[09:00] - WO */ 5947 #endif /* IS_BIG_ENDIAN */ 5948 #if IS_LITTLE_ENDIAN 5949 uint32_t mer_ln_h_rstb : 10; /* DP_fal_mer_line_side_reset_control1_TYPE[09:00] - WO */ 5950 uint32_t reserved_10 : 1; /* DP_fal_mer_line_side_reset_control1_TYPE[10] - RSVD */ 5951 uint32_t mgt_datapath_rstb : 1; /* DP_fal_mer_line_side_reset_control1_TYPE[11] - WO */ 5952 uint32_t fal_ln_h_rstb : 4; /* DP_fal_mer_line_side_reset_control1_TYPE[15:12] - WO */ 5953 uint32_t reserved : 16; 5954 #endif /* IS_LITTLE_ENDIAN */ 5955 } fields; 5956 } DP_fal_mer_line_side_reset_control1_TYPE; 5957 5958 typedef DP_fal_mer_line_side_reset_control1_TYPE DP_FAL_MER_LINE_SIDE_RESET_CONTROL1_TYPE_T; 5959 5960 typedef union { 5961 uint32_t data; 5962 struct { 5963 #if IS_BIG_ENDIAN 5964 uint32_t reserved : 16; 5965 uint32_t fmon0_main_ctrl : 14; /* DP_fmon0_main_control_TYPE[15:02] - WO */ 5966 uint32_t reserved_00 : 2; /* DP_fmon0_main_control_TYPE[01:00] - RSVD */ 5967 #endif /* IS_BIG_ENDIAN */ 5968 #if IS_LITTLE_ENDIAN 5969 uint32_t reserved_00 : 2; /* DP_fmon0_main_control_TYPE[01:00] - RSVD */ 5970 uint32_t fmon0_main_ctrl : 14; /* DP_fmon0_main_control_TYPE[15:02] - WO */ 5971 uint32_t reserved : 16; 5972 #endif /* IS_LITTLE_ENDIAN */ 5973 } fields; 5974 } DP_fmon0_main_control_TYPE; 5975 5976 typedef DP_fmon0_main_control_TYPE DP_FMON0_MAIN_CONTROL_TYPE_T; 5977 5978 typedef union { 5979 uint32_t data; 5980 struct { 5981 #if IS_BIG_ENDIAN 5982 uint32_t reserved : 16; 5983 uint32_t fmon1_main_ctrl : 14; /* DP_fmon1_main_control_TYPE[15:02] - WO */ 5984 uint32_t reserved_00 : 2; /* DP_fmon1_main_control_TYPE[01:00] - RSVD */ 5985 #endif /* IS_BIG_ENDIAN */ 5986 #if IS_LITTLE_ENDIAN 5987 uint32_t reserved_00 : 2; /* DP_fmon1_main_control_TYPE[01:00] - RSVD */ 5988 uint32_t fmon1_main_ctrl : 14; /* DP_fmon1_main_control_TYPE[15:02] - WO */ 5989 uint32_t reserved : 16; 5990 #endif /* IS_LITTLE_ENDIAN */ 5991 } fields; 5992 } DP_fmon1_main_control_TYPE; 5993 5994 typedef DP_fmon1_main_control_TYPE DP_FMON1_MAIN_CONTROL_TYPE_T; 5995 5996 typedef union { 5997 uint32_t data; 5998 struct { 5999 #if IS_BIG_ENDIAN 6000 uint32_t reserved : 16; 6001 uint32_t fmon2_main_ctrl : 14; /* DP_fmon2_main_control_TYPE[15:02] - WO */ 6002 uint32_t reserved_00 : 2; /* DP_fmon2_main_control_TYPE[01:00] - RSVD */ 6003 #endif /* IS_BIG_ENDIAN */ 6004 #if IS_LITTLE_ENDIAN 6005 uint32_t reserved_00 : 2; /* DP_fmon2_main_control_TYPE[01:00] - RSVD */ 6006 uint32_t fmon2_main_ctrl : 14; /* DP_fmon2_main_control_TYPE[15:02] - WO */ 6007 uint32_t reserved : 16; 6008 #endif /* IS_LITTLE_ENDIAN */ 6009 } fields; 6010 } DP_fmon2_main_control_TYPE; 6011 6012 typedef DP_fmon2_main_control_TYPE DP_FMON2_MAIN_CONTROL_TYPE_T; 6013 6014 typedef union { 6015 uint32_t data; 6016 struct { 6017 #if IS_BIG_ENDIAN 6018 uint32_t reserved : 16; 6019 uint32_t fmon3_main_ctrl : 14; /* DP_fmon3_main_control_TYPE[15:02] - WO */ 6020 uint32_t reserved_00 : 2; /* DP_fmon3_main_control_TYPE[01:00] - RSVD */ 6021 #endif /* IS_BIG_ENDIAN */ 6022 #if IS_LITTLE_ENDIAN 6023 uint32_t reserved_00 : 2; /* DP_fmon3_main_control_TYPE[01:00] - RSVD */ 6024 uint32_t fmon3_main_ctrl : 14; /* DP_fmon3_main_control_TYPE[15:02] - WO */ 6025 uint32_t reserved : 16; 6026 #endif /* IS_LITTLE_ENDIAN */ 6027 } fields; 6028 } DP_fmon3_main_control_TYPE; 6029 6030 typedef DP_fmon3_main_control_TYPE DP_FMON3_MAIN_CONTROL_TYPE_T; 6031 6032 typedef union { 6033 uint32_t data; 6034 struct { 6035 #if IS_BIG_ENDIAN 6036 uint32_t reserved : 16; 6037 uint32_t mmon0_main_ctrl : 14; /* DP_mmon0_main_control_TYPE[15:02] - WO */ 6038 uint32_t reserved_00 : 2; /* DP_mmon0_main_control_TYPE[01:00] - RSVD */ 6039 #endif /* IS_BIG_ENDIAN */ 6040 #if IS_LITTLE_ENDIAN 6041 uint32_t reserved_00 : 2; /* DP_mmon0_main_control_TYPE[01:00] - RSVD */ 6042 uint32_t mmon0_main_ctrl : 14; /* DP_mmon0_main_control_TYPE[15:02] - WO */ 6043 uint32_t reserved : 16; 6044 #endif /* IS_LITTLE_ENDIAN */ 6045 } fields; 6046 } DP_mmon0_main_control_TYPE; 6047 6048 typedef DP_mmon0_main_control_TYPE DP_MMON0_MAIN_CONTROL_TYPE_T; 6049 6050 typedef union { 6051 uint32_t data; 6052 struct { 6053 #if IS_BIG_ENDIAN 6054 uint32_t reserved : 16; 6055 uint32_t mmon1_main_ctrl : 14; /* DP_mmon1_main_control_TYPE[15:02] - WO */ 6056 uint32_t reserved_00 : 2; /* DP_mmon1_main_control_TYPE[01:00] - RSVD */ 6057 #endif /* IS_BIG_ENDIAN */ 6058 #if IS_LITTLE_ENDIAN 6059 uint32_t reserved_00 : 2; /* DP_mmon1_main_control_TYPE[01:00] - RSVD */ 6060 uint32_t mmon1_main_ctrl : 14; /* DP_mmon1_main_control_TYPE[15:02] - WO */ 6061 uint32_t reserved : 16; 6062 #endif /* IS_LITTLE_ENDIAN */ 6063 } fields; 6064 } DP_mmon1_main_control_TYPE; 6065 6066 typedef DP_mmon1_main_control_TYPE DP_MMON1_MAIN_CONTROL_TYPE_T; 6067 6068 typedef union { 6069 uint32_t data; 6070 struct { 6071 #if IS_BIG_ENDIAN 6072 uint32_t reserved : 16; 6073 uint32_t mmon2_main_ctrl : 14; /* DP_mmon2_main_control_TYPE[15:02] - WO */ 6074 uint32_t reserved_00 : 2; /* DP_mmon2_main_control_TYPE[01:00] - RSVD */ 6075 #endif /* IS_BIG_ENDIAN */ 6076 #if IS_LITTLE_ENDIAN 6077 uint32_t reserved_00 : 2; /* DP_mmon2_main_control_TYPE[01:00] - RSVD */ 6078 uint32_t mmon2_main_ctrl : 14; /* DP_mmon2_main_control_TYPE[15:02] - WO */ 6079 uint32_t reserved : 16; 6080 #endif /* IS_LITTLE_ENDIAN */ 6081 } fields; 6082 } DP_mmon2_main_control_TYPE; 6083 6084 typedef DP_mmon2_main_control_TYPE DP_MMON2_MAIN_CONTROL_TYPE_T; 6085 6086 typedef union { 6087 uint32_t data; 6088 struct { 6089 #if IS_BIG_ENDIAN 6090 uint32_t reserved : 16; 6091 uint32_t mmon3_main_ctrl : 14; /* DP_mmon3_main_control_TYPE[15:02] - WO */ 6092 uint32_t reserved_00 : 2; /* DP_mmon3_main_control_TYPE[01:00] - RSVD */ 6093 #endif /* IS_BIG_ENDIAN */ 6094 #if IS_LITTLE_ENDIAN 6095 uint32_t reserved_00 : 2; /* DP_mmon3_main_control_TYPE[01:00] - RSVD */ 6096 uint32_t mmon3_main_ctrl : 14; /* DP_mmon3_main_control_TYPE[15:02] - WO */ 6097 uint32_t reserved : 16; 6098 #endif /* IS_LITTLE_ENDIAN */ 6099 } fields; 6100 } DP_mmon3_main_control_TYPE; 6101 6102 typedef DP_mmon3_main_control_TYPE DP_MMON3_MAIN_CONTROL_TYPE_T; 6103 6104 typedef union { 6105 uint32_t data; 6106 struct { 6107 #if IS_BIG_ENDIAN 6108 uint32_t reserved : 16; 6109 uint32_t mmon4_main_ctrl : 14; /* DP_mmon4_main_control_TYPE[15:02] - WO */ 6110 uint32_t reserved_00 : 2; /* DP_mmon4_main_control_TYPE[01:00] - RSVD */ 6111 #endif /* IS_BIG_ENDIAN */ 6112 #if IS_LITTLE_ENDIAN 6113 uint32_t reserved_00 : 2; /* DP_mmon4_main_control_TYPE[01:00] - RSVD */ 6114 uint32_t mmon4_main_ctrl : 14; /* DP_mmon4_main_control_TYPE[15:02] - WO */ 6115 uint32_t reserved : 16; 6116 #endif /* IS_LITTLE_ENDIAN */ 6117 } fields; 6118 } DP_mmon4_main_control_TYPE; 6119 6120 typedef DP_mmon4_main_control_TYPE DP_MMON4_MAIN_CONTROL_TYPE_T; 6121 6122 typedef union { 6123 uint32_t data; 6124 struct { 6125 #if IS_BIG_ENDIAN 6126 uint32_t reserved : 16; 6127 uint32_t mmon5_main_ctrl : 14; /* DP_mmon5_main_control_TYPE[15:02] - WO */ 6128 uint32_t reserved_00 : 2; /* DP_mmon5_main_control_TYPE[01:00] - RSVD */ 6129 #endif /* IS_BIG_ENDIAN */ 6130 #if IS_LITTLE_ENDIAN 6131 uint32_t reserved_00 : 2; /* DP_mmon5_main_control_TYPE[01:00] - RSVD */ 6132 uint32_t mmon5_main_ctrl : 14; /* DP_mmon5_main_control_TYPE[15:02] - WO */ 6133 uint32_t reserved : 16; 6134 #endif /* IS_LITTLE_ENDIAN */ 6135 } fields; 6136 } DP_mmon5_main_control_TYPE; 6137 6138 typedef DP_mmon5_main_control_TYPE DP_MMON5_MAIN_CONTROL_TYPE_T; 6139 6140 typedef union { 6141 uint32_t data; 6142 struct { 6143 #if IS_BIG_ENDIAN 6144 uint32_t reserved : 16; 6145 uint32_t mmon6_main_ctrl : 14; /* DP_mmon6_main_control_TYPE[15:02] - WO */ 6146 uint32_t reserved_00 : 2; /* DP_mmon6_main_control_TYPE[01:00] - RSVD */ 6147 #endif /* IS_BIG_ENDIAN */ 6148 #if IS_LITTLE_ENDIAN 6149 uint32_t reserved_00 : 2; /* DP_mmon6_main_control_TYPE[01:00] - RSVD */ 6150 uint32_t mmon6_main_ctrl : 14; /* DP_mmon6_main_control_TYPE[15:02] - WO */ 6151 uint32_t reserved : 16; 6152 #endif /* IS_LITTLE_ENDIAN */ 6153 } fields; 6154 } DP_mmon6_main_control_TYPE; 6155 6156 typedef DP_mmon6_main_control_TYPE DP_MMON6_MAIN_CONTROL_TYPE_T; 6157 6158 typedef union { 6159 uint32_t data; 6160 struct { 6161 #if IS_BIG_ENDIAN 6162 uint32_t reserved : 16; 6163 uint32_t mmon7_main_ctrl : 14; /* DP_mmon7_main_control_TYPE[15:02] - WO */ 6164 uint32_t reserved_00 : 2; /* DP_mmon7_main_control_TYPE[01:00] - RSVD */ 6165 #endif /* IS_BIG_ENDIAN */ 6166 #if IS_LITTLE_ENDIAN 6167 uint32_t reserved_00 : 2; /* DP_mmon7_main_control_TYPE[01:00] - RSVD */ 6168 uint32_t mmon7_main_ctrl : 14; /* DP_mmon7_main_control_TYPE[15:02] - WO */ 6169 uint32_t reserved : 16; 6170 #endif /* IS_LITTLE_ENDIAN */ 6171 } fields; 6172 } DP_mmon7_main_control_TYPE; 6173 6174 typedef DP_mmon7_main_control_TYPE DP_MMON7_MAIN_CONTROL_TYPE_T; 6175 6176 typedef union { 6177 uint32_t data; 6178 struct { 6179 #if IS_BIG_ENDIAN 6180 uint32_t reserved : 16; 6181 uint32_t mmon8_main_ctrl : 14; /* DP_mmon8_main_control_TYPE[15:02] - WO */ 6182 uint32_t reserved_00 : 2; /* DP_mmon8_main_control_TYPE[01:00] - RSVD */ 6183 #endif /* IS_BIG_ENDIAN */ 6184 #if IS_LITTLE_ENDIAN 6185 uint32_t reserved_00 : 2; /* DP_mmon8_main_control_TYPE[01:00] - RSVD */ 6186 uint32_t mmon8_main_ctrl : 14; /* DP_mmon8_main_control_TYPE[15:02] - WO */ 6187 uint32_t reserved : 16; 6188 #endif /* IS_LITTLE_ENDIAN */ 6189 } fields; 6190 } DP_mmon8_main_control_TYPE; 6191 6192 typedef DP_mmon8_main_control_TYPE DP_MMON8_MAIN_CONTROL_TYPE_T; 6193 6194 typedef union { 6195 uint32_t data; 6196 struct { 6197 #if IS_BIG_ENDIAN 6198 uint32_t reserved : 16; 6199 uint32_t mmon9_main_ctrl : 14; /* DP_mmon9_main_control_TYPE[15:02] - WO */ 6200 uint32_t reserved_00 : 2; /* DP_mmon9_main_control_TYPE[01:00] - RSVD */ 6201 #endif /* IS_BIG_ENDIAN */ 6202 #if IS_LITTLE_ENDIAN 6203 uint32_t reserved_00 : 2; /* DP_mmon9_main_control_TYPE[01:00] - RSVD */ 6204 uint32_t mmon9_main_ctrl : 14; /* DP_mmon9_main_control_TYPE[15:02] - WO */ 6205 uint32_t reserved : 16; 6206 #endif /* IS_LITTLE_ENDIAN */ 6207 } fields; 6208 } DP_mmon9_main_control_TYPE; 6209 6210 typedef DP_mmon9_main_control_TYPE DP_MMON9_MAIN_CONTROL_TYPE_T; 6211 6212 typedef union { 6213 uint32_t data; 6214 struct { 6215 #if IS_BIG_ENDIAN 6216 uint32_t reserved : 16; 6217 uint32_t fmon0_main_stat : 15; /* DP_fmon0_main_status_TYPE[15:01] - RO */ 6218 uint32_t reserved_00 : 1; /* DP_fmon0_main_status_TYPE[00] - RSVD */ 6219 #endif /* IS_BIG_ENDIAN */ 6220 #if IS_LITTLE_ENDIAN 6221 uint32_t reserved_00 : 1; /* DP_fmon0_main_status_TYPE[00] - RSVD */ 6222 uint32_t fmon0_main_stat : 15; /* DP_fmon0_main_status_TYPE[15:01] - RO */ 6223 uint32_t reserved : 16; 6224 #endif /* IS_LITTLE_ENDIAN */ 6225 } fields; 6226 } DP_fmon0_main_status_TYPE; 6227 6228 typedef DP_fmon0_main_status_TYPE DP_FMON0_MAIN_STATUS_TYPE_T; 6229 6230 typedef union { 6231 uint32_t data; 6232 struct { 6233 #if IS_BIG_ENDIAN 6234 uint32_t reserved : 16; 6235 uint32_t fmon1_main_stat : 15; /* DP_fmon1_main_status_TYPE[15:01] - RO */ 6236 uint32_t reserved_00 : 1; /* DP_fmon1_main_status_TYPE[00] - RSVD */ 6237 #endif /* IS_BIG_ENDIAN */ 6238 #if IS_LITTLE_ENDIAN 6239 uint32_t reserved_00 : 1; /* DP_fmon1_main_status_TYPE[00] - RSVD */ 6240 uint32_t fmon1_main_stat : 15; /* DP_fmon1_main_status_TYPE[15:01] - RO */ 6241 uint32_t reserved : 16; 6242 #endif /* IS_LITTLE_ENDIAN */ 6243 } fields; 6244 } DP_fmon1_main_status_TYPE; 6245 6246 typedef DP_fmon1_main_status_TYPE DP_FMON1_MAIN_STATUS_TYPE_T; 6247 6248 typedef union { 6249 uint32_t data; 6250 struct { 6251 #if IS_BIG_ENDIAN 6252 uint32_t reserved : 16; 6253 uint32_t fmon2_main_stat : 15; /* DP_fmon2_main_status_TYPE[15:01] - RO */ 6254 uint32_t reserved_00 : 1; /* DP_fmon2_main_status_TYPE[00] - RSVD */ 6255 #endif /* IS_BIG_ENDIAN */ 6256 #if IS_LITTLE_ENDIAN 6257 uint32_t reserved_00 : 1; /* DP_fmon2_main_status_TYPE[00] - RSVD */ 6258 uint32_t fmon2_main_stat : 15; /* DP_fmon2_main_status_TYPE[15:01] - RO */ 6259 uint32_t reserved : 16; 6260 #endif /* IS_LITTLE_ENDIAN */ 6261 } fields; 6262 } DP_fmon2_main_status_TYPE; 6263 6264 typedef DP_fmon2_main_status_TYPE DP_FMON2_MAIN_STATUS_TYPE_T; 6265 6266 typedef union { 6267 uint32_t data; 6268 struct { 6269 #if IS_BIG_ENDIAN 6270 uint32_t reserved : 16; 6271 uint32_t fmon3_main_stat : 15; /* DP_fmon3_main_status_TYPE[15:01] - RO */ 6272 uint32_t reserved_00 : 1; /* DP_fmon3_main_status_TYPE[00] - RSVD */ 6273 #endif /* IS_BIG_ENDIAN */ 6274 #if IS_LITTLE_ENDIAN 6275 uint32_t reserved_00 : 1; /* DP_fmon3_main_status_TYPE[00] - RSVD */ 6276 uint32_t fmon3_main_stat : 15; /* DP_fmon3_main_status_TYPE[15:01] - RO */ 6277 uint32_t reserved : 16; 6278 #endif /* IS_LITTLE_ENDIAN */ 6279 } fields; 6280 } DP_fmon3_main_status_TYPE; 6281 6282 typedef DP_fmon3_main_status_TYPE DP_FMON3_MAIN_STATUS_TYPE_T; 6283 6284 typedef union { 6285 uint32_t data; 6286 struct { 6287 #if IS_BIG_ENDIAN 6288 uint32_t reserved : 16; 6289 uint32_t mmon0_main_stat : 15; /* DP_mmon0_main_status_TYPE[15:01] - RO */ 6290 uint32_t reserved_00 : 1; /* DP_mmon0_main_status_TYPE[00] - RSVD */ 6291 #endif /* IS_BIG_ENDIAN */ 6292 #if IS_LITTLE_ENDIAN 6293 uint32_t reserved_00 : 1; /* DP_mmon0_main_status_TYPE[00] - RSVD */ 6294 uint32_t mmon0_main_stat : 15; /* DP_mmon0_main_status_TYPE[15:01] - RO */ 6295 uint32_t reserved : 16; 6296 #endif /* IS_LITTLE_ENDIAN */ 6297 } fields; 6298 } DP_mmon0_main_status_TYPE; 6299 6300 typedef DP_mmon0_main_status_TYPE DP_MMON0_MAIN_STATUS_TYPE_T; 6301 6302 typedef union { 6303 uint32_t data; 6304 struct { 6305 #if IS_BIG_ENDIAN 6306 uint32_t reserved : 16; 6307 uint32_t mmon1_main_stat : 15; /* DP_mmon1_main_status_TYPE[15:01] - RO */ 6308 uint32_t reserved_00 : 1; /* DP_mmon1_main_status_TYPE[00] - RSVD */ 6309 #endif /* IS_BIG_ENDIAN */ 6310 #if IS_LITTLE_ENDIAN 6311 uint32_t reserved_00 : 1; /* DP_mmon1_main_status_TYPE[00] - RSVD */ 6312 uint32_t mmon1_main_stat : 15; /* DP_mmon1_main_status_TYPE[15:01] - RO */ 6313 uint32_t reserved : 16; 6314 #endif /* IS_LITTLE_ENDIAN */ 6315 } fields; 6316 } DP_mmon1_main_status_TYPE; 6317 6318 typedef DP_mmon1_main_status_TYPE DP_MMON1_MAIN_STATUS_TYPE_T; 6319 6320 typedef union { 6321 uint32_t data; 6322 struct { 6323 #if IS_BIG_ENDIAN 6324 uint32_t reserved : 16; 6325 uint32_t mmon2_main_stat : 15; /* DP_mmon2_main_status_TYPE[15:01] - RO */ 6326 uint32_t reserved_00 : 1; /* DP_mmon2_main_status_TYPE[00] - RSVD */ 6327 #endif /* IS_BIG_ENDIAN */ 6328 #if IS_LITTLE_ENDIAN 6329 uint32_t reserved_00 : 1; /* DP_mmon2_main_status_TYPE[00] - RSVD */ 6330 uint32_t mmon2_main_stat : 15; /* DP_mmon2_main_status_TYPE[15:01] - RO */ 6331 uint32_t reserved : 16; 6332 #endif /* IS_LITTLE_ENDIAN */ 6333 } fields; 6334 } DP_mmon2_main_status_TYPE; 6335 6336 typedef DP_mmon2_main_status_TYPE DP_MMON2_MAIN_STATUS_TYPE_T; 6337 6338 typedef union { 6339 uint32_t data; 6340 struct { 6341 #if IS_BIG_ENDIAN 6342 uint32_t reserved : 16; 6343 uint32_t mmon3_main_stat : 15; /* DP_mmon3_main_status_TYPE[15:01] - RO */ 6344 uint32_t reserved_00 : 1; /* DP_mmon3_main_status_TYPE[00] - RSVD */ 6345 #endif /* IS_BIG_ENDIAN */ 6346 #if IS_LITTLE_ENDIAN 6347 uint32_t reserved_00 : 1; /* DP_mmon3_main_status_TYPE[00] - RSVD */ 6348 uint32_t mmon3_main_stat : 15; /* DP_mmon3_main_status_TYPE[15:01] - RO */ 6349 uint32_t reserved : 16; 6350 #endif /* IS_LITTLE_ENDIAN */ 6351 } fields; 6352 } DP_mmon3_main_status_TYPE; 6353 6354 typedef DP_mmon3_main_status_TYPE DP_MMON3_MAIN_STATUS_TYPE_T; 6355 6356 typedef union { 6357 uint32_t data; 6358 struct { 6359 #if IS_BIG_ENDIAN 6360 uint32_t reserved : 16; 6361 uint32_t mmon4_main_stat : 15; /* DP_mmon4_main_status_TYPE[15:01] - RO */ 6362 uint32_t reserved_00 : 1; /* DP_mmon4_main_status_TYPE[00] - RSVD */ 6363 #endif /* IS_BIG_ENDIAN */ 6364 #if IS_LITTLE_ENDIAN 6365 uint32_t reserved_00 : 1; /* DP_mmon4_main_status_TYPE[00] - RSVD */ 6366 uint32_t mmon4_main_stat : 15; /* DP_mmon4_main_status_TYPE[15:01] - RO */ 6367 uint32_t reserved : 16; 6368 #endif /* IS_LITTLE_ENDIAN */ 6369 } fields; 6370 } DP_mmon4_main_status_TYPE; 6371 6372 typedef DP_mmon4_main_status_TYPE DP_MMON4_MAIN_STATUS_TYPE_T; 6373 6374 typedef union { 6375 uint32_t data; 6376 struct { 6377 #if IS_BIG_ENDIAN 6378 uint32_t reserved : 16; 6379 uint32_t mmon5_main_stat : 15; /* DP_mmon5_main_status_TYPE[15:01] - RO */ 6380 uint32_t reserved_00 : 1; /* DP_mmon5_main_status_TYPE[00] - RSVD */ 6381 #endif /* IS_BIG_ENDIAN */ 6382 #if IS_LITTLE_ENDIAN 6383 uint32_t reserved_00 : 1; /* DP_mmon5_main_status_TYPE[00] - RSVD */ 6384 uint32_t mmon5_main_stat : 15; /* DP_mmon5_main_status_TYPE[15:01] - RO */ 6385 uint32_t reserved : 16; 6386 #endif /* IS_LITTLE_ENDIAN */ 6387 } fields; 6388 } DP_mmon5_main_status_TYPE; 6389 6390 typedef DP_mmon5_main_status_TYPE DP_MMON5_MAIN_STATUS_TYPE_T; 6391 6392 typedef union { 6393 uint32_t data; 6394 struct { 6395 #if IS_BIG_ENDIAN 6396 uint32_t reserved : 16; 6397 uint32_t mmon6_main_stat : 15; /* DP_mmon6_main_status_TYPE[15:01] - RO */ 6398 uint32_t reserved_00 : 1; /* DP_mmon6_main_status_TYPE[00] - RSVD */ 6399 #endif /* IS_BIG_ENDIAN */ 6400 #if IS_LITTLE_ENDIAN 6401 uint32_t reserved_00 : 1; /* DP_mmon6_main_status_TYPE[00] - RSVD */ 6402 uint32_t mmon6_main_stat : 15; /* DP_mmon6_main_status_TYPE[15:01] - RO */ 6403 uint32_t reserved : 16; 6404 #endif /* IS_LITTLE_ENDIAN */ 6405 } fields; 6406 } DP_mmon6_main_status_TYPE; 6407 6408 typedef DP_mmon6_main_status_TYPE DP_MMON6_MAIN_STATUS_TYPE_T; 6409 6410 typedef union { 6411 uint32_t data; 6412 struct { 6413 #if IS_BIG_ENDIAN 6414 uint32_t reserved : 16; 6415 uint32_t mmon7_main_stat : 15; /* DP_mmon7_main_status_TYPE[15:01] - RO */ 6416 uint32_t reserved_00 : 1; /* DP_mmon7_main_status_TYPE[00] - RSVD */ 6417 #endif /* IS_BIG_ENDIAN */ 6418 #if IS_LITTLE_ENDIAN 6419 uint32_t reserved_00 : 1; /* DP_mmon7_main_status_TYPE[00] - RSVD */ 6420 uint32_t mmon7_main_stat : 15; /* DP_mmon7_main_status_TYPE[15:01] - RO */ 6421 uint32_t reserved : 16; 6422 #endif /* IS_LITTLE_ENDIAN */ 6423 } fields; 6424 } DP_mmon7_main_status_TYPE; 6425 6426 typedef DP_mmon7_main_status_TYPE DP_MMON7_MAIN_STATUS_TYPE_T; 6427 6428 typedef union { 6429 uint32_t data; 6430 struct { 6431 #if IS_BIG_ENDIAN 6432 uint32_t reserved : 16; 6433 uint32_t mmon8_main_stat : 15; /* DP_mmon8_main_status_TYPE[15:01] - RO */ 6434 uint32_t reserved_00 : 1; /* DP_mmon8_main_status_TYPE[00] - RSVD */ 6435 #endif /* IS_BIG_ENDIAN */ 6436 #if IS_LITTLE_ENDIAN 6437 uint32_t reserved_00 : 1; /* DP_mmon8_main_status_TYPE[00] - RSVD */ 6438 uint32_t mmon8_main_stat : 15; /* DP_mmon8_main_status_TYPE[15:01] - RO */ 6439 uint32_t reserved : 16; 6440 #endif /* IS_LITTLE_ENDIAN */ 6441 } fields; 6442 } DP_mmon8_main_status_TYPE; 6443 6444 typedef DP_mmon8_main_status_TYPE DP_MMON8_MAIN_STATUS_TYPE_T; 6445 6446 typedef union { 6447 uint32_t data; 6448 struct { 6449 #if IS_BIG_ENDIAN 6450 uint32_t reserved : 16; 6451 uint32_t mmon9_main_stat : 15; /* DP_mmon9_main_status_TYPE[15:01] - RO */ 6452 uint32_t reserved_00 : 1; /* DP_mmon9_main_status_TYPE[00] - RSVD */ 6453 #endif /* IS_BIG_ENDIAN */ 6454 #if IS_LITTLE_ENDIAN 6455 uint32_t reserved_00 : 1; /* DP_mmon9_main_status_TYPE[00] - RSVD */ 6456 uint32_t mmon9_main_stat : 15; /* DP_mmon9_main_status_TYPE[15:01] - RO */ 6457 uint32_t reserved : 16; 6458 #endif /* IS_LITTLE_ENDIAN */ 6459 } fields; 6460 } DP_mmon9_main_status_TYPE; 6461 6462 typedef DP_mmon9_main_status_TYPE DP_MMON9_MAIN_STATUS_TYPE_T; 6463 6464 typedef union { 6465 uint32_t data; 6466 struct { 6467 #if IS_BIG_ENDIAN 6468 uint32_t reserved : 16; 6469 uint32_t reserved_15 : 1; /* DP_fmon0_cl49_ber_status_TYPE[15] - RSVD */ 6470 uint32_t fmon0_cl49_ber_stat : 15; /* DP_fmon0_cl49_ber_status_TYPE[14:00] - RO */ 6471 #endif /* IS_BIG_ENDIAN */ 6472 #if IS_LITTLE_ENDIAN 6473 uint32_t fmon0_cl49_ber_stat : 15; /* DP_fmon0_cl49_ber_status_TYPE[14:00] - RO */ 6474 uint32_t reserved_15 : 1; /* DP_fmon0_cl49_ber_status_TYPE[15] - RSVD */ 6475 uint32_t reserved : 16; 6476 #endif /* IS_LITTLE_ENDIAN */ 6477 } fields; 6478 } DP_fmon0_cl49_ber_status_TYPE; 6479 6480 typedef DP_fmon0_cl49_ber_status_TYPE DP_FMON0_CL49_BER_STATUS_TYPE_T; 6481 6482 typedef union { 6483 uint32_t data; 6484 struct { 6485 #if IS_BIG_ENDIAN 6486 uint32_t reserved : 16; 6487 uint32_t reserved_15 : 1; /* DP_fmon1_cl49_ber_status_TYPE[15] - RSVD */ 6488 uint32_t fmon1_cl49_ber_stat : 15; /* DP_fmon1_cl49_ber_status_TYPE[14:00] - RO */ 6489 #endif /* IS_BIG_ENDIAN */ 6490 #if IS_LITTLE_ENDIAN 6491 uint32_t fmon1_cl49_ber_stat : 15; /* DP_fmon1_cl49_ber_status_TYPE[14:00] - RO */ 6492 uint32_t reserved_15 : 1; /* DP_fmon1_cl49_ber_status_TYPE[15] - RSVD */ 6493 uint32_t reserved : 16; 6494 #endif /* IS_LITTLE_ENDIAN */ 6495 } fields; 6496 } DP_fmon1_cl49_ber_status_TYPE; 6497 6498 typedef DP_fmon1_cl49_ber_status_TYPE DP_FMON1_CL49_BER_STATUS_TYPE_T; 6499 6500 typedef union { 6501 uint32_t data; 6502 struct { 6503 #if IS_BIG_ENDIAN 6504 uint32_t reserved : 16; 6505 uint32_t reserved_15 : 1; /* DP_fmon2_cl49_ber_status_TYPE[15] - RSVD */ 6506 uint32_t fmon2_cl49_ber_stat : 15; /* DP_fmon2_cl49_ber_status_TYPE[14:00] - RO */ 6507 #endif /* IS_BIG_ENDIAN */ 6508 #if IS_LITTLE_ENDIAN 6509 uint32_t fmon2_cl49_ber_stat : 15; /* DP_fmon2_cl49_ber_status_TYPE[14:00] - RO */ 6510 uint32_t reserved_15 : 1; /* DP_fmon2_cl49_ber_status_TYPE[15] - RSVD */ 6511 uint32_t reserved : 16; 6512 #endif /* IS_LITTLE_ENDIAN */ 6513 } fields; 6514 } DP_fmon2_cl49_ber_status_TYPE; 6515 6516 typedef DP_fmon2_cl49_ber_status_TYPE DP_FMON2_CL49_BER_STATUS_TYPE_T; 6517 6518 typedef union { 6519 uint32_t data; 6520 struct { 6521 #if IS_BIG_ENDIAN 6522 uint32_t reserved : 16; 6523 uint32_t reserved_15 : 1; /* DP_fmon3_cl49_ber_status_TYPE[15] - RSVD */ 6524 uint32_t fmon3_cl49_ber_stat : 15; /* DP_fmon3_cl49_ber_status_TYPE[14:00] - RO */ 6525 #endif /* IS_BIG_ENDIAN */ 6526 #if IS_LITTLE_ENDIAN 6527 uint32_t fmon3_cl49_ber_stat : 15; /* DP_fmon3_cl49_ber_status_TYPE[14:00] - RO */ 6528 uint32_t reserved_15 : 1; /* DP_fmon3_cl49_ber_status_TYPE[15] - RSVD */ 6529 uint32_t reserved : 16; 6530 #endif /* IS_LITTLE_ENDIAN */ 6531 } fields; 6532 } DP_fmon3_cl49_ber_status_TYPE; 6533 6534 typedef DP_fmon3_cl49_ber_status_TYPE DP_FMON3_CL49_BER_STATUS_TYPE_T; 6535 6536 typedef union { 6537 uint32_t data; 6538 struct { 6539 #if IS_BIG_ENDIAN 6540 uint32_t reserved : 16; 6541 uint32_t reserved_15 : 1; /* DP_mmon0_cl49_ber_status_TYPE[15] - RSVD */ 6542 uint32_t mmon0_cl49_ber_stat : 15; /* DP_mmon0_cl49_ber_status_TYPE[14:00] - RO */ 6543 #endif /* IS_BIG_ENDIAN */ 6544 #if IS_LITTLE_ENDIAN 6545 uint32_t mmon0_cl49_ber_stat : 15; /* DP_mmon0_cl49_ber_status_TYPE[14:00] - RO */ 6546 uint32_t reserved_15 : 1; /* DP_mmon0_cl49_ber_status_TYPE[15] - RSVD */ 6547 uint32_t reserved : 16; 6548 #endif /* IS_LITTLE_ENDIAN */ 6549 } fields; 6550 } DP_mmon0_cl49_ber_status_TYPE; 6551 6552 typedef DP_mmon0_cl49_ber_status_TYPE DP_MMON0_CL49_BER_STATUS_TYPE_T; 6553 6554 typedef union { 6555 uint32_t data; 6556 struct { 6557 #if IS_BIG_ENDIAN 6558 uint32_t reserved : 16; 6559 uint32_t reserved_15 : 1; /* DP_mmon1_cl49_ber_status_TYPE[15] - RSVD */ 6560 uint32_t mmon1_cl49_ber_stat : 15; /* DP_mmon1_cl49_ber_status_TYPE[14:00] - RO */ 6561 #endif /* IS_BIG_ENDIAN */ 6562 #if IS_LITTLE_ENDIAN 6563 uint32_t mmon1_cl49_ber_stat : 15; /* DP_mmon1_cl49_ber_status_TYPE[14:00] - RO */ 6564 uint32_t reserved_15 : 1; /* DP_mmon1_cl49_ber_status_TYPE[15] - RSVD */ 6565 uint32_t reserved : 16; 6566 #endif /* IS_LITTLE_ENDIAN */ 6567 } fields; 6568 } DP_mmon1_cl49_ber_status_TYPE; 6569 6570 typedef DP_mmon1_cl49_ber_status_TYPE DP_MMON1_CL49_BER_STATUS_TYPE_T; 6571 6572 typedef union { 6573 uint32_t data; 6574 struct { 6575 #if IS_BIG_ENDIAN 6576 uint32_t reserved : 16; 6577 uint32_t reserved_15 : 1; /* DP_mmon2_cl49_ber_status_TYPE[15] - RSVD */ 6578 uint32_t mmon2_cl49_ber_stat : 15; /* DP_mmon2_cl49_ber_status_TYPE[14:00] - RO */ 6579 #endif /* IS_BIG_ENDIAN */ 6580 #if IS_LITTLE_ENDIAN 6581 uint32_t mmon2_cl49_ber_stat : 15; /* DP_mmon2_cl49_ber_status_TYPE[14:00] - RO */ 6582 uint32_t reserved_15 : 1; /* DP_mmon2_cl49_ber_status_TYPE[15] - RSVD */ 6583 uint32_t reserved : 16; 6584 #endif /* IS_LITTLE_ENDIAN */ 6585 } fields; 6586 } DP_mmon2_cl49_ber_status_TYPE; 6587 6588 typedef DP_mmon2_cl49_ber_status_TYPE DP_MMON2_CL49_BER_STATUS_TYPE_T; 6589 6590 typedef union { 6591 uint32_t data; 6592 struct { 6593 #if IS_BIG_ENDIAN 6594 uint32_t reserved : 16; 6595 uint32_t reserved_15 : 1; /* DP_mmon3_cl49_ber_status_TYPE[15] - RSVD */ 6596 uint32_t mmon3_cl49_ber_stat : 15; /* DP_mmon3_cl49_ber_status_TYPE[14:00] - RO */ 6597 #endif /* IS_BIG_ENDIAN */ 6598 #if IS_LITTLE_ENDIAN 6599 uint32_t mmon3_cl49_ber_stat : 15; /* DP_mmon3_cl49_ber_status_TYPE[14:00] - RO */ 6600 uint32_t reserved_15 : 1; /* DP_mmon3_cl49_ber_status_TYPE[15] - RSVD */ 6601 uint32_t reserved : 16; 6602 #endif /* IS_LITTLE_ENDIAN */ 6603 } fields; 6604 } DP_mmon3_cl49_ber_status_TYPE; 6605 6606 typedef DP_mmon3_cl49_ber_status_TYPE DP_MMON3_CL49_BER_STATUS_TYPE_T; 6607 6608 typedef union { 6609 uint32_t data; 6610 struct { 6611 #if IS_BIG_ENDIAN 6612 uint32_t reserved : 16; 6613 uint32_t reserved_15 : 1; /* DP_mmon4_cl49_ber_status_TYPE[15] - RSVD */ 6614 uint32_t mmon4_cl49_ber_stat : 15; /* DP_mmon4_cl49_ber_status_TYPE[14:00] - RO */ 6615 #endif /* IS_BIG_ENDIAN */ 6616 #if IS_LITTLE_ENDIAN 6617 uint32_t mmon4_cl49_ber_stat : 15; /* DP_mmon4_cl49_ber_status_TYPE[14:00] - RO */ 6618 uint32_t reserved_15 : 1; /* DP_mmon4_cl49_ber_status_TYPE[15] - RSVD */ 6619 uint32_t reserved : 16; 6620 #endif /* IS_LITTLE_ENDIAN */ 6621 } fields; 6622 } DP_mmon4_cl49_ber_status_TYPE; 6623 6624 typedef DP_mmon4_cl49_ber_status_TYPE DP_MMON4_CL49_BER_STATUS_TYPE_T; 6625 6626 typedef union { 6627 uint32_t data; 6628 struct { 6629 #if IS_BIG_ENDIAN 6630 uint32_t reserved : 16; 6631 uint32_t reserved_15 : 1; /* DP_mmon5_cl49_ber_status_TYPE[15] - RSVD */ 6632 uint32_t mmon5_cl49_ber_stat : 15; /* DP_mmon5_cl49_ber_status_TYPE[14:00] - RO */ 6633 #endif /* IS_BIG_ENDIAN */ 6634 #if IS_LITTLE_ENDIAN 6635 uint32_t mmon5_cl49_ber_stat : 15; /* DP_mmon5_cl49_ber_status_TYPE[14:00] - RO */ 6636 uint32_t reserved_15 : 1; /* DP_mmon5_cl49_ber_status_TYPE[15] - RSVD */ 6637 uint32_t reserved : 16; 6638 #endif /* IS_LITTLE_ENDIAN */ 6639 } fields; 6640 } DP_mmon5_cl49_ber_status_TYPE; 6641 6642 typedef DP_mmon5_cl49_ber_status_TYPE DP_MMON5_CL49_BER_STATUS_TYPE_T; 6643 6644 typedef union { 6645 uint32_t data; 6646 struct { 6647 #if IS_BIG_ENDIAN 6648 uint32_t reserved : 16; 6649 uint32_t reserved_15 : 1; /* DP_mmon6_cl49_ber_status_TYPE[15] - RSVD */ 6650 uint32_t mmon6_cl49_ber_stat : 15; /* DP_mmon6_cl49_ber_status_TYPE[14:00] - RO */ 6651 #endif /* IS_BIG_ENDIAN */ 6652 #if IS_LITTLE_ENDIAN 6653 uint32_t mmon6_cl49_ber_stat : 15; /* DP_mmon6_cl49_ber_status_TYPE[14:00] - RO */ 6654 uint32_t reserved_15 : 1; /* DP_mmon6_cl49_ber_status_TYPE[15] - RSVD */ 6655 uint32_t reserved : 16; 6656 #endif /* IS_LITTLE_ENDIAN */ 6657 } fields; 6658 } DP_mmon6_cl49_ber_status_TYPE; 6659 6660 typedef DP_mmon6_cl49_ber_status_TYPE DP_MMON6_CL49_BER_STATUS_TYPE_T; 6661 6662 typedef union { 6663 uint32_t data; 6664 struct { 6665 #if IS_BIG_ENDIAN 6666 uint32_t reserved : 16; 6667 uint32_t reserved_15 : 1; /* DP_mmon7_cl49_ber_status_TYPE[15] - RSVD */ 6668 uint32_t mmon7_cl49_ber_stat : 15; /* DP_mmon7_cl49_ber_status_TYPE[14:00] - RO */ 6669 #endif /* IS_BIG_ENDIAN */ 6670 #if IS_LITTLE_ENDIAN 6671 uint32_t mmon7_cl49_ber_stat : 15; /* DP_mmon7_cl49_ber_status_TYPE[14:00] - RO */ 6672 uint32_t reserved_15 : 1; /* DP_mmon7_cl49_ber_status_TYPE[15] - RSVD */ 6673 uint32_t reserved : 16; 6674 #endif /* IS_LITTLE_ENDIAN */ 6675 } fields; 6676 } DP_mmon7_cl49_ber_status_TYPE; 6677 6678 typedef DP_mmon7_cl49_ber_status_TYPE DP_MMON7_CL49_BER_STATUS_TYPE_T; 6679 6680 typedef union { 6681 uint32_t data; 6682 struct { 6683 #if IS_BIG_ENDIAN 6684 uint32_t reserved : 16; 6685 uint32_t reserved_15 : 1; /* DP_mmon8_cl49_ber_status_TYPE[15] - RSVD */ 6686 uint32_t mmon8_cl49_ber_stat : 15; /* DP_mmon8_cl49_ber_status_TYPE[14:00] - RO */ 6687 #endif /* IS_BIG_ENDIAN */ 6688 #if IS_LITTLE_ENDIAN 6689 uint32_t mmon8_cl49_ber_stat : 15; /* DP_mmon8_cl49_ber_status_TYPE[14:00] - RO */ 6690 uint32_t reserved_15 : 1; /* DP_mmon8_cl49_ber_status_TYPE[15] - RSVD */ 6691 uint32_t reserved : 16; 6692 #endif /* IS_LITTLE_ENDIAN */ 6693 } fields; 6694 } DP_mmon8_cl49_ber_status_TYPE; 6695 6696 typedef DP_mmon8_cl49_ber_status_TYPE DP_MMON8_CL49_BER_STATUS_TYPE_T; 6697 6698 typedef union { 6699 uint32_t data; 6700 struct { 6701 #if IS_BIG_ENDIAN 6702 uint32_t reserved : 16; 6703 uint32_t reserved_15 : 1; /* DP_mmon9_cl49_ber_status_TYPE[15] - RSVD */ 6704 uint32_t mmon9_cl49_ber_stat : 15; /* DP_mmon9_cl49_ber_status_TYPE[14:00] - RO */ 6705 #endif /* IS_BIG_ENDIAN */ 6706 #if IS_LITTLE_ENDIAN 6707 uint32_t mmon9_cl49_ber_stat : 15; /* DP_mmon9_cl49_ber_status_TYPE[14:00] - RO */ 6708 uint32_t reserved_15 : 1; /* DP_mmon9_cl49_ber_status_TYPE[15] - RSVD */ 6709 uint32_t reserved : 16; 6710 #endif /* IS_LITTLE_ENDIAN */ 6711 } fields; 6712 } DP_mmon9_cl49_ber_status_TYPE; 6713 6714 typedef DP_mmon9_cl49_ber_status_TYPE DP_MMON9_CL49_BER_STATUS_TYPE_T; 6715 6716 typedef union { 6717 uint32_t data; 6718 struct { 6719 #if IS_BIG_ENDIAN 6720 uint32_t reserved : 16; 6721 uint32_t fmon0_ber_cnt_msb : 16; /* DP_fmon0_ber_count_msb_TYPE[15:00] - RO */ 6722 #endif /* IS_BIG_ENDIAN */ 6723 #if IS_LITTLE_ENDIAN 6724 uint32_t fmon0_ber_cnt_msb : 16; /* DP_fmon0_ber_count_msb_TYPE[15:00] - RO */ 6725 uint32_t reserved : 16; 6726 #endif /* IS_LITTLE_ENDIAN */ 6727 } fields; 6728 } DP_fmon0_ber_count_msb_TYPE; 6729 6730 typedef DP_fmon0_ber_count_msb_TYPE DP_FMON0_BER_COUNT_MSB_TYPE_T; 6731 6732 typedef union { 6733 uint32_t data; 6734 struct { 6735 #if IS_BIG_ENDIAN 6736 uint32_t reserved : 16; 6737 uint32_t fmon1_ber_cnt_msb : 16; /* DP_fmon1_ber_count_msb_TYPE[15:00] - RO */ 6738 #endif /* IS_BIG_ENDIAN */ 6739 #if IS_LITTLE_ENDIAN 6740 uint32_t fmon1_ber_cnt_msb : 16; /* DP_fmon1_ber_count_msb_TYPE[15:00] - RO */ 6741 uint32_t reserved : 16; 6742 #endif /* IS_LITTLE_ENDIAN */ 6743 } fields; 6744 } DP_fmon1_ber_count_msb_TYPE; 6745 6746 typedef DP_fmon1_ber_count_msb_TYPE DP_FMON1_BER_COUNT_MSB_TYPE_T; 6747 6748 typedef union { 6749 uint32_t data; 6750 struct { 6751 #if IS_BIG_ENDIAN 6752 uint32_t reserved : 16; 6753 uint32_t fmon2_ber_cnt_msb : 16; /* DP_fmon2_ber_count_msb_TYPE[15:00] - RO */ 6754 #endif /* IS_BIG_ENDIAN */ 6755 #if IS_LITTLE_ENDIAN 6756 uint32_t fmon2_ber_cnt_msb : 16; /* DP_fmon2_ber_count_msb_TYPE[15:00] - RO */ 6757 uint32_t reserved : 16; 6758 #endif /* IS_LITTLE_ENDIAN */ 6759 } fields; 6760 } DP_fmon2_ber_count_msb_TYPE; 6761 6762 typedef DP_fmon2_ber_count_msb_TYPE DP_FMON2_BER_COUNT_MSB_TYPE_T; 6763 6764 typedef union { 6765 uint32_t data; 6766 struct { 6767 #if IS_BIG_ENDIAN 6768 uint32_t reserved : 16; 6769 uint32_t fmon3_ber_cnt_msb : 16; /* DP_fmon3_ber_count_msb_TYPE[15:00] - RO */ 6770 #endif /* IS_BIG_ENDIAN */ 6771 #if IS_LITTLE_ENDIAN 6772 uint32_t fmon3_ber_cnt_msb : 16; /* DP_fmon3_ber_count_msb_TYPE[15:00] - RO */ 6773 uint32_t reserved : 16; 6774 #endif /* IS_LITTLE_ENDIAN */ 6775 } fields; 6776 } DP_fmon3_ber_count_msb_TYPE; 6777 6778 typedef DP_fmon3_ber_count_msb_TYPE DP_FMON3_BER_COUNT_MSB_TYPE_T; 6779 6780 typedef union { 6781 uint32_t data; 6782 struct { 6783 #if IS_BIG_ENDIAN 6784 uint32_t reserved : 16; 6785 uint32_t mmon0_ber_cnt_msb : 16; /* DP_mmon0_ber_count_msb_TYPE[15:00] - RO */ 6786 #endif /* IS_BIG_ENDIAN */ 6787 #if IS_LITTLE_ENDIAN 6788 uint32_t mmon0_ber_cnt_msb : 16; /* DP_mmon0_ber_count_msb_TYPE[15:00] - RO */ 6789 uint32_t reserved : 16; 6790 #endif /* IS_LITTLE_ENDIAN */ 6791 } fields; 6792 } DP_mmon0_ber_count_msb_TYPE; 6793 6794 typedef DP_mmon0_ber_count_msb_TYPE DP_MMON0_BER_COUNT_MSB_TYPE_T; 6795 6796 typedef union { 6797 uint32_t data; 6798 struct { 6799 #if IS_BIG_ENDIAN 6800 uint32_t reserved : 16; 6801 uint32_t mmon1_ber_cnt_msb : 16; /* DP_mmon1_ber_count_msb_TYPE[15:00] - RO */ 6802 #endif /* IS_BIG_ENDIAN */ 6803 #if IS_LITTLE_ENDIAN 6804 uint32_t mmon1_ber_cnt_msb : 16; /* DP_mmon1_ber_count_msb_TYPE[15:00] - RO */ 6805 uint32_t reserved : 16; 6806 #endif /* IS_LITTLE_ENDIAN */ 6807 } fields; 6808 } DP_mmon1_ber_count_msb_TYPE; 6809 6810 typedef DP_mmon1_ber_count_msb_TYPE DP_MMON1_BER_COUNT_MSB_TYPE_T; 6811 6812 typedef union { 6813 uint32_t data; 6814 struct { 6815 #if IS_BIG_ENDIAN 6816 uint32_t reserved : 16; 6817 uint32_t mmon2_ber_cnt_msb : 16; /* DP_mmon2_ber_count_msb_TYPE[15:00] - RO */ 6818 #endif /* IS_BIG_ENDIAN */ 6819 #if IS_LITTLE_ENDIAN 6820 uint32_t mmon2_ber_cnt_msb : 16; /* DP_mmon2_ber_count_msb_TYPE[15:00] - RO */ 6821 uint32_t reserved : 16; 6822 #endif /* IS_LITTLE_ENDIAN */ 6823 } fields; 6824 } DP_mmon2_ber_count_msb_TYPE; 6825 6826 typedef DP_mmon2_ber_count_msb_TYPE DP_MMON2_BER_COUNT_MSB_TYPE_T; 6827 6828 typedef union { 6829 uint32_t data; 6830 struct { 6831 #if IS_BIG_ENDIAN 6832 uint32_t reserved : 16; 6833 uint32_t mmon3_ber_cnt_msb : 16; /* DP_mmon3_ber_count_msb_TYPE[15:00] - RO */ 6834 #endif /* IS_BIG_ENDIAN */ 6835 #if IS_LITTLE_ENDIAN 6836 uint32_t mmon3_ber_cnt_msb : 16; /* DP_mmon3_ber_count_msb_TYPE[15:00] - RO */ 6837 uint32_t reserved : 16; 6838 #endif /* IS_LITTLE_ENDIAN */ 6839 } fields; 6840 } DP_mmon3_ber_count_msb_TYPE; 6841 6842 typedef DP_mmon3_ber_count_msb_TYPE DP_MMON3_BER_COUNT_MSB_TYPE_T; 6843 6844 typedef union { 6845 uint32_t data; 6846 struct { 6847 #if IS_BIG_ENDIAN 6848 uint32_t reserved : 16; 6849 uint32_t mmon4_ber_cnt_msb : 16; /* DP_mmon4_ber_count_msb_TYPE[15:00] - RO */ 6850 #endif /* IS_BIG_ENDIAN */ 6851 #if IS_LITTLE_ENDIAN 6852 uint32_t mmon4_ber_cnt_msb : 16; /* DP_mmon4_ber_count_msb_TYPE[15:00] - RO */ 6853 uint32_t reserved : 16; 6854 #endif /* IS_LITTLE_ENDIAN */ 6855 } fields; 6856 } DP_mmon4_ber_count_msb_TYPE; 6857 6858 typedef DP_mmon4_ber_count_msb_TYPE DP_MMON4_BER_COUNT_MSB_TYPE_T; 6859 6860 typedef union { 6861 uint32_t data; 6862 struct { 6863 #if IS_BIG_ENDIAN 6864 uint32_t reserved : 16; 6865 uint32_t mmon5_ber_cnt_msb : 16; /* DP_mmon5_ber_count_msb_TYPE[15:00] - RO */ 6866 #endif /* IS_BIG_ENDIAN */ 6867 #if IS_LITTLE_ENDIAN 6868 uint32_t mmon5_ber_cnt_msb : 16; /* DP_mmon5_ber_count_msb_TYPE[15:00] - RO */ 6869 uint32_t reserved : 16; 6870 #endif /* IS_LITTLE_ENDIAN */ 6871 } fields; 6872 } DP_mmon5_ber_count_msb_TYPE; 6873 6874 typedef DP_mmon5_ber_count_msb_TYPE DP_MMON5_BER_COUNT_MSB_TYPE_T; 6875 6876 typedef union { 6877 uint32_t data; 6878 struct { 6879 #if IS_BIG_ENDIAN 6880 uint32_t reserved : 16; 6881 uint32_t mmon6_ber_cnt_msb : 16; /* DP_mmon6_ber_count_msb_TYPE[15:00] - RO */ 6882 #endif /* IS_BIG_ENDIAN */ 6883 #if IS_LITTLE_ENDIAN 6884 uint32_t mmon6_ber_cnt_msb : 16; /* DP_mmon6_ber_count_msb_TYPE[15:00] - RO */ 6885 uint32_t reserved : 16; 6886 #endif /* IS_LITTLE_ENDIAN */ 6887 } fields; 6888 } DP_mmon6_ber_count_msb_TYPE; 6889 6890 typedef DP_mmon6_ber_count_msb_TYPE DP_MMON6_BER_COUNT_MSB_TYPE_T; 6891 6892 typedef union { 6893 uint32_t data; 6894 struct { 6895 #if IS_BIG_ENDIAN 6896 uint32_t reserved : 16; 6897 uint32_t mmon7_ber_cnt_msb : 16; /* DP_mmon7_ber_count_msb_TYPE[15:00] - RO */ 6898 #endif /* IS_BIG_ENDIAN */ 6899 #if IS_LITTLE_ENDIAN 6900 uint32_t mmon7_ber_cnt_msb : 16; /* DP_mmon7_ber_count_msb_TYPE[15:00] - RO */ 6901 uint32_t reserved : 16; 6902 #endif /* IS_LITTLE_ENDIAN */ 6903 } fields; 6904 } DP_mmon7_ber_count_msb_TYPE; 6905 6906 typedef DP_mmon7_ber_count_msb_TYPE DP_MMON7_BER_COUNT_MSB_TYPE_T; 6907 6908 typedef union { 6909 uint32_t data; 6910 struct { 6911 #if IS_BIG_ENDIAN 6912 uint32_t reserved : 16; 6913 uint32_t mmon8_ber_cnt_msb : 16; /* DP_mmon8_ber_count_msb_TYPE[15:00] - RO */ 6914 #endif /* IS_BIG_ENDIAN */ 6915 #if IS_LITTLE_ENDIAN 6916 uint32_t mmon8_ber_cnt_msb : 16; /* DP_mmon8_ber_count_msb_TYPE[15:00] - RO */ 6917 uint32_t reserved : 16; 6918 #endif /* IS_LITTLE_ENDIAN */ 6919 } fields; 6920 } DP_mmon8_ber_count_msb_TYPE; 6921 6922 typedef DP_mmon8_ber_count_msb_TYPE DP_MMON8_BER_COUNT_MSB_TYPE_T; 6923 6924 typedef union { 6925 uint32_t data; 6926 struct { 6927 #if IS_BIG_ENDIAN 6928 uint32_t reserved : 16; 6929 uint32_t mmon9_ber_cnt_msb : 16; /* DP_mmon9_ber_count_msb_TYPE[15:00] - RO */ 6930 #endif /* IS_BIG_ENDIAN */ 6931 #if IS_LITTLE_ENDIAN 6932 uint32_t mmon9_ber_cnt_msb : 16; /* DP_mmon9_ber_count_msb_TYPE[15:00] - RO */ 6933 uint32_t reserved : 16; 6934 #endif /* IS_LITTLE_ENDIAN */ 6935 } fields; 6936 } DP_mmon9_ber_count_msb_TYPE; 6937 6938 typedef DP_mmon9_ber_count_msb_TYPE DP_MMON9_BER_COUNT_MSB_TYPE_T; 6939 6940 typedef union { 6941 uint32_t data; 6942 struct { 6943 #if IS_BIG_ENDIAN 6944 uint32_t reserved : 16; 6945 uint32_t reserved_08 : 8; /* DP_fmon0_live_status_TYPE[15:08] - RSVD */ 6946 uint32_t fmon0_live_stat : 7; /* DP_fmon0_live_status_TYPE[07:01] - RO */ 6947 uint32_t reserved_00 : 1; /* DP_fmon0_live_status_TYPE[00] - RSVD */ 6948 #endif /* IS_BIG_ENDIAN */ 6949 #if IS_LITTLE_ENDIAN 6950 uint32_t reserved_00 : 1; /* DP_fmon0_live_status_TYPE[00] - RSVD */ 6951 uint32_t fmon0_live_stat : 7; /* DP_fmon0_live_status_TYPE[07:01] - RO */ 6952 uint32_t reserved_08 : 8; /* DP_fmon0_live_status_TYPE[15:08] - RSVD */ 6953 uint32_t reserved : 16; 6954 #endif /* IS_LITTLE_ENDIAN */ 6955 } fields; 6956 } DP_fmon0_live_status_TYPE; 6957 6958 typedef DP_fmon0_live_status_TYPE DP_FMON0_LIVE_STATUS_TYPE_T; 6959 6960 typedef union { 6961 uint32_t data; 6962 struct { 6963 #if IS_BIG_ENDIAN 6964 uint32_t reserved : 16; 6965 uint32_t reserved_08 : 8; /* DP_fmon1_live_status_TYPE[15:08] - RSVD */ 6966 uint32_t fmon1_live_stat : 7; /* DP_fmon1_live_status_TYPE[07:01] - RO */ 6967 uint32_t reserved_00 : 1; /* DP_fmon1_live_status_TYPE[00] - RSVD */ 6968 #endif /* IS_BIG_ENDIAN */ 6969 #if IS_LITTLE_ENDIAN 6970 uint32_t reserved_00 : 1; /* DP_fmon1_live_status_TYPE[00] - RSVD */ 6971 uint32_t fmon1_live_stat : 7; /* DP_fmon1_live_status_TYPE[07:01] - RO */ 6972 uint32_t reserved_08 : 8; /* DP_fmon1_live_status_TYPE[15:08] - RSVD */ 6973 uint32_t reserved : 16; 6974 #endif /* IS_LITTLE_ENDIAN */ 6975 } fields; 6976 } DP_fmon1_live_status_TYPE; 6977 6978 typedef DP_fmon1_live_status_TYPE DP_FMON1_LIVE_STATUS_TYPE_T; 6979 6980 typedef union { 6981 uint32_t data; 6982 struct { 6983 #if IS_BIG_ENDIAN 6984 uint32_t reserved : 16; 6985 uint32_t reserved_08 : 8; /* DP_fmon2_live_status_TYPE[15:08] - RSVD */ 6986 uint32_t fmon2_live_stat : 7; /* DP_fmon2_live_status_TYPE[07:01] - RO */ 6987 uint32_t reserved_00 : 1; /* DP_fmon2_live_status_TYPE[00] - RSVD */ 6988 #endif /* IS_BIG_ENDIAN */ 6989 #if IS_LITTLE_ENDIAN 6990 uint32_t reserved_00 : 1; /* DP_fmon2_live_status_TYPE[00] - RSVD */ 6991 uint32_t fmon2_live_stat : 7; /* DP_fmon2_live_status_TYPE[07:01] - RO */ 6992 uint32_t reserved_08 : 8; /* DP_fmon2_live_status_TYPE[15:08] - RSVD */ 6993 uint32_t reserved : 16; 6994 #endif /* IS_LITTLE_ENDIAN */ 6995 } fields; 6996 } DP_fmon2_live_status_TYPE; 6997 6998 typedef DP_fmon2_live_status_TYPE DP_FMON2_LIVE_STATUS_TYPE_T; 6999 7000 typedef union { 7001 uint32_t data; 7002 struct { 7003 #if IS_BIG_ENDIAN 7004 uint32_t reserved : 16; 7005 uint32_t reserved_08 : 8; /* DP_fmon3_live_status_TYPE[15:08] - RSVD */ 7006 uint32_t fmon3_live_stat : 7; /* DP_fmon3_live_status_TYPE[07:01] - RO */ 7007 uint32_t reserved_00 : 1; /* DP_fmon3_live_status_TYPE[00] - RSVD */ 7008 #endif /* IS_BIG_ENDIAN */ 7009 #if IS_LITTLE_ENDIAN 7010 uint32_t reserved_00 : 1; /* DP_fmon3_live_status_TYPE[00] - RSVD */ 7011 uint32_t fmon3_live_stat : 7; /* DP_fmon3_live_status_TYPE[07:01] - RO */ 7012 uint32_t reserved_08 : 8; /* DP_fmon3_live_status_TYPE[15:08] - RSVD */ 7013 uint32_t reserved : 16; 7014 #endif /* IS_LITTLE_ENDIAN */ 7015 } fields; 7016 } DP_fmon3_live_status_TYPE; 7017 7018 typedef DP_fmon3_live_status_TYPE DP_FMON3_LIVE_STATUS_TYPE_T; 7019 7020 typedef union { 7021 uint32_t data; 7022 struct { 7023 #if IS_BIG_ENDIAN 7024 uint32_t reserved : 16; 7025 uint32_t reserved_08 : 8; /* DP_mmon0_live_status_TYPE[15:08] - RSVD */ 7026 uint32_t mmon0_live_stat : 7; /* DP_mmon0_live_status_TYPE[07:01] - RO */ 7027 uint32_t reserved_00 : 1; /* DP_mmon0_live_status_TYPE[00] - RSVD */ 7028 #endif /* IS_BIG_ENDIAN */ 7029 #if IS_LITTLE_ENDIAN 7030 uint32_t reserved_00 : 1; /* DP_mmon0_live_status_TYPE[00] - RSVD */ 7031 uint32_t mmon0_live_stat : 7; /* DP_mmon0_live_status_TYPE[07:01] - RO */ 7032 uint32_t reserved_08 : 8; /* DP_mmon0_live_status_TYPE[15:08] - RSVD */ 7033 uint32_t reserved : 16; 7034 #endif /* IS_LITTLE_ENDIAN */ 7035 } fields; 7036 } DP_mmon0_live_status_TYPE; 7037 7038 typedef DP_mmon0_live_status_TYPE DP_MMON0_LIVE_STATUS_TYPE_T; 7039 7040 typedef union { 7041 uint32_t data; 7042 struct { 7043 #if IS_BIG_ENDIAN 7044 uint32_t reserved : 16; 7045 uint32_t reserved_08 : 8; /* DP_mmon1_live_status_TYPE[15:08] - RSVD */ 7046 uint32_t mmon1_live_stat : 7; /* DP_mmon1_live_status_TYPE[07:01] - RO */ 7047 uint32_t reserved_00 : 1; /* DP_mmon1_live_status_TYPE[00] - RSVD */ 7048 #endif /* IS_BIG_ENDIAN */ 7049 #if IS_LITTLE_ENDIAN 7050 uint32_t reserved_00 : 1; /* DP_mmon1_live_status_TYPE[00] - RSVD */ 7051 uint32_t mmon1_live_stat : 7; /* DP_mmon1_live_status_TYPE[07:01] - RO */ 7052 uint32_t reserved_08 : 8; /* DP_mmon1_live_status_TYPE[15:08] - RSVD */ 7053 uint32_t reserved : 16; 7054 #endif /* IS_LITTLE_ENDIAN */ 7055 } fields; 7056 } DP_mmon1_live_status_TYPE; 7057 7058 typedef DP_mmon1_live_status_TYPE DP_MMON1_LIVE_STATUS_TYPE_T; 7059 7060 typedef union { 7061 uint32_t data; 7062 struct { 7063 #if IS_BIG_ENDIAN 7064 uint32_t reserved : 16; 7065 uint32_t reserved_08 : 8; /* DP_mmon2_live_status_TYPE[15:08] - RSVD */ 7066 uint32_t mmon2_live_stat : 7; /* DP_mmon2_live_status_TYPE[07:01] - RO */ 7067 uint32_t reserved_00 : 1; /* DP_mmon2_live_status_TYPE[00] - RSVD */ 7068 #endif /* IS_BIG_ENDIAN */ 7069 #if IS_LITTLE_ENDIAN 7070 uint32_t reserved_00 : 1; /* DP_mmon2_live_status_TYPE[00] - RSVD */ 7071 uint32_t mmon2_live_stat : 7; /* DP_mmon2_live_status_TYPE[07:01] - RO */ 7072 uint32_t reserved_08 : 8; /* DP_mmon2_live_status_TYPE[15:08] - RSVD */ 7073 uint32_t reserved : 16; 7074 #endif /* IS_LITTLE_ENDIAN */ 7075 } fields; 7076 } DP_mmon2_live_status_TYPE; 7077 7078 typedef DP_mmon2_live_status_TYPE DP_MMON2_LIVE_STATUS_TYPE_T; 7079 7080 typedef union { 7081 uint32_t data; 7082 struct { 7083 #if IS_BIG_ENDIAN 7084 uint32_t reserved : 16; 7085 uint32_t reserved_08 : 8; /* DP_mmon3_live_status_TYPE[15:08] - RSVD */ 7086 uint32_t mmon3_live_stat : 7; /* DP_mmon3_live_status_TYPE[07:01] - RO */ 7087 uint32_t reserved_00 : 1; /* DP_mmon3_live_status_TYPE[00] - RSVD */ 7088 #endif /* IS_BIG_ENDIAN */ 7089 #if IS_LITTLE_ENDIAN 7090 uint32_t reserved_00 : 1; /* DP_mmon3_live_status_TYPE[00] - RSVD */ 7091 uint32_t mmon3_live_stat : 7; /* DP_mmon3_live_status_TYPE[07:01] - RO */ 7092 uint32_t reserved_08 : 8; /* DP_mmon3_live_status_TYPE[15:08] - RSVD */ 7093 uint32_t reserved : 16; 7094 #endif /* IS_LITTLE_ENDIAN */ 7095 } fields; 7096 } DP_mmon3_live_status_TYPE; 7097 7098 typedef DP_mmon3_live_status_TYPE DP_MMON3_LIVE_STATUS_TYPE_T; 7099 7100 typedef union { 7101 uint32_t data; 7102 struct { 7103 #if IS_BIG_ENDIAN 7104 uint32_t reserved : 16; 7105 uint32_t reserved_08 : 8; /* DP_mmon4_live_status_TYPE[15:08] - RSVD */ 7106 uint32_t mmon4_live_stat : 7; /* DP_mmon4_live_status_TYPE[07:01] - RO */ 7107 uint32_t reserved_00 : 1; /* DP_mmon4_live_status_TYPE[00] - RSVD */ 7108 #endif /* IS_BIG_ENDIAN */ 7109 #if IS_LITTLE_ENDIAN 7110 uint32_t reserved_00 : 1; /* DP_mmon4_live_status_TYPE[00] - RSVD */ 7111 uint32_t mmon4_live_stat : 7; /* DP_mmon4_live_status_TYPE[07:01] - RO */ 7112 uint32_t reserved_08 : 8; /* DP_mmon4_live_status_TYPE[15:08] - RSVD */ 7113 uint32_t reserved : 16; 7114 #endif /* IS_LITTLE_ENDIAN */ 7115 } fields; 7116 } DP_mmon4_live_status_TYPE; 7117 7118 typedef DP_mmon4_live_status_TYPE DP_MMON4_LIVE_STATUS_TYPE_T; 7119 7120 typedef union { 7121 uint32_t data; 7122 struct { 7123 #if IS_BIG_ENDIAN 7124 uint32_t reserved : 16; 7125 uint32_t reserved_08 : 8; /* DP_mmon5_live_status_TYPE[15:08] - RSVD */ 7126 uint32_t mmon5_live_stat : 7; /* DP_mmon5_live_status_TYPE[07:01] - RO */ 7127 uint32_t reserved_00 : 1; /* DP_mmon5_live_status_TYPE[00] - RSVD */ 7128 #endif /* IS_BIG_ENDIAN */ 7129 #if IS_LITTLE_ENDIAN 7130 uint32_t reserved_00 : 1; /* DP_mmon5_live_status_TYPE[00] - RSVD */ 7131 uint32_t mmon5_live_stat : 7; /* DP_mmon5_live_status_TYPE[07:01] - RO */ 7132 uint32_t reserved_08 : 8; /* DP_mmon5_live_status_TYPE[15:08] - RSVD */ 7133 uint32_t reserved : 16; 7134 #endif /* IS_LITTLE_ENDIAN */ 7135 } fields; 7136 } DP_mmon5_live_status_TYPE; 7137 7138 typedef DP_mmon5_live_status_TYPE DP_MMON5_LIVE_STATUS_TYPE_T; 7139 7140 typedef union { 7141 uint32_t data; 7142 struct { 7143 #if IS_BIG_ENDIAN 7144 uint32_t reserved : 16; 7145 uint32_t reserved_08 : 8; /* DP_mmon6_live_status_TYPE[15:08] - RSVD */ 7146 uint32_t mmon6_live_stat : 7; /* DP_mmon6_live_status_TYPE[07:01] - RO */ 7147 uint32_t reserved_00 : 1; /* DP_mmon6_live_status_TYPE[00] - RSVD */ 7148 #endif /* IS_BIG_ENDIAN */ 7149 #if IS_LITTLE_ENDIAN 7150 uint32_t reserved_00 : 1; /* DP_mmon6_live_status_TYPE[00] - RSVD */ 7151 uint32_t mmon6_live_stat : 7; /* DP_mmon6_live_status_TYPE[07:01] - RO */ 7152 uint32_t reserved_08 : 8; /* DP_mmon6_live_status_TYPE[15:08] - RSVD */ 7153 uint32_t reserved : 16; 7154 #endif /* IS_LITTLE_ENDIAN */ 7155 } fields; 7156 } DP_mmon6_live_status_TYPE; 7157 7158 typedef DP_mmon6_live_status_TYPE DP_MMON6_LIVE_STATUS_TYPE_T; 7159 7160 typedef union { 7161 uint32_t data; 7162 struct { 7163 #if IS_BIG_ENDIAN 7164 uint32_t reserved : 16; 7165 uint32_t reserved_08 : 8; /* DP_mmon7_live_status_TYPE[15:08] - RSVD */ 7166 uint32_t mmon7_live_stat : 7; /* DP_mmon7_live_status_TYPE[07:01] - RO */ 7167 uint32_t reserved_00 : 1; /* DP_mmon7_live_status_TYPE[00] - RSVD */ 7168 #endif /* IS_BIG_ENDIAN */ 7169 #if IS_LITTLE_ENDIAN 7170 uint32_t reserved_00 : 1; /* DP_mmon7_live_status_TYPE[00] - RSVD */ 7171 uint32_t mmon7_live_stat : 7; /* DP_mmon7_live_status_TYPE[07:01] - RO */ 7172 uint32_t reserved_08 : 8; /* DP_mmon7_live_status_TYPE[15:08] - RSVD */ 7173 uint32_t reserved : 16; 7174 #endif /* IS_LITTLE_ENDIAN */ 7175 } fields; 7176 } DP_mmon7_live_status_TYPE; 7177 7178 typedef DP_mmon7_live_status_TYPE DP_MMON7_LIVE_STATUS_TYPE_T; 7179 7180 typedef union { 7181 uint32_t data; 7182 struct { 7183 #if IS_BIG_ENDIAN 7184 uint32_t reserved : 16; 7185 uint32_t reserved_08 : 8; /* DP_mmon8_live_status_TYPE[15:08] - RSVD */ 7186 uint32_t mmon8_live_stat : 7; /* DP_mmon8_live_status_TYPE[07:01] - RO */ 7187 uint32_t reserved_00 : 1; /* DP_mmon8_live_status_TYPE[00] - RSVD */ 7188 #endif /* IS_BIG_ENDIAN */ 7189 #if IS_LITTLE_ENDIAN 7190 uint32_t reserved_00 : 1; /* DP_mmon8_live_status_TYPE[00] - RSVD */ 7191 uint32_t mmon8_live_stat : 7; /* DP_mmon8_live_status_TYPE[07:01] - RO */ 7192 uint32_t reserved_08 : 8; /* DP_mmon8_live_status_TYPE[15:08] - RSVD */ 7193 uint32_t reserved : 16; 7194 #endif /* IS_LITTLE_ENDIAN */ 7195 } fields; 7196 } DP_mmon8_live_status_TYPE; 7197 7198 typedef DP_mmon8_live_status_TYPE DP_MMON8_LIVE_STATUS_TYPE_T; 7199 7200 typedef union { 7201 uint32_t data; 7202 struct { 7203 #if IS_BIG_ENDIAN 7204 uint32_t reserved : 16; 7205 uint32_t reserved_08 : 8; /* DP_mmon9_live_status_TYPE[15:08] - RSVD */ 7206 uint32_t mmon9_live_stat : 7; /* DP_mmon9_live_status_TYPE[07:01] - RO */ 7207 uint32_t reserved_00 : 1; /* DP_mmon9_live_status_TYPE[00] - RSVD */ 7208 #endif /* IS_BIG_ENDIAN */ 7209 #if IS_LITTLE_ENDIAN 7210 uint32_t reserved_00 : 1; /* DP_mmon9_live_status_TYPE[00] - RSVD */ 7211 uint32_t mmon9_live_stat : 7; /* DP_mmon9_live_status_TYPE[07:01] - RO */ 7212 uint32_t reserved_08 : 8; /* DP_mmon9_live_status_TYPE[15:08] - RSVD */ 7213 uint32_t reserved : 16; 7214 #endif /* IS_LITTLE_ENDIAN */ 7215 } fields; 7216 } DP_mmon9_live_status_TYPE; 7217 7218 typedef DP_mmon9_live_status_TYPE DP_MMON9_LIVE_STATUS_TYPE_T; 7219 7220 typedef union { 7221 uint32_t data; 7222 struct { 7223 #if IS_BIG_ENDIAN 7224 uint32_t reserved : 16; 7225 uint32_t falcon_pcs_mon_rstb_frcval : 4; /* DP_pcs_mon_reset_frc_control0_TYPE[15:12] - WO */ 7226 uint32_t reserved_10 : 2; /* DP_pcs_mon_reset_frc_control0_TYPE[11:10] - RSVD */ 7227 uint32_t merlin_pcs_mon_rstb_frcval : 10; /* DP_pcs_mon_reset_frc_control0_TYPE[09:00] - WO */ 7228 #endif /* IS_BIG_ENDIAN */ 7229 #if IS_LITTLE_ENDIAN 7230 uint32_t merlin_pcs_mon_rstb_frcval : 10; /* DP_pcs_mon_reset_frc_control0_TYPE[09:00] - WO */ 7231 uint32_t reserved_10 : 2; /* DP_pcs_mon_reset_frc_control0_TYPE[11:10] - RSVD */ 7232 uint32_t falcon_pcs_mon_rstb_frcval : 4; /* DP_pcs_mon_reset_frc_control0_TYPE[15:12] - WO */ 7233 uint32_t reserved : 16; 7234 #endif /* IS_LITTLE_ENDIAN */ 7235 } fields; 7236 } DP_pcs_mon_reset_frc_control0_TYPE; 7237 7238 typedef DP_pcs_mon_reset_frc_control0_TYPE DP_PCS_MON_RESET_FRC_CONTROL0_TYPE_T; 7239 7240 typedef union { 7241 uint32_t data; 7242 struct { 7243 #if IS_BIG_ENDIAN 7244 uint32_t reserved : 16; 7245 uint32_t falcon_pcs_mon_rstb_frc : 4; /* DP_pcs_mon_reset_frc_control1_TYPE[15:12] - WO */ 7246 uint32_t reserved_10 : 2; /* DP_pcs_mon_reset_frc_control1_TYPE[11:10] - RSVD */ 7247 uint32_t merlin_pcs_mon_rstb_frc : 10; /* DP_pcs_mon_reset_frc_control1_TYPE[09:00] - WO */ 7248 #endif /* IS_BIG_ENDIAN */ 7249 #if IS_LITTLE_ENDIAN 7250 uint32_t merlin_pcs_mon_rstb_frc : 10; /* DP_pcs_mon_reset_frc_control1_TYPE[09:00] - WO */ 7251 uint32_t reserved_10 : 2; /* DP_pcs_mon_reset_frc_control1_TYPE[11:10] - RSVD */ 7252 uint32_t falcon_pcs_mon_rstb_frc : 4; /* DP_pcs_mon_reset_frc_control1_TYPE[15:12] - WO */ 7253 uint32_t reserved : 16; 7254 #endif /* IS_LITTLE_ENDIAN */ 7255 } fields; 7256 } DP_pcs_mon_reset_frc_control1_TYPE; 7257 7258 typedef DP_pcs_mon_reset_frc_control1_TYPE DP_PCS_MON_RESET_FRC_CONTROL1_TYPE_T; 7259 7260 7261 /*-----------------------------------------------*/ 7262 /* Structs for MRX_TEST Bank */ 7263 /*-----------------------------------------------*/ 7264 typedef union { 7265 uint32_t data; 7266 struct { 7267 #if IS_BIG_ENDIAN 7268 uint32_t reserved : 16; 7269 uint32_t pat_chk_din : 16; /* MRX_TEST_pattern_TYPE[15:00] - WO */ 7270 #endif /* IS_BIG_ENDIAN */ 7271 #if IS_LITTLE_ENDIAN 7272 uint32_t pat_chk_din : 16; /* MRX_TEST_pattern_TYPE[15:00] - WO */ 7273 uint32_t reserved : 16; 7274 #endif /* IS_LITTLE_ENDIAN */ 7275 } fields; 7276 } MRX_TEST_pattern_TYPE; 7277 7278 typedef MRX_TEST_pattern_TYPE MRX_TEST_PATTERN_TYPE_T; 7279 7280 typedef union { 7281 uint32_t data; 7282 struct { 7283 #if IS_BIG_ENDIAN 7284 uint32_t reserved : 16; 7285 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln0_TYPE[15:02] - RSVD */ 7286 uint32_t pat_chk_unlock_dis_ln0 : 1; /* MRX_TEST_control1_ln0_TYPE[01] - WO */ 7287 uint32_t pat_chk_en_ln0 : 1; /* MRX_TEST_control1_ln0_TYPE[00] - WO */ 7288 #endif /* IS_BIG_ENDIAN */ 7289 #if IS_LITTLE_ENDIAN 7290 uint32_t pat_chk_en_ln0 : 1; /* MRX_TEST_control1_ln0_TYPE[00] - WO */ 7291 uint32_t pat_chk_unlock_dis_ln0 : 1; /* MRX_TEST_control1_ln0_TYPE[01] - WO */ 7292 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln0_TYPE[15:02] - RSVD */ 7293 uint32_t reserved : 16; 7294 #endif /* IS_LITTLE_ENDIAN */ 7295 } fields; 7296 } MRX_TEST_control1_ln0_TYPE; 7297 7298 typedef MRX_TEST_control1_ln0_TYPE MRX_TEST_CONTROL1_LN0_TYPE_T; 7299 7300 typedef union { 7301 uint32_t data; 7302 struct { 7303 #if IS_BIG_ENDIAN 7304 uint32_t reserved : 16; 7305 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln1_TYPE[15:02] - RSVD */ 7306 uint32_t pat_chk_unlock_dis_ln1 : 1; /* MRX_TEST_control1_ln1_TYPE[01] - WO */ 7307 uint32_t pat_chk_en_ln1 : 1; /* MRX_TEST_control1_ln1_TYPE[00] - WO */ 7308 #endif /* IS_BIG_ENDIAN */ 7309 #if IS_LITTLE_ENDIAN 7310 uint32_t pat_chk_en_ln1 : 1; /* MRX_TEST_control1_ln1_TYPE[00] - WO */ 7311 uint32_t pat_chk_unlock_dis_ln1 : 1; /* MRX_TEST_control1_ln1_TYPE[01] - WO */ 7312 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln1_TYPE[15:02] - RSVD */ 7313 uint32_t reserved : 16; 7314 #endif /* IS_LITTLE_ENDIAN */ 7315 } fields; 7316 } MRX_TEST_control1_ln1_TYPE; 7317 7318 typedef MRX_TEST_control1_ln1_TYPE MRX_TEST_CONTROL1_LN1_TYPE_T; 7319 7320 typedef union { 7321 uint32_t data; 7322 struct { 7323 #if IS_BIG_ENDIAN 7324 uint32_t reserved : 16; 7325 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln2_TYPE[15:02] - RSVD */ 7326 uint32_t pat_chk_unlock_dis_ln2 : 1; /* MRX_TEST_control1_ln2_TYPE[01] - WO */ 7327 uint32_t pat_chk_en_ln2 : 1; /* MRX_TEST_control1_ln2_TYPE[00] - WO */ 7328 #endif /* IS_BIG_ENDIAN */ 7329 #if IS_LITTLE_ENDIAN 7330 uint32_t pat_chk_en_ln2 : 1; /* MRX_TEST_control1_ln2_TYPE[00] - WO */ 7331 uint32_t pat_chk_unlock_dis_ln2 : 1; /* MRX_TEST_control1_ln2_TYPE[01] - WO */ 7332 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln2_TYPE[15:02] - RSVD */ 7333 uint32_t reserved : 16; 7334 #endif /* IS_LITTLE_ENDIAN */ 7335 } fields; 7336 } MRX_TEST_control1_ln2_TYPE; 7337 7338 typedef MRX_TEST_control1_ln2_TYPE MRX_TEST_CONTROL1_LN2_TYPE_T; 7339 7340 typedef union { 7341 uint32_t data; 7342 struct { 7343 #if IS_BIG_ENDIAN 7344 uint32_t reserved : 16; 7345 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln3_TYPE[15:02] - RSVD */ 7346 uint32_t pat_chk_unlock_dis_ln3 : 1; /* MRX_TEST_control1_ln3_TYPE[01] - WO */ 7347 uint32_t pat_chk_en_ln3 : 1; /* MRX_TEST_control1_ln3_TYPE[00] - WO */ 7348 #endif /* IS_BIG_ENDIAN */ 7349 #if IS_LITTLE_ENDIAN 7350 uint32_t pat_chk_en_ln3 : 1; /* MRX_TEST_control1_ln3_TYPE[00] - WO */ 7351 uint32_t pat_chk_unlock_dis_ln3 : 1; /* MRX_TEST_control1_ln3_TYPE[01] - WO */ 7352 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln3_TYPE[15:02] - RSVD */ 7353 uint32_t reserved : 16; 7354 #endif /* IS_LITTLE_ENDIAN */ 7355 } fields; 7356 } MRX_TEST_control1_ln3_TYPE; 7357 7358 typedef MRX_TEST_control1_ln3_TYPE MRX_TEST_CONTROL1_LN3_TYPE_T; 7359 7360 typedef union { 7361 uint32_t data; 7362 struct { 7363 #if IS_BIG_ENDIAN 7364 uint32_t reserved : 16; 7365 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln4_TYPE[15:02] - RSVD */ 7366 uint32_t pat_chk_unlock_dis_ln4 : 1; /* MRX_TEST_control1_ln4_TYPE[01] - WO */ 7367 uint32_t pat_chk_en_ln4 : 1; /* MRX_TEST_control1_ln4_TYPE[00] - WO */ 7368 #endif /* IS_BIG_ENDIAN */ 7369 #if IS_LITTLE_ENDIAN 7370 uint32_t pat_chk_en_ln4 : 1; /* MRX_TEST_control1_ln4_TYPE[00] - WO */ 7371 uint32_t pat_chk_unlock_dis_ln4 : 1; /* MRX_TEST_control1_ln4_TYPE[01] - WO */ 7372 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln4_TYPE[15:02] - RSVD */ 7373 uint32_t reserved : 16; 7374 #endif /* IS_LITTLE_ENDIAN */ 7375 } fields; 7376 } MRX_TEST_control1_ln4_TYPE; 7377 7378 typedef MRX_TEST_control1_ln4_TYPE MRX_TEST_CONTROL1_LN4_TYPE_T; 7379 7380 typedef union { 7381 uint32_t data; 7382 struct { 7383 #if IS_BIG_ENDIAN 7384 uint32_t reserved : 16; 7385 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln5_TYPE[15:02] - RSVD */ 7386 uint32_t pat_chk_unlock_dis_ln5 : 1; /* MRX_TEST_control1_ln5_TYPE[01] - WO */ 7387 uint32_t pat_chk_en_ln5 : 1; /* MRX_TEST_control1_ln5_TYPE[00] - WO */ 7388 #endif /* IS_BIG_ENDIAN */ 7389 #if IS_LITTLE_ENDIAN 7390 uint32_t pat_chk_en_ln5 : 1; /* MRX_TEST_control1_ln5_TYPE[00] - WO */ 7391 uint32_t pat_chk_unlock_dis_ln5 : 1; /* MRX_TEST_control1_ln5_TYPE[01] - WO */ 7392 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln5_TYPE[15:02] - RSVD */ 7393 uint32_t reserved : 16; 7394 #endif /* IS_LITTLE_ENDIAN */ 7395 } fields; 7396 } MRX_TEST_control1_ln5_TYPE; 7397 7398 typedef MRX_TEST_control1_ln5_TYPE MRX_TEST_CONTROL1_LN5_TYPE_T; 7399 7400 typedef union { 7401 uint32_t data; 7402 struct { 7403 #if IS_BIG_ENDIAN 7404 uint32_t reserved : 16; 7405 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln6_TYPE[15:02] - RSVD */ 7406 uint32_t pat_chk_unlock_dis_ln6 : 1; /* MRX_TEST_control1_ln6_TYPE[01] - WO */ 7407 uint32_t pat_chk_en_ln6 : 1; /* MRX_TEST_control1_ln6_TYPE[00] - WO */ 7408 #endif /* IS_BIG_ENDIAN */ 7409 #if IS_LITTLE_ENDIAN 7410 uint32_t pat_chk_en_ln6 : 1; /* MRX_TEST_control1_ln6_TYPE[00] - WO */ 7411 uint32_t pat_chk_unlock_dis_ln6 : 1; /* MRX_TEST_control1_ln6_TYPE[01] - WO */ 7412 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln6_TYPE[15:02] - RSVD */ 7413 uint32_t reserved : 16; 7414 #endif /* IS_LITTLE_ENDIAN */ 7415 } fields; 7416 } MRX_TEST_control1_ln6_TYPE; 7417 7418 typedef MRX_TEST_control1_ln6_TYPE MRX_TEST_CONTROL1_LN6_TYPE_T; 7419 7420 typedef union { 7421 uint32_t data; 7422 struct { 7423 #if IS_BIG_ENDIAN 7424 uint32_t reserved : 16; 7425 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln7_TYPE[15:02] - RSVD */ 7426 uint32_t pat_chk_unlock_dis_ln7 : 1; /* MRX_TEST_control1_ln7_TYPE[01] - WO */ 7427 uint32_t pat_chk_en_ln7 : 1; /* MRX_TEST_control1_ln7_TYPE[00] - WO */ 7428 #endif /* IS_BIG_ENDIAN */ 7429 #if IS_LITTLE_ENDIAN 7430 uint32_t pat_chk_en_ln7 : 1; /* MRX_TEST_control1_ln7_TYPE[00] - WO */ 7431 uint32_t pat_chk_unlock_dis_ln7 : 1; /* MRX_TEST_control1_ln7_TYPE[01] - WO */ 7432 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln7_TYPE[15:02] - RSVD */ 7433 uint32_t reserved : 16; 7434 #endif /* IS_LITTLE_ENDIAN */ 7435 } fields; 7436 } MRX_TEST_control1_ln7_TYPE; 7437 7438 typedef MRX_TEST_control1_ln7_TYPE MRX_TEST_CONTROL1_LN7_TYPE_T; 7439 7440 typedef union { 7441 uint32_t data; 7442 struct { 7443 #if IS_BIG_ENDIAN 7444 uint32_t reserved : 16; 7445 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln8_TYPE[15:02] - RSVD */ 7446 uint32_t pat_chk_unlock_dis_ln8 : 1; /* MRX_TEST_control1_ln8_TYPE[01] - WO */ 7447 uint32_t pat_chk_en_ln8 : 1; /* MRX_TEST_control1_ln8_TYPE[00] - WO */ 7448 #endif /* IS_BIG_ENDIAN */ 7449 #if IS_LITTLE_ENDIAN 7450 uint32_t pat_chk_en_ln8 : 1; /* MRX_TEST_control1_ln8_TYPE[00] - WO */ 7451 uint32_t pat_chk_unlock_dis_ln8 : 1; /* MRX_TEST_control1_ln8_TYPE[01] - WO */ 7452 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln8_TYPE[15:02] - RSVD */ 7453 uint32_t reserved : 16; 7454 #endif /* IS_LITTLE_ENDIAN */ 7455 } fields; 7456 } MRX_TEST_control1_ln8_TYPE; 7457 7458 typedef MRX_TEST_control1_ln8_TYPE MRX_TEST_CONTROL1_LN8_TYPE_T; 7459 7460 typedef union { 7461 uint32_t data; 7462 struct { 7463 #if IS_BIG_ENDIAN 7464 uint32_t reserved : 16; 7465 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln9_TYPE[15:02] - RSVD */ 7466 uint32_t pat_chk_unlock_dis_ln9 : 1; /* MRX_TEST_control1_ln9_TYPE[01] - WO */ 7467 uint32_t pat_chk_en_ln9 : 1; /* MRX_TEST_control1_ln9_TYPE[00] - WO */ 7468 #endif /* IS_BIG_ENDIAN */ 7469 #if IS_LITTLE_ENDIAN 7470 uint32_t pat_chk_en_ln9 : 1; /* MRX_TEST_control1_ln9_TYPE[00] - WO */ 7471 uint32_t pat_chk_unlock_dis_ln9 : 1; /* MRX_TEST_control1_ln9_TYPE[01] - WO */ 7472 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_control1_ln9_TYPE[15:02] - RSVD */ 7473 uint32_t reserved : 16; 7474 #endif /* IS_LITTLE_ENDIAN */ 7475 } fields; 7476 } MRX_TEST_control1_ln9_TYPE; 7477 7478 typedef MRX_TEST_control1_ln9_TYPE MRX_TEST_CONTROL1_LN9_TYPE_T; 7479 7480 typedef union { 7481 uint32_t data; 7482 struct { 7483 #if IS_BIG_ENDIAN 7484 uint32_t reserved : 16; 7485 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln0_TYPE[15:02] - RSVD */ 7486 uint32_t pat_chk_err_lh_ln0 : 1; /* MRX_TEST_status1_ln0_TYPE[01] - RO */ 7487 uint32_t pat_chk_lock_ll_ln0 : 1; /* MRX_TEST_status1_ln0_TYPE[00] - RO */ 7488 #endif /* IS_BIG_ENDIAN */ 7489 #if IS_LITTLE_ENDIAN 7490 uint32_t pat_chk_lock_ll_ln0 : 1; /* MRX_TEST_status1_ln0_TYPE[00] - RO */ 7491 uint32_t pat_chk_err_lh_ln0 : 1; /* MRX_TEST_status1_ln0_TYPE[01] - RO */ 7492 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln0_TYPE[15:02] - RSVD */ 7493 uint32_t reserved : 16; 7494 #endif /* IS_LITTLE_ENDIAN */ 7495 } fields; 7496 } MRX_TEST_status1_ln0_TYPE; 7497 7498 typedef MRX_TEST_status1_ln0_TYPE MRX_TEST_STATUS1_LN0_TYPE_T; 7499 7500 typedef union { 7501 uint32_t data; 7502 struct { 7503 #if IS_BIG_ENDIAN 7504 uint32_t reserved : 16; 7505 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln1_TYPE[15:02] - RSVD */ 7506 uint32_t pat_chk_err_lh_ln1 : 1; /* MRX_TEST_status1_ln1_TYPE[01] - RO */ 7507 uint32_t pat_chk_lock_ll_ln1 : 1; /* MRX_TEST_status1_ln1_TYPE[00] - RO */ 7508 #endif /* IS_BIG_ENDIAN */ 7509 #if IS_LITTLE_ENDIAN 7510 uint32_t pat_chk_lock_ll_ln1 : 1; /* MRX_TEST_status1_ln1_TYPE[00] - RO */ 7511 uint32_t pat_chk_err_lh_ln1 : 1; /* MRX_TEST_status1_ln1_TYPE[01] - RO */ 7512 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln1_TYPE[15:02] - RSVD */ 7513 uint32_t reserved : 16; 7514 #endif /* IS_LITTLE_ENDIAN */ 7515 } fields; 7516 } MRX_TEST_status1_ln1_TYPE; 7517 7518 typedef MRX_TEST_status1_ln1_TYPE MRX_TEST_STATUS1_LN1_TYPE_T; 7519 7520 typedef union { 7521 uint32_t data; 7522 struct { 7523 #if IS_BIG_ENDIAN 7524 uint32_t reserved : 16; 7525 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln2_TYPE[15:02] - RSVD */ 7526 uint32_t pat_chk_err_lh_ln2 : 1; /* MRX_TEST_status1_ln2_TYPE[01] - RO */ 7527 uint32_t pat_chk_lock_ll_ln2 : 1; /* MRX_TEST_status1_ln2_TYPE[00] - RO */ 7528 #endif /* IS_BIG_ENDIAN */ 7529 #if IS_LITTLE_ENDIAN 7530 uint32_t pat_chk_lock_ll_ln2 : 1; /* MRX_TEST_status1_ln2_TYPE[00] - RO */ 7531 uint32_t pat_chk_err_lh_ln2 : 1; /* MRX_TEST_status1_ln2_TYPE[01] - RO */ 7532 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln2_TYPE[15:02] - RSVD */ 7533 uint32_t reserved : 16; 7534 #endif /* IS_LITTLE_ENDIAN */ 7535 } fields; 7536 } MRX_TEST_status1_ln2_TYPE; 7537 7538 typedef MRX_TEST_status1_ln2_TYPE MRX_TEST_STATUS1_LN2_TYPE_T; 7539 7540 typedef union { 7541 uint32_t data; 7542 struct { 7543 #if IS_BIG_ENDIAN 7544 uint32_t reserved : 16; 7545 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln3_TYPE[15:02] - RSVD */ 7546 uint32_t pat_chk_err_lh_ln3 : 1; /* MRX_TEST_status1_ln3_TYPE[01] - RO */ 7547 uint32_t pat_chk_lock_ll_ln3 : 1; /* MRX_TEST_status1_ln3_TYPE[00] - RO */ 7548 #endif /* IS_BIG_ENDIAN */ 7549 #if IS_LITTLE_ENDIAN 7550 uint32_t pat_chk_lock_ll_ln3 : 1; /* MRX_TEST_status1_ln3_TYPE[00] - RO */ 7551 uint32_t pat_chk_err_lh_ln3 : 1; /* MRX_TEST_status1_ln3_TYPE[01] - RO */ 7552 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln3_TYPE[15:02] - RSVD */ 7553 uint32_t reserved : 16; 7554 #endif /* IS_LITTLE_ENDIAN */ 7555 } fields; 7556 } MRX_TEST_status1_ln3_TYPE; 7557 7558 typedef MRX_TEST_status1_ln3_TYPE MRX_TEST_STATUS1_LN3_TYPE_T; 7559 7560 typedef union { 7561 uint32_t data; 7562 struct { 7563 #if IS_BIG_ENDIAN 7564 uint32_t reserved : 16; 7565 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln4_TYPE[15:02] - RSVD */ 7566 uint32_t pat_chk_err_lh_ln4 : 1; /* MRX_TEST_status1_ln4_TYPE[01] - RO */ 7567 uint32_t pat_chk_lock_ll_ln4 : 1; /* MRX_TEST_status1_ln4_TYPE[00] - RO */ 7568 #endif /* IS_BIG_ENDIAN */ 7569 #if IS_LITTLE_ENDIAN 7570 uint32_t pat_chk_lock_ll_ln4 : 1; /* MRX_TEST_status1_ln4_TYPE[00] - RO */ 7571 uint32_t pat_chk_err_lh_ln4 : 1; /* MRX_TEST_status1_ln4_TYPE[01] - RO */ 7572 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln4_TYPE[15:02] - RSVD */ 7573 uint32_t reserved : 16; 7574 #endif /* IS_LITTLE_ENDIAN */ 7575 } fields; 7576 } MRX_TEST_status1_ln4_TYPE; 7577 7578 typedef MRX_TEST_status1_ln4_TYPE MRX_TEST_STATUS1_LN4_TYPE_T; 7579 7580 typedef union { 7581 uint32_t data; 7582 struct { 7583 #if IS_BIG_ENDIAN 7584 uint32_t reserved : 16; 7585 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln5_TYPE[15:02] - RSVD */ 7586 uint32_t pat_chk_err_lh_ln5 : 1; /* MRX_TEST_status1_ln5_TYPE[01] - RO */ 7587 uint32_t pat_chk_lock_ll_ln5 : 1; /* MRX_TEST_status1_ln5_TYPE[00] - RO */ 7588 #endif /* IS_BIG_ENDIAN */ 7589 #if IS_LITTLE_ENDIAN 7590 uint32_t pat_chk_lock_ll_ln5 : 1; /* MRX_TEST_status1_ln5_TYPE[00] - RO */ 7591 uint32_t pat_chk_err_lh_ln5 : 1; /* MRX_TEST_status1_ln5_TYPE[01] - RO */ 7592 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln5_TYPE[15:02] - RSVD */ 7593 uint32_t reserved : 16; 7594 #endif /* IS_LITTLE_ENDIAN */ 7595 } fields; 7596 } MRX_TEST_status1_ln5_TYPE; 7597 7598 typedef MRX_TEST_status1_ln5_TYPE MRX_TEST_STATUS1_LN5_TYPE_T; 7599 7600 typedef union { 7601 uint32_t data; 7602 struct { 7603 #if IS_BIG_ENDIAN 7604 uint32_t reserved : 16; 7605 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln6_TYPE[15:02] - RSVD */ 7606 uint32_t pat_chk_err_lh_ln6 : 1; /* MRX_TEST_status1_ln6_TYPE[01] - RO */ 7607 uint32_t pat_chk_lock_ll_ln6 : 1; /* MRX_TEST_status1_ln6_TYPE[00] - RO */ 7608 #endif /* IS_BIG_ENDIAN */ 7609 #if IS_LITTLE_ENDIAN 7610 uint32_t pat_chk_lock_ll_ln6 : 1; /* MRX_TEST_status1_ln6_TYPE[00] - RO */ 7611 uint32_t pat_chk_err_lh_ln6 : 1; /* MRX_TEST_status1_ln6_TYPE[01] - RO */ 7612 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln6_TYPE[15:02] - RSVD */ 7613 uint32_t reserved : 16; 7614 #endif /* IS_LITTLE_ENDIAN */ 7615 } fields; 7616 } MRX_TEST_status1_ln6_TYPE; 7617 7618 typedef MRX_TEST_status1_ln6_TYPE MRX_TEST_STATUS1_LN6_TYPE_T; 7619 7620 typedef union { 7621 uint32_t data; 7622 struct { 7623 #if IS_BIG_ENDIAN 7624 uint32_t reserved : 16; 7625 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln7_TYPE[15:02] - RSVD */ 7626 uint32_t pat_chk_err_lh_ln7 : 1; /* MRX_TEST_status1_ln7_TYPE[01] - RO */ 7627 uint32_t pat_chk_lock_ll_ln7 : 1; /* MRX_TEST_status1_ln7_TYPE[00] - RO */ 7628 #endif /* IS_BIG_ENDIAN */ 7629 #if IS_LITTLE_ENDIAN 7630 uint32_t pat_chk_lock_ll_ln7 : 1; /* MRX_TEST_status1_ln7_TYPE[00] - RO */ 7631 uint32_t pat_chk_err_lh_ln7 : 1; /* MRX_TEST_status1_ln7_TYPE[01] - RO */ 7632 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln7_TYPE[15:02] - RSVD */ 7633 uint32_t reserved : 16; 7634 #endif /* IS_LITTLE_ENDIAN */ 7635 } fields; 7636 } MRX_TEST_status1_ln7_TYPE; 7637 7638 typedef MRX_TEST_status1_ln7_TYPE MRX_TEST_STATUS1_LN7_TYPE_T; 7639 7640 typedef union { 7641 uint32_t data; 7642 struct { 7643 #if IS_BIG_ENDIAN 7644 uint32_t reserved : 16; 7645 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln8_TYPE[15:02] - RSVD */ 7646 uint32_t pat_chk_err_lh_ln8 : 1; /* MRX_TEST_status1_ln8_TYPE[01] - RO */ 7647 uint32_t pat_chk_lock_ll_ln8 : 1; /* MRX_TEST_status1_ln8_TYPE[00] - RO */ 7648 #endif /* IS_BIG_ENDIAN */ 7649 #if IS_LITTLE_ENDIAN 7650 uint32_t pat_chk_lock_ll_ln8 : 1; /* MRX_TEST_status1_ln8_TYPE[00] - RO */ 7651 uint32_t pat_chk_err_lh_ln8 : 1; /* MRX_TEST_status1_ln8_TYPE[01] - RO */ 7652 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln8_TYPE[15:02] - RSVD */ 7653 uint32_t reserved : 16; 7654 #endif /* IS_LITTLE_ENDIAN */ 7655 } fields; 7656 } MRX_TEST_status1_ln8_TYPE; 7657 7658 typedef MRX_TEST_status1_ln8_TYPE MRX_TEST_STATUS1_LN8_TYPE_T; 7659 7660 typedef union { 7661 uint32_t data; 7662 struct { 7663 #if IS_BIG_ENDIAN 7664 uint32_t reserved : 16; 7665 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln9_TYPE[15:02] - RSVD */ 7666 uint32_t pat_chk_err_lh_ln9 : 1; /* MRX_TEST_status1_ln9_TYPE[01] - RO */ 7667 uint32_t pat_chk_lock_ll_ln9 : 1; /* MRX_TEST_status1_ln9_TYPE[00] - RO */ 7668 #endif /* IS_BIG_ENDIAN */ 7669 #if IS_LITTLE_ENDIAN 7670 uint32_t pat_chk_lock_ll_ln9 : 1; /* MRX_TEST_status1_ln9_TYPE[00] - RO */ 7671 uint32_t pat_chk_err_lh_ln9 : 1; /* MRX_TEST_status1_ln9_TYPE[01] - RO */ 7672 uint32_t reserved_for_eco_02 : 14; /* MRX_TEST_status1_ln9_TYPE[15:02] - RSVD */ 7673 uint32_t reserved : 16; 7674 #endif /* IS_LITTLE_ENDIAN */ 7675 } fields; 7676 } MRX_TEST_status1_ln9_TYPE; 7677 7678 typedef MRX_TEST_status1_ln9_TYPE MRX_TEST_STATUS1_LN9_TYPE_T; 7679 7680 7681 /*-----------------------------------------------*/ 7682 /* Structs for DRX_TEST Bank */ 7683 /*-----------------------------------------------*/ 7684 typedef union { 7685 uint32_t data; 7686 struct { 7687 #if IS_BIG_ENDIAN 7688 uint32_t reserved : 16; 7689 uint32_t pat_chk_din : 16; /* DRX_TEST_pattern_TYPE[15:00] - WO */ 7690 #endif /* IS_BIG_ENDIAN */ 7691 #if IS_LITTLE_ENDIAN 7692 uint32_t pat_chk_din : 16; /* DRX_TEST_pattern_TYPE[15:00] - WO */ 7693 uint32_t reserved : 16; 7694 #endif /* IS_LITTLE_ENDIAN */ 7695 } fields; 7696 } DRX_TEST_pattern_TYPE; 7697 7698 typedef DRX_TEST_pattern_TYPE DRX_TEST_PATTERN_TYPE_T; 7699 7700 typedef union { 7701 uint32_t data; 7702 struct { 7703 #if IS_BIG_ENDIAN 7704 uint32_t reserved : 16; 7705 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln0_TYPE[15:02] - RSVD */ 7706 uint32_t pat_chk_unlock_dis_ln0 : 1; /* DRX_TEST_control_ln0_TYPE[01] - WO */ 7707 uint32_t pat_chk_en_ln0 : 1; /* DRX_TEST_control_ln0_TYPE[00] - WO */ 7708 #endif /* IS_BIG_ENDIAN */ 7709 #if IS_LITTLE_ENDIAN 7710 uint32_t pat_chk_en_ln0 : 1; /* DRX_TEST_control_ln0_TYPE[00] - WO */ 7711 uint32_t pat_chk_unlock_dis_ln0 : 1; /* DRX_TEST_control_ln0_TYPE[01] - WO */ 7712 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln0_TYPE[15:02] - RSVD */ 7713 uint32_t reserved : 16; 7714 #endif /* IS_LITTLE_ENDIAN */ 7715 } fields; 7716 } DRX_TEST_control_ln0_TYPE; 7717 7718 typedef DRX_TEST_control_ln0_TYPE DRX_TEST_CONTROL_LN0_TYPE_T; 7719 7720 typedef union { 7721 uint32_t data; 7722 struct { 7723 #if IS_BIG_ENDIAN 7724 uint32_t reserved : 16; 7725 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln1_TYPE[15:02] - RSVD */ 7726 uint32_t pat_chk_unlock_dis_ln1 : 1; /* DRX_TEST_control_ln1_TYPE[01] - WO */ 7727 uint32_t pat_chk_en_ln1 : 1; /* DRX_TEST_control_ln1_TYPE[00] - WO */ 7728 #endif /* IS_BIG_ENDIAN */ 7729 #if IS_LITTLE_ENDIAN 7730 uint32_t pat_chk_en_ln1 : 1; /* DRX_TEST_control_ln1_TYPE[00] - WO */ 7731 uint32_t pat_chk_unlock_dis_ln1 : 1; /* DRX_TEST_control_ln1_TYPE[01] - WO */ 7732 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln1_TYPE[15:02] - RSVD */ 7733 uint32_t reserved : 16; 7734 #endif /* IS_LITTLE_ENDIAN */ 7735 } fields; 7736 } DRX_TEST_control_ln1_TYPE; 7737 7738 typedef DRX_TEST_control_ln1_TYPE DRX_TEST_CONTROL_LN1_TYPE_T; 7739 7740 typedef union { 7741 uint32_t data; 7742 struct { 7743 #if IS_BIG_ENDIAN 7744 uint32_t reserved : 16; 7745 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln2_TYPE[15:02] - RSVD */ 7746 uint32_t pat_chk_unlock_dis_ln2 : 1; /* DRX_TEST_control_ln2_TYPE[01] - WO */ 7747 uint32_t pat_chk_en_ln2 : 1; /* DRX_TEST_control_ln2_TYPE[00] - WO */ 7748 #endif /* IS_BIG_ENDIAN */ 7749 #if IS_LITTLE_ENDIAN 7750 uint32_t pat_chk_en_ln2 : 1; /* DRX_TEST_control_ln2_TYPE[00] - WO */ 7751 uint32_t pat_chk_unlock_dis_ln2 : 1; /* DRX_TEST_control_ln2_TYPE[01] - WO */ 7752 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln2_TYPE[15:02] - RSVD */ 7753 uint32_t reserved : 16; 7754 #endif /* IS_LITTLE_ENDIAN */ 7755 } fields; 7756 } DRX_TEST_control_ln2_TYPE; 7757 7758 typedef DRX_TEST_control_ln2_TYPE DRX_TEST_CONTROL_LN2_TYPE_T; 7759 7760 typedef union { 7761 uint32_t data; 7762 struct { 7763 #if IS_BIG_ENDIAN 7764 uint32_t reserved : 16; 7765 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln3_TYPE[15:02] - RSVD */ 7766 uint32_t pat_chk_unlock_dis_ln3 : 1; /* DRX_TEST_control_ln3_TYPE[01] - WO */ 7767 uint32_t pat_chk_en_ln3 : 1; /* DRX_TEST_control_ln3_TYPE[00] - WO */ 7768 #endif /* IS_BIG_ENDIAN */ 7769 #if IS_LITTLE_ENDIAN 7770 uint32_t pat_chk_en_ln3 : 1; /* DRX_TEST_control_ln3_TYPE[00] - WO */ 7771 uint32_t pat_chk_unlock_dis_ln3 : 1; /* DRX_TEST_control_ln3_TYPE[01] - WO */ 7772 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_control_ln3_TYPE[15:02] - RSVD */ 7773 uint32_t reserved : 16; 7774 #endif /* IS_LITTLE_ENDIAN */ 7775 } fields; 7776 } DRX_TEST_control_ln3_TYPE; 7777 7778 typedef DRX_TEST_control_ln3_TYPE DRX_TEST_CONTROL_LN3_TYPE_T; 7779 7780 typedef union { 7781 uint32_t data; 7782 struct { 7783 #if IS_BIG_ENDIAN 7784 uint32_t reserved : 16; 7785 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln0_TYPE[15:02] - RSVD */ 7786 uint32_t pat_chk_err_lh_ln0 : 1; /* DRX_TEST_status_ln0_TYPE[01] - RO */ 7787 uint32_t pat_chk_lock_ll_ln0 : 1; /* DRX_TEST_status_ln0_TYPE[00] - RO */ 7788 #endif /* IS_BIG_ENDIAN */ 7789 #if IS_LITTLE_ENDIAN 7790 uint32_t pat_chk_lock_ll_ln0 : 1; /* DRX_TEST_status_ln0_TYPE[00] - RO */ 7791 uint32_t pat_chk_err_lh_ln0 : 1; /* DRX_TEST_status_ln0_TYPE[01] - RO */ 7792 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln0_TYPE[15:02] - RSVD */ 7793 uint32_t reserved : 16; 7794 #endif /* IS_LITTLE_ENDIAN */ 7795 } fields; 7796 } DRX_TEST_status_ln0_TYPE; 7797 7798 typedef DRX_TEST_status_ln0_TYPE DRX_TEST_STATUS_LN0_TYPE_T; 7799 7800 typedef union { 7801 uint32_t data; 7802 struct { 7803 #if IS_BIG_ENDIAN 7804 uint32_t reserved : 16; 7805 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln1_TYPE[15:02] - RSVD */ 7806 uint32_t pat_chk_err_lh_ln1 : 1; /* DRX_TEST_status_ln1_TYPE[01] - RO */ 7807 uint32_t pat_chk_lock_ll_ln1 : 1; /* DRX_TEST_status_ln1_TYPE[00] - RO */ 7808 #endif /* IS_BIG_ENDIAN */ 7809 #if IS_LITTLE_ENDIAN 7810 uint32_t pat_chk_lock_ll_ln1 : 1; /* DRX_TEST_status_ln1_TYPE[00] - RO */ 7811 uint32_t pat_chk_err_lh_ln1 : 1; /* DRX_TEST_status_ln1_TYPE[01] - RO */ 7812 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln1_TYPE[15:02] - RSVD */ 7813 uint32_t reserved : 16; 7814 #endif /* IS_LITTLE_ENDIAN */ 7815 } fields; 7816 } DRX_TEST_status_ln1_TYPE; 7817 7818 typedef DRX_TEST_status_ln1_TYPE DRX_TEST_STATUS_LN1_TYPE_T; 7819 7820 typedef union { 7821 uint32_t data; 7822 struct { 7823 #if IS_BIG_ENDIAN 7824 uint32_t reserved : 16; 7825 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln2_TYPE[15:02] - RSVD */ 7826 uint32_t pat_chk_err_lh_ln2 : 1; /* DRX_TEST_status_ln2_TYPE[01] - RO */ 7827 uint32_t pat_chk_lock_ll_ln2 : 1; /* DRX_TEST_status_ln2_TYPE[00] - RO */ 7828 #endif /* IS_BIG_ENDIAN */ 7829 #if IS_LITTLE_ENDIAN 7830 uint32_t pat_chk_lock_ll_ln2 : 1; /* DRX_TEST_status_ln2_TYPE[00] - RO */ 7831 uint32_t pat_chk_err_lh_ln2 : 1; /* DRX_TEST_status_ln2_TYPE[01] - RO */ 7832 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln2_TYPE[15:02] - RSVD */ 7833 uint32_t reserved : 16; 7834 #endif /* IS_LITTLE_ENDIAN */ 7835 } fields; 7836 } DRX_TEST_status_ln2_TYPE; 7837 7838 typedef DRX_TEST_status_ln2_TYPE DRX_TEST_STATUS_LN2_TYPE_T; 7839 7840 typedef union { 7841 uint32_t data; 7842 struct { 7843 #if IS_BIG_ENDIAN 7844 uint32_t reserved : 16; 7845 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln3_TYPE[15:02] - RSVD */ 7846 uint32_t pat_chk_err_lh_ln3 : 1; /* DRX_TEST_status_ln3_TYPE[01] - RO */ 7847 uint32_t pat_chk_lock_ll_ln3 : 1; /* DRX_TEST_status_ln3_TYPE[00] - RO */ 7848 #endif /* IS_BIG_ENDIAN */ 7849 #if IS_LITTLE_ENDIAN 7850 uint32_t pat_chk_lock_ll_ln3 : 1; /* DRX_TEST_status_ln3_TYPE[00] - RO */ 7851 uint32_t pat_chk_err_lh_ln3 : 1; /* DRX_TEST_status_ln3_TYPE[01] - RO */ 7852 uint32_t reserved_for_eco_02 : 14; /* DRX_TEST_status_ln3_TYPE[15:02] - RSVD */ 7853 uint32_t reserved : 16; 7854 #endif /* IS_LITTLE_ENDIAN */ 7855 } fields; 7856 } DRX_TEST_status_ln3_TYPE; 7857 7858 typedef DRX_TEST_status_ln3_TYPE DRX_TEST_STATUS_LN3_TYPE_T; 7859 7860 7861 /*-----------------------------------------------*/ 7862 /* Structs for MERLIN_IF Bank */ 7863 /*-----------------------------------------------*/ 7864 typedef union { 7865 uint32_t data; 7866 struct { 7867 #if IS_BIG_ENDIAN 7868 uint32_t reserved : 16; 7869 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane0_TYPE[15:11] - RSVD */ 7870 uint32_t pmd_ext_los_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[10] - WO */ 7871 uint32_t pmd_ext_los_0_frcval : 1; /* MERLIN_IF_control1_lane0_TYPE[09] - WO */ 7872 uint32_t pmd_osr_mode_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[08] - WO */ 7873 uint32_t pmd_osr_mode_0_frcval : 4; /* MERLIN_IF_control1_lane0_TYPE[07:04] - WO */ 7874 uint32_t pmd_tx_disable_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[03] - WO */ 7875 uint32_t pmd_tx_disable_0_frcval : 1; /* MERLIN_IF_control1_lane0_TYPE[02] - WO */ 7876 uint32_t pmd_rx_dme_en_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[01] - WO */ 7877 uint32_t pmd_rx_dme_en_0_frcval : 1; /* MERLIN_IF_control1_lane0_TYPE[00] - WO */ 7878 #endif /* IS_BIG_ENDIAN */ 7879 #if IS_LITTLE_ENDIAN 7880 uint32_t pmd_rx_dme_en_0_frcval : 1; /* MERLIN_IF_control1_lane0_TYPE[00] - WO */ 7881 uint32_t pmd_rx_dme_en_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[01] - WO */ 7882 uint32_t pmd_tx_disable_0_frcval : 1; /* MERLIN_IF_control1_lane0_TYPE[02] - WO */ 7883 uint32_t pmd_tx_disable_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[03] - WO */ 7884 uint32_t pmd_osr_mode_0_frcval : 4; /* MERLIN_IF_control1_lane0_TYPE[07:04] - WO */ 7885 uint32_t pmd_osr_mode_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[08] - WO */ 7886 uint32_t pmd_ext_los_0_frcval : 1; /* MERLIN_IF_control1_lane0_TYPE[09] - WO */ 7887 uint32_t pmd_ext_los_0_frc : 1; /* MERLIN_IF_control1_lane0_TYPE[10] - WO */ 7888 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane0_TYPE[15:11] - RSVD */ 7889 uint32_t reserved : 16; 7890 #endif /* IS_LITTLE_ENDIAN */ 7891 } fields; 7892 } MERLIN_IF_control1_lane0_TYPE; 7893 7894 typedef MERLIN_IF_control1_lane0_TYPE MERLIN_IF_CONTROL1_LANE0_TYPE_T; 7895 7896 typedef union { 7897 uint32_t data; 7898 struct { 7899 #if IS_BIG_ENDIAN 7900 uint32_t reserved : 16; 7901 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane1_TYPE[15:11] - RSVD */ 7902 uint32_t pmd_ext_los_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[10] - WO */ 7903 uint32_t pmd_ext_los_1_frcval : 1; /* MERLIN_IF_control1_lane1_TYPE[09] - WO */ 7904 uint32_t pmd_osr_mode_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[08] - WO */ 7905 uint32_t pmd_osr_mode_1_frcval : 4; /* MERLIN_IF_control1_lane1_TYPE[07:04] - WO */ 7906 uint32_t pmd_tx_disable_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[03] - WO */ 7907 uint32_t pmd_tx_disable_1_frcval : 1; /* MERLIN_IF_control1_lane1_TYPE[02] - WO */ 7908 uint32_t pmd_rx_dme_en_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[01] - WO */ 7909 uint32_t pmd_rx_dme_en_1_frcval : 1; /* MERLIN_IF_control1_lane1_TYPE[00] - WO */ 7910 #endif /* IS_BIG_ENDIAN */ 7911 #if IS_LITTLE_ENDIAN 7912 uint32_t pmd_rx_dme_en_1_frcval : 1; /* MERLIN_IF_control1_lane1_TYPE[00] - WO */ 7913 uint32_t pmd_rx_dme_en_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[01] - WO */ 7914 uint32_t pmd_tx_disable_1_frcval : 1; /* MERLIN_IF_control1_lane1_TYPE[02] - WO */ 7915 uint32_t pmd_tx_disable_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[03] - WO */ 7916 uint32_t pmd_osr_mode_1_frcval : 4; /* MERLIN_IF_control1_lane1_TYPE[07:04] - WO */ 7917 uint32_t pmd_osr_mode_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[08] - WO */ 7918 uint32_t pmd_ext_los_1_frcval : 1; /* MERLIN_IF_control1_lane1_TYPE[09] - WO */ 7919 uint32_t pmd_ext_los_1_frc : 1; /* MERLIN_IF_control1_lane1_TYPE[10] - WO */ 7920 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane1_TYPE[15:11] - RSVD */ 7921 uint32_t reserved : 16; 7922 #endif /* IS_LITTLE_ENDIAN */ 7923 } fields; 7924 } MERLIN_IF_control1_lane1_TYPE; 7925 7926 typedef MERLIN_IF_control1_lane1_TYPE MERLIN_IF_CONTROL1_LANE1_TYPE_T; 7927 7928 typedef union { 7929 uint32_t data; 7930 struct { 7931 #if IS_BIG_ENDIAN 7932 uint32_t reserved : 16; 7933 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane2_TYPE[15:11] - RSVD */ 7934 uint32_t pmd_ext_los_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[10] - WO */ 7935 uint32_t pmd_ext_los_2_frcval : 1; /* MERLIN_IF_control1_lane2_TYPE[09] - WO */ 7936 uint32_t pmd_osr_mode_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[08] - WO */ 7937 uint32_t pmd_osr_mode_2_frcval : 4; /* MERLIN_IF_control1_lane2_TYPE[07:04] - WO */ 7938 uint32_t pmd_tx_disable_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[03] - WO */ 7939 uint32_t pmd_tx_disable_2_frcval : 1; /* MERLIN_IF_control1_lane2_TYPE[02] - WO */ 7940 uint32_t pmd_rx_dme_en_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[01] - WO */ 7941 uint32_t pmd_rx_dme_en_2_frcval : 1; /* MERLIN_IF_control1_lane2_TYPE[00] - WO */ 7942 #endif /* IS_BIG_ENDIAN */ 7943 #if IS_LITTLE_ENDIAN 7944 uint32_t pmd_rx_dme_en_2_frcval : 1; /* MERLIN_IF_control1_lane2_TYPE[00] - WO */ 7945 uint32_t pmd_rx_dme_en_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[01] - WO */ 7946 uint32_t pmd_tx_disable_2_frcval : 1; /* MERLIN_IF_control1_lane2_TYPE[02] - WO */ 7947 uint32_t pmd_tx_disable_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[03] - WO */ 7948 uint32_t pmd_osr_mode_2_frcval : 4; /* MERLIN_IF_control1_lane2_TYPE[07:04] - WO */ 7949 uint32_t pmd_osr_mode_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[08] - WO */ 7950 uint32_t pmd_ext_los_2_frcval : 1; /* MERLIN_IF_control1_lane2_TYPE[09] - WO */ 7951 uint32_t pmd_ext_los_2_frc : 1; /* MERLIN_IF_control1_lane2_TYPE[10] - WO */ 7952 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane2_TYPE[15:11] - RSVD */ 7953 uint32_t reserved : 16; 7954 #endif /* IS_LITTLE_ENDIAN */ 7955 } fields; 7956 } MERLIN_IF_control1_lane2_TYPE; 7957 7958 typedef MERLIN_IF_control1_lane2_TYPE MERLIN_IF_CONTROL1_LANE2_TYPE_T; 7959 7960 typedef union { 7961 uint32_t data; 7962 struct { 7963 #if IS_BIG_ENDIAN 7964 uint32_t reserved : 16; 7965 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane3_TYPE[15:11] - RSVD */ 7966 uint32_t pmd_ext_los_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[10] - WO */ 7967 uint32_t pmd_ext_los_3_frcval : 1; /* MERLIN_IF_control1_lane3_TYPE[09] - WO */ 7968 uint32_t pmd_osr_mode_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[08] - WO */ 7969 uint32_t pmd_osr_mode_3_frcval : 4; /* MERLIN_IF_control1_lane3_TYPE[07:04] - WO */ 7970 uint32_t pmd_tx_disable_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[03] - WO */ 7971 uint32_t pmd_tx_disable_3_frcval : 1; /* MERLIN_IF_control1_lane3_TYPE[02] - WO */ 7972 uint32_t pmd_rx_dme_en_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[01] - WO */ 7973 uint32_t pmd_rx_dme_en_3_frcval : 1; /* MERLIN_IF_control1_lane3_TYPE[00] - WO */ 7974 #endif /* IS_BIG_ENDIAN */ 7975 #if IS_LITTLE_ENDIAN 7976 uint32_t pmd_rx_dme_en_3_frcval : 1; /* MERLIN_IF_control1_lane3_TYPE[00] - WO */ 7977 uint32_t pmd_rx_dme_en_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[01] - WO */ 7978 uint32_t pmd_tx_disable_3_frcval : 1; /* MERLIN_IF_control1_lane3_TYPE[02] - WO */ 7979 uint32_t pmd_tx_disable_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[03] - WO */ 7980 uint32_t pmd_osr_mode_3_frcval : 4; /* MERLIN_IF_control1_lane3_TYPE[07:04] - WO */ 7981 uint32_t pmd_osr_mode_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[08] - WO */ 7982 uint32_t pmd_ext_los_3_frcval : 1; /* MERLIN_IF_control1_lane3_TYPE[09] - WO */ 7983 uint32_t pmd_ext_los_3_frc : 1; /* MERLIN_IF_control1_lane3_TYPE[10] - WO */ 7984 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane3_TYPE[15:11] - RSVD */ 7985 uint32_t reserved : 16; 7986 #endif /* IS_LITTLE_ENDIAN */ 7987 } fields; 7988 } MERLIN_IF_control1_lane3_TYPE; 7989 7990 typedef MERLIN_IF_control1_lane3_TYPE MERLIN_IF_CONTROL1_LANE3_TYPE_T; 7991 7992 typedef union { 7993 uint32_t data; 7994 struct { 7995 #if IS_BIG_ENDIAN 7996 uint32_t reserved : 16; 7997 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane4_TYPE[15:11] - RSVD */ 7998 uint32_t pmd_ext_los_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[10] - WO */ 7999 uint32_t pmd_ext_los_4_frcval : 1; /* MERLIN_IF_control1_lane4_TYPE[09] - WO */ 8000 uint32_t pmd_osr_mode_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[08] - WO */ 8001 uint32_t pmd_osr_mode_4_frcval : 4; /* MERLIN_IF_control1_lane4_TYPE[07:04] - WO */ 8002 uint32_t pmd_tx_disable_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[03] - WO */ 8003 uint32_t pmd_tx_disable_4_frcval : 1; /* MERLIN_IF_control1_lane4_TYPE[02] - WO */ 8004 uint32_t pmd_rx_dme_en_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[01] - WO */ 8005 uint32_t pmd_rx_dme_en_4_frcval : 1; /* MERLIN_IF_control1_lane4_TYPE[00] - WO */ 8006 #endif /* IS_BIG_ENDIAN */ 8007 #if IS_LITTLE_ENDIAN 8008 uint32_t pmd_rx_dme_en_4_frcval : 1; /* MERLIN_IF_control1_lane4_TYPE[00] - WO */ 8009 uint32_t pmd_rx_dme_en_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[01] - WO */ 8010 uint32_t pmd_tx_disable_4_frcval : 1; /* MERLIN_IF_control1_lane4_TYPE[02] - WO */ 8011 uint32_t pmd_tx_disable_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[03] - WO */ 8012 uint32_t pmd_osr_mode_4_frcval : 4; /* MERLIN_IF_control1_lane4_TYPE[07:04] - WO */ 8013 uint32_t pmd_osr_mode_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[08] - WO */ 8014 uint32_t pmd_ext_los_4_frcval : 1; /* MERLIN_IF_control1_lane4_TYPE[09] - WO */ 8015 uint32_t pmd_ext_los_4_frc : 1; /* MERLIN_IF_control1_lane4_TYPE[10] - WO */ 8016 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane4_TYPE[15:11] - RSVD */ 8017 uint32_t reserved : 16; 8018 #endif /* IS_LITTLE_ENDIAN */ 8019 } fields; 8020 } MERLIN_IF_control1_lane4_TYPE; 8021 8022 typedef MERLIN_IF_control1_lane4_TYPE MERLIN_IF_CONTROL1_LANE4_TYPE_T; 8023 8024 typedef union { 8025 uint32_t data; 8026 struct { 8027 #if IS_BIG_ENDIAN 8028 uint32_t reserved : 16; 8029 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane5_TYPE[15:11] - RSVD */ 8030 uint32_t pmd_ext_los_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[10] - WO */ 8031 uint32_t pmd_ext_los_5_frcval : 1; /* MERLIN_IF_control1_lane5_TYPE[09] - WO */ 8032 uint32_t pmd_osr_mode_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[08] - WO */ 8033 uint32_t pmd_osr_mode_5_frcval : 4; /* MERLIN_IF_control1_lane5_TYPE[07:04] - WO */ 8034 uint32_t pmd_tx_disable_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[03] - WO */ 8035 uint32_t pmd_tx_disable_5_frcval : 1; /* MERLIN_IF_control1_lane5_TYPE[02] - WO */ 8036 uint32_t pmd_rx_dme_en_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[01] - WO */ 8037 uint32_t pmd_rx_dme_en_5_frcval : 1; /* MERLIN_IF_control1_lane5_TYPE[00] - WO */ 8038 #endif /* IS_BIG_ENDIAN */ 8039 #if IS_LITTLE_ENDIAN 8040 uint32_t pmd_rx_dme_en_5_frcval : 1; /* MERLIN_IF_control1_lane5_TYPE[00] - WO */ 8041 uint32_t pmd_rx_dme_en_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[01] - WO */ 8042 uint32_t pmd_tx_disable_5_frcval : 1; /* MERLIN_IF_control1_lane5_TYPE[02] - WO */ 8043 uint32_t pmd_tx_disable_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[03] - WO */ 8044 uint32_t pmd_osr_mode_5_frcval : 4; /* MERLIN_IF_control1_lane5_TYPE[07:04] - WO */ 8045 uint32_t pmd_osr_mode_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[08] - WO */ 8046 uint32_t pmd_ext_los_5_frcval : 1; /* MERLIN_IF_control1_lane5_TYPE[09] - WO */ 8047 uint32_t pmd_ext_los_5_frc : 1; /* MERLIN_IF_control1_lane5_TYPE[10] - WO */ 8048 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane5_TYPE[15:11] - RSVD */ 8049 uint32_t reserved : 16; 8050 #endif /* IS_LITTLE_ENDIAN */ 8051 } fields; 8052 } MERLIN_IF_control1_lane5_TYPE; 8053 8054 typedef MERLIN_IF_control1_lane5_TYPE MERLIN_IF_CONTROL1_LANE5_TYPE_T; 8055 8056 typedef union { 8057 uint32_t data; 8058 struct { 8059 #if IS_BIG_ENDIAN 8060 uint32_t reserved : 16; 8061 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane6_TYPE[15:11] - RSVD */ 8062 uint32_t pmd_ext_los_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[10] - WO */ 8063 uint32_t pmd_ext_los_6_frcval : 1; /* MERLIN_IF_control1_lane6_TYPE[09] - WO */ 8064 uint32_t pmd_osr_mode_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[08] - WO */ 8065 uint32_t pmd_osr_mode_6_frcval : 4; /* MERLIN_IF_control1_lane6_TYPE[07:04] - WO */ 8066 uint32_t pmd_tx_disable_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[03] - WO */ 8067 uint32_t pmd_tx_disable_6_frcval : 1; /* MERLIN_IF_control1_lane6_TYPE[02] - WO */ 8068 uint32_t pmd_rx_dme_en_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[01] - WO */ 8069 uint32_t pmd_rx_dme_en_6_frcval : 1; /* MERLIN_IF_control1_lane6_TYPE[00] - WO */ 8070 #endif /* IS_BIG_ENDIAN */ 8071 #if IS_LITTLE_ENDIAN 8072 uint32_t pmd_rx_dme_en_6_frcval : 1; /* MERLIN_IF_control1_lane6_TYPE[00] - WO */ 8073 uint32_t pmd_rx_dme_en_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[01] - WO */ 8074 uint32_t pmd_tx_disable_6_frcval : 1; /* MERLIN_IF_control1_lane6_TYPE[02] - WO */ 8075 uint32_t pmd_tx_disable_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[03] - WO */ 8076 uint32_t pmd_osr_mode_6_frcval : 4; /* MERLIN_IF_control1_lane6_TYPE[07:04] - WO */ 8077 uint32_t pmd_osr_mode_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[08] - WO */ 8078 uint32_t pmd_ext_los_6_frcval : 1; /* MERLIN_IF_control1_lane6_TYPE[09] - WO */ 8079 uint32_t pmd_ext_los_6_frc : 1; /* MERLIN_IF_control1_lane6_TYPE[10] - WO */ 8080 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane6_TYPE[15:11] - RSVD */ 8081 uint32_t reserved : 16; 8082 #endif /* IS_LITTLE_ENDIAN */ 8083 } fields; 8084 } MERLIN_IF_control1_lane6_TYPE; 8085 8086 typedef MERLIN_IF_control1_lane6_TYPE MERLIN_IF_CONTROL1_LANE6_TYPE_T; 8087 8088 typedef union { 8089 uint32_t data; 8090 struct { 8091 #if IS_BIG_ENDIAN 8092 uint32_t reserved : 16; 8093 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane7_TYPE[15:11] - RSVD */ 8094 uint32_t pmd_ext_los_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[10] - WO */ 8095 uint32_t pmd_ext_los_7_frcval : 1; /* MERLIN_IF_control1_lane7_TYPE[09] - WO */ 8096 uint32_t pmd_osr_mode_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[08] - WO */ 8097 uint32_t pmd_osr_mode_7_frcval : 4; /* MERLIN_IF_control1_lane7_TYPE[07:04] - WO */ 8098 uint32_t pmd_tx_disable_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[03] - WO */ 8099 uint32_t pmd_tx_disable_7_frcval : 1; /* MERLIN_IF_control1_lane7_TYPE[02] - WO */ 8100 uint32_t pmd_rx_dme_en_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[01] - WO */ 8101 uint32_t pmd_rx_dme_en_7_frcval : 1; /* MERLIN_IF_control1_lane7_TYPE[00] - WO */ 8102 #endif /* IS_BIG_ENDIAN */ 8103 #if IS_LITTLE_ENDIAN 8104 uint32_t pmd_rx_dme_en_7_frcval : 1; /* MERLIN_IF_control1_lane7_TYPE[00] - WO */ 8105 uint32_t pmd_rx_dme_en_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[01] - WO */ 8106 uint32_t pmd_tx_disable_7_frcval : 1; /* MERLIN_IF_control1_lane7_TYPE[02] - WO */ 8107 uint32_t pmd_tx_disable_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[03] - WO */ 8108 uint32_t pmd_osr_mode_7_frcval : 4; /* MERLIN_IF_control1_lane7_TYPE[07:04] - WO */ 8109 uint32_t pmd_osr_mode_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[08] - WO */ 8110 uint32_t pmd_ext_los_7_frcval : 1; /* MERLIN_IF_control1_lane7_TYPE[09] - WO */ 8111 uint32_t pmd_ext_los_7_frc : 1; /* MERLIN_IF_control1_lane7_TYPE[10] - WO */ 8112 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane7_TYPE[15:11] - RSVD */ 8113 uint32_t reserved : 16; 8114 #endif /* IS_LITTLE_ENDIAN */ 8115 } fields; 8116 } MERLIN_IF_control1_lane7_TYPE; 8117 8118 typedef MERLIN_IF_control1_lane7_TYPE MERLIN_IF_CONTROL1_LANE7_TYPE_T; 8119 8120 typedef union { 8121 uint32_t data; 8122 struct { 8123 #if IS_BIG_ENDIAN 8124 uint32_t reserved : 16; 8125 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane8_TYPE[15:11] - RSVD */ 8126 uint32_t pmd_ext_los_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[10] - WO */ 8127 uint32_t pmd_ext_los_8_frcval : 1; /* MERLIN_IF_control1_lane8_TYPE[09] - WO */ 8128 uint32_t pmd_osr_mode_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[08] - WO */ 8129 uint32_t pmd_osr_mode_8_frcval : 4; /* MERLIN_IF_control1_lane8_TYPE[07:04] - WO */ 8130 uint32_t pmd_tx_disable_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[03] - WO */ 8131 uint32_t pmd_tx_disable_8_frcval : 1; /* MERLIN_IF_control1_lane8_TYPE[02] - WO */ 8132 uint32_t pmd_rx_dme_en_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[01] - WO */ 8133 uint32_t pmd_rx_dme_en_8_frcval : 1; /* MERLIN_IF_control1_lane8_TYPE[00] - WO */ 8134 #endif /* IS_BIG_ENDIAN */ 8135 #if IS_LITTLE_ENDIAN 8136 uint32_t pmd_rx_dme_en_8_frcval : 1; /* MERLIN_IF_control1_lane8_TYPE[00] - WO */ 8137 uint32_t pmd_rx_dme_en_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[01] - WO */ 8138 uint32_t pmd_tx_disable_8_frcval : 1; /* MERLIN_IF_control1_lane8_TYPE[02] - WO */ 8139 uint32_t pmd_tx_disable_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[03] - WO */ 8140 uint32_t pmd_osr_mode_8_frcval : 4; /* MERLIN_IF_control1_lane8_TYPE[07:04] - WO */ 8141 uint32_t pmd_osr_mode_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[08] - WO */ 8142 uint32_t pmd_ext_los_8_frcval : 1; /* MERLIN_IF_control1_lane8_TYPE[09] - WO */ 8143 uint32_t pmd_ext_los_8_frc : 1; /* MERLIN_IF_control1_lane8_TYPE[10] - WO */ 8144 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane8_TYPE[15:11] - RSVD */ 8145 uint32_t reserved : 16; 8146 #endif /* IS_LITTLE_ENDIAN */ 8147 } fields; 8148 } MERLIN_IF_control1_lane8_TYPE; 8149 8150 typedef MERLIN_IF_control1_lane8_TYPE MERLIN_IF_CONTROL1_LANE8_TYPE_T; 8151 8152 typedef union { 8153 uint32_t data; 8154 struct { 8155 #if IS_BIG_ENDIAN 8156 uint32_t reserved : 16; 8157 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane9_TYPE[15:11] - RSVD */ 8158 uint32_t pmd_ext_los_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[10] - WO */ 8159 uint32_t pmd_ext_los_9_frcval : 1; /* MERLIN_IF_control1_lane9_TYPE[09] - WO */ 8160 uint32_t pmd_osr_mode_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[08] - WO */ 8161 uint32_t pmd_osr_mode_9_frcval : 4; /* MERLIN_IF_control1_lane9_TYPE[07:04] - WO */ 8162 uint32_t pmd_tx_disable_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[03] - WO */ 8163 uint32_t pmd_tx_disable_9_frcval : 1; /* MERLIN_IF_control1_lane9_TYPE[02] - WO */ 8164 uint32_t pmd_rx_dme_en_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[01] - WO */ 8165 uint32_t pmd_rx_dme_en_9_frcval : 1; /* MERLIN_IF_control1_lane9_TYPE[00] - WO */ 8166 #endif /* IS_BIG_ENDIAN */ 8167 #if IS_LITTLE_ENDIAN 8168 uint32_t pmd_rx_dme_en_9_frcval : 1; /* MERLIN_IF_control1_lane9_TYPE[00] - WO */ 8169 uint32_t pmd_rx_dme_en_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[01] - WO */ 8170 uint32_t pmd_tx_disable_9_frcval : 1; /* MERLIN_IF_control1_lane9_TYPE[02] - WO */ 8171 uint32_t pmd_tx_disable_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[03] - WO */ 8172 uint32_t pmd_osr_mode_9_frcval : 4; /* MERLIN_IF_control1_lane9_TYPE[07:04] - WO */ 8173 uint32_t pmd_osr_mode_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[08] - WO */ 8174 uint32_t pmd_ext_los_9_frcval : 1; /* MERLIN_IF_control1_lane9_TYPE[09] - WO */ 8175 uint32_t pmd_ext_los_9_frc : 1; /* MERLIN_IF_control1_lane9_TYPE[10] - WO */ 8176 uint32_t reserved_11 : 5; /* MERLIN_IF_control1_lane9_TYPE[15:11] - RSVD */ 8177 uint32_t reserved : 16; 8178 #endif /* IS_LITTLE_ENDIAN */ 8179 } fields; 8180 } MERLIN_IF_control1_lane9_TYPE; 8181 8182 typedef MERLIN_IF_control1_lane9_TYPE MERLIN_IF_CONTROL1_LANE9_TYPE_T; 8183 8184 typedef union { 8185 uint32_t data; 8186 struct { 8187 #if IS_BIG_ENDIAN 8188 uint32_t reserved : 16; 8189 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane0_TYPE[15:08] - RSVD */ 8190 uint32_t pmd_ln_tx_h_pwrdn_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[07] - WO */ 8191 uint32_t pmd_ln_tx_h_pwrdn_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[06] - WO */ 8192 uint32_t pmd_ln_rx_h_pwrdn_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[05] - WO */ 8193 uint32_t pmd_ln_rx_h_pwrdn_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[04] - WO */ 8194 uint32_t pmd_ln_dp_h_rstb_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[03] - WO */ 8195 uint32_t pmd_ln_dp_h_rstb_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[02] - WO */ 8196 uint32_t pmd_ln_h_rstb_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[01] - WO */ 8197 uint32_t pmd_ln_h_rstb_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[00] - WO */ 8198 #endif /* IS_BIG_ENDIAN */ 8199 #if IS_LITTLE_ENDIAN 8200 uint32_t pmd_ln_h_rstb_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[00] - WO */ 8201 uint32_t pmd_ln_h_rstb_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[01] - WO */ 8202 uint32_t pmd_ln_dp_h_rstb_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[02] - WO */ 8203 uint32_t pmd_ln_dp_h_rstb_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[03] - WO */ 8204 uint32_t pmd_ln_rx_h_pwrdn_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[04] - WO */ 8205 uint32_t pmd_ln_rx_h_pwrdn_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[05] - WO */ 8206 uint32_t pmd_ln_tx_h_pwrdn_0_frcval : 1; /* MERLIN_IF_control2_lane0_TYPE[06] - WO */ 8207 uint32_t pmd_ln_tx_h_pwrdn_0_frc : 1; /* MERLIN_IF_control2_lane0_TYPE[07] - WO */ 8208 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane0_TYPE[15:08] - RSVD */ 8209 uint32_t reserved : 16; 8210 #endif /* IS_LITTLE_ENDIAN */ 8211 } fields; 8212 } MERLIN_IF_control2_lane0_TYPE; 8213 8214 typedef MERLIN_IF_control2_lane0_TYPE MERLIN_IF_CONTROL2_LANE0_TYPE_T; 8215 8216 typedef union { 8217 uint32_t data; 8218 struct { 8219 #if IS_BIG_ENDIAN 8220 uint32_t reserved : 16; 8221 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane1_TYPE[15:08] - RSVD */ 8222 uint32_t pmd_ln_tx_h_pwrdn_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[07] - WO */ 8223 uint32_t pmd_ln_tx_h_pwrdn_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[06] - WO */ 8224 uint32_t pmd_ln_rx_h_pwrdn_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[05] - WO */ 8225 uint32_t pmd_ln_rx_h_pwrdn_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[04] - WO */ 8226 uint32_t pmd_ln_dp_h_rstb_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[03] - WO */ 8227 uint32_t pmd_ln_dp_h_rstb_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[02] - WO */ 8228 uint32_t pmd_ln_h_rstb_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[01] - WO */ 8229 uint32_t pmd_ln_h_rstb_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[00] - WO */ 8230 #endif /* IS_BIG_ENDIAN */ 8231 #if IS_LITTLE_ENDIAN 8232 uint32_t pmd_ln_h_rstb_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[00] - WO */ 8233 uint32_t pmd_ln_h_rstb_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[01] - WO */ 8234 uint32_t pmd_ln_dp_h_rstb_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[02] - WO */ 8235 uint32_t pmd_ln_dp_h_rstb_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[03] - WO */ 8236 uint32_t pmd_ln_rx_h_pwrdn_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[04] - WO */ 8237 uint32_t pmd_ln_rx_h_pwrdn_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[05] - WO */ 8238 uint32_t pmd_ln_tx_h_pwrdn_1_frcval : 1; /* MERLIN_IF_control2_lane1_TYPE[06] - WO */ 8239 uint32_t pmd_ln_tx_h_pwrdn_1_frc : 1; /* MERLIN_IF_control2_lane1_TYPE[07] - WO */ 8240 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane1_TYPE[15:08] - RSVD */ 8241 uint32_t reserved : 16; 8242 #endif /* IS_LITTLE_ENDIAN */ 8243 } fields; 8244 } MERLIN_IF_control2_lane1_TYPE; 8245 8246 typedef MERLIN_IF_control2_lane1_TYPE MERLIN_IF_CONTROL2_LANE1_TYPE_T; 8247 8248 typedef union { 8249 uint32_t data; 8250 struct { 8251 #if IS_BIG_ENDIAN 8252 uint32_t reserved : 16; 8253 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane2_TYPE[15:08] - RSVD */ 8254 uint32_t pmd_ln_tx_h_pwrdn_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[07] - WO */ 8255 uint32_t pmd_ln_tx_h_pwrdn_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[06] - WO */ 8256 uint32_t pmd_ln_rx_h_pwrdn_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[05] - WO */ 8257 uint32_t pmd_ln_rx_h_pwrdn_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[04] - WO */ 8258 uint32_t pmd_ln_dp_h_rstb_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[03] - WO */ 8259 uint32_t pmd_ln_dp_h_rstb_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[02] - WO */ 8260 uint32_t pmd_ln_h_rstb_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[01] - WO */ 8261 uint32_t pmd_ln_h_rstb_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[00] - WO */ 8262 #endif /* IS_BIG_ENDIAN */ 8263 #if IS_LITTLE_ENDIAN 8264 uint32_t pmd_ln_h_rstb_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[00] - WO */ 8265 uint32_t pmd_ln_h_rstb_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[01] - WO */ 8266 uint32_t pmd_ln_dp_h_rstb_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[02] - WO */ 8267 uint32_t pmd_ln_dp_h_rstb_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[03] - WO */ 8268 uint32_t pmd_ln_rx_h_pwrdn_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[04] - WO */ 8269 uint32_t pmd_ln_rx_h_pwrdn_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[05] - WO */ 8270 uint32_t pmd_ln_tx_h_pwrdn_2_frcval : 1; /* MERLIN_IF_control2_lane2_TYPE[06] - WO */ 8271 uint32_t pmd_ln_tx_h_pwrdn_2_frc : 1; /* MERLIN_IF_control2_lane2_TYPE[07] - WO */ 8272 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane2_TYPE[15:08] - RSVD */ 8273 uint32_t reserved : 16; 8274 #endif /* IS_LITTLE_ENDIAN */ 8275 } fields; 8276 } MERLIN_IF_control2_lane2_TYPE; 8277 8278 typedef MERLIN_IF_control2_lane2_TYPE MERLIN_IF_CONTROL2_LANE2_TYPE_T; 8279 8280 typedef union { 8281 uint32_t data; 8282 struct { 8283 #if IS_BIG_ENDIAN 8284 uint32_t reserved : 16; 8285 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane3_TYPE[15:08] - RSVD */ 8286 uint32_t pmd_ln_tx_h_pwrdn_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[07] - WO */ 8287 uint32_t pmd_ln_tx_h_pwrdn_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[06] - WO */ 8288 uint32_t pmd_ln_rx_h_pwrdn_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[05] - WO */ 8289 uint32_t pmd_ln_rx_h_pwrdn_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[04] - WO */ 8290 uint32_t pmd_ln_dp_h_rstb_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[03] - WO */ 8291 uint32_t pmd_ln_dp_h_rstb_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[02] - WO */ 8292 uint32_t pmd_ln_h_rstb_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[01] - WO */ 8293 uint32_t pmd_ln_h_rstb_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[00] - WO */ 8294 #endif /* IS_BIG_ENDIAN */ 8295 #if IS_LITTLE_ENDIAN 8296 uint32_t pmd_ln_h_rstb_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[00] - WO */ 8297 uint32_t pmd_ln_h_rstb_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[01] - WO */ 8298 uint32_t pmd_ln_dp_h_rstb_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[02] - WO */ 8299 uint32_t pmd_ln_dp_h_rstb_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[03] - WO */ 8300 uint32_t pmd_ln_rx_h_pwrdn_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[04] - WO */ 8301 uint32_t pmd_ln_rx_h_pwrdn_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[05] - WO */ 8302 uint32_t pmd_ln_tx_h_pwrdn_3_frcval : 1; /* MERLIN_IF_control2_lane3_TYPE[06] - WO */ 8303 uint32_t pmd_ln_tx_h_pwrdn_3_frc : 1; /* MERLIN_IF_control2_lane3_TYPE[07] - WO */ 8304 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane3_TYPE[15:08] - RSVD */ 8305 uint32_t reserved : 16; 8306 #endif /* IS_LITTLE_ENDIAN */ 8307 } fields; 8308 } MERLIN_IF_control2_lane3_TYPE; 8309 8310 typedef MERLIN_IF_control2_lane3_TYPE MERLIN_IF_CONTROL2_LANE3_TYPE_T; 8311 8312 typedef union { 8313 uint32_t data; 8314 struct { 8315 #if IS_BIG_ENDIAN 8316 uint32_t reserved : 16; 8317 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane4_TYPE[15:08] - RSVD */ 8318 uint32_t pmd_ln_tx_h_pwrdn_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[07] - WO */ 8319 uint32_t pmd_ln_tx_h_pwrdn_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[06] - WO */ 8320 uint32_t pmd_ln_rx_h_pwrdn_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[05] - WO */ 8321 uint32_t pmd_ln_rx_h_pwrdn_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[04] - WO */ 8322 uint32_t pmd_ln_dp_h_rstb_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[03] - WO */ 8323 uint32_t pmd_ln_dp_h_rstb_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[02] - WO */ 8324 uint32_t pmd_ln_h_rstb_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[01] - WO */ 8325 uint32_t pmd_ln_h_rstb_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[00] - WO */ 8326 #endif /* IS_BIG_ENDIAN */ 8327 #if IS_LITTLE_ENDIAN 8328 uint32_t pmd_ln_h_rstb_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[00] - WO */ 8329 uint32_t pmd_ln_h_rstb_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[01] - WO */ 8330 uint32_t pmd_ln_dp_h_rstb_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[02] - WO */ 8331 uint32_t pmd_ln_dp_h_rstb_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[03] - WO */ 8332 uint32_t pmd_ln_rx_h_pwrdn_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[04] - WO */ 8333 uint32_t pmd_ln_rx_h_pwrdn_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[05] - WO */ 8334 uint32_t pmd_ln_tx_h_pwrdn_4_frcval : 1; /* MERLIN_IF_control2_lane4_TYPE[06] - WO */ 8335 uint32_t pmd_ln_tx_h_pwrdn_4_frc : 1; /* MERLIN_IF_control2_lane4_TYPE[07] - WO */ 8336 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane4_TYPE[15:08] - RSVD */ 8337 uint32_t reserved : 16; 8338 #endif /* IS_LITTLE_ENDIAN */ 8339 } fields; 8340 } MERLIN_IF_control2_lane4_TYPE; 8341 8342 typedef MERLIN_IF_control2_lane4_TYPE MERLIN_IF_CONTROL2_LANE4_TYPE_T; 8343 8344 typedef union { 8345 uint32_t data; 8346 struct { 8347 #if IS_BIG_ENDIAN 8348 uint32_t reserved : 16; 8349 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane5_TYPE[15:08] - RSVD */ 8350 uint32_t pmd_ln_tx_h_pwrdn_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[07] - WO */ 8351 uint32_t pmd_ln_tx_h_pwrdn_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[06] - WO */ 8352 uint32_t pmd_ln_rx_h_pwrdn_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[05] - WO */ 8353 uint32_t pmd_ln_rx_h_pwrdn_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[04] - WO */ 8354 uint32_t pmd_ln_dp_h_rstb_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[03] - WO */ 8355 uint32_t pmd_ln_dp_h_rstb_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[02] - WO */ 8356 uint32_t pmd_ln_h_rstb_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[01] - WO */ 8357 uint32_t pmd_ln_h_rstb_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[00] - WO */ 8358 #endif /* IS_BIG_ENDIAN */ 8359 #if IS_LITTLE_ENDIAN 8360 uint32_t pmd_ln_h_rstb_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[00] - WO */ 8361 uint32_t pmd_ln_h_rstb_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[01] - WO */ 8362 uint32_t pmd_ln_dp_h_rstb_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[02] - WO */ 8363 uint32_t pmd_ln_dp_h_rstb_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[03] - WO */ 8364 uint32_t pmd_ln_rx_h_pwrdn_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[04] - WO */ 8365 uint32_t pmd_ln_rx_h_pwrdn_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[05] - WO */ 8366 uint32_t pmd_ln_tx_h_pwrdn_5_frcval : 1; /* MERLIN_IF_control2_lane5_TYPE[06] - WO */ 8367 uint32_t pmd_ln_tx_h_pwrdn_5_frc : 1; /* MERLIN_IF_control2_lane5_TYPE[07] - WO */ 8368 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane5_TYPE[15:08] - RSVD */ 8369 uint32_t reserved : 16; 8370 #endif /* IS_LITTLE_ENDIAN */ 8371 } fields; 8372 } MERLIN_IF_control2_lane5_TYPE; 8373 8374 typedef MERLIN_IF_control2_lane5_TYPE MERLIN_IF_CONTROL2_LANE5_TYPE_T; 8375 8376 typedef union { 8377 uint32_t data; 8378 struct { 8379 #if IS_BIG_ENDIAN 8380 uint32_t reserved : 16; 8381 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane6_TYPE[15:08] - RSVD */ 8382 uint32_t pmd_ln_tx_h_pwrdn_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[07] - WO */ 8383 uint32_t pmd_ln_tx_h_pwrdn_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[06] - WO */ 8384 uint32_t pmd_ln_rx_h_pwrdn_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[05] - WO */ 8385 uint32_t pmd_ln_rx_h_pwrdn_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[04] - WO */ 8386 uint32_t pmd_ln_dp_h_rstb_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[03] - WO */ 8387 uint32_t pmd_ln_dp_h_rstb_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[02] - WO */ 8388 uint32_t pmd_ln_h_rstb_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[01] - WO */ 8389 uint32_t pmd_ln_h_rstb_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[00] - WO */ 8390 #endif /* IS_BIG_ENDIAN */ 8391 #if IS_LITTLE_ENDIAN 8392 uint32_t pmd_ln_h_rstb_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[00] - WO */ 8393 uint32_t pmd_ln_h_rstb_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[01] - WO */ 8394 uint32_t pmd_ln_dp_h_rstb_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[02] - WO */ 8395 uint32_t pmd_ln_dp_h_rstb_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[03] - WO */ 8396 uint32_t pmd_ln_rx_h_pwrdn_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[04] - WO */ 8397 uint32_t pmd_ln_rx_h_pwrdn_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[05] - WO */ 8398 uint32_t pmd_ln_tx_h_pwrdn_6_frcval : 1; /* MERLIN_IF_control2_lane6_TYPE[06] - WO */ 8399 uint32_t pmd_ln_tx_h_pwrdn_6_frc : 1; /* MERLIN_IF_control2_lane6_TYPE[07] - WO */ 8400 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane6_TYPE[15:08] - RSVD */ 8401 uint32_t reserved : 16; 8402 #endif /* IS_LITTLE_ENDIAN */ 8403 } fields; 8404 } MERLIN_IF_control2_lane6_TYPE; 8405 8406 typedef MERLIN_IF_control2_lane6_TYPE MERLIN_IF_CONTROL2_LANE6_TYPE_T; 8407 8408 typedef union { 8409 uint32_t data; 8410 struct { 8411 #if IS_BIG_ENDIAN 8412 uint32_t reserved : 16; 8413 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane7_TYPE[15:08] - RSVD */ 8414 uint32_t pmd_ln_tx_h_pwrdn_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[07] - WO */ 8415 uint32_t pmd_ln_tx_h_pwrdn_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[06] - WO */ 8416 uint32_t pmd_ln_rx_h_pwrdn_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[05] - WO */ 8417 uint32_t pmd_ln_rx_h_pwrdn_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[04] - WO */ 8418 uint32_t pmd_ln_dp_h_rstb_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[03] - WO */ 8419 uint32_t pmd_ln_dp_h_rstb_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[02] - WO */ 8420 uint32_t pmd_ln_h_rstb_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[01] - WO */ 8421 uint32_t pmd_ln_h_rstb_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[00] - WO */ 8422 #endif /* IS_BIG_ENDIAN */ 8423 #if IS_LITTLE_ENDIAN 8424 uint32_t pmd_ln_h_rstb_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[00] - WO */ 8425 uint32_t pmd_ln_h_rstb_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[01] - WO */ 8426 uint32_t pmd_ln_dp_h_rstb_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[02] - WO */ 8427 uint32_t pmd_ln_dp_h_rstb_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[03] - WO */ 8428 uint32_t pmd_ln_rx_h_pwrdn_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[04] - WO */ 8429 uint32_t pmd_ln_rx_h_pwrdn_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[05] - WO */ 8430 uint32_t pmd_ln_tx_h_pwrdn_7_frcval : 1; /* MERLIN_IF_control2_lane7_TYPE[06] - WO */ 8431 uint32_t pmd_ln_tx_h_pwrdn_7_frc : 1; /* MERLIN_IF_control2_lane7_TYPE[07] - WO */ 8432 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane7_TYPE[15:08] - RSVD */ 8433 uint32_t reserved : 16; 8434 #endif /* IS_LITTLE_ENDIAN */ 8435 } fields; 8436 } MERLIN_IF_control2_lane7_TYPE; 8437 8438 typedef MERLIN_IF_control2_lane7_TYPE MERLIN_IF_CONTROL2_LANE7_TYPE_T; 8439 8440 typedef union { 8441 uint32_t data; 8442 struct { 8443 #if IS_BIG_ENDIAN 8444 uint32_t reserved : 16; 8445 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane8_TYPE[15:08] - RSVD */ 8446 uint32_t pmd_ln_tx_h_pwrdn_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[07] - WO */ 8447 uint32_t pmd_ln_tx_h_pwrdn_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[06] - WO */ 8448 uint32_t pmd_ln_rx_h_pwrdn_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[05] - WO */ 8449 uint32_t pmd_ln_rx_h_pwrdn_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[04] - WO */ 8450 uint32_t pmd_ln_dp_h_rstb_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[03] - WO */ 8451 uint32_t pmd_ln_dp_h_rstb_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[02] - WO */ 8452 uint32_t pmd_ln_h_rstb_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[01] - WO */ 8453 uint32_t pmd_ln_h_rstb_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[00] - WO */ 8454 #endif /* IS_BIG_ENDIAN */ 8455 #if IS_LITTLE_ENDIAN 8456 uint32_t pmd_ln_h_rstb_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[00] - WO */ 8457 uint32_t pmd_ln_h_rstb_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[01] - WO */ 8458 uint32_t pmd_ln_dp_h_rstb_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[02] - WO */ 8459 uint32_t pmd_ln_dp_h_rstb_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[03] - WO */ 8460 uint32_t pmd_ln_rx_h_pwrdn_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[04] - WO */ 8461 uint32_t pmd_ln_rx_h_pwrdn_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[05] - WO */ 8462 uint32_t pmd_ln_tx_h_pwrdn_8_frcval : 1; /* MERLIN_IF_control2_lane8_TYPE[06] - WO */ 8463 uint32_t pmd_ln_tx_h_pwrdn_8_frc : 1; /* MERLIN_IF_control2_lane8_TYPE[07] - WO */ 8464 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane8_TYPE[15:08] - RSVD */ 8465 uint32_t reserved : 16; 8466 #endif /* IS_LITTLE_ENDIAN */ 8467 } fields; 8468 } MERLIN_IF_control2_lane8_TYPE; 8469 8470 typedef MERLIN_IF_control2_lane8_TYPE MERLIN_IF_CONTROL2_LANE8_TYPE_T; 8471 8472 typedef union { 8473 uint32_t data; 8474 struct { 8475 #if IS_BIG_ENDIAN 8476 uint32_t reserved : 16; 8477 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane9_TYPE[15:08] - RSVD */ 8478 uint32_t pmd_ln_tx_h_pwrdn_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[07] - WO */ 8479 uint32_t pmd_ln_tx_h_pwrdn_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[06] - WO */ 8480 uint32_t pmd_ln_rx_h_pwrdn_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[05] - WO */ 8481 uint32_t pmd_ln_rx_h_pwrdn_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[04] - WO */ 8482 uint32_t pmd_ln_dp_h_rstb_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[03] - WO */ 8483 uint32_t pmd_ln_dp_h_rstb_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[02] - WO */ 8484 uint32_t pmd_ln_h_rstb_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[01] - WO */ 8485 uint32_t pmd_ln_h_rstb_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[00] - WO */ 8486 #endif /* IS_BIG_ENDIAN */ 8487 #if IS_LITTLE_ENDIAN 8488 uint32_t pmd_ln_h_rstb_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[00] - WO */ 8489 uint32_t pmd_ln_h_rstb_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[01] - WO */ 8490 uint32_t pmd_ln_dp_h_rstb_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[02] - WO */ 8491 uint32_t pmd_ln_dp_h_rstb_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[03] - WO */ 8492 uint32_t pmd_ln_rx_h_pwrdn_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[04] - WO */ 8493 uint32_t pmd_ln_rx_h_pwrdn_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[05] - WO */ 8494 uint32_t pmd_ln_tx_h_pwrdn_9_frcval : 1; /* MERLIN_IF_control2_lane9_TYPE[06] - WO */ 8495 uint32_t pmd_ln_tx_h_pwrdn_9_frc : 1; /* MERLIN_IF_control2_lane9_TYPE[07] - WO */ 8496 uint32_t reserved_08 : 8; /* MERLIN_IF_control2_lane9_TYPE[15:08] - RSVD */ 8497 uint32_t reserved : 16; 8498 #endif /* IS_LITTLE_ENDIAN */ 8499 } fields; 8500 } MERLIN_IF_control2_lane9_TYPE; 8501 8502 typedef MERLIN_IF_control2_lane9_TYPE MERLIN_IF_CONTROL2_LANE9_TYPE_T; 8503 8504 typedef union { 8505 uint32_t data; 8506 struct { 8507 #if IS_BIG_ENDIAN 8508 uint32_t reserved : 16; 8509 uint32_t reserved_10 : 6; /* MERLIN_IF_common_control_TYPE[15:10] - RSVD */ 8510 uint32_t i_refsel : 3; /* MERLIN_IF_common_control_TYPE[09:07] - WO */ 8511 uint32_t i_ref_cmos_clk_hz : 1; /* MERLIN_IF_common_control_TYPE[06] - WO */ 8512 uint32_t i_pd_cml_refclk_chout : 1; /* MERLIN_IF_common_control_TYPE[05] - WO */ 8513 uint32_t pmd_iddq : 1; /* MERLIN_IF_common_control_TYPE[04] - WO */ 8514 uint32_t pmd_core_dp_h_rstb_frc : 1; /* MERLIN_IF_common_control_TYPE[03] - WO */ 8515 uint32_t pmd_core_dp_h_rstb_frcval : 1; /* MERLIN_IF_common_control_TYPE[02] - WO */ 8516 uint32_t pmd_por_h_rstb_frc : 1; /* MERLIN_IF_common_control_TYPE[01] - WO */ 8517 uint32_t pmd_por_h_rstb_frcval : 1; /* MERLIN_IF_common_control_TYPE[00] - WO */ 8518 #endif /* IS_BIG_ENDIAN */ 8519 #if IS_LITTLE_ENDIAN 8520 uint32_t pmd_por_h_rstb_frcval : 1; /* MERLIN_IF_common_control_TYPE[00] - WO */ 8521 uint32_t pmd_por_h_rstb_frc : 1; /* MERLIN_IF_common_control_TYPE[01] - WO */ 8522 uint32_t pmd_core_dp_h_rstb_frcval : 1; /* MERLIN_IF_common_control_TYPE[02] - WO */ 8523 uint32_t pmd_core_dp_h_rstb_frc : 1; /* MERLIN_IF_common_control_TYPE[03] - WO */ 8524 uint32_t pmd_iddq : 1; /* MERLIN_IF_common_control_TYPE[04] - WO */ 8525 uint32_t i_pd_cml_refclk_chout : 1; /* MERLIN_IF_common_control_TYPE[05] - WO */ 8526 uint32_t i_ref_cmos_clk_hz : 1; /* MERLIN_IF_common_control_TYPE[06] - WO */ 8527 uint32_t i_refsel : 3; /* MERLIN_IF_common_control_TYPE[09:07] - WO */ 8528 uint32_t reserved_10 : 6; /* MERLIN_IF_common_control_TYPE[15:10] - RSVD */ 8529 uint32_t reserved : 16; 8530 #endif /* IS_LITTLE_ENDIAN */ 8531 } fields; 8532 } MERLIN_IF_common_control_TYPE; 8533 8534 typedef MERLIN_IF_common_control_TYPE MERLIN_IF_COMMON_CONTROL_TYPE_T; 8535 8536 typedef union { 8537 uint32_t data; 8538 struct { 8539 #if IS_BIG_ENDIAN 8540 uint32_t reserved : 16; 8541 uint32_t reserved_06 : 10; /* MERLIN_IF_rescal_TYPE[15:06] - RSVD */ 8542 uint32_t pmd_rescal_done_bypass : 1; /* MERLIN_IF_rescal_TYPE[05] - WO */ 8543 uint32_t pmd_rescal_frc : 1; /* MERLIN_IF_rescal_TYPE[04] - WO */ 8544 uint32_t pmd_rescal_frcval : 4; /* MERLIN_IF_rescal_TYPE[03:00] - WO */ 8545 #endif /* IS_BIG_ENDIAN */ 8546 #if IS_LITTLE_ENDIAN 8547 uint32_t pmd_rescal_frcval : 4; /* MERLIN_IF_rescal_TYPE[03:00] - WO */ 8548 uint32_t pmd_rescal_frc : 1; /* MERLIN_IF_rescal_TYPE[04] - WO */ 8549 uint32_t pmd_rescal_done_bypass : 1; /* MERLIN_IF_rescal_TYPE[05] - WO */ 8550 uint32_t reserved_06 : 10; /* MERLIN_IF_rescal_TYPE[15:06] - RSVD */ 8551 uint32_t reserved : 16; 8552 #endif /* IS_LITTLE_ENDIAN */ 8553 } fields; 8554 } MERLIN_IF_rescal_TYPE; 8555 8556 typedef MERLIN_IF_rescal_TYPE MERLIN_IF_RESCAL_TYPE_T; 8557 8558 typedef union { 8559 uint32_t data; 8560 struct { 8561 #if IS_BIG_ENDIAN 8562 uint32_t reserved : 16; 8563 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane0_TYPE[15:04] - RSVD */ 8564 uint32_t pmd_tx_clk_vld_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[03] - RO */ 8565 uint32_t pmd_rx_clk_vld_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[02] - RO */ 8566 uint32_t pmd_rx_lock_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[01] - RO */ 8567 uint32_t pmd_signal_detect_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[00] - RO */ 8568 #endif /* IS_BIG_ENDIAN */ 8569 #if IS_LITTLE_ENDIAN 8570 uint32_t pmd_signal_detect_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[00] - RO */ 8571 uint32_t pmd_rx_lock_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[01] - RO */ 8572 uint32_t pmd_rx_clk_vld_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[02] - RO */ 8573 uint32_t pmd_tx_clk_vld_0 : 1; /* MERLIN_IF_repeater_status_lane0_TYPE[03] - RO */ 8574 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane0_TYPE[15:04] - RSVD */ 8575 uint32_t reserved : 16; 8576 #endif /* IS_LITTLE_ENDIAN */ 8577 } fields; 8578 } MERLIN_IF_repeater_status_lane0_TYPE; 8579 8580 typedef MERLIN_IF_repeater_status_lane0_TYPE MERLIN_IF_REPEATER_STATUS_LANE0_TYPE_T; 8581 8582 typedef union { 8583 uint32_t data; 8584 struct { 8585 #if IS_BIG_ENDIAN 8586 uint32_t reserved : 16; 8587 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane1_TYPE[15:04] - RSVD */ 8588 uint32_t pmd_tx_clk_vld_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[03] - RO */ 8589 uint32_t pmd_rx_clk_vld_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[02] - RO */ 8590 uint32_t pmd_rx_lock_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[01] - RO */ 8591 uint32_t pmd_signal_detect_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[00] - RO */ 8592 #endif /* IS_BIG_ENDIAN */ 8593 #if IS_LITTLE_ENDIAN 8594 uint32_t pmd_signal_detect_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[00] - RO */ 8595 uint32_t pmd_rx_lock_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[01] - RO */ 8596 uint32_t pmd_rx_clk_vld_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[02] - RO */ 8597 uint32_t pmd_tx_clk_vld_1 : 1; /* MERLIN_IF_repeater_status_lane1_TYPE[03] - RO */ 8598 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane1_TYPE[15:04] - RSVD */ 8599 uint32_t reserved : 16; 8600 #endif /* IS_LITTLE_ENDIAN */ 8601 } fields; 8602 } MERLIN_IF_repeater_status_lane1_TYPE; 8603 8604 typedef MERLIN_IF_repeater_status_lane1_TYPE MERLIN_IF_REPEATER_STATUS_LANE1_TYPE_T; 8605 8606 typedef union { 8607 uint32_t data; 8608 struct { 8609 #if IS_BIG_ENDIAN 8610 uint32_t reserved : 16; 8611 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane2_TYPE[15:04] - RSVD */ 8612 uint32_t pmd_tx_clk_vld_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[03] - RO */ 8613 uint32_t pmd_rx_clk_vld_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[02] - RO */ 8614 uint32_t pmd_rx_lock_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[01] - RO */ 8615 uint32_t pmd_signal_detect_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[00] - RO */ 8616 #endif /* IS_BIG_ENDIAN */ 8617 #if IS_LITTLE_ENDIAN 8618 uint32_t pmd_signal_detect_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[00] - RO */ 8619 uint32_t pmd_rx_lock_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[01] - RO */ 8620 uint32_t pmd_rx_clk_vld_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[02] - RO */ 8621 uint32_t pmd_tx_clk_vld_2 : 1; /* MERLIN_IF_repeater_status_lane2_TYPE[03] - RO */ 8622 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane2_TYPE[15:04] - RSVD */ 8623 uint32_t reserved : 16; 8624 #endif /* IS_LITTLE_ENDIAN */ 8625 } fields; 8626 } MERLIN_IF_repeater_status_lane2_TYPE; 8627 8628 typedef MERLIN_IF_repeater_status_lane2_TYPE MERLIN_IF_REPEATER_STATUS_LANE2_TYPE_T; 8629 8630 typedef union { 8631 uint32_t data; 8632 struct { 8633 #if IS_BIG_ENDIAN 8634 uint32_t reserved : 16; 8635 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane3_TYPE[15:04] - RSVD */ 8636 uint32_t pmd_tx_clk_vld_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[03] - RO */ 8637 uint32_t pmd_rx_clk_vld_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[02] - RO */ 8638 uint32_t pmd_rx_lock_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[01] - RO */ 8639 uint32_t pmd_signal_detect_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[00] - RO */ 8640 #endif /* IS_BIG_ENDIAN */ 8641 #if IS_LITTLE_ENDIAN 8642 uint32_t pmd_signal_detect_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[00] - RO */ 8643 uint32_t pmd_rx_lock_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[01] - RO */ 8644 uint32_t pmd_rx_clk_vld_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[02] - RO */ 8645 uint32_t pmd_tx_clk_vld_3 : 1; /* MERLIN_IF_repeater_status_lane3_TYPE[03] - RO */ 8646 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane3_TYPE[15:04] - RSVD */ 8647 uint32_t reserved : 16; 8648 #endif /* IS_LITTLE_ENDIAN */ 8649 } fields; 8650 } MERLIN_IF_repeater_status_lane3_TYPE; 8651 8652 typedef MERLIN_IF_repeater_status_lane3_TYPE MERLIN_IF_REPEATER_STATUS_LANE3_TYPE_T; 8653 8654 typedef union { 8655 uint32_t data; 8656 struct { 8657 #if IS_BIG_ENDIAN 8658 uint32_t reserved : 16; 8659 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane4_TYPE[15:04] - RSVD */ 8660 uint32_t pmd_tx_clk_vld_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[03] - RO */ 8661 uint32_t pmd_rx_clk_vld_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[02] - RO */ 8662 uint32_t pmd_rx_lock_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[01] - RO */ 8663 uint32_t pmd_signal_detect_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[00] - RO */ 8664 #endif /* IS_BIG_ENDIAN */ 8665 #if IS_LITTLE_ENDIAN 8666 uint32_t pmd_signal_detect_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[00] - RO */ 8667 uint32_t pmd_rx_lock_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[01] - RO */ 8668 uint32_t pmd_rx_clk_vld_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[02] - RO */ 8669 uint32_t pmd_tx_clk_vld_4 : 1; /* MERLIN_IF_repeater_status_lane4_TYPE[03] - RO */ 8670 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane4_TYPE[15:04] - RSVD */ 8671 uint32_t reserved : 16; 8672 #endif /* IS_LITTLE_ENDIAN */ 8673 } fields; 8674 } MERLIN_IF_repeater_status_lane4_TYPE; 8675 8676 typedef MERLIN_IF_repeater_status_lane4_TYPE MERLIN_IF_REPEATER_STATUS_LANE4_TYPE_T; 8677 8678 typedef union { 8679 uint32_t data; 8680 struct { 8681 #if IS_BIG_ENDIAN 8682 uint32_t reserved : 16; 8683 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane5_TYPE[15:04] - RSVD */ 8684 uint32_t pmd_tx_clk_vld_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[03] - RO */ 8685 uint32_t pmd_rx_clk_vld_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[02] - RO */ 8686 uint32_t pmd_rx_lock_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[01] - RO */ 8687 uint32_t pmd_signal_detect_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[00] - RO */ 8688 #endif /* IS_BIG_ENDIAN */ 8689 #if IS_LITTLE_ENDIAN 8690 uint32_t pmd_signal_detect_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[00] - RO */ 8691 uint32_t pmd_rx_lock_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[01] - RO */ 8692 uint32_t pmd_rx_clk_vld_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[02] - RO */ 8693 uint32_t pmd_tx_clk_vld_5 : 1; /* MERLIN_IF_repeater_status_lane5_TYPE[03] - RO */ 8694 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane5_TYPE[15:04] - RSVD */ 8695 uint32_t reserved : 16; 8696 #endif /* IS_LITTLE_ENDIAN */ 8697 } fields; 8698 } MERLIN_IF_repeater_status_lane5_TYPE; 8699 8700 typedef MERLIN_IF_repeater_status_lane5_TYPE MERLIN_IF_REPEATER_STATUS_LANE5_TYPE_T; 8701 8702 typedef union { 8703 uint32_t data; 8704 struct { 8705 #if IS_BIG_ENDIAN 8706 uint32_t reserved : 16; 8707 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane6_TYPE[15:04] - RSVD */ 8708 uint32_t pmd_tx_clk_vld_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[03] - RO */ 8709 uint32_t pmd_rx_clk_vld_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[02] - RO */ 8710 uint32_t pmd_rx_lock_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[01] - RO */ 8711 uint32_t pmd_signal_detect_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[00] - RO */ 8712 #endif /* IS_BIG_ENDIAN */ 8713 #if IS_LITTLE_ENDIAN 8714 uint32_t pmd_signal_detect_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[00] - RO */ 8715 uint32_t pmd_rx_lock_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[01] - RO */ 8716 uint32_t pmd_rx_clk_vld_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[02] - RO */ 8717 uint32_t pmd_tx_clk_vld_6 : 1; /* MERLIN_IF_repeater_status_lane6_TYPE[03] - RO */ 8718 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane6_TYPE[15:04] - RSVD */ 8719 uint32_t reserved : 16; 8720 #endif /* IS_LITTLE_ENDIAN */ 8721 } fields; 8722 } MERLIN_IF_repeater_status_lane6_TYPE; 8723 8724 typedef MERLIN_IF_repeater_status_lane6_TYPE MERLIN_IF_REPEATER_STATUS_LANE6_TYPE_T; 8725 8726 typedef union { 8727 uint32_t data; 8728 struct { 8729 #if IS_BIG_ENDIAN 8730 uint32_t reserved : 16; 8731 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane7_TYPE[15:04] - RSVD */ 8732 uint32_t pmd_tx_clk_vld_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[03] - RO */ 8733 uint32_t pmd_rx_clk_vld_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[02] - RO */ 8734 uint32_t pmd_rx_lock_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[01] - RO */ 8735 uint32_t pmd_signal_detect_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[00] - RO */ 8736 #endif /* IS_BIG_ENDIAN */ 8737 #if IS_LITTLE_ENDIAN 8738 uint32_t pmd_signal_detect_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[00] - RO */ 8739 uint32_t pmd_rx_lock_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[01] - RO */ 8740 uint32_t pmd_rx_clk_vld_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[02] - RO */ 8741 uint32_t pmd_tx_clk_vld_7 : 1; /* MERLIN_IF_repeater_status_lane7_TYPE[03] - RO */ 8742 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane7_TYPE[15:04] - RSVD */ 8743 uint32_t reserved : 16; 8744 #endif /* IS_LITTLE_ENDIAN */ 8745 } fields; 8746 } MERLIN_IF_repeater_status_lane7_TYPE; 8747 8748 typedef MERLIN_IF_repeater_status_lane7_TYPE MERLIN_IF_REPEATER_STATUS_LANE7_TYPE_T; 8749 8750 typedef union { 8751 uint32_t data; 8752 struct { 8753 #if IS_BIG_ENDIAN 8754 uint32_t reserved : 16; 8755 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane8_TYPE[15:04] - RSVD */ 8756 uint32_t pmd_tx_clk_vld_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[03] - RO */ 8757 uint32_t pmd_rx_clk_vld_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[02] - RO */ 8758 uint32_t pmd_rx_lock_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[01] - RO */ 8759 uint32_t pmd_signal_detect_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[00] - RO */ 8760 #endif /* IS_BIG_ENDIAN */ 8761 #if IS_LITTLE_ENDIAN 8762 uint32_t pmd_signal_detect_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[00] - RO */ 8763 uint32_t pmd_rx_lock_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[01] - RO */ 8764 uint32_t pmd_rx_clk_vld_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[02] - RO */ 8765 uint32_t pmd_tx_clk_vld_8 : 1; /* MERLIN_IF_repeater_status_lane8_TYPE[03] - RO */ 8766 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane8_TYPE[15:04] - RSVD */ 8767 uint32_t reserved : 16; 8768 #endif /* IS_LITTLE_ENDIAN */ 8769 } fields; 8770 } MERLIN_IF_repeater_status_lane8_TYPE; 8771 8772 typedef MERLIN_IF_repeater_status_lane8_TYPE MERLIN_IF_REPEATER_STATUS_LANE8_TYPE_T; 8773 8774 typedef union { 8775 uint32_t data; 8776 struct { 8777 #if IS_BIG_ENDIAN 8778 uint32_t reserved : 16; 8779 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane9_TYPE[15:04] - RSVD */ 8780 uint32_t pmd_tx_clk_vld_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[03] - RO */ 8781 uint32_t pmd_rx_clk_vld_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[02] - RO */ 8782 uint32_t pmd_rx_lock_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[01] - RO */ 8783 uint32_t pmd_signal_detect_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[00] - RO */ 8784 #endif /* IS_BIG_ENDIAN */ 8785 #if IS_LITTLE_ENDIAN 8786 uint32_t pmd_signal_detect_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[00] - RO */ 8787 uint32_t pmd_rx_lock_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[01] - RO */ 8788 uint32_t pmd_rx_clk_vld_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[02] - RO */ 8789 uint32_t pmd_tx_clk_vld_9 : 1; /* MERLIN_IF_repeater_status_lane9_TYPE[03] - RO */ 8790 uint32_t reserved_04 : 12; /* MERLIN_IF_repeater_status_lane9_TYPE[15:04] - RSVD */ 8791 uint32_t reserved : 16; 8792 #endif /* IS_LITTLE_ENDIAN */ 8793 } fields; 8794 } MERLIN_IF_repeater_status_lane9_TYPE; 8795 8796 typedef MERLIN_IF_repeater_status_lane9_TYPE MERLIN_IF_REPEATER_STATUS_LANE9_TYPE_T; 8797 8798 typedef union { 8799 uint32_t data; 8800 struct { 8801 #if IS_BIG_ENDIAN 8802 uint32_t reserved : 16; 8803 uint32_t reserved_01 : 15; /* MERLIN_IF_pmd_pll_lock_status_TYPE[15:01] - RSVD */ 8804 uint32_t pmd_pll_lock : 1; /* MERLIN_IF_pmd_pll_lock_status_TYPE[00] - RO */ 8805 #endif /* IS_BIG_ENDIAN */ 8806 #if IS_LITTLE_ENDIAN 8807 uint32_t pmd_pll_lock : 1; /* MERLIN_IF_pmd_pll_lock_status_TYPE[00] - RO */ 8808 uint32_t reserved_01 : 15; /* MERLIN_IF_pmd_pll_lock_status_TYPE[15:01] - RSVD */ 8809 uint32_t reserved : 16; 8810 #endif /* IS_LITTLE_ENDIAN */ 8811 } fields; 8812 } MERLIN_IF_pmd_pll_lock_status_TYPE; 8813 8814 typedef MERLIN_IF_pmd_pll_lock_status_TYPE MERLIN_IF_PMD_PLL_LOCK_STATUS_TYPE_T; 8815 8816 8817 /*-----------------------------------------------*/ 8818 /* Structs for FALCON_IF Bank */ 8819 /*-----------------------------------------------*/ 8820 typedef union { 8821 uint32_t data; 8822 struct { 8823 #if IS_BIG_ENDIAN 8824 uint32_t reserved : 16; 8825 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane0_TYPE[15:09] - RSVD */ 8826 uint32_t pmd_osr_mode_0_frc : 1; /* FALCON_IF_control1_lane0_TYPE[08] - WO */ 8827 uint32_t pmd_osr_mode_0_frcval : 4; /* FALCON_IF_control1_lane0_TYPE[07:04] - WO */ 8828 uint32_t pmd_tx_disable_0_frc : 1; /* FALCON_IF_control1_lane0_TYPE[03] - WO */ 8829 uint32_t pmd_tx_disable_0_frcval : 1; /* FALCON_IF_control1_lane0_TYPE[02] - WO */ 8830 uint32_t pmd_ext_los_0_frc : 1; /* FALCON_IF_control1_lane0_TYPE[01] - WO */ 8831 uint32_t pmd_ext_los_0_frcval : 1; /* FALCON_IF_control1_lane0_TYPE[00] - WO */ 8832 #endif /* IS_BIG_ENDIAN */ 8833 #if IS_LITTLE_ENDIAN 8834 uint32_t pmd_ext_los_0_frcval : 1; /* FALCON_IF_control1_lane0_TYPE[00] - WO */ 8835 uint32_t pmd_ext_los_0_frc : 1; /* FALCON_IF_control1_lane0_TYPE[01] - WO */ 8836 uint32_t pmd_tx_disable_0_frcval : 1; /* FALCON_IF_control1_lane0_TYPE[02] - WO */ 8837 uint32_t pmd_tx_disable_0_frc : 1; /* FALCON_IF_control1_lane0_TYPE[03] - WO */ 8838 uint32_t pmd_osr_mode_0_frcval : 4; /* FALCON_IF_control1_lane0_TYPE[07:04] - WO */ 8839 uint32_t pmd_osr_mode_0_frc : 1; /* FALCON_IF_control1_lane0_TYPE[08] - WO */ 8840 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane0_TYPE[15:09] - RSVD */ 8841 uint32_t reserved : 16; 8842 #endif /* IS_LITTLE_ENDIAN */ 8843 } fields; 8844 } FALCON_IF_control1_lane0_TYPE; 8845 8846 typedef FALCON_IF_control1_lane0_TYPE FALCON_IF_CONTROL1_LANE0_TYPE_T; 8847 8848 typedef union { 8849 uint32_t data; 8850 struct { 8851 #if IS_BIG_ENDIAN 8852 uint32_t reserved : 16; 8853 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane1_TYPE[15:09] - RSVD */ 8854 uint32_t pmd_osr_mode_1_frc : 1; /* FALCON_IF_control1_lane1_TYPE[08] - WO */ 8855 uint32_t pmd_osr_mode_1_frcval : 4; /* FALCON_IF_control1_lane1_TYPE[07:04] - WO */ 8856 uint32_t pmd_tx_disable_1_frc : 1; /* FALCON_IF_control1_lane1_TYPE[03] - WO */ 8857 uint32_t pmd_tx_disable_1_frcval : 1; /* FALCON_IF_control1_lane1_TYPE[02] - WO */ 8858 uint32_t pmd_ext_los_1_frc : 1; /* FALCON_IF_control1_lane1_TYPE[01] - WO */ 8859 uint32_t pmd_ext_los_1_frcval : 1; /* FALCON_IF_control1_lane1_TYPE[00] - WO */ 8860 #endif /* IS_BIG_ENDIAN */ 8861 #if IS_LITTLE_ENDIAN 8862 uint32_t pmd_ext_los_1_frcval : 1; /* FALCON_IF_control1_lane1_TYPE[00] - WO */ 8863 uint32_t pmd_ext_los_1_frc : 1; /* FALCON_IF_control1_lane1_TYPE[01] - WO */ 8864 uint32_t pmd_tx_disable_1_frcval : 1; /* FALCON_IF_control1_lane1_TYPE[02] - WO */ 8865 uint32_t pmd_tx_disable_1_frc : 1; /* FALCON_IF_control1_lane1_TYPE[03] - WO */ 8866 uint32_t pmd_osr_mode_1_frcval : 4; /* FALCON_IF_control1_lane1_TYPE[07:04] - WO */ 8867 uint32_t pmd_osr_mode_1_frc : 1; /* FALCON_IF_control1_lane1_TYPE[08] - WO */ 8868 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane1_TYPE[15:09] - RSVD */ 8869 uint32_t reserved : 16; 8870 #endif /* IS_LITTLE_ENDIAN */ 8871 } fields; 8872 } FALCON_IF_control1_lane1_TYPE; 8873 8874 typedef FALCON_IF_control1_lane1_TYPE FALCON_IF_CONTROL1_LANE1_TYPE_T; 8875 8876 typedef union { 8877 uint32_t data; 8878 struct { 8879 #if IS_BIG_ENDIAN 8880 uint32_t reserved : 16; 8881 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane2_TYPE[15:09] - RSVD */ 8882 uint32_t pmd_osr_mode_2_frc : 1; /* FALCON_IF_control1_lane2_TYPE[08] - WO */ 8883 uint32_t pmd_osr_mode_2_frcval : 4; /* FALCON_IF_control1_lane2_TYPE[07:04] - WO */ 8884 uint32_t pmd_tx_disable_2_frc : 1; /* FALCON_IF_control1_lane2_TYPE[03] - WO */ 8885 uint32_t pmd_tx_disable_2_frcval : 1; /* FALCON_IF_control1_lane2_TYPE[02] - WO */ 8886 uint32_t pmd_ext_los_2_frc : 1; /* FALCON_IF_control1_lane2_TYPE[01] - WO */ 8887 uint32_t pmd_ext_los_2_frcval : 1; /* FALCON_IF_control1_lane2_TYPE[00] - WO */ 8888 #endif /* IS_BIG_ENDIAN */ 8889 #if IS_LITTLE_ENDIAN 8890 uint32_t pmd_ext_los_2_frcval : 1; /* FALCON_IF_control1_lane2_TYPE[00] - WO */ 8891 uint32_t pmd_ext_los_2_frc : 1; /* FALCON_IF_control1_lane2_TYPE[01] - WO */ 8892 uint32_t pmd_tx_disable_2_frcval : 1; /* FALCON_IF_control1_lane2_TYPE[02] - WO */ 8893 uint32_t pmd_tx_disable_2_frc : 1; /* FALCON_IF_control1_lane2_TYPE[03] - WO */ 8894 uint32_t pmd_osr_mode_2_frcval : 4; /* FALCON_IF_control1_lane2_TYPE[07:04] - WO */ 8895 uint32_t pmd_osr_mode_2_frc : 1; /* FALCON_IF_control1_lane2_TYPE[08] - WO */ 8896 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane2_TYPE[15:09] - RSVD */ 8897 uint32_t reserved : 16; 8898 #endif /* IS_LITTLE_ENDIAN */ 8899 } fields; 8900 } FALCON_IF_control1_lane2_TYPE; 8901 8902 typedef FALCON_IF_control1_lane2_TYPE FALCON_IF_CONTROL1_LANE2_TYPE_T; 8903 8904 typedef union { 8905 uint32_t data; 8906 struct { 8907 #if IS_BIG_ENDIAN 8908 uint32_t reserved : 16; 8909 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane3_TYPE[15:09] - RSVD */ 8910 uint32_t pmd_osr_mode_3_frc : 1; /* FALCON_IF_control1_lane3_TYPE[08] - WO */ 8911 uint32_t pmd_osr_mode_3_frcval : 4; /* FALCON_IF_control1_lane3_TYPE[07:04] - WO */ 8912 uint32_t pmd_tx_disable_3_frc : 1; /* FALCON_IF_control1_lane3_TYPE[03] - WO */ 8913 uint32_t pmd_tx_disable_3_frcval : 1; /* FALCON_IF_control1_lane3_TYPE[02] - WO */ 8914 uint32_t pmd_ext_los_3_frc : 1; /* FALCON_IF_control1_lane3_TYPE[01] - WO */ 8915 uint32_t pmd_ext_los_3_frcval : 1; /* FALCON_IF_control1_lane3_TYPE[00] - WO */ 8916 #endif /* IS_BIG_ENDIAN */ 8917 #if IS_LITTLE_ENDIAN 8918 uint32_t pmd_ext_los_3_frcval : 1; /* FALCON_IF_control1_lane3_TYPE[00] - WO */ 8919 uint32_t pmd_ext_los_3_frc : 1; /* FALCON_IF_control1_lane3_TYPE[01] - WO */ 8920 uint32_t pmd_tx_disable_3_frcval : 1; /* FALCON_IF_control1_lane3_TYPE[02] - WO */ 8921 uint32_t pmd_tx_disable_3_frc : 1; /* FALCON_IF_control1_lane3_TYPE[03] - WO */ 8922 uint32_t pmd_osr_mode_3_frcval : 4; /* FALCON_IF_control1_lane3_TYPE[07:04] - WO */ 8923 uint32_t pmd_osr_mode_3_frc : 1; /* FALCON_IF_control1_lane3_TYPE[08] - WO */ 8924 uint32_t reserved_09 : 7; /* FALCON_IF_control1_lane3_TYPE[15:09] - RSVD */ 8925 uint32_t reserved : 16; 8926 #endif /* IS_LITTLE_ENDIAN */ 8927 } fields; 8928 } FALCON_IF_control1_lane3_TYPE; 8929 8930 typedef FALCON_IF_control1_lane3_TYPE FALCON_IF_CONTROL1_LANE3_TYPE_T; 8931 8932 typedef union { 8933 uint32_t data; 8934 struct { 8935 #if IS_BIG_ENDIAN 8936 uint32_t reserved : 16; 8937 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane0_TYPE[15:08] - RSVD */ 8938 uint32_t pmd_ln_tx_h_pwrdn_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[07] - WO */ 8939 uint32_t pmd_ln_tx_h_pwrdn_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[06] - WO */ 8940 uint32_t pmd_ln_rx_h_pwrdn_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[05] - WO */ 8941 uint32_t pmd_ln_rx_h_pwrdn_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[04] - WO */ 8942 uint32_t pmd_ln_dp_h_rstb_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[03] - WO */ 8943 uint32_t pmd_ln_dp_h_rstb_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[02] - WO */ 8944 uint32_t pmd_ln_h_rstb_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[01] - WO */ 8945 uint32_t pmd_ln_h_rstb_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[00] - WO */ 8946 #endif /* IS_BIG_ENDIAN */ 8947 #if IS_LITTLE_ENDIAN 8948 uint32_t pmd_ln_h_rstb_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[00] - WO */ 8949 uint32_t pmd_ln_h_rstb_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[01] - WO */ 8950 uint32_t pmd_ln_dp_h_rstb_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[02] - WO */ 8951 uint32_t pmd_ln_dp_h_rstb_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[03] - WO */ 8952 uint32_t pmd_ln_rx_h_pwrdn_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[04] - WO */ 8953 uint32_t pmd_ln_rx_h_pwrdn_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[05] - WO */ 8954 uint32_t pmd_ln_tx_h_pwrdn_0_frcval : 1; /* FALCON_IF_control2_lane0_TYPE[06] - WO */ 8955 uint32_t pmd_ln_tx_h_pwrdn_0_frc : 1; /* FALCON_IF_control2_lane0_TYPE[07] - WO */ 8956 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane0_TYPE[15:08] - RSVD */ 8957 uint32_t reserved : 16; 8958 #endif /* IS_LITTLE_ENDIAN */ 8959 } fields; 8960 } FALCON_IF_control2_lane0_TYPE; 8961 8962 typedef FALCON_IF_control2_lane0_TYPE FALCON_IF_CONTROL2_LANE0_TYPE_T; 8963 8964 typedef union { 8965 uint32_t data; 8966 struct { 8967 #if IS_BIG_ENDIAN 8968 uint32_t reserved : 16; 8969 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane1_TYPE[15:08] - RSVD */ 8970 uint32_t pmd_ln_tx_h_pwrdn_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[07] - WO */ 8971 uint32_t pmd_ln_tx_h_pwrdn_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[06] - WO */ 8972 uint32_t pmd_ln_rx_h_pwrdn_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[05] - WO */ 8973 uint32_t pmd_ln_rx_h_pwrdn_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[04] - WO */ 8974 uint32_t pmd_ln_dp_h_rstb_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[03] - WO */ 8975 uint32_t pmd_ln_dp_h_rstb_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[02] - WO */ 8976 uint32_t pmd_ln_h_rstb_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[01] - WO */ 8977 uint32_t pmd_ln_h_rstb_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[00] - WO */ 8978 #endif /* IS_BIG_ENDIAN */ 8979 #if IS_LITTLE_ENDIAN 8980 uint32_t pmd_ln_h_rstb_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[00] - WO */ 8981 uint32_t pmd_ln_h_rstb_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[01] - WO */ 8982 uint32_t pmd_ln_dp_h_rstb_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[02] - WO */ 8983 uint32_t pmd_ln_dp_h_rstb_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[03] - WO */ 8984 uint32_t pmd_ln_rx_h_pwrdn_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[04] - WO */ 8985 uint32_t pmd_ln_rx_h_pwrdn_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[05] - WO */ 8986 uint32_t pmd_ln_tx_h_pwrdn_1_frcval : 1; /* FALCON_IF_control2_lane1_TYPE[06] - WO */ 8987 uint32_t pmd_ln_tx_h_pwrdn_1_frc : 1; /* FALCON_IF_control2_lane1_TYPE[07] - WO */ 8988 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane1_TYPE[15:08] - RSVD */ 8989 uint32_t reserved : 16; 8990 #endif /* IS_LITTLE_ENDIAN */ 8991 } fields; 8992 } FALCON_IF_control2_lane1_TYPE; 8993 8994 typedef FALCON_IF_control2_lane1_TYPE FALCON_IF_CONTROL2_LANE1_TYPE_T; 8995 8996 typedef union { 8997 uint32_t data; 8998 struct { 8999 #if IS_BIG_ENDIAN 9000 uint32_t reserved : 16; 9001 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane2_TYPE[15:08] - RSVD */ 9002 uint32_t pmd_ln_tx_h_pwrdn_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[07] - WO */ 9003 uint32_t pmd_ln_tx_h_pwrdn_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[06] - WO */ 9004 uint32_t pmd_ln_rx_h_pwrdn_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[05] - WO */ 9005 uint32_t pmd_ln_rx_h_pwrdn_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[04] - WO */ 9006 uint32_t pmd_ln_dp_h_rstb_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[03] - WO */ 9007 uint32_t pmd_ln_dp_h_rstb_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[02] - WO */ 9008 uint32_t pmd_ln_h_rstb_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[01] - WO */ 9009 uint32_t pmd_ln_h_rstb_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[00] - WO */ 9010 #endif /* IS_BIG_ENDIAN */ 9011 #if IS_LITTLE_ENDIAN 9012 uint32_t pmd_ln_h_rstb_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[00] - WO */ 9013 uint32_t pmd_ln_h_rstb_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[01] - WO */ 9014 uint32_t pmd_ln_dp_h_rstb_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[02] - WO */ 9015 uint32_t pmd_ln_dp_h_rstb_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[03] - WO */ 9016 uint32_t pmd_ln_rx_h_pwrdn_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[04] - WO */ 9017 uint32_t pmd_ln_rx_h_pwrdn_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[05] - WO */ 9018 uint32_t pmd_ln_tx_h_pwrdn_2_frcval : 1; /* FALCON_IF_control2_lane2_TYPE[06] - WO */ 9019 uint32_t pmd_ln_tx_h_pwrdn_2_frc : 1; /* FALCON_IF_control2_lane2_TYPE[07] - WO */ 9020 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane2_TYPE[15:08] - RSVD */ 9021 uint32_t reserved : 16; 9022 #endif /* IS_LITTLE_ENDIAN */ 9023 } fields; 9024 } FALCON_IF_control2_lane2_TYPE; 9025 9026 typedef FALCON_IF_control2_lane2_TYPE FALCON_IF_CONTROL2_LANE2_TYPE_T; 9027 9028 typedef union { 9029 uint32_t data; 9030 struct { 9031 #if IS_BIG_ENDIAN 9032 uint32_t reserved : 16; 9033 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane3_TYPE[15:08] - RSVD */ 9034 uint32_t pmd_ln_tx_h_pwrdn_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[07] - WO */ 9035 uint32_t pmd_ln_tx_h_pwrdn_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[06] - WO */ 9036 uint32_t pmd_ln_rx_h_pwrdn_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[05] - WO */ 9037 uint32_t pmd_ln_rx_h_pwrdn_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[04] - WO */ 9038 uint32_t pmd_ln_dp_h_rstb_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[03] - WO */ 9039 uint32_t pmd_ln_dp_h_rstb_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[02] - WO */ 9040 uint32_t pmd_ln_h_rstb_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[01] - WO */ 9041 uint32_t pmd_ln_h_rstb_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[00] - WO */ 9042 #endif /* IS_BIG_ENDIAN */ 9043 #if IS_LITTLE_ENDIAN 9044 uint32_t pmd_ln_h_rstb_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[00] - WO */ 9045 uint32_t pmd_ln_h_rstb_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[01] - WO */ 9046 uint32_t pmd_ln_dp_h_rstb_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[02] - WO */ 9047 uint32_t pmd_ln_dp_h_rstb_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[03] - WO */ 9048 uint32_t pmd_ln_rx_h_pwrdn_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[04] - WO */ 9049 uint32_t pmd_ln_rx_h_pwrdn_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[05] - WO */ 9050 uint32_t pmd_ln_tx_h_pwrdn_3_frcval : 1; /* FALCON_IF_control2_lane3_TYPE[06] - WO */ 9051 uint32_t pmd_ln_tx_h_pwrdn_3_frc : 1; /* FALCON_IF_control2_lane3_TYPE[07] - WO */ 9052 uint32_t reserved_08 : 8; /* FALCON_IF_control2_lane3_TYPE[15:08] - RSVD */ 9053 uint32_t reserved : 16; 9054 #endif /* IS_LITTLE_ENDIAN */ 9055 } fields; 9056 } FALCON_IF_control2_lane3_TYPE; 9057 9058 typedef FALCON_IF_control2_lane3_TYPE FALCON_IF_CONTROL2_LANE3_TYPE_T; 9059 9060 typedef union { 9061 uint32_t data; 9062 struct { 9063 #if IS_BIG_ENDIAN 9064 uint32_t reserved : 16; 9065 uint32_t reserved_06 : 10; /* FALCON_IF_common_control_TYPE[15:06] - RSVD */ 9066 uint32_t tx_drv_hv_disable : 1; /* FALCON_IF_common_control_TYPE[05] - WO */ 9067 uint32_t pmd_iddq : 1; /* FALCON_IF_common_control_TYPE[04] - WO */ 9068 uint32_t pmd_core_dp_h_rstb_frc : 1; /* FALCON_IF_common_control_TYPE[03] - WO */ 9069 uint32_t pmd_core_dp_h_rstb_frcval : 1; /* FALCON_IF_common_control_TYPE[02] - WO */ 9070 uint32_t pmd_por_h_rstb_frc : 1; /* FALCON_IF_common_control_TYPE[01] - WO */ 9071 uint32_t pmd_por_h_rstb_frcval : 1; /* FALCON_IF_common_control_TYPE[00] - WO */ 9072 #endif /* IS_BIG_ENDIAN */ 9073 #if IS_LITTLE_ENDIAN 9074 uint32_t pmd_por_h_rstb_frcval : 1; /* FALCON_IF_common_control_TYPE[00] - WO */ 9075 uint32_t pmd_por_h_rstb_frc : 1; /* FALCON_IF_common_control_TYPE[01] - WO */ 9076 uint32_t pmd_core_dp_h_rstb_frcval : 1; /* FALCON_IF_common_control_TYPE[02] - WO */ 9077 uint32_t pmd_core_dp_h_rstb_frc : 1; /* FALCON_IF_common_control_TYPE[03] - WO */ 9078 uint32_t pmd_iddq : 1; /* FALCON_IF_common_control_TYPE[04] - WO */ 9079 uint32_t tx_drv_hv_disable : 1; /* FALCON_IF_common_control_TYPE[05] - WO */ 9080 uint32_t reserved_06 : 10; /* FALCON_IF_common_control_TYPE[15:06] - RSVD */ 9081 uint32_t reserved : 16; 9082 #endif /* IS_LITTLE_ENDIAN */ 9083 } fields; 9084 } FALCON_IF_common_control_TYPE; 9085 9086 typedef FALCON_IF_common_control_TYPE FALCON_IF_COMMON_CONTROL_TYPE_T; 9087 9088 typedef union { 9089 uint32_t data; 9090 struct { 9091 #if IS_BIG_ENDIAN 9092 uint32_t reserved : 16; 9093 uint32_t reserved_06 : 10; /* FALCON_IF_rescal_TYPE[15:06] - RSVD */ 9094 uint32_t pmd_rescal_done_bypass : 1; /* FALCON_IF_rescal_TYPE[05] - WO */ 9095 uint32_t pmd_rescal_frc : 1; /* FALCON_IF_rescal_TYPE[04] - WO */ 9096 uint32_t pmd_rescal_frcval : 4; /* FALCON_IF_rescal_TYPE[03:00] - WO */ 9097 #endif /* IS_BIG_ENDIAN */ 9098 #if IS_LITTLE_ENDIAN 9099 uint32_t pmd_rescal_frcval : 4; /* FALCON_IF_rescal_TYPE[03:00] - WO */ 9100 uint32_t pmd_rescal_frc : 1; /* FALCON_IF_rescal_TYPE[04] - WO */ 9101 uint32_t pmd_rescal_done_bypass : 1; /* FALCON_IF_rescal_TYPE[05] - WO */ 9102 uint32_t reserved_06 : 10; /* FALCON_IF_rescal_TYPE[15:06] - RSVD */ 9103 uint32_t reserved : 16; 9104 #endif /* IS_LITTLE_ENDIAN */ 9105 } fields; 9106 } FALCON_IF_rescal_TYPE; 9107 9108 typedef FALCON_IF_rescal_TYPE FALCON_IF_RESCAL_TYPE_T; 9109 9110 typedef union { 9111 uint32_t data; 9112 struct { 9113 #if IS_BIG_ENDIAN 9114 uint32_t reserved : 16; 9115 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane0_TYPE[15:03] - RSVD */ 9116 uint32_t pmd_signal_detect_0 : 1; /* FALCON_IF_repeater_status_lane0_TYPE[02] - RO */ 9117 uint32_t pmd_tx_clk_vld_0 : 1; /* FALCON_IF_repeater_status_lane0_TYPE[01] - RO */ 9118 uint32_t pmd_rx_clk_vld_0 : 1; /* FALCON_IF_repeater_status_lane0_TYPE[00] - RO */ 9119 #endif /* IS_BIG_ENDIAN */ 9120 #if IS_LITTLE_ENDIAN 9121 uint32_t pmd_rx_clk_vld_0 : 1; /* FALCON_IF_repeater_status_lane0_TYPE[00] - RO */ 9122 uint32_t pmd_tx_clk_vld_0 : 1; /* FALCON_IF_repeater_status_lane0_TYPE[01] - RO */ 9123 uint32_t pmd_signal_detect_0 : 1; /* FALCON_IF_repeater_status_lane0_TYPE[02] - RO */ 9124 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane0_TYPE[15:03] - RSVD */ 9125 uint32_t reserved : 16; 9126 #endif /* IS_LITTLE_ENDIAN */ 9127 } fields; 9128 } FALCON_IF_repeater_status_lane0_TYPE; 9129 9130 typedef FALCON_IF_repeater_status_lane0_TYPE FALCON_IF_REPEATER_STATUS_LANE0_TYPE_T; 9131 9132 typedef union { 9133 uint32_t data; 9134 struct { 9135 #if IS_BIG_ENDIAN 9136 uint32_t reserved : 16; 9137 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane1_TYPE[15:03] - RSVD */ 9138 uint32_t pmd_signal_detect_1 : 1; /* FALCON_IF_repeater_status_lane1_TYPE[02] - RO */ 9139 uint32_t pmd_tx_clk_vld_1 : 1; /* FALCON_IF_repeater_status_lane1_TYPE[01] - RO */ 9140 uint32_t pmd_rx_clk_vld_1 : 1; /* FALCON_IF_repeater_status_lane1_TYPE[00] - RO */ 9141 #endif /* IS_BIG_ENDIAN */ 9142 #if IS_LITTLE_ENDIAN 9143 uint32_t pmd_rx_clk_vld_1 : 1; /* FALCON_IF_repeater_status_lane1_TYPE[00] - RO */ 9144 uint32_t pmd_tx_clk_vld_1 : 1; /* FALCON_IF_repeater_status_lane1_TYPE[01] - RO */ 9145 uint32_t pmd_signal_detect_1 : 1; /* FALCON_IF_repeater_status_lane1_TYPE[02] - RO */ 9146 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane1_TYPE[15:03] - RSVD */ 9147 uint32_t reserved : 16; 9148 #endif /* IS_LITTLE_ENDIAN */ 9149 } fields; 9150 } FALCON_IF_repeater_status_lane1_TYPE; 9151 9152 typedef FALCON_IF_repeater_status_lane1_TYPE FALCON_IF_REPEATER_STATUS_LANE1_TYPE_T; 9153 9154 typedef union { 9155 uint32_t data; 9156 struct { 9157 #if IS_BIG_ENDIAN 9158 uint32_t reserved : 16; 9159 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane2_TYPE[15:03] - RSVD */ 9160 uint32_t pmd_signal_detect_2 : 1; /* FALCON_IF_repeater_status_lane2_TYPE[02] - RO */ 9161 uint32_t pmd_tx_clk_vld_2 : 1; /* FALCON_IF_repeater_status_lane2_TYPE[01] - RO */ 9162 uint32_t pmd_rx_clk_vld_2 : 1; /* FALCON_IF_repeater_status_lane2_TYPE[00] - RO */ 9163 #endif /* IS_BIG_ENDIAN */ 9164 #if IS_LITTLE_ENDIAN 9165 uint32_t pmd_rx_clk_vld_2 : 1; /* FALCON_IF_repeater_status_lane2_TYPE[00] - RO */ 9166 uint32_t pmd_tx_clk_vld_2 : 1; /* FALCON_IF_repeater_status_lane2_TYPE[01] - RO */ 9167 uint32_t pmd_signal_detect_2 : 1; /* FALCON_IF_repeater_status_lane2_TYPE[02] - RO */ 9168 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane2_TYPE[15:03] - RSVD */ 9169 uint32_t reserved : 16; 9170 #endif /* IS_LITTLE_ENDIAN */ 9171 } fields; 9172 } FALCON_IF_repeater_status_lane2_TYPE; 9173 9174 typedef FALCON_IF_repeater_status_lane2_TYPE FALCON_IF_REPEATER_STATUS_LANE2_TYPE_T; 9175 9176 typedef union { 9177 uint32_t data; 9178 struct { 9179 #if IS_BIG_ENDIAN 9180 uint32_t reserved : 16; 9181 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane3_TYPE[15:03] - RSVD */ 9182 uint32_t pmd_signal_detect_3 : 1; /* FALCON_IF_repeater_status_lane3_TYPE[02] - RO */ 9183 uint32_t pmd_tx_clk_vld_3 : 1; /* FALCON_IF_repeater_status_lane3_TYPE[01] - RO */ 9184 uint32_t pmd_rx_clk_vld_3 : 1; /* FALCON_IF_repeater_status_lane3_TYPE[00] - RO */ 9185 #endif /* IS_BIG_ENDIAN */ 9186 #if IS_LITTLE_ENDIAN 9187 uint32_t pmd_rx_clk_vld_3 : 1; /* FALCON_IF_repeater_status_lane3_TYPE[00] - RO */ 9188 uint32_t pmd_tx_clk_vld_3 : 1; /* FALCON_IF_repeater_status_lane3_TYPE[01] - RO */ 9189 uint32_t pmd_signal_detect_3 : 1; /* FALCON_IF_repeater_status_lane3_TYPE[02] - RO */ 9190 uint32_t reserved_03 : 13; /* FALCON_IF_repeater_status_lane3_TYPE[15:03] - RSVD */ 9191 uint32_t reserved : 16; 9192 #endif /* IS_LITTLE_ENDIAN */ 9193 } fields; 9194 } FALCON_IF_repeater_status_lane3_TYPE; 9195 9196 typedef FALCON_IF_repeater_status_lane3_TYPE FALCON_IF_REPEATER_STATUS_LANE3_TYPE_T; 9197 9198 typedef union { 9199 uint32_t data; 9200 struct { 9201 #if IS_BIG_ENDIAN 9202 uint32_t reserved : 16; 9203 uint32_t reserved_01 : 15; /* FALCON_IF_pmd_pll_sts_TYPE[15:01] - RSVD */ 9204 uint32_t pmd_pll_lock : 1; /* FALCON_IF_pmd_pll_sts_TYPE[00] - RO */ 9205 #endif /* IS_BIG_ENDIAN */ 9206 #if IS_LITTLE_ENDIAN 9207 uint32_t pmd_pll_lock : 1; /* FALCON_IF_pmd_pll_sts_TYPE[00] - RO */ 9208 uint32_t reserved_01 : 15; /* FALCON_IF_pmd_pll_sts_TYPE[15:01] - RSVD */ 9209 uint32_t reserved : 16; 9210 #endif /* IS_LITTLE_ENDIAN */ 9211 } fields; 9212 } FALCON_IF_pmd_pll_sts_TYPE; 9213 9214 typedef FALCON_IF_pmd_pll_sts_TYPE FALCON_IF_PMD_PLL_STS_TYPE_T; 9215 9216 9217 /*-----------------------------------------------*/ 9218 /* Structs for M10G_SIGDET Bank */ 9219 /*-----------------------------------------------*/ 9220 typedef union { 9221 uint32_t data; 9222 struct { 9223 #if IS_BIG_ENDIAN 9224 uint32_t reserved : 16; 9225 uint32_t reserved_09 : 7; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[15:09] - RSVD */ 9226 uint32_t signal_detect_frc_val : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[08] - RW */ 9227 uint32_t signal_detect_frc : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[07] - RW */ 9228 uint32_t energy_detect_frc_val : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[06] - RW */ 9229 uint32_t energy_detect_frc : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[05] - RW */ 9230 uint32_t signal_detect_filter_1us : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[04] - RW */ 9231 uint32_t ignore_lp_mode : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[03] - RW */ 9232 uint32_t ext_los_inv : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[02] - RW */ 9233 uint32_t ext_los_en : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[01] - RW */ 9234 uint32_t afe_signal_detect_dis : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[00] - RW */ 9235 #endif /* IS_BIG_ENDIAN */ 9236 #if IS_LITTLE_ENDIAN 9237 uint32_t afe_signal_detect_dis : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[00] - RW */ 9238 uint32_t ext_los_en : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[01] - RW */ 9239 uint32_t ext_los_inv : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[02] - RW */ 9240 uint32_t ignore_lp_mode : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[03] - RW */ 9241 uint32_t signal_detect_filter_1us : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[04] - RW */ 9242 uint32_t energy_detect_frc : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[05] - RW */ 9243 uint32_t energy_detect_frc_val : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[06] - RW */ 9244 uint32_t signal_detect_frc : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[07] - RW */ 9245 uint32_t signal_detect_frc_val : 1; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[08] - RW */ 9246 uint32_t reserved_09 : 7; /* M10G_SIGDET_SIGDET_CTRL_1_TYPE[15:09] - RSVD */ 9247 uint32_t reserved : 16; 9248 #endif /* IS_LITTLE_ENDIAN */ 9249 } fields; 9250 } M10G_SIGDET_SIGDET_CTRL_1_TYPE; 9251 9252 typedef M10G_SIGDET_SIGDET_CTRL_1_TYPE M10G_SIGDET_SIGDET_CTRL_1_TYPE_T; 9253 9254 9255 /*-----------------------------------------------*/ 9256 /* Structs for M10G_CKRST_CTRL Bank */ 9257 /*-----------------------------------------------*/ 9258 typedef union { 9259 uint32_t data; 9260 struct { 9261 #if IS_BIG_ENDIAN 9262 uint32_t reserved : 16; 9263 uint32_t osr_mode_frc : 1; /* M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE[15] - RW */ 9264 uint32_t reserved_04 : 11; /* M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE[14:04] - RSVD */ 9265 uint32_t osr_mode_frc_val : 4; /* M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE[03:00] - RW */ 9266 #endif /* IS_BIG_ENDIAN */ 9267 #if IS_LITTLE_ENDIAN 9268 uint32_t osr_mode_frc_val : 4; /* M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE[03:00] - RW */ 9269 uint32_t reserved_04 : 11; /* M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE[14:04] - RSVD */ 9270 uint32_t osr_mode_frc : 1; /* M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE[15] - RW */ 9271 uint32_t reserved : 16; 9272 #endif /* IS_LITTLE_ENDIAN */ 9273 } fields; 9274 } M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE; 9275 9276 typedef M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE M10G_CKRST_CTRL_OSR_MODE_CONTROL_TYPE_T; 9277 9278 typedef union { 9279 uint32_t data; 9280 struct { 9281 #if IS_BIG_ENDIAN 9282 uint32_t reserved : 16; 9283 uint32_t reserved_15 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[15] - RSVD */ 9284 uint32_t reserved_14 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[14] - RSVD */ 9285 uint32_t reserved_13 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[13] - RSVD */ 9286 uint32_t reserved_12 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[12] - RSVD */ 9287 uint32_t ln_tx_s_pwrdn : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[11] - RW */ 9288 uint32_t reserved_10 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[10] - RSVD */ 9289 uint32_t reserved_09 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[09] - RSVD */ 9290 uint32_t reserved_08 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[08] - RSVD */ 9291 uint32_t reserved_07 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[07] - RSVD */ 9292 uint32_t ln_rx_s_pwrdn : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[06] - RW */ 9293 uint32_t reserved_05 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[05] - RSVD */ 9294 uint32_t reserved_04 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[04] - RSVD */ 9295 uint32_t reserved_03 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[03] - RSVD */ 9296 uint32_t reserved_02 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[02] - RSVD */ 9297 uint32_t ln_dp_s_rstb : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[01] - RW */ 9298 uint32_t ln_s_rstb : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[00] - RW */ 9299 #endif /* IS_BIG_ENDIAN */ 9300 #if IS_LITTLE_ENDIAN 9301 uint32_t ln_s_rstb : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[00] - RW */ 9302 uint32_t ln_dp_s_rstb : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[01] - RW */ 9303 uint32_t reserved_02 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[02] - RSVD */ 9304 uint32_t reserved_03 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[03] - RSVD */ 9305 uint32_t reserved_04 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[04] - RSVD */ 9306 uint32_t reserved_05 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[05] - RSVD */ 9307 uint32_t ln_rx_s_pwrdn : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[06] - RW */ 9308 uint32_t reserved_07 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[07] - RSVD */ 9309 uint32_t reserved_08 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[08] - RSVD */ 9310 uint32_t reserved_09 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[09] - RSVD */ 9311 uint32_t reserved_10 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[10] - RSVD */ 9312 uint32_t ln_tx_s_pwrdn : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[11] - RW */ 9313 uint32_t reserved_12 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[12] - RSVD */ 9314 uint32_t reserved_13 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[13] - RSVD */ 9315 uint32_t reserved_14 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[14] - RSVD */ 9316 uint32_t reserved_15 : 1; /* M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[15] - RSVD */ 9317 uint32_t reserved : 16; 9318 #endif /* IS_LITTLE_ENDIAN */ 9319 } fields; 9320 } M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE; 9321 9322 typedef M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE_T; 9323 9324 typedef union { 9325 uint32_t data; 9326 struct { 9327 #if IS_BIG_ENDIAN 9328 uint32_t reserved : 16; 9329 uint32_t reserved_11 : 5; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:11] - RSVD */ 9330 uint32_t afe_txclk_reset_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[10] - RW */ 9331 uint32_t afe_txclk_reset_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[09] - RW */ 9332 uint32_t afe_sigdet_pwrdn : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[08] - RW */ 9333 uint32_t afe_tx_reset_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[07] - RW */ 9334 uint32_t afe_tx_reset_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[06] - RW */ 9335 uint32_t afe_tx_pwrdn_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[05] - RW */ 9336 uint32_t afe_tx_pwrdn_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[04] - RW */ 9337 uint32_t afe_rx_reset_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 9338 uint32_t afe_rx_reset_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 9339 uint32_t afe_rx_pwrdn_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 9340 uint32_t afe_rx_pwrdn_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 9341 #endif /* IS_BIG_ENDIAN */ 9342 #if IS_LITTLE_ENDIAN 9343 uint32_t afe_rx_pwrdn_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 9344 uint32_t afe_rx_pwrdn_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 9345 uint32_t afe_rx_reset_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 9346 uint32_t afe_rx_reset_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 9347 uint32_t afe_tx_pwrdn_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[04] - RW */ 9348 uint32_t afe_tx_pwrdn_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[05] - RW */ 9349 uint32_t afe_tx_reset_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[06] - RW */ 9350 uint32_t afe_tx_reset_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[07] - RW */ 9351 uint32_t afe_sigdet_pwrdn : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[08] - RW */ 9352 uint32_t afe_txclk_reset_frc : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[09] - RW */ 9353 uint32_t afe_txclk_reset_frc_val : 1; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[10] - RW */ 9354 uint32_t reserved_11 : 5; /* M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:11] - RSVD */ 9355 uint32_t reserved : 16; 9356 #endif /* IS_LITTLE_ENDIAN */ 9357 } fields; 9358 } M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE; 9359 9360 typedef M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE_T; 9361 9362 9363 /*-----------------------------------------------*/ 9364 /* Structs for M10G_PLL_CAL Bank */ 9365 /*-----------------------------------------------*/ 9366 typedef union { 9367 uint32_t data; 9368 struct { 9369 #if IS_BIG_ENDIAN 9370 uint32_t reserved : 16; 9371 uint32_t pll_fail_stky : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[15] - RO */ 9372 uint32_t cal_state : 4; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[14:11] - RO */ 9373 uint32_t cal_valid : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[10] - RO */ 9374 uint32_t pll_lock : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[09] - RO */ 9375 uint32_t pll_lock_bar_stky : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[08] - RO */ 9376 uint32_t reserved_07 : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[07] - RSVD */ 9377 uint32_t pll_range : 7; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[06:00] - RO */ 9378 #endif /* IS_BIG_ENDIAN */ 9379 #if IS_LITTLE_ENDIAN 9380 uint32_t pll_range : 7; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[06:00] - RO */ 9381 uint32_t reserved_07 : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[07] - RSVD */ 9382 uint32_t pll_lock_bar_stky : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[08] - RO */ 9383 uint32_t pll_lock : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[09] - RO */ 9384 uint32_t cal_valid : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[10] - RO */ 9385 uint32_t cal_state : 4; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[14:11] - RO */ 9386 uint32_t pll_fail_stky : 1; /* M10G_PLL_CAL_PLL_CALSTS_0_TYPE[15] - RO */ 9387 uint32_t reserved : 16; 9388 #endif /* IS_LITTLE_ENDIAN */ 9389 } fields; 9390 } M10G_PLL_CAL_PLL_CALSTS_0_TYPE; 9391 9392 typedef M10G_PLL_CAL_PLL_CALSTS_0_TYPE M10G_PLL_CAL_PLL_CALSTS_0_TYPE_T; 9393 9394 9395 /*-----------------------------------------------*/ 9396 /* Structs for M10G_AMSCOM Bank */ 9397 /*-----------------------------------------------*/ 9398 typedef union { 9399 uint32_t data; 9400 struct { 9401 #if IS_BIG_ENDIAN 9402 uint32_t reserved : 16; 9403 uint32_t div : 5; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[15:11] - RW */ 9404 uint32_t reserved_10 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[10] - RSVD */ 9405 uint32_t reserved_09 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[09] - RSVD */ 9406 uint32_t reserved_08 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[08] - RSVD */ 9407 uint32_t reserved_07 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[07] - RSVD */ 9408 uint32_t reserved_06 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[06] - RSVD */ 9409 uint32_t reserved_05 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[05] - RSVD */ 9410 uint32_t reserved_04 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[04] - RSVD */ 9411 uint32_t reserved_03 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[03] - RSVD */ 9412 uint32_t reserved_01 : 2; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[02:01] - RSVD */ 9413 uint32_t reserved_00 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[00] - RSVD */ 9414 #endif /* IS_BIG_ENDIAN */ 9415 #if IS_LITTLE_ENDIAN 9416 uint32_t reserved_00 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[00] - RSVD */ 9417 uint32_t reserved_01 : 2; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[02:01] - RSVD */ 9418 uint32_t reserved_03 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[03] - RSVD */ 9419 uint32_t reserved_04 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[04] - RSVD */ 9420 uint32_t reserved_05 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[05] - RSVD */ 9421 uint32_t reserved_06 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[06] - RSVD */ 9422 uint32_t reserved_07 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[07] - RSVD */ 9423 uint32_t reserved_08 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[08] - RSVD */ 9424 uint32_t reserved_09 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[09] - RSVD */ 9425 uint32_t reserved_10 : 1; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[10] - RSVD */ 9426 uint32_t div : 5; /* M10G_AMSCOM_PLL_CTRL_3_TYPE[15:11] - RW */ 9427 uint32_t reserved : 16; 9428 #endif /* IS_LITTLE_ENDIAN */ 9429 } fields; 9430 } M10G_AMSCOM_PLL_CTRL_3_TYPE; 9431 9432 typedef M10G_AMSCOM_PLL_CTRL_3_TYPE M10G_AMSCOM_PLL_CTRL_3_TYPE_T; 9433 9434 typedef union { 9435 uint32_t data; 9436 struct { 9437 #if IS_BIG_ENDIAN 9438 uint32_t reserved : 16; 9439 uint32_t i_ndiv_frac_l : 4; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[15:12] - RW */ 9440 uint32_t reserved_10 : 2; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[11:10] - RSVD */ 9441 uint32_t reserved_09 : 1; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[09] - RSVD */ 9442 uint32_t reserved_08 : 1; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[08] - RSVD */ 9443 uint32_t reserved_05 : 3; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[07:05] - RSVD */ 9444 uint32_t reserved_04 : 1; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[04] - RSVD */ 9445 uint32_t reserved_00 : 4; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[03:00] - RSVD */ 9446 #endif /* IS_BIG_ENDIAN */ 9447 #if IS_LITTLE_ENDIAN 9448 uint32_t reserved_00 : 4; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[03:00] - RSVD */ 9449 uint32_t reserved_04 : 1; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[04] - RSVD */ 9450 uint32_t reserved_05 : 3; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[07:05] - RSVD */ 9451 uint32_t reserved_08 : 1; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[08] - RSVD */ 9452 uint32_t reserved_09 : 1; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[09] - RSVD */ 9453 uint32_t reserved_10 : 2; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[11:10] - RSVD */ 9454 uint32_t i_ndiv_frac_l : 4; /* M10G_AMSCOM_PLL_CTRL_6_TYPE[15:12] - RW */ 9455 uint32_t reserved : 16; 9456 #endif /* IS_LITTLE_ENDIAN */ 9457 } fields; 9458 } M10G_AMSCOM_PLL_CTRL_6_TYPE; 9459 9460 typedef M10G_AMSCOM_PLL_CTRL_6_TYPE M10G_AMSCOM_PLL_CTRL_6_TYPE_T; 9461 9462 typedef union { 9463 uint32_t data; 9464 struct { 9465 #if IS_BIG_ENDIAN 9466 uint32_t reserved : 16; 9467 uint32_t reserved_14 : 2; /* M10G_AMSCOM_PLL_CTRL_7_TYPE[15:14] - RSVD */ 9468 uint32_t i_ndiv_frac_h : 14; /* M10G_AMSCOM_PLL_CTRL_7_TYPE[13:00] - RW */ 9469 #endif /* IS_BIG_ENDIAN */ 9470 #if IS_LITTLE_ENDIAN 9471 uint32_t i_ndiv_frac_h : 14; /* M10G_AMSCOM_PLL_CTRL_7_TYPE[13:00] - RW */ 9472 uint32_t reserved_14 : 2; /* M10G_AMSCOM_PLL_CTRL_7_TYPE[15:14] - RSVD */ 9473 uint32_t reserved : 16; 9474 #endif /* IS_LITTLE_ENDIAN */ 9475 } fields; 9476 } M10G_AMSCOM_PLL_CTRL_7_TYPE; 9477 9478 typedef M10G_AMSCOM_PLL_CTRL_7_TYPE M10G_AMSCOM_PLL_CTRL_7_TYPE_T; 9479 9480 typedef union { 9481 uint32_t data; 9482 struct { 9483 #if IS_BIG_ENDIAN 9484 uint32_t reserved : 16; 9485 uint32_t i_ndiv_dither_en : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[15] - RW */ 9486 uint32_t i_pll_sdm_pwrdnb : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[14] - RW */ 9487 uint32_t mmd_en : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[13] - RW */ 9488 uint32_t mmd_prsc4or5pwdb : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[12] - RW */ 9489 uint32_t mmd_prsc8or9pwdb : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[11] - RW */ 9490 uint32_t mmd_div_range : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[10] - RW */ 9491 uint32_t i_ndiv_int : 10; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[09:00] - RW */ 9492 #endif /* IS_BIG_ENDIAN */ 9493 #if IS_LITTLE_ENDIAN 9494 uint32_t i_ndiv_int : 10; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[09:00] - RW */ 9495 uint32_t mmd_div_range : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[10] - RW */ 9496 uint32_t mmd_prsc8or9pwdb : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[11] - RW */ 9497 uint32_t mmd_prsc4or5pwdb : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[12] - RW */ 9498 uint32_t mmd_en : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[13] - RW */ 9499 uint32_t i_pll_sdm_pwrdnb : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[14] - RW */ 9500 uint32_t i_ndiv_dither_en : 1; /* M10G_AMSCOM_PLL_CTRL_8_TYPE[15] - RW */ 9501 uint32_t reserved : 16; 9502 #endif /* IS_LITTLE_ENDIAN */ 9503 } fields; 9504 } M10G_AMSCOM_PLL_CTRL_8_TYPE; 9505 9506 typedef M10G_AMSCOM_PLL_CTRL_8_TYPE M10G_AMSCOM_PLL_CTRL_8_TYPE_T; 9507 9508 typedef union { 9509 uint32_t data; 9510 struct { 9511 #if IS_BIG_ENDIAN 9512 uint32_t reserved : 16; 9513 uint32_t reserved_14 : 2; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[15:14] - RSVD */ 9514 uint32_t reserved_11 : 3; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[13:11] - RSVD */ 9515 uint32_t reserved_08 : 3; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[10:08] - RSVD */ 9516 uint32_t reserved_07 : 1; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[07] - RSVD */ 9517 uint32_t reserved_03 : 4; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[06:03] - RSVD */ 9518 uint32_t i_pll_frac_mode : 2; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[02:01] - RW */ 9519 uint32_t mmd_resetb : 1; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[00] - RW */ 9520 #endif /* IS_BIG_ENDIAN */ 9521 #if IS_LITTLE_ENDIAN 9522 uint32_t mmd_resetb : 1; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[00] - RW */ 9523 uint32_t i_pll_frac_mode : 2; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[02:01] - RW */ 9524 uint32_t reserved_03 : 4; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[06:03] - RSVD */ 9525 uint32_t reserved_07 : 1; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[07] - RSVD */ 9526 uint32_t reserved_08 : 3; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[10:08] - RSVD */ 9527 uint32_t reserved_11 : 3; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[13:11] - RSVD */ 9528 uint32_t reserved_14 : 2; /* M10G_AMSCOM_PLL_CTRL_9_TYPE[15:14] - RSVD */ 9529 uint32_t reserved : 16; 9530 #endif /* IS_LITTLE_ENDIAN */ 9531 } fields; 9532 } M10G_AMSCOM_PLL_CTRL_9_TYPE; 9533 9534 typedef M10G_AMSCOM_PLL_CTRL_9_TYPE M10G_AMSCOM_PLL_CTRL_9_TYPE_T; 9535 9536 9537 /*-----------------------------------------------*/ 9538 /* Structs for M10G_PATT_GEN Bank */ 9539 /*-----------------------------------------------*/ 9540 typedef union { 9541 uint32_t data; 9542 struct { 9543 #if IS_BIG_ENDIAN 9544 uint32_t reserved : 16; 9545 uint32_t patt_gen_seq_0 : 16; /* M10G_PATT_GEN_patt_gen_seq_0_TYPE[15:00] - RW */ 9546 #endif /* IS_BIG_ENDIAN */ 9547 #if IS_LITTLE_ENDIAN 9548 uint32_t patt_gen_seq_0 : 16; /* M10G_PATT_GEN_patt_gen_seq_0_TYPE[15:00] - RW */ 9549 uint32_t reserved : 16; 9550 #endif /* IS_LITTLE_ENDIAN */ 9551 } fields; 9552 } M10G_PATT_GEN_patt_gen_seq_0_TYPE; 9553 9554 typedef M10G_PATT_GEN_patt_gen_seq_0_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_0_TYPE_T; 9555 9556 typedef union { 9557 uint32_t data; 9558 struct { 9559 #if IS_BIG_ENDIAN 9560 uint32_t reserved : 16; 9561 uint32_t patt_gen_seq_1 : 16; /* M10G_PATT_GEN_patt_gen_seq_1_TYPE[15:00] - RW */ 9562 #endif /* IS_BIG_ENDIAN */ 9563 #if IS_LITTLE_ENDIAN 9564 uint32_t patt_gen_seq_1 : 16; /* M10G_PATT_GEN_patt_gen_seq_1_TYPE[15:00] - RW */ 9565 uint32_t reserved : 16; 9566 #endif /* IS_LITTLE_ENDIAN */ 9567 } fields; 9568 } M10G_PATT_GEN_patt_gen_seq_1_TYPE; 9569 9570 typedef M10G_PATT_GEN_patt_gen_seq_1_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_1_TYPE_T; 9571 9572 typedef union { 9573 uint32_t data; 9574 struct { 9575 #if IS_BIG_ENDIAN 9576 uint32_t reserved : 16; 9577 uint32_t patt_gen_seq_2 : 16; /* M10G_PATT_GEN_patt_gen_seq_2_TYPE[15:00] - RW */ 9578 #endif /* IS_BIG_ENDIAN */ 9579 #if IS_LITTLE_ENDIAN 9580 uint32_t patt_gen_seq_2 : 16; /* M10G_PATT_GEN_patt_gen_seq_2_TYPE[15:00] - RW */ 9581 uint32_t reserved : 16; 9582 #endif /* IS_LITTLE_ENDIAN */ 9583 } fields; 9584 } M10G_PATT_GEN_patt_gen_seq_2_TYPE; 9585 9586 typedef M10G_PATT_GEN_patt_gen_seq_2_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_2_TYPE_T; 9587 9588 typedef union { 9589 uint32_t data; 9590 struct { 9591 #if IS_BIG_ENDIAN 9592 uint32_t reserved : 16; 9593 uint32_t patt_gen_seq_3 : 16; /* M10G_PATT_GEN_patt_gen_seq_3_TYPE[15:00] - RW */ 9594 #endif /* IS_BIG_ENDIAN */ 9595 #if IS_LITTLE_ENDIAN 9596 uint32_t patt_gen_seq_3 : 16; /* M10G_PATT_GEN_patt_gen_seq_3_TYPE[15:00] - RW */ 9597 uint32_t reserved : 16; 9598 #endif /* IS_LITTLE_ENDIAN */ 9599 } fields; 9600 } M10G_PATT_GEN_patt_gen_seq_3_TYPE; 9601 9602 typedef M10G_PATT_GEN_patt_gen_seq_3_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_3_TYPE_T; 9603 9604 typedef union { 9605 uint32_t data; 9606 struct { 9607 #if IS_BIG_ENDIAN 9608 uint32_t reserved : 16; 9609 uint32_t patt_gen_seq_4 : 16; /* M10G_PATT_GEN_patt_gen_seq_4_TYPE[15:00] - RW */ 9610 #endif /* IS_BIG_ENDIAN */ 9611 #if IS_LITTLE_ENDIAN 9612 uint32_t patt_gen_seq_4 : 16; /* M10G_PATT_GEN_patt_gen_seq_4_TYPE[15:00] - RW */ 9613 uint32_t reserved : 16; 9614 #endif /* IS_LITTLE_ENDIAN */ 9615 } fields; 9616 } M10G_PATT_GEN_patt_gen_seq_4_TYPE; 9617 9618 typedef M10G_PATT_GEN_patt_gen_seq_4_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_4_TYPE_T; 9619 9620 typedef union { 9621 uint32_t data; 9622 struct { 9623 #if IS_BIG_ENDIAN 9624 uint32_t reserved : 16; 9625 uint32_t patt_gen_seq_5 : 16; /* M10G_PATT_GEN_patt_gen_seq_5_TYPE[15:00] - RW */ 9626 #endif /* IS_BIG_ENDIAN */ 9627 #if IS_LITTLE_ENDIAN 9628 uint32_t patt_gen_seq_5 : 16; /* M10G_PATT_GEN_patt_gen_seq_5_TYPE[15:00] - RW */ 9629 uint32_t reserved : 16; 9630 #endif /* IS_LITTLE_ENDIAN */ 9631 } fields; 9632 } M10G_PATT_GEN_patt_gen_seq_5_TYPE; 9633 9634 typedef M10G_PATT_GEN_patt_gen_seq_5_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_5_TYPE_T; 9635 9636 typedef union { 9637 uint32_t data; 9638 struct { 9639 #if IS_BIG_ENDIAN 9640 uint32_t reserved : 16; 9641 uint32_t patt_gen_seq_6 : 16; /* M10G_PATT_GEN_patt_gen_seq_6_TYPE[15:00] - RW */ 9642 #endif /* IS_BIG_ENDIAN */ 9643 #if IS_LITTLE_ENDIAN 9644 uint32_t patt_gen_seq_6 : 16; /* M10G_PATT_GEN_patt_gen_seq_6_TYPE[15:00] - RW */ 9645 uint32_t reserved : 16; 9646 #endif /* IS_LITTLE_ENDIAN */ 9647 } fields; 9648 } M10G_PATT_GEN_patt_gen_seq_6_TYPE; 9649 9650 typedef M10G_PATT_GEN_patt_gen_seq_6_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_6_TYPE_T; 9651 9652 typedef union { 9653 uint32_t data; 9654 struct { 9655 #if IS_BIG_ENDIAN 9656 uint32_t reserved : 16; 9657 uint32_t patt_gen_seq_7 : 16; /* M10G_PATT_GEN_patt_gen_seq_7_TYPE[15:00] - RW */ 9658 #endif /* IS_BIG_ENDIAN */ 9659 #if IS_LITTLE_ENDIAN 9660 uint32_t patt_gen_seq_7 : 16; /* M10G_PATT_GEN_patt_gen_seq_7_TYPE[15:00] - RW */ 9661 uint32_t reserved : 16; 9662 #endif /* IS_LITTLE_ENDIAN */ 9663 } fields; 9664 } M10G_PATT_GEN_patt_gen_seq_7_TYPE; 9665 9666 typedef M10G_PATT_GEN_patt_gen_seq_7_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_7_TYPE_T; 9667 9668 typedef union { 9669 uint32_t data; 9670 struct { 9671 #if IS_BIG_ENDIAN 9672 uint32_t reserved : 16; 9673 uint32_t patt_gen_seq_8 : 16; /* M10G_PATT_GEN_patt_gen_seq_8_TYPE[15:00] - RW */ 9674 #endif /* IS_BIG_ENDIAN */ 9675 #if IS_LITTLE_ENDIAN 9676 uint32_t patt_gen_seq_8 : 16; /* M10G_PATT_GEN_patt_gen_seq_8_TYPE[15:00] - RW */ 9677 uint32_t reserved : 16; 9678 #endif /* IS_LITTLE_ENDIAN */ 9679 } fields; 9680 } M10G_PATT_GEN_patt_gen_seq_8_TYPE; 9681 9682 typedef M10G_PATT_GEN_patt_gen_seq_8_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_8_TYPE_T; 9683 9684 typedef union { 9685 uint32_t data; 9686 struct { 9687 #if IS_BIG_ENDIAN 9688 uint32_t reserved : 16; 9689 uint32_t patt_gen_seq_9 : 16; /* M10G_PATT_GEN_patt_gen_seq_9_TYPE[15:00] - RW */ 9690 #endif /* IS_BIG_ENDIAN */ 9691 #if IS_LITTLE_ENDIAN 9692 uint32_t patt_gen_seq_9 : 16; /* M10G_PATT_GEN_patt_gen_seq_9_TYPE[15:00] - RW */ 9693 uint32_t reserved : 16; 9694 #endif /* IS_LITTLE_ENDIAN */ 9695 } fields; 9696 } M10G_PATT_GEN_patt_gen_seq_9_TYPE; 9697 9698 typedef M10G_PATT_GEN_patt_gen_seq_9_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_9_TYPE_T; 9699 9700 typedef union { 9701 uint32_t data; 9702 struct { 9703 #if IS_BIG_ENDIAN 9704 uint32_t reserved : 16; 9705 uint32_t patt_gen_seq_10 : 16; /* M10G_PATT_GEN_patt_gen_seq_10_TYPE[15:00] - RW */ 9706 #endif /* IS_BIG_ENDIAN */ 9707 #if IS_LITTLE_ENDIAN 9708 uint32_t patt_gen_seq_10 : 16; /* M10G_PATT_GEN_patt_gen_seq_10_TYPE[15:00] - RW */ 9709 uint32_t reserved : 16; 9710 #endif /* IS_LITTLE_ENDIAN */ 9711 } fields; 9712 } M10G_PATT_GEN_patt_gen_seq_10_TYPE; 9713 9714 typedef M10G_PATT_GEN_patt_gen_seq_10_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_10_TYPE_T; 9715 9716 typedef union { 9717 uint32_t data; 9718 struct { 9719 #if IS_BIG_ENDIAN 9720 uint32_t reserved : 16; 9721 uint32_t patt_gen_seq_11 : 16; /* M10G_PATT_GEN_patt_gen_seq_11_TYPE[15:00] - RW */ 9722 #endif /* IS_BIG_ENDIAN */ 9723 #if IS_LITTLE_ENDIAN 9724 uint32_t patt_gen_seq_11 : 16; /* M10G_PATT_GEN_patt_gen_seq_11_TYPE[15:00] - RW */ 9725 uint32_t reserved : 16; 9726 #endif /* IS_LITTLE_ENDIAN */ 9727 } fields; 9728 } M10G_PATT_GEN_patt_gen_seq_11_TYPE; 9729 9730 typedef M10G_PATT_GEN_patt_gen_seq_11_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_11_TYPE_T; 9731 9732 typedef union { 9733 uint32_t data; 9734 struct { 9735 #if IS_BIG_ENDIAN 9736 uint32_t reserved : 16; 9737 uint32_t patt_gen_seq_12 : 16; /* M10G_PATT_GEN_patt_gen_seq_12_TYPE[15:00] - RW */ 9738 #endif /* IS_BIG_ENDIAN */ 9739 #if IS_LITTLE_ENDIAN 9740 uint32_t patt_gen_seq_12 : 16; /* M10G_PATT_GEN_patt_gen_seq_12_TYPE[15:00] - RW */ 9741 uint32_t reserved : 16; 9742 #endif /* IS_LITTLE_ENDIAN */ 9743 } fields; 9744 } M10G_PATT_GEN_patt_gen_seq_12_TYPE; 9745 9746 typedef M10G_PATT_GEN_patt_gen_seq_12_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_12_TYPE_T; 9747 9748 typedef union { 9749 uint32_t data; 9750 struct { 9751 #if IS_BIG_ENDIAN 9752 uint32_t reserved : 16; 9753 uint32_t patt_gen_seq_13 : 16; /* M10G_PATT_GEN_patt_gen_seq_13_TYPE[15:00] - RW */ 9754 #endif /* IS_BIG_ENDIAN */ 9755 #if IS_LITTLE_ENDIAN 9756 uint32_t patt_gen_seq_13 : 16; /* M10G_PATT_GEN_patt_gen_seq_13_TYPE[15:00] - RW */ 9757 uint32_t reserved : 16; 9758 #endif /* IS_LITTLE_ENDIAN */ 9759 } fields; 9760 } M10G_PATT_GEN_patt_gen_seq_13_TYPE; 9761 9762 typedef M10G_PATT_GEN_patt_gen_seq_13_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_13_TYPE_T; 9763 9764 typedef union { 9765 uint32_t data; 9766 struct { 9767 #if IS_BIG_ENDIAN 9768 uint32_t reserved : 16; 9769 uint32_t patt_gen_seq_14 : 16; /* M10G_PATT_GEN_patt_gen_seq_14_TYPE[15:00] - RW */ 9770 #endif /* IS_BIG_ENDIAN */ 9771 #if IS_LITTLE_ENDIAN 9772 uint32_t patt_gen_seq_14 : 16; /* M10G_PATT_GEN_patt_gen_seq_14_TYPE[15:00] - RW */ 9773 uint32_t reserved : 16; 9774 #endif /* IS_LITTLE_ENDIAN */ 9775 } fields; 9776 } M10G_PATT_GEN_patt_gen_seq_14_TYPE; 9777 9778 typedef M10G_PATT_GEN_patt_gen_seq_14_TYPE M10G_PATT_GEN_PATT_GEN_SEQ_14_TYPE_T; 9779 9780 9781 /*-----------------------------------------------*/ 9782 /* Structs for M10G_TX_FED Bank */ 9783 /*-----------------------------------------------*/ 9784 typedef union { 9785 uint32_t data; 9786 struct { 9787 #if IS_BIG_ENDIAN 9788 uint32_t reserved : 16; 9789 uint32_t reserved_10 : 6; /* M10G_TX_FED_txfir_control1_TYPE[15:10] - RSVD */ 9790 uint32_t txfir_post_override : 5; /* M10G_TX_FED_txfir_control1_TYPE[09:05] - RW */ 9791 uint32_t reserved_04 : 1; /* M10G_TX_FED_txfir_control1_TYPE[04] - RSVD */ 9792 uint32_t txfir_pre_override : 4; /* M10G_TX_FED_txfir_control1_TYPE[03:00] - RW */ 9793 #endif /* IS_BIG_ENDIAN */ 9794 #if IS_LITTLE_ENDIAN 9795 uint32_t txfir_pre_override : 4; /* M10G_TX_FED_txfir_control1_TYPE[03:00] - RW */ 9796 uint32_t reserved_04 : 1; /* M10G_TX_FED_txfir_control1_TYPE[04] - RSVD */ 9797 uint32_t txfir_post_override : 5; /* M10G_TX_FED_txfir_control1_TYPE[09:05] - RW */ 9798 uint32_t reserved_10 : 6; /* M10G_TX_FED_txfir_control1_TYPE[15:10] - RSVD */ 9799 uint32_t reserved : 16; 9800 #endif /* IS_LITTLE_ENDIAN */ 9801 } fields; 9802 } M10G_TX_FED_txfir_control1_TYPE; 9803 9804 typedef M10G_TX_FED_txfir_control1_TYPE M10G_TX_FED_TXFIR_CONTROL1_TYPE_T; 9805 9806 typedef union { 9807 uint32_t data; 9808 struct { 9809 #if IS_BIG_ENDIAN 9810 uint32_t reserved : 16; 9811 uint32_t txfir_override_en : 1; /* M10G_TX_FED_txfir_control2_TYPE[15] - RW */ 9812 uint32_t reserved_11 : 4; /* M10G_TX_FED_txfir_control2_TYPE[14:11] - RSVD */ 9813 uint32_t txfir_post2 : 4; /* M10G_TX_FED_txfir_control2_TYPE[10:07] - RW */ 9814 uint32_t reserved_06 : 1; /* M10G_TX_FED_txfir_control2_TYPE[06] - RSVD */ 9815 uint32_t txfir_main_override : 6; /* M10G_TX_FED_txfir_control2_TYPE[05:00] - RW */ 9816 #endif /* IS_BIG_ENDIAN */ 9817 #if IS_LITTLE_ENDIAN 9818 uint32_t txfir_main_override : 6; /* M10G_TX_FED_txfir_control2_TYPE[05:00] - RW */ 9819 uint32_t reserved_06 : 1; /* M10G_TX_FED_txfir_control2_TYPE[06] - RSVD */ 9820 uint32_t txfir_post2 : 4; /* M10G_TX_FED_txfir_control2_TYPE[10:07] - RW */ 9821 uint32_t reserved_11 : 4; /* M10G_TX_FED_txfir_control2_TYPE[14:11] - RSVD */ 9822 uint32_t txfir_override_en : 1; /* M10G_TX_FED_txfir_control2_TYPE[15] - RW */ 9823 uint32_t reserved : 16; 9824 #endif /* IS_LITTLE_ENDIAN */ 9825 } fields; 9826 } M10G_TX_FED_txfir_control2_TYPE; 9827 9828 typedef M10G_TX_FED_txfir_control2_TYPE M10G_TX_FED_TXFIR_CONTROL2_TYPE_T; 9829 9830 typedef union { 9831 uint32_t data; 9832 struct { 9833 #if IS_BIG_ENDIAN 9834 uint32_t reserved : 16; 9835 uint32_t txfir_post2_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[15:12] - RW */ 9836 uint32_t txfir_post_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[11:08] - RW */ 9837 uint32_t txfir_main_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[07:04] - RW */ 9838 uint32_t txfir_pre_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[03:00] - RW */ 9839 #endif /* IS_BIG_ENDIAN */ 9840 #if IS_LITTLE_ENDIAN 9841 uint32_t txfir_pre_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[03:00] - RW */ 9842 uint32_t txfir_main_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[07:04] - RW */ 9843 uint32_t txfir_post_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[11:08] - RW */ 9844 uint32_t txfir_post2_offset : 4; /* M10G_TX_FED_txfir_control3_TYPE[15:12] - RW */ 9845 uint32_t reserved : 16; 9846 #endif /* IS_LITTLE_ENDIAN */ 9847 } fields; 9848 } M10G_TX_FED_txfir_control3_TYPE; 9849 9850 typedef M10G_TX_FED_txfir_control3_TYPE M10G_TX_FED_TXFIR_CONTROL3_TYPE_T; 9851 9852 9853 /*-----------------------------------------------*/ 9854 /* Structs for M10G_TLB_RX Bank */ 9855 /*-----------------------------------------------*/ 9856 typedef union { 9857 uint32_t data; 9858 struct { 9859 #if IS_BIG_ENDIAN 9860 uint32_t reserved : 16; 9861 uint32_t reserved_12 : 4; /* M10G_TLB_RX_prbs_chk_config_TYPE[15:12] - RSVD */ 9862 uint32_t prbs_chk_clk_en_frc_on : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[11] - RW */ 9863 uint32_t reserved_10 : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[10] - RSVD */ 9864 uint32_t reserved_09 : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[09] - RSVD */ 9865 uint32_t reserved_08 : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[08] - RSVD */ 9866 uint32_t prbs_chk_en_auto_mode : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[07] - RW */ 9867 uint32_t prbs_chk_mode : 2; /* M10G_TLB_RX_prbs_chk_config_TYPE[06:05] - RW */ 9868 uint32_t prbs_chk_inv : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[04] - RW */ 9869 uint32_t prbs_chk_mode_sel : 3; /* M10G_TLB_RX_prbs_chk_config_TYPE[03:01] - RW */ 9870 uint32_t prbs_chk_en : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[00] - RW */ 9871 #endif /* IS_BIG_ENDIAN */ 9872 #if IS_LITTLE_ENDIAN 9873 uint32_t prbs_chk_en : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[00] - RW */ 9874 uint32_t prbs_chk_mode_sel : 3; /* M10G_TLB_RX_prbs_chk_config_TYPE[03:01] - RW */ 9875 uint32_t prbs_chk_inv : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[04] - RW */ 9876 uint32_t prbs_chk_mode : 2; /* M10G_TLB_RX_prbs_chk_config_TYPE[06:05] - RW */ 9877 uint32_t prbs_chk_en_auto_mode : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[07] - RW */ 9878 uint32_t reserved_08 : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[08] - RSVD */ 9879 uint32_t reserved_09 : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[09] - RSVD */ 9880 uint32_t reserved_10 : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[10] - RSVD */ 9881 uint32_t prbs_chk_clk_en_frc_on : 1; /* M10G_TLB_RX_prbs_chk_config_TYPE[11] - RW */ 9882 uint32_t reserved_12 : 4; /* M10G_TLB_RX_prbs_chk_config_TYPE[15:12] - RSVD */ 9883 uint32_t reserved : 16; 9884 #endif /* IS_LITTLE_ENDIAN */ 9885 } fields; 9886 } M10G_TLB_RX_prbs_chk_config_TYPE; 9887 9888 typedef M10G_TLB_RX_prbs_chk_config_TYPE M10G_TLB_RX_PRBS_CHK_CONFIG_TYPE_T; 9889 9890 typedef union { 9891 uint32_t data; 9892 struct { 9893 #if IS_BIG_ENDIAN 9894 uint32_t reserved : 16; 9895 uint32_t reserved_04 : 12; /* M10G_TLB_RX_dig_lpbk_config_TYPE[15:04] - RSVD */ 9896 uint32_t reserved_03 : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[03] - RSVD */ 9897 uint32_t reserved_02 : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[02] - RSVD */ 9898 uint32_t reserved_01 : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[01] - RSVD */ 9899 uint32_t dig_lpbk_en : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[00] - RW */ 9900 #endif /* IS_BIG_ENDIAN */ 9901 #if IS_LITTLE_ENDIAN 9902 uint32_t dig_lpbk_en : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[00] - RW */ 9903 uint32_t reserved_01 : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[01] - RSVD */ 9904 uint32_t reserved_02 : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[02] - RSVD */ 9905 uint32_t reserved_03 : 1; /* M10G_TLB_RX_dig_lpbk_config_TYPE[03] - RSVD */ 9906 uint32_t reserved_04 : 12; /* M10G_TLB_RX_dig_lpbk_config_TYPE[15:04] - RSVD */ 9907 uint32_t reserved : 16; 9908 #endif /* IS_LITTLE_ENDIAN */ 9909 } fields; 9910 } M10G_TLB_RX_dig_lpbk_config_TYPE; 9911 9912 typedef M10G_TLB_RX_dig_lpbk_config_TYPE M10G_TLB_RX_DIG_LPBK_CONFIG_TYPE_T; 9913 9914 typedef union { 9915 uint32_t data; 9916 struct { 9917 #if IS_BIG_ENDIAN 9918 uint32_t reserved : 16; 9919 uint32_t reserved_03 : 13; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[15:03] - RSVD */ 9920 uint32_t reserved_02 : 1; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[02] - RSVD */ 9921 uint32_t reserved_01 : 1; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[01] - RSVD */ 9922 uint32_t rx_pmd_dp_invert : 1; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[00] - RW */ 9923 #endif /* IS_BIG_ENDIAN */ 9924 #if IS_LITTLE_ENDIAN 9925 uint32_t rx_pmd_dp_invert : 1; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[00] - RW */ 9926 uint32_t reserved_01 : 1; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[01] - RSVD */ 9927 uint32_t reserved_02 : 1; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[02] - RSVD */ 9928 uint32_t reserved_03 : 13; /* M10G_TLB_RX_tlb_rx_misc_config_TYPE[15:03] - RSVD */ 9929 uint32_t reserved : 16; 9930 #endif /* IS_LITTLE_ENDIAN */ 9931 } fields; 9932 } M10G_TLB_RX_tlb_rx_misc_config_TYPE; 9933 9934 typedef M10G_TLB_RX_tlb_rx_misc_config_TYPE M10G_TLB_RX_TLB_RX_MISC_CONFIG_TYPE_T; 9935 9936 typedef union { 9937 uint32_t data; 9938 struct { 9939 #if IS_BIG_ENDIAN 9940 uint32_t reserved : 16; 9941 uint32_t reserved_01 : 15; /* M10G_TLB_RX_prbs_chk_lock_status_TYPE[15:01] - RSVD */ 9942 uint32_t prbs_chk_lock : 1; /* M10G_TLB_RX_prbs_chk_lock_status_TYPE[00] - RO */ 9943 #endif /* IS_BIG_ENDIAN */ 9944 #if IS_LITTLE_ENDIAN 9945 uint32_t prbs_chk_lock : 1; /* M10G_TLB_RX_prbs_chk_lock_status_TYPE[00] - RO */ 9946 uint32_t reserved_01 : 15; /* M10G_TLB_RX_prbs_chk_lock_status_TYPE[15:01] - RSVD */ 9947 uint32_t reserved : 16; 9948 #endif /* IS_LITTLE_ENDIAN */ 9949 } fields; 9950 } M10G_TLB_RX_prbs_chk_lock_status_TYPE; 9951 9952 typedef M10G_TLB_RX_prbs_chk_lock_status_TYPE M10G_TLB_RX_PRBS_CHK_LOCK_STATUS_TYPE_T; 9953 9954 typedef union { 9955 uint32_t data; 9956 struct { 9957 #if IS_BIG_ENDIAN 9958 uint32_t reserved : 16; 9959 uint32_t prbs_chk_lock_lost_lh : 1; /* M10G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[15] - RO */ 9960 uint32_t prbs_chk_err_cnt_msb : 15; /* M10G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[14:00] - RO */ 9961 #endif /* IS_BIG_ENDIAN */ 9962 #if IS_LITTLE_ENDIAN 9963 uint32_t prbs_chk_err_cnt_msb : 15; /* M10G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[14:00] - RO */ 9964 uint32_t prbs_chk_lock_lost_lh : 1; /* M10G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[15] - RO */ 9965 uint32_t reserved : 16; 9966 #endif /* IS_LITTLE_ENDIAN */ 9967 } fields; 9968 } M10G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE; 9969 9970 typedef M10G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE M10G_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_TYPE_T; 9971 9972 typedef union { 9973 uint32_t data; 9974 struct { 9975 #if IS_BIG_ENDIAN 9976 uint32_t reserved : 16; 9977 uint32_t prbs_chk_err_cnt_lsb : 16; /* M10G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE[15:00] - RO */ 9978 #endif /* IS_BIG_ENDIAN */ 9979 #if IS_LITTLE_ENDIAN 9980 uint32_t prbs_chk_err_cnt_lsb : 16; /* M10G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE[15:00] - RO */ 9981 uint32_t reserved : 16; 9982 #endif /* IS_LITTLE_ENDIAN */ 9983 } fields; 9984 } M10G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE; 9985 9986 typedef M10G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE M10G_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_TYPE_T; 9987 9988 typedef union { 9989 uint32_t data; 9990 struct { 9991 #if IS_BIG_ENDIAN 9992 uint32_t reserved : 16; 9993 uint32_t reserved_02 : 14; /* M10G_TLB_RX_pmd_rx_lock_status_TYPE[15:02] - RSVD */ 9994 uint32_t pmd_rx_lock_change : 1; /* M10G_TLB_RX_pmd_rx_lock_status_TYPE[01] - RO */ 9995 uint32_t pmd_rx_lock : 1; /* M10G_TLB_RX_pmd_rx_lock_status_TYPE[00] - RO */ 9996 #endif /* IS_BIG_ENDIAN */ 9997 #if IS_LITTLE_ENDIAN 9998 uint32_t pmd_rx_lock : 1; /* M10G_TLB_RX_pmd_rx_lock_status_TYPE[00] - RO */ 9999 uint32_t pmd_rx_lock_change : 1; /* M10G_TLB_RX_pmd_rx_lock_status_TYPE[01] - RO */ 10000 uint32_t reserved_02 : 14; /* M10G_TLB_RX_pmd_rx_lock_status_TYPE[15:02] - RSVD */ 10001 uint32_t reserved : 16; 10002 #endif /* IS_LITTLE_ENDIAN */ 10003 } fields; 10004 } M10G_TLB_RX_pmd_rx_lock_status_TYPE; 10005 10006 typedef M10G_TLB_RX_pmd_rx_lock_status_TYPE M10G_TLB_RX_PMD_RX_LOCK_STATUS_TYPE_T; 10007 10008 10009 /*-----------------------------------------------*/ 10010 /* Structs for M10G_TLB_TX Bank */ 10011 /*-----------------------------------------------*/ 10012 typedef union { 10013 uint32_t data; 10014 struct { 10015 #if IS_BIG_ENDIAN 10016 uint32_t reserved : 16; 10017 uint32_t patt_gen_start_pos : 4; /* M10G_TLB_TX_patt_gen_config_TYPE[15:12] - RW */ 10018 uint32_t patt_gen_stop_pos : 4; /* M10G_TLB_TX_patt_gen_config_TYPE[11:08] - RW */ 10019 uint32_t reserved_04 : 4; /* M10G_TLB_TX_patt_gen_config_TYPE[07:04] - RSVD */ 10020 uint32_t patt_gen_mode_sel : 3; /* M10G_TLB_TX_patt_gen_config_TYPE[03:01] - RW */ 10021 uint32_t patt_gen_en : 1; /* M10G_TLB_TX_patt_gen_config_TYPE[00] - RW */ 10022 #endif /* IS_BIG_ENDIAN */ 10023 #if IS_LITTLE_ENDIAN 10024 uint32_t patt_gen_en : 1; /* M10G_TLB_TX_patt_gen_config_TYPE[00] - RW */ 10025 uint32_t patt_gen_mode_sel : 3; /* M10G_TLB_TX_patt_gen_config_TYPE[03:01] - RW */ 10026 uint32_t reserved_04 : 4; /* M10G_TLB_TX_patt_gen_config_TYPE[07:04] - RSVD */ 10027 uint32_t patt_gen_stop_pos : 4; /* M10G_TLB_TX_patt_gen_config_TYPE[11:08] - RW */ 10028 uint32_t patt_gen_start_pos : 4; /* M10G_TLB_TX_patt_gen_config_TYPE[15:12] - RW */ 10029 uint32_t reserved : 16; 10030 #endif /* IS_LITTLE_ENDIAN */ 10031 } fields; 10032 } M10G_TLB_TX_patt_gen_config_TYPE; 10033 10034 typedef M10G_TLB_TX_patt_gen_config_TYPE M10G_TLB_TX_PATT_GEN_CONFIG_TYPE_T; 10035 10036 typedef union { 10037 uint32_t data; 10038 struct { 10039 #if IS_BIG_ENDIAN 10040 uint32_t reserved : 16; 10041 uint32_t reserved_06 : 10; /* M10G_TLB_TX_prbs_gen_config_TYPE[15:06] - RSVD */ 10042 uint32_t prbs_gen_err_ins : 1; /* M10G_TLB_TX_prbs_gen_config_TYPE[05] - RW */ 10043 uint32_t prbs_gen_inv : 1; /* M10G_TLB_TX_prbs_gen_config_TYPE[04] - RW */ 10044 uint32_t prbs_gen_mode_sel : 3; /* M10G_TLB_TX_prbs_gen_config_TYPE[03:01] - RW */ 10045 uint32_t prbs_gen_en : 1; /* M10G_TLB_TX_prbs_gen_config_TYPE[00] - RW */ 10046 #endif /* IS_BIG_ENDIAN */ 10047 #if IS_LITTLE_ENDIAN 10048 uint32_t prbs_gen_en : 1; /* M10G_TLB_TX_prbs_gen_config_TYPE[00] - RW */ 10049 uint32_t prbs_gen_mode_sel : 3; /* M10G_TLB_TX_prbs_gen_config_TYPE[03:01] - RW */ 10050 uint32_t prbs_gen_inv : 1; /* M10G_TLB_TX_prbs_gen_config_TYPE[04] - RW */ 10051 uint32_t prbs_gen_err_ins : 1; /* M10G_TLB_TX_prbs_gen_config_TYPE[05] - RW */ 10052 uint32_t reserved_06 : 10; /* M10G_TLB_TX_prbs_gen_config_TYPE[15:06] - RSVD */ 10053 uint32_t reserved : 16; 10054 #endif /* IS_LITTLE_ENDIAN */ 10055 } fields; 10056 } M10G_TLB_TX_prbs_gen_config_TYPE; 10057 10058 typedef M10G_TLB_TX_prbs_gen_config_TYPE M10G_TLB_TX_PRBS_GEN_CONFIG_TYPE_T; 10059 10060 typedef union { 10061 uint32_t data; 10062 struct { 10063 #if IS_BIG_ENDIAN 10064 uint32_t reserved : 16; 10065 uint32_t reserved_03 : 13; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[15:03] - RSVD */ 10066 uint32_t reserved_02 : 1; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[02] - RSVD */ 10067 uint32_t reserved_01 : 1; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[01] - RSVD */ 10068 uint32_t rmt_lpbk_en : 1; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[00] - RW */ 10069 #endif /* IS_BIG_ENDIAN */ 10070 #if IS_LITTLE_ENDIAN 10071 uint32_t rmt_lpbk_en : 1; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[00] - RW */ 10072 uint32_t reserved_01 : 1; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[01] - RSVD */ 10073 uint32_t reserved_02 : 1; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[02] - RSVD */ 10074 uint32_t reserved_03 : 13; /* M10G_TLB_TX_rmt_lpbk_config_TYPE[15:03] - RSVD */ 10075 uint32_t reserved : 16; 10076 #endif /* IS_LITTLE_ENDIAN */ 10077 } fields; 10078 } M10G_TLB_TX_rmt_lpbk_config_TYPE; 10079 10080 typedef M10G_TLB_TX_rmt_lpbk_config_TYPE M10G_TLB_TX_RMT_LPBK_CONFIG_TYPE_T; 10081 10082 typedef union { 10083 uint32_t data; 10084 struct { 10085 #if IS_BIG_ENDIAN 10086 uint32_t reserved : 16; 10087 uint32_t reserved_03 : 13; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[15:03] - RSVD */ 10088 uint32_t reserved_02 : 1; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[02] - RSVD */ 10089 uint32_t reserved_01 : 1; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[01] - RSVD */ 10090 uint32_t tx_pmd_dp_invert : 1; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[00] - RW */ 10091 #endif /* IS_BIG_ENDIAN */ 10092 #if IS_LITTLE_ENDIAN 10093 uint32_t tx_pmd_dp_invert : 1; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[00] - RW */ 10094 uint32_t reserved_01 : 1; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[01] - RSVD */ 10095 uint32_t reserved_02 : 1; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[02] - RSVD */ 10096 uint32_t reserved_03 : 13; /* M10G_TLB_TX_tlb_tx_misc_config_TYPE[15:03] - RSVD */ 10097 uint32_t reserved : 16; 10098 #endif /* IS_LITTLE_ENDIAN */ 10099 } fields; 10100 } M10G_TLB_TX_tlb_tx_misc_config_TYPE; 10101 10102 typedef M10G_TLB_TX_tlb_tx_misc_config_TYPE M10G_TLB_TX_TLB_TX_MISC_CONFIG_TYPE_T; 10103 10104 10105 /*-----------------------------------------------*/ 10106 /* Structs for F25G_SIGDET Bank */ 10107 /*-----------------------------------------------*/ 10108 typedef union { 10109 uint32_t data; 10110 struct { 10111 #if IS_BIG_ENDIAN 10112 uint32_t reserved : 16; 10113 uint32_t energy_detect_mask_count : 5; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[15:11] - RW */ 10114 uint32_t reserved_09 : 2; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[10:09] - RSVD */ 10115 uint32_t signal_detect_frc_val : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[08] - RW */ 10116 uint32_t signal_detect_frc : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[07] - RW */ 10117 uint32_t energy_detect_frc_val : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[06] - RW */ 10118 uint32_t energy_detect_frc : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[05] - RW */ 10119 uint32_t signal_detect_filter_1us : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[04] - RW */ 10120 uint32_t ignore_lp_mode : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[03] - RW */ 10121 uint32_t ext_los_inv : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[02] - RW */ 10122 uint32_t ext_los_en : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[01] - RW */ 10123 uint32_t afe_signal_detect_dis : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[00] - RW */ 10124 #endif /* IS_BIG_ENDIAN */ 10125 #if IS_LITTLE_ENDIAN 10126 uint32_t afe_signal_detect_dis : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[00] - RW */ 10127 uint32_t ext_los_en : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[01] - RW */ 10128 uint32_t ext_los_inv : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[02] - RW */ 10129 uint32_t ignore_lp_mode : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[03] - RW */ 10130 uint32_t signal_detect_filter_1us : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[04] - RW */ 10131 uint32_t energy_detect_frc : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[05] - RW */ 10132 uint32_t energy_detect_frc_val : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[06] - RW */ 10133 uint32_t signal_detect_frc : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[07] - RW */ 10134 uint32_t signal_detect_frc_val : 1; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[08] - RW */ 10135 uint32_t reserved_09 : 2; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[10:09] - RSVD */ 10136 uint32_t energy_detect_mask_count : 5; /* F25G_SIGDET_SIGDET_CTRL_1_TYPE[15:11] - RW */ 10137 uint32_t reserved : 16; 10138 #endif /* IS_LITTLE_ENDIAN */ 10139 } fields; 10140 } F25G_SIGDET_SIGDET_CTRL_1_TYPE; 10141 10142 typedef F25G_SIGDET_SIGDET_CTRL_1_TYPE F25G_SIGDET_SIGDET_CTRL_1_TYPE_T; 10143 10144 10145 /*-----------------------------------------------*/ 10146 /* Structs for F25G_CKRST_CTRL_RPTR Bank */ 10147 /*-----------------------------------------------*/ 10148 typedef union { 10149 uint32_t data; 10150 struct { 10151 #if IS_BIG_ENDIAN 10152 uint32_t reserved : 16; 10153 uint32_t osr_mode_frc : 1; /* F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE[15] - RW */ 10154 uint32_t reserved_04 : 11; /* F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE[14:04] - RSVD */ 10155 uint32_t osr_mode_frc_val : 4; /* F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE[03:00] - RW */ 10156 #endif /* IS_BIG_ENDIAN */ 10157 #if IS_LITTLE_ENDIAN 10158 uint32_t osr_mode_frc_val : 4; /* F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE[03:00] - RW */ 10159 uint32_t reserved_04 : 11; /* F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE[14:04] - RSVD */ 10160 uint32_t osr_mode_frc : 1; /* F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE[15] - RW */ 10161 uint32_t reserved : 16; 10162 #endif /* IS_LITTLE_ENDIAN */ 10163 } fields; 10164 } F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE; 10165 10166 typedef F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_TYPE_T; 10167 10168 typedef union { 10169 uint32_t data; 10170 struct { 10171 #if IS_BIG_ENDIAN 10172 uint32_t reserved : 16; 10173 uint32_t reserved_05 : 11; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[15:05] - RSVD */ 10174 uint32_t afe_sigdet_pwrdn : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[04] - RW */ 10175 uint32_t ln_tx_s_pwrdn : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[03] - RW */ 10176 uint32_t ln_rx_s_pwrdn : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[02] - RW */ 10177 uint32_t ln_dp_s_rstb : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[01] - RW */ 10178 uint32_t reserved_00 : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[00] - RSVD */ 10179 #endif /* IS_BIG_ENDIAN */ 10180 #if IS_LITTLE_ENDIAN 10181 uint32_t reserved_00 : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[00] - RSVD */ 10182 uint32_t ln_dp_s_rstb : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[01] - RW */ 10183 uint32_t ln_rx_s_pwrdn : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[02] - RW */ 10184 uint32_t ln_tx_s_pwrdn : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[03] - RW */ 10185 uint32_t afe_sigdet_pwrdn : 1; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[04] - RW */ 10186 uint32_t reserved_05 : 11; /* F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE[15:05] - RSVD */ 10187 uint32_t reserved : 16; 10188 #endif /* IS_LITTLE_ENDIAN */ 10189 } fields; 10190 } F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE; 10191 10192 typedef F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_TYPE_T; 10193 10194 typedef union { 10195 uint32_t data; 10196 struct { 10197 #if IS_BIG_ENDIAN 10198 uint32_t reserved : 16; 10199 uint32_t reserved_10 : 6; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10200 uint32_t afe_rx_rclk20_pwrdn_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[09] - RW */ 10201 uint32_t afe_rx_rclk20_pwrdn_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[08] - RW */ 10202 uint32_t afe_tx_reset_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[07] - RW */ 10203 uint32_t afe_tx_reset_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[06] - RW */ 10204 uint32_t afe_tx_pwrdn_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[05] - RW */ 10205 uint32_t afe_tx_pwrdn_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[04] - RW */ 10206 uint32_t afe_rx_reset_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 10207 uint32_t afe_rx_reset_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 10208 uint32_t afe_rx_pwrdn_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 10209 uint32_t afe_rx_pwrdn_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 10210 #endif /* IS_BIG_ENDIAN */ 10211 #if IS_LITTLE_ENDIAN 10212 uint32_t afe_rx_pwrdn_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 10213 uint32_t afe_rx_pwrdn_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 10214 uint32_t afe_rx_reset_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 10215 uint32_t afe_rx_reset_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 10216 uint32_t afe_tx_pwrdn_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[04] - RW */ 10217 uint32_t afe_tx_pwrdn_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[05] - RW */ 10218 uint32_t afe_tx_reset_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[06] - RW */ 10219 uint32_t afe_tx_reset_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[07] - RW */ 10220 uint32_t afe_rx_rclk20_pwrdn_frc : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[08] - RW */ 10221 uint32_t afe_rx_rclk20_pwrdn_frc_val : 1; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[09] - RW */ 10222 uint32_t reserved_10 : 6; /* F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10223 uint32_t reserved : 16; 10224 #endif /* IS_LITTLE_ENDIAN */ 10225 } fields; 10226 } F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE; 10227 10228 typedef F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE_T; 10229 10230 typedef union { 10231 uint32_t data; 10232 struct { 10233 #if IS_BIG_ENDIAN 10234 uint32_t reserved : 16; 10235 uint32_t reserved_01 : 15; /* F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE[15:01] - RSVD */ 10236 uint32_t ln_s_rstb : 1; /* F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE[00] - RW */ 10237 #endif /* IS_BIG_ENDIAN */ 10238 #if IS_LITTLE_ENDIAN 10239 uint32_t ln_s_rstb : 1; /* F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE[00] - RW */ 10240 uint32_t reserved_01 : 15; /* F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE[15:01] - RSVD */ 10241 uint32_t reserved : 16; 10242 #endif /* IS_LITTLE_ENDIAN */ 10243 } fields; 10244 } F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE; 10245 10246 typedef F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_TYPE_T; 10247 10248 10249 /*-----------------------------------------------*/ 10250 /* Structs for F25G_PLL_CAL_COM Bank */ 10251 /*-----------------------------------------------*/ 10252 typedef union { 10253 uint32_t data; 10254 struct { 10255 #if IS_BIG_ENDIAN 10256 uint32_t reserved : 16; 10257 uint32_t reserved_14 : 2; /* F25G_PLL_CAL_COM_CTL_5_TYPE[15:14] - RSVD */ 10258 uint32_t refclk_divcnt : 14; /* F25G_PLL_CAL_COM_CTL_5_TYPE[13:00] - RW */ 10259 #endif /* IS_BIG_ENDIAN */ 10260 #if IS_LITTLE_ENDIAN 10261 uint32_t refclk_divcnt : 14; /* F25G_PLL_CAL_COM_CTL_5_TYPE[13:00] - RW */ 10262 uint32_t reserved_14 : 2; /* F25G_PLL_CAL_COM_CTL_5_TYPE[15:14] - RSVD */ 10263 uint32_t reserved : 16; 10264 #endif /* IS_LITTLE_ENDIAN */ 10265 } fields; 10266 } F25G_PLL_CAL_COM_CTL_5_TYPE; 10267 10268 typedef F25G_PLL_CAL_COM_CTL_5_TYPE F25G_PLL_CAL_COM_CTL_5_TYPE_T; 10269 10270 typedef union { 10271 uint32_t data; 10272 struct { 10273 #if IS_BIG_ENDIAN 10274 uint32_t reserved : 16; 10275 uint32_t reserved_11 : 5; /* F25G_PLL_CAL_COM_CTL_7_TYPE[15:11] - RSVD */ 10276 uint32_t reserved_10 : 1; /* F25G_PLL_CAL_COM_CTL_7_TYPE[10] - RSVD */ 10277 uint32_t reserved_06 : 4; /* F25G_PLL_CAL_COM_CTL_7_TYPE[09:06] - RSVD */ 10278 uint32_t reserved_05 : 1; /* F25G_PLL_CAL_COM_CTL_7_TYPE[05] - RSVD */ 10279 uint32_t pll_mode : 5; /* F25G_PLL_CAL_COM_CTL_7_TYPE[04:00] - RW */ 10280 #endif /* IS_BIG_ENDIAN */ 10281 #if IS_LITTLE_ENDIAN 10282 uint32_t pll_mode : 5; /* F25G_PLL_CAL_COM_CTL_7_TYPE[04:00] - RW */ 10283 uint32_t reserved_05 : 1; /* F25G_PLL_CAL_COM_CTL_7_TYPE[05] - RSVD */ 10284 uint32_t reserved_06 : 4; /* F25G_PLL_CAL_COM_CTL_7_TYPE[09:06] - RSVD */ 10285 uint32_t reserved_10 : 1; /* F25G_PLL_CAL_COM_CTL_7_TYPE[10] - RSVD */ 10286 uint32_t reserved_11 : 5; /* F25G_PLL_CAL_COM_CTL_7_TYPE[15:11] - RSVD */ 10287 uint32_t reserved : 16; 10288 #endif /* IS_LITTLE_ENDIAN */ 10289 } fields; 10290 } F25G_PLL_CAL_COM_CTL_7_TYPE; 10291 10292 typedef F25G_PLL_CAL_COM_CTL_7_TYPE F25G_PLL_CAL_COM_CTL_7_TYPE_T; 10293 10294 typedef union { 10295 uint32_t data; 10296 struct { 10297 #if IS_BIG_ENDIAN 10298 uint32_t reserved : 16; 10299 uint32_t lost_pll_lock_sm : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[15] - RO */ 10300 uint32_t cap_done : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[14] - RO */ 10301 uint32_t cap_pass : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[13] - RO */ 10302 uint32_t freq_done_sm : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[12] - RO */ 10303 uint32_t freq_pass_sm : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[11] - RO */ 10304 uint32_t pll_seq_done : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[10] - RO */ 10305 uint32_t pll_seq_pass : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[09] - RO */ 10306 uint32_t pll_lock : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[08] - RO */ 10307 uint32_t reserved_07 : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[07] - RSVD */ 10308 uint32_t cap_done_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[06] - RO */ 10309 uint32_t cap_pass_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[05] - RO */ 10310 uint32_t freq_done_sm_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[04] - RO */ 10311 uint32_t freq_pass_sm_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[03] - RO */ 10312 uint32_t pll_seq_done_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[02] - RO */ 10313 uint32_t pll_seq_pass_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[01] - RO */ 10314 uint32_t pll_lock_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[00] - RO */ 10315 #endif /* IS_BIG_ENDIAN */ 10316 #if IS_LITTLE_ENDIAN 10317 uint32_t pll_lock_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[00] - RO */ 10318 uint32_t pll_seq_pass_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[01] - RO */ 10319 uint32_t pll_seq_done_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[02] - RO */ 10320 uint32_t freq_pass_sm_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[03] - RO */ 10321 uint32_t freq_done_sm_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[04] - RO */ 10322 uint32_t cap_pass_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[05] - RO */ 10323 uint32_t cap_done_lh_ll : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[06] - RO */ 10324 uint32_t reserved_07 : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[07] - RSVD */ 10325 uint32_t pll_lock : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[08] - RO */ 10326 uint32_t pll_seq_pass : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[09] - RO */ 10327 uint32_t pll_seq_done : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[10] - RO */ 10328 uint32_t freq_pass_sm : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[11] - RO */ 10329 uint32_t freq_done_sm : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[12] - RO */ 10330 uint32_t cap_pass : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[13] - RO */ 10331 uint32_t cap_done : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[14] - RO */ 10332 uint32_t lost_pll_lock_sm : 1; /* F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE[15] - RO */ 10333 uint32_t reserved : 16; 10334 #endif /* IS_LITTLE_ENDIAN */ 10335 } fields; 10336 } F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE; 10337 10338 typedef F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE F25G_PLL_CAL_COM_CTL_STATUS_0_TYPE_T; 10339 10340 10341 /*-----------------------------------------------*/ 10342 /* Structs for F25G_AMS_COM Bank */ 10343 /*-----------------------------------------------*/ 10344 typedef union { 10345 uint32_t data; 10346 struct { 10347 #if IS_BIG_ENDIAN 10348 uint32_t reserved : 16; 10349 uint32_t ams_pll_test_rx : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[15] - RW */ 10350 uint32_t ams_pll_test_pll : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[14] - RW */ 10351 uint32_t reserved_13 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[13] - RSVD */ 10352 uint32_t reserved_12 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[12] - RSVD */ 10353 uint32_t reserved_11 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[11] - RSVD */ 10354 uint32_t reserved_10 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[10] - RSVD */ 10355 uint32_t reserved_09 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[09] - RSVD */ 10356 uint32_t reserved_08 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[08] - RSVD */ 10357 uint32_t reserved_07 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[07] - RSVD */ 10358 uint32_t reserved_06 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[06] - RSVD */ 10359 uint32_t reserved_05 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[05] - RSVD */ 10360 uint32_t reserved_04 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[04] - RSVD */ 10361 uint32_t reserved_03 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[03] - RSVD */ 10362 uint32_t reserved_02 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[02] - RSVD */ 10363 uint32_t reserved_01 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[01] - RSVD */ 10364 uint32_t reserved_00 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[00] - RSVD */ 10365 #endif /* IS_BIG_ENDIAN */ 10366 #if IS_LITTLE_ENDIAN 10367 uint32_t reserved_00 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[00] - RSVD */ 10368 uint32_t reserved_01 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[01] - RSVD */ 10369 uint32_t reserved_02 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[02] - RSVD */ 10370 uint32_t reserved_03 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[03] - RSVD */ 10371 uint32_t reserved_04 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[04] - RSVD */ 10372 uint32_t reserved_05 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[05] - RSVD */ 10373 uint32_t reserved_06 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[06] - RSVD */ 10374 uint32_t reserved_07 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[07] - RSVD */ 10375 uint32_t reserved_08 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[08] - RSVD */ 10376 uint32_t reserved_09 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[09] - RSVD */ 10377 uint32_t reserved_10 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[10] - RSVD */ 10378 uint32_t reserved_11 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[11] - RSVD */ 10379 uint32_t reserved_12 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[12] - RSVD */ 10380 uint32_t reserved_13 : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[13] - RSVD */ 10381 uint32_t ams_pll_test_pll : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[14] - RW */ 10382 uint32_t ams_pll_test_rx : 1; /* F25G_AMS_COM_PLL_CONTROL_3_TYPE[15] - RW */ 10383 uint32_t reserved : 16; 10384 #endif /* IS_LITTLE_ENDIAN */ 10385 } fields; 10386 } F25G_AMS_COM_PLL_CONTROL_3_TYPE; 10387 10388 typedef F25G_AMS_COM_PLL_CONTROL_3_TYPE F25G_AMS_COM_PLL_CONTROL_3_TYPE_T; 10389 10390 10391 /*-----------------------------------------------*/ 10392 /* Structs for F25G_PATT_GEN_COM Bank */ 10393 /*-----------------------------------------------*/ 10394 typedef union { 10395 uint32_t data; 10396 struct { 10397 #if IS_BIG_ENDIAN 10398 uint32_t reserved : 16; 10399 uint32_t patt_gen_seq_0 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_0_TYPE[15:00] - RW */ 10400 #endif /* IS_BIG_ENDIAN */ 10401 #if IS_LITTLE_ENDIAN 10402 uint32_t patt_gen_seq_0 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_0_TYPE[15:00] - RW */ 10403 uint32_t reserved : 16; 10404 #endif /* IS_LITTLE_ENDIAN */ 10405 } fields; 10406 } F25G_PATT_GEN_COM_patt_gen_seq_0_TYPE; 10407 10408 typedef F25G_PATT_GEN_COM_patt_gen_seq_0_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_0_TYPE_T; 10409 10410 typedef union { 10411 uint32_t data; 10412 struct { 10413 #if IS_BIG_ENDIAN 10414 uint32_t reserved : 16; 10415 uint32_t patt_gen_seq_1 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_1_TYPE[15:00] - RW */ 10416 #endif /* IS_BIG_ENDIAN */ 10417 #if IS_LITTLE_ENDIAN 10418 uint32_t patt_gen_seq_1 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_1_TYPE[15:00] - RW */ 10419 uint32_t reserved : 16; 10420 #endif /* IS_LITTLE_ENDIAN */ 10421 } fields; 10422 } F25G_PATT_GEN_COM_patt_gen_seq_1_TYPE; 10423 10424 typedef F25G_PATT_GEN_COM_patt_gen_seq_1_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_1_TYPE_T; 10425 10426 typedef union { 10427 uint32_t data; 10428 struct { 10429 #if IS_BIG_ENDIAN 10430 uint32_t reserved : 16; 10431 uint32_t patt_gen_seq_2 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_2_TYPE[15:00] - RW */ 10432 #endif /* IS_BIG_ENDIAN */ 10433 #if IS_LITTLE_ENDIAN 10434 uint32_t patt_gen_seq_2 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_2_TYPE[15:00] - RW */ 10435 uint32_t reserved : 16; 10436 #endif /* IS_LITTLE_ENDIAN */ 10437 } fields; 10438 } F25G_PATT_GEN_COM_patt_gen_seq_2_TYPE; 10439 10440 typedef F25G_PATT_GEN_COM_patt_gen_seq_2_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_2_TYPE_T; 10441 10442 typedef union { 10443 uint32_t data; 10444 struct { 10445 #if IS_BIG_ENDIAN 10446 uint32_t reserved : 16; 10447 uint32_t patt_gen_seq_3 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_3_TYPE[15:00] - RW */ 10448 #endif /* IS_BIG_ENDIAN */ 10449 #if IS_LITTLE_ENDIAN 10450 uint32_t patt_gen_seq_3 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_3_TYPE[15:00] - RW */ 10451 uint32_t reserved : 16; 10452 #endif /* IS_LITTLE_ENDIAN */ 10453 } fields; 10454 } F25G_PATT_GEN_COM_patt_gen_seq_3_TYPE; 10455 10456 typedef F25G_PATT_GEN_COM_patt_gen_seq_3_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_3_TYPE_T; 10457 10458 typedef union { 10459 uint32_t data; 10460 struct { 10461 #if IS_BIG_ENDIAN 10462 uint32_t reserved : 16; 10463 uint32_t patt_gen_seq_4 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_4_TYPE[15:00] - RW */ 10464 #endif /* IS_BIG_ENDIAN */ 10465 #if IS_LITTLE_ENDIAN 10466 uint32_t patt_gen_seq_4 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_4_TYPE[15:00] - RW */ 10467 uint32_t reserved : 16; 10468 #endif /* IS_LITTLE_ENDIAN */ 10469 } fields; 10470 } F25G_PATT_GEN_COM_patt_gen_seq_4_TYPE; 10471 10472 typedef F25G_PATT_GEN_COM_patt_gen_seq_4_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_4_TYPE_T; 10473 10474 typedef union { 10475 uint32_t data; 10476 struct { 10477 #if IS_BIG_ENDIAN 10478 uint32_t reserved : 16; 10479 uint32_t patt_gen_seq_5 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_5_TYPE[15:00] - RW */ 10480 #endif /* IS_BIG_ENDIAN */ 10481 #if IS_LITTLE_ENDIAN 10482 uint32_t patt_gen_seq_5 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_5_TYPE[15:00] - RW */ 10483 uint32_t reserved : 16; 10484 #endif /* IS_LITTLE_ENDIAN */ 10485 } fields; 10486 } F25G_PATT_GEN_COM_patt_gen_seq_5_TYPE; 10487 10488 typedef F25G_PATT_GEN_COM_patt_gen_seq_5_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_5_TYPE_T; 10489 10490 typedef union { 10491 uint32_t data; 10492 struct { 10493 #if IS_BIG_ENDIAN 10494 uint32_t reserved : 16; 10495 uint32_t patt_gen_seq_6 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_6_TYPE[15:00] - RW */ 10496 #endif /* IS_BIG_ENDIAN */ 10497 #if IS_LITTLE_ENDIAN 10498 uint32_t patt_gen_seq_6 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_6_TYPE[15:00] - RW */ 10499 uint32_t reserved : 16; 10500 #endif /* IS_LITTLE_ENDIAN */ 10501 } fields; 10502 } F25G_PATT_GEN_COM_patt_gen_seq_6_TYPE; 10503 10504 typedef F25G_PATT_GEN_COM_patt_gen_seq_6_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_6_TYPE_T; 10505 10506 typedef union { 10507 uint32_t data; 10508 struct { 10509 #if IS_BIG_ENDIAN 10510 uint32_t reserved : 16; 10511 uint32_t patt_gen_seq_7 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_7_TYPE[15:00] - RW */ 10512 #endif /* IS_BIG_ENDIAN */ 10513 #if IS_LITTLE_ENDIAN 10514 uint32_t patt_gen_seq_7 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_7_TYPE[15:00] - RW */ 10515 uint32_t reserved : 16; 10516 #endif /* IS_LITTLE_ENDIAN */ 10517 } fields; 10518 } F25G_PATT_GEN_COM_patt_gen_seq_7_TYPE; 10519 10520 typedef F25G_PATT_GEN_COM_patt_gen_seq_7_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_7_TYPE_T; 10521 10522 typedef union { 10523 uint32_t data; 10524 struct { 10525 #if IS_BIG_ENDIAN 10526 uint32_t reserved : 16; 10527 uint32_t patt_gen_seq_8 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_8_TYPE[15:00] - RW */ 10528 #endif /* IS_BIG_ENDIAN */ 10529 #if IS_LITTLE_ENDIAN 10530 uint32_t patt_gen_seq_8 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_8_TYPE[15:00] - RW */ 10531 uint32_t reserved : 16; 10532 #endif /* IS_LITTLE_ENDIAN */ 10533 } fields; 10534 } F25G_PATT_GEN_COM_patt_gen_seq_8_TYPE; 10535 10536 typedef F25G_PATT_GEN_COM_patt_gen_seq_8_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_8_TYPE_T; 10537 10538 typedef union { 10539 uint32_t data; 10540 struct { 10541 #if IS_BIG_ENDIAN 10542 uint32_t reserved : 16; 10543 uint32_t patt_gen_seq_9 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_9_TYPE[15:00] - RW */ 10544 #endif /* IS_BIG_ENDIAN */ 10545 #if IS_LITTLE_ENDIAN 10546 uint32_t patt_gen_seq_9 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_9_TYPE[15:00] - RW */ 10547 uint32_t reserved : 16; 10548 #endif /* IS_LITTLE_ENDIAN */ 10549 } fields; 10550 } F25G_PATT_GEN_COM_patt_gen_seq_9_TYPE; 10551 10552 typedef F25G_PATT_GEN_COM_patt_gen_seq_9_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_9_TYPE_T; 10553 10554 typedef union { 10555 uint32_t data; 10556 struct { 10557 #if IS_BIG_ENDIAN 10558 uint32_t reserved : 16; 10559 uint32_t patt_gen_seq_10 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_10_TYPE[15:00] - RW */ 10560 #endif /* IS_BIG_ENDIAN */ 10561 #if IS_LITTLE_ENDIAN 10562 uint32_t patt_gen_seq_10 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_10_TYPE[15:00] - RW */ 10563 uint32_t reserved : 16; 10564 #endif /* IS_LITTLE_ENDIAN */ 10565 } fields; 10566 } F25G_PATT_GEN_COM_patt_gen_seq_10_TYPE; 10567 10568 typedef F25G_PATT_GEN_COM_patt_gen_seq_10_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_10_TYPE_T; 10569 10570 typedef union { 10571 uint32_t data; 10572 struct { 10573 #if IS_BIG_ENDIAN 10574 uint32_t reserved : 16; 10575 uint32_t patt_gen_seq_11 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_11_TYPE[15:00] - RW */ 10576 #endif /* IS_BIG_ENDIAN */ 10577 #if IS_LITTLE_ENDIAN 10578 uint32_t patt_gen_seq_11 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_11_TYPE[15:00] - RW */ 10579 uint32_t reserved : 16; 10580 #endif /* IS_LITTLE_ENDIAN */ 10581 } fields; 10582 } F25G_PATT_GEN_COM_patt_gen_seq_11_TYPE; 10583 10584 typedef F25G_PATT_GEN_COM_patt_gen_seq_11_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_11_TYPE_T; 10585 10586 typedef union { 10587 uint32_t data; 10588 struct { 10589 #if IS_BIG_ENDIAN 10590 uint32_t reserved : 16; 10591 uint32_t patt_gen_seq_12 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_12_TYPE[15:00] - RW */ 10592 #endif /* IS_BIG_ENDIAN */ 10593 #if IS_LITTLE_ENDIAN 10594 uint32_t patt_gen_seq_12 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_12_TYPE[15:00] - RW */ 10595 uint32_t reserved : 16; 10596 #endif /* IS_LITTLE_ENDIAN */ 10597 } fields; 10598 } F25G_PATT_GEN_COM_patt_gen_seq_12_TYPE; 10599 10600 typedef F25G_PATT_GEN_COM_patt_gen_seq_12_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_12_TYPE_T; 10601 10602 typedef union { 10603 uint32_t data; 10604 struct { 10605 #if IS_BIG_ENDIAN 10606 uint32_t reserved : 16; 10607 uint32_t patt_gen_seq_13 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_13_TYPE[15:00] - RW */ 10608 #endif /* IS_BIG_ENDIAN */ 10609 #if IS_LITTLE_ENDIAN 10610 uint32_t patt_gen_seq_13 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_13_TYPE[15:00] - RW */ 10611 uint32_t reserved : 16; 10612 #endif /* IS_LITTLE_ENDIAN */ 10613 } fields; 10614 } F25G_PATT_GEN_COM_patt_gen_seq_13_TYPE; 10615 10616 typedef F25G_PATT_GEN_COM_patt_gen_seq_13_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_13_TYPE_T; 10617 10618 typedef union { 10619 uint32_t data; 10620 struct { 10621 #if IS_BIG_ENDIAN 10622 uint32_t reserved : 16; 10623 uint32_t patt_gen_seq_14 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_14_TYPE[15:00] - RW */ 10624 #endif /* IS_BIG_ENDIAN */ 10625 #if IS_LITTLE_ENDIAN 10626 uint32_t patt_gen_seq_14 : 16; /* F25G_PATT_GEN_COM_patt_gen_seq_14_TYPE[15:00] - RW */ 10627 uint32_t reserved : 16; 10628 #endif /* IS_LITTLE_ENDIAN */ 10629 } fields; 10630 } F25G_PATT_GEN_COM_patt_gen_seq_14_TYPE; 10631 10632 typedef F25G_PATT_GEN_COM_patt_gen_seq_14_TYPE F25G_PATT_GEN_COM_PATT_GEN_SEQ_14_TYPE_T; 10633 10634 10635 /*-----------------------------------------------*/ 10636 /* Structs for F25G_TX_FED Bank */ 10637 /*-----------------------------------------------*/ 10638 typedef union { 10639 uint32_t data; 10640 struct { 10641 #if IS_BIG_ENDIAN 10642 uint32_t reserved : 16; 10643 uint32_t reserved_12 : 4; /* F25G_TX_FED_txfir_control0_TYPE[15:12] - RSVD */ 10644 int32_t txfir_post_offset : 4; /* F25G_TX_FED_txfir_control0_TYPE[11:08] - RW */ 10645 int32_t txfir_main_offset : 4; /* F25G_TX_FED_txfir_control0_TYPE[07:04] - RW */ 10646 int32_t txfir_pre_offset : 4; /* F25G_TX_FED_txfir_control0_TYPE[03:00] - RW */ 10647 #endif /* IS_BIG_ENDIAN */ 10648 #if IS_LITTLE_ENDIAN 10649 int32_t txfir_pre_offset : 4; /* F25G_TX_FED_txfir_control0_TYPE[03:00] - RW */ 10650 int32_t txfir_main_offset : 4; /* F25G_TX_FED_txfir_control0_TYPE[07:04] - RW */ 10651 int32_t txfir_post_offset : 4; /* F25G_TX_FED_txfir_control0_TYPE[11:08] - RW */ 10652 uint32_t reserved_12 : 4; /* F25G_TX_FED_txfir_control0_TYPE[15:12] - RSVD */ 10653 uint32_t reserved : 16; 10654 #endif /* IS_LITTLE_ENDIAN */ 10655 } fields; 10656 } F25G_TX_FED_txfir_control0_TYPE; 10657 10658 typedef F25G_TX_FED_txfir_control0_TYPE F25G_TX_FED_TXFIR_CONTROL0_TYPE_T; 10659 10660 typedef union { 10661 uint32_t data; 10662 struct { 10663 #if IS_BIG_ENDIAN 10664 uint32_t reserved : 16; 10665 uint32_t reserved_12 : 4; /* F25G_TX_FED_txfir_control1_TYPE[15:12] - RSVD */ 10666 int32_t txfir_post2_offset : 4; /* F25G_TX_FED_txfir_control1_TYPE[11:08] - RW */ 10667 uint32_t reserved_05 : 3; /* F25G_TX_FED_txfir_control1_TYPE[07:05] - RSVD */ 10668 int32_t txfir_post2 : 5; /* F25G_TX_FED_txfir_control1_TYPE[04:00] - RW */ 10669 #endif /* IS_BIG_ENDIAN */ 10670 #if IS_LITTLE_ENDIAN 10671 int32_t txfir_post2 : 5; /* F25G_TX_FED_txfir_control1_TYPE[04:00] - RW */ 10672 uint32_t reserved_05 : 3; /* F25G_TX_FED_txfir_control1_TYPE[07:05] - RSVD */ 10673 int32_t txfir_post2_offset : 4; /* F25G_TX_FED_txfir_control1_TYPE[11:08] - RW */ 10674 uint32_t reserved_12 : 4; /* F25G_TX_FED_txfir_control1_TYPE[15:12] - RSVD */ 10675 uint32_t reserved : 16; 10676 #endif /* IS_LITTLE_ENDIAN */ 10677 } fields; 10678 } F25G_TX_FED_txfir_control1_TYPE; 10679 10680 typedef F25G_TX_FED_txfir_control1_TYPE F25G_TX_FED_TXFIR_CONTROL1_TYPE_T; 10681 10682 typedef union { 10683 uint32_t data; 10684 struct { 10685 #if IS_BIG_ENDIAN 10686 uint32_t reserved : 16; 10687 uint32_t reserved_12 : 4; /* F25G_TX_FED_txfir_control2_TYPE[15:12] - RSVD */ 10688 int32_t txfir_post3_offset : 4; /* F25G_TX_FED_txfir_control2_TYPE[11:08] - RW */ 10689 uint32_t reserved_04 : 4; /* F25G_TX_FED_txfir_control2_TYPE[07:04] - RSVD */ 10690 int32_t txfir_post3 : 4; /* F25G_TX_FED_txfir_control2_TYPE[03:00] - RW */ 10691 #endif /* IS_BIG_ENDIAN */ 10692 #if IS_LITTLE_ENDIAN 10693 int32_t txfir_post3 : 4; /* F25G_TX_FED_txfir_control2_TYPE[03:00] - RW */ 10694 uint32_t reserved_04 : 4; /* F25G_TX_FED_txfir_control2_TYPE[07:04] - RSVD */ 10695 int32_t txfir_post3_offset : 4; /* F25G_TX_FED_txfir_control2_TYPE[11:08] - RW */ 10696 uint32_t reserved_12 : 4; /* F25G_TX_FED_txfir_control2_TYPE[15:12] - RSVD */ 10697 uint32_t reserved : 16; 10698 #endif /* IS_LITTLE_ENDIAN */ 10699 } fields; 10700 } F25G_TX_FED_txfir_control2_TYPE; 10701 10702 typedef F25G_TX_FED_txfir_control2_TYPE F25G_TX_FED_TXFIR_CONTROL2_TYPE_T; 10703 10704 10705 /*-----------------------------------------------*/ 10706 /* Structs for F25G_TLB_RX Bank */ 10707 /*-----------------------------------------------*/ 10708 typedef union { 10709 uint32_t data; 10710 struct { 10711 #if IS_BIG_ENDIAN 10712 uint32_t reserved : 16; 10713 uint32_t reserved_13 : 3; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[15:13] - RSVD */ 10714 uint32_t prbs_chk_ool_cnt : 5; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[12:08] - RW */ 10715 uint32_t reserved_05 : 3; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[07:05] - RSVD */ 10716 uint32_t prbs_chk_lock_cnt : 5; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[04:00] - RW */ 10717 #endif /* IS_BIG_ENDIAN */ 10718 #if IS_LITTLE_ENDIAN 10719 uint32_t prbs_chk_lock_cnt : 5; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[04:00] - RW */ 10720 uint32_t reserved_05 : 3; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[07:05] - RSVD */ 10721 uint32_t prbs_chk_ool_cnt : 5; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[12:08] - RW */ 10722 uint32_t reserved_13 : 3; /* F25G_TLB_RX_prbs_chk_cnt_config_TYPE[15:13] - RSVD */ 10723 uint32_t reserved : 16; 10724 #endif /* IS_LITTLE_ENDIAN */ 10725 } fields; 10726 } F25G_TLB_RX_prbs_chk_cnt_config_TYPE; 10727 10728 typedef F25G_TLB_RX_prbs_chk_cnt_config_TYPE F25G_TLB_RX_PRBS_CHK_CNT_CONFIG_TYPE_T; 10729 10730 typedef union { 10731 uint32_t data; 10732 struct { 10733 #if IS_BIG_ENDIAN 10734 uint32_t reserved : 16; 10735 uint32_t reserved_12 : 4; /* F25G_TLB_RX_prbs_chk_config_TYPE[15:12] - RSVD */ 10736 uint32_t prbs_chk_clk_en_frc_on : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[11] - RW */ 10737 uint32_t reserved_10 : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[10] - RSVD */ 10738 uint32_t reserved_09 : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[09] - RSVD */ 10739 uint32_t reserved_08 : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[08] - RSVD */ 10740 uint32_t prbs_chk_en_auto_mode : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[07] - RW */ 10741 uint32_t prbs_chk_mode : 2; /* F25G_TLB_RX_prbs_chk_config_TYPE[06:05] - RW */ 10742 uint32_t prbs_chk_inv : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[04] - RW */ 10743 uint32_t prbs_chk_mode_sel : 3; /* F25G_TLB_RX_prbs_chk_config_TYPE[03:01] - RW */ 10744 uint32_t prbs_chk_en : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[00] - RW */ 10745 #endif /* IS_BIG_ENDIAN */ 10746 #if IS_LITTLE_ENDIAN 10747 uint32_t prbs_chk_en : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[00] - RW */ 10748 uint32_t prbs_chk_mode_sel : 3; /* F25G_TLB_RX_prbs_chk_config_TYPE[03:01] - RW */ 10749 uint32_t prbs_chk_inv : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[04] - RW */ 10750 uint32_t prbs_chk_mode : 2; /* F25G_TLB_RX_prbs_chk_config_TYPE[06:05] - RW */ 10751 uint32_t prbs_chk_en_auto_mode : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[07] - RW */ 10752 uint32_t reserved_08 : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[08] - RSVD */ 10753 uint32_t reserved_09 : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[09] - RSVD */ 10754 uint32_t reserved_10 : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[10] - RSVD */ 10755 uint32_t prbs_chk_clk_en_frc_on : 1; /* F25G_TLB_RX_prbs_chk_config_TYPE[11] - RW */ 10756 uint32_t reserved_12 : 4; /* F25G_TLB_RX_prbs_chk_config_TYPE[15:12] - RSVD */ 10757 uint32_t reserved : 16; 10758 #endif /* IS_LITTLE_ENDIAN */ 10759 } fields; 10760 } F25G_TLB_RX_prbs_chk_config_TYPE; 10761 10762 typedef F25G_TLB_RX_prbs_chk_config_TYPE F25G_TLB_RX_PRBS_CHK_CONFIG_TYPE_T; 10763 10764 typedef union { 10765 uint32_t data; 10766 struct { 10767 #if IS_BIG_ENDIAN 10768 uint32_t reserved : 16; 10769 uint32_t reserved_04 : 12; /* F25G_TLB_RX_dig_lpbk_config_TYPE[15:04] - RSVD */ 10770 uint32_t reserved_03 : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[03] - RSVD */ 10771 uint32_t reserved_02 : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[02] - RSVD */ 10772 uint32_t reserved_01 : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[01] - RSVD */ 10773 uint32_t dig_lpbk_en : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[00] - RW */ 10774 #endif /* IS_BIG_ENDIAN */ 10775 #if IS_LITTLE_ENDIAN 10776 uint32_t dig_lpbk_en : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[00] - RW */ 10777 uint32_t reserved_01 : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[01] - RSVD */ 10778 uint32_t reserved_02 : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[02] - RSVD */ 10779 uint32_t reserved_03 : 1; /* F25G_TLB_RX_dig_lpbk_config_TYPE[03] - RSVD */ 10780 uint32_t reserved_04 : 12; /* F25G_TLB_RX_dig_lpbk_config_TYPE[15:04] - RSVD */ 10781 uint32_t reserved : 16; 10782 #endif /* IS_LITTLE_ENDIAN */ 10783 } fields; 10784 } F25G_TLB_RX_dig_lpbk_config_TYPE; 10785 10786 typedef F25G_TLB_RX_dig_lpbk_config_TYPE F25G_TLB_RX_DIG_LPBK_CONFIG_TYPE_T; 10787 10788 typedef union { 10789 uint32_t data; 10790 struct { 10791 #if IS_BIG_ENDIAN 10792 uint32_t reserved : 16; 10793 uint32_t reserved_04 : 12; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[15:04] - RSVD */ 10794 uint32_t reserved_03 : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[03] - RSVD */ 10795 uint32_t reserved_02 : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[02] - RSVD */ 10796 uint32_t reserved_01 : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[01] - RSVD */ 10797 uint32_t rx_pmd_dp_invert : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[00] - RW */ 10798 #endif /* IS_BIG_ENDIAN */ 10799 #if IS_LITTLE_ENDIAN 10800 uint32_t rx_pmd_dp_invert : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[00] - RW */ 10801 uint32_t reserved_01 : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[01] - RSVD */ 10802 uint32_t reserved_02 : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[02] - RSVD */ 10803 uint32_t reserved_03 : 1; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[03] - RSVD */ 10804 uint32_t reserved_04 : 12; /* F25G_TLB_RX_tlb_rx_misc_config_TYPE[15:04] - RSVD */ 10805 uint32_t reserved : 16; 10806 #endif /* IS_LITTLE_ENDIAN */ 10807 } fields; 10808 } F25G_TLB_RX_tlb_rx_misc_config_TYPE; 10809 10810 typedef F25G_TLB_RX_tlb_rx_misc_config_TYPE F25G_TLB_RX_TLB_RX_MISC_CONFIG_TYPE_T; 10811 10812 typedef union { 10813 uint32_t data; 10814 struct { 10815 #if IS_BIG_ENDIAN 10816 uint32_t reserved : 16; 10817 uint32_t reserved_01 : 15; /* F25G_TLB_RX_prbs_chk_lock_status_TYPE[15:01] - RSVD */ 10818 uint32_t prbs_chk_lock : 1; /* F25G_TLB_RX_prbs_chk_lock_status_TYPE[00] - RO */ 10819 #endif /* IS_BIG_ENDIAN */ 10820 #if IS_LITTLE_ENDIAN 10821 uint32_t prbs_chk_lock : 1; /* F25G_TLB_RX_prbs_chk_lock_status_TYPE[00] - RO */ 10822 uint32_t reserved_01 : 15; /* F25G_TLB_RX_prbs_chk_lock_status_TYPE[15:01] - RSVD */ 10823 uint32_t reserved : 16; 10824 #endif /* IS_LITTLE_ENDIAN */ 10825 } fields; 10826 } F25G_TLB_RX_prbs_chk_lock_status_TYPE; 10827 10828 typedef F25G_TLB_RX_prbs_chk_lock_status_TYPE F25G_TLB_RX_PRBS_CHK_LOCK_STATUS_TYPE_T; 10829 10830 typedef union { 10831 uint32_t data; 10832 struct { 10833 #if IS_BIG_ENDIAN 10834 uint32_t reserved : 16; 10835 uint32_t prbs_chk_lock_lost_lh : 1; /* F25G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[15] - RO */ 10836 uint32_t prbs_chk_err_cnt_msb : 15; /* F25G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[14:00] - RO */ 10837 #endif /* IS_BIG_ENDIAN */ 10838 #if IS_LITTLE_ENDIAN 10839 uint32_t prbs_chk_err_cnt_msb : 15; /* F25G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[14:00] - RO */ 10840 uint32_t prbs_chk_lock_lost_lh : 1; /* F25G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE[15] - RO */ 10841 uint32_t reserved : 16; 10842 #endif /* IS_LITTLE_ENDIAN */ 10843 } fields; 10844 } F25G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE; 10845 10846 typedef F25G_TLB_RX_prbs_chk_err_cnt_msb_status_TYPE F25G_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_TYPE_T; 10847 10848 typedef union { 10849 uint32_t data; 10850 struct { 10851 #if IS_BIG_ENDIAN 10852 uint32_t reserved : 16; 10853 uint32_t prbs_chk_err_cnt_lsb : 16; /* F25G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE[15:00] - RO */ 10854 #endif /* IS_BIG_ENDIAN */ 10855 #if IS_LITTLE_ENDIAN 10856 uint32_t prbs_chk_err_cnt_lsb : 16; /* F25G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE[15:00] - RO */ 10857 uint32_t reserved : 16; 10858 #endif /* IS_LITTLE_ENDIAN */ 10859 } fields; 10860 } F25G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE; 10861 10862 typedef F25G_TLB_RX_prbs_chk_err_cnt_lsb_status_TYPE F25G_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_TYPE_T; 10863 10864 typedef union { 10865 uint32_t data; 10866 struct { 10867 #if IS_BIG_ENDIAN 10868 uint32_t reserved : 16; 10869 uint32_t reserved_02 : 14; /* F25G_TLB_RX_pmd_rx_lock_status_TYPE[15:02] - RSVD */ 10870 uint32_t pmd_rx_lock_change : 1; /* F25G_TLB_RX_pmd_rx_lock_status_TYPE[01] - RO */ 10871 uint32_t pmd_rx_lock : 1; /* F25G_TLB_RX_pmd_rx_lock_status_TYPE[00] - RO */ 10872 #endif /* IS_BIG_ENDIAN */ 10873 #if IS_LITTLE_ENDIAN 10874 uint32_t pmd_rx_lock : 1; /* F25G_TLB_RX_pmd_rx_lock_status_TYPE[00] - RO */ 10875 uint32_t pmd_rx_lock_change : 1; /* F25G_TLB_RX_pmd_rx_lock_status_TYPE[01] - RO */ 10876 uint32_t reserved_02 : 14; /* F25G_TLB_RX_pmd_rx_lock_status_TYPE[15:02] - RSVD */ 10877 uint32_t reserved : 16; 10878 #endif /* IS_LITTLE_ENDIAN */ 10879 } fields; 10880 } F25G_TLB_RX_pmd_rx_lock_status_TYPE; 10881 10882 typedef F25G_TLB_RX_pmd_rx_lock_status_TYPE F25G_TLB_RX_PMD_RX_LOCK_STATUS_TYPE_T; 10883 10884 10885 /*-----------------------------------------------*/ 10886 /* Structs for F25G_TLB_TX Bank */ 10887 /*-----------------------------------------------*/ 10888 typedef union { 10889 uint32_t data; 10890 struct { 10891 #if IS_BIG_ENDIAN 10892 uint32_t reserved : 16; 10893 uint32_t patt_gen_start_pos : 4; /* F25G_TLB_TX_patt_gen_config_TYPE[15:12] - RW */ 10894 uint32_t patt_gen_stop_pos : 4; /* F25G_TLB_TX_patt_gen_config_TYPE[11:08] - RW */ 10895 uint32_t reserved_01 : 7; /* F25G_TLB_TX_patt_gen_config_TYPE[07:01] - RSVD */ 10896 uint32_t patt_gen_en : 1; /* F25G_TLB_TX_patt_gen_config_TYPE[00] - RW */ 10897 #endif /* IS_BIG_ENDIAN */ 10898 #if IS_LITTLE_ENDIAN 10899 uint32_t patt_gen_en : 1; /* F25G_TLB_TX_patt_gen_config_TYPE[00] - RW */ 10900 uint32_t reserved_01 : 7; /* F25G_TLB_TX_patt_gen_config_TYPE[07:01] - RSVD */ 10901 uint32_t patt_gen_stop_pos : 4; /* F25G_TLB_TX_patt_gen_config_TYPE[11:08] - RW */ 10902 uint32_t patt_gen_start_pos : 4; /* F25G_TLB_TX_patt_gen_config_TYPE[15:12] - RW */ 10903 uint32_t reserved : 16; 10904 #endif /* IS_LITTLE_ENDIAN */ 10905 } fields; 10906 } F25G_TLB_TX_patt_gen_config_TYPE; 10907 10908 typedef F25G_TLB_TX_patt_gen_config_TYPE F25G_TLB_TX_PATT_GEN_CONFIG_TYPE_T; 10909 10910 typedef union { 10911 uint32_t data; 10912 struct { 10913 #if IS_BIG_ENDIAN 10914 uint32_t reserved : 16; 10915 uint32_t reserved_06 : 10; /* F25G_TLB_TX_prbs_gen_config_TYPE[15:06] - RSVD */ 10916 uint32_t prbs_gen_err_ins : 1; /* F25G_TLB_TX_prbs_gen_config_TYPE[05] - RW */ 10917 uint32_t prbs_gen_inv : 1; /* F25G_TLB_TX_prbs_gen_config_TYPE[04] - RW */ 10918 uint32_t prbs_gen_mode_sel : 3; /* F25G_TLB_TX_prbs_gen_config_TYPE[03:01] - RW */ 10919 uint32_t prbs_gen_en : 1; /* F25G_TLB_TX_prbs_gen_config_TYPE[00] - RW */ 10920 #endif /* IS_BIG_ENDIAN */ 10921 #if IS_LITTLE_ENDIAN 10922 uint32_t prbs_gen_en : 1; /* F25G_TLB_TX_prbs_gen_config_TYPE[00] - RW */ 10923 uint32_t prbs_gen_mode_sel : 3; /* F25G_TLB_TX_prbs_gen_config_TYPE[03:01] - RW */ 10924 uint32_t prbs_gen_inv : 1; /* F25G_TLB_TX_prbs_gen_config_TYPE[04] - RW */ 10925 uint32_t prbs_gen_err_ins : 1; /* F25G_TLB_TX_prbs_gen_config_TYPE[05] - RW */ 10926 uint32_t reserved_06 : 10; /* F25G_TLB_TX_prbs_gen_config_TYPE[15:06] - RSVD */ 10927 uint32_t reserved : 16; 10928 #endif /* IS_LITTLE_ENDIAN */ 10929 } fields; 10930 } F25G_TLB_TX_prbs_gen_config_TYPE; 10931 10932 typedef F25G_TLB_TX_prbs_gen_config_TYPE F25G_TLB_TX_PRBS_GEN_CONFIG_TYPE_T; 10933 10934 typedef union { 10935 uint32_t data; 10936 struct { 10937 #if IS_BIG_ENDIAN 10938 uint32_t reserved : 16; 10939 uint32_t reserved_03 : 13; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[15:03] - RSVD */ 10940 uint32_t reserved_02 : 1; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[02] - RSVD */ 10941 uint32_t reserved_01 : 1; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[01] - RSVD */ 10942 uint32_t rmt_lpbk_en : 1; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[00] - RW */ 10943 #endif /* IS_BIG_ENDIAN */ 10944 #if IS_LITTLE_ENDIAN 10945 uint32_t rmt_lpbk_en : 1; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[00] - RW */ 10946 uint32_t reserved_01 : 1; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[01] - RSVD */ 10947 uint32_t reserved_02 : 1; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[02] - RSVD */ 10948 uint32_t reserved_03 : 13; /* F25G_TLB_TX_rmt_lpbk_config_TYPE[15:03] - RSVD */ 10949 uint32_t reserved : 16; 10950 #endif /* IS_LITTLE_ENDIAN */ 10951 } fields; 10952 } F25G_TLB_TX_rmt_lpbk_config_TYPE; 10953 10954 typedef F25G_TLB_TX_rmt_lpbk_config_TYPE F25G_TLB_TX_RMT_LPBK_CONFIG_TYPE_T; 10955 10956 typedef union { 10957 uint32_t data; 10958 struct { 10959 #if IS_BIG_ENDIAN 10960 uint32_t reserved : 16; 10961 uint32_t reserved_04 : 12; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[15:04] - RSVD */ 10962 uint32_t reserved_03 : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[03] - RSVD */ 10963 uint32_t reserved_02 : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[02] - RSVD */ 10964 uint32_t reserved_01 : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[01] - RSVD */ 10965 uint32_t tx_pmd_dp_invert : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[00] - RW */ 10966 #endif /* IS_BIG_ENDIAN */ 10967 #if IS_LITTLE_ENDIAN 10968 uint32_t tx_pmd_dp_invert : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[00] - RW */ 10969 uint32_t reserved_01 : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[01] - RSVD */ 10970 uint32_t reserved_02 : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[02] - RSVD */ 10971 uint32_t reserved_03 : 1; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[03] - RSVD */ 10972 uint32_t reserved_04 : 12; /* F25G_TLB_TX_tlb_tx_misc_config_TYPE[15:04] - RSVD */ 10973 uint32_t reserved : 16; 10974 #endif /* IS_LITTLE_ENDIAN */ 10975 } fields; 10976 } F25G_TLB_TX_tlb_tx_misc_config_TYPE; 10977 10978 typedef F25G_TLB_TX_tlb_tx_misc_config_TYPE F25G_TLB_TX_TLB_TX_MISC_CONFIG_TYPE_T; 10979 10980 10981 /*-----------------------------------------------*/ 10982 /* Structs for IEEE_AN_BLK0 Bank */ 10983 /*-----------------------------------------------*/ 10984 typedef union { 10985 uint32_t data; 10986 struct { 10987 #if IS_BIG_ENDIAN 10988 uint32_t reserved : 16; 10989 uint32_t an_reset : 1; /* IEEE_AN_BLK0_an_control_register_TYPE[15] - SC */ 10990 uint32_t reserved_13 : 2; /* IEEE_AN_BLK0_an_control_register_TYPE[14:13] - RSVD */ 10991 uint32_t auto_negotiationenable : 1; /* IEEE_AN_BLK0_an_control_register_TYPE[12] - WO */ 10992 uint32_t reserved_10 : 2; /* IEEE_AN_BLK0_an_control_register_TYPE[11:10] - RSVD */ 10993 uint32_t restart_auto_negotiation : 1; /* IEEE_AN_BLK0_an_control_register_TYPE[09] - SC */ 10994 uint32_t reserved_00 : 9; /* IEEE_AN_BLK0_an_control_register_TYPE[08:00] - RSVD */ 10995 #endif /* IS_BIG_ENDIAN */ 10996 #if IS_LITTLE_ENDIAN 10997 uint32_t reserved_00 : 9; /* IEEE_AN_BLK0_an_control_register_TYPE[08:00] - RSVD */ 10998 uint32_t restart_auto_negotiation : 1; /* IEEE_AN_BLK0_an_control_register_TYPE[09] - SC */ 10999 uint32_t reserved_10 : 2; /* IEEE_AN_BLK0_an_control_register_TYPE[11:10] - RSVD */ 11000 uint32_t auto_negotiationenable : 1; /* IEEE_AN_BLK0_an_control_register_TYPE[12] - WO */ 11001 uint32_t reserved_13 : 2; /* IEEE_AN_BLK0_an_control_register_TYPE[14:13] - RSVD */ 11002 uint32_t an_reset : 1; /* IEEE_AN_BLK0_an_control_register_TYPE[15] - SC */ 11003 uint32_t reserved : 16; 11004 #endif /* IS_LITTLE_ENDIAN */ 11005 } fields; 11006 } IEEE_AN_BLK0_an_control_register_TYPE; 11007 11008 typedef IEEE_AN_BLK0_an_control_register_TYPE IEEE_AN_BLK0_AN_CONTROL_REGISTER_TYPE_T; 11009 11010 typedef union { 11011 uint32_t data; 11012 struct { 11013 #if IS_BIG_ENDIAN 11014 uint32_t reserved : 16; 11015 uint32_t reserved_10 : 6; /* IEEE_AN_BLK0_an_status_register_TYPE[15:10] - RSVD */ 11016 uint32_t parallel_detection_fault : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[09] - LH */ 11017 uint32_t reserved_08 : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[08] - RSVD */ 11018 uint32_t extended_next_pagestatus : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[07] - RO */ 11019 uint32_t page_received : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[06] - LH */ 11020 uint32_t auto_negotiationcomplete : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[05] - RO */ 11021 uint32_t remote_fault : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[04] - LH */ 11022 uint32_t auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[03] - RO */ 11023 uint32_t link_status : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[02] - LL */ 11024 uint32_t reserved_01 : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[01] - RSVD */ 11025 uint32_t link_partner_auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[00] - RO */ 11026 #endif /* IS_BIG_ENDIAN */ 11027 #if IS_LITTLE_ENDIAN 11028 uint32_t link_partner_auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[00] - RO */ 11029 uint32_t reserved_01 : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[01] - RSVD */ 11030 uint32_t link_status : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[02] - LL */ 11031 uint32_t auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[03] - RO */ 11032 uint32_t remote_fault : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[04] - LH */ 11033 uint32_t auto_negotiationcomplete : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[05] - RO */ 11034 uint32_t page_received : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[06] - LH */ 11035 uint32_t extended_next_pagestatus : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[07] - RO */ 11036 uint32_t reserved_08 : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[08] - RSVD */ 11037 uint32_t parallel_detection_fault : 1; /* IEEE_AN_BLK0_an_status_register_TYPE[09] - LH */ 11038 uint32_t reserved_10 : 6; /* IEEE_AN_BLK0_an_status_register_TYPE[15:10] - RSVD */ 11039 uint32_t reserved : 16; 11040 #endif /* IS_LITTLE_ENDIAN */ 11041 } fields; 11042 } IEEE_AN_BLK0_an_status_register_TYPE; 11043 11044 typedef IEEE_AN_BLK0_an_status_register_TYPE IEEE_AN_BLK0_AN_STATUS_REGISTER_TYPE_T; 11045 11046 typedef union { 11047 uint32_t data; 11048 struct { 11049 #if IS_BIG_ENDIAN 11050 uint32_t reserved : 16; 11051 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_identifier_register_0_TYPE[15:00] - RO */ 11052 #endif /* IS_BIG_ENDIAN */ 11053 #if IS_LITTLE_ENDIAN 11054 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_identifier_register_0_TYPE[15:00] - RO */ 11055 uint32_t reserved : 16; 11056 #endif /* IS_LITTLE_ENDIAN */ 11057 } fields; 11058 } IEEE_AN_BLK0_an_identifier_register_0_TYPE; 11059 11060 typedef IEEE_AN_BLK0_an_identifier_register_0_TYPE IEEE_AN_BLK0_AN_IDENTIFIER_REGISTER_0_TYPE_T; 11061 11062 typedef union { 11063 uint32_t data; 11064 struct { 11065 #if IS_BIG_ENDIAN 11066 uint32_t reserved : 16; 11067 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_identifier_register_1_TYPE[15:00] - RO */ 11068 #endif /* IS_BIG_ENDIAN */ 11069 #if IS_LITTLE_ENDIAN 11070 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_identifier_register_1_TYPE[15:00] - RO */ 11071 uint32_t reserved : 16; 11072 #endif /* IS_LITTLE_ENDIAN */ 11073 } fields; 11074 } IEEE_AN_BLK0_an_identifier_register_1_TYPE; 11075 11076 typedef IEEE_AN_BLK0_an_identifier_register_1_TYPE IEEE_AN_BLK0_AN_IDENTIFIER_REGISTER_1_TYPE_T; 11077 11078 typedef union { 11079 uint32_t data; 11080 struct { 11081 #if IS_BIG_ENDIAN 11082 uint32_t reserved : 16; 11083 uint32_t reserved_12 : 4; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[15:12] - RSVD */ 11084 uint32_t seperate_pma_4_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[11] - RO */ 11085 uint32_t seperate_pma_3_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[10] - RO */ 11086 uint32_t seperate_pma_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[09] - RO */ 11087 uint32_t seperate_pma_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[08] - RO */ 11088 uint32_t an_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[07] - RO */ 11089 uint32_t tc_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[06] - RO */ 11090 uint32_t dte_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[05] - RO */ 11091 uint32_t phy_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[04] - RO */ 11092 uint32_t pcs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[03] - RO */ 11093 uint32_t wis_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[02] - RO */ 11094 uint32_t pmd_pma_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[01] - RO */ 11095 uint32_t clause_22registers_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[00] - RO */ 11096 #endif /* IS_BIG_ENDIAN */ 11097 #if IS_LITTLE_ENDIAN 11098 uint32_t clause_22registers_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[00] - RO */ 11099 uint32_t pmd_pma_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[01] - RO */ 11100 uint32_t wis_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[02] - RO */ 11101 uint32_t pcs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[03] - RO */ 11102 uint32_t phy_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[04] - RO */ 11103 uint32_t dte_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[05] - RO */ 11104 uint32_t tc_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[06] - RO */ 11105 uint32_t an_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[07] - RO */ 11106 uint32_t seperate_pma_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[08] - RO */ 11107 uint32_t seperate_pma_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[09] - RO */ 11108 uint32_t seperate_pma_3_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[10] - RO */ 11109 uint32_t seperate_pma_4_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[11] - RO */ 11110 uint32_t reserved_12 : 4; /* IEEE_AN_BLK0_an_devices_in_package_1_TYPE[15:12] - RSVD */ 11111 uint32_t reserved : 16; 11112 #endif /* IS_LITTLE_ENDIAN */ 11113 } fields; 11114 } IEEE_AN_BLK0_an_devices_in_package_1_TYPE; 11115 11116 typedef IEEE_AN_BLK0_an_devices_in_package_1_TYPE IEEE_AN_BLK0_AN_DEVICES_IN_PACKAGE_1_TYPE_T; 11117 11118 typedef union { 11119 uint32_t data; 11120 struct { 11121 #if IS_BIG_ENDIAN 11122 uint32_t reserved : 16; 11123 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[15] - RO */ 11124 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[14] - RO */ 11125 uint32_t clause_22extension_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[13] - RO */ 11126 uint32_t reserved_00 : 13; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[12:00] - RSVD */ 11127 #endif /* IS_BIG_ENDIAN */ 11128 #if IS_LITTLE_ENDIAN 11129 uint32_t reserved_00 : 13; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[12:00] - RSVD */ 11130 uint32_t clause_22extension_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[13] - RO */ 11131 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[14] - RO */ 11132 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_TYPE[15] - RO */ 11133 uint32_t reserved : 16; 11134 #endif /* IS_LITTLE_ENDIAN */ 11135 } fields; 11136 } IEEE_AN_BLK0_an_devices_in_package_2_TYPE; 11137 11138 typedef IEEE_AN_BLK0_an_devices_in_package_2_TYPE IEEE_AN_BLK0_AN_DEVICES_IN_PACKAGE_2_TYPE_T; 11139 11140 typedef union { 11141 uint32_t data; 11142 struct { 11143 #if IS_BIG_ENDIAN 11144 uint32_t reserved : 16; 11145 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_oui_id0_register_TYPE[15:00] - RO */ 11146 #endif /* IS_BIG_ENDIAN */ 11147 #if IS_LITTLE_ENDIAN 11148 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_oui_id0_register_TYPE[15:00] - RO */ 11149 uint32_t reserved : 16; 11150 #endif /* IS_LITTLE_ENDIAN */ 11151 } fields; 11152 } IEEE_AN_BLK0_an_oui_id0_register_TYPE; 11153 11154 typedef IEEE_AN_BLK0_an_oui_id0_register_TYPE IEEE_AN_BLK0_AN_OUI_ID0_REGISTER_TYPE_T; 11155 11156 typedef union { 11157 uint32_t data; 11158 struct { 11159 #if IS_BIG_ENDIAN 11160 uint32_t reserved : 16; 11161 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_oui_id1_reg_TYPE[15:00] - RO */ 11162 #endif /* IS_BIG_ENDIAN */ 11163 #if IS_LITTLE_ENDIAN 11164 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_oui_id1_reg_TYPE[15:00] - RO */ 11165 uint32_t reserved : 16; 11166 #endif /* IS_LITTLE_ENDIAN */ 11167 } fields; 11168 } IEEE_AN_BLK0_an_oui_id1_reg_TYPE; 11169 11170 typedef IEEE_AN_BLK0_an_oui_id1_reg_TYPE IEEE_AN_BLK0_AN_OUI_ID1_REG_TYPE_T; 11171 11172 11173 /*-----------------------------------------------*/ 11174 /* Structs for IEEE_AN_BLK1 Bank */ 11175 /*-----------------------------------------------*/ 11176 typedef union { 11177 uint32_t data; 11178 struct { 11179 #if IS_BIG_ENDIAN 11180 uint32_t reserved : 16; 11181 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[15] - WO */ 11182 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[14] - RO */ 11183 uint32_t remote_fault : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[13] - WO */ 11184 uint32_t pause : 3; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[12:10] - WO */ 11185 uint32_t echoed_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[09:05] - WO */ 11186 uint32_t selector_field : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[04:00] - WO */ 11187 #endif /* IS_BIG_ENDIAN */ 11188 #if IS_LITTLE_ENDIAN 11189 uint32_t selector_field : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[04:00] - WO */ 11190 uint32_t echoed_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[09:05] - WO */ 11191 uint32_t pause : 3; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[12:10] - WO */ 11192 uint32_t remote_fault : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[13] - WO */ 11193 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[14] - RO */ 11194 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_TYPE[15] - WO */ 11195 uint32_t reserved : 16; 11196 #endif /* IS_LITTLE_ENDIAN */ 11197 } fields; 11198 } IEEE_AN_BLK1_an_advertisement_1_register_TYPE; 11199 11200 typedef IEEE_AN_BLK1_an_advertisement_1_register_TYPE IEEE_AN_BLK1_AN_ADVERTISEMENT_1_REGISTER_TYPE_T; 11201 11202 typedef union { 11203 uint32_t data; 11204 struct { 11205 #if IS_BIG_ENDIAN 11206 uint32_t reserved : 16; 11207 uint32_t techability : 11; /* IEEE_AN_BLK1_an_advertisement_2_register_TYPE[15:05] - WO */ 11208 uint32_t transmitted_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_2_register_TYPE[04:00] - WO */ 11209 #endif /* IS_BIG_ENDIAN */ 11210 #if IS_LITTLE_ENDIAN 11211 uint32_t transmitted_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_2_register_TYPE[04:00] - WO */ 11212 uint32_t techability : 11; /* IEEE_AN_BLK1_an_advertisement_2_register_TYPE[15:05] - WO */ 11213 uint32_t reserved : 16; 11214 #endif /* IS_LITTLE_ENDIAN */ 11215 } fields; 11216 } IEEE_AN_BLK1_an_advertisement_2_register_TYPE; 11217 11218 typedef IEEE_AN_BLK1_an_advertisement_2_register_TYPE IEEE_AN_BLK1_AN_ADVERTISEMENT_2_REGISTER_TYPE_T; 11219 11220 typedef union { 11221 uint32_t data; 11222 struct { 11223 #if IS_BIG_ENDIAN 11224 uint32_t reserved : 16; 11225 uint32_t fec_requested : 2; /* IEEE_AN_BLK1_an_advertisement_3_register_TYPE[15:14] - WO */ 11226 uint32_t an_adv_d45_d32 : 14; /* IEEE_AN_BLK1_an_advertisement_3_register_TYPE[13:00] - WO */ 11227 #endif /* IS_BIG_ENDIAN */ 11228 #if IS_LITTLE_ENDIAN 11229 uint32_t an_adv_d45_d32 : 14; /* IEEE_AN_BLK1_an_advertisement_3_register_TYPE[13:00] - WO */ 11230 uint32_t fec_requested : 2; /* IEEE_AN_BLK1_an_advertisement_3_register_TYPE[15:14] - WO */ 11231 uint32_t reserved : 16; 11232 #endif /* IS_LITTLE_ENDIAN */ 11233 } fields; 11234 } IEEE_AN_BLK1_an_advertisement_3_register_TYPE; 11235 11236 typedef IEEE_AN_BLK1_an_advertisement_3_register_TYPE IEEE_AN_BLK1_AN_ADVERTISEMENT_3_REGISTER_TYPE_T; 11237 11238 typedef union { 11239 uint32_t data; 11240 struct { 11241 #if IS_BIG_ENDIAN 11242 uint32_t reserved : 16; 11243 uint32_t d15_d0 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_TYPE[15:00] - RO */ 11244 #endif /* IS_BIG_ENDIAN */ 11245 #if IS_LITTLE_ENDIAN 11246 uint32_t d15_d0 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_TYPE[15:00] - RO */ 11247 uint32_t reserved : 16; 11248 #endif /* IS_LITTLE_ENDIAN */ 11249 } fields; 11250 } IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_TYPE; 11251 11252 typedef IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_TYPE IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_1_REG_TYPE_T; 11253 11254 typedef union { 11255 uint32_t data; 11256 struct { 11257 #if IS_BIG_ENDIAN 11258 uint32_t reserved : 16; 11259 uint32_t d31_16 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_TYPE[15:00] - RO */ 11260 #endif /* IS_BIG_ENDIAN */ 11261 #if IS_LITTLE_ENDIAN 11262 uint32_t d31_16 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_TYPE[15:00] - RO */ 11263 uint32_t reserved : 16; 11264 #endif /* IS_LITTLE_ENDIAN */ 11265 } fields; 11266 } IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_TYPE; 11267 11268 typedef IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_TYPE IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_2_REG_TYPE_T; 11269 11270 typedef union { 11271 uint32_t data; 11272 struct { 11273 #if IS_BIG_ENDIAN 11274 uint32_t reserved : 16; 11275 uint32_t d47_32 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_TYPE[15:00] - RO */ 11276 #endif /* IS_BIG_ENDIAN */ 11277 #if IS_LITTLE_ENDIAN 11278 uint32_t d47_32 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_TYPE[15:00] - RO */ 11279 uint32_t reserved : 16; 11280 #endif /* IS_LITTLE_ENDIAN */ 11281 } fields; 11282 } IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_TYPE; 11283 11284 typedef IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_TYPE IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_3_REG_TYPE_T; 11285 11286 typedef union { 11287 uint32_t data; 11288 struct { 11289 #if IS_BIG_ENDIAN 11290 uint32_t reserved : 16; 11291 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[15] - WO */ 11292 uint32_t reserved_14 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[14] - RSVD */ 11293 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[13] - WO */ 11294 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[12] - WO */ 11295 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[11] - RO */ 11296 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[10:00] - WO */ 11297 #endif /* IS_BIG_ENDIAN */ 11298 #if IS_LITTLE_ENDIAN 11299 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[10:00] - WO */ 11300 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[11] - RO */ 11301 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[12] - WO */ 11302 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[13] - WO */ 11303 uint32_t reserved_14 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[14] - RSVD */ 11304 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE[15] - WO */ 11305 uint32_t reserved : 16; 11306 #endif /* IS_LITTLE_ENDIAN */ 11307 } fields; 11308 } IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE; 11309 11310 typedef IEEE_AN_BLK1_an_xnp_transmit_1_register_TYPE IEEE_AN_BLK1_AN_XNP_TRANSMIT_1_REGISTER_TYPE_T; 11311 11312 typedef union { 11313 uint32_t data; 11314 struct { 11315 #if IS_BIG_ENDIAN 11316 uint32_t reserved : 16; 11317 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_2_register_TYPE[15:00] - WO */ 11318 #endif /* IS_BIG_ENDIAN */ 11319 #if IS_LITTLE_ENDIAN 11320 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_2_register_TYPE[15:00] - WO */ 11321 uint32_t reserved : 16; 11322 #endif /* IS_LITTLE_ENDIAN */ 11323 } fields; 11324 } IEEE_AN_BLK1_an_xnp_transmit_2_register_TYPE; 11325 11326 typedef IEEE_AN_BLK1_an_xnp_transmit_2_register_TYPE IEEE_AN_BLK1_AN_XNP_TRANSMIT_2_REGISTER_TYPE_T; 11327 11328 typedef union { 11329 uint32_t data; 11330 struct { 11331 #if IS_BIG_ENDIAN 11332 uint32_t reserved : 16; 11333 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_3_register_TYPE[15:00] - WO */ 11334 #endif /* IS_BIG_ENDIAN */ 11335 #if IS_LITTLE_ENDIAN 11336 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_3_register_TYPE[15:00] - WO */ 11337 uint32_t reserved : 16; 11338 #endif /* IS_LITTLE_ENDIAN */ 11339 } fields; 11340 } IEEE_AN_BLK1_an_xnp_transmit_3_register_TYPE; 11341 11342 typedef IEEE_AN_BLK1_an_xnp_transmit_3_register_TYPE IEEE_AN_BLK1_AN_XNP_TRANSMIT_3_REGISTER_TYPE_T; 11343 11344 typedef union { 11345 uint32_t data; 11346 struct { 11347 #if IS_BIG_ENDIAN 11348 uint32_t reserved : 16; 11349 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[15] - RO */ 11350 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[14] - RO */ 11351 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[13] - RO */ 11352 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[12] - RO */ 11353 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[11] - RO */ 11354 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[10:00] - RO */ 11355 #endif /* IS_BIG_ENDIAN */ 11356 #if IS_LITTLE_ENDIAN 11357 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[10:00] - RO */ 11358 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[11] - RO */ 11359 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[12] - RO */ 11360 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[13] - RO */ 11361 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[14] - RO */ 11362 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE[15] - RO */ 11363 uint32_t reserved : 16; 11364 #endif /* IS_LITTLE_ENDIAN */ 11365 } fields; 11366 } IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE; 11367 11368 typedef IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_TYPE IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_1_REGISTER_TYPE_T; 11369 11370 typedef union { 11371 uint32_t data; 11372 struct { 11373 #if IS_BIG_ENDIAN 11374 uint32_t reserved : 16; 11375 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_TYPE[15:00] - RO */ 11376 #endif /* IS_BIG_ENDIAN */ 11377 #if IS_LITTLE_ENDIAN 11378 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_TYPE[15:00] - RO */ 11379 uint32_t reserved : 16; 11380 #endif /* IS_LITTLE_ENDIAN */ 11381 } fields; 11382 } IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_TYPE; 11383 11384 typedef IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_TYPE IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_2_REGISTER_TYPE_T; 11385 11386 typedef union { 11387 uint32_t data; 11388 struct { 11389 #if IS_BIG_ENDIAN 11390 uint32_t reserved : 16; 11391 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_TYPE[15:00] - RO */ 11392 #endif /* IS_BIG_ENDIAN */ 11393 #if IS_LITTLE_ENDIAN 11394 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_TYPE[15:00] - RO */ 11395 uint32_t reserved : 16; 11396 #endif /* IS_LITTLE_ENDIAN */ 11397 } fields; 11398 } IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_TYPE; 11399 11400 typedef IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_TYPE IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_3_REGISTER_TYPE_T; 11401 11402 11403 /*-----------------------------------------------*/ 11404 /* Structs for IEEE_AN_BLK3 Bank */ 11405 /*-----------------------------------------------*/ 11406 typedef union { 11407 uint32_t data; 11408 struct { 11409 #if IS_BIG_ENDIAN 11410 uint32_t reserved : 16; 11411 uint32_t reserved_12 : 4; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[15:12] - RSVD */ 11412 uint32_t onehundredbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[11] - RO */ 11413 uint32_t onehundredbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[10] - RO */ 11414 uint32_t onehundredbase_kp4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[09] - RO */ 11415 uint32_t onehundredbase_cr10 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[08] - RO */ 11416 uint32_t reserved_07 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[07] - RSVD */ 11417 uint32_t fortygbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[06] - RO */ 11418 uint32_t fortygbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[05] - RO */ 11419 uint32_t fec_negotiated : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[04] - RO */ 11420 uint32_t tengbase_kr : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[03] - RO */ 11421 uint32_t tengbase_kx4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[02] - RO */ 11422 uint32_t gigbase_kx : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[01] - RO */ 11423 uint32_t bp_an_ability : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[00] - RO */ 11424 #endif /* IS_BIG_ENDIAN */ 11425 #if IS_LITTLE_ENDIAN 11426 uint32_t bp_an_ability : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[00] - RO */ 11427 uint32_t gigbase_kx : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[01] - RO */ 11428 uint32_t tengbase_kx4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[02] - RO */ 11429 uint32_t tengbase_kr : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[03] - RO */ 11430 uint32_t fec_negotiated : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[04] - RO */ 11431 uint32_t fortygbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[05] - RO */ 11432 uint32_t fortygbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[06] - RO */ 11433 uint32_t reserved_07 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[07] - RSVD */ 11434 uint32_t onehundredbase_cr10 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[08] - RO */ 11435 uint32_t onehundredbase_kp4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[09] - RO */ 11436 uint32_t onehundredbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[10] - RO */ 11437 uint32_t onehundredbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[11] - RO */ 11438 uint32_t reserved_12 : 4; /* IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE[15:12] - RSVD */ 11439 uint32_t reserved : 16; 11440 #endif /* IS_LITTLE_ENDIAN */ 11441 } fields; 11442 } IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE; 11443 11444 typedef IEEE_AN_BLK3_backplane_ethernet_status_register_TYPE IEEE_AN_BLK3_BACKPLANE_ETHERNET_STATUS_REGISTER_TYPE_T; 11445 11446 typedef union { 11447 uint32_t data; 11448 struct { 11449 #if IS_BIG_ENDIAN 11450 uint32_t reserved : 16; 11451 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_adv_TYPE[15:07] - RSVD */ 11452 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_adv_TYPE[06] - WO */ 11453 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_adv_TYPE[05] - WO */ 11454 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_adv_TYPE[04] - WO */ 11455 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_adv_TYPE[03:00] - RSVD */ 11456 #endif /* IS_BIG_ENDIAN */ 11457 #if IS_LITTLE_ENDIAN 11458 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_adv_TYPE[03:00] - RSVD */ 11459 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_adv_TYPE[04] - WO */ 11460 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_adv_TYPE[05] - WO */ 11461 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_adv_TYPE[06] - WO */ 11462 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_adv_TYPE[15:07] - RSVD */ 11463 uint32_t reserved : 16; 11464 #endif /* IS_LITTLE_ENDIAN */ 11465 } fields; 11466 } IEEE_AN_BLK3_EEE_adv_TYPE; 11467 11468 typedef IEEE_AN_BLK3_EEE_adv_TYPE IEEE_AN_BLK3_EEE_ADV_TYPE_T; 11469 11470 typedef union { 11471 uint32_t data; 11472 struct { 11473 #if IS_BIG_ENDIAN 11474 uint32_t reserved : 16; 11475 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[15:07] - RSVD */ 11476 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[06] - RO */ 11477 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[05] - RO */ 11478 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[04] - RO */ 11479 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[03:00] - RSVD */ 11480 #endif /* IS_BIG_ENDIAN */ 11481 #if IS_LITTLE_ENDIAN 11482 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[03:00] - RSVD */ 11483 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[04] - RO */ 11484 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[05] - RO */ 11485 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[06] - RO */ 11486 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_lp_adv_TYPE[15:07] - RSVD */ 11487 uint32_t reserved : 16; 11488 #endif /* IS_LITTLE_ENDIAN */ 11489 } fields; 11490 } IEEE_AN_BLK3_EEE_lp_adv_TYPE; 11491 11492 typedef IEEE_AN_BLK3_EEE_lp_adv_TYPE IEEE_AN_BLK3_EEE_LP_ADV_TYPE_T; 11493 11494 11495 /*-----------------------------------------------*/ 11496 /* Structs for DEV7_SLICE Bank */ 11497 /*-----------------------------------------------*/ 11498 typedef union { 11499 uint32_t data; 11500 struct { 11501 #if IS_BIG_ENDIAN 11502 uint32_t reserved : 16; 11503 uint32_t dev : 1; /* DEV7_SLICE_slice_TYPE[15] - WO */ 11504 uint32_t reserved_12 : 3; /* DEV7_SLICE_slice_TYPE[14:12] - RSVD */ 11505 uint32_t cast : 4; /* DEV7_SLICE_slice_TYPE[11:08] - WO */ 11506 uint32_t lane : 4; /* DEV7_SLICE_slice_TYPE[07:04] - WO */ 11507 uint32_t reserved_01 : 3; /* DEV7_SLICE_slice_TYPE[03:01] - RSVD */ 11508 uint32_t ip : 1; /* DEV7_SLICE_slice_TYPE[00] - WO */ 11509 #endif /* IS_BIG_ENDIAN */ 11510 #if IS_LITTLE_ENDIAN 11511 uint32_t ip : 1; /* DEV7_SLICE_slice_TYPE[00] - WO */ 11512 uint32_t reserved_01 : 3; /* DEV7_SLICE_slice_TYPE[03:01] - RSVD */ 11513 uint32_t lane : 4; /* DEV7_SLICE_slice_TYPE[07:04] - WO */ 11514 uint32_t cast : 4; /* DEV7_SLICE_slice_TYPE[11:08] - WO */ 11515 uint32_t reserved_12 : 3; /* DEV7_SLICE_slice_TYPE[14:12] - RSVD */ 11516 uint32_t dev : 1; /* DEV7_SLICE_slice_TYPE[15] - WO */ 11517 uint32_t reserved : 16; 11518 #endif /* IS_LITTLE_ENDIAN */ 11519 } fields; 11520 } DEV7_SLICE_slice_TYPE; 11521 11522 typedef DEV7_SLICE_slice_TYPE DEV7_SLICE_SLICE_TYPE_T; 11523 11524 11525 #endif /* chip_reg_structs__H */