sesto_cfg_seq.h (24593B)
1 /*---------------------------------------------------------------------- 2 * 3 * Broadcom Corporation 4 * Proprietary and Confidential information 5 * All rights reserved 6 * This source file is the property of Broadcom Corporation, and 7 * may not be copied or distributed in any isomorphic form without the 8 * prior written consent of Broadcom Corporation. 9 *--------------------------------------------------------------------- 10 * File : sesto_cfg_seq.h 11 * Description: c functions implementing Tier1 12 *---------------------------------------------------------------------*/ 13 /* 14 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 15 * 16 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 17 * 18 */ 19 20 21 #ifndef SESTO_CFG_SEQ_H 22 #define SESTO_CFG_SEQ_H 23 #include <phymod/phymod_acc.h> 24 #include "sesto_serdes/common/srds_api_err_code.h" 25 26 #define SESTO_DEV_PMA_PMD 1 27 #define SESTO_DEV_AN 7 28 #define SESTO_M0_EEPROM_PAGE_SIZE 64 29 #define SESTO_FW_DLOAD_RETRY_CNT 50000 30 #define SESTO_ENABLE 1 31 #define SESTO_DISABLE 0 32 #define SESTO_SPD_100G 100000 33 #define SESTO_SPD_106G 106000 34 #define SESTO_SPD_1G 1000 35 #define SESTO_SPD_10G 10000 36 #define SESTO_SPD_11G 11000 37 #define SESTO_SPD_20G 20000 38 #define SESTO_SPD_21G 21000 39 #define SESTO_SPD_40G 40000 40 #define SESTO_SPD_42G 42000 41 #define SESTO_MAX_FALCON_LANE 4 42 #define SESTO_MAX_MERLIN_LANE 10 43 #define SESTO_DISABLE 0 44 #define SESTO_ENABLE 1 45 #define SESTO_M0_INTR_GRP 0 46 #define SESTO_MM_INTR_GRP 1 47 #define SESTO_DF_INTR_GRP 2 48 #define SESTO_DEMUX_INTR_GRP 3 49 #define SESTO_MUX_INTR_GRP 4 50 #define SESTO_FW_ALREADY_DOWNLOADED 0xFAD 51 #define SESTO_PMD_ID0 0xAE02 52 #define SESTO_PMD_ID1 0x5290 53 #define SESTO_CHIP_ID_82764 0x82764 54 #define SESTO_CHIP_ID_82792 0x82792 55 #define SESTO_CHIP_ID_82790 0x82790 56 #define SESTO_CHIP_ID_82796 0x82796 57 #define SESTO_MAX_INTRS_SUPPORT 8 58 59 typedef enum { 60 MSGOUT_DONTCARE = 0x0000, 61 MSGOUT_GET_CNT = 0x8888, 62 MSGOUT_GET_LSB = 0xABCD, 63 MSGOUT_GET_MSB = 0x4321, 64 MSGOUT_GET_2B = 0xEEEE, 65 MSGOUT_GET_B = 0xF00D, 66 MSGOUT_ERR = 0x0BAD, 67 MSGOUT_NEXT = 0x2222, 68 MSGOUT_NOT_DWNLD = 0x0101, 69 MSGOUT_DWNLD_ALREADY = 0x0202, 70 MSGOUT_DWNLD_DONE = 0x0303, 71 MSGOUT_PRGRM_DONE = 0x0404 72 } SESTO_MSGOUT_E; 73 74 typedef enum { 75 SESTO_MERLIN_CORE = 0, 76 SESTO_FALCON_CORE = 1 77 }SESTO_CORE_TYPE; 78 79 typedef struct { 80 uint16_t pass_thru; 81 uint16_t gearbox_100g_inverse_mode; 82 uint16_t BCM84793_capablity; 83 SESTO_CORE_TYPE passthru_sys_side_core; 84 uint16_t reserved; 85 }SESTO_DEVICE_AUX_MODE_T; 86 87 typedef enum { 88 SESTO_SLICE_UNICAST = 0, 89 SESTO_SLICE_MULTICAST = 1, 90 SESTO_SLICE_BROADCAST = 2, 91 SESTO_CAST_INVALID = 3 92 }SESTO_SLICE_CAST_TYPE; 93 94 typedef enum { 95 SESTO_IF_LINE = 0, 96 SESTO_IF_SYS = 1 97 }SESTO_IF_SIDE; 98 99 typedef enum { 100 SESTO_AN_NONE = 0, 101 SESTO_AN_CL73 = 1, 102 SESTO_AN_PROP = 2 103 }SESTO_AN_MODE; 104 105 typedef enum { 106 SESTO_PLL_MODE_64 = 0x0, /*4'b0000*/ 107 SESTO_PLL_MODE_66 = 0x1, /*4'b0001*/ 108 SESTO_PLL_MODE_80 = 0x2, /*4'b0010*/ 109 SESTO_PLL_MODE_128 = 0x3, /*4'b0011*/ 110 SESTO_PLL_MODE_132 = 0x4, /*4'b0100*/ 111 SESTO_PLL_MODE_140 = 0x5, /*4'b0101*/ 112 SESTO_PLL_MODE_160 = 0x6, /*4'b0110*/ 113 SESTO_PLL_MODE_165 = 0x7, /*4'b0111*/ 114 SESTO_PLL_MODE_168 = 0x8, /*4'b1000*/ 115 SESTO_PLL_MODE_170 = 0x9, /*4'b1001*/ 116 SESTO_PLL_MODE_175 = 0xa, /*4'b1010*/ 117 SESTO_PLL_MODE_180 = 0xb, /*4'b1011*/ 118 SESTO_PLL_MODE_184 = 0xc, /*4'b1100*/ 119 SESTO_PLL_MODE_200 = 0xd, /*4'b1101*/ 120 SESTO_PLL_MODE_224 = 0xe, /*4'b1110*/ 121 SESTO_PLL_MODE_264 = 0xf, /*4'b1111*/ 122 /*Sesto Specific*/ 123 SESTO_PLL_MODE_33 = 0x10, 124 SESTO_PLL_MODE_32 = 0x11, 125 SESTO_PLL_MODE_16 = 0x12, 126 SESTO_PLL_MODE_82P5= 0x13, 127 SESTO_PLL_MODE_40 = 0x14, 128 SESTO_PLL_MODE_70 = 0x15, 129 SESTO_PLL_MODE_INVALID = -1 130 } SESTO_PLL_MODE_E; 131 132 typedef enum { 133 SESTO_INT_M0_SLV_SYSRESET_REQ = 0, 134 SESTO_INT_M0_MST_SYSRESET_REQ, 135 SESTO_INT_M0_SLV_LOCKUP, 136 SESTO_INT_M0_MST_LOCKUP, 137 SESTO_INT_M0_SLV_MISC_INTR, 138 SESTO_INT_M0_MST_MISC_INTR, 139 SESTO_INT_M0_SLV_MSGOUT_INTR, 140 SESTO_INT_M0_MST_MSGOUT_INTR, 141 SESTO_INT_M0_SLV_DED, 142 SESTO_INT_M0_SLV_SEC, 143 SESTO_INT_M0_MST_DED, 144 SESTO_INT_M0_MST_SEC, 145 SESTO_INT_MODULE2_INTRB_LOW, 146 SESTO_INT_MODULE2_INTRB_HIGH, 147 SESTO_INT_MODULE1_INTRB_LOW, 148 SESTO_INT_MODULE1_INTRB_HIGH, 149 SESTO_INT_MUX_PMD_LOCK_LOST, 150 SESTO_INT_MUX_PMD_LOCK_FOUND, 151 SESTO_INT_MUX_SIGDET_LOST, 152 SESTO_INT_MUX_SIGDET_FOUND, 153 SESTO_INT_PLL_10G_LOCK_LOST, 154 SESTO_INT_PLL_10G_LOCK_FOUND, 155 SESTO_INT_MERLIN_PMI_ARB_WDOG_EXP, 156 SESTO_INT_MERLIN_PMI_M0_WDOG_EXP, 157 SESTO_INT_DEMUX_PMD_LOCK_LOST, 158 SESTO_INT_DEMUX_PMD_LOCK_FOUND, 159 SESTO_INT_DEMUX_SIGDET_LOST, 160 SESTO_INT_DEMUX_SIGDET_FOUND, 161 SESTO_INT_PLL_25G_LOCK_LOST, 162 SESTO_INT_PLL_25G_LOCK_FOUND, 163 SESTO_INT_FALCON_PMD_ARB_WDOG_EXP, 164 SESTO_INT_FALCON_PMD_M0_WDOG_EXP, 165 SESTO_INT_CL91_RX_ALIGN_LOST, 166 SESTO_INT_CL91_RX_ALIGN_FOUND, 167 SESTO_INT_DEMUX_ONEG_INBAND_MSG_LOST, 168 SESTO_INT_DEMUX_ONEG_INBAND_MSG_FOUND, 169 SESTO_INT_DEMUX_PCS_MON_LOCK_LOST, 170 SESTO_INT_DEMUX_PCS_MON_LOCK_FOUND, 171 SESTO_INT_DEMUX_FIFOERR, 172 SESTO_INT_DEMUX_CL73_AN_RESTARTED, 173 SESTO_INT_DEMUX_CL73_AN_COMPLETE, 174 SESTO_INT_CL91_TX_ALIGN_LOST, 175 SESTO_INT_CL91_TX_ALIGN_FOUND, 176 SESTO_INT_MUX_ONEG_INBAND_MSG_LOST, 177 SESTO_INT_MUX_ONEG_INBAND_MSG_FOUND, 178 SESTO_INT_MUX_PCS_MON_LOCK_LOST, 179 SESTO_INT_MUX_PCS_MON_LOCK_FOUND, 180 SESTO_INT_MUX_FIFOERR, 181 SESTO_INT_MUX_CL73_AN_RESTARTED, 182 SESTO_INT_MUX_CL73_AN_COMPLETE, 183 SESTO_INT_MUX_CL73_AN_RESTARTED_P2, 184 SESTO_INT_MUX_CL73_AN_RESTARTED_P1, 185 SESTO_INT_MUX_CL73_AN_COMPLETE_P2, 186 SESTO_INT_MUX_CL73_AN_COMPLETE_P1 187 } SESTO_INTR_TYPE_E; 188 189 #define SESTO_IF_ERR_RETURN(A) \ 190 do { \ 191 if ((rv = (A)) != PHYMOD_E_NONE) \ 192 { goto ERR; } \ 193 } while (0) 194 195 #define SESTO_RETURN_WITH_ERR(A, B) \ 196 do { \ 197 PHYMOD_DEBUG_ERROR(B); \ 198 rv = (A); \ 199 { goto ERR; } \ 200 } while (0) 201 202 #define READ_SESTO_PMA_PMD_REG(acc, addr, value) \ 203 do { \ 204 uint32_t read_tmp; \ 205 SESTO_IF_ERR_RETURN \ 206 (PHYMOD_BUS_READ(acc, ((SESTO_DEV_PMA_PMD << 16) | addr), &read_tmp)); \ 207 value = (read_tmp & 0xffff); \ 208 } while (0); 209 210 #define WRITE_SESTO_PMA_PMD_REG(acc, addr, value) \ 211 SESTO_IF_ERR_RETURN \ 212 (PHYMOD_BUS_WRITE(acc, (SESTO_DEV_PMA_PMD << 16) | addr, value)); 213 214 #define READ_SESTO_AN_REG(acc, addr, value) \ 215 do { \ 216 uint32_t an_read_tmp; \ 217 SESTO_IF_ERR_RETURN \ 218 (PHYMOD_BUS_READ(acc, ((SESTO_DEV_AN << 16) | addr), &an_read_tmp)); \ 219 value = (an_read_tmp & 0xffff); \ 220 } while (0); 221 222 #define WRITE_SESTO_AN_REG(acc, addr, value) \ 223 SESTO_IF_ERR_RETURN \ 224 (PHYMOD_BUS_WRITE(acc, (SESTO_DEV_AN << 16) | addr, value)); 225 226 #define SESTO_CHIP_FIELD_WRITE(acc, reg_name, field_name, value) \ 227 do { \ 228 reg_name##_TYPE_T cfw_tmp; \ 229 READ_SESTO_PMA_PMD_REG(acc, reg_name##_ADR, cfw_tmp.data); \ 230 cfw_tmp.fields.field_name = value; \ 231 WRITE_SESTO_PMA_PMD_REG(acc, reg_name##_ADR, cfw_tmp.data); \ 232 } while (0); 233 234 #define SESTO_CHIP_FIELD_READ(acc, reg_name, field_name, value) \ 235 do { \ 236 reg_name##_TYPE_T cfr_tmp; \ 237 READ_SESTO_PMA_PMD_REG(acc, reg_name##_ADR, cfr_tmp.data); \ 238 value = cfr_tmp.fields.field_name; \ 239 } while (0); 240 241 #define SESTO_GET_CORE(_C, _LT, _ST) \ 242 { \ 243 SESTO_DEVICE_AUX_MODE_T *aux_mode_m; \ 244 aux_mode_m = (SESTO_DEVICE_AUX_MODE_T*)_C.device_aux_modes; \ 245 if (aux_mode_m->pass_thru) { \ 246 _LT = (aux_mode_m->passthru_sys_side_core == SESTO_FALCON_CORE) ? SESTO_MERLIN_CORE : SESTO_FALCON_CORE; \ 247 } else if (_C.data_rate == SESTO_SPD_100G || _C.data_rate == SESTO_SPD_106G) { \ 248 _LT = (aux_mode_m->gearbox_100g_inverse_mode) ? SESTO_MERLIN_CORE : SESTO_FALCON_CORE ; \ 249 } else { \ 250 _LT = (aux_mode_m->passthru_sys_side_core == SESTO_FALCON_CORE) ? SESTO_MERLIN_CORE : SESTO_FALCON_CORE; \ 251 } \ 252 _ST = (_LT == SESTO_MERLIN_CORE) ? SESTO_FALCON_CORE : SESTO_MERLIN_CORE; \ 253 } 254 255 #define SESTO_IS_MULTI_BROAD_CAST_SET(_C) (_C == SESTO_SLICE_MULTICAST || _C == SESTO_SLICE_BROADCAST) 256 #define SESTO_GET_INTF_SIDE(phy, if_side) (if_side = (phy->port_loc == phymodPortLocSys) ? SESTO_IF_SYS : SESTO_IF_LINE) 257 #define SESTO_GET_CORE_SLICE_INFO(_ACC, _IP, _CON, _C_V, _M_V) \ 258 do { \ 259 SESTO_CORE_TYPE line_ip_type, sys_ip_type; \ 260 uint16_t intf_side = 0; \ 261 SESTO_GET_INTF_SIDE(_ACC, intf_side); \ 262 SESTO_GET_CORE(_CON, line_ip_type, sys_ip_type); \ 263 _IP = (intf_side == SESTO_IF_LINE) ? line_ip_type : sys_ip_type; \ 264 _sesto_lane_cast_get(_ACC, _IP, _C_V, _M_V); \ 265 }while(0); 266 267 #define SESTO_GET_IP(_ACC, _CON, _IP) \ 268 do { \ 269 SESTO_CORE_TYPE line_ip_type, sys_ip_type; \ 270 uint16_t intf_side = 0; \ 271 SESTO_GET_INTF_SIDE(_ACC, intf_side); \ 272 SESTO_GET_CORE(_CON, line_ip_type, sys_ip_type); \ 273 _IP = (intf_side == SESTO_IF_LINE) ? line_ip_type : sys_ip_type; \ 274 }while(0); 275 276 #define SESTO_RESET_SLICE(_P, _DT) \ 277 if (_DT == SESTO_DEV_PMA_PMD) { \ 278 SESTO_IF_ERR_RETURN \ 279 (PHYMOD_BUS_WRITE(_P, (SESTO_DEV_PMA_PMD << 16) | DEV1_SLICE_SLICE_ADR ,0x0)); \ 280 } else { \ 281 SESTO_IF_ERR_RETURN \ 282 (PHYMOD_BUS_WRITE(_P, (SESTO_DEV_AN << 16) | DEV7_SLICE_SLICE_ADR , 0x0)); \ 283 } 284 285 #define SESTO_GET_PORT_FROM_MODE(_C, _PRT, aux_mode) \ 286 do { \ 287 if (_C->data_rate == SESTO_SPD_100G || _C->data_rate == SESTO_SPD_106G) { \ 288 _PRT = 1; \ 289 } else if ((_C->data_rate == SESTO_SPD_40G || _C->data_rate == SESTO_SPD_42G) && aux_mode->pass_thru) { \ 290 _PRT = 1; \ 291 } else if ((_C->data_rate == SESTO_SPD_40G || _C->data_rate == SESTO_SPD_42G) && (!aux_mode->pass_thru)){ \ 292 _PRT = 2; \ 293 } else if (_C->data_rate == SESTO_SPD_20G || _C->data_rate == SESTO_SPD_21G) { \ 294 _PRT = 2; \ 295 } else if (_C->data_rate == SESTO_SPD_1G || _C->data_rate == SESTO_SPD_10G \ 296 || _C->data_rate == SESTO_SPD_11G) { \ 297 _PRT = 4; \ 298 } \ 299 }while(0); 300 301 typedef enum { 302 SESTO_CL73_NO_TECH = 0, 303 SESTO_CL73_1000BASE_KX = 0x1, 304 SESTO_CL73_10GBASE_KX4 = 0x2, 305 SESTO_CL73_10GBASE_KR = 0x4, 306 SESTO_CL73_40GBASE_KR4 = 0x8, 307 SESTO_CL73_40GBASE_CR4 = 0x10, 308 SESTO_CL73_100GBASE_CR10 = 0x20, 309 SESTO_CL73_100GBASE_KP4 = 0x40, 310 SESTO_CL73_100GBASE_KR4 = 0x80, 311 SESTO_CL73_100GBASE_CR4 = 0x100 312 } SESTO_CL73_SPEED_T; 313 314 typedef enum { 315 SESTO_NO_PAUSE = 0, 316 SESTO_ASYM_PAUSE, 317 SESTO_SYMM_PAUSE, 318 SESTO_ASYM_SYMM_PAUSE, 319 SESTO_AN_PAUSE_COUNT 320 } SESTO_AN_PAUSE_T; 321 322 /* Module controller I2C master commands */ 323 typedef enum { 324 SESTO_FLUSH = 0, 325 SESTO_RANDOM_ADDRESS_READ, 326 SESTO_CURRENT_ADDRESS_READ, 327 SESTO_WRITE 328 } SESTO_I2CM_CMD_E; 329 330 typedef struct SESTO_AN_ADV_ABILITY_S{ 331 SESTO_CL73_SPEED_T an_base_speed; 332 SESTO_AN_PAUSE_T an_pause; 333 uint16_t an_fec; 334 uint16_t an_cl72; 335 } sesto_an_adv_ability_t; 336 337 typedef struct sesto_an_ability_s { 338 sesto_an_adv_ability_t cl73_adv; /*includes cl73 related */ 339 uint32_t an_master_lane; /* Master lane belongs to port. For 10 lane port[0-9], for 4 lane port [0-3], for 2 lane port [0-1]*/ 340 } sesto_an_ability_t; 341 342 #define SESTO_FALCON 343 #define SESTO_MERLIN 344 345 int sesto_get_chipid(const phymod_access_t *pa, uint32_t *chipid, uint32_t *rev); 346 347 int _sesto_wait_mst_msgout(const phymod_access_t *pa, 348 SESTO_MSGOUT_E exp_message, 349 int poll_time); 350 351 int _sesto_core_init(const phymod_core_access_t* core, 352 const phymod_core_init_config_t* init_config); 353 354 int _sesto_set_slice_reg(const phymod_access_t* pm_acc, SESTO_SLICE_CAST_TYPE cast_type, 355 uint16_t ip, uint16_t dev_type, uint16_t mcast_val, uint16_t lane); 356 357 void _sesto_lane_cast_get(const phymod_phy_access_t *phy, SESTO_CORE_TYPE ip, 358 uint16_t *cast_type, uint16_t *mcast_val); 359 360 int _sesto_phy_interface_config_get(const phymod_phy_access_t *phy, 361 uint32_t flags, phymod_phy_inf_config_t *config); 362 363 int _sesto_rx_pmd_lock_get(const phymod_phy_access_t *phy, uint32_t* rx_pmd_locked); 364 365 int _sesto_config_dut_mode_reg(const phymod_phy_access_t *phy, 366 const phymod_phy_inf_config_t* config); 367 368 int _sesto_udms_config(const phymod_phy_access_t *phy, 369 const phymod_phy_inf_config_t* config, 370 SESTO_AN_MODE mode); 371 372 int _sesto_phy_interface_config_set(const phymod_phy_access_t *phy, 373 uint32_t flags, const phymod_phy_inf_config_t* config); 374 375 int sesto_is_lane_mask_set(const phymod_phy_access_t *phy, uint16_t prt, 376 const phymod_phy_inf_config_t *config); 377 378 int _sesto_config_dut_mode_reg(const phymod_phy_access_t *phy, 379 const phymod_phy_inf_config_t* config); 380 381 int _sesto_udms_config(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config, 382 SESTO_AN_MODE mode); 383 384 int _sesto_interface_set(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config); 385 386 int _sesto_phy_interface_config_set(const phymod_phy_access_t* pa, uint32_t flags, 387 const phymod_phy_inf_config_t* config); 388 389 int _sesto_phy_interface_config_get(const phymod_phy_access_t *phy, uint32_t flags, 390 phymod_phy_inf_config_t *config); 391 392 int _sesto_phy_pcs_link_get(const phymod_phy_access_t *phy, uint32_t *pcs_link); 393 394 int _sesto_configure_ref_clock(const phymod_access_t *pa, phymod_ref_clk_t ref_clk); 395 396 int _sesto_get_pll_modes(phymod_ref_clk_t ref_clk, const phymod_phy_inf_config_t *config, 397 uint16_t *fal_pll_mode, uint16_t *mer_pll_mode); 398 399 int _sesto_map_mer_pll_div(SESTO_PLL_MODE_E pll_mode); 400 401 int _sesto_config_pll_div(const phymod_access_t *pa, const phymod_phy_inf_config_t *config); 402 403 int _sesto_core_dp_rstb(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t cfg); 404 405 int _sesto_core_reset_set(const phymod_access_t *pa, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction); 406 407 int _sesto_get_pcs_link_status(const phymod_phy_access_t *phy, uint32_t *link_sts, uint32_t* lock_lost_lh, uint32_t* error_count); 408 409 int _sesto_pcs_link_monitor_enable_set(const phymod_phy_access_t *phy, uint16_t en_dis); 410 411 int _sesto_pcs_link_monitor_enable_get(const phymod_phy_access_t *phy, uint32_t *get_pcs); 412 413 int _sesto_fw_enable(const phymod_access_t *pa, uint16_t en_dis) ; 414 415 int _sesto_get_ieee_intf(const phymod_phy_access_t *phy, uint16_t ip, const phymod_phy_inf_config_t *config, uint16_t *intf); 416 417 int _sesto_set_ieee_intf(const phymod_phy_access_t *phy, uint16_t intf, const phymod_phy_inf_config_t *config, uint16_t ip); 418 419 int _sesto_loopback_set(const phymod_phy_access_t *phy, phymod_loopback_mode_t loopback, uint32_t enable); 420 421 int _sesto_loopback_get(const phymod_phy_access_t *phy, phymod_loopback_mode_t loopback, uint32_t *enable); 422 423 int _sesto_tx_rx_polarity_set(const phymod_phy_access_t *phy, uint32_t tx_polarity, uint32_t rx_polarity); 424 425 int _sesto_tx_rx_polarity_get(const phymod_phy_access_t *phy, uint32_t *tx_polarity, uint32_t *rx_polarity); 426 427 int _sesto_tx_set(const phymod_phy_access_t *phy, const phymod_tx_t* tx); 428 429 int _sesto_tx_get(const phymod_phy_access_t *phy, phymod_tx_t* tx); 430 431 int _sesto_rx_set(const phymod_phy_access_t *phy, const phymod_rx_t* rx); 432 433 int _sesto_rx_get(const phymod_phy_access_t *phy, phymod_rx_t* rx); 434 435 int _sesto_tx_power_set(const phymod_phy_access_t *phy, uint32_t power_tx); 436 437 int _sesto_rx_power_set(const phymod_phy_access_t *phy, uint32_t power_rx); 438 439 int _sesto_tx_rx_power_get(const phymod_phy_access_t *phy, phymod_phy_power_t* power); 440 441 int _sesto_force_tx_training_set(const phymod_phy_access_t *phy, uint32_t enable); 442 443 int _sesto_force_tx_training_get(const phymod_phy_access_t *phy, uint32_t *enable); 444 445 int _sesto_force_tx_training_status_get(const phymod_phy_access_t *phy, phymod_cl72_status_t* status); 446 447 int _sesto_phy_reset_set(const phymod_phy_access_t *phy, const phymod_phy_reset_t* reset); 448 449 int _sesto_phy_reset_get(const phymod_phy_access_t *phy, phymod_phy_reset_t* reset); 450 451 int _sesto_phy_status_dump(const phymod_phy_access_t *phy); 452 453 int _sesto_tx_lane_control_set(const phymod_phy_access_t *phy, phymod_phy_tx_lane_control_t tx_control); 454 455 int _sesto_rx_lane_control_set(const phymod_phy_access_t *phy, phymod_phy_rx_lane_control_t rx_control); 456 457 int _sesto_tx_lane_control_get(const phymod_phy_access_t *phy, phymod_phy_tx_lane_control_t *tx_control); 458 459 int _sesto_rx_lane_control_get(const phymod_phy_access_t *phy, phymod_phy_rx_lane_control_t *rx_control); 460 461 int _sesto_ext_intr_status_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t* intr_status); 462 463 int _sesto_ext_intr_enable_set(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t enable); 464 465 int _sesto_ext_intr_enable_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t* enable); 466 467 int _sesto_ext_intr_status_clear(const phymod_phy_access_t *phy, uint32_t intr_type); 468 469 int _sesto_pll_sequencer_restart(const phymod_core_access_t *core, phymod_sequencer_operation_t operation); 470 471 int _sesto_fec_enable_set(const phymod_phy_access_t *phy, uint32_t enable); 472 473 int _sesto_fec_enable_get(const phymod_phy_access_t *phy, uint32_t* enable); 474 475 int _sesto_config_hcd_link_sts(const phymod_access_t *pa, phymod_phy_inf_config_t config, uint16_t ip); 476 477 int _sesto_autoneg_ability_set(const phymod_phy_access_t *phy, sesto_an_ability_t *an_ability); 478 479 int _sesto_autoneg_set(const phymod_phy_access_t *phy, const phymod_autoneg_control_t* an); 480 481 int _sesto_autoneg_get(const phymod_phy_access_t *phy, phymod_autoneg_control_t* an, uint32_t *an_done); 482 483 int _sesto_autoneg_ability_get(const phymod_phy_access_t *phy, sesto_an_ability_t *an_ablity); 484 485 int _sesto_autoneg_remote_ability_get(const phymod_phy_access_t *phy, phymod_autoneg_ability_t* an_ability_get); 486 487 int _sesto_pcs_link_monitor_enable_get(const phymod_phy_access_t *phy, uint32_t *get_pcs); 488 489 int _sesto_pcs_link_monitor_enable_set(const phymod_phy_access_t *phy, uint16_t en_dis); 490 491 int _sesto_port_from_lane_map_get(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* cfg, uint16_t *port); 492 493 int _sesto_gpio_config_set(const phymod_access_t *pa, int pin_no, phymod_gpio_mode_t gpio_mode); 494 495 int _sesto_gpio_config_get(const phymod_access_t *pa, int pin_no, phymod_gpio_mode_t* gpio_mode); 496 497 int _sesto_gpio_pin_value_set(const phymod_access_t *pa, int pin_no, int value); 498 499 int _sesto_gpio_pin_value_get(const phymod_access_t *pa, int pin_no, int* value); 500 501 int _sesto_module_write(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, uint32_t no_of_bytes, const uint8_t *write_data); 502 503 int _sesto_module_read(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, uint32_t no_of_bytes, uint8_t *read_data); 504 505 int _sesto_set_module_command(const phymod_access_t *pa, uint16_t xfer_addr, uint32_t slv_addr, unsigned char xfer_cnt, SESTO_I2CM_CMD_E cmd); 506 507 int _sesto_phy_repeater_mode_set(const phymod_phy_access_t *phy, phymod_operation_mode_t repeater_mode); 508 509 int _sesto_core_cfg_polarity_set(const phymod_phy_access_t *phy, uint32_t tx_polarity, uint32_t rx_polarity); 510 511 int _sesto_core_cfg_tx_set(const phymod_phy_access_t *phy,const phymod_tx_t* tx); 512 513 int _sesto_rx_adaptation_resume(const phymod_phy_access_t* phy); 514 515 err_code_t _sesto_merlin_read_pll_range(const phymod_access_t *pa, uint32_t *pll_range); 516 517 err_code_t _sesto_falcon_read_pll_range(const phymod_access_t *pa, uint32_t *pll_range); 518 519 int _sesto_firmware_lane_config_set(const phymod_phy_access_t* pa, phymod_firmware_lane_config_t fw_config); 520 521 int _sesto_firmware_lane_config_get(const phymod_phy_access_t* pa, phymod_firmware_lane_config_t* fw_config); 522 523 int _sesto_phy_short_channel_mode_set(const phymod_phy_access_t *phy, uint32_t enable); 524 525 int _sesto_phy_short_channel_mode_get(const phymod_phy_access_t *phy, uint32_t *enable, uint32_t *status); 526 527 int _sesto_phy_eye_margin_est_get(const phymod_phy_access_t *phy, int *left_eye_mUI, int *right_eye_mUI, int *upper_eye_mV, int *lower_eye_mV); 528 #endif /* SESTO_CFG_SEQ_H */