sesto_address_defines.h (63790B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 /*================================================================*/ 8 /* Automatically Generated by rdbHC.sh */ 9 /* - Do Not Edit - */ 10 /*================================================================*/ 11 #ifndef chip_address_defines__H 12 #define chip_address_defines__H 13 14 /*-----------------------------------------------*/ 15 /* Defines for IEEE_PMA_PMD_BLK0 Bank */ 16 /*-----------------------------------------------*/ 17 #define IEEE_PMA_PMD_BLK0_BASEADR (0x0000) 18 #define IEEE_PMA_PMD_BLK0_PMD_CONTROL_REGISTER_ADR (0x0000) 19 #define IEEE_PMA_PMD_BLK0_STATUS_REGISTER_ADR (0x0001) 20 #define IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_0_ADR (0x0002) 21 #define IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_1_ADR (0x0003) 22 #define IEEE_PMA_PMD_BLK0_PMD_SPEED_ABILITY_ADR (0x0004) 23 #define IEEE_PMA_PMD_BLK0_DEVICES_IN_PACKAGE_1_ADR (0x0005) 24 #define IEEE_PMA_PMD_BLK0_DEVICES_IN_PACKAGE_2_ADR (0x0006) 25 #define IEEE_PMA_PMD_BLK0_PMD_CONTROL_2_REGISTER_ADR (0x0007) 26 #define IEEE_PMA_PMD_BLK0_STATUS_REGISTER_2_ADR (0x0008) 27 #define IEEE_PMA_PMD_BLK0_PMD_TRANSMIT_DISABLE_REGISTER_ADR (0x0009) 28 #define IEEE_PMA_PMD_BLK0_PMD_EXTENDED_ABILITY_REGISTER_ADR (0x000b) 29 #define IEEE_PMA_PMD_BLK0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_ADR (0x000d) 30 #define IEEE_PMA_PMD_BLK0_PMD_OUI_ID0_REGISTER_ADR (0x000e) 31 #define IEEE_PMA_PMD_BLK0_PMD_OUI_ID1_REG_ADR (0x000f) 32 33 /*-----------------------------------------------*/ 34 /* Defines for M10G_CL72_IEEE_TX Bank */ 35 /*-----------------------------------------------*/ 36 #define M10G_CL72_IEEE_TX_BASEADR (0x0090) 37 #define M10G_CL72_IEEE_TX_BASE_R_PMD_CONTROL_REGISTER_150_ADR (0x0096) 38 #define M10G_CL72_IEEE_TX_BASE_R_PMD_STATUS_REGISTER_151_ADR (0x0097) 39 #define M10G_CL72_IEEE_TX_BASE_R_LP_COEFF_UPDATE_REGISTER_152_ADR (0x0098) 40 #define M10G_CL72_IEEE_TX_BASE_R_LD_COEFF_UPDATE_REGISTER_154_ADR (0x009a) 41 #define M10G_CL72_IEEE_TX_BASE_R_LD_STATUS_REPORT_REGISTER_155_ADR (0x009b) 42 43 /*-----------------------------------------------*/ 44 /* Defines for M10G_CL72_IEEE_RX Bank */ 45 /*-----------------------------------------------*/ 46 #define M10G_CL72_IEEE_RX_BASEADR (0x0090) 47 #define M10G_CL72_IEEE_RX_BASE_R_LD_STATUS_REPORT_REGISTER_153_ADR (0x0099) 48 49 /*-----------------------------------------------*/ 50 /* Defines for F25G_CL93n72_IEEE_TX Bank */ 51 /*-----------------------------------------------*/ 52 #define F25G_CL93N72_IEEE_TX_BASEADR (0x0090) 53 #define F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150_ADR (0x0096) 54 #define F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151_ADR (0x0097) 55 #define F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154_ADR (0x009a) 56 #define F25G_CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155_ADR (0x009b) 57 58 /*-----------------------------------------------*/ 59 /* Defines for F25G_CL93n72_IEEE_RX Bank */ 60 /*-----------------------------------------------*/ 61 #define F25G_CL93N72_IEEE_RX_BASEADR (0x0090) 62 #define F25G_CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152_ADR (0x0098) 63 #define F25G_CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153_ADR (0x0099) 64 65 /*-----------------------------------------------*/ 66 /* Defines for IEEE_CL91_RX Bank */ 67 /*-----------------------------------------------*/ 68 #define IEEE_CL91_RX_BASEADR (0x0000) 69 #define IEEE_CL91_RX_FEC_CONTROL_ADR (0x00c8) 70 #define IEEE_CL91_RX_FEC_STATUS_ADR (0x00c9) 71 #define IEEE_CL91_RX_FEC_CORR_CW_CNT_LOWER_REG_ADR (0x00ca) 72 #define IEEE_CL91_RX_FEC_CORR_CW_CNT_UPPER_REG_ADR (0x00cb) 73 #define IEEE_CL91_RX_FEC_UNCORR_CW_CNT_LOWER_REG_ADR (0x00cc) 74 #define IEEE_CL91_RX_FEC_UNCORR_CW_CNT_UPPER_REG_ADR (0x00cd) 75 #define IEEE_CL91_RX_FEC_LANE_MAPPING_ADR (0x00ce) 76 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_0_LOWER_REG_ADR (0x00d2) 77 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_0_UPPER_REG_ADR (0x00d3) 78 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_1_LOWER_REG_ADR (0x00d4) 79 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_1_UPPER_REG_ADR (0x00d5) 80 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_2_LOWER_REG_ADR (0x00d6) 81 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_2_UPPER_REG_ADR (0x00d7) 82 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_3_LOWER_REG_ADR (0x00d8) 83 #define IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_3_UPPER_REG_ADR (0x00d9) 84 85 /*-----------------------------------------------*/ 86 /* Defines for IEEE_CL91_TX Bank */ 87 /*-----------------------------------------------*/ 88 #define IEEE_CL91_TX_BASEADR (0x0000) 89 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_0_REG_ADR (0x00e6) 90 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_1_REG_ADR (0x00e7) 91 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_2_REG_ADR (0x00e8) 92 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_3_REG_ADR (0x00e9) 93 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_4_REG_ADR (0x00ea) 94 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_5_REG_ADR (0x00eb) 95 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_6_REG_ADR (0x00ec) 96 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_7_REG_ADR (0x00ed) 97 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_8_REG_ADR (0x00ee) 98 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_9_REG_ADR (0x00ef) 99 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_10_REG_ADR (0x00f0) 100 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_11_REG_ADR (0x00f1) 101 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_12_REG_ADR (0x00f2) 102 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_13_REG_ADR (0x00f3) 103 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_14_REG_ADR (0x00f4) 104 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_15_REG_ADR (0x00f5) 105 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_16_REG_ADR (0x00f6) 106 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_17_REG_ADR (0x00f7) 107 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_18_REG_ADR (0x00f8) 108 #define IEEE_CL91_TX_BIP_ERR_CNT_LN_19_REG_ADR (0x00f9) 109 #define IEEE_CL91_TX_PCS_LN_0_MAPPING_REG_ADR (0x00fa) 110 #define IEEE_CL91_TX_PCS_LN_1_MAPPING_REG_ADR (0x00fb) 111 #define IEEE_CL91_TX_PCS_LN_2_MAPPING_REG_ADR (0x00fc) 112 #define IEEE_CL91_TX_PCS_LN_3_MAPPING_REG_ADR (0x00fd) 113 #define IEEE_CL91_TX_PCS_LN_4_MAPPING_REG_ADR (0x00fe) 114 #define IEEE_CL91_TX_PCS_LN_5_MAPPING_REG_ADR (0x00ff) 115 #define IEEE_CL91_TX_PCS_LN_6_MAPPING_REG_ADR (0x0100) 116 #define IEEE_CL91_TX_PCS_LN_7_MAPPING_REG_ADR (0x0101) 117 #define IEEE_CL91_TX_PCS_LN_8_MAPPING_REG_ADR (0x0102) 118 #define IEEE_CL91_TX_PCS_LN_9_MAPPING_REG_ADR (0x0103) 119 #define IEEE_CL91_TX_PCS_LN_10_MAPPING_REG_ADR (0x0104) 120 #define IEEE_CL91_TX_PCS_LN_11_MAPPING_REG_ADR (0x0105) 121 #define IEEE_CL91_TX_PCS_LN_12_MAPPING_REG_ADR (0x0106) 122 #define IEEE_CL91_TX_PCS_LN_13_MAPPING_REG_ADR (0x0107) 123 #define IEEE_CL91_TX_PCS_LN_14_MAPPING_REG_ADR (0x0108) 124 #define IEEE_CL91_TX_PCS_LN_15_MAPPING_REG_ADR (0x0109) 125 #define IEEE_CL91_TX_PCS_LN_16_MAPPING_REG_ADR (0x010a) 126 #define IEEE_CL91_TX_PCS_LN_17_MAPPING_REG_ADR (0x010b) 127 #define IEEE_CL91_TX_PCS_LN_18_MAPPING_REG_ADR (0x010c) 128 #define IEEE_CL91_TX_PCS_LN_19_MAPPING_REG_ADR (0x010d) 129 #define IEEE_CL91_TX_PCS_ALIGN_STATUS1_REG_ADR (0x0118) 130 #define IEEE_CL91_TX_PCS_ALIGN_STATUS2_REG_ADR (0x0119) 131 #define IEEE_CL91_TX_PCS_ALIGN_STATUS3_REG_ADR (0x011a) 132 #define IEEE_CL91_TX_PCS_ALIGN_STATUS4_REG_ADR (0x011b) 133 134 /*-----------------------------------------------*/ 135 /* Defines for DEV1_SLICE Bank */ 136 /*-----------------------------------------------*/ 137 #define DEV1_SLICE_BASEADR (0x0000) 138 #define DEV1_SLICE_SLICE_ADR (0x8000) 139 140 /*-----------------------------------------------*/ 141 /* Defines for SES_MDICS_PMI_ARB_MASK Bank */ 142 /*-----------------------------------------------*/ 143 #define SES_MDICS_PMI_ARB_MASK_BASEADR (0x0000) 144 #define SES_MDICS_PMI_ARB_MASK_CTRL_ADR (0x8020) 145 146 /*-----------------------------------------------*/ 147 /* Defines for SES_GEN_CNTRLS Bank */ 148 /*-----------------------------------------------*/ 149 #define SES_GEN_CNTRLS_BASEADR (0x0000) 150 #define SES_GEN_CNTRLS_GEN_CONTROL1_ADR (0x8200) 151 #define SES_GEN_CNTRLS_GEN_CONTROL2_ADR (0x8201) 152 #define SES_GEN_CNTRLS_GEN_CONTROL3_ADR (0x8202) 153 #define SES_GEN_CNTRLS_SPI_MST_CODE_START_PTR_ADR (0x8210) 154 #define SES_GEN_CNTRLS_SPI_SLV_CODE_START_PTR_ADR (0x8211) 155 #define SES_GEN_CNTRLS_SPI_CODE_LOAD_EN_ADR (0x8212) 156 #define SES_GEN_CNTRLS_SPI_EEPROM_CONTROL_ADR (0x8213) 157 #define SES_GEN_CNTRLS_MSCR_ADR (0x8214) 158 #define SES_GEN_CNTRLS_MSGOUT_ADR (0x8215) 159 #define SES_GEN_CNTRLS_MSGIN_ADR (0x8216) 160 #define SES_GEN_CNTRLS_BOOT_ADR (0x8217) 161 #define SES_GEN_CNTRLS_SLV_MSGOUT_ADR (0x8218) 162 #define SES_GEN_CNTRLS_SLV_MSGIN_ADR (0x8219) 163 #define SES_GEN_CNTRLS_GPREG10_ADR (0x822a) 164 #define SES_GEN_CNTRLS_GPREG11_ADR (0x822b) 165 #define SES_GEN_CNTRLS_GPREG12_ADR (0x822c) 166 #define SES_GEN_CNTRLS_GPREG13_ADR (0x822d) 167 #define SES_GEN_CNTRLS_GPREG14_ADR (0x822e) 168 #define SES_GEN_CNTRLS_GPREG15_ADR (0x822f) 169 #define SES_GEN_CNTRLS_MST_RUNNING_CHKSUM_ADR (0x8230) 170 #define SES_GEN_CNTRLS_SLV_RUNNING_CHKSUM_ADR (0x8231) 171 #define SES_GEN_CNTRLS_MST_RUNNING_BYTE_CNT_ADR (0x8232) 172 #define SES_GEN_CNTRLS_SLV_RUNNING_BYTE_CNT_ADR (0x8233) 173 #define SES_GEN_CNTRLS_FIRMWARE_VERSION_ADR (0x8234) 174 #define SES_GEN_CNTRLS_FIRMWARE_ENABLE_ADR (0x8235) 175 #define SES_GEN_CNTRLS_MICRO_SYNC_0_ADR (0x8240) 176 #define SES_GEN_CNTRLS_MICRO_SYNC_1_ADR (0x8241) 177 #define SES_GEN_CNTRLS_MICRO_SYNC_2_ADR (0x8242) 178 #define SES_GEN_CNTRLS_MICRO_SYNC_3_ADR (0x8243) 179 #define SES_GEN_CNTRLS_MICRO_SYNC_4_ADR (0x8244) 180 #define SES_GEN_CNTRLS_MICRO_SYNC_5_ADR (0x8245) 181 #define SES_GEN_CNTRLS_MICRO_SYNC_6_ADR (0x8246) 182 #define SES_GEN_CNTRLS_MICRO_SYNC_7_ADR (0x8247) 183 184 /*-----------------------------------------------*/ 185 /* Defines for SES_MICRO_BOOT Bank */ 186 /*-----------------------------------------------*/ 187 #define SES_MICRO_BOOT_BASEADR (0x0000) 188 #define SES_MICRO_BOOT_BOOT_POR_ADR (0x82ff) 189 190 /*-----------------------------------------------*/ 191 /* Defines for SES_M0ACCESS_ADDR Bank */ 192 /*-----------------------------------------------*/ 193 #define SES_M0ACCESS_ADDR_BASEADR (0x0000) 194 #define SES_M0ACCESS_ADDR_MASTER_DRAM_MEM_ADD_ADR (0x8401) 195 196 /*-----------------------------------------------*/ 197 /* Defines for SES_M0ACCESS_DATA Bank */ 198 /*-----------------------------------------------*/ 199 #define SES_M0ACCESS_DATA_BASEADR (0x0000) 200 #define SES_M0ACCESS_DATA_MASTER_DRAM_WDATA_ADR (0x8414) 201 #define SES_M0ACCESS_DATA_MASTER_DRAM_RDATA_ADR (0x8415) 202 203 /*-----------------------------------------------*/ 204 /* Defines for SES_CTRL Bank */ 205 /*-----------------------------------------------*/ 206 #define SES_CTRL_BASEADR (0x0000) 207 #define SES_CTRL_CHIP_ID_ADR (0x8a00) 208 #define SES_CTRL_CHIP_REVISION_ADR (0x8a01) 209 #define SES_CTRL_M0_EISR_ADR (0x8a10) 210 #define SES_CTRL_M0_EIPR_ADR (0x8a11) 211 #define SES_CTRL_M0_EIER_ADR (0x8a12) 212 #define SES_CTRL_MM_EISR_ADR (0x8a13) 213 #define SES_CTRL_MM_EIPR_ADR (0x8a14) 214 #define SES_CTRL_MM_EIER_ADR (0x8a15) 215 #define SES_CTRL_DF_EISR_ADR (0x8a16) 216 #define SES_CTRL_DF_EIPR_ADR (0x8a17) 217 #define SES_CTRL_DF_EIER_ADR (0x8a18) 218 #define SES_CTRL_DEMUX_EISR_ADR (0x8a19) 219 #define SES_CTRL_DEMUX_EIPR_ADR (0x8a1a) 220 #define SES_CTRL_DEMUX_EIER_ADR (0x8a1b) 221 #define SES_CTRL_MUX_EISR_ADR (0x8a1c) 222 #define SES_CTRL_MUX_EIPR_ADR (0x8a1d) 223 #define SES_CTRL_MUX_EIER_ADR (0x8a1e) 224 #define SES_CTRL_GENERAL_PURPOSE_IO_CTRL0_ADR (0x8a80) 225 #define SES_CTRL_GENERAL_PURPOSE_IO_CTRL1_ADR (0x8a81) 226 #define SES_CTRL_TEST_PAD_CTRL_ADR (0x8a82) 227 #define SES_CTRL_CLOCK_SCALER_CTRL_ADR (0x8af0) 228 229 /*-----------------------------------------------*/ 230 /* Defines for SES_MODULE_CNTRL Bank */ 231 /*-----------------------------------------------*/ 232 #define SES_MODULE_CNTRL_BASEADR (0x0000) 233 #define SES_MODULE_CNTRL_CONTROL_ADR (0x8700) 234 #define SES_MODULE_CNTRL_STATUS_ADR (0x8701) 235 #define SES_MODULE_CNTRL_XFER_COUNT_ADR (0x8702) 236 #define SES_MODULE_CNTRL_ADDRESS_ADR (0x8703) 237 #define SES_MODULE_CNTRL_XFER_ADDRESS_ADR (0x8704) 238 #define SES_MODULE_CNTRL_DEV_ID_ADR (0x8705) 239 #define SES_MODULE_CNTRL_RAM_NVR0_ADR (0x8800) 240 241 /*-----------------------------------------------*/ 242 /* Defines for SES_PAD_CTRL Bank */ 243 /*-----------------------------------------------*/ 244 #define SES_PAD_CTRL_BASEADR (0x0000) 245 #define SES_PAD_CTRL_EXT_UC_RSTB_OUT_CONTROL_ADR (0x8a54) 246 #define SES_PAD_CTRL_MOD_LOPWR_CONTROL_ADR (0x8a58) 247 #define SES_PAD_CTRL_MOD_LOPWR_STATUS_ADR (0x8a59) 248 #define SES_PAD_CTRL_MOD_ABS_CONTROL_ADR (0x8a5a) 249 #define SES_PAD_CTRL_MOD_ABS_STATUS_ADR (0x8a5b) 250 #define SES_PAD_CTRL_MOD_RSTN_CONTROL_ADR (0x8a5c) 251 #define SES_PAD_CTRL_MOD_RSTN_STATUS_ADR (0x8a5d) 252 #define SES_PAD_CTRL_MOD_INTRN_CONTROL_ADR (0x8a5e) 253 #define SES_PAD_CTRL_MOD_INTRN_STATUS_ADR (0x8a5f) 254 #define SES_PAD_CTRL_MOD_TX_DIS_LOPWR2_CONTROL_ADR (0x8a60) 255 #define SES_PAD_CTRL_MOD_TX_DIS_LOPWR2_STATUS_ADR (0x8a61) 256 #define SES_PAD_CTRL_MOD_RX_LOS_ABS2_CONTROL_ADR (0x8a62) 257 #define SES_PAD_CTRL_MOD_RX_LOS_ABS2_STATUS_ADR (0x8a63) 258 #define SES_PAD_CTRL_GPIO_0_CONTROL_ADR (0x8a64) 259 #define SES_PAD_CTRL_GPIO_0_STATUS_ADR (0x8a65) 260 #define SES_PAD_CTRL_GPIO_1_CONTROL_ADR (0x8a66) 261 #define SES_PAD_CTRL_GPIO_1_STATUS_ADR (0x8a67) 262 #define SES_PAD_CTRL_GPIO_2_CONTROL_ADR (0x8a68) 263 #define SES_PAD_CTRL_GPIO_2_STATUS_ADR (0x8a69) 264 #define SES_PAD_CTRL_GPIO_3_CONTROL_ADR (0x8a6a) 265 #define SES_PAD_CTRL_GPIO_3_STATUS_ADR (0x8a6b) 266 267 /*-----------------------------------------------*/ 268 /* Defines for CL91_USER_RX Bank */ 269 /*-----------------------------------------------*/ 270 #define CL91_USER_RX_BASEADR (0x9400) 271 #define CL91_USER_RX_STATUS_ADR (0x9400) 272 #define CL91_USER_RX_LATCHED_STATUS_ADR (0x9401) 273 #define CL91_USER_RX_PHY_LN0_MAPPING_CTRL1_ADR (0x9406) 274 #define CL91_USER_RX_PHY_LN0_MAPPING_CTRL2_ADR (0x9407) 275 #define CL91_USER_RX_PHY_LN0_MAPPING_CTRL3_ADR (0x9408) 276 #define CL91_USER_RX_PHY_LN1_MAPPING_CTRL1_ADR (0x9409) 277 #define CL91_USER_RX_PHY_LN1_MAPPING_CTRL2_ADR (0x940a) 278 #define CL91_USER_RX_PHY_LN1_MAPPING_CTRL3_ADR (0x940b) 279 #define CL91_USER_RX_PHY_LN2_MAPPING_CTRL1_ADR (0x940c) 280 #define CL91_USER_RX_PHY_LN2_MAPPING_CTRL2_ADR (0x940d) 281 #define CL91_USER_RX_PHY_LN2_MAPPING_CTRL3_ADR (0x940e) 282 #define CL91_USER_RX_PHY_LN3_MAPPING_CTRL1_ADR (0x940f) 283 #define CL91_USER_RX_PHY_LN3_MAPPING_CTRL2_ADR (0x9410) 284 #define CL91_USER_RX_PHY_LN3_MAPPING_CTRL3_ADR (0x9411) 285 286 /*-----------------------------------------------*/ 287 /* Defines for CL91_USER_TX Bank */ 288 /*-----------------------------------------------*/ 289 #define CL91_USER_TX_BASEADR (0x9c00) 290 #define CL91_USER_TX_STATUS1_ADR (0x9c01) 291 #define CL91_USER_TX_STATUS2_ADR (0x9c02) 292 #define CL91_USER_TX_STATUS3_ADR (0x9c03) 293 #define CL91_USER_TX_STATUS4_ADR (0x9c04) 294 #define CL91_USER_TX_STATUS5_ADR (0x9c05) 295 #define CL91_USER_TX_LN0_STATUS_ADR (0x9c06) 296 #define CL91_USER_TX_LN1_STATUS_ADR (0x9c07) 297 #define CL91_USER_TX_LN2_STATUS_ADR (0x9c08) 298 #define CL91_USER_TX_LN3_STATUS_ADR (0x9c09) 299 #define CL91_USER_TX_LN4_STATUS_ADR (0x9c0a) 300 #define CL91_USER_TX_LN5_STATUS_ADR (0x9c0b) 301 #define CL91_USER_TX_LN6_STATUS_ADR (0x9c0c) 302 #define CL91_USER_TX_LN7_STATUS_ADR (0x9c0d) 303 #define CL91_USER_TX_LN8_STATUS_ADR (0x9c0e) 304 #define CL91_USER_TX_LN9_STATUS_ADR (0x9c0f) 305 #define CL91_USER_TX_LN10_STATUS_ADR (0x9c10) 306 #define CL91_USER_TX_LN11_STATUS_ADR (0x9c11) 307 #define CL91_USER_TX_LN12_STATUS_ADR (0x9c12) 308 #define CL91_USER_TX_LN13_STATUS_ADR (0x9c13) 309 #define CL91_USER_TX_LN14_STATUS_ADR (0x9c14) 310 #define CL91_USER_TX_LN15_STATUS_ADR (0x9c15) 311 #define CL91_USER_TX_LN16_STATUS_ADR (0x9c16) 312 #define CL91_USER_TX_LN17_STATUS_ADR (0x9c17) 313 #define CL91_USER_TX_LN18_STATUS_ADR (0x9c18) 314 #define CL91_USER_TX_LN19_STATUS_ADR (0x9c19) 315 316 /*-----------------------------------------------*/ 317 /* Defines for RX_ANA_REGS Bank */ 318 /*-----------------------------------------------*/ 319 #define RX_ANA_REGS_BASEADR (0xc0b0) 320 #define RX_ANA_REGS_ANARXCONTROL3_ADR (0xc0ba) 321 322 /*-----------------------------------------------*/ 323 /* Defines for DP Bank */ 324 /*-----------------------------------------------*/ 325 #define DP_BASEADR (0x0000) 326 #define DP_DP_CONTROL0_ADR (0xa100) 327 #define DP_SESTO_MODE_CTRL0_ADR (0xa101) 328 #define DP_SESTO_MODE_CTRL1_ADR (0xa102) 329 #define DP_LANE_RESET_CONTROL0_ADR (0xa103) 330 #define DP_DECODED_MODE_STATUS0_ADR (0xa108) 331 #define DP_DECODED_MODE_STATUS1_ADR (0xa109) 332 #define DP_DEMUX_FEC_RC_CTRL_ADR (0xa10a) 333 #define DP_DEMUX_P0_FIFO_CTRL_ADR (0xa10b) 334 #define DP_DEMUX_P1_FIFO_CTRL_ADR (0xa10c) 335 #define DP_DEMUX_P2_FIFO_CTRL_ADR (0xa10d) 336 #define DP_DEMUX_P3_FIFO_CTRL_ADR (0xa10e) 337 #define DP_MUX_FEC_RC_CTRL_ADR (0xa10f) 338 #define DP_MUX_P0_FIFO_CTRL_ADR (0xa110) 339 #define DP_MUX_P1_FIFO_CTRL_ADR (0xa111) 340 #define DP_MUX_P2_FIFO_CTRL_ADR (0xa112) 341 #define DP_MUX_P3_FIFO_CTRL_ADR (0xa113) 342 #define DP_MUX_P4_FIFO_CTRL_ADR (0xa114) 343 #define DP_MUX_P5_FIFO_CTRL_ADR (0xa115) 344 #define DP_MUX_P6_FIFO_CTRL_ADR (0xa116) 345 #define DP_MUX_P7_FIFO_CTRL_ADR (0xa117) 346 #define DP_MUX_P8_FIFO_CTRL_ADR (0xa118) 347 #define DP_MUX_P9_FIFO_CTRL_ADR (0xa119) 348 #define DP_COMMON_FIFO_CTRL_ADR (0xa11a) 349 #define DP_MUX_FERR_LH_ADR (0xa140) 350 #define DP_DEMUX_FERR_LH_ADR (0xa141) 351 #define DP_MUX_FEC_RC_FERR_LH_ADR (0xa142) 352 #define DP_DEMUX_FEC_RC_FERR_LH_ADR (0xa143) 353 #define DP_MER_AN_LANE_SELECT_ADR (0xa200) 354 #define DP_FAL_AN_LANE_SELECT_ADR (0xa201) 355 #define DP_FAL_MER_LINE_SIDE_RESET_CONTROL1_ADR (0xa208) 356 #define DP_FMON0_MAIN_CONTROL_ADR (0xa220) 357 #define DP_FMON1_MAIN_CONTROL_ADR (0xa221) 358 #define DP_FMON2_MAIN_CONTROL_ADR (0xa222) 359 #define DP_FMON3_MAIN_CONTROL_ADR (0xa223) 360 #define DP_MMON0_MAIN_CONTROL_ADR (0xa224) 361 #define DP_MMON1_MAIN_CONTROL_ADR (0xa225) 362 #define DP_MMON2_MAIN_CONTROL_ADR (0xa226) 363 #define DP_MMON3_MAIN_CONTROL_ADR (0xa227) 364 #define DP_MMON4_MAIN_CONTROL_ADR (0xa228) 365 #define DP_MMON5_MAIN_CONTROL_ADR (0xa229) 366 #define DP_MMON6_MAIN_CONTROL_ADR (0xa22a) 367 #define DP_MMON7_MAIN_CONTROL_ADR (0xa22b) 368 #define DP_MMON8_MAIN_CONTROL_ADR (0xa22c) 369 #define DP_MMON9_MAIN_CONTROL_ADR (0xa22d) 370 #define DP_FMON0_MAIN_STATUS_ADR (0xa274) 371 #define DP_FMON1_MAIN_STATUS_ADR (0xa275) 372 #define DP_FMON2_MAIN_STATUS_ADR (0xa276) 373 #define DP_FMON3_MAIN_STATUS_ADR (0xa277) 374 #define DP_MMON0_MAIN_STATUS_ADR (0xa278) 375 #define DP_MMON1_MAIN_STATUS_ADR (0xa279) 376 #define DP_MMON2_MAIN_STATUS_ADR (0xa27a) 377 #define DP_MMON3_MAIN_STATUS_ADR (0xa27b) 378 #define DP_MMON4_MAIN_STATUS_ADR (0xa27c) 379 #define DP_MMON5_MAIN_STATUS_ADR (0xa27d) 380 #define DP_MMON6_MAIN_STATUS_ADR (0xa27e) 381 #define DP_MMON7_MAIN_STATUS_ADR (0xa27f) 382 #define DP_MMON8_MAIN_STATUS_ADR (0xa280) 383 #define DP_MMON9_MAIN_STATUS_ADR (0xa281) 384 #define DP_FMON0_CL49_BER_STATUS_ADR (0xa282) 385 #define DP_FMON1_CL49_BER_STATUS_ADR (0xa283) 386 #define DP_FMON2_CL49_BER_STATUS_ADR (0xa284) 387 #define DP_FMON3_CL49_BER_STATUS_ADR (0xa285) 388 #define DP_MMON0_CL49_BER_STATUS_ADR (0xa286) 389 #define DP_MMON1_CL49_BER_STATUS_ADR (0xa287) 390 #define DP_MMON2_CL49_BER_STATUS_ADR (0xa288) 391 #define DP_MMON3_CL49_BER_STATUS_ADR (0xa289) 392 #define DP_MMON4_CL49_BER_STATUS_ADR (0xa28a) 393 #define DP_MMON5_CL49_BER_STATUS_ADR (0xa28b) 394 #define DP_MMON6_CL49_BER_STATUS_ADR (0xa28c) 395 #define DP_MMON7_CL49_BER_STATUS_ADR (0xa28d) 396 #define DP_MMON8_CL49_BER_STATUS_ADR (0xa28e) 397 #define DP_MMON9_CL49_BER_STATUS_ADR (0xa28f) 398 #define DP_FMON0_BER_COUNT_MSB_ADR (0xa290) 399 #define DP_FMON1_BER_COUNT_MSB_ADR (0xa291) 400 #define DP_FMON2_BER_COUNT_MSB_ADR (0xa292) 401 #define DP_FMON3_BER_COUNT_MSB_ADR (0xa293) 402 #define DP_MMON0_BER_COUNT_MSB_ADR (0xa294) 403 #define DP_MMON1_BER_COUNT_MSB_ADR (0xa295) 404 #define DP_MMON2_BER_COUNT_MSB_ADR (0xa296) 405 #define DP_MMON3_BER_COUNT_MSB_ADR (0xa297) 406 #define DP_MMON4_BER_COUNT_MSB_ADR (0xa298) 407 #define DP_MMON5_BER_COUNT_MSB_ADR (0xa299) 408 #define DP_MMON6_BER_COUNT_MSB_ADR (0xa29a) 409 #define DP_MMON7_BER_COUNT_MSB_ADR (0xa29b) 410 #define DP_MMON8_BER_COUNT_MSB_ADR (0xa29c) 411 #define DP_MMON9_BER_COUNT_MSB_ADR (0xa29d) 412 #define DP_FMON0_LIVE_STATUS_ADR (0xa29e) 413 #define DP_FMON1_LIVE_STATUS_ADR (0xa29f) 414 #define DP_FMON2_LIVE_STATUS_ADR (0xa2a0) 415 #define DP_FMON3_LIVE_STATUS_ADR (0xa2a1) 416 #define DP_MMON0_LIVE_STATUS_ADR (0xa2a2) 417 #define DP_MMON1_LIVE_STATUS_ADR (0xa2a3) 418 #define DP_MMON2_LIVE_STATUS_ADR (0xa2a4) 419 #define DP_MMON3_LIVE_STATUS_ADR (0xa2a5) 420 #define DP_MMON4_LIVE_STATUS_ADR (0xa2a6) 421 #define DP_MMON5_LIVE_STATUS_ADR (0xa2a7) 422 #define DP_MMON6_LIVE_STATUS_ADR (0xa2a8) 423 #define DP_MMON7_LIVE_STATUS_ADR (0xa2a9) 424 #define DP_MMON8_LIVE_STATUS_ADR (0xa2aa) 425 #define DP_MMON9_LIVE_STATUS_ADR (0xa2ab) 426 #define DP_PCS_MON_RESET_FRC_CONTROL0_ADR (0xa2ac) 427 #define DP_PCS_MON_RESET_FRC_CONTROL1_ADR (0xa2ad) 428 429 /*-----------------------------------------------*/ 430 /* Defines for MRX_TEST Bank */ 431 /*-----------------------------------------------*/ 432 #define MRX_TEST_BASEADR (0x0000) 433 #define MRX_TEST_PATTERN_ADR (0xa914) 434 #define MRX_TEST_CONTROL1_LN0_ADR (0xa915) 435 #define MRX_TEST_CONTROL1_LN1_ADR (0xa916) 436 #define MRX_TEST_CONTROL1_LN2_ADR (0xa917) 437 #define MRX_TEST_CONTROL1_LN3_ADR (0xa918) 438 #define MRX_TEST_CONTROL1_LN4_ADR (0xa919) 439 #define MRX_TEST_CONTROL1_LN5_ADR (0xa91a) 440 #define MRX_TEST_CONTROL1_LN6_ADR (0xa91b) 441 #define MRX_TEST_CONTROL1_LN7_ADR (0xa91c) 442 #define MRX_TEST_CONTROL1_LN8_ADR (0xa91d) 443 #define MRX_TEST_CONTROL1_LN9_ADR (0xa91e) 444 #define MRX_TEST_STATUS1_LN0_ADR (0xa91f) 445 #define MRX_TEST_STATUS1_LN1_ADR (0xa920) 446 #define MRX_TEST_STATUS1_LN2_ADR (0xa921) 447 #define MRX_TEST_STATUS1_LN3_ADR (0xa922) 448 #define MRX_TEST_STATUS1_LN4_ADR (0xa923) 449 #define MRX_TEST_STATUS1_LN5_ADR (0xa924) 450 #define MRX_TEST_STATUS1_LN6_ADR (0xa925) 451 #define MRX_TEST_STATUS1_LN7_ADR (0xa926) 452 #define MRX_TEST_STATUS1_LN8_ADR (0xa927) 453 #define MRX_TEST_STATUS1_LN9_ADR (0xa928) 454 455 /*-----------------------------------------------*/ 456 /* Defines for DRX_TEST Bank */ 457 /*-----------------------------------------------*/ 458 #define DRX_TEST_BASEADR (0x0000) 459 #define DRX_TEST_PATTERN_ADR (0xb900) 460 #define DRX_TEST_CONTROL_LN0_ADR (0xb901) 461 #define DRX_TEST_CONTROL_LN1_ADR (0xb902) 462 #define DRX_TEST_CONTROL_LN2_ADR (0xb903) 463 #define DRX_TEST_CONTROL_LN3_ADR (0xb904) 464 #define DRX_TEST_STATUS_LN0_ADR (0xb905) 465 #define DRX_TEST_STATUS_LN1_ADR (0xb906) 466 #define DRX_TEST_STATUS_LN2_ADR (0xb907) 467 #define DRX_TEST_STATUS_LN3_ADR (0xb908) 468 469 /*-----------------------------------------------*/ 470 /* Defines for MERLIN_IF Bank */ 471 /*-----------------------------------------------*/ 472 #define MERLIN_IF_BASEADR (0xae00) 473 #define MERLIN_IF_CONTROL1_LANE0_ADR (0xae00) 474 #define MERLIN_IF_CONTROL1_LANE1_ADR (0xae01) 475 #define MERLIN_IF_CONTROL1_LANE2_ADR (0xae02) 476 #define MERLIN_IF_CONTROL1_LANE3_ADR (0xae03) 477 #define MERLIN_IF_CONTROL1_LANE4_ADR (0xae04) 478 #define MERLIN_IF_CONTROL1_LANE5_ADR (0xae05) 479 #define MERLIN_IF_CONTROL1_LANE6_ADR (0xae06) 480 #define MERLIN_IF_CONTROL1_LANE7_ADR (0xae07) 481 #define MERLIN_IF_CONTROL1_LANE8_ADR (0xae08) 482 #define MERLIN_IF_CONTROL1_LANE9_ADR (0xae09) 483 #define MERLIN_IF_CONTROL2_LANE0_ADR (0xae10) 484 #define MERLIN_IF_CONTROL2_LANE1_ADR (0xae11) 485 #define MERLIN_IF_CONTROL2_LANE2_ADR (0xae12) 486 #define MERLIN_IF_CONTROL2_LANE3_ADR (0xae13) 487 #define MERLIN_IF_CONTROL2_LANE4_ADR (0xae14) 488 #define MERLIN_IF_CONTROL2_LANE5_ADR (0xae15) 489 #define MERLIN_IF_CONTROL2_LANE6_ADR (0xae16) 490 #define MERLIN_IF_CONTROL2_LANE7_ADR (0xae17) 491 #define MERLIN_IF_CONTROL2_LANE8_ADR (0xae18) 492 #define MERLIN_IF_CONTROL2_LANE9_ADR (0xae19) 493 #define MERLIN_IF_COMMON_CONTROL_ADR (0xae20) 494 #define MERLIN_IF_RESCAL_ADR (0xae21) 495 #define MERLIN_IF_REPEATER_STATUS_LANE0_ADR (0xae22) 496 #define MERLIN_IF_REPEATER_STATUS_LANE1_ADR (0xae23) 497 #define MERLIN_IF_REPEATER_STATUS_LANE2_ADR (0xae24) 498 #define MERLIN_IF_REPEATER_STATUS_LANE3_ADR (0xae25) 499 #define MERLIN_IF_REPEATER_STATUS_LANE4_ADR (0xae26) 500 #define MERLIN_IF_REPEATER_STATUS_LANE5_ADR (0xae27) 501 #define MERLIN_IF_REPEATER_STATUS_LANE6_ADR (0xae28) 502 #define MERLIN_IF_REPEATER_STATUS_LANE7_ADR (0xae29) 503 #define MERLIN_IF_REPEATER_STATUS_LANE8_ADR (0xae30) 504 #define MERLIN_IF_REPEATER_STATUS_LANE9_ADR (0xae31) 505 #define MERLIN_IF_PMD_PLL_LOCK_STATUS_ADR (0xae36) 506 507 /*-----------------------------------------------*/ 508 /* Defines for FALCON_IF Bank */ 509 /*-----------------------------------------------*/ 510 #define FALCON_IF_BASEADR (0xbe00) 511 #define FALCON_IF_CONTROL1_LANE0_ADR (0xbe00) 512 #define FALCON_IF_CONTROL1_LANE1_ADR (0xbe01) 513 #define FALCON_IF_CONTROL1_LANE2_ADR (0xbe02) 514 #define FALCON_IF_CONTROL1_LANE3_ADR (0xbe03) 515 #define FALCON_IF_CONTROL2_LANE0_ADR (0xbe04) 516 #define FALCON_IF_CONTROL2_LANE1_ADR (0xbe05) 517 #define FALCON_IF_CONTROL2_LANE2_ADR (0xbe06) 518 #define FALCON_IF_CONTROL2_LANE3_ADR (0xbe07) 519 #define FALCON_IF_COMMON_CONTROL_ADR (0xbe08) 520 #define FALCON_IF_RESCAL_ADR (0xbe09) 521 #define FALCON_IF_REPEATER_STATUS_LANE0_ADR (0xbe10) 522 #define FALCON_IF_REPEATER_STATUS_LANE1_ADR (0xbe11) 523 #define FALCON_IF_REPEATER_STATUS_LANE2_ADR (0xbe12) 524 #define FALCON_IF_REPEATER_STATUS_LANE3_ADR (0xbe13) 525 #define FALCON_IF_PMD_PLL_STS_ADR (0xbe21) 526 527 /*-----------------------------------------------*/ 528 /* Defines for M10G_SIGDET Bank */ 529 /*-----------------------------------------------*/ 530 #define M10G_SIGDET_BASEADR (0xd0c0) 531 #define M10G_SIGDET_SIGDET_CTRL_1_ADR (0xd0c1) 532 533 /*-----------------------------------------------*/ 534 /* Defines for M10G_CKRST_CTRL Bank */ 535 /*-----------------------------------------------*/ 536 #define M10G_CKRST_CTRL_BASEADR (0xd080) 537 #define M10G_CKRST_CTRL_OSR_MODE_CONTROL_ADR (0xd080) 538 #define M10G_CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL_ADR (0xd081) 539 #define M10G_CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_ADR (0xd082) 540 541 /*-----------------------------------------------*/ 542 /* Defines for M10G_PLL_CAL Bank */ 543 /*-----------------------------------------------*/ 544 #define M10G_PLL_CAL_BASEADR (0xd120) 545 #define M10G_PLL_CAL_PLL_CALSTS_0_ADR (0xd128) 546 547 /*-----------------------------------------------*/ 548 /* Defines for M10G_AMSCOM Bank */ 549 /*-----------------------------------------------*/ 550 #define M10G_AMSCOM_BASEADR (0xd0b0) 551 #define M10G_AMSCOM_PLL_CTRL_3_ADR (0xd0b3) 552 #define M10G_AMSCOM_PLL_CTRL_6_ADR (0xd0b6) 553 #define M10G_AMSCOM_PLL_CTRL_7_ADR (0xd0b7) 554 #define M10G_AMSCOM_PLL_CTRL_8_ADR (0xd0b8) 555 #define M10G_AMSCOM_PLL_CTRL_9_ADR (0xd0b9) 556 557 /*-----------------------------------------------*/ 558 /* Defines for M10G_PATT_GEN Bank */ 559 /*-----------------------------------------------*/ 560 #define M10G_PATT_GEN_BASEADR (0xd100) 561 #define M10G_PATT_GEN_PATT_GEN_SEQ_0_ADR (0xd100) 562 #define M10G_PATT_GEN_PATT_GEN_SEQ_1_ADR (0xd101) 563 #define M10G_PATT_GEN_PATT_GEN_SEQ_2_ADR (0xd102) 564 #define M10G_PATT_GEN_PATT_GEN_SEQ_3_ADR (0xd103) 565 #define M10G_PATT_GEN_PATT_GEN_SEQ_4_ADR (0xd104) 566 #define M10G_PATT_GEN_PATT_GEN_SEQ_5_ADR (0xd105) 567 #define M10G_PATT_GEN_PATT_GEN_SEQ_6_ADR (0xd106) 568 #define M10G_PATT_GEN_PATT_GEN_SEQ_7_ADR (0xd107) 569 #define M10G_PATT_GEN_PATT_GEN_SEQ_8_ADR (0xd108) 570 #define M10G_PATT_GEN_PATT_GEN_SEQ_9_ADR (0xd109) 571 #define M10G_PATT_GEN_PATT_GEN_SEQ_10_ADR (0xd10a) 572 #define M10G_PATT_GEN_PATT_GEN_SEQ_11_ADR (0xd10b) 573 #define M10G_PATT_GEN_PATT_GEN_SEQ_12_ADR (0xd10c) 574 #define M10G_PATT_GEN_PATT_GEN_SEQ_13_ADR (0xd10d) 575 #define M10G_PATT_GEN_PATT_GEN_SEQ_14_ADR (0xd10e) 576 577 /*-----------------------------------------------*/ 578 /* Defines for M10G_TX_FED Bank */ 579 /*-----------------------------------------------*/ 580 #define M10G_TX_FED_BASEADR (0xd110) 581 #define M10G_TX_FED_TXFIR_CONTROL1_ADR (0xd110) 582 #define M10G_TX_FED_TXFIR_CONTROL2_ADR (0xd111) 583 #define M10G_TX_FED_TXFIR_CONTROL3_ADR (0xd112) 584 585 /*-----------------------------------------------*/ 586 /* Defines for M10G_TLB_RX Bank */ 587 /*-----------------------------------------------*/ 588 #define M10G_TLB_RX_BASEADR (0xd0d0) 589 #define M10G_TLB_RX_PRBS_CHK_CONFIG_ADR (0xd0d1) 590 #define M10G_TLB_RX_DIG_LPBK_CONFIG_ADR (0xd0d2) 591 #define M10G_TLB_RX_TLB_RX_MISC_CONFIG_ADR (0xd0d3) 592 #define M10G_TLB_RX_PRBS_CHK_LOCK_STATUS_ADR (0xd0d9) 593 #define M10G_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_ADR (0xd0da) 594 #define M10G_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_ADR (0xd0db) 595 #define M10G_TLB_RX_PMD_RX_LOCK_STATUS_ADR (0xd0dc) 596 597 /*-----------------------------------------------*/ 598 /* Defines for M10G_TLB_TX Bank */ 599 /*-----------------------------------------------*/ 600 #define M10G_TLB_TX_BASEADR (0xd0e0) 601 #define M10G_TLB_TX_PATT_GEN_CONFIG_ADR (0xd0e0) 602 #define M10G_TLB_TX_PRBS_GEN_CONFIG_ADR (0xd0e1) 603 #define M10G_TLB_TX_RMT_LPBK_CONFIG_ADR (0xd0e2) 604 #define M10G_TLB_TX_TLB_TX_MISC_CONFIG_ADR (0xd0e3) 605 606 /*-----------------------------------------------*/ 607 /* Defines for F25G_SIGDET Bank */ 608 /*-----------------------------------------------*/ 609 #define F25G_SIGDET_BASEADR (0xd0e0) 610 #define F25G_SIGDET_SIGDET_CTRL_1_ADR (0xd0e1) 611 612 /*-----------------------------------------------*/ 613 /* Defines for F25G_CKRST_CTRL_RPTR Bank */ 614 /*-----------------------------------------------*/ 615 #define F25G_CKRST_CTRL_RPTR_BASEADR (0xd0b0) 616 #define F25G_CKRST_CTRL_RPTR_OSR_MODE_CONTROL_ADR (0xd0b0) 617 #define F25G_CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_ADR (0xd0b1) 618 #define F25G_CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_ADR (0xd0b2) 619 #define F25G_CKRST_CTRL_RPTR_LN_S_RSTB_CONTROL_ADR (0xd0be) 620 621 /*-----------------------------------------------*/ 622 /* Defines for F25G_PLL_CAL_COM Bank */ 623 /*-----------------------------------------------*/ 624 #define F25G_PLL_CAL_COM_BASEADR (0xd140) 625 #define F25G_PLL_CAL_COM_CTL_5_ADR (0xd145) 626 #define F25G_PLL_CAL_COM_CTL_7_ADR (0xd147) 627 #define F25G_PLL_CAL_COM_CTL_STATUS_0_ADR (0xd148) 628 629 /*-----------------------------------------------*/ 630 /* Defines for F25G_AMS_COM Bank */ 631 /*-----------------------------------------------*/ 632 #define F25G_AMS_COM_BASEADR (0xd110) 633 #define F25G_AMS_COM_PLL_CONTROL_3_ADR (0xd113) 634 635 /*-----------------------------------------------*/ 636 /* Defines for F25G_PATT_GEN_COM Bank */ 637 /*-----------------------------------------------*/ 638 #define F25G_PATT_GEN_COM_BASEADR (0xd120) 639 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_0_ADR (0xd120) 640 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_1_ADR (0xd121) 641 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_2_ADR (0xd122) 642 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_3_ADR (0xd123) 643 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_4_ADR (0xd124) 644 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_5_ADR (0xd125) 645 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_6_ADR (0xd126) 646 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_7_ADR (0xd127) 647 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_8_ADR (0xd128) 648 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_9_ADR (0xd129) 649 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_10_ADR (0xd12a) 650 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_11_ADR (0xd12b) 651 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_12_ADR (0xd12c) 652 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_13_ADR (0xd12d) 653 #define F25G_PATT_GEN_COM_PATT_GEN_SEQ_14_ADR (0xd12e) 654 655 /*-----------------------------------------------*/ 656 /* Defines for F25G_TX_FED Bank */ 657 /*-----------------------------------------------*/ 658 #define F25G_TX_FED_BASEADR (0xd130) 659 #define F25G_TX_FED_TXFIR_CONTROL0_ADR (0xd130) 660 #define F25G_TX_FED_TXFIR_CONTROL1_ADR (0xd131) 661 #define F25G_TX_FED_TXFIR_CONTROL2_ADR (0xd132) 662 663 /*-----------------------------------------------*/ 664 /* Defines for F25G_TLB_RX Bank */ 665 /*-----------------------------------------------*/ 666 #define F25G_TLB_RX_BASEADR (0xd160) 667 #define F25G_TLB_RX_PRBS_CHK_CNT_CONFIG_ADR (0xd160) 668 #define F25G_TLB_RX_PRBS_CHK_CONFIG_ADR (0xd161) 669 #define F25G_TLB_RX_DIG_LPBK_CONFIG_ADR (0xd162) 670 #define F25G_TLB_RX_TLB_RX_MISC_CONFIG_ADR (0xd163) 671 #define F25G_TLB_RX_PRBS_CHK_LOCK_STATUS_ADR (0xd169) 672 #define F25G_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_ADR (0xd16a) 673 #define F25G_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_ADR (0xd16b) 674 #define F25G_TLB_RX_PMD_RX_LOCK_STATUS_ADR (0xd16c) 675 676 /*-----------------------------------------------*/ 677 /* Defines for F25G_TLB_TX Bank */ 678 /*-----------------------------------------------*/ 679 #define F25G_TLB_TX_BASEADR (0xd170) 680 #define F25G_TLB_TX_PATT_GEN_CONFIG_ADR (0xd170) 681 #define F25G_TLB_TX_PRBS_GEN_CONFIG_ADR (0xd171) 682 #define F25G_TLB_TX_RMT_LPBK_CONFIG_ADR (0xd172) 683 #define F25G_TLB_TX_TLB_TX_MISC_CONFIG_ADR (0xd173) 684 685 /*-----------------------------------------------*/ 686 /* Defines for IEEE_AN_BLK0 Bank */ 687 /*-----------------------------------------------*/ 688 #define IEEE_AN_BLK0_BASEADR (0x0000) 689 #define IEEE_AN_BLK0_AN_CONTROL_REGISTER_ADR (0x0000) 690 #define IEEE_AN_BLK0_AN_STATUS_REGISTER_ADR (0x0001) 691 #define IEEE_AN_BLK0_AN_IDENTIFIER_REGISTER_0_ADR (0x0002) 692 #define IEEE_AN_BLK0_AN_IDENTIFIER_REGISTER_1_ADR (0x0003) 693 #define IEEE_AN_BLK0_AN_DEVICES_IN_PACKAGE_1_ADR (0x0005) 694 #define IEEE_AN_BLK0_AN_DEVICES_IN_PACKAGE_2_ADR (0x0006) 695 #define IEEE_AN_BLK0_AN_OUI_ID0_REGISTER_ADR (0x000e) 696 #define IEEE_AN_BLK0_AN_OUI_ID1_REG_ADR (0x000f) 697 698 /*-----------------------------------------------*/ 699 /* Defines for IEEE_AN_BLK1 Bank */ 700 /*-----------------------------------------------*/ 701 #define IEEE_AN_BLK1_BASEADR (0x0010) 702 #define IEEE_AN_BLK1_AN_ADVERTISEMENT_1_REGISTER_ADR (0x0010) 703 #define IEEE_AN_BLK1_AN_ADVERTISEMENT_2_REGISTER_ADR (0x0011) 704 #define IEEE_AN_BLK1_AN_ADVERTISEMENT_3_REGISTER_ADR (0x0012) 705 #define IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_1_REG_ADR (0x0013) 706 #define IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_2_REG_ADR (0x0014) 707 #define IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_3_REG_ADR (0x0015) 708 #define IEEE_AN_BLK1_AN_XNP_TRANSMIT_1_REGISTER_ADR (0x0016) 709 #define IEEE_AN_BLK1_AN_XNP_TRANSMIT_2_REGISTER_ADR (0x0017) 710 #define IEEE_AN_BLK1_AN_XNP_TRANSMIT_3_REGISTER_ADR (0x0018) 711 #define IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_1_REGISTER_ADR (0x0019) 712 #define IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_2_REGISTER_ADR (0x001a) 713 #define IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_3_REGISTER_ADR (0x001b) 714 715 /*-----------------------------------------------*/ 716 /* Defines for IEEE_AN_BLK3 Bank */ 717 /*-----------------------------------------------*/ 718 #define IEEE_AN_BLK3_BASEADR (0x0030) 719 #define IEEE_AN_BLK3_BACKPLANE_ETHERNET_STATUS_REGISTER_ADR (0x0030) 720 #define IEEE_AN_BLK3_EEE_ADV_ADR (0x003c) 721 #define IEEE_AN_BLK3_EEE_LP_ADV_ADR (0x003d) 722 723 /*-----------------------------------------------*/ 724 /* Defines for DEV7_SLICE Bank */ 725 /*-----------------------------------------------*/ 726 #define DEV7_SLICE_BASEADR (0x0000) 727 #define DEV7_SLICE_SLICE_ADR (0x8000) 728 729 #endif /* chip_address_defines__H */