quadra28_cfg_seq.h (28272B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #ifndef __QUADRA28_CFG_SEQ_H__ 11 #define __QUADRA28_CFG_SEQ_H__ 12 13 #include <phymod/phymod.h> 14 #include <phymod/phymod_diagnostics.h> 15 #include "quadra28_types.h" 16 #include "quadra28_serdes/common/srds_api_enum.h" 17 /* 18 * Global Variables 19 */ 20 21 /* 22 * Functions 23 */ 24 25 /* 26 * Functions for Manipulating Chip/Port Cfg Descriptors 27 */ 28 29 /* 30 * Functions 31 */ 32 33 /* 34 * Functions for Manipulating Chip/Port Cfg Descriptors 35 */ 36 37 38 39 #define QUADRA28_IS_DUAL(devid) \ 40 ((devid) == QUADRA28_ID_82071 ||\ 41 (devid) == QUADRA28_ID_82315 \ 42 ) 43 44 #define QUADRA28_IS_QUAD(devid)\ 45 ((devid) == QUADRA28_ID_82071 ||\ 46 (devid) == QUADRA28_ID_82314 ||\ 47 (devid) == QUADRA28_ID_82315 \ 48 ) 49 50 #define QUADRA28_IS_OCTAL(devid)\ 51 ((devid) == QUADRA28_ID_82071 ||\ 52 (devid) == QUADRA28_ID_82070 ||\ 53 (devid) == QUADRA28_ID_82314 ||\ 54 (devid) == QUADRA28_ID_82315 \ 55 ) 56 57 #define QUADRA28_GET_IF_SIDE(_FLAGS, _SIDE) \ 58 { \ 59 if(((_FLAGS >> 31) & 0x1) == 0x1) { \ 60 _SIDE = Q28_INTF_SYS; \ 61 } else { \ 62 _SIDE = Q28_INTF_LINE; \ 63 } \ 64 } 65 66 #define QUADRA28_GET_LOC(_PHY, _SIDE) \ 67 { \ 68 if(_PHY->port_loc == phymodPortLocSys) { \ 69 _SIDE = Q28_INTF_SYS; \ 70 } else { \ 71 _SIDE = Q28_INTF_LINE; \ 72 } \ 73 } 74 75 #define QUADRA28_PMD_ID0 0xae02 76 #define QUADRA28_PMD_ID1 0x5250 77 #define QUADRA28_82780_CHIP_ID 0x82780 78 #define QUADRA28_8278F_CHIP_ID 0x8278F 79 #define QUADRA28_82752_CHIP_ID 0x82752 80 #define QUADRA28_82758_CHIP_ID 0x82758 81 82 #define QUADRA28_NOF_LANES_IN_CORE 4 83 #define QUADRA28_PHY_ALL_LANES 0xf 84 #define DELAY_1_MS_FROM_US 1000 85 #define Q28_ALL_LANE 0xF 86 87 /*FOV registers, Since in RDB there is no bit decription 88 * we are adding register offset as macro*/ 89 #define Q28_TOP_GP_REG0 0xC915 90 #define Q28_TOP_GP_REG1 0xC916 91 #define Q28_FOV_TYPE_N0S1 1 92 #define Q28_FOV_TYPE_N1S0 2 93 94 enum LINE_SELECTION{ 95 Q28_INTF_LINE = 0, 96 Q28_INTF_SYS = 1 97 }; 98 99 #define SIDE_SELECT(pa,r,side){ \ 100 if(Q28_INTF_LINE == side) { \ 101 PHYMOD_IF_ERR_RETURN(BCMI_QUADRA28_READ_SIDE_SELECTIONr(pa,&r)); \ 102 BCMI_QUADRA28_SIDE_SELECTIONr_SIDE_SELf_SET(r,Q28_INTF_LINE); \ 103 PHYMOD_IF_ERR_RETURN(BCMI_QUADRA28_WRITE_SIDE_SELECTIONr(pa,r)); \ 104 } else { \ 105 PHYMOD_IF_ERR_RETURN(BCMI_QUADRA28_READ_SIDE_SELECTIONr(pa,&r)); \ 106 BCMI_QUADRA28_SIDE_SELECTIONr_SIDE_SELf_SET(r,Q28_INTF_SYS); \ 107 PHYMOD_IF_ERR_RETURN(BCMI_QUADRA28_WRITE_SIDE_SELECTIONr(pa,r)); \ 108 } \ 109 } 110 111 #define QUADRA28_EN_BROADCAST(pa,r,enable) { \ 112 PHYMOD_IF_ERR_RETURN( \ 113 READ_MDIO_BROADCAST_CONTROLr(pa,&r)); \ 114 if (1 == enable) { \ 115 BCMI_QUADRA28_MDIO_BROADCAST_CONTROLr_MDIO_MCAST_ENf_SET(r,0); \ 116 BCMI_QUADRA28_MDIO_BROADCAST_CONTROLr_MDIO_BCAST_ENf_SET(r, 1); \ 117 } else { \ 118 BCMI_QUADRA28_MDIO_BROADCAST_CONTROLr_MDIO_BCAST_ENf_SET(r,0); \ 119 } \ 120 PHYMOD_IF_ERR_RETURN(WRITE_MDIO_BROADCAST_CONTROLr(pa, r)); \ 121 } 122 123 #define QUADRA28_ADDRESS_LANE(_pa,r, lane_index) { \ 124 PHYMOD_IF_ERR_RETURN( \ 125 READ_MDIO_BROADCAST_CONTROLr(pa,&r)); \ 126 BCMI_QUADRA28_MDIO_BROADCAST_CONTROLr_MDIO_BCAST_ENf_SET(r,0); \ 127 BCMI_QUADRA28_MDIO_BROADCAST_CONTROLr_MDIO_MCAST_ENf_SET(r,1); \ 128 BCMI_QUADRA28_MDIO_BROADCAST_CONTROLr_MDIO_MULTICAST_PHYADf_SET(r, lane_index); \ 129 PHYMOD_IF_ERR_RETURN(WRITE_MDIO_BROADCAST_CONTROLr(pa, r)); \ 130 } 131 132 #define QUADRA28_IS_PCS_ON(pa,r, status){ \ 133 PHYMOD_IF_ERR_RETURN( \ 134 BCMI_QUADRA28_READ_PCS_STATUS1r(pa,&r)); \ 135 *status = BCMI_QUADRA28_PCS_STATUS1r_GET(r); \ 136 } 137 138 #define QUADRA28_SELECT_SIDE(pa, r, _side) SIDE_SELECT(pa,r,_side) 139 140 #define QUADRA28_RESET_SIDE_BCST_CTRL(pa, r, _side) { \ 141 BCMI_QUADRA28_CONFIG_ACCESSr_t bcast; \ 142 if(Q28_INTF_LINE == _side) { \ 143 SIDE_SELECT(pa,r,Q28_INTF_LINE); \ 144 } else { \ 145 SIDE_SELECT(pa,r,Q28_INTF_SYS); \ 146 } \ 147 PHYMOD_IF_ERR_RETURN(BCMI_QUADRA28_READ_CONFIG_ACCESSr(pa, &bcast)); \ 148 BCMI_QUADRA28_CONFIG_ACCESSr_BROADCAST_ENABLEf_SET(bcast,0); \ 149 PHYMOD_IF_ERR_RETURN(BCMI_QUADRA28_WRITE_CONFIG_ACCESSr(pa, bcast)); \ 150 } 151 152 #define Q28_UNUSED_PARAM(x) (void)(x) 153 154 #define Q28_GET_PMD_MODE(m_acc, pmd_mode) \ 155 { \ 156 phymod_interface_t m_intf; \ 157 phymod_ref_clk_t m_ref_clk; \ 158 uint32_t m_intf_modes; \ 159 PHYMOD_IF_ERR_RETURN ( \ 160 quadra28_get_config_mode(m_acc, &m_intf, &speed, &m_ref_clk, &m_intf_modes)); \ 161 Q28_UNUSED_PARAM(m_intf); \ 162 Q28_UNUSED_PARAM(m_ref_clk); \ 163 Q28_UNUSED_PARAM(m_intf_modes); \ 164 if (speed <= Q28_SPEED_HG11) { \ 165 pmd_mode = Q28_MULTI_PMD; \ 166 } else { \ 167 pmd_mode = Q28_SINGLE_PMD; \ 168 } \ 169 } 170 171 #define Q28_10G_PHY_ID_WORK_AROUND(speed, acc) \ 172 (void)speed; 173 /* if (speed <= Q28_SPEED_HG11) { \ 174 if (acc.lane_mask == 0x2) { \ 175 acc.addr += 1; \ 176 } \ 177 if (acc.lane_mask == 0x4) { \ 178 acc.addr += 2; \ 179 } \ 180 if (acc.lane_mask == 0x8) { \ 181 acc.addr += 3; \ 182 } \ 183 } 184 */ 185 #define Q28_GET_DATAPATH(acc, dp){ \ 186 BCMI_QUADRA28_GENERAL_PURPOSE_3r_t gpreg_3; \ 187 PHYMOD_MEMSET(&gpreg_3, 0, sizeof(BCMI_QUADRA28_GENERAL_PURPOSE_3r_t)); \ 188 PHYMOD_IF_ERR_RETURN(READ_GENERAL_PURPOSE_3r(acc,&gpreg_3)); \ 189 dp = (gpreg_3.v[0] & 0x40) >> 6; \ 190 if (dp == 0) { \ 191 dp = phymodDatapathNormal; \ 192 } else { dp = phymodDatapathUll; } \ 193 } 194 195 #define Q28_BIT(X) (1<<X) 196 #define Q28_GET_SPEED_FROM_REG(reg, speed) \ 197 switch (reg & 0xf) { \ 198 case 1: \ 199 speed = SPEED_1G_OS8; \ 200 break; \ 201 case 2: \ 202 speed = Q28_SPEED_10G; \ 203 break; \ 204 case 3: \ 205 speed = SPEED_1G_OS8P25; \ 206 break; \ 207 case 4: \ 208 speed = Q28_SPEED_40G; \ 209 break; \ 210 case 7: \ 211 speed = Q28_SPEED_42G; \ 212 break; \ 213 case 8: \ 214 speed = Q28_SPEED_11P5G; \ 215 break; \ 216 case 0xc: \ 217 speed = Q28_SPEED_20G; \ 218 break; \ 219 default: \ 220 speed = Q28_SPEED_10G; \ 221 break; \ 222 } 223 224 typedef struct q28_an_ability_s { 225 int fec_ability; 226 int pause_ability; 227 }q28_an_ability_t; 228 229 typedef enum { 230 Q28_NO_PAUSE = 0, 231 Q28_ASYM_PAUSE, 232 Q28_SYMM_PAUSE, 233 Q28_ASYM_SYMM_PAUSE, 234 Q28_AN_PAUSE_COUNT 235 }q28_an_pause_t; 236 237 typedef enum { 238 Q28_CL73_NO_TECH = 0, 239 Q28_CL73_1000BASE_KX = 0x1, 240 Q28_CL73_10GBASE_KX4 = 0x2, 241 Q28_CL73_10GBASE_KR = 0x4, 242 Q28_CL73_40GBASE_KR4 = 0x8, 243 Q28_CL73_40GBASE_CR4 = 0x10, 244 Q28_CL73_100GBASE_CR10 = 0x20, 245 Q28_CL73_100GBASE_KP4 = 0x40, 246 Q28_CL73_100GBASE_KR4 = 0x80, 247 Q28_CL73_100GBASE_CR4 = 0x100 248 }q28_cl73_speed_t; 249 250 #define QUADRA28_I2C_RAM_START_ADDRESS 0x8007 251 #define QUADRA28_I2C_MAX_BYTE 256 252 #define Q28_MAX_BYTES 1 253 typedef enum { 254 Q28_I2C_WRITE = 0, 255 Q28_I2C_READ 256 }q28_i2c_acc_t; 257 258 259 int _quadra28_config_line_interface(const phymod_access_t *pa, uint32_t* reg_val, phymod_interface_t intf, uint32_t speed); 260 int _quadra28_config_sys_interface(const phymod_access_t *pa, uint32_t* reg_val, phymod_interface_t intf); 261 int _quadra28_config_port_speed(uint32_t speed, uint32_t* reg_val, uint16_t* mode_type); 262 int quadra28_rom_dload(const phymod_access_t *pa, uint8_t *new_fw, uint32_t fw_length); 263 int quadra28_firmware_info_get(const phymod_access_t *pa, phymod_core_firmware_info_t *fw_info); 264 /** Get Revision ID 265 * This function retrieves Revision ID from PHY chip 266 * 267 * @param pa Pointer to phymod access structure 268 * 269 * @return rev_id Revision ID retrieved from the chip 270 */ 271 uint16_t _quadra28_get_rev_id(const phymod_access_t *pa); 272 273 /** Get Chip ID 274 * This function retrieves Chip ID from PHY chip 275 * 276 * @param pa Pointer to phymod access structure 277 * 278 * @return chip_id Chip id retrieved from the chip 279 */ 280 uint32_t _quadra28_get_chip_id(const phymod_access_t *pa); 281 282 /** Reset Chip 283 * This function is used to reset entire chip 284 * 285 * @param pa Pointer to phymod access structure 286 * 287 * @return PHYMOD_E_NONE successful function execution 288 */ 289 int _quadra28_chip_reset(const phymod_access_t *pa); 290 291 /** Reset Register 292 * This function is used to perform register reset 293 * 294 * @param pa Pointer to phymod access structure 295 * 296 * @return PHYMOD_E_NONE successful function execution 297 */ 298 int _quadra28_register_rst(const phymod_access_t *pa); 299 300 301 /** Configure PRBS generator 302 * This function is used to configure PRBS generator with user provided 303 * polynomial and invert data information 304 * 305 * @param pa Pointer to phymod access structure 306 * @param flags Flags to prbs config 307 * @param prbs_mode User specified polynomial 308 * 0 - PRBS7 309 * 1 - PRBS9 310 * 2 - PRBS11 311 * 3 - PRBS15 312 * 4 - PRBS23 313 * 5 - PRBS31 314 * 6 - PRBS58 315 * 316 * @param prbs_inv User specified invert data config 317 * 0 - do not invert PRBS data 318 * 1 - invert PRBS data 319 * 320 * @return PHYMOD_E_NONE successful function execution 321 */ 322 /*int quadra28_prbs_config_set(const phymod_access_t *pa, 323 uint32_t flags, 324 enum srds_prbs_polynomial_enum prbs_mode, 325 uint32_t prbs_inv);*/ 326 327 328 /** Enable PRBS generator and PRBS checker 329 * This function is used to enable or disable PRBS generator and PRBS checker 330 * as requested by the user 331 * 332 * @param pa Pointer to phymod access structure 333 * @param flags Flags to prbs config 334 * @param enable Enable or disable as specified by the user 335 * 1 - Enable 336 * 0 - Disable 337 * 338 * @return PHYMOD_E_NONE successful function execution 339 */ 340 int quadra28_prbs_enable_set(const phymod_phy_access_t *pa, uint32_t flags, uint32_t enable); 341 342 /** Get Enable status of PRBS generator and PRBS checker 343 * This function is used to retrieve the enable status of PRBS generator and 344 * PRBS checker 345 * 346 * @param pa Pointer to phymod access structure 347 * @param flags Flags to prbs config 348 * @param *enable Enable or disable read from chip 349 * 1 - Enable 350 * 0 - Disable 351 * 352 * @return PHYMOD_E_NONE successful function execution 353 */ 354 int quadra28_prbs_enable_get(const phymod_phy_access_t *pa, uint32_t flags, uint32_t *enable); 355 356 357 358 /** Get PRBS lock and error status 359 * This function is used to retrieve PRBS lock, loss of lock and error counts 360 * from the chip 361 * 362 * @param pa Pointer to phymod access structure 363 * @param lock_status PRBS lock status denotes PRBS generator and 364 * checker are locked to same polynomial data 365 * @param lock_loss Loss of lock denotes PRBS generator and checker 366 * are not in sync 367 * @param error_count PRBS error count retrieved from chip 368 * 369 * @return PHYMOD_E_NONE successful function execution 370 */ 371 int quadra28_prbs_status_get(const phymod_phy_access_t *pa, 372 uint32_t *lock_status, 373 uint32_t *lock_loss, 374 uint32_t *error_count); 375 376 /** Get lane descriptor 377 * This function is used to retrieve lane descriptor from package lane 378 * 379 * @param chip_id chip id number 380 * @param pa Pointer to phymod access structure 381 * @param pkg_lane Package lane number 382 * 383 * @return pkg_ln_des Lane descriptor structure contains the info 384 * about package lane and die lane mapping 385 */ 386 /*const struct _quadra28_PKG_LANE_CFG_S* _quadra28_pkg_ln_des(uint32_t chip_id, const phymod_access_t *pa, int pkg_lane);*/ 387 388 /** Get link status of PHY 389 * This function is used to retrieve the link status of PHY chip 390 * 391 * @param pa Pointer to phymod access structure 392 * 393 * @param link_status link status of the PHY 394 * 1 - Up 395 * 0 - Down 396 * 397 * @return PHYMOD_E_NONE successful function execution 398 */ 399 int quadra28_chk_phy_link_mode_status(const phymod_access_t *pa, 400 uint32_t *link_status); 401 402 /** Set config mode 403 * This function is used to set the operating mode of the PHY 404 * 405 * @param pa Pointer to phymod access structure 406 * @param intf Interface specified by user 407 * @param speed Speed val as specified by user 408 * @param ref_clk Reference clock frequency to set 409 * the PHY into specified interface 410 * and speed 411 * 412 * @return PHYMOD_E_NONE successful function execution 413 */ 414 int quadra28_set_config_mode(const phymod_phy_access_t *phy, 415 phymod_interface_t intf, 416 uint32_t speed, 417 phymod_ref_clk_t ref_clk, uint32_t datapath, uint16_t retimer); 418 419 /** Get config mode 420 * This function is used to retrieve the operating mode of the PHY 421 * 422 * @param pa Pointer to phymod access structure 423 * @param intf Interface type 424 * @param speed Speed val retrieved from PHY 425 * @param ref_clk Reference clock frequency to set 426 * the PHY into specified interface 427 * and speed 428 * @param interface_modes mode which is currently unused 429 * 430 * @return PHYMOD_E_NONE successful function execution 431 */ 432 int quadra28_get_config_mode(const phymod_access_t *phy, 433 phymod_interface_t *intf, 434 uint32_t *speed, 435 phymod_ref_clk_t *ref_clk, 436 uint32_t *interface_modes); 437 438 /** Configure PRBS generator 439 * This function is used to configure PRBS generator with user provided 440 * polynomial and invert data information 441 * 442 * @param pa Pointer to phymod access structure 443 * @param flags Flags to prbs config 444 * @param prbs_mode User specified polynomial 445 * 0 - PRBS7 446 * 1 - PRBS9 447 * 2 - PRBS11 448 * 3 - PRBS15 449 * 4 - PRBS23 450 * 5 - PRBS31 451 * 6 - PRBS58 452 * 453 * @param prbs_inv User specified invert data config 454 * 0 - do not invert PRBS data 455 * 1 - invert PRBS data 456 * 457 * @return PHYMOD_E_NONE successful function execution 458 */ 459 int quara28_prbs_config_set(const phymod_phy_access_t *pc, 460 uint32_t flags, 461 uint32_t prbs_mode, 462 uint32_t prbs_inv); 463 464 /** Get PRBS generator configuration 465 * This function is used to retrieve PRBS generator configuration from 466 * the chip 467 * 468 * @param pa Pointer to phymod access structure 469 * @param flags Flags for prbs 470 * @param prbs_mode Configured Polynomial retrieved from chip 471 * @param prbs_inv Configured invert data retrieved from chip 472 * 0 - do not invert PRBS data 473 * 1 - invert PRBS data 474 * 475 * @return PHYMOD_E_NONE successful function execution 476 */ 477 int quadra28_prbs_config_get(const phymod_phy_access_t *pa, 478 uint32_t flags, 479 enum srds_prbs_polynomial_enum *prbs_mode, 480 uint32_t *prbs_inv); 481 482 /** Get phymod interface type from pma type 483 * This function is used to retrieve PHYMOD interface type from pma_type 484 * 485 * @param pma_type pma type read from mode register 486 * @param intf PHYMOD interface type 487 * @param speed Speed val 488 * 489 * @return PHYMOD_E_NONE successful function execution 490 */ 491 int _quadra28_get_phymod_interface_type(uint16_t pma_type, 492 phymod_interface_t *intf, 493 uint32_t *speed); 494 495 496 /** PMD lock get 497 * 498 * @param pa Pointer to phymod access structure 499 * @param rx_seq_done RX sew done status 500 * 501 * @return PHYMOD_E_NONE successful function execution 502 */ 503 int quadra28_pmd_lock_get(const phymod_phy_access_t *phy, uint32_t *rx_seq_done); 504 /** Get pma type from interface and speed 505 * This function is used to get the pma type from interface and speed. 506 * This pma type will be programmed to mode register for different PHY modes 507 * 508 * @param intf PHYMOD interface type 509 * @param speed Speed val 510 * 511 * @return pma_typeselection pma type calculated with interface and speed 512 */ 513 uint16_t _quadra28_get_pma_type_selection(phymod_interface_t intf, uint32_t speed); 514 515 516 int quadra28_tx_rx_polarity_set (const phymod_phy_access_t *phy, 517 uint32_t tx_polarity, 518 uint32_t rx_polarity); 519 520 521 int quadra28_tx_rx_polarity_get (const phymod_phy_access_t *phy, 522 uint32_t *tx_polarity, 523 uint32_t *rx_polarity); 524 525 526 int quadra28_link_status(const phymod_phy_access_t *phy, uint32_t *link_status); 527 528 int quadra28_reg_read(const phymod_access_t *pa, uint32_t addr, uint32_t *val); 529 530 int quadra28_reg_write(const phymod_access_t *pa, uint32_t addr, uint32_t val); 531 532 int _quadra28_refclk_set(const phymod_access_t *pa, uint32_t ref_clk) ; 533 534 int quadra28_get_chip_id(const phymod_access_t *pa); 535 536 int quadra28_tx_lane_control_set(const phymod_phy_access_t *phy, 537 phymod_phy_tx_lane_control_t tx_control); 538 539 int quadra28_tx_squelch_get(const phymod_phy_access_t *phy, 540 int *tx_squelch); 541 542 int quadra28_rx_lane_control_set(const phymod_phy_access_t *phy, 543 phymod_phy_rx_lane_control_t rx_control); 544 545 546 int quadra28_rx_squelch_get(const phymod_phy_access_t *phy, int *rx_squelch); 547 548 int quadra28_display_eye_scan(const phymod_phy_access_t *pa); 549 550 int quadra28_ber_proj (const phymod_phy_access_t *pa, const phymod_phy_eyescan_options_t* eyescan_options); 551 552 int _quadra28_phy_status_dump(const phymod_phy_access_t *phy); 553 554 int _quadra28_phy_diagnostics_get(const phymod_phy_access_t *pa, phymod_phy_diagnostics_t* diag); 555 556 int quadra28_soft_reset(const phymod_access_t* pa, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction); 557 558 int _quadra28_phy_reset_set(const phymod_phy_access_t *phy, const phymod_phy_reset_t* reset); 559 560 int _quadra28_phy_reset_get(const phymod_phy_access_t *phy, phymod_phy_reset_t* reset); 561 562 int _quadra28_loopback_set(const phymod_phy_access_t *phy, phymod_loopback_mode_t loopback, uint32_t enable); 563 564 int _quadra28_loopback_get(const phymod_phy_access_t *phy, phymod_loopback_mode_t loopback, uint32_t* enable); 565 566 int _quadra28_phy_power_set(const phymod_phy_access_t* phy, const phymod_phy_power_t* power); 567 568 int _quadra28_phy_power_get(const phymod_phy_access_t* phy, phymod_phy_power_t* power); 569 570 int _quadra28_intf_update_wait_check(const phymod_access_t *pa, uint32_t apps_mode_val, 571 int32_t timeout) ; 572 573 int quadra28_channel_select (const phymod_access_t *pa, uint16_t lane); 574 575 int _quadra28_pll_seq_restart(const phymod_access_t *pa, uint32_t flag, phymod_sequencer_operation_t operation); 576 577 int _quadra28_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx); 578 579 int _quadra28_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx); 580 581 int _quadra28_phy_rx_set(const phymod_phy_access_t* phy, const phymod_rx_t* rx); 582 583 int _quadra28_phy_rx_get(const phymod_phy_access_t* phy, phymod_rx_t* rx); 584 585 int _quadra28_phy_autoneg_ability_set(const phymod_access_t* pa, q28_an_ability_t an_ability); 586 587 588 int _quadra28_phy_autoneg_ability_get(const phymod_access_t* pa, phymod_autoneg_ability_t* an_ability_get_type); 589 590 int _quadra28_phy_autoneg_get(const phymod_access_t* phy, phymod_autoneg_control_t* an, uint32_t* an_done); 591 592 int _quadra28_phy_autoneg_remote_ability_get(const phymod_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type); 593 594 int _quadra28_phy_autoneg_set(const phymod_access_t* pa, const phymod_autoneg_control_t* an); 595 596 int _quadra28_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en); 597 598 int _quadra28_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en); 599 600 int _quadra28_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status); 601 602 int _quadra28_phy_retimer_enable(const phymod_access_t *pa, uint32_t enable); 603 604 int _quadra28_phy_fec_enable_set(const phymod_phy_access_t* phy, uint32_t enable); 605 606 int _quadra28_phy_fec_enable_get(const phymod_phy_access_t* phy, uint32_t* enable); 607 608 int _quadra28_finish_mask_seq(const phymod_access_t *pa); 609 610 int _quadra28_set_datapath(const phymod_access_t *pa, int speed, phymod_datapath_t op_datapath); 611 612 int _quadra28_phy_retimer_enable_get(const phymod_access_t *pa, uint32_t *enable); 613 614 int _quadra28_i2c_read(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, 615 uint32_t no_of_bytes, uint8_t *read_data); 616 617 int _quadra28_i2c_write(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, 618 uint32_t no_of_bytes, const uint8_t *write_data); 619 620 int _quadra28_i2c_rw(const phymod_access_t *pa, uint32_t slv_addr, 621 uint32_t slave_start_addr, uint16_t xfer_cnt, uint8_t acc_type, uint8_t *data); 622 623 int _quadra28_edc_config_set(const phymod_phy_access_t* phy, const phymod_edc_config_t* edc_config); 624 625 int _quadra28_edc_config_get(const phymod_phy_access_t* phy, phymod_edc_config_t* edc_config); 626 627 int quadra28_before_fw_load(const phymod_core_access_t* core, 628 const phymod_core_init_config_t *init_config, uint32_t chip_id); 629 int quadra28_bcast_fw_load(const phymod_core_access_t* core, 630 const phymod_core_init_config_t *init_config, 631 uint8_t *new_fw, 632 uint32_t fw_length); 633 634 int quadra28_bcast_after_fw_load(const phymod_core_access_t* core, uint32_t chip_id); 635 int quadra28_bcast_disable(const phymod_core_access_t* core, uint32_t chip_id); 636 637 int _quadra28_failover_mode_set(const phymod_phy_access_t* phy, phymod_failover_mode_t failover_mode); 638 639 int _quadra28_failover_mode_get(const phymod_phy_access_t* phy, phymod_failover_mode_t* failover_mode); 640 641 int _quadra28_clear_mode_config(phymod_access_t *pa); 642 643 int _quadra28_phy_rx_adaptation_resume(const phymod_phy_access_t *phy); 644 645 int _quadra28_phy_gpio_config_set(const phymod_phy_access_t* phy, int pin_no, phymod_gpio_mode_t gpio_mode); 646 647 int _quadra28_phy_gpio_config_get(const phymod_phy_access_t* phy, int pin_no, phymod_gpio_mode_t* gpio_mode); 648 649 /*Set/Get the output/input value of a PHY GPIO pin*/ 650 int _quadra28_phy_gpio_pin_value_set(const phymod_phy_access_t* phy, int pin_no, int value); 651 652 int _quadra28_phy_gpio_pin_value_get(const phymod_phy_access_t* phy, int pin_no, int* value); 653 654 #endif /*__QUADRA28_CFG_SEQ_H__*/ 655