qmod16_diagnostics.c (48321B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 #ifndef _DV_TB_ 8 #define _SDK_QMOD16_ 1 9 #endif 10 11 #ifdef _DV_TB_ 12 #include "qmod16_phyreg.h" 13 #include <stdint.h> 14 #include "qmod16_main.h" 15 #include "qmod16_enum_defines.h" 16 #include "qmod16.h" 17 #include "qmod16_defines.h" 18 #include "qmod16_phyreg.h" 19 #include "qe16PCSRegEnums.h" 20 #include "phy_tsc_iblk.h" 21 #endif 22 23 #ifdef _SDK_QMOD16_ 24 #include "phy_tsc_iblk.h" 25 #include <phymod/phymod.h> 26 #include <phymod/phymod_system.h> 27 #include <phymod/phymod_util.h> 28 #include <phymod/phymod_debug.h> 29 #include <phymod/chip/bcmi_qtce16_xgxs_defs.h> 30 #include "qmod16_enum_defines.h" 31 #include "qmod16.h" 32 #include "qmod16_device.h" 33 #include "qmod16_sc_lkup_table.h" 34 #include "qe16PCSRegEnums.h" 35 #endif 36 37 #define _TRGO_(a,l) PHYMOD_DEBUG_ERROR(("<< PHY_TRG: Adr:%06d Ln:%02d\n",a,l)); 38 #define _TRGC_(a,l) PHYMOD_DEBUG_ERROR((">> PHY TRG: Adr:%06d Ln:%02d\n",a,l)); 39 #ifndef PHYMOD_ST 40 #ifdef _SDK_QMOD16_ 41 #define PHYMOD_ST phymod_access_t 42 #define _TRG_OPN(a) _TRGO_(a->addr, a->lane_mask) 43 #define _TRG_CLS(a) _TRGC_(a->addr, a->lane_mask) 44 #endif /*_SDK_QMOD16_ */ 45 #endif /* PHYMOD_ST */ 46 47 #ifdef _DV_TB_ 48 #define PHYMOD_ST qmod16_st 49 #define _TRG_OPN(a) _TRGO_(a->prt_ad, a->this_lane) 50 #define _TRG_CLS(a) _TRGC_(a->prt_ad, a->this_lane) 51 #endif 52 53 int qmod16_diag_link(PHYMOD_ST *ws); 54 int qmod16_diag_st(PHYMOD_ST *ws, int resolved_speed); 55 56 /** 57 @brief Field OVR diagnostic function 58 @param pc handle to current TSCE context (#PHYMOD_ST) 59 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 60 @details Field OVR Details 61 Check if the field OVR is set, and if OVR enabled, print the OVR value 62 */ 63 64 int qmod16_diag_field_or(PHYMOD_ST *ws) 65 { 66 return PHYMOD_E_NONE; 67 } 68 69 /** 70 @brief pmd pcs lane cfg diagnostic function 71 @param pc handle to current TSCE context (#PHYMOD_ST) 72 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 73 @details Get the uc controls for pmd lane cfg 74 Read the pcs_lane_cfg information from uc RAM. To check if the pmd is to be 75 programmed from pcs lane cfg. 76 */ 77 int qmod16_diag_pmd_pcs_lane_cfg(PHYMOD_ST *ws, int lane) 78 { 79 return PHYMOD_E_NONE ; 80 } /* qmod16_diag_pmd_pcs_lane_cfg */ 81 82 STATIC 83 int qmod16_an_hcd_spd_get (uint16_t spd, char *mystr, int len) 84 { 85 char *an_spd = "UNDEF"; 86 87 if (spd == 1) an_spd ="10M"; 88 if (spd == 2) an_spd ="100M"; 89 if (spd == 3) an_spd ="1000M"; 90 if (spd == 5) an_spd ="1G_KX1"; 91 if (spd == 6) an_spd ="2p5G_X1"; 92 93 PHYMOD_STRNCPY(mystr, an_spd, len); 94 95 return PHYMOD_E_NONE; 96 } 97 98 STATIC 99 int qmod16_an_local_spd_get (uint16_t spd, char *mystr, int len) 100 { 101 char *an_spd = "RESERVE"; 102 103 if (spd == 0) an_spd ="10Mb/s"; 104 if (spd == 1) an_spd ="100Mb/s"; 105 if (spd == 2) an_spd ="1Gb/s"; 106 if (spd == 4) an_spd ="2.5Gb/s"; 107 108 PHYMOD_STRNCPY(mystr, an_spd, len); 109 110 return PHYMOD_E_NONE; 111 } 112 113 114 115 /** 116 @brief Speed diagnostic function 117 @param pc handle to current TSCE context (#PHYMOD_ST) 118 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 119 @details Speed Details 120 1. Get the Speed set 121 2. Get the Speed valis and Speed Done Status 122 3. Get the final stats of the speed 123 */ 124 int qmod16_diag_speed(PHYMOD_ST *pc) 125 { 126 SC_X4_STSr_t sc_ctrl_status; 127 MAIN_SETUPr_t setup_reg; 128 PLL_CTL8r_t pll_div_reg; 129 RXTXCOM_OSR_MODE_CTLr_t reg_osr_mode; 130 131 SC_X4_FI_SP0_RSLVD_SPDr_t sc_final_sp0_resolved_speed; 132 SC_X4_FI_SP1_RSLVD_SPDr_t sc_final_sp1_resolved_speed; 133 SC_X4_FI_SP2_RSLVD_SPDr_t sc_final_sp2_resolved_speed; 134 SC_X4_FI_SP3_RSLVD_SPDr_t sc_final_sp3_resolved_speed; 135 SC_X4_FI_SP0_RSLVD0r_t sc_final_sp0_resolved_0; 136 SC_X4_FI_SP1_RSLVD0r_t sc_final_sp1_resolved_0; 137 SC_X4_FI_SP2_RSLVD0r_t sc_final_sp2_resolved_0; 138 SC_X4_FI_SP3_RSLVD0r_t sc_final_sp3_resolved_0; 139 140 SC_X4_FI_SP0_RSLVD1r_t sc_final_sp0_resolved_1; 141 SC_X4_FI_SP1_RSLVD1r_t sc_final_sp1_resolved_1; 142 SC_X4_FI_SP2_RSLVD1r_t sc_final_sp2_resolved_1; 143 SC_X4_FI_SP3_RSLVD1r_t sc_final_sp3_resolved_1; 144 145 SC_X4_FI_SP0_RSLVD2r_t sc_final_sp0_resolved_2; 146 SC_X4_FI_SP1_RSLVD2r_t sc_final_sp1_resolved_2; 147 SC_X4_FI_SP2_RSLVD2r_t sc_final_sp2_resolved_2; 148 SC_X4_FI_SP3_RSLVD2r_t sc_final_sp3_resolved_2; 149 150 SC_X4_FI_SP0_RSLVD3r_t sc_final_sp0_resolved_3; 151 SC_X4_FI_SP1_RSLVD3r_t sc_final_sp1_resolved_3; 152 SC_X4_FI_SP2_RSLVD3r_t sc_final_sp2_resolved_3; 153 SC_X4_FI_SP3_RSLVD3r_t sc_final_sp3_resolved_3; 154 155 SC_X4_FI_SP0_RSLVD4r_t sc_final_sp0_resolved_4; 156 SC_X4_FI_SP1_RSLVD4r_t sc_final_sp1_resolved_4; 157 SC_X4_FI_SP2_RSLVD4r_t sc_final_sp2_resolved_4; 158 SC_X4_FI_SP3_RSLVD4r_t sc_final_sp3_resolved_4; 159 160 SC_X4_FI_SP0_RSLVD5r_t sc_final_sp0_resolved_5; 161 SC_X4_FI_SP1_RSLVD5r_t sc_final_sp1_resolved_5; 162 SC_X4_FI_SP2_RSLVD5r_t sc_final_sp2_resolved_5; 163 SC_X4_FI_SP3_RSLVD5r_t sc_final_sp3_resolved_5; 164 165 SC_X4_FI_SP0_RSLVD6r_t sc_final_sp0_resolved_6; 166 SC_X4_FI_SP1_RSLVD6r_t sc_final_sp1_resolved_6; 167 SC_X4_FI_SP2_RSLVD6r_t sc_final_sp2_resolved_6; 168 SC_X4_FI_SP3_RSLVD6r_t sc_final_sp3_resolved_6; 169 170 SC_X4_FI_SP0_RSLVD_SPDr_CLR(sc_final_sp0_resolved_speed); 171 SC_X4_FI_SP1_RSLVD_SPDr_CLR(sc_final_sp1_resolved_speed); 172 SC_X4_FI_SP2_RSLVD_SPDr_CLR(sc_final_sp2_resolved_speed); 173 SC_X4_FI_SP3_RSLVD_SPDr_CLR(sc_final_sp3_resolved_speed); 174 SC_X4_FI_SP0_RSLVD0r_CLR(sc_final_sp0_resolved_0); 175 SC_X4_FI_SP1_RSLVD0r_CLR(sc_final_sp1_resolved_0); 176 SC_X4_FI_SP2_RSLVD0r_CLR(sc_final_sp2_resolved_0); 177 SC_X4_FI_SP3_RSLVD0r_CLR(sc_final_sp3_resolved_0); 178 SC_X4_FI_SP0_RSLVD1r_CLR(sc_final_sp0_resolved_1); 179 SC_X4_FI_SP1_RSLVD1r_CLR(sc_final_sp1_resolved_1); 180 SC_X4_FI_SP2_RSLVD1r_CLR(sc_final_sp2_resolved_1); 181 SC_X4_FI_SP3_RSLVD1r_CLR(sc_final_sp3_resolved_1); 182 SC_X4_FI_SP0_RSLVD2r_CLR(sc_final_sp0_resolved_2); 183 SC_X4_FI_SP1_RSLVD2r_CLR(sc_final_sp1_resolved_2); 184 SC_X4_FI_SP2_RSLVD2r_CLR(sc_final_sp2_resolved_2); 185 SC_X4_FI_SP3_RSLVD2r_CLR(sc_final_sp3_resolved_2); 186 SC_X4_FI_SP0_RSLVD3r_CLR(sc_final_sp0_resolved_3); 187 SC_X4_FI_SP1_RSLVD3r_CLR(sc_final_sp1_resolved_3); 188 SC_X4_FI_SP2_RSLVD3r_CLR(sc_final_sp2_resolved_3); 189 SC_X4_FI_SP3_RSLVD3r_CLR(sc_final_sp3_resolved_3); 190 SC_X4_FI_SP0_RSLVD4r_CLR(sc_final_sp0_resolved_4); 191 SC_X4_FI_SP1_RSLVD4r_CLR(sc_final_sp1_resolved_4); 192 SC_X4_FI_SP2_RSLVD4r_CLR(sc_final_sp2_resolved_4); 193 SC_X4_FI_SP3_RSLVD4r_CLR(sc_final_sp3_resolved_4); 194 SC_X4_FI_SP0_RSLVD5r_CLR(sc_final_sp0_resolved_5); 195 SC_X4_FI_SP1_RSLVD5r_CLR(sc_final_sp1_resolved_5); 196 SC_X4_FI_SP2_RSLVD5r_CLR(sc_final_sp2_resolved_5); 197 SC_X4_FI_SP3_RSLVD5r_CLR(sc_final_sp3_resolved_5); 198 SC_X4_FI_SP0_RSLVD6r_CLR(sc_final_sp0_resolved_6); 199 SC_X4_FI_SP1_RSLVD6r_CLR(sc_final_sp1_resolved_6); 200 SC_X4_FI_SP2_RSLVD6r_CLR(sc_final_sp2_resolved_6); 201 SC_X4_FI_SP3_RSLVD6r_CLR(sc_final_sp3_resolved_6); 202 203 /*1. Get the Speed valid and Speed Done Status */ 204 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc,&sc_ctrl_status)); 205 206 /*2. Get the Speed set */ 207 /*2a PLLDIV and the refclk settings */ 208 PHYMOD_IF_ERR_RETURN(READ_MAIN_SETUPr(pc,&setup_reg)); 209 PHYMOD_IF_ERR_RETURN(READ_PLL_CTL8r(pc,&pll_div_reg)); 210 PHYMOD_IF_ERR_RETURN(READ_RXTXCOM_OSR_MODE_CTLr(pc, ®_osr_mode)); 211 212 /*3. Get the final stats for the speed */ 213 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD0r(pc,&sc_final_sp0_resolved_0)); 214 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD0r(pc,&sc_final_sp1_resolved_0)); 215 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD0r(pc,&sc_final_sp2_resolved_0)); 216 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD0r(pc,&sc_final_sp3_resolved_0)); 217 218 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD1r(pc,&sc_final_sp0_resolved_1)); 219 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD1r(pc,&sc_final_sp1_resolved_1)); 220 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD1r(pc,&sc_final_sp2_resolved_1)); 221 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD1r(pc,&sc_final_sp3_resolved_1)); 222 223 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD2r(pc,&sc_final_sp0_resolved_2)); 224 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD2r(pc,&sc_final_sp1_resolved_2)); 225 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD2r(pc,&sc_final_sp2_resolved_2)); 226 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD2r(pc,&sc_final_sp3_resolved_2)); 227 228 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD3r(pc,&sc_final_sp0_resolved_3)); 229 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD3r(pc,&sc_final_sp1_resolved_3)); 230 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD3r(pc,&sc_final_sp2_resolved_3)); 231 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD3r(pc,&sc_final_sp3_resolved_3)); 232 233 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD4r(pc,&sc_final_sp0_resolved_4)); 234 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD4r(pc,&sc_final_sp1_resolved_4)); 235 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD4r(pc,&sc_final_sp2_resolved_4)); 236 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD4r(pc,&sc_final_sp3_resolved_4)); 237 238 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD5r(pc,&sc_final_sp0_resolved_5)); 239 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD5r(pc,&sc_final_sp1_resolved_5)); 240 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD5r(pc,&sc_final_sp2_resolved_5)); 241 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD5r(pc,&sc_final_sp3_resolved_5)); 242 243 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD6r(pc,&sc_final_sp0_resolved_6)); 244 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD6r(pc,&sc_final_sp1_resolved_6)); 245 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD6r(pc,&sc_final_sp2_resolved_6)); 246 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD6r(pc,&sc_final_sp3_resolved_6)); 247 248 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d SPEED |\n", pc->addr, pc->lane_mask)); 249 PHYMOD_DEBUG_ERROR(("+------------------+-------------------------+----------------------------------+\n")); 250 PHYMOD_DEBUG_ERROR(("| SPEED (LANE) | STATS (SUBPORT) | CREDIT STATS (SUBPORT) |\n")); 251 PHYMOD_DEBUG_ERROR(("+------------------+-------------------------+----------------------------------+\n")); 252 PHYMOD_DEBUG_ERROR(("| SPD CHG VLD : %2d | QSGMII EN : %s %s %s %s | SGMII SPD : %d %d %d %d |\n", 253 SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(sc_ctrl_status), 254 SC_X4_FI_SP3_RSLVD0r_QSGMII_ENf_GET(sc_final_sp3_resolved_0)? "Y" : "N", 255 SC_X4_FI_SP2_RSLVD0r_QSGMII_ENf_GET(sc_final_sp2_resolved_0)? "Y" : "N", 256 SC_X4_FI_SP1_RSLVD0r_QSGMII_ENf_GET(sc_final_sp1_resolved_0)? "Y" : "N", 257 SC_X4_FI_SP0_RSLVD0r_QSGMII_ENf_GET(sc_final_sp0_resolved_0)? "Y" : "N", 258 SC_X4_FI_SP3_RSLVD1r_SGMII_SPD_SWITCHf_GET(sc_final_sp3_resolved_1), 259 SC_X4_FI_SP2_RSLVD1r_SGMII_SPD_SWITCHf_GET(sc_final_sp2_resolved_1), 260 SC_X4_FI_SP1_RSLVD1r_SGMII_SPD_SWITCHf_GET(sc_final_sp1_resolved_1), 261 SC_X4_FI_SP0_RSLVD1r_SGMII_SPD_SWITCHf_GET(sc_final_sp0_resolved_1))); 262 263 PHYMOD_DEBUG_ERROR(("| SPD CHG DONE: %2d | DEL MODE : %02d %02d %02d %02d | CLK CNT0 : %04d %04d %04d %04d |\n", 264 SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(sc_ctrl_status), 265 SC_X4_FI_SP3_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp3_resolved_0), 266 SC_X4_FI_SP2_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp2_resolved_0), 267 SC_X4_FI_SP1_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp1_resolved_0), 268 SC_X4_FI_SP0_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp0_resolved_0), 269 SC_X4_FI_SP3_RSLVD1r_CLOCKCNT0f_GET(sc_final_sp3_resolved_1), 270 SC_X4_FI_SP2_RSLVD1r_CLOCKCNT0f_GET(sc_final_sp2_resolved_1), 271 SC_X4_FI_SP1_RSLVD1r_CLOCKCNT0f_GET(sc_final_sp1_resolved_1), 272 SC_X4_FI_SP0_RSLVD1r_CLOCKCNT0f_GET(sc_final_sp0_resolved_1))); 273 274 PHYMOD_DEBUG_ERROR(("| REF CLOCK : %2d | SPD RSLVD : %02d %02d %02d %02d | CLK CNT1 : %04d %04d %04d %04d |\n", 275 MAIN_SETUPr_REFCLK_SELf_GET(setup_reg), 276 SC_X4_FI_SP3_RSLVD_SPDr_SPEEDf_GET(sc_final_sp3_resolved_speed), 277 SC_X4_FI_SP2_RSLVD_SPDr_SPEEDf_GET(sc_final_sp2_resolved_speed), 278 SC_X4_FI_SP1_RSLVD_SPDr_SPEEDf_GET(sc_final_sp1_resolved_speed), 279 SC_X4_FI_SP0_RSLVD_SPDr_SPEEDf_GET(sc_final_sp0_resolved_speed), 280 SC_X4_FI_SP3_RSLVD2r_CLOCKCNT1f_GET(sc_final_sp3_resolved_2), 281 SC_X4_FI_SP2_RSLVD2r_CLOCKCNT1f_GET(sc_final_sp2_resolved_2), 282 SC_X4_FI_SP1_RSLVD2r_CLOCKCNT1f_GET(sc_final_sp1_resolved_2), 283 SC_X4_FI_SP0_RSLVD2r_CLOCKCNT1f_GET(sc_final_sp0_resolved_2))); 284 285 PHYMOD_DEBUG_ERROR(("| PLL DIV : %2d | | LP CNT0 : %04d %04d %04d %04d |\n", 286 PLL_CTL8r_I_NDIV_INTf_GET(pll_div_reg), 287 SC_X4_FI_SP3_RSLVD3r_LOOPCNT0f_GET(sc_final_sp3_resolved_3), 288 SC_X4_FI_SP2_RSLVD3r_LOOPCNT0f_GET(sc_final_sp2_resolved_3), 289 SC_X4_FI_SP1_RSLVD3r_LOOPCNT0f_GET(sc_final_sp1_resolved_3), 290 SC_X4_FI_SP0_RSLVD3r_LOOPCNT0f_GET(sc_final_sp0_resolved_3))); 291 292 PHYMOD_DEBUG_ERROR(("| OS MODE : %2s | | LP CNT1 : %04d %04d %04d %04d |\n", 293 e2s_qmod16_os_mode_type[RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_GET(reg_osr_mode)]+19, 294 SC_X4_FI_SP3_RSLVD3r_LOOPCNT1f_GET(sc_final_sp3_resolved_3), 295 SC_X4_FI_SP2_RSLVD3r_LOOPCNT1f_GET(sc_final_sp2_resolved_3), 296 SC_X4_FI_SP1_RSLVD3r_LOOPCNT1f_GET(sc_final_sp1_resolved_3), 297 SC_X4_FI_SP0_RSLVD3r_LOOPCNT1f_GET(sc_final_sp0_resolved_3))); 298 299 300 PHYMOD_DEBUG_ERROR(("| | MAC CGC : %04d %04d %04d %04d |\n", 301 SC_X4_FI_SP3_RSLVD4r_MAC_CREDITGENCNTf_GET(sc_final_sp3_resolved_4), 302 SC_X4_FI_SP2_RSLVD4r_MAC_CREDITGENCNTf_GET(sc_final_sp2_resolved_4), 303 SC_X4_FI_SP1_RSLVD4r_MAC_CREDITGENCNTf_GET(sc_final_sp1_resolved_4), 304 SC_X4_FI_SP0_RSLVD4r_MAC_CREDITGENCNTf_GET(sc_final_sp0_resolved_4))); 305 306 PHYMOD_DEBUG_ERROR(("| | REP: %d%d%d%d | PCS CRD EN : %d%d%d%d |\n", 307 SC_X4_FI_SP3_RSLVD5r_REPLICATION_CNTf_GET(sc_final_sp3_resolved_5), 308 SC_X4_FI_SP2_RSLVD5r_REPLICATION_CNTf_GET(sc_final_sp2_resolved_5), 309 SC_X4_FI_SP1_RSLVD5r_REPLICATION_CNTf_GET(sc_final_sp1_resolved_5), 310 SC_X4_FI_SP0_RSLVD5r_REPLICATION_CNTf_GET(sc_final_sp0_resolved_5), 311 SC_X4_FI_SP3_RSLVD5r_PCS_CREDITENABLEf_GET(sc_final_sp3_resolved_5), 312 SC_X4_FI_SP2_RSLVD5r_PCS_CREDITENABLEf_GET(sc_final_sp2_resolved_5), 313 SC_X4_FI_SP1_RSLVD5r_PCS_CREDITENABLEf_GET(sc_final_sp1_resolved_5), 314 SC_X4_FI_SP0_RSLVD5r_PCS_CREDITENABLEf_GET(sc_final_sp0_resolved_5))); 315 316 PHYMOD_DEBUG_ERROR(("| | PCS CK CNT : %04d %04d %04d %04d |\n", 317 SC_X4_FI_SP3_RSLVD5r_PCS_CLOCKCNT0f_GET(sc_final_sp3_resolved_5), 318 SC_X4_FI_SP2_RSLVD5r_PCS_CLOCKCNT0f_GET(sc_final_sp2_resolved_5), 319 SC_X4_FI_SP1_RSLVD5r_PCS_CLOCKCNT0f_GET(sc_final_sp1_resolved_5), 320 SC_X4_FI_SP0_RSLVD5r_PCS_CLOCKCNT0f_GET(sc_final_sp0_resolved_5))); 321 322 PHYMOD_DEBUG_ERROR(("| | CRDGEN CNT : %04d %04d %04d %04d |\n", 323 SC_X4_FI_SP3_RSLVD6r_PCS_CREDITGENCNTf_GET(sc_final_sp3_resolved_6), 324 SC_X4_FI_SP2_RSLVD6r_PCS_CREDITGENCNTf_GET(sc_final_sp2_resolved_6), 325 SC_X4_FI_SP1_RSLVD6r_PCS_CREDITGENCNTf_GET(sc_final_sp1_resolved_6), 326 SC_X4_FI_SP0_RSLVD6r_PCS_CREDITGENCNTf_GET(sc_final_sp0_resolved_6))); 327 328 PHYMOD_DEBUG_ERROR(("+------------------+-------------------------+----------------------------------+\n")); 329 330 return PHYMOD_E_NONE; 331 } 332 333 334 int qmod16_diag_autoneg_abilities(PHYMOD_ST *pc) 335 { 336 AN_X4_ABI_SP0_ENSr_t sp0_an_ena; 337 AN_X4_ABI_SP1_ENSr_t sp1_an_ena; 338 AN_X4_ABI_SP2_ENSr_t sp2_an_ena; 339 AN_X4_ABI_SP3_ENSr_t sp3_an_ena; 340 341 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t sp0_cl37_base; 342 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t sp1_cl37_base; 343 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t sp2_cl37_base; 344 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t sp3_cl37_base; 345 346 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t sp0_cl37_bam; 347 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t sp1_cl37_bam; 348 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t sp2_cl37_bam; 349 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t sp3_cl37_bam; 350 351 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t sp0_over1g; 352 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t sp1_over1g; 353 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t sp2_over1g; 354 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t sp3_over1g; 355 356 AN_X4_ABI_SP0_CTLSr_t sp0_an_ctrl; 357 AN_X4_ABI_SP1_CTLSr_t sp1_an_ctrl; 358 AN_X4_ABI_SP2_CTLSr_t sp2_an_ctrl; 359 AN_X4_ABI_SP3_CTLSr_t sp3_an_ctrl; 360 361 char sgmii_spd[4][8]; 362 363 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_ENSr(pc, &sp0_an_ena)); 364 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_ENSr(pc, &sp1_an_ena)); 365 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_ENSr(pc, &sp2_an_ena)); 366 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_ENSr(pc, &sp3_an_ena)); 367 368 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, &sp0_cl37_base)); 369 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, &sp1_cl37_base)); 370 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, &sp2_cl37_base)); 371 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, &sp3_cl37_base)); 372 373 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, &sp0_cl37_bam)); 374 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, &sp1_cl37_bam)); 375 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, &sp2_cl37_bam)); 376 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, &sp3_cl37_bam)); 377 378 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, &sp0_over1g)); 379 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, &sp1_over1g)); 380 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, &sp2_over1g)); 381 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, &sp3_over1g)); 382 383 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_CTLSr(pc, &sp0_an_ctrl)); 384 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_CTLSr(pc, &sp1_an_ctrl)); 385 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_CTLSr(pc, &sp2_an_ctrl)); 386 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_CTLSr(pc, &sp3_an_ctrl)); 387 388 PHYMOD_DEBUG_ERROR(("+----------------------------------------+----------------------------------------+\n")); 389 PHYMOD_DEBUG_ERROR(("| ANX4 CTRL: 0x%04X 0x%04X 0x%04X 0x%04X | ANX4 ENS : 0x%04X 0x%04X 0x%04X 0x%04X |\n", 390 AN_X4_ABI_SP3_CTLSr_GET(sp3_an_ctrl), 391 AN_X4_ABI_SP2_CTLSr_GET(sp2_an_ctrl), 392 AN_X4_ABI_SP1_CTLSr_GET(sp1_an_ctrl), 393 AN_X4_ABI_SP0_CTLSr_GET(sp0_an_ctrl), 394 AN_X4_ABI_SP3_ENSr_GET(sp3_an_ena), 395 AN_X4_ABI_SP2_ENSr_GET(sp2_an_ena), 396 AN_X4_ABI_SP1_ENSr_GET(sp1_an_ena), 397 AN_X4_ABI_SP0_ENSr_GET(sp0_an_ena))); 398 399 PHYMOD_DEBUG_ERROR(("| CL37 BASE: 0x%04X 0x%04X 0x%04X 0x%04X | CL37 BAM : 0x%04X 0x%04X 0x%04X 0x%04X |\n", 400 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_GET(sp3_cl37_base), 401 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_GET(sp2_cl37_base), 402 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_GET(sp1_cl37_base), 403 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_GET(sp0_cl37_base), 404 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_GET(sp3_cl37_bam), 405 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_GET(sp2_cl37_bam), 406 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_GET(sp1_cl37_bam), 407 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_GET(sp0_cl37_bam))); 408 409 PHYMOD_DEBUG_ERROR(("| ANX4 OVR0: 0x%04X 0x%04X 0x%04X 0x%04X | |\n", 410 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_GET(sp3_over1g), 411 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_GET(sp2_over1g), 412 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_GET(sp1_over1g), 413 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_GET(sp0_over1g))); 414 415 PHYMOD_DEBUG_ERROR(("+----------------------+-----------------------+-------------------------+\n")); 416 PHYMOD_DEBUG_ERROR(("| CL37 ENA : %d%d%d%d | BAM ENA : %d%d%d%d | SGMII ENA : %d%d%d%d |\n", 417 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(sp3_an_ena), 418 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(sp2_an_ena), 419 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(sp1_an_ena), 420 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(sp0_an_ena), 421 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_GET(sp3_an_ena), 422 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_GET(sp2_an_ena), 423 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_GET(sp1_an_ena), 424 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_GET(sp0_an_ena), 425 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(sp3_an_ena), 426 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(sp2_an_ena), 427 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(sp1_an_ena), 428 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(sp0_an_ena))); 429 430 PHYMOD_DEBUG_ERROR(("| AN RESTART : %d%d%d%d | QSGMII ENA : %d%d%d%d | USXGMII ENA: %d%d%d%d |\n", 431 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_GET(sp3_an_ena), 432 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_GET(sp2_an_ena), 433 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_GET(sp1_an_ena), 434 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_GET(sp0_an_ena), 435 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_GET(sp3_an_ena), 436 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_GET(sp2_an_ena), 437 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_GET(sp1_an_ena), 438 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_GET(sp0_an_ena), 439 AN_X4_ABI_SP3_ENSr_USXGMII_ENf_GET(sp3_an_ena), 440 AN_X4_ABI_SP2_ENSr_USXGMII_ENf_GET(sp2_an_ena), 441 AN_X4_ABI_SP1_ENSr_USXGMII_ENf_GET(sp1_an_ena), 442 AN_X4_ABI_SP0_ENSr_USXGMII_ENf_GET(sp0_an_ena))); 443 444 PHYMOD_DEBUG_ERROR(("| BAM2SGMII ENA : %d%d%d%d | SGMII2CL37 ENA : %d%d%d%d | |\n", 445 AN_X4_ABI_SP3_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(sp3_an_ena), 446 AN_X4_ABI_SP2_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(sp2_an_ena), 447 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(sp1_an_ena), 448 AN_X4_ABI_SP0_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(sp0_an_ena), 449 AN_X4_ABI_SP3_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(sp3_an_ena), 450 AN_X4_ABI_SP2_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(sp2_an_ena), 451 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(sp1_an_ena), 452 AN_X4_ABI_SP0_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(sp0_an_ena))); 453 454 PHYMOD_DEBUG_ERROR(("| FAIL COUNT LIM: %-4d %-4d %-4d %-4d |\n", 455 AN_X4_ABI_SP3_CTLSr_AN_FAIL_COUNT_LIMITf_GET(sp3_an_ctrl), 456 AN_X4_ABI_SP2_CTLSr_AN_FAIL_COUNT_LIMITf_GET(sp2_an_ctrl), 457 AN_X4_ABI_SP1_CTLSr_AN_FAIL_COUNT_LIMITf_GET(sp1_an_ctrl), 458 AN_X4_ABI_SP0_CTLSr_AN_FAIL_COUNT_LIMITf_GET(sp0_an_ctrl))); 459 460 PHYMOD_IF_ERR_RETURN 461 (qmod16_an_local_spd_get(AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(sp0_cl37_base), sgmii_spd[0], sizeof(sgmii_spd[0]))); 462 PHYMOD_IF_ERR_RETURN 463 (qmod16_an_local_spd_get(AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(sp1_cl37_base), sgmii_spd[1], sizeof(sgmii_spd[1]))); 464 PHYMOD_IF_ERR_RETURN 465 (qmod16_an_local_spd_get(AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(sp2_cl37_base), sgmii_spd[2], sizeof(sgmii_spd[2]))); 466 PHYMOD_IF_ERR_RETURN 467 (qmod16_an_local_spd_get(AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(sp3_cl37_base), sgmii_spd[3], sizeof(sgmii_spd[3]))); 468 469 PHYMOD_DEBUG_ERROR(("+---------------- -+-------------------+---------------------------------------+\n")); 470 PHYMOD_DEBUG_ERROR(("| CL37 ABILITIES (SUBPORT) |\n")); 471 PHYMOD_DEBUG_ERROR(("+------------------+-----------------------------------------------------------+\n")); 472 PHYMOD_DEBUG_ERROR(("| SWRST DIS : %d%d%d%d | ANRST DIS : %d%d%d%d |\n", 473 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_GET(sp3_cl37_base), 474 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_GET(sp2_cl37_base), 475 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_GET(sp1_cl37_base), 476 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_GET(sp0_cl37_base), 477 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_GET(sp3_cl37_base), 478 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_GET(sp2_cl37_base), 479 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_GET(sp1_cl37_base), 480 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_GET(sp0_cl37_base))); 481 482 PHYMOD_DEBUG_ERROR(("| LINK STS : %d%d%d%d | NEXT PAGE : %d%d%d%d |\n", 483 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_GET(sp3_cl37_base), 484 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_GET(sp2_cl37_base), 485 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_GET(sp1_cl37_base), 486 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_GET(sp0_cl37_base), 487 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_GET(sp3_cl37_base), 488 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_GET(sp2_cl37_base), 489 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_GET(sp1_cl37_base), 490 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_GET(sp0_cl37_base))); 491 492 PHYMOD_DEBUG_ERROR(("| HALF DUPLX: %d%d%d%d | FULL DUPLEX : %d%d%d%d |\n", 493 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_GET(sp3_cl37_base), 494 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_GET(sp2_cl37_base), 495 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_GET(sp1_cl37_base), 496 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_GET(sp0_cl37_base), 497 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(sp3_cl37_base), 498 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(sp2_cl37_base), 499 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(sp1_cl37_base), 500 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(sp0_cl37_base))); 501 502 PHYMOD_DEBUG_ERROR(("| PAUSE : %d%d%d%d | SGMII MASTER : %d%d%d%d |\n", 503 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(sp3_cl37_base), 504 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(sp2_cl37_base), 505 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(sp1_cl37_base), 506 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_GET(sp0_cl37_base), 507 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(sp3_cl37_base), 508 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(sp2_cl37_base), 509 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(sp1_cl37_base), 510 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(sp0_cl37_base))); 511 512 PHYMOD_DEBUG_ERROR(("| SGMII FDUP: %d%d%d%d | SGMII SPD : %-8s %-8s %-8s %-8s |\n", 513 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(sp3_cl37_base), 514 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(sp2_cl37_base), 515 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(sp1_cl37_base), 516 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(sp0_cl37_base), 517 sgmii_spd[3],sgmii_spd[2], sgmii_spd[1], sgmii_spd[0])); 518 519 return PHYMOD_E_NONE; 520 } 521 522 523 /** 524 @brief Autoneg diagnostic function 525 @param pc handle to current QTCE16 context (#PHYMOD_ST) 526 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 527 @details Autoneg diags 528 1. Get the AN complete status for AN37/73 529 2. Get the resolved HCD 530 3. Get the link up status after AN 531 */ 532 int qmod16_diag_autoneg(PHYMOD_ST *pc) 533 { 534 AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr_t sp0_an_page_seq_status; 535 AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr_t sp1_an_page_seq_status; 536 AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr_t sp2_an_page_seq_status; 537 AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr_t sp3_an_page_seq_status; 538 AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_t sp0_an_hcd_status; 539 AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_t sp1_an_hcd_status; 540 AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_t sp2_an_hcd_status; 541 AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_t sp3_an_hcd_status; 542 AN_X4_SW_SP0_AN_MISC_STSr_t sp0_an_misc_status; 543 AN_X4_SW_SP1_AN_MISC_STSr_t sp1_an_misc_status; 544 AN_X4_SW_SP2_AN_MISC_STSr_t sp2_an_misc_status; 545 AN_X4_SW_SP3_AN_MISC_STSr_t sp3_an_misc_status; 546 char an_spd[4][8]; 547 548 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr(pc, &sp0_an_page_seq_status)); 549 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr(pc, &sp1_an_page_seq_status)); 550 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr(pc, &sp2_an_page_seq_status)); 551 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr(pc, &sp3_an_page_seq_status)); 552 553 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr(pc, &sp0_an_hcd_status)); 554 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr(pc, &sp1_an_hcd_status)); 555 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr(pc, &sp2_an_hcd_status)); 556 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr(pc, &sp3_an_hcd_status)); 557 558 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP0_AN_MISC_STSr(pc, &sp0_an_misc_status)); 559 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP1_AN_MISC_STSr(pc, &sp1_an_misc_status)); 560 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP2_AN_MISC_STSr(pc, &sp2_an_misc_status)); 561 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP3_AN_MISC_STSr(pc, &sp3_an_misc_status)); 562 563 PHYMOD_IF_ERR_RETURN 564 (qmod16_an_hcd_spd_get (AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp0_an_hcd_status), an_spd[0], sizeof(an_spd[0]))); 565 PHYMOD_IF_ERR_RETURN 566 (qmod16_an_hcd_spd_get (AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp1_an_hcd_status), an_spd[1], sizeof(an_spd[1]))); 567 PHYMOD_IF_ERR_RETURN 568 (qmod16_an_hcd_spd_get (AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp2_an_hcd_status), an_spd[2], sizeof(an_spd[2]))); 569 PHYMOD_IF_ERR_RETURN 570 (qmod16_an_hcd_spd_get (AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp3_an_hcd_status), an_spd[3], sizeof(an_spd[3]))); 571 572 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d AUTONEG (SUBPORT) |\n", 573 pc->addr, pc->lane_mask)); 574 PHYMOD_DEBUG_ERROR(("+----------------+-------------+------------------------------+-------------------+\n")); 575 PHYMOD_DEBUG_ERROR(("| AN37 CMPL: %c%c%c%c | AN HCD SPD : %-8s %-8s %-8s %-8s | AN LINK : %s %s %s %s |\n", 576 (AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp3_an_page_seq_status) == 1) ? 'Y' : 'N', 577 (AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp2_an_page_seq_status) == 1) ? 'Y' : 'N', 578 (AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp1_an_page_seq_status) == 1) ? 'Y' : 'N', 579 (AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp0_an_page_seq_status) == 1) ? 'Y' : 'N', 580 an_spd[3], an_spd[2], an_spd[1], an_spd[0], 581 ((AN_X4_SW_SP3_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp3_an_page_seq_status) == 1) && 582 (AN_X4_SW_SP3_AN_MISC_STSr_AN_COMPLETEf_GET(sp3_an_misc_status) == 1))? "UP":"DN", 583 ((AN_X4_SW_SP2_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp2_an_page_seq_status) == 1) && 584 (AN_X4_SW_SP2_AN_MISC_STSr_AN_COMPLETEf_GET(sp2_an_misc_status) == 1))? "UP":"DN", 585 ((AN_X4_SW_SP1_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp1_an_page_seq_status) == 1) && 586 (AN_X4_SW_SP1_AN_MISC_STSr_AN_COMPLETEf_GET(sp1_an_misc_status) == 1))? "UP":"DN", 587 ((AN_X4_SW_SP0_AN_PAGE_SEQUENCER_STSr_AN_ST_CL37_COMPLETEf_GET(sp0_an_page_seq_status) == 1) && 588 (AN_X4_SW_SP0_AN_MISC_STSr_AN_COMPLETEf_GET(sp0_an_misc_status) == 1))? "UP":"DN")); 589 590 PHYMOD_IF_ERR_RETURN 591 (qmod16_diag_autoneg_abilities(pc)); 592 PHYMOD_DEBUG_ERROR(("+-------------------+--------------------+-----------------+-------------------+\n")); 593 594 return PHYMOD_E_NONE; 595 } 596 597 /** 598 @brief Topology diagnostic function. 599 @param pc handle to current TSCE context (#PHYMOD_ST) 600 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 601 @details Get the topology details 602 1. LoopBack 603 a. Remote Loopback - RX loopback 604 i. PCS loopback 605 ii. PMD loopback 606 b. Local loopback/gloop - TX loopback 607 i. PCS loopback 608 ii. PMD loopback 609 2. LaneSwap 610 a. PCS LaneSwap(RX) 611 b. PMD LaneSwap(TX) 612 3. Polarity Inversion 613 a. tx 614 b. rx 615 4. Master PortNum, port mode and single port mode 616 */ 617 int qmod16_diag_topology(PHYMOD_ST *pc) 618 { 619 MAIN_LPBK_CTLr_t pcs_loopback_ctrl; 620 TLB_RX_DIG_LPBK_CFGr_t pmd_loopback_dig; 621 TLB_TX_RMT_LPBK_CFGr_t pmd_loopback_remote; 622 MAIN_LN_SWPr_t pcs_lane_swap; 623 LN_ADDR0r_t pmd_lane_addr_0; 624 LN_ADDR1r_t pmd_lane_addr_1; 625 LN_ADDR2r_t pmd_lane_addr_2; 626 LN_ADDR3r_t pmd_lane_addr_3; 627 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 628 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 629 MAIN_SETUPr_t reg_main0_setup; 630 uint16_t pcs_lcl_lb, pcs_rmt_lb, pmd_dig_lb, pmd_rmt_lb; 631 632 /* Main0 Setup Register */ 633 /*1. Loopback */ 634 PHYMOD_IF_ERR_RETURN(READ_MAIN_LPBK_CTLr(pc, &pcs_loopback_ctrl)); 635 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_DIG_LPBK_CFGr(pc, &pmd_loopback_dig)); 636 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_RMT_LPBK_CFGr(pc, &pmd_loopback_remote)); 637 638 /*2. LaneSwap */ 639 PHYMOD_IF_ERR_RETURN(READ_MAIN_LN_SWPr(pc, &pcs_lane_swap)); 640 PHYMOD_IF_ERR_RETURN(READ_LN_ADDR0r(pc, &pmd_lane_addr_0)); 641 PHYMOD_IF_ERR_RETURN(READ_LN_ADDR1r(pc, &pmd_lane_addr_1)); 642 PHYMOD_IF_ERR_RETURN(READ_LN_ADDR2r(pc, &pmd_lane_addr_2)); 643 PHYMOD_IF_ERR_RETURN(READ_LN_ADDR3r(pc, &pmd_lane_addr_3)); 644 645 /*3.Polarity Inversion */ 646 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_TLB_TX_MISC_CFGr(pc, &tx_pol_inv)); 647 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_TLB_RX_MISC_CFGr(pc, &rx_pol_inv)); 648 649 /* 4. Master PortNum */ 650 PHYMOD_IF_ERR_RETURN(READ_MAIN_SETUPr(pc, ®_main0_setup)); 651 652 /* Print the information here */ 653 pcs_lcl_lb = MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 654 pcs_rmt_lb = MAIN_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(pcs_loopback_ctrl); 655 pmd_dig_lb = TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(pmd_loopback_dig); 656 pmd_rmt_lb = TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(pmd_loopback_remote); 657 658 PHYMOD_DEBUG_ERROR(("\n")); 659 PHYMOD_DEBUG_ERROR(("+---------------------------------------------------------------------+\n")); 660 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d TOPOLOGY (LANE) |\n", pc->addr, pc->lane_mask)); 661 PHYMOD_DEBUG_ERROR(("+-------------------+-----------------------------+-------------------+\n")); 662 PHYMOD_DEBUG_ERROR(("| PCSLCL LPBK: %c%c%c%c | PCS LANE SWAP TX L2P : %d%d%d%d | TX POLARITY : %d |\n", 663 (pcs_lcl_lb & 8) ? 'Y':'N', 664 (pcs_lcl_lb & 4) ? 'Y':'N', 665 (pcs_lcl_lb & 2) ? 'Y':'N', 666 (pcs_lcl_lb & 1) ? 'Y':'N', 667 MAIN_LN_SWPr_LOG3_TO_PHY_TX_LNSWAP_SELf_GET(pcs_lane_swap), 668 MAIN_LN_SWPr_LOG2_TO_PHY_TX_LNSWAP_SELf_GET(pcs_lane_swap), 669 MAIN_LN_SWPr_LOG1_TO_PHY_TX_LNSWAP_SELf_GET(pcs_lane_swap), 670 MAIN_LN_SWPr_LOG0_TO_PHY_TX_LNSWAP_SELf_GET(pcs_lane_swap), 671 TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv))); 672 673 PHYMOD_DEBUG_ERROR(("| PCSRMT LPBK: %c%c%c%c | PCS LANE SWAP RX L2P : %d%d%d%d | RX POLARITY : %d |\n", 674 (pcs_rmt_lb & 8) ? 'Y':'N', 675 (pcs_rmt_lb & 4) ? 'Y':'N', 676 (pcs_rmt_lb & 2) ? 'Y':'N', 677 (pcs_rmt_lb & 1) ? 'Y':'N', 678 MAIN_LN_SWPr_LOG3_TO_PHY_RX_LNSWAP_SELf_GET(pcs_lane_swap), 679 MAIN_LN_SWPr_LOG2_TO_PHY_RX_LNSWAP_SELf_GET(pcs_lane_swap), 680 MAIN_LN_SWPr_LOG1_TO_PHY_RX_LNSWAP_SELf_GET(pcs_lane_swap), 681 MAIN_LN_SWPr_LOG0_TO_PHY_RX_LNSWAP_SELf_GET(pcs_lane_swap), 682 TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv))); 683 684 PHYMOD_DEBUG_ERROR(("| PMDDIG LPBK: %c%c%c%c | PMD LANE TX ADDR : %d%d%d%d | PORT NUM : %d |\n", 685 (pmd_dig_lb & 8) ? 'Y':'N', 686 (pmd_dig_lb & 4) ? 'Y':'N', 687 (pmd_dig_lb & 2) ? 'Y':'N', 688 (pmd_dig_lb & 1) ? 'Y':'N', 689 LN_ADDR3r_TX_LANE_ADDR_3f_GET(pmd_lane_addr_3), 690 LN_ADDR2r_TX_LANE_ADDR_2f_GET(pmd_lane_addr_2), 691 LN_ADDR1r_TX_LANE_ADDR_1f_GET(pmd_lane_addr_1), 692 LN_ADDR0r_TX_LANE_ADDR_0f_GET(pmd_lane_addr_0), 693 MAIN_SETUPr_MASTER_PORT_NUMf_GET(reg_main0_setup))); 694 695 PHYMOD_DEBUG_ERROR(("| PMDREM LPBK: %c%c%c%c | PMD LANE RX ADDR : %d%d%d%d | SNGLMODE : %d |\n", 696 (pmd_rmt_lb & 8) ? 'Y':'N', 697 (pmd_rmt_lb & 4) ? 'Y':'N', 698 (pmd_rmt_lb & 2) ? 'Y':'N', 699 (pmd_rmt_lb & 1) ? 'Y':'N', 700 LN_ADDR3r_RX_LANE_ADDR_3f_GET(pmd_lane_addr_3), 701 LN_ADDR2r_RX_LANE_ADDR_2f_GET(pmd_lane_addr_2), 702 LN_ADDR1r_RX_LANE_ADDR_1f_GET(pmd_lane_addr_1), 703 LN_ADDR0r_RX_LANE_ADDR_0f_GET(pmd_lane_addr_0), 704 MAIN_SETUPr_SINGLE_PORT_MODEf_GET(reg_main0_setup))); 705 706 PHYMOD_DEBUG_ERROR(("+-------------------+----------------------+-----------------------------+\n")); 707 708 return PHYMOD_E_NONE; 709 } 710 711 /** 712 @brief Get the link status 713 @param pc handle to current TSCE context (#PHYMOD_ST) 714 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 715 @details Call all the Diags 716 */ 717 int qmod16_diag_general(PHYMOD_ST *ws) 718 { 719 qmod16_diag_topology(ws); 720 qmod16_diag_link(ws); 721 qmod16_diag_autoneg(ws); 722 qmod16_diag_speed(ws); 723 724 return (PHYMOD_E_NONE); 725 } 726 727 /** 728 @brief Get the link status 729 @param pc handle to current TSCE context (#PHYMOD_ST) 730 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 731 @details Print the link status. 732 1. pmd_live_status 733 a. pll_lock_sts : PMD PLL lock indication 734 2a. pmd_lane_live_status 735 a. signal_detect_sts : The signal detected on the lane 736 b. rx_lock_sts : The recovery clock locked for the rx lane 737 2b. pmd_lane_latched_status 738 3a. pcs_live_status 739 a. sync status : per port: Live Sync Status indicator for cl36, cl48, brcm mode. Comma detect/code sync 740 per lane: Live Block Lock Status indicator for cl49, cl82.Sync bits locked, on the 2 sync bits of the 66 bits(of 64/66 encoding) 741 b. link_status : Link status for that port 742 3b. pcs_latched_status 743 */ 744 int qmod16_diag_link(PHYMOD_ST *pc) 745 { 746 PMD_X1_STSr_t pmd_live_status; 747 PMD_X4_STSr_t pmd_lane_live_status; 748 PMD_X4_LATCH_STSr_t pmd_lane_latched_status[4]; 749 PCS_LIVE_STSr_t pcs_live_status; 750 PCS_LATCH_STSr_t pcs_latched_status; 751 RX_X4_CL49_STS0_PCS_LIVE_STSr_t cl49_live_status; 752 RX_X4_CL49_STS0_PCS_LATCH_STS0r_t cl49_latch_status; 753 phymod_access_t *lpc = (phymod_access_t*)pc; 754 755 int i,rx_lock_sts[4],sig_det_sts[4], this_lane; 756 757 /*1. pmd_live_status */ 758 PHYMOD_IF_ERR_RETURN(READ_PMD_X1_STSr(pc, &pmd_live_status)); 759 760 /*2a. pmd_lane_live_status */ 761 /*2b. pmd_lane_latched_status */ 762 763 this_lane = lpc->lane_mask; 764 for(i=0; i < 4; i++) { 765 lpc->lane_mask = 1<<i; 766 PHYMOD_IF_ERR_RETURN(READ_PMD_X4_STSr(lpc, &pmd_lane_live_status)); 767 sig_det_sts[i] = PMD_X4_STSr_SIGNAL_DETECT_STSf_GET(pmd_lane_live_status); 768 rx_lock_sts[i] = PMD_X4_STSr_RX_LOCK_STSf_GET(pmd_lane_live_status); 769 770 PMD_X4_LATCH_STSr_CLR(pmd_lane_latched_status[i]); 771 PHYMOD_IF_ERR_RETURN(READ_PMD_X4_LATCH_STSr(pc, &pmd_lane_latched_status[i])); 772 } 773 lpc->lane_mask = this_lane; 774 775 /*3a. pcs_live_status */ 776 /*3b. pcs_latched_status */ 777 PHYMOD_IF_ERR_RETURN(READ_PCS_LIVE_STSr(pc, &pcs_live_status)); 778 PHYMOD_IF_ERR_RETURN(READ_PCS_LATCH_STSr(pc, &pcs_latched_status)); 779 PHYMOD_IF_ERR_RETURN(READ_RX_X4_CL49_STS0_PCS_LIVE_STSr(pc, &cl49_live_status)); 780 PHYMOD_IF_ERR_RETURN(READ_RX_X4_CL49_STS0_PCS_LATCH_STS0r(pc, &cl49_latch_status)); 781 782 /* Print the information here */ 783 PHYMOD_DEBUG_ERROR(("| TRG ADR : %06d LANE: %02d LINK STATE | LH | LL |\n", pc->addr, pc->lane_mask)); 784 PHYMOD_DEBUG_ERROR(("+---------LANE----------+----------------SUBPORT----------+---------+--------+\n")); 785 PHYMOD_DEBUG_ERROR(("| PMD PLL LOCK : %c | PCS SYNC : %c%c%c%c | PCS SYNC STAT : %d%d%d%d : %d%d%d%d |\n", 786 (PMD_X1_STSr_PLL_LOCK_STSf_GET(pmd_live_status) == 1) ? 'Y' : 'N', 787 (PCS_LIVE_STSr_SYNC_STATUS_SP3f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 788 (PCS_LIVE_STSr_SYNC_STATUS_SP2f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 789 (PCS_LIVE_STSr_SYNC_STATUS_SP1f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 790 (PCS_LIVE_STSr_SYNC_STATUS_SP0f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 791 PCS_LATCH_STSr_SYNC_STATUS_LH_SP3f_GET(pcs_latched_status), 792 PCS_LATCH_STSr_SYNC_STATUS_LH_SP2f_GET(pcs_latched_status), 793 PCS_LATCH_STSr_SYNC_STATUS_LH_SP1f_GET(pcs_latched_status), 794 PCS_LATCH_STSr_SYNC_STATUS_LH_SP0f_GET(pcs_latched_status), 795 PCS_LATCH_STSr_SYNC_STATUS_LL_SP3f_GET(pcs_latched_status), 796 PCS_LATCH_STSr_SYNC_STATUS_LL_SP2f_GET(pcs_latched_status), 797 PCS_LATCH_STSr_SYNC_STATUS_LL_SP1f_GET(pcs_latched_status), 798 PCS_LATCH_STSr_SYNC_STATUS_LL_SP0f_GET(pcs_latched_status))); 799 800 PHYMOD_DEBUG_ERROR(("| PMD SIG DETECT : %c%c%c%c | PCS LINK : %c%c%c%c | PCS LINK STAT : %d%d%d%d : %d%d%d%d |\n", 801 (sig_det_sts[3] == 1)? 'Y':'N', 802 (sig_det_sts[2] == 1)? 'Y':'N', 803 (sig_det_sts[1] == 1)? 'Y':'N', 804 (sig_det_sts[0] == 1)? 'Y':'N', 805 (PCS_LIVE_STSr_LINK_STATUS_SP3f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 806 (PCS_LIVE_STSr_LINK_STATUS_SP2f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 807 (PCS_LIVE_STSr_LINK_STATUS_SP1f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 808 (PCS_LIVE_STSr_LINK_STATUS_SP0f_GET(pcs_live_status) == 1) ? 'Y' : 'N', 809 PCS_LATCH_STSr_LINK_STATUS_LH_SP3f_GET(pcs_latched_status), 810 PCS_LATCH_STSr_LINK_STATUS_LH_SP2f_GET(pcs_latched_status), 811 PCS_LATCH_STSr_LINK_STATUS_LH_SP1f_GET(pcs_latched_status), 812 PCS_LATCH_STSr_LINK_STATUS_LH_SP0f_GET(pcs_latched_status), 813 PCS_LATCH_STSr_LINK_STATUS_LL_SP3f_GET(pcs_latched_status), 814 PCS_LATCH_STSr_LINK_STATUS_LL_SP2f_GET(pcs_latched_status), 815 PCS_LATCH_STSr_LINK_STATUS_LL_SP1f_GET(pcs_latched_status), 816 PCS_LATCH_STSr_LINK_STATUS_LL_SP0f_GET(pcs_latched_status))); 817 818 /* AM lock status and AM lock latch status is pre lane. Repeat 4 time for 4 subprots */ 819 PHYMOD_DEBUG_ERROR(("| PMD LOCK : %c%c%c%c | AM LOCK : %c%c%c%c | AM LOCK STAT : %d%d%d%d : %d%d%d%d |\n", 820 (rx_lock_sts[3] == 1)? 'Y':'N', 821 (rx_lock_sts[2] == 1)? 'Y':'N', 822 (rx_lock_sts[1] == 1)? 'Y':'N', 823 (rx_lock_sts[0] == 1)? 'Y':'N', 824 RX_X4_CL49_STS0_PCS_LIVE_STSr_AM_LOCKf_GET(cl49_live_status) ? 'Y' : 'N', 825 RX_X4_CL49_STS0_PCS_LIVE_STSr_AM_LOCKf_GET(cl49_live_status) ? 'Y' : 'N', 826 RX_X4_CL49_STS0_PCS_LIVE_STSr_AM_LOCKf_GET(cl49_live_status) ? 'Y' : 'N', 827 RX_X4_CL49_STS0_PCS_LIVE_STSr_AM_LOCKf_GET(cl49_live_status) ? 'Y' : 'N', 828 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LHf_GET(cl49_latch_status), 829 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LHf_GET(cl49_latch_status), 830 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LHf_GET(cl49_latch_status), 831 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LHf_GET(cl49_latch_status), 832 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LLf_GET(cl49_latch_status), 833 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LLf_GET(cl49_latch_status), 834 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LLf_GET(cl49_latch_status), 835 RX_X4_CL49_STS0_PCS_LATCH_STS0r_AM_LOCK_LLf_GET(cl49_latch_status))); 836 837 PHYMOD_DEBUG_ERROR(("| PMD LATCH HI : %d%d%d%d | |\n", 838 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[3]), 839 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[2]), 840 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[1]), 841 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LHf_GET(pmd_lane_latched_status[0]))); 842 843 PHYMOD_DEBUG_ERROR(("| PMD LATCH LO : %d%d%d%d | |\n", 844 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[3]), 845 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[2]), 846 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[1]), 847 PMD_X4_LATCH_STSr_SIGNAL_DETECT_LLf_GET(pmd_lane_latched_status[0]))); 848 849 PHYMOD_DEBUG_ERROR(("| RXLOCK LATCH HI: %d%d%d%d | |\n", 850 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[3]), 851 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[2]), 852 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[1]), 853 PMD_X4_LATCH_STSr_RX_LOCK_LHf_GET(pmd_lane_latched_status[0]))); 854 855 PHYMOD_DEBUG_ERROR(("| RXLOCK LATCH LO: %d%d%d%d | |\n", 856 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[3]), 857 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[2]), 858 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[1]), 859 PMD_X4_LATCH_STSr_RX_LOCK_LLf_GET(pmd_lane_latched_status[0]))); 860 861 PHYMOD_DEBUG_ERROR(("+-----------------------+------------------+---------------------------------+\n")); 862 863 return PHYMOD_E_NONE; 864 } 865 866 867 /** 868 @brief Internal Tfc info (PRTP. vs. PktGen vs. MAC dataetc.). 869 @param pc handle to current TSCE context (#PHYMOD_ST) 870 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_ERROR else. 871 @details Print the Internal Tfc types. 872 */ 873 int qmod16_diag_internal_tfc(PHYMOD_ST *ws) 874 { 875 return PHYMOD_E_NONE; 876 } 877 878 /** 879 @brief Soft Table diagnostic function 880 @param pc handle to current TSCE context (#PHYMOD_ST) 881 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 882 @details ST diags 883 Print the soft table enteries 884 if the resolved_speed is not set, then all the table enteries are displayed 885 */ 886 int qmod16_diag_st(PHYMOD_ST *ws, int resolved_speed) 887 { 888 return PHYMOD_E_NONE; 889 } /*qmod16_diag_st */ 890 891 /** 892 @brief AN Timers diagnostic function 893 @param pc handle to current TSCE context (#PHYMOD_ST) 894 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 895 @details Prints the AN timers 896 */ 897 int qmod16_diag_an_timers(PHYMOD_ST* ws) 898 { 899 return PHYMOD_E_NONE; 900 } 901 902 /** 903 @brief Prints out the debug state register 904 @param pc handle to current TSCE context (#PHYMOD_ST) 905 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 906 @details Prints the debug state regs. 907 */ 908 int qmod16_diag_state(PHYMOD_ST* ws) 909 { 910 return PHYMOD_E_NONE; 911 } 912 913 /** 914 @brief TBD 915 @param pc handle to current TSCE context (#PHYMOD_ST) 916 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 917 @details Misc debug 918 */ 919 int qmod16_diag_debug(PHYMOD_ST* ws) 920 { 921 return PHYMOD_E_NONE; 922 } 923 924 int qmod16_diag_g_rd_ram(PHYMOD_ST *ws, int mode, int lane) 925 { 926 return PHYMOD_E_NONE ; 927 } 928 929 int qmod16_diag_g_rd_uC(PHYMOD_ST *ws, int lane) 930 { 931 return PHYMOD_E_NONE ; 932 } 933 934 int qmod16_diag_g_info(PHYMOD_ST *ws) 935 { 936 return PHYMOD_E_NONE ; 937 } 938 939 int qmod16_diag_ieee(PHYMOD_ST *ws) 940 { 941 return PHYMOD_E_NONE; 942 } 943 944 /*! 945 946 */ 947 int qmod16_diag(PHYMOD_ST *pc, qmod16_diag_type diag_type) 948 { 949 int rv; 950 rv = PHYMOD_E_NONE; 951 952 PHYMOD_DEBUG_ERROR(("+------------------------------------------------------------------------------+\n")); 953 if (diag_type & QMOD16_DIAG_GENERAL) { rv |= qmod16_diag_general(pc); } 954 if (diag_type & QMOD16_DIAG_TOPOLOGY) { rv |= qmod16_diag_topology(pc); } 955 if (diag_type & QMOD16_DIAG_LINK) { rv |= qmod16_diag_link(pc); } 956 if (diag_type & QMOD16_DIAG_SPEED) { rv |= qmod16_diag_speed(pc); } 957 if (diag_type & QMOD16_DIAG_ANEG) { rv |= qmod16_diag_autoneg(pc); } 958 if (diag_type & QMOD16_DIAG_TFC) { rv |= qmod16_diag_internal_tfc(pc); } 959 if (diag_type & QMOD16_DIAG_AN_TIMERS) { rv |= qmod16_diag_an_timers(pc); } 960 if (diag_type & QMOD16_DIAG_STATE) { rv |= qmod16_diag_state(pc); } 961 if (diag_type & QMOD16_DIAG_DEBUG) { rv |= qmod16_diag_debug(pc); } 962 return rv; 963 } 964 965 /*! 966 */ 967 int qmod16_diag_disp(PHYMOD_ST *pc, const char* cmd_str) 968 { 969 qmod16_diag_type type; 970 971 if (!cmd_str) { 972 type = QMOD16_DIAG_GENERAL; 973 } else if (!PHYMOD_STRCMP(cmd_str, "topo")) { 974 type = QMOD16_DIAG_TOPOLOGY; 975 } else if (!PHYMOD_STRCMP(cmd_str, "link")) { 976 type = QMOD16_DIAG_LINK; 977 } else if (!PHYMOD_STRCMP(cmd_str, "speed")) { 978 type = QMOD16_DIAG_SPEED; 979 } else if (!PHYMOD_STRCMP(cmd_str, "aneg")) { 980 type = QMOD16_DIAG_ANEG; 981 } else if (!PHYMOD_STRCMP(cmd_str, "tfc")) { 982 type = QMOD16_DIAG_TFC; 983 } else if (!PHYMOD_STRCMP(cmd_str, "antimers")) { 984 type = QMOD16_DIAG_AN_TIMERS; 985 } else if (!PHYMOD_STRCMP(cmd_str, "state")) { 986 type = QMOD16_DIAG_STATE; 987 } else if (!PHYMOD_STRCMP(cmd_str, "debug")) { 988 type = QMOD16_DIAG_DEBUG; 989 } else { 990 type = QMOD16_DIAG_GENERAL; 991 } 992 return (qmod16_diag(pc, type)); 993 } 994 995 996