qmod16_defines.h (8059B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *---------------------------------------------------------------------- 14 * Description: define enumerators and qmod16_st 15 *----------------------------------------------------------------------*/ 16 17 #ifndef _qmod16_DEFINES_H_ 18 #define _qmod16_DEFINES_H_ 19 20 #include "qmod16_enum_defines.h" 21 22 /*! \struct qmod16_st 23 24 This is the central TSCE context storing information of a single TE. 25 It has multiple sections, each with a set of elementtsc 26 27 \li Address Context: Elements to uniquely access a TSCE 28 29 */ 30 31 typedef struct { 32 #if defined (_DV_TB_) 33 /* ===== BEGIN ===== TSCE port address section */ 34 /*! chip number of the chip where the TSCE resides, defined by MDK/SDK 35 * platforms. It is not user in verilog and customer software platforms. */ 36 int unit; 37 /*! Port no. defined in MDK/SDK platforms. It is not used in verilog and 38 * customer software platforms. */ 39 int port; 40 /*! Port address strap value. Used only in TSCE verif. env. to identify 41 * the TSCE to the station manager */ 42 int prt_ad; 43 #endif 44 /*! lanes to access. Can simultaneously select multiple lanes. */ 45 qmod16_lane_select lane_select; 46 /*! Current lane being processed can be 0, 1, 2 or 3. */ 47 int this_lane; 48 int sub_port; 49 /*! May not need this. Legacy. Ignore lane number implications*/ 50 int adjust_port_mode; 51 /*! Tier1 Features are controlled by adding values to this var. Currently we 52 * manage with 32 bits (int type). If more bits are needed to specify a 53 * feature,more feature control variables will be added or this will be 54 * turned into an array. In general we try to use at most 8 bits per lane. */ 55 int per_lane_control; 56 57 int pcs_gloop; 58 int pmd_gloop; 59 int pcs_rloop; 60 61 int pmd_reset_control; 62 63 int pkt_number; 64 int pkt_size; 65 int ipg_size; 66 67 /*! see doc. on qmod16_spd_intfc_type */ 68 qmod16_spd_intfc_type spd_intf; 69 /*! Serial Bus protocol or PCB */ 70 qmod16_regacc_type regacc_type; 71 /*! combo or independent */ 72 qmod16_port_type port_type; 73 /*! Single copy registers cannot be modified repeatedly. Tier1 init function 74 * access these registers has to do this only once between resets in 75 * independent mode when the same Tier1 is called for multiple lanes. This 76 * sticky bit, remembers if the single copy regs. were already modified. */ 77 int tsc_touched; 78 int tsc_port_touched; 79 int pcs_lane_swap_touched; 80 int pmd_touched; 81 int uc_touched; 82 83 int master_portnum; 84 /*! Lane swap contl variable. The positional values of the 8 nibbles indicate 85 * location of the logical lanes, like so. rx3_rx2_rx1_rx0_tx3_tx2_tx1_tx0. 86 * Default value 0x32103210 indicates no lanes swapped. */ 87 int lane_swap; 88 /*! Address of reg. to access */ 89 int accAddr; 90 /*! Data context. Contains data to write or data that is just read. Also 91 * contains revid after read_revid. */ 92 int accData; 93 /*! Various status of the link. Note check status of one link at a time. */ 94 int diag_type; 95 /*! Autoneg types. */ 96 qmod16_an_type an_type; 97 /*! Autoneg parameter RF */ 98 int an_rf; 99 /*! Autoneg parameter pause */ 100 int an_pause; 101 /*! Autoneg parameter various speeds (bit encoded) */ 102 int an_tech_ability; 103 int an_bam37_ability; 104 /*! Control information the driver prints. If set to zero, only warnings and 105 * errors will be printed. If set to 1, msgs (developers discretion will be 106 * printed) but not register transactions. If set to 2 transactions will be 107 * printed (plus everything else). 108 */ 109 int verbosity; 110 /* last 4 bits are for TSCE state information */ 111 int ctrl_type; 112 /*! for when user wants to provide custom refclk. Will also work for 113 * standard values. The 10ths value of the frequency need not be entered. So 156.1 114 * becomes 156 115 */ 116 int refclk; 117 /*! pll div value is auto computed. But override is provided. */ 118 int plldiv; 119 120 int vga_frzval; 121 int vga_frcfrz; 122 int dfe_frzval; 123 int dfe_frcfrz; 124 int linkup_bert_cnt[4] ; 125 int firmware_mode ; 126 int an_ctl ; 127 int pattern_enable ; 128 int pattern_type ; 129 130 int prbs_inv; 131 int prbs_enable; 132 int prbs_check_mode; 133 int real_check; 134 135 /* SC Table Entry */ 136 int sc_mode; /* choose the override modes to pick the 137 speed fields */ 138 int qsgmii_mode; /* Qsgmii_mode */ 139 int speed; /* Speed */ 140 int subp_speed; /* Set subport speed, needed for qmode*/ 141 int pcs_lane_map_sel; 142 int num_lanes; /* Number of lanes */ 143 144 int pll_mode; /* PLL mode */ 145 146 int t_pma_os_mode; /* T_PMA over-sampling mode */ 147 int t_encode_mode; /* TX Encode mode */ 148 149 int r_dec1_mode; /* R_DEC1 Decode mode */ 150 int r_deskew_mode; /* R_DESKEW mode */ 151 int r_desc2_mode; /* R_DESC2 mode */ 152 int r_desc2_byte_deletion; /* R_DESC2 byte-deletion mode */ 153 int r_dec1_brcm64b66_descr; /* R_DEC1 Descramble mode */ 154 155 int sigdet_filter; /* Signal detect mode */ 156 int blk_sync_mode; /* Block Sync Mode */ 157 int r_reorder_mode; /* R_REORDER mode */ 158 int cl36_en; /* CL36_EN mode */ 159 160 int sgmii; 161 int qsgmii_en; 162 int crd_en; 163 int clkcnt0; 164 int clkcnt1; 165 int lpcnt0; 166 int lpcnt1; 167 int mac_cgc; 168 int pcs_repcnt; 169 int pcs_crdten; 170 int pcs_clkcnt; 171 int pcs_cgc; 172 int uc_active; 173 /*CL37 capabilities*/ 174 int cl37_an_pause; 175 int cl37_an_hd; 176 int cl37_an_fd; 177 int cl37_an_np; 178 int an_tick_override; 179 int an_tick_denominator; 180 int an_tick_numerator; 181 int an_fail_cnt; 182 int an_oui_ctrl; 183 int cl37_sgmii_speed; 184 int cl37_sgmii_duplex; 185 int cl37_sgmii_master_mode; 186 int cl37_bam_code; 187 int cl37_bam_ovr1g_en; 188 int cl37_bam_ovr1g_pgcnt; 189 int cl37_bam_speed; 190 int cl37_bam_to_sgmii_auto_enable; 191 int sgmii_to_cl37_auto_enable; 192 int cl37_bam_en; 193 int cl37_sgmii_en; 194 int cl37_an_en; 195 int cl37_an_restart; 196 int cl37_sw_restart_reset_disable; 197 int cl37_an_disable_reset_disable; 198 int transmit_nonce; 199 int base_selector; 200 int oui_upper_data; 201 int oui_lower_data; 202 int cl37_restart_timer_period; 203 int cl37_ack_timer_period; 204 int cl37_error_timer_period; 205 int cl37_sgmii_timer_period; 206 int link_fail_inhibit_timer_not_cl72_period; 207 int pd_sd_timer_period; 208 int an_ignore_link_timer; 209 int bam_spd_pri_5_0; 210 int bam_spd_pri_11_6; 211 int bam_spd_pri_17_12; 212 int bam_spd_pri_23_18; 213 int bam_spd_pri_29_24; 214 int bam_spd_pri_35_30; 215 int no_of_lanes; 216 int pd_kx_en; 217 int pd_kx4_en; 218 int an_pd_to_cl37_enable; 219 int cl37_high_vco; 220 int single_port_mode; 221 int pd_to_cl37_retry_cnt; 222 int pd_to_cl37_wait_timer; 223 int disable_rf_report; 224 /* NICK */ 225 int linkfailtimer_dis; 226 int linkfailtimerqua_en; 227 int an_good_check_trap; 228 int an_good_trap; 229 int tx_reset_count; 230 int cl37_sync_status_filter; 231 } qmod16_st; 232 233 /* function table */ 234 typedef int (*tier1FuncTable)(qmod16_st* c); 235 236 #endif /* _qmod16_DEFINES_H_ */