qmod16_cfg_seq.c (247029B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * $Copyright: (c) 2017 Broadcom Corporation All Rights Reserved.$ 8 * Broadcom Corporation 9 * Proprietary and Confidential information 10 * All rights reserved 11 * This source file is the property of Broadcom Corporation, and 12 * may not be copied or distributed in any isomorphic form without the 13 * prior written consent of Broadcom Corporation. 14 *--------------------------------------------------------------------- 15 * File : 1mod16_cfg_seq.c 16 * Description: c functions implementing Tier1s for QTCE16 Serdes Driver 17 *---------------------------------------------------------------------*/ 18 19 #ifndef _DV_TB_ 20 #define _SDK_QMOD16_ 1 21 #endif 22 23 #ifdef _DV_TB_ 24 #include <stdint.h> 25 #include "qmod16_main.h" 26 #include "qmod16_defines.h" 27 #include "qe16PCSRegEnums.h" 28 #include "phy_tsc_iblk.h" 29 #include "bcmi_qtc_xgxs_defs.h" 30 #endif /* _DV_TB_ */ 31 32 #ifdef _SDK_QMOD16_ 33 #include "phy_tsc_iblk.h" 34 #include <phymod/phymod.h> 35 #include <phymod/phymod_system.h> 36 #include <phymod/phymod_util.h> 37 #include <phymod/phymod_debug.h> 38 #include <phymod/chip/bcmi_qtce16_xgxs_defs.h> 39 #include "qmod16_enum_defines.h" 40 #include "qmod16.h" 41 #include "qmod16_device.h" 42 #include "qmod16_sc_lkup_table.h" 43 #include "qe16PCSRegEnums.h" 44 #include "merlin16/tier1/merlin16_internal.h" 45 #endif /* _SDK_QMOD16_ */ 46 47 #ifndef PHYMOD_ST 48 #ifdef _SDK_QMOD16_ 49 #define PHYMOD_ST const phymod_access_t 50 #else 51 #define PHYMOD_ST qmod16_st 52 #endif /* _SDK_QMOD16_ */ 53 #endif /* PHYMOD_ST */ 54 55 #ifdef _SDK_QMOD16_ 56 #define QMOD16_DBG_IN_FUNC_INFO(pc) \ 57 PHYMOD_VDBG(QMOD16_DBG_FUNC,pc,("-22%s: Adr:%08x Ln:%02d\n", __func__, pc->addr, pc->lane_mask)) 58 #define QMOD16_DBG_OUT_FUNC_INFO(pc) \ 59 PHYMOD_VDBG(QMOD16_DBG_FUNC,pc,("-22%s: Adr:%08x Ln:%02d\n", __func__, pc->addr, pc->lane_mask)) 60 #endif 61 62 #ifdef _DV_TB_ 63 #define QMOD16_DBG_IN_FUNC_INFO(pc) \ 64 PHYMOD_VDBG(QMOD16_DBG_FUNC, pc, \ 65 ("QMOD16 IN Function : %s Port Add : %d Lane No: %d\n", \ 66 __func__, pc->prt_ad, pc->this_lane)) 67 #define QMOD16_DBG_OUT_FUNC_INFO(pc) \ 68 PHYMOD_VDBG(QMOD16_DBG_FUNC, pc, \ 69 ("QMOD16 OUT of Function : %s Port Add : %d Lane No: %d\n", \ 70 __func__, pc->prt_ad, pc->this_lane)) 71 int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 72 #endif 73 74 static qmod16_sc_pmd_entry_st qmod16_sc_pmd_entry[] = { 75 /*SPD_10M 0*/ { 1, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 76 /*SPD_10M 1*/ { 1, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 77 /*SPD_100M 2*/ { 1, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 78 /*SPD_1000M 3*/ { 1, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 79 /*SPD_1G_CX1 4*/ { 1, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 80 /*SPD_1G_KX1 5*/ { 1, QMOD16_PMA_OS_MODE_8_25, QMOD16_PLL_MODE_DIV_66, 0, 0, 1}, 81 /*SPD_2p5G 6*/ { 1, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 82 /*SPD_5G_X1 7*/ { 1, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_40, 1, 0, 0}, 83 /*SPD_10G_CX4 8*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 84 /*SPD_10G_KX4 9*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 85 /*SPD_10G_X4 10*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 86 /*SPD_13G_X4 11*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_52, 0, 0, 1}, 87 /*SPD_15G_X4 12*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_60, 0, 0, 1}, 88 /*SPD_16G_X4 13*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 1}, 89 /*SPD_20G_CX4 14*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 90 /*SPD_10G_CX2 15*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_40, 0, 0, 1}, 91 /*SPD_10G_X2 16*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_40, 1, 0, 1}, 92 /*SPD_20G_X4 17*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_40, 1, 0, 1}, 93 /*SPD_10p5G_X2 18*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 94 /*SPD_21G_X4 19*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 95 /*SPD_12p7G_X2 20*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 96 /*SPD_25p45G_X4 21*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_42, 1, 0, 0}, 97 /*SPD_15p75G_X2 22*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_52, 1, 0, 0}, 98 /*SPD_31p5G_X4 23*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_52, 1, 0, 0}, 99 /*SPD_31p5G_KR4 24*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_52, 1, 0, 0}, 100 /*SPD_20G_CX2 25*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 101 /*SPD_20G_X2 26*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 102 /*SPD_40G_X4 27*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 103 /*SPD_10G_KR1 28*/ { 0, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 104 /*SPD_10p6_X1 29*/ { 0, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 105 /*SPD_20G_KR2 30*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 106 /*SPD_20G_CR2 31*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 107 /*SPD_21G_X2 32*/ { 2, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 108 /*SPD_40G_KR4 33*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 109 /*SPD_40G_CR4 34*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 110 /*SPD_42G_X4 35*/ { 4, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 111 /*SPD_100G_CR10 36*/ {10, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 112 /*SPD_107G_CR10 37*/ {10, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 113 /*SPD_120G_X12 38*/ {12, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 1, 0, 0}, 114 /*SPD_127G_X12 39*/ {12, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_70, 1, 0, 0}, 115 /*SPD_ILLEGAL 40*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 116 /*SPD_ILLEGAL 41*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 117 /*SPD_ILLEGAL 42*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 118 /*SPD_ILLEGAL 43*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 119 /*SPD_ILLEGAL 44*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 120 /*SPD_ILLEGAL 45*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 121 /*SPD_ILLEGAL 46*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 122 /*SPD_ILLEGAL 47*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 123 /*SPD_ILLEGAL 48*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 124 /*SPD_5G_KR1 49*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 125 /*SPD_10p5G_X4 50*/ { 4, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_42, 0, 0, 0}, 126 /*SPD_ILLEGAL 51*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 127 /*SPD_ILLEGAL 52*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0}, 128 /*SPD_10M_10p3125 53*/ { 1, QMOD16_PMA_OS_MODE_8_25, QMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 129 /*SPD_100M_10p3125 54*/ { 1, QMOD16_PMA_OS_MODE_8_25, QMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 130 /*SPD_1000M_10p3125 55*/ { 1, QMOD16_PMA_OS_MODE_8_25, QMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 131 /*SPD_2p5G_X1_10p3125 56*/ { 1, QMOD16_PMA_OS_MODE_3_3,QMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 132 /*SPEED_10M_X1_10 : 57*/ { 1, QMOD16_PMA_OS_MODE_8, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 133 /*SPEED_100M_X1_10 : 58*/ { 1, QMOD16_PMA_OS_MODE_8, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 134 /*SPEED_1000M_X1_10 : 59*/ { 1, QMOD16_PMA_OS_MODE_8, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 135 /*SPEED_4G_X1_10 : 60*/ { 1, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 136 /*SPEED_4G_X1_10 : 61*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 137 /*SPEED_4G_X1_10 : 62*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 138 /*SPEED_4G_X1_10 : 63*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 139 /*SPEED_4G_X1_10 : 64*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 140 /*SPEED_4G_X1_10 : 65*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 141 /*SPEED_4G_X1_10 : 66*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 142 /*SPEED_4G_X1_10 : 67*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 143 /*SPEED_4G_X1_10 : 68*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 144 /*SPEED_4G_X1_10 : 69*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 145 /*SPEED_4G_X1_10 : 70*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 146 /*SPEED_4G_X1_10 : 71*/ { 0, QMOD16_PMA_OS_MODE_2, QMOD16_PLL_MODE_DIV_64, 0, 0, 0}, 147 /*SPEED_10G_X1_10: 72*/ { 1, QMOD16_PMA_OS_MODE_1, QMOD16_PLL_MODE_DIV_66, 0, 0, 0}, 148 /*SPD_ILLEGAL 73*/ { 0, QMOD16_PMA_OS_MODE_5, QMOD16_PLL_MODE_DIV_40, 0, 0, 0} 149 }; 150 151 int _qmod16_set_port_mode_select(PHYMOD_ST *pc); 152 int _qmod16_configure_sc_speed_configuration(PHYMOD_ST* pc); 153 int _qmod16_init_pcs_fs(PHYMOD_ST* pc); 154 int _qmod16_init_pcs_an(PHYMOD_ST* pc); 155 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 156 157 #ifdef _DV_TB_ 158 int qmod16_set_an_port_mode(PHYMOD_ST* pc); 159 int qmod16_autoneg_set(PHYMOD_ST* pc); 160 int qmod16_set_qport_spd(PHYMOD_ST* pc); 161 int qmod16_autoneg_control(PHYMOD_ST* pc); 162 int qmod16_an_abilities_enables(PHYMOD_ST* pc,int sub_port); 163 int qmod16_an_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port); 164 int qmod16_autoneg_abilities_controls(PHYMOD_ST* pc,int sub_port); 165 int qmod16_autoneg_cl37_base_abilities(PHYMOD_ST* pc,int sub_port); 166 int qmod16_autoneg_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port); 167 int qmod16_autoneg_cl37_bam_over1g_abilities(PHYMOD_ST* pc,int sub_port); 168 int qmod16_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status); 169 int qmod16_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pat, int check_mode); 170 int qmod16_prbs_control(PHYMOD_ST* pc, int prbs_enable); 171 int qmod16_prbs_rx_enable_set(PHYMOD_ST* pc, int enable); 172 int qmod16_prbs_tx_enable_set(PHYMOD_ST* pc, int enable); 173 int qmod16_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data); 174 int qmod16_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode); 175 int qmod16_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data); 176 int qmod16_prbs_tx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial); 177 int qmod16_prbs_rx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial); 178 int qmod16_pmd_lane_swap(PHYMOD_ST *pc); 179 int qmod16_check_sc_stats(PHYMOD_ST* pc); 180 int prog_shim_ff_threshold(PHYMOD_ST* pc); 181 int qmod16_disable_set(PHYMOD_ST* pc); 182 int qmod16_credit_control(PHYMOD_ST* pc, int enable); 183 int qmod16_tx_lane_control_set(PHYMOD_ST* pc, int enable, tx_lane_disable_type_t tx_dis_type); 184 int qmod16_pll_lock_get(PHYMOD_ST* pc, int* lockStatus); 185 #endif /* _DV_TB_ */ 186 187 /** 188 @brief update the port mode 189 @param pc handle to current TSCE context (#PHYMOD_ST) 190 @param pll_restart Indicates if required to restart PLL. 191 @returns The value PHYMOD_E_NONE upon successful completion 192 */ 193 int qmod16_update_port_mode(PHYMOD_ST *pc, int single_port_mode) 194 { 195 MAIN_SETUPr_t mode_reg; 196 READ_MAIN_SETUPr(pc, &mode_reg); 197 198 MAIN_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, single_port_mode); 199 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SETUPr(pc, mode_reg)); 200 return PHYMOD_E_NONE ; 201 } 202 203 /*! 204 @brief This function reads TX-PLL PLL_LOCK bit. 205 @param pc handle to current TSCE context (#PHYMOD_ST) 206 @param lockStatus reference which is updated with lock status. 207 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 208 @details Read PLL lock status. Returns 1 or 0 (locked/not) 209 */ 210 211 int qmod16_pll_lock_get(PHYMOD_ST* pc, int* lockStatus) 212 { 213 PMD_X1_STSr_t reg_pmd_x1_sts; 214 QMOD16_DBG_IN_FUNC_INFO(pc); 215 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 216 217 *lockStatus = PMD_X1_STSr_PLL_LOCK_STSf_GET(reg_pmd_x1_sts); 218 return PHYMOD_E_NONE; 219 } 220 221 /** 222 @brief This function reads TX-PMD PMD_LOCK bit. 223 @param pc handle to current TSCE context (#PHYMOD_ST) 224 @param lockStatus reference which is updated with pmd_lock status 225 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 226 @details Read PMD lock status Returns 1 or 0 (locked/not) 227 */ 228 229 int qmod16_pmd_lock_get(PHYMOD_ST* pc, uint32_t * lockStatus) 230 { 231 PMD_X4_STSr_t reg_pmd_x4_sts; 232 QMOD16_DBG_IN_FUNC_INFO(pc); 233 READ_PMD_X4_STSr(pc, ®_pmd_x4_sts); 234 235 *lockStatus = PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_sts); 236 return PHYMOD_E_NONE; 237 } 238 239 #ifdef _DV_TB_ 240 /* 241 @brief This function waits for TX-PLL PLL_LOCK bit. The register is one copy 242 @param pc handle to current TSCE context (#PHYMOD_ST) 243 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 244 @details Wait for PLL to lock. Cannot be used in SDK. 245 */ 246 247 int qmod16_pll_lock_wait(PHYMOD_ST* pc, int timeOutValue) 248 { 249 int rv; 250 QMOD16_DBG_IN_FUNC_INFO(pc); 251 252 rv = qmod16_regbit_set_wait_check(pc, 253 0x9012, 254 1, 1, timeOutValue); 255 /* TBD PMD_X1_STATUS_PLL_LOCK_STS_MASK, 1, timeOutValue); */ 256 if (rv == SOC_E_TIMEOUT) { 257 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d Timeout PLL lock:\n", __func__, pc->port)); 258 return (SOC_E_TIMEOUT); 259 } 260 return PHYMOD_E_NONE; 261 } 262 #endif 263 264 #ifdef _DV_TB_ 265 /* 266 @brief This function waits for the the RX-PMD to lock. 267 @param pc handle to current TSCE context (#PHYMOD_ST) 268 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 269 @details This function has a time out limit (TE_PLL_WAIT*50) micro-second in driver. 270 or TE_PLL_WAIT/20 pulling count in simualtion, if per_lane_control is set. Otherwise, 271 if per_lane_control==0, it reads back PMD_LIVE_STATUS and put it on accData. 272 */ 273 int qmod16_wait_pmd_lock(PHYMOD_ST* pc, int timeOutValue, int* lockStatus) 274 { 275 int rv; 276 PMD_X4_STSr_t reg_pmd_x4_stats; 277 QMOD16_DBG_IN_FUNC_INFO(pc); 278 279 PMD_X4_STSr_CLR(reg_pmd_x4_stats); 280 281 if (pc->per_lane_control) { 282 rv = qmod16_regbit_set_wait_check(pc, 0xc012, 1,1,timeOutValue); 283 /* TBD PMD_X4_STATUS_RX_LOCK_STS_MASK,1,timeOutValue); */ 284 285 if (rv == SOC_E_TIMEOUT) { 286 PHYMOD_DEBUG_ERROR(("%-22s ERROR: P=%0d Timeout RX PMD lock:\n", __func__, pc->port)); 287 pc->accData = 0; 288 *lockStatus = 0; 289 return rv; 290 } else { 291 pc->accData = 1; 292 *lockStatus = 1; 293 } 294 } else { 295 READ_PMD_X4_STSr(pc, ®_pmd_x4_stats); 296 if (PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_stats)) { 297 pc->accData = 1; 298 *lockStatus = 1; 299 } else { 300 pc->accData = 0; 301 *lockStatus = 0; 302 } 303 } 304 return (PHYMOD_E_NONE); 305 } 306 #endif 307 308 309 #ifdef _DV_TB_ 310 /** 311 @brief controls PCS Bypass Control function. 312 @param pc handle to current TSCE context (#PHYMOD_ST) 313 @param cntl Control value (bypass, un-bypass) 314 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 315 @details Set cntl <B>0 to disable</B> PCS and <B>1 to enable</B> PCS 316 When bypassed, PCS relinquishes control of PMD resets and PCS logic programming. 317 TEMod can take complete control of PMD programming. Bypass is also used in ILKN 318 mode where the PCS is not used. 319 320 */ 321 int qmod16_pcs_bypass_ctl (PHYMOD_ST* pc, int cntl) 322 { 323 SC_X4_BYPASSr_t reg_sc_bypass; 324 325 QMOD16_DBG_IN_FUNC_INFO(pc); 326 SC_X4_BYPASSr_CLR(reg_sc_bypass); 327 328 if (cntl==TEMOD_SC_MODE_BYPASS) { 329 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 1); 330 } else { 331 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_sc_bypass, 0); 332 } 333 334 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_BYPASSr( pc, reg_sc_bypass)); 335 336 return PHYMOD_E_NONE; 337 } 338 #endif 339 340 #ifdef _DV_TB_ 341 /** 342 @brief Controls PMD datapath resets. 343 @param pc handle to current TSCE context (#PHYMOD_ST) 344 @param cntl Controls if PMD should be reset or unset 345 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 346 @details Set cntl arg <B>0</B>:disable <B>1</B>: enable 347 The PMD datapath is reset even if PCS is actively controlling PMD resets. 348 There are two types of control. One per lane and one per Core. 349 */ 350 int qmod16_pmd_reset_bypass (PHYMOD_ST* pc, int cntl) /* PMD_RESET_BYPASS */ 351 { 352 int lnCntl, coreCntl; 353 lnCntl = cntl & 0x10 ; 354 coreCntl = cntl & 0x1 ; 355 PMD_X4_OVRRr_t reg_pmd_x4_or; 356 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 357 PMD_X1_OVRRr_t reg_pmd_x1_or; 358 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 359 SC_X4_CTLr_t reg_sc_ctrl; 360 361 QMOD16_DBG_IN_FUNC_INFO(pc); 362 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 363 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 364 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 365 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 366 SC_X4_CTLr_CLR(reg_sc_ctrl); 367 368 if (lnCntl) { 369 PMD_X4_OVRRr_LN_RX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 1); 370 PMD_X4_OVRRr_LN_TX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 1); 371 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 372 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 0); 373 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 0); 374 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 375 376 /* toggle added */ 377 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 378 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 379 380 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 381 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 382 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 383 384 PMD_X4_OVRRr_LN_RX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 385 PMD_X4_OVRRr_LN_TX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 386 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 387 388 } else { 389 PMD_X4_OVRRr_LN_RX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 390 PMD_X4_OVRRr_LN_TX_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 391 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 392 393 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 394 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 395 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 396 } 397 398 if (coreCntl) { 399 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 1); 400 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 401 402 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 0); 403 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 404 405 /* toggle added */ 406 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 407 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 408 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 409 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 410 411 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 412 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 413 414 } else { 415 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 416 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 417 418 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 419 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 420 } 421 422 /* sw_speed_change toggled */ 423 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 424 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 425 426 SC_X4_CTLr_CLR(reg_sc_ctrl); 427 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 1); 428 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 429 430 return PHYMOD_E_NONE; 431 } /* PMD_RESET_BYPASS */ 432 #endif 433 434 435 #ifdef _SDK_QMOD16_ 436 /*! 437 \brief Controls the setting/resetting of autoneg timers. 438 \param pc handle to current TSCE context (#PHYMOD_ST) 439 \returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 440 \details 441 Get aneg features via #PHYMOD_ST->an_tech_ability and write the pages 442 This does not start the autoneg. That is done in qmod16_autoneg_control 443 444 */ 445 int qmod16_autoneg_timer_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 446 { 447 CL37_RESTARTr_t reg_cl37_restart_timers; 448 CL37_ACKr_t reg_cl37_ack_timers; 449 450 LNK_UP_TYPEr_t reg_link_up_timer; 451 SGMII_CL37_TMR_TYPEr_t reg_an_cl37_sgmii_tmr; 452 453 IGNORE_LNK_TMR_TYPEr_t reg_ignore_link_timers; 454 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_t reg_inhbt_not_cl72_timers; 455 456 /*0x9250 AN_X1_TIMERS_cl37_restart */ 457 CL37_RESTARTr_CLR(reg_cl37_restart_timers); 458 /* coverity[operator_confusion] */ 459 CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_SET(reg_cl37_restart_timers, 0x29a); 460 PHYMOD_IF_ERR_RETURN(WRITE_CL37_RESTARTr(pc, reg_cl37_restart_timers)); 461 462 /*0x9251 AN_X1_TIMERS_cl37_ack */ 463 CL37_ACKr_CLR(reg_cl37_ack_timers); 464 /* coverity[operator_confusion] */ 465 CL37_ACKr_CL37_ACK_TIMER_PERIODf_SET(reg_cl37_ack_timers, 0x29a); 466 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ACKr(pc, reg_cl37_ack_timers)); 467 468 /*TBD::0x9254 AN_X1_TIMERS_sgmii_cl73_timer_type*/ 469 SGMII_CL37_TMR_TYPEr_CLR(reg_an_cl37_sgmii_tmr); 470 /* coverity[operator_confusion] */ 471 SGMII_CL37_TMR_TYPEr_SGMII_TIMERf_SET(reg_an_cl37_sgmii_tmr, 0x6b); 472 PHYMOD_IF_ERR_RETURN(WRITE_SGMII_CL37_TMR_TYPEr(pc, reg_an_cl37_sgmii_tmr)); 473 474 /*TBD::0x9255 AN_X1_TIMERS_link_up_typ*/ 475 LNK_UP_TYPEr_CLR(reg_link_up_timer); 476 LNK_UP_TYPEr_SET(reg_link_up_timer, 0x29a); 477 PHYMOD_IF_ERR_RETURN(WRITE_LNK_UP_TYPEr(pc, reg_link_up_timer)); 478 479 /*0x9256 AN_X1_TIMERS_ignore_link */ 480 IGNORE_LNK_TMR_TYPEr_CLR(reg_ignore_link_timers); 481 IGNORE_LNK_TMR_TYPEr_SET(reg_ignore_link_timers, 0x29a); 482 PHYMOD_IF_ERR_RETURN(WRITE_IGNORE_LNK_TMR_TYPEr(pc, reg_ignore_link_timers)); 483 484 /*0x9256 AN_X1_TIMERS_link_fail_inhbt_tmr_not_cl72 */ 485 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_CLR(reg_inhbt_not_cl72_timers); 486 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_SET(reg_inhbt_not_cl72_timers, 0x8382); 487 PHYMOD_IF_ERR_RETURN(WRITE_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr(pc, reg_inhbt_not_cl72_timers)); 488 489 return PHYMOD_E_NONE; 490 } 491 #endif 492 493 #ifdef _DV_TB_ 494 /** 495 @brief Controls the setting/resetting of autoneg advertisement registers. 496 @param pc handle to current TSCE context (#PHYMOD_ST) 497 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 498 @details 499 Get aneg features via #PHYMOD_ST->an_tech_ability and write the pages 500 This does not start the autoneg. That is done in qmod16_autoneg_control 501 502 */ 503 int qmod16_autoneg_abilities_controls(PHYMOD_ST* pc, int sub_port) 504 { 505 AN_X4_ABI_SP0_CTLSr_t reg_an_ctrl_sp0; 506 AN_X4_ABI_SP1_CTLSr_t reg_an_ctrl_sp1; 507 AN_X4_ABI_SP2_CTLSr_t reg_an_ctrl_sp2; 508 AN_X4_ABI_SP3_CTLSr_t reg_an_ctrl_sp3; 509 510 if (sub_port == 0) { 511 AN_X4_ABI_SP0_CTLSr_CLR(reg_an_ctrl_sp0); 512 AN_X4_ABI_SP0_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp0, pc->an_good_trap); 513 AN_X4_ABI_SP0_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp0, pc->an_good_check_trap); 514 AN_X4_ABI_SP0_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp0, pc->linkfailtimer_dis); 515 AN_X4_ABI_SP0_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp0, pc->linkfailtimerqua_en); 516 AN_X4_ABI_SP0_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp0, pc->an_fail_cnt); 517 AN_X4_ABI_SP0_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp0, pc->an_oui_ctrl); 518 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_CTLSr(pc, reg_an_ctrl_sp0)); 519 } else if (sub_port == 1) { 520 AN_X4_ABI_SP1_CTLSr_CLR(reg_an_ctrl_sp1); 521 AN_X4_ABI_SP1_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp1, pc->an_good_trap); 522 AN_X4_ABI_SP1_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp1, pc->an_good_check_trap); 523 AN_X4_ABI_SP1_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp1, pc->linkfailtimer_dis); 524 AN_X4_ABI_SP1_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp1, pc->linkfailtimerqua_en); 525 AN_X4_ABI_SP1_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp1, pc->an_fail_cnt); 526 AN_X4_ABI_SP1_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp1, pc->an_oui_ctrl); 527 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_CTLSr(pc, reg_an_ctrl_sp1)); 528 } else if (sub_port == 2) { 529 AN_X4_ABI_SP2_CTLSr_CLR(reg_an_ctrl_sp2); 530 AN_X4_ABI_SP2_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp2, pc->an_good_trap); 531 AN_X4_ABI_SP2_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp2, pc->an_good_check_trap); 532 AN_X4_ABI_SP2_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp2, pc->linkfailtimer_dis); 533 AN_X4_ABI_SP2_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp2, pc->linkfailtimerqua_en); 534 AN_X4_ABI_SP2_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp2, pc->an_fail_cnt); 535 AN_X4_ABI_SP2_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp2, pc->an_oui_ctrl); 536 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_CTLSr(pc, reg_an_ctrl_sp2)); 537 } else if (sub_port == 3) { 538 AN_X4_ABI_SP3_CTLSr_CLR(reg_an_ctrl_sp3); 539 AN_X4_ABI_SP3_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp3, pc->an_good_trap); 540 AN_X4_ABI_SP3_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp3, pc->an_good_check_trap); 541 AN_X4_ABI_SP3_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp3, pc->linkfailtimer_dis); 542 AN_X4_ABI_SP3_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp3, pc->linkfailtimerqua_en); 543 AN_X4_ABI_SP3_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp3, pc->an_fail_cnt); 544 AN_X4_ABI_SP3_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp3, pc->an_oui_ctrl); 545 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_CTLSr(pc, reg_an_ctrl_sp3)); 546 } 547 548 return PHYMOD_E_NONE; 549 } 550 int qmod16_autoneg_cl37_base_abilities(PHYMOD_ST* pc,int sub_port) 551 { 552 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 553 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 554 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 555 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 556 557 if (sub_port == 0) { 558 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 559 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_speed & 7)); 560 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_duplex & 1)); 561 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_fd & 1)); 562 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_hd & 1)); 563 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_pause & 3)); 564 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_np & 1)); 565 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_master_mode & 1)); 566 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_link_status & 1)); 567 568 if (pc->cl37_bam_en) { 569 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 0); 570 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, 0); 571 } else { 572 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 1); 573 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 574 } 575 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_disable_reset_disable & 1)); 576 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp0)); 577 } else if (sub_port == 1) { 578 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 579 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_speed & 7)); 580 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_duplex & 1)); 581 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_fd & 1)); 582 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_hd & 1)); 583 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_pause & 3)); 584 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_np & 1)); 585 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_master_mode & 1)); 586 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_link_status & 1)); 587 588 if (pc->cl37_bam_en) { 589 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 0); 590 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, 0); 591 } else { 592 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 1); 593 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 594 } 595 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_disable_reset_disable & 1)); 596 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp1)); 597 } else if (sub_port == 2) { 598 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 599 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_speed & 7)); 600 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_duplex & 1)); 601 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_fd & 1)); 602 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_hd & 1)); 603 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_pause & 3)); 604 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_np & 1)); 605 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_master_mode & 1)); 606 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_link_status & 1)); 607 608 if (pc->cl37_bam_en) { 609 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 0); 610 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, 0); 611 } else { 612 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 1); 613 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 614 } 615 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_disable_reset_disable & 1)); 616 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp2)); 617 } else if (sub_port == 3) { 618 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 619 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_speed & 7)); 620 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_duplex & 1)); 621 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_fd & 1)); 622 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_hd & 1)); 623 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_pause & 3)); 624 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_np & 1)); 625 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_master_mode & 1)); 626 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_LINK_STATUSf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_link_status & 1)); 627 628 if (pc->cl37_bam_en) { 629 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 0); 630 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, 0); 631 } else { 632 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 1); 633 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 634 } 635 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_disable_reset_disable & 1)); 636 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp3)); 637 } 638 639 return PHYMOD_E_NONE; 640 } 641 int qmod16_autoneg_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port) 642 { 643 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp0; 644 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp1; 645 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp2; 646 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp3; 647 648 if (sub_port==0) { 649 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp0); 650 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp0, (pc->cl37_bam_ovr1g_pgcnt & 3)); 651 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp0, (pc->cl37_bam_ovr1g_en & 1)); 652 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp0, (pc->cl37_bam_code & 0x1ff)); 653 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp0)); 654 } else if (sub_port==1) { 655 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp1); 656 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp1, (pc->cl37_bam_ovr1g_pgcnt & 3)); 657 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp1, (pc->cl37_bam_ovr1g_en & 1)); 658 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp1, (pc->cl37_bam_code & 0x1ff)); 659 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp1)); 660 } else if (sub_port==2) { 661 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp2); 662 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp2, (pc->cl37_bam_ovr1g_pgcnt & 3)); 663 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp2, (pc->cl37_bam_ovr1g_en & 1)); 664 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp2, (pc->cl37_bam_code & 0x1ff)); 665 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp2)); 666 } else if (sub_port==3) { 667 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp3); 668 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp3, (pc->cl37_bam_ovr1g_pgcnt & 3)); 669 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp3, (pc->cl37_bam_ovr1g_en & 1)); 670 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp3, (pc->cl37_bam_code & 0x1ff)); 671 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp3)); 672 } 673 674 return PHYMOD_E_NONE; 675 } 676 int qmod16_autoneg_cl37_bam_over1g_abilities(PHYMOD_ST* pc,int sub_port) 677 { 678 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp0; 679 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp1; 680 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp2; 681 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp3; 682 if (sub_port == 0) { 683 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp0); 684 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp0, (pc->cl37_bam_speed & 0x7ff)); 685 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp0)); 686 } else if (sub_port == 1) { 687 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp1); 688 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp1, (pc->cl37_bam_speed & 0x7ff)); 689 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp1)); 690 } else if (sub_port == 2) { 691 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp2); 692 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp2, (pc->cl37_bam_speed & 0x7ff)); 693 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp2)); 694 } else if (sub_port == 3) { 695 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp3); 696 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp3, (pc->cl37_bam_speed & 0x7ff)); 697 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp3)); 698 } 699 return PHYMOD_E_NONE; 700 } 701 int qmod16_autoneg_set(PHYMOD_ST* pc) /* AUTONEG_SET */ 702 { 703 704 QMOD16_DBG_IN_FUNC_INFO(pc); 705 706 qmod16_autoneg_abilities_controls(pc,pc->sub_port); 707 708 if (pc->sc_mode == QMOD16_SC_MODE_AN_CL37) { 709 /* an37 */ 710 /*Local device cl37 base abilities setting*/ 711 qmod16_autoneg_cl37_base_abilities(pc,pc->sub_port); 712 713 /*Local device cl37 bam abilities setting*/ 714 715 qmod16_autoneg_cl37_bam_abilities(pc,pc->sub_port); 716 717 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC184 *******/ 718 if (pc->cl37_bam_speed) { 719 qmod16_autoneg_cl37_bam_over1g_abilities(pc,pc->sub_port); 720 } 721 } 722 return PHYMOD_E_NONE; 723 } 724 #endif 725 726 /* 727 @brief To get autoneg control registers. 728 @param pc handle to current TSCE context (#PHYMOD_ST) 729 @param an_control details 730 @param an_complete reference which is updated with an_complete info 731 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 732 @details Upper layer software calls this function to get autoneg info. 733 734 <B>How to call:</B><br> 735 <p>Call directly </p> 736 */ 737 738 int qmod16_autoneg_control_get(PHYMOD_ST* pc, int sub_port, qmod16_an_control_t *an_control, int *an_complete) 739 { 740 /* code not complete.*/ 741 AN_X4_SW_SP0_AN_MISC_STSr_t an_misc_reg_sub0; 742 AN_X4_SW_SP1_AN_MISC_STSr_t an_misc_reg_sub1; 743 AN_X4_SW_SP2_AN_MISC_STSr_t an_misc_reg_sub2; 744 AN_X4_SW_SP3_AN_MISC_STSr_t an_misc_reg_sub3; 745 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 746 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 747 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 748 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 749 750 an_control->num_lane_adv = 1; 751 an_control->enable = 0; 752 *an_complete = 0; 753 switch (sub_port) { 754 case 0: 755 READ_AN_X4_ABI_SP0_ENSr(pc, ®_an_enb0); 756 if (AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb0)) { 757 an_control->enable = 1; 758 an_control->an_type = QMOD16_AN_MODE_SGMII; 759 } else if (AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb0)) { 760 an_control->enable = 1; 761 an_control->an_type = QMOD16_AN_MODE_CL37BAM; 762 } else if (AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(reg_an_enb0)) { 763 an_control->enable = 1; 764 an_control->an_type = QMOD16_AN_MODE_CL37; 765 } else { 766 an_control->enable = 0; 767 an_control->an_type = QMOD16_AN_MODE_NONE; 768 } 769 READ_AN_X4_SW_SP0_AN_MISC_STSr(pc, &an_misc_reg_sub0); 770 *an_complete = AN_X4_SW_SP0_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub0); 771 break; 772 case 1: 773 READ_AN_X4_ABI_SP1_ENSr(pc, ®_an_enb1); 774 if (AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb1)) { 775 an_control->enable = 1; 776 an_control->an_type = QMOD16_AN_MODE_SGMII; 777 } else if (AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb1)) { 778 an_control->enable = 1; 779 an_control->an_type = QMOD16_AN_MODE_CL37BAM; 780 } else if (AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(reg_an_enb1)) { 781 an_control->enable = 1; 782 an_control->an_type = QMOD16_AN_MODE_CL37; 783 } else { 784 an_control->enable = 0; 785 an_control->an_type = QMOD16_AN_MODE_NONE; 786 } 787 READ_AN_X4_SW_SP1_AN_MISC_STSr(pc, &an_misc_reg_sub1); 788 *an_complete = AN_X4_SW_SP1_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub1); 789 break; 790 case 2: 791 READ_AN_X4_ABI_SP2_ENSr(pc, ®_an_enb2); 792 if (AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb2)) { 793 an_control->enable = 1; 794 an_control->an_type = QMOD16_AN_MODE_SGMII; 795 } else if (AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb2)) { 796 an_control->enable = 1; 797 an_control->an_type = QMOD16_AN_MODE_CL37BAM; 798 } else if (AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(reg_an_enb2)) { 799 an_control->enable = 1; 800 an_control->an_type = QMOD16_AN_MODE_CL37; 801 } else { 802 an_control->enable = 0; 803 an_control->an_type = QMOD16_AN_MODE_NONE; 804 } 805 READ_AN_X4_SW_SP2_AN_MISC_STSr(pc, &an_misc_reg_sub2); 806 *an_complete = AN_X4_SW_SP2_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub2); 807 break; 808 default: 809 READ_AN_X4_ABI_SP3_ENSr(pc, ®_an_enb3); 810 if (AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb3)) { 811 an_control->enable = 1; 812 an_control->an_type = QMOD16_AN_MODE_SGMII; 813 } else if (AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb3)) { 814 an_control->enable = 1; 815 an_control->an_type = QMOD16_AN_MODE_CL37BAM; 816 } else if (AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(reg_an_enb3)) { 817 an_control->enable = 1; 818 an_control->an_type = QMOD16_AN_MODE_CL37; 819 } else { 820 an_control->enable = 0; 821 an_control->an_type = QMOD16_AN_MODE_NONE; 822 } 823 READ_AN_X4_SW_SP3_AN_MISC_STSr(pc, &an_misc_reg_sub3); 824 *an_complete = AN_X4_SW_SP3_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub3); 825 break; 826 } 827 return PHYMOD_E_NONE; 828 } 829 830 /** 831 @brief To get autoneg advertisement registers. 832 @param pc handle to current TSCE context (#PHYMOD_ST) 833 @param an_ability_st, with the local abilities 834 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 835 @details Upper layer software calls this function to get local autoneg 836 info. 837 838 <B>How to call:</B><br> 839 <p>Call directly </p> 840 */ 841 842 int qmod16_autoneg_local_ability_get(PHYMOD_ST* pc, qmod16_an_ability_t *an_ability_st, int sub_port) 843 { 844 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 845 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 846 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 847 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 848 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 849 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 850 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 851 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 852 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp0; 853 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp1; 854 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp2; 855 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp3; 856 AN_X4_LP_SP0_LP_BASE_PAGE1r_t reg_lp_sp0 ; 857 AN_X4_LP_SP1_LP_BASE_PAGE1r_t reg_lp_sp1 ; 858 AN_X4_LP_SP2_LP_BASE_PAGE1r_t reg_lp_sp2 ; 859 AN_X4_LP_SP3_LP_BASE_PAGE1r_t reg_lp_sp3 ; 860 uint16_t value=0 ; 861 862 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_NONE ; 863 an_ability_st->cl37_adv.cl37_sgmii_speed = 0 ; 864 an_ability_st->cl37_adv.an_pause = 0 ; 865 an_ability_st->cl37_adv.an_bam_speed = 0 ; 866 an_ability_st->cl37_adv.an_duplex = 0 ; 867 868 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 869 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 870 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp0); 871 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 872 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 873 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp1); 874 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 875 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 876 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp2); 877 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 878 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 879 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp3); 880 AN_X4_LP_SP0_LP_BASE_PAGE1r_CLR(reg_lp_sp0) ; 881 AN_X4_LP_SP1_LP_BASE_PAGE1r_CLR(reg_lp_sp1) ; 882 AN_X4_LP_SP2_LP_BASE_PAGE1r_CLR(reg_lp_sp2) ; 883 AN_X4_LP_SP3_LP_BASE_PAGE1r_CLR(reg_lp_sp3) ; 884 885 if (sub_port == 0) { 886 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP0_ENSr(pc, ®_an_enb0)); 887 if (AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(reg_an_enb0)) { 888 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 889 890 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp0)); 891 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp0); 892 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_FULL_DUPLEX_SET ; 893 894 /* no combined modes yet; cl37 default full duplex */ 895 if (AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb0)) { 896 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 897 an_ability_st->cl37_adv.an_pause = QMOD16_SYMM_PAUSE ; 898 899 if (AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp0)) { /* master mode dicates a role */ 900 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp0) ; 901 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp0))? 902 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 903 } else { 904 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP0_LP_BASE_PAGE1r(pc, ®_lp_sp0)); 905 value = AN_X4_LP_SP0_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp0) ; 906 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 907 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 908 } 909 } 910 if (AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb0)) { 911 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 912 913 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp0)); 914 if (AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp0)) { 915 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 916 } 917 } 918 } 919 } else if (sub_port == 1) { 920 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP1_ENSr(pc, ®_an_enb1)); 921 if (AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(reg_an_enb1)) { 922 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 923 924 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp1)); 925 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp1); 926 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_FULL_DUPLEX_SET ; 927 928 /* no combined modes yet */ 929 if (AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb1)) { 930 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 931 an_ability_st->cl37_adv.an_pause = QMOD16_SYMM_PAUSE ; 932 933 if (AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp1)) { 934 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp1) ; 935 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp1))? 936 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 937 } else { 938 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP1_LP_BASE_PAGE1r(pc, ®_lp_sp1)); 939 value = AN_X4_LP_SP1_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp1) ; 940 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 941 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 942 } 943 } 944 if (AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb1)) { 945 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 946 947 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp1)); 948 if (AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp1)) { 949 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 950 } 951 } 952 } 953 } else if (sub_port == 2) { 954 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP2_ENSr(pc, ®_an_enb2)); 955 if (AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(reg_an_enb2)) { 956 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 957 958 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp2)); 959 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp2); 960 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_FULL_DUPLEX_SET ; 961 962 /* no combined modes yet */ 963 if (AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb2)) { 964 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 965 an_ability_st->cl37_adv.an_pause = QMOD16_SYMM_PAUSE ; 966 967 if (AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp2)) { 968 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp2) ; 969 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp2))? 970 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 971 } else { 972 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP2_LP_BASE_PAGE1r(pc, ®_lp_sp2)); 973 value = AN_X4_LP_SP2_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp2) ; 974 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 975 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 976 } 977 } 978 if (AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb2)) { 979 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 980 981 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp2)); 982 if (AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp2)) { 983 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 984 } 985 } 986 } 987 } else if (sub_port == 3) { 988 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP3_ENSr(pc, ®_an_enb3)); 989 if (AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(reg_an_enb3)) { 990 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 991 992 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp3)); 993 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp3); 994 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_FULL_DUPLEX_SET; 995 996 /* no combined modes yet */ 997 if (AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb3)) { 998 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 999 an_ability_st->cl37_adv.an_pause = QMOD16_SYMM_PAUSE ; 1000 1001 if (AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp3)) { 1002 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp3) ; 1003 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp3))? 1004 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 1005 } else { 1006 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP3_LP_BASE_PAGE1r(pc, ®_lp_sp3)); 1007 value = AN_X4_LP_SP3_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp3) ; 1008 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1009 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 1010 } 1011 } 1012 if (AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb3)) { 1013 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 1014 1015 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp3)); 1016 if (AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp3)) { 1017 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 1018 } 1019 } 1020 } 1021 } else { return PHYMOD_E_PARAM ; } 1022 return PHYMOD_E_NONE; 1023 } 1024 1025 /** 1026 @brief To get autoneg advertisement registers. 1027 @param pc handle to current TSCE context (#PHYMOD_ST) 1028 @param an_ability_st, with the remote abilities 1029 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1030 @details Upper layer software calls this function to get autoneg 1031 info. 1032 */ 1033 1034 int qmod16_autoneg_remote_ability_get(PHYMOD_ST* pc, qmod16_an_ability_t *an_ability_st, int sub_port) 1035 { 1036 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 1037 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 1038 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 1039 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 1040 AN_X4_LP_SP0_LP_BASE_PAGE1r_t reg_lp_sp0 ; /* 0xc248 */ 1041 AN_X4_LP_SP1_LP_BASE_PAGE1r_t reg_lp_sp1 ; 1042 AN_X4_LP_SP2_LP_BASE_PAGE1r_t reg_lp_sp2 ; 1043 AN_X4_LP_SP3_LP_BASE_PAGE1r_t reg_lp_sp3 ; 1044 AN_X4_LP_SP0_LP_MP1024_UP1r_t reg_bam37_sp0 ; /* 0xc254 */ 1045 AN_X4_LP_SP1_LP_MP1024_UP1r_t reg_bam37_sp1 ; /* 0xc254 */ 1046 AN_X4_LP_SP2_LP_MP1024_UP1r_t reg_bam37_sp2 ; /* 0xc254 */ 1047 AN_X4_LP_SP3_LP_MP1024_UP1r_t reg_bam37_sp3 ; /* 0xc254 */ 1048 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 1049 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 1050 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 1051 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 1052 uint16_t value = 0; 1053 1054 #define QMOD16_AN_SGMII_SPEED_MASK 0x7 1055 #define QMOD16_AN_SGMII_SPEED_BIT 9 1056 #define QMOD16_AN_SGMII_DUPLEX_MASK 0x1 1057 #define QMOD16_AN_SGMII_DUPLEX_BIT 12 1058 #define QMOD16_AN_CL37_DUPLEX_MASK 0x3 1059 #define QMOD16_AN_CL37_DUPLEX_BIT 5 1060 #define QMOD16_AN_CL37_PAUSE_MASK 0x3 1061 #define QMOD16_AN_CL37_PAUSE_BIT 7 1062 1063 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_NONE ; 1064 an_ability_st->cl37_adv.cl37_sgmii_speed = 0 ; 1065 an_ability_st->cl37_adv.an_pause = 0 ; 1066 an_ability_st->cl37_adv.an_bam_speed = 0 ; 1067 an_ability_st->cl37_adv.an_duplex = 0 ; 1068 1069 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1070 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1071 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1072 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1073 AN_X4_LP_SP0_LP_BASE_PAGE1r_CLR(reg_lp_sp0) ; 1074 AN_X4_LP_SP1_LP_BASE_PAGE1r_CLR(reg_lp_sp1) ; 1075 AN_X4_LP_SP2_LP_BASE_PAGE1r_CLR(reg_lp_sp2) ; 1076 AN_X4_LP_SP3_LP_BASE_PAGE1r_CLR(reg_lp_sp3) ; 1077 AN_X4_LP_SP0_LP_MP1024_UP1r_CLR(reg_bam37_sp0) ; 1078 AN_X4_LP_SP1_LP_MP1024_UP1r_CLR(reg_bam37_sp1) ; 1079 AN_X4_LP_SP2_LP_MP1024_UP1r_CLR(reg_bam37_sp2) ; 1080 AN_X4_LP_SP3_LP_MP1024_UP1r_CLR(reg_bam37_sp3) ; 1081 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 1082 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 1083 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 1084 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 1085 1086 if (sub_port == 0) { 1087 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP0_ENSr(pc, ®_an_enb0)); 1088 1089 if (AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(reg_an_enb0)) { 1090 /* no combined modes yet */ 1091 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP0_LP_BASE_PAGE1r(pc, ®_lp_sp0)); 1092 if (AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb0)) { 1093 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 1094 1095 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp0)); 1096 1097 if (AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp0)) { /* master mode dicates a role */ 1098 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp0) ; 1099 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp0))? 1100 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 1101 } else { 1102 value = AN_X4_LP_SP0_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp0) ; 1103 an_ability_st->cl37_adv.cl37_sgmii_speed = QMOD16_AN_SGMII_SPEED_MASK & (value >> QMOD16_AN_SGMII_SPEED_BIT); 1104 an_ability_st->cl37_adv.an_duplex = (QMOD16_AN_SGMII_DUPLEX_MASK & (value >> QMOD16_AN_SGMII_DUPLEX_BIT)) ? QMOD16_AN_FULL_DUPLEX_SET : QMOD16_AN_HALF_DUPLEX_SET; 1105 } 1106 an_ability_st->cl37_adv.an_pause = QMOD16_ASYM_SYMM_PAUSE ; 1107 } else { 1108 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 1109 value = AN_X4_LP_SP0_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp0) ; 1110 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_CL37_DUPLEX_MASK & (value >> QMOD16_AN_CL37_DUPLEX_BIT) ; 1111 an_ability_st->cl37_adv.an_pause = QMOD16_AN_CL37_PAUSE_MASK & (value >> QMOD16_AN_CL37_PAUSE_BIT) ; 1112 } 1113 if (AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb0)) { 1114 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 1115 1116 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP0_LP_MP1024_UP1r(pc, ®_bam37_sp0)); 1117 1118 if (AN_X4_LP_SP0_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp0) & 0x1) { 1119 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 1120 } 1121 } 1122 } 1123 } else if (sub_port == 1) { 1124 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP1_ENSr(pc, ®_an_enb1)); 1125 if (AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(reg_an_enb1)) { 1126 /* no combined modes yet */ 1127 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP1_LP_BASE_PAGE1r(pc, ®_lp_sp1)); 1128 if (AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb1)) { 1129 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 1130 1131 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp1)); 1132 if (AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp1)) { 1133 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp1) ; 1134 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp1))? 1135 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 1136 } else { 1137 value = AN_X4_LP_SP1_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp1) ; 1138 an_ability_st->cl37_adv.cl37_sgmii_speed = QMOD16_AN_SGMII_SPEED_MASK & (value >> QMOD16_AN_SGMII_SPEED_BIT) ; 1139 an_ability_st->cl37_adv.an_duplex = (QMOD16_AN_SGMII_DUPLEX_MASK & (value >> QMOD16_AN_SGMII_DUPLEX_BIT)) ? QMOD16_AN_FULL_DUPLEX_SET : QMOD16_AN_HALF_DUPLEX_SET; 1140 } 1141 an_ability_st->cl37_adv.an_pause = QMOD16_ASYM_SYMM_PAUSE ; 1142 } else { 1143 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 1144 value = AN_X4_LP_SP1_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp1) ; 1145 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_CL37_DUPLEX_MASK & (value >> QMOD16_AN_CL37_DUPLEX_BIT) ; 1146 an_ability_st->cl37_adv.an_pause = QMOD16_AN_CL37_PAUSE_MASK & (value >> QMOD16_AN_CL37_PAUSE_BIT) ; 1147 } 1148 if (AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb1)) { 1149 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 1150 1151 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP1_LP_MP1024_UP1r(pc, ®_bam37_sp1)); 1152 1153 if (AN_X4_LP_SP1_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp1) & 0x1) { 1154 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 1155 } 1156 } 1157 } 1158 } else if (sub_port == 2) { 1159 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP2_ENSr(pc, ®_an_enb2)); 1160 if (AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(reg_an_enb2)) { 1161 /* no combined modes yet */ 1162 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP2_LP_BASE_PAGE1r(pc, ®_lp_sp2)); 1163 if (AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb2)) { 1164 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 1165 1166 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp2)); 1167 1168 if (AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp2)) { 1169 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp2) ; 1170 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp2))? 1171 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 1172 } else { 1173 value = AN_X4_LP_SP2_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp2) ; 1174 an_ability_st->cl37_adv.cl37_sgmii_speed = QMOD16_AN_SGMII_SPEED_MASK & (value >> QMOD16_AN_SGMII_SPEED_BIT) ; 1175 an_ability_st->cl37_adv.an_duplex = (QMOD16_AN_SGMII_DUPLEX_MASK & (value >> QMOD16_AN_SGMII_DUPLEX_BIT)) ? QMOD16_AN_FULL_DUPLEX_SET : QMOD16_AN_HALF_DUPLEX_SET; 1176 } 1177 an_ability_st->cl37_adv.an_pause = QMOD16_ASYM_SYMM_PAUSE ; 1178 } else { 1179 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 1180 value = AN_X4_LP_SP2_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp2) ; 1181 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_CL37_DUPLEX_MASK & (value >> QMOD16_AN_CL37_DUPLEX_BIT) ; 1182 an_ability_st->cl37_adv.an_pause = QMOD16_AN_CL37_PAUSE_MASK & (value >> QMOD16_AN_CL37_PAUSE_BIT) ; 1183 } 1184 if (AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb2)) { 1185 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 1186 1187 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP2_LP_MP1024_UP1r(pc, ®_bam37_sp2)); 1188 1189 if (AN_X4_LP_SP2_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp2) & 0x1) { 1190 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 1191 } 1192 } 1193 } 1194 } else if (sub_port == 3) { 1195 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP3_ENSr(pc, ®_an_enb3)); 1196 if (AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(reg_an_enb3)) { 1197 /* no combined modes yet */ 1198 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP3_LP_BASE_PAGE1r(pc, ®_lp_sp3)); 1199 if (AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb3)) { 1200 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_SGMII ; 1201 1202 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp3)); 1203 if (AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp3)) { 1204 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp3) ; 1205 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp3))? 1206 QMOD16_AN_FULL_DUPLEX_SET:QMOD16_AN_HALF_DUPLEX_SET; 1207 } else { 1208 value = AN_X4_LP_SP3_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp3) ; 1209 an_ability_st->cl37_adv.cl37_sgmii_speed = QMOD16_AN_SGMII_SPEED_MASK & (value >> QMOD16_AN_SGMII_SPEED_BIT) ; 1210 an_ability_st->cl37_adv.an_duplex = (QMOD16_AN_SGMII_DUPLEX_MASK & (value >> QMOD16_AN_SGMII_DUPLEX_BIT)) ? QMOD16_AN_FULL_DUPLEX_SET : QMOD16_AN_HALF_DUPLEX_SET; 1211 } 1212 an_ability_st->cl37_adv.an_pause = QMOD16_ASYM_SYMM_PAUSE ; 1213 } else { 1214 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37 ; 1215 value = AN_X4_LP_SP3_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp3) ; 1216 an_ability_st->cl37_adv.an_duplex = QMOD16_AN_CL37_DUPLEX_MASK & (value >> QMOD16_AN_CL37_DUPLEX_BIT) ; 1217 an_ability_st->cl37_adv.an_pause = QMOD16_AN_CL37_PAUSE_MASK & (value >> QMOD16_AN_CL37_PAUSE_BIT) ; 1218 } 1219 if (AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb3)) { 1220 an_ability_st->cl37_adv.an_type = QMOD16_AN_MODE_CL37BAM ; 1221 1222 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP3_LP_MP1024_UP1r(pc, ®_bam37_sp3)); 1223 1224 if (AN_X4_LP_SP3_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp3) & 0x1) { 1225 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD16_CL37_BAM_2p5GBASE_X) ; 1226 } 1227 } 1228 } 1229 } else { return PHYMOD_E_PARAM ; } 1230 1231 return PHYMOD_E_NONE; 1232 } 1233 1234 int qmod16_autoneg_resolution_ability_get(PHYMOD_ST* pc, qmod16_an_ability_t *an_ability_st, int sub_port) 1235 { 1236 AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_t sp0_an_hcd_status; 1237 AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_t sp1_an_hcd_status; 1238 AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_t sp2_an_hcd_status; 1239 AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_t sp3_an_hcd_status; 1240 1241 AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_CLR(sp0_an_hcd_status); 1242 AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_CLR(sp1_an_hcd_status); 1243 AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_CLR(sp2_an_hcd_status); 1244 AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_CLR(sp3_an_hcd_status); 1245 1246 if (sub_port == 0) { 1247 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr(pc, &sp0_an_hcd_status)); 1248 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp0_an_hcd_status); 1249 an_ability_st->cl37_adv.an_duplex = AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_AN_HCD_DUPLEXf_GET(sp0_an_hcd_status); 1250 an_ability_st->cl37_adv.an_pause = AN_X4_SW_SP0_AN_ABIL_RESOLUTION_STSr_AN_HCD_PAUSEf_GET(sp0_an_hcd_status); 1251 } 1252 else if (sub_port == 1) { 1253 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr(pc, &sp1_an_hcd_status)); 1254 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp1_an_hcd_status); 1255 an_ability_st->cl37_adv.an_duplex = AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_AN_HCD_DUPLEXf_GET(sp1_an_hcd_status); 1256 an_ability_st->cl37_adv.an_pause = AN_X4_SW_SP1_AN_ABIL_RESOLUTION_STSr_AN_HCD_PAUSEf_GET(sp1_an_hcd_status); 1257 } 1258 else if (sub_port == 2) { 1259 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr(pc, &sp2_an_hcd_status)); 1260 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp2_an_hcd_status); 1261 an_ability_st->cl37_adv.an_duplex = AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_AN_HCD_DUPLEXf_GET(sp2_an_hcd_status); 1262 an_ability_st->cl37_adv.an_pause = AN_X4_SW_SP2_AN_ABIL_RESOLUTION_STSr_AN_HCD_PAUSEf_GET(sp2_an_hcd_status); 1263 } 1264 else if (sub_port == 3) { 1265 PHYMOD_IF_ERR_RETURN(READ_AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr(pc, &sp3_an_hcd_status)); 1266 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_AN_HCD_SPEEDf_GET(sp3_an_hcd_status); 1267 an_ability_st->cl37_adv.an_duplex = AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_AN_HCD_DUPLEXf_GET(sp3_an_hcd_status); 1268 an_ability_st->cl37_adv.an_pause = AN_X4_SW_SP3_AN_ABIL_RESOLUTION_STSr_AN_HCD_PAUSEf_GET(sp3_an_hcd_status); 1269 } else { 1270 return PHYMOD_E_PARAM; 1271 } 1272 1273 return PHYMOD_E_NONE; 1274 } 1275 1276 /* 1277 @brief Controls port RX squelch 1278 @param pc handle to current TSCE context (#PHYMOD_ST) 1279 @param enable is the control to RX squelch 1280 @returns The value PHYMOD_E_NONE upon successful completion. 1281 @details Controls port RX squelch 1282 */ 1283 int qmod16_rx_squelch_set(PHYMOD_ST *pc, int enable) 1284 { 1285 SIGDET_CTL1r_t sigdet_ctl; 1286 1287 SIGDET_CTL1r_CLR(sigdet_ctl); 1288 1289 if (enable) { 1290 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 1291 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 1292 } else { 1293 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 1294 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 1295 } 1296 PHYMOD_IF_ERR_RETURN(MODIFY_SIGDET_CTL1r(pc, sigdet_ctl)); 1297 1298 return PHYMOD_E_NONE; 1299 } 1300 1301 /** 1302 @brief Controls port TX squelch 1303 @param pc handle to current TSCE context (#PHYMOD_ST) 1304 @param enable is the control to TX squelch 1305 @returns The value PHYMOD_E_NONE upon successful completion. 1306 @details Controls port TX squelch 1307 */ 1308 int qmod16_tx_squelch_set(PHYMOD_ST *pc, int enable) 1309 { 1310 TXFIR_MISC_CTL0r_t tx_misc_ctl; 1311 1312 TXFIR_MISC_CTL0r_CLR(tx_misc_ctl); 1313 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL0r(pc, &tx_misc_ctl)); 1314 TXFIR_MISC_CTL0r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 1315 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL0r(pc, tx_misc_ctl)); 1316 1317 return PHYMOD_E_NONE; 1318 } 1319 1320 /** 1321 @brief Controls port TX/RX squelch 1322 @param pc handle to current TSCE context (#PHYMOD_ST) 1323 @param enable is the control to TX/RX squelch. Enable=1 means enable the port,no squelch 1324 @returns The value PHYMOD_E_NONE upon successful completion. 1325 @details Controls port TX/RX squelch 1326 */ 1327 int qmod16_port_enable_set(PHYMOD_ST *pc, int enable) 1328 { 1329 if (enable) { 1330 qmod16_rx_squelch_set(pc, 0); 1331 qmod16_tx_squelch_set(pc, 0); 1332 } else { 1333 qmod16_rx_squelch_set(pc, 1); 1334 qmod16_tx_squelch_set(pc, 1); 1335 } 1336 1337 return PHYMOD_E_NONE; 1338 } 1339 1340 /** 1341 @brief Get port TX squelch control settings 1342 @param pc handle to current TSCE context (#PHYMOD_ST) 1343 @param val Receiver for status of TX squelch 1344 @returns The value PHYMOD_E_NONE upon successful completion. 1345 @details Get port TX squelch control settings 1346 */ 1347 int qmod16_tx_squelch_get(PHYMOD_ST *pc, int *val) 1348 { 1349 TXFIR_MISC_CTL0r_t tx_misc_ctl; 1350 1351 TXFIR_MISC_CTL0r_CLR(tx_misc_ctl); 1352 1353 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL0r(pc, &tx_misc_ctl)); 1354 *val = TXFIR_MISC_CTL0r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 1355 1356 return PHYMOD_E_NONE; 1357 } 1358 1359 /** 1360 @brief Gets port RX squelch settings 1361 @param pc handle to current TSCE context (#PHYMOD_ST) 1362 @param val Receiver for status of RX squelch 1363 @returns The value PHYMOD_E_NONE upon successful completion. 1364 @details Gets port RX squelch settings 1365 */ 1366 int qmod16_rx_squelch_get(PHYMOD_ST *pc, int *val) 1367 { 1368 SIGDET_CTL1r_t sigdet_ctl; 1369 1370 SIGDET_CTL1r_CLR(sigdet_ctl); 1371 1372 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 1373 *val = SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 1374 1375 return PHYMOD_E_NONE; 1376 } 1377 1378 /** 1379 @brief Get port TX/RX squelch Settings 1380 @param pc handle to current TSCE context (#PHYMOD_ST) 1381 @param tx_enable - get the TX squelch settings 1382 @param rx_enable - get the RX squelch settings 1383 @returns The value PHYMOD_E_NONE upon successful completion. 1384 @details Controls port TX/RX squelch 1385 */ 1386 int qmod16_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable) 1387 { 1388 1389 qmod16_rx_squelch_get(pc, rx_enable); 1390 qmod16_tx_squelch_get(pc, tx_enable); 1391 1392 return PHYMOD_E_NONE; 1393 } 1394 1395 1396 1397 /** 1398 @brief Controls setting/resetting of autoneg ability and enabling/disabling 1399 @param pc handle to current TSCE context (#PHYMOD_ST) 1400 @param an_control structure with AN controls 1401 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1402 1403 This function programs auto-negotiation (AN) modes for the TSCE. It can 1404 enable/disable clause37/clause73/BAM autonegotiation capabilities. Call this 1405 function once for combo mode and once per lane in independent lane mode. 1406 1407 The autonegotiation mode is controlled by setting specific bits of 1408 #PHYMOD_ST::an_type. 1409 1410 The autonegotiation mode is indicated by setting an_type with 1411 1412 \li QMOD16_AN_NONE (disable AN) 1413 \li QMOD16_CL73 1414 \li QMOD16_CL73_BAM 1415 \li QMOD16_HPAM 1416 */ 1417 1418 #ifdef _DV_TB_ 1419 int qmod16_an_abilities_enables(PHYMOD_ST* pc,int sub_port) 1420 { 1421 uint16_t cl37_bam_enable ; 1422 uint16_t cl37_sgmii_enable, cl37_enable,qsgmii_enable,usxgmii_enable; 1423 uint16_t link_status_echo,duplex_mode_echo,speed_echo,eee_capability_echo,eee_clock_capability_echo; 1424 uint16_t cl37_restart; 1425 1426 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 1427 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 1428 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 1429 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 1430 SC_X4_SC_AN_SUBP_CTLr_t reg_see_sc; 1431 QMOD16_DBG_IN_FUNC_INFO(pc); 1432 1433 link_status_echo = 0x0; 1434 duplex_mode_echo = 0x0; 1435 speed_echo = 0x0; 1436 eee_capability_echo = 0x0; 1437 eee_clock_capability_echo = 0x0; 1438 1439 cl37_bam_enable = 0x0; 1440 cl37_sgmii_enable = 0x0; 1441 qsgmii_enable = 0x0; 1442 usxgmii_enable = 0x0; 1443 cl37_enable = 0x0; 1444 cl37_restart = 0x0; 1445 1446 if (pc->sc_mode == QMOD16_SC_MODE_AN_CL37) { 1447 link_status_echo = pc->link_status_echo; 1448 duplex_mode_echo = pc->duplex_mode_echo; 1449 speed_echo = pc->speed_echo; 1450 eee_capability_echo = pc->eee_capability_echo; 1451 eee_clock_capability_echo = pc->eee_clock_capability_echo; 1452 cl37_restart = pc->cl37_an_restart; 1453 cl37_enable = pc->cl37_an_en; 1454 cl37_bam_enable = pc->cl37_bam_en; 1455 cl37_sgmii_enable = pc->cl37_sgmii_en; 1456 qsgmii_enable = pc->qsgmii_mode; 1457 usxgmii_enable = pc->usxgmii_mode; 1458 } else { 1459 return PHYMOD_E_FAIL; 1460 } 1461 1462 if (pc->tsc_port_touched == 0) { 1463 SC_X4_SC_AN_SUBP_CTLr_CLR(reg_see_sc); 1464 SC_X4_SC_AN_SUBP_CTLr_SET(reg_see_sc,pc->sub_port); 1465 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_SC_AN_SUBP_CTLr(pc, reg_see_sc)); 1466 } 1467 1468 if (cl37_restart == 0) { 1469 if (sub_port == 0) { 1470 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1471 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,0); 1472 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1473 } else if (sub_port == 1) { 1474 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1475 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,0); 1476 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1477 } else if (sub_port == 2) { 1478 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1479 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,0); 1480 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1481 } else if (sub_port == 3) { 1482 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1483 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,0); 1484 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1485 } 1486 } 1487 1488 /*Setting X4 abilities*/ 1489 if (sub_port == 0) { 1490 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1491 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,cl37_restart); 1492 AN_X4_ABI_SP0_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb0,pc->sgmii_to_cl37_auto_enable); 1493 AN_X4_ABI_SP0_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb0,pc->cl37_bam_to_sgmii_auto_enable); 1494 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,cl37_enable); 1495 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb0,cl37_sgmii_enable); 1496 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb0,cl37_bam_enable); 1497 AN_X4_ABI_SP0_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb0,pc->disable_rf_report); 1498 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_SET(reg_an_enb0,qsgmii_enable); 1499 AN_X4_ABI_SP0_ENSr_USXGMII_ENf_SET(reg_an_enb0,usxgmii_enable); 1500 AN_X4_ABI_SP0_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb0,link_status_echo); 1501 AN_X4_ABI_SP0_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb0,duplex_mode_echo); 1502 AN_X4_ABI_SP0_ENSr_SPEED_ECHOf_SET(reg_an_enb0,speed_echo); 1503 AN_X4_ABI_SP0_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb0,eee_capability_echo); 1504 AN_X4_ABI_SP0_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb0,eee_clock_capability_echo); 1505 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1506 } else if (sub_port == 1) { 1507 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1508 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,cl37_restart); 1509 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb1,pc->sgmii_to_cl37_auto_enable); 1510 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb1,pc->cl37_bam_to_sgmii_auto_enable); 1511 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,cl37_enable); 1512 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb1,cl37_sgmii_enable); 1513 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb1,cl37_bam_enable); 1514 AN_X4_ABI_SP1_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb1,pc->disable_rf_report); 1515 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1,qsgmii_enable); 1516 AN_X4_ABI_SP1_ENSr_USXGMII_ENf_SET(reg_an_enb1,usxgmii_enable); 1517 AN_X4_ABI_SP1_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb1,link_status_echo); 1518 AN_X4_ABI_SP1_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb1,duplex_mode_echo); 1519 AN_X4_ABI_SP1_ENSr_SPEED_ECHOf_SET(reg_an_enb1,speed_echo); 1520 AN_X4_ABI_SP1_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb1,eee_capability_echo); 1521 AN_X4_ABI_SP1_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb1,eee_clock_capability_echo); 1522 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1523 } else if (sub_port == 2) { 1524 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1525 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,cl37_restart); 1526 AN_X4_ABI_SP2_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb2,pc->sgmii_to_cl37_auto_enable); 1527 AN_X4_ABI_SP2_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb2,pc->cl37_bam_to_sgmii_auto_enable); 1528 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,cl37_enable); 1529 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb2,cl37_sgmii_enable); 1530 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb2,cl37_bam_enable); 1531 AN_X4_ABI_SP2_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb2,pc->disable_rf_report); 1532 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_SET(reg_an_enb2,qsgmii_enable); 1533 AN_X4_ABI_SP2_ENSr_USXGMII_ENf_SET(reg_an_enb2,usxgmii_enable); 1534 AN_X4_ABI_SP2_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb2,link_status_echo); 1535 AN_X4_ABI_SP2_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb2,duplex_mode_echo); 1536 AN_X4_ABI_SP2_ENSr_SPEED_ECHOf_SET(reg_an_enb2,speed_echo); 1537 AN_X4_ABI_SP2_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb2,eee_capability_echo); 1538 AN_X4_ABI_SP2_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb2,eee_clock_capability_echo); 1539 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1540 } else if (sub_port == 3) { 1541 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1542 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,cl37_restart); 1543 AN_X4_ABI_SP3_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb3,pc->sgmii_to_cl37_auto_enable); 1544 AN_X4_ABI_SP3_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb3,pc->cl37_bam_to_sgmii_auto_enable); 1545 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,cl37_enable); 1546 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb3,cl37_sgmii_enable); 1547 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb3,cl37_bam_enable); 1548 AN_X4_ABI_SP3_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb3,pc->disable_rf_report); 1549 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3,qsgmii_enable); 1550 AN_X4_ABI_SP3_ENSr_USXGMII_ENf_SET(reg_an_enb3,usxgmii_enable); 1551 AN_X4_ABI_SP3_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb3,link_status_echo); 1552 AN_X4_ABI_SP3_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb3,duplex_mode_echo); 1553 AN_X4_ABI_SP3_ENSr_SPEED_ECHOf_SET(reg_an_enb3,speed_echo); 1554 AN_X4_ABI_SP3_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb3,eee_capability_echo); 1555 AN_X4_ABI_SP3_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb3,eee_clock_capability_echo); 1556 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1557 } 1558 1559 if (cl37_restart) { 1560 if (sub_port == 0) { 1561 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1562 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,0); 1563 AN_X4_ABI_SP0_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb0,pc->sgmii_to_cl37_auto_enable); 1564 AN_X4_ABI_SP0_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb0,pc->cl37_bam_to_sgmii_auto_enable); 1565 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,cl37_enable); 1566 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb0,cl37_sgmii_enable); 1567 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb0,cl37_bam_enable); 1568 AN_X4_ABI_SP0_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb0,pc->disable_rf_report); 1569 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_SET(reg_an_enb0,qsgmii_enable); 1570 AN_X4_ABI_SP0_ENSr_USXGMII_ENf_SET(reg_an_enb0,usxgmii_enable); 1571 AN_X4_ABI_SP0_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb0,link_status_echo); 1572 AN_X4_ABI_SP0_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb0,duplex_mode_echo); 1573 AN_X4_ABI_SP0_ENSr_SPEED_ECHOf_SET(reg_an_enb0,speed_echo); 1574 AN_X4_ABI_SP0_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb0,eee_capability_echo); 1575 AN_X4_ABI_SP0_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb0,eee_clock_capability_echo); 1576 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1577 } else if (sub_port == 1) { 1578 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1579 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,0); 1580 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb1,pc->sgmii_to_cl37_auto_enable); 1581 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb1,pc->cl37_bam_to_sgmii_auto_enable); 1582 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,cl37_enable); 1583 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb1,cl37_sgmii_enable); 1584 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb1,cl37_bam_enable); 1585 AN_X4_ABI_SP1_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb1,pc->disable_rf_report); 1586 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1,qsgmii_enable); 1587 AN_X4_ABI_SP1_ENSr_USXGMII_ENf_SET(reg_an_enb1,usxgmii_enable); 1588 AN_X4_ABI_SP1_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb1,link_status_echo); 1589 AN_X4_ABI_SP1_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb1,duplex_mode_echo); 1590 AN_X4_ABI_SP1_ENSr_SPEED_ECHOf_SET(reg_an_enb1,speed_echo); 1591 AN_X4_ABI_SP1_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb1,eee_capability_echo); 1592 AN_X4_ABI_SP1_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb1,eee_clock_capability_echo); 1593 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1594 } else if (sub_port == 2) { 1595 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1596 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,0); 1597 AN_X4_ABI_SP2_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb2,pc->sgmii_to_cl37_auto_enable); 1598 AN_X4_ABI_SP2_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb2,pc->cl37_bam_to_sgmii_auto_enable); 1599 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,cl37_enable); 1600 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb2,cl37_sgmii_enable); 1601 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb2,cl37_bam_enable); 1602 AN_X4_ABI_SP2_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb2,pc->disable_rf_report); 1603 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_SET(reg_an_enb2,qsgmii_enable); 1604 AN_X4_ABI_SP2_ENSr_USXGMII_ENf_SET(reg_an_enb2,usxgmii_enable); 1605 AN_X4_ABI_SP2_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb2,link_status_echo); 1606 AN_X4_ABI_SP2_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb2,duplex_mode_echo); 1607 AN_X4_ABI_SP2_ENSr_SPEED_ECHOf_SET(reg_an_enb2,speed_echo); 1608 AN_X4_ABI_SP2_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb2,eee_capability_echo); 1609 AN_X4_ABI_SP2_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb2,eee_clock_capability_echo); 1610 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1611 } else if (sub_port == 3) { 1612 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1613 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,0); 1614 AN_X4_ABI_SP3_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb3,pc->sgmii_to_cl37_auto_enable); 1615 AN_X4_ABI_SP3_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb3,pc->cl37_bam_to_sgmii_auto_enable); 1616 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,cl37_enable); 1617 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb3,cl37_sgmii_enable); 1618 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb3,cl37_bam_enable); 1619 AN_X4_ABI_SP3_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb3,pc->disable_rf_report); 1620 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3,qsgmii_enable); 1621 AN_X4_ABI_SP3_ENSr_USXGMII_ENf_SET(reg_an_enb3,usxgmii_enable); 1622 AN_X4_ABI_SP3_ENSr_LINK_STATUS_ECHOf_SET(reg_an_enb3,link_status_echo); 1623 AN_X4_ABI_SP3_ENSr_DUPLEX_MODE_ECHOf_SET(reg_an_enb3,duplex_mode_echo); 1624 AN_X4_ABI_SP3_ENSr_SPEED_ECHOf_SET(reg_an_enb3,speed_echo); 1625 AN_X4_ABI_SP3_ENSr_EEE_CAPABILITY_ECHOf_SET(reg_an_enb3,eee_capability_echo); 1626 AN_X4_ABI_SP3_ENSr_EEE_CLOCK_CAPABILITY_ECHOf_SET(reg_an_enb3,eee_clock_capability_echo); 1627 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1628 } 1629 } 1630 return PHYMOD_E_NONE; 1631 } 1632 int qmod16_an_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port) 1633 { 1634 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1635 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp0; 1636 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp1; 1637 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp2; 1638 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp3; 1639 QMOD16_DBG_IN_FUNC_INFO(pc); 1640 1641 cl37_bam_code = 0x0; 1642 over1g_ability = 0x0; 1643 over1g_page_count = 0x0; 1644 1645 1646 if (pc->sc_mode == QMOD16_SC_MODE_AN_CL37) { 1647 cl37_bam_code = pc->cl37_bam_code & 0x1ff; 1648 over1g_ability = pc->cl37_bam_ovr1g_en & 1; 1649 over1g_page_count = pc->cl37_bam_ovr1g_pgcnt & 3; /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1650 } else { 1651 return PHYMOD_E_FAIL; 1652 } 1653 1654 1655 /* cl37 bam abilities 0xc182 */ 1656 if (sub_port == 0) { 1657 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp0); 1658 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp0, over1g_page_count); 1659 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp0, over1g_ability); 1660 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp0, cl37_bam_code); 1661 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp0)); 1662 } else if (sub_port == 1) { 1663 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp1); 1664 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp1, over1g_page_count); 1665 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp1, over1g_ability); 1666 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp1, cl37_bam_code); 1667 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp1)); 1668 } else if (sub_port == 2) { 1669 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp2); 1670 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp2, over1g_page_count); 1671 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp2, over1g_ability); 1672 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp2, cl37_bam_code); 1673 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp2)); 1674 } else if (sub_port == 3) { 1675 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp3); 1676 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp3, over1g_page_count); 1677 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp3, over1g_ability); 1678 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp3, cl37_bam_code); 1679 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp3)); 1680 } 1681 1682 return PHYMOD_E_NONE; 1683 } 1684 1685 int qmod16_autoneg_control(PHYMOD_ST* pc) 1686 { 1687 1688 QMOD16_DBG_IN_FUNC_INFO(pc); 1689 1690 if (pc->sc_mode != QMOD16_SC_MODE_AN_CL37) { 1691 return PHYMOD_E_FAIL; 1692 } 1693 1694 if(pc->usxgmii_mode){ 1695 qmod16_set_qport_spd(pc); 1696 } 1697 1698 qmod16_an_cl37_bam_abilities(pc,pc->sub_port); 1699 1700 qmod16_an_abilities_enables(pc,pc->sub_port); 1701 1702 return PHYMOD_E_NONE; 1703 } /* qmod16_autoneg_control */ 1704 1705 #endif 1706 1707 #ifdef _SDK_QMOD16_ 1708 1709 int qmod16_an_cl37_bam_abilities(PHYMOD_ST* pc, qmod16_an_ability_t *an_ability, int sub_port) 1710 { 1711 1712 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1713 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp0; 1714 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp1; 1715 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp2; 1716 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp3; 1717 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp0; 1718 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp1; 1719 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp2; 1720 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp3; 1721 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp0; 1722 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp1; 1723 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp2; 1724 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp3; 1725 1726 QMOD16_DBG_IN_FUNC_INFO(pc); 1727 1728 cl37_bam_code = 0x1; 1729 over1g_ability = 0x1; 1730 over1g_page_count = 0x0; 1731 1732 /* cl37 bam abilities 0xc182 */ 1733 if (sub_port == 0) { 1734 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp0); 1735 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp0, 1); 1736 MODIFY_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp0); 1737 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp0); 1738 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp0, 1); 1739 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp0, 1); 1740 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp0); 1741 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp0, over1g_page_count); 1742 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp0, over1g_ability); 1743 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp0, cl37_bam_code); 1744 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp0)); 1745 MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp0); 1746 } else if (sub_port == 1) { 1747 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp1); 1748 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp1, 1); 1749 MODIFY_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp1); 1750 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp1); 1751 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp1, 1); 1752 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp1, 1); 1753 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp1); 1754 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp1, over1g_page_count); 1755 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp1, over1g_ability); 1756 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp1, cl37_bam_code); 1757 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp1)); 1758 MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp1); 1759 } else if (sub_port == 2) { 1760 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp2); 1761 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp2, 1); 1762 MODIFY_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp2); 1763 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp2); 1764 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp2, 1); 1765 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp2, 1); 1766 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp2); 1767 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp2, over1g_page_count); 1768 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp2, over1g_ability); 1769 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp2, cl37_bam_code); 1770 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp2)); 1771 MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp2); 1772 } else if (sub_port == 3) { 1773 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp3); 1774 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp3, 1); 1775 MODIFY_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp3); 1776 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp3); 1777 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp3, 1); 1778 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp3, 1); 1779 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp3); 1780 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp3, over1g_page_count); 1781 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp3, over1g_ability); 1782 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp3, cl37_bam_code); 1783 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp3)); 1784 MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp3); 1785 } 1786 return PHYMOD_E_NONE; 1787 } 1788 1789 int qmod16_autoneg_cl37_base_abilities(PHYMOD_ST* pc, qmod16_an_ability_t *an_ability, int sub_port) 1790 { 1791 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 1792 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 1793 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 1794 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 1795 1796 if (sub_port == 0) { 1797 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 1798 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp0, (an_ability->cl37_adv.cl37_sgmii_speed & 7)); 1799 if (an_ability->cl37_adv.an_duplex & QMOD16_AN_HALF_DUPLEX_SET) { 1800 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, 0); 1801 } else { 1802 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, 1); 1803 } 1804 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp0, (an_ability->cl37_adv.an_pause & 3)); 1805 1806 if (an_ability->cl37_adv.an_bam_speed) { 1807 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 0); 1808 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, 0); 1809 } else { 1810 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 1); 1811 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, 1); 1812 } 1813 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 1); 1814 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp0)); 1815 } else if (sub_port == 1) { 1816 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 1817 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp1, (an_ability->cl37_adv.cl37_sgmii_speed & 7)); 1818 if (an_ability->cl37_adv.an_duplex & QMOD16_AN_HALF_DUPLEX_SET) { 1819 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, 0); 1820 } else { 1821 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, 1); 1822 } 1823 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp1, (an_ability->cl37_adv.an_pause & 3)); 1824 1825 if (an_ability->cl37_adv.an_bam_speed) { 1826 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 0); 1827 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, 0); 1828 } else { 1829 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 1); 1830 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, 1); 1831 } 1832 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 1); 1833 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp1)); 1834 } else if (sub_port == 2) { 1835 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 1836 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp2, (an_ability->cl37_adv.cl37_sgmii_speed & 7)); 1837 if (an_ability->cl37_adv.an_duplex & QMOD16_AN_HALF_DUPLEX_SET) { 1838 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, 0); 1839 } else { 1840 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, 1); 1841 } 1842 1843 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp2, (an_ability->cl37_adv.an_pause & 3)); 1844 1845 if (an_ability->cl37_adv.an_bam_speed) { 1846 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 0); 1847 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, 0); 1848 } else { 1849 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 1); 1850 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, 1); 1851 } 1852 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 1); 1853 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp2)); 1854 } else if (sub_port == 3) { 1855 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 1856 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp3, (an_ability->cl37_adv.cl37_sgmii_speed & 7)); 1857 if (an_ability->cl37_adv.an_duplex & QMOD16_AN_HALF_DUPLEX_SET) { 1858 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, 0); 1859 } else { 1860 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, 1); 1861 } 1862 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp3, (an_ability->cl37_adv.an_pause & 3)); 1863 1864 if (an_ability->cl37_adv.an_bam_speed) { 1865 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 0); 1866 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, 0); 1867 } else { 1868 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 1); 1869 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, 1); 1870 } 1871 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 1); 1872 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp3)); 1873 } 1874 1875 return PHYMOD_E_NONE; 1876 } 1877 1878 int qmod16_autoneg_set(PHYMOD_ST* pc, 1879 qmod16_an_ability_t *an_ability_st, int sub_port) /* AUTONEG_SET */ 1880 { 1881 qmod16_autoneg_cl37_base_abilities(pc, an_ability_st, sub_port); 1882 qmod16_an_cl37_bam_abilities(pc, an_ability_st, sub_port); 1883 return PHYMOD_E_NONE; 1884 } 1885 1886 1887 int qmod16_autoneg_control(PHYMOD_ST* pc, qmod16_an_control_t *an_control, int sub_port) 1888 { 1889 uint16_t cl37_bam_enable ; 1890 uint16_t cl37_sgmii_enable, cl37_enable,qsgmii_enable, usxgmii_enable; 1891 uint16_t cl37_restart; 1892 1893 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 1894 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 1895 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 1896 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 1897 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t cl37_base_ability; 1898 QMOD16_DBG_IN_FUNC_INFO(pc); 1899 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(cl37_base_ability); 1900 1901 cl37_bam_enable = 0x0; 1902 cl37_sgmii_enable = 0x0; 1903 qsgmii_enable = 0x0; 1904 usxgmii_enable = 0x0; 1905 cl37_enable = 0x0; 1906 cl37_restart = 0x0; 1907 1908 if (an_control->an_type == QMOD16_AN_MODE_CL37) { 1909 cl37_restart = an_control->enable; 1910 cl37_enable = an_control->enable; 1911 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(cl37_base_ability, 1); 1912 MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, cl37_base_ability); 1913 } else if (an_control->an_type == QMOD16_AN_MODE_SGMII) { 1914 cl37_sgmii_enable = an_control->enable; 1915 cl37_restart = an_control->enable; 1916 cl37_enable = an_control->enable; 1917 } else { 1918 cl37_bam_enable = 1; 1919 cl37_restart = an_control->enable; 1920 cl37_enable = an_control->enable; 1921 } 1922 1923 /* next check if we need to enable qsgmii/uxsgmii mode */ 1924 if (PHYMOD_ACC_F_QMODE_GET(pc)) { 1925 qsgmii_enable = an_control->enable; 1926 } else if (PHYMOD_ACC_F_USXMODE_GET(pc)) { 1927 usxgmii_enable = an_control->enable; 1928 } 1929 1930 /*Setting X4 abilities*/ 1931 if (sub_port == 0) { 1932 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1933 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0, cl37_restart); 1934 1935 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0, cl37_enable); 1936 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb0, cl37_sgmii_enable); 1937 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb0, cl37_bam_enable); 1938 1939 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_SET(reg_an_enb0, qsgmii_enable); 1940 AN_X4_ABI_SP0_ENSr_USXGMII_ENf_SET(reg_an_enb0, usxgmii_enable); 1941 1942 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1943 } else if (sub_port == 1) { 1944 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1945 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1, cl37_restart); 1946 1947 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1, cl37_enable); 1948 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb1, cl37_sgmii_enable); 1949 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb1, cl37_bam_enable); 1950 1951 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1, qsgmii_enable); 1952 AN_X4_ABI_SP1_ENSr_USXGMII_ENf_SET(reg_an_enb1, usxgmii_enable); 1953 1954 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1955 } else if (sub_port == 2) { 1956 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1957 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2, cl37_restart); 1958 1959 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2, cl37_enable); 1960 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb2, cl37_sgmii_enable); 1961 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb2, cl37_bam_enable); 1962 1963 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_SET(reg_an_enb2, qsgmii_enable); 1964 AN_X4_ABI_SP2_ENSr_USXGMII_ENf_SET(reg_an_enb2, usxgmii_enable); 1965 1966 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1967 } else if (sub_port == 3) { 1968 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1969 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3, cl37_restart); 1970 1971 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3, cl37_enable); 1972 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb3, cl37_sgmii_enable); 1973 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb3, cl37_bam_enable); 1974 1975 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3, qsgmii_enable); 1976 AN_X4_ABI_SP3_ENSr_USXGMII_ENf_SET(reg_an_enb3, usxgmii_enable); 1977 1978 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1979 } 1980 1981 if (cl37_restart) { 1982 if (sub_port == 0) { 1983 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1984 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,0); 1985 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1986 } else if (sub_port == 1) { 1987 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1988 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,0); 1989 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1990 } else if (sub_port == 2) { 1991 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1992 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,0); 1993 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1994 } else if (sub_port == 3) { 1995 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1996 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,0); 1997 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1998 } 1999 } 2000 2001 return PHYMOD_E_NONE; 2002 } /* qmod16_autoneg_control */ 2003 #endif /* _SDK_QMOD16_*/ 2004 2005 #ifdef _DV_TB_ 2006 /* 2007 @brief Speeds up DSC and VGA functions for simulation purpose only 2008 @param pc handle to current TSCE context (#PHYMOD_ST) 2009 @returns The value PHYMOD_E_NONE upon successful completion. 2010 @details 2011 2012 This function speeds up PLL, DSC and VGA functions for any speed mode. Please don't 2013 call this function in normal operation. 2014 Set #PHYMOD_ST::per_lane_control to 1 for speed up. 2015 2016 This function is controlled by the following register bit: 2017 2018 \li acq2_timeout, acq1_timeout, acqcdr_timeout (0xc210) -> 0x0421 2019 \li acqvga_timeout (0xc211) -> 0x0800 2020 2021 */ 2022 int qmod16_afe_speed_up_dsc_vga(PHYMOD_ST* pc, int pmd_touched) /* AFE_SPEED_UP_DSC_VGA */ 2023 { 2024 PLL_CALCTL0r_t reg_pll_calctl0; 2025 PLL_CALCTL1r_t reg_pll_calctl1; 2026 PLL_CALCTL2r_t reg_pll_calctl2; 2027 TXFIR_UC_CTL0r_t reg_uc_ctl0; 2028 2029 QMOD16_DBG_IN_FUNC_INFO(pc); 2030 2031 DSC_SM_CTL4r_t reg_ctrl4; 2032 2033 PLL_CALCTL0r_CLR(reg_pll_calctl0); 2034 PLL_CALCTL1r_CLR(reg_pll_calctl1); 2035 PLL_CALCTL2r_CLR(reg_pll_calctl2); 2036 TXFIR_UC_CTL0r_CLR(reg_uc_ctl0); 2037 2038 DSC_SM_CTL4r_CLR(reg_ctrl4); 2039 2040 if (pmd_touched == 0) { 2041 /* PLL speed_up begin */ 2042 /* write ( "calib_step_time", 0x52);*/ 2043 PLL_CALCTL0r_CALIB_STEP_TIMEf_SET(reg_pll_calctl0, 0x52); 2044 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CALCTL0r(pc, reg_pll_calctl0)); 2045 2046 /* write ( "freqdet_time", 0x28F);*/ 2047 PLL_CALCTL1r_FREQDET_TIMEf_SET(reg_pll_calctl1, 0x28f); 2048 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CALCTL1r(pc, reg_pll_calctl1)); 2049 2050 /* write ( "calib_cap_charge_time", 0x28);*/ 2051 PLL_CALCTL2r_CALIB_CAP_CHARGE_TIMEf_SET(reg_pll_calctl2, 0x28); 2052 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CALCTL2r(pc, reg_pll_calctl2)); 2053 2054 2055 /*************************/ 2056 #ifdef OLD_CODE 2057 /* refclk_divcnt = 5 (default 16'h186a ) */ 2058 PLL_CAL_CTL5r_REFCLK_DIVCNTf_SET(reg_ctrl5, 0x5); 2059 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL5r(pc, reg_ctrl5)); 2060 2061 /* refclk_divcnt_sel = 7 */ 2062 /* data = 0x7 << PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_SHIFT ; */ 2063 PLL_CAL_CTL6r_REFCLK_DIVCNT_SELf_SET(reg_ctrl6, 0x7); 2064 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL6r(pc, reg_ctrl6)); 2065 2066 /* vco_start_time = 5 */ 2067 /* data = 0x5 << PLL_CAL_COM_CTL_0_VCO_START_TIME_SHIFT ; */ 2068 PLL_CAL_CTL0r_VCO_START_TIMEf_SET(reg_ctrl0, 0x5); 2069 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL0r(pc, reg_ctrl0)); 2070 2071 /* pre_freq_det_time = 8'd100 , retry_time = 8'd100 */ 2072 PLL_CAL_CTL1r_PRE_FREQ_DET_TIMEf_SET(reg_ctrl1, 0xc8); 2073 PLL_CAL_CTL1r_RETRY_TIMEf_SET(reg_ctrl1, 0xff); 2074 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL1r(pc, reg_ctrl1)); 2075 2076 /* res_cal_cntr = 0 win_cal_cntr=1 */ 2077 PLL_CAL_CTL2r_RES_CAL_CNTRf_SET(reg_ctrl2, 0x2); 2078 PLL_CAL_CTL2r_WIN_CAL_CNTRf_SET(reg_ctrl2, 0x1); 2079 2080 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL2r(pc, reg_ctrl2)); 2081 #endif /* OLD_CODE */ 2082 2083 } 2084 /* PLL speed_up end */ 2085 2086 /* write ( "tx_disable_timer_ctrl", 0);*/ 2087 TXFIR_UC_CTL0r_TX_DISABLE_TIMER_CTRLf_SET(reg_uc_ctl0, 0x0); 2088 PHYMOD_IF_ERR_RETURN (MODIFY_TXFIR_UC_CTL0r(pc, reg_uc_ctl0)); 2089 2090 /* DSC speed_up begin */ 2091 DSC_SM_CTL4r_HW_TUNE_TIMEOUTf_SET(reg_ctrl4, 0x1); 2092 DSC_SM_CTL4r_CDR_SETTLE_TIMEOUTf_SET(reg_ctrl4, 0x1); 2093 DSC_SM_CTL4r_ACQ_CDR_TIMEOUTf_SET(reg_ctrl4, 0x4); 2094 2095 PHYMOD_IF_ERR_RETURN (MODIFY_DSC_SM_CTL4r(pc, reg_ctrl4)); 2096 2097 /* DSC speed_up end */ 2098 2099 return PHYMOD_E_NONE; 2100 } 2101 #endif /* _DV_TB_ */ 2102 2103 static int _qmod16_getRevDetails(PHYMOD_ST* pc) 2104 { 2105 MAIN_SERDESIDr_t reg_serdesid; 2106 2107 MAIN_SERDESIDr_CLR(reg_serdesid); 2108 PHYMOD_IF_ERR_RETURN(READ_MAIN_SERDESIDr(pc,®_serdesid)); 2109 return (MAIN_SERDESIDr_GET(reg_serdesid)); 2110 } 2111 2112 #ifdef _DV_TB_ 2113 /** 2114 @brief Init routine sets various operating modes of TSCE. 2115 @param pc handle to current TSCE context (#PHYMOD_ST) 2116 @param pmd_touched 2117 @param spd_intf #qmod_spd_intfc_type 2118 @param pll_mode # to override the pll div 2119 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 2120 @details 2121 2122 This function is called once per TSCE. It cannot be called multiple times 2123 and should be called immediately after reset. Elements of #PHYMOD_ST should be 2124 initialized to required values prior to calling this function. The following 2125 sub-configurations are performed here. 2126 2127 \li Set pll divider for VCO setting in PMD. pll divider is calculated from max_speed. 2128 */ 2129 2130 int qmod16_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, qmod16_spd_intfc_type spd_intf, int pll_mode) /* SET_PLL_MODE */ 2131 { 2132 PLL_CTL8r_t reg_ctl8; 2133 PLL_CTL9r_t reg_ctl9; 2134 int speed; 2135 int pll_ndiv; 2136 int pll_mode_lcl; 2137 2138 QMOD16_DBG_IN_FUNC_INFO(pc); 2139 PLL_CTL8r_CLR(reg_ctl8); 2140 PLL_CTL9r_CLR(reg_ctl9); 2141 2142 if (pmd_touched == 0) { 2143 /* the default values for following register fields are ok */ 2144 /* 2145 write ( "i_pll_sdm_pwrdnb", 1); 2146 2147 write ( "i_pll_frac_mode[1:0]", 2'b10); 2148 2149 if (pll_integer_mode) { 2150 write ( "i_ndiv_frac_h[13:0]" 0); 2151 write ( "i_ndiv_frac_l[3:0]" 0); 2152 } else { 2153 write ( "i_ndiv_frac_h[13:0]" <value>); 2154 write ( "i_ndiv_frac_l[3:0]" <value>); 2155 } 2156 2157 if (pll_integer_mode) { 2158 write ( "i_ndiv_dither_en", 0); 2159 } else { 2160 write ( "i_ndiv_dither_en", 1); 2161 } 2162 */ 2163 2164 qmod16_get_mapped_speed(spd_intf, &speed); 2165 /*Support Override PLL DIV */ 2166 if(pll_mode & 0x80000000) { 2167 pll_mode_lcl = pll_mode & 0x3ff; 2168 get_pll_ndiv(pll_mode_lcl, &pll_ndiv); 2169 PLL_CTL8r_I_NDIV_INTf_SET(reg_ctl8, (pll_ndiv) & 0x0000ffff); 2170 } else { 2171 get_pll_ndiv(sc_pmd_entry[speed].pll_mode, &pll_ndiv); 2172 PLL_CTL8r_I_NDIV_INTf_SET(reg_ctl8, pll_ndiv); 2173 } 2174 2175 /*if( pc->verbosity) {*/ 2176 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, PLL_CTL8r_I_NDIV_INTf_GET(reg_ctl8)); 2177 printf("%-22s: main0_setup=%x\n", __func__, PLL_CTL8r_I_NDIV_INTf_GET(reg_ctl8)); 2178 /*}*/ 2179 2180 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CTL8r(pc, reg_ctl8)); 2181 2182 /* write ( "mmd_resetb" 0); */ 2183 PLL_CTL9r_MMD_RESETBf_SET(reg_ctl9, 0); 2184 2185 /* dummy read to kill some time* */ 2186 PHYMOD_IF_ERR_RETURN (READ_PLL_CTL8r(pc, ®_ctl8)); 2187 2188 /* write ( "mmd_resetb" 1); */ 2189 /* mmd_resetb should be asserted and deasserted every time a different divider value is programmed. */ 2190 PLL_CTL9r_MMD_RESETBf_SET(reg_ctl9, 1); 2191 2192 } 2193 2194 return PHYMOD_E_NONE; 2195 2196 } /* qmod_set_pll_mode(PHYMOD_ST* pc) */ 2197 #endif 2198 2199 #ifdef _DV_TB_ 2200 /** 2201 @brief set the AN tick overrides 2202 @param pc handle to current TSCE context (#PHYMOD_ST) 2203 @param tick_override 2204 @param numerator 2205 @param denominator 2206 @returns PHYMOD_E_NONE if successful. 2207 @details 2208 */ 2209 int qmod16_tick_override_set(PHYMOD_ST* pc, int tick_override, int numerator, int denominator) 2210 { 2211 return PHYMOD_E_NONE; 2212 2213 } 2214 #endif /* _DV_TB_ */ 2215 2216 /** 2217 @brief Set the AN Portmode and Single Port for AN of TSCE. 2218 @param pc handle to current TSCE context (#PHYMOD_ST) 2219 @param number_of_lanes 2220 @param starting lane #port no. 2221 @param single_port 2222 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 2223 @details 2224 2225 This function can be called multiple times.Elements of #PHYMOD_ST should be 2226 initialized to required values prior to calling this function. The following 2227 sub-configurations are performed here. 2228 2229 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 2230 2231 */ 2232 #ifdef _DV_TB_ 2233 int qmod16_set_an_port_mode(PHYMOD_ST* pc) /* SET_AN_PORT_MODE */ 2234 { 2235 uint16_t data; /*, mask;*/ 2236 /* 2237 PHYMOD_ST pc_10G_X1; 2238 PHYMOD_ST* pc_10G_X1_tmp; 2239 PHYMOD_ST pc_40G_X4; 2240 PHYMOD_ST* pc_40G_X4_tmp; 2241 PHYMOD_ST pc_100G_X4; 2242 PHYMOD_ST* pc_100G_X4_tmp; 2243 */ 2244 MAIN_SETUPr_t reg_main_setup; 2245 2246 CL37_RESTARTr_t reg_cl37_restart_timers; 2247 CL37_ACKr_t reg_cl37_ack_timers; 2248 CL37_ERRr_t reg_cl37_err_timers; 2249 CL37_SYNC_STS_FILTER_TMRr_t reg_an_sync_stat_fil_timer; 2250 LNK_UP_TYPEr_t reg_link_up_timer; 2251 SGMII_CL37_TMR_TYPEr_t reg_an_cl37_sgmii_tmr; 2252 MAIN_TICK_CTL1r_t reg_tick_ctrl; 2253 MAIN_TICK_CTL0r_t reg_tick_ctrl0; 2254 IGNORE_LNK_TMR_TYPEr_t reg_ignore_link_timers; 2255 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_t reg_inhbt_not_cl72_timers; 2256 2257 BAM_SPD_PRI_5_0r_t reg_bam_pri5; 2258 OUI_LWRr_t reg_an_oui_lower; 2259 OUI_UPRr_t reg_an_oui_upper; 2260 SC_X1_TX_RST_CNTr_t reg_sc_rst_cnt; 2261 2262 QMOD16_DBG_IN_FUNC_INFO(pc); 2263 MAIN_SETUPr_CLR(reg_main_setup); 2264 2265 data=0; 2266 2267 /*Ref clock selection*/ 2268 data = main0_refClkSelect_clk_156p25MHz; 2269 2270 /*For AN port mode should be always QUAD*/ 2271 2272 PHYMOD_IF_ERR_RETURN (READ_MAIN_SETUPr(pc, ®_main_setup)); 2273 2274 MAIN_SETUPr_REFCLK_SELf_SET(reg_main_setup, data); 2275 data = 0; 2276 2277 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SETUPr(pc,reg_main_setup)); 2278 2279 /*Tick over_write enable*/ 2280 MAIN_TICK_CTL1r_CLR(reg_tick_ctrl); 2281 MAIN_TICK_CTL0r_CLR(reg_tick_ctrl0); 2282 2283 MAIN_TICK_CTL1r_TICK_OVERRIDEf_SET(reg_tick_ctrl, pc->an_tick_override); 2284 MAIN_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(reg_tick_ctrl, (pc->an_tick_numerator & 0x7fff0) >> 4); 2285 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_TICK_CTL1r(pc, reg_tick_ctrl)); 2286 2287 data=0; 2288 /*Setting numerator to 0x10 and denominator to 0x1 for CL37*/ 2289 MAIN_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_tick_ctrl0,(pc->an_tick_denominator & 0x3ff)); 2290 MAIN_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_tick_ctrl0,(pc->an_tick_numerator & 0xf)); 2291 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_TICK_CTL0r(pc, reg_tick_ctrl0)); 2292 2293 /*0x9250 AN_X1_TIMERS_cl37_restart */ 2294 CL37_RESTARTr_CLR(reg_cl37_restart_timers); 2295 data = pc->cl37_restart_timer_period; 2296 if (data == 0) 2297 data = 0x1f; 2298 CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_SET(reg_cl37_restart_timers, data); 2299 PHYMOD_IF_ERR_RETURN(WRITE_CL37_RESTARTr(pc, reg_cl37_restart_timers)); 2300 /*0x9251 AN_X1_TIMERS_cl37_ack */ 2301 CL37_ACKr_CLR(reg_cl37_ack_timers); 2302 data = pc->cl37_ack_timer_period; 2303 if (data == 0) 2304 data = 0x1f; 2305 CL37_ACKr_CL37_ACK_TIMER_PERIODf_SET(reg_cl37_ack_timers, data); 2306 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ACKr(pc, reg_cl37_ack_timers)); 2307 /*0x9252 AN_X1_TIMERS_cl37_error */ 2308 CL37_ERRr_CLR(reg_cl37_err_timers); 2309 data = pc->cl37_error_timer_period; 2310 CL37_ERRr_CL37_ERROR_TIMER_PERIODf_SET(reg_cl37_err_timers, data); 2311 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ERRr(pc, reg_cl37_err_timers)); 2312 /*0x9253 AN_X1_TIMERS_cl37_sync_status_filter_timer*/ 2313 data = pc->cl37_sync_status_filter; 2314 CL37_SYNC_STS_FILTER_TMRr_CLR(reg_an_sync_stat_fil_timer); 2315 CL37_SYNC_STS_FILTER_TMRr_CL37_SYNC_STATUS_FILTER_TIMER_PERIODf_SET(reg_an_sync_stat_fil_timer, data); 2316 PHYMOD_IF_ERR_RETURN(WRITE_CL37_SYNC_STS_FILTER_TMRr(pc, reg_an_sync_stat_fil_timer)); 2317 /*TBD::0x9254 AN_X1_TIMERS_link_up_typ*/ 2318 data = pc->cl37_sgmii_timer_period; 2319 SGMII_CL37_TMR_TYPEr_CLR(reg_an_cl37_sgmii_tmr); 2320 SGMII_CL37_TMR_TYPEr_SGMII_TIMERf_SET(reg_an_cl37_sgmii_tmr, data); 2321 PHYMOD_IF_ERR_RETURN(WRITE_SGMII_CL37_TMR_TYPEr(pc, reg_an_cl37_sgmii_tmr)); 2322 /*TBD::0x9255 AN_X1_TIMERS_sgmii_cl73_timer_type*/ 2323 if (pc->an_tick_override) 2324 data = 100; 2325 else 2326 data = 2; 2327 LNK_UP_TYPEr_CLR(reg_link_up_timer); 2328 LNK_UP_TYPEr_SET(reg_link_up_timer, data); 2329 PHYMOD_IF_ERR_RETURN(WRITE_LNK_UP_TYPEr(pc, reg_link_up_timer)); 2330 /*0x9256 AN_X1_TIMERS_ignore_link */ 2331 IGNORE_LNK_TMR_TYPEr_CLR(reg_ignore_link_timers); 2332 data = pc->an_ignore_link_timer; 2333 IGNORE_LNK_TMR_TYPEr_SET(reg_ignore_link_timers, data); 2334 PHYMOD_IF_ERR_RETURN(WRITE_IGNORE_LNK_TMR_TYPEr(pc, reg_ignore_link_timers)); 2335 /*0x9256 AN_X1_TIMERS_link_fail_inhbt_tmr_not_cl72 */ 2336 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_CLR(reg_inhbt_not_cl72_timers); 2337 data = pc->link_fail_inhibit_timer_not_cl72_period; 2338 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_SET(reg_inhbt_not_cl72_timers, data); 2339 PHYMOD_IF_ERR_RETURN(WRITE_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr(pc, reg_inhbt_not_cl72_timers)); 2340 /*TBD::0x9263 sc_x1_control_tx_reset_count*/ 2341 data = pc->tx_reset_count; 2342 SC_X1_TX_RST_CNTr_CLR(reg_sc_rst_cnt); 2343 SC_X1_TX_RST_CNTr_TX_RESET_COUNTf_SET(reg_sc_rst_cnt, data); 2344 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_TX_RST_CNTr(pc, reg_sc_rst_cnt)); 2345 /*0x9240 AN_X1_CONTROL_oui_upper */ 2346 data = (pc->oui_upper_data & 0xff); 2347 OUI_UPRr_CLR(reg_an_oui_upper); 2348 OUI_UPRr_OUI_UPPER_DATAf_SET(reg_an_oui_upper, data); 2349 PHYMOD_IF_ERR_RETURN(WRITE_OUI_UPRr(pc, reg_an_oui_upper)); 2350 /*0x9241 AN_X1_CONTROL_oui_lower */ 2351 data = ((pc->oui_lower_data)); 2352 OUI_LWRr_CLR(reg_an_oui_lower); 2353 OUI_LWRr_OUI_LOWER_DATAf_SET(reg_an_oui_lower, data); 2354 PHYMOD_IF_ERR_RETURN(WRITE_OUI_LWRr(pc, reg_an_oui_lower)); 2355 /*0x9242 AN_X1_CONTROL_BAM_SPEED_PRI_5_0 */ 2356 data = ((pc->bam_spd_pri_5_0)); 2357 BAM_SPD_PRI_5_0r_CLR(reg_bam_pri5); 2358 BAM_SPD_PRI_5_0r_SET(reg_bam_pri5, data); 2359 PHYMOD_IF_ERR_RETURN(WRITE_BAM_SPD_PRI_5_0r(pc, reg_bam_pri5)); 2360 return PHYMOD_E_NONE; 2361 } /* qmod16_set_an_port_mode(PHYMOD_ST* pc) */ 2362 #endif 2363 2364 #ifdef _SDK_QMOD16_ 2365 int qmod16_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) /* SET_AN_PORT_MODE */ 2366 { 2367 MAIN_SETUPr_t mode_reg; 2368 READ_MAIN_SETUPr(pc, &mode_reg); 2369 2370 MAIN_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, single_port); 2371 PHYMOD_IF_ERR_RETURN( MODIFY_MAIN_SETUPr(pc, mode_reg)); 2372 return PHYMOD_E_NONE; 2373 } 2374 #endif /* _SDK_QMOD16_ */ 2375 2376 int qmod16_refclk_set(PHYMOD_ST* pc, qmod16_ref_clk_t refclk) 2377 { 2378 MAIN_SETUPr_t reg_setup; 2379 TOP_USER_CTL0r_t dig_top_user_reg; 2380 2381 MAIN_SETUPr_CLR(reg_setup); 2382 PHYMOD_IF_ERR_RETURN(READ_MAIN_SETUPr(pc, ®_setup)); 2383 PHYMOD_IF_ERR_RETURN(READ_TOP_USER_CTL0r(pc, &dig_top_user_reg)); 2384 2385 if (refclk == QMOD16REFCLK125MHZ) { 2386 MAIN_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_125MHz); 2387 TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x1f4); 2388 } else if (refclk == QMOD16REFCLK156MHZ) { 2389 MAIN_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_156p25MHz); 2390 TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_reg, 0x271); 2391 }else { 2392 /* not supported */ 2393 return PHYMOD_E_FAIL; 2394 } 2395 2396 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SETUPr(pc,reg_setup)); 2397 PHYMOD_IF_ERR_RETURN(MODIFY_TOP_USER_CTL0r(pc, dig_top_user_reg)); 2398 2399 return PHYMOD_E_NONE; 2400 } 2401 2402 2403 /** 2404 @brief Sets loopback mode at PCS/PMD parallel interface. (PCS gloop). 2405 @param pc handle to current TSCE context (#PHYMOD_ST) 2406 @param enable loopbacks. 2407 @returns The value PHYMOD_E_NONE upon successful completion 2408 2409 This function sets the TX-to-RX digital loopback mode at the PCS/PMD parallel interface, which is set 2410 based on port_type. 2411 2412 \li 0:1 : Enable TX->RX loopback 2413 \li 0:0 : Disable TX->RX loopback 2414 2415 Note that this function can program <B>multiple lanes simultaneously</B>. 2416 2417 */ 2418 int qmod16_tx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int num_lanes) /* TX_LOOPBACK_CONTROL */ 2419 { 2420 BCMI_QTC_XGXS_MAIN_LPBK_CTLr_t reg_lb_ctrl; 2421 BCMI_QTC_XGXS_PMD_X4_OVRRr_t reg_pmd_ovr; 2422 BCMI_QTC_XGXS_PMD_X4_CTLr_t reg_pmd_ctrl; 2423 uint16_t lane_mask, data, tmp_data, i; 2424 2425 QMOD16_DBG_IN_FUNC_INFO(pc); 2426 lane_mask = 0; 2427 READ_MAIN_LPBK_CTLr(pc, ®_lb_ctrl); 2428 tmp_data = MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2429 PMD_X4_OVRRr_CLR(reg_pmd_ovr); 2430 PMD_X4_CTLr_CLR(reg_pmd_ctrl); 2431 2432 2433 data = 0; 2434 for (i = 0; i < num_lanes; i++) { 2435 lane_mask |= 1 << (starting_lane + i); 2436 data |= enable << (starting_lane + i); 2437 } 2438 2439 tmp_data &= ~lane_mask; 2440 tmp_data |= data; 2441 MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, tmp_data); 2442 2443 PHYMOD_IF_ERR_RETURN 2444 (MODIFY_MAIN_LPBK_CTLr(pc, reg_lb_ctrl)); 2445 2446 /* signal_detect and rx_lock */ 2447 if (enable) { 2448 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 1); 2449 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 1); 2450 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 1); 2451 } else { 2452 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 0); 2453 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 0); 2454 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 0); 2455 } 2456 2457 PHYMOD_IF_ERR_RETURN 2458 (MODIFY_PMD_X4_OVRRr(pc, reg_pmd_ovr)); 2459 2460 /* set tx_disable */ 2461 if (enable) { 2462 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 1); 2463 } else { 2464 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 0); 2465 } 2466 /* mask = PMD_X4_CONTROL_TX_DISABLE_MASK ; */ 2467 PHYMOD_IF_ERR_RETURN 2468 (MODIFY_PMD_X4_CTLr(pc, reg_pmd_ctrl)); 2469 /* When the phy is put in gloop, the rx clk changes, so need to reset the rxp to clear the rx pipe */ 2470 qmod16_rx_lane_control_set(pc, 1); 2471 2472 return PHYMOD_E_NONE; 2473 } 2474 2475 2476 int qmod16_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable) /* TX_LOOPBACK_get */ 2477 { 2478 MAIN_LPBK_CTLr_t loopReg; 2479 READ_MAIN_LPBK_CTLr(pc, &loopReg); 2480 *enable = MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(loopReg); 2481 2482 return PHYMOD_E_NONE; 2483 } 2484 2485 int qmod16_rx_loopback_get(PHYMOD_ST* pc, uint32_t *enable) /* TX_LOOPBACK_get */ 2486 { 2487 MAIN_LPBK_CTLr_t loopReg; 2488 READ_MAIN_LPBK_CTLr(pc, &loopReg); 2489 *enable = MAIN_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(loopReg); 2490 2491 return PHYMOD_E_NONE; 2492 } 2493 2494 #ifdef _DV_TB_ 2495 /*! 2496 @brief Sets loopback mode at PMD serial interface. (gloop(PCS) + PMD) 2497 @param pc handle to current TSCE context (#PHYMOD_ST) 2498 @param cntl select tx/rx loopback 2499 @returns The value PHYMOD_E_NONE upon successful completion 2500 2501 This function sets the PMD TX-to-RX digital loopback mode. 2502 2503 \li 0:1 : Enable TX->RX loopback 2504 \li 0:0 : Disable TX->RX loopback 2505 2506 Note that this function can program <B>multiple lanes simultaneously</B>. 2507 As an example, to enable gloop on all lanes, 2508 set #PHYMOD_ST::per_lane_control to 0x01010101 2509 2510 */ 2511 int qmod16_tx_pmd_loopback_control(PHYMOD_ST* pc, int cntl) /* TX_PMD_LOOPBACK_CONTROL */ 2512 { 2513 BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_CFGr_t reg_lpbk_cfg; 2514 2515 QMOD16_DBG_IN_FUNC_INFO(pc); 2516 TLB_RX_DIG_LPBK_CFGr_CLR(reg_lpbk_cfg); 2517 READ_TLB_RX_DIG_LPBK_CFGr(pc, ®_lpbk_cfg); 2518 2519 /*cntl = (pc-> pmd_gloop);*/ 2520 if (cntl) { 2521 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 1); 2522 } else { 2523 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 0); 2524 } 2525 PHYMOD_IF_ERR_RETURN 2526 (WRITE_TLB_RX_DIG_LPBK_CFGr(pc, reg_lpbk_cfg)); 2527 return PHYMOD_E_NONE; 2528 2529 } 2530 #endif 2531 2532 /** 2533 @brief Sets loopback mode at PCS serial interface. (pcs -> rloop) 2534 @param pc handle to current TSCE context (#PHYMOD_ST) 2535 @returns The value PHYMOD_E_NONE upon successful completion 2536 2537 This function sets the RX-to-TX(PCS) Remote loopback mode, based on port_type. 2538 2539 \li 0:1 : Enable RX->TX loopback 2540 \li 0:0 : Disable RX->TX loopback 2541 2542 Note that this function can program <B>multiple lanes simultaneously</B>. 2543 As an example, to enable gloop on all lanes, 2544 set #PHYMOD_ST::per_lane_control to 0x01010101 2545 2546 */ 2547 int qmod16_rx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int port_type) /* RX_LOOPBACK_CONTROL */ 2548 { 2549 MAIN_LPBK_CTLr_t reg_lb_ctrl; 2550 TX_PI_CTL5r_t reg_tx_pi_ctl5; 2551 /*TLB_TX_TX_PI_LOOP_TIMING_CFGr_t reg_lb_timing; */ 2552 TX_PI_CTL0r_t reg_com_ctrl; 2553 uint16_t lane_mask, data, data_temp; 2554 2555 QMOD16_DBG_IN_FUNC_INFO(pc); 2556 MAIN_LPBK_CTLr_CLR(reg_lb_ctrl); 2557 TX_PI_CTL5r_CLR(reg_tx_pi_ctl5); 2558 /* TLB_TX_TX_PI_LOOP_TIMING_CFGr_CLR(reg_lb_timing); */ 2559 TX_PI_CTL0r_CLR(reg_com_ctrl); 2560 2561 lane_mask = 0; 2562 switch (port_type) { 2563 case QMOD16_MULTI_PORT: lane_mask = (1 << (starting_lane%4)); break; 2564 case QMOD16_TRI1_PORT: lane_mask = ((starting_lane%4)==2)?0xc : (1 << (starting_lane%4)); break; 2565 case QMOD16_TRI2_PORT: lane_mask = ((starting_lane%4)==0)?0x3 : (1 << (starting_lane%4)); break; 2566 case QMOD16_DXGXS: lane_mask = ((starting_lane%4)==0)?0x3 : 0xc; break; 2567 case QMOD16_SINGLE_PORT: lane_mask = 0xf; break; 2568 default: break ; 2569 } 2570 data = enable ? lane_mask : 0; 2571 2572 PHYMOD_IF_ERR_RETURN 2573 (READ_MAIN_LPBK_CTLr(pc, ®_lb_ctrl)); 2574 2575 data_temp = MAIN_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2576 data_temp = data_temp & ~lane_mask; 2577 data = data | data_temp; 2578 2579 TX_PI_CTL5r_TX_PI_REPEATER_MODE_ENf_SET(reg_tx_pi_ctl5, 0); 2580 PHYMOD_IF_ERR_RETURN 2581 (MODIFY_TX_PI_CTL5r(pc, reg_tx_pi_ctl5)); 2582 2583 TX_PI_CTL0r_TX_PI_ENf_SET(reg_com_ctrl, 1); 2584 TX_PI_CTL0r_TX_PI_JITTER_FILTER_ENf_SET(reg_com_ctrl, 1); 2585 PHYMOD_IF_ERR_RETURN 2586 (MODIFY_TX_PI_CTL0r(pc, reg_com_ctrl)); 2587 2588 /* wait for 25 us here*/ 2589 2590 TX_PI_CTL0r_CLR(reg_com_ctrl); 2591 TX_PI_CTL0r_TX_PI_EXT_CTRL_ENf_SET(reg_com_ctrl, 1); 2592 PHYMOD_IF_ERR_RETURN 2593 (MODIFY_TX_PI_CTL0r(pc, reg_com_ctrl)); 2594 2595 MAIN_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, data ); 2596 PHYMOD_IF_ERR_RETURN 2597 (MODIFY_MAIN_LPBK_CTLr(pc, reg_lb_ctrl)); 2598 2599 return PHYMOD_E_NONE; 2600 } 2601 2602 /*! 2603 @brief get port speed configured 2604 @param pc handle to current TSCE context (#PHYMOD_ST) 2605 @param get the resolved speed cfg in the spd_intf 2606 @returns The value PHYMOD_E_NONE upon successful completion. 2607 @details get port speed configured 2608 */ 2609 int qmod16_spd_intf_get(PHYMOD_ST* pc, int *spd_intf) /* SET_SPD_INTF */ 2610 { 2611 return PHYMOD_E_NONE; 2612 } 2613 2614 /*! 2615 @brief tx lane reset and enable of any particular lane 2616 @param pc handle to current TSCE context (#PHYMOD_ST) 2617 @param enable Enable/disable traffic or reset/unreset lane 2618 @param tx_dis_type enum type #tx_lane_disable_type_t 2619 @param pc handle to current TSCE context (#PHYMOD_ST) 2620 @returns The value PHYMOD_E_NONE upon successful completion. 2621 @details 2622 This function is used to reset tx lane and enable/disable tx lane of any 2623 transmit lane. Set bit 0 of #PHYMOD_ST::per_lane_control to enable the TX_LANE 2624 (1) or disable the TX lane (0). When diable TX lane, two types of operations 2625 are inovked independently. 2626 If #PHYMOD_ST::per_lane_control bit [7:4] = 1, only traffic is disabled. 2627 (QMOD16_TX_LANE_TRAFFIC =0x10) 2628 If bit [7:4] = 2, only reset function is invoked. 2629 (QMOD16_TX_LANE_RESET = 0x20) 2630 2631 */ 2632 int qmod16_tx_lane_control_set(PHYMOD_ST* pc, tx_lane_disable_type_t tx_dis_type) /* TX_LANE_CONTROL */ 2633 { 2634 MISCr_t reg_misc_ctrl; 2635 2636 QMOD16_DBG_IN_FUNC_INFO(pc); 2637 MISCr_CLR(reg_misc_ctrl); 2638 2639 switch (tx_dis_type) { 2640 case QMOD16_TX_LANE_RESET: 2641 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 2642 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2643 MISCr_CLR(reg_misc_ctrl); 2644 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 2645 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2646 break; 2647 case QMOD16_TX_LANE_TRAFFIC_ENABLE: 2648 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 2649 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2650 break; 2651 case QMOD16_TX_LANE_TRAFFIC_DISABLE: 2652 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 2653 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2654 break; 2655 case QMOD16_TX_LANE_RESET_TRAFFIC_ENABLE: 2656 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 2657 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2658 MISCr_CLR(reg_misc_ctrl); 2659 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 2660 MISCr_TX_FIFO_WATERMARKf_SET(reg_misc_ctrl,16); 2661 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2662 break; 2663 case QMOD16_TX_LANE_RESET_TRAFFIC_DISABLE: 2664 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 2665 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2666 MISCr_CLR(reg_misc_ctrl); 2667 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 2668 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2669 break; 2670 default: 2671 break; 2672 } 2673 return PHYMOD_E_NONE; 2674 } 2675 2676 int qmod16_reset(PHYMOD_ST* pc) /* pcs reset CONTROL */ 2677 { 2678 SC_X4_CTLr_t reg; 2679 2680 QMOD16_DBG_IN_FUNC_INFO(pc); 2681 2682 /* write 0 to the speed change */ 2683 SC_X4_CTLr_CLR(reg); 2684 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 2685 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 2686 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg)); 2687 2688 return PHYMOD_E_NONE; 2689 } 2690 2691 /** 2692 @brief Read the 16 bit rev. id value etc. 2693 @param pc handle to current TSCE context (#PHYMOD_ST) 2694 @param *revid int ref. to return revision id to calling function. 2695 @returns The value PHYMOD_E_NONE upon successful completion. 2696 @details 2697 This fucntion reads the revid register that contains core number, revision 2698 number and stores the 16-bit value in the revid 2699 2700 */ 2701 int qmod16_revid_read(PHYMOD_ST* pc, uint32_t *revid) /* REVID_READ */ 2702 { 2703 *revid=_qmod16_getRevDetails(pc); 2704 return PHYMOD_E_NONE; 2705 } 2706 2707 #ifdef _DV_TB_ 2708 /** 2709 @brief Read the 16 bit rev. id value etc. 2710 @param pc handle to current TSCE context (#PHYMOD_ST) 2711 @returns The value PHYMOD_E_NONE upon successful completion 2712 @details Per Port PCS Init 2713 2714 */ 2715 int qmod16_init_pcs(PHYMOD_ST* pc) /* INIT_PCS */ 2716 { 2717 QMOD16_DBG_IN_FUNC_INFO(pc); 2718 _qmod16_set_port_mode_select(pc); 2719 qmod16_rx_lane_control_set(pc, 1); 2720 qmod16_tx_lane_control(pc, 1, 0); /* TX_LANE_CONTROL */ 2721 2722 if ((pc->sc_mode == QMOD16_SC_MODE_AN_CL37)) 2723 _qmod16_init_pcs_an(pc); 2724 else /* Forced Speed */ 2725 _qmod16_init_pcs_fs(pc); 2726 2727 return PHYMOD_E_NONE; 2728 } 2729 #endif 2730 2731 /** 2732 @brief Init the PMD 2733 @param pc handle to current TSCE context (#PHYMOD_ST) 2734 @param pmd_touched If the PMD is already initialized 2735 @returns The value PHYMOD_E_NONE upon successful completion 2736 @details Per core PMD resets (both datapath and entire core) 2737 We only intend to use this function if the PMD has never been initialized. 2738 */ 2739 int qmod16_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched) /* PMD_RESET_SEQ */ 2740 { 2741 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 2742 2743 QMOD16_DBG_IN_FUNC_INFO(pc); 2744 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 2745 2746 if (pmd_touched == 0) { 2747 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 2748 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 2749 PHYMOD_IF_ERR_RETURN(BCMI_QTC_XGXS_WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 2750 } 2751 2752 return PHYMOD_E_NONE; 2753 } 2754 2755 /** 2756 @brief Wait for SC done bit set. 2757 @param pc handle to current TSCE context (#PHYMOD_ST) 2758 @param data handle to return SC_X4_CONTROL_STATUS reg. 2759 @returns The value PHYMOD_E_NONE upon successful completion 2760 @details Wait for SC done bit set. This is a very short wait Hence we allow a 2761 loop here. We never allow looping in tier1 as a rule. All looping should be done 2762 in tier2 and above. 2763 2764 */ 2765 int qmod16_wait_sc_done(PHYMOD_ST* pc, uint16_t *data) 2766 { 2767 static int timeOut = 5000; 2768 int localTimeOut = timeOut; 2769 SC_X4_STSr_t reg_sc_ctrl_sts; 2770 2771 QMOD16_DBG_IN_FUNC_INFO(pc); 2772 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 2773 2774 while (1) { 2775 localTimeOut--; 2776 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2777 if ((SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(reg_sc_ctrl_sts) == 1) || localTimeOut < 1) 2778 break; 2779 } 2780 return PHYMOD_E_NONE; 2781 2782 } 2783 2784 #ifdef _DV_TB_ 2785 /** 2786 @brief Read the 16 bit rev. id value etc. 2787 @param pc handle to current TSCE context (#PHYMOD_ST) 2788 @returns The value PHYMOD_E_NONE upon successful completion 2789 @details Per Port PCS Init 2790 */ 2791 int _qmod16_wait_sc_stats_set(PHYMOD_ST* pc) 2792 { 2793 uint16_t data; 2794 SC_X4_STSr_t reg_sc_ctrl_sts; 2795 2796 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 2797 2798 while (1) { 2799 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2800 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 2801 if (data == 1) 2802 break; 2803 } 2804 return PHYMOD_E_NONE; 2805 } 2806 #endif 2807 2808 /** 2809 @brief Read PCS Link status 2810 @param pc handle to current TSCE context (#PHYMOD_ST) 2811 @param *link Reference for Status of PCS Link 2812 @returns The value PHYMOD_E_NONE upon successful completion 2813 @details Per Port PCS Init 2814 2815 */ 2816 int qmod16_get_pcs_link_status(PHYMOD_ST* pc, uint32_t sub_port, uint32_t *link) 2817 { 2818 BCMI_QTC_XGXS_PCS_LIVE_STSr_t reg_pcs_live_sts; 2819 BCMI_QTC_XGXS_PCS_LATCH_STSr_t reg_pcs_ll_sts; 2820 uint16_t loc_link ; 2821 2822 QMOD16_DBG_IN_FUNC_INFO(pc); 2823 2824 BCMI_QTC_XGXS_PCS_LIVE_STSr_CLR(reg_pcs_live_sts); 2825 BCMI_QTC_XGXS_PCS_LATCH_STSr_CLR(reg_pcs_ll_sts) ; 2826 2827 PHYMOD_IF_ERR_RETURN (BCMI_QTC_XGXS_READ_PCS_LIVE_STSr(pc, ®_pcs_live_sts)); 2828 PHYMOD_IF_ERR_RETURN (BCMI_QTC_XGXS_READ_PCS_LATCH_STSr(pc, ®_pcs_ll_sts)) ; 2829 2830 /* next check if we are in qsgmii mode */ 2831 if (PHYMOD_ACC_F_QMODE_GET(pc) || PHYMOD_ACC_F_USXMODE_GET(pc)) { 2832 switch (sub_port) { 2833 case 0: 2834 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP0f_GET(reg_pcs_live_sts); 2835 if (loc_link) { 2836 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP0f_GET(reg_pcs_ll_sts))?0:1 ; 2837 } 2838 break; 2839 case 1: 2840 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP1f_GET(reg_pcs_live_sts); 2841 if (loc_link) { 2842 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP1f_GET(reg_pcs_ll_sts))?0:1 ; 2843 } 2844 break; 2845 case 2: 2846 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP2f_GET(reg_pcs_live_sts); 2847 if (loc_link) { 2848 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP2f_GET(reg_pcs_ll_sts))?0:1 ; 2849 } 2850 break; 2851 default: 2852 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP3f_GET(reg_pcs_live_sts); 2853 if (loc_link) { 2854 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP3f_GET(reg_pcs_ll_sts))?0:1 ; 2855 } 2856 break; 2857 } 2858 /* *link = BCMI_QTC_XGXS_PCS_LIVE_STSr_GET(reg_pcs_live_sts); */ 2859 } else { 2860 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP0f_GET(reg_pcs_live_sts); 2861 if (loc_link) { 2862 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP0f_GET(reg_pcs_ll_sts))?0:1 ; 2863 } 2864 } 2865 *link = loc_link ; 2866 return PHYMOD_E_NONE; 2867 } /* _SDK_QMOD16_ */ 2868 2869 2870 #ifdef _DV_TB_ 2871 /** 2872 @brief Read the 16 bit rev. id value etc. 2873 @param pc handle to current TSCE context (#PHYMOD_ST) 2874 @returns The value PHYMOD_E_NONE upon successful completion 2875 @details Per Port PCS Init 2876 2877 */ 2878 int qmod16_mld_am_timers_set(PHYMOD_ST* pc,int rx_am_timer_init_val,int tx_am_timer_init_val) /*MLD_AM_TIMERS_SET */ 2879 { 2880 return PHYMOD_E_NONE; 2881 } 2882 #endif 2883 2884 /** 2885 @brief PMD per lane reset 2886 @param pc handle to current TSCE context (#PHYMOD_ST) 2887 @returns The value PHYMOD_E_NONE upon successful completion 2888 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2889 2890 */ 2891 int qmod16_pmd_x4_reset(PHYMOD_ST* pc) /* PMD_X4_RESET */ 2892 { 2893 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2894 2895 QMOD16_DBG_IN_FUNC_INFO(pc); 2896 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2897 PMD_X4_CTLr_LN_RX_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2898 PMD_X4_CTLr_LN_TX_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2899 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2900 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 2901 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2902 2903 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2904 PMD_X4_CTLr_LN_RX_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2905 PMD_X4_CTLr_LN_TX_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2906 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2907 PMD_X4_CTLr_LN_TX_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 2908 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 2909 2910 return PHYMOD_E_NONE; 2911 } 2912 2913 #ifdef _DV_TB_ 2914 /** 2915 @brief Initialize the PMD in independent mode. (No PCS involved) 2916 @param pc handle to current TSCE context (#PHYMOD_ST) 2917 @param pmd_touched 2918 @param uc_active 2919 @param spd_intf #qmod_spd_intfc_type 2920 @param t_pma_os_mode per lane OS Mode in PMD 2921 @returns The value PHYMOD_E_NONE upon successful completion 2922 @details Per Port PMD Init done by software 2923 2924 */ 2925 int qmod16_init_pmd_sw(PHYMOD_ST* pc, int pmd_touched, int uc_active, 2926 qmod16_spd_intfc_type spd_intf, int t_pma_os_mode) /* INIT_PMD_SW */ 2927 { 2928 QMOD16_DBG_IN_FUNC_INFO(pc); 2929 qmod16_init_pmd(pc, pmd_touched, uc_active); 2930 qmod16_pmd_osmode_set(pc, spd_intf, t_pma_os_mode); 2931 return PHYMOD_E_NONE; 2932 } 2933 2934 /** 2935 @brief Initialize PMD. for both PCS and independent modes. 2936 @param pc handle to current TSCE context (#PHYMOD_ST) 2937 @param pmd_touched Indicates this PMD was previously initialized for another 2938 port in the same core. 2939 @param uc_active Actually means PMD config. will come from PCS and not TMod 2940 @returns PHYMOD_E_NONE upon success, PHYMOD_E_FAIL else. 2941 @details Per Port PMD Init 2942 2943 */ 2944 int qmod16_init_pmd(PHYMOD_ST* pc, int pmd_touched, int uc_active) /* INIT_PMD */ 2945 { 2946 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwrdwn_ctrl; 2947 TOP_USER_CTL0r_t reg_usr_ctrl; 2948 2949 QMOD16_DBG_IN_FUNC_INFO(pc); 2950 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwrdwn_ctrl); 2951 TOP_USER_CTL0r_CLR(reg_usr_ctrl); 2952 2953 /* REMOVED NOT NEEDED 2954 TXFIR_MISC_CTL1r_CLR(reg_misc1_ctrl); 2955 TXFIR_MISC_CTL1r_DP_RESET_TX_DISABLE_DISf_SET(reg_misc1_ctrl, 1); 2956 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL1r(pc,reg_misc1_ctrl)); 2957 */ 2958 2959 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwrdwn_ctrl, 1); 2960 PHYMOD_IF_ERR_RETURN(MODIFY_RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr(pc, reg_pwrdwn_ctrl)); 2961 2962 if (pmd_touched == 0) { 2963 if(uc_active == 1){ 2964 TOP_USER_CTL0r_UC_ACTIVEf_SET(reg_usr_ctrl, 1); 2965 TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 2966 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 2967 PHYMOD_IF_ERR_RETURN (MODIFY_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 2968 } else{ 2969 TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 2970 PHYMOD_IF_ERR_RETURN (MODIFY_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 2971 } 2972 } 2973 2974 return PHYMOD_E_NONE; 2975 } 2976 #endif 2977 2978 /** 2979 @brief PMD per lane reset get 2980 @param pc handle to current TSCE context (#PHYMOD_ST) 2981 @returns The value PHYMOD_E_NONE upon successful completion 2982 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 2983 */ 2984 int qmod16_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset) /* PMD_X4_RESET */ 2985 { 2986 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 2987 2988 QMOD16_DBG_IN_FUNC_INFO(pc); 2989 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 2990 PHYMOD_IF_ERR_RETURN (READ_PMD_X4_CTLr(pc, ®_pmd_x4_ctrl)); 2991 2992 if (PMD_X4_CTLr_LN_RX_H_RSTBf_GET(reg_pmd_x4_ctrl) && 2993 PMD_X4_CTLr_LN_RX_DP_H_RSTBf_GET(reg_pmd_x4_ctrl)) { 2994 *is_in_reset = 0 ; 2995 } else { 2996 *is_in_reset = 1 ; 2997 } 2998 return PHYMOD_E_NONE; 2999 } 3000 3001 /** 3002 @brief Set Per lane OS mode set in PMD 3003 @param pc handle to current TSCE context (#PHYMOD_ST) 3004 @param spd_intf speed type #qmod16_spd_intfc_type 3005 @param os_mode over sample rate. 3006 @returns The value PHYMOD_E_NONE upon successful completion 3007 @details Per Port PMD Init 3008 3009 */ 3010 int qmod16_pmd_osmode_set(PHYMOD_ST* pc, qmod16_spd_intfc_type spd_intf, int os_mode) /* INIT_PMD */ 3011 { 3012 RXTXCOM_OSR_MODE_CTLr_t reg_osr_mode; 3013 int speed; 3014 3015 QMOD16_DBG_IN_FUNC_INFO(pc); 3016 RXTXCOM_OSR_MODE_CTLr_CLR(reg_osr_mode); 3017 qmod16_get_mapped_speed(spd_intf, &speed); 3018 3019 /*os_mode = 0x0; */ /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 3020 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 3021 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 3022 if (os_mode & 0x80000000) { 3023 os_mode = (os_mode) & 0x0000ffff; 3024 } else { 3025 os_mode = qmod16_sc_pmd_entry[speed].t_pma_os_mode; 3026 } 3027 3028 RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode, 1); 3029 RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 3030 3031 PHYMOD_IF_ERR_RETURN 3032 (MODIFY_RXTXCOM_OSR_MODE_CTLr(pc, reg_osr_mode)); 3033 3034 return PHYMOD_E_NONE; 3035 } 3036 3037 /** 3038 @brief Get Per lane OS mode set in PMD 3039 @param pc handle to current TSCE context (#PHYMOD_ST) 3040 @param os_mode over sample rate. 3041 @returns The value PHYMOD_E_NONE upon successful completion 3042 @details Per Port PMD Init 3043 3044 */ 3045 int qmod16_pmd_osmode_get(PHYMOD_ST* pc, int *os_mode) /* INIT_PMD */ 3046 { 3047 RXTXCOM_OSR_MODE_CTLr_t reg_osr_mode; 3048 3049 QMOD16_DBG_IN_FUNC_INFO(pc); 3050 RXTXCOM_OSR_MODE_CTLr_CLR(reg_osr_mode); 3051 3052 PHYMOD_IF_ERR_RETURN 3053 (READ_RXTXCOM_OSR_MODE_CTLr(pc, ®_osr_mode)); 3054 3055 if (RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRCf_GET(reg_osr_mode) == 1) { 3056 *os_mode = RXTXCOM_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_GET(reg_osr_mode); 3057 } else { 3058 *os_mode = 0xff; 3059 } 3060 return PHYMOD_E_NONE; 3061 } 3062 3063 /** 3064 @brief Generic Override mechanism. Any PCS parameter can be overriden. 3065 @param pc handle to current TSCE context (#PHYMOD_ST) 3066 param cntl bit mask of parameters to override. 3067 @returns The value PHYMOD_E_NONE upon successful completion 3068 @details The cntl encoding is as follows. 3069 3070 NUM_LANES_OEN | 3071 OS_MODE_OEN | 3072 DESKEWMODE_OEN | 3073 DESC2_MODE_OEN | 3074 CL36BYTEDELETEMODE_OEN | 3075 BRCM64B66_DESCRAMBLER_ENABLE_OEN | 3076 CHK_END_EN_OEN | 3077 BLOCK_SYNC_MODE_OEN | 3078 DECODERMODE_OEN | 3079 ENCODEMODE_OEN | 3080 DESCRAMBLERMODE_OEN | 3081 SCR_MODE_OEN 3082 3083 */ 3084 int qmod16_override_set(PHYMOD_ST* pc, override_type_t or_type, uint16_t or_val) /* OVERRIDE_SET */ 3085 { 3086 int or_value; 3087 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 3088 PMA_CTLr_t reg_os_mode_or_val; 3089 PCS_CTLr_t reg_pcs_or_val; 3090 CL36TX_CTLr_t reg_cl36_or_val; 3091 TX_X4_SP0_CRED0r_t reg_sp0_credit_or_val; 3092 3093 QMOD16_DBG_IN_FUNC_INFO(pc); 3094 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 3095 3096 or_value = or_val & 0x0000ffff; 3097 3098 switch (or_type) { 3099 case QMOD16_OVERRIDE_RESET : 3100 /* reset credits */ 3101 WRITE_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3102 3103 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3104 break; 3105 case QMOD16_OVERRIDE_ALL : 3106 /* get info. from table and apply it to all credit regs. */ 3107 break; 3108 case QMOD16_OVERRIDE_QSGMII_EN: 3109 CL36TX_CTLr_CLR(reg_cl36_or_val); 3110 CL36TX_CTLr_QSGMII_ENf_SET(reg_cl36_or_val,or_value); 3111 MODIFY_CL36TX_CTLr(pc,reg_cl36_or_val); 3112 /*Set the override enable*/ 3113 SC_X4_FLD_OVRR_EN0_TYPEr_QSGMII_EN_OENf_SET(reg_or_en0,1); 3114 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3115 break; 3116 case QMOD16_OVERRIDE_CL36BYTEDEL_MODE: 3117 PCS_CTLr_CLR(reg_pcs_or_val); 3118 PCS_CTLr_CL36BYTEDELETEMODEf_SET(reg_pcs_or_val,or_value); 3119 MODIFY_PCS_CTLr(pc,reg_pcs_or_val); 3120 /*Set the override enable*/ 3121 SC_X4_FLD_OVRR_EN0_TYPEr_CL36BYTEDELETEMODE_OENf_SET(reg_or_en0,1); 3122 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3123 break; 3124 case QMOD16_OVERRIDE_OS_MODE: 3125 PMA_CTLr_CLR(reg_os_mode_or_val); 3126 PMA_CTLr_OS_MODEf_SET(reg_os_mode_or_val,or_value); 3127 MODIFY_PMA_CTLr(pc,reg_os_mode_or_val); 3128 /*Set the override enable*/ 3129 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(reg_or_en0,1); 3130 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3131 break; 3132 case QMOD16_OVERRIDE_CREDIT_EN: 3133 TX_X4_SP0_CRED0r_CLR(reg_sp0_credit_or_val); 3134 TX_X4_SP0_CRED0r_CREDITENABLEf_SET(reg_sp0_credit_or_val,or_value); 3135 MODIFY_TX_X4_SP0_CRED0r(pc,reg_sp0_credit_or_val); 3136 /*Set the override enable*/ 3137 SC_X4_FLD_OVRR_EN0_TYPEr_CREDITENABLE_OENf_SET(reg_or_en0,1); 3138 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3139 } 3140 return PHYMOD_E_NONE; 3141 3142 } 3143 3144 3145 /** 3146 @brief Override the credits. 3147 @param pc handle to current TSCE context (#PHYMOD_ST) 3148 @param credit_type type of credit to override #credit_type_t 3149 @param userCredit User override value 3150 @returns The value PHYMOD_E_NONE upon successful completion 3151 @details Credit override mechanism is a seperate function. However it is similar 3152 to other override mechanisms. 3153 3154 */ 3155 int qmod16_credit_override_set(PHYMOD_ST* pc, credit_type_t credit_type, int userCredit) /* CREDIT_OVERRIDE_SET */ 3156 { 3157 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_enable_type; 3158 TX_X4_SP0_CRED0r_t reg_credit0; 3159 TX_X4_SP0_CRED1r_t reg_credit1; 3160 TX_X4_SP0_LOOPCNTr_t reg_loopcnt; 3161 TX_X4_SP0_MAC_CREDGENCNTr_t reg_maccreditgen; 3162 TX_X4_SP0_PCS_CLKCNT0r_t reg_pcs_clk_cnt; 3163 TX_X4_SP0_PCS_CREDGENCNTr_t reg_pcs_creditgen; 3164 3165 QMOD16_DBG_IN_FUNC_INFO(pc); 3166 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_enable_type); 3167 TX_X4_SP0_CRED0r_CLR(reg_credit0); 3168 TX_X4_SP0_CRED1r_CLR(reg_credit1); 3169 TX_X4_SP0_LOOPCNTr_CLR(reg_loopcnt); 3170 TX_X4_SP0_MAC_CREDGENCNTr_CLR(reg_maccreditgen); 3171 TX_X4_SP0_PCS_CLKCNT0r_CLR(reg_pcs_clk_cnt); 3172 TX_X4_SP0_PCS_CREDGENCNTr_CLR(reg_pcs_creditgen); 3173 3174 switch ( credit_type ) { 3175 case QMOD16_CREDIT_RESET: 3176 /* reset credits */ 3177 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 3178 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 0); 3179 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 0); 3180 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 0); 3181 SC_X4_FLD_OVRR_EN0_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 0); 3182 SC_X4_FLD_OVRR_EN0_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 3183 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 0); 3184 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 3185 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 3186 SC_X4_FLD_OVRR_EN0_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 0); 3187 3188 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3189 break; 3190 case QMOD16_CREDIT_TABLE: 3191 /* get info. from table and apply it to all credit regs. */ 3192 break; 3193 case QMOD16_CREDIT_CLOCK_COUNT_0: 3194 /* write to clockcnt0 */ 3195 TX_X4_SP0_CRED0r_CLOCKCNT0f_SET(reg_credit0, userCredit); 3196 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_CRED0r(pc, reg_credit0)); 3197 /*Set the override enable*/ 3198 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 3199 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3200 break; 3201 case QMOD16_CREDIT_CLOCK_COUNT_1: /* (cntl & 0x00020000) */ 3202 /* write to clockcnt1 */ 3203 TX_X4_SP0_CRED1r_CLOCKCNT1f_SET(reg_credit1, userCredit); 3204 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_CRED1r(pc, reg_credit1)); 3205 /*Set the override enable*/ 3206 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 1); 3207 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3208 break; 3209 case QMOD16_CREDIT_LOOP_COUNT_0: 3210 /* write to loopcnt0 */ 3211 TX_X4_SP0_LOOPCNTr_LOOPCNT0f_SET(reg_loopcnt, userCredit); 3212 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_LOOPCNTr(pc, reg_loopcnt)); 3213 /*Set the override enable*/ 3214 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 1); 3215 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3216 break; 3217 case QMOD16_CREDIT_LOOP_COUNT_1: /* (cntl & 0x00080000) */ 3218 /* write to pcs_clockcnt0 */ 3219 TX_X4_SP0_LOOPCNTr_LOOPCNT1f_SET(reg_loopcnt, userCredit); 3220 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_LOOPCNTr(pc, reg_loopcnt)); 3221 /*Set the override enable*/ 3222 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 1); 3223 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3224 break; 3225 case QMOD16_CREDIT_MAC: /* (cntl & 0x00100000) */ 3226 /* write to mac_creditgencnt */ 3227 TX_X4_SP0_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(reg_maccreditgen, userCredit); 3228 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_MAC_CREDGENCNTr(pc, reg_maccreditgen)); 3229 /*Set the override enable*/ 3230 SC_X4_FLD_OVRR_EN0_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 3231 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3232 break; 3233 case QMOD16_CREDIT_PCS_CLOCK_COUNT_0: /* (cntl & 0x00200000) */ 3234 /* write to pcs_clockcnt0 */ 3235 TX_X4_SP0_PCS_CLKCNT0r_PCS_CLOCKCNT0f_SET(reg_pcs_clk_cnt, userCredit); 3236 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3237 /*Set the override enable*/ 3238 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 3239 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3240 break; 3241 case QMOD16_CREDIT_PCS_GEN_COUNT: /* (cntl & 0x00400000) */ 3242 /* write to pcs_creditgencnt */ 3243 TX_X4_SP0_PCS_CREDGENCNTr_PCS_CREDITGENCNTf_SET(reg_pcs_creditgen, userCredit) ; 3244 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CREDGENCNTr(pc, reg_pcs_creditgen)); 3245 /*Set the override enable*/ 3246 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 3247 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3248 break; 3249 case QMOD16_CREDIT_EN: /* (cntl & 0x00800000) */ 3250 /* write to pcs_crden */ 3251 TX_X4_SP0_PCS_CLKCNT0r_PCS_CREDITENABLEf_SET(reg_pcs_clk_cnt, userCredit); 3252 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3253 /*Set the override enable*/ 3254 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 1); 3255 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3256 break; 3257 case QMOD16_CREDIT_PCS_REPCNT: /* (cntl & 0x01000000) */ 3258 /* write to pcs_repcnt */ 3259 TX_X4_SP0_PCS_CLKCNT0r_REPLICATION_CNTf_SET(reg_pcs_clk_cnt, userCredit); 3260 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3261 /*Set the override enable*/ 3262 SC_X4_FLD_OVRR_EN0_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 1); 3263 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3264 break; 3265 case QMOD16_CREDIT_SGMII_SPD: /* (cntl & 0x02000000) */ 3266 /* write to sgmii */ 3267 TX_X4_SP0_CRED0r_SGMII_SPD_SWITCHf_SET(reg_credit0, userCredit); 3268 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_CRED0r(pc, reg_credit0)); 3269 /*Set the override enable*/ 3270 SC_X4_FLD_OVRR_EN0_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 1); 3271 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3272 break; 3273 default: 3274 return PHYMOD_E_FAIL; 3275 break; 3276 } 3277 return PHYMOD_E_NONE; 3278 } /* CREDIT_SET */ 3279 3280 /** 3281 @brief Read the 16 bit rev. id value etc. 3282 @param pc handle to current TSCE context (#PHYMOD_ST) 3283 @returns The value PHYMOD_E_NONE upon successful completion 3284 @details 3285 3286 */ 3287 int qmod16_pmd_lane_reset(PHYMOD_ST* pc) /* PMD_LANE_RESET */ 3288 { 3289 return PHYMOD_E_NONE; 3290 } 3291 3292 #ifdef _DV_TB_ 3293 /** 3294 @brief Control per lane clause 72 auto tuning function (training patterns) 3295 @param pc handle to current TSCE context (#PHYMOD_ST) 3296 @param cl_72_type #cl72_type_t 3297 @returns The value PHYMOD_E_NONE upon successful completion 3298 @details 3299 This function enables/disables clause-72 auto-tuning per lane. It is used 3300 in 40G_KR4, 40G_CR4, 10G_KR modes etc. 3301 Lane is selected via #PHYMOD_ST::lane_select. 3302 This Function is controlled by #PHYMOD_ST::per_lane_control as follows. 3303 3304 \li 0Xxxxxxxx3 (b11): Enable CL72 hardware block 3305 \li 0Xxxxxxxx2 (b01): Disable CL72 hardware block 3306 \li 0Xxxxxxxx0 (b00): no changed. 3307 \li 0Xxxxxxx3- (b011----): Forced enable CL72 under AN. 3308 \li 0Xxxxxxx7- (b111----): Forced disable CL72 under AN. 3309 \li 0Xxxxxxx1- (b001----): Default CL72 under AN. 3310 \li 0Xxxxxxx0- (b000----): no changed 3311 \li 0Xxxxxx100 : read back CL72 HW en bit and put in accData. 3312 3313 */ 3314 int qmod16_clause72_control(PHYMOD_ST* pc, cl72_type_t cl_72_type) /* CLAUSE_72_CONTROL */ 3315 { 3316 return PHYMOD_E_NONE; 3317 } /* clause72_control */ 3318 #endif /* _DV_TB_ */ 3319 3320 #ifdef _DV_TB_ 3321 3322 int qmod16_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status) 3323 { 3324 TLB_RX_PRBS_CHK_LOCK_STSr_t reg_prbs_chk_lock; 3325 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t reg_prbs_err_cnt_msb; 3326 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t reg_prbs_err_cnt_lsb; 3327 int lock, lock_lost, err ; 3328 3329 QMOD16_DBG_IN_FUNC_INFO(pc); 3330 pc->accData = 0 ; 3331 3332 TLB_RX_PRBS_CHK_LOCK_STSr_CLR(reg_prbs_chk_lock); 3333 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_CLR(reg_prbs_err_cnt_msb); 3334 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_CLR(reg_prbs_err_cnt_lsb); 3335 3336 PHYMOD_IF_ERR_RETURN 3337 ( READ_TLB_RX_PRBS_CHK_LOCK_STSr(pc, ®_prbs_chk_lock)); 3338 PHYMOD_IF_ERR_RETURN 3339 (READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(pc, ®_prbs_err_cnt_msb)); 3340 PHYMOD_IF_ERR_RETURN 3341 (READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(pc, ®_prbs_err_cnt_lsb)); 3342 3343 lock = TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock) ? 1 : 0 ; 3344 lock_lost = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb) ? 1 : 0 ; 3345 err = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 3346 err = (err << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 3347 3348 #ifdef _DV_TB_ 3349 printf("prbs_check u=%0d p=%0d ln=%0d lck=%0d lost=%0d err=%0d(H%x L%x)\n", 3350 pc->unit, pc->port, pc->this_lane, lock, lock_lost, err, reg_prbs_err_cnt_msb, reg_prbs_err_cnt_lsb); 3351 #endif 3352 3353 if (TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock)) { 3354 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 3355 /* locked now but lost before */ 3356 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb); 3357 *prbs_status = (*prbs_status << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) | 1 ; /* locked once, so one error at least */ 3358 pc->accData = real_check ? 1 : 0 ; 3359 return PHYMOD_E_FAIL; 3360 } else { 3361 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 3362 *prbs_status = (*prbs_status << 16)| TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 3363 if (err) { 3364 pc->accData = real_check ? 1 : 0 ; 3365 return PHYMOD_E_FAIL; 3366 } 3367 } 3368 } else { 3369 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 3370 *prbs_status = -2 ; /* locked before but lost now */ 3371 pc->accData = real_check ? 1 : 0 ; 3372 return PHYMOD_E_FAIL; 3373 } else { 3374 *prbs_status = -1 ; /* never locked */ 3375 pc->accData = real_check ? 1 : 0 ; 3376 return PHYMOD_E_FAIL; 3377 } 3378 } 3379 return PHYMOD_E_NONE ; 3380 } 3381 #endif /* _DV_TB_ */ 3382 3383 #ifdef _DV_TB_ 3384 3385 int qmod16_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pattern_type, int prbs_check_mode) /* PRBS_MODE */ 3386 { 3387 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 3388 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 3389 /* SC_X4_BYPASSr_t reg_bypass; */ 3390 3391 /*int prbs_check_mode ; */ 3392 int prbs_sel_tx, prbs_inv_tx ; 3393 int prbs_sel_rx, prbs_inv_rx ; 3394 3395 3396 QMOD16_DBG_IN_FUNC_INFO(pc); 3397 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 3398 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 3399 3400 prbs_sel_tx = pattern_type; 3401 prbs_sel_rx = pattern_type; 3402 prbs_inv_tx = prbs_inv; 3403 prbs_inv_rx = prbs_inv; 3404 3405 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(reg_prbs_gen_cfg, prbs_sel_tx); 3406 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(reg_prbs_gen_cfg, prbs_inv_tx); 3407 3408 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 3409 3410 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(reg_prbs_chk_cfg, prbs_check_mode); 3411 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(reg_prbs_chk_cfg, prbs_sel_rx); 3412 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(reg_prbs_chk_cfg, prbs_inv_rx); 3413 3414 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 3415 3416 return PHYMOD_E_NONE; 3417 3418 } /* PRBS_MODE */ 3419 #endif /* _DV_TB_ */ 3420 3421 #ifdef _DV_TB_ 3422 3423 int qmod16_prbs_control(PHYMOD_ST* pc, int prbs_enable) /* PRBS_CONTROL */ 3424 { 3425 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 3426 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 3427 int prbs_rx_en, prbs_tx_en ; 3428 3429 QMOD16_DBG_IN_FUNC_INFO(pc); 3430 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 3431 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 3432 3433 prbs_tx_en = prbs_enable; 3434 prbs_rx_en = prbs_enable; 3435 3436 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(reg_prbs_gen_cfg, prbs_tx_en); 3437 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 3438 3439 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(reg_prbs_chk_cfg, prbs_rx_en); 3440 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 3441 3442 return PHYMOD_E_NONE; 3443 3444 } /* PRBS_CONTROL */ 3445 #endif /* _DV_TB_ */ 3446 3447 #ifdef _DV_TB_ 3448 /** 3449 @brief Sets CJPAT/CRPAT parameters for a particular port 3450 @param pc handle to current TSCE context (#PHYMOD_ST) 3451 @param port handle to current TSCE context (#PHYMOD_ST) 3452 @param pattern_type type of CJPat 3453 @param pkt_number number of packets 3454 @param pkt_size size of packets 3455 @param ipg_size IPG between packets 3456 @returns The value PHYMOD_E_NONE upon successful completion 3457 3458 This function enables either a CJPAT or CRPAT for a particular port. 3459 The speed mode of the lane must be chosen from the enumerated type 3460 #qmod_spd_intfc_type and set in the 3461 #PHYMOD_ST::spd_intf field. To enable CJPAT, set #PHYMOD_ST::per_lane_control to 3462 the value #USE_CJPAT; to enable CRPAT, set #PHYMOD_ST::per_lane_control to the 3463 value #USE_CRPAT. This function is used in tandem with qmod_cjpat_crpat_check(). 3464 3465 */ 3466 3467 int qmod16_cjpat_crpat_mode_set(PHYMOD_ST* pc, qmod16_spd_intfc_type spd_intf, int port, int pattern_type, int pkt_number, int pkt_size, int ipg_size) /* CJPAT_CRPAT_MODE_SET */ 3468 { 3469 3470 int number_pkt, crc_check,intf_type, rx_port_sel, tx_port_sel; 3471 int pkt_size_int, ipg_size_int,payload_type; 3472 uint16_t data16 ; 3473 3474 printf("debug> qmod_cjpat_crpat_mode_set called / port = %x , pattern_type = %x , pkt_number = %x , pkt_size = %x , ipg_size = %x",port,pattern_type, pkt_number, pkt_size, ipg_size); 3475 BCMI_QTC_XGXS_PKTGENCTL1r_t reg_pktgenctl1; 3476 BCMI_QTC_XGXS_PKTGENCTL2r_t reg_pktgenctl2; 3477 BCMI_QTC_XGXS_PAYLOADBYTESr_t payloadbytes; 3478 3479 QMOD16_DBG_IN_FUNC_INFO(pc); 3480 BCMI_QTC_XGXS_PKTGENCTL1r_CLR(reg_pktgenctl1); 3481 BCMI_QTC_XGXS_PKTGENCTL2r_CLR(reg_pktgenctl2); 3482 BCMI_QTC_XGXS_PAYLOADBYTESr_CLR(payloadbytes); 3483 3484 number_pkt = pkt_number ; 3485 crc_check = 1 ; 3486 rx_port_sel= port*4 ; 3487 tx_port_sel= port*4 ; 3488 /* printf("DEBUG>> tx_port_sel = %d", tx_port_sel); */ 3489 3490 pkt_size_int = pkt_size ; 3491 /* pkt_size_int = 1; 3492 ipg_size_int = 8 ;*/ 3493 ipg_size_int = ipg_size ; 3494 3495 /* payload_type = pattern_type; */ 3496 3497 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 3498 payload_type = 0; 3499 } else { 3500 payload_type = pattern_type; 3501 } 3502 3503 3504 /* intf_type 0: XLGMII/XGMII; 1: MIII/GMII */ 3505 3506 intf_type = ((spd_intf == TEMOD_SPD_10_X1_SGMII) | 3507 (spd_intf == TEMOD_SPD_100_X1_SGMII) | 3508 (spd_intf == TEMOD_SPD_1000_X1_SGMII) | 3509 (spd_intf == TEMOD_SPD_10_SGMII) | 3510 (spd_intf == TEMOD_SPD_100_SGMII) | 3511 (spd_intf == TEMOD_SPD_1000_SGMII) | 3512 (spd_intf == TEMOD_SPD_2500) | 3513 (spd_intf == TEMOD_SPD_2500_X1)| 3514 (spd_intf == TEMOD_SPD_10_X1_10)| 3515 (spd_intf == TEMOD_SPD_100_X1_10)| 3516 (spd_intf == TEMOD_SPD_1000_X1_10)| 3517 (spd_intf == TEMOD_SPD_10_X1_12P5)| 3518 (spd_intf == TEMOD_SPD_100_X1_12P5)| 3519 (spd_intf == TEMOD_SPD_1000_X1_12P5)| 3520 (spd_intf == TEMOD_SPD_2500_X1_12P5) 3521 ) ? 0 : 1; 3522 3523 /* if payload type is Repeat 2 Bytes in 0x9040*/ 3524 3525 if (payload_type == 0) { 3526 data16 = 0x2323; 3527 BCMI_QTC_XGXS_PAYLOADBYTESr_BYTE1f_SET(payloadbytes, ((data16 >> 8) & 0xff)); 3528 BCMI_QTC_XGXS_PAYLOADBYTESr_BYTE0f_SET(payloadbytes, (data16 & 0xff)); 3529 BCMI_QTC_XGXS_WRITE_PAYLOADBYTESr(pc,payloadbytes); 3530 } 3531 3532 /* 0x9030 */ 3533 3534 BCMI_QTC_XGXS_PKTGENCTL1r_TX_PORT_SELf_SET(reg_pktgenctl1, tx_port_sel); 3535 BCMI_QTC_XGXS_PKTGENCTL1r_RX_PORT_SELf_SET(reg_pktgenctl1, rx_port_sel); 3536 BCMI_QTC_XGXS_PKTGENCTL1r_RX_PKT_CHECK_ENf_SET(reg_pktgenctl1, crc_check); 3537 BCMI_QTC_XGXS_PKTGENCTL1r_RX_BUS_TYPEf_SET(reg_pktgenctl1, intf_type); 3538 BCMI_QTC_XGXS_PKTGENCTL1r_NUMBER_PKTf_SET(reg_pktgenctl1, number_pkt); 3539 3540 PHYMOD_IF_ERR_RETURN 3541 (BCMI_QTC_XGXS_WRITE_PKTGENCTL1r(pc, reg_pktgenctl1)); 3542 3543 /*BCMI_QTC_XGXS_WRITE_PKTGENCTL1r*/ 3544 3545 /* 0x9031 */ 3546 3547 BCMI_QTC_XGXS_PKTGENCTL2r_IPG_SIZEf_SET(reg_pktgenctl2, ipg_size_int); 3548 BCMI_QTC_XGXS_PKTGENCTL2r_PKT_SIZEf_SET(reg_pktgenctl2, pkt_size_int); 3549 BCMI_QTC_XGXS_PKTGENCTL2r_PAYLOAD_TYPEf_SET(reg_pktgenctl2, payload_type); 3550 BCMI_QTC_XGXS_PKTGENCTL2r_TX_BUS_TYPEf_SET(reg_pktgenctl2, intf_type); 3551 3552 PHYMOD_IF_ERR_RETURN 3553 (BCMI_QTC_XGXS_WRITE_PKTGENCTL2r(pc, reg_pktgenctl2)); 3554 3555 return PHYMOD_E_NONE; 3556 } /* int qmod_cjpat_crpat_mode_set */ 3557 3558 /** 3559 @brief Checks CJPAT/CRPAT parameters for a particular port 3560 @param pc handle to current TSCE context (#PHYMOD_ST) 3561 @returns The value PHYMOD_E_NONE upon successful completion 3562 3563 This function checks for CJPAT or CRPAT for a particular port. The speed mode 3564 of the lane must be chosen from the enumerated type #qmod_spd_intfc_type and 3565 set in the #PHYMOD_ST::spd_intf field. CJPAT/CRPAT must first enabled using 3566 #qmod_cjpat_crpat_control(). The duration of packet transmission is controlled 3567 externally and is the time duration between the two function calls above. 3568 3569 This function compares the CJPAT/CRPAT TX and RX counters and prints the 3570 results. Currently only packet count is supported. 3571 3572 This function reads the following registers: 3573 3574 \li PATGEN1_TXPKTCNT_U (0xC040) Upper 16b of count of Transmitted packets 3575 \li PATGEN1_TXPKTCNT_L (0xC041) Lower 16b of count of Transmitted packets 3576 \li PATGEN1_RXPKTCNT_U (0xC042) Upper 16b of count of Recieved packets 3577 \li PATGEN1_RXPKTCNT_L (0xC043) Lower 16b of count of Recieved packets 3578 \li PKTGEN0_CRCERRORCOUNT (0x9033) CRC error conunt 3579 3580 */ 3581 3582 int qmod16_cjpat_crpat_check(PHYMOD_ST* pc) /* CJPAT_CRPAT_CHECK */ 3583 { 3584 uint32_t sp0_tx_cnt, sp0_rx_cnt ; 3585 uint32_t sp1_tx_cnt, sp1_rx_cnt ; 3586 uint32_t sp2_tx_cnt, sp2_rx_cnt ; 3587 uint32_t sp3_tx_cnt, sp3_rx_cnt ; 3588 3589 3590 /* for SP0 */ 3591 PKT_CTRS_X4_SP0_TXPKTCNT_Ur_t sp0_reg_tx_u; /* To do: change reg_tx_* names by adding SP0, SP1 .. : DONE*/ 3592 PKT_CTRS_X4_SP0_TXPKTCNT_Lr_t sp0_reg_tx_l; 3593 PKT_CTRS_X4_SP0_RXPKTCNT_Ur_t sp0_reg_rx_u; 3594 PKT_CTRS_X4_SP0_RXPKTCNT_Lr_t sp0_reg_rx_l; 3595 3596 /* for SP1 */ 3597 PKT_CTRS_X4_SP1_TXPKTCNT_Ur_t sp1_reg_tx_u; 3598 PKT_CTRS_X4_SP1_TXPKTCNT_Lr_t sp1_reg_tx_l; 3599 PKT_CTRS_X4_SP1_RXPKTCNT_Ur_t sp1_reg_rx_u; 3600 PKT_CTRS_X4_SP1_RXPKTCNT_Lr_t sp1_reg_rx_l; 3601 3602 /* for SP2 */ 3603 PKT_CTRS_X4_SP2_TXPKTCNT_Ur_t sp2_reg_tx_u; 3604 PKT_CTRS_X4_SP2_TXPKTCNT_Lr_t sp2_reg_tx_l; 3605 PKT_CTRS_X4_SP2_RXPKTCNT_Ur_t sp2_reg_rx_u; 3606 PKT_CTRS_X4_SP2_RXPKTCNT_Lr_t sp2_reg_rx_l; 3607 3608 /* for SP3 */ 3609 PKT_CTRS_X4_SP3_TXPKTCNT_Ur_t sp3_reg_tx_u; 3610 PKT_CTRS_X4_SP3_TXPKTCNT_Lr_t sp3_reg_tx_l; 3611 PKT_CTRS_X4_SP3_RXPKTCNT_Ur_t sp3_reg_rx_u; 3612 PKT_CTRS_X4_SP3_RXPKTCNT_Lr_t sp3_reg_rx_l; 3613 3614 3615 CRCERRCNTr_t reg_crc_cnt; 3616 3617 QMOD16_DBG_IN_FUNC_INFO(pc); 3618 3619 /* for SP0 */ /* To do: implement this functionality for all SP and add check for SGMII or QSGMII modes */ 3620 3621 /*Check to be performed */ 3622 if((pc->port== 0)||(pc->port == 4)||(pc->port == 8)||(pc->port == 12)) { 3623 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur_CLR(sp0_reg_tx_u); 3624 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_TXPKTCNT_Ur(pc, &sp0_reg_tx_u); 3625 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr_CLR(sp0_reg_tx_l); 3626 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_TXPKTCNT_Lr(pc, &sp0_reg_tx_l); 3627 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur_CLR(sp0_reg_rx_u); 3628 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_RXPKTCNT_Ur(pc, &sp0_reg_rx_u); 3629 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr_CLR(sp0_reg_rx_l); 3630 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_RXPKTCNT_Lr(pc, &sp0_reg_rx_l); 3631 3632 BCMI_QTC_XGXS_CRCERRCNTr_CLR(reg_crc_cnt); 3633 BCMI_QTC_XGXS_READ_CRCERRCNTr(pc, ®_crc_cnt); 3634 3635 sp0_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur_GET(sp0_reg_tx_u) <<16; 3636 sp0_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr_GET(sp0_reg_tx_l); 3637 3638 sp0_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur_GET(sp0_reg_rx_u) <<16; 3639 sp0_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr_GET(sp0_reg_rx_l); 3640 } 3641 3642 3643 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur_CLR(sp1_reg_tx_u); 3644 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_TXPKTCNT_Ur(pc, &sp1_reg_tx_u); 3645 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr_CLR(sp1_reg_tx_l); 3646 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_TXPKTCNT_Lr(pc, &sp1_reg_tx_l); 3647 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur_CLR(sp1_reg_rx_u); 3648 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_RXPKTCNT_Ur(pc, &sp1_reg_rx_u); 3649 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr_CLR(sp1_reg_rx_l); 3650 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_RXPKTCNT_Lr(pc, &sp1_reg_rx_l); 3651 3652 sp1_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur_GET(sp1_reg_tx_u) <<16; 3653 sp1_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr_GET(sp1_reg_tx_l); 3654 3655 sp1_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur_GET(sp1_reg_rx_u) <<16; 3656 sp1_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr_GET(sp1_reg_rx_l); 3657 3658 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur_CLR(sp2_reg_tx_u); 3659 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_TXPKTCNT_Ur(pc, &sp2_reg_tx_u); 3660 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr_CLR(sp2_reg_tx_l); 3661 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_TXPKTCNT_Lr(pc, &sp2_reg_tx_l); 3662 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur_CLR(sp2_reg_rx_u); 3663 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_RXPKTCNT_Ur(pc, &sp2_reg_rx_u); 3664 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr_CLR(sp2_reg_rx_l); 3665 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_RXPKTCNT_Lr(pc, &sp2_reg_rx_l); 3666 3667 sp2_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur_GET(sp2_reg_tx_u) <<16; 3668 sp2_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr_GET(sp2_reg_tx_l); 3669 3670 sp2_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur_GET(sp2_reg_rx_u) <<16; 3671 sp2_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr_GET(sp2_reg_rx_l); 3672 3673 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur_CLR(sp3_reg_tx_u); 3674 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_TXPKTCNT_Ur(pc, &sp3_reg_tx_u); 3675 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr_CLR(sp3_reg_tx_l); 3676 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_TXPKTCNT_Lr(pc, &sp3_reg_tx_l); 3677 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur_CLR(sp3_reg_rx_u); 3678 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_RXPKTCNT_Ur(pc, &sp3_reg_rx_u); 3679 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr_CLR(sp3_reg_rx_l); 3680 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_RXPKTCNT_Lr(pc, &sp3_reg_rx_l); 3681 3682 sp3_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur_GET(sp3_reg_tx_u) <<16; 3683 sp3_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr_GET(sp3_reg_tx_l); 3684 3685 sp3_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur_GET(sp3_reg_rx_u) <<16; 3686 sp3_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr_GET(sp3_reg_rx_l); 3687 3688 3689 #ifdef _DV_TB_ 3690 pc->accData = 0 ; 3691 /* printf("\n CHECKING \n"); */ 3692 #endif /* _DV_TB_ */ 3693 if( ((sp0_tx_cnt != sp0_rx_cnt) ||(sp0_tx_cnt==0)) ) { 3694 #ifdef _DV_TB_ 3695 3696 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d sp0_tx_cnt=%0d sp0_rx_cnt=%0d mismatch\n", __func__, pc->unit, pc->port, sp0_tx_cnt, sp0_rx_cnt)); 3697 pc->accData = 1; 3698 #endif /* _DV_TB_ */ 3699 return PHYMOD_E_FAIL; 3700 } 3701 /* Check the other cnt regs */ 3702 if( ((sp1_tx_cnt != sp1_rx_cnt) ||(sp1_tx_cnt!=0))||((sp2_tx_cnt != sp2_rx_cnt) ||(sp2_tx_cnt!=0))||((sp3_tx_cnt != sp3_rx_cnt) ||(sp3_tx_cnt!=0)) ) { 3703 #ifdef _DV_TB_ 3704 3705 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d sp1_tx_cnt=%0d sp1_rx_cnt=%0d sp2_tx_cnt=%0d sp2_rx_cnt=%0d sp3_tx_cnt=%0d sp3_rx_cnt=%0d mismatch\n", __func__, pc->unit, pc->port, sp1_tx_cnt, sp1_rx_cnt, sp2_tx_cnt, sp2_rx_cnt, sp3_tx_cnt, sp3_rx_cnt )); 3706 pc->accData = 1; 3707 #endif /* _DV_TB_ */ 3708 return PHYMOD_E_FAIL; 3709 } 3710 3711 3712 if(reg_crc_cnt.crcerrcnt[0]) { 3713 #ifdef _DV_TB_ 3714 3715 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d crc error=%0d\n", __func__, pc->unit, pc->port, reg_crc_cnt.crcerrcnt[0])); 3716 pc->accData = 1; 3717 #endif /* _DV_TB_ */ 3718 return PHYMOD_E_FAIL; 3719 } 3720 3721 return PHYMOD_E_NONE; 3722 } 3723 3724 3725 int qmod16_cjpat_crpat_control(PHYMOD_ST* pc, int enable) /* CJPAT_CRPAT_CONTROL */ 3726 { 3727 3728 PKTGENCTL2r_t reg; 3729 3730 QMOD16_DBG_IN_FUNC_INFO(pc); 3731 PKTGENCTL2r_CLR(reg); 3732 /* 0x9031 */ 3733 PHYMOD_IF_ERR_RETURN 3734 (READ_PKTGENCTL2r(pc, ®)); 3735 3736 if(enable) { 3737 BCMI_QTC_XGXS_PKTGENCTL2r_PKTGEN_ENf_SET(reg, 1); 3738 3739 } else { 3740 BCMI_QTC_XGXS_PKTGENCTL2r_PKTGEN_ENf_SET(reg, 0); 3741 } 3742 PHYMOD_IF_ERR_RETURN 3743 (WRITE_PKTGENCTL2r(pc, reg)); 3744 3745 3746 return PHYMOD_E_NONE; 3747 } 3748 #endif 3749 3750 3751 int qmod16_pcs_lane_swap(PHYMOD_ST *pc, int lane_tx_map, int lane_rx_map) 3752 { 3753 3754 /* unsigned int pcs_map;*/ 3755 MAIN_LN_SWPr_t reg; 3756 QMOD16_DBG_IN_FUNC_INFO(pc) ; 3757 3758 MAIN_LN_SWPr_CLR(reg); 3759 3760 MAIN_LN_SWPr_LOG0_TO_PHY_TX_LNSWAP_SELf_SET(reg, (lane_tx_map >> 0) & 0x3); 3761 MAIN_LN_SWPr_LOG1_TO_PHY_TX_LNSWAP_SELf_SET(reg, (lane_tx_map >> 4) & 0x3); 3762 MAIN_LN_SWPr_LOG2_TO_PHY_TX_LNSWAP_SELf_SET(reg, (lane_tx_map >> 8) & 0x3); 3763 MAIN_LN_SWPr_LOG3_TO_PHY_TX_LNSWAP_SELf_SET(reg, (lane_tx_map >> 12) & 0x3 ); 3764 3765 MAIN_LN_SWPr_LOG0_TO_PHY_RX_LNSWAP_SELf_SET(reg, (lane_rx_map >> 0) & 0x3); 3766 MAIN_LN_SWPr_LOG1_TO_PHY_RX_LNSWAP_SELf_SET(reg, (lane_rx_map >> 4) & 0x3); 3767 MAIN_LN_SWPr_LOG2_TO_PHY_RX_LNSWAP_SELf_SET(reg, (lane_rx_map >> 8) & 0x3); 3768 MAIN_LN_SWPr_LOG3_TO_PHY_RX_LNSWAP_SELf_SET(reg, (lane_rx_map >> 12) & 0x3 ); 3769 3770 PHYMOD_IF_ERR_RETURN 3771 (MODIFY_MAIN_LN_SWPr(pc, reg)) ; 3772 3773 return PHYMOD_E_NONE ; 3774 } 3775 3776 3777 /** 3778 @brief Control pram ablity 3779 @param pc handle to current TSCE context (#PHYMOD_ST) 3780 @param enable Enable value for PRAM set. 3781 @returns The value PHYMOD_E_NONE upon successful completion 3782 @details Per core PMD resets (both datapath and entire core) 3783 We only intend to use this function if the PMD has never been initialized. 3784 */ 3785 int qmod16_pram_abl_enable_set(PHYMOD_ST* pc, int enable) /* PMD_RESET_SEQ */ 3786 { 3787 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 3788 3789 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 3790 3791 PMD_X1_CTLr_PRAM_ABILITYf_SET(reg_pmd_x1_ctrl,enable); 3792 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 3793 3794 return PHYMOD_E_NONE; 3795 } 3796 3797 #ifdef _DV_TB_ 3798 /** 3799 @brief Read the 16 bit rev. id value etc. 3800 @param pc handle to current TSCE context (#PHYMOD_ST) 3801 @returns The value PHYMOD_E_NONE upon successful 3802 @details PCS Init calls this Per Port PCS Init routine 3803 */ 3804 int _qmod16_set_port_mode_select(PHYMOD_ST* pc) 3805 { 3806 MAIN_SETUPr_t reg; 3807 QMOD16_DBG_IN_FUNC_INFO(pc); 3808 3809 3810 MAIN_SETUPr_CLR(reg); 3811 MAIN_SETUPr_MAC_TO_PCS_LANE_MAP_SEL_SGMIIf_SET(reg,pc->pcs_lane_map_sel); 3812 if(pc->tsc_touched == 1) { 3813 MAIN_SETUPr_CLR(reg); 3814 } else { 3815 MAIN_SETUPr_MASTER_PORT_NUMf_SET(reg, pc->master_portnum); 3816 BCMI_QTC_XGXS_MAIN_SETUPr_CL37_10G_VCOf_SET(reg, pc->cl37_10g_vco); 3817 MAIN_SETUPr_PLL_RESET_ENf_SET(reg, 1); 3818 MAIN_SETUPr_MAP_FAULTS_TO_LINK_STATUSf_SET(reg,pc->map_faults_to_link_status); 3819 3820 /* Program the tx shim fifo thresholds for usxgmii mode speeds. */ 3821 if (pc->usxgmii_mode) { 3822 prog_shim_ff_threshold(pc); 3823 } 3824 } 3825 3826 MAIN_SETUPr_SINGLE_PORT_MODEf_SET(reg, pc->single_port_mode); 3827 if(pc->sc_mode == TEMOD_SC_MODE_AN_CL37) { 3828 MAIN_SETUPr_REFCLK_SELf_SET(reg, pc->refclk); 3829 } else { 3830 MAIN_SETUPr_REFCLK_SELf_SET(reg, pc->refclk); 3831 } 3832 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN_SETUPr(pc, reg)); 3833 3834 return PHYMOD_E_NONE; 3835 } 3836 #endif 3837 3838 #ifdef _DV_TB_ 3839 /** 3840 @brief Read the 16 bit rev. id value etc. 3841 @param pc handle to current TSCE context (#PHYMOD_ST) 3842 @returns The value PHYMOD_E_NONE upon successful completion 3843 @details Per Port PCS Init 3844 3845 */ 3846 /* TBD PARAMETERIZE CODE for SDK*/ 3847 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc) 3848 { 3849 3850 SC_X1_SPD_OVRR0_SPDr_t reg0_ovr_spd; 3851 SC_X1_SPD_OVRR0_0r_t reg0_ovr; 3852 SC_X1_SPD_OVRR0_1r_t reg0_ovr1; 3853 SC_X1_SPD_OVRR0_2r_t reg0_ovr2; 3854 SC_X1_SPD_OVRR0_3r_t reg0_ovr3; 3855 SC_X1_SPD_OVRR0_4r_t reg0_ovr4; 3856 SC_X1_SPD_OVRR0_5r_t reg0_ovr5; 3857 SC_X1_SPD_OVRR0_6r_t reg0_ovr6; 3858 3859 SC_X1_SPD_OVRR1_SPDr_t reg1_ovr_spd; 3860 SC_X1_SPD_OVRR1_0r_t reg1_ovr; 3861 SC_X1_SPD_OVRR1_1r_t reg1_ovr1; 3862 SC_X1_SPD_OVRR1_2r_t reg1_ovr2; 3863 SC_X1_SPD_OVRR1_3r_t reg1_ovr3; 3864 SC_X1_SPD_OVRR1_4r_t reg1_ovr4; 3865 SC_X1_SPD_OVRR1_5r_t reg1_ovr5; 3866 SC_X1_SPD_OVRR1_6r_t reg1_ovr6; 3867 3868 SC_X1_SPD_OVRR2_SPDr_t reg2_ovr_spd; 3869 SC_X1_SPD_OVRR2_0r_t reg2_ovr; 3870 SC_X1_SPD_OVRR2_1r_t reg2_ovr1; 3871 SC_X1_SPD_OVRR2_2r_t reg2_ovr2; 3872 SC_X1_SPD_OVRR2_3r_t reg2_ovr3; 3873 SC_X1_SPD_OVRR2_4r_t reg2_ovr4; 3874 SC_X1_SPD_OVRR2_5r_t reg2_ovr5; 3875 SC_X1_SPD_OVRR2_6r_t reg2_ovr6; 3876 3877 SC_X1_SPD_OVRR3_SPDr_t reg3_ovr_spd; 3878 SC_X1_SPD_OVRR3_0r_t reg3_ovr; 3879 SC_X1_SPD_OVRR3_1r_t reg3_ovr1; 3880 SC_X1_SPD_OVRR3_2r_t reg3_ovr2; 3881 SC_X1_SPD_OVRR3_3r_t reg3_ovr3; 3882 SC_X1_SPD_OVRR3_4r_t reg3_ovr4; 3883 SC_X1_SPD_OVRR3_5r_t reg3_ovr5; 3884 SC_X1_SPD_OVRR3_6r_t reg3_ovr6; 3885 3886 if (st_entry_num == 0) { 3887 3888 SC_X1_SPD_OVRR0_SPDr_CLR(reg0_ovr_spd); 3889 SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(reg0_ovr_spd, st_entry_speed); 3890 3891 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, reg0_ovr_spd)); 3892 3893 SC_X1_SPD_OVRR0_0r_CLR(reg0_ovr); 3894 SC_X1_SPD_OVRR0_1r_CLR(reg0_ovr1); 3895 SC_X1_SPD_OVRR0_2r_CLR(reg0_ovr2); 3896 SC_X1_SPD_OVRR0_3r_CLR(reg0_ovr3); 3897 SC_X1_SPD_OVRR0_4r_CLR(reg0_ovr4); 3898 SC_X1_SPD_OVRR0_5r_CLR(reg0_ovr5); 3899 SC_X1_SPD_OVRR0_6r_CLR(reg0_ovr6); 3900 3901 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(reg0_ovr, pc->t_pma_os_mode); 3902 SC_X1_SPD_OVRR0_0r_CL36BYTEDELETEMODEf_SET(reg0_ovr, pc->r_desc2_byte_deletion); 3903 SC_X1_SPD_OVRR0_0r_QSGMII_ENf_SET(reg0_ovr, pc->qsgmii_mode); 3904 3905 3906 3907 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 3908 3909 SC_X1_SPD_OVRR0_1r_CLOCKCNT0f_SET(reg0_ovr1, pc->clkcnt0); 3910 SC_X1_SPD_OVRR0_1r_SGMII_SPD_SWITCHf_SET(reg0_ovr1, pc->sgmii); 3911 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 3912 3913 SC_X1_SPD_OVRR0_2r_CLOCKCNT1f_SET(reg0_ovr2, pc->clkcnt1); 3914 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 3915 3916 SC_X1_SPD_OVRR0_3r_LOOPCNT1f_SET(reg0_ovr3, pc->lpcnt1); 3917 SC_X1_SPD_OVRR0_3r_LOOPCNT0f_SET(reg0_ovr3, pc->lpcnt0); 3918 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, reg0_ovr3)); 3919 3920 SC_X1_SPD_OVRR0_4r_MAC_CREDITGENCNTf_SET(reg0_ovr4, pc->mac_cgc); 3921 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, reg0_ovr4)); 3922 3923 3924 SC_X1_SPD_OVRR0_5r_PCS_CLOCKCNT0f_SET(reg0_ovr5, pc->pcs_clkcnt); 3925 SC_X1_SPD_OVRR0_5r_PCS_CREDITENABLEf_SET(reg0_ovr5, pc->pcs_crdten); 3926 SC_X1_SPD_OVRR0_5r_REPLICATION_CNTf_SET(reg0_ovr5, pc->pcs_repcnt); 3927 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, reg0_ovr5)); 3928 3929 SC_X1_SPD_OVRR0_6r_PCS_CREDITGENCNTf_SET(reg0_ovr6, pc->pcs_cgc); 3930 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_6r(pc, reg0_ovr6)); 3931 } /* (st_entry_num == 0) */ 3932 3933 else if (st_entry_num == 1) { 3934 3935 3936 SC_X1_SPD_OVRR1_SPDr_CLR(reg1_ovr_spd); 3937 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(reg1_ovr_spd, st_entry_speed); 3938 3939 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, reg1_ovr_spd)); 3940 3941 SC_X1_SPD_OVRR1_0r_CLR(reg1_ovr); 3942 SC_X1_SPD_OVRR1_1r_CLR(reg1_ovr1); 3943 SC_X1_SPD_OVRR1_2r_CLR(reg1_ovr2); 3944 SC_X1_SPD_OVRR1_3r_CLR(reg1_ovr3); 3945 SC_X1_SPD_OVRR1_4r_CLR(reg1_ovr4); 3946 SC_X1_SPD_OVRR1_5r_CLR(reg1_ovr5); 3947 SC_X1_SPD_OVRR1_6r_CLR(reg1_ovr6); 3948 3949 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(reg1_ovr, pc->t_pma_os_mode); 3950 SC_X1_SPD_OVRR1_0r_CL36BYTEDELETEMODEf_SET(reg1_ovr, pc->r_desc2_byte_deletion); 3951 SC_X1_SPD_OVRR1_0r_QSGMII_ENf_SET(reg1_ovr, pc->qsgmii_mode); 3952 3953 3954 3955 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 3956 3957 SC_X1_SPD_OVRR1_1r_CLOCKCNT0f_SET(reg1_ovr1, pc->clkcnt0); 3958 SC_X1_SPD_OVRR1_1r_SGMII_SPD_SWITCHf_SET(reg1_ovr1, pc->sgmii); 3959 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 3960 3961 SC_X1_SPD_OVRR1_2r_CLOCKCNT1f_SET(reg1_ovr2, pc->clkcnt1); 3962 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 3963 3964 SC_X1_SPD_OVRR1_3r_LOOPCNT1f_SET(reg1_ovr3, pc->lpcnt1); 3965 SC_X1_SPD_OVRR1_3r_LOOPCNT0f_SET(reg1_ovr3, pc->lpcnt0); 3966 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, reg1_ovr3)); 3967 3968 SC_X1_SPD_OVRR1_4r_MAC_CREDITGENCNTf_SET(reg1_ovr4, pc->mac_cgc); 3969 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, reg1_ovr4)); 3970 3971 3972 SC_X1_SPD_OVRR1_5r_PCS_CLOCKCNT0f_SET(reg1_ovr5, pc->pcs_clkcnt); 3973 SC_X1_SPD_OVRR1_5r_PCS_CREDITENABLEf_SET(reg1_ovr5, pc->pcs_crdten); 3974 SC_X1_SPD_OVRR1_5r_REPLICATION_CNTf_SET(reg1_ovr5, pc->pcs_repcnt); 3975 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, reg1_ovr5)); 3976 3977 SC_X1_SPD_OVRR1_6r_PCS_CREDITGENCNTf_SET(reg1_ovr6, pc->pcs_cgc); 3978 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_6r(pc, reg1_ovr6)); 3979 3980 3981 3982 } /* (st_entry_num == 1) */ 3983 3984 else if (st_entry_num == 2) { 3985 3986 SC_X1_SPD_OVRR2_SPDr_CLR(reg2_ovr_spd); 3987 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(reg2_ovr_spd, st_entry_speed); 3988 3989 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, reg2_ovr_spd)); 3990 3991 SC_X1_SPD_OVRR2_0r_CLR(reg2_ovr); 3992 SC_X1_SPD_OVRR2_1r_CLR(reg2_ovr1); 3993 SC_X1_SPD_OVRR2_2r_CLR(reg2_ovr2); 3994 SC_X1_SPD_OVRR2_3r_CLR(reg2_ovr3); 3995 SC_X1_SPD_OVRR2_4r_CLR(reg2_ovr4); 3996 SC_X1_SPD_OVRR2_5r_CLR(reg2_ovr5); 3997 SC_X1_SPD_OVRR2_6r_CLR(reg2_ovr6); 3998 3999 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(reg2_ovr, pc->t_pma_os_mode); 4000 SC_X1_SPD_OVRR2_0r_CL36BYTEDELETEMODEf_SET(reg2_ovr, pc->r_desc2_byte_deletion); 4001 SC_X1_SPD_OVRR2_0r_QSGMII_ENf_SET(reg2_ovr, pc->qsgmii_mode); 4002 4003 4004 4005 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 4006 4007 SC_X1_SPD_OVRR2_1r_CLOCKCNT0f_SET(reg2_ovr1, pc->clkcnt0); 4008 SC_X1_SPD_OVRR2_1r_SGMII_SPD_SWITCHf_SET(reg2_ovr1, pc->sgmii); 4009 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 4010 4011 SC_X1_SPD_OVRR2_2r_CLOCKCNT1f_SET(reg2_ovr2, pc->clkcnt1); 4012 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 4013 4014 SC_X1_SPD_OVRR2_3r_LOOPCNT1f_SET(reg2_ovr3, pc->lpcnt1); 4015 SC_X1_SPD_OVRR2_3r_LOOPCNT0f_SET(reg2_ovr3, pc->lpcnt0); 4016 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, reg2_ovr3)); 4017 4018 SC_X1_SPD_OVRR2_4r_MAC_CREDITGENCNTf_SET(reg2_ovr4, pc->mac_cgc); 4019 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, reg2_ovr4)); 4020 4021 4022 SC_X1_SPD_OVRR2_5r_PCS_CLOCKCNT0f_SET(reg2_ovr5, pc->pcs_clkcnt); 4023 SC_X1_SPD_OVRR2_5r_PCS_CREDITENABLEf_SET(reg2_ovr5, pc->pcs_crdten); 4024 SC_X1_SPD_OVRR2_5r_REPLICATION_CNTf_SET(reg2_ovr5, pc->pcs_repcnt); 4025 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, reg2_ovr5)); 4026 4027 SC_X1_SPD_OVRR2_6r_PCS_CREDITGENCNTf_SET(reg2_ovr6, pc->pcs_cgc); 4028 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_6r(pc, reg2_ovr6)); 4029 4030 4031 } /* (st_entry_num == 2) */ 4032 4033 else /*(st_entry_num == 3) */ { 4034 4035 SC_X1_SPD_OVRR3_SPDr_CLR(reg3_ovr_spd); 4036 SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(reg3_ovr_spd, st_entry_speed); 4037 4038 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, reg3_ovr_spd)); 4039 4040 SC_X1_SPD_OVRR3_0r_CLR(reg3_ovr); 4041 SC_X1_SPD_OVRR3_1r_CLR(reg3_ovr1); 4042 SC_X1_SPD_OVRR3_2r_CLR(reg3_ovr2); 4043 SC_X1_SPD_OVRR3_3r_CLR(reg3_ovr3); 4044 SC_X1_SPD_OVRR3_4r_CLR(reg3_ovr4); 4045 SC_X1_SPD_OVRR3_5r_CLR(reg3_ovr5); 4046 SC_X1_SPD_OVRR3_6r_CLR(reg3_ovr6); 4047 4048 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(reg3_ovr, pc->t_pma_os_mode); 4049 SC_X1_SPD_OVRR3_0r_CL36BYTEDELETEMODEf_SET(reg3_ovr, pc->r_desc2_byte_deletion); 4050 SC_X1_SPD_OVRR3_0r_QSGMII_ENf_SET(reg3_ovr, pc->qsgmii_mode); 4051 4052 4053 4054 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 4055 4056 SC_X1_SPD_OVRR3_1r_CLOCKCNT0f_SET(reg3_ovr1, pc->clkcnt0); 4057 SC_X1_SPD_OVRR3_1r_SGMII_SPD_SWITCHf_SET(reg3_ovr1, pc->sgmii); 4058 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 4059 4060 SC_X1_SPD_OVRR3_2r_CLOCKCNT1f_SET(reg3_ovr2, pc->clkcnt1); 4061 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 4062 4063 SC_X1_SPD_OVRR3_3r_LOOPCNT1f_SET(reg3_ovr3, pc->lpcnt1); 4064 SC_X1_SPD_OVRR3_3r_LOOPCNT0f_SET(reg3_ovr3, pc->lpcnt0); 4065 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, reg3_ovr3)); 4066 4067 SC_X1_SPD_OVRR3_4r_MAC_CREDITGENCNTf_SET(reg3_ovr4, pc->mac_cgc); 4068 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, reg3_ovr4)); 4069 4070 4071 SC_X1_SPD_OVRR3_5r_PCS_CLOCKCNT0f_SET(reg3_ovr5, pc->pcs_clkcnt); 4072 SC_X1_SPD_OVRR3_5r_PCS_CREDITENABLEf_SET(reg3_ovr5, pc->pcs_crdten); 4073 SC_X1_SPD_OVRR3_5r_REPLICATION_CNTf_SET(reg3_ovr5, pc->pcs_repcnt); 4074 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, reg3_ovr5)); 4075 4076 SC_X1_SPD_OVRR3_6r_PCS_CREDITGENCNTf_SET(reg3_ovr6, pc->pcs_cgc); 4077 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_6r(pc, reg3_ovr6)); 4078 } /* (st_entry_num == 3) */ 4079 return PHYMOD_E_NONE; 4080 } 4081 #endif 4082 4083 #ifdef _DV_TB_ 4084 /** 4085 @brief Read the 16 bit rev. id value etc. 4086 @param pc handle to current TSCE context (#PHYMOD_ST) 4087 @returns The value PHYMOD_E_NONE upon successful completion 4088 @details Per Port PCS Init 4089 */ 4090 int _qmod16_configure_sc_speed_configuration(PHYMOD_ST* pc) 4091 { 4092 int data =0; 4093 int mask =0; 4094 int st_entry =0; 4095 int speed_entry = 0; 4096 PHYMOD_ST pc_st_tmp; 4097 PHYMOD_ST* pc_st; 4098 4099 if (pc->sc_mode == QMOD16_SC_MODE_HT_WITH_BASIC_OVERRIDE) { 4100 /* Configure the ffec_eb regsiter */ 4101 data |= (1 << 10); 4102 mask |= 0x0400; 4103 4104 } 4105 else if(pc->sc_mode == QMOD16_SC_MODE_ST_OVERRIDE) { 4106 } 4107 else if (pc->sc_mode == QMOD16_SC_MODE_ST) { 4108 st_entry = pc->per_lane_control & 0xff; 4109 speed_entry = (pc->per_lane_control & 0xff00) >> 8; 4110 4111 /* 4112 A pc_st_tmp is created so the overriden expected values passed from SV are not 4113 loaded in ST, and the ST has the same HT values 4114 */ 4115 init_qmod16_st(&pc_st_tmp); 4116 pc_st_tmp.spd_intf = pc->spd_intf; 4117 pc_st_tmp.prt_ad = pc->prt_ad; 4118 pc_st_tmp.unit = pc->unit; 4119 pc_st_tmp.port_type = pc->port_type; 4120 pc_st_tmp.this_lane = pc->this_lane; 4121 pc_st_tmp.sc_mode = pc->sc_mode; 4122 pc_st = &pc_st_tmp; 4123 qmod16_sc_lkup_table(pc_st); 4124 /*configure the ST regsiters */ 4125 _configure_st_entry(st_entry, speed_entry, pc_st); 4126 4127 } 4128 return PHYMOD_E_NONE; 4129 } 4130 #endif 4131 4132 #ifdef _DV_TB_ 4133 /** 4134 @brief Read the 16 bit rev. id value etc. 4135 @param pc handle to current TSCE context (#PHYMOD_ST) 4136 @returns The value PHYMOD_E_NONE upon successful completion 4137 @details Per Port PCS Init 4138 */ 4139 int _qmod16_init_pcs_an(PHYMOD_ST* pc) 4140 { 4141 #ifdef OLD_CODE 4142 UC_COMMAND4r_t reg_com4; 4143 UC_COMMANDr_t reg_com; 4144 4145 UC_COMMAND4r_CLR(reg_com4); 4146 UC_COMMANDr_CLR(reg_com); 4147 4148 UC_COMMAND4r_MICRO_SYSTEM_CLK_ENf_SET(reg_com4,1); 4149 UC_COMMAND4r_MICRO_SYSTEM_RESET_Nf_SET(reg_com4,1); 4150 PHYMOD_IF_ERR_RETURN(MODIFY_UC_COMMAND4r(pc, reg_com4)); 4151 4152 UC_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(reg_com,1); 4153 PHYMOD_IF_ERR_RETURN(MODIFY_UC_COMMANDr(pc, reg_com)); 4154 #endif /*OLD_CODE*/ 4155 if(pc->uc_active){ 4156 UC_CLK_CTL0r_t reg_ctrl0; 4157 UC_RST_CTL0r_t reg_rst_ctrl0; 4158 4159 UC_CLK_CTL0r_CLR(reg_ctrl0); 4160 UC_RST_CTL0r_CLR(reg_rst_ctrl0); 4161 4162 UC_CLK_CTL0r_MICRO_MASTER_CLK_ENf_SET(reg_ctrl0, 1); 4163 PHYMOD_IF_ERR_RETURN(MODIFY_UC_CLK_CTL0r(pc, reg_ctrl0)); 4164 4165 UC_RST_CTL0r_MICRO_MASTER_RSTBf_SET(reg_rst_ctrl0, 1); 4166 PHYMOD_IF_ERR_RETURN(MODIFY_UC_RST_CTL0r(pc, reg_rst_ctrl0)); 4167 } 4168 4169 qmod16_set_an_port_mode(pc); 4170 pc->port_type=QMOD16_MULTI_PORT; 4171 qmod16_autoneg_set(pc); 4172 4173 qmod16_autoneg_control(pc); 4174 4175 return PHYMOD_E_NONE; 4176 } 4177 #endif /* _DV_TB_ */ 4178 4179 /** 4180 @brief trigger the speed change bit 4181 @param pc handle to current TSCE context (#PHYMOD_ST) 4182 @returns The value PHYMOD_E_NONE upon successful completion 4183 @details 4184 */ 4185 4186 int qmod16_trigger_speed_change(PHYMOD_ST* pc) 4187 { 4188 SC_X4_CTLr_t reg; 4189 4190 QMOD16_DBG_IN_FUNC_INFO(pc); 4191 #ifdef _DV_TB_ 4192 pc->adjust_port_mode = 1; 4193 #endif /* _DV_TB_ */ 4194 /* write 0 to the speed change */ 4195 SC_X4_CTLr_CLR(reg); 4196 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 4197 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 4198 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg)); 4199 4200 /* write 1 to the speed change. No need to read again before write*/ 4201 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 1); 4202 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg)); 4203 #ifdef _DV_TB_ 4204 pc->adjust_port_mode = 0; 4205 #endif /* _DV_TB_ */ 4206 4207 return PHYMOD_E_NONE; 4208 } 4209 4210 #ifdef _DV_TB_ 4211 /** 4212 @brief Read the 16 bit rev. id value etc. 4213 @param pc handle to current TSCE context (#PHYMOD_ST) 4214 @returns The value PHYMOD_E_NONE upon successful completion 4215 @details Per Port PCS Init 4216 */ 4217 int _read_and_compare_final_status(PHYMOD_ST* pc) 4218 { 4219 uint16_t fail; 4220 int actual_speed; 4221 PHYMOD_ST sc_final_stats_actual; 4222 PHYMOD_ST* sc_final_stats_actual_tmp; 4223 4224 SC_X4_FI_SP0_RSLVD_SPDr_t reg_resolved_sp0_spd; 4225 SC_X4_FI_SP0_RSLVD0r_t reg_resolved_sp0_0; 4226 SC_X4_FI_SP0_RSLVD1r_t reg_resolved_sp0_1; 4227 SC_X4_FI_SP0_RSLVD2r_t reg_resolved_sp0_2; 4228 SC_X4_FI_SP0_RSLVD3r_t reg_resolved_sp0_3; 4229 SC_X4_FI_SP0_RSLVD4r_t reg_resolved_sp0_4; 4230 SC_X4_FI_SP0_RSLVD5r_t reg_resolved_sp0_5; 4231 SC_X4_FI_SP0_RSLVD6r_t reg_resolved_sp0_6; 4232 4233 SC_X4_FI_SP1_RSLVD_SPDr_t reg_resolved_sp1_spd; 4234 SC_X4_FI_SP1_RSLVD0r_t reg_resolved_sp1_0; 4235 SC_X4_FI_SP1_RSLVD1r_t reg_resolved_sp1_1; 4236 SC_X4_FI_SP1_RSLVD2r_t reg_resolved_sp1_2; 4237 SC_X4_FI_SP1_RSLVD3r_t reg_resolved_sp1_3; 4238 SC_X4_FI_SP1_RSLVD4r_t reg_resolved_sp1_4; 4239 SC_X4_FI_SP1_RSLVD5r_t reg_resolved_sp1_5; 4240 SC_X4_FI_SP1_RSLVD6r_t reg_resolved_sp1_6; 4241 4242 SC_X4_FI_SP2_RSLVD_SPDr_t reg_resolved_sp2_spd; 4243 SC_X4_FI_SP2_RSLVD0r_t reg_resolved_sp2_0; 4244 SC_X4_FI_SP2_RSLVD1r_t reg_resolved_sp2_1; 4245 SC_X4_FI_SP2_RSLVD2r_t reg_resolved_sp2_2; 4246 SC_X4_FI_SP2_RSLVD3r_t reg_resolved_sp2_3; 4247 SC_X4_FI_SP2_RSLVD4r_t reg_resolved_sp2_4; 4248 SC_X4_FI_SP2_RSLVD5r_t reg_resolved_sp2_5; 4249 SC_X4_FI_SP2_RSLVD6r_t reg_resolved_sp2_6; 4250 4251 SC_X4_FI_SP3_RSLVD_SPDr_t reg_resolved_sp3_spd; 4252 SC_X4_FI_SP3_RSLVD0r_t reg_resolved_sp3_0; 4253 SC_X4_FI_SP3_RSLVD1r_t reg_resolved_sp3_1; 4254 SC_X4_FI_SP3_RSLVD2r_t reg_resolved_sp3_2; 4255 SC_X4_FI_SP3_RSLVD3r_t reg_resolved_sp3_3; 4256 SC_X4_FI_SP3_RSLVD4r_t reg_resolved_sp3_4; 4257 SC_X4_FI_SP3_RSLVD5r_t reg_resolved_sp3_5; 4258 SC_X4_FI_SP3_RSLVD6r_t reg_resolved_sp3_6; 4259 4260 if (pc->sub_port == 0) { 4261 SC_X4_FI_SP0_RSLVD_SPDr_CLR(reg_resolved_sp0_spd); 4262 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD_SPDr(pc, ®_resolved_sp0_spd)); 4263 actual_speed = SC_X4_FI_SP0_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp0_spd); 4264 sc_final_stats_actual.speed = actual_speed; 4265 4266 SC_X4_FI_SP0_RSLVD0r_CLR(reg_resolved_sp0_0); 4267 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD0r(pc, ®_resolved_sp0_0)); 4268 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP0_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp0_0); 4269 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP0_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp0_0); 4270 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP0_RSLVD0r_OS_MODEf_GET(reg_resolved_sp0_0); 4271 4272 SC_X4_FI_SP0_RSLVD1r_CLR(reg_resolved_sp0_1); 4273 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD1r(pc, ®_resolved_sp0_1)); 4274 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP0_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp0_1); 4275 sc_final_stats_actual.sgmii = SC_X4_FI_SP0_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp0_1); 4276 4277 SC_X4_FI_SP0_RSLVD2r_CLR(reg_resolved_sp0_2); 4278 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD2r(pc, ®_resolved_sp0_2)); 4279 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP0_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp0_2); 4280 4281 SC_X4_FI_SP0_RSLVD3r_CLR(reg_resolved_sp0_3); 4282 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD3r(pc, ®_resolved_sp0_3)); 4283 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP0_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp0_3); 4284 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP0_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp0_3); 4285 4286 SC_X4_FI_SP0_RSLVD4r_CLR(reg_resolved_sp0_4); 4287 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD4r(pc, ®_resolved_sp0_4)); 4288 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP0_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp0_4); 4289 4290 SC_X4_FI_SP0_RSLVD5r_CLR(reg_resolved_sp0_5); 4291 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD5r(pc, ®_resolved_sp0_5)); 4292 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP0_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp0_5); 4293 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP0_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp0_5); 4294 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP0_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp0_5); 4295 4296 SC_X4_FI_SP0_RSLVD6r_CLR(reg_resolved_sp0_6); 4297 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD6r(pc, ®_resolved_sp0_6)); 4298 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP0_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp0_6); 4299 } 4300 4301 if (pc->sub_port == 1) { 4302 SC_X4_FI_SP1_RSLVD_SPDr_CLR(reg_resolved_sp1_spd); 4303 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD_SPDr(pc, ®_resolved_sp1_spd)); 4304 actual_speed = SC_X4_FI_SP1_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp1_spd); 4305 sc_final_stats_actual.speed = actual_speed; 4306 4307 SC_X4_FI_SP1_RSLVD0r_CLR(reg_resolved_sp1_0); 4308 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD0r(pc, ®_resolved_sp1_0)); 4309 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP1_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp1_0); 4310 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP1_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp1_0); 4311 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP1_RSLVD0r_OS_MODEf_GET(reg_resolved_sp1_0); 4312 4313 SC_X4_FI_SP1_RSLVD1r_CLR(reg_resolved_sp1_1); 4314 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD1r(pc, ®_resolved_sp1_1)); 4315 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP1_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp1_1); 4316 sc_final_stats_actual.sgmii = SC_X4_FI_SP1_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp1_1); 4317 4318 SC_X4_FI_SP1_RSLVD2r_CLR(reg_resolved_sp1_2); 4319 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD2r(pc, ®_resolved_sp1_2)); 4320 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP1_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp1_2); 4321 4322 SC_X4_FI_SP1_RSLVD3r_CLR(reg_resolved_sp1_3); 4323 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD3r(pc, ®_resolved_sp1_3)); 4324 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP1_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp1_3); 4325 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP1_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp1_3); 4326 4327 SC_X4_FI_SP1_RSLVD4r_CLR(reg_resolved_sp1_4); 4328 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD4r(pc, ®_resolved_sp1_4)); 4329 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP1_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp1_4); 4330 4331 SC_X4_FI_SP1_RSLVD5r_CLR(reg_resolved_sp1_5); 4332 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD5r(pc, ®_resolved_sp1_5)); 4333 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP1_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp1_5); 4334 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP1_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp1_5); 4335 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP1_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp1_5); 4336 4337 SC_X4_FI_SP1_RSLVD6r_CLR(reg_resolved_sp1_6); 4338 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD6r(pc, ®_resolved_sp1_6)); 4339 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP1_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp1_6); 4340 } 4341 4342 if (pc->sub_port == 2) { 4343 SC_X4_FI_SP2_RSLVD_SPDr_CLR(reg_resolved_sp2_spd); 4344 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD_SPDr(pc, ®_resolved_sp2_spd)); 4345 actual_speed = SC_X4_FI_SP2_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp2_spd); 4346 sc_final_stats_actual.speed = actual_speed; 4347 4348 SC_X4_FI_SP2_RSLVD0r_CLR(reg_resolved_sp2_0); 4349 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD0r(pc, ®_resolved_sp2_0)); 4350 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP2_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp2_0); 4351 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP2_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp2_0); 4352 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP2_RSLVD0r_OS_MODEf_GET(reg_resolved_sp2_0); 4353 4354 SC_X4_FI_SP2_RSLVD1r_CLR(reg_resolved_sp2_1); 4355 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD1r(pc, ®_resolved_sp2_1)); 4356 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP2_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp2_1); 4357 sc_final_stats_actual.sgmii = SC_X4_FI_SP2_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp2_1); 4358 4359 SC_X4_FI_SP2_RSLVD2r_CLR(reg_resolved_sp2_2); 4360 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD2r(pc, ®_resolved_sp2_2)); 4361 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP2_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp2_2); 4362 4363 SC_X4_FI_SP2_RSLVD3r_CLR(reg_resolved_sp2_3); 4364 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD3r(pc, ®_resolved_sp2_3)); 4365 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP2_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp2_3); 4366 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP2_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp2_3); 4367 4368 SC_X4_FI_SP2_RSLVD4r_CLR(reg_resolved_sp2_4); 4369 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD4r(pc, ®_resolved_sp2_4)); 4370 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP2_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp2_4); 4371 4372 SC_X4_FI_SP2_RSLVD5r_CLR(reg_resolved_sp2_5); 4373 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD5r(pc, ®_resolved_sp2_5)); 4374 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP2_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp2_5); 4375 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP2_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp2_5); 4376 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP2_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp2_5); 4377 4378 SC_X4_FI_SP2_RSLVD6r_CLR(reg_resolved_sp2_6); 4379 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD6r(pc, ®_resolved_sp2_6)); 4380 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP2_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp2_6); 4381 } 4382 4383 if (pc->sub_port == 3) { 4384 SC_X4_FI_SP3_RSLVD_SPDr_CLR(reg_resolved_sp3_spd); 4385 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD_SPDr(pc, ®_resolved_sp3_spd)); 4386 actual_speed = SC_X4_FI_SP3_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp3_spd); 4387 sc_final_stats_actual.speed = actual_speed; 4388 4389 SC_X4_FI_SP3_RSLVD0r_CLR(reg_resolved_sp3_0); 4390 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD0r(pc, ®_resolved_sp3_0)); 4391 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP3_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp3_0); 4392 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP3_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp3_0); 4393 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP3_RSLVD0r_OS_MODEf_GET(reg_resolved_sp3_0); 4394 4395 SC_X4_FI_SP3_RSLVD1r_CLR(reg_resolved_sp3_1); 4396 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD1r(pc, ®_resolved_sp3_1)); 4397 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP3_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp3_1); 4398 sc_final_stats_actual.sgmii = SC_X4_FI_SP3_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp3_1); 4399 4400 SC_X4_FI_SP3_RSLVD2r_CLR(reg_resolved_sp3_2); 4401 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD2r(pc, ®_resolved_sp3_2)); 4402 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP3_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp3_2); 4403 4404 SC_X4_FI_SP3_RSLVD3r_CLR(reg_resolved_sp3_3); 4405 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD3r(pc, ®_resolved_sp3_3)); 4406 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP3_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp3_3); 4407 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP3_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp3_3); 4408 4409 SC_X4_FI_SP3_RSLVD4r_CLR(reg_resolved_sp3_4); 4410 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD4r(pc, ®_resolved_sp3_4)); 4411 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP3_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp3_4); 4412 4413 SC_X4_FI_SP3_RSLVD5r_CLR(reg_resolved_sp3_5); 4414 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD5r(pc, ®_resolved_sp3_5)); 4415 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP3_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp3_5); 4416 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP3_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp3_5); 4417 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP3_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp3_5); 4418 4419 SC_X4_FI_SP3_RSLVD6r_CLR(reg_resolved_sp3_6); 4420 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD6r(pc, ®_resolved_sp3_6)); 4421 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP3_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp3_6); 4422 } 4423 4424 /* Compare the actual and expected stats */ 4425 fail = 0; 4426 4427 if (pc->spd_intf == QMOD16_SPD_4000) { 4428 if (pc->subp_speed == 2) { 4429 pc->clkcnt0 = 1000; 4430 pc->mac_cgc = 999; 4431 pc->sgmii = 1; 4432 pc->pcs_repcnt = 1; 4433 pc->pcs_crdten = 1; 4434 pc->r_desc2_byte_deletion = 1; 4435 } 4436 if (pc->subp_speed == 1) { 4437 pc->clkcnt0 = 100; 4438 pc->mac_cgc = 99; 4439 pc->sgmii = 1; 4440 pc->pcs_repcnt = 0; 4441 pc->pcs_crdten = 1; 4442 pc->r_desc2_byte_deletion = 0; 4443 } 4444 if (pc->subp_speed == 0) { 4445 pc->clkcnt0 = 10; 4446 pc->mac_cgc = 9; 4447 pc->pcs_clkcnt = 0; 4448 pc->pcs_cgc = 0; 4449 } 4450 } 4451 4452 if (pc->sc_mode == QMOD16_SC_MODE_ST) { 4453 if (actual_speed != (pc->per_lane_control >> 8)) 4454 fail = 1; 4455 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (QMOD16_SPD_10000_XFI << 8))) { /* DV Verification Only */ 4456 if (actual_speed != digital_operationSpeeds_SPEED_10G_KR1) 4457 fail = 1; 4458 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (QMOD16_SPD_10_SGMII << 8))) { /* DV Verification Only */ 4459 if (actual_speed != digital_operationSpeeds_SPEED_10M) 4460 fail = 1; 4461 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (QMOD16_SPD_5000_XFI << 8))) { /* DV Verification Only */ 4462 if (actual_speed != digital_operationSpeeds_SPEED_5G_KR1) 4463 fail = 1; 4464 } else { 4465 if (actual_speed != pc->speed) 4466 fail = 1; 4467 } 4468 4469 if (sc_final_stats_actual.t_pma_os_mode != pc->t_pma_os_mode) 4470 fail = 1; 4471 4472 if (sc_final_stats_actual.qsgmii_en != pc->qsgmii_en) 4473 fail = 1; 4474 4475 if (sc_final_stats_actual.r_desc2_byte_deletion != pc->r_desc2_byte_deletion) 4476 fail = 1; 4477 4478 if (sc_final_stats_actual.sgmii != pc->sgmii) 4479 fail = 1; 4480 if (sc_final_stats_actual.clkcnt0 != pc->clkcnt0) 4481 fail = 1; 4482 if (sc_final_stats_actual.clkcnt1 != pc->clkcnt1) 4483 fail = 1; 4484 if (sc_final_stats_actual.lpcnt0 != pc->lpcnt0) 4485 fail = 1; 4486 if (sc_final_stats_actual.lpcnt1 != pc->lpcnt1) 4487 fail = 1; 4488 if (sc_final_stats_actual.mac_cgc != pc->mac_cgc) 4489 fail = 1; 4490 if (sc_final_stats_actual.pcs_repcnt != pc->pcs_repcnt) 4491 fail = 1; 4492 if (sc_final_stats_actual.pcs_crdten != pc->pcs_crdten) 4493 fail = 1; 4494 if (sc_final_stats_actual.pcs_clkcnt != pc->pcs_clkcnt) 4495 fail = 1; 4496 if (sc_final_stats_actual.pcs_cgc != pc->pcs_cgc) 4497 fail = 1; 4498 4499 pc->accData = fail; 4500 if (fail == 1) { 4501 sc_final_stats_actual_tmp = &sc_final_stats_actual; 4502 qmod16_print_qmod16_sc_lkup_table(sc_final_stats_actual_tmp); 4503 qmod16_print_qmod16_sc_lkup_table(pc); 4504 return PHYMOD_E_FAIL; 4505 } 4506 return PHYMOD_E_NONE; 4507 4508 } 4509 #endif 4510 4511 #ifdef _DV_TB_ 4512 /** 4513 @brief Read the 16 bit rev. id value etc. 4514 @param pc handle to current TSCE context (#PHYMOD_ST) 4515 @returns The value PHYMOD_E_NONE upon successful completion 4516 @details Per Port PCS Init for forced speeds 4517 4518 */ 4519 int _qmod16_init_pcs_fs(PHYMOD_ST* pc) 4520 { 4521 uint16_t data; 4522 SC_X4_CTLr_t reg_swmode; 4523 4524 _qmod16_get_sc_speed_configuration(pc); 4525 _qmod16_configure_sc_speed_configuration(pc); 4526 4527 /* Set speed */ 4528 if (pc->sc_mode == QMOD16_SC_MODE_ST) { 4529 data = (pc->per_lane_control & 0xff00) >> 8; 4530 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (QMOD16_SPD_10_SGMII << 8))) {/* DV Verification Only */ 4531 data = digital_operationSpeeds_SPEED_10M; 4532 } else if ((pc->per_lane_control & 0xffff) == (0x004 | (QMOD16_SPD_5000_XFI << 8))) {/* DV Verification Only */ 4533 data = digital_operationSpeeds_SPEED_5G_KR1; 4534 } else { 4535 data = pc->speed; 4536 } 4537 SC_X4_CTLr_CLR(reg_swmode); 4538 SC_X4_CTLr_SW_SPEEDf_SET(reg_swmode, data); 4539 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_swmode)); 4540 4541 qmod16_trigger_speed_change(pc); 4542 _qmod16_wait_sc_stats_set(pc); 4543 return PHYMOD_E_NONE; 4544 } 4545 #endif 4546 4547 #ifdef _DV_TB_ 4548 /* 4549 *THIS FUNCTION PROGRAMS THE SHIM FIFO STATUS 4550 */ 4551 int prog_shim_ff_threshold(PHYMOD_ST* pc) 4552 { 4553 MAIN_SHIM_FF_THRr_t shim_thresh_t; 4554 4555 PHYMOD_MEMSET(&shim_thresh_t, 0, sizeof(shim_thresh_t)); 4556 4557 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_2P5Gf_SET(shim_thresh_t, 3); 4558 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_1Gf_SET(shim_thresh_t, 3); 4559 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_100Mf_SET (shim_thresh_t, 3); 4560 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_10Mf_SET (shim_thresh_t, 3); 4561 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN_SHIM_FF_THRr(pc, shim_thresh_t)); 4562 4563 return PHYMOD_E_NONE; 4564 } 4565 #endif 4566 4567 int qmod16_usgmii_shim_fifo_threshold_set(PHYMOD_ST* pc) 4568 { 4569 MAIN_SHIM_FF_THRr_t shim_thresh_t; 4570 4571 PHYMOD_MEMSET(&shim_thresh_t, 0, sizeof(shim_thresh_t)); 4572 4573 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_2P5Gf_SET(shim_thresh_t, 3); 4574 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_1Gf_SET(shim_thresh_t, 3); 4575 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_100Mf_SET (shim_thresh_t, 3); 4576 MAIN_SHIM_FF_THRr_SHIM_FF_THRESHOLD_10Mf_SET (shim_thresh_t, 3); 4577 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN_SHIM_FF_THRr(pc, shim_thresh_t)); 4578 4579 return PHYMOD_E_NONE; 4580 } 4581 4582 #ifdef _DV_TB_ 4583 /** 4584 @brief Checks to ensure SC has programmed the PCS as expected 4585 @param pc handle to current TSCE context (#PHYMOD_ST) 4586 @returns The value PHYMOD_E_NONE upon successful completion. 4587 @details Called to Configure tsc12 for 100G+ speeds 4588 4589 */ 4590 4591 int qmod16_check_sc_stats(PHYMOD_ST* pc) /* CHECK_SC_STATS */ 4592 { 4593 uint16_t data ; 4594 4595 QMOD16_DBG_IN_FUNC_INFO(pc); 4596 data = _read_and_compare_final_status(pc); 4597 4598 return data; 4599 } 4600 #endif /* _DV_TB_ */ 4601 4602 #ifdef _DV_TB_ 4603 /** 4604 @brief 4605 @param 4606 @returns The value PHYMOD_E_NONE upon successful completion. 4607 @details 4608 4609 */ 4610 4611 int qmod16_disable_set(PHYMOD_ST* pc) /* CHECK_SC_STATS */ 4612 { 4613 SC_X4_CTLr_t reg_sc_ctrl; 4614 4615 QMOD16_DBG_IN_FUNC_INFO(pc); 4616 SC_X4_CTLr_CLR(reg_sc_ctrl); 4617 4618 /* write 0 to the speed change */ 4619 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 4620 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 4621 4622 return PHYMOD_E_NONE; 4623 } 4624 #endif /* _DV_TB_ */ 4625 4626 #ifdef _DV_TB_ 4627 /** 4628 @brief 4629 @param 4630 @returns The value PHYMOD_E_NONE upon successful completion. 4631 @details 4632 4633 */ 4634 4635 int qmod16_credit_control(PHYMOD_ST* pc, int enable) /* CHECK_SC_STATS */ 4636 { 4637 return PHYMOD_E_NONE; 4638 } 4639 #endif /* _DV_TB_ */ 4640 4641 /** 4642 @brief Get info on Disable status of the Port 4643 @param pc handle to current TSCE context (#PHYMOD_ST) 4644 @returns The value PHYMOD_E_NONE upon successful completion 4645 @details Disables the port by writing 0 to the speed config logic in PCS. 4646 This makes the PCS to bring down the PCS blocks and also apply lane datapath 4647 reset to the PMD. There is no control input to this function since it only does 4648 one thing. 4649 4650 */ 4651 int qmod16_disable_set(PHYMOD_ST* pc) 4652 { 4653 SC_X4_CTLr_t reg_sc_ctrl; 4654 4655 QMOD16_DBG_IN_FUNC_INFO(pc); 4656 SC_X4_CTLr_CLR(reg_sc_ctrl); 4657 4658 /* write 0 to the speed change */ 4659 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 4660 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 4661 4662 return PHYMOD_E_NONE; 4663 } 4664 4665 int qmod16_disable_get(PHYMOD_ST *pc, uint32_t *enable) 4666 { 4667 SC_X4_CTLr_t reg_sc_ctrl; 4668 4669 QMOD16_DBG_IN_FUNC_INFO(pc); 4670 SC_X4_CTLr_CLR(reg_sc_ctrl); 4671 4672 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®_sc_ctrl)); 4673 *enable = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 4674 4675 return PHYMOD_E_NONE; 4676 } 4677 4678 /** 4679 @brief get the rx lane reset staus for any lane 4680 @param pc handle to current TSCE context (#PHYMOD_ST) 4681 @param get the status as *value 4682 @returns The value PHYMOD_E_NONE upon successful completion. 4683 4684 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 4685 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 4686 read back RSTB_LANE. 4687 */ 4688 4689 int qmod16_rx_lane_control_get(PHYMOD_ST* pc, int *value) /* RX_LANE_CONTROL */ 4690 { 4691 PMA_CTLr_t reg_pma_ctrl; 4692 4693 QMOD16_DBG_IN_FUNC_INFO(pc); 4694 PMA_CTLr_CLR(reg_pma_ctrl); 4695 PHYMOD_IF_ERR_RETURN (READ_PMA_CTLr(pc, ®_pma_ctrl)); 4696 4697 if (PMA_CTLr_RSTB_LANEf_GET(reg_pma_ctrl)) { 4698 *value = 1; 4699 } else { 4700 *value = 0; 4701 } 4702 return PHYMOD_E_NONE; 4703 } 4704 4705 /** 4706 @brief Get the plldiv from lookup table 4707 @param pc handle to current TSCE context (#PHYMOD_ST) 4708 @param spd_intf speed as specified by enum #qmod16_spd_intfc_type 4709 @param plldiv Receives the pll divider value 4710 @param speed_vec Receives the speed id. 4711 @returns The value PHYMOD_E_NONE upon successful completion 4712 @details Get the plldiv from lookup table 4713 */ 4714 int qmod16_plldiv_lkup_get(PHYMOD_ST* pc, qmod16_spd_intfc_type spd_intf, uint32_t *plldiv, uint16_t *speed_vec) 4715 { 4716 int speed_id; 4717 4718 qmod16_get_mapped_speed(spd_intf, &speed_id); 4719 *plldiv = qmod16_sc_pmd_entry[speed_id].pll_mode; 4720 *speed_vec = speed_id ; 4721 4722 return PHYMOD_E_NONE; 4723 } 4724 4725 /** 4726 @brief rx lane reset and enable of any particular lane 4727 @param pc handle to current TSCE context (#PHYMOD_ST) 4728 @param enable to reset the lane. 4729 @returns The value PHYMOD_E_NONE upon successful completion. 4730 4731 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 4732 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 4733 read back RSTB_LANE. 4734 4735 */ 4736 int qmod16_rx_lane_control_set(PHYMOD_ST* pc, int enable) /* RX_LANE_CONTROL */ 4737 { 4738 PMA_CTLr_t reg_pma_ctrl; 4739 4740 QMOD16_DBG_IN_FUNC_INFO(pc); 4741 PMA_CTLr_CLR(reg_pma_ctrl); 4742 if (enable) { 4743 PMA_CTLr_RSTB_LANEf_SET(reg_pma_ctrl, 1); 4744 PHYMOD_IF_ERR_RETURN (MODIFY_PMA_CTLr(pc, reg_pma_ctrl)); 4745 } else { 4746 /* bit set to 0 for disabling RXP */ 4747 PMA_CTLr_RSTB_LANEf_SET( reg_pma_ctrl, 0); 4748 PHYMOD_IF_ERR_RETURN (MODIFY_PMA_CTLr(pc, reg_pma_ctrl)); 4749 } 4750 return PHYMOD_E_NONE; 4751 } 4752 4753 /*! 4754 @brief tx lane reset and enable of any particular lane 4755 @param pc handle to current TSCE context (#PHYMOD_ST) 4756 @param *reset returns the tx_reset configured. 4757 @param *enable returns the tx_enable configured. 4758 @returns The value PHYMOD_E_NONE upon successful completion. 4759 @details 4760 returns the configured tx lane reset and enable of any particular lane 4761 */ 4762 int qmod16_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable) /* TX_LANE_CONTROL_GET */ 4763 { 4764 MISCr_t reg_misc_ctrl; 4765 4766 QMOD16_DBG_IN_FUNC_INFO(pc); 4767 MISCr_CLR(reg_misc_ctrl); 4768 4769 PHYMOD_IF_ERR_RETURN (READ_MISCr(pc, ®_misc_ctrl)); 4770 *reset = MISCr_RSTB_TX_LANEf_GET(reg_misc_ctrl); 4771 *enable = MISCr_ENABLE_TX_LANEf_GET(reg_misc_ctrl); 4772 4773 return PHYMOD_E_NONE; 4774 } 4775 4776 #ifdef _DV_TB_ 4777 int qmod16_prbs_rx_enable_set(PHYMOD_ST* pc, int enable) 4778 { 4779 return PHYMOD_E_NONE; 4780 } 4781 #endif 4782 4783 #ifdef _DV_TB_ 4784 int qmod16_prbs_tx_enable_set(PHYMOD_ST* pc, int enable) /* PRBS_MODE */ 4785 { 4786 return PHYMOD_E_NONE; 4787 4788 } /* PRBS_MODE */ 4789 #endif 4790 4791 #ifdef _DV_TB_ 4792 int qmod16_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data) /* PRBS_MODE */ 4793 { 4794 return PHYMOD_E_NONE; 4795 4796 } /* PRBS_MODE */ 4797 #endif 4798 4799 #ifdef _DV_TB_ 4800 int qmod16_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode) /* PRBS_MODE */ 4801 { 4802 return PHYMOD_E_NONE; 4803 4804 } /* PRBS_MODE */ 4805 #endif 4806 4807 #ifdef _DV_TB_ 4808 int qmod16_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data) /* PRBS_MODE */ 4809 { 4810 return PHYMOD_E_NONE; 4811 4812 } /* PRBS_MODE */ 4813 #endif 4814 4815 #ifdef _DV_TB_ 4816 int qmod16_prbs_tx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial) /* PRBS_MODE */ 4817 { 4818 return PHYMOD_E_NONE; 4819 4820 } /* PRBS_MODE */ 4821 #endif 4822 4823 #ifdef _DV_TB_ 4824 int qmod16_prbs_rx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial) /* PRBS_MODE */ 4825 { 4826 return PHYMOD_E_NONE; 4827 4828 } /* PRBS_MODE */ 4829 #endif 4830 4831 #ifdef _DV_TB_ 4832 int qmod16_prbs_rx_enable_set(PHYMOD_ST* pc, int enable) 4833 { 4834 return PHYMOD_E_NONE; 4835 } 4836 #endif 4837 4838 /*! 4839 @brief Read the 16 bit rev. id value etc. 4840 @param pc handle to current TSCE context (#PHYMOD_ST) 4841 @param cntl input (see details) 4842 @param value handle to current TSCE context (#PHYMOD_ST) 4843 @returns The value PHYMOD_E_NONE upon successful completion 4844 @details Per Port PMD Override. 4845 Can be enhanced to also configure per core PMD Override 4846 Various bits are enabled as bit encoded by the cntl parameter 4847 \li 0x8000 ln_dp_h_rstb_oen 4848 \li 0x4000 tx_disable_oen 4849 \li 0x2000 rx_dme_en_oen 4850 \li 0x1000 osr_mode_oen 4851 \li 0x0800 lane_mode_oen 4852 \li 0x0400 rx_clk_vld_ovrd 4853 \li 0x0200 signal_detect_ovrd 4854 \li 0x0100 rx_lock_ovrd 4855 4856 */ 4857 int qmod16_pmd_override_control(PHYMOD_ST* pc, int cntl, int value) /* PMD_OVERRIDE_CONTROL */ 4858 { 4859 return PHYMOD_E_NONE; 4860 } 4861 4862 /** 4863 @brief Set subport speed in qsgmii mode 4864 @param pc handle to current TSCE context (#PHYMOD_ST) 4865 @returns The value PHYMOD_E_NONE upon successful completion. 4866 @details Set subport speed in qsgmii mode 4867 4868 */ 4869 4870 int qmod16_set_qport_spd(PHYMOD_ST* pc, int sub_port, qmod16_spd_intfc_type spd_intf) 4871 { 4872 SC_X4_QSGMII_SPDr_t reg_qsgmii_spd; 4873 int speed_id = 0; 4874 4875 QMOD16_DBG_IN_FUNC_INFO(pc); 4876 SC_X4_QSGMII_SPDr_CLR(reg_qsgmii_spd); 4877 4878 if ((spd_intf == QMOD16_SPD_10_SGMII) || (spd_intf == QMOD16_SPD_10_X1_SGMII)) { speed_id = 2; } 4879 if ((spd_intf == QMOD16_SPD_100_SGMII) || (spd_intf == QMOD16_SPD_100_X1_SGMII)) { speed_id = 1; } 4880 if ((spd_intf == QMOD16_SPD_1000_SGMII) || (spd_intf == QMOD16_SPD_1000_X1_SGMII)) { speed_id = 0; } 4881 if (spd_intf == QMOD16_SPD_2500_USXGMII) { speed_id = 3; } 4882 4883 switch(sub_port) { 4884 case 0: SC_X4_QSGMII_SPDr_SPEED_SP0f_SET(reg_qsgmii_spd, speed_id); break ; 4885 case 1: SC_X4_QSGMII_SPDr_SPEED_SP1f_SET(reg_qsgmii_spd, speed_id); break ; 4886 case 2: SC_X4_QSGMII_SPDr_SPEED_SP2f_SET(reg_qsgmii_spd, speed_id); break ; 4887 case 3: SC_X4_QSGMII_SPDr_SPEED_SP3f_SET(reg_qsgmii_spd, speed_id); break ; 4888 default: break ; 4889 } 4890 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_QSGMII_SPDr( pc, reg_qsgmii_spd)); 4891 4892 return PHYMOD_E_NONE; 4893 } 4894 4895 int qmod16_get_qport_spd(PHYMOD_ST* pc, int sub_port, qmod16_spd_intfc_type *spd_intf) 4896 { 4897 SC_X4_QSGMII_SPDr_t reg_qsgmii_spd; 4898 int speed_id = 0; 4899 4900 QMOD16_DBG_IN_FUNC_INFO(pc); 4901 SC_X4_QSGMII_SPDr_CLR(reg_qsgmii_spd); 4902 PHYMOD_IF_ERR_RETURN (READ_SC_X4_QSGMII_SPDr(pc, ®_qsgmii_spd)); 4903 4904 switch (sub_port) { 4905 case 0: 4906 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP0f_GET(reg_qsgmii_spd); 4907 break ; 4908 case 1: 4909 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP1f_GET(reg_qsgmii_spd); 4910 break ; 4911 case 2: 4912 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP2f_GET(reg_qsgmii_spd); 4913 break ; 4914 case 3: 4915 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP3f_GET(reg_qsgmii_spd); 4916 break ; 4917 default: 4918 break ; 4919 } 4920 4921 switch (speed_id) { 4922 case 3: 4923 *spd_intf = QMOD16_SPD_2500_USXGMII; 4924 break; 4925 case 2: 4926 *spd_intf = QMOD16_SPD_10_SGMII; 4927 break; 4928 case 1: 4929 *spd_intf = QMOD16_SPD_100_SGMII; 4930 break; 4931 default: 4932 *spd_intf = QMOD16_SPD_1000_SGMII; 4933 break; 4934 } 4935 4936 return PHYMOD_E_NONE; 4937 } 4938 4939 /* 4940 @brief use spare registers to get the state info for shared QSGMII ports. 4941 @param pc handle to current TSCE context (#PHYMOD_ST) 4942 @param qmod16_state_type has MOD_PORT_STATE_CONFIGED(1), 4943 QMOD16_PORT_STATE_TX_SQUELCH(2), QMOD16_PORT_STATE_RX_SQUELCH(3). 4944 @param sub_port and value to choose which bit to set. 4945 @param all_sub_port_val returns all shared ports information. 4946 @returns The value PHYMOD_E_NONE upon successful completion. 4947 4948 These set/get functions will set and get the state info for shared QSGMII ports 4949 that might affect how each lane will react to BCM APIs. 4950 */ 4951 int qmod16_port_state_set(PHYMOD_ST* pc, int qmod16_state_type, int sub_port, int val) 4952 { 4953 SPARE0r_t reg_spare0 ; 4954 SPARE1r_t reg_spare1 ; 4955 int all_sub_port_val = 0; 4956 4957 QMOD16_DBG_IN_FUNC_INFO(pc); 4958 SPARE0r_CLR(reg_spare0); 4959 SPARE1r_CLR(reg_spare1); 4960 switch (qmod16_state_type) { 4961 case QMOD16_PORT_STATE_CONFIGED: 4962 PHYMOD_IF_ERR_RETURN(READ_SPARE0r(pc, ®_spare0)); 4963 all_sub_port_val = SPARE0r_SPARE0f_GET(reg_spare0) & 0xf; 4964 if (val) { 4965 all_sub_port_val |= 1<< sub_port; 4966 } else { 4967 all_sub_port_val = all_sub_port_val & ~(1 << sub_port); 4968 } 4969 SPARE0r_SPARE0f_SET(reg_spare0, all_sub_port_val); 4970 PHYMOD_IF_ERR_RETURN(WRITE_SPARE0r(pc, reg_spare0)); 4971 break; 4972 case QMOD16_PORT_STATE_TX_SQUELCH: 4973 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 4974 all_sub_port_val = SPARE1r_SPARE1f_GET(reg_spare1); 4975 if (val) { 4976 all_sub_port_val |= 1<< sub_port; 4977 } else { 4978 all_sub_port_val = all_sub_port_val & ~(1 << sub_port); 4979 } 4980 SPARE1r_SPARE1f_SET(reg_spare1, all_sub_port_val); 4981 PHYMOD_IF_ERR_RETURN(WRITE_SPARE1r(pc, reg_spare1)); 4982 break; 4983 case QMOD16_PORT_STATE_RX_SQUELCH: 4984 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 4985 all_sub_port_val = SPARE1r_SPARE1f_GET(reg_spare1); 4986 if (val) { 4987 all_sub_port_val |= 1<< (sub_port+4); 4988 } else { 4989 all_sub_port_val = all_sub_port_val & ~(1 << (sub_port+4)); 4990 } 4991 SPARE1r_SPARE1f_SET(reg_spare1, all_sub_port_val); 4992 PHYMOD_IF_ERR_RETURN(WRITE_SPARE1r(pc, reg_spare1)); 4993 break; 4994 default: 4995 return PHYMOD_E_PARAM; 4996 break; 4997 } 4998 return PHYMOD_E_NONE; 4999 } 5000 5001 int qmod16_port_state_get(PHYMOD_ST* pc, int qmod16_state_type, int *all_sub_port_val) 5002 { 5003 SPARE0r_t reg_spare0 ; 5004 SPARE1r_t reg_spare1 ; 5005 5006 QMOD16_DBG_IN_FUNC_INFO(pc); 5007 SPARE0r_CLR(reg_spare0); 5008 SPARE1r_CLR(reg_spare1); 5009 switch (qmod16_state_type) { 5010 case QMOD16_PORT_STATE_CONFIGED: 5011 PHYMOD_IF_ERR_RETURN(READ_SPARE0r(pc, ®_spare0)); 5012 *all_sub_port_val = SPARE0r_SPARE0f_GET(reg_spare0) & 0xf; 5013 break; 5014 case QMOD16_PORT_STATE_TX_SQUELCH: 5015 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 5016 *all_sub_port_val = SPARE1r_SPARE1f_GET(reg_spare1) & 0xf; 5017 break; 5018 case QMOD16_PORT_STATE_RX_SQUELCH: 5019 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 5020 *all_sub_port_val = (SPARE1r_SPARE1f_GET(reg_spare1) >> 4) & 0xf; 5021 break; 5022 default: 5023 return PHYMOD_E_PARAM; 5024 break; 5025 } 5026 return PHYMOD_E_NONE; 5027 } 5028 5029 #ifdef _DV_TB_ 5030 /** 5031 @brief Set qsgmii_en for tx and rx 5032 @param pc handle to current TSCE context (#PHYMOD_ST) 5033 @returns The value PHYMOD_E_NONE upon successful completion. 5034 @details Set subport speed in qsgmii mode 5035 5036 */ 5037 5038 int qmod16_set_qsgmii_en(PHYMOD_ST* pc) 5039 { 5040 CL36TX_CTLr_t reg_cl36tx_ctl; 5041 CL36_RXr_t reg_cl36_rx; 5042 5043 QMOD16_DBG_IN_FUNC_INFO(pc); 5044 CL36TX_CTLr_CLR(reg_cl36tx_ctl); 5045 CL36_RXr_CLR(reg_cl36_rx); 5046 5047 CL36TX_CTLr_QSGMII_ENf_SET(reg_cl36tx_ctl, pc->qsgmii_mode); 5048 CL36_RXr_QSGMII_ENf_SET(reg_cl36_rx, pc->qsgmii_mode); 5049 5050 PHYMOD_IF_ERR_RETURN (MODIFY_CL36TX_CTLr( pc, reg_cl36tx_ctl)); 5051 PHYMOD_IF_ERR_RETURN (MODIFY_CL36_RXr( pc, reg_cl36_rx)); 5052 5053 return PHYMOD_E_NONE; 5054 } 5055 #endif 5056 5057 int qmod16_speedchange_get (PHYMOD_ST *pc, uint32_t* enable) 5058 { 5059 SC_X4_CTLr_t reg_sc_ctrl; 5060 5061 QMOD16_DBG_IN_FUNC_INFO(pc); 5062 SC_X4_CTLr_CLR(reg_sc_ctrl); 5063 5064 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc,®_sc_ctrl)); 5065 *enable = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 5066 5067 return PHYMOD_E_NONE; 5068 } 5069 5070 int qmod16_get_plldiv (PHYMOD_ST *pc, uint32_t *pll_mode) 5071 { 5072 5073 uint32_t pll_div; 5074 5075 PHYMOD_IF_ERR_RETURN 5076 (merlin16_INTERNAL_read_pll_div(pc, &pll_div)); 5077 5078 /* merlin16_INTERNAL_read_pll_div() puts one of merlin16_pll_div_enum 5079 * as the returned value in pll_div 5080 */ 5081 switch (pll_div) { 5082 case 0x00000046UL: *pll_mode = QMOD16_PLL_MODE_DIV_70; 5083 break; 5084 case 0x00000042UL: *pll_mode = QMOD16_PLL_MODE_DIV_66; 5085 break; 5086 case 0x00000040UL: *pll_mode = QMOD16_PLL_MODE_DIV_64; 5087 break; 5088 case 0x0000003CUL: *pll_mode = QMOD16_PLL_MODE_DIV_60; 5089 break; 5090 case 0x0000005CUL: *pll_mode = QMOD16_PLL_MODE_DIV_92; 5091 break; 5092 case 0x00000050UL: *pll_mode = QMOD16_PLL_MODE_DIV_80; 5093 break; 5094 default: return PHYMOD_E_NONE; 5095 break; 5096 } 5097 5098 return PHYMOD_E_NONE; 5099 } 5100 5101 int qmod16_master_port_num_set ( PHYMOD_ST *pc, int port_num) 5102 { 5103 MAIN_SETUPr_t main_reg; 5104 5105 MAIN_SETUPr_CLR(main_reg); 5106 MAIN_SETUPr_MASTER_PORT_NUMf_SET(main_reg, port_num); 5107 MODIFY_MAIN_SETUPr(pc, main_reg); 5108 5109 return PHYMOD_E_NONE; 5110 } 5111 5112 int qmod16_pcs_lane_swap_get (PHYMOD_ST *pc, uint32_t *tx_swap, uint32_t *rx_swap) 5113 { 5114 unsigned int pcs_map; 5115 MAIN_LN_SWPr_t reg; 5116 QMOD16_DBG_IN_FUNC_INFO(pc); 5117 5118 MAIN_LN_SWPr_CLR(reg); 5119 5120 PHYMOD_IF_ERR_RETURN 5121 (READ_MAIN_LN_SWPr(pc, ®)) ; 5122 5123 pcs_map = MAIN_LN_SWPr_GET(reg); 5124 5125 *tx_swap = (((pcs_map >> 0) & 0x3) << 0) | 5126 (((pcs_map >> 2) & 0x3) << 4) | 5127 (((pcs_map >> 4) & 0x3) << 8) | 5128 (((pcs_map >> 6) & 0x3) << 12) ; 5129 5130 *rx_swap = (((pcs_map >> 8) & 0x3) << 0) | 5131 (((pcs_map >> 10) & 0x3) << 4) | 5132 (((pcs_map >> 12) & 0x3) << 8) | 5133 (((pcs_map >> 14) & 0x3) << 12) ; 5134 5135 return PHYMOD_E_NONE ; 5136 } 5137 5138 5139 int qmod16_pll_reset_enable_set ( PHYMOD_ST *pc , int enable) 5140 { 5141 MAIN_SETUPr_t main_reg; 5142 5143 MAIN_SETUPr_CLR(main_reg); 5144 MAIN_SETUPr_PLL_RESET_ENf_SET(main_reg, enable); 5145 MODIFY_MAIN_SETUPr(pc, main_reg); 5146 return PHYMOD_E_NONE ; 5147 } 5148 5149 5150 /*! 5151 @brief get port speed id configured 5152 @param pc handle to current TSCE context (#PHYMOD_ST) 5153 @param speed_id Receives the the resolved speed cfg as recorded in h/w 5154 @returns The value PHYMOD_E_NONE upon successful completion. 5155 @details get port speed configured 5156 */ 5157 int qmod16_speed_id_get ( PHYMOD_ST *pc, int *speed_id, int subport) 5158 { 5159 SC_X4_FI_SP0_RSLVD_SPDr_t sc_final_sp0_resolved_speed; 5160 SC_X4_FI_SP0_RSLVD0r_t sc_final_sp0_resolved_0; 5161 SC_X4_FI_SP1_RSLVD0r_t sc_final_sp1_resolved_0; 5162 SC_X4_FI_SP2_RSLVD0r_t sc_final_sp2_resolved_0; 5163 SC_X4_FI_SP3_RSLVD0r_t sc_final_sp3_resolved_0; 5164 SC_X4_QSGMII_SPDr_t sc_qsgmii_spd; 5165 int sp_spd_id; 5166 5167 QMOD16_DBG_IN_FUNC_INFO(pc); 5168 5169 SC_X4_FI_SP0_RSLVD_SPDr_CLR(sc_final_sp0_resolved_speed); 5170 SC_X4_FI_SP0_RSLVD0r_CLR(sc_final_sp0_resolved_0); 5171 SC_X4_FI_SP1_RSLVD0r_CLR(sc_final_sp1_resolved_0); 5172 SC_X4_FI_SP2_RSLVD0r_CLR(sc_final_sp2_resolved_0); 5173 SC_X4_FI_SP3_RSLVD0r_CLR(sc_final_sp3_resolved_0); 5174 SC_X4_QSGMII_SPDr_CLR(sc_qsgmii_spd); 5175 5176 /* next check if we are in qsgmii mode */ 5177 if (PHYMOD_ACC_F_QMODE_GET(pc)) { 5178 switch (subport) { 5179 case 1: 5180 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD0r(pc,&sc_final_sp1_resolved_0)); 5181 sp_spd_id = SC_X4_FI_SP1_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp1_resolved_0); 5182 break ; 5183 case 2: 5184 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD0r(pc,&sc_final_sp2_resolved_0)); 5185 sp_spd_id = SC_X4_FI_SP2_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp2_resolved_0); 5186 break ; 5187 case 3: 5188 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD0r(pc,&sc_final_sp3_resolved_0)); 5189 sp_spd_id = SC_X4_FI_SP3_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp3_resolved_0); 5190 break ; 5191 default: 5192 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD0r(pc,&sc_final_sp0_resolved_0)); /* 0xc041 */ 5193 sp_spd_id = SC_X4_FI_SP0_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp0_resolved_0); 5194 break ; 5195 } 5196 switch (sp_spd_id) { 5197 case 0: 5198 sp_spd_id = digital_operationSpeeds_SPEED_100M; 5199 break; 5200 case 1: 5201 sp_spd_id = digital_operationSpeeds_SPEED_10M; 5202 break; 5203 default: 5204 sp_spd_id = digital_operationSpeeds_SPEED_1000M; 5205 break; 5206 } 5207 } else if (PHYMOD_ACC_F_USXMODE_GET(pc)) { 5208 PHYMOD_IF_ERR_RETURN(READ_SC_X4_QSGMII_SPDr(pc, &sc_qsgmii_spd)); 5209 switch (subport) { 5210 case 1: 5211 sp_spd_id = SC_X4_QSGMII_SPDr_SPEED_SP1f_GET(sc_qsgmii_spd); 5212 break ; 5213 case 2: 5214 sp_spd_id = SC_X4_QSGMII_SPDr_SPEED_SP2f_GET(sc_qsgmii_spd); 5215 break ; 5216 case 3: 5217 sp_spd_id = SC_X4_QSGMII_SPDr_SPEED_SP3f_GET(sc_qsgmii_spd); 5218 break ; 5219 default: 5220 sp_spd_id = SC_X4_QSGMII_SPDr_SPEED_SP0f_GET(sc_qsgmii_spd); 5221 break ; 5222 } 5223 switch (sp_spd_id) { 5224 case 0: 5225 sp_spd_id = digital_operationSpeeds_SPEED_1000M; 5226 break; 5227 case 1: 5228 sp_spd_id = digital_operationSpeeds_SPEED_100M; 5229 break; 5230 case 2: 5231 sp_spd_id = digital_operationSpeeds_SPEED_10M; 5232 break; 5233 default: 5234 sp_spd_id = digital_operationSpeeds_SPEED_2p5G_X1; 5235 break; 5236 } 5237 } else { 5238 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD_SPDr(pc,&sc_final_sp0_resolved_speed)); 5239 sp_spd_id = SC_X4_FI_SP0_RSLVD_SPDr_SPEEDf_GET(sc_final_sp0_resolved_speed); 5240 } 5241 5242 *speed_id = sp_spd_id ; 5243 5244 return PHYMOD_E_NONE; 5245 } 5246 5247 /** 5248 @brief Gets the TX And RX Polarity 5249 @param pc handle to current TSCE context (#PHYMOD_ST) 5250 @param tx_polarity Receive Polarity for TX side 5251 @param rx_polarity Receive Polarity for RX side 5252 @returns The value PHYMOD_E_NONE upon successful completion. 5253 @details Gets the TX And RX Polarity 5254 */ 5255 int qmod16_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity) 5256 { 5257 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 5258 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 5259 5260 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_TLB_TX_MISC_CFGr(pc, &tx_pol_inv)); 5261 *tx_polarity = TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv); 5262 5263 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_TLB_RX_MISC_CFGr(pc, &rx_pol_inv)); 5264 *rx_polarity = TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv); 5265 5266 return PHYMOD_E_NONE; 5267 } 5268 5269 /** 5270 @brief Sets the TX And RX Polarity 5271 @param pc handle to current TSCE context (#PHYMOD_ST) 5272 @param tx_polarity Control Polarity for TX side 5273 @param rx_polarity Control Polarity for RX side 5274 @returns The value PHYMOD_E_NONE upon successful completion. 5275 @details Sets the TX And RX Polarity 5276 */ 5277 int qmod16_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity) 5278 { 5279 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 5280 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 5281 5282 TLB_TX_TLB_TX_MISC_CFGr_CLR(tx_pol_inv); 5283 TLB_RX_TLB_RX_MISC_CFGr_CLR(rx_pol_inv); 5284 5285 TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pol_inv, tx_polarity); 5286 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_TLB_TX_MISC_CFGr(pc, tx_pol_inv)); 5287 5288 TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pol_inv, rx_polarity); 5289 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_TLB_RX_MISC_CFGr(pc, rx_pol_inv)); 5290 5291 return PHYMOD_E_NONE; 5292 } 5293 5294 int qmod16_clause72_control(PHYMOD_ST *pc, int cl72_en) 5295 { 5296 uint32_t enable = 0; 5297 PHYMOD_ST* sa__ = pc; 5298 5299 PHYMOD_IF_ERR_RETURN(wr_cl72_ieee_training_enable(cl72_en)); 5300 PHYMOD_IF_ERR_RETURN(wr_cl72_ieee_restart_training(cl72_en)); 5301 5302 PHYMOD_IF_ERR_RETURN(qmod16_disable_get(pc, &enable)); 5303 if (enable == 0x1) { 5304 PHYMOD_IF_ERR_RETURN(qmod16_trigger_speed_change(pc)); 5305 } 5306 5307 return PHYMOD_E_NONE; 5308 } 5309 5310 /** 5311 @brief Set the port speed and enable the port 5312 @param pc handle to current QTCE context (#PHYMOD_ST) 5313 @param spd_intf the speed to set the port enum #qmod16_set_spd_intf 5314 @returns The value PHYMOD_E_NONE upon successful completion 5315 @details Sets the port to the specified speed and triggers the port, and waits 5316 for the port to be configured 5317 */ 5318 int qmod16_set_spd_intf(PHYMOD_ST *pc, qmod16_spd_intfc_type spd_intf, int no_trig) 5319 { 5320 SC_X4_CTLr_t xgxs_x4_ctrl; 5321 int speed_id = 0; 5322 5323 QMOD16_DBG_IN_FUNC_INFO(pc); 5324 5325 PHYMOD_IF_ERR_RETURN (qmod16_get_mapped_speed(spd_intf, &speed_id)); 5326 /* write the speed_id into the speed_change register */ 5327 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 5328 SC_X4_CTLr_SW_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 5329 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 5330 /*next call the speed_change routine */ 5331 if (no_trig) { 5332 5333 } else { 5334 PHYMOD_IF_ERR_RETURN (qmod16_trigger_speed_change(pc)); 5335 /* removed check for the speed_change_done init*/ 5336 } 5337 return PHYMOD_E_NONE; 5338 } 5339 5340 /** 5341 @brief to figure out the lane id and sub port id from the lane mask 5342 @param pc handle to current QTCE context (#PHYMOD_ST) 5343 @returns The value PHYMOD_E_NONE upon successful completion 5344 @details based on lane mask and QMODE flag to decide the real 5345 lane id and sub port id. 5346 */ 5347 int qmod16_lane_info(PHYMOD_ST *pa, int *lane, int *sub_port) 5348 { 5349 int i = 0 ; uint32_t mask ; 5350 mask = pa->lane_mask ; 5351 *lane = 0 ; *sub_port=0 ; 5352 if (mask==0) return PHYMOD_E_INTERNAL ; 5353 while (1) { 5354 if (mask & 0xf) { 5355 switch (mask) { 5356 case 0x1: *sub_port=0 ; break ; 5357 case 0x2: *sub_port=1 ; break ; 5358 case 0x4: *sub_port=2 ; break ; 5359 case 0x8: *sub_port=3 ; break ; 5360 case 0xf: *sub_port=0 ; break ; 5361 default: 5362 return PHYMOD_E_INTERNAL ; break; 5363 } 5364 } 5365 mask = mask >> 4; 5366 if (mask) { 5367 i++ ; 5368 } else { 5369 break ; 5370 } 5371 } 5372 *lane = i ; 5373 if (!(PHYMOD_ACC_F_QMODE_GET(pa) || PHYMOD_ACC_F_USXMODE_GET(pa))) { /* no qmode */ 5374 *lane = *sub_port; *sub_port=0; 5375 } 5376 return PHYMOD_E_NONE ; 5377 } 5378 5379 /** 5380 @brief EEE Control Set 5381 @param pc handle to current QTCE context (#PHYMOD_ST) 5382 @param enable enable or disable EEE control 5383 @returns The value PHYMOD_E_NONE upon successful completion 5384 @details EEE Control 5385 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 5386 enable =0 : Convert LPI to idle. So MAC will not see it. 5387 5388 */ 5389 int qmod16_eee_control_set(PHYMOD_ST* pc, uint32_t enable) 5390 { 5391 /* PCS_CTLr_t is for writing the RX reg; CL36TX_CTLr_t is for writing the TX reg */ 5392 PCS_CTLr_t reg_pcs_or_val; 5393 CL36TX_CTLr_t reg_cl36_or_val; 5394 TX_X4_CL49_CTL0_TX_ENC_CTL0r_t reg_cl49_ctl0_enc_val; 5395 RX_X4_CL49_CTL0_DEC_CTL0r_t reg_cl49_ctl0_dec_val; 5396 5397 QMOD16_DBG_IN_FUNC_INFO(pc); 5398 5399 if ( PHYMOD_ACC_F_USXMODE_GET(pc)) { 5400 /* USXGMII LPI */ 5401 TX_X4_CL49_CTL0_TX_ENC_CTL0r_CLR(reg_cl49_ctl0_enc_val); 5402 TX_X4_CL49_CTL0_TX_ENC_CTL0r_TX_LPI_ENABLEf_SET(reg_cl49_ctl0_enc_val, enable & 0x1); 5403 PHYMOD_IF_ERR_RETURN (MODIFY_TX_X4_CL49_CTL0_TX_ENC_CTL0r(pc, reg_cl49_ctl0_enc_val)); 5404 5405 RX_X4_CL49_CTL0_DEC_CTL0r_CLR(reg_cl49_ctl0_dec_val); 5406 RX_X4_CL49_CTL0_DEC_CTL0r_LPI_ENABLEf_SET(reg_cl49_ctl0_dec_val, enable & 0x1); 5407 PHYMOD_IF_ERR_RETURN (MODIFY_RX_X4_CL49_CTL0_DEC_CTL0r(pc, reg_cl49_ctl0_dec_val)); 5408 } else { 5409 PCS_CTLr_CLR(reg_pcs_or_val); 5410 CL36TX_CTLr_CLR(reg_cl36_or_val); 5411 5412 PCS_CTLr_LPI_ENABLEf_SET(reg_pcs_or_val, enable & 0x1); 5413 PHYMOD_IF_ERR_RETURN (MODIFY_PCS_CTLr(pc, reg_pcs_or_val)); 5414 5415 CL36TX_CTLr_CL36TX_LPI_ENf_SET(reg_cl36_or_val, enable & 0x1); 5416 PHYMOD_IF_ERR_RETURN (MODIFY_CL36TX_CTLr(pc, reg_cl36_or_val)); 5417 } 5418 5419 return PHYMOD_E_NONE; 5420 } 5421 5422 /** 5423 @brief EEE Control Get 5424 @param pc handle to current QTCE context (#PHYMOD_ST) 5425 @param enable handle to pass back EEE control 5426 @returns The value PHYMOD_E_NONE upon successful completion 5427 @details EEE Control 5428 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 5429 enable =0 : Convert LPI to idle. So MAC will not see it. 5430 5431 */ 5432 int qmod16_eee_control_get(PHYMOD_ST* pc, uint32_t *enable) 5433 { 5434 /* PCS_CTLr_t is for reading the RX reg */ 5435 PCS_CTLr_t reg_pcs_or_val; 5436 TX_X4_CL49_CTL0_TX_ENC_CTL0r_t reg_cl49_ctl0_enc_val; 5437 5438 QMOD16_DBG_IN_FUNC_INFO(pc); 5439 5440 if ( PHYMOD_ACC_F_USXMODE_GET(pc)) { 5441 TX_X4_CL49_CTL0_TX_ENC_CTL0r_CLR(reg_cl49_ctl0_enc_val); 5442 PHYMOD_IF_ERR_RETURN (READ_TX_X4_CL49_CTL0_TX_ENC_CTL0r(pc, ®_cl49_ctl0_enc_val)); 5443 *enable = TX_X4_CL49_CTL0_TX_ENC_CTL0r_TX_LPI_ENABLEf_GET(reg_cl49_ctl0_enc_val); 5444 } 5445 else { 5446 PCS_CTLr_CLR(reg_pcs_or_val); 5447 PHYMOD_IF_ERR_RETURN (READ_PCS_CTLr(pc, ®_pcs_or_val)); 5448 *enable = PCS_CTLr_LPI_ENABLEf_GET(reg_pcs_or_val); 5449 } 5450 5451 return PHYMOD_E_NONE; 5452 } 5453 5454 STATIC 5455 int _qmod16_rx_phy_lane_get(PHYMOD_ST *pc, int rx_logical_lane, int* rx_phy_lane) 5456 { 5457 MAIN_LN_SWPr_t reg_lane_swap; 5458 phymod_access_t pa_copy; 5459 5460 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5461 5462 /*always use lane 0 copy since register is single copy */ 5463 pa_copy.lane_mask = 0x1; 5464 5465 PHYMOD_IF_ERR_RETURN 5466 (READ_MAIN_LN_SWPr(&pa_copy, ®_lane_swap)); 5467 5468 switch (rx_logical_lane) { 5469 case 0: 5470 *rx_phy_lane = MAIN_LN_SWPr_LOG0_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5471 break; 5472 case 1: 5473 *rx_phy_lane = MAIN_LN_SWPr_LOG1_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5474 break; 5475 case 2: 5476 *rx_phy_lane = MAIN_LN_SWPr_LOG2_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5477 break; 5478 case 3: 5479 *rx_phy_lane = MAIN_LN_SWPr_LOG3_TO_PHY_RX_LNSWAP_SELf_GET(reg_lane_swap); 5480 break; 5481 default: 5482 return PHYMOD_E_PARAM; 5483 } 5484 5485 return PHYMOD_E_NONE; 5486 } 5487 5488 int qmod16_synce_mode_set(PHYMOD_ST *pc, int mode0, int mode1) 5489 { 5490 int start_lane = 0, num_lane = 0, phy_lane = 0; 5491 MAIN_SYNCE_CTLr_t reg_main_synce_ctl; 5492 5493 PHYMOD_IF_ERR_RETURN 5494 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5495 5496 PHYMOD_IF_ERR_RETURN 5497 (_qmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5498 5499 MAIN_SYNCE_CTLr_CLR(reg_main_synce_ctl); 5500 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_CTLr(pc, ®_main_synce_ctl)); 5501 5502 switch(phy_lane) { 5503 case 0: 5504 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN0f_SET(reg_main_synce_ctl, mode0); 5505 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN0f_SET(reg_main_synce_ctl, mode1); 5506 break; 5507 case 1: 5508 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN1f_SET(reg_main_synce_ctl, mode0); 5509 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN1f_SET(reg_main_synce_ctl, mode1); 5510 break; 5511 case 2: 5512 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN2f_SET(reg_main_synce_ctl, mode0); 5513 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN2f_SET(reg_main_synce_ctl, mode1); 5514 break; 5515 case 3: 5516 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN3f_SET(reg_main_synce_ctl, mode0); 5517 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN3f_SET(reg_main_synce_ctl, mode1); 5518 break; 5519 default: 5520 return PHYMOD_E_PARAM; 5521 } 5522 5523 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SYNCE_CTLr(pc, reg_main_synce_ctl)); 5524 5525 return PHYMOD_E_NONE; 5526 } 5527 5528 int qmod16_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val) 5529 { 5530 int start_lane = 0, num_lane = 0, phy_lane = 0; 5531 MAIN_SYNCE_DIVISOR0_PHY_LN0r_t reg_synce_divisor_lane0; 5532 MAIN_SYNCE_DIVISOR1_PHY_LN1r_t reg_synce_divisor_lane1; 5533 MAIN_SYNCE_DIVISOR2_PHY_LN2r_t reg_synce_divisor_lane2; 5534 MAIN_SYNCE_DIVISOR3_PHY_LN3r_t reg_synce_divisor_lane3; 5535 5536 PHYMOD_IF_ERR_RETURN 5537 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5538 5539 PHYMOD_IF_ERR_RETURN 5540 (_qmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5541 5542 switch(phy_lane) { 5543 case 0: 5544 MAIN_SYNCE_DIVISOR0_PHY_LN0r_CLR(reg_synce_divisor_lane0); 5545 MAIN_SYNCE_DIVISOR0_PHY_LN0r_SET(reg_synce_divisor_lane0, val); 5546 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR0_PHY_LN0r(pc, reg_synce_divisor_lane0)); 5547 break; 5548 case 1: 5549 MAIN_SYNCE_DIVISOR1_PHY_LN1r_CLR(reg_synce_divisor_lane1); 5550 MAIN_SYNCE_DIVISOR1_PHY_LN1r_SET(reg_synce_divisor_lane1, val); 5551 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR1_PHY_LN1r(pc, reg_synce_divisor_lane1)); 5552 break; 5553 case 2: 5554 MAIN_SYNCE_DIVISOR2_PHY_LN2r_CLR(reg_synce_divisor_lane2); 5555 MAIN_SYNCE_DIVISOR2_PHY_LN2r_SET(reg_synce_divisor_lane2, val); 5556 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR2_PHY_LN2r(pc, reg_synce_divisor_lane2)); 5557 break; 5558 case 3: 5559 MAIN_SYNCE_DIVISOR3_PHY_LN3r_CLR(reg_synce_divisor_lane3); 5560 MAIN_SYNCE_DIVISOR3_PHY_LN3r_SET(reg_synce_divisor_lane3, val); 5561 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR3_PHY_LN3r(pc, reg_synce_divisor_lane3)); 5562 break; 5563 default: 5564 return PHYMOD_E_PARAM; 5565 } 5566 5567 return PHYMOD_E_NONE; 5568 } 5569 5570 int qmod16_synce_mode_get(PHYMOD_ST *pc, int *mode0, int *mode1) 5571 { 5572 int start_lane = 0, num_lane = 0, phy_lane = 0; 5573 MAIN_SYNCE_CTLr_t reg_main_synce_ctl; 5574 5575 PHYMOD_IF_ERR_RETURN 5576 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5577 5578 PHYMOD_IF_ERR_RETURN 5579 (_qmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5580 5581 MAIN_SYNCE_CTLr_CLR(reg_main_synce_ctl); 5582 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_CTLr(pc, ®_main_synce_ctl)); 5583 5584 switch(phy_lane) { 5585 case 0: 5586 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN0f_GET(reg_main_synce_ctl); 5587 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN0f_GET(reg_main_synce_ctl); 5588 break; 5589 case 1: 5590 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN1f_GET(reg_main_synce_ctl); 5591 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN1f_GET(reg_main_synce_ctl); 5592 break; 5593 case 2: 5594 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN2f_GET(reg_main_synce_ctl); 5595 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN2f_GET(reg_main_synce_ctl); 5596 break; 5597 case 3: 5598 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN3f_GET(reg_main_synce_ctl); 5599 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN3f_GET(reg_main_synce_ctl); 5600 break; 5601 default: 5602 return PHYMOD_E_PARAM; 5603 } 5604 5605 return PHYMOD_E_NONE; 5606 } 5607 5608 int qmod16_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val) 5609 { 5610 int start_lane = 0, num_lane = 0, phy_lane = 0; 5611 MAIN_SYNCE_DIVISOR0_PHY_LN0r_t reg_synce_divisor_lane0; 5612 MAIN_SYNCE_DIVISOR1_PHY_LN1r_t reg_synce_divisor_lane1; 5613 MAIN_SYNCE_DIVISOR2_PHY_LN2r_t reg_synce_divisor_lane2; 5614 MAIN_SYNCE_DIVISOR3_PHY_LN3r_t reg_synce_divisor_lane3; 5615 5616 PHYMOD_IF_ERR_RETURN 5617 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5618 5619 PHYMOD_IF_ERR_RETURN 5620 (_qmod16_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5621 5622 switch(phy_lane) { 5623 case 0: 5624 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR0_PHY_LN0r(pc, ®_synce_divisor_lane0)); 5625 *val = MAIN_SYNCE_DIVISOR0_PHY_LN0r_GET(reg_synce_divisor_lane0); 5626 break; 5627 case 1: 5628 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR1_PHY_LN1r(pc, ®_synce_divisor_lane1)); 5629 *val = MAIN_SYNCE_DIVISOR1_PHY_LN1r_GET(reg_synce_divisor_lane1); 5630 break; 5631 case 2: 5632 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR2_PHY_LN2r(pc, ®_synce_divisor_lane2)); 5633 *val = MAIN_SYNCE_DIVISOR2_PHY_LN2r_GET(reg_synce_divisor_lane2); 5634 break; 5635 case 3: 5636 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR3_PHY_LN3r(pc, ®_synce_divisor_lane3)); 5637 *val = MAIN_SYNCE_DIVISOR3_PHY_LN3r_GET(reg_synce_divisor_lane3); 5638 break; 5639 default: 5640 return PHYMOD_E_PARAM; 5641 } 5642 5643 return PHYMOD_E_NONE; 5644 } 5645 5646 #ifdef _DV_TB_ 5647 /* 5648 @brief Set AM insert interval 5649 @param pc handle to current TSCE context (#PHYMOD_ST) 5650 @returns The value PHYMOD_E_NONE upon successful completion. 5651 @details Set AM insert interval 5652 */ 5653 5654 int qmod16_set_am_insert_intval(PHYMOD_ST* pc, int am_insert_intval) 5655 { 5656 USXGMII_AM_INSERTION_INTERVALr_t reg_am_insert_intval; 5657 5658 QMOD16_DBG_IN_FUNC_INFO(pc); 5659 USXGMII_AM_INSERTION_INTERVALr_CLR(reg_am_insert_intval); 5660 5661 printf("qmod_set_am_insert_intval() : AM_INSERTION_INTERVAL %04x\n", am_insert_intval); 5662 5663 USXGMII_AM_INSERTION_INTERVALr_AM_INSERTION_INTERVALf_SET(reg_am_insert_intval, am_insert_intval); 5664 PHYMOD_IF_ERR_RETURN (MODIFY_USXGMII_AM_INSERTION_INTERVALr( pc, reg_am_insert_intval)); 5665 5666 return PHYMOD_E_NONE; 5667 } 5668 5669 /* 5670 @brief Set preserve preamble 5671 @param pc handle to current TSCE context (#PHYMOD_ST) 5672 @returns The value PHYMOD_E_NONE upon successful completion. 5673 @details Set preserve preamble 5674 */ 5675 5676 int qmod16_set_preserve_preamble(PHYMOD_ST* pc, int preserve_preamble) 5677 { 5678 MAIN_SETUPr_t reg_main_setup; 5679 5680 QMOD16_DBG_IN_FUNC_INFO(pc); 5681 MAIN_SETUPr_CLR(reg_main_setup); 5682 5683 printf("qmod_set_preserve_preamble() : PRESERVE_PREAMBLE %04x\n", preserve_preamble); 5684 5685 MAIN_SETUPr_PRESERVE_PREAMBLEf_SET(reg_main_setup, preserve_preamble); 5686 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN_SETUPr( pc, reg_main_setup)); 5687 5688 return PHYMOD_E_NONE; 5689 } 5690 #endif