qe16PCSRegEnums.h (175462B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 #ifndef __PCS_ENUMS_H__ 8 #define __PCS_ENUMS_H__ 9 /**************************************************************************** 10 * Core Enums. 11 */ 12 /**************************************************************************** 13 * Enums: an_x4_sw_management_cl36TxEEEStates_l 14 */ 15 #define an_x4_sw_management_cl36TxEEEStates_l_TX_REFRESH 8 16 #define an_x4_sw_management_cl36TxEEEStates_l_TX_QUIET 4 17 #define an_x4_sw_management_cl36TxEEEStates_l_TX_SLEEP 2 18 #define an_x4_sw_management_cl36TxEEEStates_l_TX_ACTIVE 1 19 20 /**************************************************************************** 21 * Enums: an_x4_sw_management_cl36TxEEEStates_c 22 */ 23 #define an_x4_sw_management_cl36TxEEEStates_c_TX_REFRESH 3 24 #define an_x4_sw_management_cl36TxEEEStates_c_TX_QUIET 2 25 #define an_x4_sw_management_cl36TxEEEStates_c_TX_SLEEP 1 26 #define an_x4_sw_management_cl36TxEEEStates_c_TX_ACTIVE 0 27 28 /**************************************************************************** 29 * Enums: an_x4_sw_management_cl49TxEEEStates_l 30 */ 31 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_2 64 32 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_1 32 33 #define an_x4_sw_management_cl49TxEEEStates_l_TX_WAKE 16 34 #define an_x4_sw_management_cl49TxEEEStates_l_TX_REFRESH 8 35 #define an_x4_sw_management_cl49TxEEEStates_l_TX_QUIET 4 36 #define an_x4_sw_management_cl49TxEEEStates_l_TX_SLEEP 2 37 #define an_x4_sw_management_cl49TxEEEStates_l_TX_ACTIVE 1 38 39 /**************************************************************************** 40 * Enums: an_x4_sw_management_cl49TxEEEStates_c 41 */ 42 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_2 6 43 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_1 5 44 #define an_x4_sw_management_cl49TxEEEStates_c_TX_WAKE 4 45 #define an_x4_sw_management_cl49TxEEEStates_c_TX_REFRESH 3 46 #define an_x4_sw_management_cl49TxEEEStates_c_TX_QUIET 2 47 #define an_x4_sw_management_cl49TxEEEStates_c_TX_SLEEP 1 48 #define an_x4_sw_management_cl49TxEEEStates_c_TX_ACTIVE 0 49 50 /**************************************************************************** 51 * Enums: an_x4_sw_management_cl36RxEEEStates_l 52 */ 53 #define an_x4_sw_management_cl36RxEEEStates_l_RX_LINK_FAIL 32 54 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WTF 16 55 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WAKE 8 56 #define an_x4_sw_management_cl36RxEEEStates_l_RX_QUIET 4 57 #define an_x4_sw_management_cl36RxEEEStates_l_RX_SLEEP 2 58 #define an_x4_sw_management_cl36RxEEEStates_l_RX_ACTIVE 1 59 60 /**************************************************************************** 61 * Enums: an_x4_sw_management_cl36RxEEEStates_c 62 */ 63 #define an_x4_sw_management_cl36RxEEEStates_c_RX_LINK_FAIL 5 64 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WTF 4 65 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WAKE 3 66 #define an_x4_sw_management_cl36RxEEEStates_c_RX_QUIET 2 67 #define an_x4_sw_management_cl36RxEEEStates_c_RX_SLEEP 1 68 #define an_x4_sw_management_cl36RxEEEStates_c_RX_ACTIVE 0 69 70 /**************************************************************************** 71 * Enums: an_x4_sw_management_cl49RxEEEStates_l 72 */ 73 #define an_x4_sw_management_cl49RxEEEStates_l_RX_LINK_FAIL 32 74 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WTF 16 75 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WAKE 8 76 #define an_x4_sw_management_cl49RxEEEStates_l_RX_QUIET 4 77 #define an_x4_sw_management_cl49RxEEEStates_l_RX_SLEEP 2 78 #define an_x4_sw_management_cl49RxEEEStates_l_RX_ACTIVE 1 79 80 /**************************************************************************** 81 * Enums: an_x4_sw_management_cl49RxEEEStates_c 82 */ 83 #define an_x4_sw_management_cl49RxEEEStates_c_RX_LINK_FAIL 5 84 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WTF 4 85 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WAKE 3 86 #define an_x4_sw_management_cl49RxEEEStates_c_RX_QUIET 2 87 #define an_x4_sw_management_cl49RxEEEStates_c_RX_SLEEP 1 88 #define an_x4_sw_management_cl49RxEEEStates_c_RX_ACTIVE 0 89 90 /**************************************************************************** 91 * Enums: an_x4_sw_management_cl48TxEEEStates_l 92 */ 93 #define an_x4_sw_management_cl48TxEEEStates_l_TX_REFRESH 8 94 #define an_x4_sw_management_cl48TxEEEStates_l_TX_QUIET 4 95 #define an_x4_sw_management_cl48TxEEEStates_l_TX_SLEEP 2 96 #define an_x4_sw_management_cl48TxEEEStates_l_TX_ACTIVE 1 97 98 /**************************************************************************** 99 * Enums: an_x4_sw_management_cl48TxEEEStates_c 100 */ 101 #define an_x4_sw_management_cl48TxEEEStates_c_TX_REFRESH 3 102 #define an_x4_sw_management_cl48TxEEEStates_c_TX_QUIET 2 103 #define an_x4_sw_management_cl48TxEEEStates_c_TX_SLEEP 1 104 #define an_x4_sw_management_cl48TxEEEStates_c_TX_ACTIVE 0 105 106 /**************************************************************************** 107 * Enums: an_x4_sw_management_cl48RxEEEStates_l 108 */ 109 #define an_x4_sw_management_cl48RxEEEStates_l_RX_LINK_FAIL 32 110 #define an_x4_sw_management_cl48RxEEEStates_l_RX_WAKE 16 111 #define an_x4_sw_management_cl48RxEEEStates_l_RX_QUIET 8 112 #define an_x4_sw_management_cl48RxEEEStates_l_RX_DEACT 4 113 #define an_x4_sw_management_cl48RxEEEStates_l_RX_SLEEP 2 114 #define an_x4_sw_management_cl48RxEEEStates_l_RX_ACTIVE 1 115 116 /**************************************************************************** 117 * Enums: an_x4_sw_management_cl48RxEEEStates_c 118 */ 119 #define an_x4_sw_management_cl48RxEEEStates_c_RX_LINK_FAIL 5 120 #define an_x4_sw_management_cl48RxEEEStates_c_RX_WAKE 4 121 #define an_x4_sw_management_cl48RxEEEStates_c_RX_QUIET 3 122 #define an_x4_sw_management_cl48RxEEEStates_c_RX_DEACT 2 123 #define an_x4_sw_management_cl48RxEEEStates_c_RX_SLEEP 1 124 #define an_x4_sw_management_cl48RxEEEStates_c_RX_ACTIVE 0 125 126 /**************************************************************************** 127 * Enums: an_x4_sw_management_IQP_Options 128 */ 129 #define an_x4_sw_management_IQP_Options_i50uA 0 130 #define an_x4_sw_management_IQP_Options_i100uA 1 131 #define an_x4_sw_management_IQP_Options_i150uA 2 132 #define an_x4_sw_management_IQP_Options_i200uA 3 133 #define an_x4_sw_management_IQP_Options_i250uA 4 134 #define an_x4_sw_management_IQP_Options_i300uA 5 135 #define an_x4_sw_management_IQP_Options_i350uA 6 136 #define an_x4_sw_management_IQP_Options_i400uA 7 137 #define an_x4_sw_management_IQP_Options_i450uA 8 138 #define an_x4_sw_management_IQP_Options_i500uA 9 139 #define an_x4_sw_management_IQP_Options_i550uA 10 140 #define an_x4_sw_management_IQP_Options_i600uA 11 141 #define an_x4_sw_management_IQP_Options_i650uA 12 142 #define an_x4_sw_management_IQP_Options_i700uA 13 143 #define an_x4_sw_management_IQP_Options_i750uA 14 144 #define an_x4_sw_management_IQP_Options_i800uA 15 145 146 /**************************************************************************** 147 * Enums: an_x4_sw_management_IDriver_Options 148 */ 149 #define an_x4_sw_management_IDriver_Options_v680mV 0 150 #define an_x4_sw_management_IDriver_Options_v730mV 1 151 #define an_x4_sw_management_IDriver_Options_v780mV 2 152 #define an_x4_sw_management_IDriver_Options_v830mV 3 153 #define an_x4_sw_management_IDriver_Options_v880mV 4 154 #define an_x4_sw_management_IDriver_Options_v930mV 5 155 #define an_x4_sw_management_IDriver_Options_v980mV 6 156 #define an_x4_sw_management_IDriver_Options_v1010mV 7 157 #define an_x4_sw_management_IDriver_Options_v1040mV 8 158 #define an_x4_sw_management_IDriver_Options_v1060mV 9 159 #define an_x4_sw_management_IDriver_Options_v1070mV 10 160 #define an_x4_sw_management_IDriver_Options_v1080mV 11 161 #define an_x4_sw_management_IDriver_Options_v1085mV 12 162 #define an_x4_sw_management_IDriver_Options_v1090mV 13 163 #define an_x4_sw_management_IDriver_Options_v1095mV 14 164 #define an_x4_sw_management_IDriver_Options_v1100mV 15 165 166 /**************************************************************************** 167 * Enums: an_x4_sw_management_operationModes 168 */ 169 #define an_x4_sw_management_operationModes_XGXS 0 170 #define an_x4_sw_management_operationModes_XGXG_nCC 1 171 #define an_x4_sw_management_operationModes_Indlane_OS8 4 172 #define an_x4_sw_management_operationModes_IndLane_OS5 5 173 #define an_x4_sw_management_operationModes_PCI 7 174 #define an_x4_sw_management_operationModes_XGXS_nLQ 8 175 #define an_x4_sw_management_operationModes_XGXS_nLQnCC 9 176 #define an_x4_sw_management_operationModes_PBypass 10 177 #define an_x4_sw_management_operationModes_PBypass_nDSK 11 178 #define an_x4_sw_management_operationModes_ComboCoreMode 12 179 #define an_x4_sw_management_operationModes_Clocks_off 15 180 181 /**************************************************************************** 182 * Enums: an_x4_sw_management_synce_enum 183 */ 184 #define an_x4_sw_management_synce_enum_SYNCE_NO_DIV 0 185 #define an_x4_sw_management_synce_enum_SYNCE_DIV_7 1 186 #define an_x4_sw_management_synce_enum_SYNCE_DIV_11 2 187 188 /**************************************************************************** 189 * Enums: an_x4_sw_management_operationSpeeds 190 */ 191 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1_12p5 65 192 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_12p5 64 193 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_12p5 63 194 #define an_x4_sw_management_operationSpeeds_SPEED_100M_12p5 62 195 #define an_x4_sw_management_operationSpeeds_SPEED_10M_12p5 61 196 #define an_x4_sw_management_operationSpeeds_SPEED_4G_X1_10 60 197 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_X1_10 59 198 #define an_x4_sw_management_operationSpeeds_SPEED_100M_X1_10 58 199 #define an_x4_sw_management_operationSpeeds_SPEED_10M_X1_10 57 200 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_10p3125 56 201 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_10p3125 55 202 #define an_x4_sw_management_operationSpeeds_SPEED_100M_10p3125 54 203 #define an_x4_sw_management_operationSpeeds_SPEED_10M_10p3125 53 204 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X4 50 205 #define an_x4_sw_management_operationSpeeds_SPEED_5G_KR1 49 206 #define an_x4_sw_management_operationSpeeds_SPEED_127G_X12 39 207 #define an_x4_sw_management_operationSpeeds_SPEED_120G_X12 38 208 #define an_x4_sw_management_operationSpeeds_SPEED_107G_X10 37 209 #define an_x4_sw_management_operationSpeeds_SPEED_100G_CR10 36 210 #define an_x4_sw_management_operationSpeeds_SPEED_42G_X4 35 211 #define an_x4_sw_management_operationSpeeds_SPEED_40G_CR4 34 212 #define an_x4_sw_management_operationSpeeds_SPEED_40G_KR4 33 213 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X2 32 214 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CR2 31 215 #define an_x4_sw_management_operationSpeeds_SPEED_20G_KR2 30 216 #define an_x4_sw_management_operationSpeeds_SPEED_10p6_X1 29 217 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KR1 28 218 #define an_x4_sw_management_operationSpeeds_SPEED_40G_X4 27 219 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X2 26 220 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX2 25 221 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_KR4 24 222 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_X4 23 223 #define an_x4_sw_management_operationSpeeds_SPEED_15p75G_X2 22 224 #define an_x4_sw_management_operationSpeeds_SPEED_25p45G_X4 21 225 #define an_x4_sw_management_operationSpeeds_SPEED_12p7G_X2 20 226 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X4 19 227 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X2 18 228 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X4 17 229 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X2 16 230 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX2 15 231 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX4 14 232 #define an_x4_sw_management_operationSpeeds_SPEED_16G_X4 13 233 #define an_x4_sw_management_operationSpeeds_SPEED_15G_X4 12 234 #define an_x4_sw_management_operationSpeeds_SPEED_13G_X4 11 235 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X4 10 236 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KX4 9 237 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX4 8 238 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1 7 239 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1 6 240 #define an_x4_sw_management_operationSpeeds_SPEED_1G_KX1 5 241 #define an_x4_sw_management_operationSpeeds_SPEED_1G_CX1 4 242 #define an_x4_sw_management_operationSpeeds_SPEED_1000M 3 243 #define an_x4_sw_management_operationSpeeds_SPEED_100M 2 244 #define an_x4_sw_management_operationSpeeds_SPEED_10M 1 245 246 /**************************************************************************** 247 * Enums: an_x4_sw_management_actualSpeeds 248 */ 249 #define an_x4_sw_management_actualSpeeds_dr_10M 0 250 #define an_x4_sw_management_actualSpeeds_dr_100M 1 251 #define an_x4_sw_management_actualSpeeds_dr_1G 2 252 #define an_x4_sw_management_actualSpeeds_dr_2p5G 3 253 #define an_x4_sw_management_actualSpeeds_dr_5G_X4 4 254 #define an_x4_sw_management_actualSpeeds_dr_6G_X4 5 255 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG 6 256 #define an_x4_sw_management_actualSpeeds_dr_10G_CX4 7 257 #define an_x4_sw_management_actualSpeeds_dr_12G_HiG 8 258 #define an_x4_sw_management_actualSpeeds_dr_12p5G_X4 9 259 #define an_x4_sw_management_actualSpeeds_dr_13G_X4 10 260 #define an_x4_sw_management_actualSpeeds_dr_15G_X4 11 261 #define an_x4_sw_management_actualSpeeds_dr_16G_X4 12 262 #define an_x4_sw_management_actualSpeeds_dr_1G_KX 13 263 #define an_x4_sw_management_actualSpeeds_dr_10G_KX4 14 264 #define an_x4_sw_management_actualSpeeds_dr_10G_KR 15 265 #define an_x4_sw_management_actualSpeeds_dr_5G 16 266 #define an_x4_sw_management_actualSpeeds_dr_6p4G 17 267 #define an_x4_sw_management_actualSpeeds_dr_20G_X4 18 268 #define an_x4_sw_management_actualSpeeds_dr_21G_X4 19 269 #define an_x4_sw_management_actualSpeeds_dr_25G_X4 20 270 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS 21 271 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS 22 272 #define an_x4_sw_management_actualSpeeds_dr_10p5G_HiG_DXGXS 23 273 #define an_x4_sw_management_actualSpeeds_dr_10p5G_DXGXS 24 274 #define an_x4_sw_management_actualSpeeds_dr_12p773G_HiG_DXGXS 25 275 #define an_x4_sw_management_actualSpeeds_dr_12p773G_DXGXS 26 276 #define an_x4_sw_management_actualSpeeds_dr_10G_XFI 27 277 #define an_x4_sw_management_actualSpeeds_dr_40G 28 278 #define an_x4_sw_management_actualSpeeds_dr_20G_HiG_DXGXS 29 279 #define an_x4_sw_management_actualSpeeds_dr_20G_DXGXS 30 280 #define an_x4_sw_management_actualSpeeds_dr_10G_SFI 31 281 #define an_x4_sw_management_actualSpeeds_dr_31p5G 32 282 #define an_x4_sw_management_actualSpeeds_dr_32p7G 33 283 #define an_x4_sw_management_actualSpeeds_dr_20G_SCR 34 284 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 285 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS_SCR 36 286 #define an_x4_sw_management_actualSpeeds_dr_12G_R2 37 287 #define an_x4_sw_management_actualSpeeds_dr_10G_X2 38 288 #define an_x4_sw_management_actualSpeeds_dr_40G_KR4 39 289 #define an_x4_sw_management_actualSpeeds_dr_40G_CR4 40 290 #define an_x4_sw_management_actualSpeeds_dr_100G_CR10 41 291 #define an_x4_sw_management_actualSpeeds_dr_15p75G_DXGXS 44 292 #define an_x4_sw_management_actualSpeeds_dr_20G_KR2 57 293 #define an_x4_sw_management_actualSpeeds_dr_20G_CR2 58 294 295 /**************************************************************************** 296 * Enums: an_x4_sw_management_actualSpeedsMisc1 297 */ 298 #define an_x4_sw_management_actualSpeedsMisc1_dr_2500BRCM_X1 16 299 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X4 17 300 #define an_x4_sw_management_actualSpeedsMisc1_dr_6000BRCM_X4 18 301 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GHiGig_X4 19 302 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GBASE_CX4 20 303 #define an_x4_sw_management_actualSpeedsMisc1_dr_12GHiGig_X4 21 304 #define an_x4_sw_management_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 305 #define an_x4_sw_management_actualSpeedsMisc1_dr_13GHiGig_X4 23 306 #define an_x4_sw_management_actualSpeedsMisc1_dr_15GHiGig_X4 24 307 #define an_x4_sw_management_actualSpeedsMisc1_dr_16GHiGig_X4 25 308 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X1 26 309 #define an_x4_sw_management_actualSpeedsMisc1_dr_6363BRCM_X1 27 310 #define an_x4_sw_management_actualSpeedsMisc1_dr_20GHiGig_X4 28 311 #define an_x4_sw_management_actualSpeedsMisc1_dr_21GHiGig_X4 29 312 #define an_x4_sw_management_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 313 #define an_x4_sw_management_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 314 315 /**************************************************************************** 316 * Enums: an_x4_sw_management_IndLaneModes 317 */ 318 #define an_x4_sw_management_IndLaneModes_SWSDR_div2 0 319 #define an_x4_sw_management_IndLaneModes_SWSDR_div1 1 320 #define an_x4_sw_management_IndLaneModes_DWSDR_div2 2 321 #define an_x4_sw_management_IndLaneModes_DWSDR_div1 3 322 323 /**************************************************************************** 324 * Enums: an_x4_sw_management_prbsSelect 325 */ 326 #define an_x4_sw_management_prbsSelect_prbs7 0 327 #define an_x4_sw_management_prbsSelect_prbs15 1 328 #define an_x4_sw_management_prbsSelect_prbs23 2 329 #define an_x4_sw_management_prbsSelect_prbs31 3 330 331 /**************************************************************************** 332 * Enums: an_x4_sw_management_vcoDivider 333 */ 334 #define an_x4_sw_management_vcoDivider_div32 0 335 #define an_x4_sw_management_vcoDivider_div36 1 336 #define an_x4_sw_management_vcoDivider_div40 2 337 #define an_x4_sw_management_vcoDivider_div42 3 338 #define an_x4_sw_management_vcoDivider_div48 4 339 #define an_x4_sw_management_vcoDivider_div50 5 340 #define an_x4_sw_management_vcoDivider_div52 6 341 #define an_x4_sw_management_vcoDivider_div54 7 342 #define an_x4_sw_management_vcoDivider_div60 8 343 #define an_x4_sw_management_vcoDivider_div64 9 344 #define an_x4_sw_management_vcoDivider_div66 10 345 #define an_x4_sw_management_vcoDivider_div68 11 346 #define an_x4_sw_management_vcoDivider_div70 12 347 #define an_x4_sw_management_vcoDivider_div80 13 348 #define an_x4_sw_management_vcoDivider_div92 14 349 #define an_x4_sw_management_vcoDivider_div100 15 350 351 /**************************************************************************** 352 * Enums: an_x4_sw_management_refClkSelect 353 */ 354 #define an_x4_sw_management_refClkSelect_clk_25MHz 0 355 #define an_x4_sw_management_refClkSelect_clk_100MHz 1 356 #define an_x4_sw_management_refClkSelect_clk_125MHz 2 357 #define an_x4_sw_management_refClkSelect_clk_156p25MHz 3 358 #define an_x4_sw_management_refClkSelect_clk_187p5MHz 4 359 #define an_x4_sw_management_refClkSelect_clk_161p25Mhz 5 360 #define an_x4_sw_management_refClkSelect_clk_50Mhz 6 361 #define an_x4_sw_management_refClkSelect_clk_106p25Mhz 7 362 363 /**************************************************************************** 364 * Enums: an_x4_sw_management_aerMMDdevTypeSelect 365 */ 366 #define an_x4_sw_management_aerMMDdevTypeSelect_combo_core 0 367 #define an_x4_sw_management_aerMMDdevTypeSelect_PMA_PMD 1 368 #define an_x4_sw_management_aerMMDdevTypeSelect_PCS 3 369 #define an_x4_sw_management_aerMMDdevTypeSelect_PHY 4 370 #define an_x4_sw_management_aerMMDdevTypeSelect_DTE 5 371 #define an_x4_sw_management_aerMMDdevTypeSelect_CL73_AN 7 372 373 /**************************************************************************** 374 * Enums: an_x4_sw_management_aerMMDportSelect 375 */ 376 #define an_x4_sw_management_aerMMDportSelect_ln0 0 377 #define an_x4_sw_management_aerMMDportSelect_ln1 1 378 #define an_x4_sw_management_aerMMDportSelect_ln2 2 379 #define an_x4_sw_management_aerMMDportSelect_ln3 3 380 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1_2_3 511 381 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1 512 382 #define an_x4_sw_management_aerMMDportSelect_BCST_ln2_3 513 383 384 /**************************************************************************** 385 * Enums: an_x4_sw_management_firmwareModeSelect 386 */ 387 #define an_x4_sw_management_firmwareModeSelect_DEFAULT 0 388 #define an_x4_sw_management_firmwareModeSelect_SFP_OPT_LR 1 389 #define an_x4_sw_management_firmwareModeSelect_SFP_DAC 2 390 #define an_x4_sw_management_firmwareModeSelect_XLAUI 3 391 #define an_x4_sw_management_firmwareModeSelect_LONG_CH_6G 4 392 393 /**************************************************************************** 394 * Enums: an_x4_sw_management_tempIdxSelect 395 */ 396 #define an_x4_sw_management_tempIdxSelect_LTE__22p9C 15 397 #define an_x4_sw_management_tempIdxSelect_LTE__12p6C 14 398 #define an_x4_sw_management_tempIdxSelect_LTE__3p0C 13 399 #define an_x4_sw_management_tempIdxSelect_LTE_6p7C 12 400 #define an_x4_sw_management_tempIdxSelect_LTE_16p4C 11 401 #define an_x4_sw_management_tempIdxSelect_LTE_26p6C 10 402 #define an_x4_sw_management_tempIdxSelect_LTE_36p3C 9 403 #define an_x4_sw_management_tempIdxSelect_LTE_46p0C 8 404 #define an_x4_sw_management_tempIdxSelect_LTE_56p2C 7 405 #define an_x4_sw_management_tempIdxSelect_LTE_65p9C 6 406 #define an_x4_sw_management_tempIdxSelect_LTE_75p6C 5 407 #define an_x4_sw_management_tempIdxSelect_LTE_85p3C 4 408 #define an_x4_sw_management_tempIdxSelect_LTE_95p5C 3 409 #define an_x4_sw_management_tempIdxSelect_LTE_105p2C 2 410 #define an_x4_sw_management_tempIdxSelect_LTE_114p9C 1 411 #define an_x4_sw_management_tempIdxSelect_LTE_125p1C 0 412 413 /**************************************************************************** 414 * Enums: an_x4_sw_management_tla_ln_seq_status 415 */ 416 #define an_x4_sw_management_tla_ln_seq_status_INIT 1 417 #define an_x4_sw_management_tla_ln_seq_status_SET_AN_SPEED 2 418 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_SPEED 4 419 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_DONE 8 420 #define an_x4_sw_management_tla_ln_seq_status_SET_RS_SPEED 16 421 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_CL72EN 32 422 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_SPEED 64 423 #define an_x4_sw_management_tla_ln_seq_status_AN_IGNORE_LINK 128 424 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD_CHECK 256 425 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD 512 426 #define an_x4_sw_management_tla_ln_seq_status_AN_FAIL 1024 427 #define an_x4_sw_management_tla_ln_seq_status_AN_DEAD 2048 428 #define an_x4_sw_management_tla_ln_seq_status_SET_PD_SPEED 4096 429 #define an_x4_sw_management_tla_ln_seq_status_WAIT_PD_SPEED 8192 430 #define an_x4_sw_management_tla_ln_seq_status_PD_IGNORE_LINK 16384 431 #define an_x4_sw_management_tla_ln_seq_status_PD_GOOD_CHECK 32768 432 433 /**************************************************************************** 434 * Enums: an_x4_sw_management_tla_ln_seq_status1 435 */ 436 #define an_x4_sw_management_tla_ln_seq_status1_SW_SPEED_CHANGE 64 437 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_SW 32 438 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_DISABLE 16 439 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_LINK 8 440 #define an_x4_sw_management_tla_ln_seq_status1_PD_START_CL37_AN 4 441 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_CL37_AN_DONE 2 442 #define an_x4_sw_management_tla_ln_seq_status1_PD_DONE_CL37 1 443 444 /**************************************************************************** 445 * Enums: digital_cl36TxEEEStates_l 446 */ 447 #define digital_cl36TxEEEStates_l_TX_REFRESH 8 448 #define digital_cl36TxEEEStates_l_TX_QUIET 4 449 #define digital_cl36TxEEEStates_l_TX_SLEEP 2 450 #define digital_cl36TxEEEStates_l_TX_ACTIVE 1 451 452 /**************************************************************************** 453 * Enums: digital_cl36TxEEEStates_c 454 */ 455 #define digital_cl36TxEEEStates_c_TX_REFRESH 3 456 #define digital_cl36TxEEEStates_c_TX_QUIET 2 457 #define digital_cl36TxEEEStates_c_TX_SLEEP 1 458 #define digital_cl36TxEEEStates_c_TX_ACTIVE 0 459 460 /**************************************************************************** 461 * Enums: digital_cl49TxEEEStates_l 462 */ 463 #define digital_cl49TxEEEStates_l_SCR_RESET_2 64 464 #define digital_cl49TxEEEStates_l_SCR_RESET_1 32 465 #define digital_cl49TxEEEStates_l_TX_WAKE 16 466 #define digital_cl49TxEEEStates_l_TX_REFRESH 8 467 #define digital_cl49TxEEEStates_l_TX_QUIET 4 468 #define digital_cl49TxEEEStates_l_TX_SLEEP 2 469 #define digital_cl49TxEEEStates_l_TX_ACTIVE 1 470 471 /**************************************************************************** 472 * Enums: digital_cl49TxEEEStates_c 473 */ 474 #define digital_cl49TxEEEStates_c_SCR_RESET_2 6 475 #define digital_cl49TxEEEStates_c_SCR_RESET_1 5 476 #define digital_cl49TxEEEStates_c_TX_WAKE 4 477 #define digital_cl49TxEEEStates_c_TX_REFRESH 3 478 #define digital_cl49TxEEEStates_c_TX_QUIET 2 479 #define digital_cl49TxEEEStates_c_TX_SLEEP 1 480 #define digital_cl49TxEEEStates_c_TX_ACTIVE 0 481 482 /**************************************************************************** 483 * Enums: digital_cl36RxEEEStates_l 484 */ 485 #define digital_cl36RxEEEStates_l_RX_LINK_FAIL 32 486 #define digital_cl36RxEEEStates_l_RX_WTF 16 487 #define digital_cl36RxEEEStates_l_RX_WAKE 8 488 #define digital_cl36RxEEEStates_l_RX_QUIET 4 489 #define digital_cl36RxEEEStates_l_RX_SLEEP 2 490 #define digital_cl36RxEEEStates_l_RX_ACTIVE 1 491 492 /**************************************************************************** 493 * Enums: digital_cl36RxEEEStates_c 494 */ 495 #define digital_cl36RxEEEStates_c_RX_LINK_FAIL 5 496 #define digital_cl36RxEEEStates_c_RX_WTF 4 497 #define digital_cl36RxEEEStates_c_RX_WAKE 3 498 #define digital_cl36RxEEEStates_c_RX_QUIET 2 499 #define digital_cl36RxEEEStates_c_RX_SLEEP 1 500 #define digital_cl36RxEEEStates_c_RX_ACTIVE 0 501 502 /**************************************************************************** 503 * Enums: digital_cl49RxEEEStates_l 504 */ 505 #define digital_cl49RxEEEStates_l_RX_LINK_FAIL 32 506 #define digital_cl49RxEEEStates_l_RX_WTF 16 507 #define digital_cl49RxEEEStates_l_RX_WAKE 8 508 #define digital_cl49RxEEEStates_l_RX_QUIET 4 509 #define digital_cl49RxEEEStates_l_RX_SLEEP 2 510 #define digital_cl49RxEEEStates_l_RX_ACTIVE 1 511 512 /**************************************************************************** 513 * Enums: digital_cl49RxEEEStates_c 514 */ 515 #define digital_cl49RxEEEStates_c_RX_LINK_FAIL 5 516 #define digital_cl49RxEEEStates_c_RX_WTF 4 517 #define digital_cl49RxEEEStates_c_RX_WAKE 3 518 #define digital_cl49RxEEEStates_c_RX_QUIET 2 519 #define digital_cl49RxEEEStates_c_RX_SLEEP 1 520 #define digital_cl49RxEEEStates_c_RX_ACTIVE 0 521 522 /**************************************************************************** 523 * Enums: digital_cl48TxEEEStates_l 524 */ 525 #define digital_cl48TxEEEStates_l_TX_REFRESH 8 526 #define digital_cl48TxEEEStates_l_TX_QUIET 4 527 #define digital_cl48TxEEEStates_l_TX_SLEEP 2 528 #define digital_cl48TxEEEStates_l_TX_ACTIVE 1 529 530 /**************************************************************************** 531 * Enums: digital_cl48TxEEEStates_c 532 */ 533 #define digital_cl48TxEEEStates_c_TX_REFRESH 3 534 #define digital_cl48TxEEEStates_c_TX_QUIET 2 535 #define digital_cl48TxEEEStates_c_TX_SLEEP 1 536 #define digital_cl48TxEEEStates_c_TX_ACTIVE 0 537 538 /**************************************************************************** 539 * Enums: digital_cl48RxEEEStates_l 540 */ 541 #define digital_cl48RxEEEStates_l_RX_LINK_FAIL 32 542 #define digital_cl48RxEEEStates_l_RX_WAKE 16 543 #define digital_cl48RxEEEStates_l_RX_QUIET 8 544 #define digital_cl48RxEEEStates_l_RX_DEACT 4 545 #define digital_cl48RxEEEStates_l_RX_SLEEP 2 546 #define digital_cl48RxEEEStates_l_RX_ACTIVE 1 547 548 /**************************************************************************** 549 * Enums: digital_cl48RxEEEStates_c 550 */ 551 #define digital_cl48RxEEEStates_c_RX_LINK_FAIL 5 552 #define digital_cl48RxEEEStates_c_RX_WAKE 4 553 #define digital_cl48RxEEEStates_c_RX_QUIET 3 554 #define digital_cl48RxEEEStates_c_RX_DEACT 2 555 #define digital_cl48RxEEEStates_c_RX_SLEEP 1 556 #define digital_cl48RxEEEStates_c_RX_ACTIVE 0 557 558 /**************************************************************************** 559 * Enums: digital_IQP_Options 560 */ 561 #define digital_IQP_Options_i50uA 0 562 #define digital_IQP_Options_i100uA 1 563 #define digital_IQP_Options_i150uA 2 564 #define digital_IQP_Options_i200uA 3 565 #define digital_IQP_Options_i250uA 4 566 #define digital_IQP_Options_i300uA 5 567 #define digital_IQP_Options_i350uA 6 568 #define digital_IQP_Options_i400uA 7 569 #define digital_IQP_Options_i450uA 8 570 #define digital_IQP_Options_i500uA 9 571 #define digital_IQP_Options_i550uA 10 572 #define digital_IQP_Options_i600uA 11 573 #define digital_IQP_Options_i650uA 12 574 #define digital_IQP_Options_i700uA 13 575 #define digital_IQP_Options_i750uA 14 576 #define digital_IQP_Options_i800uA 15 577 578 /**************************************************************************** 579 * Enums: digital_IDriver_Options 580 */ 581 #define digital_IDriver_Options_v680mV 0 582 #define digital_IDriver_Options_v730mV 1 583 #define digital_IDriver_Options_v780mV 2 584 #define digital_IDriver_Options_v830mV 3 585 #define digital_IDriver_Options_v880mV 4 586 #define digital_IDriver_Options_v930mV 5 587 #define digital_IDriver_Options_v980mV 6 588 #define digital_IDriver_Options_v1010mV 7 589 #define digital_IDriver_Options_v1040mV 8 590 #define digital_IDriver_Options_v1060mV 9 591 #define digital_IDriver_Options_v1070mV 10 592 #define digital_IDriver_Options_v1080mV 11 593 #define digital_IDriver_Options_v1085mV 12 594 #define digital_IDriver_Options_v1090mV 13 595 #define digital_IDriver_Options_v1095mV 14 596 #define digital_IDriver_Options_v1100mV 15 597 598 /**************************************************************************** 599 * Enums: digital_operationModes 600 */ 601 #define digital_operationModes_XGXS 0 602 #define digital_operationModes_XGXG_nCC 1 603 #define digital_operationModes_Indlane_OS8 4 604 #define digital_operationModes_IndLane_OS5 5 605 #define digital_operationModes_PCI 7 606 #define digital_operationModes_XGXS_nLQ 8 607 #define digital_operationModes_XGXS_nLQnCC 9 608 #define digital_operationModes_PBypass 10 609 #define digital_operationModes_PBypass_nDSK 11 610 #define digital_operationModes_ComboCoreMode 12 611 #define digital_operationModes_Clocks_off 15 612 613 /**************************************************************************** 614 * Enums: digital_synce_enum 615 */ 616 #define digital_synce_enum_SYNCE_NO_DIV 0 617 #define digital_synce_enum_SYNCE_DIV_7 1 618 #define digital_synce_enum_SYNCE_DIV_11 2 619 620 /**************************************************************************** 621 * Enums: digital_operationSpeeds 622 */ 623 #define digital_operationSpeeds_SPEED_10p3125G_X1 72 624 #define digital_operationSpeeds_SPEED_5G_X1_12p5 65 625 #define digital_operationSpeeds_SPEED_2p5G_X1_12p5 64 626 #define digital_operationSpeeds_SPEED_1000M_12p5 63 627 #define digital_operationSpeeds_SPEED_100M_12p5 62 628 #define digital_operationSpeeds_SPEED_10M_12p5 61 629 #define digital_operationSpeeds_SPEED_4G_X1_10 60 630 #define digital_operationSpeeds_SPEED_1000M_X1_10 59 631 #define digital_operationSpeeds_SPEED_100M_X1_10 58 632 #define digital_operationSpeeds_SPEED_10M_X1_10 57 633 #define digital_operationSpeeds_SPEED_2p5G_X1_10p3125 56 634 #define digital_operationSpeeds_SPEED_1000M_10p3125 55 635 #define digital_operationSpeeds_SPEED_100M_10p3125 54 636 #define digital_operationSpeeds_SPEED_10M_10p3125 53 637 #define digital_operationSpeeds_SPEED_10p5G_X4 50 638 #define digital_operationSpeeds_SPEED_5G_KR1 49 639 #define digital_operationSpeeds_SPEED_127G_X12 39 640 #define digital_operationSpeeds_SPEED_120G_X12 38 641 #define digital_operationSpeeds_SPEED_107G_X10 37 642 #define digital_operationSpeeds_SPEED_100G_CR10 36 643 #define digital_operationSpeeds_SPEED_42G_X4 35 644 #define digital_operationSpeeds_SPEED_40G_CR4 34 645 #define digital_operationSpeeds_SPEED_40G_KR4 33 646 #define digital_operationSpeeds_SPEED_21G_X2 32 647 #define digital_operationSpeeds_SPEED_20G_CR2 31 648 #define digital_operationSpeeds_SPEED_20G_KR2 30 649 #define digital_operationSpeeds_SPEED_10p6_X1 29 650 #define digital_operationSpeeds_SPEED_10G_KR1 28 651 #define digital_operationSpeeds_SPEED_40G_X4 27 652 #define digital_operationSpeeds_SPEED_20G_X2 26 653 #define digital_operationSpeeds_SPEED_20G_CX2 25 654 #define digital_operationSpeeds_SPEED_31p5G_KR4 24 655 #define digital_operationSpeeds_SPEED_31p5G_X4 23 656 #define digital_operationSpeeds_SPEED_15p75G_X2 22 657 #define digital_operationSpeeds_SPEED_25p45G_X4 21 658 #define digital_operationSpeeds_SPEED_12p7G_X2 20 659 #define digital_operationSpeeds_SPEED_21G_X4 19 660 #define digital_operationSpeeds_SPEED_10p5G_X2 18 661 #define digital_operationSpeeds_SPEED_20G_X4 17 662 #define digital_operationSpeeds_SPEED_10G_X2 16 663 #define digital_operationSpeeds_SPEED_10G_CX2 15 664 #define digital_operationSpeeds_SPEED_20G_CX4 14 665 #define digital_operationSpeeds_SPEED_16G_X4 13 666 #define digital_operationSpeeds_SPEED_15G_X4 12 667 #define digital_operationSpeeds_SPEED_13G_X4 11 668 #define digital_operationSpeeds_SPEED_10G_X4 10 669 #define digital_operationSpeeds_SPEED_10G_KX4 9 670 #define digital_operationSpeeds_SPEED_10G_CX4 8 671 #define digital_operationSpeeds_SPEED_5G_X1 7 672 #define digital_operationSpeeds_SPEED_2p5G_X1 6 673 #define digital_operationSpeeds_SPEED_1G_KX1 5 674 #define digital_operationSpeeds_SPEED_1G_CX1 4 675 #define digital_operationSpeeds_SPEED_1000M 3 676 #define digital_operationSpeeds_SPEED_100M 2 677 #define digital_operationSpeeds_SPEED_10M 1 678 679 /**************************************************************************** 680 * Enums: digital_actualSpeeds 681 */ 682 #define digital_actualSpeeds_dr_10M 0 683 #define digital_actualSpeeds_dr_100M 1 684 #define digital_actualSpeeds_dr_1G 2 685 #define digital_actualSpeeds_dr_2p5G 3 686 #define digital_actualSpeeds_dr_5G_X4 4 687 #define digital_actualSpeeds_dr_6G_X4 5 688 #define digital_actualSpeeds_dr_10G_HiG 6 689 #define digital_actualSpeeds_dr_10G_CX4 7 690 #define digital_actualSpeeds_dr_12G_HiG 8 691 #define digital_actualSpeeds_dr_12p5G_X4 9 692 #define digital_actualSpeeds_dr_13G_X4 10 693 #define digital_actualSpeeds_dr_15G_X4 11 694 #define digital_actualSpeeds_dr_16G_X4 12 695 #define digital_actualSpeeds_dr_1G_KX 13 696 #define digital_actualSpeeds_dr_10G_KX4 14 697 #define digital_actualSpeeds_dr_10G_KR 15 698 #define digital_actualSpeeds_dr_5G 16 699 #define digital_actualSpeeds_dr_6p4G 17 700 #define digital_actualSpeeds_dr_20G_X4 18 701 #define digital_actualSpeeds_dr_21G_X4 19 702 #define digital_actualSpeeds_dr_25G_X4 20 703 #define digital_actualSpeeds_dr_10G_HiG_DXGXS 21 704 #define digital_actualSpeeds_dr_10G_DXGXS 22 705 #define digital_actualSpeeds_dr_10p5G_HiG_DXGXS 23 706 #define digital_actualSpeeds_dr_10p5G_DXGXS 24 707 #define digital_actualSpeeds_dr_12p773G_HiG_DXGXS 25 708 #define digital_actualSpeeds_dr_12p773G_DXGXS 26 709 #define digital_actualSpeeds_dr_10G_XFI 27 710 #define digital_actualSpeeds_dr_40G 28 711 #define digital_actualSpeeds_dr_20G_HiG_DXGXS 29 712 #define digital_actualSpeeds_dr_20G_DXGXS 30 713 #define digital_actualSpeeds_dr_10G_SFI 31 714 #define digital_actualSpeeds_dr_31p5G 32 715 #define digital_actualSpeeds_dr_32p7G 33 716 #define digital_actualSpeeds_dr_20G_SCR 34 717 #define digital_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 718 #define digital_actualSpeeds_dr_10G_DXGXS_SCR 36 719 #define digital_actualSpeeds_dr_12G_R2 37 720 #define digital_actualSpeeds_dr_10G_X2 38 721 #define digital_actualSpeeds_dr_40G_KR4 39 722 #define digital_actualSpeeds_dr_40G_CR4 40 723 #define digital_actualSpeeds_dr_100G_CR10 41 724 #define digital_actualSpeeds_dr_15p75G_DXGXS 44 725 #define digital_actualSpeeds_dr_20G_KR2 57 726 #define digital_actualSpeeds_dr_20G_CR2 58 727 728 /**************************************************************************** 729 * Enums: digital_actualSpeedsMisc1 730 */ 731 #define digital_actualSpeedsMisc1_dr_2500BRCM_X1 16 732 #define digital_actualSpeedsMisc1_dr_5000BRCM_X4 17 733 #define digital_actualSpeedsMisc1_dr_6000BRCM_X4 18 734 #define digital_actualSpeedsMisc1_dr_10GHiGig_X4 19 735 #define digital_actualSpeedsMisc1_dr_10GBASE_CX4 20 736 #define digital_actualSpeedsMisc1_dr_12GHiGig_X4 21 737 #define digital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 738 #define digital_actualSpeedsMisc1_dr_13GHiGig_X4 23 739 #define digital_actualSpeedsMisc1_dr_15GHiGig_X4 24 740 #define digital_actualSpeedsMisc1_dr_16GHiGig_X4 25 741 #define digital_actualSpeedsMisc1_dr_5000BRCM_X1 26 742 #define digital_actualSpeedsMisc1_dr_6363BRCM_X1 27 743 #define digital_actualSpeedsMisc1_dr_20GHiGig_X4 28 744 #define digital_actualSpeedsMisc1_dr_21GHiGig_X4 29 745 #define digital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 746 #define digital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 747 748 /**************************************************************************** 749 * Enums: digital_IndLaneModes 750 */ 751 #define digital_IndLaneModes_SWSDR_div2 0 752 #define digital_IndLaneModes_SWSDR_div1 1 753 #define digital_IndLaneModes_DWSDR_div2 2 754 #define digital_IndLaneModes_DWSDR_div1 3 755 756 /**************************************************************************** 757 * Enums: digital_prbsSelect 758 */ 759 #define digital_prbsSelect_prbs7 0 760 #define digital_prbsSelect_prbs15 1 761 #define digital_prbsSelect_prbs23 2 762 #define digital_prbsSelect_prbs31 3 763 764 /**************************************************************************** 765 * Enums: digital_vcoDivider 766 */ 767 #define digital_vcoDivider_div32 0 768 #define digital_vcoDivider_div36 1 769 #define digital_vcoDivider_div40 2 770 #define digital_vcoDivider_div42 3 771 #define digital_vcoDivider_div48 4 772 #define digital_vcoDivider_div50 5 773 #define digital_vcoDivider_div52 6 774 #define digital_vcoDivider_div54 7 775 #define digital_vcoDivider_div60 8 776 #define digital_vcoDivider_div64 9 777 #define digital_vcoDivider_div66 10 778 #define digital_vcoDivider_div68 11 779 #define digital_vcoDivider_div70 12 780 #define digital_vcoDivider_div80 13 781 #define digital_vcoDivider_div92 14 782 #define digital_vcoDivider_div100 15 783 784 /**************************************************************************** 785 * Enums: digital_refClkSelect 786 */ 787 #define digital_refClkSelect_clk_25MHz 0 788 #define digital_refClkSelect_clk_100MHz 1 789 #define digital_refClkSelect_clk_125MHz 2 790 #define digital_refClkSelect_clk_156p25MHz 3 791 #define digital_refClkSelect_clk_187p5MHz 4 792 #define digital_refClkSelect_clk_161p25Mhz 5 793 #define digital_refClkSelect_clk_50Mhz 6 794 #define digital_refClkSelect_clk_106p25Mhz 7 795 796 /**************************************************************************** 797 * Enums: digital_aerMMDdevTypeSelect 798 */ 799 #define digital_aerMMDdevTypeSelect_combo_core 0 800 #define digital_aerMMDdevTypeSelect_PMA_PMD 1 801 #define digital_aerMMDdevTypeSelect_PCS 3 802 #define digital_aerMMDdevTypeSelect_PHY 4 803 #define digital_aerMMDdevTypeSelect_DTE 5 804 #define digital_aerMMDdevTypeSelect_CL73_AN 7 805 806 /**************************************************************************** 807 * Enums: digital_aerMMDportSelect 808 */ 809 #define digital_aerMMDportSelect_ln0 0 810 #define digital_aerMMDportSelect_ln1 1 811 #define digital_aerMMDportSelect_ln2 2 812 #define digital_aerMMDportSelect_ln3 3 813 #define digital_aerMMDportSelect_BCST_ln0_1_2_3 511 814 #define digital_aerMMDportSelect_BCST_ln0_1 512 815 #define digital_aerMMDportSelect_BCST_ln2_3 513 816 817 /**************************************************************************** 818 * Enums: digital_firmwareModeSelect 819 */ 820 #define digital_firmwareModeSelect_DEFAULT 0 821 #define digital_firmwareModeSelect_SFP_OPT_LR 1 822 #define digital_firmwareModeSelect_SFP_DAC 2 823 #define digital_firmwareModeSelect_XLAUI 3 824 #define digital_firmwareModeSelect_LONG_CH_6G 4 825 826 /**************************************************************************** 827 * Enums: digital_tempIdxSelect 828 */ 829 #define digital_tempIdxSelect_LTE__22p9C 15 830 #define digital_tempIdxSelect_LTE__12p6C 14 831 #define digital_tempIdxSelect_LTE__3p0C 13 832 #define digital_tempIdxSelect_LTE_6p7C 12 833 #define digital_tempIdxSelect_LTE_16p4C 11 834 #define digital_tempIdxSelect_LTE_26p6C 10 835 #define digital_tempIdxSelect_LTE_36p3C 9 836 #define digital_tempIdxSelect_LTE_46p0C 8 837 #define digital_tempIdxSelect_LTE_56p2C 7 838 #define digital_tempIdxSelect_LTE_65p9C 6 839 #define digital_tempIdxSelect_LTE_75p6C 5 840 #define digital_tempIdxSelect_LTE_85p3C 4 841 #define digital_tempIdxSelect_LTE_95p5C 3 842 #define digital_tempIdxSelect_LTE_105p2C 2 843 #define digital_tempIdxSelect_LTE_114p9C 1 844 #define digital_tempIdxSelect_LTE_125p1C 0 845 846 /**************************************************************************** 847 * Enums: generic_cl36TxEEEStates_l 848 */ 849 #define generic_cl36TxEEEStates_l_TX_REFRESH 8 850 #define generic_cl36TxEEEStates_l_TX_QUIET 4 851 #define generic_cl36TxEEEStates_l_TX_SLEEP 2 852 #define generic_cl36TxEEEStates_l_TX_ACTIVE 1 853 854 /**************************************************************************** 855 * Enums: generic_cl36TxEEEStates_c 856 */ 857 #define generic_cl36TxEEEStates_c_TX_REFRESH 3 858 #define generic_cl36TxEEEStates_c_TX_QUIET 2 859 #define generic_cl36TxEEEStates_c_TX_SLEEP 1 860 #define generic_cl36TxEEEStates_c_TX_ACTIVE 0 861 862 /**************************************************************************** 863 * Enums: generic_cl49TxEEEStates_l 864 */ 865 #define generic_cl49TxEEEStates_l_SCR_RESET_2 64 866 #define generic_cl49TxEEEStates_l_SCR_RESET_1 32 867 #define generic_cl49TxEEEStates_l_TX_WAKE 16 868 #define generic_cl49TxEEEStates_l_TX_REFRESH 8 869 #define generic_cl49TxEEEStates_l_TX_QUIET 4 870 #define generic_cl49TxEEEStates_l_TX_SLEEP 2 871 #define generic_cl49TxEEEStates_l_TX_ACTIVE 1 872 873 /**************************************************************************** 874 * Enums: generic_cl49TxEEEStates_c 875 */ 876 #define generic_cl49TxEEEStates_c_SCR_RESET_2 6 877 #define generic_cl49TxEEEStates_c_SCR_RESET_1 5 878 #define generic_cl49TxEEEStates_c_TX_WAKE 4 879 #define generic_cl49TxEEEStates_c_TX_REFRESH 3 880 #define generic_cl49TxEEEStates_c_TX_QUIET 2 881 #define generic_cl49TxEEEStates_c_TX_SLEEP 1 882 #define generic_cl49TxEEEStates_c_TX_ACTIVE 0 883 884 /**************************************************************************** 885 * Enums: generic_cl36RxEEEStates_l 886 */ 887 #define generic_cl36RxEEEStates_l_RX_LINK_FAIL 32 888 #define generic_cl36RxEEEStates_l_RX_WTF 16 889 #define generic_cl36RxEEEStates_l_RX_WAKE 8 890 #define generic_cl36RxEEEStates_l_RX_QUIET 4 891 #define generic_cl36RxEEEStates_l_RX_SLEEP 2 892 #define generic_cl36RxEEEStates_l_RX_ACTIVE 1 893 894 /**************************************************************************** 895 * Enums: generic_cl36RxEEEStates_c 896 */ 897 #define generic_cl36RxEEEStates_c_RX_LINK_FAIL 5 898 #define generic_cl36RxEEEStates_c_RX_WTF 4 899 #define generic_cl36RxEEEStates_c_RX_WAKE 3 900 #define generic_cl36RxEEEStates_c_RX_QUIET 2 901 #define generic_cl36RxEEEStates_c_RX_SLEEP 1 902 #define generic_cl36RxEEEStates_c_RX_ACTIVE 0 903 904 /**************************************************************************** 905 * Enums: generic_cl49RxEEEStates_l 906 */ 907 #define generic_cl49RxEEEStates_l_RX_LINK_FAIL 32 908 #define generic_cl49RxEEEStates_l_RX_WTF 16 909 #define generic_cl49RxEEEStates_l_RX_WAKE 8 910 #define generic_cl49RxEEEStates_l_RX_QUIET 4 911 #define generic_cl49RxEEEStates_l_RX_SLEEP 2 912 #define generic_cl49RxEEEStates_l_RX_ACTIVE 1 913 914 /**************************************************************************** 915 * Enums: generic_cl49RxEEEStates_c 916 */ 917 #define generic_cl49RxEEEStates_c_RX_LINK_FAIL 5 918 #define generic_cl49RxEEEStates_c_RX_WTF 4 919 #define generic_cl49RxEEEStates_c_RX_WAKE 3 920 #define generic_cl49RxEEEStates_c_RX_QUIET 2 921 #define generic_cl49RxEEEStates_c_RX_SLEEP 1 922 #define generic_cl49RxEEEStates_c_RX_ACTIVE 0 923 924 /**************************************************************************** 925 * Enums: generic_cl48TxEEEStates_l 926 */ 927 #define generic_cl48TxEEEStates_l_TX_REFRESH 8 928 #define generic_cl48TxEEEStates_l_TX_QUIET 4 929 #define generic_cl48TxEEEStates_l_TX_SLEEP 2 930 #define generic_cl48TxEEEStates_l_TX_ACTIVE 1 931 932 /**************************************************************************** 933 * Enums: generic_cl48TxEEEStates_c 934 */ 935 #define generic_cl48TxEEEStates_c_TX_REFRESH 3 936 #define generic_cl48TxEEEStates_c_TX_QUIET 2 937 #define generic_cl48TxEEEStates_c_TX_SLEEP 1 938 #define generic_cl48TxEEEStates_c_TX_ACTIVE 0 939 940 /**************************************************************************** 941 * Enums: generic_cl48RxEEEStates_l 942 */ 943 #define generic_cl48RxEEEStates_l_RX_LINK_FAIL 32 944 #define generic_cl48RxEEEStates_l_RX_WAKE 16 945 #define generic_cl48RxEEEStates_l_RX_QUIET 8 946 #define generic_cl48RxEEEStates_l_RX_DEACT 4 947 #define generic_cl48RxEEEStates_l_RX_SLEEP 2 948 #define generic_cl48RxEEEStates_l_RX_ACTIVE 1 949 950 /**************************************************************************** 951 * Enums: generic_cl48RxEEEStates_c 952 */ 953 #define generic_cl48RxEEEStates_c_RX_LINK_FAIL 5 954 #define generic_cl48RxEEEStates_c_RX_WAKE 4 955 #define generic_cl48RxEEEStates_c_RX_QUIET 3 956 #define generic_cl48RxEEEStates_c_RX_DEACT 2 957 #define generic_cl48RxEEEStates_c_RX_SLEEP 1 958 #define generic_cl48RxEEEStates_c_RX_ACTIVE 0 959 960 /**************************************************************************** 961 * Enums: generic_IQP_Options 962 */ 963 #define generic_IQP_Options_i50uA 0 964 #define generic_IQP_Options_i100uA 1 965 #define generic_IQP_Options_i150uA 2 966 #define generic_IQP_Options_i200uA 3 967 #define generic_IQP_Options_i250uA 4 968 #define generic_IQP_Options_i300uA 5 969 #define generic_IQP_Options_i350uA 6 970 #define generic_IQP_Options_i400uA 7 971 #define generic_IQP_Options_i450uA 8 972 #define generic_IQP_Options_i500uA 9 973 #define generic_IQP_Options_i550uA 10 974 #define generic_IQP_Options_i600uA 11 975 #define generic_IQP_Options_i650uA 12 976 #define generic_IQP_Options_i700uA 13 977 #define generic_IQP_Options_i750uA 14 978 #define generic_IQP_Options_i800uA 15 979 980 /**************************************************************************** 981 * Enums: generic_IDriver_Options 982 */ 983 #define generic_IDriver_Options_v680mV 0 984 #define generic_IDriver_Options_v730mV 1 985 #define generic_IDriver_Options_v780mV 2 986 #define generic_IDriver_Options_v830mV 3 987 #define generic_IDriver_Options_v880mV 4 988 #define generic_IDriver_Options_v930mV 5 989 #define generic_IDriver_Options_v980mV 6 990 #define generic_IDriver_Options_v1010mV 7 991 #define generic_IDriver_Options_v1040mV 8 992 #define generic_IDriver_Options_v1060mV 9 993 #define generic_IDriver_Options_v1070mV 10 994 #define generic_IDriver_Options_v1080mV 11 995 #define generic_IDriver_Options_v1085mV 12 996 #define generic_IDriver_Options_v1090mV 13 997 #define generic_IDriver_Options_v1095mV 14 998 #define generic_IDriver_Options_v1100mV 15 999 1000 /**************************************************************************** 1001 * Enums: generic_operationModes 1002 */ 1003 #define generic_operationModes_XGXS 0 1004 #define generic_operationModes_XGXG_nCC 1 1005 #define generic_operationModes_Indlane_OS8 4 1006 #define generic_operationModes_IndLane_OS5 5 1007 #define generic_operationModes_PCI 7 1008 #define generic_operationModes_XGXS_nLQ 8 1009 #define generic_operationModes_XGXS_nLQnCC 9 1010 #define generic_operationModes_PBypass 10 1011 #define generic_operationModes_PBypass_nDSK 11 1012 #define generic_operationModes_ComboCoreMode 12 1013 #define generic_operationModes_Clocks_off 15 1014 1015 /**************************************************************************** 1016 * Enums: generic_synce_enum 1017 */ 1018 #define generic_synce_enum_SYNCE_NO_DIV 0 1019 #define generic_synce_enum_SYNCE_DIV_7 1 1020 #define generic_synce_enum_SYNCE_DIV_11 2 1021 1022 /**************************************************************************** 1023 * Enums: generic_operationSpeeds 1024 */ 1025 #define generic_operationSpeeds_SPEED_5G_X1_12p5 65 1026 #define generic_operationSpeeds_SPEED_2p5G_X1_12p5 64 1027 #define generic_operationSpeeds_SPEED_1000M_12p5 63 1028 #define generic_operationSpeeds_SPEED_100M_12p5 62 1029 #define generic_operationSpeeds_SPEED_10M_12p5 61 1030 #define generic_operationSpeeds_SPEED_4G_X1_10 60 1031 #define generic_operationSpeeds_SPEED_1000M_X1_10 59 1032 #define generic_operationSpeeds_SPEED_100M_X1_10 58 1033 #define generic_operationSpeeds_SPEED_10M_X1_10 57 1034 #define generic_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1035 #define generic_operationSpeeds_SPEED_1000M_10p3125 55 1036 #define generic_operationSpeeds_SPEED_100M_10p3125 54 1037 #define generic_operationSpeeds_SPEED_10M_10p3125 53 1038 #define generic_operationSpeeds_SPEED_10p5G_X4 50 1039 #define generic_operationSpeeds_SPEED_5G_KR1 49 1040 #define generic_operationSpeeds_SPEED_127G_X12 39 1041 #define generic_operationSpeeds_SPEED_120G_X12 38 1042 #define generic_operationSpeeds_SPEED_107G_X10 37 1043 #define generic_operationSpeeds_SPEED_100G_CR10 36 1044 #define generic_operationSpeeds_SPEED_42G_X4 35 1045 #define generic_operationSpeeds_SPEED_40G_CR4 34 1046 #define generic_operationSpeeds_SPEED_40G_KR4 33 1047 #define generic_operationSpeeds_SPEED_21G_X2 32 1048 #define generic_operationSpeeds_SPEED_20G_CR2 31 1049 #define generic_operationSpeeds_SPEED_20G_KR2 30 1050 #define generic_operationSpeeds_SPEED_10p6_X1 29 1051 #define generic_operationSpeeds_SPEED_10G_KR1 28 1052 #define generic_operationSpeeds_SPEED_40G_X4 27 1053 #define generic_operationSpeeds_SPEED_20G_X2 26 1054 #define generic_operationSpeeds_SPEED_20G_CX2 25 1055 #define generic_operationSpeeds_SPEED_31p5G_KR4 24 1056 #define generic_operationSpeeds_SPEED_31p5G_X4 23 1057 #define generic_operationSpeeds_SPEED_15p75G_X2 22 1058 #define generic_operationSpeeds_SPEED_25p45G_X4 21 1059 #define generic_operationSpeeds_SPEED_12p7G_X2 20 1060 #define generic_operationSpeeds_SPEED_21G_X4 19 1061 #define generic_operationSpeeds_SPEED_10p5G_X2 18 1062 #define generic_operationSpeeds_SPEED_20G_X4 17 1063 #define generic_operationSpeeds_SPEED_10G_X2 16 1064 #define generic_operationSpeeds_SPEED_10G_CX2 15 1065 #define generic_operationSpeeds_SPEED_20G_CX4 14 1066 #define generic_operationSpeeds_SPEED_16G_X4 13 1067 #define generic_operationSpeeds_SPEED_15G_X4 12 1068 #define generic_operationSpeeds_SPEED_13G_X4 11 1069 #define generic_operationSpeeds_SPEED_10G_X4 10 1070 #define generic_operationSpeeds_SPEED_10G_KX4 9 1071 #define generic_operationSpeeds_SPEED_10G_CX4 8 1072 #define generic_operationSpeeds_SPEED_5G_X1 7 1073 #define generic_operationSpeeds_SPEED_2p5G_X1 6 1074 #define generic_operationSpeeds_SPEED_1G_KX1 5 1075 #define generic_operationSpeeds_SPEED_1G_CX1 4 1076 #define generic_operationSpeeds_SPEED_1000M 3 1077 #define generic_operationSpeeds_SPEED_100M 2 1078 #define generic_operationSpeeds_SPEED_10M 1 1079 1080 /**************************************************************************** 1081 * Enums: generic_actualSpeeds 1082 */ 1083 #define generic_actualSpeeds_dr_10M 0 1084 #define generic_actualSpeeds_dr_100M 1 1085 #define generic_actualSpeeds_dr_1G 2 1086 #define generic_actualSpeeds_dr_2p5G 3 1087 #define generic_actualSpeeds_dr_5G_X4 4 1088 #define generic_actualSpeeds_dr_6G_X4 5 1089 #define generic_actualSpeeds_dr_10G_HiG 6 1090 #define generic_actualSpeeds_dr_10G_CX4 7 1091 #define generic_actualSpeeds_dr_12G_HiG 8 1092 #define generic_actualSpeeds_dr_12p5G_X4 9 1093 #define generic_actualSpeeds_dr_13G_X4 10 1094 #define generic_actualSpeeds_dr_15G_X4 11 1095 #define generic_actualSpeeds_dr_16G_X4 12 1096 #define generic_actualSpeeds_dr_1G_KX 13 1097 #define generic_actualSpeeds_dr_10G_KX4 14 1098 #define generic_actualSpeeds_dr_10G_KR 15 1099 #define generic_actualSpeeds_dr_5G 16 1100 #define generic_actualSpeeds_dr_6p4G 17 1101 #define generic_actualSpeeds_dr_20G_X4 18 1102 #define generic_actualSpeeds_dr_21G_X4 19 1103 #define generic_actualSpeeds_dr_25G_X4 20 1104 #define generic_actualSpeeds_dr_10G_HiG_DXGXS 21 1105 #define generic_actualSpeeds_dr_10G_DXGXS 22 1106 #define generic_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1107 #define generic_actualSpeeds_dr_10p5G_DXGXS 24 1108 #define generic_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1109 #define generic_actualSpeeds_dr_12p773G_DXGXS 26 1110 #define generic_actualSpeeds_dr_10G_XFI 27 1111 #define generic_actualSpeeds_dr_40G 28 1112 #define generic_actualSpeeds_dr_20G_HiG_DXGXS 29 1113 #define generic_actualSpeeds_dr_20G_DXGXS 30 1114 #define generic_actualSpeeds_dr_10G_SFI 31 1115 #define generic_actualSpeeds_dr_31p5G 32 1116 #define generic_actualSpeeds_dr_32p7G 33 1117 #define generic_actualSpeeds_dr_20G_SCR 34 1118 #define generic_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1119 #define generic_actualSpeeds_dr_10G_DXGXS_SCR 36 1120 #define generic_actualSpeeds_dr_12G_R2 37 1121 #define generic_actualSpeeds_dr_10G_X2 38 1122 #define generic_actualSpeeds_dr_40G_KR4 39 1123 #define generic_actualSpeeds_dr_40G_CR4 40 1124 #define generic_actualSpeeds_dr_100G_CR10 41 1125 #define generic_actualSpeeds_dr_15p75G_DXGXS 44 1126 #define generic_actualSpeeds_dr_20G_KR2 57 1127 #define generic_actualSpeeds_dr_20G_CR2 58 1128 1129 /**************************************************************************** 1130 * Enums: generic_actualSpeedsMisc1 1131 */ 1132 #define generic_actualSpeedsMisc1_dr_2500BRCM_X1 16 1133 #define generic_actualSpeedsMisc1_dr_5000BRCM_X4 17 1134 #define generic_actualSpeedsMisc1_dr_6000BRCM_X4 18 1135 #define generic_actualSpeedsMisc1_dr_10GHiGig_X4 19 1136 #define generic_actualSpeedsMisc1_dr_10GBASE_CX4 20 1137 #define generic_actualSpeedsMisc1_dr_12GHiGig_X4 21 1138 #define generic_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1139 #define generic_actualSpeedsMisc1_dr_13GHiGig_X4 23 1140 #define generic_actualSpeedsMisc1_dr_15GHiGig_X4 24 1141 #define generic_actualSpeedsMisc1_dr_16GHiGig_X4 25 1142 #define generic_actualSpeedsMisc1_dr_5000BRCM_X1 26 1143 #define generic_actualSpeedsMisc1_dr_6363BRCM_X1 27 1144 #define generic_actualSpeedsMisc1_dr_20GHiGig_X4 28 1145 #define generic_actualSpeedsMisc1_dr_21GHiGig_X4 29 1146 #define generic_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1147 #define generic_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1148 1149 /**************************************************************************** 1150 * Enums: generic_IndLaneModes 1151 */ 1152 #define generic_IndLaneModes_SWSDR_div2 0 1153 #define generic_IndLaneModes_SWSDR_div1 1 1154 #define generic_IndLaneModes_DWSDR_div2 2 1155 #define generic_IndLaneModes_DWSDR_div1 3 1156 1157 /**************************************************************************** 1158 * Enums: generic_prbsSelect 1159 */ 1160 #define generic_prbsSelect_prbs7 0 1161 #define generic_prbsSelect_prbs15 1 1162 #define generic_prbsSelect_prbs23 2 1163 #define generic_prbsSelect_prbs31 3 1164 1165 /**************************************************************************** 1166 * Enums: generic_vcoDivider 1167 */ 1168 #define generic_vcoDivider_div32 0 1169 #define generic_vcoDivider_div36 1 1170 #define generic_vcoDivider_div40 2 1171 #define generic_vcoDivider_div42 3 1172 #define generic_vcoDivider_div48 4 1173 #define generic_vcoDivider_div50 5 1174 #define generic_vcoDivider_div52 6 1175 #define generic_vcoDivider_div54 7 1176 #define generic_vcoDivider_div60 8 1177 #define generic_vcoDivider_div64 9 1178 #define generic_vcoDivider_div66 10 1179 #define generic_vcoDivider_div68 11 1180 #define generic_vcoDivider_div70 12 1181 #define generic_vcoDivider_div80 13 1182 #define generic_vcoDivider_div92 14 1183 #define generic_vcoDivider_div100 15 1184 1185 /**************************************************************************** 1186 * Enums: generic_refClkSelect 1187 */ 1188 #define generic_refClkSelect_clk_25MHz 0 1189 #define generic_refClkSelect_clk_100MHz 1 1190 #define generic_refClkSelect_clk_125MHz 2 1191 #define generic_refClkSelect_clk_156p25MHz 3 1192 #define generic_refClkSelect_clk_187p5MHz 4 1193 #define generic_refClkSelect_clk_161p25Mhz 5 1194 #define generic_refClkSelect_clk_50Mhz 6 1195 #define generic_refClkSelect_clk_106p25Mhz 7 1196 1197 /**************************************************************************** 1198 * Enums: generic_aerMMDdevTypeSelect 1199 */ 1200 #define generic_aerMMDdevTypeSelect_combo_core 0 1201 #define generic_aerMMDdevTypeSelect_PMA_PMD 1 1202 #define generic_aerMMDdevTypeSelect_PCS 3 1203 #define generic_aerMMDdevTypeSelect_PHY 4 1204 #define generic_aerMMDdevTypeSelect_DTE 5 1205 #define generic_aerMMDdevTypeSelect_CL73_AN 7 1206 1207 /**************************************************************************** 1208 * Enums: generic_aerMMDportSelect 1209 */ 1210 #define generic_aerMMDportSelect_ln0 0 1211 #define generic_aerMMDportSelect_ln1 1 1212 #define generic_aerMMDportSelect_ln2 2 1213 #define generic_aerMMDportSelect_ln3 3 1214 #define generic_aerMMDportSelect_BCST_ln0_1_2_3 511 1215 #define generic_aerMMDportSelect_BCST_ln0_1 512 1216 #define generic_aerMMDportSelect_BCST_ln2_3 513 1217 1218 /**************************************************************************** 1219 * Enums: generic_firmwareModeSelect 1220 */ 1221 #define generic_firmwareModeSelect_DEFAULT 0 1222 #define generic_firmwareModeSelect_SFP_OPT_LR 1 1223 #define generic_firmwareModeSelect_SFP_DAC 2 1224 #define generic_firmwareModeSelect_XLAUI 3 1225 #define generic_firmwareModeSelect_LONG_CH_6G 4 1226 1227 /**************************************************************************** 1228 * Enums: generic_tempIdxSelect 1229 */ 1230 #define generic_tempIdxSelect_LTE__22p9C 15 1231 #define generic_tempIdxSelect_LTE__12p6C 14 1232 #define generic_tempIdxSelect_LTE__3p0C 13 1233 #define generic_tempIdxSelect_LTE_6p7C 12 1234 #define generic_tempIdxSelect_LTE_16p4C 11 1235 #define generic_tempIdxSelect_LTE_26p6C 10 1236 #define generic_tempIdxSelect_LTE_36p3C 9 1237 #define generic_tempIdxSelect_LTE_46p0C 8 1238 #define generic_tempIdxSelect_LTE_56p2C 7 1239 #define generic_tempIdxSelect_LTE_65p9C 6 1240 #define generic_tempIdxSelect_LTE_75p6C 5 1241 #define generic_tempIdxSelect_LTE_85p3C 4 1242 #define generic_tempIdxSelect_LTE_95p5C 3 1243 #define generic_tempIdxSelect_LTE_105p2C 2 1244 #define generic_tempIdxSelect_LTE_114p9C 1 1245 #define generic_tempIdxSelect_LTE_125p1C 0 1246 1247 /**************************************************************************** 1248 * Enums: main0_cl36TxEEEStates_l 1249 */ 1250 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1251 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1252 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1253 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1254 1255 /**************************************************************************** 1256 * Enums: main0_cl36TxEEEStates_c 1257 */ 1258 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1259 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1260 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1261 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1262 1263 /**************************************************************************** 1264 * Enums: main0_cl49TxEEEStates_l 1265 */ 1266 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1267 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1268 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1269 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1270 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1271 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1272 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1273 1274 /**************************************************************************** 1275 * Enums: main0_cl49TxEEEStates_c 1276 */ 1277 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1278 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1279 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1280 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1281 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1282 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1283 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1284 1285 /**************************************************************************** 1286 * Enums: main0_cl36RxEEEStates_l 1287 */ 1288 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1289 #define main0_cl36RxEEEStates_l_RX_WTF 16 1290 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1291 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1292 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1293 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1294 1295 /**************************************************************************** 1296 * Enums: main0_cl36RxEEEStates_c 1297 */ 1298 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1299 #define main0_cl36RxEEEStates_c_RX_WTF 4 1300 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1301 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1302 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1303 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1304 1305 /**************************************************************************** 1306 * Enums: main0_cl49RxEEEStates_l 1307 */ 1308 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1309 #define main0_cl49RxEEEStates_l_RX_WTF 16 1310 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1311 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1312 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 1313 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 1314 1315 /**************************************************************************** 1316 * Enums: main0_cl49RxEEEStates_c 1317 */ 1318 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1319 #define main0_cl49RxEEEStates_c_RX_WTF 4 1320 #define main0_cl49RxEEEStates_c_RX_WAKE 3 1321 #define main0_cl49RxEEEStates_c_RX_QUIET 2 1322 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 1323 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 1324 1325 /**************************************************************************** 1326 * Enums: main0_cl48TxEEEStates_l 1327 */ 1328 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 1329 #define main0_cl48TxEEEStates_l_TX_QUIET 4 1330 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 1331 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 1332 1333 /**************************************************************************** 1334 * Enums: main0_cl48TxEEEStates_c 1335 */ 1336 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 1337 #define main0_cl48TxEEEStates_c_TX_QUIET 2 1338 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 1339 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 1340 1341 /**************************************************************************** 1342 * Enums: main0_cl48RxEEEStates_l 1343 */ 1344 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1345 #define main0_cl48RxEEEStates_l_RX_WAKE 16 1346 #define main0_cl48RxEEEStates_l_RX_QUIET 8 1347 #define main0_cl48RxEEEStates_l_RX_DEACT 4 1348 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 1349 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 1350 1351 /**************************************************************************** 1352 * Enums: main0_cl48RxEEEStates_c 1353 */ 1354 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1355 #define main0_cl48RxEEEStates_c_RX_WAKE 4 1356 #define main0_cl48RxEEEStates_c_RX_QUIET 3 1357 #define main0_cl48RxEEEStates_c_RX_DEACT 2 1358 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 1359 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 1360 1361 /**************************************************************************** 1362 * Enums: main0_IQP_Options 1363 */ 1364 #define main0_IQP_Options_i50uA 0 1365 #define main0_IQP_Options_i100uA 1 1366 #define main0_IQP_Options_i150uA 2 1367 #define main0_IQP_Options_i200uA 3 1368 #define main0_IQP_Options_i250uA 4 1369 #define main0_IQP_Options_i300uA 5 1370 #define main0_IQP_Options_i350uA 6 1371 #define main0_IQP_Options_i400uA 7 1372 #define main0_IQP_Options_i450uA 8 1373 #define main0_IQP_Options_i500uA 9 1374 #define main0_IQP_Options_i550uA 10 1375 #define main0_IQP_Options_i600uA 11 1376 #define main0_IQP_Options_i650uA 12 1377 #define main0_IQP_Options_i700uA 13 1378 #define main0_IQP_Options_i750uA 14 1379 #define main0_IQP_Options_i800uA 15 1380 1381 /**************************************************************************** 1382 * Enums: main0_IDriver_Options 1383 */ 1384 #define main0_IDriver_Options_v680mV 0 1385 #define main0_IDriver_Options_v730mV 1 1386 #define main0_IDriver_Options_v780mV 2 1387 #define main0_IDriver_Options_v830mV 3 1388 #define main0_IDriver_Options_v880mV 4 1389 #define main0_IDriver_Options_v930mV 5 1390 #define main0_IDriver_Options_v980mV 6 1391 #define main0_IDriver_Options_v1010mV 7 1392 #define main0_IDriver_Options_v1040mV 8 1393 #define main0_IDriver_Options_v1060mV 9 1394 #define main0_IDriver_Options_v1070mV 10 1395 #define main0_IDriver_Options_v1080mV 11 1396 #define main0_IDriver_Options_v1085mV 12 1397 #define main0_IDriver_Options_v1090mV 13 1398 #define main0_IDriver_Options_v1095mV 14 1399 #define main0_IDriver_Options_v1100mV 15 1400 1401 /**************************************************************************** 1402 * Enums: main0_operationModes 1403 */ 1404 #define main0_operationModes_XGXS 0 1405 #define main0_operationModes_XGXG_nCC 1 1406 #define main0_operationModes_Indlane_OS8 4 1407 #define main0_operationModes_IndLane_OS5 5 1408 #define main0_operationModes_PCI 7 1409 #define main0_operationModes_XGXS_nLQ 8 1410 #define main0_operationModes_XGXS_nLQnCC 9 1411 #define main0_operationModes_PBypass 10 1412 #define main0_operationModes_PBypass_nDSK 11 1413 #define main0_operationModes_ComboCoreMode 12 1414 #define main0_operationModes_Clocks_off 15 1415 1416 /**************************************************************************** 1417 * Enums: main0_synce_enum 1418 */ 1419 #define main0_synce_enum_SYNCE_NO_DIV 0 1420 #define main0_synce_enum_SYNCE_DIV_7 1 1421 #define main0_synce_enum_SYNCE_DIV_11 2 1422 1423 /**************************************************************************** 1424 * Enums: main0_operationSpeeds 1425 */ 1426 #define main0_operationSpeeds_SPEED_5G_X1_12p5 65 1427 #define main0_operationSpeeds_SPEED_2p5G_X1_12p5 64 1428 #define main0_operationSpeeds_SPEED_1000M_12p5 63 1429 #define main0_operationSpeeds_SPEED_100M_12p5 62 1430 #define main0_operationSpeeds_SPEED_10M_12p5 61 1431 #define main0_operationSpeeds_SPEED_4G_X1_10 60 1432 #define main0_operationSpeeds_SPEED_1000M_X1_10 59 1433 #define main0_operationSpeeds_SPEED_100M_X1_10 58 1434 #define main0_operationSpeeds_SPEED_10M_X1_10 57 1435 #define main0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1436 #define main0_operationSpeeds_SPEED_1000M_10p3125 55 1437 #define main0_operationSpeeds_SPEED_100M_10p3125 54 1438 #define main0_operationSpeeds_SPEED_10M_10p3125 53 1439 #define main0_operationSpeeds_SPEED_10p5G_X4 50 1440 #define main0_operationSpeeds_SPEED_5G_KR1 49 1441 #define main0_operationSpeeds_SPEED_127G_X12 39 1442 #define main0_operationSpeeds_SPEED_120G_X12 38 1443 #define main0_operationSpeeds_SPEED_107G_X10 37 1444 #define main0_operationSpeeds_SPEED_100G_CR10 36 1445 #define main0_operationSpeeds_SPEED_42G_X4 35 1446 #define main0_operationSpeeds_SPEED_40G_CR4 34 1447 #define main0_operationSpeeds_SPEED_40G_KR4 33 1448 #define main0_operationSpeeds_SPEED_21G_X2 32 1449 #define main0_operationSpeeds_SPEED_20G_CR2 31 1450 #define main0_operationSpeeds_SPEED_20G_KR2 30 1451 #define main0_operationSpeeds_SPEED_10p6_X1 29 1452 #define main0_operationSpeeds_SPEED_10G_KR1 28 1453 #define main0_operationSpeeds_SPEED_40G_X4 27 1454 #define main0_operationSpeeds_SPEED_20G_X2 26 1455 #define main0_operationSpeeds_SPEED_20G_CX2 25 1456 #define main0_operationSpeeds_SPEED_31p5G_KR4 24 1457 #define main0_operationSpeeds_SPEED_31p5G_X4 23 1458 #define main0_operationSpeeds_SPEED_15p75G_X2 22 1459 #define main0_operationSpeeds_SPEED_25p45G_X4 21 1460 #define main0_operationSpeeds_SPEED_12p7G_X2 20 1461 #define main0_operationSpeeds_SPEED_21G_X4 19 1462 #define main0_operationSpeeds_SPEED_10p5G_X2 18 1463 #define main0_operationSpeeds_SPEED_20G_X4 17 1464 #define main0_operationSpeeds_SPEED_10G_X2 16 1465 #define main0_operationSpeeds_SPEED_10G_CX2 15 1466 #define main0_operationSpeeds_SPEED_20G_CX4 14 1467 #define main0_operationSpeeds_SPEED_16G_X4 13 1468 #define main0_operationSpeeds_SPEED_15G_X4 12 1469 #define main0_operationSpeeds_SPEED_13G_X4 11 1470 #define main0_operationSpeeds_SPEED_10G_X4 10 1471 #define main0_operationSpeeds_SPEED_10G_KX4 9 1472 #define main0_operationSpeeds_SPEED_10G_CX4 8 1473 #define main0_operationSpeeds_SPEED_5G_X1 7 1474 #define main0_operationSpeeds_SPEED_2p5G_X1 6 1475 #define main0_operationSpeeds_SPEED_1G_KX1 5 1476 #define main0_operationSpeeds_SPEED_1G_CX1 4 1477 #define main0_operationSpeeds_SPEED_1000M 3 1478 #define main0_operationSpeeds_SPEED_100M 2 1479 #define main0_operationSpeeds_SPEED_10M 1 1480 1481 /**************************************************************************** 1482 * Enums: main0_actualSpeeds 1483 */ 1484 #define main0_actualSpeeds_dr_10M 0 1485 #define main0_actualSpeeds_dr_100M 1 1486 #define main0_actualSpeeds_dr_1G 2 1487 #define main0_actualSpeeds_dr_2p5G 3 1488 #define main0_actualSpeeds_dr_5G_X4 4 1489 #define main0_actualSpeeds_dr_6G_X4 5 1490 #define main0_actualSpeeds_dr_10G_HiG 6 1491 #define main0_actualSpeeds_dr_10G_CX4 7 1492 #define main0_actualSpeeds_dr_12G_HiG 8 1493 #define main0_actualSpeeds_dr_12p5G_X4 9 1494 #define main0_actualSpeeds_dr_13G_X4 10 1495 #define main0_actualSpeeds_dr_15G_X4 11 1496 #define main0_actualSpeeds_dr_16G_X4 12 1497 #define main0_actualSpeeds_dr_1G_KX 13 1498 #define main0_actualSpeeds_dr_10G_KX4 14 1499 #define main0_actualSpeeds_dr_10G_KR 15 1500 #define main0_actualSpeeds_dr_5G 16 1501 #define main0_actualSpeeds_dr_6p4G 17 1502 #define main0_actualSpeeds_dr_20G_X4 18 1503 #define main0_actualSpeeds_dr_21G_X4 19 1504 #define main0_actualSpeeds_dr_25G_X4 20 1505 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 1506 #define main0_actualSpeeds_dr_10G_DXGXS 22 1507 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1508 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 1509 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1510 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 1511 #define main0_actualSpeeds_dr_10G_XFI 27 1512 #define main0_actualSpeeds_dr_40G 28 1513 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 1514 #define main0_actualSpeeds_dr_20G_DXGXS 30 1515 #define main0_actualSpeeds_dr_10G_SFI 31 1516 #define main0_actualSpeeds_dr_31p5G 32 1517 #define main0_actualSpeeds_dr_32p7G 33 1518 #define main0_actualSpeeds_dr_20G_SCR 34 1519 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1520 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 1521 #define main0_actualSpeeds_dr_12G_R2 37 1522 #define main0_actualSpeeds_dr_10G_X2 38 1523 #define main0_actualSpeeds_dr_40G_KR4 39 1524 #define main0_actualSpeeds_dr_40G_CR4 40 1525 #define main0_actualSpeeds_dr_100G_CR10 41 1526 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 1527 #define main0_actualSpeeds_dr_20G_KR2 57 1528 #define main0_actualSpeeds_dr_20G_CR2 58 1529 1530 /**************************************************************************** 1531 * Enums: main0_actualSpeedsMisc1 1532 */ 1533 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1534 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1535 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1536 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1537 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1538 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1539 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1540 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1541 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1542 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1543 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1544 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1545 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1546 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1547 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1548 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1549 1550 /**************************************************************************** 1551 * Enums: main0_IndLaneModes 1552 */ 1553 #define main0_IndLaneModes_SWSDR_div2 0 1554 #define main0_IndLaneModes_SWSDR_div1 1 1555 #define main0_IndLaneModes_DWSDR_div2 2 1556 #define main0_IndLaneModes_DWSDR_div1 3 1557 1558 /**************************************************************************** 1559 * Enums: main0_prbsSelect 1560 */ 1561 #define main0_prbsSelect_prbs7 0 1562 #define main0_prbsSelect_prbs15 1 1563 #define main0_prbsSelect_prbs23 2 1564 #define main0_prbsSelect_prbs31 3 1565 1566 /**************************************************************************** 1567 * Enums: main0_vcoDivider 1568 */ 1569 #define main0_vcoDivider_div32 0 1570 #define main0_vcoDivider_div36 1 1571 #define main0_vcoDivider_div40 2 1572 #define main0_vcoDivider_div42 3 1573 #define main0_vcoDivider_div48 4 1574 #define main0_vcoDivider_div50 5 1575 #define main0_vcoDivider_div52 6 1576 #define main0_vcoDivider_div54 7 1577 #define main0_vcoDivider_div60 8 1578 #define main0_vcoDivider_div64 9 1579 #define main0_vcoDivider_div66 10 1580 #define main0_vcoDivider_div68 11 1581 #define main0_vcoDivider_div70 12 1582 #define main0_vcoDivider_div80 13 1583 #define main0_vcoDivider_div92 14 1584 #define main0_vcoDivider_div100 15 1585 1586 /**************************************************************************** 1587 * Enums: main0_refClkSelect 1588 */ 1589 #define main0_refClkSelect_clk_25MHz 0 1590 #define main0_refClkSelect_clk_100MHz 1 1591 #define main0_refClkSelect_clk_125MHz 2 1592 #define main0_refClkSelect_clk_156p25MHz 3 1593 #define main0_refClkSelect_clk_187p5MHz 4 1594 #define main0_refClkSelect_clk_161p25Mhz 5 1595 #define main0_refClkSelect_clk_50Mhz 6 1596 #define main0_refClkSelect_clk_106p25Mhz 7 1597 1598 /**************************************************************************** 1599 * Enums: main0_aerMMDdevTypeSelect 1600 */ 1601 #define main0_aerMMDdevTypeSelect_combo_core 0 1602 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 1603 #define main0_aerMMDdevTypeSelect_PCS 3 1604 #define main0_aerMMDdevTypeSelect_PHY 4 1605 #define main0_aerMMDdevTypeSelect_DTE 5 1606 #define main0_aerMMDdevTypeSelect_CL73_AN 7 1607 1608 /**************************************************************************** 1609 * Enums: main0_aerMMDportSelect 1610 */ 1611 #define main0_aerMMDportSelect_ln0 0 1612 #define main0_aerMMDportSelect_ln1 1 1613 #define main0_aerMMDportSelect_ln2 2 1614 #define main0_aerMMDportSelect_ln3 3 1615 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 1616 #define main0_aerMMDportSelect_BCST_ln0_1 512 1617 #define main0_aerMMDportSelect_BCST_ln2_3 513 1618 1619 /**************************************************************************** 1620 * Enums: main0_firmwareModeSelect 1621 */ 1622 #define main0_firmwareModeSelect_DEFAULT 0 1623 #define main0_firmwareModeSelect_SFP_OPT_LR 1 1624 #define main0_firmwareModeSelect_SFP_DAC 2 1625 #define main0_firmwareModeSelect_XLAUI 3 1626 #define main0_firmwareModeSelect_LONG_CH_6G 4 1627 1628 /**************************************************************************** 1629 * Enums: main0_tempIdxSelect 1630 */ 1631 #define main0_tempIdxSelect_LTE__22p9C 15 1632 #define main0_tempIdxSelect_LTE__12p6C 14 1633 #define main0_tempIdxSelect_LTE__3p0C 13 1634 #define main0_tempIdxSelect_LTE_6p7C 12 1635 #define main0_tempIdxSelect_LTE_16p4C 11 1636 #define main0_tempIdxSelect_LTE_26p6C 10 1637 #define main0_tempIdxSelect_LTE_36p3C 9 1638 #define main0_tempIdxSelect_LTE_46p0C 8 1639 #define main0_tempIdxSelect_LTE_56p2C 7 1640 #define main0_tempIdxSelect_LTE_65p9C 6 1641 #define main0_tempIdxSelect_LTE_75p6C 5 1642 #define main0_tempIdxSelect_LTE_85p3C 4 1643 #define main0_tempIdxSelect_LTE_95p5C 3 1644 #define main0_tempIdxSelect_LTE_105p2C 2 1645 #define main0_tempIdxSelect_LTE_114p9C 1 1646 #define main0_tempIdxSelect_LTE_125p1C 0 1647 1648 /**************************************************************************** 1649 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 1650 */ 1651 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 1652 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 1653 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 1654 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 1655 1656 /**************************************************************************** 1657 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 1658 */ 1659 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 1660 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 1661 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 1662 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 1663 1664 /**************************************************************************** 1665 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 1666 */ 1667 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 1668 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 1669 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 1670 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 1671 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 1672 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 1673 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 1674 1675 /**************************************************************************** 1676 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 1677 */ 1678 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 1679 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 1680 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 1681 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 1682 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 1683 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 1684 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 1685 1686 /**************************************************************************** 1687 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 1688 */ 1689 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1690 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 1691 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 1692 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 1693 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 1694 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 1695 1696 /**************************************************************************** 1697 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 1698 */ 1699 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1700 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 1701 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 1702 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 1703 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 1704 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 1705 1706 /**************************************************************************** 1707 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 1708 */ 1709 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1710 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 1711 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 1712 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 1713 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 1714 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 1715 1716 /**************************************************************************** 1717 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 1718 */ 1719 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1720 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 1721 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 1722 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 1723 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 1724 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 1725 1726 /**************************************************************************** 1727 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 1728 */ 1729 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 1730 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 1731 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 1732 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 1733 1734 /**************************************************************************** 1735 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 1736 */ 1737 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 1738 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 1739 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 1740 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 1741 1742 /**************************************************************************** 1743 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 1744 */ 1745 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1746 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 1747 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 1748 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 1749 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 1750 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 1751 1752 /**************************************************************************** 1753 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 1754 */ 1755 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1756 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 1757 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 1758 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 1759 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 1760 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 1761 1762 /**************************************************************************** 1763 * Enums: sc_x1_speed_override0_IQP_Options 1764 */ 1765 #define sc_x1_speed_override0_IQP_Options_i50uA 0 1766 #define sc_x1_speed_override0_IQP_Options_i100uA 1 1767 #define sc_x1_speed_override0_IQP_Options_i150uA 2 1768 #define sc_x1_speed_override0_IQP_Options_i200uA 3 1769 #define sc_x1_speed_override0_IQP_Options_i250uA 4 1770 #define sc_x1_speed_override0_IQP_Options_i300uA 5 1771 #define sc_x1_speed_override0_IQP_Options_i350uA 6 1772 #define sc_x1_speed_override0_IQP_Options_i400uA 7 1773 #define sc_x1_speed_override0_IQP_Options_i450uA 8 1774 #define sc_x1_speed_override0_IQP_Options_i500uA 9 1775 #define sc_x1_speed_override0_IQP_Options_i550uA 10 1776 #define sc_x1_speed_override0_IQP_Options_i600uA 11 1777 #define sc_x1_speed_override0_IQP_Options_i650uA 12 1778 #define sc_x1_speed_override0_IQP_Options_i700uA 13 1779 #define sc_x1_speed_override0_IQP_Options_i750uA 14 1780 #define sc_x1_speed_override0_IQP_Options_i800uA 15 1781 1782 /**************************************************************************** 1783 * Enums: sc_x1_speed_override0_IDriver_Options 1784 */ 1785 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 1786 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 1787 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 1788 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 1789 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 1790 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 1791 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 1792 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 1793 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 1794 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 1795 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 1796 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 1797 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 1798 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 1799 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 1800 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 1801 1802 /**************************************************************************** 1803 * Enums: sc_x1_speed_override0_operationModes 1804 */ 1805 #define sc_x1_speed_override0_operationModes_XGXS 0 1806 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 1807 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 1808 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 1809 #define sc_x1_speed_override0_operationModes_PCI 7 1810 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 1811 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 1812 #define sc_x1_speed_override0_operationModes_PBypass 10 1813 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 1814 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 1815 #define sc_x1_speed_override0_operationModes_Clocks_off 15 1816 1817 /**************************************************************************** 1818 * Enums: sc_x1_speed_override0_synce_enum 1819 */ 1820 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 1821 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 1822 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 1823 1824 /**************************************************************************** 1825 * Enums: sc_x1_speed_override0_operationSpeeds 1826 */ 1827 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1_12p5 65 1828 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_12p5 64 1829 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_12p5 63 1830 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_12p5 62 1831 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_12p5 61 1832 #define sc_x1_speed_override0_operationSpeeds_SPEED_4G_X1_10 60 1833 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_X1_10 59 1834 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_X1_10 58 1835 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_X1_10 57 1836 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1837 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_10p3125 55 1838 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_10p3125 54 1839 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_10p3125 53 1840 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X4 50 1841 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_KR1 49 1842 #define sc_x1_speed_override0_operationSpeeds_SPEED_127G_X12 39 1843 #define sc_x1_speed_override0_operationSpeeds_SPEED_120G_X12 38 1844 #define sc_x1_speed_override0_operationSpeeds_SPEED_107G_X10 37 1845 #define sc_x1_speed_override0_operationSpeeds_SPEED_100G_CR10 36 1846 #define sc_x1_speed_override0_operationSpeeds_SPEED_42G_X4 35 1847 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_CR4 34 1848 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_KR4 33 1849 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X2 32 1850 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CR2 31 1851 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_KR2 30 1852 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p6_X1 29 1853 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KR1 28 1854 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_X4 27 1855 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X2 26 1856 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX2 25 1857 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_KR4 24 1858 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_X4 23 1859 #define sc_x1_speed_override0_operationSpeeds_SPEED_15p75G_X2 22 1860 #define sc_x1_speed_override0_operationSpeeds_SPEED_25p45G_X4 21 1861 #define sc_x1_speed_override0_operationSpeeds_SPEED_12p7G_X2 20 1862 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X4 19 1863 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X2 18 1864 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X4 17 1865 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X2 16 1866 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX2 15 1867 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX4 14 1868 #define sc_x1_speed_override0_operationSpeeds_SPEED_16G_X4 13 1869 #define sc_x1_speed_override0_operationSpeeds_SPEED_15G_X4 12 1870 #define sc_x1_speed_override0_operationSpeeds_SPEED_13G_X4 11 1871 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X4 10 1872 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KX4 9 1873 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX4 8 1874 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1 7 1875 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1 6 1876 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_KX1 5 1877 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_CX1 4 1878 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M 3 1879 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M 2 1880 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M 1 1881 1882 /**************************************************************************** 1883 * Enums: sc_x1_speed_override0_actualSpeeds 1884 */ 1885 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 1886 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 1887 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 1888 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 1889 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 1890 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 1891 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 1892 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 1893 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 1894 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 1895 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 1896 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 1897 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 1898 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 1899 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 1900 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 1901 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 1902 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 1903 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 1904 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 1905 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 1906 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 1907 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 1908 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1909 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 1910 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1911 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 1912 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 1913 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 1914 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 1915 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 1916 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 1917 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 1918 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 1919 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 1920 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1921 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 1922 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 1923 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 1924 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 1925 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 1926 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 1927 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 1928 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 1929 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 1930 1931 /**************************************************************************** 1932 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 1933 */ 1934 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1935 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1936 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1937 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1938 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1939 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1940 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1941 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1942 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1943 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1944 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1945 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1946 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1947 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1948 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1949 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1950 1951 /**************************************************************************** 1952 * Enums: sc_x1_speed_override0_IndLaneModes 1953 */ 1954 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 1955 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 1956 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 1957 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 1958 1959 /**************************************************************************** 1960 * Enums: sc_x1_speed_override0_prbsSelect 1961 */ 1962 #define sc_x1_speed_override0_prbsSelect_prbs7 0 1963 #define sc_x1_speed_override0_prbsSelect_prbs15 1 1964 #define sc_x1_speed_override0_prbsSelect_prbs23 2 1965 #define sc_x1_speed_override0_prbsSelect_prbs31 3 1966 1967 /**************************************************************************** 1968 * Enums: sc_x1_speed_override0_vcoDivider 1969 */ 1970 #define sc_x1_speed_override0_vcoDivider_div32 0 1971 #define sc_x1_speed_override0_vcoDivider_div36 1 1972 #define sc_x1_speed_override0_vcoDivider_div40 2 1973 #define sc_x1_speed_override0_vcoDivider_div42 3 1974 #define sc_x1_speed_override0_vcoDivider_div48 4 1975 #define sc_x1_speed_override0_vcoDivider_div50 5 1976 #define sc_x1_speed_override0_vcoDivider_div52 6 1977 #define sc_x1_speed_override0_vcoDivider_div54 7 1978 #define sc_x1_speed_override0_vcoDivider_div60 8 1979 #define sc_x1_speed_override0_vcoDivider_div64 9 1980 #define sc_x1_speed_override0_vcoDivider_div66 10 1981 #define sc_x1_speed_override0_vcoDivider_div68 11 1982 #define sc_x1_speed_override0_vcoDivider_div70 12 1983 #define sc_x1_speed_override0_vcoDivider_div80 13 1984 #define sc_x1_speed_override0_vcoDivider_div92 14 1985 #define sc_x1_speed_override0_vcoDivider_div100 15 1986 1987 /**************************************************************************** 1988 * Enums: sc_x1_speed_override0_refClkSelect 1989 */ 1990 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 1991 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 1992 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 1993 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 1994 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 1995 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 1996 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 1997 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 1998 1999 /**************************************************************************** 2000 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 2001 */ 2002 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 2003 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 2004 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 2005 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 2006 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 2007 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 2008 2009 /**************************************************************************** 2010 * Enums: sc_x1_speed_override0_aerMMDportSelect 2011 */ 2012 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 2013 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 2014 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 2015 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 2016 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 2017 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 2018 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 2019 2020 /**************************************************************************** 2021 * Enums: sc_x1_speed_override0_firmwareModeSelect 2022 */ 2023 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 2024 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 2025 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 2026 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 2027 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 2028 2029 /**************************************************************************** 2030 * Enums: sc_x1_speed_override0_tempIdxSelect 2031 */ 2032 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 2033 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 2034 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 2035 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 2036 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 2037 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 2038 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 2039 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 2040 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 2041 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 2042 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 2043 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 2044 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 2045 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 2046 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 2047 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 2048 2049 /**************************************************************************** 2050 * Enums: sc_x4_control_cl36TxEEEStates_l 2051 */ 2052 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 2053 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 2054 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 2055 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 2056 2057 /**************************************************************************** 2058 * Enums: sc_x4_control_cl36TxEEEStates_c 2059 */ 2060 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 2061 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 2062 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 2063 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 2064 2065 /**************************************************************************** 2066 * Enums: sc_x4_control_cl49TxEEEStates_l 2067 */ 2068 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 2069 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 2070 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 2071 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 2072 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 2073 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 2074 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 2075 2076 /**************************************************************************** 2077 * Enums: sc_x4_control_cl49TxEEEStates_c 2078 */ 2079 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 2080 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 2081 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 2082 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 2083 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 2084 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 2085 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 2086 2087 /**************************************************************************** 2088 * Enums: sc_x4_control_cl36RxEEEStates_l 2089 */ 2090 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 2091 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 2092 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 2093 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 2094 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 2095 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 2096 2097 /**************************************************************************** 2098 * Enums: sc_x4_control_cl36RxEEEStates_c 2099 */ 2100 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 2101 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 2102 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 2103 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 2104 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 2105 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 2106 2107 /**************************************************************************** 2108 * Enums: sc_x4_control_cl49RxEEEStates_l 2109 */ 2110 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 2111 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 2112 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 2113 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 2114 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 2115 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 2116 2117 /**************************************************************************** 2118 * Enums: sc_x4_control_cl49RxEEEStates_c 2119 */ 2120 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 2121 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 2122 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 2123 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 2124 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 2125 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 2126 2127 /**************************************************************************** 2128 * Enums: sc_x4_control_cl48TxEEEStates_l 2129 */ 2130 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 2131 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 2132 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 2133 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 2134 2135 /**************************************************************************** 2136 * Enums: sc_x4_control_cl48TxEEEStates_c 2137 */ 2138 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 2139 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 2140 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 2141 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 2142 2143 /**************************************************************************** 2144 * Enums: sc_x4_control_cl48RxEEEStates_l 2145 */ 2146 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 2147 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 2148 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 2149 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 2150 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 2151 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 2152 2153 /**************************************************************************** 2154 * Enums: sc_x4_control_cl48RxEEEStates_c 2155 */ 2156 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 2157 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 2158 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 2159 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 2160 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 2161 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 2162 2163 /**************************************************************************** 2164 * Enums: sc_x4_control_IQP_Options 2165 */ 2166 #define sc_x4_control_IQP_Options_i50uA 0 2167 #define sc_x4_control_IQP_Options_i100uA 1 2168 #define sc_x4_control_IQP_Options_i150uA 2 2169 #define sc_x4_control_IQP_Options_i200uA 3 2170 #define sc_x4_control_IQP_Options_i250uA 4 2171 #define sc_x4_control_IQP_Options_i300uA 5 2172 #define sc_x4_control_IQP_Options_i350uA 6 2173 #define sc_x4_control_IQP_Options_i400uA 7 2174 #define sc_x4_control_IQP_Options_i450uA 8 2175 #define sc_x4_control_IQP_Options_i500uA 9 2176 #define sc_x4_control_IQP_Options_i550uA 10 2177 #define sc_x4_control_IQP_Options_i600uA 11 2178 #define sc_x4_control_IQP_Options_i650uA 12 2179 #define sc_x4_control_IQP_Options_i700uA 13 2180 #define sc_x4_control_IQP_Options_i750uA 14 2181 #define sc_x4_control_IQP_Options_i800uA 15 2182 2183 /**************************************************************************** 2184 * Enums: sc_x4_control_IDriver_Options 2185 */ 2186 #define sc_x4_control_IDriver_Options_v680mV 0 2187 #define sc_x4_control_IDriver_Options_v730mV 1 2188 #define sc_x4_control_IDriver_Options_v780mV 2 2189 #define sc_x4_control_IDriver_Options_v830mV 3 2190 #define sc_x4_control_IDriver_Options_v880mV 4 2191 #define sc_x4_control_IDriver_Options_v930mV 5 2192 #define sc_x4_control_IDriver_Options_v980mV 6 2193 #define sc_x4_control_IDriver_Options_v1010mV 7 2194 #define sc_x4_control_IDriver_Options_v1040mV 8 2195 #define sc_x4_control_IDriver_Options_v1060mV 9 2196 #define sc_x4_control_IDriver_Options_v1070mV 10 2197 #define sc_x4_control_IDriver_Options_v1080mV 11 2198 #define sc_x4_control_IDriver_Options_v1085mV 12 2199 #define sc_x4_control_IDriver_Options_v1090mV 13 2200 #define sc_x4_control_IDriver_Options_v1095mV 14 2201 #define sc_x4_control_IDriver_Options_v1100mV 15 2202 2203 /**************************************************************************** 2204 * Enums: sc_x4_control_operationModes 2205 */ 2206 #define sc_x4_control_operationModes_XGXS 0 2207 #define sc_x4_control_operationModes_XGXG_nCC 1 2208 #define sc_x4_control_operationModes_Indlane_OS8 4 2209 #define sc_x4_control_operationModes_IndLane_OS5 5 2210 #define sc_x4_control_operationModes_PCI 7 2211 #define sc_x4_control_operationModes_XGXS_nLQ 8 2212 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 2213 #define sc_x4_control_operationModes_PBypass 10 2214 #define sc_x4_control_operationModes_PBypass_nDSK 11 2215 #define sc_x4_control_operationModes_ComboCoreMode 12 2216 #define sc_x4_control_operationModes_Clocks_off 15 2217 2218 /**************************************************************************** 2219 * Enums: sc_x4_control_synce_enum 2220 */ 2221 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 2222 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 2223 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 2224 2225 /**************************************************************************** 2226 * Enums: sc_x4_control_operationSpeeds 2227 */ 2228 #define sc_x4_control_operationSpeeds_SPEED_5G_X1_12p5 65 2229 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_12p5 64 2230 #define sc_x4_control_operationSpeeds_SPEED_1000M_12p5 63 2231 #define sc_x4_control_operationSpeeds_SPEED_100M_12p5 62 2232 #define sc_x4_control_operationSpeeds_SPEED_10M_12p5 61 2233 #define sc_x4_control_operationSpeeds_SPEED_4G_X1_10 60 2234 #define sc_x4_control_operationSpeeds_SPEED_1000M_X1_10 59 2235 #define sc_x4_control_operationSpeeds_SPEED_100M_X1_10 58 2236 #define sc_x4_control_operationSpeeds_SPEED_10M_X1_10 57 2237 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2238 #define sc_x4_control_operationSpeeds_SPEED_1000M_10p3125 55 2239 #define sc_x4_control_operationSpeeds_SPEED_100M_10p3125 54 2240 #define sc_x4_control_operationSpeeds_SPEED_10M_10p3125 53 2241 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X4 50 2242 #define sc_x4_control_operationSpeeds_SPEED_5G_KR1 49 2243 #define sc_x4_control_operationSpeeds_SPEED_127G_X12 39 2244 #define sc_x4_control_operationSpeeds_SPEED_120G_X12 38 2245 #define sc_x4_control_operationSpeeds_SPEED_107G_X10 37 2246 #define sc_x4_control_operationSpeeds_SPEED_100G_CR10 36 2247 #define sc_x4_control_operationSpeeds_SPEED_42G_X4 35 2248 #define sc_x4_control_operationSpeeds_SPEED_40G_CR4 34 2249 #define sc_x4_control_operationSpeeds_SPEED_40G_KR4 33 2250 #define sc_x4_control_operationSpeeds_SPEED_21G_X2 32 2251 #define sc_x4_control_operationSpeeds_SPEED_20G_CR2 31 2252 #define sc_x4_control_operationSpeeds_SPEED_20G_KR2 30 2253 #define sc_x4_control_operationSpeeds_SPEED_10p6_X1 29 2254 #define sc_x4_control_operationSpeeds_SPEED_10G_KR1 28 2255 #define sc_x4_control_operationSpeeds_SPEED_40G_X4 27 2256 #define sc_x4_control_operationSpeeds_SPEED_20G_X2 26 2257 #define sc_x4_control_operationSpeeds_SPEED_20G_CX2 25 2258 #define sc_x4_control_operationSpeeds_SPEED_31p5G_KR4 24 2259 #define sc_x4_control_operationSpeeds_SPEED_31p5G_X4 23 2260 #define sc_x4_control_operationSpeeds_SPEED_15p75G_X2 22 2261 #define sc_x4_control_operationSpeeds_SPEED_25p45G_X4 21 2262 #define sc_x4_control_operationSpeeds_SPEED_12p7G_X2 20 2263 #define sc_x4_control_operationSpeeds_SPEED_21G_X4 19 2264 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X2 18 2265 #define sc_x4_control_operationSpeeds_SPEED_20G_X4 17 2266 #define sc_x4_control_operationSpeeds_SPEED_10G_X2 16 2267 #define sc_x4_control_operationSpeeds_SPEED_10G_CX2 15 2268 #define sc_x4_control_operationSpeeds_SPEED_20G_CX4 14 2269 #define sc_x4_control_operationSpeeds_SPEED_16G_X4 13 2270 #define sc_x4_control_operationSpeeds_SPEED_15G_X4 12 2271 #define sc_x4_control_operationSpeeds_SPEED_13G_X4 11 2272 #define sc_x4_control_operationSpeeds_SPEED_10G_X4 10 2273 #define sc_x4_control_operationSpeeds_SPEED_10G_KX4 9 2274 #define sc_x4_control_operationSpeeds_SPEED_10G_CX4 8 2275 #define sc_x4_control_operationSpeeds_SPEED_5G_X1 7 2276 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1 6 2277 #define sc_x4_control_operationSpeeds_SPEED_1G_KX1 5 2278 #define sc_x4_control_operationSpeeds_SPEED_1G_CX1 4 2279 #define sc_x4_control_operationSpeeds_SPEED_1000M 3 2280 #define sc_x4_control_operationSpeeds_SPEED_100M 2 2281 #define sc_x4_control_operationSpeeds_SPEED_10M 1 2282 2283 /**************************************************************************** 2284 * Enums: sc_x4_control_actualSpeeds 2285 */ 2286 #define sc_x4_control_actualSpeeds_dr_10M 0 2287 #define sc_x4_control_actualSpeeds_dr_100M 1 2288 #define sc_x4_control_actualSpeeds_dr_1G 2 2289 #define sc_x4_control_actualSpeeds_dr_2p5G 3 2290 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 2291 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 2292 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 2293 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 2294 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 2295 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 2296 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 2297 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 2298 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 2299 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 2300 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 2301 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 2302 #define sc_x4_control_actualSpeeds_dr_5G 16 2303 #define sc_x4_control_actualSpeeds_dr_6p4G 17 2304 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 2305 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 2306 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 2307 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 2308 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 2309 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2310 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 2311 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2312 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 2313 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 2314 #define sc_x4_control_actualSpeeds_dr_40G 28 2315 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 2316 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 2317 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 2318 #define sc_x4_control_actualSpeeds_dr_31p5G 32 2319 #define sc_x4_control_actualSpeeds_dr_32p7G 33 2320 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 2321 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2322 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 2323 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 2324 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 2325 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 2326 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 2327 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 2328 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 2329 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 2330 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 2331 2332 /**************************************************************************** 2333 * Enums: sc_x4_control_actualSpeedsMisc1 2334 */ 2335 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 2336 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 2337 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 2338 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 2339 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 2340 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 2341 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2342 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 2343 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 2344 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 2345 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 2346 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 2347 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 2348 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 2349 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2350 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2351 2352 /**************************************************************************** 2353 * Enums: sc_x4_control_IndLaneModes 2354 */ 2355 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 2356 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 2357 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 2358 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 2359 2360 /**************************************************************************** 2361 * Enums: sc_x4_control_prbsSelect 2362 */ 2363 #define sc_x4_control_prbsSelect_prbs7 0 2364 #define sc_x4_control_prbsSelect_prbs15 1 2365 #define sc_x4_control_prbsSelect_prbs23 2 2366 #define sc_x4_control_prbsSelect_prbs31 3 2367 2368 /**************************************************************************** 2369 * Enums: sc_x4_control_vcoDivider 2370 */ 2371 #define sc_x4_control_vcoDivider_div32 0 2372 #define sc_x4_control_vcoDivider_div36 1 2373 #define sc_x4_control_vcoDivider_div40 2 2374 #define sc_x4_control_vcoDivider_div42 3 2375 #define sc_x4_control_vcoDivider_div48 4 2376 #define sc_x4_control_vcoDivider_div50 5 2377 #define sc_x4_control_vcoDivider_div52 6 2378 #define sc_x4_control_vcoDivider_div54 7 2379 #define sc_x4_control_vcoDivider_div60 8 2380 #define sc_x4_control_vcoDivider_div64 9 2381 #define sc_x4_control_vcoDivider_div66 10 2382 #define sc_x4_control_vcoDivider_div68 11 2383 #define sc_x4_control_vcoDivider_div70 12 2384 #define sc_x4_control_vcoDivider_div80 13 2385 #define sc_x4_control_vcoDivider_div92 14 2386 #define sc_x4_control_vcoDivider_div100 15 2387 2388 /**************************************************************************** 2389 * Enums: sc_x4_control_refClkSelect 2390 */ 2391 #define sc_x4_control_refClkSelect_clk_25MHz 0 2392 #define sc_x4_control_refClkSelect_clk_100MHz 1 2393 #define sc_x4_control_refClkSelect_clk_125MHz 2 2394 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 2395 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 2396 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 2397 #define sc_x4_control_refClkSelect_clk_50Mhz 6 2398 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 2399 2400 /**************************************************************************** 2401 * Enums: sc_x4_control_aerMMDdevTypeSelect 2402 */ 2403 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 2404 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 2405 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 2406 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 2407 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 2408 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 2409 2410 /**************************************************************************** 2411 * Enums: sc_x4_control_aerMMDportSelect 2412 */ 2413 #define sc_x4_control_aerMMDportSelect_ln0 0 2414 #define sc_x4_control_aerMMDportSelect_ln1 1 2415 #define sc_x4_control_aerMMDportSelect_ln2 2 2416 #define sc_x4_control_aerMMDportSelect_ln3 3 2417 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 2418 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 2419 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 2420 2421 /**************************************************************************** 2422 * Enums: sc_x4_control_firmwareModeSelect 2423 */ 2424 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 2425 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 2426 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 2427 #define sc_x4_control_firmwareModeSelect_XLAUI 3 2428 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 2429 2430 /**************************************************************************** 2431 * Enums: sc_x4_control_tempIdxSelect 2432 */ 2433 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 2434 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 2435 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 2436 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 2437 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 2438 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 2439 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 2440 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 2441 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 2442 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 2443 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 2444 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 2445 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 2446 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 2447 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 2448 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 2449 2450 /**************************************************************************** 2451 * Enums: sc_x4_control_sc_seq_status 2452 */ 2453 #define sc_x4_control_sc_seq_status_START 32768 2454 #define sc_x4_control_sc_seq_status_RESET_PCS 16384 2455 #define sc_x4_control_sc_seq_status_RESET_PMD_LANE 8192 2456 #define sc_x4_control_sc_seq_status_RESET_PMD_PLL 4096 2457 #define sc_x4_control_sc_seq_status_APPLY_SPEED_CFG 2048 2458 #define sc_x4_control_sc_seq_status_WAIT_CFG_DONE 1024 2459 #define sc_x4_control_sc_seq_status_ACTIVATE_PMD 512 2460 #define sc_x4_control_sc_seq_status_WAIT_PLL_RESET 256 2461 #define sc_x4_control_sc_seq_status_PLL_LOCK_FAIL 128 2462 #define sc_x4_control_sc_seq_status_ACTIVATE_TX 64 2463 #define sc_x4_control_sc_seq_status_WAIT_PMD_LOCK 32 2464 #define sc_x4_control_sc_seq_status_ACTIVATE_RX 16 2465 #define sc_x4_control_sc_seq_status_PMD_LOCK_FAIL 8 2466 #define sc_x4_control_sc_seq_status_DONE 4 2467 #define sc_x4_control_sc_seq_status_STOP 2 2468 #define sc_x4_control_sc_seq_status_BYPASS 1 2469 2470 /**************************************************************************** 2471 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 2472 */ 2473 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 2474 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 2475 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 2476 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 2477 2478 /**************************************************************************** 2479 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 2480 */ 2481 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 2482 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 2483 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 2484 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 2485 2486 /**************************************************************************** 2487 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 2488 */ 2489 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 2490 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 2491 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 2492 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 2493 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 2494 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 2495 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 2496 2497 /**************************************************************************** 2498 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 2499 */ 2500 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 2501 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 2502 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 2503 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 2504 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 2505 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 2506 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 2507 2508 /**************************************************************************** 2509 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 2510 */ 2511 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 2512 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 2513 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 2514 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 2515 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 2516 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 2517 2518 /**************************************************************************** 2519 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 2520 */ 2521 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 2522 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 2523 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 2524 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 2525 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 2526 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 2527 2528 /**************************************************************************** 2529 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 2530 */ 2531 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 2532 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 2533 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 2534 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 2535 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 2536 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 2537 2538 /**************************************************************************** 2539 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 2540 */ 2541 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 2542 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 2543 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 2544 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 2545 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 2546 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 2547 2548 /**************************************************************************** 2549 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 2550 */ 2551 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 2552 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 2553 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 2554 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 2555 2556 /**************************************************************************** 2557 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 2558 */ 2559 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 2560 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 2561 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 2562 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 2563 2564 /**************************************************************************** 2565 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 2566 */ 2567 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 2568 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 2569 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 2570 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 2571 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 2572 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 2573 2574 /**************************************************************************** 2575 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 2576 */ 2577 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 2578 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 2579 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 2580 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 2581 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 2582 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 2583 2584 /**************************************************************************** 2585 * Enums: sc_x4_final_config_status_IQP_Options 2586 */ 2587 #define sc_x4_final_config_status_IQP_Options_i50uA 0 2588 #define sc_x4_final_config_status_IQP_Options_i100uA 1 2589 #define sc_x4_final_config_status_IQP_Options_i150uA 2 2590 #define sc_x4_final_config_status_IQP_Options_i200uA 3 2591 #define sc_x4_final_config_status_IQP_Options_i250uA 4 2592 #define sc_x4_final_config_status_IQP_Options_i300uA 5 2593 #define sc_x4_final_config_status_IQP_Options_i350uA 6 2594 #define sc_x4_final_config_status_IQP_Options_i400uA 7 2595 #define sc_x4_final_config_status_IQP_Options_i450uA 8 2596 #define sc_x4_final_config_status_IQP_Options_i500uA 9 2597 #define sc_x4_final_config_status_IQP_Options_i550uA 10 2598 #define sc_x4_final_config_status_IQP_Options_i600uA 11 2599 #define sc_x4_final_config_status_IQP_Options_i650uA 12 2600 #define sc_x4_final_config_status_IQP_Options_i700uA 13 2601 #define sc_x4_final_config_status_IQP_Options_i750uA 14 2602 #define sc_x4_final_config_status_IQP_Options_i800uA 15 2603 2604 /**************************************************************************** 2605 * Enums: sc_x4_final_config_status_IDriver_Options 2606 */ 2607 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 2608 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 2609 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 2610 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 2611 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 2612 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 2613 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 2614 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 2615 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 2616 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 2617 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 2618 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 2619 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 2620 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 2621 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 2622 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 2623 2624 /**************************************************************************** 2625 * Enums: sc_x4_final_config_status_operationModes 2626 */ 2627 #define sc_x4_final_config_status_operationModes_XGXS 0 2628 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 2629 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 2630 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 2631 #define sc_x4_final_config_status_operationModes_PCI 7 2632 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 2633 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 2634 #define sc_x4_final_config_status_operationModes_PBypass 10 2635 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 2636 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 2637 #define sc_x4_final_config_status_operationModes_Clocks_off 15 2638 2639 /**************************************************************************** 2640 * Enums: sc_x4_final_config_status_synce_enum 2641 */ 2642 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 2643 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 2644 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 2645 2646 /**************************************************************************** 2647 * Enums: sc_x4_final_config_status_operationSpeeds 2648 */ 2649 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1_12p5 65 2650 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_12p5 64 2651 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_12p5 63 2652 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_12p5 62 2653 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_12p5 61 2654 #define sc_x4_final_config_status_operationSpeeds_SPEED_4G_X1_10 60 2655 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_X1_10 59 2656 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_X1_10 58 2657 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_X1_10 57 2658 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2659 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_10p3125 55 2660 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_10p3125 54 2661 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_10p3125 53 2662 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X4 50 2663 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_KR1 49 2664 #define sc_x4_final_config_status_operationSpeeds_SPEED_127G_X12 39 2665 #define sc_x4_final_config_status_operationSpeeds_SPEED_120G_X12 38 2666 #define sc_x4_final_config_status_operationSpeeds_SPEED_107G_X10 37 2667 #define sc_x4_final_config_status_operationSpeeds_SPEED_100G_CR10 36 2668 #define sc_x4_final_config_status_operationSpeeds_SPEED_42G_X4 35 2669 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_CR4 34 2670 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_KR4 33 2671 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X2 32 2672 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CR2 31 2673 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_KR2 30 2674 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p6_X1 29 2675 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KR1 28 2676 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_X4 27 2677 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X2 26 2678 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX2 25 2679 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_KR4 24 2680 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_X4 23 2681 #define sc_x4_final_config_status_operationSpeeds_SPEED_15p75G_X2 22 2682 #define sc_x4_final_config_status_operationSpeeds_SPEED_25p45G_X4 21 2683 #define sc_x4_final_config_status_operationSpeeds_SPEED_12p7G_X2 20 2684 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X4 19 2685 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X2 18 2686 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X4 17 2687 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X2 16 2688 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX2 15 2689 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX4 14 2690 #define sc_x4_final_config_status_operationSpeeds_SPEED_16G_X4 13 2691 #define sc_x4_final_config_status_operationSpeeds_SPEED_15G_X4 12 2692 #define sc_x4_final_config_status_operationSpeeds_SPEED_13G_X4 11 2693 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X4 10 2694 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KX4 9 2695 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX4 8 2696 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1 7 2697 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1 6 2698 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_KX1 5 2699 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_CX1 4 2700 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M 3 2701 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M 2 2702 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M 1 2703 2704 /**************************************************************************** 2705 * Enums: sc_x4_final_config_status_actualSpeeds 2706 */ 2707 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 2708 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 2709 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 2710 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 2711 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 2712 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 2713 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 2714 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 2715 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 2716 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 2717 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 2718 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 2719 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 2720 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 2721 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 2722 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 2723 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 2724 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 2725 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 2726 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 2727 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 2728 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 2729 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 2730 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2731 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 2732 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2733 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 2734 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 2735 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 2736 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 2737 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 2738 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 2739 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 2740 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 2741 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 2742 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2743 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 2744 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 2745 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 2746 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 2747 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 2748 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 2749 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 2750 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 2751 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 2752 2753 /**************************************************************************** 2754 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 2755 */ 2756 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 2757 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 2758 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 2759 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 2760 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 2761 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 2762 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2763 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 2764 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 2765 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 2766 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 2767 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 2768 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 2769 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 2770 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2771 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2772 2773 /**************************************************************************** 2774 * Enums: sc_x4_final_config_status_IndLaneModes 2775 */ 2776 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 2777 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 2778 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 2779 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 2780 2781 /**************************************************************************** 2782 * Enums: sc_x4_final_config_status_prbsSelect 2783 */ 2784 #define sc_x4_final_config_status_prbsSelect_prbs7 0 2785 #define sc_x4_final_config_status_prbsSelect_prbs15 1 2786 #define sc_x4_final_config_status_prbsSelect_prbs23 2 2787 #define sc_x4_final_config_status_prbsSelect_prbs31 3 2788 2789 /**************************************************************************** 2790 * Enums: sc_x4_final_config_status_vcoDivider 2791 */ 2792 #define sc_x4_final_config_status_vcoDivider_div32 0 2793 #define sc_x4_final_config_status_vcoDivider_div36 1 2794 #define sc_x4_final_config_status_vcoDivider_div40 2 2795 #define sc_x4_final_config_status_vcoDivider_div42 3 2796 #define sc_x4_final_config_status_vcoDivider_div48 4 2797 #define sc_x4_final_config_status_vcoDivider_div50 5 2798 #define sc_x4_final_config_status_vcoDivider_div52 6 2799 #define sc_x4_final_config_status_vcoDivider_div54 7 2800 #define sc_x4_final_config_status_vcoDivider_div60 8 2801 #define sc_x4_final_config_status_vcoDivider_div64 9 2802 #define sc_x4_final_config_status_vcoDivider_div66 10 2803 #define sc_x4_final_config_status_vcoDivider_div68 11 2804 #define sc_x4_final_config_status_vcoDivider_div70 12 2805 #define sc_x4_final_config_status_vcoDivider_div80 13 2806 #define sc_x4_final_config_status_vcoDivider_div92 14 2807 #define sc_x4_final_config_status_vcoDivider_div100 15 2808 2809 /**************************************************************************** 2810 * Enums: sc_x4_final_config_status_refClkSelect 2811 */ 2812 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 2813 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 2814 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 2815 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 2816 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 2817 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 2818 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 2819 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 2820 2821 /**************************************************************************** 2822 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 2823 */ 2824 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 2825 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 2826 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 2827 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 2828 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 2829 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 2830 2831 /**************************************************************************** 2832 * Enums: sc_x4_final_config_status_aerMMDportSelect 2833 */ 2834 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 2835 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 2836 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 2837 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 2838 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 2839 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 2840 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 2841 2842 /**************************************************************************** 2843 * Enums: sc_x4_final_config_status_firmwareModeSelect 2844 */ 2845 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 2846 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 2847 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 2848 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 2849 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 2850 2851 /**************************************************************************** 2852 * Enums: sc_x4_final_config_status_tempIdxSelect 2853 */ 2854 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 2855 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 2856 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 2857 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 2858 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 2859 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 2860 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 2861 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 2862 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 2863 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 2864 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 2865 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 2866 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 2867 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 2868 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 2869 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 2870 2871 /**************************************************************************** 2872 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 2873 */ 2874 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 2875 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 2876 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 2877 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 2878 2879 /**************************************************************************** 2880 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 2881 */ 2882 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 2883 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 2884 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 2885 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 2886 2887 /**************************************************************************** 2888 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 2889 */ 2890 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 2891 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 2892 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 2893 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 2894 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 2895 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 2896 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 2897 2898 /**************************************************************************** 2899 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 2900 */ 2901 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 2902 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 2903 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 2904 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 2905 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 2906 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 2907 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 2908 2909 /**************************************************************************** 2910 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 2911 */ 2912 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2913 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 2914 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 2915 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 2916 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 2917 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 2918 2919 /**************************************************************************** 2920 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 2921 */ 2922 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2923 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 2924 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 2925 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 2926 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 2927 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 2928 2929 /**************************************************************************** 2930 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 2931 */ 2932 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2933 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 2934 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 2935 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 2936 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 2937 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 2938 2939 /**************************************************************************** 2940 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 2941 */ 2942 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2943 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 2944 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 2945 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 2946 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 2947 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 2948 2949 /**************************************************************************** 2950 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 2951 */ 2952 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 2953 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 2954 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 2955 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 2956 2957 /**************************************************************************** 2958 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 2959 */ 2960 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 2961 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 2962 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 2963 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 2964 2965 /**************************************************************************** 2966 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 2967 */ 2968 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2969 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 2970 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 2971 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 2972 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 2973 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 2974 2975 /**************************************************************************** 2976 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 2977 */ 2978 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2979 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 2980 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 2981 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 2982 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 2983 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 2984 2985 /**************************************************************************** 2986 * Enums: tx_x4_credit_gen0_IQP_Options 2987 */ 2988 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 2989 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 2990 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 2991 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 2992 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 2993 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 2994 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 2995 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 2996 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 2997 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 2998 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 2999 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 3000 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 3001 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 3002 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 3003 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 3004 3005 /**************************************************************************** 3006 * Enums: tx_x4_credit_gen0_IDriver_Options 3007 */ 3008 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 3009 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 3010 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 3011 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 3012 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 3013 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 3014 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 3015 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 3016 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 3017 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 3018 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 3019 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 3020 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 3021 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 3022 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 3023 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 3024 3025 /**************************************************************************** 3026 * Enums: tx_x4_credit_gen0_operationModes 3027 */ 3028 #define tx_x4_credit_gen0_operationModes_XGXS 0 3029 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 3030 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 3031 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 3032 #define tx_x4_credit_gen0_operationModes_PCI 7 3033 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 3034 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 3035 #define tx_x4_credit_gen0_operationModes_PBypass 10 3036 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 3037 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 3038 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 3039 3040 /**************************************************************************** 3041 * Enums: tx_x4_credit_gen0_synce_enum 3042 */ 3043 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 3044 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 3045 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 3046 3047 /**************************************************************************** 3048 * Enums: tx_x4_credit_gen0_operationSpeeds 3049 */ 3050 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1_12p5 65 3051 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_12p5 64 3052 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_12p5 63 3053 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_12p5 62 3054 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_12p5 61 3055 #define tx_x4_credit_gen0_operationSpeeds_SPEED_4G_X1_10 60 3056 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_X1_10 59 3057 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_X1_10 58 3058 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_X1_10 57 3059 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3060 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_10p3125 55 3061 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_10p3125 54 3062 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_10p3125 53 3063 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X4 50 3064 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_KR1 49 3065 #define tx_x4_credit_gen0_operationSpeeds_SPEED_127G_X12 39 3066 #define tx_x4_credit_gen0_operationSpeeds_SPEED_120G_X12 38 3067 #define tx_x4_credit_gen0_operationSpeeds_SPEED_107G_X10 37 3068 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100G_CR10 36 3069 #define tx_x4_credit_gen0_operationSpeeds_SPEED_42G_X4 35 3070 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_CR4 34 3071 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_KR4 33 3072 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X2 32 3073 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CR2 31 3074 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_KR2 30 3075 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p6_X1 29 3076 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KR1 28 3077 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_X4 27 3078 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X2 26 3079 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX2 25 3080 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_KR4 24 3081 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_X4 23 3082 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15p75G_X2 22 3083 #define tx_x4_credit_gen0_operationSpeeds_SPEED_25p45G_X4 21 3084 #define tx_x4_credit_gen0_operationSpeeds_SPEED_12p7G_X2 20 3085 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X4 19 3086 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X2 18 3087 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X4 17 3088 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X2 16 3089 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX2 15 3090 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX4 14 3091 #define tx_x4_credit_gen0_operationSpeeds_SPEED_16G_X4 13 3092 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15G_X4 12 3093 #define tx_x4_credit_gen0_operationSpeeds_SPEED_13G_X4 11 3094 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X4 10 3095 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KX4 9 3096 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX4 8 3097 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1 7 3098 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1 6 3099 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_KX1 5 3100 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_CX1 4 3101 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M 3 3102 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M 2 3103 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M 1 3104 3105 /**************************************************************************** 3106 * Enums: tx_x4_credit_gen0_actualSpeeds 3107 */ 3108 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 3109 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 3110 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 3111 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 3112 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 3113 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 3114 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 3115 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 3116 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 3117 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 3118 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 3119 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 3120 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 3121 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 3122 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 3123 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 3124 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 3125 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 3126 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 3127 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 3128 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 3129 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 3130 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 3131 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3132 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 3133 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3134 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 3135 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 3136 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 3137 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 3138 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 3139 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 3140 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 3141 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 3142 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 3143 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3144 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 3145 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 3146 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 3147 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 3148 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 3149 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 3150 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 3151 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 3152 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 3153 3154 /**************************************************************************** 3155 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 3156 */ 3157 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3158 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3159 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3160 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3161 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3162 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3163 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3164 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3165 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3166 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3167 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3168 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3169 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3170 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3171 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3172 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3173 3174 /**************************************************************************** 3175 * Enums: tx_x4_credit_gen0_IndLaneModes 3176 */ 3177 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 3178 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 3179 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 3180 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 3181 3182 /**************************************************************************** 3183 * Enums: tx_x4_credit_gen0_prbsSelect 3184 */ 3185 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 3186 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 3187 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 3188 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 3189 3190 /**************************************************************************** 3191 * Enums: tx_x4_credit_gen0_vcoDivider 3192 */ 3193 #define tx_x4_credit_gen0_vcoDivider_div32 0 3194 #define tx_x4_credit_gen0_vcoDivider_div36 1 3195 #define tx_x4_credit_gen0_vcoDivider_div40 2 3196 #define tx_x4_credit_gen0_vcoDivider_div42 3 3197 #define tx_x4_credit_gen0_vcoDivider_div48 4 3198 #define tx_x4_credit_gen0_vcoDivider_div50 5 3199 #define tx_x4_credit_gen0_vcoDivider_div52 6 3200 #define tx_x4_credit_gen0_vcoDivider_div54 7 3201 #define tx_x4_credit_gen0_vcoDivider_div60 8 3202 #define tx_x4_credit_gen0_vcoDivider_div64 9 3203 #define tx_x4_credit_gen0_vcoDivider_div66 10 3204 #define tx_x4_credit_gen0_vcoDivider_div68 11 3205 #define tx_x4_credit_gen0_vcoDivider_div70 12 3206 #define tx_x4_credit_gen0_vcoDivider_div80 13 3207 #define tx_x4_credit_gen0_vcoDivider_div92 14 3208 #define tx_x4_credit_gen0_vcoDivider_div100 15 3209 3210 /**************************************************************************** 3211 * Enums: tx_x4_credit_gen0_refClkSelect 3212 */ 3213 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 3214 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 3215 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 3216 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 3217 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 3218 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 3219 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 3220 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 3221 3222 /**************************************************************************** 3223 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 3224 */ 3225 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 3226 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 3227 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 3228 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 3229 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 3230 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 3231 3232 /**************************************************************************** 3233 * Enums: tx_x4_credit_gen0_aerMMDportSelect 3234 */ 3235 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 3236 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 3237 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 3238 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 3239 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 3240 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 3241 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 3242 3243 /**************************************************************************** 3244 * Enums: tx_x4_credit_gen0_firmwareModeSelect 3245 */ 3246 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 3247 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 3248 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 3249 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 3250 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 3251 3252 /**************************************************************************** 3253 * Enums: tx_x4_credit_gen0_tempIdxSelect 3254 */ 3255 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 3256 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 3257 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 3258 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 3259 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 3260 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 3261 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 3262 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 3263 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 3264 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 3265 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 3266 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 3267 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 3268 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 3269 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 3270 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 3271 3272 /**************************************************************************** 3273 * End of RDB defined Enums *******************************************/ 3274 #endif /* __PCS_ENUMS_H__ */