qtce16_dispatch.c (7898B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 * 9 * 10 * DO NOT EDIT THIS FILE! 11 */ 12 13 #include <phymod/phymod.h> 14 #include <phymod/phymod_system.h> 15 #include <phymod/phymod.h> 16 #include <phymod/phymod_dispatch.h> 17 18 #ifdef PHYMOD_QTCE16_SUPPORT 19 20 #include <phymod/chip/qtce16.h> 21 22 #include <phymod/chip/merlin16.h> 23 24 __phymod__dispatch__t__ phymod_qtce16_driver = { 25 26 qtce16_core_identify, 27 qtce16_core_info_get, 28 qtce16_core_lane_map_set, 29 qtce16_core_lane_map_get, 30 NULL, /* phymod_core_reset_set */ 31 NULL, /* phymod_core_reset_get */ 32 qtce16_core_firmware_info_get, 33 qtce16_phy_firmware_core_config_set, 34 qtce16_phy_firmware_core_config_get, 35 qtce16_phy_firmware_lane_config_set, 36 qtce16_phy_firmware_lane_config_get, 37 NULL, /* phymod_core_pll_sequencer_restart */ 38 NULL, /* phymod_core_wait_event */ 39 NULL, /* phymod_phy_rx_restart */ 40 qtce16_phy_polarity_set, 41 qtce16_phy_polarity_get, 42 qtce16_phy_tx_set, 43 qtce16_phy_tx_get, 44 NULL, /* phymod_phy_training_tx_fir_post_set */ 45 merlin16_phy_media_type_tx_get, 46 NULL, /* phymod_phy_tx_override_set */ 47 NULL, /* phymod_phy_tx_override_get */ 48 NULL, /* phymod_phy_txpi_config_set */ 49 NULL, /* phymod_phy_txpi_config_get */ 50 NULL, /* phymod_phy_rx_set */ 51 NULL, /* phymod_phy_rx_get */ 52 NULL, /* phymod_phy_rx_adaptation_resume */ 53 NULL, /* phymod_phy_reset_set */ 54 NULL, /* phymod_phy_reset_get */ 55 qtce16_phy_power_set, 56 qtce16_phy_power_get, 57 NULL, /* phymod_phy_hg2_codec_control_set */ 58 NULL, /* phymod_phy_hg2_codec_control_get */ 59 qtce16_phy_tx_lane_control_set, 60 qtce16_phy_tx_lane_control_get, 61 qtce16_phy_rx_lane_control_set, 62 qtce16_phy_rx_lane_control_get, 63 NULL, /* phymod_phy_fec_enable_set */ 64 NULL, /* phymod_phy_fec_enable_get */ 65 NULL, /* phymod_phy_fec_override_set */ 66 NULL, /* phymod_phy_fec_override_get */ 67 NULL, /* phymod_phy_forced_speed_line_side_set */ 68 NULL, /* phymod_phy_forced_speed_line_side_get */ 69 NULL, /* phymod_phy_autoneg_line_side_set */ 70 NULL, /* phymod_phy_autoneg_line_side_get */ 71 NULL, /* phymod_phy_flow_control_mode_set */ 72 NULL, /* phymod_phy_flow_control_mode_get */ 73 NULL, /* phymod_phy_psm_cos_bmp_set */ 74 NULL, /* phymod_phy_psm_cos_bmp_get */ 75 NULL, /* phymod_phy_pfc_use_ip_cos_set */ 76 NULL, /* phymod_phy_pfc_use_ip_cos_get */ 77 NULL, /* phymod_phy_autoneg_oui_set */ 78 NULL, /* phymod_phy_autoneg_oui_get */ 79 qtce16_phy_eee_set, 80 qtce16_phy_eee_get, 81 qtce16_phy_interface_config_set, 82 qtce16_phy_interface_config_get, 83 qtce16_phy_cl72_set, 84 qtce16_phy_cl72_get, 85 qtce16_phy_cl72_status_get, 86 qtce16_phy_autoneg_ability_set, 87 qtce16_phy_autoneg_ability_get, 88 qtce16_phy_autoneg_remote_ability_get, 89 qtce16_phy_autoneg_set, 90 qtce16_phy_autoneg_get, 91 NULL, /* phymod_phy_autoneg_restart_set */ 92 qtce16_phy_autoneg_status_get, 93 qtce16_core_init, 94 qtce16_phy_pll_multiplier_get, 95 qtce16_phy_init, 96 qtce16_phy_loopback_set, 97 qtce16_phy_loopback_get, 98 qtce16_phy_rx_pmd_locked_get, 99 NULL, /* phymod_phy_rx_signal_detect_get */ 100 qtce16_phy_link_status_get, 101 NULL, /* phymod_phy_status_dump */ 102 NULL, /* phymod_phy_pcs_userspeed_set */ 103 NULL, /* phymod_phy_pcs_userspeed_get */ 104 qtce16_phy_reg_read, 105 qtce16_phy_reg_write, 106 NULL, /* phymod_phy_private_read */ 107 NULL, /* phymod_phy_private_write */ 108 NULL, /* phymod_phy_rev_id */ 109 NULL, /* phymod_phy_lane_cross_switch_map_set */ 110 NULL, /* phymod_phy_lane_cross_switch_map_get */ 111 NULL, /* phymod_phy_intr_enable_set */ 112 NULL, /* phymod_phy_intr_enable_get */ 113 NULL, /* phymod_phy_intr_status_get */ 114 NULL, /* phymod_phy_intr_status_clear */ 115 NULL, /* phymod_phy_i2c_read */ 116 NULL, /* phymod_phy_i2c_write */ 117 NULL, /* phymod_phy_gpio_config_set */ 118 NULL, /* phymod_phy_gpio_config_get */ 119 NULL, /* phymod_phy_gpio_pin_value_set */ 120 NULL, /* phymod_phy_gpio_pin_value_get */ 121 NULL, /* phymod_timesync_config_set */ 122 NULL, /* phymod_timesync_config_get */ 123 NULL, /* phymod_timesync_enable_set */ 124 NULL, /* phymod_timesync_enable_get */ 125 NULL, /* phymod_timesync_nco_addend_set */ 126 NULL, /* phymod_timesync_nco_addend_get */ 127 NULL, /* phymod_timesync_framesync_mode_set */ 128 NULL, /* phymod_timesync_framesync_mode_get */ 129 NULL, /* phymod_timesync_local_time_set */ 130 NULL, /* phymod_timesync_local_time_get */ 131 NULL, /* phymod_timesync_load_ctrl_set */ 132 NULL, /* phymod_timesync_load_ctrl_get */ 133 NULL, /* phymod_timesync_tx_timestamp_offset_set */ 134 NULL, /* phymod_timesync_tx_timestamp_offset_get */ 135 NULL, /* phymod_timesync_rx_timestamp_offset_set */ 136 NULL, /* phymod_timesync_rx_timestamp_offset_get */ 137 NULL, /* phymod_timesync_capture_timestamp_get */ 138 NULL, /* phymod_timesync_heartbeat_timestamp_get */ 139 NULL, /* phymod_timesync_do_sync */ 140 NULL, /* phymod_timesync_offset_set */ 141 NULL, /* phymod_timesync_adjust_set */ 142 NULL, /* phymod_edc_config_set */ 143 NULL, /* phymod_edc_config_get */ 144 NULL, /* phymod_phy_core_mode_set */ 145 NULL, /* phymod_phy_core_mode_get */ 146 NULL, /* phymod_failover_mode_set */ 147 NULL, /* phymod_failover_mode_get */ 148 NULL, /* phymod_port_init */ 149 NULL, /* phymod_phy_autoneg_try_enable */ 150 NULL, /* phymod_debug_ether */ 151 NULL, /* phymod_reset_interface */ 152 NULL, /* phymod_phy_short_chn_mode_enable_set */ 153 NULL, /* phymod_phy_short_chn_mode_enable_get */ 154 NULL, /* phymod_port_enable_set */ 155 NULL, /* phymod_port_enable_get */ 156 NULL, /* phymod_phy_eye_margin_est_get */ 157 NULL, /* phymod_phy_multi_get */ 158 NULL, /* phymod_phy_rescal_set */ 159 NULL, /* phymod_phy_rescal_get */ 160 NULL, /* phymod_phy_sw_an_control_status_get */ 161 NULL, /* phymod_phy_sw_an_base_page_exchange_handler */ 162 NULL, /* phymod_phy_sw_an_lp_page_rdy_handler */ 163 NULL, /* phymod_phy_sw_an_advert_set */ 164 NULL, /* phymod_phy_sw_autoneg_enable */ 165 NULL, /* phymod_phy_speed_config_set */ 166 NULL, /* phymod_phy_speed_config_get */ 167 NULL, /* phymod_phy_op_mode_get */ 168 NULL, /* phymod_phy_tx_taps_default_get */ 169 NULL, /* phymod_phy_lane_config_default_get */ 170 NULL, /* phymod_phy_firmware_load_info_get */ 171 NULL, /* phymod_phy_autoneg_advert_ability_set */ 172 NULL, /* phymod_phy_autoneg_advert_ability_get */ 173 NULL, /* phymod_phy_autoneg_remote_advert_ability_get */ 174 NULL, /* phymod_phy_bond_in_pwrdn_override */ 175 NULL, /* phymod_phy_tx_pam4_precoder_enable_set */ 176 NULL, /* phymod_phy_tx_pam4_precoder_enable_get */ 177 NULL, /* phymod_phy_tx_phase_lock_set */ 178 NULL, /* phymod_phy_pll_reconfig */ 179 NULL, /* phymod_phy_pll_pwrdn */ 180 NULL, /* phymod_phy_linkdown_transmit_set */ 181 NULL, /* phymod_phy_linkdown_transmit_get */ 182 qtce16_phy_synce_clk_ctrl_set, 183 qtce16_phy_synce_clk_ctrl_get, 184 NULL, /* phymod_phy_pcs_enable_set */ 185 qtce16_phy_rx_ppm_get, 186 NULL, /* phymod_phy_channel_loss_hint_set */ 187 NULL, /* phymod_phy_channel_loss_hint_get */ 188 NULL, /* phymod_intr_handler */ 189 NULL, /* phymod_timesync_tx_info_get */ 190 NULL, /* phymod_phy_master_set */ 191 NULL, /* phymod_phy_master_get */ 192 NULL, /* phymod_phy_pcs_lane_swap_adjust */ 193 NULL, /* phymod_phy_load_speed_id_entry */ 194 NULL, /* phymod_phy_pmd_override_enable_set */ 195 NULL, /* phymod_phy_duplex_set */ 196 NULL, /* phymod_phy_duplex_get */ 197 NULL, /* phymod_phy_pmd_info_init */ 198 NULL, /* phymod_phy_pll_powerdown_get */ 199 NULL, /* phymod_phy_pmd_info_size_get */ 200 NULL, /* phymod_phy_fec_bypass_indication_set */ 201 NULL, /* phymod_phy_fec_bypass_indication_get */ 202 }; 203 204 #endif /* PHYMOD_QTCE16_SUPPORT */