qtce_diagnostics.c (18635B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod_system.h> 11 #include <phymod/phymod_diagnostics.h> 12 #include <phymod/phymod_config.h> 13 #include <phymod/phymod_util.h> 14 #include <phymod/phymod_config.h> 15 #include "../../qtce/tier1/qmod_enum_defines.h" 16 #include "../../qtce/tier1/qmod.h" 17 #include "../../eagle/tier1/eagle_tsc_common.h" 18 #include "../../eagle/tier1/eagle_tsc_interface.h" 19 #include "../../eagle/tier1/eagle_cfg_seq.h" 20 #include "../../eagle/tier1/eagle_tsc_debug_functions.h" 21 22 /* extern err_code_t eagle_tsc_read_event_log( const phymod_access_t *pa, uint8_t *trace_mem,enum event_log_display_mode_enum display_mode); */ 23 24 #ifdef PHYMOD_QTCE_SUPPORT 25 26 /*phymod, internal enum mappings*/ 27 STATIC 28 int _qtce_prbs_poly_phymod_to_eagle(phymod_prbs_poly_t phymod_poly, enum srds_prbs_polynomial_enum *eagle_poly) 29 { 30 switch(phymod_poly){ 31 case phymodPrbsPoly7: 32 *eagle_poly = PRBS_7; 33 break; 34 case phymodPrbsPoly9: 35 *eagle_poly = PRBS_9; 36 break; 37 case phymodPrbsPoly11: 38 *eagle_poly = PRBS_11; 39 break; 40 case phymodPrbsPoly15: 41 *eagle_poly = PRBS_15; 42 break; 43 case phymodPrbsPoly23: 44 *eagle_poly = PRBS_23; 45 break; 46 case phymodPrbsPoly31: 47 *eagle_poly = PRBS_31; 48 break; 49 case phymodPrbsPoly58: 50 *eagle_poly = PRBS_58; 51 break; 52 default: 53 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("unsupported poly for qtce %u"), phymod_poly)); 54 } 55 return PHYMOD_E_NONE; 56 } 57 58 STATIC 59 int _qtce_prbs_poly_qtce_to_phymod(eagle_prbs_polynomial_type_t tsce_poly, phymod_prbs_poly_t *phymod_poly) 60 { 61 switch(tsce_poly){ 62 case EAGLE_PRBS_POLYNOMIAL_7: 63 *phymod_poly = phymodPrbsPoly7; 64 break; 65 case EAGLE_PRBS_POLYNOMIAL_9: 66 *phymod_poly = phymodPrbsPoly9; 67 break; 68 case EAGLE_PRBS_POLYNOMIAL_11: 69 *phymod_poly = phymodPrbsPoly11; 70 break; 71 case EAGLE_PRBS_POLYNOMIAL_15: 72 *phymod_poly = phymodPrbsPoly15; 73 break; 74 case EAGLE_PRBS_POLYNOMIAL_23: 75 *phymod_poly = phymodPrbsPoly23; 76 break; 77 case EAGLE_PRBS_POLYNOMIAL_31: 78 *phymod_poly = phymodPrbsPoly31; 79 break; 80 case EAGLE_PRBS_POLYNOMIAL_58: 81 *phymod_poly = phymodPrbsPoly58; 82 break; 83 default: 84 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("uknown poly %u"), tsce_poly)); 85 } 86 return PHYMOD_E_NONE; 87 } 88 89 #ifdef PHYMOD_TO_QTCE_OS_MODE_TRANS 90 STATIC 91 int _qtce_os_mode_phymod_to_qtce(phymod_osr_mode_t phymod_os_mode, qmod_os_mode_type *tsce_os_mode) 92 { 93 switch(phymod_os_mode){ 94 case phymodOversampleMode1: 95 *tsce_os_mode = QMOD_PMA_OS_MODE_1; 96 break; 97 case phymodOversampleMode2: 98 *tsce_os_mode = QMOD_PMA_OS_MODE_2; 99 break; 100 case phymodOversampleMode3: 101 *tsce_os_mode = QMOD_PMA_OS_MODE_3; 102 break; 103 case phymodOversampleMode3P3: 104 *tsce_os_mode = QMOD_PMA_OS_MODE_3_3; 105 break; 106 case phymodOversampleMode4: 107 *tsce_os_mode = QMOD_PMA_OS_MODE_4; 108 break; 109 case phymodOversampleMode5: 110 *tsce_os_mode = QMOD_PMA_OS_MODE_5; 111 break; 112 case phymodOversampleMode8: 113 *tsce_os_mode = QMOD_PMA_OS_MODE_8; 114 break; 115 case phymodOversampleMode8P25: 116 *tsce_os_mode = QMOD_PMA_OS_MODE_8_25; 117 break; 118 case phymodOversampleMode10: 119 *tsce_os_mode = QMOD_PMA_OS_MODE_10; 120 break; 121 default: 122 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("unsupported over sample mode for qtce %u"), phymod_os_mode)); 123 } 124 return PHYMOD_E_NONE; 125 } 126 #endif 127 128 STATIC 129 int _qtce_os_mode_qtce_to_phymod(qmod_os_mode_type tsce_os_mode, phymod_osr_mode_t *phymod_os_mode) 130 { 131 switch(tsce_os_mode){ 132 case QMOD_PMA_OS_MODE_1: 133 *phymod_os_mode = phymodOversampleMode1; 134 break; 135 case QMOD_PMA_OS_MODE_2: 136 *phymod_os_mode = phymodOversampleMode2; 137 break; 138 case QMOD_PMA_OS_MODE_3: 139 *phymod_os_mode = phymodOversampleMode3; 140 break; 141 case QMOD_PMA_OS_MODE_3_3: 142 *phymod_os_mode = phymodOversampleMode3P3; 143 break; 144 case QMOD_PMA_OS_MODE_4: 145 *phymod_os_mode = phymodOversampleMode4; 146 break; 147 case QMOD_PMA_OS_MODE_5: 148 *phymod_os_mode = phymodOversampleMode5; 149 break; 150 case QMOD_PMA_OS_MODE_8: 151 *phymod_os_mode = phymodOversampleMode8; 152 break; 153 case QMOD_PMA_OS_MODE_8_25: 154 *phymod_os_mode = phymodOversampleMode8P25; 155 break; 156 case QMOD_PMA_OS_MODE_10: 157 *phymod_os_mode = phymodOversampleMode10; 158 break; 159 default: 160 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("uknown os mode %u"), tsce_os_mode)); 161 } 162 return PHYMOD_E_NONE; 163 } 164 165 /*diagnotics functions*/ 166 167 int qtce_phy_rx_slicer_position_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_slicer_position_t* position) 168 { 169 170 171 172 /* Place your code here */ 173 174 175 return PHYMOD_E_NONE; 176 177 178 } 179 180 int qtce_phy_rx_slicer_position_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_slicer_position_t* position) 181 { 182 183 184 185 /* Place your code here */ 186 187 188 return PHYMOD_E_NONE; 189 190 191 } 192 193 194 int qtce_phy_rx_slicer_position_max_get(const phymod_phy_access_t* phy, uint32_t flags, const phymod_slicer_position_t* position_min, const phymod_slicer_position_t* position_max) 195 { 196 197 198 199 /* Place your code here */ 200 201 202 return PHYMOD_E_NONE; 203 204 205 } 206 207 int qtce_phy_prbs_config_set(const phymod_phy_access_t* phy, uint32_t flags , const phymod_prbs_t* prbs) 208 { 209 phymod_phy_access_t phy_copy; 210 int start_lane, num_lane, lane_id, sub_port; 211 int i = 0; 212 213 enum srds_prbs_polynomial_enum eagle_poly; 214 215 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 216 217 /*next figure out the lane num and start_lane based on the input*/ 218 PHYMOD_IF_ERR_RETURN 219 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 220 PHYMOD_IF_ERR_RETURN 221 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 222 start_lane = lane_id; 223 224 PHYMOD_IF_ERR_RETURN(_qtce_prbs_poly_phymod_to_eagle(prbs->poly, &eagle_poly)); 225 /*first check which direction */ 226 if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 227 for (i = 0; i < num_lane; i++) { 228 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 229 PHYMOD_IF_ERR_RETURN 230 (eagle_tsc_config_rx_prbs(&phy_copy.access, eagle_poly, PRBS_INITIAL_SEED_HYSTERESIS, prbs->invert)); 231 } 232 } else if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 233 for (i = 0; i < num_lane; i++) { 234 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 235 PHYMOD_IF_ERR_RETURN 236 (eagle_tsc_config_tx_prbs(&phy_copy.access, eagle_poly, prbs->invert)); 237 } 238 } else { 239 for (i = 0; i < num_lane; i++) { 240 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 241 PHYMOD_IF_ERR_RETURN 242 (eagle_tsc_config_rx_prbs(&phy_copy.access, eagle_poly, PRBS_INITIAL_SEED_HYSTERESIS, prbs->invert)); 243 PHYMOD_IF_ERR_RETURN 244 (eagle_tsc_config_tx_prbs(&phy_copy.access, eagle_poly, prbs->invert)); 245 } 246 } 247 return PHYMOD_E_NONE; 248 } 249 250 int qtce_phy_prbs_config_get(const phymod_phy_access_t* phy, uint32_t flags , phymod_prbs_t* prbs) 251 { 252 phymod_prbs_t config_tmp; 253 eagle_prbs_polynomial_type_t tsce_poly; 254 phymod_phy_access_t phy_copy; 255 int lane_id, sub_port; 256 257 PHYMOD_IF_ERR_RETURN 258 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 259 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 260 /*There is only single lane mode in QTCE*/ 261 phy_copy.access.lane_mask = 0x1 << lane_id; 262 263 if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 264 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_inv_data_get(&phy_copy.access, &config_tmp.invert)); 265 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_poly_get(&phy_copy.access, &tsce_poly)); 266 PHYMOD_IF_ERR_RETURN(_qtce_prbs_poly_qtce_to_phymod(tsce_poly, &config_tmp.poly)); 267 prbs->invert = config_tmp.invert; 268 prbs->poly = config_tmp.poly; 269 } else if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 270 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_inv_data_get(&phy_copy.access, &config_tmp.invert)); 271 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_poly_get(&phy_copy.access, &tsce_poly)); 272 PHYMOD_IF_ERR_RETURN(_qtce_prbs_poly_qtce_to_phymod(tsce_poly, &config_tmp.poly)); 273 prbs->invert = config_tmp.invert; 274 prbs->poly = config_tmp.poly; 275 } else { 276 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_inv_data_get(&phy_copy.access, &config_tmp.invert)); 277 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_poly_get(&phy_copy.access, &tsce_poly)); 278 PHYMOD_IF_ERR_RETURN(_qtce_prbs_poly_qtce_to_phymod(tsce_poly, &config_tmp.poly)); 279 prbs->invert = config_tmp.invert; 280 prbs->poly = config_tmp.poly; 281 } 282 return PHYMOD_E_NONE; 283 } 284 285 286 287 int qtce_phy_prbs_enable_set(const phymod_phy_access_t* phy, uint32_t flags , uint32_t enable) 288 { 289 phymod_phy_access_t phy_copy; 290 int start_lane, num_lane, lane_id, sub_port; 291 int i = 0; 292 293 294 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 295 296 /*next figure out the lane num and start_lane based on the input*/ 297 PHYMOD_IF_ERR_RETURN 298 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 299 PHYMOD_IF_ERR_RETURN 300 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 301 start_lane = lane_id; 302 303 if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 304 for (i = 0; i < num_lane; i++) { 305 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 306 PHYMOD_IF_ERR_RETURN(eagle_tsc_tx_prbs_en(&phy_copy.access, enable)); 307 } 308 } else if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 309 for (i = 0; i < num_lane; i++) { 310 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 311 PHYMOD_IF_ERR_RETURN(eagle_tsc_rx_prbs_en(&phy_copy.access, enable)); 312 } 313 } else { 314 for (i = 0; i < num_lane; i++) { 315 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 316 PHYMOD_IF_ERR_RETURN(eagle_tsc_tx_prbs_en(&phy_copy.access, enable)); 317 PHYMOD_IF_ERR_RETURN(eagle_tsc_rx_prbs_en(&phy_copy.access, enable)); 318 } 319 } 320 return PHYMOD_E_NONE; 321 } 322 323 int qtce_phy_prbs_enable_get(const phymod_phy_access_t* phy, uint32_t flags , uint32_t *enable) 324 { 325 uint32_t enable_tmp; 326 phymod_phy_access_t phy_copy; 327 int lane_id, sub_port; 328 329 PHYMOD_IF_ERR_RETURN 330 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 331 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 332 /*There is only single lane mode in QTCE*/ 333 phy_copy.access.lane_mask = 0x1 << lane_id; 334 335 if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 336 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_enable_get(&phy_copy.access, &enable_tmp)); 337 *enable = enable_tmp; 338 } else if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 339 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_enable_get(&phy_copy.access, &enable_tmp)); 340 *enable = enable_tmp; 341 } else { 342 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_enable_get(&phy_copy.access, &enable_tmp)); 343 *enable = enable_tmp; 344 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_enable_get(&phy_copy.access, &enable_tmp)); 345 *enable &= enable_tmp; 346 } 347 348 return PHYMOD_E_NONE; 349 } 350 351 352 int qtce_phy_prbs_status_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_prbs_status_t* prbs_status) 353 { 354 uint8_t status = 0; 355 uint32_t prbs_err_count = 0; 356 int i, start_lane, num_lane, lane_id, sub_port; 357 phymod_phy_access_t phy_copy; 358 359 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 360 /* next figure out the lane num and start_lane based on the input */ 361 PHYMOD_IF_ERR_RETURN 362 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 363 PHYMOD_IF_ERR_RETURN 364 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 365 start_lane = lane_id; 366 367 prbs_status->prbs_lock = 1; 368 prbs_status->error_count = 0; 369 prbs_status->prbs_lock_loss = 0; 370 371 for (i = 0; i < num_lane; i++) { 372 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 373 PHYMOD_IF_ERR_RETURN(eagle_tsc_prbs_chk_lock_state(&phy_copy.access, &status)); 374 if (status) { 375 /*next check the lost of lock and error count */ 376 status = 0; 377 PHYMOD_IF_ERR_RETURN 378 (eagle_tsc_prbs_err_count_state(&phy_copy.access, &prbs_err_count, &status)); 379 PHYMOD_DEBUG_VERBOSE((" Lane :: %d PRBS Error count :: %d lock_loss=%0d\n", i, prbs_err_count, status)); 380 if (status) { 381 /*temp lost of lock */ 382 prbs_status->prbs_lock_loss = 1; 383 } else { 384 prbs_status->error_count += prbs_err_count; 385 } 386 } else { 387 PHYMOD_DEBUG_VERBOSE((" Lane :: %d PRBS not locked\n", i )); 388 prbs_status->prbs_lock = 0; 389 return PHYMOD_E_NONE; 390 } 391 } 392 return PHYMOD_E_NONE; 393 } 394 395 396 int qtce_phy_pattern_config_set(const phymod_phy_access_t* phy, const phymod_pattern_t* pattern, uint32_t* mode_sel) 397 { 398 return PHYMOD_E_NONE; 399 } 400 401 int qtce_phy_pattern_config_get(const phymod_phy_access_t* phy, phymod_pattern_t* pattern) 402 { 403 /* Place your code here */ 404 405 406 return PHYMOD_E_NONE; 407 } 408 409 int qtce_phy_pattern_enable_set(const phymod_phy_access_t* phy, uint32_t enable, uint32_t mode_sel) 410 { 411 return PHYMOD_E_NONE; 412 } 413 414 int qtce_phy_pattern_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 415 { 416 417 418 419 /* Place your code here */ 420 421 422 return PHYMOD_E_NONE; 423 } 424 425 int qtce_core_diagnostics_get(const phymod_core_access_t* core, phymod_core_diagnostics_t* diag) 426 { 427 428 429 /* Place your code here */ 430 431 432 return PHYMOD_E_NONE; 433 434 } 435 436 int qtce_phy_diagnostics_get(const phymod_phy_access_t* phy, phymod_phy_diagnostics_t* diag) 437 { 438 phymod_phy_access_t phy_copy; 439 int lane_id, sub_port; 440 qmod_os_mode_type os_mode = QMOD_PMA_OS_MODE_1; 441 phymod_diag_eyescan_t_init(&diag->eyescan); 442 phymod_diag_slicer_offset_t_init(&diag->slicer_offset); 443 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 444 PHYMOD_IF_ERR_RETURN 445 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 446 /*There is only single lane mode in QTCE*/ 447 phy_copy.access.lane_mask = 0x1 << lane_id; 448 449 PHYMOD_IF_ERR_RETURN(qmod_pmd_lock_get(&phy_copy.access, &diag->rx_lock)); 450 451 PHYMOD_IF_ERR_RETURN(_qtce_os_mode_qtce_to_phymod(os_mode, &diag->osr_mode)); 452 453 return PHYMOD_E_NONE; 454 455 } 456 457 int qtce_phy_pmd_info_dump(const phymod_phy_access_t* phy, const char *type) 458 { 459 int start_lane, num_lane, lane_id, sub_port; 460 phymod_phy_access_t phy_copy; 461 int i = 0; 462 uint32_t cmd_type; 463 uint8_t trace_mem[768]; 464 int is_in_reset = 0; 465 466 if (!type) { 467 cmd_type = (uint32_t)QMOD_DIAG_DSC; 468 } else if (!PHYMOD_STRCMP(type, "ber")) { 469 cmd_type = (uint32_t)QMOD_DIAG_BER; 470 } else if (!PHYMOD_STRCMP(type, "config")) { 471 cmd_type = (uint32_t)QMOD_DIAG_CFG; 472 } else if (!PHYMOD_STRCMP(type, "CL72") || !PHYMOD_STRCMP(type, "cl72")) { 473 cmd_type = (uint32_t)QMOD_DIAG_CL72; 474 } else if (!PHYMOD_STRCMP(type, "debug")) { 475 cmd_type = (uint32_t)QMOD_DIAG_DEBUG; 476 } else if (!PHYMOD_STRCMP(type, "state")) { 477 cmd_type = (uint32_t)QMOD_DIAG_STATE; 478 } else { 479 cmd_type = (uint32_t)QMOD_DIAG_DSC; 480 } 481 482 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 483 484 /*next figure out the lane num and start_lane based on the input*/ 485 PHYMOD_IF_ERR_RETURN 486 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 487 PHYMOD_IF_ERR_RETURN 488 (qmod_lane_info(&phy->access, &lane_id, &sub_port)); 489 start_lane = lane_id; 490 491 if (cmd_type == QMOD_DIAG_DSC) { 492 PHYMOD_IF_ERR_RETURN 493 (eagle_tsc_display_core_state(&phy_copy.access)); 494 PHYMOD_IF_ERR_RETURN 495 (eagle_tsc_display_lane_state_hdr(&phy_copy.access)); 496 for (i = 0; i < 4; i++) { 497 phy_copy.access.lane_mask = 0x1 << i ; 498 PHYMOD_IF_ERR_RETURN 499 (qmod_pmd_x4_reset_get(&phy_copy.access, &is_in_reset)); 500 if (is_in_reset) { 501 PHYMOD_DIAG_OUT((" - skip lane=%0d\n", i)); 502 continue; 503 } 504 PHYMOD_IF_ERR_RETURN 505 (eagle_tsc_display_lane_state(&phy_copy.access)); 506 } 507 } else { 508 for (i = 0; i < num_lane; i++) { 509 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 510 511 switch (cmd_type) { 512 case QMOD_DIAG_CFG: 513 PHYMOD_IF_ERR_RETURN 514 (eagle_tsc_display_core_config(&phy_copy.access)); 515 PHYMOD_IF_ERR_RETURN 516 (eagle_tsc_display_lane_config(&phy_copy.access)); 517 break; 518 519 case QMOD_DIAG_CL72: 520 PHYMOD_IF_ERR_RETURN 521 (eagle_tsc_display_cl72_status(&phy_copy.access)); 522 break; 523 524 case QMOD_DIAG_DEBUG: 525 PHYMOD_IF_ERR_RETURN 526 (eagle_tsc_display_lane_debug_status(&phy_copy.access)); 527 break; 528 529 case QMOD_DIAG_BER: 530 break; 531 532 case QMOD_DIAG_STATE: 533 default: 534 PHYMOD_IF_ERR_RETURN 535 (eagle_tsc_display_core_state_hdr(&phy_copy.access)); 536 PHYMOD_IF_ERR_RETURN 537 (eagle_tsc_display_core_state_line(&phy_copy.access)); 538 PHYMOD_IF_ERR_RETURN 539 (eagle_tsc_display_core_state(&phy_copy.access)); 540 PHYMOD_IF_ERR_RETURN 541 (eagle_tsc_display_lane_state_hdr(&phy_copy.access)); 542 PHYMOD_IF_ERR_RETURN 543 (eagle_tsc_display_lane_state(&phy_copy.access)); 544 PHYMOD_IF_ERR_RETURN 545 (eagle_tsc_read_event_log((&phy_copy.access), trace_mem, 2)); 546 break; 547 } 548 } 549 } 550 return PHYMOD_E_NONE; 551 } 552 553 int qtce_phy_pcs_info_dump(const phymod_phy_access_t* phy, const char* type) 554 { 555 phymod_phy_access_t phy_copy; 556 557 PHYMOD_MEMCPY (&phy_copy, phy, sizeof(phy_copy)); 558 PHYMOD_IF_ERR_RETURN (qmod_diag_disp(&phy_copy.access, type)); 559 560 return PHYMOD_E_NONE; 561 } 562 563 #endif /* PHYMOD_QTCE_SUPPORT */