qmod_enum_defines.h (52620B)
1 /*---------------------------------------------------------------------- 2 * : qmod_enum_defines.h, 3 * : n * 4 * Broadcom Corporation 5 * Proprietary and Confidential information 6 * All rights reserved 7 * This source file is the property of Broadcom Corporation, and 8 * may not be copied or distributed in any isomorphic form without the 9 * prior written consent of Broadcom Corporation. 10 *--------------------------------------------------------------------- 11 *--------------------------------------------------------------------- 12 ############### THIS FILE IS AUTOMATICALLY GENERATED. ############### 13 ############### DO !! NOT !! MANUALLY EDIT THIS FILE. ############### 14 *--------------------------------------------------------------------- 15 * Description: This file contains enums, elems, and doxygen comments 16 * needed for SerDes Configuration programs. 17 *--------------------------------------------------------------------- 18 * CVS INFORMATION: 19 * Please see inc/enum_desc.txt for CVS information. 20 *---------------------------------------------------------------------- 21 */ 22 /* 23 * 24 h#8 25 h#8 This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 26 h#8 27 h#8 Copyright 2007-2019 Broadcom Inc. All rights reserved. 28 h#8 Broadcom Proprietary and Confidential. All rights reserved.$ 29 */ 30 /* This file is automatically generated. Do not modify it. Modify the 31 * inc/enum_desc.txt to change enums, elems, or comments. For issues about 32 * the process that creates this file contact the qmod development team. 33 */ 34 35 #ifndef _TSCMOD_ENUM_DEFINES_H 36 #define _TSCMOD_ENUM_DEFINES_H 37 38 /*! \enum qmod_core_select 39 40 qmod_core_select selects for programming, any combination of 3 core of the PHY. 41 This is only applicable to the 12x10 version of the TSCE core. 42 A '1' in the latter part of the enum selects the core. 43 44 45 */ 46 47 typedef enum { 48 QMOD_CORE_0_0_1 = 0 , /*!< Core number 0 selected */ 49 QMOD_CORE_0_1_0 , /*!< Core number 1 selected */ 50 QMOD_CORE_1_0_0 , /*!< Core number 2 selected */ 51 QMOD_CORE_0_1_1 , /*!< Core number 0 & 1 selected */ 52 QMOD_CORE_1_0_1 , /*!< Core number 0 & 2 selected */ 53 QMOD_CORE_1_1_1 , /*!< Core number 0,1,& 2 selected */ 54 QMOD_CORE_ILLEGAL /*!< Illegal (programmatic boundary) */ 55 } qmod_core_select; 56 57 /*! \def CNT_qmod_core_select Types of enum qmod_core_select */ 58 #define CNT_qmod_core_select 7 59 60 /*! 61 \brief 62 This array returns the string version of the enum #qmod_core_select when 63 indexed by the enum var. 64 65 */ 66 extern char* e2s_qmod_core_select [CNT_qmod_core_select]; 67 /*! 68 \brief 69 This array associates the enum #qmod_core_select enum with a bit mask. 70 The index is the #qmod_core_select enum value. The value for each entry is 71 interpreted as follows. If bit [n] is 1, then core [n] is addressed; if bit [n] 72 is 0, then core [n] is addressed. 73 74 */ 75 extern int e2n_qmod_core_select [CNT_qmod_core_select]; 76 /*! \enum qmod_lane_select 77 78 qmod_lane_select selects for programming, any combination of 4 lanes of PHY. 79 A '1' in the latter part of the enum name selects the lane. Other parameters in 80 the #qmod_st will decide what to do with the selected lane(s). In most cases 81 we enable/disable a feature on the selected lanes. 82 83 If lane_select is set to QMOD_LANE_BCST for writes we broadcast to all lanes. 84 You cannot read in broadcast mode. 85 86 87 */ 88 89 typedef enum { 90 QMOD_LANE_0_0_0_1 = 0 , /*!< lane number 0 selected */ 91 QMOD_LANE_0_0_1_0 , /*!< lane number 1 selected */ 92 QMOD_LANE_0_0_1_1 , /*!< lane numbers 0,1 selected */ 93 QMOD_LANE_0_1_0_0 , /*!< lane number 2 selected */ 94 QMOD_LANE_0_1_0_1 , /*!< lane numbers 2,0 selected */ 95 QMOD_LANE_0_1_1_0 , /*!< lane numbers 2,1 selected */ 96 QMOD_LANE_0_1_1_1 , /*!< lane numbers 2,1,0 selected */ 97 QMOD_LANE_1_0_0_0 , /*!< lane number 3 selected */ 98 QMOD_LANE_1_0_0_1 , /*!< lane numbers 3,0 selected */ 99 QMOD_LANE_1_0_1_0 , /*!< lane numbers 3,1 selected */ 100 QMOD_LANE_1_0_1_1 , /*!< lane numbers 3,1,0 selected */ 101 QMOD_LANE_1_1_0_0 , /*!< lane numbers 3,2 selected */ 102 QMOD_LANE_1_1_0_1 , /*!< lane numbers 3,2,0 selected */ 103 QMOD_LANE_1_1_1_0 , /*!< lane numbers 3,2,1 selected */ 104 QMOD_LANE_1_1_1_1 , /*!< lane numbers 3,2,1,0 selected */ 105 QMOD_LANE_BCST , /*!< lane numbers 3,2,1,0 BCST */ 106 QMOD_LANE_ILLEGAL /*!< Illegal (programmatic boundary) */ 107 } qmod_lane_select; 108 109 /*! \def CNT_qmod_lane_select Types of enum qmod_lane_select */ 110 #define CNT_qmod_lane_select 17 111 112 /*! 113 \brief 114 This array returns the string version of the enum #qmod_lane_select when 115 indexed by the enum var. 116 117 */ 118 extern char* e2s_qmod_lane_select [CNT_qmod_lane_select]; 119 /*! 120 \brief 121 This array associates the enum #qmod_lane_select enum with a bit mask. 122 The index is the #qmod_lane_select enum value. The value for each entry is 123 interpreted as follows. If bit [n] is 1, then lane [n] is enabled; if bit [n] 124 is 0, then lane [n] is disabled. By enabled, we mean that such-and-such 125 function is to be called for a lane; by disabled, we mean that such-and-such 126 function is not to be called for a lane. So a value of 0xF indicates that all 127 lanes or enabled, while 0x5 indicates that only lanes 0 and 2 are enabled. 128 129 */ 130 extern int e2n_qmod_lane_select [CNT_qmod_lane_select]; 131 /*! \enum qmod_spd_intfc_type 132 133 All legal speed-interface combination are encapsulated in this enum 134 135 There are several speed and interface combinations allowed for a logical PHY 136 port. Names and speeds are self explanatory. 137 138 Speed and interface selection is combined because we don't want the speeds 139 to be incompatible with interface. 140 141 */ 142 143 typedef enum { 144 QMOD_SPD_ZERO = 0 , /*!< Illegal value (enum boundary) */ 145 QMOD_SPD_10_X1_SGMII , /*!< 10Mb SGMII (serial) */ 146 QMOD_SPD_100_X1_SGMII , /*!< 100Mb SGMII (serial) */ 147 QMOD_SPD_1000_X1_SGMII , /*!< 1Gb SGMII (serial) */ 148 QMOD_SPD_2500_X1 , /*!< 2.5Gb based on 1000BASE-X */ 149 QMOD_SPD_10_SGMII , /*!< 10Mb SGMII (serial) */ 150 QMOD_SPD_100_SGMII , /*!< 100Mb SGMII (serial) */ 151 QMOD_SPD_1000_SGMII , /*!< 1Gb SGMII (serial) */ 152 QMOD_SPD_2500 , /*!< 2.5Gb based on 1000BASE-X */ 153 QMOD_SPD_5000 , /*!< 5Gb CL36 */ 154 QMOD_SPD_1000_XFI , /*!< 1Gb */ 155 QMOD_SPD_5000_XFI , /*!< 5Gb CL49 */ 156 QMOD_SPD_10000_XFI , /*!< 10Gb serial XFI */ 157 QMOD_SPD_10600_XFI_HG , /*!< 10.5Gb serial XFI (HgSOLO) */ 158 QMOD_SPD_10000_HI , /*!< 10Gb XAUI HiG */ 159 QMOD_SPD_10000 , /*!< 10Gb XAUI */ 160 QMOD_SPD_12000_HI , /*!< 12Gb XAUI HiG */ 161 QMOD_SPD_13000 , /*!< 13Gb XAUI */ 162 QMOD_SPD_15000 , /*!< 15Gb XAUI */ 163 QMOD_SPD_16000 , /*!< 16Gb XAUI */ 164 QMOD_SPD_20000 , /*!< 20Gb XAUI */ 165 QMOD_SPD_20000_SCR , /*!< 20Gb XAUI scrambled */ 166 QMOD_SPD_21000 , /*!< 21Gb XAUI */ 167 QMOD_SPD_25455 , /*!< 25Gb XAUI 64/66 codec */ 168 QMOD_SPD_31500 , /*!< 31.5Gb quad lane XAUI */ 169 QMOD_SPD_31500_MLD , /*!< 31.5Gb quad lane MLD */ 170 QMOD_SPD_40G_X4 , /*!< 40Gb quad lane XAUI */ 171 QMOD_SPD_42G_X4 , /*!< 40Gb quad lane XAUI HiG */ 172 QMOD_SPD_40G_XLAUI , /*!< 40Gb quad lane MLD */ 173 QMOD_SPD_42G_XLAUI , /*!< 42Gb quad lane MLD */ 174 QMOD_SPD_10000_X2 , /*!< 10Gb dual lane */ 175 QMOD_SPD_10000_HI_DXGXS , /*!< 10Gb dual lane XGXS HiG */ 176 QMOD_SPD_10000_DXGXS , /*!< 10Gb dual lane XGXS */ 177 QMOD_SPD_10000_HI_DXGXS_SCR , /*!< 10Gb dual lane,scrambled,HiG */ 178 QMOD_SPD_10000_DXGXS_SCR , /*!< 10Gb dual lane scrambled */ 179 QMOD_SPD_10500_HI , /*!< 10.5Gb XAUI lane XGXS HiG */ 180 QMOD_SPD_10500_HI_DXGXS , /*!< 10.5Gb dual lane XGXS HiG */ 181 QMOD_SPD_12773_HI_DXGXS , /*!< 12.73Gb dual lane XGXS HiG */ 182 QMOD_SPD_12773_DXGXS , /*!< 12.73Gb dual lane XGXS */ 183 QMOD_SPD_15750_HI_DXGXS , /*!< 15.75Gb scrambled dual lane HiG */ 184 QMOD_SPD_20G_MLD_DXGXS , /*!< 20Gb dual lane MLD */ 185 QMOD_SPD_21G_HI_MLD_DXGXS , /*!< 20Gb dual lane HiG MLD */ 186 QMOD_SPD_20G_DXGXS , /*!< 20Gb dual lane BRCM */ 187 QMOD_SPD_21G_HI_DXGXS , /*!< 21.2Gb dual HiG(20+plldiv=70) */ 188 QMOD_SPD_100G_CR10 , /*!< 100G */ 189 QMOD_SPD_107G_HG_CR10 , /*!< 107G */ 190 QMOD_SPD_120G_CR12 , /*!< 120G */ 191 QMOD_SPD_127G_HG_CR12 , /*!< 127G */ 192 QMOD_SPD_4000 , /*!< 4G QSGMII */ 193 QMOD_SPD_10_X1_10 , /*!< 10Mb SGMII (serial) vco 10 */ 194 QMOD_SPD_100_X1_10 , /*!< 100Mb SGMII (serial) vco 10 */ 195 QMOD_SPD_1000_X1_10 , /*!< 1Gb SGMII (serial) vco 10 */ 196 QMOD_SPD_10_X1_12P5 , /*!< 10Mb SGMII (serial) vco 12p5 */ 197 QMOD_SPD_100_X1_12P5 , /*!< 100Mb SGMII (serial) vco 12p5 */ 198 QMOD_SPD_1000_X1_12P5 , /*!< 1Gb SGMII (serial) vco 12p5 */ 199 QMOD_SPD_2500_X1_12P5 , /*!< 2.5Gb SGMII vco 12p5 */ 200 QMOD_SPD_ILLEGAL /*!< Illegal value (enum boundary) */ 201 } qmod_spd_intfc_type; 202 203 /*! \def CNT_qmod_spd_intfc_type Types of enum qmod_spd_intfc_type */ 204 #define CNT_qmod_spd_intfc_type 57 205 206 /*! 207 \brief 208 This array returns the string version of the enum #qmod_lane_select when 209 indexed by the enum var. 210 211 */ 212 extern char* e2s_qmod_spd_intfc_type [CNT_qmod_spd_intfc_type]; 213 /*! 214 \brief 215 This array associates the enum #qmod_lane_select enum with a bit mask. 216 The index is the #qmod_lane_select enum value. The value for each entry is 217 interpreted as follows. If bit [n] is 1, then lane [n] is enabled; if bit [n] 218 is 0, then lane [n] is disabled. By enabled, we mean that such-and-such 219 function is to be called for a lane; by disabled, we mean that such-and-such 220 function is not to be called for a lane. So a value of 0xF indicates that all 221 lanes or enabled, while 0x5 indicates that only lanes 0 and 2 are enabled. 222 223 */ 224 extern int e2n_qmod_spd_intfc_type [CNT_qmod_spd_intfc_type]; 225 /*! \enum qmod_regacc_type 226 227 Types of MDIO to access PHY registers. IEEE clause 22 and clause 45 are 228 supported. The 8 bit parallel TOTSC bus can be used. We may use 229 230 */ 231 232 typedef enum { 233 QMOD_REGACC_CL22 = 0 , /*!< IEEE clause 22 based MDIO (for PMD only) */ 234 QMOD_REGACC_CL45 , /*!< IEEE clause 45 based MDIO (for PMD only) */ 235 QMOD_REGACC_TOTSC , /*!< Mission Mode. */ 236 QMOD_REGACC_SBUS_FD , /*!< Probably used in PM testbenches. */ 237 QMOD_REGACC_SBUS_BD , /*!< Probably used in PM testbenches. */ 238 QMOD_REGACC_ILLEGAL /*!< Illegal value (enum boundary) */ 239 } qmod_regacc_type; 240 241 /*! \def CNT_qmod_regacc_type Types of enum qmod_regacc_type */ 242 #define CNT_qmod_regacc_type 6 243 244 /*! 245 \brief 246 This array returns the string version of the enum #qmod_regacc_type when indexed 247 by the enum var. 248 249 */ 250 extern char* e2s_qmod_regacc_type [CNT_qmod_regacc_type]; 251 /*! \enum qmod_port_type 252 253 This is the port mode type enumeration. 254 255 WC can be configured in combo mode (i.e. entire WC is a single port) or 256 independent mode (i.e. WC has more than one port (2, 3, or 4) that are 257 controlled individually. 258 259 */ 260 261 typedef enum { 262 QMOD_SINGLE_PORT = 0 , /*!< single port mode: 4 channels as one logical port */ 263 QMOD_MULTI_PORT , /*!< Each channel is one logical port */ 264 QMOD_DXGXS , /*!< Each paired channel(0-1, 2-3) is one logical port */ 265 QMOD_TRI1_PORT , /*!< 3 ports, one of them paird as follows (0,1,2-3) */ 266 QMOD_TRI2_PORT , /*!< 3 ports, one of them paird as follows (0-1,2,3) */ 267 QMOD_PORT_MODE_ILLEGAL /*!< Illegal value (enum boundary) */ 268 } qmod_port_type; 269 270 /*! \def CNT_qmod_port_type Types of enum qmod_port_type */ 271 #define CNT_qmod_port_type 6 272 273 /*! 274 \brief 275 This array returns the string version of the enum #qmod_port_type when indexed 276 by the enum var. 277 278 */ 279 extern char* e2s_qmod_port_type [CNT_qmod_port_type]; 280 /*! \enum qmod_diag_type 281 282 qmod_diag_type enumerates categories of diagnostic data. 283 has many intermediate stages between down and up. This enum is work in progress 284 285 286 <table cellspacing=0> 287 <tr><td colspan=3><B>'per_lane_control' bit-mappings</B></td></tr> 288 289 <tr><td><B>Type</B></td><td><B>Description</B></td><td><B>Scope</B></td></tr> 290 291 <tr><td>General</td> 292 <td> Combo/independent, Device and Revision Id, VCO settings, Firmware state 293 and version, active/passive lanes, MDIO type. PLL info, Oversampling Info</td> 294 <td>Device</td></tr> 295 296 <tr><td>Link</td> 297 <td> Speeds, oversampling, interface, forced/Autoneg, link status, sync 298 status, RX sequencer on/off </td> 299 <td>Lane</td></tr> 300 301 <tr><td>Autoneg</td> 302 <td> Local and remote advertisement, link status, cl73/37/BAM info </td> 303 <td>Lane</td></tr> 304 305 <tr><td>Internal Traffic</td> 306 <td> PRBS type, CJPat Type, Prog_data value, Any associated recorded errors, 307 and misc. info (IPG etc.)</td> 308 <td>Lane </td></tr> 309 310 <tr> 311 <td>DFE</td> 312 <td>Equalization info, Tap settings. (pre/post/overrides), peaking filter values </td> 313 <td>Lane</td></tr> 314 315 <tr><td>IEEE info</td> 316 <td>Clause 72, FEC</td> 317 <td>Lane</td></tr> 318 319 <tr><td>Topology</td> 320 <td>Looping info (Gloop/rloop), lane swapping, polarity swap info</td> 321 <td>Device</td></tr> 322 323 <tr><td>EEE</td> 324 <td>EEE full, passthru modes, some window values?</td> 325 <td>Lane</td></tr> 326 327 <tr><td>Eye Margin</td> 328 <td>Eye margin measurement (readout only)</td> 329 <td>Lane</td></tr> 330 331 <tr><td>All</td> 332 <td>All of the above. Except eye margin.</td> 333 <td>Device</td></tr> 334 335 </table> 336 337 338 */ 339 340 typedef enum { 341 QMOD_DIAG_GENERAL = 0x00000001 , /*!< General device wide information. */ 342 QMOD_DIAG_TOPOLOGY = 0x00000002 , /*!< Loopbacks etc. */ 343 QMOD_DIAG_LINK = 0x00000004 , /*!< Link specific info. */ 344 QMOD_DIAG_SPEED = 0x00000008 , /*!< sub-category of QMOD_DIAG_LINK(for SDK) */ 345 QMOD_DIAG_ANEG = 0x00000010 , /*!< Autoneg specific info. */ 346 QMOD_DIAG_TFC = 0x00000020 , /*!< State of tx/rx internal tfc */ 347 QMOD_DIAG_AN_TIMERS = 0x00000040 , /*!< AN timers */ 348 QMOD_DIAG_STATE = 0x00000080 , /*!< Debug state registers */ 349 QMOD_DIAG_DEBUG = 0x00000100 , /*!< Debug */ 350 QMOD_DIAG_IEEE = 0x00000200 , /*!< IEEE related info */ 351 QMOD_DIAG_EEE = 0x00000400 , /*!< EEE */ 352 QMOD_SERDES_DIAG = 0x00008000 , /*!< PMD Triage */ 353 QMOD_DIAG_BER = 0x00000800 , /*!< BER - PMD bit error rate */ 354 QMOD_DIAG_CFG = 0x00001000 , /*!< CFG - PMD Lane/Core Config */ 355 QMOD_DIAG_CL72 = 0x00002000 , /*!< CL72 - Status */ 356 QMOD_DIAG_DSC = 0x00004000 , /*!< CL72 - Status */ 357 QMOD_DIAG_ALL = 0x0000ffff , /*!< Everything but eye margin */ 358 QMOD_DIAG_ILLEGAL = 0x00000000 /*!< Illegal value. programmatic boundary. */ 359 } qmod_diag_type; 360 361 /*! \def CNT_qmod_diag_type Types of enum qmod_diag_type */ 362 #define CNT_qmod_diag_type 14 363 364 /*! 365 \brief 366 This array returns the string version of the enum #qmod_port_type when indexed 367 by the enum var. 368 369 */ 370 extern char* e2s_qmod_diag_type [CNT_qmod_diag_type]; 371 /*! \enum qmod_pmd_diag_type 372 373 qmod_pmd_diag_type enumerates categories of pmd diagnostic data. 374 has many intermediate stages between down and up. This enum is work in progress 375 376 */ 377 378 typedef enum { 379 QMOD_SERDES_DIAG_CORE_CONFIG = 0x00000001 , /*!< SERDES DIAG */ 380 QMOD_SERDES_DIAG_CORE_STATE = 0x00000002 , /*!< SERDES DIAG */ 381 QMOD_SERDES_DIAG_LANE_CONFIG = 0x00000004 , /*!< SERDES DIAG */ 382 QMOD_SERDES_DIAG_LANE_DEBUG_STATUS = 0x00000008 , /*!< SERDES DIAG */ 383 QMOD_SERDES_DIAG_LANE_STATE = 0x00000010 , /*!< SERDES DIAG */ 384 QMOD_SERDES_DIAG_LANE_STATE_HDR = 0x00000020 , /*!< SERDES DIAG */ 385 QMOD_SERDES_DIAG_LANE_STATE_LEGEND = 0x00000040 , /*!< SERDES DIAG */ 386 QMOD_SERDES_DIAG_CL72_STATUS = 0x00000080 , /*!< SERDES DIAG */ 387 QMOD_SERDES_DIAG_EYE_DENSITY = 0x00000100 , /*!< SERDES DIAG */ 388 QMOD_SERDES_DIAG_EYE_SCAN = 0x00000200 , /*!< SERDES DIAG */ 389 QMOD_SERDES_DIAG_MEAS_EYE_DENSITY_DATA = 0x00000400 , /*!< SERDES DIAG */ 390 QMOD_SERDES_DIAG_MEAS_EYE_SCAN_DONE = 0x00000800 , /*!< SERDES DIAG */ 391 QMOD_SERDES_DIAG_MEAS_LOWBER_EYE = 0x00001000 , /*!< SERDES DIAG */ 392 QMOD_SERDES_DIAG_READ_EYE_SCAN_STRIPE = 0x00002000 , /*!< SERDES DIAG */ 393 QMOD_SERDES_DIAG_EYE_DENSITY_DATA = 0x00004000 , /*!< SERDES DIAG */ 394 QMOD_SERDES_DIAG_LOWBER_EYE = 0x00008000 , /*!< SERDES DIAG */ 395 QMOD_SERDES_DIAG_EYE_SCAN_VERTICAL = 0x00010000 , /*!< SERDES DIAG */ 396 QMOD_SERDES_DIAG_EYE_SCAN_STRIPE = 0x00020000 , /*!< SERDES DIAG */ 397 QMOD_SERDES_DIAG_EYE_SCAN_HEADER = 0x00040000 , /*!< SERDES DIAG */ 398 QMOD_SERDES_DIAG_EYE_SCAN_FOOTER = 0x00080000 , /*!< SERDES DIAG */ 399 QMOD_SERDES_DIAG_BER_SCAN_TEST = 0x00100000 , /*!< SERDES DIAG */ 400 QMOD_SERDES_DIAG_READ_BER_SCAN_DATA = 0x00200000 , /*!< SERDES DIAG */ 401 QMOD_SERDES_DIAG_EYE_MARGIN_PROJ = 0x00400000 , /*!< SERDES DIAG */ 402 QMOD_SERDES_DIAG_DIG_LPBK = 0x00800000 , /*!< SERDES DIAG */ 403 QMOD_SERDES_DIAG_MEAS_EYE_SCAN_START = 0x01000000 , /*!< SERDES DIAG */ 404 QMOD_SERDES_DIAG_ILLEGAL = 0x00000000 /*!< Illegal value (enum boundary) */ 405 } qmod_pmd_diag_type; 406 407 /*! \def CNT_qmod_pmd_diag_type Types of enum qmod_pmd_diag_type */ 408 #define CNT_qmod_pmd_diag_type 26 409 410 /*! 411 \brief 412 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 413 by the enum var. 414 415 */ 416 extern char* e2s_qmod_pmd_diag_type [CNT_qmod_pmd_diag_type]; 417 /*! \enum qmod_an_type 418 419 qmod_an_type enumerates different types of autoneg modes in the PHY. 420 421 */ 422 423 typedef enum { 424 QMOD_CL73 = 0 , /*!< PHY autoneg CL73 enable */ 425 QMOD_CL37 , /*!< PHY autoneg CL37 enable */ 426 QMOD_CL73_BAM , /*!< PHY autoneg CL73 enable with Brcm Aneg Mode */ 427 QMOD_CL37_BAM , /*!< PHY autoneg CL37 enable with Brcm Aneg Mode */ 428 QMOD_CL37_SGMII , /*!< PHY autoneg for SGMII */ 429 QMOD_HPAM , /*!< PHY autoneg for HP aneg */ 430 QMOD_AN_TYPE_ILLEGAL /*!< Illegal value. programmatic boundary. */ 431 } qmod_an_type; 432 433 /*! \def CNT_qmod_an_type Types of enum qmod_an_type */ 434 #define CNT_qmod_an_type 7 435 436 /*! 437 \brief 438 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 439 by the enum var. 440 441 */ 442 extern char* e2s_qmod_an_type [CNT_qmod_an_type]; 443 /*! \enum qmod_eye_direction 444 445 The direction of slicer changing always moves from the middle of the eye. 446 Currently all speeds have the following bit positions in qmod_st 447 448 \li QMOD_EYE_VU: Vertical, Upward direction 449 \li QMOD_EYE_VD: Vertical, Downward direction 450 \li QMOD_EYE_HL: Horizontal, Left direction 451 \li QMOD_EYE_HR: Horizontal, Right direction 452 453 454 */ 455 456 typedef enum { 457 QMOD_EYE_VU = 0 , /*!< Vertical, Upward direction */ 458 QMOD_EYE_VD , /*!< Vertical, Downward direction */ 459 QMOD_EYE_HL , /*!< Horizontal, Left direction */ 460 QMOD_EYE_HR , /*!< Horizontal, Right direction */ 461 QMOD_EYE_ILLEGAL /*!< Programmatic illegal boundary. */ 462 } qmod_eye_direction; 463 464 /*! \def CNT_qmod_eye_direction Types of enum qmod_eye_direction */ 465 #define CNT_qmod_eye_direction 5 466 467 /*! 468 \brief 469 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 470 by the enum var. 471 472 */ 473 extern char* e2s_qmod_eye_direction [CNT_qmod_eye_direction]; 474 475 476 typedef enum { 477 QMOD_ABILITY_1G_KX = 0 , /*!< CL73 speed 1G_KX ease */ 478 QMOD_ABILITY_10G_KX4 , /*!< please write comments */ 479 QMOD_ABILITY_10G_KR , /*!< please write comments */ 480 QMOD_ABILITY_40G_KR4 , /*!< please write comments */ 481 QMOD_ABILITY_40G_CR4 , /*!< please write comments */ 482 QMOD_ABILITY_100G_CR10 , /*!< please write comments */ 483 QMOD_ABILITY_20G_KR2 , /*!< please write comments */ 484 QMOD_ABILITY_20G_CR2 , /*!< please write comments */ 485 QMOD_ABILITY_ILLEGAL /*!< please write comments */ 486 } qmod_tech_ability; 487 488 /*! \def CNT_qmod_tech_ability Types of enum qmod_tech_ability */ 489 #define CNT_qmod_tech_ability 9 490 491 /*! 492 \brief 493 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 494 by the enum var. 495 496 */ 497 extern char* e2s_qmod_tech_ability [CNT_qmod_tech_ability]; 498 /*! 499 \brief 500 This array associates the enum #qmod_lane_select enum with a bit mask. 501 The index is the #qmod_lane_select enum value. The value for each entry is 502 interpreted as follows. If bit [n] is 1, then lane [n] is enabled; if bit [n] 503 is 0, then lane [n] is disabled. By enabled, we mean that such-and-such 504 function is to be called for a lane; by disabled, we mean that such-and-such 505 function is not to be called for a lane. So a value of 0xF indicates that all 506 lanes or enabled, while 0x5 indicates that only lanes 0 and 2 are enabled. 507 508 */ 509 extern int e2n_qmod_tech_ability [CNT_qmod_tech_ability]; 510 /*! \enum qmod_cl37bam_ability 511 512 This array associates the enum #qmod_lane_select enum with a bit mask. 513 The index is the #qmod_lane_select enum value. The value for each entry is 514 interpreted as follows. If bit [n] is 1, then lane [n] is enabled; if bit [n] 515 is 0, then lane [n] is disabled. Enabled implies the function under 516 consideration be enebled for the lane. Disabled means the opposite. So a value 517 of 0xF indicates that all lanes or enabled, while 0x5 indicates that only lanes 518 0 and 2 are enabled. 519 520 qmod_cl37bam_ability enumerates different types of speed advertisements in the 521 basic autoneg page for CL37BAM only. 522 523 Currently all speeds have the following bit positions in qmod_st 524 525 \li QMOD_BAM37ABL_2P5G Bit Pos: 0 526 \li QMOD_BAM37ABL_5G_X4 Bit Pos: 1 527 \li QMOD_BAM37ABL_6G_X4 Bit Pos: 2 528 \li QMOD_BAM37ABL_10G_HIGIG Bit Pos: 3 529 \li QMOD_BAM37ABL_10G_CX4 Bit Pos: 4 530 \li QMOD_BAM37ABL_12G_X4 Bit Pos: 5 531 \li QMOD_BAM37ABL_12P5_X4 Bit Pos: 6 532 \li QMOD_BAM37ABL_13G_X4 Bit Pos: 7 533 \li QMOD_BAM37ABL_15G_X4 Bit Pos: 8 534 \li QMOD_BAM37ABL_16G_X4 Bit Pos: 9 535 \li QMOD_BAM37ABL_20G_X4_CX4 Bit Pos: 10 536 \li QMOD_BAM37ABL_20G_X4 Bit Pos: 11 537 \li QMOD_BAM37ABL_21G_X4 Bit Pos: 12 538 \li QMOD_BAM37ABL_25P455G Bit Pos: 13 539 \li QMOD_BAM37ABL_31P5G Bit Pos: 14 540 \li QMOD_BAM37ABL_32P7G Bit Pos: 15 541 \li QMOD_BAM37ABL_40G Bit Pos: 16 542 \li QMOD_BAM37ABL_10G_X2_CX4 Bit Pos: 17 543 \li QMOD_BAM37ABL_10G_DXGXS Bit Pos: 18 544 \li QMOD_BAM37ABL_10P5G_DXGXS Bit Pos: 19 545 \li QMOD_BAM37ABL_12P7_DXGXS Bit Pos: 20 546 \li QMOD_BAM37ABL_15P75G_R2 Bit Pos: 21 547 \li QMOD_BAM37ABL_20G_X2_CX4 Bit Pos: 22 548 \li QMOD_BAM37ABL_20G_X2 Bit Pos: 23 549 550 551 */ 552 553 typedef enum { 554 QMOD_BAM37ABL_2P5G = 0 , /*!< X1 BRCM */ 555 QMOD_BAM37ABL_5G_X4 , /*!< BRCM */ 556 QMOD_BAM37ABL_6G_X4 , /*!< BRCM */ 557 QMOD_BAM37ABL_10G_HIGIG , /*!< HG (10G_X4) */ 558 QMOD_BAM37ABL_10G_CX4 , /*!< (10G_X4_CX4) */ 559 QMOD_BAM37ABL_12G_X4 , /*!< HG */ 560 QMOD_BAM37ABL_12P5_X4 , /*!< HG */ 561 QMOD_BAM37ABL_13G_X4 , /*!< HG */ 562 QMOD_BAM37ABL_15G_X4 , /*!< HG */ 563 QMOD_BAM37ABL_16G_X4 , /*!< HG */ 564 QMOD_BAM37ABL_20G_X4_CX4 , /*!< XAUI 8b10b scram(20G_X4S) */ 565 QMOD_BAM37ABL_20G_X4 , /*!< HG */ 566 QMOD_BAM37ABL_21G_X4 , /*!< HG */ 567 QMOD_BAM37ABL_25P455G , /*!< X4 HG */ 568 QMOD_BAM37ABL_31P5G , /*!< X4 HG */ 569 QMOD_BAM37ABL_32P7G , /*!< X4 HG */ 570 QMOD_BAM37ABL_40G , /*!< X4 BRCM HG (40G_X4) */ 571 QMOD_BAM37ABL_10G_X2_CX4 , /*!< 10G_X2_CX4 */ 572 QMOD_BAM37ABL_10G_DXGXS , /*!< 10G_X2 */ 573 QMOD_BAM37ABL_10P5G_DXGXS , /*!< 10P5_X2 */ 574 QMOD_BAM37ABL_12P7_DXGXS , /*!< 12P7_X2 */ 575 QMOD_BAM37ABL_15P75G_R2 , /*!< 15P75_X2 */ 576 QMOD_BAM37ABL_20G_X2_CX4 , /*!< 20G_X2_CX4 */ 577 QMOD_BAM37ABL_20G_X2 , /*!< 20G_X2 */ 578 QMOD_BAM37ABL_ILLEGAL /*!< Illegal. Programmatic boundary */ 579 } qmod_cl37bam_ability; 580 581 /*! \def CNT_qmod_cl37bam_ability Types of enum qmod_cl37bam_ability */ 582 #define CNT_qmod_cl37bam_ability 25 583 584 /*! 585 \brief 586 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 587 by the enum var. 588 589 */ 590 extern char* e2s_qmod_cl37bam_ability [CNT_qmod_cl37bam_ability]; 591 /*! \enum qmod_diag_an_type 592 593 This array associates the enum #qmod_lane_select enum with a bit mask. 594 The index is the #qmod_lane_select enum value. The value for each entry is 595 interpreted as follows. If bit [n] is 1, then lane [n] is enabled; if bit [n] 596 is 0, then lane [n] is disabled. By enabled, we mean that such-and-such 597 function is to be called for a lane; by disabled, we mean that such-and-such 598 function is not to be called for a lane. So a value of 0xF indicates that all 599 lanes or enabled, while 0x5 indicates that only lanes 0 and 2 are enabled. 600 601 */ 602 603 typedef enum { 604 QMOD_DIAG_AN_DONE = 0 , /*!< AN completion check */ 605 QMOD_DIAG_AN_HCD , /*!< AN HCD speed check */ 606 QMOD_DIAG_AN_TYPE_ILLEGAL /*!< Illegal value. programmatic boundary */ 607 } qmod_diag_an_type; 608 609 /*! \def CNT_qmod_diag_an_type Types of enum qmod_diag_an_type */ 610 #define CNT_qmod_diag_an_type 3 611 612 /*! 613 \brief 614 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 615 by the enum var. 616 617 */ 618 extern char* e2s_qmod_diag_an_type [CNT_qmod_diag_an_type]; 619 /*! \enum qmod_tier1_function_type 620 621 This array associates the enum #qmod_lane_select enum with a bit mask. 622 The index is the #qmod_lane_select enum value. The value for each entry is 623 interpreted as follows. If bit [n] is 1, then lane [n] is enabled; if bit [n] 624 is 0, then lane [n] is disabled. By enabled, we mean that such-and-such 625 function is to be called for a lane; by disabled, we mean that such-and-such 626 function is not to be called for a lane. So a value of 0xF indicates that all 627 lanes or enabled, while 0x5 indicates that only lanes 0 and 2 are enabled. 628 629 */ 630 631 typedef enum { 632 PCS_BYPASS_CTL = 0 , /*!< qmod_pcs_bypass_ctl */ 633 INIT_PCS , /*!< qmod_init_pcs */ 634 INIT_PMD_SW , /*!< qmod_init_pmd_sw */ 635 INIT_PMD , /*!< qmod_init_pmd */ 636 PMD_RESET_SEQ , /*!< qmod_pmd_reset_seq */ 637 PMD_X4_RESET , /*!< qmod_pmd_x4_reset */ 638 WAIT_SC_DONE , /*!< qmod_wait_sc_done */ 639 ENABLE_SET , /*!< qmod_enable_set */ 640 FECMODE_SET , /*!< qmod_fecmode_set */ 641 GET_PCS_LINK_STATUS , /*!< qmod_get_pcs_link_status */ 642 OVERRIDE_SET , /*!< qmod_override_set */ 643 CREDIT_OVERRIDE_SET , /*!< qmod_credit_override_set */ 644 ENCODE_SET , /*!< qmod_encode_set */ 645 DECODE_SET , /*!< qmod_decode_set */ 646 CREDIT_CONTROL , /*!< qmod_credit_control */ 647 TX_LANE_CONTROL , /*!< qmod_tx_lane_control */ 648 RX_LANE_CONTROL , /*!< qmod_rx_lane_control */ 649 TX_LANE_DISABLE , /*!< qmod_tx_lane_disable */ 650 POWER_CONTROL , /*!< qmod_power_control */ 651 AUTONEG_SET , /*!< qmod_autoneg_set */ 652 AUTONEG_GET , /*!< qmod_autoneg_get */ 653 AUTONEG_CONTROL , /*!< qmod_autoneg_control */ 654 TSC12_CONTROL , /*!< qmod_tsc12_control */ 655 CHECK_SC_STATS , /*!< qmod_check_sc_stats */ 656 REG_READ , /*!< qmod_reg_read */ 657 REG_WRITE , /*!< qmod_reg_write */ 658 PRBS_CHECK , /*!< qmod_prbs_check */ 659 CJPAT_CRPAT_MODE_SET , /*!< qmod_cjpat_crpat_mode_set */ 660 CJPAT_CRPAT_CHECK , /*!< qmod_cjpat_crpat_check */ 661 QMOD_DIAG , /*!< qmod_diag */ 662 PCS_LANE_SWAP , /*!< qmod_pcs_lane_swap */ 663 PMD_LANE_SWAP , /*!< qmod_pmd_lane_swap */ 664 PMD_LANE_SWAP_TX , /*!< qmod_pmd_lane_swap_tx */ 665 PARALLEL_DETECT_CONTROL , /*!< qmod_parallel_detect_control */ 666 REVID_READ , /*!< qmod_revid_read */ 667 SOFT_RESET , /*!< qmod_soft_reset */ 668 SET_SPD_INTF , /*!< qmod_set_spd_intf */ 669 SET_PORT_MODE , /*!< qmod_set_port_mode */ 670 EEE_PASSTHRU_SET , /*!< qmod_EEE_pass_thru_set */ 671 EEE_PASSTHRU_GET , /*!< qmod_EEE_pass_thru_get */ 672 FEC_CONTROL , /*!< qmod_FEC_control */ 673 HIGIG2_CONTROL , /*!< qmod_HIGIG2_control */ 674 LF_RF_CONTROL , /*!< qmod_LF_RF_control */ 675 RX_FAST_LOCK_CONTROL , /*!< qmod_rx_fast_lock_control */ 676 PMD_CORE_RESET , /*!< qmod_pmd_core_reset */ 677 PMD_LANE_RESET , /*!< qmod_pmd_lane_reset */ 678 AFE_SPEED_UP_DSC_VGA , /*!< qmod_afe_speed_up_dsc_vga */ 679 CLAUSE_72_CONTROL , /*!< qmod_clause72_control */ 680 PLL_SEQUENCER_CONTROL , /*!< qmod_pll_sequencer_control */ 681 PLL_LOCK_WAIT , /*!< qmod_pll_lock_wait */ 682 PROG_DATA , /*!< qmod_prog_data */ 683 RX_SEQ_CONTROL , /*!< qmod_rx_seq_control */ 684 SET_POLARITY , /*!< qmod_tx_rx_polarity */ 685 PRBS_CONTROL , /*!< qmod_prbs_control */ 686 PRBS_MODE , /*!< qmod_prbs_mode */ 687 RX_PF_CONTROL , /*!< qmod_rx_PF_control */ 688 RX_VGA_CONTROL , /*!< qmod_rx_VGA_control */ 689 CJPAT_CRPAT_CONTROL , /*!< qmod_cjpat_crpat_control */ 690 TX_LOOPBACK_CONTROL , /*!< qmod_tx_loopback_control */ 691 TX_PMD_LOOPBACK_CONTROL , /*!< qmod_tx_pmd_loopback_control */ 692 RX_LOOPBACK_CONTROL , /*!< qmod_rx_loopback_control */ 693 RX_P1_SLICER_CONTROL , /*!< qmod_rx_p1_slicer_control */ 694 RX_M1_SLICER_CONTROL , /*!< qmod_rx_m1_slicer_control */ 695 RX_D_SLICER_CONTROL , /*!< qmod_rx_d_slicer_control */ 696 WAIT_PMD_LOCK , /*!< qmod_wait_pmd_lock */ 697 FIRMWARE_SET , /*!< qmod_firmware_set */ 698 PMD_RESET_BYPASS , /*!< qmod_pmd_reset_bypass */ 699 PMD_OVERRIDE_CONTROL , /*!< qmod_pmd_override_control */ 700 SET_QPORT_SPD , /*!< qmod_set_qport_spd */ 701 SET_QSGMII_EN , /*!< qmod_set_qsgmii_en */ 702 QMODE_DISABLE_SET , /*!< qmod_disable_set */ 703 PLL_LOCK_GET , /*!< qmod_pll_lock_get */ 704 PMD_LOCK_GET , /*!< qmod_pmd_lock_get */ 705 AUTONEG_SET_INIT , /*!< qmod_autonet_set_init */ 706 AUTONEG_ABILITIES_CONTROL , /*!< qmod_autonet_abilities_controls */ 707 AUTONEG_CL37_BASE_ABILITIES , /*!< qmod_autoneg_cl37_base_abilities */ 708 AUTONEG_CL37_BAM_OVER1G_ABILITIES , /*!< qmod_autoneg_cl37_bam_over1g_abilities */ 709 AUTONEG_AUTONEG_CONTROL_GET , /*!< qmod_autoneg_control_get */ 710 AUTONEG_AUTONEG_LOCAL_ABILITY_GET , /*!< qmod_autoneg_local_ability_get */ 711 AUTONEG_AUTONEG_REMOTE_ABILITY_GET , /*!< qmod_autoneg_remote_ability_get */ 712 AUTONEG_AN_ABILITIES_ENABLES , /*!< qmod_an_abilities_enables */ 713 AUTONEG_GET_HT_ENTRIES , /*!< qmod_get_ht_entries */ 714 UPDATE_PORT_MODE_SELECT , /*!< qmod_update_port_mode_select */ 715 TX_RX_POLARITY_SET , /*!< qmod_tx_rx_polarity_set */ 716 TX_RX_POLARITY_GET , /*!< qmod_tx_rx_polarity_get */ 717 TX_PI_CONTROL_GET , /*!< qmod_tx_pi_control_get */ 718 TX_LANE_DISABLE_SET , /*!< qmod_tx_lane_disable_set */ 719 TX_LANE_DISABLE_GET , /*!< qmod_tx_lane_disable_get */ 720 SPEED_ID_GET , /*!< qmod_speed_id_get */ 721 PMD_LANE_SWAP_TX_GET , /*!< qmod_pmd_lane_swap_tx_get */ 722 PLL_RESET_ENABLE_SET , /*!< qmod_pll_reset_enable_set */ 723 PLL_MODE_SET , /*!< qmod_pll_mode_set */ 724 PCS_LANE_SWAP_GET , /*!< qmod_pcs_lane_swap_get */ 725 OSMODE_SET , /*!< qmod_osmode_set */ 726 MASTER_PORT_NUM_SET , /*!< qmod_master_port_num_set */ 727 GET_PLLDIV , /*!< qmod_get_plldiv */ 728 DISABLE_GET , /*!< qmod_disable_get */ 729 FIRMWARE_LOAD , /*!< qmod_firmware_load */ 730 PRBS_RX_POLYNOMIAL_SET , /*!< qmod_prbs_rx_polynomial_set */ 731 RX_LANE_CONTROL_SET , /*!< qmod_rx_lane_control_set */ 732 RX_LANE_CONTROL_GET , /*!< qmod_rx_lane_control_get */ 733 TRIGGER_SPEED_CHANGE , /*!< qmod_trigger_speed_change */ 734 TIER1_FUNCTION_ILLEGAL /*!< always last */ 735 } qmod_tier1_function_type; 736 737 /*! \def CNT_qmod_tier1_function_type Types of enum qmod_tier1_function_type */ 738 #define CNT_qmod_tier1_function_type 103 739 740 /*! 741 \brief 742 This array returns the string version of the enum #qmod_pmd_diag_type when indexed 743 by the enum var. 744 745 */ 746 extern char* e2s_qmod_tier1_function_type [CNT_qmod_tier1_function_type]; 747 748 /*! \def CNT_sc_mode_type Types of enum sc_mode_type */ 749 #define CNT_sc_mode_type 8 750 751 /*! 752 \brief 753 This array returns the string version of the enum 754 #qmod_core_select when 755 indexed by the enum var. 756 757 */ 758 extern char* e2s_sc_mode_type [CNT_sc_mode_type]; 759 760 /*! \enum qmod_pll_mode_type 761 qmod_pll_mode_type divides the PLL to get a clock which is a multiple of the 762 refernce clock. This clock runs all the digital logic in the MAC and PHY layers 763 and is referred to as TSC_CLK. To get the TSC_CLK, you simply multiply the 764 reference clock by the pll divider value (not the reg. bit location) 765 766 */ 767 768 typedef enum { 769 QMOD_PLL_MODE_DIV_ZERO = 0 , /*!< Illegal PLL Divider Number */ 770 QMOD_PLL_MODE_DIV_40 = 2 , /*!< Multiply ref. clk by 40 */ 771 QMOD_PLL_MODE_DIV_42 = 3 , /*!< Multiply ref. clk by 42 */ 772 QMOD_PLL_MODE_DIV_48 = 4 , /*!< Multiply ref. clk by 48 */ 773 QMOD_PLL_MODE_DIV_52 = 6 , /*!< Multiply ref. clk by 52 */ 774 QMOD_PLL_MODE_DIV_54 = 7 , /*!< Multiply ref. clk by 54 */ 775 QMOD_PLL_MODE_DIV_60 = 8 , /*!< Multiply ref. clk by 60 */ 776 QMOD_PLL_MODE_DIV_64 = 9 , /*!< Multiply ref. clk by 64 */ 777 QMOD_PLL_MODE_DIV_66 = 10 , /*!< Multiply ref. clk by 66 */ 778 QMOD_PLL_MODE_DIV_70 = 12 , /*!< Multiply ref. clk by 70 */ 779 QMOD_PLL_MODE_DIV_80 = 13 , /*!< Multiply ref. clk by 80 */ 780 QMOD_PLL_MODE_DIV_92 = 14 , /*!< Multiply ref. clk by 92 */ 781 QMOD_PLL_MODE_DIV_ILLEGAL /*!< Illegal (programmatic boundary) */ 782 } qmod_pll_mode_type; 783 784 /*! \def CNT_qmod_pll_mode_type Types of enum qmod_pll_mode_type */ 785 #define CNT_qmod_pll_mode_type 13 786 787 /*! 788 \brief 789 This array returns the string of #qmod_pll_mode_type when indexed by the enum. 790 791 */ 792 extern char* e2s_qmod_pll_mode_type [CNT_qmod_pll_mode_type]; 793 /*! 794 \brief 795 This array returns the clock multiplier of #qmod_pll_mode_type when indexed by the enum. 796 797 */ 798 extern int e2n_qmod_pll_mode_type [CNT_qmod_pll_mode_type]; 799 /*! \enum qmod_os_mode_type 800 801 802 The oversampling mode means that bits are sent out more than once to reduce 803 the effective frequency of data transfer. For example you can send 5G bits 804 over a 10G bit lane by sending every bit twice, or OS=2. When the OS is 3.3 805 it's a bit tricky, we send bits 3 or 4 times in a pattern like so 806 3,3,3,4,3,3,3,4,... Similarly for OS = 8, we send 8,8,8,9,8,8,8,9,... 807 808 809 */ 810 811 typedef enum { 812 QMOD_PMA_OS_MODE_1 = 0 , /*!< Over sampling Mode 1 */ 813 QMOD_PMA_OS_MODE_2 = 1 , /*!< Over sampling Mode 2 */ 814 QMOD_PMA_OS_MODE_3 = 2 , /*!< Over sampling Mode 3 */ 815 QMOD_PMA_OS_MODE_3_3 = 3 , /*!< Over sampling Mode 3.3 */ 816 QMOD_PMA_OS_MODE_4 = 4 , /*!< Over sampling Mode 4 */ 817 QMOD_PMA_OS_MODE_5 = 5 , /*!< Over sampling Mode 5 */ 818 QMOD_PMA_OS_MODE_7_25 = 6 , /*!< Over sampling Mode 7.25 */ 819 QMOD_PMA_OS_MODE_8 = 7 , /*!< Over sampling Mode 8 */ 820 QMOD_PMA_OS_MODE_8_25 = 8 , /*!< Over sampling Mode 8.25 */ 821 QMOD_PMA_OS_MODE_10 = 9 , /*!< Over sampling Mode 10 */ 822 QMOD_PMA_OS_MODE_ILLEGAL = 15 /*!< Over sampling Mode Illegal */ 823 } qmod_os_mode_type; 824 825 /*! \def CNT_qmod_os_mode_type Types of enum qmod_os_mode_type */ 826 #define CNT_qmod_os_mode_type 11 827 828 /*! 829 \brief 830 This array returns the string of #qmod_os_mode when indexed by the enum. 831 832 */ 833 extern char* e2s_qmod_os_mode_type [CNT_qmod_os_mode_type]; 834 /*! 835 \brief 836 This array returns the over sampling value of #qmod_os_mode when indexed by 837 the enum. For floating values 3.3 and 8.25 it returns 33 and 825. 838 839 */ 840 extern int e2n_qmod_os_mode_type [CNT_qmod_os_mode_type]; 841 /*! \enum qmod_scr_mode 842 843 This mode indicates how many bits of a 'frame' will be scrambled. We have either 844 66 or 80 bits per frame (depending on 8b10b or 64b66b encoding). Normally 845 scrambling is 846 847 \li bypassed for baud rates under 6.25G (0). 848 \li we scramble all 66 bits (1) 849 \li all 80 bits(2) 850 \li only 64 of the 66b (3). i.e we don't scramble the 'sync' bits. 851 852 */ 853 854 typedef enum { 855 QMOD_SCR_MODE_BYPASS = 0 , /*!< Scrambling Mode bypassed */ 856 QMOD_SCR_MODE_66B = 1 , /*!< Scrambling Mode 66B */ 857 QMOD_SCR_MODE_80B = 2 , /*!< Scrambling Mode 80B */ 858 QMOD_SCR_MODE_64B = 3 /*!< Scrambling Mode 64B */ 859 } qmod_scr_mode; 860 861 /*! \def CNT_qmod_scr_mode Types of enum qmod_scr_mode */ 862 #define CNT_qmod_scr_mode 4 863 864 /*! 865 \brief 866 This array returns the string of #qmod_scr_mode when indexed by the enum. 867 868 */ 869 extern char* e2s_qmod_scr_mode [CNT_qmod_scr_mode]; 870 /*! 871 \brief 872 This array returns the scrambling mode of #qmod_scr_mode when indexed by 873 the enum. 874 875 */ 876 extern int e2n_qmod_scr_mode [CNT_qmod_scr_mode]; 877 /*! \enum qmod_encode_mode 878 879 Serial bits are encoded when transmitted. The encoding depends on the baud rate 880 and the link type 881 \li 000 All encoding functions disabled for lane 882 \li 001 8b10b (cl48 ) 883 \li 010 8b10b (cl48 rxaui) 884 \li 011 8b10b (cl36 ) 885 \li 100 64b66b (cl82 ) 886 \li 101 64b66b (cl49 ) 887 \li 110 64b66b (brcm ) 888 889 */ 890 891 typedef enum { 892 QMOD_ENCODE_MODE_NONE = 0 , /*!< Encoding Mode NONE */ 893 QMOD_ENCODE_MODE_CL48 = 1 , /*!< Encoding Mode CL48 */ 894 QMOD_ENCODE_MODE_CL48_2_LANE = 2 , /*!< Encoding Mode CL48 */ 895 QMOD_ENCODE_MODE_CL36 = 3 , /*!< Encoding Mode CL36 */ 896 QMOD_ENCODE_MODE_CL82 = 4 , /*!< Encoding Mode CL82 */ 897 QMOD_ENCODE_MODE_CL49 = 5 , /*!< Encoding Mode CL49 */ 898 QMOD_ENCODE_MODE_BRCM = 6 , /*!< Encoding Mode BRCM */ 899 QMOD_ENCODE_MODE_ILLEGAL = 7 /*!< Encoding Mode Illegal */ 900 } qmod_encode_mode; 901 902 /*! \def CNT_qmod_encode_mode Types of enum qmod_encode_mode */ 903 #define CNT_qmod_encode_mode 8 904 905 /*! 906 \brief 907 This array returns the string of #qmod_encode_mode when indexed by the enum. 908 909 */ 910 extern char* e2s_qmod_encode_mode [CNT_qmod_encode_mode]; 911 /*! 912 \brief 913 This array returns the encoding mode of #qmod_encode_mode when indexed by 914 the enum. 915 916 */ 917 extern int e2n_qmod_encode_mode [CNT_qmod_encode_mode]; 918 /*! \enum qmod_check_end_mode 919 920 Check end is a disparity based error bit set by the PCS for CL48. The generation 921 of this error bit depends on the speed. 922 923 */ 924 925 typedef enum { 926 QMOD_CL48_CHECK_END_OFF = 0 , /*!< Don't generate checkend error bit */ 927 QMOD_CL48_CHECK_END_ON = 1 /*!< generate checkend error bit */ 928 } qmod_check_end_mode; 929 930 /*! \def CNT_qmod_check_end_mode Types of enum qmod_check_end_mode */ 931 #define CNT_qmod_check_end_mode 2 932 933 /*! 934 \brief 935 This array returns the string of #qmod_check_end_mode when indexed by the enum. 936 937 */ 938 extern char* e2s_qmod_check_end_mode [CNT_qmod_check_end_mode]; 939 /*! \enum qmod_sigdet_filter 940 941 No documentation available 942 943 */ 944 945 typedef enum { 946 QMOD_SIGDET_FILTER_NONCX4 = 0 , /*!< No description available */ 947 QMOD_SIGDET_FILTER_CX4 = 1 /*!< No description available */ 948 } qmod_sigdet_filter; 949 950 /*! \def CNT_qmod_sigdet_filter Types of enum qmod_sigdet_filter */ 951 #define CNT_qmod_sigdet_filter 2 952 953 /*! 954 \brief 955 This array returns the string of #qmod_sigdet_filter when indexed by the enum. 956 957 */ 958 extern char* e2s_qmod_sigdet_filter [CNT_qmod_sigdet_filter]; 959 /*! \enum qmod_blocksync_mode 960 961 A block is detected in ports with multiple lanes. PCS has to recognize blocks 962 since the bits may come in skewed in time over lanes. This feature identifies 963 the block type, which is a feature of the speed. 964 965 000 none 966 001 cl49 mode - enables func_cl49cl82_sync block 967 010 cl82 mode - enables func_cl49cl82_sync block 968 011 8b10b mode - enables the func_8b10b_sync block 969 100 fec mode - enables the func_fec_sync block 970 101 brcm 64b66b mode 971 972 */ 973 974 typedef enum { 975 QMOD_BLOCKSYNC_MODE_NONE = 0 , /*!< Block sync mode none */ 976 QMOD_BLOCKSYNC_MODE_CL49 = 1 , /*!< Block sync mode CL49 type */ 977 QMOD_BLOCKSYNC_MODE_CL82 = 2 , /*!< Block sync mode CL82 type */ 978 QMOD_BLOCKSYNC_MODE_8B10B = 3 , /*!< Block sync mode 8B10B type */ 979 QMOD_BLOCKSYNC_MODE_FEC = 4 , /*!< Block sync mode FEC type */ 980 QMOD_BLOCKSYNC_MODE_BRCM = 5 , /*!< Block sync mode BRCM type */ 981 QMOD_BLOCKSYNC_MODE_ILLEGAL = 7 /*!< Block sync mode illegal */ 982 } qmod_blocksync_mode; 983 984 /*! \def CNT_qmod_blocksync_mode Types of enum qmod_blocksync_mode */ 985 #define CNT_qmod_blocksync_mode 7 986 987 /*! 988 \brief 989 This array returns the string of #qmod_blocksync_mode when indexed by the enum. 990 991 */ 992 extern char* e2s_qmod_blocksync_mode [CNT_qmod_blocksync_mode]; 993 /*! \enum qmod_reorder_mode 994 995 Depending on aggregation mode we have various types of reordering of serial 996 bits. 997 998 */ 999 1000 typedef enum { 1001 QMOD_R_REORDER_MODE_NONE = 0 , /*!< Reorder mode NONE type */ 1002 QMOD_R_REORDER_MODE_CL48 = 1 , /*!< Reorder mode CL48 type */ 1003 QMOD_R_REORDER_MODE_CL36 = 2 , /*!< Reorder mode CL36 type */ 1004 QMOD_R_REORDER_MODE_CL36_CL48 = 3 /*!< Reorder mode CL36_CL48 type */ 1005 } qmod_reorder_mode; 1006 1007 /*! \def CNT_qmod_reorder_mode Types of enum qmod_reorder_mode */ 1008 #define CNT_qmod_reorder_mode 4 1009 1010 /*! 1011 \brief 1012 This array returns the string of #qmod_reorder_mode when indexed by the enum. 1013 1014 */ 1015 extern char* e2s_qmod_reorder_mode [CNT_qmod_reorder_mode]; 1016 /*! \enum qmod_cl36_mode 1017 1018 Cl36 mode control 1019 1020 */ 1021 1022 typedef enum { 1023 QMOD_CL36_DISABLE = 0 , /*!< */ 1024 QMOD_CL36_ENABLE = 1 /*!< */ 1025 } qmod_cl36_mode; 1026 1027 /*! \def CNT_qmod_cl36_mode Types of enum qmod_cl36_mode */ 1028 #define CNT_qmod_cl36_mode 2 1029 1030 /*! 1031 \brief 1032 This array returns the string of #qmod_cl36_mode when indexed by the enum. 1033 1034 */ 1035 extern char* e2s_qmod_cl36_mode [CNT_qmod_cl36_mode]; 1036 /*! \enum qmod_descrambler_mode 1037 1038 The descrambling must match the scrambling done at the transmitting port. 1039 1040 */ 1041 1042 typedef enum { 1043 QMOD_R_DESCR1_MODE_BYPASS = 0 , /*!< No descrambling */ 1044 QMOD_R_DESCR1_MODE_66B = 1 , /*!< 66b descrambling */ 1045 QMOD_R_DESCR1_MODE_10B = 2 , /*!< 10b descrambling */ 1046 QMOD_R_DESCR1_MODE_ILLEGAL = 3 /*!< */ 1047 } qmod_descrambler_mode; 1048 1049 /*! \def CNT_qmod_descrambler_mode Types of enum qmod_descrambler_mode */ 1050 #define CNT_qmod_descrambler_mode 4 1051 1052 /*! 1053 \brief 1054 This array returns the string of #qmod_descrambler_mode when indexed by the enum. 1055 1056 */ 1057 extern char* e2s_qmod_descrambler_mode [CNT_qmod_descrambler_mode]; 1058 /*! \enum qmod_decoder_mode 1059 1060 The descrambling must match the scrambling done at the transmitting port. 1061 1062 */ 1063 1064 typedef enum { 1065 QMOD_DECODER_MODE_NONE = 0 , /*!< decoder mode NONE */ 1066 QMOD_DECODER_MODE_CL49 = 1 , /*!< decoder mode CL49 */ 1067 QMOD_DECODER_MODE_BRCM = 2 , /*!< decoder mode BRCM */ 1068 QMOD_DECODER_MODE_ALU = 3 , /*!< decoder mode ALU */ 1069 QMOD_DECODER_MODE_CL48 = 4 , /*!< decoder mode CL48 */ 1070 QMOD_DECODER_MODE_CL36 = 5 , /*!< decoder mode CL36 */ 1071 QMOD_DECODER_MODE_CL82 = 6 , /*!< decoder mode CL82 */ 1072 QMOD_DECODER_MODE_ILLEGAL = 7 /*!< decoder mode ILLEGAL */ 1073 } qmod_decoder_mode; 1074 1075 /*! \def CNT_qmod_decoder_mode Types of enum qmod_decoder_mode */ 1076 #define CNT_qmod_decoder_mode 8 1077 1078 /*! 1079 \brief 1080 This array returns the string of #qmod_decoder_mode when indexed by the enum. 1081 1082 */ 1083 extern char* e2s_qmod_decoder_mode [CNT_qmod_decoder_mode]; 1084 /*! \enum qmod_deskew_mode 1085 1086 Deskew Mode is a function of speed. 1087 1088 */ 1089 1090 typedef enum { 1091 QMOD_R_DESKEW_MODE_BYPASS = 0 , /*!< deskew mode BYPASS */ 1092 QMOD_R_DESKEW_MODE_8B_10B = 1 , /*!< deskew mode 8B_10B */ 1093 QMOD_R_DESKEW_MODE_BRCM_66B = 2 , /*!< deskew mode BRCM_66B */ 1094 QMOD_R_DESKEW_MODE_CL82_66B = 3 , /*!< deskew mode CL82_66B */ 1095 QMOD_R_DESKEW_MODE_CL36_10B = 4 , /*!< deskew mode CL36_10B */ 1096 QMOD_R_DESKEW_MODE_ILLEGAL = 7 /*!< deskew mode ILLEGAL */ 1097 } qmod_deskew_mode; 1098 1099 /*! \def CNT_qmod_deskew_mode Types of enum qmod_deskew_mode */ 1100 #define CNT_qmod_deskew_mode 6 1101 1102 /*! 1103 \brief 1104 This array returns the string of #qmod_deskew_mode when indexed by the enum. 1105 1106 */ 1107 extern char* e2s_qmod_deskew_mode [CNT_qmod_deskew_mode]; 1108 /*! \enum qmod_descrambler2_mode 1109 1110 No description 1111 1112 */ 1113 1114 typedef enum { 1115 QMOD_DESC2_MODE_NONE = 0 , /*!< Descrambler2 mode NONE */ 1116 QMOD_DESC2_MODE_CL49 = 1 , /*!< Descrambler2 mode CL49 */ 1117 QMOD_DESC2_MODE_BRCM = 2 , /*!< Descrambler2 mode BRCM */ 1118 QMOD_DESC2_MODE_ALU = 3 , /*!< Descrambler2 mode ALU */ 1119 QMOD_DESC2_MODE_CL48 = 4 , /*!< Descrambler2 mode CL48 */ 1120 QMOD_DESC2_MODE_CL36 = 5 , /*!< Descrambler2 mode CL36 */ 1121 QMOD_DESC2_MODE_CL82 = 6 , /*!< Descrambler2 mode CL82 */ 1122 QMOD_DESC2_MODE_ILLEGAL = 7 /*!< Descrambler2 mode ILLEGAL */ 1123 } qmod_descrambler2_mode; 1124 1125 /*! \def CNT_qmod_descrambler2_mode Types of enum qmod_descrambler2_mode */ 1126 #define CNT_qmod_descrambler2_mode 8 1127 1128 /*! 1129 \brief 1130 This array returns the string of #qmod_descrambler2_mode when indexed by the enum. 1131 1132 */ 1133 extern char* e2s_qmod_descrambler2_mode [CNT_qmod_descrambler2_mode]; 1134 /*! \enum qmod_byte_del_mode 1135 1136 For low speeds, data is duplicted 10 or 100 times to run at higher bauds. For 1137 example in a 10G lane, we duplicate 100M data 100 times. On the receive side 1138 these duplicate bits must be deleted. 1139 \li 0 - 100M mode (Delete 9 out of every 10 bytes) 1140 \li 1 - 10M mode (Delete 99 out of every 100 bytes) 1141 \li 2 - Passthrough (No deletion) 1142 1143 1144 */ 1145 1146 typedef enum { 1147 QMOD_R_DESC2_BYTE_DELETION_100M = 0 , /*!< 100M type Byte deletion */ 1148 QMOD_R_DESC2_BYTE_DELETION_10M = 1 , /*!< 10M type Byte deletion */ 1149 QMOD_R_DESC2_BYTE_DELETION_NONE = 2 /*!< No Byte deletion */ 1150 } qmod_byte_del_mode; 1151 1152 /*! \def CNT_qmod_byte_del_mode Types of enum qmod_byte_del_mode */ 1153 #define CNT_qmod_byte_del_mode 3 1154 1155 /*! 1156 \brief 1157 This array returns the string of #qmod_blocksync_mode when indexed by the enum. 1158 1159 */ 1160 extern char* e2s_qmod_byte_del_mode [CNT_qmod_byte_del_mode]; 1161 /*! \enum qmod_decode_descr_mode 1162 1163 No description 1164 1165 */ 1166 1167 typedef enum { 1168 QMOD_R_DEC1_DESCR_MODE_NONE = 0 , /*!< */ 1169 QMOD_R_DEC1_DESCR_MODE_BRCM64B66B = 1 /*!< */ 1170 } qmod_decode_descr_mode; 1171 1172 /*! \def CNT_qmod_decode_descr_mode Types of enum qmod_decode_descr_mode */ 1173 #define CNT_qmod_decode_descr_mode 2 1174 1175 /*! 1176 \brief 1177 This array returns the string of #qmod_decode_descr_mode when indexed by the enum. 1178 1179 */ 1180 extern char* e2s_qmod_decode_descr_mode [CNT_qmod_decode_descr_mode]; 1181 /*! \enum an_property_enable 1182 1183 No description 1184 1185 */ 1186 1187 typedef enum { 1188 QMOD_AN_PROPERTY_ENABLE_NONE = 0x00000000 , /*!< */ 1189 QMOD_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE = 0x00000001 , /*!< */ 1190 QMOD_AN_PROPERTY_ENABLE_AN_PD_TO_CL37 = 0x00000002 , /*!< */ 1191 QMOD_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO = 0x00000004 , /*!< */ 1192 QMOD_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO = 0x00000008 , /*!< */ 1193 QMOD_AN_PROPERTY_ENABLE_HPAM_TO_CL73_AUTO = 0x00000010 , /*!< */ 1194 QMOD_AN_PROPERTY_ENABLE_CL73_BAM_TO_HPAM_AUTO = 0x00000020 , /*!< */ 1195 QMOD_AN_PROPERTY_ENABLE_ILLEGAL = 0x00000040 /*!< */ 1196 } an_property_enable; 1197 1198 /*! \def CNT_an_property_enable Types of enum an_property_enable */ 1199 #define CNT_an_property_enable 8 1200 1201 /*! \enum credit_type_t 1202 1203 No description 1204 1205 */ 1206 1207 typedef enum { 1208 QMOD_CREDIT_RESET = 0x00000000 , /*!< */ 1209 QMOD_CREDIT_TABLE = 0x00000001 , /*!< */ 1210 QMOD_CREDIT_CLOCK_COUNT_0 = 0x00000002 , /*!< */ 1211 QMOD_CREDIT_CLOCK_COUNT_1 = 0x00000004 , /*!< */ 1212 QMOD_CREDIT_LOOP_COUNT_0 = 0x00000008 , /*!< */ 1213 QMOD_CREDIT_LOOP_COUNT_1 = 0x00000010 , /*!< */ 1214 QMOD_CREDIT_MAC = 0x00000020 , /*!< */ 1215 QMOD_CREDIT_PCS_CLOCK_COUNT_0 = 0x00000040 , /*!< */ 1216 QMOD_CREDIT_PCS_GEN_COUNT = 0x00000080 , /*!< */ 1217 QMOD_CREDIT_EN = 0x00000100 , /*!< */ 1218 QMOD_CREDIT_PCS_REPCNT = 0x00000200 , /*!< */ 1219 QMOD_CREDIT_SGMII_SPD = 0x00000400 , /*!< */ 1220 QMOD_CREDIT_ILLEGAL = 0x00000800 /*!< */ 1221 } credit_type_t; 1222 1223 /*! \def CNT_credit_type_t Types of enum credit_type_t */ 1224 #define CNT_credit_type_t 13 1225 1226 /*! \enum override_type_t 1227 1228 No description 1229 1230 */ 1231 1232 typedef enum { 1233 QMOD_OVERRIDE_RESET = 0x00000000 , /*!< */ 1234 QMOD_OVERRIDE_QSGMII_EN = 0x00000003 , /*!< */ 1235 QMOD_OVERRIDE_CL36BYTEDEL_MODE = 0x00000001 , /*!< */ 1236 QMOD_OVERRIDE_OS_MODE = 0x00000002 , /*!< */ 1237 QMOD_OVERRIDE_CREDIT_EN = 0x00000008 , /*!< */ 1238 QMOD_OVERRIDE_ALL = 0x00008000 /*!< */ 1239 } override_type_t; 1240 1241 /*! \def CNT_override_type_t Types of enum override_type_t */ 1242 #define CNT_override_type_t 18 1243 1244 /*! \enum qmod_ref_clk_t 1245 1246 No description 1247 1248 */ 1249 1250 typedef enum { 1251 QMODREFCLK156MHZ = 0x00000000 , /*!< 156p25MHz */ 1252 QMODREFCLK125MHZ = 0x00000001 , /*!< 125MHz */ 1253 QMODREFCLKCOUNT = 0x00000002 /*!< */ 1254 } qmod_ref_clk_t; 1255 1256 /*! \def CNT_qmod_ref_clk_t Types of enum qmod_ref_clk_t */ 1257 #define CNT_qmod_ref_clk_t 3 1258 1259 /*! 1260 \brief 1261 This array returns the string of #an_property_enable when indexed by the enum. 1262 1263 */ 1264 extern char* e2s_qmod_ref_clk_t [CNT_qmod_ref_clk_t]; 1265 #endif /* _TSCMOD_ENUM_DEFINES_H */