qmod_enum_defines.c (14463B)
1 /**************************************************************************** 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 */ 8 9 /* This file is automatically generated. Do not modify it. Modify the 10 * inc/enum_desc.txt to change enums, elems, or comments. For issues about 11 * the process that creates this file contact the qmod development team. 12 */ 13 14 #include "qmod_enum_defines.h" 15 16 char* e2s_qmod_core_select [CNT_qmod_core_select] = { 17 "QMOD_CORE_0_0_1" , 18 "QMOD_CORE_0_1_0" , 19 "QMOD_CORE_1_0_0" , 20 "QMOD_CORE_0_1_1" , 21 "QMOD_CORE_1_0_1" , 22 "QMOD_CORE_1_1_1" , 23 "QMOD_CORE_ILLEGAL" 24 }; /* e2s_qmod_core_select */ 25 26 int e2n_qmod_core_select [CNT_qmod_core_select] = { 27 1 , 28 2 , 29 4 , 30 3 , 31 5 , 32 7 , 33 0 34 }; /* e2n_qmod_core_select */ 35 36 char* e2s_qmod_lane_select [CNT_qmod_lane_select] = { 37 "QMOD_LANE_0_0_0_1" , 38 "QMOD_LANE_0_0_1_0" , 39 "QMOD_LANE_0_0_1_1" , 40 "QMOD_LANE_0_1_0_0" , 41 "QMOD_LANE_0_1_0_1" , 42 "QMOD_LANE_0_1_1_0" , 43 "QMOD_LANE_0_1_1_1" , 44 "QMOD_LANE_1_0_0_0" , 45 "QMOD_LANE_1_0_0_1" , 46 "QMOD_LANE_1_0_1_0" , 47 "QMOD_LANE_1_0_1_1" , 48 "QMOD_LANE_1_1_0_0" , 49 "QMOD_LANE_1_1_0_1" , 50 "QMOD_LANE_1_1_1_0" , 51 "QMOD_LANE_1_1_1_1" , 52 "QMOD_LANE_BCST" , 53 "QMOD_LANE_ILLEGAL" 54 }; /* e2s_qmod_lane_select */ 55 56 int e2n_qmod_lane_select [CNT_qmod_lane_select] = { 57 1 , 58 2 , 59 3 , 60 4 , 61 5 , 62 6 , 63 7 , 64 8 , 65 9 , 66 10 , 67 11 , 68 12 , 69 13 , 70 14 , 71 15 , 72 15 , 73 0 74 }; /* e2n_qmod_lane_select */ 75 76 char* e2s_qmod_spd_intfc_type [CNT_qmod_spd_intfc_type] = { 77 "QMOD_SPD_ZERO" , 78 "QMOD_SPD_10_X1_SGMII" , 79 "QMOD_SPD_100_X1_SGMII" , 80 "QMOD_SPD_1000_X1_SGMII" , 81 "QMOD_SPD_2500_X1" , 82 "QMOD_SPD_10_SGMII" , 83 "QMOD_SPD_100_SGMII" , 84 "QMOD_SPD_1000_SGMII" , 85 "QMOD_SPD_2500" , 86 "QMOD_SPD_5000" , 87 "QMOD_SPD_1000_XFI" , 88 "QMOD_SPD_5000_XFI" , 89 "QMOD_SPD_10000_XFI" , 90 "QMOD_SPD_10600_XFI_HG" , 91 "QMOD_SPD_10000_HI" , 92 "QMOD_SPD_10000" , 93 "QMOD_SPD_12000_HI" , 94 "QMOD_SPD_13000" , 95 "QMOD_SPD_15000" , 96 "QMOD_SPD_16000" , 97 "QMOD_SPD_20000" , 98 "QMOD_SPD_20000_SCR" , 99 "QMOD_SPD_21000" , 100 "QMOD_SPD_25455" , 101 "QMOD_SPD_31500" , 102 "QMOD_SPD_31500_MLD" , 103 "QMOD_SPD_40G_X4" , 104 "QMOD_SPD_42G_X4" , 105 "QMOD_SPD_40G_XLAUI" , 106 "QMOD_SPD_42G_XLAUI" , 107 "QMOD_SPD_10000_X2" , 108 "QMOD_SPD_10000_HI_DXGXS" , 109 "QMOD_SPD_10000_DXGXS" , 110 "QMOD_SPD_10000_HI_DXGXS_SCR" , 111 "QMOD_SPD_10000_DXGXS_SCR" , 112 "QMOD_SPD_10500_HI" , 113 "QMOD_SPD_10500_HI_DXGXS" , 114 "QMOD_SPD_12773_HI_DXGXS" , 115 "QMOD_SPD_12773_DXGXS" , 116 "QMOD_SPD_15750_HI_DXGXS" , 117 "QMOD_SPD_20G_MLD_DXGXS" , 118 "QMOD_SPD_21G_HI_MLD_DXGXS" , 119 "QMOD_SPD_20G_DXGXS" , 120 "QMOD_SPD_21G_HI_DXGXS" , 121 "QMOD_SPD_100G_CR10" , 122 "QMOD_SPD_107G_HG_CR10" , 123 "QMOD_SPD_120G_CR12" , 124 "QMOD_SPD_127G_HG_CR12" , 125 "QMOD_SPD_4000" , 126 "QMOD_SPD_10_X1_10" , 127 "QMOD_SPD_100_X1_10" , 128 "QMOD_SPD_1000_X1_10" , 129 "QMOD_SPD_10_X1_12P5" , 130 "QMOD_SPD_100_X1_12P5" , 131 "QMOD_SPD_1000_X1_12P5" , 132 "QMOD_SPD_2500_X1_12P5" , 133 "QMOD_SPD_ILLEGAL" 134 }; /* e2s_qmod_spd_intfc_type */ 135 136 int e2n_qmod_spd_intfc_type [CNT_qmod_spd_intfc_type] = { 137 0 , 138 10 , 139 100 , 140 1000 , 141 2500 , 142 10 , 143 100 , 144 1000 , 145 2500 , 146 5000 , 147 5000 , 148 5000 , 149 10000 , 150 10560 , 151 10000 , 152 10000 , 153 12000 , 154 13000 , 155 15000 , 156 16000 , 157 20000 , 158 20000 , 159 21000 , 160 25000 , 161 31500 , 162 31500 , 163 40000 , 164 40000 , 165 40000 , 166 42000 , 167 10000 , 168 10000 , 169 10000 , 170 10000 , 171 10000 , 172 10500 , 173 10500 , 174 12773 , 175 12773 , 176 15750 , 177 20000 , 178 20000 , 179 20000 , 180 21000 , 181 100000 , 182 107000 , 183 120000 , 184 127000 , 185 4000 , 186 10 , 187 100 , 188 1000 , 189 10 , 190 100 , 191 1000 , 192 2500 , 193 0 194 }; /* e2n_qmod_spd_intfc_type */ 195 196 char* e2s_qmod_regacc_type [CNT_qmod_regacc_type] = { 197 "QMOD_REGACC_CL22" , 198 "QMOD_REGACC_CL45" , 199 "QMOD_REGACC_TOTSC" , 200 "QMOD_REGACC_SBUS_FD" , 201 "QMOD_REGACC_SBUS_BD" , 202 "QMOD_REGACC_ILLEGAL" 203 }; /* e2s_qmod_regacc_type */ 204 205 char* e2s_qmod_port_type [CNT_qmod_port_type] = { 206 "QMOD_SINGLE_PORT" , 207 "QMOD_MULTI_PORT" , 208 "QMOD_DXGXS" , 209 "QMOD_TRI1_PORT" , 210 "QMOD_TRI2_PORT" , 211 "QMOD_PORT_MODE_ILLEGAL" 212 }; /* e2s_qmod_port_type */ 213 214 char* e2s_qmod_diag_type [CNT_qmod_diag_type] = { 215 "QMOD_DIAG_GENERAL" , 216 "QMOD_DIAG_TOPOLOGY" , 217 "QMOD_DIAG_LINK" , 218 "QMOD_DIAG_SPEED" , 219 "QMOD_DIAG_ANEG" , 220 "QMOD_DIAG_TFC" , 221 "QMOD_DIAG_AN_TIMERS" , 222 "QMOD_DIAG_STATE" , 223 "QMOD_DIAG_DEBUG" , 224 "QMOD_DIAG_IEEE" , 225 "QMOD_DIAG_EEE" , 226 "QMOD_SERDES_DIAG" , 227 "QMOD_DIAG_ALL" , 228 "QMOD_DIAG_ILLEGAL" 229 }; /* e2s_qmod_diag_type */ 230 231 char* e2s_qmod_pmd_diag_type [CNT_qmod_pmd_diag_type] = { 232 "QMOD_SERDES_DIAG_CORE_CONFIG" , 233 "QMOD_SERDES_DIAG_CORE_STATE" , 234 "QMOD_SERDES_DIAG_LANE_CONFIG" , 235 "QMOD_SERDES_DIAG_LANE_DEBUG_STATUS" , 236 "QMOD_SERDES_DIAG_LANE_STATE" , 237 "QMOD_SERDES_DIAG_LANE_STATE_HDR" , 238 "QMOD_SERDES_DIAG_LANE_STATE_LEGEND" , 239 "QMOD_SERDES_DIAG_CL72_STATUS" , 240 "QMOD_SERDES_DIAG_EYE_DENSITY" , 241 "QMOD_SERDES_DIAG_EYE_SCAN" , 242 "QMOD_SERDES_DIAG_MEAS_EYE_DENSITY_DATA" , 243 "QMOD_SERDES_DIAG_MEAS_EYE_SCAN_DONE" , 244 "QMOD_SERDES_DIAG_MEAS_LOWBER_EYE" , 245 "QMOD_SERDES_DIAG_READ_EYE_SCAN_STRIPE" , 246 "QMOD_SERDES_DIAG_EYE_DENSITY_DATA" , 247 "QMOD_SERDES_DIAG_LOWBER_EYE" , 248 "QMOD_SERDES_DIAG_EYE_SCAN_VERTICAL" , 249 "QMOD_SERDES_DIAG_EYE_SCAN_STRIPE" , 250 "QMOD_SERDES_DIAG_EYE_SCAN_HEADER" , 251 "QMOD_SERDES_DIAG_EYE_SCAN_FOOTER" , 252 "QMOD_SERDES_DIAG_BER_SCAN_TEST" , 253 "QMOD_SERDES_DIAG_READ_BER_SCAN_DATA" , 254 "QMOD_SERDES_DIAG_EYE_MARGIN_PROJ" , 255 "QMOD_SERDES_DIAG_DIG_LPBK" , 256 "QMOD_SERDES_DIAG_MEAS_EYE_SCAN_START" , 257 "QMOD_SERDES_DIAG_ILLEGAL" 258 }; /* e2s_qmod_pmd_diag_type */ 259 260 char* e2s_qmod_an_type [CNT_qmod_an_type] = { 261 "QMOD_CL73" , 262 "QMOD_CL37" , 263 "QMOD_CL73_BAM" , 264 "QMOD_CL37_BAM" , 265 "QMOD_CL37_SGMII" , 266 "QMOD_HPAM" , 267 "QMOD_AN_TYPE_ILLEGAL" 268 }; /* e2s_qmod_an_type */ 269 270 char* e2s_qmod_eye_direction [CNT_qmod_eye_direction] = { 271 "QMOD_EYE_VU" , 272 "QMOD_EYE_VD" , 273 "QMOD_EYE_HL" , 274 "QMOD_EYE_HR" , 275 "QMOD_EYE_ILLEGAL" 276 }; /* e2s_qmod_eye_direction */ 277 278 char* e2s_qmod_tech_ability [CNT_qmod_tech_ability] = { 279 "QMOD_ABILITY_1G_KX" , 280 "QMOD_ABILITY_10G_KX4" , 281 "QMOD_ABILITY_10G_KR" , 282 "QMOD_ABILITY_40G_KR4" , 283 "QMOD_ABILITY_40G_CR4" , 284 "QMOD_ABILITY_100G_CR10" , 285 "QMOD_ABILITY_20G_KR2" , 286 "QMOD_ABILITY_20G_CR2" , 287 "QMOD_ABILITY_ILLEGAL" 288 }; /* e2s_qmod_tech_ability */ 289 290 int e2n_qmod_tech_ability [CNT_qmod_tech_ability] = { 291 0x5 , 292 0x6 , 293 0x7 , 294 0x8 , 295 0x9 , 296 0xa , 297 0x100 , 298 0x101 , 299 0x102 300 }; /* e2n_qmod_tech_ability */ 301 302 char* e2s_qmod_cl37bam_ability [CNT_qmod_cl37bam_ability] = { 303 "QMOD_BAM37ABL_2P5G" , 304 "QMOD_BAM37ABL_5G_X4" , 305 "QMOD_BAM37ABL_6G_X4" , 306 "QMOD_BAM37ABL_10G_HIGIG" , 307 "QMOD_BAM37ABL_10G_CX4" , 308 "QMOD_BAM37ABL_12G_X4" , 309 "QMOD_BAM37ABL_12P5_X4" , 310 "QMOD_BAM37ABL_13G_X4" , 311 "QMOD_BAM37ABL_15G_X4" , 312 "QMOD_BAM37ABL_16G_X4" , 313 "QMOD_BAM37ABL_20G_X4_CX4" , 314 "QMOD_BAM37ABL_20G_X4" , 315 "QMOD_BAM37ABL_21G_X4" , 316 "QMOD_BAM37ABL_25P455G" , 317 "QMOD_BAM37ABL_31P5G" , 318 "QMOD_BAM37ABL_32P7G" , 319 "QMOD_BAM37ABL_40G" , 320 "QMOD_BAM37ABL_10G_X2_CX4" , 321 "QMOD_BAM37ABL_10G_DXGXS" , 322 "QMOD_BAM37ABL_10P5G_DXGXS" , 323 "QMOD_BAM37ABL_12P7_DXGXS" , 324 "QMOD_BAM37ABL_15P75G_R2" , 325 "QMOD_BAM37ABL_20G_X2_CX4" , 326 "QMOD_BAM37ABL_20G_X2" , 327 "QMOD_BAM37ABL_ILLEGAL" 328 }; /* e2s_qmod_cl37bam_ability */ 329 330 char* e2s_qmod_diag_an_type [CNT_qmod_diag_an_type] = { 331 "QMOD_DIAG_AN_DONE" , 332 "QMOD_DIAG_AN_HCD" , 333 "QMOD_DIAG_AN_TYPE_ILLEGAL" 334 }; /* e2s_qmod_diag_an_type */ 335 336 char* e2s_qmod_tier1_function_type [CNT_qmod_tier1_function_type] = { 337 "PCS_BYPASS_CTL" , 338 "INIT_PCS" , 339 "INIT_PMD_SW" , 340 "INIT_PMD" , 341 "PMD_RESET_SEQ" , 342 "PMD_X4_RESET" , 343 "WAIT_SC_DONE" , 344 "ENABLE_SET" , 345 "FECMODE_SET" , 346 "GET_PCS_LINK_STATUS" , 347 "OVERRIDE_SET" , 348 "CREDIT_OVERRIDE_SET" , 349 "ENCODE_SET" , 350 "DECODE_SET" , 351 "CREDIT_CONTROL" , 352 "TX_LANE_CONTROL" , 353 "RX_LANE_CONTROL" , 354 "TX_LANE_DISABLE" , 355 "POWER_CONTROL" , 356 "AUTONEG_SET" , 357 "AUTONEG_GET" , 358 "AUTONEG_CONTROL" , 359 "TSC12_CONTROL" , 360 "CHECK_SC_STATS" , 361 "REG_READ" , 362 "REG_WRITE" , 363 "PRBS_CHECK" , 364 "CJPAT_CRPAT_MODE_SET" , 365 "CJPAT_CRPAT_CHECK" , 366 "QMOD_DIAG" , 367 "PCS_LANE_SWAP" , 368 "PMD_LANE_SWAP" , 369 "PMD_LANE_SWAP_TX" , 370 "PARALLEL_DETECT_CONTROL" , 371 "REVID_READ" , 372 "SOFT_RESET" , 373 "SET_SPD_INTF" , 374 "SET_PORT_MODE" , 375 "EEE_PASSTHRU_SET" , 376 "EEE_PASSTHRU_GET" , 377 "FEC_CONTROL" , 378 "HIGIG2_CONTROL" , 379 "LF_RF_CONTROL" , 380 "RX_FAST_LOCK_CONTROL" , 381 "PMD_CORE_RESET" , 382 "PMD_LANE_RESET" , 383 "AFE_SPEED_UP_DSC_VGA" , 384 "CLAUSE_72_CONTROL" , 385 "PLL_SEQUENCER_CONTROL" , 386 "PLL_LOCK_WAIT" , 387 "PROG_DATA" , 388 "RX_SEQ_CONTROL" , 389 "SET_POLARITY" , 390 "PRBS_CONTROL" , 391 "PRBS_MODE" , 392 "RX_PF_CONTROL" , 393 "RX_VGA_CONTROL" , 394 "CJPAT_CRPAT_CONTROL" , 395 "TX_LOOPBACK_CONTROL" , 396 "TX_PMD_LOOPBACK_CONTROL" , 397 "RX_LOOPBACK_CONTROL" , 398 "RX_P1_SLICER_CONTROL" , 399 "RX_M1_SLICER_CONTROL" , 400 "RX_D_SLICER_CONTROL" , 401 "WAIT_PMD_LOCK" , 402 "FIRMWARE_SET" , 403 "PMD_RESET_BYPASS" , 404 "PMD_OVERRIDE_CONTROL" , 405 "SET_QPORT_SPD" , 406 "SET_QSGMII_EN" , 407 "QMODE_DISABLE_SET" , 408 "PLL_LOCK_GET" , 409 "PMD_LOCK_GET" , 410 "AUTONEG_SET_INIT" , 411 "AUTONEG_ABILITIES_CONTROL" , 412 "AUTONEG_CL37_BASE_ABILITIES" , 413 "AUTONEG_CL37_BAM_OVER1G_ABILITIES" , 414 "AUTONEG_AUTONEG_CONTROL_GET" , 415 "AUTONEG_AUTONEG_LOCAL_ABILITY_GET" , 416 "AUTONEG_AUTONEG_REMOTE_ABILITY_GET" , 417 "AUTONEG_AN_ABILITIES_ENABLES" , 418 "AUTONEG_GET_HT_ENTRIES" , 419 "UPDATE_PORT_MODE_SELECT" , 420 "TX_RX_POLARITY_SET" , 421 "TX_RX_POLARITY_GET" , 422 "TX_PI_CONTROL_GET" , 423 "TX_LANE_DISABLE_SET" , 424 "TX_LANE_DISABLE_GET" , 425 "SPEED_ID_GET" , 426 "PMD_LANE_SWAP_TX_GET" , 427 "PLL_RESET_ENABLE_SET" , 428 "PLL_MODE_SET" , 429 "PCS_LANE_SWAP_GET" , 430 "OSMODE_SET" , 431 "MASTER_PORT_NUM_SET" , 432 "GET_PLLDIV" , 433 "DISABLE_GET" , 434 "FIRMWARE_LOAD" , 435 "PRBS_RX_POLYNOMIAL_SET" , 436 "RX_LANE_CONTROL_SET" , 437 "RX_LANE_CONTROL_GET" , 438 "TRIGGER_SPEED_CHANGE" , 439 "TIER1_FUNCTION_ILLEGAL" 440 }; /* e2s_qmod_tier1_function_type */ 441 442 443 char* e2s_qmod_pll_mode_type [CNT_qmod_pll_mode_type] = { 444 "QMOD_PLL_MODE_DIV_ZERO" , 445 "QMOD_PLL_MODE_DIV_40" , 446 "QMOD_PLL_MODE_DIV_42" , 447 "QMOD_PLL_MODE_DIV_48" , 448 "QMOD_PLL_MODE_DIV_52" , 449 "QMOD_PLL_MODE_DIV_54" , 450 "QMOD_PLL_MODE_DIV_60" , 451 "QMOD_PLL_MODE_DIV_64" , 452 "QMOD_PLL_MODE_DIV_66" , 453 "QMOD_PLL_MODE_DIV_70" , 454 "QMOD_PLL_MODE_DIV_80" , 455 "QMOD_PLL_MODE_DIV_92" , 456 "QMOD_PLL_MODE_DIV_ILLEGAL" 457 }; /* e2s_qmod_pll_mode_type */ 458 459 int e2n_qmod_pll_mode_type [CNT_qmod_pll_mode_type] = { 460 0 , 461 40 , 462 42 , 463 48 , 464 52 , 465 54 , 466 60 , 467 64 , 468 66 , 469 70 , 470 80 , 471 92 , 472 0 473 }; /* e2n_qmod_pll_mode_type */ 474 475 char* e2s_qmod_os_mode_type [CNT_qmod_os_mode_type] = { 476 "QMOD_PMA_OS_MODE_1" , 477 "QMOD_PMA_OS_MODE_2" , 478 "QMOD_PMA_OS_MODE_3" , 479 "QMOD_PMA_OS_MODE_3_3" , 480 "QMOD_PMA_OS_MODE_4" , 481 "QMOD_PMA_OS_MODE_5" , 482 "QMOD_PMA_OS_MODE_7_25" , 483 "QMOD_PMA_OS_MODE_8" , 484 "QMOD_PMA_OS_MODE_8_25" , 485 "QMOD_PMA_OS_MODE_10" , 486 "QMOD_PMA_OS_MODE_ILLEGAL" 487 }; /* e2s_qmod_os_mode_type */ 488 489 int e2n_qmod_os_mode_type [CNT_qmod_os_mode_type] = { 490 1 , 491 2 , 492 3 , 493 33 , 494 4 , 495 5 , 496 725 , 497 8 , 498 825 , 499 9 , 500 0 501 }; /* e2n_qmod_os_mode_type */ 502 503 char* e2s_qmod_scr_mode [CNT_qmod_scr_mode] = { 504 "QMOD_SCR_MODE_BYPASS" , 505 "QMOD_SCR_MODE_66B" , 506 "QMOD_SCR_MODE_80B" , 507 "QMOD_SCR_MODE_64B" 508 }; /* e2s_qmod_scr_mode */ 509 510 int e2n_qmod_scr_mode [CNT_qmod_scr_mode] = { 511 0 , 512 1 , 513 2 , 514 3 515 }; /* e2n_qmod_scr_mode */ 516 517 char* e2s_qmod_encode_mode [CNT_qmod_encode_mode] = { 518 "QMOD_ENCODE_MODE_NONE" , 519 "QMOD_ENCODE_MODE_CL48" , 520 "QMOD_ENCODE_MODE_CL48_2_LANE" , 521 "QMOD_ENCODE_MODE_CL36" , 522 "QMOD_ENCODE_MODE_CL82" , 523 "QMOD_ENCODE_MODE_CL49" , 524 "QMOD_ENCODE_MODE_BRCM" , 525 "QMOD_ENCODE_MODE_ILLEGAL" 526 }; /* e2s_qmod_encode_mode */ 527 528 int e2n_qmod_encode_mode [CNT_qmod_encode_mode] = { 529 0 , 530 1 , 531 2 , 532 3 , 533 4 , 534 5 , 535 6 , 536 7 537 }; /* e2n_qmod_encode_mode */ 538 539 char* e2s_qmod_check_end_mode [CNT_qmod_check_end_mode] = { 540 "QMOD_CL48_CHECK_END_OFF" , 541 "QMOD_CL48_CHECK_END_ON" 542 }; /* e2s_qmod_check_end_mode */ 543 544 char* e2s_qmod_sigdet_filter [CNT_qmod_sigdet_filter] = { 545 "QMOD_SIGDET_FILTER_NONCX4" , 546 "QMOD_SIGDET_FILTER_CX4" 547 }; /* e2s_qmod_sigdet_filter */ 548 549 char* e2s_qmod_blocksync_mode [CNT_qmod_blocksync_mode] = { 550 "QMOD_BLOCKSYNC_MODE_NONE" , 551 "QMOD_BLOCKSYNC_MODE_CL49" , 552 "QMOD_BLOCKSYNC_MODE_CL82" , 553 "QMOD_BLOCKSYNC_MODE_8B10B" , 554 "QMOD_BLOCKSYNC_MODE_FEC" , 555 "QMOD_BLOCKSYNC_MODE_BRCM" , 556 "QMOD_BLOCKSYNC_MODE_ILLEGAL" 557 }; /* e2s_qmod_blocksync_mode */ 558 559 char* e2s_qmod_reorder_mode [CNT_qmod_reorder_mode] = { 560 "QMOD_R_REORDER_MODE_NONE" , 561 "QMOD_R_REORDER_MODE_CL48" , 562 "QMOD_R_REORDER_MODE_CL36" , 563 "QMOD_R_REORDER_MODE_CL36_CL48" 564 }; /* e2s_qmod_reorder_mode */ 565 566 char* e2s_qmod_cl36_mode [CNT_qmod_cl36_mode] = { 567 "QMOD_CL36_DISABLE" , 568 "QMOD_CL36_ENABLE" 569 }; /* e2s_qmod_cl36_mode */ 570 571 char* e2s_qmod_descrambler_mode [CNT_qmod_descrambler_mode] = { 572 "QMOD_R_DESCR1_MODE_BYPASS" , 573 "QMOD_R_DESCR1_MODE_66B" , 574 "QMOD_R_DESCR1_MODE_10B" , 575 "QMOD_R_DESCR1_MODE_ILLEGAL" 576 }; /* e2s_qmod_descrambler_mode */ 577 578 char* e2s_qmod_decoder_mode [CNT_qmod_decoder_mode] = { 579 "QMOD_DECODER_MODE_NONE" , 580 "QMOD_DECODER_MODE_CL49" , 581 "QMOD_DECODER_MODE_BRCM" , 582 "QMOD_DECODER_MODE_ALU" , 583 "QMOD_DECODER_MODE_CL48" , 584 "QMOD_DECODER_MODE_CL36" , 585 "QMOD_DECODER_MODE_CL82" , 586 "QMOD_DECODER_MODE_ILLEGAL" 587 }; /* e2s_qmod_decoder_mode */ 588 589 char* e2s_qmod_deskew_mode [CNT_qmod_deskew_mode] = { 590 "QMOD_R_DESKEW_MODE_BYPASS" , 591 "QMOD_R_DESKEW_MODE_8B_10B" , 592 "QMOD_R_DESKEW_MODE_BRCM_66B" , 593 "QMOD_R_DESKEW_MODE_CL82_66B" , 594 "QMOD_R_DESKEW_MODE_CL36_10B" , 595 "QMOD_R_DESKEW_MODE_ILLEGAL" 596 }; /* e2s_qmod_deskew_mode */ 597 598 char* e2s_qmod_descrambler2_mode [CNT_qmod_descrambler2_mode] = { 599 "QMOD_DESC2_MODE_NONE" , 600 "QMOD_DESC2_MODE_CL49" , 601 "QMOD_DESC2_MODE_BRCM" , 602 "QMOD_DESC2_MODE_ALU" , 603 "QMOD_DESC2_MODE_CL48" , 604 "QMOD_DESC2_MODE_CL36" , 605 "QMOD_DESC2_MODE_CL82" , 606 "QMOD_DESC2_MODE_ILLEGAL" 607 }; /* e2s_qmod_descrambler2_mode */ 608 609 char* e2s_qmod_byte_del_mode [CNT_qmod_byte_del_mode] = { 610 "QMOD_R_DESC2_BYTE_DELETION_100M" , 611 "QMOD_R_DESC2_BYTE_DELETION_10M" , 612 "QMOD_R_DESC2_BYTE_DELETION_NONE" 613 }; /* e2s_qmod_byte_del_mode */ 614 615 char* e2s_qmod_decode_descr_mode [CNT_qmod_decode_descr_mode] = { 616 "QMOD_R_DEC1_DESCR_MODE_NONE" , 617 "QMOD_R_DEC1_DESCR_MODE_BRCM64B66B" 618 }; /* e2s_qmod_decode_descr_mode */ 619 620 char* e2s_qmod_ref_clk_t [CNT_qmod_ref_clk_t] = { 621 "QMODREFCLK156MHZ" , 622 "QMODREFCLK125MHZ" , 623 "QMODREFCLKCOUNT" 624 }; /* e2s_qmod_ref_clk_t */ 625