qmod_cfg_seq.c (245944B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 #ifndef _DV_TB_ 8 #define _SDK_QMOD_ 1 9 #endif 10 11 #ifdef _DV_TB_ 12 #include <stdint.h> 13 #include "qmod_main.h" 14 #include "qmod_defines.h" 15 #include "qePCSRegEnums.h" 16 /*#include "tePMDRegEnums.h"*/ 17 #include "phy_tsc_iblk.h" 18 #include "bcmi_qtc_xgxs_defs.h" 19 #endif /* _DV_TB_ */ 20 21 #ifdef _SDK_QMOD_ 22 #include "phy_tsc_iblk.h" 23 #include <phymod/phymod.h> 24 #include <phymod/phymod_system.h> 25 #include <phymod/phymod_util.h> 26 #include <phymod/phymod_debug.h> 27 #include <phymod/chip/bcmi_qtce_xgxs_defs.h> 28 #include "qmod_enum_defines.h" 29 #include "qmod.h" 30 #include "qmod_device.h" 31 #include "qmod_sc_lkup_table.h" 32 #include "qePCSRegEnums.h" 33 #endif /* _SDK_QMOD_ */ 34 35 #ifndef PHYMOD_ST 36 #ifdef _SDK_QMOD_ 37 #define PHYMOD_ST const phymod_access_t 38 #else 39 #define PHYMOD_ST qmod_st 40 #endif /* _SDK_QMOD_ */ 41 #endif /* PHYMOD_ST */ 42 43 #ifdef _SDK_QMOD_ 44 #define QMOD_DBG_IN_FUNC_INFO(pc) \ 45 PHYMOD_VDBG(QMOD_DBG_FUNC,pc,("-22%s: Adr:%08x Ln:%02d\n", __func__, pc->addr, pc->lane_mask)) 46 #define QMOD_DBG_OUT_FUNC_INFO(pc) \ 47 PHYMOD_VDBG(QMOD_DBG_FUNC,pc,("-22%s: Adr:%08x Ln:%02d\n", __func__, pc->addr, pc->lane_mask)) 48 #endif 49 50 #ifdef _DV_TB_ 51 #define QMOD_DBG_IN_FUNC_INFO(pc) \ 52 PHYMOD_VDBG(QMOD_DBG_FUNC, pc, \ 53 ("QMOD IN Function : %s Port Add : %d Lane No: %d\n", \ 54 __func__, pc->prt_ad, pc->this_lane)) 55 #define QMOD_DBG_OUT_FUNC_INFO(pc) \ 56 PHYMOD_VDBG(QMOD_DBG_FUNC, pc, \ 57 ("QMOD OUT of Function : %s Port Add : %d Lane No: %d\n", \ 58 __func__, pc->prt_ad, pc->this_lane)) 59 int phymod_debug_check(uint32_t flags, PHYMOD_ST *pc); 60 #endif 61 62 static qmod_sc_pmd_entry_st qmod_sc_pmd_entry[] = { 63 /*SPD_10M 0*/ { 1, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 64 /*SPD_10M 1*/ { 1, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 65 /*SPD_100M 2*/ { 1, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 66 /*SPD_1000M 3*/ { 1, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 67 /*SPD_1G_CX1 4*/ { 1, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 68 /*SPD_1G_KX1 5*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 1}, 69 /*SPD_2p5G 6*/ { 1, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 70 /*SPD_5G_X1 7*/ { 1, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_40, 1, 0, 0}, 71 /*SPD_10G_CX4 8*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 72 /*SPD_10G_KX4 9*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 73 /*SPD_10G_X4 10*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 74 /*SPD_13G_X4 11*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_52, 0, 0, 1}, 75 /*SPD_15G_X4 12*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_60, 0, 0, 1}, 76 /*SPD_16G_X4 13*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_64, 0, 0, 1}, 77 /*SPD_20G_CX4 14*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 78 /*SPD_10G_CX2 15*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_40, 0, 0, 1}, 79 /*SPD_10G_X2 16*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_40, 1, 0, 1}, 80 /*SPD_20G_X4 17*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_40, 1, 0, 1}, 81 /*SPD_10p5G_X2 18*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_42, 1, 0, 0}, 82 /*SPD_21G_X4 19*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_42, 1, 0, 0}, 83 /*SPD_12p7G_X2 20*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_42, 1, 0, 0}, 84 /*SPD_25p45G_X4 21*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_42, 1, 0, 0}, 85 /*SPD_15p75G_X2 22*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_52, 1, 0, 0}, 86 /*SPD_31p5G_X4 23*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_52, 1, 0, 0}, 87 /*SPD_31p5G_KR4 24*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_52, 1, 0, 0}, 88 /*SPD_20G_CX2 25*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 89 /*SPD_20G_X2 26*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 90 /*SPD_40G_X4 27*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 91 /*SPD_10G_KR1 28*/ { 0, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 92 /*SPD_10p6_X1 29*/ { 0, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_70, 1, 0, 0}, 93 /*SPD_20G_KR2 30*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 94 /*SPD_20G_CR2 31*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 95 /*SPD_21G_X2 32*/ { 2, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_70, 1, 0, 0}, 96 /*SPD_40G_KR4 33*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 97 /*SPD_40G_CR4 34*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 98 /*SPD_42G_X4 35*/ { 4, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_70, 1, 0, 0}, 99 /*SPD_100G_CR10 36*/ {10, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 100 /*SPD_107G_CR10 37*/ {10, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_70, 1, 0, 0}, 101 /*SPD_120G_X12 38*/ {12, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_66, 1, 0, 0}, 102 /*SPD_127G_X12 39*/ {12, QMOD_PMA_OS_MODE_1, QMOD_PLL_MODE_DIV_70, 1, 0, 0}, 103 /*SPD_ILLEGAL 40*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 104 /*SPD_ILLEGAL 41*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 105 /*SPD_ILLEGAL 42*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 106 /*SPD_ILLEGAL 43*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 107 /*SPD_ILLEGAL 44*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 108 /*SPD_ILLEGAL 45*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 109 /*SPD_ILLEGAL 46*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 110 /*SPD_ILLEGAL 47*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 111 /*SPD_ILLEGAL 48*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 112 /*SPD_5G_KR1 49*/ { 0, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 113 /*SPD_10p5G_X4 50*/ { 4, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_42, 0, 0, 0}, 114 /*SPD_ILLEGAL 51*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 115 /*SPD_ILLEGAL 52*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0}, 116 /*SPD_10M_10p3125 53*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 117 /*SPD_100M_10p3125 54*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 118 /*SPD_1000M_10p3125 55*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 119 /*SPD_2p5G_X1_10p3125 56*/ { 1, QMOD_PMA_OS_MODE_3_3,QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 120 /*SPEED_10M_X1_10 : 57*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 121 /*SPEED_100M_X1_10 : 58*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 122 /*SPEED_1000M_X1_10 : 59*/ { 1, QMOD_PMA_OS_MODE_8_25, QMOD_PLL_MODE_DIV_66, 0, 0, 0}, 123 /*SPEED_4G_X1_10 : 60*/ { 1, QMOD_PMA_OS_MODE_2, QMOD_PLL_MODE_DIV_64, 0, 0, 0}, 124 /*SPD_ILLEGAL 61*/ { 0, QMOD_PMA_OS_MODE_5, QMOD_PLL_MODE_DIV_40, 0, 0, 0} 125 }; 126 127 int _qmod_set_port_mode_select(PHYMOD_ST *pc); 128 int _qmod_configure_sc_speed_configuration(PHYMOD_ST* pc); 129 int _qmod_init_pcs_fs(PHYMOD_ST* pc); 130 int _qmod_init_pcs_an(PHYMOD_ST* pc); 131 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc); 132 133 #ifdef _DV_TB_ 134 int qmod_set_an_port_mode(PHYMOD_ST* pc); 135 int qmod_autoneg_set(PHYMOD_ST* pc); 136 int qmod_autoneg_control(PHYMOD_ST* pc); 137 int qmod_an_abilities_enables(PHYMOD_ST* pc,int sub_port); 138 int qmod_an_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port); 139 int qmod_autoneg_abilities_controls(PHYMOD_ST* pc,int sub_port); 140 int qmod_autoneg_cl37_base_abilities(PHYMOD_ST* pc,int sub_port); 141 int qmod_autoneg_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port); 142 int qmod_autoneg_cl37_bam_over1g_abilities(PHYMOD_ST* pc,int sub_port); 143 int qmod_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status); 144 int qmod_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pat, int check_mode); 145 int qmod_prbs_control(PHYMOD_ST* pc, int prbs_enable); 146 int qmod_prbs_rx_enable_set(PHYMOD_ST* pc, int enable); 147 int qmod_prbs_tx_enable_set(PHYMOD_ST* pc, int enable); 148 int qmod_prbs_rx_invert_data_set(PHYMOD_ST* pc, int invert_data); 149 int qmod_prbs_rx_check_mode_set(PHYMOD_ST* pc, int check_mode); 150 int qmod_prbs_tx_invert_data_set(PHYMOD_ST* pc, int invert_data); 151 int qmod_prbs_tx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial); 152 int qmod_prbs_rx_polynomial_set(PHYMOD_ST* pc, prbs_polynomial_type_t prbs_polynomial); 153 int qmod_pmd_lane_swap(PHYMOD_ST *pc); 154 int qmod_check_sc_stats(PHYMOD_ST* pc); 155 int qmod_disable_set(PHYMOD_ST* pc); 156 int qmod_credit_control(PHYMOD_ST* pc, int enable); 157 int qmod_tx_lane_control_set(PHYMOD_ST* pc, tx_lane_disable_type_t tx_dis_type); 158 int qmod_pll_lock_get(PHYMOD_ST* pc, int* lockStatus); 159 #endif /* _DV_TB_ */ 160 161 /** 162 @brief update the port mode 163 @param pc handle to current TSCE context (#PHYMOD_ST) 164 @param pll_restart Indicates if required to restart PLL. 165 @returns The value PHYMOD_E_NONE upon successful completion 166 */ 167 int qmod_update_port_mode( PHYMOD_ST *pc, int *pll_restart) 168 { 169 MAIN_SETUPr_t mode_reg; 170 READ_MAIN_SETUPr(pc, &mode_reg); 171 172 MAIN_SETUPr_SINGLE_PORT_MODEf_SET(mode_reg, 0); 173 MODIFY_MAIN_SETUPr(pc, mode_reg); 174 return PHYMOD_E_NONE ; 175 } 176 177 /*! 178 @brief This function reads TX-PLL PLL_LOCK bit. 179 @param pc handle to current TSCE context (#PHYMOD_ST) 180 @param lockStatus reference which is updated with lock status. 181 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 182 @details Read PLL lock status. Returns 1 or 0 (locked/not) 183 */ 184 185 int qmod_pll_lock_get(PHYMOD_ST* pc, int* lockStatus) 186 { 187 PMD_X1_STSr_t reg_pmd_x1_sts; 188 QMOD_DBG_IN_FUNC_INFO(pc); 189 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 190 191 *lockStatus = PMD_X1_STSr_PLL_LOCK_STSf_GET(reg_pmd_x1_sts); 192 return PHYMOD_E_NONE; 193 } 194 195 /** 196 @brief This function reads TX-PMD PMD_LOCK bit. 197 @param pc handle to current TSCE context (#PHYMOD_ST) 198 @param lockStatus reference which is updated with pmd_lock status 199 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 200 @details Read PMD lock status Returns 1 or 0 (locked/not) 201 */ 202 203 int qmod_pmd_lock_get(PHYMOD_ST* pc, uint32_t * lockStatus) 204 { 205 PMD_X1_STSr_t reg_pmd_x1_sts; 206 QMOD_DBG_IN_FUNC_INFO(pc); 207 READ_PMD_X1_STSr(pc, ®_pmd_x1_sts); 208 209 *lockStatus = PMD_X1_STSr_TX_CLK_VLD_STSf_GET(reg_pmd_x1_sts); 210 return PHYMOD_E_NONE; 211 } 212 213 #ifdef _DV_TB_ 214 /* 215 @brief This function waits for TX-PLL PLL_LOCK bit. The register is one copy 216 @param pc handle to current TSCE context (#PHYMOD_ST) 217 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 218 @details Wait for PLL to lock. Cannot be used in SDK. 219 */ 220 221 int qmod_pll_lock_wait(PHYMOD_ST* pc, int timeOutValue) 222 { 223 int rv; 224 QMOD_DBG_IN_FUNC_INFO(pc); 225 226 rv = qmod_regbit_set_wait_check(pc, 227 0x9012, 228 1, 1, timeOutValue); 229 /* TBD PMD_X1_STATUS_PLL_LOCK_STS_MASK, 1, timeOutValue); */ 230 if (rv == SOC_E_TIMEOUT) { 231 PHYMOD_DEBUG_ERROR(("%-22s ERROR: p=%0d Timeout PLL lock:\n", __func__, pc->port)); 232 return (SOC_E_TIMEOUT); 233 } 234 return PHYMOD_E_NONE; 235 } 236 #endif 237 238 #ifdef _DV_TB_ 239 /* 240 @brief This function waits for the the RX-PMD to lock. 241 @param pc handle to current TSCE context (#PHYMOD_ST) 242 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 243 @details This function has a time out limit (TE_PLL_WAIT*50) micro-second in driver. 244 or TE_PLL_WAIT/20 pulling count in simualtion, if per_lane_control is set. Otherwise, 245 if per_lane_control==0, it reads back PMD_LIVE_STATUS and put it on accData. 246 */ 247 int qmod_wait_pmd_lock(PHYMOD_ST* pc, int timeOutValue, int* lockStatus) 248 { 249 int rv; 250 PMD_X4_STSr_t reg_pmd_x4_stats; 251 QMOD_DBG_IN_FUNC_INFO(pc); 252 253 PMD_X4_STSr_CLR(reg_pmd_x4_stats); 254 255 if(pc->per_lane_control) { 256 rv = qmod_regbit_set_wait_check(pc, 0xc012, 1,1,timeOutValue); 257 /* TBD PMD_X4_STATUS_RX_LOCK_STS_MASK,1,timeOutValue); */ 258 259 if (rv == SOC_E_TIMEOUT) { 260 PHYMOD_DEBUG_ERROR(("%-22s ERROR: P=%0d Timeout RX PMD lock:\n", __func__, pc->port)); 261 pc->accData = 0; 262 *lockStatus = 0; 263 return rv; 264 } else { 265 pc->accData = 1; 266 *lockStatus = 1; 267 } 268 } else { 269 READ_PMD_X4_STSr(pc, ®_pmd_x4_stats); 270 if(PMD_X4_STSr_RX_LOCK_STSf_GET(reg_pmd_x4_stats)) { 271 pc->accData = 1; 272 *lockStatus = 1; 273 } else { 274 pc->accData = 0; 275 *lockStatus = 0; 276 } 277 } 278 return (PHYMOD_E_NONE); 279 } 280 #endif 281 282 /** 283 @brief controls PCS Bypass Control function. 284 @param pc handle to current TSCE context (#PHYMOD_ST) 285 @param cntl Control value (bypass, un-bypass) 286 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 287 @details Set cntl <B>0 to disable</B> PCS and <B>1 to enable</B> PCS 288 When bypassed, PCS relinquishes control of PMD resets and PCS logic programming. 289 TEMod can take complete control of PMD programming. Bypass is also used in ILKN 290 mode where the PCS is not used. 291 292 */ 293 int qmod_pcs_bypass_ctl (PHYMOD_ST* pc, int cntl) 294 { 295 /* remove this function. */ 296 return PHYMOD_E_FAIL; 297 } 298 299 #ifdef _DV_TB_ 300 /** 301 @brief Controls PMD datapath resets. 302 @param pc handle to current TSCE context (#PHYMOD_ST) 303 @param cntl Controls if PMD should be reset or unset 304 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 305 @details Set cntl arg <B>0</B>:disable <B>1</B>: enable 306 The PMD datapath is reset even if PCS is actively controlling PMD resets. 307 There are two types of control. One per lane and one per Core. 308 */ 309 int qmod_pmd_reset_bypass (PHYMOD_ST* pc, int cntl) /* PMD_RESET_BYPASS */ 310 { 311 int lnCntl, coreCntl; 312 lnCntl = cntl & 0x10 ; 313 coreCntl = cntl & 0x1 ; 314 PMD_X4_OVRRr_t reg_pmd_x4_or; 315 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 316 PMD_X1_OVRRr_t reg_pmd_x1_or; 317 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 318 SC_X4_CTLr_t reg_sc_ctrl; 319 320 QMOD_DBG_IN_FUNC_INFO(pc); 321 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 322 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 323 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 324 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 325 SC_X4_CTLr_CLR(reg_sc_ctrl); 326 327 if (lnCntl) { 328 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 1); 329 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 330 331 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 0); 332 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 333 334 /* toggle added */ 335 PMD_X4_OVRRr_CLR(reg_pmd_x4_or); 336 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 337 338 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 339 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 340 341 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 342 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 343 344 } else { 345 PMD_X4_OVRRr_LN_DP_H_RSTB_OENf_SET(reg_pmd_x4_or, 0); 346 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_OVRRr(pc, reg_pmd_x4_or)); 347 348 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl, 1); 349 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 350 } 351 352 if (coreCntl) { 353 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 1); 354 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 355 356 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 0); 357 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 358 359 /* toggle added */ 360 PMD_X1_OVRRr_CLR(reg_pmd_x1_or); 361 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 362 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 363 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 364 365 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 366 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 367 368 } else { 369 PMD_X1_OVRRr_CORE_DP_H_RSTB_OENf_SET(reg_pmd_x1_or, 0); 370 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_OVRRr(pc, reg_pmd_x1_or)); 371 372 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl, 1); 373 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc, reg_pmd_x1_ctrl)); 374 } 375 376 /* sw_speed_change toggled */ 377 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 378 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 379 380 SC_X4_CTLr_CLR(reg_sc_ctrl); 381 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 1); 382 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_sc_ctrl)); 383 384 return PHYMOD_E_NONE; 385 } /* PMD_RESET_BYPASS */ 386 #endif 387 388 #ifdef _SDK_QMOD_ 389 /*! 390 \brief Controls the init setting/resetting of autoneg registers. 391 \param pc handle to current TSCE context (#PHYMOD_ST) 392 \param qmod_an_init_t structure with all the onr time autoneg init cfg. 393 \returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 394 \details Get aneg features via #qmod_an_init_t. 395 This does not start the autoneg. That is done in qmod_autoneg_control 396 397 */ 398 int qmod_autoneg_set_init(PHYMOD_ST* pc, qmod_an_init_t *an_init_st) /* AUTONEG_SET */ 399 { 400 return PHYMOD_E_NONE; 401 } 402 #endif 403 404 #ifdef _SDK_QMOD_ 405 /*! 406 \brief Controls the setting/resetting of autoneg timers. 407 \param pc handle to current TSCE context (#PHYMOD_ST) 408 \returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 409 \details 410 Get aneg features via #PHYMOD_ST->an_tech_ability and write the pages 411 This does not start the autoneg. That is done in qmod_autoneg_control 412 413 */ 414 int qmod_autoneg_timer_init(PHYMOD_ST* pc) /* AUTONEG timer set*/ 415 { 416 /* 417 PHYMOD_ST pc_10G_X1; 418 PHYMOD_ST* pc_10G_X1_tmp; 419 PHYMOD_ST pc_40G_X4; 420 PHYMOD_ST* pc_40G_X4_tmp; 421 PHYMOD_ST pc_100G_X4; 422 PHYMOD_ST* pc_100G_X4_tmp; 423 */ 424 /* MAIN_SETUPr_t reg_main_setup; */ 425 426 CL37_RESTARTr_t reg_cl37_restart_timers; 427 CL37_ACKr_t reg_cl37_ack_timers; 428 /* CL37_ERRr_t reg_cl37_err_timers; */ 429 /* CL37_SYNC_STS_FILTER_TMRr_t reg_an_sync_stat_fil_timer; */ 430 LNK_UP_TYPEr_t reg_link_up_timer; 431 SGMII_CL37_TMR_TYPEr_t reg_an_cl37_sgmii_tmr; 432 /* MAIN_TICK_CTL1r_t reg_tick_ctrl; */ 433 /* MAIN_TICK_CTL0r_t reg_tick_ctrl0; */ 434 IGNORE_LNK_TMR_TYPEr_t reg_ignore_link_timers; 435 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_t reg_inhbt_not_cl72_timers; 436 437 #if 0 438 BAM_SPD_PRI_5_0r_t reg_bam_pri5; 439 OUI_LWRr_t reg_an_oui_lower; 440 OUI_UPRr_t reg_an_oui_upper; 441 SC_X1_TX_RST_CNTr_t reg_sc_rst_cnt; 442 #endif 443 444 /*0x9250 AN_X1_TIMERS_cl37_restart */ 445 CL37_RESTARTr_CLR(reg_cl37_restart_timers); 446 /* coverity[operator_confusion] */ 447 CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_SET(reg_cl37_restart_timers, 0x29a); 448 PHYMOD_IF_ERR_RETURN(WRITE_CL37_RESTARTr(pc, reg_cl37_restart_timers)); 449 450 /*0x9251 AN_X1_TIMERS_cl37_ack */ 451 CL37_ACKr_CLR(reg_cl37_ack_timers); 452 /* coverity[operator_confusion] */ 453 CL37_ACKr_CL37_ACK_TIMER_PERIODf_SET(reg_cl37_ack_timers, 0x29a); 454 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ACKr(pc, reg_cl37_ack_timers)); 455 456 #if 0 457 /*0x9252 AN_X1_TIMERS_cl37_error */ 458 CL37_ERRr_CLR(reg_cl37_err_timers); 459 data = pc->cl37_error_timer_period; 460 CL37_ERRr_CL37_ERROR_TIMER_PERIODf_SET(reg_cl37_err_timers, data); 461 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ERRr(pc, reg_cl37_err_timers)); 462 463 /*0x9253 AN_X1_TIMERS_cl37_sync_status_filter_timer*/ 464 data = pc->cl37_sync_status_filter; 465 CL37_SYNC_STS_FILTER_TMRr_CLR(reg_an_sync_stat_fil_timer); 466 CL37_SYNC_STS_FILTER_TMRr_CL37_SYNC_STATUS_FILTER_TIMER_PERIODf_SET(reg_an_sync_stat_fil_timer, data); 467 PHYMOD_IF_ERR_RETURN(WRITE_CL37_SYNC_STS_FILTER_TMRr(pc, reg_an_sync_stat_fil_timer)); 468 #endif 469 470 /*TBD::0x9254 AN_X1_TIMERS_sgmii_cl73_timer_type*/ 471 SGMII_CL37_TMR_TYPEr_CLR(reg_an_cl37_sgmii_tmr); 472 /* coverity[operator_confusion] */ 473 SGMII_CL37_TMR_TYPEr_SGMII_TIMERf_SET(reg_an_cl37_sgmii_tmr, 0x6b); 474 PHYMOD_IF_ERR_RETURN(WRITE_SGMII_CL37_TMR_TYPEr(pc, reg_an_cl37_sgmii_tmr)); 475 476 /*TBD::0x9255 AN_X1_TIMERS_link_up_typ*/ 477 LNK_UP_TYPEr_CLR(reg_link_up_timer); 478 LNK_UP_TYPEr_SET(reg_link_up_timer, 0x29a); 479 PHYMOD_IF_ERR_RETURN(WRITE_LNK_UP_TYPEr(pc, reg_link_up_timer)); 480 481 /*0x9256 AN_X1_TIMERS_ignore_link */ 482 IGNORE_LNK_TMR_TYPEr_CLR(reg_ignore_link_timers); 483 IGNORE_LNK_TMR_TYPEr_SET(reg_ignore_link_timers, 0x29a); 484 PHYMOD_IF_ERR_RETURN(WRITE_IGNORE_LNK_TMR_TYPEr(pc, reg_ignore_link_timers)); 485 486 /*0x9256 AN_X1_TIMERS_link_fail_inhbt_tmr_not_cl72 */ 487 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_CLR(reg_inhbt_not_cl72_timers); 488 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_SET(reg_inhbt_not_cl72_timers, 0x8382); 489 PHYMOD_IF_ERR_RETURN(WRITE_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr(pc, reg_inhbt_not_cl72_timers)); 490 491 #if 0 492 /*TBD::0x9263 sc_x1_control_tx_reset_count*/ 493 data = pc->tx_reset_count; 494 SC_X1_TX_RST_CNTr_CLR(reg_sc_rst_cnt); 495 SC_X1_TX_RST_CNTr_TX_RESET_COUNTf_SET(reg_sc_rst_cnt, data); 496 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_TX_RST_CNTr(pc, reg_sc_rst_cnt)); 497 498 /*0x9240 AN_X1_CONTROL_oui_upper */ 499 data = (pc->oui_upper_data & 0xff); 500 OUI_UPRr_CLR(reg_an_oui_upper); 501 OUI_UPRr_OUI_UPPER_DATAf_SET(reg_an_oui_upper, data); 502 PHYMOD_IF_ERR_RETURN(WRITE_OUI_UPRr(pc, reg_an_oui_upper)); 503 504 /*0x9241 AN_X1_CONTROL_oui_lower */ 505 data = ((pc->oui_lower_data)); 506 OUI_LWRr_CLR(reg_an_oui_lower); 507 OUI_LWRr_OUI_LOWER_DATAf_SET(reg_an_oui_lower, data); 508 PHYMOD_IF_ERR_RETURN(WRITE_OUI_LWRr(pc, reg_an_oui_lower)); 509 510 /*0x9242 AN_X1_CONTROL_BAM_SPEED_PRI_5_0 */ 511 data = ((pc->bam_spd_pri_5_0)); 512 BAM_SPD_PRI_5_0r_CLR(reg_bam_pri5); 513 BAM_SPD_PRI_5_0r_SET(reg_bam_pri5, data); 514 PHYMOD_IF_ERR_RETURN(WRITE_BAM_SPD_PRI_5_0r(pc, reg_bam_pri5)); 515 #endif 516 517 518 return PHYMOD_E_NONE; 519 } 520 #endif 521 522 #ifdef _DV_TB_ 523 /** 524 @brief Controls the setting/resetting of autoneg advertisement registers. 525 @param pc handle to current TSCE context (#PHYMOD_ST) 526 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 527 @details 528 Get aneg features via #PHYMOD_ST->an_tech_ability and write the pages 529 This does not start the autoneg. That is done in qmod_autoneg_control 530 531 */ 532 int qmod_autoneg_abilities_controls(PHYMOD_ST* pc, int sub_port) 533 { 534 AN_X4_ABI_SP0_CTLSr_t reg_an_ctrl_sp0; 535 AN_X4_ABI_SP1_CTLSr_t reg_an_ctrl_sp1; 536 AN_X4_ABI_SP2_CTLSr_t reg_an_ctrl_sp2; 537 AN_X4_ABI_SP3_CTLSr_t reg_an_ctrl_sp3; 538 539 if(sub_port == 0){ 540 AN_X4_ABI_SP0_CTLSr_CLR(reg_an_ctrl_sp0); 541 AN_X4_ABI_SP0_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp0, pc->an_good_trap); 542 AN_X4_ABI_SP0_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp0, pc->an_good_check_trap); 543 AN_X4_ABI_SP0_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp0, pc->linkfailtimer_dis); 544 AN_X4_ABI_SP0_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp0, pc->linkfailtimerqua_en); 545 AN_X4_ABI_SP0_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp0, pc->an_fail_cnt); 546 AN_X4_ABI_SP0_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp0, pc->an_oui_ctrl); 547 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_CTLSr(pc, reg_an_ctrl_sp0)); 548 }else if(sub_port == 1){ 549 AN_X4_ABI_SP1_CTLSr_CLR(reg_an_ctrl_sp1); 550 AN_X4_ABI_SP1_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp1, pc->an_good_trap); 551 AN_X4_ABI_SP1_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp1, pc->an_good_check_trap); 552 AN_X4_ABI_SP1_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp1, pc->linkfailtimer_dis); 553 AN_X4_ABI_SP1_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp1, pc->linkfailtimerqua_en); 554 AN_X4_ABI_SP1_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp1, pc->an_fail_cnt); 555 AN_X4_ABI_SP1_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp1, pc->an_oui_ctrl); 556 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_CTLSr(pc, reg_an_ctrl_sp1)); 557 }else if(sub_port == 2){ 558 AN_X4_ABI_SP2_CTLSr_CLR(reg_an_ctrl_sp2); 559 AN_X4_ABI_SP2_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp2, pc->an_good_trap); 560 AN_X4_ABI_SP2_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp2, pc->an_good_check_trap); 561 AN_X4_ABI_SP2_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp2, pc->linkfailtimer_dis); 562 AN_X4_ABI_SP2_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp2, pc->linkfailtimerqua_en); 563 AN_X4_ABI_SP2_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp2, pc->an_fail_cnt); 564 AN_X4_ABI_SP2_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp2, pc->an_oui_ctrl); 565 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_CTLSr(pc, reg_an_ctrl_sp2)); 566 }else if(sub_port == 3){ 567 AN_X4_ABI_SP3_CTLSr_CLR(reg_an_ctrl_sp3); 568 AN_X4_ABI_SP3_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl_sp3, pc->an_good_trap); 569 AN_X4_ABI_SP3_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl_sp3, pc->an_good_check_trap); 570 AN_X4_ABI_SP3_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl_sp3, pc->linkfailtimer_dis); 571 AN_X4_ABI_SP3_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl_sp3, pc->linkfailtimerqua_en); 572 AN_X4_ABI_SP3_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl_sp3, pc->an_fail_cnt); 573 AN_X4_ABI_SP3_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl_sp3, pc->an_oui_ctrl); 574 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_CTLSr(pc, reg_an_ctrl_sp3)); 575 } 576 577 return PHYMOD_E_NONE; 578 } 579 int qmod_autoneg_cl37_base_abilities(PHYMOD_ST* pc,int sub_port) 580 { 581 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 582 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 583 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 584 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 585 586 if(sub_port == 0){ 587 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 588 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_speed & 3)); 589 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_duplex & 1)); 590 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_fd & 1)); 591 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_hd & 1)); 592 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_pause & 3)); 593 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_np & 1)); 594 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_master_mode & 1)); 595 596 if(pc->cl37_bam_en){ 597 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 0); 598 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, 0); 599 }else{ 600 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 1); 601 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 602 } 603 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_disable_reset_disable & 1)); 604 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp0)); 605 }else if(sub_port == 1){ 606 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 607 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_speed & 3)); 608 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_duplex & 1)); 609 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_fd & 1)); 610 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_hd & 1)); 611 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_pause & 3)); 612 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_np & 1)); 613 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_sgmii_master_mode & 1)); 614 615 if(pc->cl37_bam_en){ 616 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 0); 617 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, 0); 618 }else { 619 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 1); 620 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 621 } 622 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, (pc->cl37_an_disable_reset_disable & 1)); 623 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp1)); 624 }else if(sub_port == 2){ 625 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 626 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_speed & 3)); 627 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_duplex & 1)); 628 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_fd & 1)); 629 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_hd & 1)); 630 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_pause & 3)); 631 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_np & 1)); 632 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_sgmii_master_mode & 1)); 633 634 if(pc->cl37_bam_en){ 635 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 0); 636 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, 0); 637 }else { 638 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 1); 639 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 640 } 641 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, (pc->cl37_an_disable_reset_disable & 1)); 642 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp2)); 643 }else if(sub_port == 3){ 644 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 645 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_speed & 3)); 646 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_duplex & 1)); 647 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_fd & 1)); 648 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_hd & 1)); 649 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_pause & 3)); 650 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_np & 1)); 651 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_sgmii_master_mode & 1)); 652 653 if(pc->cl37_bam_en){ 654 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 0); 655 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, 0); 656 }else { 657 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 1); 658 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 659 } 660 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, (pc->cl37_an_disable_reset_disable & 1)); 661 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp3)); 662 } 663 664 return PHYMOD_E_NONE; 665 } 666 int qmod_autoneg_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port) 667 { 668 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp0; 669 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp1; 670 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp2; 671 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities_sp3; 672 673 if(sub_port==0){ 674 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp0); 675 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp0, (pc->cl37_bam_ovr1g_pgcnt & 3)); 676 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp0, (pc->cl37_bam_ovr1g_en & 1)); 677 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp0, (pc->cl37_bam_code & 0x1ff)); 678 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp0)); 679 }else if(sub_port==1){ 680 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp1); 681 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp1, (pc->cl37_bam_ovr1g_pgcnt & 3)); 682 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp1, (pc->cl37_bam_ovr1g_en & 1)); 683 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp1, (pc->cl37_bam_code & 0x1ff)); 684 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp1)); 685 }else if(sub_port==2){ 686 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp2); 687 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp2, (pc->cl37_bam_ovr1g_pgcnt & 3)); 688 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp2, (pc->cl37_bam_ovr1g_en & 1)); 689 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp2, (pc->cl37_bam_code & 0x1ff)); 690 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp2)); 691 }else if(sub_port==3){ 692 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities_sp3); 693 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities_sp3, (pc->cl37_bam_ovr1g_pgcnt & 3)); 694 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities_sp3, (pc->cl37_bam_ovr1g_en & 1)); 695 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities_sp3, (pc->cl37_bam_code & 0x1ff)); 696 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities_sp3)); 697 } 698 699 return PHYMOD_E_NONE; 700 } 701 int qmod_autoneg_cl37_bam_over1g_abilities(PHYMOD_ST* pc,int sub_port) 702 { 703 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp0; 704 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp1; 705 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp2; 706 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities_sp3; 707 if(sub_port == 0){ 708 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp0); 709 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp0, (pc->cl37_bam_speed & 0x7ff)); 710 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp0)); 711 }else if(sub_port == 1){ 712 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp1); 713 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp1, (pc->cl37_bam_speed & 0x7ff)); 714 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp1)); 715 }else if(sub_port == 2){ 716 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp2); 717 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp2, (pc->cl37_bam_speed & 0x7ff)); 718 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp2)); 719 }else if(sub_port == 3){ 720 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities_sp3); 721 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities_sp3, (pc->cl37_bam_speed & 0x7ff)); 722 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities_sp3)); 723 } 724 return PHYMOD_E_NONE; 725 } 726 int qmod_autoneg_set(PHYMOD_ST* pc) /* AUTONEG_SET */ 727 { 728 /*AN_X4_ABI_SP1_CTLSr_t reg_an_ctrl;*/ 729 /*DIG_CTL1000X2r_t reg_ctrl1000x2;*/ 730 /*AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities;*/ 731 /* AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_cl37_bam_abilities;*/ 732 /*AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_over1g_abilities;*/ 733 734 QMOD_DBG_IN_FUNC_INFO(pc); 735 /* 736 AN_X4_ABI_SP1_CTLSr_CLR(reg_an_ctrl); 737 AN_X4_ABI_SP1_CTLSr_AN_GOOD_TRAPf_SET(reg_an_ctrl, pc->an_good_trap); 738 AN_X4_ABI_SP1_CTLSr_AN_GOOD_CHECK_TRAPf_SET(reg_an_ctrl, pc->an_good_check_trap); 739 AN_X4_ABI_SP1_CTLSr_LINKFAILTIMER_DISf_SET(reg_an_ctrl, pc->linkfailtimer_dis); 740 AN_X4_ABI_SP1_CTLSr_LINKFAILTIMERQUAL_ENf_SET(reg_an_ctrl, pc->linkfailtimerqua_en); 741 AN_X4_ABI_SP1_CTLSr_AN_FAIL_COUNT_LIMITf_SET(reg_an_ctrl, pc->an_fail_cnt); 742 AN_X4_ABI_SP1_CTLSr_OUI_CONTROLf_SET(reg_an_ctrl, pc->an_oui_ctrl); 743 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_CTLSr(pc, reg_an_ctrl)); 744 */ 745 qmod_autoneg_abilities_controls(pc,pc->sub_port); 746 747 /* 748 DIG_CTL1000X2r_CLR(reg_ctrl1000x2); 749 DIG_CTL1000X2r_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_ctrl1000x2, pc->disable_rf_report); 750 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_CTL1000X2r(pc, reg_ctrl1000x2)); 751 */ 752 if(pc->sc_mode == QMOD_SC_MODE_AN_CL37){ 753 /* an37 */ 754 /*Local device cl37 base abilities setting*/ 755 qmod_autoneg_cl37_base_abilities(pc,pc->sub_port); 756 /* 757 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 758 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_speed & 3)); 759 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_duplex & 1)); 760 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_fd & 1)); 761 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_HALF_DUPLEXf_SET(reg_cl37_base_abilities, (pc->cl37_an_hd & 1)); 762 AN_ABI_SP1_X4_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities, (pc->cl37_an_pause & 3)); 763 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities, (pc->cl37_an_np & 1)); 764 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities, (pc->cl37_sgmii_master_mode & 1)); 765 766 if(!(pc->cl37_bam_en)){ 767 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities); 768 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities, 1); 769 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities, 1); 770 } 771 772 773 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities)); 774 */ 775 /*Local device cl37 bam abilities setting*/ 776 777 qmod_autoneg_cl37_bam_abilities(pc,pc->sub_port); 778 /* CL37 BAM ABILITIES */ 779 /*AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_cl37_bam_abilities); 780 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_ovr1g_pgcnt & 3)); 781 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_ovr1g_en & 1)); 782 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_cl37_bam_abilities, (pc->cl37_bam_code & 0x1ff)); 783 784 PHYMOD_IF_ERR_RETURN 785 (MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_cl37_bam_abilities)); 786 787 */ 788 /***** Setting AN_X4_ABILITIES_local_device_over1g_abilities_0 0xC184 *******/ 789 if(pc->cl37_bam_speed){ 790 qmod_autoneg_cl37_bam_over1g_abilities(pc,pc->sub_port); 791 /*AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_over1g_abilities); 792 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_SET(reg_over1g_abilities, (pc->cl37_bam_speed & 0x7ff)); 793 PHYMOD_IF_ERR_RETURN(WRITE_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, reg_over1g_abilities)); 794 */ 795 } 796 797 798 }/*Completion of CL37 abilities*/ 799 800 801 return PHYMOD_E_NONE; 802 } 803 #endif 804 805 /* 806 @brief To get autoneg control registers. 807 @param pc handle to current TSCE context (#PHYMOD_ST) 808 @param an_control details 809 @param an_complete reference which is updated with an_complete info 810 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 811 @details Upper layer software calls this function to get autoneg info. 812 813 <B>How to call:</B><br> 814 <p>Call directly </p> 815 */ 816 817 int qmod_autoneg_control_get(PHYMOD_ST* pc, int sub_port, qmod_an_control_t *an_control, int *an_complete) 818 { 819 /* code not complete.*/ 820 AN_X4_SW_SP0_AN_MISC_STSr_t an_misc_reg_sub0; 821 AN_X4_SW_SP1_AN_MISC_STSr_t an_misc_reg_sub1; 822 AN_X4_SW_SP2_AN_MISC_STSr_t an_misc_reg_sub2; 823 AN_X4_SW_SP3_AN_MISC_STSr_t an_misc_reg_sub3; 824 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 825 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 826 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 827 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 828 829 an_control->num_lane_adv = 1; 830 an_control->enable = 0; 831 *an_complete = 0; 832 switch (sub_port) { 833 case 0: 834 READ_AN_X4_ABI_SP0_ENSr(pc, ®_an_enb0); 835 if (AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb0) || 836 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(reg_an_enb0)) { 837 an_control->enable = 1; 838 839 READ_AN_X4_SW_SP0_AN_MISC_STSr(pc, &an_misc_reg_sub0); 840 *an_complete = AN_X4_SW_SP0_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub0); 841 } 842 break; 843 case 1: 844 READ_AN_X4_ABI_SP1_ENSr(pc, ®_an_enb1); 845 if (AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb1) || 846 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(reg_an_enb1)) { 847 an_control->enable = 1; 848 849 READ_AN_X4_SW_SP1_AN_MISC_STSr(pc, &an_misc_reg_sub1); 850 *an_complete = AN_X4_SW_SP1_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub1); 851 } 852 break; 853 case 2: 854 READ_AN_X4_ABI_SP2_ENSr(pc, ®_an_enb2); 855 if (AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb2) || 856 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(reg_an_enb2)) { 857 an_control->enable = 1; 858 859 READ_AN_X4_SW_SP2_AN_MISC_STSr(pc, &an_misc_reg_sub2); 860 *an_complete = AN_X4_SW_SP2_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub2); 861 } 862 break; 863 default: 864 READ_AN_X4_ABI_SP3_ENSr(pc, ®_an_enb3); 865 if (AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb3) || 866 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(reg_an_enb3)) { 867 an_control->enable = 1; 868 869 READ_AN_X4_SW_SP3_AN_MISC_STSr(pc, &an_misc_reg_sub3); 870 *an_complete = AN_X4_SW_SP3_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_reg_sub3); 871 } 872 break; 873 } 874 return PHYMOD_E_NONE; 875 /* 876 This code is from TEMod. It may not match 1:1 with QTC. 877 AN_X4_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_abl; 878 AN_X4_ENSr_t reg_an_enb; 879 AN_X4_CTLSr_t an_x4_abl_ctrl; 880 AN_X4_AN_MISC_STSr_t an_misc_sts; 881 882 QMOD_DBG_IN_FUNC_INFO(pc); 883 READ_AN_X4_LOC_DEV_CL37_BASE_ABILr(pc, ®_an_cl37_abl); 884 if(AN_X4_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_an_cl37_abl) == 1){ 885 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_SGMII_MASTER_MODE; 886 } 887 888 READ_AN_X4_ENSr(pc, ®_an_enb); 889 if(AN_X4_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb) == 1){ 890 an_control->an_type = TEMOD_AN_MODE_CL37BAM; 891 an_control->enable = 1; 892 } else if ( AN_X4_ENSr_CL37_ENABLEf_GET(reg_an_enb) == 1){ 893 an_control->an_type = TEMOD_AN_MODE_CL37; 894 an_control->enable = 1; 895 } else { 896 an_control->an_type = TEMOD_AN_MODE_NONE; 897 an_control->enable = 0; 898 } 899 900 if(AN_X4_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 901 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_SGMII_TO_CL37_AUTO; 902 } else if(AN_X4_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_GET(reg_an_enb) == 1) { 903 an_control->an_property_type = TEMOD_AN_PROPERTY_ENABLE_CL37_BAM_to_SGMII_AUTO; 904 } 905 906 an_control->num_lane_adv = 1; 907 908 AN_X4_AN_MISC_STSr_CLR(an_misc_sts); 909 READ_AN_X4_AN_MISC_STSr(pc, &an_misc_sts); 910 *an_complete = AN_X4_AN_MISC_STSr_AN_COMPLETEf_GET(an_misc_sts); 911 912 return PHYMOD_E_NONE; 913 */ 914 } 915 916 /** 917 @brief To get autoneg advertisement registers. 918 @param pc handle to current TSCE context (#PHYMOD_ST) 919 @param an_ability_st, with the local abilities 920 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 921 @details Upper layer software calls this function to get local autoneg 922 info. 923 924 <B>How to call:</B><br> 925 <p>Call directly </p> 926 */ 927 928 int qmod_autoneg_local_ability_get(PHYMOD_ST* pc, qmod_an_ability_t *an_ability_st, int sub_port) 929 { 930 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 931 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 932 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 933 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 934 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 935 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 936 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 937 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 938 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp0; 939 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp1; 940 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp2; 941 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp3; 942 AN_X4_LP_SP0_LP_BASE_PAGE1r_t reg_lp_sp0 ; 943 AN_X4_LP_SP1_LP_BASE_PAGE1r_t reg_lp_sp1 ; 944 AN_X4_LP_SP2_LP_BASE_PAGE1r_t reg_lp_sp2 ; 945 AN_X4_LP_SP3_LP_BASE_PAGE1r_t reg_lp_sp3 ; 946 uint16_t value=0 ; 947 948 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_NONE ; 949 an_ability_st->cl37_adv.cl37_sgmii_speed = 0 ; 950 an_ability_st->cl37_adv.an_pause = 0 ; 951 an_ability_st->cl37_adv.an_bam_speed = 0 ; 952 an_ability_st->cl37_adv.an_duplex = 0 ; 953 954 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 955 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 956 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp0); 957 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 958 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 959 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp1); 960 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 961 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 962 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp2); 963 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 964 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 965 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp3); 966 AN_X4_LP_SP0_LP_BASE_PAGE1r_CLR(reg_lp_sp0) ; 967 AN_X4_LP_SP1_LP_BASE_PAGE1r_CLR(reg_lp_sp1) ; 968 AN_X4_LP_SP2_LP_BASE_PAGE1r_CLR(reg_lp_sp2) ; 969 AN_X4_LP_SP3_LP_BASE_PAGE1r_CLR(reg_lp_sp3) ; 970 971 if(sub_port == 0){ 972 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP0_ENSr(pc, ®_an_enb0)); 973 if(AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(reg_an_enb0)) { 974 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 975 976 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp0)); 977 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp0); 978 an_ability_st->cl37_adv.an_duplex = QMOD_AN_FULL_DUPLEX_SET ; 979 980 /* no combined modes yet; cl37 default full duplex */ 981 if(AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb0)) { 982 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 983 an_ability_st->cl37_adv.an_pause = QMOD_SYMM_PAUSE ; 984 985 if(AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp0)) { /* master mode dicates a role */ 986 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp0) ; 987 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp0))? 988 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 989 } else { 990 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP0_LP_BASE_PAGE1r(pc, ®_lp_sp0)); 991 value = AN_X4_LP_SP0_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp0) ; 992 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 993 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 994 } 995 } 996 if(AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb0)) { 997 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 998 999 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp0)); 1000 if(AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp0)) { 1001 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1002 } 1003 } 1004 } 1005 } else if(sub_port == 1){ 1006 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP1_ENSr(pc, ®_an_enb1)); 1007 if(AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(reg_an_enb1)) { 1008 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1009 1010 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp1)); 1011 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp1); 1012 an_ability_st->cl37_adv.an_duplex = QMOD_AN_FULL_DUPLEX_SET ; 1013 1014 /* no combined modes yet */ 1015 if(AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb1)) { 1016 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1017 an_ability_st->cl37_adv.an_pause = QMOD_SYMM_PAUSE ; 1018 1019 if(AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp1)) { 1020 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp1) ; 1021 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp1))? 1022 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1023 } else { 1024 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP1_LP_BASE_PAGE1r(pc, ®_lp_sp1)); 1025 value = AN_X4_LP_SP1_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp1) ; 1026 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1027 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1028 } 1029 } 1030 if(AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb1)) { 1031 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1032 1033 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp1)); 1034 if(AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp1)) { 1035 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1036 } 1037 } 1038 } 1039 } else if(sub_port == 2){ 1040 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP2_ENSr(pc, ®_an_enb2)); 1041 if(AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(reg_an_enb2)) { 1042 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1043 1044 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp2)); 1045 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp2); 1046 an_ability_st->cl37_adv.an_duplex = QMOD_AN_FULL_DUPLEX_SET ; 1047 1048 /* no combined modes yet */ 1049 if(AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb2)) { 1050 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1051 an_ability_st->cl37_adv.an_pause = QMOD_SYMM_PAUSE ; 1052 1053 if(AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp2)) { 1054 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp2) ; 1055 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp2))? 1056 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1057 } else { 1058 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP2_LP_BASE_PAGE1r(pc, ®_lp_sp2)); 1059 value = AN_X4_LP_SP2_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp2) ; 1060 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1061 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1062 } 1063 } 1064 if(AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb2)) { 1065 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1066 1067 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp2)); 1068 if(AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp2)) { 1069 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1070 } 1071 } 1072 } 1073 } else if(sub_port == 3){ 1074 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP3_ENSr(pc, ®_an_enb3)); 1075 if(AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(reg_an_enb3)) { 1076 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1077 1078 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp3)); 1079 an_ability_st->cl37_adv.an_pause = AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp3); 1080 an_ability_st->cl37_adv.an_duplex = QMOD_AN_FULL_DUPLEX_SET; 1081 1082 /* no combined modes yet */ 1083 if(AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb3)) { 1084 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1085 an_ability_st->cl37_adv.an_pause = QMOD_SYMM_PAUSE ; 1086 1087 if(AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp3)) { 1088 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp3) ; 1089 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp3))? 1090 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1091 } else { 1092 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP3_LP_BASE_PAGE1r(pc, ®_lp_sp3)); 1093 value = AN_X4_LP_SP3_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp3) ; 1094 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1095 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1096 } 1097 } 1098 if(AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb3)) { 1099 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1100 1101 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, ®_an_over1g_ability_sp3)); 1102 if(AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_GET(reg_an_over1g_ability_sp3)) { 1103 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1104 } 1105 } 1106 } 1107 } else { return PHYMOD_E_PARAM ; } 1108 return PHYMOD_E_NONE; 1109 } 1110 1111 /** 1112 @brief To get autoneg advertisement registers. 1113 @param pc handle to current TSCE context (#PHYMOD_ST) 1114 @param an_ability_st, with the remote abilities 1115 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1116 @details Upper layer software calls this function to get autoneg 1117 info. 1118 */ 1119 1120 int qmod_autoneg_remote_ability_get(PHYMOD_ST* pc, qmod_an_ability_t *an_ability_st, int sub_port) 1121 { 1122 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 1123 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 1124 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 1125 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 1126 AN_X4_LP_SP0_LP_BASE_PAGE1r_t reg_lp_sp0 ; /* 0xc248 */ 1127 AN_X4_LP_SP1_LP_BASE_PAGE1r_t reg_lp_sp1 ; 1128 AN_X4_LP_SP2_LP_BASE_PAGE1r_t reg_lp_sp2 ; 1129 AN_X4_LP_SP3_LP_BASE_PAGE1r_t reg_lp_sp3 ; 1130 AN_X4_LP_SP0_LP_MP1024_UP1r_t reg_bam37_sp0 ; /* 0xc254 */ 1131 AN_X4_LP_SP1_LP_MP1024_UP1r_t reg_bam37_sp1 ; /* 0xc254 */ 1132 AN_X4_LP_SP2_LP_MP1024_UP1r_t reg_bam37_sp2 ; /* 0xc254 */ 1133 AN_X4_LP_SP3_LP_MP1024_UP1r_t reg_bam37_sp3 ; /* 0xc254 */ 1134 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 1135 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 1136 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 1137 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 1138 uint16_t value = 0; 1139 1140 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_NONE ; 1141 an_ability_st->cl37_adv.cl37_sgmii_speed = 0 ; 1142 an_ability_st->cl37_adv.an_pause = 0 ; 1143 an_ability_st->cl37_adv.an_bam_speed = 0 ; 1144 an_ability_st->cl37_adv.an_duplex = 0 ; 1145 1146 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1147 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1148 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1149 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1150 AN_X4_LP_SP0_LP_BASE_PAGE1r_CLR(reg_lp_sp0) ; 1151 AN_X4_LP_SP1_LP_BASE_PAGE1r_CLR(reg_lp_sp1) ; 1152 AN_X4_LP_SP2_LP_BASE_PAGE1r_CLR(reg_lp_sp2) ; 1153 AN_X4_LP_SP3_LP_BASE_PAGE1r_CLR(reg_lp_sp3) ; 1154 AN_X4_LP_SP0_LP_MP1024_UP1r_CLR(reg_bam37_sp0) ; 1155 AN_X4_LP_SP1_LP_MP1024_UP1r_CLR(reg_bam37_sp1) ; 1156 AN_X4_LP_SP2_LP_MP1024_UP1r_CLR(reg_bam37_sp2) ; 1157 AN_X4_LP_SP3_LP_MP1024_UP1r_CLR(reg_bam37_sp3) ; 1158 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 1159 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 1160 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 1161 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 1162 1163 if(sub_port == 0){ 1164 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP0_ENSr(pc, ®_an_enb0)); 1165 1166 if(AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_GET(reg_an_enb0)) { 1167 /* no combined modes yet */ 1168 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP0_LP_BASE_PAGE1r(pc, ®_lp_sp0)); 1169 if(AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb0)) { 1170 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1171 1172 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp0)); 1173 1174 if(AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp0)) { /* master mode dicates a role */ 1175 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp0) ; 1176 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp0))? 1177 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1178 } else { 1179 value = AN_X4_LP_SP0_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp0) ; 1180 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1181 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1182 } 1183 an_ability_st->cl37_adv.an_pause = QMOD_ASYM_SYMM_PAUSE ; 1184 } else { 1185 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1186 value = AN_X4_LP_SP0_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp0) ; 1187 an_ability_st->cl37_adv.an_duplex = 0x3 & (value>>6) ; 1188 an_ability_st->cl37_adv.an_pause = 0x3 & (value>>7) ; 1189 } 1190 if(AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb0)) { 1191 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1192 1193 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP0_LP_MP1024_UP1r(pc, ®_bam37_sp0)); 1194 1195 if(AN_X4_LP_SP0_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp0) & 0x1) { 1196 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1197 } 1198 } 1199 } 1200 } else if(sub_port == 1){ 1201 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP1_ENSr(pc, ®_an_enb1)); 1202 if(AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_GET(reg_an_enb1)) { 1203 /* no combined modes yet */ 1204 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP1_LP_BASE_PAGE1r(pc, ®_lp_sp1)); 1205 if(AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb1)) { 1206 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1207 1208 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp1)); 1209 if(AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp1)) { 1210 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp1) ; 1211 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp1))? 1212 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1213 } else { 1214 value = AN_X4_LP_SP1_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp1) ; 1215 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1216 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1217 } 1218 an_ability_st->cl37_adv.an_pause = QMOD_ASYM_SYMM_PAUSE ; 1219 } else { 1220 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1221 value = AN_X4_LP_SP1_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp1) ; 1222 an_ability_st->cl37_adv.an_duplex = 0x3 & (value>>6) ; 1223 an_ability_st->cl37_adv.an_pause = 0x3 & (value>>7) ; 1224 } 1225 if(AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb1)) { 1226 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1227 1228 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP1_LP_MP1024_UP1r(pc, ®_bam37_sp1)); 1229 1230 if(AN_X4_LP_SP1_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp1) & 0x1) { 1231 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1232 } 1233 } 1234 } 1235 } else if(sub_port == 2){ 1236 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP2_ENSr(pc, ®_an_enb2)); 1237 if(AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_GET(reg_an_enb2)) { 1238 /* no combined modes yet */ 1239 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP2_LP_BASE_PAGE1r(pc, ®_lp_sp2)); 1240 if(AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb2)) { 1241 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1242 1243 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp2)); 1244 1245 if(AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp2)) { 1246 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp2) ; 1247 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp2))? 1248 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1249 } else { 1250 value = AN_X4_LP_SP2_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp2) ; 1251 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1252 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1253 } 1254 an_ability_st->cl37_adv.an_pause = QMOD_ASYM_SYMM_PAUSE ; 1255 } else { 1256 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1257 value = AN_X4_LP_SP2_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp2) ; 1258 an_ability_st->cl37_adv.an_duplex = 0x3 & (value>>6) ; 1259 an_ability_st->cl37_adv.an_pause = 0x3 & (value>>7) ; 1260 } 1261 if(AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb2)) { 1262 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1263 1264 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP2_LP_MP1024_UP1r(pc, ®_bam37_sp2)); 1265 1266 if(AN_X4_LP_SP2_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp2) & 0x1) { 1267 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1268 } 1269 } 1270 } 1271 } else if(sub_port == 3){ 1272 PHYMOD_IF_ERR_RETURN (READ_AN_X4_ABI_SP3_ENSr(pc, ®_an_enb3)); 1273 if(AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_GET(reg_an_enb3)) { 1274 /* no combined modes yet */ 1275 PHYMOD_IF_ERR_RETURN(READ_AN_X4_LP_SP3_LP_BASE_PAGE1r(pc, ®_lp_sp3)); 1276 if(AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_GET(reg_an_enb3)) { 1277 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_SGMII ; 1278 1279 PHYMOD_IF_ERR_RETURN(READ_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, ®_cl37_base_abilities_sp3)); 1280 if(AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_GET(reg_cl37_base_abilities_sp3)) { 1281 an_ability_st->cl37_adv.cl37_sgmii_speed = AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_GET(reg_cl37_base_abilities_sp3) ; 1282 an_ability_st->cl37_adv.an_duplex = (AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_GET(reg_cl37_base_abilities_sp3))? 1283 QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1284 } else { 1285 value = AN_X4_LP_SP3_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp3) ; 1286 an_ability_st->cl37_adv.cl37_sgmii_speed = 0x3 & (value>>10) ; 1287 an_ability_st->cl37_adv.an_duplex = (0x1 & (value>>12))? QMOD_AN_FULL_DUPLEX_SET:QMOD_AN_HALF_DUPLEX_SET; 1288 } 1289 an_ability_st->cl37_adv.an_pause = QMOD_ASYM_SYMM_PAUSE ; 1290 } else { 1291 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37 ; 1292 value = AN_X4_LP_SP3_LP_BASE_PAGE1r_LP_BASE_PAGE1_PAGE_DATAf_GET(reg_lp_sp3) ; 1293 an_ability_st->cl37_adv.an_duplex = 0x3 & (value>>6) ; 1294 an_ability_st->cl37_adv.an_pause = 0x3 & (value>>7) ; 1295 } 1296 if(AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_GET(reg_an_enb3)) { 1297 an_ability_st->cl37_adv.an_type = QMOD_AN_MODE_CL37BAM ; 1298 1299 PHYMOD_IF_ERR_RETURN (READ_AN_X4_LP_SP3_LP_MP1024_UP1r(pc, ®_bam37_sp3)); 1300 1301 if(AN_X4_LP_SP3_LP_MP1024_UP1r_LP_MP1024_UP1_PAGE_DATAf_GET(reg_bam37_sp3) & 0x1) { 1302 an_ability_st->cl37_adv.an_bam_speed |= (1 << QMOD_CL37_BAM_2p5GBASE_X) ; 1303 } 1304 } 1305 } 1306 } else { return PHYMOD_E_PARAM ; } 1307 1308 return PHYMOD_E_NONE; 1309 } 1310 1311 /* 1312 @brief Controls port RX squelch 1313 @param pc handle to current TSCE context (#PHYMOD_ST) 1314 @param enable is the control to RX squelch 1315 @returns The value PHYMOD_E_NONE upon successful completion. 1316 @details Controls port RX squelch 1317 */ 1318 int qmod_rx_squelch_set(PHYMOD_ST *pc, int enable) 1319 { 1320 SIGDET_CTL1r_t sigdet_ctl; 1321 1322 SIGDET_CTL1r_CLR(sigdet_ctl); 1323 1324 if(enable){ 1325 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 1326 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 1327 /* PHYMOD_IF_ERR_RETURN(qmod_rx_lane_control_set(pc, 0));*/ 1328 } else { 1329 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 1330 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 1331 /*PHYMOD_IF_ERR_RETURN(qmod_rx_lane_control_set(pc, 1)); */ 1332 } 1333 PHYMOD_IF_ERR_RETURN(MODIFY_SIGDET_CTL1r(pc, sigdet_ctl)); 1334 1335 return PHYMOD_E_NONE; 1336 } 1337 1338 /** 1339 @brief Controls port TX squelch 1340 @param pc handle to current TSCE context (#PHYMOD_ST) 1341 @param enable is the control to TX squelch 1342 @returns The value PHYMOD_E_NONE upon successful completion. 1343 @details Controls port TX squelch 1344 */ 1345 int qmod_tx_squelch_set(PHYMOD_ST *pc, int enable) 1346 { 1347 TXFIR_MISC_CTL1r_t tx_misc_ctl; 1348 1349 TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 1350 1351 TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 1352 PHYMOD_IF_ERR_RETURN(MODIFY_TXFIR_MISC_CTL1r(pc, tx_misc_ctl)); 1353 1354 return PHYMOD_E_NONE; 1355 } 1356 1357 /** 1358 @brief Controls port TX/RX squelch 1359 @param pc handle to current TSCE context (#PHYMOD_ST) 1360 @param enable is the control to TX/RX squelch. Enable=1 means enable the port,no squelch 1361 @returns The value PHYMOD_E_NONE upon successful completion. 1362 @details Controls port TX/RX squelch 1363 */ 1364 int qmod_port_enable_set(PHYMOD_ST *pc, int enable) 1365 { 1366 if (enable) { 1367 qmod_rx_squelch_set(pc, 0); 1368 qmod_tx_squelch_set(pc, 0); 1369 } else { 1370 qmod_rx_squelch_set(pc, 1); 1371 qmod_tx_squelch_set(pc, 1); 1372 } 1373 1374 return PHYMOD_E_NONE; 1375 } 1376 1377 /** 1378 @brief Get port TX squelch control settings 1379 @param pc handle to current TSCE context (#PHYMOD_ST) 1380 @param val Receiver for status of TX squelch 1381 @returns The value PHYMOD_E_NONE upon successful completion. 1382 @details Get port TX squelch control settings 1383 */ 1384 int qmod_tx_squelch_get(PHYMOD_ST *pc, int *val) 1385 { 1386 TXFIR_MISC_CTL1r_t tx_misc_ctl; 1387 1388 TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 1389 1390 PHYMOD_IF_ERR_RETURN(READ_TXFIR_MISC_CTL1r(pc, &tx_misc_ctl)); 1391 *val = TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 1392 1393 return PHYMOD_E_NONE; 1394 } 1395 1396 /** 1397 @brief Gets port RX squelch settings 1398 @param pc handle to current TSCE context (#PHYMOD_ST) 1399 @param val Receiver for status of RX squelch 1400 @returns The value PHYMOD_E_NONE upon successful completion. 1401 @details Gets port RX squelch settings 1402 */ 1403 int qmod_rx_squelch_get(PHYMOD_ST *pc, int *val) 1404 { 1405 SIGDET_CTL1r_t sigdet_ctl; 1406 1407 SIGDET_CTL1r_CLR(sigdet_ctl); 1408 1409 PHYMOD_IF_ERR_RETURN(READ_SIGDET_CTL1r(pc, &sigdet_ctl)); 1410 *val = SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 1411 1412 return PHYMOD_E_NONE; 1413 } 1414 1415 /** 1416 @brief Get port TX/RX squelch Settings 1417 @param pc handle to current TSCE context (#PHYMOD_ST) 1418 @param tx_enable - get the TX squelch settings 1419 @param rx_enable - get the RX squelch settings 1420 @returns The value PHYMOD_E_NONE upon successful completion. 1421 @details Controls port TX/RX squelch 1422 */ 1423 int qmod_port_enable_get(PHYMOD_ST *pc, int *tx_enable, int *rx_enable) 1424 { 1425 1426 qmod_rx_squelch_get(pc, rx_enable); 1427 qmod_tx_squelch_get(pc, tx_enable); 1428 1429 return PHYMOD_E_NONE; 1430 } 1431 1432 1433 1434 /** 1435 @brief Controls setting/resetting of autoneg ability and enabling/disabling 1436 @param pc handle to current TSCE context (#PHYMOD_ST) 1437 @param an_control structure with AN controls 1438 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 1439 1440 This function programs auto-negotiation (AN) modes for the TSCE. It can 1441 enable/disable clause37/clause73/BAM autonegotiation capabilities. Call this 1442 function once for combo mode and once per lane in independent lane mode. 1443 1444 The autonegotiation mode is controlled by setting specific bits of 1445 #PHYMOD_ST::an_type. 1446 1447 The autonegotiation mode is indicated by setting an_type with 1448 1449 \li QMOD_AN_NONE (disable AN) 1450 \li QMOD_CL73 1451 \li QMOD_CL73_BAM 1452 \li QMOD_HPAM 1453 */ 1454 1455 #ifdef _DV_TB_ 1456 int qmod_an_abilities_enables(PHYMOD_ST* pc,int sub_port) 1457 { 1458 uint16_t cl37_bam_enable ; 1459 uint16_t cl37_sgmii_enable, cl37_enable,qsgmii_enable; 1460 /* uint16_t cl37_bam_code, over1g_ability, over1g_page_count;*/ 1461 /* uint16_t sgmii_full_duplex ;*/ 1462 uint16_t cl37_restart; 1463 /* int no_an ;*/ 1464 /* UC_COMMAND3r_t reg_com3; */ 1465 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 1466 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 1467 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 1468 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 1469 SC_X4_SC_AN_SUBP_CTLr_t reg_see_sc; 1470 QMOD_DBG_IN_FUNC_INFO(pc); 1471 1472 /* TSCE_COMMANDr_t reg_com; 1473 */ 1474 1475 /* no_an = 0 ; */ 1476 1477 cl37_bam_enable = 0x0; 1478 cl37_sgmii_enable = 0x0; 1479 qsgmii_enable = 0x0; 1480 cl37_enable = 0x0; 1481 cl37_restart = 0x0; 1482 /* cl37_bam_code = 0x0;*/ 1483 /* over1g_ability = 0x0;*/ 1484 /* over1g_page_count = 0x0;*/ 1485 1486 1487 if (pc->sc_mode == QMOD_SC_MODE_AN_CL37) { 1488 cl37_restart = pc->cl37_an_restart; 1489 cl37_enable = pc->cl37_an_en; 1490 cl37_bam_enable = pc->cl37_bam_en; 1491 cl37_sgmii_enable = pc->cl37_sgmii_en; 1492 qsgmii_enable = pc->qsgmii_mode; 1493 /* cl37_bam_code = pc->cl37_bam_code & 0x1ff;*/ 1494 /* over1g_ability = pc->cl37_bam_ovr1g_en & 1;*/ 1495 /* over1g_page_count = pc->cl37_bam_ovr1g_pgcnt & 3; */ /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1496 /* sgmii_full_duplex = pc->cl37_sgmii_duplex & 1;*/ 1497 } else { 1498 /* no_an = 1 ; */ 1499 return PHYMOD_E_FAIL; 1500 } 1501 1502 if(pc->tsc_port_touched == 0){ 1503 SC_X4_SC_AN_SUBP_CTLr_CLR(reg_see_sc); 1504 SC_X4_SC_AN_SUBP_CTLr_SET(reg_see_sc,pc->sub_port); 1505 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_SC_AN_SUBP_CTLr(pc, reg_see_sc)); 1506 } 1507 1508 if(cl37_restart == 0){ 1509 if(sub_port == 0){ 1510 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1511 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,0); 1512 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1513 }else if(sub_port == 1){ 1514 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1515 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,0); 1516 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1517 }else if(sub_port == 2){ 1518 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1519 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,0); 1520 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1521 }else if(sub_port == 3){ 1522 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1523 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,0); 1524 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1525 } 1526 } 1527 1528 /*Setting X4 abilities*/ 1529 if(sub_port == 0){ 1530 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1531 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,cl37_restart); 1532 AN_X4_ABI_SP0_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb0,pc->sgmii_to_cl37_auto_enable); 1533 AN_X4_ABI_SP0_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb0,pc->cl37_bam_to_sgmii_auto_enable); 1534 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,cl37_enable); 1535 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb0,cl37_sgmii_enable); 1536 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb0,cl37_bam_enable); 1537 AN_X4_ABI_SP0_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb0,pc->disable_rf_report); 1538 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_SET(reg_an_enb0,qsgmii_enable); 1539 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1540 }else if(sub_port == 1){ 1541 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1542 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,cl37_restart); 1543 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb1,pc->sgmii_to_cl37_auto_enable); 1544 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb1,pc->cl37_bam_to_sgmii_auto_enable); 1545 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,cl37_enable); 1546 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb1,cl37_sgmii_enable); 1547 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb1,cl37_bam_enable); 1548 AN_X4_ABI_SP1_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb1,pc->disable_rf_report); 1549 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1,qsgmii_enable); 1550 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1551 }else if(sub_port == 2){ 1552 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1553 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,cl37_restart); 1554 AN_X4_ABI_SP2_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb2,pc->sgmii_to_cl37_auto_enable); 1555 AN_X4_ABI_SP2_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb2,pc->cl37_bam_to_sgmii_auto_enable); 1556 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,cl37_enable); 1557 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb2,cl37_sgmii_enable); 1558 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb2,cl37_bam_enable); 1559 AN_X4_ABI_SP2_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb2,pc->disable_rf_report); 1560 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_SET(reg_an_enb2,qsgmii_enable); 1561 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1562 }else if(sub_port == 3){ 1563 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1564 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,cl37_restart); 1565 AN_X4_ABI_SP3_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb3,pc->sgmii_to_cl37_auto_enable); 1566 AN_X4_ABI_SP3_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb3,pc->cl37_bam_to_sgmii_auto_enable); 1567 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,cl37_enable); 1568 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb3,cl37_sgmii_enable); 1569 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb3,cl37_bam_enable); 1570 AN_X4_ABI_SP3_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb3,pc->disable_rf_report); 1571 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3,qsgmii_enable); 1572 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1573 } 1574 1575 if(cl37_restart){ 1576 if(sub_port == 0){ 1577 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 1578 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,0); 1579 AN_X4_ABI_SP0_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb0,pc->sgmii_to_cl37_auto_enable); 1580 AN_X4_ABI_SP0_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb0,pc->cl37_bam_to_sgmii_auto_enable); 1581 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,cl37_enable); 1582 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb0,cl37_sgmii_enable); 1583 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb0,cl37_bam_enable); 1584 AN_X4_ABI_SP0_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb0,pc->disable_rf_report); 1585 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_SET(reg_an_enb0,qsgmii_enable); 1586 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 1587 }else if(sub_port == 1){ 1588 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 1589 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,0); 1590 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb1,pc->sgmii_to_cl37_auto_enable); 1591 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb1,pc->cl37_bam_to_sgmii_auto_enable); 1592 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,cl37_enable); 1593 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb1,cl37_sgmii_enable); 1594 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb1,cl37_bam_enable); 1595 AN_X4_ABI_SP1_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb1,pc->disable_rf_report); 1596 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1,qsgmii_enable); 1597 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 1598 }else if(sub_port == 2){ 1599 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 1600 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,0); 1601 AN_X4_ABI_SP2_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb2,pc->sgmii_to_cl37_auto_enable); 1602 AN_X4_ABI_SP2_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb2,pc->cl37_bam_to_sgmii_auto_enable); 1603 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,cl37_enable); 1604 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb2,cl37_sgmii_enable); 1605 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb2,cl37_bam_enable); 1606 AN_X4_ABI_SP2_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb2,pc->disable_rf_report); 1607 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_SET(reg_an_enb2,qsgmii_enable); 1608 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 1609 }else if(sub_port == 3){ 1610 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 1611 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,0); 1612 AN_X4_ABI_SP3_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb3,pc->sgmii_to_cl37_auto_enable); 1613 AN_X4_ABI_SP3_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb3,pc->cl37_bam_to_sgmii_auto_enable); 1614 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,cl37_enable); 1615 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb3,cl37_sgmii_enable); 1616 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb3,cl37_bam_enable); 1617 AN_X4_ABI_SP3_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb3,pc->disable_rf_report); 1618 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3,qsgmii_enable); 1619 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 1620 } 1621 } 1622 return PHYMOD_E_NONE; 1623 } 1624 int qmod_an_cl37_bam_abilities(PHYMOD_ST* pc,int sub_port) 1625 { 1626 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1627 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp0; 1628 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp1; 1629 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp2; 1630 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp3; 1631 QMOD_DBG_IN_FUNC_INFO(pc); 1632 1633 /* TSCE_COMMANDr_t reg_com; 1634 */ 1635 1636 cl37_bam_code = 0x0; 1637 over1g_ability = 0x0; 1638 over1g_page_count = 0x0; 1639 1640 1641 if (pc->sc_mode == QMOD_SC_MODE_AN_CL37) { 1642 cl37_bam_code = pc->cl37_bam_code & 0x1ff; 1643 over1g_ability = pc->cl37_bam_ovr1g_en & 1; 1644 over1g_page_count = pc->cl37_bam_ovr1g_pgcnt & 3; /* PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages */ 1645 } else { 1646 return PHYMOD_E_FAIL; 1647 } 1648 1649 1650 /* cl37 bam abilities 0xc182 */ 1651 if(sub_port == 0){ 1652 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp0); 1653 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp0, over1g_page_count, 1); 1654 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp0, over1g_ability, 1); 1655 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp0, cl37_bam_code, 1); 1656 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp0)); 1657 }else if(sub_port == 1){ 1658 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp1); 1659 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp1, over1g_page_count); 1660 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp1, over1g_ability); 1661 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp1, cl37_bam_code); 1662 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp1)); 1663 }else if(sub_port == 2){ 1664 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp2); 1665 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp2, over1g_page_count); 1666 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp2, over1g_ability); 1667 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp2, cl37_bam_code); 1668 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp2)); 1669 }else if(sub_port == 3){ 1670 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp3); 1671 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp3, over1g_page_count); 1672 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp3, over1g_ability); 1673 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp3, cl37_bam_code); 1674 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp3)); 1675 } 1676 1677 return PHYMOD_E_NONE; 1678 } 1679 1680 int qmod_autoneg_control(PHYMOD_ST* pc) 1681 { 1682 1683 /* 1684 uint16_t data ; 1685 uint16_t an_setup_enable, num_advertised_lanes, cl37_bam_enable ; 1686 uint16_t cl37_sgmii_enable, cl37_enable; 1687 uint16_t next_page ; 1688 uint16_t cl37_next_page, cl37_full_duplex; 1689 uint16_t sgmii_full_duplex ; 1690 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1691 uint16_t cl37_restart; 1692 int no_an ; 1693 */ 1694 /*AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities;*/ 1695 /* UC_COMMAND3r_t reg_com3; */ 1696 /*AN_X4_ABI_SP1_ENSr_t reg_an_enb;*/ 1697 QMOD_DBG_IN_FUNC_INFO(pc); 1698 1699 /* TSCE_COMMANDr_t reg_com; 1700 */ 1701 1702 /* 1703 no_an = 0 ; 1704 1705 an_setup_enable = 0x1; 1706 num_advertised_lanes = 0x2; 1707 cl37_bam_enable = 0x0; 1708 cl37_sgmii_enable = 0x0; 1709 cl37_enable = 0x0; 1710 next_page = 0x0; 1711 cl37_next_page = 0x0; 1712 cl37_full_duplex = 0x1; 1713 sgmii_full_duplex = 0x1; 1714 cl37_bam_code = 0x0; 1715 over1g_ability = 0x0; 1716 over1g_page_count = 0x0; 1717 cl37_restart = 0x0; 1718 1719 num_advertised_lanes = pc->no_of_lanes; 1720 */ 1721 1722 if (pc->sc_mode == QMOD_SC_MODE_AN_CL37) { 1723 /* 1724 cl37_restart = pc->cl37_an_restart; 1725 cl37_enable = pc->cl37_an_en; 1726 cl37_bam_enable = pc->cl37_bam_en; 1727 cl37_sgmii_enable = pc->cl37_sgmii_en; 1728 cl37_bam_code = pc->cl37_bam_code & 0x1ff; 1729 over1g_ability = pc->cl37_bam_ovr1g_en & 1; 1730 over1g_page_count = pc->cl37_bam_ovr1g_pgcnt & 3; // PHY-863: =1: 5 pages; =0: 3 pages; WC uses 3 pages 1731 sgmii_full_duplex = pc->cl37_sgmii_duplex & 1; 1732 cl37_next_page = pc->cl37_an_np & 1; 1733 */ 1734 } else { 1735 /* no_an = 1 ; */ 1736 return PHYMOD_E_FAIL; 1737 } 1738 1739 1740 /* cl37 bam abilities 0xc182 */ 1741 /* 1742 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities); 1743 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities, over1g_page_count); 1744 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities, over1g_ability); 1745 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities, cl37_bam_code); 1746 1747 PHYMOD_IF_ERR_RETURN 1748 (MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities)); 1749 */ 1750 qmod_an_cl37_bam_abilities(pc,pc->sub_port); 1751 /* disable ecc of uC 0xffcc */ 1752 /* 1753 TSCE_COMMAND3r_SET(reg_com3, 0x0c04); 1754 PHYMOD_IF_ERR_RETURN (TSCE_WRITE_COMMAND3r(pc, reg_com3)); 1755 */ 1756 1757 /* enable micro_controller 0xffc2 */ 1758 /* 1759 TSCE_READ_COMMANDr(pc, ®_com); 1760 TSCE_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(reg_com,1); 1761 UC_COMMAND_MDIO_UC_RESET_N_MASK)); 1762 */ 1763 /* set cl73 nonce set 0xc340 */ 1764 /* 0x924a for PHY_892 TBD*/ 1765 /* 1766 if((no_an==0)&&(pc->port_type==TSCMOD_SINGLE_PORT)) { 1767 data = 0x1a0a ; // 100ms TX_RESET_TIMER_PERIOD 1768 data = 0xd05 ; // 50ms 1769 } else { 1770 data = 0x5 ; 1771 } 1772 PHYMOD_IF_ERR_RETURN 1773 TSC_REG_WRITE(pc->unit, pc, 0x00, 0x0000924a, data)) ; 1774 */ 1775 1776 /*Disabling AN if already enabled required for dynamic speed change tests*/ 1777 1778 /*Setting X4 abilities*/ 1779 qmod_an_abilities_enables(pc,pc->sub_port); 1780 /* 1781 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb); 1782 1783 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb,0); 1784 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb)); 1785 1786 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb); 1787 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb,cl37_restart); 1788 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb,pc->sgmii_to_cl37_auto_enable); 1789 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb,pc->cl37_bam_to_sgmii_auto_enable); 1790 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb,cl37_enable); 1791 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb,cl37_sgmii_enable); 1792 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb,cl37_bam_enable); 1793 AN_X4_ABI_SP1_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb,pc->disable_rf_report); 1794 1795 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb)); 1796 */ 1797 1798 return PHYMOD_E_NONE; 1799 } /* qmod_autoneg_control */ 1800 1801 #endif 1802 1803 #ifdef _SDK_QMOD_ 1804 1805 int qmod_an_cl37_bam_abilities(PHYMOD_ST* pc, qmod_an_ability_t *an_ability, int sub_port) 1806 { 1807 1808 uint16_t cl37_bam_code, over1g_ability, over1g_page_count; 1809 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp0; 1810 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp1; 1811 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp2; 1812 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_t reg_an_cl37_bam_abilities_sp3; 1813 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp0; 1814 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp1; 1815 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp2; 1816 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_an_cl37_base_sp3; 1817 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp0; 1818 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp1; 1819 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp2; 1820 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_t reg_an_over1g_ability_sp3; 1821 1822 QMOD_DBG_IN_FUNC_INFO(pc); 1823 1824 /* TSCE_COMMANDr_t reg_com; 1825 */ 1826 1827 cl37_bam_code = 0x1; 1828 over1g_ability = 0x1; 1829 over1g_page_count = 0x0; 1830 1831 1832 1833 /* cl37 bam abilities 0xc182 */ 1834 if(sub_port == 0){ 1835 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp0); 1836 AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp0, 1); 1837 MODIFY_AN_X4_ABI_SP0_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp0); 1838 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp0); 1839 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp0, 1); 1840 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp0, 1); 1841 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp0); 1842 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp0, over1g_page_count); 1843 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp0, over1g_ability); 1844 AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp0, cl37_bam_code); 1845 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp0)); 1846 MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp0); 1847 }else if(sub_port == 1){ 1848 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp1); 1849 AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp1, 1); 1850 MODIFY_AN_X4_ABI_SP1_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp1); 1851 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp1); 1852 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp1, 1); 1853 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp1, 1); 1854 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp1); 1855 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp1, over1g_page_count); 1856 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp1, over1g_ability); 1857 AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp1, cl37_bam_code); 1858 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp1)); 1859 MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp1); 1860 }else if(sub_port == 2){ 1861 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp2); 1862 AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp2, 1); 1863 MODIFY_AN_X4_ABI_SP2_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp2); 1864 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp2); 1865 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp2, 1); 1866 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp2, 1); 1867 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp2); 1868 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp2, over1g_page_count); 1869 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp2, over1g_ability); 1870 AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp2, cl37_bam_code); 1871 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp2)); 1872 MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp2); 1873 }else if(sub_port == 3){ 1874 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_CLR(reg_an_over1g_ability_sp3); 1875 AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r_BAM_2P5GBASE_Xf_SET(reg_an_over1g_ability_sp3, 1); 1876 MODIFY_AN_X4_ABI_SP3_LOC_DEV_OVER1G_ABIL0r(pc, reg_an_over1g_ability_sp3); 1877 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_an_cl37_base_sp3); 1878 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_an_cl37_base_sp3, 1); 1879 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(reg_an_cl37_base_sp3, 1); 1880 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CLR(reg_an_cl37_bam_abilities_sp3); 1881 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_PAGE_COUNTf_SET(reg_an_cl37_bam_abilities_sp3, over1g_page_count); 1882 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_OVER1G_ABILITYf_SET(reg_an_cl37_bam_abilities_sp3, over1g_ability); 1883 AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr_CL37_BAM_CODEf_SET(reg_an_cl37_bam_abilities_sp3, cl37_bam_code); 1884 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BAM_ABILr(pc, reg_an_cl37_bam_abilities_sp3)); 1885 MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, reg_an_cl37_base_sp3); 1886 } 1887 return PHYMOD_E_NONE; 1888 } 1889 1890 int qmod_autoneg_cl37_base_abilities(PHYMOD_ST* pc, qmod_an_ability_t *an_ability, int sub_port) 1891 { 1892 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp0; 1893 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp1; 1894 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp2; 1895 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_t reg_cl37_base_abilities_sp3; 1896 1897 if(sub_port == 0){ 1898 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp0); 1899 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp0, (an_ability->cl37_adv.cl37_sgmii_speed & 3)); 1900 if(an_ability->cl37_adv.an_duplex & QMOD_AN_HALF_DUPLEX_SET) { 1901 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, 0); 1902 } else { 1903 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp0, 1); 1904 } 1905 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp0, (an_ability->cl37_adv.an_pause & 3)); 1906 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_np & 1)); */ 1907 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_master_mode & 1)); */ 1908 1909 if (an_ability->cl37_adv.an_bam_speed) { 1910 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 0); 1911 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, 0); 1912 } else { 1913 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 1); 1914 /* 1915 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 1916 */ 1917 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, 1); 1918 } 1919 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_disable_reset_disable & 1)); */ 1920 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, 1); 1921 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp0)); 1922 } else if(sub_port == 1){ 1923 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp1); 1924 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp1, (an_ability->cl37_adv.cl37_sgmii_speed & 3)); 1925 if(an_ability->cl37_adv.an_duplex & QMOD_AN_HALF_DUPLEX_SET) { 1926 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, 0); 1927 } else { 1928 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp1, 1); 1929 } 1930 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp1, (an_ability->cl37_adv.an_pause & 3)); 1931 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_np & 1)); */ 1932 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_master_mode & 1)); */ 1933 1934 if (an_ability->cl37_adv.an_bam_speed) { 1935 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 0); 1936 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, 0); 1937 } else { 1938 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 1); 1939 /* 1940 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 1941 */ 1942 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp1, 1); 1943 } 1944 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_disable_reset_disable & 1)); */ 1945 AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp1, 1); 1946 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP1_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp1)); 1947 } else if (sub_port == 2) { 1948 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp2); 1949 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp2, (an_ability->cl37_adv.cl37_sgmii_speed & 3)); 1950 if(an_ability->cl37_adv.an_duplex & QMOD_AN_HALF_DUPLEX_SET) { 1951 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, 0); 1952 } else { 1953 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp2, 1); 1954 } 1955 1956 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp2, (an_ability->cl37_adv.an_pause & 3)); 1957 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_np & 1)); */ 1958 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_master_mode & 1)); */ 1959 1960 if (an_ability->cl37_adv.an_bam_speed) { 1961 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 0); 1962 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, 0); 1963 } else { 1964 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 1); 1965 /* 1966 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 1967 */ 1968 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp2, 1); 1969 } 1970 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_disable_reset_disable & 1)); */ 1971 AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp2, 1); 1972 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP2_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp2)); 1973 } else if (sub_port == 3) { 1974 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CLR(reg_cl37_base_abilities_sp3); 1975 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_SPEEDf_SET(reg_cl37_base_abilities_sp3, (an_ability->cl37_adv.cl37_sgmii_speed & 3)); 1976 if(an_ability->cl37_adv.an_duplex & QMOD_AN_HALF_DUPLEX_SET) { 1977 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, 0); 1978 } else { 1979 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_SGMII_FULL_DUPLEXf_SET(reg_cl37_base_abilities_sp3, 1); 1980 } 1981 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_PAUSEf_SET(reg_cl37_base_abilities_sp3, (an_ability->cl37_adv.an_pause & 3)); 1982 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_NEXT_PAGEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_np & 1)); */ 1983 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_SGMII_MASTER_MODEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_sgmii_master_mode & 1)); */ 1984 1985 if (an_ability->cl37_adv.an_bam_speed) { 1986 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 0); 1987 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, 0); 1988 } else { 1989 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_RESTART_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 1); 1990 /* 1991 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp0, (pc->cl37_an_restart | pc->cl37_sw_restart_reset_disable)); 1992 */ 1993 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_SW_RESTART_RESET_DISABLEf_SET (reg_cl37_base_abilities_sp3, 1); 1994 } 1995 /* AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp0, (pc->cl37_an_disable_reset_disable & 1)); */ 1996 AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr_CL37_AN_DISABLE_RESET_DISABLEf_SET(reg_cl37_base_abilities_sp3, 1); 1997 PHYMOD_IF_ERR_RETURN(MODIFY_AN_X4_ABI_SP3_LOC_DEV_CL37_BASE_ABILr(pc, reg_cl37_base_abilities_sp3)); 1998 } 1999 2000 return PHYMOD_E_NONE; 2001 } 2002 2003 int qmod_autoneg_set(PHYMOD_ST* pc, 2004 qmod_an_ability_t *an_ability_st, int sub_port) /* AUTONEG_SET */ 2005 { 2006 qmod_autoneg_cl37_base_abilities(pc, an_ability_st, sub_port); 2007 qmod_an_cl37_bam_abilities(pc, an_ability_st, sub_port); 2008 return PHYMOD_E_NONE; 2009 } 2010 2011 2012 int qmod_autoneg_control(PHYMOD_ST* pc, qmod_an_control_t *an_control, int sub_port) 2013 { 2014 uint16_t cl37_bam_enable ; 2015 uint16_t cl37_sgmii_enable, cl37_enable,qsgmii_enable; 2016 /* uint16_t cl37_bam_code, over1g_ability, over1g_page_count;*/ 2017 /* uint16_t sgmii_full_duplex ;*/ 2018 uint16_t cl37_restart; 2019 /* int no_an ;*/ 2020 /* UC_COMMAND3r_t reg_com3; */ 2021 AN_X4_ABI_SP0_ENSr_t reg_an_enb0; 2022 AN_X4_ABI_SP1_ENSr_t reg_an_enb1; 2023 AN_X4_ABI_SP2_ENSr_t reg_an_enb2; 2024 AN_X4_ABI_SP3_ENSr_t reg_an_enb3; 2025 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_t cl37_base_ability; 2026 /* SC_X4_SC_AN_SUBP_CTLr_t reg_see_sc; */ 2027 QMOD_DBG_IN_FUNC_INFO(pc); 2028 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CLR(cl37_base_ability); 2029 2030 /* TSCE_COMMANDr_t reg_com; 2031 */ 2032 2033 /* no_an = 0 ; */ 2034 2035 cl37_bam_enable = 0x0; 2036 cl37_sgmii_enable = 0x0; 2037 qsgmii_enable = 0x0; 2038 cl37_enable = 0x0; 2039 cl37_restart = 0x0; 2040 /* cl37_bam_code = 0x0;*/ 2041 /* over1g_ability = 0x0;*/ 2042 /* over1g_page_count = 0x0;*/ 2043 2044 2045 if (an_control->an_type == QMOD_AN_MODE_CL37) { 2046 cl37_restart = an_control->enable; 2047 cl37_enable = an_control->enable; 2048 AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr_CL37_FULL_DUPLEXf_SET(cl37_base_ability, 1); 2049 MODIFY_AN_X4_ABI_SP0_LOC_DEV_CL37_BASE_ABILr(pc, cl37_base_ability); 2050 } else if (an_control->an_type == QMOD_AN_MODE_SGMII) { 2051 cl37_sgmii_enable = an_control->enable; 2052 cl37_restart = an_control->enable; 2053 cl37_enable = an_control->enable; 2054 } else { 2055 cl37_bam_enable = 1; 2056 cl37_restart = an_control->enable; 2057 cl37_enable = an_control->enable; 2058 } 2059 2060 /* next check if we need to enable qsgmii mode */ 2061 if (PHYMOD_ACC_F_QMODE_GET(pc)) { 2062 qsgmii_enable = 1; 2063 cl37_sgmii_enable = an_control->enable; 2064 } 2065 2066 /* if cl37 is enabled, then we need to enable 2067 2068 if(pc->tsc_port_touched == 0){ 2069 SC_X4_SC_AN_SUBP_CTLr_CLR(reg_see_sc); 2070 SC_X4_SC_AN_SUBP_CTLr_SET(reg_see_sc,pc->sub_port); 2071 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_SC_AN_SUBP_CTLr(pc, reg_see_sc)); 2072 } 2073 2074 if(cl37_restart == 0){ 2075 if(sub_port == 0){ 2076 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 2077 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,0); 2078 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 2079 }else if(sub_port == 1){ 2080 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 2081 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,0); 2082 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 2083 }else if(sub_port == 2){ 2084 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 2085 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,0); 2086 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 2087 }else if(sub_port == 3){ 2088 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 2089 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,0); 2090 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 2091 } 2092 } 2093 */ 2094 2095 /*Setting X4 abilities*/ 2096 if(sub_port == 0){ 2097 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 2098 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,cl37_restart); 2099 /* 2100 AN_X4_ABI_SP0_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb0,pc->sgmii_to_cl37_auto_enable); 2101 AN_X4_ABI_SP0_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb0,pc->cl37_bam_to_sgmii_auto_enable); 2102 */ 2103 AN_X4_ABI_SP0_ENSr_CL37_ENABLEf_SET(reg_an_enb0,cl37_enable); 2104 AN_X4_ABI_SP0_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb0,cl37_sgmii_enable); 2105 AN_X4_ABI_SP0_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb0,cl37_bam_enable); 2106 /* 2107 AN_X4_ABI_SP0_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb0,pc->disable_rf_report); 2108 */ 2109 AN_X4_ABI_SP0_ENSr_QSGMII_ENf_SET(reg_an_enb0,qsgmii_enable); 2110 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 2111 }else if(sub_port == 1){ 2112 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 2113 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,cl37_restart); 2114 /* 2115 AN_X4_ABI_SP1_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb1,pc->sgmii_to_cl37_auto_enable); 2116 AN_X4_ABI_SP1_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb1,pc->cl37_bam_to_sgmii_auto_enable); 2117 */ 2118 AN_X4_ABI_SP1_ENSr_CL37_ENABLEf_SET(reg_an_enb1,cl37_enable); 2119 AN_X4_ABI_SP1_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb1,cl37_sgmii_enable); 2120 AN_X4_ABI_SP1_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb1,cl37_bam_enable); 2121 /* 2122 AN_X4_ABI_SP1_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb1,pc->disable_rf_report); 2123 */ 2124 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1,qsgmii_enable); 2125 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 2126 }else if(sub_port == 2){ 2127 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 2128 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,cl37_restart); 2129 /* 2130 AN_X4_ABI_SP2_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb2,pc->sgmii_to_cl37_auto_enable); 2131 AN_X4_ABI_SP2_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb2,pc->cl37_bam_to_sgmii_auto_enable); 2132 */ 2133 AN_X4_ABI_SP2_ENSr_CL37_ENABLEf_SET(reg_an_enb2,cl37_enable); 2134 AN_X4_ABI_SP2_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb2,cl37_sgmii_enable); 2135 AN_X4_ABI_SP2_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb2,cl37_bam_enable); 2136 /* 2137 AN_X4_ABI_SP2_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb2,pc->disable_rf_report); 2138 */ 2139 AN_X4_ABI_SP2_ENSr_QSGMII_ENf_SET(reg_an_enb2,qsgmii_enable); 2140 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 2141 }else if(sub_port == 3){ 2142 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 2143 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,cl37_restart); 2144 /* 2145 AN_X4_ABI_SP3_ENSr_SGMII_TO_CL37_AUTO_ENABLEf_SET(reg_an_enb3,pc->sgmii_to_cl37_auto_enable); 2146 AN_X4_ABI_SP3_ENSr_CL37_BAM_TO_SGMII_AUTO_ENABLEf_SET(reg_an_enb3,pc->cl37_bam_to_sgmii_auto_enable); 2147 */ 2148 AN_X4_ABI_SP3_ENSr_CL37_ENABLEf_SET(reg_an_enb3,cl37_enable); 2149 AN_X4_ABI_SP3_ENSr_CL37_SGMII_ENABLEf_SET(reg_an_enb3,cl37_sgmii_enable); 2150 AN_X4_ABI_SP3_ENSr_CL37_BAM_ENABLEf_SET(reg_an_enb3,cl37_bam_enable); 2151 /* 2152 AN_X4_ABI_SP3_ENSr_DISABLE_REMOTE_FAULT_REPORTINGf_SET(reg_an_enb3,pc->disable_rf_report); 2153 */ 2154 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3,qsgmii_enable); 2155 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 2156 } 2157 2158 if(cl37_restart){ 2159 if(sub_port == 0){ 2160 AN_X4_ABI_SP0_ENSr_CLR(reg_an_enb0); 2161 AN_X4_ABI_SP0_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb0,0); 2162 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP0_ENSr(pc, reg_an_enb0)); 2163 }else if(sub_port == 1){ 2164 AN_X4_ABI_SP1_ENSr_CLR(reg_an_enb1); 2165 AN_X4_ABI_SP1_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb1,0); 2166 AN_X4_ABI_SP1_ENSr_QSGMII_ENf_SET(reg_an_enb1,qsgmii_enable); 2167 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP1_ENSr(pc, reg_an_enb1)); 2168 }else if(sub_port == 2){ 2169 AN_X4_ABI_SP2_ENSr_CLR(reg_an_enb2); 2170 AN_X4_ABI_SP2_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb2,0); 2171 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP2_ENSr(pc, reg_an_enb2)); 2172 }else if(sub_port == 3){ 2173 AN_X4_ABI_SP3_ENSr_CLR(reg_an_enb3); 2174 AN_X4_ABI_SP3_ENSr_CL37_AN_RESTARTf_SET(reg_an_enb3,0); 2175 AN_X4_ABI_SP3_ENSr_QSGMII_ENf_SET(reg_an_enb3,qsgmii_enable); 2176 PHYMOD_IF_ERR_RETURN (MODIFY_AN_X4_ABI_SP3_ENSr(pc, reg_an_enb3)); 2177 } 2178 } 2179 2180 return PHYMOD_E_NONE; 2181 } /* qmod_autoneg_control */ 2182 #endif /* _SDK_QMOD_*/ 2183 2184 #ifdef _DV_TB_ 2185 /* 2186 @brief Speeds up DSC and VGA functions for simulation purpose only 2187 @param pc handle to current TSCE context (#PHYMOD_ST) 2188 @returns The value PHYMOD_E_NONE upon successful completion. 2189 @details 2190 2191 This function speeds up PLL, DSC and VGA functions for any speed mode. Please don't 2192 call this function in normal operation. 2193 Set #PHYMOD_ST::per_lane_control to 1 for speed up. 2194 2195 This function is controlled by the following register bit: 2196 2197 \li acq2_timeout, acq1_timeout, acqcdr_timeout (0xc210) -> 0x0421 2198 \li acqvga_timeout (0xc211) -> 0x0800 2199 2200 */ 2201 int qmod_afe_speed_up_dsc_vga(PHYMOD_ST* pc, int pmd_touched) /* AFE_SPEED_UP_DSC_VGA */ 2202 { 2203 PLL_CAL_CTL0r_t reg_ctrl0; 2204 PLL_CAL_CTL1r_t reg_ctrl1; 2205 PLL_CAL_CTL2r_t reg_ctrl2; 2206 PLL_CAL_CTL5r_t reg_ctrl5; 2207 PLL_CAL_CTL6r_t reg_ctrl6; 2208 DSC_SM_CTL4r_t reg_ctrl4; 2209 2210 QMOD_DBG_IN_FUNC_INFO(pc); 2211 PLL_CAL_CTL5r_CLR(reg_ctrl5); 2212 PLL_CAL_CTL6r_CLR(reg_ctrl6); 2213 PLL_CAL_CTL0r_CLR(reg_ctrl0); 2214 PLL_CAL_CTL1r_CLR(reg_ctrl1); 2215 PLL_CAL_CTL2r_CLR(reg_ctrl2); 2216 DSC_SM_CTL4r_CLR(reg_ctrl4); 2217 2218 if (pmd_touched == 0) { 2219 /* PLL speed_up begin */ 2220 /* refclk_divcnt = 5 (default 16'h186a ) */ 2221 PLL_CAL_CTL5r_REFCLK_DIVCNTf_SET(reg_ctrl5, 0x5); 2222 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL5r(pc, reg_ctrl5)); 2223 2224 /* refclk_divcnt_sel = 7 */ 2225 /* data = 0x7 << PLL_CAL_COM_CTL_6_REFCLK_DIVCNT_SEL_SHIFT ; */ 2226 PLL_CAL_CTL6r_REFCLK_DIVCNT_SELf_SET(reg_ctrl6, 0x7); 2227 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL6r(pc, reg_ctrl6)); 2228 2229 /* vco_start_time = 5 */ 2230 /* data = 0x5 << PLL_CAL_COM_CTL_0_VCO_START_TIME_SHIFT ; */ 2231 PLL_CAL_CTL0r_VCO_START_TIMEf_SET(reg_ctrl0, 0x5); 2232 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL0r(pc, reg_ctrl0)); 2233 2234 /* pre_freq_det_time = 8'd100 , retry_time = 8'd100 */ 2235 PLL_CAL_CTL1r_PRE_FREQ_DET_TIMEf_SET(reg_ctrl1, 0xc8); 2236 PLL_CAL_CTL1r_RETRY_TIMEf_SET(reg_ctrl1, 0xff); 2237 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL1r(pc, reg_ctrl1)); 2238 2239 /* res_cal_cntr = 0 win_cal_cntr=1 */ 2240 PLL_CAL_CTL2r_RES_CAL_CNTRf_SET(reg_ctrl2, 0x2); 2241 PLL_CAL_CTL2r_WIN_CAL_CNTRf_SET(reg_ctrl2, 0x1); 2242 2243 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL2r(pc, reg_ctrl2)); 2244 2245 } 2246 /* PLL speed_up end */ 2247 /* DSC speed_up begin */ 2248 2249 DSC_SM_CTL4r_HW_TUNE_TIMEOUTf_SET(reg_ctrl4, 0x1); 2250 DSC_SM_CTL4r_CDR_SETTLE_TIMEOUTf_SET(reg_ctrl4, 0x1); 2251 DSC_SM_CTL4r_ACQ_CDR_TIMEOUTf_SET(reg_ctrl4, 0x4); 2252 2253 PHYMOD_IF_ERR_RETURN (MODIFY_DSC_SM_CTL4r(pc, reg_ctrl4)); 2254 2255 /* DSC speed_up end */ 2256 2257 return PHYMOD_E_NONE; 2258 } 2259 #endif /* _DV_TB_ */ 2260 2261 static int _qmod_getRevDetails(PHYMOD_ST* pc) 2262 { 2263 MAIN_SERDESIDr_t reg_serdesid; 2264 2265 MAIN_SERDESIDr_CLR(reg_serdesid); 2266 PHYMOD_IF_ERR_RETURN(READ_MAIN_SERDESIDr(pc,®_serdesid)); 2267 return (MAIN_SERDESIDr_GET(reg_serdesid)); 2268 } 2269 2270 /** 2271 @brief Init routine sets various operating modes of TSCE. 2272 @param pc handle to current TSCE context (#PHYMOD_ST) 2273 @param pmd_touched 2274 @param spd_intf #qmod_spd_intfc_type 2275 @param pll_mode # to override the pll div 2276 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 2277 @details 2278 2279 This function is called once per TSCE. It cannot be called multiple times 2280 and should be called immediately after reset. Elements of #PHYMOD_ST should be 2281 initialized to required values prior to calling this function. The following 2282 sub-configurations are performed here. 2283 2284 \li Set pll divider for VCO setting in PMD. pll divider is calculated from max_speed. 2285 */ 2286 2287 int qmod_set_pll_mode(PHYMOD_ST* pc, int pmd_touched, qmod_spd_intfc_type spd_intf, int pll_mode) /* SET_PLL_MODE */ 2288 { 2289 PLL_CAL_CTL7r_t reg_ctl7; 2290 int speed; 2291 2292 QMOD_DBG_IN_FUNC_INFO(pc); 2293 PLL_CAL_CTL7r_CLR(reg_ctl7); 2294 if (pmd_touched == 0) { 2295 qmod_get_mapped_speed(spd_intf, &speed); 2296 /*Support Override PLL DIV */ 2297 if(pll_mode & 0x80000000) { 2298 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (pll_mode) & 0x0000ffff); 2299 } else { 2300 PLL_CAL_CTL7r_PLL_MODEf_SET(reg_ctl7, (qmod_sc_pmd_entry[speed].pll_mode)); 2301 } 2302 2303 #ifdef _DV_TB_ 2304 if( pc->verbosity) { 2305 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 2306 printf("%-22s: main0_setup=%x\n", __func__, PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7)); 2307 } 2308 #endif 2309 PHYMOD_IF_ERR_RETURN (MODIFY_PLL_CAL_CTL7r(pc, reg_ctl7)); 2310 } 2311 return PHYMOD_E_NONE; 2312 2313 } /* qmod_set_pll_mode(PHYMOD_ST* pc) */ 2314 2315 #ifdef _DV_TB_ 2316 /** 2317 @brief set the AN tick overrides 2318 @param pc handle to current TSCE context (#PHYMOD_ST) 2319 @param tick_override 2320 @param numerator 2321 @param denominator 2322 @returns PHYMOD_E_NONE if successful. 2323 @details 2324 */ 2325 int qmod_tick_override_set(PHYMOD_ST* pc, int tick_override, int numerator, int denominator) 2326 { 2327 return PHYMOD_E_NONE; 2328 2329 } 2330 #endif /* _DV_TB_ */ 2331 2332 /** 2333 @brief Set the AN Portmode and Single Port for AN of TSCE. 2334 @param pc handle to current TSCE context (#PHYMOD_ST) 2335 @param number_of_lanes 2336 @param starting lane #port no. 2337 @param single_port 2338 @returns PHYMOD_E_NONE if successful. PHYMOD_E_FAIL else. 2339 @details 2340 2341 This function can be called multiple times.Elements of #PHYMOD_ST should be 2342 initialized to required values prior to calling this function. The following 2343 sub-configurations are performed here. 2344 2345 \li Set pll divider for VCO setting (0x9000[12, 11:8]). pll divider is calculated from max_speed. 2346 2347 */ 2348 #ifdef _DV_TB_ 2349 int qmod_set_an_port_mode(PHYMOD_ST* pc) /* SET_AN_PORT_MODE */ 2350 { 2351 uint16_t data; /*, mask;*/ 2352 /* 2353 PHYMOD_ST pc_10G_X1; 2354 PHYMOD_ST* pc_10G_X1_tmp; 2355 PHYMOD_ST pc_40G_X4; 2356 PHYMOD_ST* pc_40G_X4_tmp; 2357 PHYMOD_ST pc_100G_X4; 2358 PHYMOD_ST* pc_100G_X4_tmp; 2359 */ 2360 MAIN_SETUPr_t reg_main_setup; 2361 2362 CL37_RESTARTr_t reg_cl37_restart_timers; 2363 CL37_ACKr_t reg_cl37_ack_timers; 2364 CL37_ERRr_t reg_cl37_err_timers; 2365 CL37_SYNC_STS_FILTER_TMRr_t reg_an_sync_stat_fil_timer; 2366 LNK_UP_TYPEr_t reg_link_up_timer; 2367 SGMII_CL37_TMR_TYPEr_t reg_an_cl37_sgmii_tmr; 2368 MAIN_TICK_CTL1r_t reg_tick_ctrl; 2369 MAIN_TICK_CTL0r_t reg_tick_ctrl0; 2370 IGNORE_LNK_TMR_TYPEr_t reg_ignore_link_timers; 2371 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_t reg_inhbt_not_cl72_timers; 2372 2373 BAM_SPD_PRI_5_0r_t reg_bam_pri5; 2374 OUI_LWRr_t reg_an_oui_lower; 2375 OUI_UPRr_t reg_an_oui_upper; 2376 SC_X1_TX_RST_CNTr_t reg_sc_rst_cnt; 2377 2378 QMOD_DBG_IN_FUNC_INFO(pc); 2379 MAIN_SETUPr_CLR(reg_main_setup); 2380 2381 data=0; 2382 /* mask=0;*/ 2383 /*Ref clock selection*/ 2384 data = main0_refClkSelect_clk_156p25MHz; 2385 /*Selectng div 40 for CL37*/ 2386 /*if(pc->sc_mode == QMOD_SC_MODE_AN_CL37) 2387 data = data | (MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div40 << 2388 MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT); */ 2389 /*Selectng div 66 for CL77*/ 2390 /*if(pc->sc_mode == QMOD_SC_MODE_AN_CL73) 2391 data = data | (MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_div66 << 2392 MAIN0_SETUP_DEFAULT_PLL_MODE_AFE_SHIFT);*/ 2393 2394 /*For AN port mode should be always QUAD*/ 2395 2396 PHYMOD_IF_ERR_RETURN (READ_MAIN_SETUPr(pc, ®_main_setup)); 2397 2398 MAIN_SETUPr_REFCLK_SELf_SET(reg_main_setup, data); 2399 data = 0; 2400 2401 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SETUPr(pc,reg_main_setup)); 2402 2403 /*Tick over_write enable*/ 2404 MAIN_TICK_CTL1r_CLR(reg_tick_ctrl); 2405 MAIN_TICK_CTL0r_CLR(reg_tick_ctrl0); 2406 2407 MAIN_TICK_CTL1r_TICK_OVERRIDEf_SET(reg_tick_ctrl, pc->an_tick_override); 2408 MAIN_TICK_CTL1r_TICK_NUMERATOR_UPPERf_SET(reg_tick_ctrl, (pc->an_tick_numerator & 0x7fff0) >> 4); 2409 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_TICK_CTL1r(pc, reg_tick_ctrl)); 2410 2411 data=0; 2412 /*Setting numerator to 0x10 and denominator to 0x1 for CL37*/ 2413 MAIN_TICK_CTL0r_TICK_DENOMINATORf_SET(reg_tick_ctrl0,(pc->an_tick_denominator & 0x3ff)); 2414 MAIN_TICK_CTL0r_TICK_NUMERATOR_LOWERf_SET(reg_tick_ctrl0,(pc->an_tick_numerator & 0xf)); 2415 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_TICK_CTL0r(pc, reg_tick_ctrl0)); 2416 2417 2418 /*AN from ST 2419 #if defined (_DV_TB_) 2420 if(pc->per_lane_control & 0x4) { 2421 pc_10G_X1 = *pc; 2422 pc_10G_X1.speed = digital_operationSpeeds_SPEED_10G_KR1; 2423 pc_10G_X1_tmp = &pc_10G_X1; 2424 get_ht_entries(pc_10G_X1_tmp); 2425 if(pc->cl72_en & 0x80000000) 2426 pc_10G_X1_tmp->cl72_en = 0x0; 2427 else 2428 pc_10G_X1_tmp->cl72_en = 0x1; 2429 pc_10G_X1_tmp->cl72_en = pc_10G_X1_tmp->cl72_en | 0x40000000; 2430 _configure_st_entry(1, digital_operationSpeeds_SPEED_40G_KR4, pc_10G_X1_tmp); 2431 } 2432 else if(pc->per_lane_control & 0x8) { 2433 pc_40G_X4 = *pc; 2434 pc_40G_X4.speed = digital_operationSpeeds_SPEED_40G_KR4; 2435 pc_40G_X4_tmp = &pc_40G_X4; 2436 get_ht_entries(pc_40G_X4_tmp); 2437 if(pc->cl72_en & 0x80000000) 2438 pc_40G_X4_tmp->cl72_en = 0x0; 2439 else 2440 pc_40G_X4_tmp->cl72_en = 0x1; 2441 pc_40G_X4_tmp->cl72_en = pc_40G_X4_tmp->cl72_en | 0x40000000; 2442 _configure_st_entry(1, digital_operationSpeeds_SPEED_10G_KR1, pc_40G_X4_tmp); 2443 } 2444 else if(pc->per_lane_control & 0x20) { 2445 pc_100G_X4 = *pc; 2446 pc_100G_X4.speed = digital_operationSpeeds_SPEED_100M; 2447 pc_100G_X4_tmp = &pc_100G_X4; 2448 get_ht_entries(pc_100G_X4_tmp); 2449 pc_100G_X4_tmp->cl72_en = pc_100G_X4_tmp->cl72_en | 0x40000000; 2450 pc_100G_X4_tmp->this_lane = 0; 2451 pc_100G_X4_tmp->prt_ad = 1; 2452 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 2453 pc_100G_X4_tmp->this_lane = 4; 2454 pc_100G_X4_tmp->prt_ad = 5; 2455 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 2456 pc_100G_X4_tmp->this_lane = 8; 2457 pc_100G_X4_tmp->prt_ad = 9; 2458 _configure_st_entry(1, digital_operationSpeeds_SPEED_100G_CR10, pc_100G_X4_tmp); 2459 } 2460 #endif 2461 */ 2462 2463 /*0x9250 AN_X1_TIMERS_cl37_restart */ 2464 CL37_RESTARTr_CLR(reg_cl37_restart_timers); 2465 data = pc->cl37_restart_timer_period; 2466 if(data == 0) 2467 data = 0x1f; 2468 CL37_RESTARTr_CL37_RESTART_TIMER_PERIODf_SET(reg_cl37_restart_timers, data); 2469 PHYMOD_IF_ERR_RETURN(WRITE_CL37_RESTARTr(pc, reg_cl37_restart_timers)); 2470 /*0x9251 AN_X1_TIMERS_cl37_ack */ 2471 CL37_ACKr_CLR(reg_cl37_ack_timers); 2472 data = pc->cl37_ack_timer_period; 2473 if(data == 0) 2474 data = 0x1f; 2475 CL37_ACKr_CL37_ACK_TIMER_PERIODf_SET(reg_cl37_ack_timers, data); 2476 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ACKr(pc, reg_cl37_ack_timers)); 2477 /*0x9252 AN_X1_TIMERS_cl37_error */ 2478 CL37_ERRr_CLR(reg_cl37_err_timers); 2479 data = pc->cl37_error_timer_period; 2480 CL37_ERRr_CL37_ERROR_TIMER_PERIODf_SET(reg_cl37_err_timers, data); 2481 PHYMOD_IF_ERR_RETURN(WRITE_CL37_ERRr(pc, reg_cl37_err_timers)); 2482 /*0x9253 AN_X1_TIMERS_cl37_sync_status_filter_timer*/ 2483 data = pc->cl37_sync_status_filter; 2484 CL37_SYNC_STS_FILTER_TMRr_CLR(reg_an_sync_stat_fil_timer); 2485 CL37_SYNC_STS_FILTER_TMRr_CL37_SYNC_STATUS_FILTER_TIMER_PERIODf_SET(reg_an_sync_stat_fil_timer, data); 2486 PHYMOD_IF_ERR_RETURN(WRITE_CL37_SYNC_STS_FILTER_TMRr(pc, reg_an_sync_stat_fil_timer)); 2487 /*TBD::0x9254 AN_X1_TIMERS_link_up_typ*/ 2488 data = pc->cl37_sgmii_timer_period; 2489 SGMII_CL37_TMR_TYPEr_CLR(reg_an_cl37_sgmii_tmr); 2490 SGMII_CL37_TMR_TYPEr_SGMII_TIMERf_SET(reg_an_cl37_sgmii_tmr, data); 2491 PHYMOD_IF_ERR_RETURN(WRITE_SGMII_CL37_TMR_TYPEr(pc, reg_an_cl37_sgmii_tmr)); 2492 /*TBD::0x9255 AN_X1_TIMERS_sgmii_cl73_timer_type*/ 2493 if(pc->an_tick_override) 2494 data = 100; 2495 else 2496 data = 2; 2497 LNK_UP_TYPEr_CLR(reg_link_up_timer); 2498 LNK_UP_TYPEr_SET(reg_link_up_timer, data); 2499 PHYMOD_IF_ERR_RETURN(WRITE_LNK_UP_TYPEr(pc, reg_link_up_timer)); 2500 /*0x9256 AN_X1_TIMERS_ignore_link */ 2501 IGNORE_LNK_TMR_TYPEr_CLR(reg_ignore_link_timers); 2502 data = pc->an_ignore_link_timer; 2503 IGNORE_LNK_TMR_TYPEr_SET(reg_ignore_link_timers, data); 2504 PHYMOD_IF_ERR_RETURN(WRITE_IGNORE_LNK_TMR_TYPEr(pc, reg_ignore_link_timers)); 2505 /*0x9256 AN_X1_TIMERS_link_fail_inhbt_tmr_not_cl72 */ 2506 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_CLR(reg_inhbt_not_cl72_timers); 2507 data = pc->link_fail_inhibit_timer_not_cl72_period; 2508 LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr_SET(reg_inhbt_not_cl72_timers, data); 2509 PHYMOD_IF_ERR_RETURN(WRITE_LNK_FAIL_INHBT_TMR_NOT_CL72_TYPEr(pc, reg_inhbt_not_cl72_timers)); 2510 /*TBD::0x9263 sc_x1_control_tx_reset_count*/ 2511 data = pc->tx_reset_count; 2512 SC_X1_TX_RST_CNTr_CLR(reg_sc_rst_cnt); 2513 SC_X1_TX_RST_CNTr_TX_RESET_COUNTf_SET(reg_sc_rst_cnt, data); 2514 PHYMOD_IF_ERR_RETURN(WRITE_SC_X1_TX_RST_CNTr(pc, reg_sc_rst_cnt)); 2515 /*0x9240 AN_X1_CONTROL_oui_upper */ 2516 data = (pc->oui_upper_data & 0xff); 2517 OUI_UPRr_CLR(reg_an_oui_upper); 2518 OUI_UPRr_OUI_UPPER_DATAf_SET(reg_an_oui_upper, data); 2519 PHYMOD_IF_ERR_RETURN(WRITE_OUI_UPRr(pc, reg_an_oui_upper)); 2520 /*0x9241 AN_X1_CONTROL_oui_lower */ 2521 data = ((pc->oui_lower_data)); 2522 OUI_LWRr_CLR(reg_an_oui_lower); 2523 OUI_LWRr_OUI_LOWER_DATAf_SET(reg_an_oui_lower, data); 2524 PHYMOD_IF_ERR_RETURN(WRITE_OUI_LWRr(pc, reg_an_oui_lower)); 2525 /*0x9242 AN_X1_CONTROL_BAM_SPEED_PRI_5_0 */ 2526 data = ((pc->bam_spd_pri_5_0)); 2527 BAM_SPD_PRI_5_0r_CLR(reg_bam_pri5); 2528 BAM_SPD_PRI_5_0r_SET(reg_bam_pri5, data); 2529 PHYMOD_IF_ERR_RETURN(WRITE_BAM_SPD_PRI_5_0r(pc, reg_bam_pri5)); 2530 return PHYMOD_E_NONE; 2531 } /* qmod_set_an_port_mode(PHYMOD_ST* pc) */ 2532 #endif 2533 2534 #ifdef _SDK_QMOD_ 2535 int qmod_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) /* SET_AN_PORT_MODE */ 2536 { 2537 return PHYMOD_E_NONE; 2538 } /* qmod_set_an_port_mode(PHYMOD_ST* pc, int num_of_lanes, int starting_lane, int single_port) */ 2539 #endif /* _SDK_QMOD_ */ 2540 2541 int qmod_refclk_set(PHYMOD_ST* pc, qmod_ref_clk_t refclk) 2542 { 2543 MAIN_SETUPr_t reg_setup; 2544 2545 MAIN_SETUPr_CLR(reg_setup); 2546 PHYMOD_IF_ERR_RETURN (READ_MAIN_SETUPr(pc, ®_setup)); 2547 2548 if(refclk!=QMODREFCLK125MHZ) { 2549 MAIN_SETUPr_REFCLK_SELf_SET(reg_setup, main0_refClkSelect_clk_156p25MHz); 2550 } else { 2551 /* not supported */ 2552 return PHYMOD_E_FAIL; 2553 } 2554 2555 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SETUPr(pc,reg_setup)); 2556 return PHYMOD_E_NONE; 2557 } 2558 2559 2560 /** 2561 @brief Sets loopback mode at PCS/PMD parallel interface. (PCS gloop). 2562 @param pc handle to current TSCE context (#PHYMOD_ST) 2563 @param enable loopbacks. 2564 @returns The value PHYMOD_E_NONE upon successful completion 2565 2566 This function sets the TX-to-RX digital loopback mode at the PCS/PMD parallel interface, which is set 2567 based on port_type. 2568 2569 \li 0:1 : Enable TX->RX loopback 2570 \li 0:0 : Disable TX->RX loopback 2571 2572 Note that this function can program <B>multiple lanes simultaneously</B>. 2573 2574 */ 2575 int qmod_tx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int num_lanes) /* TX_LOOPBACK_CONTROL */ 2576 { 2577 BCMI_QTC_XGXS_MAIN_LPBK_CTLr_t reg_lb_ctrl; 2578 BCMI_QTC_XGXS_PMD_X4_OVRRr_t reg_pmd_ovr; 2579 BCMI_QTC_XGXS_PMD_X4_CTLr_t reg_pmd_ctrl; 2580 uint16_t lane_mask, data, tmp_data, i; 2581 2582 QMOD_DBG_IN_FUNC_INFO(pc); 2583 lane_mask = 0; 2584 READ_MAIN_LPBK_CTLr(pc, ®_lb_ctrl); 2585 tmp_data = MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2586 PMD_X4_OVRRr_CLR(reg_pmd_ovr); 2587 PMD_X4_CTLr_CLR(reg_pmd_ctrl); 2588 2589 2590 data = 0; 2591 for (i = 0; i < num_lanes; i++) { 2592 lane_mask |= 1 << (starting_lane + i); 2593 data |= enable << (starting_lane + i); 2594 } 2595 2596 tmp_data &= ~lane_mask; 2597 tmp_data |= data; 2598 MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, tmp_data); 2599 2600 #if 0 2601 2602 switch(port_type) { 2603 case QMOD_MULTI_PORT: lane_mask = (1 << (starting_lane%4)); break; 2604 case QMOD_TRI1_PORT: lane_mask = ((starting_lane%4)==2)?0xc : (1 << (starting_lane%4)); break; 2605 case QMOD_TRI2_PORT: lane_mask = ((starting_lane%4)==0)?0x3 : (1 << (starting_lane%4)); break; 2606 case QMOD_DXGXS: lane_mask = ((starting_lane%4)==0)?0x3 : 0xc; break; 2607 case QMOD_SINGLE_PORT: lane_mask = 0xf; break; 2608 default: break ; 2609 } 2610 data = enable ? lane_mask : 0; 2611 2612 PHYMOD_IF_ERR_RETURN 2613 (READ_MAIN_LPBK_CTLr(pc, ®_lb_ctrl)); 2614 2615 data_temp = MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2616 data_temp = data_temp & ~lane_mask; 2617 data = data | data_temp; 2618 2619 MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, data); 2620 #endif 2621 2622 PHYMOD_IF_ERR_RETURN 2623 (MODIFY_MAIN_LPBK_CTLr(pc, reg_lb_ctrl)); 2624 2625 /* signal_detect and rx_lock OVRDf are set in core_init, no need to set them again in here */ 2626 if (enable) { 2627 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 1); 2628 } else { 2629 PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_ovr, 0); 2630 } 2631 2632 PHYMOD_IF_ERR_RETURN 2633 (MODIFY_PMD_X4_OVRRr(pc, reg_pmd_ovr)); 2634 2635 /* set tx_disable */ 2636 if (enable) { 2637 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 1); 2638 } else { 2639 PMD_X4_CTLr_TX_DISABLEf_SET(reg_pmd_ctrl, 0); 2640 } 2641 /* mask = PMD_X4_CONTROL_TX_DISABLE_MASK ; */ 2642 PHYMOD_IF_ERR_RETURN 2643 (MODIFY_PMD_X4_CTLr(pc, reg_pmd_ctrl)); 2644 /* When the phy is put in gloop, the rx clk changes, so need to reset the rxp to clear the rx pipe */ 2645 qmod_rx_lane_control_set(pc, 1); 2646 2647 return PHYMOD_E_NONE; 2648 2649 } 2650 2651 2652 int qmod_tx_loopback_get(PHYMOD_ST* pc, uint32_t *enable) /* TX_LOOPBACK_get */ 2653 { 2654 MAIN_LPBK_CTLr_t loopReg; 2655 READ_MAIN_LPBK_CTLr(pc, &loopReg); 2656 *enable = MAIN_LPBK_CTLr_LOCAL_PCS_LOOPBACK_ENABLEf_GET(loopReg); 2657 2658 return PHYMOD_E_NONE; 2659 } 2660 2661 #ifdef _DV_TB_ 2662 /*! 2663 @brief Sets loopback mode at PMD serial interface. (gloop(PCS) + PMD) 2664 @param pc handle to current TSCE context (#PHYMOD_ST) 2665 @param cntl select tx/rx loopback 2666 @returns The value PHYMOD_E_NONE upon successful completion 2667 2668 This function sets the PMD TX-to-RX digital loopback mode. 2669 2670 \li 0:1 : Enable TX->RX loopback 2671 \li 0:0 : Disable TX->RX loopback 2672 2673 Note that this function can program <B>multiple lanes simultaneously</B>. 2674 As an example, to enable gloop on all lanes, 2675 set #PHYMOD_ST::per_lane_control to 0x01010101 2676 2677 */ 2678 int qmod_tx_pmd_loopback_control(PHYMOD_ST* pc, int cntl) /* TX_PMD_LOOPBACK_CONTROL */ 2679 { 2680 BCMI_QTC_XGXS_TLB_RX_DIG_LPBK_CFGr_t reg_lpbk_cfg; 2681 2682 QMOD_DBG_IN_FUNC_INFO(pc); 2683 TLB_RX_DIG_LPBK_CFGr_CLR(reg_lpbk_cfg); 2684 READ_TLB_RX_DIG_LPBK_CFGr(pc, ®_lpbk_cfg); 2685 2686 /*cntl = (pc-> pmd_gloop);*/ 2687 if (cntl) { 2688 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 1); 2689 } else { 2690 TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_SET(reg_lpbk_cfg, 0); 2691 } 2692 PHYMOD_IF_ERR_RETURN 2693 (WRITE_TLB_RX_DIG_LPBK_CFGr(pc, reg_lpbk_cfg)); 2694 return PHYMOD_E_NONE; 2695 2696 } 2697 #endif 2698 2699 /** 2700 @brief Sets loopback mode at PMD serial interface. (pcs -> rloop) 2701 @param pc handle to current TSCE context (#PHYMOD_ST) 2702 @returns The value PHYMOD_E_NONE upon successful completion 2703 2704 This function sets the RX-to-TX(PCS) Remote loopback mode, based on port_type. 2705 2706 \li 0:1 : Enable RX->TX loopback 2707 \li 0:0 : Disable RX->TX loopback 2708 2709 Note that this function can program <B>multiple lanes simultaneously</B>. 2710 As an example, to enable gloop on all lanes, 2711 set #PHYMOD_ST::per_lane_control to 0x01010101 2712 2713 */ 2714 int qmod_rx_loopback_control(PHYMOD_ST* pc, int enable, int starting_lane, int port_type) /* RX_LOOPBACK_CONTROL */ 2715 { 2716 BCMI_QTC_XGXS_MAIN_LPBK_CTLr_t reg_lb_ctrl; 2717 BCMI_QTC_XGXS_TLB_TX_TX_PI_LOOP_TIMING_CFGr_t reg_lb_timing; 2718 BCMI_QTC_XGXS_TX_PI_CTL0r_t reg_com_ctrl; 2719 uint16_t lane_mask, data, data_temp; 2720 2721 QMOD_DBG_IN_FUNC_INFO(pc); 2722 MAIN_LPBK_CTLr_CLR(reg_lb_ctrl); 2723 TLB_TX_TX_PI_LOOP_TIMING_CFGr_CLR(reg_lb_timing); 2724 TX_PI_CTL0r_CLR(reg_com_ctrl); 2725 2726 lane_mask = 0; 2727 switch(port_type) { 2728 case QMOD_MULTI_PORT: lane_mask = (1 << (starting_lane%4)); break; 2729 case QMOD_TRI1_PORT: lane_mask = ((starting_lane%4)==2)?0xc : (1 << (starting_lane%4)); break; 2730 case QMOD_TRI2_PORT: lane_mask = ((starting_lane%4)==0)?0x3 : (1 << (starting_lane%4)); break; 2731 case QMOD_DXGXS: lane_mask = ((starting_lane%4)==0)?0x3 : 0xc; break; 2732 case QMOD_SINGLE_PORT: lane_mask = 0xf; break; 2733 default: break ; 2734 } 2735 data = enable ? lane_mask : 0; 2736 2737 PHYMOD_IF_ERR_RETURN 2738 (READ_MAIN_LPBK_CTLr(pc, ®_lb_ctrl)); 2739 2740 data_temp = MAIN_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_GET(reg_lb_ctrl); 2741 data_temp = data_temp & ~lane_mask; 2742 data = data | data_temp; 2743 2744 2745 MAIN_LPBK_CTLr_REMOTE_PCS_LOOPBACK_ENABLEf_SET(reg_lb_ctrl, data ); 2746 PHYMOD_IF_ERR_RETURN 2747 (MODIFY_MAIN_LPBK_CTLr(pc, reg_lb_ctrl)); 2748 2749 /* set Tx_PI */ 2750 TLB_TX_TX_PI_LOOP_TIMING_CFGr_TX_PI_LOOP_TIMING_SRC_SELf_SET(reg_lb_timing, 1); 2751 2752 PHYMOD_IF_ERR_RETURN 2753 (MODIFY_TLB_TX_TX_PI_LOOP_TIMING_CFGr(pc, reg_lb_timing)); 2754 2755 TX_PI_CTL0r_TX_PI_ENf_SET(reg_com_ctrl, 1); 2756 PHYMOD_IF_ERR_RETURN 2757 (MODIFY_TX_PI_CTL0r(pc, reg_com_ctrl)); 2758 return PHYMOD_E_NONE; 2759 } 2760 2761 /** 2762 @brief set tx encoder of any particular lane 2763 @param pc handle to current TSCE context (#PHYMOD_ST) 2764 @returns The value PHYMOD_E_NONE upon successful completion. 2765 2766 This function is used to select encoder of any transmit lane. 2767 2768 \li select encodeMode 2769 2770 */ 2771 #ifdef _DV_TB_ 2772 int qmod_encode_set(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf) /* ENCODE_SET */ 2773 { 2774 return PHYMOD_E_NONE; 2775 } 2776 #endif /* _DV_TB_ */ 2777 2778 #ifdef _SDK_QMOD_ 2779 2780 int qmod_encode_set(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf) /* ENCODE_SET */ 2781 { 2782 return PHYMOD_E_NONE; 2783 2784 } 2785 2786 #endif /* _SDK_QMOD_ */ 2787 2788 /** 2789 @brief set rx decoder of any particular lane 2790 @param pc handle to current TSCE context (#PHYMOD_ST) 2791 @returns The value PHYMOD_E_NONE upon successful completion. 2792 @details This function is used to select decoder of any receive lane. 2793 2794 \li select decodeMode 2795 2796 */ 2797 2798 #ifdef _DV_TB_ 2799 int qmod_decode_set(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf) /* DECODE_SET */ 2800 { 2801 2802 return PHYMOD_E_NONE; 2803 } /* DECODE_SET */ 2804 #endif 2805 2806 #ifdef _SDK_QMOD_ 2807 int qmod_decode_set(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf) /* DECODE_SET */ 2808 { 2809 return PHYMOD_E_NONE; 2810 } /* DECODE_SET */ 2811 2812 #endif /* SDK_QMOD_ */ 2813 2814 /*! 2815 @brief get port speed configured 2816 @param pc handle to current TSCE context (#PHYMOD_ST) 2817 @param get the resolved speed cfg in the spd_intf 2818 @returns The value PHYMOD_E_NONE upon successful completion. 2819 @details get port speed configured 2820 */ 2821 int qmod_spd_intf_get(PHYMOD_ST* pc, int *spd_intf) /* SET_SPD_INTF */ 2822 { 2823 return PHYMOD_E_NONE; 2824 } 2825 2826 /*! 2827 @brief tx lane reset and enable of any particular lane 2828 @param pc handle to current TSCE context (#PHYMOD_ST) 2829 @param enable Enable/disable traffic or reset/unreset lane 2830 @param tx_dis_type enum type #tx_lane_disable_type_t 2831 @param pc handle to current TSCE context (#PHYMOD_ST) 2832 @returns The value PHYMOD_E_NONE upon successful completion. 2833 @details 2834 This function is used to reset tx lane and enable/disable tx lane of any 2835 transmit lane. Set bit 0 of #PHYMOD_ST::per_lane_control to enable the TX_LANE 2836 (1) or disable the TX lane (0). When diable TX lane, two types of operations 2837 are inovked independently. 2838 If #PHYMOD_ST::per_lane_control bit [7:4] = 1, only traffic is disabled. 2839 (QMOD_TX_LANE_TRAFFIC =0x10) 2840 If bit [7:4] = 2, only reset function is invoked. 2841 (QMOD_TX_LANE_RESET = 0x20) 2842 2843 */ 2844 int qmod_tx_lane_control_set(PHYMOD_ST* pc, tx_lane_disable_type_t tx_dis_type) /* TX_LANE_CONTROL */ 2845 { 2846 MISCr_t reg_misc_ctrl; 2847 2848 QMOD_DBG_IN_FUNC_INFO(pc); 2849 MISCr_CLR(reg_misc_ctrl); 2850 2851 switch(tx_dis_type) { 2852 case QMOD_TX_LANE_RESET: 2853 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 2854 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2855 MISCr_CLR(reg_misc_ctrl); 2856 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 2857 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2858 break; 2859 case QMOD_TX_LANE_TRAFFIC_ENABLE: 2860 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 2861 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2862 break; 2863 case QMOD_TX_LANE_TRAFFIC_DISABLE: 2864 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 2865 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2866 break; 2867 case QMOD_TX_LANE_RESET_TRAFFIC_ENABLE: 2868 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 2869 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2870 MISCr_CLR(reg_misc_ctrl); 2871 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 2872 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2873 break; 2874 case QMOD_TX_LANE_RESET_TRAFFIC_DISABLE: 2875 MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 2876 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2877 MISCr_CLR(reg_misc_ctrl); 2878 MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 2879 PHYMOD_IF_ERR_RETURN (MODIFY_MISCr(pc, reg_misc_ctrl)); 2880 break; 2881 default: 2882 break; 2883 } 2884 return PHYMOD_E_NONE; 2885 } 2886 2887 int qmod_reset(PHYMOD_ST* pc) /* pcs reset CONTROL */ 2888 { 2889 SC_X4_CTLr_t reg; 2890 2891 QMOD_DBG_IN_FUNC_INFO(pc); 2892 2893 /* write 0 to the speed change */ 2894 SC_X4_CTLr_CLR(reg); 2895 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 2896 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 2897 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg)); 2898 2899 return PHYMOD_E_NONE; 2900 } 2901 2902 /** 2903 @brief Read the 16 bit rev. id value etc. 2904 @param pc handle to current TSCE context (#PHYMOD_ST) 2905 @param *revid int ref. to return revision id to calling function. 2906 @returns The value PHYMOD_E_NONE upon successful completion. 2907 @details 2908 This fucntion reads the revid register that contains core number, revision 2909 number and stores the 16-bit value in the revid 2910 2911 */ 2912 int qmod_revid_read(PHYMOD_ST* pc, uint32_t *revid) /* REVID_READ */ 2913 { 2914 *revid=_qmod_getRevDetails(pc); 2915 return PHYMOD_E_NONE; 2916 } 2917 2918 #ifdef _DV_TB_ 2919 /** 2920 @brief Read the 16 bit rev. id value etc. 2921 @param pc handle to current TSCE context (#PHYMOD_ST) 2922 @returns The value PHYMOD_E_NONE upon successful completion 2923 @details Per Port PCS Init 2924 2925 */ 2926 int qmod_init_pcs(PHYMOD_ST* pc) /* INIT_PCS */ 2927 { 2928 QMOD_DBG_IN_FUNC_INFO(pc); 2929 _qmod_set_port_mode_select(pc); 2930 qmod_rx_lane_control_set(pc, 1); 2931 qmod_tx_lane_control_set(pc, QMOD_TX_LANE_RESET_TRAFFIC_ENABLE); /* TX_LANE_CONTROL */ 2932 2933 if((pc->sc_mode == QMOD_SC_MODE_AN_CL37)) 2934 _qmod_init_pcs_an(pc); 2935 else /* Forced Speed */ 2936 _qmod_init_pcs_fs(pc); 2937 2938 return PHYMOD_E_NONE; 2939 } 2940 #endif 2941 2942 /** 2943 @brief Init the PMD 2944 @param pc handle to current TSCE context (#PHYMOD_ST) 2945 @param pmd_touched If the PMD is already initialized 2946 @returns The value PHYMOD_E_NONE upon successful completion 2947 @details Per core PMD resets (both datapath and entire core) 2948 We only intend to use this function if the PMD has never been initialized. 2949 */ 2950 int qmod_pmd_reset_seq(PHYMOD_ST* pc, int pmd_touched) /* PMD_RESET_SEQ */ 2951 { 2952 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 2953 #ifdef KEEP_THIS 2954 SC_X4_BYPASSr_t reg_bypass; 2955 SC_X4_BYPASSr_CLR(reg_bypass); 2956 #endif 2957 QMOD_DBG_IN_FUNC_INFO(pc); 2958 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 2959 2960 if (pmd_touched == 0) { 2961 PMD_X1_CTLr_POR_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 2962 PMD_X1_CTLr_CORE_DP_H_RSTBf_SET(reg_pmd_x1_ctrl,1); 2963 PHYMOD_IF_ERR_RETURN(BCMI_QTC_XGXS_WRITE_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 2964 } 2965 2966 #ifdef KEEP_THIS 2967 SC_X4_BYPASSr_SC_BYPASSf_SET(reg_bypass, 1); 2968 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_BYPASSr(pc,reg_bypass)); 2969 #endif 2970 2971 return PHYMOD_E_NONE; 2972 } 2973 2974 /** 2975 @brief Wait for SC done bit set. 2976 @param pc handle to current TSCE context (#PHYMOD_ST) 2977 @param data handle to return SC_X4_CONTROL_STATUS reg. 2978 @returns The value PHYMOD_E_NONE upon successful completion 2979 @details Wait for SC done bit set. This is a very short wait Hence we allow a 2980 loop here. We never allow looping in tier1 as a rule. All looping should be done 2981 in tier2 and above. 2982 2983 */ 2984 int qmod_wait_sc_done(PHYMOD_ST* pc, uint16_t *data) 2985 { 2986 static int timeOut = 5000; 2987 int localTimeOut = timeOut; 2988 SC_X4_STSr_t reg_sc_ctrl_sts; 2989 2990 QMOD_DBG_IN_FUNC_INFO(pc); 2991 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 2992 2993 while(1) { 2994 localTimeOut--; 2995 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 2996 if((SC_X4_STSr_SW_SPEED_CHANGE_DONEf_GET(reg_sc_ctrl_sts) == 1) || localTimeOut < 1) 2997 break; 2998 } 2999 return PHYMOD_E_NONE; 3000 3001 } 3002 3003 #ifdef _DV_TB_ 3004 /** 3005 @brief Read the 16 bit rev. id value etc. 3006 @param pc handle to current TSCE context (#PHYMOD_ST) 3007 @returns The value PHYMOD_E_NONE upon successful completion 3008 @details Per Port PCS Init 3009 */ 3010 int _qmod_wait_sc_stats_set(PHYMOD_ST* pc) 3011 { 3012 uint16_t data; 3013 SC_X4_STSr_t reg_sc_ctrl_sts; 3014 3015 SC_X4_STSr_CLR(reg_sc_ctrl_sts); 3016 3017 while(1){ 3018 PHYMOD_IF_ERR_RETURN(READ_SC_X4_STSr(pc, ®_sc_ctrl_sts)); 3019 data = SC_X4_STSr_SW_SPEED_CONFIG_VLDf_GET(reg_sc_ctrl_sts); 3020 if(data == 1) 3021 break; 3022 } 3023 return PHYMOD_E_NONE; 3024 } 3025 #endif 3026 3027 /** 3028 @brief Read PCS Link status 3029 @param pc handle to current TSCE context (#PHYMOD_ST) 3030 @param *link Reference for Status of PCS Link 3031 @returns The value PHYMOD_E_NONE upon successful completion 3032 @details Per Port PCS Init 3033 3034 */ 3035 /* _SDK_QMOD_ */ 3036 int qmod_get_pcs_link_status(PHYMOD_ST* pc, uint32_t sub_port, uint32_t *link) 3037 { 3038 BCMI_QTC_XGXS_PCS_LIVE_STSr_t reg_pcs_live_sts; 3039 BCMI_QTC_XGXS_PCS_LATCH_STSr_t reg_pcs_ll_sts; 3040 uint16_t loc_link ; 3041 3042 QMOD_DBG_IN_FUNC_INFO(pc); 3043 3044 BCMI_QTC_XGXS_PCS_LIVE_STSr_CLR(reg_pcs_live_sts); 3045 BCMI_QTC_XGXS_PCS_LATCH_STSr_CLR(reg_pcs_ll_sts) ; 3046 3047 PHYMOD_IF_ERR_RETURN (BCMI_QTC_XGXS_READ_PCS_LIVE_STSr(pc, ®_pcs_live_sts)); 3048 PHYMOD_IF_ERR_RETURN (BCMI_QTC_XGXS_READ_PCS_LATCH_STSr(pc, ®_pcs_ll_sts)) ; 3049 3050 /* next check if we are in qsgmii mode */ 3051 if (PHYMOD_ACC_F_QMODE_GET(pc)) { 3052 switch (sub_port) { 3053 case 0: 3054 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP0f_GET(reg_pcs_live_sts); 3055 if(loc_link) { 3056 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP0f_GET(reg_pcs_ll_sts))?0:1 ; 3057 } 3058 break; 3059 case 1: 3060 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP1f_GET(reg_pcs_live_sts); 3061 if(loc_link) { 3062 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP1f_GET(reg_pcs_ll_sts))?0:1 ; 3063 } 3064 break; 3065 case 2: 3066 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP2f_GET(reg_pcs_live_sts); 3067 if(loc_link) { 3068 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP2f_GET(reg_pcs_ll_sts))?0:1 ; 3069 } 3070 break; 3071 default: 3072 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP3f_GET(reg_pcs_live_sts); 3073 if(loc_link) { 3074 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP3f_GET(reg_pcs_ll_sts))?0:1 ; 3075 } 3076 break; 3077 } 3078 /* *link = BCMI_QTC_XGXS_PCS_LIVE_STSr_GET(reg_pcs_live_sts); */ 3079 } else { 3080 loc_link = BCMI_QTC_XGXS_PCS_LIVE_STSr_LINK_STATUS_SP0f_GET(reg_pcs_live_sts); 3081 if(loc_link) { 3082 loc_link = (BCMI_QTC_XGXS_PCS_LATCH_STSr_LINK_STATUS_LL_SP0f_GET(reg_pcs_ll_sts))?0:1 ; 3083 } 3084 } 3085 *link = loc_link ; 3086 return PHYMOD_E_NONE; 3087 } /* _SDK_QMOD_ */ 3088 3089 3090 #ifdef _DV_TB_ 3091 /** 3092 @brief Read the 16 bit rev. id value etc. 3093 @param pc handle to current TSCE context (#PHYMOD_ST) 3094 @returns The value PHYMOD_E_NONE upon successful completion 3095 @details Per Port PCS Init 3096 3097 */ 3098 int qmod_mld_am_timers_set(PHYMOD_ST* pc,int rx_am_timer_init_val,int tx_am_timer_init_val) /*MLD_AM_TIMERS_SET */ 3099 { 3100 return PHYMOD_E_NONE; 3101 } 3102 #endif 3103 3104 /** 3105 @brief PMD per lane reset 3106 @param pc handle to current TSCE context (#PHYMOD_ST) 3107 @returns The value PHYMOD_E_NONE upon successful completion 3108 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 3109 3110 */ 3111 int qmod_pmd_x4_reset(PHYMOD_ST* pc) /* PMD_X4_RESET */ 3112 { 3113 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 3114 3115 QMOD_DBG_IN_FUNC_INFO(pc); 3116 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 3117 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 3118 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 3119 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 3120 3121 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 3122 PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 3123 PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 3124 PHYMOD_IF_ERR_RETURN (MODIFY_PMD_X4_CTLr(pc, reg_pmd_x4_ctrl)); 3125 3126 return PHYMOD_E_NONE; 3127 } 3128 3129 /** 3130 @brief PMD per lane reset get 3131 @param pc handle to current TSCE context (#PHYMOD_ST) 3132 @returns The value PHYMOD_E_NONE upon successful completion 3133 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 3134 */ 3135 int qmod_pmd_x4_reset_get(PHYMOD_ST* pc, int *is_in_reset) /* PMD_X4_RESET */ 3136 { 3137 PMD_X4_CTLr_t reg_pmd_x4_ctrl; 3138 3139 QMOD_DBG_IN_FUNC_INFO(pc); 3140 PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 3141 PHYMOD_IF_ERR_RETURN (READ_PMD_X4_CTLr(pc, ®_pmd_x4_ctrl)); 3142 3143 if(PMD_X4_CTLr_LN_H_RSTBf_GET(reg_pmd_x4_ctrl) && 3144 PMD_X4_CTLr_LN_DP_H_RSTBf_GET(reg_pmd_x4_ctrl)) { 3145 *is_in_reset = 0 ; 3146 } else { 3147 *is_in_reset = 1 ; 3148 } 3149 return PHYMOD_E_NONE; 3150 } 3151 3152 /** 3153 @brief Initialize the PMD in independent mode. (No PCS involved) 3154 @param pc handle to current TSCE context (#PHYMOD_ST) 3155 @param pmd_touched 3156 @param uc_active 3157 @param spd_intf #qmod_spd_intfc_type 3158 @param t_pma_os_mode per lane OS Mode in PMD 3159 @returns The value PHYMOD_E_NONE upon successful completion 3160 @details Per Port PMD Init done by software 3161 3162 */ 3163 int qmod_init_pmd_sw(PHYMOD_ST* pc, int pmd_touched, int uc_active, 3164 qmod_spd_intfc_type spd_intf, int t_pma_os_mode) /* INIT_PMD_SW */ 3165 { 3166 QMOD_DBG_IN_FUNC_INFO(pc); 3167 qmod_init_pmd(pc, pmd_touched, uc_active); 3168 qmod_pmd_osmode_set(pc, spd_intf, t_pma_os_mode); 3169 return PHYMOD_E_NONE; 3170 } 3171 3172 /** 3173 @brief Initialize PMD. for both PCS and independent modes. 3174 @param pc handle to current TSCE context (#PHYMOD_ST) 3175 @param pmd_touched Indicates this PMD was previously initialized for another 3176 port in the same core. 3177 @param uc_active Actually means PMD config. will come from PCS and not TMod 3178 @returns PHYMOD_E_NONE upon success, PHYMOD_E_FAIL else. 3179 @details Per Port PMD Init 3180 3181 */ 3182 int qmod_init_pmd(PHYMOD_ST* pc, int pmd_touched, int uc_active) /* INIT_PMD */ 3183 { 3184 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwrdwn_ctrl; 3185 DIG_TOP_USER_CTL0r_t reg_usr_ctrl; 3186 3187 QMOD_DBG_IN_FUNC_INFO(pc); 3188 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwrdwn_ctrl); 3189 DIG_TOP_USER_CTL0r_CLR(reg_usr_ctrl); 3190 3191 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwrdwn_ctrl, 1); 3192 PHYMOD_IF_ERR_RETURN(MODIFY_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pc, reg_pwrdwn_ctrl)); 3193 3194 if (pmd_touched == 0) { 3195 if(uc_active == 1){ 3196 DIG_TOP_USER_CTL0r_UC_ACTIVEf_SET(reg_usr_ctrl, 1); 3197 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 3198 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 3199 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 3200 } else{ 3201 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 3202 PHYMOD_IF_ERR_RETURN (MODIFY_DIG_TOP_USER_CTL0r(pc, reg_usr_ctrl)); 3203 } 3204 } 3205 3206 return PHYMOD_E_NONE; 3207 } 3208 3209 /** 3210 @brief Set Per lane OS mode set in PMD 3211 @param pc handle to current TSCE context (#PHYMOD_ST) 3212 @param spd_intf speed type #qmod_spd_intfc_type 3213 @param os_mode over sample rate. 3214 @returns The value PHYMOD_E_NONE upon successful completion 3215 @details Per Port PMD Init 3216 3217 */ 3218 int qmod_pmd_osmode_set(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf, int os_mode) /* INIT_PMD */ 3219 { 3220 CKRST_OSR_MODE_CTLr_t reg_osr_mode; 3221 int speed; 3222 3223 QMOD_DBG_IN_FUNC_INFO(pc); 3224 CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode); 3225 qmod_get_mapped_speed(spd_intf, &speed); 3226 3227 /*os_mode = 0x0; */ /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 3228 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 3229 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 3230 if(os_mode & 0x80000000) { 3231 os_mode = (os_mode) & 0x0000ffff; 3232 } 3233 else { 3234 os_mode = qmod_sc_pmd_entry[speed].t_pma_os_mode; 3235 } 3236 3237 CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode, 1); 3238 CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 3239 3240 PHYMOD_IF_ERR_RETURN 3241 (MODIFY_CKRST_OSR_MODE_CTLr(pc, reg_osr_mode)); 3242 3243 return PHYMOD_E_NONE; 3244 } 3245 3246 /** 3247 @brief Get Per lane OS mode set in PMD 3248 @param pc handle to current TSCE context (#PHYMOD_ST) 3249 @param os_mode over sample rate. 3250 @returns The value PHYMOD_E_NONE upon successful completion 3251 @details Per Port PMD Init 3252 3253 */ 3254 int qmod_pmd_osmode_get(PHYMOD_ST* pc, int *os_mode) /* INIT_PMD */ 3255 { 3256 CKRST_OSR_MODE_CTLr_t reg_osr_mode; 3257 3258 QMOD_DBG_IN_FUNC_INFO(pc); 3259 CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode); 3260 3261 PHYMOD_IF_ERR_RETURN 3262 (READ_CKRST_OSR_MODE_CTLr(pc, ®_osr_mode)); 3263 3264 if(CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_GET(reg_osr_mode) == 1) 3265 *os_mode = CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_GET(reg_osr_mode); 3266 else 3267 *os_mode = 0xff; 3268 3269 return PHYMOD_E_NONE; 3270 } 3271 3272 /** 3273 @brief Generic Override mechanism. Any PCS parameter can be overriden. 3274 @param pc handle to current TSCE context (#PHYMOD_ST) 3275 param cntl bit mask of parameters to override. 3276 @returns The value PHYMOD_E_NONE upon successful completion 3277 @details The cntl encoding is as follows. 3278 3279 NUM_LANES_OEN | 3280 OS_MODE_OEN | 3281 DESKEWMODE_OEN | 3282 DESC2_MODE_OEN | 3283 CL36BYTEDELETEMODE_OEN | 3284 BRCM64B66_DESCRAMBLER_ENABLE_OEN | 3285 CHK_END_EN_OEN | 3286 BLOCK_SYNC_MODE_OEN | 3287 DECODERMODE_OEN | 3288 ENCODEMODE_OEN | 3289 DESCRAMBLERMODE_OEN | 3290 SCR_MODE_OEN 3291 3292 */ 3293 int qmod_override_set(PHYMOD_ST* pc, override_type_t or_type, uint16_t or_val) /* OVERRIDE_SET */ 3294 { 3295 int or_value; 3296 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_or_en0; 3297 PMA_CTLr_t reg_os_mode_or_val; 3298 PCS_CTLr_t reg_pcs_or_val; 3299 CL36TX_CTLr_t reg_cl36_or_val; 3300 TX_X4_SP0_CRED0r_t reg_sp0_credit_or_val; 3301 3302 QMOD_DBG_IN_FUNC_INFO(pc); 3303 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_or_en0); 3304 3305 or_value = or_val & 0x0000ffff; 3306 3307 switch(or_type) { 3308 case QMOD_OVERRIDE_RESET : 3309 /* reset credits */ 3310 WRITE_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3311 3312 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3313 break; 3314 case QMOD_OVERRIDE_ALL : 3315 /* get info. from table and apply it to all credit regs. */ 3316 break; 3317 case QMOD_OVERRIDE_QSGMII_EN: 3318 CL36TX_CTLr_CLR(reg_cl36_or_val); 3319 CL36TX_CTLr_QSGMII_ENf_SET(reg_cl36_or_val,or_value); 3320 MODIFY_CL36TX_CTLr(pc,reg_cl36_or_val); 3321 /*Set the override enable*/ 3322 SC_X4_FLD_OVRR_EN0_TYPEr_QSGMII_EN_OENf_SET(reg_or_en0,1); 3323 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3324 break; 3325 case QMOD_OVERRIDE_CL36BYTEDEL_MODE: 3326 PCS_CTLr_CLR(reg_pcs_or_val); 3327 PCS_CTLr_CL36BYTEDELETEMODEf_SET(reg_pcs_or_val,or_value); 3328 MODIFY_PCS_CTLr(pc,reg_pcs_or_val); 3329 /*Set the override enable*/ 3330 SC_X4_FLD_OVRR_EN0_TYPEr_CL36BYTEDELETEMODE_OENf_SET(reg_or_en0,1); 3331 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3332 break; 3333 case QMOD_OVERRIDE_OS_MODE: 3334 PMA_CTLr_CLR(reg_os_mode_or_val); 3335 PMA_CTLr_OS_MODEf_SET(reg_os_mode_or_val,or_value); 3336 MODIFY_PMA_CTLr(pc,reg_os_mode_or_val); 3337 /*Set the override enable*/ 3338 SC_X4_FLD_OVRR_EN0_TYPEr_OS_MODE_OENf_SET(reg_or_en0,1); 3339 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3340 break; 3341 case QMOD_OVERRIDE_CREDIT_EN: 3342 TX_X4_SP0_CRED0r_CLR(reg_sp0_credit_or_val); 3343 TX_X4_SP0_CRED0r_CREDITENABLEf_SET(reg_sp0_credit_or_val,or_value); 3344 MODIFY_TX_X4_SP0_CRED0r(pc,reg_sp0_credit_or_val); 3345 /*Set the override enable*/ 3346 SC_X4_FLD_OVRR_EN0_TYPEr_CREDITENABLE_OENf_SET(reg_or_en0,1); 3347 MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc,reg_or_en0); 3348 } 3349 return PHYMOD_E_NONE; 3350 3351 } 3352 3353 3354 /** 3355 @brief Override the credits. 3356 @param pc handle to current TSCE context (#PHYMOD_ST) 3357 @param credit_type type of credit to override #credit_type_t 3358 @param userCredit User override value 3359 @returns The value PHYMOD_E_NONE upon successful completion 3360 @details Credit override mechanism is a seperate function. However it is similar 3361 to other override mechanisms. 3362 3363 */ 3364 int qmod_credit_override_set(PHYMOD_ST* pc, credit_type_t credit_type, int userCredit) /* CREDIT_OVERRIDE_SET */ 3365 { 3366 SC_X4_FLD_OVRR_EN0_TYPEr_t reg_enable_type; 3367 TX_X4_SP0_CRED0r_t reg_credit0; 3368 TX_X4_SP0_CRED1r_t reg_credit1; 3369 TX_X4_SP0_LOOPCNTr_t reg_loopcnt; 3370 TX_X4_SP0_MAC_CREDGENCNTr_t reg_maccreditgen; 3371 TX_X4_SP0_PCS_CLKCNT0r_t reg_pcs_clk_cnt; 3372 TX_X4_SP0_PCS_CREDGENCNTr_t reg_pcs_creditgen; 3373 3374 QMOD_DBG_IN_FUNC_INFO(pc); 3375 SC_X4_FLD_OVRR_EN0_TYPEr_CLR(reg_enable_type); 3376 TX_X4_SP0_CRED0r_CLR(reg_credit0); 3377 TX_X4_SP0_CRED1r_CLR(reg_credit1); 3378 TX_X4_SP0_LOOPCNTr_CLR(reg_loopcnt); 3379 TX_X4_SP0_MAC_CREDGENCNTr_CLR(reg_maccreditgen); 3380 TX_X4_SP0_PCS_CLKCNT0r_CLR(reg_pcs_clk_cnt); 3381 TX_X4_SP0_PCS_CREDGENCNTr_CLR(reg_pcs_creditgen); 3382 3383 switch ( credit_type ) { 3384 case QMOD_CREDIT_RESET: 3385 /* reset credits */ 3386 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 3387 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 0); 3388 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 0); 3389 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 0); 3390 SC_X4_FLD_OVRR_EN0_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 0); 3391 SC_X4_FLD_OVRR_EN0_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 3392 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 0); 3393 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 0); 3394 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 0); 3395 SC_X4_FLD_OVRR_EN0_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 0); 3396 3397 PHYMOD_IF_ERR_RETURN(WRITE_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3398 break; 3399 case QMOD_CREDIT_TABLE: 3400 /* get info. from table and apply it to all credit regs. */ 3401 break; 3402 case QMOD_CREDIT_CLOCK_COUNT_0: 3403 /* write to clockcnt0 */ 3404 TX_X4_SP0_CRED0r_CLOCKCNT0f_SET(reg_credit0, userCredit); 3405 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_CRED0r(pc, reg_credit0)); 3406 /*Set the override enable*/ 3407 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 3408 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3409 break; 3410 case QMOD_CREDIT_CLOCK_COUNT_1: /* (cntl & 0x00020000) */ 3411 /* write to clockcnt1 */ 3412 TX_X4_SP0_CRED1r_CLOCKCNT1f_SET(reg_credit1, userCredit); 3413 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_CRED1r(pc, reg_credit1)); 3414 /*Set the override enable*/ 3415 SC_X4_FLD_OVRR_EN0_TYPEr_CLOCKCNT1_OENf_SET(reg_enable_type, 1); 3416 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3417 break; 3418 case QMOD_CREDIT_LOOP_COUNT_0: 3419 /* write to loopcnt0 */ 3420 TX_X4_SP0_LOOPCNTr_LOOPCNT0f_SET(reg_loopcnt, userCredit); 3421 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_LOOPCNTr(pc, reg_loopcnt)); 3422 /*Set the override enable*/ 3423 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT0_OENf_SET(reg_enable_type, 1); 3424 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3425 break; 3426 case QMOD_CREDIT_LOOP_COUNT_1: /* (cntl & 0x00080000) */ 3427 /* write to pcs_clockcnt0 */ 3428 TX_X4_SP0_LOOPCNTr_LOOPCNT1f_SET(reg_loopcnt, userCredit); 3429 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_LOOPCNTr(pc, reg_loopcnt)); 3430 /*Set the override enable*/ 3431 SC_X4_FLD_OVRR_EN0_TYPEr_LOOPCNT1_OENf_SET(reg_enable_type, 1); 3432 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3433 break; 3434 case QMOD_CREDIT_MAC: /* (cntl & 0x00100000) */ 3435 /* write to mac_creditgencnt */ 3436 TX_X4_SP0_MAC_CREDGENCNTr_MAC_CREDITGENCNTf_SET(reg_maccreditgen, userCredit); 3437 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_MAC_CREDGENCNTr(pc, reg_maccreditgen)); 3438 /*Set the override enable*/ 3439 SC_X4_FLD_OVRR_EN0_TYPEr_MAC_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 3440 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3441 break; 3442 case QMOD_CREDIT_PCS_CLOCK_COUNT_0: /* (cntl & 0x00200000) */ 3443 /* write to pcs_clockcnt0 */ 3444 TX_X4_SP0_PCS_CLKCNT0r_PCS_CLOCKCNT0f_SET(reg_pcs_clk_cnt, userCredit); 3445 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3446 /*Set the override enable*/ 3447 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CLOCKCNT0_OENf_SET(reg_enable_type, 1); 3448 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3449 break; 3450 case QMOD_CREDIT_PCS_GEN_COUNT: /* (cntl & 0x00400000) */ 3451 /* write to pcs_creditgencnt */ 3452 TX_X4_SP0_PCS_CREDGENCNTr_PCS_CREDITGENCNTf_SET(reg_pcs_creditgen, userCredit) ; 3453 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CREDGENCNTr(pc, reg_pcs_creditgen)); 3454 /*Set the override enable*/ 3455 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITGENCNT_OENf_SET(reg_enable_type, 1); 3456 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3457 break; 3458 case QMOD_CREDIT_EN: /* (cntl & 0x00800000) */ 3459 /* write to pcs_crden */ 3460 TX_X4_SP0_PCS_CLKCNT0r_PCS_CREDITENABLEf_SET(reg_pcs_clk_cnt, userCredit); 3461 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3462 /*Set the override enable*/ 3463 SC_X4_FLD_OVRR_EN0_TYPEr_PCS_CREDITENABLE_OENf_SET(reg_enable_type, 1); 3464 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3465 break; 3466 case QMOD_CREDIT_PCS_REPCNT: /* (cntl & 0x01000000) */ 3467 /* write to pcs_repcnt */ 3468 TX_X4_SP0_PCS_CLKCNT0r_REPLICATION_CNTf_SET(reg_pcs_clk_cnt, userCredit); 3469 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_PCS_CLKCNT0r(pc, reg_pcs_clk_cnt)); 3470 /*Set the override enable*/ 3471 SC_X4_FLD_OVRR_EN0_TYPEr_REPLICATION_CNT_OENf_SET(reg_enable_type, 1); 3472 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3473 break; 3474 case QMOD_CREDIT_SGMII_SPD: /* (cntl & 0x02000000) */ 3475 /* write to sgmii */ 3476 TX_X4_SP0_CRED0r_SGMII_SPD_SWITCHf_SET(reg_credit0, userCredit); 3477 PHYMOD_IF_ERR_RETURN(MODIFY_TX_X4_SP0_CRED0r(pc, reg_credit0)); 3478 /*Set the override enable*/ 3479 SC_X4_FLD_OVRR_EN0_TYPEr_SGMII_SPD_SWITCH_OENf_SET(reg_enable_type, 1); 3480 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_FLD_OVRR_EN0_TYPEr(pc, reg_enable_type)); 3481 break; 3482 default: 3483 return PHYMOD_E_FAIL; 3484 break; 3485 } 3486 return PHYMOD_E_NONE; 3487 } /* CREDIT_SET */ 3488 3489 /** 3490 @brief Read the 16 bit rev. id value etc. 3491 @param pc handle to current TSCE context (#PHYMOD_ST) 3492 @returns The value PHYMOD_E_NONE upon successful completion 3493 @details 3494 3495 */ 3496 int qmod_pmd_lane_reset(PHYMOD_ST* pc) /* PMD_LANE_RESET */ 3497 { 3498 return PHYMOD_E_NONE; 3499 } 3500 3501 #ifdef _DV_TB_ 3502 /** 3503 @brief Control per lane clause 72 auto tuning function (training patterns) 3504 @param pc handle to current TSCE context (#PHYMOD_ST) 3505 @param cl_72_type #cl72_type_t 3506 @returns The value PHYMOD_E_NONE upon successful completion 3507 @details 3508 This function enables/disables clause-72 auto-tuning per lane. It is used 3509 in 40G_KR4, 40G_CR4, 10G_KR modes etc. 3510 Lane is selected via #PHYMOD_ST::lane_select. 3511 This Function is controlled by #PHYMOD_ST::per_lane_control as follows. 3512 3513 \li 0Xxxxxxxx3 (b11): Enable CL72 hardware block 3514 \li 0Xxxxxxxx2 (b01): Disable CL72 hardware block 3515 \li 0Xxxxxxxx0 (b00): no changed. 3516 \li 0Xxxxxxx3- (b011----): Forced enable CL72 under AN. 3517 \li 0Xxxxxxx7- (b111----): Forced disable CL72 under AN. 3518 \li 0Xxxxxxx1- (b001----): Default CL72 under AN. 3519 \li 0Xxxxxxx0- (b000----): no changed 3520 \li 0Xxxxxx100 : read back CL72 HW en bit and put in accData. 3521 3522 */ 3523 int qmod_clause72_control(PHYMOD_ST* pc, cl72_type_t cl_72_type) /* CLAUSE_72_CONTROL */ 3524 { 3525 return PHYMOD_E_NONE; 3526 } /* clause72_control */ 3527 #endif /* _DV_TB_ */ 3528 3529 #ifdef _DV_TB_ 3530 3531 int qmod_prbs_check(PHYMOD_ST* pc, int real_check, int *prbs_status) 3532 { 3533 TLB_RX_PRBS_CHK_LOCK_STSr_t reg_prbs_chk_lock; 3534 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_t reg_prbs_err_cnt_msb; 3535 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_t reg_prbs_err_cnt_lsb; 3536 int lock, lock_lost, err ; 3537 3538 QMOD_DBG_IN_FUNC_INFO(pc); 3539 pc->accData = 0 ; 3540 3541 TLB_RX_PRBS_CHK_LOCK_STSr_CLR(reg_prbs_chk_lock); 3542 TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_CLR(reg_prbs_err_cnt_msb); 3543 TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_CLR(reg_prbs_err_cnt_lsb); 3544 3545 PHYMOD_IF_ERR_RETURN 3546 ( READ_TLB_RX_PRBS_CHK_LOCK_STSr(pc, ®_prbs_chk_lock)); 3547 PHYMOD_IF_ERR_RETURN 3548 (READ_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr(pc, ®_prbs_err_cnt_msb)); 3549 PHYMOD_IF_ERR_RETURN 3550 (READ_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr(pc, ®_prbs_err_cnt_lsb)); 3551 3552 lock = TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock) ? 1 : 0 ; 3553 lock_lost = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb) ? 1 : 0 ; 3554 err = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 3555 err = (err << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 3556 3557 #ifdef _DV_TB_ 3558 printf("prbs_check u=%0d p=%0d ln=%0d lck=%0d lost=%0d err=%0d(H%x L%x)\n", 3559 pc->unit, pc->port, pc->this_lane, lock, lock_lost, err, reg_prbs_err_cnt_msb, reg_prbs_err_cnt_lsb); 3560 #endif 3561 3562 if (TLB_RX_PRBS_CHK_LOCK_STSr_PRBS_CHK_LOCKf_GET(reg_prbs_chk_lock)) { 3563 if (TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 3564 /* locked now but lost before */ 3565 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb); 3566 *prbs_status = (*prbs_status << 16) | TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) | 1 ; /* locked once, so one error at least */ 3567 pc->accData = real_check ? 1 : 0 ; 3568 return PHYMOD_E_FAIL; 3569 } else { 3570 *prbs_status = TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_ERR_CNT_MSBf_GET(reg_prbs_err_cnt_msb) ; 3571 *prbs_status = (*prbs_status << 16)| TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_PRBS_CHK_ERR_CNT_LSBf_GET(reg_prbs_err_cnt_lsb) ; 3572 if (err) { 3573 pc->accData = real_check ? 1 : 0 ; 3574 return PHYMOD_E_FAIL; 3575 } 3576 } 3577 } else { 3578 if(TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_PRBS_CHK_LOCK_LOST_LHf_GET(reg_prbs_err_cnt_msb)) { 3579 *prbs_status = -2 ; /* locked before but lost now */ 3580 pc->accData = real_check ? 1 : 0 ; 3581 return PHYMOD_E_FAIL; 3582 } else { 3583 *prbs_status = -1 ; /* never locked */ 3584 pc->accData = real_check ? 1 : 0 ; 3585 return PHYMOD_E_FAIL; 3586 } 3587 } 3588 return PHYMOD_E_NONE ; 3589 } 3590 #endif /* _DV_TB_ */ 3591 3592 #ifdef _DV_TB_ 3593 3594 int qmod_prbs_mode(PHYMOD_ST* pc, int port, int prbs_inv, int pattern_type, int prbs_check_mode) /* PRBS_MODE */ 3595 { 3596 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 3597 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 3598 /* SC_X4_BYPASSr_t reg_bypass; */ 3599 3600 /*int prbs_check_mode ; */ 3601 int prbs_sel_tx, prbs_inv_tx ; 3602 int prbs_sel_rx, prbs_inv_rx ; 3603 3604 3605 QMOD_DBG_IN_FUNC_INFO(pc); 3606 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 3607 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 3608 3609 prbs_sel_tx = pattern_type; 3610 prbs_sel_rx = pattern_type; 3611 prbs_inv_tx = prbs_inv; 3612 prbs_inv_rx = prbs_inv; 3613 3614 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_SET(reg_prbs_gen_cfg, prbs_sel_tx); 3615 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_SET(reg_prbs_gen_cfg, prbs_inv_tx); 3616 3617 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 3618 3619 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODEf_SET(reg_prbs_chk_cfg, prbs_check_mode); 3620 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_SET(reg_prbs_chk_cfg, prbs_sel_rx); 3621 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_SET(reg_prbs_chk_cfg, prbs_inv_rx); 3622 3623 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 3624 3625 return PHYMOD_E_NONE; 3626 3627 } /* PRBS_MODE */ 3628 #endif /* _DV_TB_ */ 3629 3630 #ifdef _DV_TB_ 3631 3632 int qmod_prbs_control(PHYMOD_ST* pc, int prbs_enable) /* PRBS_CONTROL */ 3633 { 3634 TLB_TX_PRBS_GEN_CFGr_t reg_prbs_gen_cfg; 3635 TLB_RX_PRBS_CHK_CFGr_t reg_prbs_chk_cfg; 3636 int prbs_rx_en, prbs_tx_en ; 3637 3638 QMOD_DBG_IN_FUNC_INFO(pc); 3639 TLB_TX_PRBS_GEN_CFGr_CLR(reg_prbs_gen_cfg); 3640 TLB_RX_PRBS_CHK_CFGr_CLR(reg_prbs_chk_cfg); 3641 3642 prbs_tx_en = prbs_enable; 3643 prbs_rx_en = prbs_enable; 3644 3645 TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_SET(reg_prbs_gen_cfg, prbs_tx_en); 3646 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_TX_PRBS_GEN_CFGr(pc, reg_prbs_gen_cfg)); 3647 3648 TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_SET(reg_prbs_chk_cfg, prbs_rx_en); 3649 PHYMOD_IF_ERR_RETURN (MODIFY_TLB_RX_PRBS_CHK_CFGr(pc, reg_prbs_chk_cfg)); 3650 3651 return PHYMOD_E_NONE; 3652 3653 } /* PRBS_CONTROL */ 3654 #endif /* _DV_TB_ */ 3655 3656 /** 3657 @brief Sets CJPAT/CRPAT parameters for a particular port 3658 @param pc handle to current TSCE context (#PHYMOD_ST) 3659 @param port handle to current TSCE context (#PHYMOD_ST) 3660 @param pattern_type type of CJPat 3661 @param pkt_number number of packets 3662 @param pkt_size size of packets 3663 @param ipg_size IPG between packets 3664 @returns The value PHYMOD_E_NONE upon successful completion 3665 3666 This function enables either a CJPAT or CRPAT for a particular port. 3667 The speed mode of the lane must be chosen from the enumerated type 3668 #qmod_spd_intfc_type and set in the 3669 #PHYMOD_ST::spd_intf field. To enable CJPAT, set #PHYMOD_ST::per_lane_control to 3670 the value #USE_CJPAT; to enable CRPAT, set #PHYMOD_ST::per_lane_control to the 3671 value #USE_CRPAT. This function is used in tandem with qmod_cjpat_crpat_check(). 3672 3673 */ 3674 3675 int qmod_cjpat_crpat_mode_set(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf, int port, int pattern_type, int pkt_number, int pkt_size, int ipg_size) /* CJPAT_CRPAT_MODE_SET */ 3676 { 3677 3678 int number_pkt, crc_check,intf_type, rx_port_sel, tx_port_sel; 3679 int pkt_size_int, ipg_size_int,payload_type; 3680 uint16_t data16 ; 3681 3682 BCMI_QTC_XGXS_PKTGENCTL1r_t reg_pktgenctl1; 3683 BCMI_QTC_XGXS_PKTGENCTL2r_t reg_pktgenctl2; 3684 BCMI_QTC_XGXS_PAYLOADBYTESr_t payloadbytes; 3685 3686 QMOD_DBG_IN_FUNC_INFO(pc); 3687 BCMI_QTC_XGXS_PKTGENCTL1r_CLR(reg_pktgenctl1); 3688 BCMI_QTC_XGXS_PKTGENCTL2r_CLR(reg_pktgenctl2); 3689 BCMI_QTC_XGXS_PAYLOADBYTESr_CLR(payloadbytes); 3690 3691 3692 number_pkt = pkt_number ; 3693 crc_check = 1 ; 3694 rx_port_sel= port*4 ; 3695 tx_port_sel= port*4 ; 3696 3697 3698 pkt_size_int = pkt_size ; 3699 /* pkt_size_int = 1; 3700 ipg_size_int = 8 ;*/ 3701 ipg_size_int = ipg_size ; 3702 3703 /* payload_type = pattern_type; */ 3704 3705 if ((pattern_type == 0x9) | (pattern_type == 0xA)) { 3706 payload_type = 0; 3707 } else { 3708 payload_type = pattern_type; 3709 } 3710 3711 3712 /* intf_type 0: XLGMII/XGMII; 1: MIII/GMII */ 3713 3714 intf_type = ((spd_intf == QMOD_SPD_10_X1_SGMII) | 3715 (spd_intf == QMOD_SPD_100_X1_SGMII) | 3716 (spd_intf == QMOD_SPD_1000_X1_SGMII) | 3717 (spd_intf == QMOD_SPD_10_SGMII) | 3718 (spd_intf == QMOD_SPD_100_SGMII) | 3719 (spd_intf == QMOD_SPD_1000_SGMII) | 3720 (spd_intf == QMOD_SPD_2500) | 3721 (spd_intf == QMOD_SPD_2500_X1)| 3722 (spd_intf == QMOD_SPD_10_X1_10)| 3723 (spd_intf == QMOD_SPD_100_X1_10)| 3724 (spd_intf == QMOD_SPD_1000_X1_10)| 3725 (spd_intf == QMOD_SPD_10_X1_12P5)| 3726 (spd_intf == QMOD_SPD_100_X1_12P5)| 3727 (spd_intf == QMOD_SPD_1000_X1_12P5)| 3728 (spd_intf == QMOD_SPD_2500_X1_12P5) 3729 ) ? 0 : 1; 3730 3731 3732 /* if payload type is Repeat 2 Bytes in 0x9040*/ 3733 3734 if (payload_type == 0) { 3735 data16 = 0x2323; 3736 BCMI_QTC_XGXS_PAYLOADBYTESr_BYTE1f_SET(payloadbytes, ((data16 >> 8) & 0xff)); 3737 BCMI_QTC_XGXS_PAYLOADBYTESr_BYTE0f_SET(payloadbytes, (data16 & 0xff)); 3738 BCMI_QTC_XGXS_WRITE_PAYLOADBYTESr(pc,payloadbytes); 3739 } 3740 3741 /* 0x9030 */ 3742 3743 BCMI_QTC_XGXS_PKTGENCTL1r_TX_PORT_SELf_SET(reg_pktgenctl1, tx_port_sel); 3744 BCMI_QTC_XGXS_PKTGENCTL1r_RX_PORT_SELf_SET(reg_pktgenctl1, rx_port_sel); 3745 BCMI_QTC_XGXS_PKTGENCTL1r_RX_PKT_CHECK_ENf_SET(reg_pktgenctl1, crc_check); 3746 BCMI_QTC_XGXS_PKTGENCTL1r_RX_BUS_TYPEf_SET(reg_pktgenctl1, intf_type); 3747 BCMI_QTC_XGXS_PKTGENCTL1r_NUMBER_PKTf_SET(reg_pktgenctl1, number_pkt); 3748 3749 PHYMOD_IF_ERR_RETURN 3750 (BCMI_QTC_XGXS_WRITE_PKTGENCTL1r(pc, reg_pktgenctl1)); 3751 3752 /*BCMI_QTC_XGXS_WRITE_PKTGENCTL1r*/ 3753 3754 /* 0x9031 */ 3755 3756 BCMI_QTC_XGXS_PKTGENCTL2r_IPG_SIZEf_SET(reg_pktgenctl2, ipg_size_int); 3757 BCMI_QTC_XGXS_PKTGENCTL2r_PKT_SIZEf_SET(reg_pktgenctl2, pkt_size_int); 3758 BCMI_QTC_XGXS_PKTGENCTL2r_PAYLOAD_TYPEf_SET(reg_pktgenctl2, payload_type); 3759 BCMI_QTC_XGXS_PKTGENCTL2r_TX_BUS_TYPEf_SET(reg_pktgenctl2, intf_type); 3760 3761 PHYMOD_IF_ERR_RETURN 3762 (BCMI_QTC_XGXS_WRITE_PKTGENCTL2r(pc, reg_pktgenctl2)); 3763 3764 3765 3766 return PHYMOD_E_NONE; 3767 } /* int qmod_cjpat_crpat_mode_set */ 3768 3769 /** 3770 @brief Checks CJPAT/CRPAT parameters for a particular port 3771 @param pc handle to current TSCE context (#PHYMOD_ST) 3772 @returns The value PHYMOD_E_NONE upon successful completion 3773 3774 This function checks for CJPAT or CRPAT for a particular port. The speed mode 3775 of the lane must be chosen from the enumerated type #qmod_spd_intfc_type and 3776 set in the #PHYMOD_ST::spd_intf field. CJPAT/CRPAT must first enabled using 3777 #qmod_cjpat_crpat_control(). The duration of packet transmission is controlled 3778 externally and is the time duration between the two function calls above. 3779 3780 This function compares the CJPAT/CRPAT TX and RX counters and prints the 3781 results. Currently only packet count is supported. 3782 3783 This function reads the following registers: 3784 3785 \li PATGEN1_TXPKTCNT_U (0xC040) Upper 16b of count of Transmitted packets 3786 \li PATGEN1_TXPKTCNT_L (0xC041) Lower 16b of count of Transmitted packets 3787 \li PATGEN1_RXPKTCNT_U (0xC042) Upper 16b of count of Recieved packets 3788 \li PATGEN1_RXPKTCNT_L (0xC043) Lower 16b of count of Recieved packets 3789 \li PKTGEN0_CRCERRORCOUNT (0x9033) CRC error conunt 3790 */ 3791 3792 int qmod_cjpat_crpat_check(PHYMOD_ST* pc) /* CJPAT_CRPAT_CHECK */ 3793 { 3794 return PHYMOD_E_FAIL; 3795 #if 0 3796 Disabled support for this function. Will figure out how to do this later. 3797 uint32_t sp0_tx_cnt, sp0_rx_cnt; 3798 uint32_t sp1_tx_cnt, sp1_rx_cnt; 3799 uint32_t sp2_tx_cnt, sp2_rx_cnt; 3800 uint32_t sp3_tx_cnt, sp3_rx_cnt; 3801 3802 /* for SP0 */ 3803 PKT_CTRS_X4_SP0_TXPKTCNT_Ur_t sp0_reg_tx_u; /* To do: change reg_tx_* names by adding SP0, SP1 .. : DONE*/ 3804 PKT_CTRS_X4_SP0_TXPKTCNT_Lr_t sp0_reg_tx_l; 3805 PKT_CTRS_X4_SP0_RXPKTCNT_Ur_t sp0_reg_rx_u; 3806 PKT_CTRS_X4_SP0_RXPKTCNT_Lr_t sp0_reg_rx_l; 3807 3808 /* for SP1 */ 3809 PKT_CTRS_X4_SP1_TXPKTCNT_Ur_t sp1_reg_tx_u; 3810 PKT_CTRS_X4_SP1_TXPKTCNT_Lr_t sp1_reg_tx_l; 3811 PKT_CTRS_X4_SP1_RXPKTCNT_Ur_t sp1_reg_rx_u; 3812 PKT_CTRS_X4_SP1_RXPKTCNT_Lr_t sp1_reg_rx_l; 3813 3814 /* for SP2 */ 3815 PKT_CTRS_X4_SP2_TXPKTCNT_Ur_t sp2_reg_tx_u; 3816 PKT_CTRS_X4_SP2_TXPKTCNT_Lr_t sp2_reg_tx_l; 3817 PKT_CTRS_X4_SP2_RXPKTCNT_Ur_t sp2_reg_rx_u; 3818 PKT_CTRS_X4_SP2_RXPKTCNT_Lr_t sp2_reg_rx_l; 3819 3820 /* for SP3 */ 3821 PKT_CTRS_X4_SP3_TXPKTCNT_Ur_t sp3_reg_tx_u; 3822 PKT_CTRS_X4_SP3_TXPKTCNT_Lr_t sp3_reg_tx_l; 3823 PKT_CTRS_X4_SP3_RXPKTCNT_Ur_t sp3_reg_rx_u; 3824 PKT_CTRS_X4_SP3_RXPKTCNT_Lr_t sp3_reg_rx_l; 3825 3826 CRCERRCNTr_t reg_crc_cnt; 3827 3828 QMOD_DBG_IN_FUNC_INFO(pc); 3829 3830 /* for SP0 */ /* To do: implement this functionality for all SP and add check for SGMII or QSGMII modes */ 3831 3832 /*Check to be performed */ 3833 if((pc->port== 0)||(pc->port == 4)||(pc->port == 8)||(pc->port == 12)) { 3834 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur_CLR(sp0_reg_tx_u); 3835 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_TXPKTCNT_Ur(pc, &sp0_reg_tx_u); 3836 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr_CLR(sp0_reg_tx_l); 3837 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_TXPKTCNT_Lr(pc, &sp0_reg_tx_l); 3838 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur_CLR(sp0_reg_rx_u); 3839 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_RXPKTCNT_Ur(pc, &sp0_reg_rx_u); 3840 BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr_CLR(sp0_reg_rx_l); 3841 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP0_RXPKTCNT_Lr(pc, &sp0_reg_rx_l); 3842 3843 BCMI_QTC_XGXS_CRCERRCNTr_CLR(reg_crc_cnt); 3844 BCMI_QTC_XGXS_READ_CRCERRCNTr(pc, ®_crc_cnt); 3845 3846 sp0_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Ur_GET(sp0_reg_tx_u) <<16; 3847 sp0_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_TXPKTCNT_Lr_GET(sp0_reg_tx_l); 3848 3849 sp0_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Ur_GET(sp0_reg_rx_u) <<16; 3850 sp0_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP0_RXPKTCNT_Lr_GET(sp0_reg_rx_l); 3851 } 3852 3853 3854 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur_CLR(sp1_reg_tx_u); 3855 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_TXPKTCNT_Ur(pc, &sp1_reg_tx_u); 3856 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr_CLR(sp1_reg_tx_l); 3857 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_TXPKTCNT_Lr(pc, &sp1_reg_tx_l); 3858 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur_CLR(sp1_reg_rx_u); 3859 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_RXPKTCNT_Ur(pc, &sp1_reg_rx_u); 3860 BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr_CLR(sp1_reg_rx_l); 3861 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP1_RXPKTCNT_Lr(pc, &sp1_reg_rx_l); 3862 3863 sp1_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Ur_GET(sp1_reg_tx_u) <<16; 3864 sp1_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_TXPKTCNT_Lr_GET(sp1_reg_tx_l); 3865 3866 sp1_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Ur_GET(sp1_reg_rx_u) <<16; 3867 sp1_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP1_RXPKTCNT_Lr_GET(sp1_reg_rx_l); 3868 3869 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur_CLR(sp2_reg_tx_u); 3870 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_TXPKTCNT_Ur(pc, &sp2_reg_tx_u); 3871 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr_CLR(sp2_reg_tx_l); 3872 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_TXPKTCNT_Lr(pc, &sp2_reg_tx_l); 3873 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur_CLR(sp2_reg_rx_u); 3874 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_RXPKTCNT_Ur(pc, &sp2_reg_rx_u); 3875 BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr_CLR(sp2_reg_rx_l); 3876 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP2_RXPKTCNT_Lr(pc, &sp2_reg_rx_l); 3877 3878 sp2_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Ur_GET(sp2_reg_tx_u) <<16; 3879 sp2_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_TXPKTCNT_Lr_GET(sp2_reg_tx_l); 3880 3881 sp2_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Ur_GET(sp2_reg_rx_u) <<16; 3882 sp2_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP2_RXPKTCNT_Lr_GET(sp2_reg_rx_l); 3883 3884 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur_CLR(sp3_reg_tx_u); 3885 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_TXPKTCNT_Ur(pc, &sp3_reg_tx_u); 3886 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr_CLR(sp3_reg_tx_l); 3887 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_TXPKTCNT_Lr(pc, &sp3_reg_tx_l); 3888 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur_CLR(sp3_reg_rx_u); 3889 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_RXPKTCNT_Ur(pc, &sp3_reg_rx_u); 3890 BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr_CLR(sp3_reg_rx_l); 3891 BCMI_QTC_XGXS_READ_PKT_CTRS_X4_SP3_RXPKTCNT_Lr(pc, &sp3_reg_rx_l); 3892 3893 sp3_tx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Ur_GET(sp3_reg_tx_u) <<16; 3894 sp3_tx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_TXPKTCNT_Lr_GET(sp3_reg_tx_l); 3895 3896 sp3_rx_cnt = BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Ur_GET(sp3_reg_rx_u) <<16; 3897 sp3_rx_cnt |= BCMI_QTC_XGXS_PKT_CTRS_X4_SP3_RXPKTCNT_Lr_GET(sp3_reg_rx_l); 3898 3899 3900 #ifdef _DV_TB_ 3901 pc->accData = 0 ; 3902 #endif /* _DV_TB_ */ 3903 if( ((sp0_tx_cnt != sp0_rx_cnt) ||(sp0_tx_cnt==0)) ) { 3904 #ifdef _DV_TB_ 3905 3906 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d sp0_tx_cnt=%0d sp0_rx_cnt=%0d mismatch\n", __func__, pc->unit, pc->port, sp0_tx_cnt, sp0_rx_cnt)); 3907 pc->accData = 1; 3908 #endif /* _DV_TB_ */ 3909 return PHYMOD_E_FAIL; 3910 } 3911 /* Check the other cnt regs */ 3912 if( ((sp1_tx_cnt != sp1_rx_cnt) ||(sp1_tx_cnt!=0))||((sp2_tx_cnt != sp2_rx_cnt) ||(sp2_tx_cnt!=0))||((sp3_tx_cnt != sp3_rx_cnt) ||(sp3_tx_cnt!=0)) ) { 3913 #ifdef _DV_TB_ 3914 3915 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d sp1_tx_cnt=%0d sp1_rx_cnt=%0d sp2_tx_cnt=%0d sp2_rx_cnt=%0d sp3_tx_cnt=%0d sp3_rx_cnt=%0d mismatch\n", __func__, pc->unit, pc->port, sp1_tx_cnt, sp1_rx_cnt, sp2_tx_cnt, sp2_rx_cnt, sp3_tx_cnt, sp3_rx_cnt )); 3916 pc->accData = 1; 3917 #endif /* _DV_TB_ */ 3918 return PHYMOD_E_FAIL; 3919 } 3920 3921 3922 if(reg_crc_cnt.crcerrcnt[0]) { 3923 #ifdef _DV_TB_ 3924 3925 PHYMOD_DEBUG_ERROR(("%-22s ERROR: u=%0d p=%0d crc error=%0d\n", __func__, pc->unit, pc->port, reg_crc_cnt.crcerrcnt[0])); 3926 pc->accData = 1; 3927 #endif /* _DV_TB_ */ 3928 return PHYMOD_E_FAIL; 3929 } 3930 3931 return PHYMOD_E_NONE; 3932 #endif 3933 } 3934 3935 3936 int qmod_cjpat_crpat_control(PHYMOD_ST* pc, int enable) /* CJPAT_CRPAT_CONTROL */ 3937 { 3938 3939 PKTGENCTL2r_t reg; 3940 3941 QMOD_DBG_IN_FUNC_INFO(pc); 3942 PKTGENCTL2r_CLR(reg); 3943 /* 0x9031 */ 3944 PHYMOD_IF_ERR_RETURN 3945 (READ_PKTGENCTL2r(pc, ®)); 3946 3947 if(enable) { 3948 BCMI_QTC_XGXS_PKTGENCTL2r_PKTGEN_ENf_SET(reg, 1); 3949 3950 } else { 3951 BCMI_QTC_XGXS_PKTGENCTL2r_PKTGEN_ENf_SET(reg, 0); 3952 } 3953 PHYMOD_IF_ERR_RETURN 3954 (WRITE_PKTGENCTL2r(pc, reg)); 3955 3956 3957 return PHYMOD_E_NONE; 3958 } 3959 3960 3961 int qmod_pcs_lane_swap(PHYMOD_ST *pc, int lane_map) 3962 { 3963 3964 /* unsigned int pcs_map;*/ 3965 MAIN_LN_SWPr_t reg; 3966 QMOD_DBG_IN_FUNC_INFO(pc) ; 3967 3968 MAIN_LN_SWPr_CLR(reg); 3969 3970 MAIN_LN_SWPr_LOG0_TO_PHY_LNSWAP_SELf_SET(reg, (lane_map >> 0) & 0x3); 3971 MAIN_LN_SWPr_LOG1_TO_PHY_LNSWAP_SELf_SET(reg, (lane_map >> 4) & 0x3); 3972 MAIN_LN_SWPr_LOG2_TO_PHY_LNSWAP_SELf_SET(reg, (lane_map >> 8) & 0x3); 3973 MAIN_LN_SWPr_LOG3_TO_PHY_LNSWAP_SELf_SET(reg, (lane_map >> 12) & 0x3 ); 3974 3975 3976 PHYMOD_IF_ERR_RETURN 3977 (MODIFY_MAIN_LN_SWPr(pc, reg)) ; 3978 3979 return PHYMOD_E_NONE ; 3980 } 3981 3982 #ifdef _DV_TB_ 3983 /** 3984 @brief sets PMD TX lane swap values for all lanes simultaneously. 3985 @param pc handle to current TSCE context (#PHYMOD_ST) 3986 @returns The value PHYMOD_E_NONE upon successful completion 3987 3988 This function sets the TX lane swap values for all lanes simultaneously. 3989 3990 The TSCE has several two sets of lane swap registers per lane. This function 3991 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 3992 after all other analog/digital functionality. For RX, the lane swap occurs 3993 prior to all other analog/digital functionality. 3994 3995 It is not advisable to swap lanes without going through reset. 3996 3997 How the swap is done is indicated in the #PHYMOD_ST::per_lane_control field; 3998 bits 0 through 15 represent the swap settings for RX while bits 16 3999 through 31 represent the swap settings for TX. 4000 4001 Each 4 bit chunk within both the RX and TX sections represent the swap settings 4002 for a particular lane as follows: 4003 4004 Bits lane assignment 4005 4006 \li 15:12 TX lane 3 4007 \li 11:8 TX lane 2 4008 \li 7:4 TX lane 1 4009 \li 3:0 TX lane 0 4010 4011 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 4012 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 4013 indicating that there is no re-routing of traffic. As an example, to swap lanes 4014 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 4015 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 4016 per_lane_control should be set to 0x2301_2301. 4017 4018 */ 4019 int qmod_pmd_lane_swap(PHYMOD_ST *pc) 4020 { 4021 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg_adr_01; 4022 DIG_LN_ADDR_2_3r_t reg_adr_23; 4023 unsigned int map; 4024 unsigned int lane_addr_0, lane_addr_1, lane_addr_2, lane_addr_3; 4025 4026 QMOD_DBG_IN_FUNC_INFO(pc); 4027 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg_adr_01); 4028 DIG_LN_ADDR_2_3r_CLR(reg_adr_23); 4029 4030 map = (unsigned int)pc->per_lane_control; 4031 4032 lane_addr_0 = (map >> 16) & 0xf; 4033 lane_addr_1 = (map >> 20) & 0xf; 4034 lane_addr_2 = (map >> 24) & 0xf; 4035 lane_addr_3 = (map >> 28) & 0xf; 4036 4037 #ifdef _DV_TB_ 4038 pc->adjust_port_mode = 1; 4039 #endif 4040 #ifdef _SDK_QMOD_ 4041 4042 #endif 4043 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_0f_SET(reg_adr_01, lane_addr_0); 4044 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_1f_SET(reg_adr_01, lane_addr_1); 4045 PHYMOD_IF_ERR_RETURN 4046 (MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, reg_adr_01)); 4047 4048 DIG_LN_ADDR_2_3r_LANE_ADDR_2f_SET(reg_adr_23, lane_addr_2); 4049 DIG_LN_ADDR_2_3r_LANE_ADDR_3f_SET(reg_adr_23, lane_addr_3); 4050 4051 PHYMOD_IF_ERR_RETURN 4052 (WRITE_DIG_LN_ADDR_2_3r(pc, reg_adr_23)); 4053 4054 #ifdef _DV_TB_ 4055 pc->adjust_port_mode = 0; 4056 #endif 4057 #ifdef _SDK_QMOD_ 4058 4059 #endif 4060 return PHYMOD_E_NONE ; 4061 } 4062 #endif /* _DV_TB_ */ 4063 4064 /** 4065 @brief sets PMD TX lane swap values for all lanes simultaneously. 4066 @param pc handle to current TSCE context (#PHYMOD_ST) 4067 @returns The value PHYMOD_E_NONE upon successful completion 4068 4069 This function sets the TX lane swap values for all lanes simultaneously. 4070 4071 The TSCE has several two sets of lane swap registers per lane. This function uses the 4072 lane swap registers closest to the pads. For TX, the lane swap occurs after all other 4073 analog/digital functionality. For RX, the lane swap occurs prior to all other 4074 analog/digital functionality. 4075 4076 It is not advisable to swap lanes without going through reset. 4077 4078 How the swap is done is indicated in the #PHYMOD_ST::per_lane_control field; 4079 bits 0 through 15 represent the swap settings for RX while bits 16 4080 through 31 represent the swap settings for TX. 4081 4082 Each 4 bit chunk within both the RX and TX sections represent the swap settings 4083 for a particular lane as follows: 4084 4085 Bits lane assignment 4086 4087 \li 15:12 TX lane 3 4088 \li 11:8 TX lane 2 4089 \li 7:4 TX lane 1 4090 \li 3:0 TX lane 0 4091 4092 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 4093 mapping. By default, the equivalent per_lane_control settings are 0x3210_3210, 4094 indicating that there is no re-routing of traffic. As an example, to swap lanes 4095 0 and 1 for both RX and TX, the per_lane_control should be set to 0x3201_3201. 4096 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 4097 per_lane_control should be set to 0x2301_2301. 4098 4099 */ 4100 4101 int qmod_pmd_lane_swap_tx(PHYMOD_ST *pc, uint32_t tx_lane_map) 4102 { 4103 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 4104 DIG_TX_LN_MAP_0_1_2r_t reg; 4105 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg1; 4106 4107 QMOD_DBG_IN_FUNC_INFO(pc); 4108 DIG_TX_LN_MAP_0_1_2r_CLR(reg); 4109 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg1); 4110 4111 tx_lane_map_0 = tx_lane_map & 0xf; 4112 tx_lane_map_1 = (tx_lane_map>>4) & 0xf; 4113 tx_lane_map_2 = (tx_lane_map>>8) & 0xf; 4114 tx_lane_map_3 = (tx_lane_map>>12) & 0xf; 4115 4116 #ifdef _DV_TB_ 4117 pc->adjust_port_mode = 1; 4118 #endif 4119 #ifdef _SDK_QMOD_ 4120 4121 #endif 4122 4123 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_SET(reg, tx_lane_map_0); 4124 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_SET(reg, tx_lane_map_1); 4125 DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_SET(reg, tx_lane_map_2); 4126 4127 PHYMOD_IF_ERR_RETURN 4128 (WRITE_DIG_TX_LN_MAP_0_1_2r(pc, reg)); 4129 4130 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_SET(reg1, tx_lane_map_3); 4131 PHYMOD_IF_ERR_RETURN 4132 (MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, reg1)); 4133 4134 #ifdef _DV_TB_ 4135 pc->adjust_port_mode = 0; 4136 #endif 4137 #ifdef _SDK_QMOD_ 4138 4139 #endif 4140 return PHYMOD_E_NONE ; 4141 } 4142 4143 /** 4144 @brief sets PMD TX lane swap values for all lanes simultaneously. 4145 @param pc handle to current TSCE context (#PHYMOD_ST) 4146 @param addr_lane_index lane swap info as described in description 4147 @returns The value PHYMOD_E_NONE upon successful completion 4148 4149 This function sets the TX lane swap values for all lanes simultaneously. 4150 4151 The TSCE has several two sets of lane swap registers per lane. This function 4152 uses the lane swap registers closest to the pads. For TX, the lane swap occurs 4153 after all other analog/digital functionality. For RX, the lane swap occurs 4154 prior to all other analog/digital functionality. 4155 4156 It is not advisable to swap lanes without going through reset. 4157 4158 How the swap is done is indicated in the lane control field; 4159 bits 0 through 15 represent the swap settings for RX while bits 16 4160 through 31 represent the swap settings for TX. 4161 4162 Each 4 bit chunk within both the RX and TX sections represent the swap settings 4163 for a particular lane as follows: 4164 4165 Bits lane assignment 4166 4167 \li 15:12 TX lane 3 4168 \li 11:8 TX lane 2 4169 \li 7:4 TX lane 1 4170 \li 3:0 TX lane 0 4171 4172 Each 4-bit value may be either 0, 1, 2 or 3, with the value indicating the lane 4173 mapping. By default, the equivalent addr_lane_index settings are 0x3210_3210, 4174 indicating that there is no re-routing of traffic. As an example, to swap lanes 4175 0 and 1 for both RX and TX, the addr_lane_index should be set to 0x3201_3201. 4176 To swap lanes 0 and 1, and also lanes 2 and 3 for both RX and TX, the 4177 addr_lane_index should be set to 0x2301_2301. 4178 4179 */ 4180 int qmod_pmd_addr_lane_swap(PHYMOD_ST *pc, uint32_t addr_lane_index) 4181 { 4182 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg_adr_01; 4183 DIG_LN_ADDR_2_3r_t reg_adr_23; 4184 unsigned int map; 4185 unsigned int lane_addr_0, lane_addr_1, lane_addr_2, lane_addr_3; 4186 4187 QMOD_DBG_IN_FUNC_INFO(pc); 4188 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg_adr_01); 4189 DIG_LN_ADDR_2_3r_CLR(reg_adr_23); 4190 4191 #ifdef _DV_TB_ 4192 map = (unsigned int)pc->per_lane_control; 4193 4194 lane_addr_0 = (map >> 16) & 0xf; 4195 lane_addr_1 = (map >> 20) & 0xf; 4196 lane_addr_2 = (map >> 24) & 0xf; 4197 lane_addr_3 = (map >> 28) & 0xf; 4198 4199 #else 4200 map = addr_lane_index ; 4201 4202 lane_addr_0 = (map >> 0) & 0xf; 4203 lane_addr_1 = (map >> 4) & 0xf; 4204 lane_addr_2 = (map >> 8) & 0xf; 4205 lane_addr_3 = (map >> 12) & 0xf; 4206 #endif 4207 4208 #ifdef _DV_TB_ 4209 pc->adjust_port_mode = 1; 4210 #endif 4211 4212 #ifdef _SDK_QMOD_ 4213 4214 #endif 4215 4216 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_0f_SET(reg_adr_01, lane_addr_0); 4217 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_LANE_ADDR_1f_SET(reg_adr_01, lane_addr_1); 4218 PHYMOD_IF_ERR_RETURN 4219 (MODIFY_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, reg_adr_01)); 4220 4221 DIG_LN_ADDR_2_3r_LANE_ADDR_2f_SET(reg_adr_23, lane_addr_2); 4222 DIG_LN_ADDR_2_3r_LANE_ADDR_3f_SET(reg_adr_23, lane_addr_3); 4223 4224 PHYMOD_IF_ERR_RETURN 4225 (WRITE_DIG_LN_ADDR_2_3r(pc, reg_adr_23)); 4226 4227 #ifdef _DV_TB_ 4228 pc->adjust_port_mode = 0; 4229 #endif 4230 #ifdef _SDK_QMOD_ 4231 4232 #endif 4233 4234 return PHYMOD_E_NONE ; 4235 } 4236 4237 4238 /** 4239 @brief Control pram ablity 4240 @param pc handle to current TSCE context (#PHYMOD_ST) 4241 @param enable Enable value for PRAM set. 4242 @returns The value PHYMOD_E_NONE upon successful completion 4243 @details Per core PMD resets (both datapath and entire core) 4244 We only intend to use this function if the PMD has never been initialized. 4245 */ 4246 /* ???? */ 4247 int qmod_pram_abl_enable_set(PHYMOD_ST* pc, int enable) /* PMD_RESET_SEQ */ 4248 { 4249 PMD_X1_CTLr_t reg_pmd_x1_ctrl; 4250 4251 PMD_X1_CTLr_CLR(reg_pmd_x1_ctrl); 4252 4253 PMD_X1_CTLr_PRAM_ABILITYf_SET(reg_pmd_x1_ctrl,enable); 4254 PHYMOD_IF_ERR_RETURN(MODIFY_PMD_X1_CTLr(pc,reg_pmd_x1_ctrl)); 4255 4256 return PHYMOD_E_NONE; 4257 } 4258 4259 /** 4260 @brief is used to power down transmitter or receiver per lane basis. 4261 @param pc handle to current TSCE context (a.k.a #PHYMOD_ST) 4262 @returns PHYMOD_E_NONE if no errors. PHYMOD_E_FAIL else. 4263 @details 4264 4265 This function is used to power on/off the TX and RX lanes in one swoop. To 4266 change the power down state for TX or RX, bit-wise OR one of the following 4267 4268 \li CHANGE_TX0_PWRED_STATE 0x10 4269 \li CHANGE_TX1_PWRED_STATE 0x20 4270 \li CHANGE_TX2_PWRED_STATE 0x40 4271 \li CHANGE_TX3_PWRED_STATE 0x80 4272 4273 <br> 4274 4275 \li CHANGE_RX0_PWRED_STATE 0x1000 4276 \li CHANGE_RX1_PWRED_STATE 0x2000 4277 \li CHANGE_RX2_PWRED_STATE 0x4000 4278 \li CHANGE_RX3_PWRED_STATE 0x8000 4279 4280 into #PHYMOD_ST::per_lane_control. These values serve as masks for whether the 4281 power on/off for a particular lane should be changed. 4282 4283 To turn off the power for the selected TX/RX lane, bit-wise OR one of these 4284 4285 \li PWR_DOWN_TX0 0x1 4286 \li PWR_DOWN_TX1 0x2 4287 \li PWR_DOWN_TX2 0x4 4288 \li PWR_DOWN_TX3 0x8 4289 4290 <br> 4291 4292 \li PWR_DOWN_RX0 0x100 4293 \li PWR_DOWN_RX1 0x200 4294 \li PWR_DOWN_RX2 0x400 4295 \li PWR_DOWN_RX3 0x800 4296 4297 into #PHYMOD_ST::per_lane_control. 4298 4299 As an example, to turn off the TX power on lane 0, turn on the TX power on lane1, 4300 leave the RX power states along with the TX power on lanes 2 and 3 unaffected, set 4301 4302 #PHYMOD_ST::per_lane_control = CHANGE_TX0_PWRED_STATE | 4303 PWR_DOWN_TX0 | 4304 CHANGE_TX1_PWRED_STATE; 4305 */ 4306 int qmod_power_control(PHYMOD_ST* pc) 4307 { 4308 return PHYMOD_E_NONE; 4309 } 4310 4311 #ifdef _DV_TB_ 4312 /** 4313 @brief Read the 16 bit rev. id value etc. 4314 @param pc handle to current TSCE context (#PHYMOD_ST) 4315 @returns The value PHYMOD_E_NONE upon successful 4316 @details PCS Init calls this Per Port PCS Init routine 4317 */ 4318 int _qmod_set_port_mode_select(PHYMOD_ST* pc) 4319 { 4320 MAIN_SETUPr_t reg; 4321 4322 MAIN_LN_SWPr_t ln_swp_reg; 4323 QMOD_DBG_IN_FUNC_INFO(pc); 4324 4325 MAIN_LN_SWPr_CLR(ln_swp_reg); 4326 4327 MAIN_LN_SWPr_MAC_TO_PCS_LANE_MAP_SEL_SGMIIf_SET(ln_swp_reg,pc->pcs_lane_map_sel); 4328 4329 PHYMOD_IF_ERR_RETURN 4330 (MODIFY_MAIN_LN_SWPr(pc, ln_swp_reg)) ; 4331 4332 MAIN_SETUPr_CLR(reg); 4333 if(pc->tsc_touched == 1) { 4334 MAIN_SETUPr_CLR(reg); 4335 } else { 4336 MAIN_SETUPr_MASTER_PORT_NUMf_SET(reg, pc->master_portnum); 4337 MAIN_SETUPr_PLL_RESET_ENf_SET(reg, 1); 4338 } 4339 4340 if(pc->sc_mode == QMOD_SC_MODE_AN_CL37) { 4341 MAIN_SETUPr_CL37_HIGH_VCOf_SET(reg, pc->cl37_high_vco); 4342 MAIN_SETUPr_SINGLE_PORT_MODEf_SET(reg, pc->single_port_mode); 4343 MAIN_SETUPr_REFCLK_SELf_SET(reg, pc->refclk); 4344 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN_SETUPr(pc, reg)); 4345 } else { 4346 MAIN_SETUPr_CL37_HIGH_VCOf_SET(reg, pc->cl37_high_vco); 4347 MAIN_SETUPr_REFCLK_SELf_SET(reg, pc->refclk); 4348 PHYMOD_IF_ERR_RETURN (MODIFY_MAIN_SETUPr(pc, reg)); 4349 } 4350 return PHYMOD_E_NONE; 4351 } 4352 #endif 4353 4354 #ifdef _DV_TB_ 4355 /** 4356 @brief Read the 16 bit rev. id value etc. 4357 @param pc handle to current TSCE context (#PHYMOD_ST) 4358 @returns The value PHYMOD_E_NONE upon successful completion 4359 @details Per Port PCS Init 4360 4361 */ 4362 /* TBD PARAMETERIZE CODE for SDK*/ 4363 int _configure_st_entry(int st_entry_num, int st_entry_speed, PHYMOD_ST* pc) 4364 { 4365 4366 SC_X1_SPD_OVRR0_SPDr_t reg0_ovr_spd; 4367 SC_X1_SPD_OVRR0_0r_t reg0_ovr; 4368 SC_X1_SPD_OVRR0_1r_t reg0_ovr1; 4369 SC_X1_SPD_OVRR0_2r_t reg0_ovr2; 4370 SC_X1_SPD_OVRR0_3r_t reg0_ovr3; 4371 SC_X1_SPD_OVRR0_4r_t reg0_ovr4; 4372 SC_X1_SPD_OVRR0_5r_t reg0_ovr5; 4373 SC_X1_SPD_OVRR0_6r_t reg0_ovr6; 4374 4375 SC_X1_SPD_OVRR1_SPDr_t reg1_ovr_spd; 4376 SC_X1_SPD_OVRR1_0r_t reg1_ovr; 4377 SC_X1_SPD_OVRR1_1r_t reg1_ovr1; 4378 SC_X1_SPD_OVRR1_2r_t reg1_ovr2; 4379 SC_X1_SPD_OVRR1_3r_t reg1_ovr3; 4380 SC_X1_SPD_OVRR1_4r_t reg1_ovr4; 4381 SC_X1_SPD_OVRR1_5r_t reg1_ovr5; 4382 SC_X1_SPD_OVRR1_6r_t reg1_ovr6; 4383 4384 SC_X1_SPD_OVRR2_SPDr_t reg2_ovr_spd; 4385 SC_X1_SPD_OVRR2_0r_t reg2_ovr; 4386 SC_X1_SPD_OVRR2_1r_t reg2_ovr1; 4387 SC_X1_SPD_OVRR2_2r_t reg2_ovr2; 4388 SC_X1_SPD_OVRR2_3r_t reg2_ovr3; 4389 SC_X1_SPD_OVRR2_4r_t reg2_ovr4; 4390 SC_X1_SPD_OVRR2_5r_t reg2_ovr5; 4391 SC_X1_SPD_OVRR2_6r_t reg2_ovr6; 4392 4393 SC_X1_SPD_OVRR3_SPDr_t reg3_ovr_spd; 4394 SC_X1_SPD_OVRR3_0r_t reg3_ovr; 4395 SC_X1_SPD_OVRR3_1r_t reg3_ovr1; 4396 SC_X1_SPD_OVRR3_2r_t reg3_ovr2; 4397 SC_X1_SPD_OVRR3_3r_t reg3_ovr3; 4398 SC_X1_SPD_OVRR3_4r_t reg3_ovr4; 4399 SC_X1_SPD_OVRR3_5r_t reg3_ovr5; 4400 SC_X1_SPD_OVRR3_6r_t reg3_ovr6; 4401 4402 if(st_entry_num == 0) { 4403 4404 SC_X1_SPD_OVRR0_SPDr_CLR(reg0_ovr_spd); 4405 SC_X1_SPD_OVRR0_SPDr_SPEEDf_SET(reg0_ovr_spd, st_entry_speed); 4406 4407 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_SPDr(pc, reg0_ovr_spd)); 4408 4409 SC_X1_SPD_OVRR0_0r_CLR(reg0_ovr); 4410 SC_X1_SPD_OVRR0_1r_CLR(reg0_ovr1); 4411 SC_X1_SPD_OVRR0_2r_CLR(reg0_ovr2); 4412 SC_X1_SPD_OVRR0_3r_CLR(reg0_ovr3); 4413 SC_X1_SPD_OVRR0_4r_CLR(reg0_ovr4); 4414 SC_X1_SPD_OVRR0_5r_CLR(reg0_ovr5); 4415 SC_X1_SPD_OVRR0_6r_CLR(reg0_ovr6); 4416 4417 SC_X1_SPD_OVRR0_0r_OS_MODEf_SET(reg0_ovr, pc->t_pma_os_mode); 4418 SC_X1_SPD_OVRR0_0r_CL36BYTEDELETEMODEf_SET(reg0_ovr, pc->r_desc2_byte_deletion); 4419 SC_X1_SPD_OVRR0_0r_QSGMII_ENf_SET(reg0_ovr, pc->qsgmii_mode); 4420 4421 4422 4423 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_0r(pc, reg0_ovr)); 4424 4425 SC_X1_SPD_OVRR0_1r_CLOCKCNT0f_SET(reg0_ovr1, pc->clkcnt0); 4426 SC_X1_SPD_OVRR0_1r_SGMII_SPD_SWITCHf_SET(reg0_ovr1, pc->sgmii); 4427 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_1r(pc, reg0_ovr1)); 4428 4429 SC_X1_SPD_OVRR0_2r_CLOCKCNT1f_SET(reg0_ovr2, pc->clkcnt1); 4430 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_2r(pc, reg0_ovr2)); 4431 4432 SC_X1_SPD_OVRR0_3r_LOOPCNT1f_SET(reg0_ovr3, pc->lpcnt1); 4433 SC_X1_SPD_OVRR0_3r_LOOPCNT0f_SET(reg0_ovr3, pc->lpcnt0); 4434 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_3r(pc, reg0_ovr3)); 4435 4436 SC_X1_SPD_OVRR0_4r_MAC_CREDITGENCNTf_SET(reg0_ovr4, pc->mac_cgc); 4437 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_4r(pc, reg0_ovr4)); 4438 4439 4440 SC_X1_SPD_OVRR0_5r_PCS_CLOCKCNT0f_SET(reg0_ovr5, pc->pcs_clkcnt); 4441 SC_X1_SPD_OVRR0_5r_PCS_CREDITENABLEf_SET(reg0_ovr5, pc->pcs_crdten); 4442 SC_X1_SPD_OVRR0_5r_REPLICATION_CNTf_SET(reg0_ovr5, pc->pcs_repcnt); 4443 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_5r(pc, reg0_ovr5)); 4444 4445 SC_X1_SPD_OVRR0_6r_PCS_CREDITGENCNTf_SET(reg0_ovr6, pc->pcs_cgc); 4446 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR0_6r(pc, reg0_ovr6)); 4447 } /* (st_entry_num == 0) */ 4448 4449 else if(st_entry_num == 1) { 4450 4451 4452 SC_X1_SPD_OVRR1_SPDr_CLR(reg1_ovr_spd); 4453 SC_X1_SPD_OVRR1_SPDr_SPEEDf_SET(reg1_ovr_spd, st_entry_speed); 4454 4455 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_SPDr(pc, reg1_ovr_spd)); 4456 4457 SC_X1_SPD_OVRR1_0r_CLR(reg1_ovr); 4458 SC_X1_SPD_OVRR1_1r_CLR(reg1_ovr1); 4459 SC_X1_SPD_OVRR1_2r_CLR(reg1_ovr2); 4460 SC_X1_SPD_OVRR1_3r_CLR(reg1_ovr3); 4461 SC_X1_SPD_OVRR1_4r_CLR(reg1_ovr4); 4462 SC_X1_SPD_OVRR1_5r_CLR(reg1_ovr5); 4463 SC_X1_SPD_OVRR1_6r_CLR(reg1_ovr6); 4464 4465 SC_X1_SPD_OVRR1_0r_OS_MODEf_SET(reg1_ovr, pc->t_pma_os_mode); 4466 SC_X1_SPD_OVRR1_0r_CL36BYTEDELETEMODEf_SET(reg1_ovr, pc->r_desc2_byte_deletion); 4467 SC_X1_SPD_OVRR1_0r_QSGMII_ENf_SET(reg1_ovr, pc->qsgmii_mode); 4468 4469 4470 4471 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_0r(pc, reg1_ovr)); 4472 4473 SC_X1_SPD_OVRR1_1r_CLOCKCNT0f_SET(reg1_ovr1, pc->clkcnt0); 4474 SC_X1_SPD_OVRR1_1r_SGMII_SPD_SWITCHf_SET(reg1_ovr1, pc->sgmii); 4475 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_1r(pc, reg1_ovr1)); 4476 4477 SC_X1_SPD_OVRR1_2r_CLOCKCNT1f_SET(reg1_ovr2, pc->clkcnt1); 4478 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_2r(pc, reg1_ovr2)); 4479 4480 SC_X1_SPD_OVRR1_3r_LOOPCNT1f_SET(reg1_ovr3, pc->lpcnt1); 4481 SC_X1_SPD_OVRR1_3r_LOOPCNT0f_SET(reg1_ovr3, pc->lpcnt0); 4482 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_3r(pc, reg1_ovr3)); 4483 4484 SC_X1_SPD_OVRR1_4r_MAC_CREDITGENCNTf_SET(reg1_ovr4, pc->mac_cgc); 4485 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_4r(pc, reg1_ovr4)); 4486 4487 4488 SC_X1_SPD_OVRR1_5r_PCS_CLOCKCNT0f_SET(reg1_ovr5, pc->pcs_clkcnt); 4489 SC_X1_SPD_OVRR1_5r_PCS_CREDITENABLEf_SET(reg1_ovr5, pc->pcs_crdten); 4490 SC_X1_SPD_OVRR1_5r_REPLICATION_CNTf_SET(reg1_ovr5, pc->pcs_repcnt); 4491 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_5r(pc, reg1_ovr5)); 4492 4493 SC_X1_SPD_OVRR1_6r_PCS_CREDITGENCNTf_SET(reg1_ovr6, pc->pcs_cgc); 4494 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR1_6r(pc, reg1_ovr6)); 4495 4496 4497 4498 } /* (st_entry_num == 1) */ 4499 4500 else if(st_entry_num == 2) { 4501 4502 SC_X1_SPD_OVRR2_SPDr_CLR(reg2_ovr_spd); 4503 SC_X1_SPD_OVRR2_SPDr_SPEEDf_SET(reg2_ovr_spd, st_entry_speed); 4504 4505 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_SPDr(pc, reg2_ovr_spd)); 4506 4507 SC_X1_SPD_OVRR2_0r_CLR(reg2_ovr); 4508 SC_X1_SPD_OVRR2_1r_CLR(reg2_ovr1); 4509 SC_X1_SPD_OVRR2_2r_CLR(reg2_ovr2); 4510 SC_X1_SPD_OVRR2_3r_CLR(reg2_ovr3); 4511 SC_X1_SPD_OVRR2_4r_CLR(reg2_ovr4); 4512 SC_X1_SPD_OVRR2_5r_CLR(reg2_ovr5); 4513 SC_X1_SPD_OVRR2_6r_CLR(reg2_ovr6); 4514 4515 SC_X1_SPD_OVRR2_0r_OS_MODEf_SET(reg2_ovr, pc->t_pma_os_mode); 4516 SC_X1_SPD_OVRR2_0r_CL36BYTEDELETEMODEf_SET(reg2_ovr, pc->r_desc2_byte_deletion); 4517 SC_X1_SPD_OVRR2_0r_QSGMII_ENf_SET(reg2_ovr, pc->qsgmii_mode); 4518 4519 4520 4521 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_0r(pc, reg2_ovr)); 4522 4523 SC_X1_SPD_OVRR2_1r_CLOCKCNT0f_SET(reg2_ovr1, pc->clkcnt0); 4524 SC_X1_SPD_OVRR2_1r_SGMII_SPD_SWITCHf_SET(reg2_ovr1, pc->sgmii); 4525 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_1r(pc, reg2_ovr1)); 4526 4527 SC_X1_SPD_OVRR2_2r_CLOCKCNT1f_SET(reg2_ovr2, pc->clkcnt1); 4528 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_2r(pc, reg2_ovr2)); 4529 4530 SC_X1_SPD_OVRR2_3r_LOOPCNT1f_SET(reg2_ovr3, pc->lpcnt1); 4531 SC_X1_SPD_OVRR2_3r_LOOPCNT0f_SET(reg2_ovr3, pc->lpcnt0); 4532 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_3r(pc, reg2_ovr3)); 4533 4534 SC_X1_SPD_OVRR2_4r_MAC_CREDITGENCNTf_SET(reg2_ovr4, pc->mac_cgc); 4535 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_4r(pc, reg2_ovr4)); 4536 4537 4538 SC_X1_SPD_OVRR2_5r_PCS_CLOCKCNT0f_SET(reg2_ovr5, pc->pcs_clkcnt); 4539 SC_X1_SPD_OVRR2_5r_PCS_CREDITENABLEf_SET(reg2_ovr5, pc->pcs_crdten); 4540 SC_X1_SPD_OVRR2_5r_REPLICATION_CNTf_SET(reg2_ovr5, pc->pcs_repcnt); 4541 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_5r(pc, reg2_ovr5)); 4542 4543 SC_X1_SPD_OVRR2_6r_PCS_CREDITGENCNTf_SET(reg2_ovr6, pc->pcs_cgc); 4544 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR2_6r(pc, reg2_ovr6)); 4545 4546 4547 } /* (st_entry_num == 2) */ 4548 4549 else /*(st_entry_num == 3) */ { 4550 4551 SC_X1_SPD_OVRR3_SPDr_CLR(reg3_ovr_spd); 4552 SC_X1_SPD_OVRR3_SPDr_SPEEDf_SET(reg3_ovr_spd, st_entry_speed); 4553 4554 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_SPDr(pc, reg3_ovr_spd)); 4555 4556 SC_X1_SPD_OVRR3_0r_CLR(reg3_ovr); 4557 SC_X1_SPD_OVRR3_1r_CLR(reg3_ovr1); 4558 SC_X1_SPD_OVRR3_2r_CLR(reg3_ovr2); 4559 SC_X1_SPD_OVRR3_3r_CLR(reg3_ovr3); 4560 SC_X1_SPD_OVRR3_4r_CLR(reg3_ovr4); 4561 SC_X1_SPD_OVRR3_5r_CLR(reg3_ovr5); 4562 SC_X1_SPD_OVRR3_6r_CLR(reg3_ovr6); 4563 4564 SC_X1_SPD_OVRR3_0r_OS_MODEf_SET(reg3_ovr, pc->t_pma_os_mode); 4565 SC_X1_SPD_OVRR3_0r_CL36BYTEDELETEMODEf_SET(reg3_ovr, pc->r_desc2_byte_deletion); 4566 SC_X1_SPD_OVRR3_0r_QSGMII_ENf_SET(reg3_ovr, pc->qsgmii_mode); 4567 4568 4569 4570 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_0r(pc, reg3_ovr)); 4571 4572 SC_X1_SPD_OVRR3_1r_CLOCKCNT0f_SET(reg3_ovr1, pc->clkcnt0); 4573 SC_X1_SPD_OVRR3_1r_SGMII_SPD_SWITCHf_SET(reg3_ovr1, pc->sgmii); 4574 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_1r(pc, reg3_ovr1)); 4575 4576 SC_X1_SPD_OVRR3_2r_CLOCKCNT1f_SET(reg3_ovr2, pc->clkcnt1); 4577 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_2r(pc, reg3_ovr2)); 4578 4579 SC_X1_SPD_OVRR3_3r_LOOPCNT1f_SET(reg3_ovr3, pc->lpcnt1); 4580 SC_X1_SPD_OVRR3_3r_LOOPCNT0f_SET(reg3_ovr3, pc->lpcnt0); 4581 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_3r(pc, reg3_ovr3)); 4582 4583 SC_X1_SPD_OVRR3_4r_MAC_CREDITGENCNTf_SET(reg3_ovr4, pc->mac_cgc); 4584 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_4r(pc, reg3_ovr4)); 4585 4586 4587 SC_X1_SPD_OVRR3_5r_PCS_CLOCKCNT0f_SET(reg3_ovr5, pc->pcs_clkcnt); 4588 SC_X1_SPD_OVRR3_5r_PCS_CREDITENABLEf_SET(reg3_ovr5, pc->pcs_crdten); 4589 SC_X1_SPD_OVRR3_5r_REPLICATION_CNTf_SET(reg3_ovr5, pc->pcs_repcnt); 4590 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_5r(pc, reg3_ovr5)); 4591 4592 SC_X1_SPD_OVRR3_6r_PCS_CREDITGENCNTf_SET(reg3_ovr6, pc->pcs_cgc); 4593 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X1_SPD_OVRR3_6r(pc, reg3_ovr6)); 4594 } /* (st_entry_num == 3) */ 4595 return PHYMOD_E_NONE; 4596 } 4597 #endif 4598 4599 #ifdef _DV_TB_ 4600 /** 4601 @brief Read the 16 bit rev. id value etc. 4602 @param pc handle to current TSCE context (#PHYMOD_ST) 4603 @returns The value PHYMOD_E_NONE upon successful completion 4604 @details Per Port PCS Init 4605 */ 4606 int _qmod_configure_sc_speed_configuration(PHYMOD_ST* pc) 4607 { 4608 int data =0; 4609 int mask =0; 4610 int st_entry =0; 4611 int speed_entry = 0; 4612 PHYMOD_ST pc_st_tmp; 4613 PHYMOD_ST* pc_st; 4614 4615 if(pc->sc_mode == QMOD_SC_MODE_HT_WITH_BASIC_OVERRIDE){ 4616 /* Configure the ffec_eb regsiter */ 4617 data |= (1 << 10); 4618 mask |= 0x0400; 4619 4620 } 4621 else if(pc->sc_mode == QMOD_SC_MODE_ST) { 4622 st_entry = pc->per_lane_control & 0xff; 4623 speed_entry = (pc->per_lane_control & 0xff00) >> 8; 4624 4625 /* 4626 A pc_st_tmp is created so the overriden expected values passed from SV are not 4627 loaded in ST, and the ST has the same HT values 4628 */ 4629 init_qmod_st(&pc_st_tmp); 4630 pc_st_tmp.spd_intf = pc->spd_intf; 4631 pc_st_tmp.prt_ad = pc->prt_ad; 4632 pc_st_tmp.unit = pc->unit; 4633 pc_st_tmp.port_type = pc->port_type; 4634 pc_st_tmp.this_lane = pc->this_lane; 4635 pc_st_tmp.sc_mode = pc->sc_mode; 4636 pc_st = &pc_st_tmp; 4637 qmod_sc_lkup_table(pc_st); 4638 /*configure the ST regsiters */ 4639 _configure_st_entry(st_entry, speed_entry, pc_st); 4640 4641 } 4642 return PHYMOD_E_NONE; 4643 } 4644 #endif 4645 4646 #ifdef _DV_TB_ 4647 /** 4648 @brief Read the 16 bit rev. id value etc. 4649 @param pc handle to current TSCE context (#PHYMOD_ST) 4650 @returns The value PHYMOD_E_NONE upon successful completion 4651 @details Per Port PCS Init 4652 */ 4653 int _qmod_init_pcs_an(PHYMOD_ST* pc) 4654 { 4655 UC_COMMAND4r_t reg_com4; 4656 UC_COMMANDr_t reg_com; 4657 4658 UC_COMMAND4r_CLR(reg_com4); 4659 UC_COMMANDr_CLR(reg_com); 4660 4661 if(pc->uc_active){ 4662 UC_COMMAND4r_MICRO_SYSTEM_CLK_ENf_SET(reg_com4,1); 4663 UC_COMMAND4r_MICRO_SYSTEM_RESET_Nf_SET(reg_com4,1); 4664 PHYMOD_IF_ERR_RETURN(MODIFY_UC_COMMAND4r(pc, reg_com4)); 4665 4666 UC_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(reg_com,1); 4667 PHYMOD_IF_ERR_RETURN(MODIFY_UC_COMMANDr(pc, reg_com)); 4668 } 4669 qmod_set_an_port_mode(pc); 4670 pc->port_type=QMOD_MULTI_PORT; 4671 qmod_autoneg_set(pc); 4672 4673 qmod_autoneg_control(pc); 4674 4675 return PHYMOD_E_NONE; 4676 } 4677 #endif /* _DV_TB_ */ 4678 #ifdef _SDK_QMOD_TEMP_ 4679 4680 int _qmod_init_pcs_an(PHYMOD_ST* pc) 4681 { 4682 return PHYMOD_E_NONE; 4683 } 4684 #endif /* _SDK_QMOD_TEMP_ */ 4685 4686 /** 4687 @brief Read the 16 bit rev. id value etc. 4688 @param pc handle to current TSCE context (#PHYMOD_ST) 4689 @returns The value PHYMOD_E_NONE upon successful completion 4690 @details Per Port PCS Init 4691 */ 4692 4693 int qmod_trigger_speed_change(PHYMOD_ST* pc) 4694 { 4695 SC_X4_CTLr_t reg; 4696 4697 QMOD_DBG_IN_FUNC_INFO(pc); 4698 #ifdef _DV_TB_ 4699 pc->adjust_port_mode = 1; 4700 #endif /* _DV_TB_ */ 4701 #ifdef _SDK_QMOD_ 4702 4703 #endif 4704 4705 /* write 0 to the speed change */ 4706 SC_X4_CTLr_CLR(reg); 4707 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc, ®)); 4708 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 0); 4709 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg)); 4710 4711 /* write 1 to the speed change. No need to read again before write*/ 4712 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg, 1); 4713 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg)); 4714 4715 #ifdef _DV_TB_ 4716 pc->adjust_port_mode = 0; 4717 #endif /* _DV_TB_ */ 4718 #ifdef _SDK_QMOD_ 4719 4720 #endif 4721 4722 return PHYMOD_E_NONE; 4723 } 4724 4725 #ifdef _DV_TB_ 4726 /** 4727 @brief Read the 16 bit rev. id value etc. 4728 @param pc handle to current TSCE context (#PHYMOD_ST) 4729 @returns The value PHYMOD_E_NONE upon successful completion 4730 @details Per Port PCS Init 4731 */ 4732 int _read_and_compare_final_status(PHYMOD_ST* pc) 4733 { 4734 uint16_t fail; 4735 int actual_speed; 4736 PHYMOD_ST sc_final_stats_actual; 4737 PHYMOD_ST* sc_final_stats_actual_tmp; 4738 4739 SC_X4_FI_SP0_RSLVD_SPDr_t reg_resolved_sp0_spd; 4740 SC_X4_FI_SP0_RSLVD0r_t reg_resolved_sp0_0; 4741 SC_X4_FI_SP0_RSLVD1r_t reg_resolved_sp0_1; 4742 SC_X4_FI_SP0_RSLVD2r_t reg_resolved_sp0_2; 4743 SC_X4_FI_SP0_RSLVD3r_t reg_resolved_sp0_3; 4744 SC_X4_FI_SP0_RSLVD4r_t reg_resolved_sp0_4; 4745 SC_X4_FI_SP0_RSLVD5r_t reg_resolved_sp0_5; 4746 SC_X4_FI_SP0_RSLVD6r_t reg_resolved_sp0_6; 4747 4748 SC_X4_FI_SP1_RSLVD_SPDr_t reg_resolved_sp1_spd; 4749 SC_X4_FI_SP1_RSLVD0r_t reg_resolved_sp1_0; 4750 SC_X4_FI_SP1_RSLVD1r_t reg_resolved_sp1_1; 4751 SC_X4_FI_SP1_RSLVD2r_t reg_resolved_sp1_2; 4752 SC_X4_FI_SP1_RSLVD3r_t reg_resolved_sp1_3; 4753 SC_X4_FI_SP1_RSLVD4r_t reg_resolved_sp1_4; 4754 SC_X4_FI_SP1_RSLVD5r_t reg_resolved_sp1_5; 4755 SC_X4_FI_SP1_RSLVD6r_t reg_resolved_sp1_6; 4756 4757 SC_X4_FI_SP2_RSLVD_SPDr_t reg_resolved_sp2_spd; 4758 SC_X4_FI_SP2_RSLVD0r_t reg_resolved_sp2_0; 4759 SC_X4_FI_SP2_RSLVD1r_t reg_resolved_sp2_1; 4760 SC_X4_FI_SP2_RSLVD2r_t reg_resolved_sp2_2; 4761 SC_X4_FI_SP2_RSLVD3r_t reg_resolved_sp2_3; 4762 SC_X4_FI_SP2_RSLVD4r_t reg_resolved_sp2_4; 4763 SC_X4_FI_SP2_RSLVD5r_t reg_resolved_sp2_5; 4764 SC_X4_FI_SP2_RSLVD6r_t reg_resolved_sp2_6; 4765 4766 SC_X4_FI_SP3_RSLVD_SPDr_t reg_resolved_sp3_spd; 4767 SC_X4_FI_SP3_RSLVD0r_t reg_resolved_sp3_0; 4768 SC_X4_FI_SP3_RSLVD1r_t reg_resolved_sp3_1; 4769 SC_X4_FI_SP3_RSLVD2r_t reg_resolved_sp3_2; 4770 SC_X4_FI_SP3_RSLVD3r_t reg_resolved_sp3_3; 4771 SC_X4_FI_SP3_RSLVD4r_t reg_resolved_sp3_4; 4772 SC_X4_FI_SP3_RSLVD5r_t reg_resolved_sp3_5; 4773 SC_X4_FI_SP3_RSLVD6r_t reg_resolved_sp3_6; 4774 4775 if(pc->sub_port == 0){ 4776 SC_X4_FI_SP0_RSLVD_SPDr_CLR(reg_resolved_sp0_spd); 4777 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD_SPDr(pc, ®_resolved_sp0_spd)); 4778 actual_speed = SC_X4_FI_SP0_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp0_spd); 4779 sc_final_stats_actual.speed = actual_speed; 4780 4781 SC_X4_FI_SP0_RSLVD0r_CLR(reg_resolved_sp0_0); 4782 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD0r(pc, ®_resolved_sp0_0)); 4783 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP0_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp0_0); 4784 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP0_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp0_0); 4785 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP0_RSLVD0r_OS_MODEf_GET(reg_resolved_sp0_0); 4786 4787 SC_X4_FI_SP0_RSLVD1r_CLR(reg_resolved_sp0_1); 4788 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD1r(pc, ®_resolved_sp0_1)); 4789 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP0_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp0_1); 4790 sc_final_stats_actual.sgmii = SC_X4_FI_SP0_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp0_1); 4791 4792 SC_X4_FI_SP0_RSLVD2r_CLR(reg_resolved_sp0_2); 4793 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD2r(pc, ®_resolved_sp0_2)); 4794 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP0_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp0_2); 4795 4796 SC_X4_FI_SP0_RSLVD3r_CLR(reg_resolved_sp0_3); 4797 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD3r(pc, ®_resolved_sp0_3)); 4798 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP0_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp0_3); 4799 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP0_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp0_3); 4800 4801 SC_X4_FI_SP0_RSLVD4r_CLR(reg_resolved_sp0_4); 4802 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD4r(pc, ®_resolved_sp0_4)); 4803 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP0_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp0_4); 4804 4805 SC_X4_FI_SP0_RSLVD5r_CLR(reg_resolved_sp0_5); 4806 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD5r(pc, ®_resolved_sp0_5)); 4807 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP0_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp0_5); 4808 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP0_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp0_5); 4809 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP0_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp0_5); 4810 4811 SC_X4_FI_SP0_RSLVD6r_CLR(reg_resolved_sp0_6); 4812 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP0_RSLVD6r(pc, ®_resolved_sp0_6)); 4813 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP0_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp0_6); 4814 } 4815 4816 if(pc->sub_port == 1){ 4817 SC_X4_FI_SP1_RSLVD_SPDr_CLR(reg_resolved_sp1_spd); 4818 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD_SPDr(pc, ®_resolved_sp1_spd)); 4819 actual_speed = SC_X4_FI_SP1_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp1_spd); 4820 sc_final_stats_actual.speed = actual_speed; 4821 4822 SC_X4_FI_SP1_RSLVD0r_CLR(reg_resolved_sp1_0); 4823 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD0r(pc, ®_resolved_sp1_0)); 4824 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP1_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp1_0); 4825 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP1_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp1_0); 4826 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP1_RSLVD0r_OS_MODEf_GET(reg_resolved_sp1_0); 4827 4828 SC_X4_FI_SP1_RSLVD1r_CLR(reg_resolved_sp1_1); 4829 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD1r(pc, ®_resolved_sp1_1)); 4830 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP1_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp1_1); 4831 sc_final_stats_actual.sgmii = SC_X4_FI_SP1_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp1_1); 4832 4833 SC_X4_FI_SP1_RSLVD2r_CLR(reg_resolved_sp1_2); 4834 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD2r(pc, ®_resolved_sp1_2)); 4835 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP1_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp1_2); 4836 4837 SC_X4_FI_SP1_RSLVD3r_CLR(reg_resolved_sp1_3); 4838 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD3r(pc, ®_resolved_sp1_3)); 4839 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP1_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp1_3); 4840 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP1_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp1_3); 4841 4842 SC_X4_FI_SP1_RSLVD4r_CLR(reg_resolved_sp1_4); 4843 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD4r(pc, ®_resolved_sp1_4)); 4844 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP1_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp1_4); 4845 4846 SC_X4_FI_SP1_RSLVD5r_CLR(reg_resolved_sp1_5); 4847 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD5r(pc, ®_resolved_sp1_5)); 4848 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP1_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp1_5); 4849 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP1_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp1_5); 4850 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP1_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp1_5); 4851 4852 SC_X4_FI_SP1_RSLVD6r_CLR(reg_resolved_sp1_6); 4853 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP1_RSLVD6r(pc, ®_resolved_sp1_6)); 4854 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP1_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp1_6); 4855 } 4856 4857 if(pc->sub_port == 2){ 4858 SC_X4_FI_SP2_RSLVD_SPDr_CLR(reg_resolved_sp2_spd); 4859 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD_SPDr(pc, ®_resolved_sp2_spd)); 4860 actual_speed = SC_X4_FI_SP2_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp2_spd); 4861 sc_final_stats_actual.speed = actual_speed; 4862 4863 SC_X4_FI_SP2_RSLVD0r_CLR(reg_resolved_sp2_0); 4864 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD0r(pc, ®_resolved_sp2_0)); 4865 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP2_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp2_0); 4866 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP2_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp2_0); 4867 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP2_RSLVD0r_OS_MODEf_GET(reg_resolved_sp2_0); 4868 4869 SC_X4_FI_SP2_RSLVD1r_CLR(reg_resolved_sp2_1); 4870 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD1r(pc, ®_resolved_sp2_1)); 4871 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP2_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp2_1); 4872 sc_final_stats_actual.sgmii = SC_X4_FI_SP2_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp2_1); 4873 4874 SC_X4_FI_SP2_RSLVD2r_CLR(reg_resolved_sp2_2); 4875 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD2r(pc, ®_resolved_sp2_2)); 4876 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP2_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp2_2); 4877 4878 SC_X4_FI_SP2_RSLVD3r_CLR(reg_resolved_sp2_3); 4879 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD3r(pc, ®_resolved_sp2_3)); 4880 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP2_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp2_3); 4881 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP2_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp2_3); 4882 4883 SC_X4_FI_SP2_RSLVD4r_CLR(reg_resolved_sp2_4); 4884 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD4r(pc, ®_resolved_sp2_4)); 4885 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP2_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp2_4); 4886 4887 SC_X4_FI_SP2_RSLVD5r_CLR(reg_resolved_sp2_5); 4888 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD5r(pc, ®_resolved_sp2_5)); 4889 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP2_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp2_5); 4890 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP2_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp2_5); 4891 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP2_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp2_5); 4892 4893 SC_X4_FI_SP2_RSLVD6r_CLR(reg_resolved_sp2_6); 4894 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP2_RSLVD6r(pc, ®_resolved_sp2_6)); 4895 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP2_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp2_6); 4896 } 4897 4898 if(pc->sub_port == 3){ 4899 SC_X4_FI_SP3_RSLVD_SPDr_CLR(reg_resolved_sp3_spd); 4900 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD_SPDr(pc, ®_resolved_sp3_spd)); 4901 actual_speed = SC_X4_FI_SP3_RSLVD_SPDr_SPEEDf_GET(reg_resolved_sp3_spd); 4902 sc_final_stats_actual.speed = actual_speed; 4903 4904 SC_X4_FI_SP3_RSLVD0r_CLR(reg_resolved_sp3_0); 4905 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD0r(pc, ®_resolved_sp3_0)); 4906 sc_final_stats_actual.qsgmii_en = SC_X4_FI_SP3_RSLVD0r_QSGMII_ENf_GET(reg_resolved_sp3_0); 4907 sc_final_stats_actual.r_desc2_byte_deletion = SC_X4_FI_SP3_RSLVD0r_CL36BYTEDELETEMODEf_GET(reg_resolved_sp3_0); 4908 sc_final_stats_actual.t_pma_os_mode = SC_X4_FI_SP3_RSLVD0r_OS_MODEf_GET(reg_resolved_sp3_0); 4909 4910 SC_X4_FI_SP3_RSLVD1r_CLR(reg_resolved_sp3_1); 4911 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD1r(pc, ®_resolved_sp3_1)); 4912 sc_final_stats_actual.clkcnt0 = SC_X4_FI_SP3_RSLVD1r_CLOCKCNT0f_GET(reg_resolved_sp3_1); 4913 sc_final_stats_actual.sgmii = SC_X4_FI_SP3_RSLVD1r_SGMII_SPD_SWITCHf_GET(reg_resolved_sp3_1); 4914 4915 SC_X4_FI_SP3_RSLVD2r_CLR(reg_resolved_sp3_2); 4916 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD2r(pc, ®_resolved_sp3_2)); 4917 sc_final_stats_actual.clkcnt1 = SC_X4_FI_SP3_RSLVD2r_CLOCKCNT1f_GET(reg_resolved_sp3_2); 4918 4919 SC_X4_FI_SP3_RSLVD3r_CLR(reg_resolved_sp3_3); 4920 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD3r(pc, ®_resolved_sp3_3)); 4921 sc_final_stats_actual.lpcnt1 = SC_X4_FI_SP3_RSLVD3r_LOOPCNT1f_GET(reg_resolved_sp3_3); 4922 sc_final_stats_actual.lpcnt0 = SC_X4_FI_SP3_RSLVD3r_LOOPCNT0f_GET(reg_resolved_sp3_3); 4923 4924 SC_X4_FI_SP3_RSLVD4r_CLR(reg_resolved_sp3_4); 4925 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD4r(pc, ®_resolved_sp3_4)); 4926 sc_final_stats_actual.mac_cgc = SC_X4_FI_SP3_RSLVD4r_MAC_CREDITGENCNTf_GET(reg_resolved_sp3_4); 4927 4928 SC_X4_FI_SP3_RSLVD5r_CLR(reg_resolved_sp3_5); 4929 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD5r(pc, ®_resolved_sp3_5)); 4930 sc_final_stats_actual.pcs_clkcnt = SC_X4_FI_SP3_RSLVD5r_PCS_CLOCKCNT0f_GET(reg_resolved_sp3_5); 4931 sc_final_stats_actual.pcs_crdten = SC_X4_FI_SP3_RSLVD5r_PCS_CREDITENABLEf_GET(reg_resolved_sp3_5); 4932 sc_final_stats_actual.pcs_repcnt = SC_X4_FI_SP3_RSLVD5r_REPLICATION_CNTf_GET(reg_resolved_sp3_5); 4933 4934 SC_X4_FI_SP3_RSLVD6r_CLR(reg_resolved_sp3_6); 4935 PHYMOD_IF_ERR_RETURN(READ_SC_X4_FI_SP3_RSLVD6r(pc, ®_resolved_sp3_6)); 4936 sc_final_stats_actual.pcs_cgc = SC_X4_FI_SP3_RSLVD6r_PCS_CREDITGENCNTf_GET(reg_resolved_sp3_6); 4937 } 4938 4939 /* Compare the actual and expected stats */ 4940 fail = 0; 4941 4942 if(pc->spd_intf == QMOD_SPD_4000){ 4943 if(pc->subp_speed == 2){ 4944 pc->clkcnt0 = 1000; 4945 pc->mac_cgc = 999; 4946 pc->sgmii = 1; 4947 pc->pcs_repcnt = 1; 4948 pc->pcs_crdten = 1; 4949 pc->r_desc2_byte_deletion = 1; 4950 } 4951 if(pc->subp_speed == 1){ 4952 pc->clkcnt0 = 100; 4953 pc->mac_cgc = 99; 4954 pc->sgmii = 1; 4955 pc->pcs_repcnt = 0; 4956 pc->pcs_crdten = 1; 4957 pc->r_desc2_byte_deletion = 0; 4958 } 4959 if(pc->subp_speed == 0){ 4960 pc->clkcnt0 = 10; 4961 pc->mac_cgc = 9; 4962 pc->pcs_clkcnt = 0; 4963 pc->pcs_cgc = 0; 4964 } 4965 } 4966 4967 if(pc->sc_mode == QMOD_SC_MODE_ST) { 4968 if(actual_speed != (pc->per_lane_control >> 8)) 4969 fail = 1; 4970 } else if((pc->per_lane_control & 0xffff) == (0x004 | (QMOD_SPD_10000_XFI << 8))) { /* DV Verification Only */ 4971 if(actual_speed != digital_operationSpeeds_SPEED_10G_KR1) 4972 fail = 1; 4973 } else if((pc->per_lane_control & 0xffff) == (0x004 | (QMOD_SPD_10_SGMII << 8))) { /* DV Verification Only */ 4974 if(actual_speed != digital_operationSpeeds_SPEED_10M) 4975 fail = 1; 4976 } else if((pc->per_lane_control & 0xffff) == (0x004 | (QMOD_SPD_5000_XFI << 8))) { /* DV Verification Only */ 4977 if(actual_speed != digital_operationSpeeds_SPEED_5G_KR1) 4978 fail = 1; 4979 } else { 4980 if(actual_speed != pc->speed) 4981 fail = 1; 4982 } 4983 4984 if(sc_final_stats_actual.t_pma_os_mode != pc->t_pma_os_mode) 4985 fail = 1; 4986 4987 if(sc_final_stats_actual.qsgmii_en != pc->qsgmii_en) 4988 fail = 1; 4989 4990 if(sc_final_stats_actual.r_desc2_byte_deletion != pc->r_desc2_byte_deletion) 4991 fail = 1; 4992 4993 /*if(sc_final_stats_actual.cl36_en != pc->cl36_en) 4994 fail = 1;*/ 4995 4996 if(sc_final_stats_actual.sgmii != pc->sgmii) 4997 fail = 1; 4998 if(sc_final_stats_actual.clkcnt0 != pc->clkcnt0) 4999 fail = 1; 5000 if(sc_final_stats_actual.clkcnt1 != pc->clkcnt1) 5001 fail = 1; 5002 if(sc_final_stats_actual.lpcnt0 != pc->lpcnt0) 5003 fail = 1; 5004 if(sc_final_stats_actual.lpcnt1 != pc->lpcnt1) 5005 fail = 1; 5006 if(sc_final_stats_actual.mac_cgc != pc->mac_cgc) 5007 fail = 1; 5008 if(sc_final_stats_actual.pcs_repcnt != pc->pcs_repcnt) 5009 fail = 1; 5010 if(sc_final_stats_actual.pcs_crdten != pc->pcs_crdten) 5011 fail = 1; 5012 if(sc_final_stats_actual.pcs_clkcnt != pc->pcs_clkcnt) 5013 fail = 1; 5014 if(sc_final_stats_actual.pcs_cgc != pc->pcs_cgc) 5015 fail = 1; 5016 5017 pc->accData = fail; 5018 if(fail == 1) { 5019 sc_final_stats_actual_tmp = &sc_final_stats_actual; 5020 qmod_print_qmod_sc_lkup_table(sc_final_stats_actual_tmp); 5021 qmod_print_qmod_sc_lkup_table(pc); 5022 return PHYMOD_E_FAIL; 5023 } 5024 return PHYMOD_E_NONE; 5025 5026 } 5027 #endif 5028 5029 #ifdef _DV_TB_ 5030 /** 5031 @brief Read the 16 bit rev. id value etc. 5032 @param pc handle to current TSCE context (#PHYMOD_ST) 5033 @returns The value PHYMOD_E_NONE upon successful completion 5034 @details Per Port PCS Init for forced speeds 5035 5036 */ 5037 int _qmod_init_pcs_fs(PHYMOD_ST* pc) 5038 { 5039 uint16_t data; 5040 SC_X4_CTLr_t reg_swmode; 5041 5042 _qmod_get_sc_speed_configuration(pc); 5043 _qmod_configure_sc_speed_configuration(pc); 5044 5045 /* Set speed */ 5046 if(pc->sc_mode == QMOD_SC_MODE_ST) 5047 data = (pc->per_lane_control & 0xff00) >> 8; 5048 else if((pc->per_lane_control & 0xffff) == (0x004 | (QMOD_SPD_10_SGMII << 8))) /* DV Verification Only */ 5049 data = digital_operationSpeeds_SPEED_10M; 5050 else if((pc->per_lane_control & 0xffff) == (0x004 | (QMOD_SPD_5000_XFI << 8))) /* DV Verification Only */ 5051 data = digital_operationSpeeds_SPEED_5G_KR1; 5052 else 5053 data = pc->speed; 5054 5055 SC_X4_CTLr_CLR(reg_swmode); 5056 SC_X4_CTLr_SW_SPEEDf_SET(reg_swmode, data); 5057 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc, reg_swmode)); 5058 5059 qmod_trigger_speed_change(pc); 5060 _qmod_wait_sc_stats_set(pc); 5061 return PHYMOD_E_NONE; 5062 } 5063 #endif 5064 5065 #ifdef _DV_TB_ 5066 /** 5067 @brief Checks to ensure SC has programmed the PCS as expected 5068 @param pc handle to current TSCE context (#PHYMOD_ST) 5069 @returns The value PHYMOD_E_NONE upon successful completion. 5070 @details Called to Configure tsc12 for 100G+ speeds 5071 5072 */ 5073 5074 int qmod_check_sc_stats(PHYMOD_ST* pc) /* CHECK_SC_STATS */ 5075 { 5076 uint16_t data ; 5077 5078 QMOD_DBG_IN_FUNC_INFO(pc); 5079 data = _read_and_compare_final_status(pc); 5080 5081 return data; 5082 } 5083 #endif /* _DV_TB_ */ 5084 5085 #ifdef _DV_TB_ 5086 /** 5087 @brief 5088 @param 5089 @returns The value PHYMOD_E_NONE upon successful completion. 5090 @details 5091 5092 */ 5093 5094 int qmod_disable_set(PHYMOD_ST* pc) /* CHECK_SC_STATS */ 5095 { 5096 SC_X4_CTLr_t reg_sc_ctrl; 5097 5098 QMOD_DBG_IN_FUNC_INFO(pc); 5099 SC_X4_CTLr_CLR(reg_sc_ctrl); 5100 5101 /* write 0 to the speed change */ 5102 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 5103 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 5104 5105 return PHYMOD_E_NONE; 5106 } 5107 #endif /* _DV_TB_ */ 5108 5109 /** 5110 @brief Get info on Disable status of the Port 5111 @param pc handle to current TSCE context (#PHYMOD_ST) 5112 @returns The value PHYMOD_E_NONE upon successful completion 5113 @details Disables the port by writing 0 to the speed config logic in PCS. 5114 This makes the PCS to bring down the PCS blocks and also apply lane datapath 5115 reset to the PMD. There is no control input to this function since it only does 5116 one thing. 5117 5118 */ 5119 int qmod_disable_set(PHYMOD_ST* pc) 5120 { 5121 SC_X4_CTLr_t reg_sc_ctrl; 5122 5123 QMOD_DBG_IN_FUNC_INFO(pc); 5124 SC_X4_CTLr_CLR(reg_sc_ctrl); 5125 5126 /* write 0 to the speed change */ 5127 SC_X4_CTLr_SW_SPEED_CHANGEf_SET(reg_sc_ctrl, 0); 5128 PHYMOD_IF_ERR_RETURN(MODIFY_SC_X4_CTLr(pc,reg_sc_ctrl)); 5129 5130 return PHYMOD_E_NONE; 5131 } 5132 5133 /** 5134 @brief Get the plldiv from lookup table 5135 @param pc handle to current TSCE context (#PHYMOD_ST) 5136 @param spd_intf speed as specified by enum #qmod_spd_intfc_type 5137 @param plldiv Receives the pll divider value 5138 @param speed_vec Receives the speed id. 5139 @returns The value PHYMOD_E_NONE upon successful completion 5140 @details Get the plldiv from lookup table 5141 */ 5142 int qmod_plldiv_lkup_get(PHYMOD_ST* pc, qmod_spd_intfc_type spd_intf, uint32_t *plldiv, uint16_t *speed_vec) 5143 { 5144 int speed_id; 5145 5146 qmod_get_mapped_speed(spd_intf, &speed_id); 5147 *plldiv = qmod_sc_pmd_entry[speed_id].pll_mode; 5148 *speed_vec = speed_id ; 5149 5150 return PHYMOD_E_NONE; 5151 } 5152 5153 5154 /** 5155 @brief get the rx lane reset staus for any lane 5156 @param pc handle to current TSCE context (#PHYMOD_ST) 5157 @param get the status as *value 5158 @returns The value PHYMOD_E_NONE upon successful completion. 5159 5160 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 5161 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 5162 read back RSTB_LANE. 5163 */ 5164 5165 int qmod_rx_lane_control_get(PHYMOD_ST* pc, int *value) /* RX_LANE_CONTROL */ 5166 { 5167 return PHYMOD_E_NONE; 5168 } 5169 5170 /** 5171 @brief rx lane reset and enable of any particular lane 5172 @param pc handle to current TSCE context (#PHYMOD_ST) 5173 @param enable to reset the lane. 5174 @returns The value PHYMOD_E_NONE upon successful completion. 5175 5176 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 5177 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 5178 read back RSTB_LANE. 5179 5180 */ 5181 int qmod_rx_lane_control_set(PHYMOD_ST* pc, int enable) /* RX_LANE_CONTROL */ 5182 { 5183 PMA_CTLr_t reg_pma_ctrl; 5184 MAIN_LN_SWPr_t reg; 5185 unsigned int pcs_map; 5186 int i, logic_lane=0; 5187 int physical_lane=0; 5188 phymod_access_t pa_copy; 5189 5190 QMOD_DBG_IN_FUNC_INFO(pc); 5191 PMA_CTLr_CLR(reg_pma_ctrl); 5192 MAIN_LN_SWPr_CLR(reg); 5193 5194 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5195 PHYMOD_IF_ERR_RETURN 5196 (READ_MAIN_LN_SWPr(pc, ®)) ; 5197 5198 pcs_map = MAIN_LN_SWPr_GET(reg) & 0xff; 5199 /*If lane is swapped, re-map the lane mask*/ 5200 if (pcs_map != 0xe4) { 5201 for (i = 0; i < QMOD_NOF_LANES_IN_CORE; i++) { 5202 if(pc->lane_mask & (1 << i)) { 5203 logic_lane = i; 5204 break; 5205 } 5206 } 5207 for (i = 0; i < QMOD_NOF_LANES_IN_CORE; i++) { 5208 physical_lane = (pcs_map >> (i * 2)) & 0x3; 5209 if (physical_lane == logic_lane) { 5210 pa_copy.lane_mask = 1 << i; 5211 break; 5212 } 5213 } 5214 } 5215 if (enable) { 5216 PMA_CTLr_RSTB_LANEf_SET(reg_pma_ctrl, 1); 5217 PHYMOD_IF_ERR_RETURN (MODIFY_PMA_CTLr(&pa_copy, reg_pma_ctrl)); 5218 } else { 5219 /* bit set to 0 for disabling RXP */ 5220 PMA_CTLr_RSTB_LANEf_SET( reg_pma_ctrl, 0); 5221 PHYMOD_IF_ERR_RETURN (MODIFY_PMA_CTLr(&pa_copy, reg_pma_ctrl)); 5222 } 5223 return PHYMOD_E_NONE; 5224 } 5225 5226 /*! 5227 @brief tx lane reset and enable of any particular lane 5228 @param pc handle to current TSCE context (#PHYMOD_ST) 5229 @param *reset returns the tx_reset configured. 5230 @param *enable returns the tx_enable configured. 5231 @returns The value PHYMOD_E_NONE upon successful completion. 5232 @details 5233 returns the configured tx lane reset and enable of any particular lane 5234 */ 5235 int qmod_tx_lane_control_get(PHYMOD_ST* pc, int *reset, int *enable) /* TX_LANE_CONTROL_GET */ 5236 { 5237 MISCr_t reg_misc_ctrl; 5238 5239 QMOD_DBG_IN_FUNC_INFO(pc); 5240 MISCr_CLR(reg_misc_ctrl); 5241 5242 PHYMOD_IF_ERR_RETURN (READ_MISCr(pc, ®_misc_ctrl)); 5243 *reset = MISCr_RSTB_TX_LANEf_GET(reg_misc_ctrl); 5244 *enable = MISCr_ENABLE_TX_LANEf_GET(reg_misc_ctrl); 5245 5246 return PHYMOD_E_NONE; 5247 } 5248 5249 5250 #ifdef _DV_TB_ 5251 int qmod_prbs_rx_enable_set(PHYMOD_ST* pc, int enable) 5252 { 5253 return PHYMOD_E_NONE; 5254 } 5255 #endif 5256 5257 /*! 5258 @brief Read the 16 bit rev. id value etc. 5259 @param pc handle to current TSCE context (#PHYMOD_ST) 5260 @param cntl input (see details) 5261 @param value handle to current TSCE context (#PHYMOD_ST) 5262 @returns The value PHYMOD_E_NONE upon successful completion 5263 @details Per Port PMD Override. 5264 Can be enhanced to also configure per core PMD Override 5265 Various bits are enabled as bit encoded by the cntl parameter 5266 \li 0x8000 ln_dp_h_rstb_oen 5267 \li 0x4000 tx_disable_oen 5268 \li 0x2000 rx_dme_en_oen 5269 \li 0x1000 osr_mode_oen 5270 \li 0x0800 lane_mode_oen 5271 \li 0x0400 rx_clk_vld_ovrd 5272 \li 0x0200 signal_detect_ovrd 5273 \li 0x0100 rx_lock_ovrd 5274 5275 */ 5276 int qmod_pmd_override_control(PHYMOD_ST* pc, int cntl, int value) /* PMD_OVERRIDE_CONTROL */ 5277 { 5278 return PHYMOD_E_NONE; 5279 } 5280 5281 /** 5282 @brief Set subport speed in qsgmii mode 5283 @param pc handle to current TSCE context (#PHYMOD_ST) 5284 @returns The value PHYMOD_E_NONE upon successful completion. 5285 @details Set subport speed in qsgmii mode 5286 5287 */ 5288 5289 int qmod_set_qport_spd(PHYMOD_ST* pc, int sub_port, qmod_spd_intfc_type spd_intf) 5290 { 5291 SC_X4_QSGMII_SPDr_t reg_qsgmii_spd; 5292 int speed_id = 0; 5293 5294 QMOD_DBG_IN_FUNC_INFO(pc); 5295 SC_X4_QSGMII_SPDr_CLR(reg_qsgmii_spd); 5296 5297 if ((spd_intf == QMOD_SPD_10_SGMII) || (spd_intf == QMOD_SPD_10_X1_SGMII)) speed_id = 2; 5298 if ((spd_intf == QMOD_SPD_100_SGMII) || (spd_intf == QMOD_SPD_100_X1_SGMII)) speed_id = 1; 5299 if ((spd_intf == QMOD_SPD_1000_SGMII) || (spd_intf == QMOD_SPD_1000_X1_SGMII)) speed_id = 0; 5300 5301 switch(sub_port) { 5302 case 0: SC_X4_QSGMII_SPDr_SPEED_SP0f_SET(reg_qsgmii_spd, speed_id); break ; 5303 case 1: SC_X4_QSGMII_SPDr_SPEED_SP1f_SET(reg_qsgmii_spd, speed_id); break ; 5304 case 2: SC_X4_QSGMII_SPDr_SPEED_SP2f_SET(reg_qsgmii_spd, speed_id); break ; 5305 case 3: SC_X4_QSGMII_SPDr_SPEED_SP3f_SET(reg_qsgmii_spd, speed_id); break ; 5306 default: break ; 5307 } 5308 PHYMOD_IF_ERR_RETURN (MODIFY_SC_X4_QSGMII_SPDr( pc, reg_qsgmii_spd)); 5309 5310 5311 return PHYMOD_E_NONE; 5312 } 5313 5314 int qmod_get_qport_spd(PHYMOD_ST* pc, int sub_port, qmod_spd_intfc_type *spd_intf) 5315 { 5316 SC_X4_QSGMII_SPDr_t reg_qsgmii_spd; 5317 int speed_id = 0; 5318 5319 QMOD_DBG_IN_FUNC_INFO(pc); 5320 SC_X4_QSGMII_SPDr_CLR(reg_qsgmii_spd); 5321 PHYMOD_IF_ERR_RETURN (READ_SC_X4_QSGMII_SPDr(pc, ®_qsgmii_spd)); 5322 5323 switch (sub_port) { 5324 case 0: 5325 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP0f_GET(reg_qsgmii_spd); 5326 break ; 5327 case 1: 5328 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP1f_GET(reg_qsgmii_spd); 5329 break ; 5330 case 2: 5331 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP2f_GET(reg_qsgmii_spd); 5332 break ; 5333 case 3: 5334 speed_id = SC_X4_QSGMII_SPDr_SPEED_SP3f_GET(reg_qsgmii_spd); 5335 break ; 5336 default: 5337 break ; 5338 } 5339 5340 switch (speed_id) { 5341 case 2: 5342 *spd_intf = QMOD_SPD_10_SGMII; 5343 break; 5344 case 1: 5345 *spd_intf = QMOD_SPD_100_SGMII; 5346 break; 5347 default: 5348 *spd_intf = QMOD_SPD_1000_SGMII; 5349 break; 5350 } 5351 5352 return PHYMOD_E_NONE; 5353 } 5354 5355 /* 5356 @brief use spare registers to get the state info for shared QSGMII ports. 5357 @param pc handle to current TSCE context (#PHYMOD_ST) 5358 @param qmod_state_type has MOD_PORT_STATE_CONFIGED(1), 5359 QMOD_PORT_STATE_TX_SQUELCH(2), QMOD_PORT_STATE_RX_SQUELCH(3). 5360 @param sub_port and value to choose which bit to set. 5361 @param all_sub_port_val returns all shared ports information. 5362 @returns The value PHYMOD_E_NONE upon successful completion. 5363 5364 These set/get functions will set and get the state info for shared QSGMII ports 5365 that might affect how each lane will react to BCM APIs. 5366 */ 5367 int qmod_port_state_set(PHYMOD_ST* pc, int qmod_state_type, int sub_port, int val) 5368 { 5369 SPARE0r_t reg_spare0 ; 5370 SPARE1r_t reg_spare1 ; 5371 int all_sub_port_val = 0; 5372 5373 QMOD_DBG_IN_FUNC_INFO(pc); 5374 SPARE0r_CLR(reg_spare0); 5375 SPARE1r_CLR(reg_spare1); 5376 switch (qmod_state_type) { 5377 case QMOD_PORT_STATE_CONFIGED: 5378 PHYMOD_IF_ERR_RETURN(READ_SPARE0r(pc, ®_spare0)); 5379 all_sub_port_val = SPARE0r_SPARE0f_GET(reg_spare0) & 0xf; 5380 if (val) { 5381 all_sub_port_val |= 1<< sub_port; 5382 } else { 5383 all_sub_port_val = all_sub_port_val & ~(1 << sub_port); 5384 } 5385 SPARE0r_SPARE0f_SET(reg_spare0, all_sub_port_val); 5386 PHYMOD_IF_ERR_RETURN(WRITE_SPARE0r(pc, reg_spare0)); 5387 break; 5388 case QMOD_PORT_STATE_TX_SQUELCH: 5389 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 5390 all_sub_port_val = SPARE1r_SPARE1f_GET(reg_spare1); 5391 if (val) { 5392 all_sub_port_val |= 1<< sub_port; 5393 } else { 5394 all_sub_port_val = all_sub_port_val & ~(1 << sub_port); 5395 } 5396 SPARE1r_SPARE1f_SET(reg_spare1, all_sub_port_val); 5397 PHYMOD_IF_ERR_RETURN(WRITE_SPARE1r(pc, reg_spare1)); 5398 break; 5399 case QMOD_PORT_STATE_RX_SQUELCH: 5400 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 5401 all_sub_port_val = SPARE1r_SPARE1f_GET(reg_spare1); 5402 if (val) { 5403 all_sub_port_val |= 1<< (sub_port+4); 5404 } else { 5405 all_sub_port_val = all_sub_port_val & ~(1 << (sub_port+4)); 5406 } 5407 SPARE1r_SPARE1f_SET(reg_spare1, all_sub_port_val); 5408 PHYMOD_IF_ERR_RETURN(WRITE_SPARE1r(pc, reg_spare1)); 5409 break; 5410 default: 5411 return PHYMOD_E_PARAM; 5412 break; 5413 } 5414 return PHYMOD_E_NONE; 5415 } 5416 5417 int qmod_port_state_get(PHYMOD_ST* pc, int qmod_state_type, int *all_sub_port_val) 5418 { 5419 SPARE0r_t reg_spare0 ; 5420 SPARE1r_t reg_spare1 ; 5421 5422 QMOD_DBG_IN_FUNC_INFO(pc); 5423 SPARE0r_CLR(reg_spare0); 5424 SPARE1r_CLR(reg_spare1); 5425 switch (qmod_state_type) { 5426 case QMOD_PORT_STATE_CONFIGED: 5427 PHYMOD_IF_ERR_RETURN(READ_SPARE0r(pc, ®_spare0)); 5428 *all_sub_port_val = SPARE0r_SPARE0f_GET(reg_spare0) & 0xf; 5429 break; 5430 case QMOD_PORT_STATE_TX_SQUELCH: 5431 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 5432 *all_sub_port_val = SPARE1r_SPARE1f_GET(reg_spare1) & 0xf; 5433 break; 5434 case QMOD_PORT_STATE_RX_SQUELCH: 5435 PHYMOD_IF_ERR_RETURN(READ_SPARE1r(pc, ®_spare1)); 5436 *all_sub_port_val = (SPARE1r_SPARE1f_GET(reg_spare1) >> 4) & 0xf; 5437 break; 5438 default: 5439 return PHYMOD_E_PARAM; 5440 break; 5441 } 5442 return PHYMOD_E_NONE; 5443 } 5444 5445 #ifdef _DV_TB_ 5446 /** 5447 @brief Set qsgmii_en for tx and rx 5448 @param pc handle to current TSCE context (#PHYMOD_ST) 5449 @returns The value PHYMOD_E_NONE upon successful completion. 5450 @details Set subport speed in qsgmii mode 5451 5452 */ 5453 5454 int qmod_set_qsgmii_en(PHYMOD_ST* pc) 5455 { 5456 CL36TX_CTLr_t reg_cl36tx_ctl; 5457 CL36_RXr_t reg_cl36_rx; 5458 5459 QMOD_DBG_IN_FUNC_INFO(pc); 5460 CL36TX_CTLr_CLR(reg_cl36tx_ctl); 5461 CL36_RXr_CLR(reg_cl36_rx); 5462 5463 CL36TX_CTLr_QSGMII_ENf_SET(reg_cl36tx_ctl, pc->qsgmii_mode); 5464 CL36_RXr_QSGMII_ENf_SET(reg_cl36_rx, pc->qsgmii_mode); 5465 5466 PHYMOD_IF_ERR_RETURN (MODIFY_CL36TX_CTLr( pc, reg_cl36tx_ctl)); 5467 PHYMOD_IF_ERR_RETURN (MODIFY_CL36_RXr( pc, reg_cl36_rx)); 5468 5469 return PHYMOD_E_NONE; 5470 } 5471 #endif 5472 5473 int qmod_speedchange_get (PHYMOD_ST *pc, uint32_t* enable) 5474 { 5475 SC_X4_CTLr_t reg_sc_ctrl; 5476 5477 QMOD_DBG_IN_FUNC_INFO(pc); 5478 SC_X4_CTLr_CLR(reg_sc_ctrl); 5479 5480 PHYMOD_IF_ERR_RETURN(READ_SC_X4_CTLr(pc,®_sc_ctrl)); 5481 *enable = SC_X4_CTLr_SW_SPEED_CHANGEf_GET(reg_sc_ctrl); 5482 5483 return PHYMOD_E_NONE; 5484 } 5485 5486 int qmod_get_plldiv (PHYMOD_ST *pc, uint32_t *pll_div) 5487 { 5488 PLL_CAL_CTL7r_t reg_ctl7; 5489 READ_PLL_CAL_CTL7r(pc, ®_ctl7); 5490 *pll_div = PLL_CAL_CTL7r_PLL_MODEf_GET(reg_ctl7); 5491 5492 return PHYMOD_E_NONE; 5493 } 5494 int qmod_master_port_num_set ( PHYMOD_ST *pc, int port_num) 5495 { 5496 MAIN_SETUPr_t main_reg; 5497 5498 MAIN_SETUPr_CLR(main_reg); 5499 MAIN_SETUPr_MASTER_PORT_NUMf_SET(main_reg, port_num); 5500 MODIFY_MAIN_SETUPr(pc, main_reg); 5501 5502 return PHYMOD_E_NONE; 5503 } 5504 5505 int qmod_pcs_lane_swap_get (PHYMOD_ST *pc, uint32_t *tx_rx_swap) 5506 { 5507 unsigned int pcs_map; 5508 MAIN_LN_SWPr_t reg; 5509 QMOD_DBG_IN_FUNC_INFO(pc); 5510 5511 MAIN_LN_SWPr_CLR(reg); 5512 5513 PHYMOD_IF_ERR_RETURN 5514 (READ_MAIN_LN_SWPr(pc, ®)) ; 5515 5516 pcs_map = MAIN_LN_SWPr_GET(reg); 5517 5518 *tx_rx_swap = (((pcs_map >> 0) & 0x3) << 0) | 5519 (((pcs_map >> 2) & 0x3) << 4) | 5520 (((pcs_map >> 4) & 0x3) << 8) | 5521 (((pcs_map >> 6) & 0x3) << 12) ; 5522 5523 return PHYMOD_E_NONE ; 5524 } 5525 5526 int qmod_pll_reset_enable_set ( PHYMOD_ST *pc , int enable) 5527 { 5528 MAIN_SETUPr_t main_reg; 5529 5530 MAIN_SETUPr_CLR(main_reg); 5531 MAIN_SETUPr_PLL_RESET_ENf_SET(main_reg, enable); 5532 MODIFY_MAIN_SETUPr(pc, main_reg); 5533 return PHYMOD_E_NONE ; 5534 } 5535 5536 int qmod_pmd_lane_swap_tx_get ( PHYMOD_ST *pc, uint32_t *tx_lane_map) 5537 { 5538 uint16_t tx_lane_map_0, tx_lane_map_1, tx_lane_map_2, tx_lane_map_3; 5539 DIG_TX_LN_MAP_0_1_2r_t reg; 5540 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_t reg1; 5541 5542 QMOD_DBG_IN_FUNC_INFO(pc); 5543 DIG_TX_LN_MAP_0_1_2r_CLR(reg); 5544 DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_CLR(reg1); 5545 5546 PHYMOD_IF_ERR_RETURN 5547 (READ_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r(pc, ®1)); 5548 PHYMOD_IF_ERR_RETURN 5549 (READ_DIG_TX_LN_MAP_0_1_2r(pc, ®)); 5550 5551 5552 tx_lane_map_0 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_0f_GET(reg); 5553 tx_lane_map_1 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_1f_GET(reg); 5554 tx_lane_map_2 = DIG_TX_LN_MAP_0_1_2r_TX_LANE_MAP_2f_GET(reg); 5555 tx_lane_map_3 = DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_TX_LANE_MAP_3f_GET(reg1); 5556 5557 *tx_lane_map = ((tx_lane_map_0 & 0xf) << 0) 5558 | ((tx_lane_map_1 & 0xf) << 4) 5559 | ((tx_lane_map_2 & 0xf) << 8) 5560 | ((tx_lane_map_3 & 0xf) << 12); 5561 5562 return PHYMOD_E_NONE ; 5563 } 5564 5565 /*! 5566 @brief get port speed id configured 5567 @param pc handle to current TSCE context (#PHYMOD_ST) 5568 @param speed_id Receives the the resolved speed cfg as recorded in h/w 5569 @returns The value PHYMOD_E_NONE upon successful completion. 5570 @details get port speed configured 5571 */ 5572 int qmod_speed_id_get ( PHYMOD_ST *pc, int *speed_id, int subport) 5573 { 5574 int start_lane, num_lane; 5575 SC_X4_FI_SP0_RSLVD_SPDr_t sc_final_sp0_resolved_speed; 5576 SC_X4_FI_SP0_RSLVD0r_t sc_final_sp0_resolved_0; 5577 SC_X4_FI_SP1_RSLVD0r_t sc_final_sp1_resolved_0; 5578 SC_X4_FI_SP2_RSLVD0r_t sc_final_sp2_resolved_0; 5579 SC_X4_FI_SP3_RSLVD0r_t sc_final_sp3_resolved_0; 5580 5581 5582 int sp_spd_id; 5583 5584 PHYMOD_IF_ERR_RETURN 5585 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5586 5587 QMOD_DBG_IN_FUNC_INFO(pc); 5588 5589 SC_X4_FI_SP0_RSLVD_SPDr_CLR(sc_final_sp0_resolved_speed); 5590 5591 SC_X4_FI_SP0_RSLVD0r_CLR(sc_final_sp0_resolved_0); 5592 SC_X4_FI_SP1_RSLVD0r_CLR(sc_final_sp1_resolved_0); 5593 SC_X4_FI_SP2_RSLVD0r_CLR(sc_final_sp2_resolved_0); 5594 SC_X4_FI_SP3_RSLVD0r_CLR(sc_final_sp3_resolved_0); 5595 5596 5597 /* next check if we are in qsgmii mode */ 5598 if (!PHYMOD_ACC_F_QMODE_GET(pc)) { 5599 /* switch (start_lane) { 5600 case 1: READ_SC_X4_FI_SP1_RSLVD_SPDr(pc,&sc_final_sp1_resolved_speed); 5601 sp_spd_id = SC_X4_FI_SP1_RSLVD_SPDr_SPEEDf_GET(sc_final_sp1_resolved_speed); 5602 break ; 5603 case 2: READ_SC_X4_FI_SP2_RSLVD_SPDr(pc,&sc_final_sp2_resolved_speed); 5604 sp_spd_id = SC_X4_FI_SP2_RSLVD_SPDr_SPEEDf_GET(sc_final_sp2_resolved_speed); 5605 break ; 5606 case 3: READ_SC_X4_FI_SP3_RSLVD_SPDr(pc,&sc_final_sp3_resolved_speed); 5607 sp_spd_id = SC_X4_FI_SP3_RSLVD_SPDr_SPEEDf_GET(sc_final_sp3_resolved_speed); 5608 break ; 5609 default: */ 5610 READ_SC_X4_FI_SP0_RSLVD_SPDr(pc,&sc_final_sp0_resolved_speed); 5611 sp_spd_id = SC_X4_FI_SP0_RSLVD_SPDr_SPEEDf_GET(sc_final_sp0_resolved_speed); 5612 /* break ; */ 5613 } else { 5614 switch (subport) { 5615 case 1: READ_SC_X4_FI_SP1_RSLVD0r(pc,&sc_final_sp1_resolved_0); 5616 sp_spd_id = SC_X4_FI_SP1_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp1_resolved_0); 5617 break ; 5618 case 2: READ_SC_X4_FI_SP2_RSLVD0r(pc,&sc_final_sp2_resolved_0); 5619 sp_spd_id = SC_X4_FI_SP2_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp2_resolved_0); 5620 break ; 5621 case 3: READ_SC_X4_FI_SP3_RSLVD0r(pc,&sc_final_sp3_resolved_0); 5622 sp_spd_id = SC_X4_FI_SP3_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp3_resolved_0); 5623 break ; 5624 default: 5625 READ_SC_X4_FI_SP0_RSLVD0r(pc,&sc_final_sp0_resolved_0); 5626 sp_spd_id = SC_X4_FI_SP0_RSLVD0r_CL36BYTEDELETEMODEf_GET(sc_final_sp0_resolved_0); 5627 break ; 5628 } 5629 switch (sp_spd_id) { 5630 case 0: 5631 sp_spd_id = 0x2; 5632 break; 5633 case 1: 5634 sp_spd_id = 0x1; 5635 break; 5636 default: 5637 sp_spd_id = 0x3; 5638 break; 5639 } 5640 5641 } 5642 5643 *speed_id = sp_spd_id ; 5644 5645 return PHYMOD_E_NONE; 5646 } 5647 5648 /** 5649 @brief Gets the TX And RX Polarity 5650 @param pc handle to current TSCE context (#PHYMOD_ST) 5651 @param tx_polarity Receive Polarity for TX side 5652 @param rx_polarity Receive Polarity for RX side 5653 @returns The value PHYMOD_E_NONE upon successful completion. 5654 @details Gets the TX And RX Polarity 5655 */ 5656 int qmod_tx_rx_polarity_get ( PHYMOD_ST *pc, uint32_t* tx_polarity, uint32_t* rx_polarity) 5657 { 5658 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 5659 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 5660 5661 PHYMOD_IF_ERR_RETURN(READ_TLB_TX_TLB_TX_MISC_CFGr(pc, &tx_pol_inv)); 5662 *tx_polarity = TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv); 5663 5664 PHYMOD_IF_ERR_RETURN(READ_TLB_RX_TLB_RX_MISC_CFGr(pc, &rx_pol_inv)); 5665 *rx_polarity = TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv); 5666 5667 return PHYMOD_E_NONE; 5668 } 5669 5670 /** 5671 @brief Sets the TX And RX Polarity 5672 @param pc handle to current TSCE context (#PHYMOD_ST) 5673 @param tx_polarity Control Polarity for TX side 5674 @param rx_polarity Control Polarity for RX side 5675 @returns The value PHYMOD_E_NONE upon successful completion. 5676 @details Sets the TX And RX Polarity 5677 */ 5678 int qmod_tx_rx_polarity_set ( PHYMOD_ST *pc, uint32_t tx_polarity, uint32_t rx_polarity) 5679 { 5680 TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 5681 TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 5682 5683 TLB_TX_TLB_TX_MISC_CFGr_CLR(tx_pol_inv); 5684 TLB_RX_TLB_RX_MISC_CFGr_CLR(rx_pol_inv); 5685 5686 TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pol_inv, tx_polarity); 5687 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_TX_TLB_TX_MISC_CFGr(pc, tx_pol_inv)); 5688 5689 TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pol_inv, rx_polarity); 5690 PHYMOD_IF_ERR_RETURN(MODIFY_TLB_RX_TLB_RX_MISC_CFGr(pc, rx_pol_inv)); 5691 5692 return PHYMOD_E_NONE; 5693 } 5694 5695 /** 5696 @brief Set the port speed and enable the port 5697 @param pc handle to current QTCE context (#PHYMOD_ST) 5698 @param spd_intf the speed to set the port enum #qmod_set_spd_intf 5699 @returns The value PHYMOD_E_NONE upon successful completion 5700 @details Sets the port to the specified speed and triggers the port, and waits 5701 for the port to be configured 5702 */ 5703 int qmod_set_spd_intf(PHYMOD_ST *pc, qmod_spd_intfc_type spd_intf, int no_trig) 5704 { 5705 SC_X4_CTLr_t xgxs_x4_ctrl; 5706 phymod_access_t pa_copy; 5707 int speed_id = 0, start_lane = 0, num_lane = 0; 5708 5709 QMOD_DBG_IN_FUNC_INFO(pc); 5710 5711 /* need to figure out what's the starting lane */ 5712 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5713 PHYMOD_IF_ERR_RETURN 5714 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5715 pa_copy.lane_mask = 0x1 << start_lane; 5716 5717 PHYMOD_IF_ERR_RETURN (qmod_get_mapped_speed(spd_intf, &speed_id)); 5718 /* write the speed_id into the speed_change register */ 5719 SC_X4_CTLr_CLR(xgxs_x4_ctrl); 5720 SC_X4_CTLr_SW_SPEEDf_SET(xgxs_x4_ctrl, speed_id); 5721 MODIFY_SC_X4_CTLr(pc, xgxs_x4_ctrl); 5722 /*next call the speed_change routine */ 5723 if(no_trig) { 5724 5725 } else { 5726 PHYMOD_IF_ERR_RETURN (qmod_trigger_speed_change(&pa_copy)); 5727 /* removed check for the speed_change_done init*/ 5728 } 5729 return PHYMOD_E_NONE; 5730 } 5731 5732 5733 int qmod_pll_sequencer_control(PHYMOD_ST *pa, int enable) 5734 { 5735 return PHYMOD_E_NONE; 5736 } 5737 5738 /* #ifdef _SDK_QMOD_ */ 5739 int qmod_lane_info(PHYMOD_ST *pa, int *lane, int *sub_port) 5740 { 5741 int i = 0 ; uint32_t mask ; 5742 mask = pa->lane_mask ; 5743 *lane = 0 ; *sub_port=0 ; 5744 if(mask==0) return PHYMOD_E_INTERNAL ; 5745 while(1) { 5746 if(mask & 0xf) { 5747 switch(mask) { 5748 case 0x1: *sub_port=0 ; break ; 5749 case 0x2: *sub_port=1 ; break ; 5750 case 0x4: *sub_port=2 ; break ; 5751 case 0x8: *sub_port=3 ; break ; 5752 case 0xf: *sub_port=0 ; break ; 5753 default: 5754 return PHYMOD_E_INTERNAL ; break; 5755 } 5756 } 5757 mask = mask >> 4; 5758 if(mask) { 5759 i++ ; 5760 } else { 5761 break ; 5762 } 5763 } 5764 *lane = i ; 5765 if(!PHYMOD_ACC_F_QMODE_GET(pa)) { /* no qmode */ 5766 *lane = *sub_port; *sub_port=0; 5767 } 5768 return PHYMOD_E_NONE ; 5769 } 5770 /* #endif */ 5771 5772 /** 5773 @brief EEE Control Set 5774 @param pc handle to current QTCE context (#PHYMOD_ST) 5775 @param enable enable or disable EEE control 5776 @returns The value PHYMOD_E_NONE upon successful completion 5777 @details EEE Control 5778 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 5779 enable =0 : Convert LPI to idle. So MAC will not see it. 5780 5781 */ 5782 int qmod_eee_control_set(PHYMOD_ST* pc, uint32_t enable) 5783 { 5784 /* PCS_CTLr_t is for writing the RX reg; CL36TX_CTLr_t is for writing the TX reg */ 5785 PCS_CTLr_t reg_pcs_or_val; 5786 CL36TX_CTLr_t reg_cl36_or_val; 5787 5788 /* following variables are to find out the lane ID and the subport ID of the current logical port */ 5789 phymod_access_t pa_copy; 5790 int lane_id=0, sub_port=0; 5791 5792 QMOD_DBG_IN_FUNC_INFO(pc); 5793 5794 /* figure out what's the starting lane */ 5795 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5796 PHYMOD_IF_ERR_RETURN 5797 (qmod_lane_info(pc, &lane_id, &sub_port)); 5798 5799 pa_copy.lane_mask = 0x1 << lane_id; 5800 5801 PCS_CTLr_CLR(reg_pcs_or_val); 5802 CL36TX_CTLr_CLR(reg_cl36_or_val); 5803 5804 PCS_CTLr_LPI_ENABLEf_SET(reg_pcs_or_val, enable & 0x1); 5805 PHYMOD_IF_ERR_RETURN (MODIFY_PCS_CTLr(&pa_copy, reg_pcs_or_val)); 5806 5807 CL36TX_CTLr_CL36TX_LPI_ENf_SET(reg_cl36_or_val, enable & 0x1); 5808 PHYMOD_IF_ERR_RETURN (MODIFY_CL36TX_CTLr(&pa_copy,reg_cl36_or_val)); 5809 5810 return PHYMOD_E_NONE; 5811 } 5812 5813 /** 5814 @brief EEE Control Get 5815 @param pc handle to current QTCE context (#PHYMOD_ST) 5816 @param enable handle to pass back EEE control 5817 @returns The value PHYMOD_E_NONE upon successful completion 5818 @details EEE Control 5819 enable =1 : Allow LPI pass through. i.e. dont convert LPI. 5820 enable =0 : Convert LPI to idle. So MAC will not see it. 5821 5822 */ 5823 int qmod_eee_control_get(PHYMOD_ST* pc, uint32_t *enable) 5824 { 5825 /* PCS_CTLr_t is for reading the RX reg */ 5826 PCS_CTLr_t reg_pcs_or_val; 5827 5828 /* following variables are to find out the lane ID and the subport ID of the current logical port */ 5829 phymod_access_t pa_copy; 5830 int lane_id=0, sub_port=0; 5831 5832 QMOD_DBG_IN_FUNC_INFO(pc); 5833 5834 /* figure out what's the starting lane */ 5835 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5836 PHYMOD_IF_ERR_RETURN 5837 (qmod_lane_info(pc, &lane_id, &sub_port)); 5838 5839 pa_copy.lane_mask = 0x1 << lane_id; 5840 5841 PCS_CTLr_CLR(reg_pcs_or_val); 5842 PHYMOD_IF_ERR_RETURN (READ_PCS_CTLr(&pa_copy, ®_pcs_or_val)); 5843 *enable = PCS_CTLr_LPI_ENABLEf_GET(reg_pcs_or_val); 5844 5845 return PHYMOD_E_NONE; 5846 } 5847 int qmod_pmd_lane_override(PHYMOD_ST* pc, qmod_pmd_lane_override_t ovrd_type) 5848 { 5849 BCMI_QTC_XGXS_PMD_X4_OVRRr_t reg_pmd_ovr; 5850 5851 PMD_X4_OVRRr_CLR(reg_pmd_ovr); 5852 5853 switch (ovrd_type) { 5854 case QMOD_PMD_LANE_SIGNAL_DETECT_OVRD: 5855 PMD_X4_OVRRr_SIGNAL_DETECT_OVRDf_SET(reg_pmd_ovr, 1); 5856 break; 5857 case QMOD_PMD_LANE_RX_LOCK_OVRD: 5858 PMD_X4_OVRRr_RX_LOCK_OVRDf_SET(reg_pmd_ovr, 1); 5859 break; 5860 default: 5861 return PHYMOD_E_NONE ; 5862 break; 5863 } 5864 PHYMOD_IF_ERR_RETURN 5865 (MODIFY_PMD_X4_OVRRr(pc, reg_pmd_ovr)); 5866 5867 return PHYMOD_E_NONE ; 5868 } 5869 5870 STATIC 5871 int _qmod_rx_phy_lane_get(PHYMOD_ST *pc, int rx_logical_lane, int* rx_phy_lane) 5872 { 5873 MAIN_LN_SWPr_t reg_lane_swap; 5874 phymod_access_t pa_copy; 5875 5876 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 5877 5878 /*always use lane 0 copy since register is single copy */ 5879 pa_copy.lane_mask = 0x1; 5880 5881 PHYMOD_IF_ERR_RETURN 5882 (READ_MAIN_LN_SWPr(&pa_copy, ®_lane_swap)); 5883 5884 switch (rx_logical_lane) { 5885 case 0: 5886 *rx_phy_lane = MAIN_LN_SWPr_LOG0_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 5887 break; 5888 case 1: 5889 *rx_phy_lane = MAIN_LN_SWPr_LOG1_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 5890 break; 5891 case 2: 5892 *rx_phy_lane = MAIN_LN_SWPr_LOG2_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 5893 break; 5894 case 3: 5895 *rx_phy_lane = MAIN_LN_SWPr_LOG3_TO_PHY_LNSWAP_SELf_GET(reg_lane_swap); 5896 break; 5897 default: 5898 return PHYMOD_E_PARAM; 5899 } 5900 5901 return PHYMOD_E_NONE; 5902 } 5903 5904 int qmod_synce_mode_set(PHYMOD_ST *pc, int mode0, int mode1) 5905 { 5906 int start_lane = 0, num_lane = 0, phy_lane = 0; 5907 MAIN_SYNCE_CTLr_t reg_main_synce_ctl; 5908 5909 PHYMOD_IF_ERR_RETURN 5910 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5911 5912 PHYMOD_IF_ERR_RETURN 5913 (_qmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5914 5915 MAIN_SYNCE_CTLr_CLR(reg_main_synce_ctl); 5916 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_CTLr(pc, ®_main_synce_ctl)); 5917 5918 switch(phy_lane) { 5919 case 0: 5920 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN0f_SET(reg_main_synce_ctl, mode0); 5921 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN0f_SET(reg_main_synce_ctl, mode1); 5922 break; 5923 case 1: 5924 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN1f_SET(reg_main_synce_ctl, mode0); 5925 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN1f_SET(reg_main_synce_ctl, mode1); 5926 break; 5927 case 2: 5928 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN2f_SET(reg_main_synce_ctl, mode0); 5929 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN2f_SET(reg_main_synce_ctl, mode1); 5930 break; 5931 case 3: 5932 MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN3f_SET(reg_main_synce_ctl, mode0); 5933 MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN3f_SET(reg_main_synce_ctl, mode1); 5934 break; 5935 default: 5936 return PHYMOD_E_PARAM; 5937 } 5938 5939 PHYMOD_IF_ERR_RETURN(MODIFY_MAIN_SYNCE_CTLr(pc, reg_main_synce_ctl)); 5940 5941 return PHYMOD_E_NONE; 5942 } 5943 5944 int qmod_synce_clk_ctrl_set(PHYMOD_ST *pc, uint32_t val) 5945 { 5946 int start_lane = 0, num_lane = 0, phy_lane = 0; 5947 MAIN_SYNCE_DIVISOR0_PHY_LN0r_t reg_synce_divisor_lane0; 5948 MAIN_SYNCE_DIVISOR1_PHY_LN1r_t reg_synce_divisor_lane1; 5949 MAIN_SYNCE_DIVISOR2_PHY_LN2r_t reg_synce_divisor_lane2; 5950 MAIN_SYNCE_DIVISOR3_PHY_LN3r_t reg_synce_divisor_lane3; 5951 5952 PHYMOD_IF_ERR_RETURN 5953 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5954 5955 PHYMOD_IF_ERR_RETURN 5956 (_qmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5957 5958 switch(phy_lane) { 5959 case 0: 5960 MAIN_SYNCE_DIVISOR0_PHY_LN0r_CLR(reg_synce_divisor_lane0); 5961 MAIN_SYNCE_DIVISOR0_PHY_LN0r_SET(reg_synce_divisor_lane0, val); 5962 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR0_PHY_LN0r(pc, reg_synce_divisor_lane0)); 5963 break; 5964 case 1: 5965 MAIN_SYNCE_DIVISOR1_PHY_LN1r_CLR(reg_synce_divisor_lane1); 5966 MAIN_SYNCE_DIVISOR1_PHY_LN1r_SET(reg_synce_divisor_lane1, val); 5967 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR1_PHY_LN1r(pc, reg_synce_divisor_lane1)); 5968 break; 5969 case 2: 5970 MAIN_SYNCE_DIVISOR2_PHY_LN2r_CLR(reg_synce_divisor_lane2); 5971 MAIN_SYNCE_DIVISOR2_PHY_LN2r_SET(reg_synce_divisor_lane2, val); 5972 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR2_PHY_LN2r(pc, reg_synce_divisor_lane2)); 5973 break; 5974 case 3: 5975 MAIN_SYNCE_DIVISOR3_PHY_LN3r_CLR(reg_synce_divisor_lane3); 5976 MAIN_SYNCE_DIVISOR3_PHY_LN3r_SET(reg_synce_divisor_lane3, val); 5977 PHYMOD_IF_ERR_RETURN(WRITE_MAIN_SYNCE_DIVISOR3_PHY_LN3r(pc, reg_synce_divisor_lane3)); 5978 break; 5979 default: 5980 return PHYMOD_E_PARAM; 5981 } 5982 5983 return PHYMOD_E_NONE; 5984 } 5985 5986 int qmod_synce_mode_get(PHYMOD_ST *pc, int *mode0, int *mode1) 5987 { 5988 int start_lane = 0, num_lane = 0, phy_lane = 0; 5989 MAIN_SYNCE_CTLr_t reg_main_synce_ctl; 5990 5991 PHYMOD_IF_ERR_RETURN 5992 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 5993 5994 PHYMOD_IF_ERR_RETURN 5995 (_qmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 5996 5997 MAIN_SYNCE_CTLr_CLR(reg_main_synce_ctl); 5998 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_CTLr(pc, ®_main_synce_ctl)); 5999 6000 switch(phy_lane) { 6001 case 0: 6002 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN0f_GET(reg_main_synce_ctl); 6003 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN0f_GET(reg_main_synce_ctl); 6004 break; 6005 case 1: 6006 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN1f_GET(reg_main_synce_ctl); 6007 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN1f_GET(reg_main_synce_ctl); 6008 break; 6009 case 2: 6010 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN2f_GET(reg_main_synce_ctl); 6011 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN2f_GET(reg_main_synce_ctl); 6012 break; 6013 case 3: 6014 *mode0 = MAIN_SYNCE_CTLr_SYNCE_MODE0_PHY_LN3f_GET(reg_main_synce_ctl); 6015 *mode1 = MAIN_SYNCE_CTLr_SYNCE_MODE1_PHY_LN3f_GET(reg_main_synce_ctl); 6016 break; 6017 default: 6018 return PHYMOD_E_PARAM; 6019 } 6020 6021 return PHYMOD_E_NONE; 6022 } 6023 6024 int qmod_synce_clk_ctrl_get(PHYMOD_ST *pc, uint32_t *val) 6025 { 6026 int start_lane = 0, num_lane = 0, phy_lane = 0; 6027 MAIN_SYNCE_DIVISOR0_PHY_LN0r_t reg_synce_divisor_lane0; 6028 MAIN_SYNCE_DIVISOR1_PHY_LN1r_t reg_synce_divisor_lane1; 6029 MAIN_SYNCE_DIVISOR2_PHY_LN2r_t reg_synce_divisor_lane2; 6030 MAIN_SYNCE_DIVISOR3_PHY_LN3r_t reg_synce_divisor_lane3; 6031 6032 PHYMOD_IF_ERR_RETURN 6033 (phymod_util_lane_config_get(pc, &start_lane, &num_lane)); 6034 6035 PHYMOD_IF_ERR_RETURN 6036 (_qmod_rx_phy_lane_get(pc, start_lane, &phy_lane)); 6037 6038 switch(phy_lane) { 6039 case 0: 6040 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR0_PHY_LN0r(pc, ®_synce_divisor_lane0)); 6041 *val = MAIN_SYNCE_DIVISOR0_PHY_LN0r_GET(reg_synce_divisor_lane0); 6042 break; 6043 case 1: 6044 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR1_PHY_LN1r(pc, ®_synce_divisor_lane1)); 6045 *val = MAIN_SYNCE_DIVISOR1_PHY_LN1r_GET(reg_synce_divisor_lane1); 6046 break; 6047 case 2: 6048 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR2_PHY_LN2r(pc, ®_synce_divisor_lane2)); 6049 *val = MAIN_SYNCE_DIVISOR2_PHY_LN2r_GET(reg_synce_divisor_lane2); 6050 break; 6051 case 3: 6052 PHYMOD_IF_ERR_RETURN(READ_MAIN_SYNCE_DIVISOR3_PHY_LN3r(pc, ®_synce_divisor_lane3)); 6053 *val = MAIN_SYNCE_DIVISOR3_PHY_LN3r_GET(reg_synce_divisor_lane3); 6054 break; 6055 default: 6056 return PHYMOD_E_PARAM; 6057 } 6058 6059 return PHYMOD_E_NONE; 6060 }