qePCSRegEnums.h (175400B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 */ 6 7 #ifndef __PCS_ENUMS_H__ 8 #define __PCS_ENUMS_H__ 9 /**************************************************************************** 10 * Core Enums. 11 */ 12 /**************************************************************************** 13 * Enums: an_x4_sw_management_cl36TxEEEStates_l 14 */ 15 #define an_x4_sw_management_cl36TxEEEStates_l_TX_REFRESH 8 16 #define an_x4_sw_management_cl36TxEEEStates_l_TX_QUIET 4 17 #define an_x4_sw_management_cl36TxEEEStates_l_TX_SLEEP 2 18 #define an_x4_sw_management_cl36TxEEEStates_l_TX_ACTIVE 1 19 20 /**************************************************************************** 21 * Enums: an_x4_sw_management_cl36TxEEEStates_c 22 */ 23 #define an_x4_sw_management_cl36TxEEEStates_c_TX_REFRESH 3 24 #define an_x4_sw_management_cl36TxEEEStates_c_TX_QUIET 2 25 #define an_x4_sw_management_cl36TxEEEStates_c_TX_SLEEP 1 26 #define an_x4_sw_management_cl36TxEEEStates_c_TX_ACTIVE 0 27 28 /**************************************************************************** 29 * Enums: an_x4_sw_management_cl49TxEEEStates_l 30 */ 31 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_2 64 32 #define an_x4_sw_management_cl49TxEEEStates_l_SCR_RESET_1 32 33 #define an_x4_sw_management_cl49TxEEEStates_l_TX_WAKE 16 34 #define an_x4_sw_management_cl49TxEEEStates_l_TX_REFRESH 8 35 #define an_x4_sw_management_cl49TxEEEStates_l_TX_QUIET 4 36 #define an_x4_sw_management_cl49TxEEEStates_l_TX_SLEEP 2 37 #define an_x4_sw_management_cl49TxEEEStates_l_TX_ACTIVE 1 38 39 /**************************************************************************** 40 * Enums: an_x4_sw_management_cl49TxEEEStates_c 41 */ 42 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_2 6 43 #define an_x4_sw_management_cl49TxEEEStates_c_SCR_RESET_1 5 44 #define an_x4_sw_management_cl49TxEEEStates_c_TX_WAKE 4 45 #define an_x4_sw_management_cl49TxEEEStates_c_TX_REFRESH 3 46 #define an_x4_sw_management_cl49TxEEEStates_c_TX_QUIET 2 47 #define an_x4_sw_management_cl49TxEEEStates_c_TX_SLEEP 1 48 #define an_x4_sw_management_cl49TxEEEStates_c_TX_ACTIVE 0 49 50 /**************************************************************************** 51 * Enums: an_x4_sw_management_cl36RxEEEStates_l 52 */ 53 #define an_x4_sw_management_cl36RxEEEStates_l_RX_LINK_FAIL 32 54 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WTF 16 55 #define an_x4_sw_management_cl36RxEEEStates_l_RX_WAKE 8 56 #define an_x4_sw_management_cl36RxEEEStates_l_RX_QUIET 4 57 #define an_x4_sw_management_cl36RxEEEStates_l_RX_SLEEP 2 58 #define an_x4_sw_management_cl36RxEEEStates_l_RX_ACTIVE 1 59 60 /**************************************************************************** 61 * Enums: an_x4_sw_management_cl36RxEEEStates_c 62 */ 63 #define an_x4_sw_management_cl36RxEEEStates_c_RX_LINK_FAIL 5 64 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WTF 4 65 #define an_x4_sw_management_cl36RxEEEStates_c_RX_WAKE 3 66 #define an_x4_sw_management_cl36RxEEEStates_c_RX_QUIET 2 67 #define an_x4_sw_management_cl36RxEEEStates_c_RX_SLEEP 1 68 #define an_x4_sw_management_cl36RxEEEStates_c_RX_ACTIVE 0 69 70 /**************************************************************************** 71 * Enums: an_x4_sw_management_cl49RxEEEStates_l 72 */ 73 #define an_x4_sw_management_cl49RxEEEStates_l_RX_LINK_FAIL 32 74 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WTF 16 75 #define an_x4_sw_management_cl49RxEEEStates_l_RX_WAKE 8 76 #define an_x4_sw_management_cl49RxEEEStates_l_RX_QUIET 4 77 #define an_x4_sw_management_cl49RxEEEStates_l_RX_SLEEP 2 78 #define an_x4_sw_management_cl49RxEEEStates_l_RX_ACTIVE 1 79 80 /**************************************************************************** 81 * Enums: an_x4_sw_management_cl49RxEEEStates_c 82 */ 83 #define an_x4_sw_management_cl49RxEEEStates_c_RX_LINK_FAIL 5 84 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WTF 4 85 #define an_x4_sw_management_cl49RxEEEStates_c_RX_WAKE 3 86 #define an_x4_sw_management_cl49RxEEEStates_c_RX_QUIET 2 87 #define an_x4_sw_management_cl49RxEEEStates_c_RX_SLEEP 1 88 #define an_x4_sw_management_cl49RxEEEStates_c_RX_ACTIVE 0 89 90 /**************************************************************************** 91 * Enums: an_x4_sw_management_cl48TxEEEStates_l 92 */ 93 #define an_x4_sw_management_cl48TxEEEStates_l_TX_REFRESH 8 94 #define an_x4_sw_management_cl48TxEEEStates_l_TX_QUIET 4 95 #define an_x4_sw_management_cl48TxEEEStates_l_TX_SLEEP 2 96 #define an_x4_sw_management_cl48TxEEEStates_l_TX_ACTIVE 1 97 98 /**************************************************************************** 99 * Enums: an_x4_sw_management_cl48TxEEEStates_c 100 */ 101 #define an_x4_sw_management_cl48TxEEEStates_c_TX_REFRESH 3 102 #define an_x4_sw_management_cl48TxEEEStates_c_TX_QUIET 2 103 #define an_x4_sw_management_cl48TxEEEStates_c_TX_SLEEP 1 104 #define an_x4_sw_management_cl48TxEEEStates_c_TX_ACTIVE 0 105 106 /**************************************************************************** 107 * Enums: an_x4_sw_management_cl48RxEEEStates_l 108 */ 109 #define an_x4_sw_management_cl48RxEEEStates_l_RX_LINK_FAIL 32 110 #define an_x4_sw_management_cl48RxEEEStates_l_RX_WAKE 16 111 #define an_x4_sw_management_cl48RxEEEStates_l_RX_QUIET 8 112 #define an_x4_sw_management_cl48RxEEEStates_l_RX_DEACT 4 113 #define an_x4_sw_management_cl48RxEEEStates_l_RX_SLEEP 2 114 #define an_x4_sw_management_cl48RxEEEStates_l_RX_ACTIVE 1 115 116 /**************************************************************************** 117 * Enums: an_x4_sw_management_cl48RxEEEStates_c 118 */ 119 #define an_x4_sw_management_cl48RxEEEStates_c_RX_LINK_FAIL 5 120 #define an_x4_sw_management_cl48RxEEEStates_c_RX_WAKE 4 121 #define an_x4_sw_management_cl48RxEEEStates_c_RX_QUIET 3 122 #define an_x4_sw_management_cl48RxEEEStates_c_RX_DEACT 2 123 #define an_x4_sw_management_cl48RxEEEStates_c_RX_SLEEP 1 124 #define an_x4_sw_management_cl48RxEEEStates_c_RX_ACTIVE 0 125 126 /**************************************************************************** 127 * Enums: an_x4_sw_management_IQP_Options 128 */ 129 #define an_x4_sw_management_IQP_Options_i50uA 0 130 #define an_x4_sw_management_IQP_Options_i100uA 1 131 #define an_x4_sw_management_IQP_Options_i150uA 2 132 #define an_x4_sw_management_IQP_Options_i200uA 3 133 #define an_x4_sw_management_IQP_Options_i250uA 4 134 #define an_x4_sw_management_IQP_Options_i300uA 5 135 #define an_x4_sw_management_IQP_Options_i350uA 6 136 #define an_x4_sw_management_IQP_Options_i400uA 7 137 #define an_x4_sw_management_IQP_Options_i450uA 8 138 #define an_x4_sw_management_IQP_Options_i500uA 9 139 #define an_x4_sw_management_IQP_Options_i550uA 10 140 #define an_x4_sw_management_IQP_Options_i600uA 11 141 #define an_x4_sw_management_IQP_Options_i650uA 12 142 #define an_x4_sw_management_IQP_Options_i700uA 13 143 #define an_x4_sw_management_IQP_Options_i750uA 14 144 #define an_x4_sw_management_IQP_Options_i800uA 15 145 146 /**************************************************************************** 147 * Enums: an_x4_sw_management_IDriver_Options 148 */ 149 #define an_x4_sw_management_IDriver_Options_v680mV 0 150 #define an_x4_sw_management_IDriver_Options_v730mV 1 151 #define an_x4_sw_management_IDriver_Options_v780mV 2 152 #define an_x4_sw_management_IDriver_Options_v830mV 3 153 #define an_x4_sw_management_IDriver_Options_v880mV 4 154 #define an_x4_sw_management_IDriver_Options_v930mV 5 155 #define an_x4_sw_management_IDriver_Options_v980mV 6 156 #define an_x4_sw_management_IDriver_Options_v1010mV 7 157 #define an_x4_sw_management_IDriver_Options_v1040mV 8 158 #define an_x4_sw_management_IDriver_Options_v1060mV 9 159 #define an_x4_sw_management_IDriver_Options_v1070mV 10 160 #define an_x4_sw_management_IDriver_Options_v1080mV 11 161 #define an_x4_sw_management_IDriver_Options_v1085mV 12 162 #define an_x4_sw_management_IDriver_Options_v1090mV 13 163 #define an_x4_sw_management_IDriver_Options_v1095mV 14 164 #define an_x4_sw_management_IDriver_Options_v1100mV 15 165 166 /**************************************************************************** 167 * Enums: an_x4_sw_management_operationModes 168 */ 169 #define an_x4_sw_management_operationModes_XGXS 0 170 #define an_x4_sw_management_operationModes_XGXG_nCC 1 171 #define an_x4_sw_management_operationModes_Indlane_OS8 4 172 #define an_x4_sw_management_operationModes_IndLane_OS5 5 173 #define an_x4_sw_management_operationModes_PCI 7 174 #define an_x4_sw_management_operationModes_XGXS_nLQ 8 175 #define an_x4_sw_management_operationModes_XGXS_nLQnCC 9 176 #define an_x4_sw_management_operationModes_PBypass 10 177 #define an_x4_sw_management_operationModes_PBypass_nDSK 11 178 #define an_x4_sw_management_operationModes_ComboCoreMode 12 179 #define an_x4_sw_management_operationModes_Clocks_off 15 180 181 /**************************************************************************** 182 * Enums: an_x4_sw_management_synce_enum 183 */ 184 #define an_x4_sw_management_synce_enum_SYNCE_NO_DIV 0 185 #define an_x4_sw_management_synce_enum_SYNCE_DIV_7 1 186 #define an_x4_sw_management_synce_enum_SYNCE_DIV_11 2 187 188 /**************************************************************************** 189 * Enums: an_x4_sw_management_operationSpeeds 190 */ 191 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1_12p5 65 192 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_12p5 64 193 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_12p5 63 194 #define an_x4_sw_management_operationSpeeds_SPEED_100M_12p5 62 195 #define an_x4_sw_management_operationSpeeds_SPEED_10M_12p5 61 196 #define an_x4_sw_management_operationSpeeds_SPEED_4G_X1_10 60 197 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_X1_10 59 198 #define an_x4_sw_management_operationSpeeds_SPEED_100M_X1_10 58 199 #define an_x4_sw_management_operationSpeeds_SPEED_10M_X1_10 57 200 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1_10p3125 56 201 #define an_x4_sw_management_operationSpeeds_SPEED_1000M_10p3125 55 202 #define an_x4_sw_management_operationSpeeds_SPEED_100M_10p3125 54 203 #define an_x4_sw_management_operationSpeeds_SPEED_10M_10p3125 53 204 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X4 50 205 #define an_x4_sw_management_operationSpeeds_SPEED_5G_KR1 49 206 #define an_x4_sw_management_operationSpeeds_SPEED_127G_X12 39 207 #define an_x4_sw_management_operationSpeeds_SPEED_120G_X12 38 208 #define an_x4_sw_management_operationSpeeds_SPEED_107G_X10 37 209 #define an_x4_sw_management_operationSpeeds_SPEED_100G_CR10 36 210 #define an_x4_sw_management_operationSpeeds_SPEED_42G_X4 35 211 #define an_x4_sw_management_operationSpeeds_SPEED_40G_CR4 34 212 #define an_x4_sw_management_operationSpeeds_SPEED_40G_KR4 33 213 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X2 32 214 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CR2 31 215 #define an_x4_sw_management_operationSpeeds_SPEED_20G_KR2 30 216 #define an_x4_sw_management_operationSpeeds_SPEED_10p6_X1 29 217 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KR1 28 218 #define an_x4_sw_management_operationSpeeds_SPEED_40G_X4 27 219 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X2 26 220 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX2 25 221 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_KR4 24 222 #define an_x4_sw_management_operationSpeeds_SPEED_31p5G_X4 23 223 #define an_x4_sw_management_operationSpeeds_SPEED_15p75G_X2 22 224 #define an_x4_sw_management_operationSpeeds_SPEED_25p45G_X4 21 225 #define an_x4_sw_management_operationSpeeds_SPEED_12p7G_X2 20 226 #define an_x4_sw_management_operationSpeeds_SPEED_21G_X4 19 227 #define an_x4_sw_management_operationSpeeds_SPEED_10p5G_X2 18 228 #define an_x4_sw_management_operationSpeeds_SPEED_20G_X4 17 229 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X2 16 230 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX2 15 231 #define an_x4_sw_management_operationSpeeds_SPEED_20G_CX4 14 232 #define an_x4_sw_management_operationSpeeds_SPEED_16G_X4 13 233 #define an_x4_sw_management_operationSpeeds_SPEED_15G_X4 12 234 #define an_x4_sw_management_operationSpeeds_SPEED_13G_X4 11 235 #define an_x4_sw_management_operationSpeeds_SPEED_10G_X4 10 236 #define an_x4_sw_management_operationSpeeds_SPEED_10G_KX4 9 237 #define an_x4_sw_management_operationSpeeds_SPEED_10G_CX4 8 238 #define an_x4_sw_management_operationSpeeds_SPEED_5G_X1 7 239 #define an_x4_sw_management_operationSpeeds_SPEED_2p5G_X1 6 240 #define an_x4_sw_management_operationSpeeds_SPEED_1G_KX1 5 241 #define an_x4_sw_management_operationSpeeds_SPEED_1G_CX1 4 242 #define an_x4_sw_management_operationSpeeds_SPEED_1000M 3 243 #define an_x4_sw_management_operationSpeeds_SPEED_100M 2 244 #define an_x4_sw_management_operationSpeeds_SPEED_10M 1 245 246 /**************************************************************************** 247 * Enums: an_x4_sw_management_actualSpeeds 248 */ 249 #define an_x4_sw_management_actualSpeeds_dr_10M 0 250 #define an_x4_sw_management_actualSpeeds_dr_100M 1 251 #define an_x4_sw_management_actualSpeeds_dr_1G 2 252 #define an_x4_sw_management_actualSpeeds_dr_2p5G 3 253 #define an_x4_sw_management_actualSpeeds_dr_5G_X4 4 254 #define an_x4_sw_management_actualSpeeds_dr_6G_X4 5 255 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG 6 256 #define an_x4_sw_management_actualSpeeds_dr_10G_CX4 7 257 #define an_x4_sw_management_actualSpeeds_dr_12G_HiG 8 258 #define an_x4_sw_management_actualSpeeds_dr_12p5G_X4 9 259 #define an_x4_sw_management_actualSpeeds_dr_13G_X4 10 260 #define an_x4_sw_management_actualSpeeds_dr_15G_X4 11 261 #define an_x4_sw_management_actualSpeeds_dr_16G_X4 12 262 #define an_x4_sw_management_actualSpeeds_dr_1G_KX 13 263 #define an_x4_sw_management_actualSpeeds_dr_10G_KX4 14 264 #define an_x4_sw_management_actualSpeeds_dr_10G_KR 15 265 #define an_x4_sw_management_actualSpeeds_dr_5G 16 266 #define an_x4_sw_management_actualSpeeds_dr_6p4G 17 267 #define an_x4_sw_management_actualSpeeds_dr_20G_X4 18 268 #define an_x4_sw_management_actualSpeeds_dr_21G_X4 19 269 #define an_x4_sw_management_actualSpeeds_dr_25G_X4 20 270 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS 21 271 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS 22 272 #define an_x4_sw_management_actualSpeeds_dr_10p5G_HiG_DXGXS 23 273 #define an_x4_sw_management_actualSpeeds_dr_10p5G_DXGXS 24 274 #define an_x4_sw_management_actualSpeeds_dr_12p773G_HiG_DXGXS 25 275 #define an_x4_sw_management_actualSpeeds_dr_12p773G_DXGXS 26 276 #define an_x4_sw_management_actualSpeeds_dr_10G_XFI 27 277 #define an_x4_sw_management_actualSpeeds_dr_40G 28 278 #define an_x4_sw_management_actualSpeeds_dr_20G_HiG_DXGXS 29 279 #define an_x4_sw_management_actualSpeeds_dr_20G_DXGXS 30 280 #define an_x4_sw_management_actualSpeeds_dr_10G_SFI 31 281 #define an_x4_sw_management_actualSpeeds_dr_31p5G 32 282 #define an_x4_sw_management_actualSpeeds_dr_32p7G 33 283 #define an_x4_sw_management_actualSpeeds_dr_20G_SCR 34 284 #define an_x4_sw_management_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 285 #define an_x4_sw_management_actualSpeeds_dr_10G_DXGXS_SCR 36 286 #define an_x4_sw_management_actualSpeeds_dr_12G_R2 37 287 #define an_x4_sw_management_actualSpeeds_dr_10G_X2 38 288 #define an_x4_sw_management_actualSpeeds_dr_40G_KR4 39 289 #define an_x4_sw_management_actualSpeeds_dr_40G_CR4 40 290 #define an_x4_sw_management_actualSpeeds_dr_100G_CR10 41 291 #define an_x4_sw_management_actualSpeeds_dr_15p75G_DXGXS 44 292 #define an_x4_sw_management_actualSpeeds_dr_20G_KR2 57 293 #define an_x4_sw_management_actualSpeeds_dr_20G_CR2 58 294 295 /**************************************************************************** 296 * Enums: an_x4_sw_management_actualSpeedsMisc1 297 */ 298 #define an_x4_sw_management_actualSpeedsMisc1_dr_2500BRCM_X1 16 299 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X4 17 300 #define an_x4_sw_management_actualSpeedsMisc1_dr_6000BRCM_X4 18 301 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GHiGig_X4 19 302 #define an_x4_sw_management_actualSpeedsMisc1_dr_10GBASE_CX4 20 303 #define an_x4_sw_management_actualSpeedsMisc1_dr_12GHiGig_X4 21 304 #define an_x4_sw_management_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 305 #define an_x4_sw_management_actualSpeedsMisc1_dr_13GHiGig_X4 23 306 #define an_x4_sw_management_actualSpeedsMisc1_dr_15GHiGig_X4 24 307 #define an_x4_sw_management_actualSpeedsMisc1_dr_16GHiGig_X4 25 308 #define an_x4_sw_management_actualSpeedsMisc1_dr_5000BRCM_X1 26 309 #define an_x4_sw_management_actualSpeedsMisc1_dr_6363BRCM_X1 27 310 #define an_x4_sw_management_actualSpeedsMisc1_dr_20GHiGig_X4 28 311 #define an_x4_sw_management_actualSpeedsMisc1_dr_21GHiGig_X4 29 312 #define an_x4_sw_management_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 313 #define an_x4_sw_management_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 314 315 /**************************************************************************** 316 * Enums: an_x4_sw_management_IndLaneModes 317 */ 318 #define an_x4_sw_management_IndLaneModes_SWSDR_div2 0 319 #define an_x4_sw_management_IndLaneModes_SWSDR_div1 1 320 #define an_x4_sw_management_IndLaneModes_DWSDR_div2 2 321 #define an_x4_sw_management_IndLaneModes_DWSDR_div1 3 322 323 /**************************************************************************** 324 * Enums: an_x4_sw_management_prbsSelect 325 */ 326 #define an_x4_sw_management_prbsSelect_prbs7 0 327 #define an_x4_sw_management_prbsSelect_prbs15 1 328 #define an_x4_sw_management_prbsSelect_prbs23 2 329 #define an_x4_sw_management_prbsSelect_prbs31 3 330 331 /**************************************************************************** 332 * Enums: an_x4_sw_management_vcoDivider 333 */ 334 #define an_x4_sw_management_vcoDivider_div32 0 335 #define an_x4_sw_management_vcoDivider_div36 1 336 #define an_x4_sw_management_vcoDivider_div40 2 337 #define an_x4_sw_management_vcoDivider_div42 3 338 #define an_x4_sw_management_vcoDivider_div48 4 339 #define an_x4_sw_management_vcoDivider_div50 5 340 #define an_x4_sw_management_vcoDivider_div52 6 341 #define an_x4_sw_management_vcoDivider_div54 7 342 #define an_x4_sw_management_vcoDivider_div60 8 343 #define an_x4_sw_management_vcoDivider_div64 9 344 #define an_x4_sw_management_vcoDivider_div66 10 345 #define an_x4_sw_management_vcoDivider_div68 11 346 #define an_x4_sw_management_vcoDivider_div70 12 347 #define an_x4_sw_management_vcoDivider_div80 13 348 #define an_x4_sw_management_vcoDivider_div92 14 349 #define an_x4_sw_management_vcoDivider_div100 15 350 351 /**************************************************************************** 352 * Enums: an_x4_sw_management_refClkSelect 353 */ 354 #define an_x4_sw_management_refClkSelect_clk_25MHz 0 355 #define an_x4_sw_management_refClkSelect_clk_100MHz 1 356 #define an_x4_sw_management_refClkSelect_clk_125MHz 2 357 #define an_x4_sw_management_refClkSelect_clk_156p25MHz 3 358 #define an_x4_sw_management_refClkSelect_clk_187p5MHz 4 359 #define an_x4_sw_management_refClkSelect_clk_161p25Mhz 5 360 #define an_x4_sw_management_refClkSelect_clk_50Mhz 6 361 #define an_x4_sw_management_refClkSelect_clk_106p25Mhz 7 362 363 /**************************************************************************** 364 * Enums: an_x4_sw_management_aerMMDdevTypeSelect 365 */ 366 #define an_x4_sw_management_aerMMDdevTypeSelect_combo_core 0 367 #define an_x4_sw_management_aerMMDdevTypeSelect_PMA_PMD 1 368 #define an_x4_sw_management_aerMMDdevTypeSelect_PCS 3 369 #define an_x4_sw_management_aerMMDdevTypeSelect_PHY 4 370 #define an_x4_sw_management_aerMMDdevTypeSelect_DTE 5 371 #define an_x4_sw_management_aerMMDdevTypeSelect_CL73_AN 7 372 373 /**************************************************************************** 374 * Enums: an_x4_sw_management_aerMMDportSelect 375 */ 376 #define an_x4_sw_management_aerMMDportSelect_ln0 0 377 #define an_x4_sw_management_aerMMDportSelect_ln1 1 378 #define an_x4_sw_management_aerMMDportSelect_ln2 2 379 #define an_x4_sw_management_aerMMDportSelect_ln3 3 380 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1_2_3 511 381 #define an_x4_sw_management_aerMMDportSelect_BCST_ln0_1 512 382 #define an_x4_sw_management_aerMMDportSelect_BCST_ln2_3 513 383 384 /**************************************************************************** 385 * Enums: an_x4_sw_management_firmwareModeSelect 386 */ 387 #define an_x4_sw_management_firmwareModeSelect_DEFAULT 0 388 #define an_x4_sw_management_firmwareModeSelect_SFP_OPT_LR 1 389 #define an_x4_sw_management_firmwareModeSelect_SFP_DAC 2 390 #define an_x4_sw_management_firmwareModeSelect_XLAUI 3 391 #define an_x4_sw_management_firmwareModeSelect_LONG_CH_6G 4 392 393 /**************************************************************************** 394 * Enums: an_x4_sw_management_tempIdxSelect 395 */ 396 #define an_x4_sw_management_tempIdxSelect_LTE__22p9C 15 397 #define an_x4_sw_management_tempIdxSelect_LTE__12p6C 14 398 #define an_x4_sw_management_tempIdxSelect_LTE__3p0C 13 399 #define an_x4_sw_management_tempIdxSelect_LTE_6p7C 12 400 #define an_x4_sw_management_tempIdxSelect_LTE_16p4C 11 401 #define an_x4_sw_management_tempIdxSelect_LTE_26p6C 10 402 #define an_x4_sw_management_tempIdxSelect_LTE_36p3C 9 403 #define an_x4_sw_management_tempIdxSelect_LTE_46p0C 8 404 #define an_x4_sw_management_tempIdxSelect_LTE_56p2C 7 405 #define an_x4_sw_management_tempIdxSelect_LTE_65p9C 6 406 #define an_x4_sw_management_tempIdxSelect_LTE_75p6C 5 407 #define an_x4_sw_management_tempIdxSelect_LTE_85p3C 4 408 #define an_x4_sw_management_tempIdxSelect_LTE_95p5C 3 409 #define an_x4_sw_management_tempIdxSelect_LTE_105p2C 2 410 #define an_x4_sw_management_tempIdxSelect_LTE_114p9C 1 411 #define an_x4_sw_management_tempIdxSelect_LTE_125p1C 0 412 413 /**************************************************************************** 414 * Enums: an_x4_sw_management_tla_ln_seq_status 415 */ 416 #define an_x4_sw_management_tla_ln_seq_status_INIT 1 417 #define an_x4_sw_management_tla_ln_seq_status_SET_AN_SPEED 2 418 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_SPEED 4 419 #define an_x4_sw_management_tla_ln_seq_status_WAIT_AN_DONE 8 420 #define an_x4_sw_management_tla_ln_seq_status_SET_RS_SPEED 16 421 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_CL72EN 32 422 #define an_x4_sw_management_tla_ln_seq_status_WAIT_RS_SPEED 64 423 #define an_x4_sw_management_tla_ln_seq_status_AN_IGNORE_LINK 128 424 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD_CHECK 256 425 #define an_x4_sw_management_tla_ln_seq_status_AN_GOOD 512 426 #define an_x4_sw_management_tla_ln_seq_status_AN_FAIL 1024 427 #define an_x4_sw_management_tla_ln_seq_status_AN_DEAD 2048 428 #define an_x4_sw_management_tla_ln_seq_status_SET_PD_SPEED 4096 429 #define an_x4_sw_management_tla_ln_seq_status_WAIT_PD_SPEED 8192 430 #define an_x4_sw_management_tla_ln_seq_status_PD_IGNORE_LINK 16384 431 #define an_x4_sw_management_tla_ln_seq_status_PD_GOOD_CHECK 32768 432 433 /**************************************************************************** 434 * Enums: an_x4_sw_management_tla_ln_seq_status1 435 */ 436 #define an_x4_sw_management_tla_ln_seq_status1_SW_SPEED_CHANGE 64 437 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_SW 32 438 #define an_x4_sw_management_tla_ln_seq_status1_RELEASE_DISABLE 16 439 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_LINK 8 440 #define an_x4_sw_management_tla_ln_seq_status1_PD_START_CL37_AN 4 441 #define an_x4_sw_management_tla_ln_seq_status1_PD_WAIT_CL37_AN_DONE 2 442 #define an_x4_sw_management_tla_ln_seq_status1_PD_DONE_CL37 1 443 444 /**************************************************************************** 445 * Enums: digital_cl36TxEEEStates_l 446 */ 447 #define digital_cl36TxEEEStates_l_TX_REFRESH 8 448 #define digital_cl36TxEEEStates_l_TX_QUIET 4 449 #define digital_cl36TxEEEStates_l_TX_SLEEP 2 450 #define digital_cl36TxEEEStates_l_TX_ACTIVE 1 451 452 /**************************************************************************** 453 * Enums: digital_cl36TxEEEStates_c 454 */ 455 #define digital_cl36TxEEEStates_c_TX_REFRESH 3 456 #define digital_cl36TxEEEStates_c_TX_QUIET 2 457 #define digital_cl36TxEEEStates_c_TX_SLEEP 1 458 #define digital_cl36TxEEEStates_c_TX_ACTIVE 0 459 460 /**************************************************************************** 461 * Enums: digital_cl49TxEEEStates_l 462 */ 463 #define digital_cl49TxEEEStates_l_SCR_RESET_2 64 464 #define digital_cl49TxEEEStates_l_SCR_RESET_1 32 465 #define digital_cl49TxEEEStates_l_TX_WAKE 16 466 #define digital_cl49TxEEEStates_l_TX_REFRESH 8 467 #define digital_cl49TxEEEStates_l_TX_QUIET 4 468 #define digital_cl49TxEEEStates_l_TX_SLEEP 2 469 #define digital_cl49TxEEEStates_l_TX_ACTIVE 1 470 471 /**************************************************************************** 472 * Enums: digital_cl49TxEEEStates_c 473 */ 474 #define digital_cl49TxEEEStates_c_SCR_RESET_2 6 475 #define digital_cl49TxEEEStates_c_SCR_RESET_1 5 476 #define digital_cl49TxEEEStates_c_TX_WAKE 4 477 #define digital_cl49TxEEEStates_c_TX_REFRESH 3 478 #define digital_cl49TxEEEStates_c_TX_QUIET 2 479 #define digital_cl49TxEEEStates_c_TX_SLEEP 1 480 #define digital_cl49TxEEEStates_c_TX_ACTIVE 0 481 482 /**************************************************************************** 483 * Enums: digital_cl36RxEEEStates_l 484 */ 485 #define digital_cl36RxEEEStates_l_RX_LINK_FAIL 32 486 #define digital_cl36RxEEEStates_l_RX_WTF 16 487 #define digital_cl36RxEEEStates_l_RX_WAKE 8 488 #define digital_cl36RxEEEStates_l_RX_QUIET 4 489 #define digital_cl36RxEEEStates_l_RX_SLEEP 2 490 #define digital_cl36RxEEEStates_l_RX_ACTIVE 1 491 492 /**************************************************************************** 493 * Enums: digital_cl36RxEEEStates_c 494 */ 495 #define digital_cl36RxEEEStates_c_RX_LINK_FAIL 5 496 #define digital_cl36RxEEEStates_c_RX_WTF 4 497 #define digital_cl36RxEEEStates_c_RX_WAKE 3 498 #define digital_cl36RxEEEStates_c_RX_QUIET 2 499 #define digital_cl36RxEEEStates_c_RX_SLEEP 1 500 #define digital_cl36RxEEEStates_c_RX_ACTIVE 0 501 502 /**************************************************************************** 503 * Enums: digital_cl49RxEEEStates_l 504 */ 505 #define digital_cl49RxEEEStates_l_RX_LINK_FAIL 32 506 #define digital_cl49RxEEEStates_l_RX_WTF 16 507 #define digital_cl49RxEEEStates_l_RX_WAKE 8 508 #define digital_cl49RxEEEStates_l_RX_QUIET 4 509 #define digital_cl49RxEEEStates_l_RX_SLEEP 2 510 #define digital_cl49RxEEEStates_l_RX_ACTIVE 1 511 512 /**************************************************************************** 513 * Enums: digital_cl49RxEEEStates_c 514 */ 515 #define digital_cl49RxEEEStates_c_RX_LINK_FAIL 5 516 #define digital_cl49RxEEEStates_c_RX_WTF 4 517 #define digital_cl49RxEEEStates_c_RX_WAKE 3 518 #define digital_cl49RxEEEStates_c_RX_QUIET 2 519 #define digital_cl49RxEEEStates_c_RX_SLEEP 1 520 #define digital_cl49RxEEEStates_c_RX_ACTIVE 0 521 522 /**************************************************************************** 523 * Enums: digital_cl48TxEEEStates_l 524 */ 525 #define digital_cl48TxEEEStates_l_TX_REFRESH 8 526 #define digital_cl48TxEEEStates_l_TX_QUIET 4 527 #define digital_cl48TxEEEStates_l_TX_SLEEP 2 528 #define digital_cl48TxEEEStates_l_TX_ACTIVE 1 529 530 /**************************************************************************** 531 * Enums: digital_cl48TxEEEStates_c 532 */ 533 #define digital_cl48TxEEEStates_c_TX_REFRESH 3 534 #define digital_cl48TxEEEStates_c_TX_QUIET 2 535 #define digital_cl48TxEEEStates_c_TX_SLEEP 1 536 #define digital_cl48TxEEEStates_c_TX_ACTIVE 0 537 538 /**************************************************************************** 539 * Enums: digital_cl48RxEEEStates_l 540 */ 541 #define digital_cl48RxEEEStates_l_RX_LINK_FAIL 32 542 #define digital_cl48RxEEEStates_l_RX_WAKE 16 543 #define digital_cl48RxEEEStates_l_RX_QUIET 8 544 #define digital_cl48RxEEEStates_l_RX_DEACT 4 545 #define digital_cl48RxEEEStates_l_RX_SLEEP 2 546 #define digital_cl48RxEEEStates_l_RX_ACTIVE 1 547 548 /**************************************************************************** 549 * Enums: digital_cl48RxEEEStates_c 550 */ 551 #define digital_cl48RxEEEStates_c_RX_LINK_FAIL 5 552 #define digital_cl48RxEEEStates_c_RX_WAKE 4 553 #define digital_cl48RxEEEStates_c_RX_QUIET 3 554 #define digital_cl48RxEEEStates_c_RX_DEACT 2 555 #define digital_cl48RxEEEStates_c_RX_SLEEP 1 556 #define digital_cl48RxEEEStates_c_RX_ACTIVE 0 557 558 /**************************************************************************** 559 * Enums: digital_IQP_Options 560 */ 561 #define digital_IQP_Options_i50uA 0 562 #define digital_IQP_Options_i100uA 1 563 #define digital_IQP_Options_i150uA 2 564 #define digital_IQP_Options_i200uA 3 565 #define digital_IQP_Options_i250uA 4 566 #define digital_IQP_Options_i300uA 5 567 #define digital_IQP_Options_i350uA 6 568 #define digital_IQP_Options_i400uA 7 569 #define digital_IQP_Options_i450uA 8 570 #define digital_IQP_Options_i500uA 9 571 #define digital_IQP_Options_i550uA 10 572 #define digital_IQP_Options_i600uA 11 573 #define digital_IQP_Options_i650uA 12 574 #define digital_IQP_Options_i700uA 13 575 #define digital_IQP_Options_i750uA 14 576 #define digital_IQP_Options_i800uA 15 577 578 /**************************************************************************** 579 * Enums: digital_IDriver_Options 580 */ 581 #define digital_IDriver_Options_v680mV 0 582 #define digital_IDriver_Options_v730mV 1 583 #define digital_IDriver_Options_v780mV 2 584 #define digital_IDriver_Options_v830mV 3 585 #define digital_IDriver_Options_v880mV 4 586 #define digital_IDriver_Options_v930mV 5 587 #define digital_IDriver_Options_v980mV 6 588 #define digital_IDriver_Options_v1010mV 7 589 #define digital_IDriver_Options_v1040mV 8 590 #define digital_IDriver_Options_v1060mV 9 591 #define digital_IDriver_Options_v1070mV 10 592 #define digital_IDriver_Options_v1080mV 11 593 #define digital_IDriver_Options_v1085mV 12 594 #define digital_IDriver_Options_v1090mV 13 595 #define digital_IDriver_Options_v1095mV 14 596 #define digital_IDriver_Options_v1100mV 15 597 598 /**************************************************************************** 599 * Enums: digital_operationModes 600 */ 601 #define digital_operationModes_XGXS 0 602 #define digital_operationModes_XGXG_nCC 1 603 #define digital_operationModes_Indlane_OS8 4 604 #define digital_operationModes_IndLane_OS5 5 605 #define digital_operationModes_PCI 7 606 #define digital_operationModes_XGXS_nLQ 8 607 #define digital_operationModes_XGXS_nLQnCC 9 608 #define digital_operationModes_PBypass 10 609 #define digital_operationModes_PBypass_nDSK 11 610 #define digital_operationModes_ComboCoreMode 12 611 #define digital_operationModes_Clocks_off 15 612 613 /**************************************************************************** 614 * Enums: digital_synce_enum 615 */ 616 #define digital_synce_enum_SYNCE_NO_DIV 0 617 #define digital_synce_enum_SYNCE_DIV_7 1 618 #define digital_synce_enum_SYNCE_DIV_11 2 619 620 /**************************************************************************** 621 * Enums: digital_operationSpeeds 622 */ 623 #define digital_operationSpeeds_SPEED_5G_X1_12p5 65 624 #define digital_operationSpeeds_SPEED_2p5G_X1_12p5 64 625 #define digital_operationSpeeds_SPEED_1000M_12p5 63 626 #define digital_operationSpeeds_SPEED_100M_12p5 62 627 #define digital_operationSpeeds_SPEED_10M_12p5 61 628 #define digital_operationSpeeds_SPEED_4G_X1_10 60 629 #define digital_operationSpeeds_SPEED_1000M_X1_10 59 630 #define digital_operationSpeeds_SPEED_100M_X1_10 58 631 #define digital_operationSpeeds_SPEED_10M_X1_10 57 632 #define digital_operationSpeeds_SPEED_2p5G_X1_10p3125 56 633 #define digital_operationSpeeds_SPEED_1000M_10p3125 55 634 #define digital_operationSpeeds_SPEED_100M_10p3125 54 635 #define digital_operationSpeeds_SPEED_10M_10p3125 53 636 #define digital_operationSpeeds_SPEED_10p5G_X4 50 637 #define digital_operationSpeeds_SPEED_5G_KR1 49 638 #define digital_operationSpeeds_SPEED_127G_X12 39 639 #define digital_operationSpeeds_SPEED_120G_X12 38 640 #define digital_operationSpeeds_SPEED_107G_X10 37 641 #define digital_operationSpeeds_SPEED_100G_CR10 36 642 #define digital_operationSpeeds_SPEED_42G_X4 35 643 #define digital_operationSpeeds_SPEED_40G_CR4 34 644 #define digital_operationSpeeds_SPEED_40G_KR4 33 645 #define digital_operationSpeeds_SPEED_21G_X2 32 646 #define digital_operationSpeeds_SPEED_20G_CR2 31 647 #define digital_operationSpeeds_SPEED_20G_KR2 30 648 #define digital_operationSpeeds_SPEED_10p6_X1 29 649 #define digital_operationSpeeds_SPEED_10G_KR1 28 650 #define digital_operationSpeeds_SPEED_40G_X4 27 651 #define digital_operationSpeeds_SPEED_20G_X2 26 652 #define digital_operationSpeeds_SPEED_20G_CX2 25 653 #define digital_operationSpeeds_SPEED_31p5G_KR4 24 654 #define digital_operationSpeeds_SPEED_31p5G_X4 23 655 #define digital_operationSpeeds_SPEED_15p75G_X2 22 656 #define digital_operationSpeeds_SPEED_25p45G_X4 21 657 #define digital_operationSpeeds_SPEED_12p7G_X2 20 658 #define digital_operationSpeeds_SPEED_21G_X4 19 659 #define digital_operationSpeeds_SPEED_10p5G_X2 18 660 #define digital_operationSpeeds_SPEED_20G_X4 17 661 #define digital_operationSpeeds_SPEED_10G_X2 16 662 #define digital_operationSpeeds_SPEED_10G_CX2 15 663 #define digital_operationSpeeds_SPEED_20G_CX4 14 664 #define digital_operationSpeeds_SPEED_16G_X4 13 665 #define digital_operationSpeeds_SPEED_15G_X4 12 666 #define digital_operationSpeeds_SPEED_13G_X4 11 667 #define digital_operationSpeeds_SPEED_10G_X4 10 668 #define digital_operationSpeeds_SPEED_10G_KX4 9 669 #define digital_operationSpeeds_SPEED_10G_CX4 8 670 #define digital_operationSpeeds_SPEED_5G_X1 7 671 #define digital_operationSpeeds_SPEED_2p5G_X1 6 672 #define digital_operationSpeeds_SPEED_1G_KX1 5 673 #define digital_operationSpeeds_SPEED_1G_CX1 4 674 #define digital_operationSpeeds_SPEED_1000M 3 675 #define digital_operationSpeeds_SPEED_100M 2 676 #define digital_operationSpeeds_SPEED_10M 1 677 678 /**************************************************************************** 679 * Enums: digital_actualSpeeds 680 */ 681 #define digital_actualSpeeds_dr_10M 0 682 #define digital_actualSpeeds_dr_100M 1 683 #define digital_actualSpeeds_dr_1G 2 684 #define digital_actualSpeeds_dr_2p5G 3 685 #define digital_actualSpeeds_dr_5G_X4 4 686 #define digital_actualSpeeds_dr_6G_X4 5 687 #define digital_actualSpeeds_dr_10G_HiG 6 688 #define digital_actualSpeeds_dr_10G_CX4 7 689 #define digital_actualSpeeds_dr_12G_HiG 8 690 #define digital_actualSpeeds_dr_12p5G_X4 9 691 #define digital_actualSpeeds_dr_13G_X4 10 692 #define digital_actualSpeeds_dr_15G_X4 11 693 #define digital_actualSpeeds_dr_16G_X4 12 694 #define digital_actualSpeeds_dr_1G_KX 13 695 #define digital_actualSpeeds_dr_10G_KX4 14 696 #define digital_actualSpeeds_dr_10G_KR 15 697 #define digital_actualSpeeds_dr_5G 16 698 #define digital_actualSpeeds_dr_6p4G 17 699 #define digital_actualSpeeds_dr_20G_X4 18 700 #define digital_actualSpeeds_dr_21G_X4 19 701 #define digital_actualSpeeds_dr_25G_X4 20 702 #define digital_actualSpeeds_dr_10G_HiG_DXGXS 21 703 #define digital_actualSpeeds_dr_10G_DXGXS 22 704 #define digital_actualSpeeds_dr_10p5G_HiG_DXGXS 23 705 #define digital_actualSpeeds_dr_10p5G_DXGXS 24 706 #define digital_actualSpeeds_dr_12p773G_HiG_DXGXS 25 707 #define digital_actualSpeeds_dr_12p773G_DXGXS 26 708 #define digital_actualSpeeds_dr_10G_XFI 27 709 #define digital_actualSpeeds_dr_40G 28 710 #define digital_actualSpeeds_dr_20G_HiG_DXGXS 29 711 #define digital_actualSpeeds_dr_20G_DXGXS 30 712 #define digital_actualSpeeds_dr_10G_SFI 31 713 #define digital_actualSpeeds_dr_31p5G 32 714 #define digital_actualSpeeds_dr_32p7G 33 715 #define digital_actualSpeeds_dr_20G_SCR 34 716 #define digital_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 717 #define digital_actualSpeeds_dr_10G_DXGXS_SCR 36 718 #define digital_actualSpeeds_dr_12G_R2 37 719 #define digital_actualSpeeds_dr_10G_X2 38 720 #define digital_actualSpeeds_dr_40G_KR4 39 721 #define digital_actualSpeeds_dr_40G_CR4 40 722 #define digital_actualSpeeds_dr_100G_CR10 41 723 #define digital_actualSpeeds_dr_15p75G_DXGXS 44 724 #define digital_actualSpeeds_dr_20G_KR2 57 725 #define digital_actualSpeeds_dr_20G_CR2 58 726 727 /**************************************************************************** 728 * Enums: digital_actualSpeedsMisc1 729 */ 730 #define digital_actualSpeedsMisc1_dr_2500BRCM_X1 16 731 #define digital_actualSpeedsMisc1_dr_5000BRCM_X4 17 732 #define digital_actualSpeedsMisc1_dr_6000BRCM_X4 18 733 #define digital_actualSpeedsMisc1_dr_10GHiGig_X4 19 734 #define digital_actualSpeedsMisc1_dr_10GBASE_CX4 20 735 #define digital_actualSpeedsMisc1_dr_12GHiGig_X4 21 736 #define digital_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 737 #define digital_actualSpeedsMisc1_dr_13GHiGig_X4 23 738 #define digital_actualSpeedsMisc1_dr_15GHiGig_X4 24 739 #define digital_actualSpeedsMisc1_dr_16GHiGig_X4 25 740 #define digital_actualSpeedsMisc1_dr_5000BRCM_X1 26 741 #define digital_actualSpeedsMisc1_dr_6363BRCM_X1 27 742 #define digital_actualSpeedsMisc1_dr_20GHiGig_X4 28 743 #define digital_actualSpeedsMisc1_dr_21GHiGig_X4 29 744 #define digital_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 745 #define digital_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 746 747 /**************************************************************************** 748 * Enums: digital_IndLaneModes 749 */ 750 #define digital_IndLaneModes_SWSDR_div2 0 751 #define digital_IndLaneModes_SWSDR_div1 1 752 #define digital_IndLaneModes_DWSDR_div2 2 753 #define digital_IndLaneModes_DWSDR_div1 3 754 755 /**************************************************************************** 756 * Enums: digital_prbsSelect 757 */ 758 #define digital_prbsSelect_prbs7 0 759 #define digital_prbsSelect_prbs15 1 760 #define digital_prbsSelect_prbs23 2 761 #define digital_prbsSelect_prbs31 3 762 763 /**************************************************************************** 764 * Enums: digital_vcoDivider 765 */ 766 #define digital_vcoDivider_div32 0 767 #define digital_vcoDivider_div36 1 768 #define digital_vcoDivider_div40 2 769 #define digital_vcoDivider_div42 3 770 #define digital_vcoDivider_div48 4 771 #define digital_vcoDivider_div50 5 772 #define digital_vcoDivider_div52 6 773 #define digital_vcoDivider_div54 7 774 #define digital_vcoDivider_div60 8 775 #define digital_vcoDivider_div64 9 776 #define digital_vcoDivider_div66 10 777 #define digital_vcoDivider_div68 11 778 #define digital_vcoDivider_div70 12 779 #define digital_vcoDivider_div80 13 780 #define digital_vcoDivider_div92 14 781 #define digital_vcoDivider_div100 15 782 783 /**************************************************************************** 784 * Enums: digital_refClkSelect 785 */ 786 #define digital_refClkSelect_clk_25MHz 0 787 #define digital_refClkSelect_clk_100MHz 1 788 #define digital_refClkSelect_clk_125MHz 2 789 #define digital_refClkSelect_clk_156p25MHz 3 790 #define digital_refClkSelect_clk_187p5MHz 4 791 #define digital_refClkSelect_clk_161p25Mhz 5 792 #define digital_refClkSelect_clk_50Mhz 6 793 #define digital_refClkSelect_clk_106p25Mhz 7 794 795 /**************************************************************************** 796 * Enums: digital_aerMMDdevTypeSelect 797 */ 798 #define digital_aerMMDdevTypeSelect_combo_core 0 799 #define digital_aerMMDdevTypeSelect_PMA_PMD 1 800 #define digital_aerMMDdevTypeSelect_PCS 3 801 #define digital_aerMMDdevTypeSelect_PHY 4 802 #define digital_aerMMDdevTypeSelect_DTE 5 803 #define digital_aerMMDdevTypeSelect_CL73_AN 7 804 805 /**************************************************************************** 806 * Enums: digital_aerMMDportSelect 807 */ 808 #define digital_aerMMDportSelect_ln0 0 809 #define digital_aerMMDportSelect_ln1 1 810 #define digital_aerMMDportSelect_ln2 2 811 #define digital_aerMMDportSelect_ln3 3 812 #define digital_aerMMDportSelect_BCST_ln0_1_2_3 511 813 #define digital_aerMMDportSelect_BCST_ln0_1 512 814 #define digital_aerMMDportSelect_BCST_ln2_3 513 815 816 /**************************************************************************** 817 * Enums: digital_firmwareModeSelect 818 */ 819 #define digital_firmwareModeSelect_DEFAULT 0 820 #define digital_firmwareModeSelect_SFP_OPT_LR 1 821 #define digital_firmwareModeSelect_SFP_DAC 2 822 #define digital_firmwareModeSelect_XLAUI 3 823 #define digital_firmwareModeSelect_LONG_CH_6G 4 824 825 /**************************************************************************** 826 * Enums: digital_tempIdxSelect 827 */ 828 #define digital_tempIdxSelect_LTE__22p9C 15 829 #define digital_tempIdxSelect_LTE__12p6C 14 830 #define digital_tempIdxSelect_LTE__3p0C 13 831 #define digital_tempIdxSelect_LTE_6p7C 12 832 #define digital_tempIdxSelect_LTE_16p4C 11 833 #define digital_tempIdxSelect_LTE_26p6C 10 834 #define digital_tempIdxSelect_LTE_36p3C 9 835 #define digital_tempIdxSelect_LTE_46p0C 8 836 #define digital_tempIdxSelect_LTE_56p2C 7 837 #define digital_tempIdxSelect_LTE_65p9C 6 838 #define digital_tempIdxSelect_LTE_75p6C 5 839 #define digital_tempIdxSelect_LTE_85p3C 4 840 #define digital_tempIdxSelect_LTE_95p5C 3 841 #define digital_tempIdxSelect_LTE_105p2C 2 842 #define digital_tempIdxSelect_LTE_114p9C 1 843 #define digital_tempIdxSelect_LTE_125p1C 0 844 845 /**************************************************************************** 846 * Enums: generic_cl36TxEEEStates_l 847 */ 848 #define generic_cl36TxEEEStates_l_TX_REFRESH 8 849 #define generic_cl36TxEEEStates_l_TX_QUIET 4 850 #define generic_cl36TxEEEStates_l_TX_SLEEP 2 851 #define generic_cl36TxEEEStates_l_TX_ACTIVE 1 852 853 /**************************************************************************** 854 * Enums: generic_cl36TxEEEStates_c 855 */ 856 #define generic_cl36TxEEEStates_c_TX_REFRESH 3 857 #define generic_cl36TxEEEStates_c_TX_QUIET 2 858 #define generic_cl36TxEEEStates_c_TX_SLEEP 1 859 #define generic_cl36TxEEEStates_c_TX_ACTIVE 0 860 861 /**************************************************************************** 862 * Enums: generic_cl49TxEEEStates_l 863 */ 864 #define generic_cl49TxEEEStates_l_SCR_RESET_2 64 865 #define generic_cl49TxEEEStates_l_SCR_RESET_1 32 866 #define generic_cl49TxEEEStates_l_TX_WAKE 16 867 #define generic_cl49TxEEEStates_l_TX_REFRESH 8 868 #define generic_cl49TxEEEStates_l_TX_QUIET 4 869 #define generic_cl49TxEEEStates_l_TX_SLEEP 2 870 #define generic_cl49TxEEEStates_l_TX_ACTIVE 1 871 872 /**************************************************************************** 873 * Enums: generic_cl49TxEEEStates_c 874 */ 875 #define generic_cl49TxEEEStates_c_SCR_RESET_2 6 876 #define generic_cl49TxEEEStates_c_SCR_RESET_1 5 877 #define generic_cl49TxEEEStates_c_TX_WAKE 4 878 #define generic_cl49TxEEEStates_c_TX_REFRESH 3 879 #define generic_cl49TxEEEStates_c_TX_QUIET 2 880 #define generic_cl49TxEEEStates_c_TX_SLEEP 1 881 #define generic_cl49TxEEEStates_c_TX_ACTIVE 0 882 883 /**************************************************************************** 884 * Enums: generic_cl36RxEEEStates_l 885 */ 886 #define generic_cl36RxEEEStates_l_RX_LINK_FAIL 32 887 #define generic_cl36RxEEEStates_l_RX_WTF 16 888 #define generic_cl36RxEEEStates_l_RX_WAKE 8 889 #define generic_cl36RxEEEStates_l_RX_QUIET 4 890 #define generic_cl36RxEEEStates_l_RX_SLEEP 2 891 #define generic_cl36RxEEEStates_l_RX_ACTIVE 1 892 893 /**************************************************************************** 894 * Enums: generic_cl36RxEEEStates_c 895 */ 896 #define generic_cl36RxEEEStates_c_RX_LINK_FAIL 5 897 #define generic_cl36RxEEEStates_c_RX_WTF 4 898 #define generic_cl36RxEEEStates_c_RX_WAKE 3 899 #define generic_cl36RxEEEStates_c_RX_QUIET 2 900 #define generic_cl36RxEEEStates_c_RX_SLEEP 1 901 #define generic_cl36RxEEEStates_c_RX_ACTIVE 0 902 903 /**************************************************************************** 904 * Enums: generic_cl49RxEEEStates_l 905 */ 906 #define generic_cl49RxEEEStates_l_RX_LINK_FAIL 32 907 #define generic_cl49RxEEEStates_l_RX_WTF 16 908 #define generic_cl49RxEEEStates_l_RX_WAKE 8 909 #define generic_cl49RxEEEStates_l_RX_QUIET 4 910 #define generic_cl49RxEEEStates_l_RX_SLEEP 2 911 #define generic_cl49RxEEEStates_l_RX_ACTIVE 1 912 913 /**************************************************************************** 914 * Enums: generic_cl49RxEEEStates_c 915 */ 916 #define generic_cl49RxEEEStates_c_RX_LINK_FAIL 5 917 #define generic_cl49RxEEEStates_c_RX_WTF 4 918 #define generic_cl49RxEEEStates_c_RX_WAKE 3 919 #define generic_cl49RxEEEStates_c_RX_QUIET 2 920 #define generic_cl49RxEEEStates_c_RX_SLEEP 1 921 #define generic_cl49RxEEEStates_c_RX_ACTIVE 0 922 923 /**************************************************************************** 924 * Enums: generic_cl48TxEEEStates_l 925 */ 926 #define generic_cl48TxEEEStates_l_TX_REFRESH 8 927 #define generic_cl48TxEEEStates_l_TX_QUIET 4 928 #define generic_cl48TxEEEStates_l_TX_SLEEP 2 929 #define generic_cl48TxEEEStates_l_TX_ACTIVE 1 930 931 /**************************************************************************** 932 * Enums: generic_cl48TxEEEStates_c 933 */ 934 #define generic_cl48TxEEEStates_c_TX_REFRESH 3 935 #define generic_cl48TxEEEStates_c_TX_QUIET 2 936 #define generic_cl48TxEEEStates_c_TX_SLEEP 1 937 #define generic_cl48TxEEEStates_c_TX_ACTIVE 0 938 939 /**************************************************************************** 940 * Enums: generic_cl48RxEEEStates_l 941 */ 942 #define generic_cl48RxEEEStates_l_RX_LINK_FAIL 32 943 #define generic_cl48RxEEEStates_l_RX_WAKE 16 944 #define generic_cl48RxEEEStates_l_RX_QUIET 8 945 #define generic_cl48RxEEEStates_l_RX_DEACT 4 946 #define generic_cl48RxEEEStates_l_RX_SLEEP 2 947 #define generic_cl48RxEEEStates_l_RX_ACTIVE 1 948 949 /**************************************************************************** 950 * Enums: generic_cl48RxEEEStates_c 951 */ 952 #define generic_cl48RxEEEStates_c_RX_LINK_FAIL 5 953 #define generic_cl48RxEEEStates_c_RX_WAKE 4 954 #define generic_cl48RxEEEStates_c_RX_QUIET 3 955 #define generic_cl48RxEEEStates_c_RX_DEACT 2 956 #define generic_cl48RxEEEStates_c_RX_SLEEP 1 957 #define generic_cl48RxEEEStates_c_RX_ACTIVE 0 958 959 /**************************************************************************** 960 * Enums: generic_IQP_Options 961 */ 962 #define generic_IQP_Options_i50uA 0 963 #define generic_IQP_Options_i100uA 1 964 #define generic_IQP_Options_i150uA 2 965 #define generic_IQP_Options_i200uA 3 966 #define generic_IQP_Options_i250uA 4 967 #define generic_IQP_Options_i300uA 5 968 #define generic_IQP_Options_i350uA 6 969 #define generic_IQP_Options_i400uA 7 970 #define generic_IQP_Options_i450uA 8 971 #define generic_IQP_Options_i500uA 9 972 #define generic_IQP_Options_i550uA 10 973 #define generic_IQP_Options_i600uA 11 974 #define generic_IQP_Options_i650uA 12 975 #define generic_IQP_Options_i700uA 13 976 #define generic_IQP_Options_i750uA 14 977 #define generic_IQP_Options_i800uA 15 978 979 /**************************************************************************** 980 * Enums: generic_IDriver_Options 981 */ 982 #define generic_IDriver_Options_v680mV 0 983 #define generic_IDriver_Options_v730mV 1 984 #define generic_IDriver_Options_v780mV 2 985 #define generic_IDriver_Options_v830mV 3 986 #define generic_IDriver_Options_v880mV 4 987 #define generic_IDriver_Options_v930mV 5 988 #define generic_IDriver_Options_v980mV 6 989 #define generic_IDriver_Options_v1010mV 7 990 #define generic_IDriver_Options_v1040mV 8 991 #define generic_IDriver_Options_v1060mV 9 992 #define generic_IDriver_Options_v1070mV 10 993 #define generic_IDriver_Options_v1080mV 11 994 #define generic_IDriver_Options_v1085mV 12 995 #define generic_IDriver_Options_v1090mV 13 996 #define generic_IDriver_Options_v1095mV 14 997 #define generic_IDriver_Options_v1100mV 15 998 999 /**************************************************************************** 1000 * Enums: generic_operationModes 1001 */ 1002 #define generic_operationModes_XGXS 0 1003 #define generic_operationModes_XGXG_nCC 1 1004 #define generic_operationModes_Indlane_OS8 4 1005 #define generic_operationModes_IndLane_OS5 5 1006 #define generic_operationModes_PCI 7 1007 #define generic_operationModes_XGXS_nLQ 8 1008 #define generic_operationModes_XGXS_nLQnCC 9 1009 #define generic_operationModes_PBypass 10 1010 #define generic_operationModes_PBypass_nDSK 11 1011 #define generic_operationModes_ComboCoreMode 12 1012 #define generic_operationModes_Clocks_off 15 1013 1014 /**************************************************************************** 1015 * Enums: generic_synce_enum 1016 */ 1017 #define generic_synce_enum_SYNCE_NO_DIV 0 1018 #define generic_synce_enum_SYNCE_DIV_7 1 1019 #define generic_synce_enum_SYNCE_DIV_11 2 1020 1021 /**************************************************************************** 1022 * Enums: generic_operationSpeeds 1023 */ 1024 #define generic_operationSpeeds_SPEED_5G_X1_12p5 65 1025 #define generic_operationSpeeds_SPEED_2p5G_X1_12p5 64 1026 #define generic_operationSpeeds_SPEED_1000M_12p5 63 1027 #define generic_operationSpeeds_SPEED_100M_12p5 62 1028 #define generic_operationSpeeds_SPEED_10M_12p5 61 1029 #define generic_operationSpeeds_SPEED_4G_X1_10 60 1030 #define generic_operationSpeeds_SPEED_1000M_X1_10 59 1031 #define generic_operationSpeeds_SPEED_100M_X1_10 58 1032 #define generic_operationSpeeds_SPEED_10M_X1_10 57 1033 #define generic_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1034 #define generic_operationSpeeds_SPEED_1000M_10p3125 55 1035 #define generic_operationSpeeds_SPEED_100M_10p3125 54 1036 #define generic_operationSpeeds_SPEED_10M_10p3125 53 1037 #define generic_operationSpeeds_SPEED_10p5G_X4 50 1038 #define generic_operationSpeeds_SPEED_5G_KR1 49 1039 #define generic_operationSpeeds_SPEED_127G_X12 39 1040 #define generic_operationSpeeds_SPEED_120G_X12 38 1041 #define generic_operationSpeeds_SPEED_107G_X10 37 1042 #define generic_operationSpeeds_SPEED_100G_CR10 36 1043 #define generic_operationSpeeds_SPEED_42G_X4 35 1044 #define generic_operationSpeeds_SPEED_40G_CR4 34 1045 #define generic_operationSpeeds_SPEED_40G_KR4 33 1046 #define generic_operationSpeeds_SPEED_21G_X2 32 1047 #define generic_operationSpeeds_SPEED_20G_CR2 31 1048 #define generic_operationSpeeds_SPEED_20G_KR2 30 1049 #define generic_operationSpeeds_SPEED_10p6_X1 29 1050 #define generic_operationSpeeds_SPEED_10G_KR1 28 1051 #define generic_operationSpeeds_SPEED_40G_X4 27 1052 #define generic_operationSpeeds_SPEED_20G_X2 26 1053 #define generic_operationSpeeds_SPEED_20G_CX2 25 1054 #define generic_operationSpeeds_SPEED_31p5G_KR4 24 1055 #define generic_operationSpeeds_SPEED_31p5G_X4 23 1056 #define generic_operationSpeeds_SPEED_15p75G_X2 22 1057 #define generic_operationSpeeds_SPEED_25p45G_X4 21 1058 #define generic_operationSpeeds_SPEED_12p7G_X2 20 1059 #define generic_operationSpeeds_SPEED_21G_X4 19 1060 #define generic_operationSpeeds_SPEED_10p5G_X2 18 1061 #define generic_operationSpeeds_SPEED_20G_X4 17 1062 #define generic_operationSpeeds_SPEED_10G_X2 16 1063 #define generic_operationSpeeds_SPEED_10G_CX2 15 1064 #define generic_operationSpeeds_SPEED_20G_CX4 14 1065 #define generic_operationSpeeds_SPEED_16G_X4 13 1066 #define generic_operationSpeeds_SPEED_15G_X4 12 1067 #define generic_operationSpeeds_SPEED_13G_X4 11 1068 #define generic_operationSpeeds_SPEED_10G_X4 10 1069 #define generic_operationSpeeds_SPEED_10G_KX4 9 1070 #define generic_operationSpeeds_SPEED_10G_CX4 8 1071 #define generic_operationSpeeds_SPEED_5G_X1 7 1072 #define generic_operationSpeeds_SPEED_2p5G_X1 6 1073 #define generic_operationSpeeds_SPEED_1G_KX1 5 1074 #define generic_operationSpeeds_SPEED_1G_CX1 4 1075 #define generic_operationSpeeds_SPEED_1000M 3 1076 #define generic_operationSpeeds_SPEED_100M 2 1077 #define generic_operationSpeeds_SPEED_10M 1 1078 1079 /**************************************************************************** 1080 * Enums: generic_actualSpeeds 1081 */ 1082 #define generic_actualSpeeds_dr_10M 0 1083 #define generic_actualSpeeds_dr_100M 1 1084 #define generic_actualSpeeds_dr_1G 2 1085 #define generic_actualSpeeds_dr_2p5G 3 1086 #define generic_actualSpeeds_dr_5G_X4 4 1087 #define generic_actualSpeeds_dr_6G_X4 5 1088 #define generic_actualSpeeds_dr_10G_HiG 6 1089 #define generic_actualSpeeds_dr_10G_CX4 7 1090 #define generic_actualSpeeds_dr_12G_HiG 8 1091 #define generic_actualSpeeds_dr_12p5G_X4 9 1092 #define generic_actualSpeeds_dr_13G_X4 10 1093 #define generic_actualSpeeds_dr_15G_X4 11 1094 #define generic_actualSpeeds_dr_16G_X4 12 1095 #define generic_actualSpeeds_dr_1G_KX 13 1096 #define generic_actualSpeeds_dr_10G_KX4 14 1097 #define generic_actualSpeeds_dr_10G_KR 15 1098 #define generic_actualSpeeds_dr_5G 16 1099 #define generic_actualSpeeds_dr_6p4G 17 1100 #define generic_actualSpeeds_dr_20G_X4 18 1101 #define generic_actualSpeeds_dr_21G_X4 19 1102 #define generic_actualSpeeds_dr_25G_X4 20 1103 #define generic_actualSpeeds_dr_10G_HiG_DXGXS 21 1104 #define generic_actualSpeeds_dr_10G_DXGXS 22 1105 #define generic_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1106 #define generic_actualSpeeds_dr_10p5G_DXGXS 24 1107 #define generic_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1108 #define generic_actualSpeeds_dr_12p773G_DXGXS 26 1109 #define generic_actualSpeeds_dr_10G_XFI 27 1110 #define generic_actualSpeeds_dr_40G 28 1111 #define generic_actualSpeeds_dr_20G_HiG_DXGXS 29 1112 #define generic_actualSpeeds_dr_20G_DXGXS 30 1113 #define generic_actualSpeeds_dr_10G_SFI 31 1114 #define generic_actualSpeeds_dr_31p5G 32 1115 #define generic_actualSpeeds_dr_32p7G 33 1116 #define generic_actualSpeeds_dr_20G_SCR 34 1117 #define generic_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1118 #define generic_actualSpeeds_dr_10G_DXGXS_SCR 36 1119 #define generic_actualSpeeds_dr_12G_R2 37 1120 #define generic_actualSpeeds_dr_10G_X2 38 1121 #define generic_actualSpeeds_dr_40G_KR4 39 1122 #define generic_actualSpeeds_dr_40G_CR4 40 1123 #define generic_actualSpeeds_dr_100G_CR10 41 1124 #define generic_actualSpeeds_dr_15p75G_DXGXS 44 1125 #define generic_actualSpeeds_dr_20G_KR2 57 1126 #define generic_actualSpeeds_dr_20G_CR2 58 1127 1128 /**************************************************************************** 1129 * Enums: generic_actualSpeedsMisc1 1130 */ 1131 #define generic_actualSpeedsMisc1_dr_2500BRCM_X1 16 1132 #define generic_actualSpeedsMisc1_dr_5000BRCM_X4 17 1133 #define generic_actualSpeedsMisc1_dr_6000BRCM_X4 18 1134 #define generic_actualSpeedsMisc1_dr_10GHiGig_X4 19 1135 #define generic_actualSpeedsMisc1_dr_10GBASE_CX4 20 1136 #define generic_actualSpeedsMisc1_dr_12GHiGig_X4 21 1137 #define generic_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1138 #define generic_actualSpeedsMisc1_dr_13GHiGig_X4 23 1139 #define generic_actualSpeedsMisc1_dr_15GHiGig_X4 24 1140 #define generic_actualSpeedsMisc1_dr_16GHiGig_X4 25 1141 #define generic_actualSpeedsMisc1_dr_5000BRCM_X1 26 1142 #define generic_actualSpeedsMisc1_dr_6363BRCM_X1 27 1143 #define generic_actualSpeedsMisc1_dr_20GHiGig_X4 28 1144 #define generic_actualSpeedsMisc1_dr_21GHiGig_X4 29 1145 #define generic_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1146 #define generic_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1147 1148 /**************************************************************************** 1149 * Enums: generic_IndLaneModes 1150 */ 1151 #define generic_IndLaneModes_SWSDR_div2 0 1152 #define generic_IndLaneModes_SWSDR_div1 1 1153 #define generic_IndLaneModes_DWSDR_div2 2 1154 #define generic_IndLaneModes_DWSDR_div1 3 1155 1156 /**************************************************************************** 1157 * Enums: generic_prbsSelect 1158 */ 1159 #define generic_prbsSelect_prbs7 0 1160 #define generic_prbsSelect_prbs15 1 1161 #define generic_prbsSelect_prbs23 2 1162 #define generic_prbsSelect_prbs31 3 1163 1164 /**************************************************************************** 1165 * Enums: generic_vcoDivider 1166 */ 1167 #define generic_vcoDivider_div32 0 1168 #define generic_vcoDivider_div36 1 1169 #define generic_vcoDivider_div40 2 1170 #define generic_vcoDivider_div42 3 1171 #define generic_vcoDivider_div48 4 1172 #define generic_vcoDivider_div50 5 1173 #define generic_vcoDivider_div52 6 1174 #define generic_vcoDivider_div54 7 1175 #define generic_vcoDivider_div60 8 1176 #define generic_vcoDivider_div64 9 1177 #define generic_vcoDivider_div66 10 1178 #define generic_vcoDivider_div68 11 1179 #define generic_vcoDivider_div70 12 1180 #define generic_vcoDivider_div80 13 1181 #define generic_vcoDivider_div92 14 1182 #define generic_vcoDivider_div100 15 1183 1184 /**************************************************************************** 1185 * Enums: generic_refClkSelect 1186 */ 1187 #define generic_refClkSelect_clk_25MHz 0 1188 #define generic_refClkSelect_clk_100MHz 1 1189 #define generic_refClkSelect_clk_125MHz 2 1190 #define generic_refClkSelect_clk_156p25MHz 3 1191 #define generic_refClkSelect_clk_187p5MHz 4 1192 #define generic_refClkSelect_clk_161p25Mhz 5 1193 #define generic_refClkSelect_clk_50Mhz 6 1194 #define generic_refClkSelect_clk_106p25Mhz 7 1195 1196 /**************************************************************************** 1197 * Enums: generic_aerMMDdevTypeSelect 1198 */ 1199 #define generic_aerMMDdevTypeSelect_combo_core 0 1200 #define generic_aerMMDdevTypeSelect_PMA_PMD 1 1201 #define generic_aerMMDdevTypeSelect_PCS 3 1202 #define generic_aerMMDdevTypeSelect_PHY 4 1203 #define generic_aerMMDdevTypeSelect_DTE 5 1204 #define generic_aerMMDdevTypeSelect_CL73_AN 7 1205 1206 /**************************************************************************** 1207 * Enums: generic_aerMMDportSelect 1208 */ 1209 #define generic_aerMMDportSelect_ln0 0 1210 #define generic_aerMMDportSelect_ln1 1 1211 #define generic_aerMMDportSelect_ln2 2 1212 #define generic_aerMMDportSelect_ln3 3 1213 #define generic_aerMMDportSelect_BCST_ln0_1_2_3 511 1214 #define generic_aerMMDportSelect_BCST_ln0_1 512 1215 #define generic_aerMMDportSelect_BCST_ln2_3 513 1216 1217 /**************************************************************************** 1218 * Enums: generic_firmwareModeSelect 1219 */ 1220 #define generic_firmwareModeSelect_DEFAULT 0 1221 #define generic_firmwareModeSelect_SFP_OPT_LR 1 1222 #define generic_firmwareModeSelect_SFP_DAC 2 1223 #define generic_firmwareModeSelect_XLAUI 3 1224 #define generic_firmwareModeSelect_LONG_CH_6G 4 1225 1226 /**************************************************************************** 1227 * Enums: generic_tempIdxSelect 1228 */ 1229 #define generic_tempIdxSelect_LTE__22p9C 15 1230 #define generic_tempIdxSelect_LTE__12p6C 14 1231 #define generic_tempIdxSelect_LTE__3p0C 13 1232 #define generic_tempIdxSelect_LTE_6p7C 12 1233 #define generic_tempIdxSelect_LTE_16p4C 11 1234 #define generic_tempIdxSelect_LTE_26p6C 10 1235 #define generic_tempIdxSelect_LTE_36p3C 9 1236 #define generic_tempIdxSelect_LTE_46p0C 8 1237 #define generic_tempIdxSelect_LTE_56p2C 7 1238 #define generic_tempIdxSelect_LTE_65p9C 6 1239 #define generic_tempIdxSelect_LTE_75p6C 5 1240 #define generic_tempIdxSelect_LTE_85p3C 4 1241 #define generic_tempIdxSelect_LTE_95p5C 3 1242 #define generic_tempIdxSelect_LTE_105p2C 2 1243 #define generic_tempIdxSelect_LTE_114p9C 1 1244 #define generic_tempIdxSelect_LTE_125p1C 0 1245 1246 /**************************************************************************** 1247 * Enums: main0_cl36TxEEEStates_l 1248 */ 1249 #define main0_cl36TxEEEStates_l_TX_REFRESH 8 1250 #define main0_cl36TxEEEStates_l_TX_QUIET 4 1251 #define main0_cl36TxEEEStates_l_TX_SLEEP 2 1252 #define main0_cl36TxEEEStates_l_TX_ACTIVE 1 1253 1254 /**************************************************************************** 1255 * Enums: main0_cl36TxEEEStates_c 1256 */ 1257 #define main0_cl36TxEEEStates_c_TX_REFRESH 3 1258 #define main0_cl36TxEEEStates_c_TX_QUIET 2 1259 #define main0_cl36TxEEEStates_c_TX_SLEEP 1 1260 #define main0_cl36TxEEEStates_c_TX_ACTIVE 0 1261 1262 /**************************************************************************** 1263 * Enums: main0_cl49TxEEEStates_l 1264 */ 1265 #define main0_cl49TxEEEStates_l_SCR_RESET_2 64 1266 #define main0_cl49TxEEEStates_l_SCR_RESET_1 32 1267 #define main0_cl49TxEEEStates_l_TX_WAKE 16 1268 #define main0_cl49TxEEEStates_l_TX_REFRESH 8 1269 #define main0_cl49TxEEEStates_l_TX_QUIET 4 1270 #define main0_cl49TxEEEStates_l_TX_SLEEP 2 1271 #define main0_cl49TxEEEStates_l_TX_ACTIVE 1 1272 1273 /**************************************************************************** 1274 * Enums: main0_cl49TxEEEStates_c 1275 */ 1276 #define main0_cl49TxEEEStates_c_SCR_RESET_2 6 1277 #define main0_cl49TxEEEStates_c_SCR_RESET_1 5 1278 #define main0_cl49TxEEEStates_c_TX_WAKE 4 1279 #define main0_cl49TxEEEStates_c_TX_REFRESH 3 1280 #define main0_cl49TxEEEStates_c_TX_QUIET 2 1281 #define main0_cl49TxEEEStates_c_TX_SLEEP 1 1282 #define main0_cl49TxEEEStates_c_TX_ACTIVE 0 1283 1284 /**************************************************************************** 1285 * Enums: main0_cl36RxEEEStates_l 1286 */ 1287 #define main0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1288 #define main0_cl36RxEEEStates_l_RX_WTF 16 1289 #define main0_cl36RxEEEStates_l_RX_WAKE 8 1290 #define main0_cl36RxEEEStates_l_RX_QUIET 4 1291 #define main0_cl36RxEEEStates_l_RX_SLEEP 2 1292 #define main0_cl36RxEEEStates_l_RX_ACTIVE 1 1293 1294 /**************************************************************************** 1295 * Enums: main0_cl36RxEEEStates_c 1296 */ 1297 #define main0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1298 #define main0_cl36RxEEEStates_c_RX_WTF 4 1299 #define main0_cl36RxEEEStates_c_RX_WAKE 3 1300 #define main0_cl36RxEEEStates_c_RX_QUIET 2 1301 #define main0_cl36RxEEEStates_c_RX_SLEEP 1 1302 #define main0_cl36RxEEEStates_c_RX_ACTIVE 0 1303 1304 /**************************************************************************** 1305 * Enums: main0_cl49RxEEEStates_l 1306 */ 1307 #define main0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1308 #define main0_cl49RxEEEStates_l_RX_WTF 16 1309 #define main0_cl49RxEEEStates_l_RX_WAKE 8 1310 #define main0_cl49RxEEEStates_l_RX_QUIET 4 1311 #define main0_cl49RxEEEStates_l_RX_SLEEP 2 1312 #define main0_cl49RxEEEStates_l_RX_ACTIVE 1 1313 1314 /**************************************************************************** 1315 * Enums: main0_cl49RxEEEStates_c 1316 */ 1317 #define main0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1318 #define main0_cl49RxEEEStates_c_RX_WTF 4 1319 #define main0_cl49RxEEEStates_c_RX_WAKE 3 1320 #define main0_cl49RxEEEStates_c_RX_QUIET 2 1321 #define main0_cl49RxEEEStates_c_RX_SLEEP 1 1322 #define main0_cl49RxEEEStates_c_RX_ACTIVE 0 1323 1324 /**************************************************************************** 1325 * Enums: main0_cl48TxEEEStates_l 1326 */ 1327 #define main0_cl48TxEEEStates_l_TX_REFRESH 8 1328 #define main0_cl48TxEEEStates_l_TX_QUIET 4 1329 #define main0_cl48TxEEEStates_l_TX_SLEEP 2 1330 #define main0_cl48TxEEEStates_l_TX_ACTIVE 1 1331 1332 /**************************************************************************** 1333 * Enums: main0_cl48TxEEEStates_c 1334 */ 1335 #define main0_cl48TxEEEStates_c_TX_REFRESH 3 1336 #define main0_cl48TxEEEStates_c_TX_QUIET 2 1337 #define main0_cl48TxEEEStates_c_TX_SLEEP 1 1338 #define main0_cl48TxEEEStates_c_TX_ACTIVE 0 1339 1340 /**************************************************************************** 1341 * Enums: main0_cl48RxEEEStates_l 1342 */ 1343 #define main0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1344 #define main0_cl48RxEEEStates_l_RX_WAKE 16 1345 #define main0_cl48RxEEEStates_l_RX_QUIET 8 1346 #define main0_cl48RxEEEStates_l_RX_DEACT 4 1347 #define main0_cl48RxEEEStates_l_RX_SLEEP 2 1348 #define main0_cl48RxEEEStates_l_RX_ACTIVE 1 1349 1350 /**************************************************************************** 1351 * Enums: main0_cl48RxEEEStates_c 1352 */ 1353 #define main0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1354 #define main0_cl48RxEEEStates_c_RX_WAKE 4 1355 #define main0_cl48RxEEEStates_c_RX_QUIET 3 1356 #define main0_cl48RxEEEStates_c_RX_DEACT 2 1357 #define main0_cl48RxEEEStates_c_RX_SLEEP 1 1358 #define main0_cl48RxEEEStates_c_RX_ACTIVE 0 1359 1360 /**************************************************************************** 1361 * Enums: main0_IQP_Options 1362 */ 1363 #define main0_IQP_Options_i50uA 0 1364 #define main0_IQP_Options_i100uA 1 1365 #define main0_IQP_Options_i150uA 2 1366 #define main0_IQP_Options_i200uA 3 1367 #define main0_IQP_Options_i250uA 4 1368 #define main0_IQP_Options_i300uA 5 1369 #define main0_IQP_Options_i350uA 6 1370 #define main0_IQP_Options_i400uA 7 1371 #define main0_IQP_Options_i450uA 8 1372 #define main0_IQP_Options_i500uA 9 1373 #define main0_IQP_Options_i550uA 10 1374 #define main0_IQP_Options_i600uA 11 1375 #define main0_IQP_Options_i650uA 12 1376 #define main0_IQP_Options_i700uA 13 1377 #define main0_IQP_Options_i750uA 14 1378 #define main0_IQP_Options_i800uA 15 1379 1380 /**************************************************************************** 1381 * Enums: main0_IDriver_Options 1382 */ 1383 #define main0_IDriver_Options_v680mV 0 1384 #define main0_IDriver_Options_v730mV 1 1385 #define main0_IDriver_Options_v780mV 2 1386 #define main0_IDriver_Options_v830mV 3 1387 #define main0_IDriver_Options_v880mV 4 1388 #define main0_IDriver_Options_v930mV 5 1389 #define main0_IDriver_Options_v980mV 6 1390 #define main0_IDriver_Options_v1010mV 7 1391 #define main0_IDriver_Options_v1040mV 8 1392 #define main0_IDriver_Options_v1060mV 9 1393 #define main0_IDriver_Options_v1070mV 10 1394 #define main0_IDriver_Options_v1080mV 11 1395 #define main0_IDriver_Options_v1085mV 12 1396 #define main0_IDriver_Options_v1090mV 13 1397 #define main0_IDriver_Options_v1095mV 14 1398 #define main0_IDriver_Options_v1100mV 15 1399 1400 /**************************************************************************** 1401 * Enums: main0_operationModes 1402 */ 1403 #define main0_operationModes_XGXS 0 1404 #define main0_operationModes_XGXG_nCC 1 1405 #define main0_operationModes_Indlane_OS8 4 1406 #define main0_operationModes_IndLane_OS5 5 1407 #define main0_operationModes_PCI 7 1408 #define main0_operationModes_XGXS_nLQ 8 1409 #define main0_operationModes_XGXS_nLQnCC 9 1410 #define main0_operationModes_PBypass 10 1411 #define main0_operationModes_PBypass_nDSK 11 1412 #define main0_operationModes_ComboCoreMode 12 1413 #define main0_operationModes_Clocks_off 15 1414 1415 /**************************************************************************** 1416 * Enums: main0_synce_enum 1417 */ 1418 #define main0_synce_enum_SYNCE_NO_DIV 0 1419 #define main0_synce_enum_SYNCE_DIV_7 1 1420 #define main0_synce_enum_SYNCE_DIV_11 2 1421 1422 /**************************************************************************** 1423 * Enums: main0_operationSpeeds 1424 */ 1425 #define main0_operationSpeeds_SPEED_5G_X1_12p5 65 1426 #define main0_operationSpeeds_SPEED_2p5G_X1_12p5 64 1427 #define main0_operationSpeeds_SPEED_1000M_12p5 63 1428 #define main0_operationSpeeds_SPEED_100M_12p5 62 1429 #define main0_operationSpeeds_SPEED_10M_12p5 61 1430 #define main0_operationSpeeds_SPEED_4G_X1_10 60 1431 #define main0_operationSpeeds_SPEED_1000M_X1_10 59 1432 #define main0_operationSpeeds_SPEED_100M_X1_10 58 1433 #define main0_operationSpeeds_SPEED_10M_X1_10 57 1434 #define main0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1435 #define main0_operationSpeeds_SPEED_1000M_10p3125 55 1436 #define main0_operationSpeeds_SPEED_100M_10p3125 54 1437 #define main0_operationSpeeds_SPEED_10M_10p3125 53 1438 #define main0_operationSpeeds_SPEED_10p5G_X4 50 1439 #define main0_operationSpeeds_SPEED_5G_KR1 49 1440 #define main0_operationSpeeds_SPEED_127G_X12 39 1441 #define main0_operationSpeeds_SPEED_120G_X12 38 1442 #define main0_operationSpeeds_SPEED_107G_X10 37 1443 #define main0_operationSpeeds_SPEED_100G_CR10 36 1444 #define main0_operationSpeeds_SPEED_42G_X4 35 1445 #define main0_operationSpeeds_SPEED_40G_CR4 34 1446 #define main0_operationSpeeds_SPEED_40G_KR4 33 1447 #define main0_operationSpeeds_SPEED_21G_X2 32 1448 #define main0_operationSpeeds_SPEED_20G_CR2 31 1449 #define main0_operationSpeeds_SPEED_20G_KR2 30 1450 #define main0_operationSpeeds_SPEED_10p6_X1 29 1451 #define main0_operationSpeeds_SPEED_10G_KR1 28 1452 #define main0_operationSpeeds_SPEED_40G_X4 27 1453 #define main0_operationSpeeds_SPEED_20G_X2 26 1454 #define main0_operationSpeeds_SPEED_20G_CX2 25 1455 #define main0_operationSpeeds_SPEED_31p5G_KR4 24 1456 #define main0_operationSpeeds_SPEED_31p5G_X4 23 1457 #define main0_operationSpeeds_SPEED_15p75G_X2 22 1458 #define main0_operationSpeeds_SPEED_25p45G_X4 21 1459 #define main0_operationSpeeds_SPEED_12p7G_X2 20 1460 #define main0_operationSpeeds_SPEED_21G_X4 19 1461 #define main0_operationSpeeds_SPEED_10p5G_X2 18 1462 #define main0_operationSpeeds_SPEED_20G_X4 17 1463 #define main0_operationSpeeds_SPEED_10G_X2 16 1464 #define main0_operationSpeeds_SPEED_10G_CX2 15 1465 #define main0_operationSpeeds_SPEED_20G_CX4 14 1466 #define main0_operationSpeeds_SPEED_16G_X4 13 1467 #define main0_operationSpeeds_SPEED_15G_X4 12 1468 #define main0_operationSpeeds_SPEED_13G_X4 11 1469 #define main0_operationSpeeds_SPEED_10G_X4 10 1470 #define main0_operationSpeeds_SPEED_10G_KX4 9 1471 #define main0_operationSpeeds_SPEED_10G_CX4 8 1472 #define main0_operationSpeeds_SPEED_5G_X1 7 1473 #define main0_operationSpeeds_SPEED_2p5G_X1 6 1474 #define main0_operationSpeeds_SPEED_1G_KX1 5 1475 #define main0_operationSpeeds_SPEED_1G_CX1 4 1476 #define main0_operationSpeeds_SPEED_1000M 3 1477 #define main0_operationSpeeds_SPEED_100M 2 1478 #define main0_operationSpeeds_SPEED_10M 1 1479 1480 /**************************************************************************** 1481 * Enums: main0_actualSpeeds 1482 */ 1483 #define main0_actualSpeeds_dr_10M 0 1484 #define main0_actualSpeeds_dr_100M 1 1485 #define main0_actualSpeeds_dr_1G 2 1486 #define main0_actualSpeeds_dr_2p5G 3 1487 #define main0_actualSpeeds_dr_5G_X4 4 1488 #define main0_actualSpeeds_dr_6G_X4 5 1489 #define main0_actualSpeeds_dr_10G_HiG 6 1490 #define main0_actualSpeeds_dr_10G_CX4 7 1491 #define main0_actualSpeeds_dr_12G_HiG 8 1492 #define main0_actualSpeeds_dr_12p5G_X4 9 1493 #define main0_actualSpeeds_dr_13G_X4 10 1494 #define main0_actualSpeeds_dr_15G_X4 11 1495 #define main0_actualSpeeds_dr_16G_X4 12 1496 #define main0_actualSpeeds_dr_1G_KX 13 1497 #define main0_actualSpeeds_dr_10G_KX4 14 1498 #define main0_actualSpeeds_dr_10G_KR 15 1499 #define main0_actualSpeeds_dr_5G 16 1500 #define main0_actualSpeeds_dr_6p4G 17 1501 #define main0_actualSpeeds_dr_20G_X4 18 1502 #define main0_actualSpeeds_dr_21G_X4 19 1503 #define main0_actualSpeeds_dr_25G_X4 20 1504 #define main0_actualSpeeds_dr_10G_HiG_DXGXS 21 1505 #define main0_actualSpeeds_dr_10G_DXGXS 22 1506 #define main0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1507 #define main0_actualSpeeds_dr_10p5G_DXGXS 24 1508 #define main0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1509 #define main0_actualSpeeds_dr_12p773G_DXGXS 26 1510 #define main0_actualSpeeds_dr_10G_XFI 27 1511 #define main0_actualSpeeds_dr_40G 28 1512 #define main0_actualSpeeds_dr_20G_HiG_DXGXS 29 1513 #define main0_actualSpeeds_dr_20G_DXGXS 30 1514 #define main0_actualSpeeds_dr_10G_SFI 31 1515 #define main0_actualSpeeds_dr_31p5G 32 1516 #define main0_actualSpeeds_dr_32p7G 33 1517 #define main0_actualSpeeds_dr_20G_SCR 34 1518 #define main0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1519 #define main0_actualSpeeds_dr_10G_DXGXS_SCR 36 1520 #define main0_actualSpeeds_dr_12G_R2 37 1521 #define main0_actualSpeeds_dr_10G_X2 38 1522 #define main0_actualSpeeds_dr_40G_KR4 39 1523 #define main0_actualSpeeds_dr_40G_CR4 40 1524 #define main0_actualSpeeds_dr_100G_CR10 41 1525 #define main0_actualSpeeds_dr_15p75G_DXGXS 44 1526 #define main0_actualSpeeds_dr_20G_KR2 57 1527 #define main0_actualSpeeds_dr_20G_CR2 58 1528 1529 /**************************************************************************** 1530 * Enums: main0_actualSpeedsMisc1 1531 */ 1532 #define main0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1533 #define main0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1534 #define main0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1535 #define main0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1536 #define main0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1537 #define main0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1538 #define main0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1539 #define main0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1540 #define main0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1541 #define main0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1542 #define main0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1543 #define main0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1544 #define main0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1545 #define main0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1546 #define main0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1547 #define main0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1548 1549 /**************************************************************************** 1550 * Enums: main0_IndLaneModes 1551 */ 1552 #define main0_IndLaneModes_SWSDR_div2 0 1553 #define main0_IndLaneModes_SWSDR_div1 1 1554 #define main0_IndLaneModes_DWSDR_div2 2 1555 #define main0_IndLaneModes_DWSDR_div1 3 1556 1557 /**************************************************************************** 1558 * Enums: main0_prbsSelect 1559 */ 1560 #define main0_prbsSelect_prbs7 0 1561 #define main0_prbsSelect_prbs15 1 1562 #define main0_prbsSelect_prbs23 2 1563 #define main0_prbsSelect_prbs31 3 1564 1565 /**************************************************************************** 1566 * Enums: main0_vcoDivider 1567 */ 1568 #define main0_vcoDivider_div32 0 1569 #define main0_vcoDivider_div36 1 1570 #define main0_vcoDivider_div40 2 1571 #define main0_vcoDivider_div42 3 1572 #define main0_vcoDivider_div48 4 1573 #define main0_vcoDivider_div50 5 1574 #define main0_vcoDivider_div52 6 1575 #define main0_vcoDivider_div54 7 1576 #define main0_vcoDivider_div60 8 1577 #define main0_vcoDivider_div64 9 1578 #define main0_vcoDivider_div66 10 1579 #define main0_vcoDivider_div68 11 1580 #define main0_vcoDivider_div70 12 1581 #define main0_vcoDivider_div80 13 1582 #define main0_vcoDivider_div92 14 1583 #define main0_vcoDivider_div100 15 1584 1585 /**************************************************************************** 1586 * Enums: main0_refClkSelect 1587 */ 1588 #define main0_refClkSelect_clk_25MHz 0 1589 #define main0_refClkSelect_clk_100MHz 1 1590 #define main0_refClkSelect_clk_125MHz 2 1591 #define main0_refClkSelect_clk_156p25MHz 3 1592 #define main0_refClkSelect_clk_187p5MHz 4 1593 #define main0_refClkSelect_clk_161p25Mhz 5 1594 #define main0_refClkSelect_clk_50Mhz 6 1595 #define main0_refClkSelect_clk_106p25Mhz 7 1596 1597 /**************************************************************************** 1598 * Enums: main0_aerMMDdevTypeSelect 1599 */ 1600 #define main0_aerMMDdevTypeSelect_combo_core 0 1601 #define main0_aerMMDdevTypeSelect_PMA_PMD 1 1602 #define main0_aerMMDdevTypeSelect_PCS 3 1603 #define main0_aerMMDdevTypeSelect_PHY 4 1604 #define main0_aerMMDdevTypeSelect_DTE 5 1605 #define main0_aerMMDdevTypeSelect_CL73_AN 7 1606 1607 /**************************************************************************** 1608 * Enums: main0_aerMMDportSelect 1609 */ 1610 #define main0_aerMMDportSelect_ln0 0 1611 #define main0_aerMMDportSelect_ln1 1 1612 #define main0_aerMMDportSelect_ln2 2 1613 #define main0_aerMMDportSelect_ln3 3 1614 #define main0_aerMMDportSelect_BCST_ln0_1_2_3 511 1615 #define main0_aerMMDportSelect_BCST_ln0_1 512 1616 #define main0_aerMMDportSelect_BCST_ln2_3 513 1617 1618 /**************************************************************************** 1619 * Enums: main0_firmwareModeSelect 1620 */ 1621 #define main0_firmwareModeSelect_DEFAULT 0 1622 #define main0_firmwareModeSelect_SFP_OPT_LR 1 1623 #define main0_firmwareModeSelect_SFP_DAC 2 1624 #define main0_firmwareModeSelect_XLAUI 3 1625 #define main0_firmwareModeSelect_LONG_CH_6G 4 1626 1627 /**************************************************************************** 1628 * Enums: main0_tempIdxSelect 1629 */ 1630 #define main0_tempIdxSelect_LTE__22p9C 15 1631 #define main0_tempIdxSelect_LTE__12p6C 14 1632 #define main0_tempIdxSelect_LTE__3p0C 13 1633 #define main0_tempIdxSelect_LTE_6p7C 12 1634 #define main0_tempIdxSelect_LTE_16p4C 11 1635 #define main0_tempIdxSelect_LTE_26p6C 10 1636 #define main0_tempIdxSelect_LTE_36p3C 9 1637 #define main0_tempIdxSelect_LTE_46p0C 8 1638 #define main0_tempIdxSelect_LTE_56p2C 7 1639 #define main0_tempIdxSelect_LTE_65p9C 6 1640 #define main0_tempIdxSelect_LTE_75p6C 5 1641 #define main0_tempIdxSelect_LTE_85p3C 4 1642 #define main0_tempIdxSelect_LTE_95p5C 3 1643 #define main0_tempIdxSelect_LTE_105p2C 2 1644 #define main0_tempIdxSelect_LTE_114p9C 1 1645 #define main0_tempIdxSelect_LTE_125p1C 0 1646 1647 /**************************************************************************** 1648 * Enums: sc_x1_speed_override0_cl36TxEEEStates_l 1649 */ 1650 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_REFRESH 8 1651 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_QUIET 4 1652 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_SLEEP 2 1653 #define sc_x1_speed_override0_cl36TxEEEStates_l_TX_ACTIVE 1 1654 1655 /**************************************************************************** 1656 * Enums: sc_x1_speed_override0_cl36TxEEEStates_c 1657 */ 1658 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_REFRESH 3 1659 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_QUIET 2 1660 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_SLEEP 1 1661 #define sc_x1_speed_override0_cl36TxEEEStates_c_TX_ACTIVE 0 1662 1663 /**************************************************************************** 1664 * Enums: sc_x1_speed_override0_cl49TxEEEStates_l 1665 */ 1666 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_2 64 1667 #define sc_x1_speed_override0_cl49TxEEEStates_l_SCR_RESET_1 32 1668 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_WAKE 16 1669 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_REFRESH 8 1670 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_QUIET 4 1671 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_SLEEP 2 1672 #define sc_x1_speed_override0_cl49TxEEEStates_l_TX_ACTIVE 1 1673 1674 /**************************************************************************** 1675 * Enums: sc_x1_speed_override0_cl49TxEEEStates_c 1676 */ 1677 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_2 6 1678 #define sc_x1_speed_override0_cl49TxEEEStates_c_SCR_RESET_1 5 1679 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_WAKE 4 1680 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_REFRESH 3 1681 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_QUIET 2 1682 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_SLEEP 1 1683 #define sc_x1_speed_override0_cl49TxEEEStates_c_TX_ACTIVE 0 1684 1685 /**************************************************************************** 1686 * Enums: sc_x1_speed_override0_cl36RxEEEStates_l 1687 */ 1688 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_LINK_FAIL 32 1689 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WTF 16 1690 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_WAKE 8 1691 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_QUIET 4 1692 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_SLEEP 2 1693 #define sc_x1_speed_override0_cl36RxEEEStates_l_RX_ACTIVE 1 1694 1695 /**************************************************************************** 1696 * Enums: sc_x1_speed_override0_cl36RxEEEStates_c 1697 */ 1698 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_LINK_FAIL 5 1699 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WTF 4 1700 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_WAKE 3 1701 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_QUIET 2 1702 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_SLEEP 1 1703 #define sc_x1_speed_override0_cl36RxEEEStates_c_RX_ACTIVE 0 1704 1705 /**************************************************************************** 1706 * Enums: sc_x1_speed_override0_cl49RxEEEStates_l 1707 */ 1708 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_LINK_FAIL 32 1709 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WTF 16 1710 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_WAKE 8 1711 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_QUIET 4 1712 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_SLEEP 2 1713 #define sc_x1_speed_override0_cl49RxEEEStates_l_RX_ACTIVE 1 1714 1715 /**************************************************************************** 1716 * Enums: sc_x1_speed_override0_cl49RxEEEStates_c 1717 */ 1718 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_LINK_FAIL 5 1719 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WTF 4 1720 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_WAKE 3 1721 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_QUIET 2 1722 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_SLEEP 1 1723 #define sc_x1_speed_override0_cl49RxEEEStates_c_RX_ACTIVE 0 1724 1725 /**************************************************************************** 1726 * Enums: sc_x1_speed_override0_cl48TxEEEStates_l 1727 */ 1728 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_REFRESH 8 1729 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_QUIET 4 1730 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_SLEEP 2 1731 #define sc_x1_speed_override0_cl48TxEEEStates_l_TX_ACTIVE 1 1732 1733 /**************************************************************************** 1734 * Enums: sc_x1_speed_override0_cl48TxEEEStates_c 1735 */ 1736 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_REFRESH 3 1737 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_QUIET 2 1738 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_SLEEP 1 1739 #define sc_x1_speed_override0_cl48TxEEEStates_c_TX_ACTIVE 0 1740 1741 /**************************************************************************** 1742 * Enums: sc_x1_speed_override0_cl48RxEEEStates_l 1743 */ 1744 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_LINK_FAIL 32 1745 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_WAKE 16 1746 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_QUIET 8 1747 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_DEACT 4 1748 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_SLEEP 2 1749 #define sc_x1_speed_override0_cl48RxEEEStates_l_RX_ACTIVE 1 1750 1751 /**************************************************************************** 1752 * Enums: sc_x1_speed_override0_cl48RxEEEStates_c 1753 */ 1754 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_LINK_FAIL 5 1755 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_WAKE 4 1756 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_QUIET 3 1757 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_DEACT 2 1758 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_SLEEP 1 1759 #define sc_x1_speed_override0_cl48RxEEEStates_c_RX_ACTIVE 0 1760 1761 /**************************************************************************** 1762 * Enums: sc_x1_speed_override0_IQP_Options 1763 */ 1764 #define sc_x1_speed_override0_IQP_Options_i50uA 0 1765 #define sc_x1_speed_override0_IQP_Options_i100uA 1 1766 #define sc_x1_speed_override0_IQP_Options_i150uA 2 1767 #define sc_x1_speed_override0_IQP_Options_i200uA 3 1768 #define sc_x1_speed_override0_IQP_Options_i250uA 4 1769 #define sc_x1_speed_override0_IQP_Options_i300uA 5 1770 #define sc_x1_speed_override0_IQP_Options_i350uA 6 1771 #define sc_x1_speed_override0_IQP_Options_i400uA 7 1772 #define sc_x1_speed_override0_IQP_Options_i450uA 8 1773 #define sc_x1_speed_override0_IQP_Options_i500uA 9 1774 #define sc_x1_speed_override0_IQP_Options_i550uA 10 1775 #define sc_x1_speed_override0_IQP_Options_i600uA 11 1776 #define sc_x1_speed_override0_IQP_Options_i650uA 12 1777 #define sc_x1_speed_override0_IQP_Options_i700uA 13 1778 #define sc_x1_speed_override0_IQP_Options_i750uA 14 1779 #define sc_x1_speed_override0_IQP_Options_i800uA 15 1780 1781 /**************************************************************************** 1782 * Enums: sc_x1_speed_override0_IDriver_Options 1783 */ 1784 #define sc_x1_speed_override0_IDriver_Options_v680mV 0 1785 #define sc_x1_speed_override0_IDriver_Options_v730mV 1 1786 #define sc_x1_speed_override0_IDriver_Options_v780mV 2 1787 #define sc_x1_speed_override0_IDriver_Options_v830mV 3 1788 #define sc_x1_speed_override0_IDriver_Options_v880mV 4 1789 #define sc_x1_speed_override0_IDriver_Options_v930mV 5 1790 #define sc_x1_speed_override0_IDriver_Options_v980mV 6 1791 #define sc_x1_speed_override0_IDriver_Options_v1010mV 7 1792 #define sc_x1_speed_override0_IDriver_Options_v1040mV 8 1793 #define sc_x1_speed_override0_IDriver_Options_v1060mV 9 1794 #define sc_x1_speed_override0_IDriver_Options_v1070mV 10 1795 #define sc_x1_speed_override0_IDriver_Options_v1080mV 11 1796 #define sc_x1_speed_override0_IDriver_Options_v1085mV 12 1797 #define sc_x1_speed_override0_IDriver_Options_v1090mV 13 1798 #define sc_x1_speed_override0_IDriver_Options_v1095mV 14 1799 #define sc_x1_speed_override0_IDriver_Options_v1100mV 15 1800 1801 /**************************************************************************** 1802 * Enums: sc_x1_speed_override0_operationModes 1803 */ 1804 #define sc_x1_speed_override0_operationModes_XGXS 0 1805 #define sc_x1_speed_override0_operationModes_XGXG_nCC 1 1806 #define sc_x1_speed_override0_operationModes_Indlane_OS8 4 1807 #define sc_x1_speed_override0_operationModes_IndLane_OS5 5 1808 #define sc_x1_speed_override0_operationModes_PCI 7 1809 #define sc_x1_speed_override0_operationModes_XGXS_nLQ 8 1810 #define sc_x1_speed_override0_operationModes_XGXS_nLQnCC 9 1811 #define sc_x1_speed_override0_operationModes_PBypass 10 1812 #define sc_x1_speed_override0_operationModes_PBypass_nDSK 11 1813 #define sc_x1_speed_override0_operationModes_ComboCoreMode 12 1814 #define sc_x1_speed_override0_operationModes_Clocks_off 15 1815 1816 /**************************************************************************** 1817 * Enums: sc_x1_speed_override0_synce_enum 1818 */ 1819 #define sc_x1_speed_override0_synce_enum_SYNCE_NO_DIV 0 1820 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_7 1 1821 #define sc_x1_speed_override0_synce_enum_SYNCE_DIV_11 2 1822 1823 /**************************************************************************** 1824 * Enums: sc_x1_speed_override0_operationSpeeds 1825 */ 1826 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1_12p5 65 1827 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_12p5 64 1828 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_12p5 63 1829 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_12p5 62 1830 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_12p5 61 1831 #define sc_x1_speed_override0_operationSpeeds_SPEED_4G_X1_10 60 1832 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_X1_10 59 1833 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_X1_10 58 1834 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_X1_10 57 1835 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 1836 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M_10p3125 55 1837 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M_10p3125 54 1838 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M_10p3125 53 1839 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X4 50 1840 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_KR1 49 1841 #define sc_x1_speed_override0_operationSpeeds_SPEED_127G_X12 39 1842 #define sc_x1_speed_override0_operationSpeeds_SPEED_120G_X12 38 1843 #define sc_x1_speed_override0_operationSpeeds_SPEED_107G_X10 37 1844 #define sc_x1_speed_override0_operationSpeeds_SPEED_100G_CR10 36 1845 #define sc_x1_speed_override0_operationSpeeds_SPEED_42G_X4 35 1846 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_CR4 34 1847 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_KR4 33 1848 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X2 32 1849 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CR2 31 1850 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_KR2 30 1851 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p6_X1 29 1852 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KR1 28 1853 #define sc_x1_speed_override0_operationSpeeds_SPEED_40G_X4 27 1854 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X2 26 1855 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX2 25 1856 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_KR4 24 1857 #define sc_x1_speed_override0_operationSpeeds_SPEED_31p5G_X4 23 1858 #define sc_x1_speed_override0_operationSpeeds_SPEED_15p75G_X2 22 1859 #define sc_x1_speed_override0_operationSpeeds_SPEED_25p45G_X4 21 1860 #define sc_x1_speed_override0_operationSpeeds_SPEED_12p7G_X2 20 1861 #define sc_x1_speed_override0_operationSpeeds_SPEED_21G_X4 19 1862 #define sc_x1_speed_override0_operationSpeeds_SPEED_10p5G_X2 18 1863 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_X4 17 1864 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X2 16 1865 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX2 15 1866 #define sc_x1_speed_override0_operationSpeeds_SPEED_20G_CX4 14 1867 #define sc_x1_speed_override0_operationSpeeds_SPEED_16G_X4 13 1868 #define sc_x1_speed_override0_operationSpeeds_SPEED_15G_X4 12 1869 #define sc_x1_speed_override0_operationSpeeds_SPEED_13G_X4 11 1870 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_X4 10 1871 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_KX4 9 1872 #define sc_x1_speed_override0_operationSpeeds_SPEED_10G_CX4 8 1873 #define sc_x1_speed_override0_operationSpeeds_SPEED_5G_X1 7 1874 #define sc_x1_speed_override0_operationSpeeds_SPEED_2p5G_X1 6 1875 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_KX1 5 1876 #define sc_x1_speed_override0_operationSpeeds_SPEED_1G_CX1 4 1877 #define sc_x1_speed_override0_operationSpeeds_SPEED_1000M 3 1878 #define sc_x1_speed_override0_operationSpeeds_SPEED_100M 2 1879 #define sc_x1_speed_override0_operationSpeeds_SPEED_10M 1 1880 1881 /**************************************************************************** 1882 * Enums: sc_x1_speed_override0_actualSpeeds 1883 */ 1884 #define sc_x1_speed_override0_actualSpeeds_dr_10M 0 1885 #define sc_x1_speed_override0_actualSpeeds_dr_100M 1 1886 #define sc_x1_speed_override0_actualSpeeds_dr_1G 2 1887 #define sc_x1_speed_override0_actualSpeeds_dr_2p5G 3 1888 #define sc_x1_speed_override0_actualSpeeds_dr_5G_X4 4 1889 #define sc_x1_speed_override0_actualSpeeds_dr_6G_X4 5 1890 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG 6 1891 #define sc_x1_speed_override0_actualSpeeds_dr_10G_CX4 7 1892 #define sc_x1_speed_override0_actualSpeeds_dr_12G_HiG 8 1893 #define sc_x1_speed_override0_actualSpeeds_dr_12p5G_X4 9 1894 #define sc_x1_speed_override0_actualSpeeds_dr_13G_X4 10 1895 #define sc_x1_speed_override0_actualSpeeds_dr_15G_X4 11 1896 #define sc_x1_speed_override0_actualSpeeds_dr_16G_X4 12 1897 #define sc_x1_speed_override0_actualSpeeds_dr_1G_KX 13 1898 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KX4 14 1899 #define sc_x1_speed_override0_actualSpeeds_dr_10G_KR 15 1900 #define sc_x1_speed_override0_actualSpeeds_dr_5G 16 1901 #define sc_x1_speed_override0_actualSpeeds_dr_6p4G 17 1902 #define sc_x1_speed_override0_actualSpeeds_dr_20G_X4 18 1903 #define sc_x1_speed_override0_actualSpeeds_dr_21G_X4 19 1904 #define sc_x1_speed_override0_actualSpeeds_dr_25G_X4 20 1905 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS 21 1906 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS 22 1907 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 1908 #define sc_x1_speed_override0_actualSpeeds_dr_10p5G_DXGXS 24 1909 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 1910 #define sc_x1_speed_override0_actualSpeeds_dr_12p773G_DXGXS 26 1911 #define sc_x1_speed_override0_actualSpeeds_dr_10G_XFI 27 1912 #define sc_x1_speed_override0_actualSpeeds_dr_40G 28 1913 #define sc_x1_speed_override0_actualSpeeds_dr_20G_HiG_DXGXS 29 1914 #define sc_x1_speed_override0_actualSpeeds_dr_20G_DXGXS 30 1915 #define sc_x1_speed_override0_actualSpeeds_dr_10G_SFI 31 1916 #define sc_x1_speed_override0_actualSpeeds_dr_31p5G 32 1917 #define sc_x1_speed_override0_actualSpeeds_dr_32p7G 33 1918 #define sc_x1_speed_override0_actualSpeeds_dr_20G_SCR 34 1919 #define sc_x1_speed_override0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 1920 #define sc_x1_speed_override0_actualSpeeds_dr_10G_DXGXS_SCR 36 1921 #define sc_x1_speed_override0_actualSpeeds_dr_12G_R2 37 1922 #define sc_x1_speed_override0_actualSpeeds_dr_10G_X2 38 1923 #define sc_x1_speed_override0_actualSpeeds_dr_40G_KR4 39 1924 #define sc_x1_speed_override0_actualSpeeds_dr_40G_CR4 40 1925 #define sc_x1_speed_override0_actualSpeeds_dr_100G_CR10 41 1926 #define sc_x1_speed_override0_actualSpeeds_dr_15p75G_DXGXS 44 1927 #define sc_x1_speed_override0_actualSpeeds_dr_20G_KR2 57 1928 #define sc_x1_speed_override0_actualSpeeds_dr_20G_CR2 58 1929 1930 /**************************************************************************** 1931 * Enums: sc_x1_speed_override0_actualSpeedsMisc1 1932 */ 1933 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_2500BRCM_X1 16 1934 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X4 17 1935 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6000BRCM_X4 18 1936 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GHiGig_X4 19 1937 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10GBASE_CX4 20 1938 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12GHiGig_X4 21 1939 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 1940 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_13GHiGig_X4 23 1941 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_15GHiGig_X4 24 1942 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_16GHiGig_X4 25 1943 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_5000BRCM_X1 26 1944 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_6363BRCM_X1 27 1945 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_20GHiGig_X4 28 1946 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_21GHiGig_X4 29 1947 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 1948 #define sc_x1_speed_override0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 1949 1950 /**************************************************************************** 1951 * Enums: sc_x1_speed_override0_IndLaneModes 1952 */ 1953 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div2 0 1954 #define sc_x1_speed_override0_IndLaneModes_SWSDR_div1 1 1955 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div2 2 1956 #define sc_x1_speed_override0_IndLaneModes_DWSDR_div1 3 1957 1958 /**************************************************************************** 1959 * Enums: sc_x1_speed_override0_prbsSelect 1960 */ 1961 #define sc_x1_speed_override0_prbsSelect_prbs7 0 1962 #define sc_x1_speed_override0_prbsSelect_prbs15 1 1963 #define sc_x1_speed_override0_prbsSelect_prbs23 2 1964 #define sc_x1_speed_override0_prbsSelect_prbs31 3 1965 1966 /**************************************************************************** 1967 * Enums: sc_x1_speed_override0_vcoDivider 1968 */ 1969 #define sc_x1_speed_override0_vcoDivider_div32 0 1970 #define sc_x1_speed_override0_vcoDivider_div36 1 1971 #define sc_x1_speed_override0_vcoDivider_div40 2 1972 #define sc_x1_speed_override0_vcoDivider_div42 3 1973 #define sc_x1_speed_override0_vcoDivider_div48 4 1974 #define sc_x1_speed_override0_vcoDivider_div50 5 1975 #define sc_x1_speed_override0_vcoDivider_div52 6 1976 #define sc_x1_speed_override0_vcoDivider_div54 7 1977 #define sc_x1_speed_override0_vcoDivider_div60 8 1978 #define sc_x1_speed_override0_vcoDivider_div64 9 1979 #define sc_x1_speed_override0_vcoDivider_div66 10 1980 #define sc_x1_speed_override0_vcoDivider_div68 11 1981 #define sc_x1_speed_override0_vcoDivider_div70 12 1982 #define sc_x1_speed_override0_vcoDivider_div80 13 1983 #define sc_x1_speed_override0_vcoDivider_div92 14 1984 #define sc_x1_speed_override0_vcoDivider_div100 15 1985 1986 /**************************************************************************** 1987 * Enums: sc_x1_speed_override0_refClkSelect 1988 */ 1989 #define sc_x1_speed_override0_refClkSelect_clk_25MHz 0 1990 #define sc_x1_speed_override0_refClkSelect_clk_100MHz 1 1991 #define sc_x1_speed_override0_refClkSelect_clk_125MHz 2 1992 #define sc_x1_speed_override0_refClkSelect_clk_156p25MHz 3 1993 #define sc_x1_speed_override0_refClkSelect_clk_187p5MHz 4 1994 #define sc_x1_speed_override0_refClkSelect_clk_161p25Mhz 5 1995 #define sc_x1_speed_override0_refClkSelect_clk_50Mhz 6 1996 #define sc_x1_speed_override0_refClkSelect_clk_106p25Mhz 7 1997 1998 /**************************************************************************** 1999 * Enums: sc_x1_speed_override0_aerMMDdevTypeSelect 2000 */ 2001 #define sc_x1_speed_override0_aerMMDdevTypeSelect_combo_core 0 2002 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PMA_PMD 1 2003 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PCS 3 2004 #define sc_x1_speed_override0_aerMMDdevTypeSelect_PHY 4 2005 #define sc_x1_speed_override0_aerMMDdevTypeSelect_DTE 5 2006 #define sc_x1_speed_override0_aerMMDdevTypeSelect_CL73_AN 7 2007 2008 /**************************************************************************** 2009 * Enums: sc_x1_speed_override0_aerMMDportSelect 2010 */ 2011 #define sc_x1_speed_override0_aerMMDportSelect_ln0 0 2012 #define sc_x1_speed_override0_aerMMDportSelect_ln1 1 2013 #define sc_x1_speed_override0_aerMMDportSelect_ln2 2 2014 #define sc_x1_speed_override0_aerMMDportSelect_ln3 3 2015 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1_2_3 511 2016 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln0_1 512 2017 #define sc_x1_speed_override0_aerMMDportSelect_BCST_ln2_3 513 2018 2019 /**************************************************************************** 2020 * Enums: sc_x1_speed_override0_firmwareModeSelect 2021 */ 2022 #define sc_x1_speed_override0_firmwareModeSelect_DEFAULT 0 2023 #define sc_x1_speed_override0_firmwareModeSelect_SFP_OPT_LR 1 2024 #define sc_x1_speed_override0_firmwareModeSelect_SFP_DAC 2 2025 #define sc_x1_speed_override0_firmwareModeSelect_XLAUI 3 2026 #define sc_x1_speed_override0_firmwareModeSelect_LONG_CH_6G 4 2027 2028 /**************************************************************************** 2029 * Enums: sc_x1_speed_override0_tempIdxSelect 2030 */ 2031 #define sc_x1_speed_override0_tempIdxSelect_LTE__22p9C 15 2032 #define sc_x1_speed_override0_tempIdxSelect_LTE__12p6C 14 2033 #define sc_x1_speed_override0_tempIdxSelect_LTE__3p0C 13 2034 #define sc_x1_speed_override0_tempIdxSelect_LTE_6p7C 12 2035 #define sc_x1_speed_override0_tempIdxSelect_LTE_16p4C 11 2036 #define sc_x1_speed_override0_tempIdxSelect_LTE_26p6C 10 2037 #define sc_x1_speed_override0_tempIdxSelect_LTE_36p3C 9 2038 #define sc_x1_speed_override0_tempIdxSelect_LTE_46p0C 8 2039 #define sc_x1_speed_override0_tempIdxSelect_LTE_56p2C 7 2040 #define sc_x1_speed_override0_tempIdxSelect_LTE_65p9C 6 2041 #define sc_x1_speed_override0_tempIdxSelect_LTE_75p6C 5 2042 #define sc_x1_speed_override0_tempIdxSelect_LTE_85p3C 4 2043 #define sc_x1_speed_override0_tempIdxSelect_LTE_95p5C 3 2044 #define sc_x1_speed_override0_tempIdxSelect_LTE_105p2C 2 2045 #define sc_x1_speed_override0_tempIdxSelect_LTE_114p9C 1 2046 #define sc_x1_speed_override0_tempIdxSelect_LTE_125p1C 0 2047 2048 /**************************************************************************** 2049 * Enums: sc_x4_control_cl36TxEEEStates_l 2050 */ 2051 #define sc_x4_control_cl36TxEEEStates_l_TX_REFRESH 8 2052 #define sc_x4_control_cl36TxEEEStates_l_TX_QUIET 4 2053 #define sc_x4_control_cl36TxEEEStates_l_TX_SLEEP 2 2054 #define sc_x4_control_cl36TxEEEStates_l_TX_ACTIVE 1 2055 2056 /**************************************************************************** 2057 * Enums: sc_x4_control_cl36TxEEEStates_c 2058 */ 2059 #define sc_x4_control_cl36TxEEEStates_c_TX_REFRESH 3 2060 #define sc_x4_control_cl36TxEEEStates_c_TX_QUIET 2 2061 #define sc_x4_control_cl36TxEEEStates_c_TX_SLEEP 1 2062 #define sc_x4_control_cl36TxEEEStates_c_TX_ACTIVE 0 2063 2064 /**************************************************************************** 2065 * Enums: sc_x4_control_cl49TxEEEStates_l 2066 */ 2067 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_2 64 2068 #define sc_x4_control_cl49TxEEEStates_l_SCR_RESET_1 32 2069 #define sc_x4_control_cl49TxEEEStates_l_TX_WAKE 16 2070 #define sc_x4_control_cl49TxEEEStates_l_TX_REFRESH 8 2071 #define sc_x4_control_cl49TxEEEStates_l_TX_QUIET 4 2072 #define sc_x4_control_cl49TxEEEStates_l_TX_SLEEP 2 2073 #define sc_x4_control_cl49TxEEEStates_l_TX_ACTIVE 1 2074 2075 /**************************************************************************** 2076 * Enums: sc_x4_control_cl49TxEEEStates_c 2077 */ 2078 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_2 6 2079 #define sc_x4_control_cl49TxEEEStates_c_SCR_RESET_1 5 2080 #define sc_x4_control_cl49TxEEEStates_c_TX_WAKE 4 2081 #define sc_x4_control_cl49TxEEEStates_c_TX_REFRESH 3 2082 #define sc_x4_control_cl49TxEEEStates_c_TX_QUIET 2 2083 #define sc_x4_control_cl49TxEEEStates_c_TX_SLEEP 1 2084 #define sc_x4_control_cl49TxEEEStates_c_TX_ACTIVE 0 2085 2086 /**************************************************************************** 2087 * Enums: sc_x4_control_cl36RxEEEStates_l 2088 */ 2089 #define sc_x4_control_cl36RxEEEStates_l_RX_LINK_FAIL 32 2090 #define sc_x4_control_cl36RxEEEStates_l_RX_WTF 16 2091 #define sc_x4_control_cl36RxEEEStates_l_RX_WAKE 8 2092 #define sc_x4_control_cl36RxEEEStates_l_RX_QUIET 4 2093 #define sc_x4_control_cl36RxEEEStates_l_RX_SLEEP 2 2094 #define sc_x4_control_cl36RxEEEStates_l_RX_ACTIVE 1 2095 2096 /**************************************************************************** 2097 * Enums: sc_x4_control_cl36RxEEEStates_c 2098 */ 2099 #define sc_x4_control_cl36RxEEEStates_c_RX_LINK_FAIL 5 2100 #define sc_x4_control_cl36RxEEEStates_c_RX_WTF 4 2101 #define sc_x4_control_cl36RxEEEStates_c_RX_WAKE 3 2102 #define sc_x4_control_cl36RxEEEStates_c_RX_QUIET 2 2103 #define sc_x4_control_cl36RxEEEStates_c_RX_SLEEP 1 2104 #define sc_x4_control_cl36RxEEEStates_c_RX_ACTIVE 0 2105 2106 /**************************************************************************** 2107 * Enums: sc_x4_control_cl49RxEEEStates_l 2108 */ 2109 #define sc_x4_control_cl49RxEEEStates_l_RX_LINK_FAIL 32 2110 #define sc_x4_control_cl49RxEEEStates_l_RX_WTF 16 2111 #define sc_x4_control_cl49RxEEEStates_l_RX_WAKE 8 2112 #define sc_x4_control_cl49RxEEEStates_l_RX_QUIET 4 2113 #define sc_x4_control_cl49RxEEEStates_l_RX_SLEEP 2 2114 #define sc_x4_control_cl49RxEEEStates_l_RX_ACTIVE 1 2115 2116 /**************************************************************************** 2117 * Enums: sc_x4_control_cl49RxEEEStates_c 2118 */ 2119 #define sc_x4_control_cl49RxEEEStates_c_RX_LINK_FAIL 5 2120 #define sc_x4_control_cl49RxEEEStates_c_RX_WTF 4 2121 #define sc_x4_control_cl49RxEEEStates_c_RX_WAKE 3 2122 #define sc_x4_control_cl49RxEEEStates_c_RX_QUIET 2 2123 #define sc_x4_control_cl49RxEEEStates_c_RX_SLEEP 1 2124 #define sc_x4_control_cl49RxEEEStates_c_RX_ACTIVE 0 2125 2126 /**************************************************************************** 2127 * Enums: sc_x4_control_cl48TxEEEStates_l 2128 */ 2129 #define sc_x4_control_cl48TxEEEStates_l_TX_REFRESH 8 2130 #define sc_x4_control_cl48TxEEEStates_l_TX_QUIET 4 2131 #define sc_x4_control_cl48TxEEEStates_l_TX_SLEEP 2 2132 #define sc_x4_control_cl48TxEEEStates_l_TX_ACTIVE 1 2133 2134 /**************************************************************************** 2135 * Enums: sc_x4_control_cl48TxEEEStates_c 2136 */ 2137 #define sc_x4_control_cl48TxEEEStates_c_TX_REFRESH 3 2138 #define sc_x4_control_cl48TxEEEStates_c_TX_QUIET 2 2139 #define sc_x4_control_cl48TxEEEStates_c_TX_SLEEP 1 2140 #define sc_x4_control_cl48TxEEEStates_c_TX_ACTIVE 0 2141 2142 /**************************************************************************** 2143 * Enums: sc_x4_control_cl48RxEEEStates_l 2144 */ 2145 #define sc_x4_control_cl48RxEEEStates_l_RX_LINK_FAIL 32 2146 #define sc_x4_control_cl48RxEEEStates_l_RX_WAKE 16 2147 #define sc_x4_control_cl48RxEEEStates_l_RX_QUIET 8 2148 #define sc_x4_control_cl48RxEEEStates_l_RX_DEACT 4 2149 #define sc_x4_control_cl48RxEEEStates_l_RX_SLEEP 2 2150 #define sc_x4_control_cl48RxEEEStates_l_RX_ACTIVE 1 2151 2152 /**************************************************************************** 2153 * Enums: sc_x4_control_cl48RxEEEStates_c 2154 */ 2155 #define sc_x4_control_cl48RxEEEStates_c_RX_LINK_FAIL 5 2156 #define sc_x4_control_cl48RxEEEStates_c_RX_WAKE 4 2157 #define sc_x4_control_cl48RxEEEStates_c_RX_QUIET 3 2158 #define sc_x4_control_cl48RxEEEStates_c_RX_DEACT 2 2159 #define sc_x4_control_cl48RxEEEStates_c_RX_SLEEP 1 2160 #define sc_x4_control_cl48RxEEEStates_c_RX_ACTIVE 0 2161 2162 /**************************************************************************** 2163 * Enums: sc_x4_control_IQP_Options 2164 */ 2165 #define sc_x4_control_IQP_Options_i50uA 0 2166 #define sc_x4_control_IQP_Options_i100uA 1 2167 #define sc_x4_control_IQP_Options_i150uA 2 2168 #define sc_x4_control_IQP_Options_i200uA 3 2169 #define sc_x4_control_IQP_Options_i250uA 4 2170 #define sc_x4_control_IQP_Options_i300uA 5 2171 #define sc_x4_control_IQP_Options_i350uA 6 2172 #define sc_x4_control_IQP_Options_i400uA 7 2173 #define sc_x4_control_IQP_Options_i450uA 8 2174 #define sc_x4_control_IQP_Options_i500uA 9 2175 #define sc_x4_control_IQP_Options_i550uA 10 2176 #define sc_x4_control_IQP_Options_i600uA 11 2177 #define sc_x4_control_IQP_Options_i650uA 12 2178 #define sc_x4_control_IQP_Options_i700uA 13 2179 #define sc_x4_control_IQP_Options_i750uA 14 2180 #define sc_x4_control_IQP_Options_i800uA 15 2181 2182 /**************************************************************************** 2183 * Enums: sc_x4_control_IDriver_Options 2184 */ 2185 #define sc_x4_control_IDriver_Options_v680mV 0 2186 #define sc_x4_control_IDriver_Options_v730mV 1 2187 #define sc_x4_control_IDriver_Options_v780mV 2 2188 #define sc_x4_control_IDriver_Options_v830mV 3 2189 #define sc_x4_control_IDriver_Options_v880mV 4 2190 #define sc_x4_control_IDriver_Options_v930mV 5 2191 #define sc_x4_control_IDriver_Options_v980mV 6 2192 #define sc_x4_control_IDriver_Options_v1010mV 7 2193 #define sc_x4_control_IDriver_Options_v1040mV 8 2194 #define sc_x4_control_IDriver_Options_v1060mV 9 2195 #define sc_x4_control_IDriver_Options_v1070mV 10 2196 #define sc_x4_control_IDriver_Options_v1080mV 11 2197 #define sc_x4_control_IDriver_Options_v1085mV 12 2198 #define sc_x4_control_IDriver_Options_v1090mV 13 2199 #define sc_x4_control_IDriver_Options_v1095mV 14 2200 #define sc_x4_control_IDriver_Options_v1100mV 15 2201 2202 /**************************************************************************** 2203 * Enums: sc_x4_control_operationModes 2204 */ 2205 #define sc_x4_control_operationModes_XGXS 0 2206 #define sc_x4_control_operationModes_XGXG_nCC 1 2207 #define sc_x4_control_operationModes_Indlane_OS8 4 2208 #define sc_x4_control_operationModes_IndLane_OS5 5 2209 #define sc_x4_control_operationModes_PCI 7 2210 #define sc_x4_control_operationModes_XGXS_nLQ 8 2211 #define sc_x4_control_operationModes_XGXS_nLQnCC 9 2212 #define sc_x4_control_operationModes_PBypass 10 2213 #define sc_x4_control_operationModes_PBypass_nDSK 11 2214 #define sc_x4_control_operationModes_ComboCoreMode 12 2215 #define sc_x4_control_operationModes_Clocks_off 15 2216 2217 /**************************************************************************** 2218 * Enums: sc_x4_control_synce_enum 2219 */ 2220 #define sc_x4_control_synce_enum_SYNCE_NO_DIV 0 2221 #define sc_x4_control_synce_enum_SYNCE_DIV_7 1 2222 #define sc_x4_control_synce_enum_SYNCE_DIV_11 2 2223 2224 /**************************************************************************** 2225 * Enums: sc_x4_control_operationSpeeds 2226 */ 2227 #define sc_x4_control_operationSpeeds_SPEED_5G_X1_12p5 65 2228 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_12p5 64 2229 #define sc_x4_control_operationSpeeds_SPEED_1000M_12p5 63 2230 #define sc_x4_control_operationSpeeds_SPEED_100M_12p5 62 2231 #define sc_x4_control_operationSpeeds_SPEED_10M_12p5 61 2232 #define sc_x4_control_operationSpeeds_SPEED_4G_X1_10 60 2233 #define sc_x4_control_operationSpeeds_SPEED_1000M_X1_10 59 2234 #define sc_x4_control_operationSpeeds_SPEED_100M_X1_10 58 2235 #define sc_x4_control_operationSpeeds_SPEED_10M_X1_10 57 2236 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2237 #define sc_x4_control_operationSpeeds_SPEED_1000M_10p3125 55 2238 #define sc_x4_control_operationSpeeds_SPEED_100M_10p3125 54 2239 #define sc_x4_control_operationSpeeds_SPEED_10M_10p3125 53 2240 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X4 50 2241 #define sc_x4_control_operationSpeeds_SPEED_5G_KR1 49 2242 #define sc_x4_control_operationSpeeds_SPEED_127G_X12 39 2243 #define sc_x4_control_operationSpeeds_SPEED_120G_X12 38 2244 #define sc_x4_control_operationSpeeds_SPEED_107G_X10 37 2245 #define sc_x4_control_operationSpeeds_SPEED_100G_CR10 36 2246 #define sc_x4_control_operationSpeeds_SPEED_42G_X4 35 2247 #define sc_x4_control_operationSpeeds_SPEED_40G_CR4 34 2248 #define sc_x4_control_operationSpeeds_SPEED_40G_KR4 33 2249 #define sc_x4_control_operationSpeeds_SPEED_21G_X2 32 2250 #define sc_x4_control_operationSpeeds_SPEED_20G_CR2 31 2251 #define sc_x4_control_operationSpeeds_SPEED_20G_KR2 30 2252 #define sc_x4_control_operationSpeeds_SPEED_10p6_X1 29 2253 #define sc_x4_control_operationSpeeds_SPEED_10G_KR1 28 2254 #define sc_x4_control_operationSpeeds_SPEED_40G_X4 27 2255 #define sc_x4_control_operationSpeeds_SPEED_20G_X2 26 2256 #define sc_x4_control_operationSpeeds_SPEED_20G_CX2 25 2257 #define sc_x4_control_operationSpeeds_SPEED_31p5G_KR4 24 2258 #define sc_x4_control_operationSpeeds_SPEED_31p5G_X4 23 2259 #define sc_x4_control_operationSpeeds_SPEED_15p75G_X2 22 2260 #define sc_x4_control_operationSpeeds_SPEED_25p45G_X4 21 2261 #define sc_x4_control_operationSpeeds_SPEED_12p7G_X2 20 2262 #define sc_x4_control_operationSpeeds_SPEED_21G_X4 19 2263 #define sc_x4_control_operationSpeeds_SPEED_10p5G_X2 18 2264 #define sc_x4_control_operationSpeeds_SPEED_20G_X4 17 2265 #define sc_x4_control_operationSpeeds_SPEED_10G_X2 16 2266 #define sc_x4_control_operationSpeeds_SPEED_10G_CX2 15 2267 #define sc_x4_control_operationSpeeds_SPEED_20G_CX4 14 2268 #define sc_x4_control_operationSpeeds_SPEED_16G_X4 13 2269 #define sc_x4_control_operationSpeeds_SPEED_15G_X4 12 2270 #define sc_x4_control_operationSpeeds_SPEED_13G_X4 11 2271 #define sc_x4_control_operationSpeeds_SPEED_10G_X4 10 2272 #define sc_x4_control_operationSpeeds_SPEED_10G_KX4 9 2273 #define sc_x4_control_operationSpeeds_SPEED_10G_CX4 8 2274 #define sc_x4_control_operationSpeeds_SPEED_5G_X1 7 2275 #define sc_x4_control_operationSpeeds_SPEED_2p5G_X1 6 2276 #define sc_x4_control_operationSpeeds_SPEED_1G_KX1 5 2277 #define sc_x4_control_operationSpeeds_SPEED_1G_CX1 4 2278 #define sc_x4_control_operationSpeeds_SPEED_1000M 3 2279 #define sc_x4_control_operationSpeeds_SPEED_100M 2 2280 #define sc_x4_control_operationSpeeds_SPEED_10M 1 2281 2282 /**************************************************************************** 2283 * Enums: sc_x4_control_actualSpeeds 2284 */ 2285 #define sc_x4_control_actualSpeeds_dr_10M 0 2286 #define sc_x4_control_actualSpeeds_dr_100M 1 2287 #define sc_x4_control_actualSpeeds_dr_1G 2 2288 #define sc_x4_control_actualSpeeds_dr_2p5G 3 2289 #define sc_x4_control_actualSpeeds_dr_5G_X4 4 2290 #define sc_x4_control_actualSpeeds_dr_6G_X4 5 2291 #define sc_x4_control_actualSpeeds_dr_10G_HiG 6 2292 #define sc_x4_control_actualSpeeds_dr_10G_CX4 7 2293 #define sc_x4_control_actualSpeeds_dr_12G_HiG 8 2294 #define sc_x4_control_actualSpeeds_dr_12p5G_X4 9 2295 #define sc_x4_control_actualSpeeds_dr_13G_X4 10 2296 #define sc_x4_control_actualSpeeds_dr_15G_X4 11 2297 #define sc_x4_control_actualSpeeds_dr_16G_X4 12 2298 #define sc_x4_control_actualSpeeds_dr_1G_KX 13 2299 #define sc_x4_control_actualSpeeds_dr_10G_KX4 14 2300 #define sc_x4_control_actualSpeeds_dr_10G_KR 15 2301 #define sc_x4_control_actualSpeeds_dr_5G 16 2302 #define sc_x4_control_actualSpeeds_dr_6p4G 17 2303 #define sc_x4_control_actualSpeeds_dr_20G_X4 18 2304 #define sc_x4_control_actualSpeeds_dr_21G_X4 19 2305 #define sc_x4_control_actualSpeeds_dr_25G_X4 20 2306 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS 21 2307 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS 22 2308 #define sc_x4_control_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2309 #define sc_x4_control_actualSpeeds_dr_10p5G_DXGXS 24 2310 #define sc_x4_control_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2311 #define sc_x4_control_actualSpeeds_dr_12p773G_DXGXS 26 2312 #define sc_x4_control_actualSpeeds_dr_10G_XFI 27 2313 #define sc_x4_control_actualSpeeds_dr_40G 28 2314 #define sc_x4_control_actualSpeeds_dr_20G_HiG_DXGXS 29 2315 #define sc_x4_control_actualSpeeds_dr_20G_DXGXS 30 2316 #define sc_x4_control_actualSpeeds_dr_10G_SFI 31 2317 #define sc_x4_control_actualSpeeds_dr_31p5G 32 2318 #define sc_x4_control_actualSpeeds_dr_32p7G 33 2319 #define sc_x4_control_actualSpeeds_dr_20G_SCR 34 2320 #define sc_x4_control_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2321 #define sc_x4_control_actualSpeeds_dr_10G_DXGXS_SCR 36 2322 #define sc_x4_control_actualSpeeds_dr_12G_R2 37 2323 #define sc_x4_control_actualSpeeds_dr_10G_X2 38 2324 #define sc_x4_control_actualSpeeds_dr_40G_KR4 39 2325 #define sc_x4_control_actualSpeeds_dr_40G_CR4 40 2326 #define sc_x4_control_actualSpeeds_dr_100G_CR10 41 2327 #define sc_x4_control_actualSpeeds_dr_15p75G_DXGXS 44 2328 #define sc_x4_control_actualSpeeds_dr_20G_KR2 57 2329 #define sc_x4_control_actualSpeeds_dr_20G_CR2 58 2330 2331 /**************************************************************************** 2332 * Enums: sc_x4_control_actualSpeedsMisc1 2333 */ 2334 #define sc_x4_control_actualSpeedsMisc1_dr_2500BRCM_X1 16 2335 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X4 17 2336 #define sc_x4_control_actualSpeedsMisc1_dr_6000BRCM_X4 18 2337 #define sc_x4_control_actualSpeedsMisc1_dr_10GHiGig_X4 19 2338 #define sc_x4_control_actualSpeedsMisc1_dr_10GBASE_CX4 20 2339 #define sc_x4_control_actualSpeedsMisc1_dr_12GHiGig_X4 21 2340 #define sc_x4_control_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2341 #define sc_x4_control_actualSpeedsMisc1_dr_13GHiGig_X4 23 2342 #define sc_x4_control_actualSpeedsMisc1_dr_15GHiGig_X4 24 2343 #define sc_x4_control_actualSpeedsMisc1_dr_16GHiGig_X4 25 2344 #define sc_x4_control_actualSpeedsMisc1_dr_5000BRCM_X1 26 2345 #define sc_x4_control_actualSpeedsMisc1_dr_6363BRCM_X1 27 2346 #define sc_x4_control_actualSpeedsMisc1_dr_20GHiGig_X4 28 2347 #define sc_x4_control_actualSpeedsMisc1_dr_21GHiGig_X4 29 2348 #define sc_x4_control_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2349 #define sc_x4_control_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2350 2351 /**************************************************************************** 2352 * Enums: sc_x4_control_IndLaneModes 2353 */ 2354 #define sc_x4_control_IndLaneModes_SWSDR_div2 0 2355 #define sc_x4_control_IndLaneModes_SWSDR_div1 1 2356 #define sc_x4_control_IndLaneModes_DWSDR_div2 2 2357 #define sc_x4_control_IndLaneModes_DWSDR_div1 3 2358 2359 /**************************************************************************** 2360 * Enums: sc_x4_control_prbsSelect 2361 */ 2362 #define sc_x4_control_prbsSelect_prbs7 0 2363 #define sc_x4_control_prbsSelect_prbs15 1 2364 #define sc_x4_control_prbsSelect_prbs23 2 2365 #define sc_x4_control_prbsSelect_prbs31 3 2366 2367 /**************************************************************************** 2368 * Enums: sc_x4_control_vcoDivider 2369 */ 2370 #define sc_x4_control_vcoDivider_div32 0 2371 #define sc_x4_control_vcoDivider_div36 1 2372 #define sc_x4_control_vcoDivider_div40 2 2373 #define sc_x4_control_vcoDivider_div42 3 2374 #define sc_x4_control_vcoDivider_div48 4 2375 #define sc_x4_control_vcoDivider_div50 5 2376 #define sc_x4_control_vcoDivider_div52 6 2377 #define sc_x4_control_vcoDivider_div54 7 2378 #define sc_x4_control_vcoDivider_div60 8 2379 #define sc_x4_control_vcoDivider_div64 9 2380 #define sc_x4_control_vcoDivider_div66 10 2381 #define sc_x4_control_vcoDivider_div68 11 2382 #define sc_x4_control_vcoDivider_div70 12 2383 #define sc_x4_control_vcoDivider_div80 13 2384 #define sc_x4_control_vcoDivider_div92 14 2385 #define sc_x4_control_vcoDivider_div100 15 2386 2387 /**************************************************************************** 2388 * Enums: sc_x4_control_refClkSelect 2389 */ 2390 #define sc_x4_control_refClkSelect_clk_25MHz 0 2391 #define sc_x4_control_refClkSelect_clk_100MHz 1 2392 #define sc_x4_control_refClkSelect_clk_125MHz 2 2393 #define sc_x4_control_refClkSelect_clk_156p25MHz 3 2394 #define sc_x4_control_refClkSelect_clk_187p5MHz 4 2395 #define sc_x4_control_refClkSelect_clk_161p25Mhz 5 2396 #define sc_x4_control_refClkSelect_clk_50Mhz 6 2397 #define sc_x4_control_refClkSelect_clk_106p25Mhz 7 2398 2399 /**************************************************************************** 2400 * Enums: sc_x4_control_aerMMDdevTypeSelect 2401 */ 2402 #define sc_x4_control_aerMMDdevTypeSelect_combo_core 0 2403 #define sc_x4_control_aerMMDdevTypeSelect_PMA_PMD 1 2404 #define sc_x4_control_aerMMDdevTypeSelect_PCS 3 2405 #define sc_x4_control_aerMMDdevTypeSelect_PHY 4 2406 #define sc_x4_control_aerMMDdevTypeSelect_DTE 5 2407 #define sc_x4_control_aerMMDdevTypeSelect_CL73_AN 7 2408 2409 /**************************************************************************** 2410 * Enums: sc_x4_control_aerMMDportSelect 2411 */ 2412 #define sc_x4_control_aerMMDportSelect_ln0 0 2413 #define sc_x4_control_aerMMDportSelect_ln1 1 2414 #define sc_x4_control_aerMMDportSelect_ln2 2 2415 #define sc_x4_control_aerMMDportSelect_ln3 3 2416 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1_2_3 511 2417 #define sc_x4_control_aerMMDportSelect_BCST_ln0_1 512 2418 #define sc_x4_control_aerMMDportSelect_BCST_ln2_3 513 2419 2420 /**************************************************************************** 2421 * Enums: sc_x4_control_firmwareModeSelect 2422 */ 2423 #define sc_x4_control_firmwareModeSelect_DEFAULT 0 2424 #define sc_x4_control_firmwareModeSelect_SFP_OPT_LR 1 2425 #define sc_x4_control_firmwareModeSelect_SFP_DAC 2 2426 #define sc_x4_control_firmwareModeSelect_XLAUI 3 2427 #define sc_x4_control_firmwareModeSelect_LONG_CH_6G 4 2428 2429 /**************************************************************************** 2430 * Enums: sc_x4_control_tempIdxSelect 2431 */ 2432 #define sc_x4_control_tempIdxSelect_LTE__22p9C 15 2433 #define sc_x4_control_tempIdxSelect_LTE__12p6C 14 2434 #define sc_x4_control_tempIdxSelect_LTE__3p0C 13 2435 #define sc_x4_control_tempIdxSelect_LTE_6p7C 12 2436 #define sc_x4_control_tempIdxSelect_LTE_16p4C 11 2437 #define sc_x4_control_tempIdxSelect_LTE_26p6C 10 2438 #define sc_x4_control_tempIdxSelect_LTE_36p3C 9 2439 #define sc_x4_control_tempIdxSelect_LTE_46p0C 8 2440 #define sc_x4_control_tempIdxSelect_LTE_56p2C 7 2441 #define sc_x4_control_tempIdxSelect_LTE_65p9C 6 2442 #define sc_x4_control_tempIdxSelect_LTE_75p6C 5 2443 #define sc_x4_control_tempIdxSelect_LTE_85p3C 4 2444 #define sc_x4_control_tempIdxSelect_LTE_95p5C 3 2445 #define sc_x4_control_tempIdxSelect_LTE_105p2C 2 2446 #define sc_x4_control_tempIdxSelect_LTE_114p9C 1 2447 #define sc_x4_control_tempIdxSelect_LTE_125p1C 0 2448 2449 /**************************************************************************** 2450 * Enums: sc_x4_control_sc_seq_status 2451 */ 2452 #define sc_x4_control_sc_seq_status_START 32768 2453 #define sc_x4_control_sc_seq_status_RESET_PCS 16384 2454 #define sc_x4_control_sc_seq_status_RESET_PMD_LANE 8192 2455 #define sc_x4_control_sc_seq_status_RESET_PMD_PLL 4096 2456 #define sc_x4_control_sc_seq_status_APPLY_SPEED_CFG 2048 2457 #define sc_x4_control_sc_seq_status_WAIT_CFG_DONE 1024 2458 #define sc_x4_control_sc_seq_status_ACTIVATE_PMD 512 2459 #define sc_x4_control_sc_seq_status_WAIT_PLL_RESET 256 2460 #define sc_x4_control_sc_seq_status_PLL_LOCK_FAIL 128 2461 #define sc_x4_control_sc_seq_status_ACTIVATE_TX 64 2462 #define sc_x4_control_sc_seq_status_WAIT_PMD_LOCK 32 2463 #define sc_x4_control_sc_seq_status_ACTIVATE_RX 16 2464 #define sc_x4_control_sc_seq_status_PMD_LOCK_FAIL 8 2465 #define sc_x4_control_sc_seq_status_DONE 4 2466 #define sc_x4_control_sc_seq_status_STOP 2 2467 #define sc_x4_control_sc_seq_status_BYPASS 1 2468 2469 /**************************************************************************** 2470 * Enums: sc_x4_final_config_status_cl36TxEEEStates_l 2471 */ 2472 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_REFRESH 8 2473 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_QUIET 4 2474 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_SLEEP 2 2475 #define sc_x4_final_config_status_cl36TxEEEStates_l_TX_ACTIVE 1 2476 2477 /**************************************************************************** 2478 * Enums: sc_x4_final_config_status_cl36TxEEEStates_c 2479 */ 2480 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_REFRESH 3 2481 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_QUIET 2 2482 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_SLEEP 1 2483 #define sc_x4_final_config_status_cl36TxEEEStates_c_TX_ACTIVE 0 2484 2485 /**************************************************************************** 2486 * Enums: sc_x4_final_config_status_cl49TxEEEStates_l 2487 */ 2488 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_2 64 2489 #define sc_x4_final_config_status_cl49TxEEEStates_l_SCR_RESET_1 32 2490 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_WAKE 16 2491 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_REFRESH 8 2492 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_QUIET 4 2493 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_SLEEP 2 2494 #define sc_x4_final_config_status_cl49TxEEEStates_l_TX_ACTIVE 1 2495 2496 /**************************************************************************** 2497 * Enums: sc_x4_final_config_status_cl49TxEEEStates_c 2498 */ 2499 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_2 6 2500 #define sc_x4_final_config_status_cl49TxEEEStates_c_SCR_RESET_1 5 2501 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_WAKE 4 2502 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_REFRESH 3 2503 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_QUIET 2 2504 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_SLEEP 1 2505 #define sc_x4_final_config_status_cl49TxEEEStates_c_TX_ACTIVE 0 2506 2507 /**************************************************************************** 2508 * Enums: sc_x4_final_config_status_cl36RxEEEStates_l 2509 */ 2510 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_LINK_FAIL 32 2511 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WTF 16 2512 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_WAKE 8 2513 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_QUIET 4 2514 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_SLEEP 2 2515 #define sc_x4_final_config_status_cl36RxEEEStates_l_RX_ACTIVE 1 2516 2517 /**************************************************************************** 2518 * Enums: sc_x4_final_config_status_cl36RxEEEStates_c 2519 */ 2520 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_LINK_FAIL 5 2521 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WTF 4 2522 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_WAKE 3 2523 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_QUIET 2 2524 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_SLEEP 1 2525 #define sc_x4_final_config_status_cl36RxEEEStates_c_RX_ACTIVE 0 2526 2527 /**************************************************************************** 2528 * Enums: sc_x4_final_config_status_cl49RxEEEStates_l 2529 */ 2530 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_LINK_FAIL 32 2531 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WTF 16 2532 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_WAKE 8 2533 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_QUIET 4 2534 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_SLEEP 2 2535 #define sc_x4_final_config_status_cl49RxEEEStates_l_RX_ACTIVE 1 2536 2537 /**************************************************************************** 2538 * Enums: sc_x4_final_config_status_cl49RxEEEStates_c 2539 */ 2540 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_LINK_FAIL 5 2541 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WTF 4 2542 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_WAKE 3 2543 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_QUIET 2 2544 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_SLEEP 1 2545 #define sc_x4_final_config_status_cl49RxEEEStates_c_RX_ACTIVE 0 2546 2547 /**************************************************************************** 2548 * Enums: sc_x4_final_config_status_cl48TxEEEStates_l 2549 */ 2550 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_REFRESH 8 2551 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_QUIET 4 2552 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_SLEEP 2 2553 #define sc_x4_final_config_status_cl48TxEEEStates_l_TX_ACTIVE 1 2554 2555 /**************************************************************************** 2556 * Enums: sc_x4_final_config_status_cl48TxEEEStates_c 2557 */ 2558 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_REFRESH 3 2559 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_QUIET 2 2560 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_SLEEP 1 2561 #define sc_x4_final_config_status_cl48TxEEEStates_c_TX_ACTIVE 0 2562 2563 /**************************************************************************** 2564 * Enums: sc_x4_final_config_status_cl48RxEEEStates_l 2565 */ 2566 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_LINK_FAIL 32 2567 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_WAKE 16 2568 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_QUIET 8 2569 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_DEACT 4 2570 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_SLEEP 2 2571 #define sc_x4_final_config_status_cl48RxEEEStates_l_RX_ACTIVE 1 2572 2573 /**************************************************************************** 2574 * Enums: sc_x4_final_config_status_cl48RxEEEStates_c 2575 */ 2576 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_LINK_FAIL 5 2577 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_WAKE 4 2578 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_QUIET 3 2579 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_DEACT 2 2580 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_SLEEP 1 2581 #define sc_x4_final_config_status_cl48RxEEEStates_c_RX_ACTIVE 0 2582 2583 /**************************************************************************** 2584 * Enums: sc_x4_final_config_status_IQP_Options 2585 */ 2586 #define sc_x4_final_config_status_IQP_Options_i50uA 0 2587 #define sc_x4_final_config_status_IQP_Options_i100uA 1 2588 #define sc_x4_final_config_status_IQP_Options_i150uA 2 2589 #define sc_x4_final_config_status_IQP_Options_i200uA 3 2590 #define sc_x4_final_config_status_IQP_Options_i250uA 4 2591 #define sc_x4_final_config_status_IQP_Options_i300uA 5 2592 #define sc_x4_final_config_status_IQP_Options_i350uA 6 2593 #define sc_x4_final_config_status_IQP_Options_i400uA 7 2594 #define sc_x4_final_config_status_IQP_Options_i450uA 8 2595 #define sc_x4_final_config_status_IQP_Options_i500uA 9 2596 #define sc_x4_final_config_status_IQP_Options_i550uA 10 2597 #define sc_x4_final_config_status_IQP_Options_i600uA 11 2598 #define sc_x4_final_config_status_IQP_Options_i650uA 12 2599 #define sc_x4_final_config_status_IQP_Options_i700uA 13 2600 #define sc_x4_final_config_status_IQP_Options_i750uA 14 2601 #define sc_x4_final_config_status_IQP_Options_i800uA 15 2602 2603 /**************************************************************************** 2604 * Enums: sc_x4_final_config_status_IDriver_Options 2605 */ 2606 #define sc_x4_final_config_status_IDriver_Options_v680mV 0 2607 #define sc_x4_final_config_status_IDriver_Options_v730mV 1 2608 #define sc_x4_final_config_status_IDriver_Options_v780mV 2 2609 #define sc_x4_final_config_status_IDriver_Options_v830mV 3 2610 #define sc_x4_final_config_status_IDriver_Options_v880mV 4 2611 #define sc_x4_final_config_status_IDriver_Options_v930mV 5 2612 #define sc_x4_final_config_status_IDriver_Options_v980mV 6 2613 #define sc_x4_final_config_status_IDriver_Options_v1010mV 7 2614 #define sc_x4_final_config_status_IDriver_Options_v1040mV 8 2615 #define sc_x4_final_config_status_IDriver_Options_v1060mV 9 2616 #define sc_x4_final_config_status_IDriver_Options_v1070mV 10 2617 #define sc_x4_final_config_status_IDriver_Options_v1080mV 11 2618 #define sc_x4_final_config_status_IDriver_Options_v1085mV 12 2619 #define sc_x4_final_config_status_IDriver_Options_v1090mV 13 2620 #define sc_x4_final_config_status_IDriver_Options_v1095mV 14 2621 #define sc_x4_final_config_status_IDriver_Options_v1100mV 15 2622 2623 /**************************************************************************** 2624 * Enums: sc_x4_final_config_status_operationModes 2625 */ 2626 #define sc_x4_final_config_status_operationModes_XGXS 0 2627 #define sc_x4_final_config_status_operationModes_XGXG_nCC 1 2628 #define sc_x4_final_config_status_operationModes_Indlane_OS8 4 2629 #define sc_x4_final_config_status_operationModes_IndLane_OS5 5 2630 #define sc_x4_final_config_status_operationModes_PCI 7 2631 #define sc_x4_final_config_status_operationModes_XGXS_nLQ 8 2632 #define sc_x4_final_config_status_operationModes_XGXS_nLQnCC 9 2633 #define sc_x4_final_config_status_operationModes_PBypass 10 2634 #define sc_x4_final_config_status_operationModes_PBypass_nDSK 11 2635 #define sc_x4_final_config_status_operationModes_ComboCoreMode 12 2636 #define sc_x4_final_config_status_operationModes_Clocks_off 15 2637 2638 /**************************************************************************** 2639 * Enums: sc_x4_final_config_status_synce_enum 2640 */ 2641 #define sc_x4_final_config_status_synce_enum_SYNCE_NO_DIV 0 2642 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_7 1 2643 #define sc_x4_final_config_status_synce_enum_SYNCE_DIV_11 2 2644 2645 /**************************************************************************** 2646 * Enums: sc_x4_final_config_status_operationSpeeds 2647 */ 2648 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1_12p5 65 2649 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_12p5 64 2650 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_12p5 63 2651 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_12p5 62 2652 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_12p5 61 2653 #define sc_x4_final_config_status_operationSpeeds_SPEED_4G_X1_10 60 2654 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_X1_10 59 2655 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_X1_10 58 2656 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_X1_10 57 2657 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1_10p3125 56 2658 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M_10p3125 55 2659 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M_10p3125 54 2660 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M_10p3125 53 2661 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X4 50 2662 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_KR1 49 2663 #define sc_x4_final_config_status_operationSpeeds_SPEED_127G_X12 39 2664 #define sc_x4_final_config_status_operationSpeeds_SPEED_120G_X12 38 2665 #define sc_x4_final_config_status_operationSpeeds_SPEED_107G_X10 37 2666 #define sc_x4_final_config_status_operationSpeeds_SPEED_100G_CR10 36 2667 #define sc_x4_final_config_status_operationSpeeds_SPEED_42G_X4 35 2668 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_CR4 34 2669 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_KR4 33 2670 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X2 32 2671 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CR2 31 2672 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_KR2 30 2673 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p6_X1 29 2674 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KR1 28 2675 #define sc_x4_final_config_status_operationSpeeds_SPEED_40G_X4 27 2676 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X2 26 2677 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX2 25 2678 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_KR4 24 2679 #define sc_x4_final_config_status_operationSpeeds_SPEED_31p5G_X4 23 2680 #define sc_x4_final_config_status_operationSpeeds_SPEED_15p75G_X2 22 2681 #define sc_x4_final_config_status_operationSpeeds_SPEED_25p45G_X4 21 2682 #define sc_x4_final_config_status_operationSpeeds_SPEED_12p7G_X2 20 2683 #define sc_x4_final_config_status_operationSpeeds_SPEED_21G_X4 19 2684 #define sc_x4_final_config_status_operationSpeeds_SPEED_10p5G_X2 18 2685 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_X4 17 2686 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X2 16 2687 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX2 15 2688 #define sc_x4_final_config_status_operationSpeeds_SPEED_20G_CX4 14 2689 #define sc_x4_final_config_status_operationSpeeds_SPEED_16G_X4 13 2690 #define sc_x4_final_config_status_operationSpeeds_SPEED_15G_X4 12 2691 #define sc_x4_final_config_status_operationSpeeds_SPEED_13G_X4 11 2692 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_X4 10 2693 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_KX4 9 2694 #define sc_x4_final_config_status_operationSpeeds_SPEED_10G_CX4 8 2695 #define sc_x4_final_config_status_operationSpeeds_SPEED_5G_X1 7 2696 #define sc_x4_final_config_status_operationSpeeds_SPEED_2p5G_X1 6 2697 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_KX1 5 2698 #define sc_x4_final_config_status_operationSpeeds_SPEED_1G_CX1 4 2699 #define sc_x4_final_config_status_operationSpeeds_SPEED_1000M 3 2700 #define sc_x4_final_config_status_operationSpeeds_SPEED_100M 2 2701 #define sc_x4_final_config_status_operationSpeeds_SPEED_10M 1 2702 2703 /**************************************************************************** 2704 * Enums: sc_x4_final_config_status_actualSpeeds 2705 */ 2706 #define sc_x4_final_config_status_actualSpeeds_dr_10M 0 2707 #define sc_x4_final_config_status_actualSpeeds_dr_100M 1 2708 #define sc_x4_final_config_status_actualSpeeds_dr_1G 2 2709 #define sc_x4_final_config_status_actualSpeeds_dr_2p5G 3 2710 #define sc_x4_final_config_status_actualSpeeds_dr_5G_X4 4 2711 #define sc_x4_final_config_status_actualSpeeds_dr_6G_X4 5 2712 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG 6 2713 #define sc_x4_final_config_status_actualSpeeds_dr_10G_CX4 7 2714 #define sc_x4_final_config_status_actualSpeeds_dr_12G_HiG 8 2715 #define sc_x4_final_config_status_actualSpeeds_dr_12p5G_X4 9 2716 #define sc_x4_final_config_status_actualSpeeds_dr_13G_X4 10 2717 #define sc_x4_final_config_status_actualSpeeds_dr_15G_X4 11 2718 #define sc_x4_final_config_status_actualSpeeds_dr_16G_X4 12 2719 #define sc_x4_final_config_status_actualSpeeds_dr_1G_KX 13 2720 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KX4 14 2721 #define sc_x4_final_config_status_actualSpeeds_dr_10G_KR 15 2722 #define sc_x4_final_config_status_actualSpeeds_dr_5G 16 2723 #define sc_x4_final_config_status_actualSpeeds_dr_6p4G 17 2724 #define sc_x4_final_config_status_actualSpeeds_dr_20G_X4 18 2725 #define sc_x4_final_config_status_actualSpeeds_dr_21G_X4 19 2726 #define sc_x4_final_config_status_actualSpeeds_dr_25G_X4 20 2727 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS 21 2728 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS 22 2729 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_HiG_DXGXS 23 2730 #define sc_x4_final_config_status_actualSpeeds_dr_10p5G_DXGXS 24 2731 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_HiG_DXGXS 25 2732 #define sc_x4_final_config_status_actualSpeeds_dr_12p773G_DXGXS 26 2733 #define sc_x4_final_config_status_actualSpeeds_dr_10G_XFI 27 2734 #define sc_x4_final_config_status_actualSpeeds_dr_40G 28 2735 #define sc_x4_final_config_status_actualSpeeds_dr_20G_HiG_DXGXS 29 2736 #define sc_x4_final_config_status_actualSpeeds_dr_20G_DXGXS 30 2737 #define sc_x4_final_config_status_actualSpeeds_dr_10G_SFI 31 2738 #define sc_x4_final_config_status_actualSpeeds_dr_31p5G 32 2739 #define sc_x4_final_config_status_actualSpeeds_dr_32p7G 33 2740 #define sc_x4_final_config_status_actualSpeeds_dr_20G_SCR 34 2741 #define sc_x4_final_config_status_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 2742 #define sc_x4_final_config_status_actualSpeeds_dr_10G_DXGXS_SCR 36 2743 #define sc_x4_final_config_status_actualSpeeds_dr_12G_R2 37 2744 #define sc_x4_final_config_status_actualSpeeds_dr_10G_X2 38 2745 #define sc_x4_final_config_status_actualSpeeds_dr_40G_KR4 39 2746 #define sc_x4_final_config_status_actualSpeeds_dr_40G_CR4 40 2747 #define sc_x4_final_config_status_actualSpeeds_dr_100G_CR10 41 2748 #define sc_x4_final_config_status_actualSpeeds_dr_15p75G_DXGXS 44 2749 #define sc_x4_final_config_status_actualSpeeds_dr_20G_KR2 57 2750 #define sc_x4_final_config_status_actualSpeeds_dr_20G_CR2 58 2751 2752 /**************************************************************************** 2753 * Enums: sc_x4_final_config_status_actualSpeedsMisc1 2754 */ 2755 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_2500BRCM_X1 16 2756 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X4 17 2757 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6000BRCM_X4 18 2758 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GHiGig_X4 19 2759 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10GBASE_CX4 20 2760 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12GHiGig_X4 21 2761 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 2762 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_13GHiGig_X4 23 2763 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_15GHiGig_X4 24 2764 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_16GHiGig_X4 25 2765 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_5000BRCM_X1 26 2766 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_6363BRCM_X1 27 2767 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_20GHiGig_X4 28 2768 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_21GHiGig_X4 29 2769 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 2770 #define sc_x4_final_config_status_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 2771 2772 /**************************************************************************** 2773 * Enums: sc_x4_final_config_status_IndLaneModes 2774 */ 2775 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div2 0 2776 #define sc_x4_final_config_status_IndLaneModes_SWSDR_div1 1 2777 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div2 2 2778 #define sc_x4_final_config_status_IndLaneModes_DWSDR_div1 3 2779 2780 /**************************************************************************** 2781 * Enums: sc_x4_final_config_status_prbsSelect 2782 */ 2783 #define sc_x4_final_config_status_prbsSelect_prbs7 0 2784 #define sc_x4_final_config_status_prbsSelect_prbs15 1 2785 #define sc_x4_final_config_status_prbsSelect_prbs23 2 2786 #define sc_x4_final_config_status_prbsSelect_prbs31 3 2787 2788 /**************************************************************************** 2789 * Enums: sc_x4_final_config_status_vcoDivider 2790 */ 2791 #define sc_x4_final_config_status_vcoDivider_div32 0 2792 #define sc_x4_final_config_status_vcoDivider_div36 1 2793 #define sc_x4_final_config_status_vcoDivider_div40 2 2794 #define sc_x4_final_config_status_vcoDivider_div42 3 2795 #define sc_x4_final_config_status_vcoDivider_div48 4 2796 #define sc_x4_final_config_status_vcoDivider_div50 5 2797 #define sc_x4_final_config_status_vcoDivider_div52 6 2798 #define sc_x4_final_config_status_vcoDivider_div54 7 2799 #define sc_x4_final_config_status_vcoDivider_div60 8 2800 #define sc_x4_final_config_status_vcoDivider_div64 9 2801 #define sc_x4_final_config_status_vcoDivider_div66 10 2802 #define sc_x4_final_config_status_vcoDivider_div68 11 2803 #define sc_x4_final_config_status_vcoDivider_div70 12 2804 #define sc_x4_final_config_status_vcoDivider_div80 13 2805 #define sc_x4_final_config_status_vcoDivider_div92 14 2806 #define sc_x4_final_config_status_vcoDivider_div100 15 2807 2808 /**************************************************************************** 2809 * Enums: sc_x4_final_config_status_refClkSelect 2810 */ 2811 #define sc_x4_final_config_status_refClkSelect_clk_25MHz 0 2812 #define sc_x4_final_config_status_refClkSelect_clk_100MHz 1 2813 #define sc_x4_final_config_status_refClkSelect_clk_125MHz 2 2814 #define sc_x4_final_config_status_refClkSelect_clk_156p25MHz 3 2815 #define sc_x4_final_config_status_refClkSelect_clk_187p5MHz 4 2816 #define sc_x4_final_config_status_refClkSelect_clk_161p25Mhz 5 2817 #define sc_x4_final_config_status_refClkSelect_clk_50Mhz 6 2818 #define sc_x4_final_config_status_refClkSelect_clk_106p25Mhz 7 2819 2820 /**************************************************************************** 2821 * Enums: sc_x4_final_config_status_aerMMDdevTypeSelect 2822 */ 2823 #define sc_x4_final_config_status_aerMMDdevTypeSelect_combo_core 0 2824 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PMA_PMD 1 2825 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PCS 3 2826 #define sc_x4_final_config_status_aerMMDdevTypeSelect_PHY 4 2827 #define sc_x4_final_config_status_aerMMDdevTypeSelect_DTE 5 2828 #define sc_x4_final_config_status_aerMMDdevTypeSelect_CL73_AN 7 2829 2830 /**************************************************************************** 2831 * Enums: sc_x4_final_config_status_aerMMDportSelect 2832 */ 2833 #define sc_x4_final_config_status_aerMMDportSelect_ln0 0 2834 #define sc_x4_final_config_status_aerMMDportSelect_ln1 1 2835 #define sc_x4_final_config_status_aerMMDportSelect_ln2 2 2836 #define sc_x4_final_config_status_aerMMDportSelect_ln3 3 2837 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1_2_3 511 2838 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln0_1 512 2839 #define sc_x4_final_config_status_aerMMDportSelect_BCST_ln2_3 513 2840 2841 /**************************************************************************** 2842 * Enums: sc_x4_final_config_status_firmwareModeSelect 2843 */ 2844 #define sc_x4_final_config_status_firmwareModeSelect_DEFAULT 0 2845 #define sc_x4_final_config_status_firmwareModeSelect_SFP_OPT_LR 1 2846 #define sc_x4_final_config_status_firmwareModeSelect_SFP_DAC 2 2847 #define sc_x4_final_config_status_firmwareModeSelect_XLAUI 3 2848 #define sc_x4_final_config_status_firmwareModeSelect_LONG_CH_6G 4 2849 2850 /**************************************************************************** 2851 * Enums: sc_x4_final_config_status_tempIdxSelect 2852 */ 2853 #define sc_x4_final_config_status_tempIdxSelect_LTE__22p9C 15 2854 #define sc_x4_final_config_status_tempIdxSelect_LTE__12p6C 14 2855 #define sc_x4_final_config_status_tempIdxSelect_LTE__3p0C 13 2856 #define sc_x4_final_config_status_tempIdxSelect_LTE_6p7C 12 2857 #define sc_x4_final_config_status_tempIdxSelect_LTE_16p4C 11 2858 #define sc_x4_final_config_status_tempIdxSelect_LTE_26p6C 10 2859 #define sc_x4_final_config_status_tempIdxSelect_LTE_36p3C 9 2860 #define sc_x4_final_config_status_tempIdxSelect_LTE_46p0C 8 2861 #define sc_x4_final_config_status_tempIdxSelect_LTE_56p2C 7 2862 #define sc_x4_final_config_status_tempIdxSelect_LTE_65p9C 6 2863 #define sc_x4_final_config_status_tempIdxSelect_LTE_75p6C 5 2864 #define sc_x4_final_config_status_tempIdxSelect_LTE_85p3C 4 2865 #define sc_x4_final_config_status_tempIdxSelect_LTE_95p5C 3 2866 #define sc_x4_final_config_status_tempIdxSelect_LTE_105p2C 2 2867 #define sc_x4_final_config_status_tempIdxSelect_LTE_114p9C 1 2868 #define sc_x4_final_config_status_tempIdxSelect_LTE_125p1C 0 2869 2870 /**************************************************************************** 2871 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_l 2872 */ 2873 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_REFRESH 8 2874 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_QUIET 4 2875 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_SLEEP 2 2876 #define tx_x4_credit_gen0_cl36TxEEEStates_l_TX_ACTIVE 1 2877 2878 /**************************************************************************** 2879 * Enums: tx_x4_credit_gen0_cl36TxEEEStates_c 2880 */ 2881 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_REFRESH 3 2882 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_QUIET 2 2883 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_SLEEP 1 2884 #define tx_x4_credit_gen0_cl36TxEEEStates_c_TX_ACTIVE 0 2885 2886 /**************************************************************************** 2887 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_l 2888 */ 2889 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_2 64 2890 #define tx_x4_credit_gen0_cl49TxEEEStates_l_SCR_RESET_1 32 2891 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_WAKE 16 2892 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_REFRESH 8 2893 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_QUIET 4 2894 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_SLEEP 2 2895 #define tx_x4_credit_gen0_cl49TxEEEStates_l_TX_ACTIVE 1 2896 2897 /**************************************************************************** 2898 * Enums: tx_x4_credit_gen0_cl49TxEEEStates_c 2899 */ 2900 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_2 6 2901 #define tx_x4_credit_gen0_cl49TxEEEStates_c_SCR_RESET_1 5 2902 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_WAKE 4 2903 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_REFRESH 3 2904 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_QUIET 2 2905 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_SLEEP 1 2906 #define tx_x4_credit_gen0_cl49TxEEEStates_c_TX_ACTIVE 0 2907 2908 /**************************************************************************** 2909 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_l 2910 */ 2911 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_LINK_FAIL 32 2912 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WTF 16 2913 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_WAKE 8 2914 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_QUIET 4 2915 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_SLEEP 2 2916 #define tx_x4_credit_gen0_cl36RxEEEStates_l_RX_ACTIVE 1 2917 2918 /**************************************************************************** 2919 * Enums: tx_x4_credit_gen0_cl36RxEEEStates_c 2920 */ 2921 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_LINK_FAIL 5 2922 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WTF 4 2923 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_WAKE 3 2924 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_QUIET 2 2925 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_SLEEP 1 2926 #define tx_x4_credit_gen0_cl36RxEEEStates_c_RX_ACTIVE 0 2927 2928 /**************************************************************************** 2929 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_l 2930 */ 2931 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_LINK_FAIL 32 2932 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WTF 16 2933 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_WAKE 8 2934 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_QUIET 4 2935 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_SLEEP 2 2936 #define tx_x4_credit_gen0_cl49RxEEEStates_l_RX_ACTIVE 1 2937 2938 /**************************************************************************** 2939 * Enums: tx_x4_credit_gen0_cl49RxEEEStates_c 2940 */ 2941 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_LINK_FAIL 5 2942 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WTF 4 2943 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_WAKE 3 2944 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_QUIET 2 2945 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_SLEEP 1 2946 #define tx_x4_credit_gen0_cl49RxEEEStates_c_RX_ACTIVE 0 2947 2948 /**************************************************************************** 2949 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_l 2950 */ 2951 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_REFRESH 8 2952 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_QUIET 4 2953 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_SLEEP 2 2954 #define tx_x4_credit_gen0_cl48TxEEEStates_l_TX_ACTIVE 1 2955 2956 /**************************************************************************** 2957 * Enums: tx_x4_credit_gen0_cl48TxEEEStates_c 2958 */ 2959 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_REFRESH 3 2960 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_QUIET 2 2961 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_SLEEP 1 2962 #define tx_x4_credit_gen0_cl48TxEEEStates_c_TX_ACTIVE 0 2963 2964 /**************************************************************************** 2965 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_l 2966 */ 2967 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_LINK_FAIL 32 2968 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_WAKE 16 2969 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_QUIET 8 2970 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_DEACT 4 2971 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_SLEEP 2 2972 #define tx_x4_credit_gen0_cl48RxEEEStates_l_RX_ACTIVE 1 2973 2974 /**************************************************************************** 2975 * Enums: tx_x4_credit_gen0_cl48RxEEEStates_c 2976 */ 2977 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_LINK_FAIL 5 2978 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_WAKE 4 2979 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_QUIET 3 2980 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_DEACT 2 2981 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_SLEEP 1 2982 #define tx_x4_credit_gen0_cl48RxEEEStates_c_RX_ACTIVE 0 2983 2984 /**************************************************************************** 2985 * Enums: tx_x4_credit_gen0_IQP_Options 2986 */ 2987 #define tx_x4_credit_gen0_IQP_Options_i50uA 0 2988 #define tx_x4_credit_gen0_IQP_Options_i100uA 1 2989 #define tx_x4_credit_gen0_IQP_Options_i150uA 2 2990 #define tx_x4_credit_gen0_IQP_Options_i200uA 3 2991 #define tx_x4_credit_gen0_IQP_Options_i250uA 4 2992 #define tx_x4_credit_gen0_IQP_Options_i300uA 5 2993 #define tx_x4_credit_gen0_IQP_Options_i350uA 6 2994 #define tx_x4_credit_gen0_IQP_Options_i400uA 7 2995 #define tx_x4_credit_gen0_IQP_Options_i450uA 8 2996 #define tx_x4_credit_gen0_IQP_Options_i500uA 9 2997 #define tx_x4_credit_gen0_IQP_Options_i550uA 10 2998 #define tx_x4_credit_gen0_IQP_Options_i600uA 11 2999 #define tx_x4_credit_gen0_IQP_Options_i650uA 12 3000 #define tx_x4_credit_gen0_IQP_Options_i700uA 13 3001 #define tx_x4_credit_gen0_IQP_Options_i750uA 14 3002 #define tx_x4_credit_gen0_IQP_Options_i800uA 15 3003 3004 /**************************************************************************** 3005 * Enums: tx_x4_credit_gen0_IDriver_Options 3006 */ 3007 #define tx_x4_credit_gen0_IDriver_Options_v680mV 0 3008 #define tx_x4_credit_gen0_IDriver_Options_v730mV 1 3009 #define tx_x4_credit_gen0_IDriver_Options_v780mV 2 3010 #define tx_x4_credit_gen0_IDriver_Options_v830mV 3 3011 #define tx_x4_credit_gen0_IDriver_Options_v880mV 4 3012 #define tx_x4_credit_gen0_IDriver_Options_v930mV 5 3013 #define tx_x4_credit_gen0_IDriver_Options_v980mV 6 3014 #define tx_x4_credit_gen0_IDriver_Options_v1010mV 7 3015 #define tx_x4_credit_gen0_IDriver_Options_v1040mV 8 3016 #define tx_x4_credit_gen0_IDriver_Options_v1060mV 9 3017 #define tx_x4_credit_gen0_IDriver_Options_v1070mV 10 3018 #define tx_x4_credit_gen0_IDriver_Options_v1080mV 11 3019 #define tx_x4_credit_gen0_IDriver_Options_v1085mV 12 3020 #define tx_x4_credit_gen0_IDriver_Options_v1090mV 13 3021 #define tx_x4_credit_gen0_IDriver_Options_v1095mV 14 3022 #define tx_x4_credit_gen0_IDriver_Options_v1100mV 15 3023 3024 /**************************************************************************** 3025 * Enums: tx_x4_credit_gen0_operationModes 3026 */ 3027 #define tx_x4_credit_gen0_operationModes_XGXS 0 3028 #define tx_x4_credit_gen0_operationModes_XGXG_nCC 1 3029 #define tx_x4_credit_gen0_operationModes_Indlane_OS8 4 3030 #define tx_x4_credit_gen0_operationModes_IndLane_OS5 5 3031 #define tx_x4_credit_gen0_operationModes_PCI 7 3032 #define tx_x4_credit_gen0_operationModes_XGXS_nLQ 8 3033 #define tx_x4_credit_gen0_operationModes_XGXS_nLQnCC 9 3034 #define tx_x4_credit_gen0_operationModes_PBypass 10 3035 #define tx_x4_credit_gen0_operationModes_PBypass_nDSK 11 3036 #define tx_x4_credit_gen0_operationModes_ComboCoreMode 12 3037 #define tx_x4_credit_gen0_operationModes_Clocks_off 15 3038 3039 /**************************************************************************** 3040 * Enums: tx_x4_credit_gen0_synce_enum 3041 */ 3042 #define tx_x4_credit_gen0_synce_enum_SYNCE_NO_DIV 0 3043 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_7 1 3044 #define tx_x4_credit_gen0_synce_enum_SYNCE_DIV_11 2 3045 3046 /**************************************************************************** 3047 * Enums: tx_x4_credit_gen0_operationSpeeds 3048 */ 3049 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1_12p5 65 3050 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_12p5 64 3051 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_12p5 63 3052 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_12p5 62 3053 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_12p5 61 3054 #define tx_x4_credit_gen0_operationSpeeds_SPEED_4G_X1_10 60 3055 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_X1_10 59 3056 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_X1_10 58 3057 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_X1_10 57 3058 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1_10p3125 56 3059 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M_10p3125 55 3060 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M_10p3125 54 3061 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M_10p3125 53 3062 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X4 50 3063 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_KR1 49 3064 #define tx_x4_credit_gen0_operationSpeeds_SPEED_127G_X12 39 3065 #define tx_x4_credit_gen0_operationSpeeds_SPEED_120G_X12 38 3066 #define tx_x4_credit_gen0_operationSpeeds_SPEED_107G_X10 37 3067 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100G_CR10 36 3068 #define tx_x4_credit_gen0_operationSpeeds_SPEED_42G_X4 35 3069 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_CR4 34 3070 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_KR4 33 3071 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X2 32 3072 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CR2 31 3073 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_KR2 30 3074 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p6_X1 29 3075 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KR1 28 3076 #define tx_x4_credit_gen0_operationSpeeds_SPEED_40G_X4 27 3077 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X2 26 3078 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX2 25 3079 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_KR4 24 3080 #define tx_x4_credit_gen0_operationSpeeds_SPEED_31p5G_X4 23 3081 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15p75G_X2 22 3082 #define tx_x4_credit_gen0_operationSpeeds_SPEED_25p45G_X4 21 3083 #define tx_x4_credit_gen0_operationSpeeds_SPEED_12p7G_X2 20 3084 #define tx_x4_credit_gen0_operationSpeeds_SPEED_21G_X4 19 3085 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10p5G_X2 18 3086 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_X4 17 3087 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X2 16 3088 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX2 15 3089 #define tx_x4_credit_gen0_operationSpeeds_SPEED_20G_CX4 14 3090 #define tx_x4_credit_gen0_operationSpeeds_SPEED_16G_X4 13 3091 #define tx_x4_credit_gen0_operationSpeeds_SPEED_15G_X4 12 3092 #define tx_x4_credit_gen0_operationSpeeds_SPEED_13G_X4 11 3093 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_X4 10 3094 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_KX4 9 3095 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10G_CX4 8 3096 #define tx_x4_credit_gen0_operationSpeeds_SPEED_5G_X1 7 3097 #define tx_x4_credit_gen0_operationSpeeds_SPEED_2p5G_X1 6 3098 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_KX1 5 3099 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1G_CX1 4 3100 #define tx_x4_credit_gen0_operationSpeeds_SPEED_1000M 3 3101 #define tx_x4_credit_gen0_operationSpeeds_SPEED_100M 2 3102 #define tx_x4_credit_gen0_operationSpeeds_SPEED_10M 1 3103 3104 /**************************************************************************** 3105 * Enums: tx_x4_credit_gen0_actualSpeeds 3106 */ 3107 #define tx_x4_credit_gen0_actualSpeeds_dr_10M 0 3108 #define tx_x4_credit_gen0_actualSpeeds_dr_100M 1 3109 #define tx_x4_credit_gen0_actualSpeeds_dr_1G 2 3110 #define tx_x4_credit_gen0_actualSpeeds_dr_2p5G 3 3111 #define tx_x4_credit_gen0_actualSpeeds_dr_5G_X4 4 3112 #define tx_x4_credit_gen0_actualSpeeds_dr_6G_X4 5 3113 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG 6 3114 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_CX4 7 3115 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_HiG 8 3116 #define tx_x4_credit_gen0_actualSpeeds_dr_12p5G_X4 9 3117 #define tx_x4_credit_gen0_actualSpeeds_dr_13G_X4 10 3118 #define tx_x4_credit_gen0_actualSpeeds_dr_15G_X4 11 3119 #define tx_x4_credit_gen0_actualSpeeds_dr_16G_X4 12 3120 #define tx_x4_credit_gen0_actualSpeeds_dr_1G_KX 13 3121 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KX4 14 3122 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_KR 15 3123 #define tx_x4_credit_gen0_actualSpeeds_dr_5G 16 3124 #define tx_x4_credit_gen0_actualSpeeds_dr_6p4G 17 3125 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_X4 18 3126 #define tx_x4_credit_gen0_actualSpeeds_dr_21G_X4 19 3127 #define tx_x4_credit_gen0_actualSpeeds_dr_25G_X4 20 3128 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS 21 3129 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS 22 3130 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_HiG_DXGXS 23 3131 #define tx_x4_credit_gen0_actualSpeeds_dr_10p5G_DXGXS 24 3132 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_HiG_DXGXS 25 3133 #define tx_x4_credit_gen0_actualSpeeds_dr_12p773G_DXGXS 26 3134 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_XFI 27 3135 #define tx_x4_credit_gen0_actualSpeeds_dr_40G 28 3136 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_HiG_DXGXS 29 3137 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_DXGXS 30 3138 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_SFI 31 3139 #define tx_x4_credit_gen0_actualSpeeds_dr_31p5G 32 3140 #define tx_x4_credit_gen0_actualSpeeds_dr_32p7G 33 3141 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_SCR 34 3142 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_HiG_DXGXS_SCR 35 3143 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_DXGXS_SCR 36 3144 #define tx_x4_credit_gen0_actualSpeeds_dr_12G_R2 37 3145 #define tx_x4_credit_gen0_actualSpeeds_dr_10G_X2 38 3146 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_KR4 39 3147 #define tx_x4_credit_gen0_actualSpeeds_dr_40G_CR4 40 3148 #define tx_x4_credit_gen0_actualSpeeds_dr_100G_CR10 41 3149 #define tx_x4_credit_gen0_actualSpeeds_dr_15p75G_DXGXS 44 3150 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_KR2 57 3151 #define tx_x4_credit_gen0_actualSpeeds_dr_20G_CR2 58 3152 3153 /**************************************************************************** 3154 * Enums: tx_x4_credit_gen0_actualSpeedsMisc1 3155 */ 3156 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_2500BRCM_X1 16 3157 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X4 17 3158 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6000BRCM_X4 18 3159 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GHiGig_X4 19 3160 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10GBASE_CX4 20 3161 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12GHiGig_X4 21 3162 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_12p5GHiGig_X4 22 3163 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_13GHiGig_X4 23 3164 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_15GHiGig_X4 24 3165 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_16GHiGig_X4 25 3166 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_5000BRCM_X1 26 3167 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_6363BRCM_X1 27 3168 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_20GHiGig_X4 28 3169 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_21GHiGig_X4 29 3170 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_25p45GHiGig_X4 30 3171 #define tx_x4_credit_gen0_actualSpeedsMisc1_dr_10G_HiG_DXGXS 31 3172 3173 /**************************************************************************** 3174 * Enums: tx_x4_credit_gen0_IndLaneModes 3175 */ 3176 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div2 0 3177 #define tx_x4_credit_gen0_IndLaneModes_SWSDR_div1 1 3178 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div2 2 3179 #define tx_x4_credit_gen0_IndLaneModes_DWSDR_div1 3 3180 3181 /**************************************************************************** 3182 * Enums: tx_x4_credit_gen0_prbsSelect 3183 */ 3184 #define tx_x4_credit_gen0_prbsSelect_prbs7 0 3185 #define tx_x4_credit_gen0_prbsSelect_prbs15 1 3186 #define tx_x4_credit_gen0_prbsSelect_prbs23 2 3187 #define tx_x4_credit_gen0_prbsSelect_prbs31 3 3188 3189 /**************************************************************************** 3190 * Enums: tx_x4_credit_gen0_vcoDivider 3191 */ 3192 #define tx_x4_credit_gen0_vcoDivider_div32 0 3193 #define tx_x4_credit_gen0_vcoDivider_div36 1 3194 #define tx_x4_credit_gen0_vcoDivider_div40 2 3195 #define tx_x4_credit_gen0_vcoDivider_div42 3 3196 #define tx_x4_credit_gen0_vcoDivider_div48 4 3197 #define tx_x4_credit_gen0_vcoDivider_div50 5 3198 #define tx_x4_credit_gen0_vcoDivider_div52 6 3199 #define tx_x4_credit_gen0_vcoDivider_div54 7 3200 #define tx_x4_credit_gen0_vcoDivider_div60 8 3201 #define tx_x4_credit_gen0_vcoDivider_div64 9 3202 #define tx_x4_credit_gen0_vcoDivider_div66 10 3203 #define tx_x4_credit_gen0_vcoDivider_div68 11 3204 #define tx_x4_credit_gen0_vcoDivider_div70 12 3205 #define tx_x4_credit_gen0_vcoDivider_div80 13 3206 #define tx_x4_credit_gen0_vcoDivider_div92 14 3207 #define tx_x4_credit_gen0_vcoDivider_div100 15 3208 3209 /**************************************************************************** 3210 * Enums: tx_x4_credit_gen0_refClkSelect 3211 */ 3212 #define tx_x4_credit_gen0_refClkSelect_clk_25MHz 0 3213 #define tx_x4_credit_gen0_refClkSelect_clk_100MHz 1 3214 #define tx_x4_credit_gen0_refClkSelect_clk_125MHz 2 3215 #define tx_x4_credit_gen0_refClkSelect_clk_156p25MHz 3 3216 #define tx_x4_credit_gen0_refClkSelect_clk_187p5MHz 4 3217 #define tx_x4_credit_gen0_refClkSelect_clk_161p25Mhz 5 3218 #define tx_x4_credit_gen0_refClkSelect_clk_50Mhz 6 3219 #define tx_x4_credit_gen0_refClkSelect_clk_106p25Mhz 7 3220 3221 /**************************************************************************** 3222 * Enums: tx_x4_credit_gen0_aerMMDdevTypeSelect 3223 */ 3224 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_combo_core 0 3225 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PMA_PMD 1 3226 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PCS 3 3227 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_PHY 4 3228 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_DTE 5 3229 #define tx_x4_credit_gen0_aerMMDdevTypeSelect_CL73_AN 7 3230 3231 /**************************************************************************** 3232 * Enums: tx_x4_credit_gen0_aerMMDportSelect 3233 */ 3234 #define tx_x4_credit_gen0_aerMMDportSelect_ln0 0 3235 #define tx_x4_credit_gen0_aerMMDportSelect_ln1 1 3236 #define tx_x4_credit_gen0_aerMMDportSelect_ln2 2 3237 #define tx_x4_credit_gen0_aerMMDportSelect_ln3 3 3238 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1_2_3 511 3239 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln0_1 512 3240 #define tx_x4_credit_gen0_aerMMDportSelect_BCST_ln2_3 513 3241 3242 /**************************************************************************** 3243 * Enums: tx_x4_credit_gen0_firmwareModeSelect 3244 */ 3245 #define tx_x4_credit_gen0_firmwareModeSelect_DEFAULT 0 3246 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_OPT_LR 1 3247 #define tx_x4_credit_gen0_firmwareModeSelect_SFP_DAC 2 3248 #define tx_x4_credit_gen0_firmwareModeSelect_XLAUI 3 3249 #define tx_x4_credit_gen0_firmwareModeSelect_LONG_CH_6G 4 3250 3251 /**************************************************************************** 3252 * Enums: tx_x4_credit_gen0_tempIdxSelect 3253 */ 3254 #define tx_x4_credit_gen0_tempIdxSelect_LTE__22p9C 15 3255 #define tx_x4_credit_gen0_tempIdxSelect_LTE__12p6C 14 3256 #define tx_x4_credit_gen0_tempIdxSelect_LTE__3p0C 13 3257 #define tx_x4_credit_gen0_tempIdxSelect_LTE_6p7C 12 3258 #define tx_x4_credit_gen0_tempIdxSelect_LTE_16p4C 11 3259 #define tx_x4_credit_gen0_tempIdxSelect_LTE_26p6C 10 3260 #define tx_x4_credit_gen0_tempIdxSelect_LTE_36p3C 9 3261 #define tx_x4_credit_gen0_tempIdxSelect_LTE_46p0C 8 3262 #define tx_x4_credit_gen0_tempIdxSelect_LTE_56p2C 7 3263 #define tx_x4_credit_gen0_tempIdxSelect_LTE_65p9C 6 3264 #define tx_x4_credit_gen0_tempIdxSelect_LTE_75p6C 5 3265 #define tx_x4_credit_gen0_tempIdxSelect_LTE_85p3C 4 3266 #define tx_x4_credit_gen0_tempIdxSelect_LTE_95p5C 3 3267 #define tx_x4_credit_gen0_tempIdxSelect_LTE_105p2C 2 3268 #define tx_x4_credit_gen0_tempIdxSelect_LTE_114p9C 1 3269 #define tx_x4_credit_gen0_tempIdxSelect_LTE_125p1C 0 3270 3271 /**************************************************************************** 3272 * End of RDB defined Enums *******************************************/ 3273 #endif /* __PCS_ENUMS_H__ */