tqmod_cfg_seq.c (27851B)
1 /*---------------------------------------------------------------------- 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * Broadcom Corporation 8 * Proprietary and Confidential information 9 * All rights reserved 10 * This source file is the property of Broadcom Corporation, and 11 * may not be copied or distributed in any isomorphic form without the 12 * prior written consent of Broadcom Corporation. 13 *--------------------------------------------------------------------- 14 * File : tqmod_cfg_seq.c 15 * Description: c functions implementing Tier1s for TEMod Serdes Driver 16 *---------------------------------------------------------------------*/ 17 18 #include <phymod/phymod.h> 19 #include <phymod/phymod_system.h> 20 #include <phymod/chip/bcmi_qsgmiie_serdes_defs.h> 21 #include "tqmod_cfg_seq.h" 22 #include <phymod/phymod_util.h> 23 24 25 int tqmod_set_spd_intf(const phymod_access_t *pa, int speed) /* SET_SPD_INTF */ 26 { 27 BCMI_QSGMIIE_SERDES_MIICONTROLr_t reg_mii_ctrl; 28 29 BCMI_QSGMIIE_SERDES_MIICONTROLr_CLR(reg_mii_ctrl); 30 BCMI_QSGMIIE_SERDES_READ_MIICONTROLr(pa, ®_mii_ctrl); 31 32 switch(speed){ 33 case 10: 34 BCMI_QSGMIIE_SERDES_MIICONTROLr_MANUAL_SPEED_0f_SET(reg_mii_ctrl, 0); 35 BCMI_QSGMIIE_SERDES_MIICONTROLr_MANUAL_SPEED_1f_SET(reg_mii_ctrl, 0); 36 break; 37 case 100: 38 BCMI_QSGMIIE_SERDES_MIICONTROLr_MANUAL_SPEED_0f_SET(reg_mii_ctrl, 1); 39 BCMI_QSGMIIE_SERDES_MIICONTROLr_MANUAL_SPEED_1f_SET(reg_mii_ctrl, 0); 40 break; 41 case 1000: 42 BCMI_QSGMIIE_SERDES_MIICONTROLr_MANUAL_SPEED_0f_SET(reg_mii_ctrl, 0); 43 BCMI_QSGMIIE_SERDES_MIICONTROLr_MANUAL_SPEED_1f_SET(reg_mii_ctrl, 1); 44 break; 45 default: 46 break; 47 } 48 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_WRITE_MIICONTROLr(pa,reg_mii_ctrl)); 49 50 return PHYMOD_E_NONE; 51 } 52 53 54 55 /** 56 @brief Initialize PMD. 57 @param pa handle to current phymod_access_t 58 @param pmd_touched Indicates this PMD was previously initialized for another 59 port in the same core. 60 @param uc_active Actually means PMD config. will come from PCS and not TMod 61 @returns SOC_E_NONE upon success, SOC_E_ERROR else. 62 @details Per Port PMD Init 63 */ 64 65 int tqmod_init_pmd_qsgmii(const phymod_access_t *pa, int pmd_active, int uc_active) /* INIT_PMD */ 66 { 67 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_t reg_misc1_ctrl; 68 BCMI_QSGMIIE_SERDES_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwrdwn_ctrl; 69 BCMI_QSGMIIE_SERDES_DIG_TOP_USER_CTL0r_t reg_usr_ctrl; 70 BCMI_QSGMIIE_SERDES_PLL_CAL_CTL7r_t reg_pll_cal_ctrl; 71 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_t reg_osr_mode_ctrl; 72 BCMI_QSGMIIE_SERDES_PMD_X4_OVRRr_t reg_pmd_overr_ctrl; 73 74 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_CLR(reg_misc1_ctrl); 75 BCMI_QSGMIIE_SERDES_READ_TXFIR_MISC_CTL1r(pa, ®_misc1_ctrl); 76 BCMI_QSGMIIE_SERDES_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwrdwn_ctrl); 77 BCMI_QSGMIIE_SERDES_READ_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pa, ®_pwrdwn_ctrl); 78 BCMI_QSGMIIE_SERDES_DIG_TOP_USER_CTL0r_CLR(reg_usr_ctrl); 79 BCMI_QSGMIIE_SERDES_READ_DIG_TOP_USER_CTL0r(pa, ®_usr_ctrl); 80 BCMI_QSGMIIE_SERDES_PLL_CAL_CTL7r_CLR(reg_pll_cal_ctrl); 81 BCMI_QSGMIIE_SERDES_READ_PLL_CAL_CTL7r(pa, ®_pll_cal_ctrl); 82 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode_ctrl); 83 BCMI_QSGMIIE_SERDES_READ_CKRST_OSR_MODE_CTLr(pa, ®_osr_mode_ctrl); 84 BCMI_QSGMIIE_SERDES_PMD_X4_OVRRr_CLR(reg_pmd_overr_ctrl); 85 BCMI_QSGMIIE_SERDES_READ_PMD_X4_OVRRr(pa, ®_pmd_overr_ctrl); 86 87 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_DP_RESET_TX_DISABLE_DISf_SET(reg_misc1_ctrl, 1); 88 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_TXFIR_MISC_CTL1r(pa, reg_misc1_ctrl)); 89 90 BCMI_QSGMIIE_SERDES_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwrdwn_ctrl, 1); 91 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pa, reg_pwrdwn_ctrl)); 92 93 94 if (pmd_active == 0) { 95 if(uc_active == 1){ 96 BCMI_QSGMIIE_SERDES_DIG_TOP_USER_CTL0r_UC_ACTIVEf_SET(reg_usr_ctrl, 1); 97 BCMI_QSGMIIE_SERDES_DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 98 /* release reset to pll data path. TBD need for all lanes and uc_active set */ 99 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_WRITE_DIG_TOP_USER_CTL0r(pa, reg_usr_ctrl)); 100 } else{ 101 BCMI_QSGMIIE_SERDES_DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg_usr_ctrl, 1); 102 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_DIG_TOP_USER_CTL0r(pa, reg_usr_ctrl)); 103 } 104 } 105 106 /* set vco at 10G */ 107 108 BCMI_QSGMIIE_SERDES_PLL_CAL_CTL7r_RESCAL_FRC_VALf_SET(reg_pll_cal_ctrl, 0x9); 109 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_PLL_CAL_CTL7r(pa, reg_pll_cal_ctrl)); 110 /* 111 if( pc->verbosity) 112 printf("%-22s: plldiv:%d data:%x\n", __func__, pc->plldiv, data); 113 114 if( pc->verbosity) 115 printf("%-22s: main0_setup=%x\n", __func__, data); 116 */ 117 118 /* set OS2 mode */ 119 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode_ctrl,1); 120 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_CKRST_OSR_MODE_CTLr(pa, reg_osr_mode_ctrl)); 121 122 /* Clear pmd_control reset by setting PMD tx_disable override enable*/ 123 BCMI_QSGMIIE_SERDES_PMD_X4_OVRRr_TX_DISABLE_OENf_SET(reg_pmd_overr_ctrl,1); 124 BCMI_QSGMIIE_SERDES_WRITE_PMD_X4_OVRRr(pa, reg_pmd_overr_ctrl); 125 126 return PHYMOD_E_NONE; 127 } 128 129 /** 130 @brief Select the ILKN path and bypass TSCE PCS 131 @param pa handle to current phymod_access_t 132 @returns The value SOC_E_NONE upon successful completion 133 @details This will enable ILKN path. PCS is set to bypass to relinquish PMD 134 control. Expect PMD to be programmed elsewhere. If we need the QSGMII PCS expect 135 the QSGMII to be already programmed at the port layer. If not, we will feed 136 garbage to the ILKN path. 137 138 <B>How to call:</B><br> 139 <p>Call directly or via #temod_tier1_selector() with enum INIT_PCS_ILKN</p> 140 */ 141 int tqmod_init_pcs_ilkn(const phymod_access_t *pa) /* INIT_PCS */ 142 { 143 BCMI_QSGMIIE_SERDES_SC_X4_BYPASSr_t reg_bypass_ctrl; 144 BCMI_QSGMIIE_SERDES_ILKN_CTL0r_t reg_serdes_ilkn_ctrl; 145 146 BCMI_QSGMIIE_SERDES_SC_X4_BYPASSr_CLR(reg_bypass_ctrl); 147 BCMI_QSGMIIE_SERDES_READ_SC_X4_BYPASSr(pa, ®_bypass_ctrl); 148 BCMI_QSGMIIE_SERDES_ILKN_CTL0r_CLR(reg_serdes_ilkn_ctrl); 149 /*BCMI_QSGMIIE_SERDES_READ_ILKN_CTL0r(pa, ®_serdes_ilkn_ctrl);*/ 150 151 BCMI_QSGMIIE_SERDES_SC_X4_BYPASSr_SC_BYPASSf_SET(reg_bypass_ctrl, 1); 152 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_SC_X4_BYPASSr(pa, reg_bypass_ctrl)); 153 154 BCMI_QSGMIIE_SERDES_ILKN_CTL0r_ILKN_SELf_SET(reg_serdes_ilkn_ctrl, 1); 155 BCMI_QSGMIIE_SERDES_ILKN_CTL0r_CREDIT_ENf_SET(reg_serdes_ilkn_ctrl, 1); 156 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_ILKN_CTL0r(pa, reg_serdes_ilkn_ctrl)); 157 158 return PHYMOD_E_NONE; 159 } 160 161 /** 162 @brief Get link status 163 @param pa handle to current phymod_access_t 164 @returns The value SOC_E_NONE upon successful completion 165 @details This will provide link status 166 <B>How to call:</B><br> 167 <p>Call directly or via #temod_tier1_selector() with enum GET_PCS_LINK_STATUS</p> 168 */ 169 int tqmod_get_pcs_link_status(const phymod_access_t *pa, uint32_t *link) 170 { 171 BCMI_QSGMIIE_SERDES_MIISTATUSr_t reg_miistatus; 172 173 BCMI_QSGMIIE_SERDES_MIISTATUSr_CLR(reg_miistatus); 174 BCMI_QSGMIIE_SERDES_READ_MIISTATUSr(pa, ®_miistatus); 175 *link = BCMI_QSGMIIE_SERDES_MIISTATUSr_LINK_STATUSf_GET(reg_miistatus); 176 177 return PHYMOD_E_NONE; 178 } 179 180 /** 181 @brief Get actual speed 182 @param pa handle to current phymod_access_t 183 @returns The value SOC_E_NONE upon successful completion 184 @details This will provide actual speed 185 <B>How to call:</B><br> 186 <p>Call directly or via #temod_tier1_selector() with enum GET_PCS_LINK_STATUS</p> 187 */ 188 189 int tqmod_speed_id_get(const phymod_access_t *pa, int *speed_id) 190 { 191 BCMI_QSGMIIE_SERDES_R1000XSTATUS1r_t reg_1000x_status; 192 BCMI_QSGMIIE_SERDES_R1000XSTATUS1r_CLR(reg_1000x_status); 193 BCMI_QSGMIIE_SERDES_READ_R1000XSTATUS1r(pa, ®_1000x_status); 194 *speed_id = BCMI_QSGMIIE_SERDES_R1000XSTATUS1r_SPEED_STATUSf_GET(reg_1000x_status); 195 return PHYMOD_E_NONE; 196 } 197 198 /** 199 @brief Enable/disable port 200 @param pa handle to current phymod_access_t 201 @returns The value SOC_E_NONE upon successful completion 202 @details This will set/unset powersave mode for each port 203 <B>How to call:</B><br> 204 */ 205 206 int tqmod_lane_enable_set(const phymod_access_t *pa, int enable) 207 { 208 BCMI_QSGMIIE_SERDES_MIICONTROLr_t reg_mii_ctrl; 209 210 BCMI_QSGMIIE_SERDES_MIICONTROLr_CLR(reg_mii_ctrl); 211 BCMI_QSGMIIE_SERDES_READ_MIICONTROLr(pa, ®_mii_ctrl); 212 if(enable) 213 BCMI_QSGMIIE_SERDES_MIICONTROLr_PWRDWN_SWf_SET(reg_mii_ctrl, 0); 214 else 215 BCMI_QSGMIIE_SERDES_MIICONTROLr_PWRDWN_SWf_SET(reg_mii_ctrl, 1); 216 217 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_WRITE_MIICONTROLr(pa,reg_mii_ctrl)); 218 return PHYMOD_E_NONE; 219 } 220 221 222 /** 223 @brief Set Per lane OS mode set in PMD 224 @param pa handle to current phymod_access_t 225 @param os_mode over sample rate. 226 @returns The value PHYMOD_E_NONE upon successful completion 227 @details Per Port PMD Init 228 229 */ 230 int tqmod_pmd_osmode_set(const phymod_access_t *pa, int os_mode) /* INIT_PMD */ 231 { 232 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_t reg_osr_mode; 233 234 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_CLR(reg_osr_mode); 235 BCMI_QSGMIIE_SERDES_READ_CKRST_OSR_MODE_CTLr(pa, ®_osr_mode); 236 237 /*os_mode = 0x0; */ /* 0= OS MODE 1; 1= OS MODE 2; 2=OS MODE 3; 238 3=OS MODE 3.3; 4=OS MODE 4; 5=OS MODE 5; 239 6=OS MODE 8; 7=OS MODE 8.25; 8: OS MODE 10*/ 240 /*if(os_mode & 0x80000000) {*/ 241 os_mode = (os_mode) & 0x0000ffff; 242 /*}*/ 243 244 /* set OS2 mode */ 245 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_OSR_MODE_FRCf_SET(reg_osr_mode,1); 246 BCMI_QSGMIIE_SERDES_CKRST_OSR_MODE_CTLr_OSR_MODE_FRC_VALf_SET(reg_osr_mode, os_mode); 247 248 PHYMOD_IF_ERR_RETURN 249 (BCMI_QSGMIIE_SERDES_WRITE_CKRST_OSR_MODE_CTLr(pa, reg_osr_mode)); 250 251 return PHYMOD_E_NONE; 252 } 253 254 /*! 255 @brief Controls the setting/resetting of autoneg advertisement registers. 256 @param pa handle to current phymod_access_t 257 @param os_mode over sample rate. 258 @returns The value PHYMOD_E_NONE upon successful completion 259 @details This function modifies the following registers: 260 */ 261 262 int tqmod_autoneg_set(const phymod_access_t *pa, int *an_en) /* AUTONEG_SET */ 263 { 264 BCMI_QSGMIIE_SERDES_MIICONTROLr_t reg_mii_ctrl; 265 266 BCMI_QSGMIIE_SERDES_MIICONTROLr_CLR(reg_mii_ctrl); 267 BCMI_QSGMIIE_SERDES_READ_MIICONTROLr(pa, ®_mii_ctrl); 268 269 BCMI_QSGMIIE_SERDES_MIICONTROLr_AUTONEG_ENABLEf_SET(reg_mii_ctrl, *an_en); 270 271 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_WRITE_MIICONTROLr(pa,reg_mii_ctrl)); 272 return PHYMOD_E_NONE; 273 } 274 275 /** 276 @brief PMD per lane reset 277 @param pa handle to current TSCE context (#const phymod_access_t) 278 @returns The value PHYMOD_E_NONE upon successful completion 279 @details Per lane PMD ln_rst and ln_dp_rst by writing to PMD_X4_CONTROL in pcs space 280 */ 281 int tqmod_pmd_x4_reset(const phymod_access_t *pa) /* PMD_X4_RESET */ 282 { 283 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_t reg_pmd_x4_ctrl; 284 285 /*TQMOD_DBG_IN_FUNC_INFO(pa);*/ 286 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 287 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 288 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,0); 289 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_PMD_X4_CTLr(pa, reg_pmd_x4_ctrl)); 290 291 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_CLR(reg_pmd_x4_ctrl); 292 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_LN_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 293 BCMI_QSGMIIE_SERDES_PMD_X4_CTLr_LN_DP_H_RSTBf_SET(reg_pmd_x4_ctrl,1); 294 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_PMD_X4_CTLr(pa, reg_pmd_x4_ctrl)); 295 296 return PHYMOD_E_NONE; 297 } 298 299 300 301 /** 302 @brief rx lane reset and enable of any particular lane 303 @param pa handle to current TSCE context (#const phymod_access_t) 304 @param enable to reset the lane. 305 @returns The value PHYMOD_E_NONE upon successful completion. 306 307 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 308 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 309 read back RSTB_LANE. 310 311 */ 312 int tqmod_rx_lane_control_set(const phymod_access_t* pa, int enable) /* RX_LANE_CONTROL */ 313 { 314 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_t reg_pma_ctrl; 315 phymod_access_t pa_copy; 316 int start_lane, num_lane; 317 318 PHYMOD_MEMCPY(&pa_copy, pa, sizeof(pa_copy)); 319 PHYMOD_IF_ERR_RETURN 320 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 321 322 pa_copy.lane_mask = 0x1 << (start_lane/4); 323 324 /*TQMOD_DBG_IN_FUNC_INFO(pa);*/ 325 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 326 if (enable) { 327 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 328 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_RX_X4_PMA_CTL0r(&pa_copy, reg_pma_ctrl)); 329 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 330 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_RSTB_LANEf_SET(reg_pma_ctrl, 1); 331 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_RX_X4_PMA_CTL0r(&pa_copy, reg_pma_ctrl)); 332 } else { 333 /* bit set to 0 for disabling RXP */ 334 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_RSTB_LANEf_SET( reg_pma_ctrl, 0); 335 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_RX_X4_PMA_CTL0r(&pa_copy, reg_pma_ctrl)); 336 } 337 return PHYMOD_E_NONE; 338 } 339 340 /** 341 @brief rx lane reset and enable of any particular lane 342 @param pa handle to current TSCE context (#const phymod_access_t) 343 @param get the configured reset of the lane. 344 @returns The value PHYMOD_E_NONE upon successful completion. 345 346 This function enables/disables rx lane (RSTB_LANE) or read back control bit for 347 that based on per_lane_control being 1 or 0. If per_lane_control is 0xa, only 348 read back RSTB_LANE. 349 350 */ 351 int tqmod_rx_lane_control_get(const phymod_access_t* pa, int *enable) 352 { 353 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_t reg_pma_ctrl; 354 phymod_access_t pa_copy; 355 int start_lane, num_lane; 356 357 PHYMOD_MEMCPY(&pa_copy, pa, sizeof(pa_copy)); 358 PHYMOD_IF_ERR_RETURN 359 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 360 361 pa_copy.lane_mask = 0x1 << (start_lane/4); 362 363 /*TQMOD_DBG_IN_FUNC_INFO(pa);*/ 364 BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_CLR(reg_pma_ctrl); 365 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_READ_RX_X4_PMA_CTL0r(&pa_copy, ®_pma_ctrl)); 366 *enable = BCMI_QSGMIIE_SERDES_RX_X4_PMA_CTL0r_RSTB_LANEf_GET( reg_pma_ctrl); 367 368 return PHYMOD_E_NONE; 369 } 370 371 372 373 /*! 374 @brief tx lane reset and enable of any particular lane 375 @param pa handle to current TSCE context (#const phymod_access_t) 376 @param enable Enable/disable traffic or reset/unreset lane 377 @param tx_dis_type enum type #txq_lane_disable_type_t 378 @returns The value PHYMOD_E_NONE upon successful completion. 379 @details 380 This function is used to reset tx lane and enable/disable tx lane of any 381 transmit lane. Set enable to enable the TX_LANE (1) or disable the TX lane (0). 382 When diable TX lane, two types of operations are invoked independently. 383 384 If enable bit [7:4] = 1, only traffic is disabled. 385 (TEMOD_TX_LANE_TRAFFIC =0x10) 386 If bit [7:4] = 2, only reset function is invoked. 387 (TEMOD_TX_LANE_RESET = 0x20) 388 */ 389 int tqmod_tx_lane_control_set(const phymod_access_t* pa, txq_lane_disable_type_t tx_dis_type) /* TX_LANE_CONTROL */ 390 { 391 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_t reg_misc_ctrl; 392 phymod_access_t pa_copy; 393 int start_lane, num_lane; 394 395 PHYMOD_MEMCPY(&pa_copy, pa, sizeof(pa_copy)); 396 PHYMOD_IF_ERR_RETURN 397 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 398 399 pa_copy.lane_mask = 0x1 << (start_lane/4); 400 401 /*TQMOD_DBG_IN_FUNC_INFO(pa);*/ 402 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_CLR(reg_misc_ctrl); 403 /*TEMOD_DBG_IN_FUNC_VIN_INFO(pa,("enable: %d, tx_dis_type: %d", enable, tx_dis_type));*/ 404 405 switch(tx_dis_type) { 406 case TQMOD_TX_LANE_RESET: 407 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 408 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 409 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_CLR(reg_misc_ctrl); 410 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 411 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 412 break; 413 case TQMOD_TX_LANE_TRAFFIC_ENABLE: 414 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 415 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 416 break; 417 case TQMOD_TX_LANE_TRAFFIC_DISABLE: 418 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 419 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 420 break; 421 case TQMOD_TX_LANE_RESET_TRAFFIC_ENABLE: 422 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 1); 423 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 424 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_CLR(reg_misc_ctrl); 425 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 1); 426 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 427 break; 428 case TQMOD_TX_LANE_RESET_TRAFFIC_DISABLE: 429 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_RSTB_TX_LANEf_SET(reg_misc_ctrl, 0); 430 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 431 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_CLR(reg_misc_ctrl); 432 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_ENABLE_TX_LANEf_SET(reg_misc_ctrl, 0); 433 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_MODIFY_TX_X4_MISCr(&pa_copy, reg_misc_ctrl)); 434 break; 435 default: 436 break; 437 } 438 439 440 return PHYMOD_E_NONE; 441 } 442 443 /*! 444 @brief tx lane reset and enable of any particular lane 445 @param pc handle to current TSCE context (#PHYMOD_ST) 446 @param *reset returns the tx_reset configured. 447 @param *enable returns the tx_enable configured. 448 @returns The value PHYMOD_E_NONE upon successful completion. 449 @details 450 returns the configured tx lane reset and enable of any particular lane 451 */ 452 int tqmod_tx_lane_control_get(PHYMOD_ST* pa, int *reset, int *enable) /* TX_LANE_CONTROL_GET */ 453 { 454 phymod_access_t pa_copy; 455 int start_lane, num_lane; 456 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_t reg_misc_ctrl; 457 458 PHYMOD_MEMCPY(&pa_copy, pa, sizeof(pa_copy)); 459 PHYMOD_IF_ERR_RETURN 460 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 461 462 pa_copy.lane_mask = 0x1 << (start_lane/4); 463 464 BCMI_QSGMIIE_SERDES_TX_X4_MISCr_CLR(reg_misc_ctrl); 465 466 467 PHYMOD_IF_ERR_RETURN (BCMI_QSGMIIE_SERDES_READ_TX_X4_MISCr(&pa_copy, ®_misc_ctrl)); 468 *reset = BCMI_QSGMIIE_SERDES_TX_X4_MISCr_RSTB_TX_LANEf_GET(reg_misc_ctrl); 469 *enable = BCMI_QSGMIIE_SERDES_TX_X4_MISCr_ENABLE_TX_LANEf_GET(reg_misc_ctrl); 470 471 return PHYMOD_E_NONE; 472 } 473 474 /** 475 @brief Controls port TX squelch 476 @param pc handle to current QSGMII context (#PHYMOD_ST) 477 @param enable is the control to TX squelch 478 @returns The value PHYMOD_E_NONE upon successful completion. 479 @details Controls port TX squelch 480 */ 481 int tqmod_tx_squelch_set(PHYMOD_ST *pc, int enable) 482 { 483 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_t tx_misc_ctl; 484 phymod_access_t pa_copy; 485 int start_lane, num_lane; 486 487 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 488 PHYMOD_IF_ERR_RETURN 489 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 490 491 pa_copy.lane_mask = 0x1 << (start_lane/4); 492 493 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 494 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_READ_TXFIR_MISC_CTL1r(&pa_copy, &tx_misc_ctl)); 495 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_SET(tx_misc_ctl, enable); 496 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_MODIFY_TXFIR_MISC_CTL1r(&pa_copy, tx_misc_ctl)); 497 498 return PHYMOD_E_NONE; 499 } 500 501 /** 502 @brief Get port TX squelch control settings 503 @param pc handle to current QSGMII context (#PHYMOD_ST) 504 @param val Receiver for status of TX squelch 505 @returns The value PHYMOD_E_NONE upon successful completion. 506 @details Get port TX squelch control settings 507 */ 508 int tqmod_tx_squelch_get(PHYMOD_ST *pc, int *val) 509 { 510 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_t tx_misc_ctl; 511 phymod_access_t pa_copy; 512 int start_lane, num_lane; 513 514 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 515 PHYMOD_IF_ERR_RETURN 516 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 517 518 pa_copy.lane_mask = 0x1 << (start_lane/4); 519 520 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_CLR(tx_misc_ctl); 521 522 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_READ_TXFIR_MISC_CTL1r(&pa_copy, &tx_misc_ctl)); 523 *val = BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_SDK_TX_DISABLEf_GET(tx_misc_ctl); 524 525 return PHYMOD_E_NONE; 526 } 527 528 /** 529 @brief Controls port RX squelch 530 @param pc handle to current QSGMII context (#PHYMOD_ST) 531 @param enable is the control to RX squelch 532 @returns The value PHYMOD_E_NONE upon successful completion. 533 @details Controls port RX squelch 534 */ 535 int tqmod_rx_squelch_set(PHYMOD_ST *pc, int enable) 536 { 537 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_t sigdet_ctl; 538 phymod_access_t pa_copy; 539 int start_lane, num_lane; 540 541 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 542 PHYMOD_IF_ERR_RETURN 543 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 544 545 pa_copy.lane_mask = 0x1 << (start_lane/4); 546 547 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_CLR(sigdet_ctl); 548 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_READ_SIGDET_CTL1r(&pa_copy, &sigdet_ctl)); 549 if(enable){ 550 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 1); 551 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 552 } else { 553 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(sigdet_ctl, 0); 554 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(sigdet_ctl, 0); 555 } 556 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_MODIFY_SIGDET_CTL1r(&pa_copy, sigdet_ctl)); 557 558 return PHYMOD_E_NONE; 559 } 560 561 562 /** 563 @brief Gets port RX squelch settings 564 @param pc handle to current QSGMII context (#PHYMOD_ST) 565 @param val Receiver for status of RX squelch 566 @returns The value PHYMOD_E_NONE upon successful completion. 567 @details Gets port RX squelch settings 568 */ 569 int tqmod_rx_squelch_get(PHYMOD_ST *pc, int *val) 570 { 571 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_t sigdet_ctl; 572 phymod_access_t pa_copy; 573 int start_lane, num_lane; 574 575 PHYMOD_MEMCPY(&pa_copy, pc, sizeof(pa_copy)); 576 PHYMOD_IF_ERR_RETURN 577 (phymod_util_lane_config_get(&pa_copy, &start_lane, &num_lane)); 578 579 pa_copy.lane_mask = 0x1 << (start_lane/4); 580 581 BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_CLR(sigdet_ctl); 582 583 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_READ_SIGDET_CTL1r(&pa_copy, &sigdet_ctl)); 584 *val = BCMI_QSGMIIE_SERDES_SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(sigdet_ctl); 585 586 return PHYMOD_E_NONE; 587 } 588 589 590 /** 591 @brief Gets the TX And RX Polarity 592 @param pa handle to current TSCE context (#const phymod_access_t) 593 @param tx_polarity Receive Polarity for TX side 594 @param rx_polarity Receive Polarity for RX side 595 @returns The value PHYMOD_E_NONE upon successful completion. 596 @details Gets the TX And RX Polarity 597 */ 598 int tqmod_tx_rx_polarity_get ( const phymod_access_t *pa, uint32_t* tx_polarity, uint32_t* rx_polarity) 599 { 600 BCMI_QSGMIIE_SERDES_TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 601 BCMI_QSGMIIE_SERDES_TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 602 603 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_READ_TLB_TX_TLB_TX_MISC_CFGr(pa, &tx_pol_inv)); 604 *tx_polarity = BCMI_QSGMIIE_SERDES_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pol_inv); 605 606 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_READ_TLB_RX_TLB_RX_MISC_CFGr(pa, &rx_pol_inv)); 607 *rx_polarity = BCMI_QSGMIIE_SERDES_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pol_inv); 608 609 return PHYMOD_E_NONE; 610 } 611 612 /** 613 @brief Sets the TX And RX Polarity 614 @param pa handle to current TSCE context (#const phymod_access_t) 615 @param tx_polarity Control Polarity for TX side 616 @param rx_polarity Control Polarity for RX side 617 @returns The value PHYMOD_E_NONE upon successful completion. 618 @details Sets the TX And RX Polarity 619 */ 620 int tqmod_tx_rx_polarity_set ( const phymod_access_t *pa, uint32_t tx_polarity, uint32_t rx_polarity) 621 { 622 BCMI_QSGMIIE_SERDES_TLB_TX_TLB_TX_MISC_CFGr_t tx_pol_inv; 623 BCMI_QSGMIIE_SERDES_TLB_RX_TLB_RX_MISC_CFGr_t rx_pol_inv; 624 625 BCMI_QSGMIIE_SERDES_TLB_TX_TLB_TX_MISC_CFGr_CLR(tx_pol_inv); 626 BCMI_QSGMIIE_SERDES_TLB_RX_TLB_RX_MISC_CFGr_CLR(rx_pol_inv); 627 628 BCMI_QSGMIIE_SERDES_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pol_inv, tx_polarity); 629 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_MODIFY_TLB_TX_TLB_TX_MISC_CFGr(pa, tx_pol_inv)); 630 631 BCMI_QSGMIIE_SERDES_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pol_inv, rx_polarity); 632 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_MODIFY_TLB_RX_TLB_RX_MISC_CFGr(pa, rx_pol_inv)); 633 634 return PHYMOD_E_NONE; 635 } 636 637 638 /** 639 @brief Enable TX 640 @param pa handle to current TSCE context (#const phymod_access_t) 641 @param tx_polarity Control Polarity for TX side 642 @param rx_polarity Control Polarity for RX side 643 @returns The value PHYMOD_E_NONE upon successful completion. 644 @details Sets tx disable bit to 0 (enable tx path) 645 */ 646 int tqmod_txfir_tx_disable_set(const phymod_access_t *pa) 647 { 648 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_t txfir_misc_ctrl1; 649 650 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_CLR(txfir_misc_ctrl1); 651 652 653 BCMI_QSGMIIE_SERDES_TXFIR_MISC_CTL1r_PMD_TX_DISABLE_PIN_DISf_SET(txfir_misc_ctrl1, 1); 654 PHYMOD_IF_ERR_RETURN(BCMI_QSGMIIE_SERDES_WRITE_TXFIR_MISC_CTL1r(pa, txfir_misc_ctrl1)); 655 656 return PHYMOD_E_NONE; 657 } 658 659 /** 660 @brief EEE Control Set 661 @param pc handle to current TSCE context (#PHYMOD_ST) 662 @param set enable, for EEE control 663 @returns The value PHYMOD_E_NONE upon successful completion 664 @details EEE Control 665 NOT SUPPORTED 666 667 */ 668 int tqmod_eee_control_set(PHYMOD_ST* pc, int enable) 669 { 670 PHYMOD_DEBUG_ERROR(("EEE NOT SUPPORTED IN QSGMIIE\n")); 671 return PHYMOD_E_FAIL; 672 } 673 674 /** 675 @brief PCS lane swap set 676 @param pc handle to current TSCE context (#PHYMOD_ST) 677 @param pcs_swap swap lane. 678 @returns The value PHYMOD_E_NONE upon successful completion 679 @details pcs_swap Tx lane Rx swap. 680 */ 681 682 int tqmod_pcs_lane_swap (PHYMOD_ST* pc, int pcs_swap) { 683 684 RXLNSWAPr_t rxLnSwap; 685 TXLNSWAPr_t txLnSwap; 686 687 RXLNSWAPr_CLR(rxLnSwap); 688 TXLNSWAPr_CLR(txLnSwap); 689 690 READ_RXLNSWAPr(pc, &rxLnSwap); 691 READ_TXLNSWAPr(pc, &txLnSwap); 692 693 RXLNSWAPr_RX_LNSWAP_FORCE3f_SET(rxLnSwap, ((pcs_swap >> 0)& 3)); 694 RXLNSWAPr_RX_LNSWAP_FORCE2f_SET(rxLnSwap, ((pcs_swap >> 2)& 3)); 695 RXLNSWAPr_RX_LNSWAP_FORCE1f_SET(rxLnSwap, ((pcs_swap >> 4)& 3)); 696 RXLNSWAPr_RX_LNSWAP_FORCE0f_SET(rxLnSwap, ((pcs_swap >> 6)& 3)); 697 698 RXLNSWAPr_RX_LNSWAP_FORCE_ENf_SET(rxLnSwap, 1); 699 RXLNSWAPr_RX_LNSWAP_LINK_ENf_SET(rxLnSwap, 1); 700 RXLNSWAPr_RX_LNSWAP_ENf_SET(rxLnSwap, 1); 701 702 TXLNSWAPr_TX_LNSWAP_FORCE3f_SET(txLnSwap, ((pcs_swap >> 0)& 3)); 703 TXLNSWAPr_TX_LNSWAP_FORCE2f_SET(txLnSwap, ((pcs_swap >> 2)& 3)); 704 TXLNSWAPr_TX_LNSWAP_FORCE1f_SET(txLnSwap, ((pcs_swap >> 4)& 3)); 705 TXLNSWAPr_TX_LNSWAP_FORCE0f_SET(txLnSwap, ((pcs_swap >> 6)& 3)); 706 707 TXLNSWAPr_TX_LNSWAP_ENf_SET(txLnSwap, 1); 708 709 WRITE_RXLNSWAPr(pc, rxLnSwap); 710 WRITE_TXLNSWAPr(pc, txLnSwap); 711 712 return PHYMOD_E_NONE; 713 } 714 715 /** 716 @brief PCS lane swap get 717 @param pc handle to current TSCE context (#PHYMOD_ST) 718 @param pcs_swap swap lane. 719 @returns The value PHYMOD_E_NONE upon successful completion 720 @details pcs_swap Tx lane Rx swap. 721 */ 722 723 int tqmod_pcs_lane_swap_get (PHYMOD_ST* pc, uint32_t *pcs_swap) { 724 725 int lnswap[4]; 726 RXLNSWAPr_t rxLnSwap; 727 728 RXLNSWAPr_CLR(rxLnSwap); 729 READ_RXLNSWAPr(pc, &rxLnSwap); 730 731 lnswap[3]=RXLNSWAPr_RX_LNSWAP_FORCE3f_GET(rxLnSwap); 732 lnswap[2]=RXLNSWAPr_RX_LNSWAP_FORCE2f_GET(rxLnSwap); 733 lnswap[1]=RXLNSWAPr_RX_LNSWAP_FORCE1f_GET(rxLnSwap); 734 lnswap[0]=RXLNSWAPr_RX_LNSWAP_FORCE0f_GET(rxLnSwap); 735 736 *pcs_swap=(lnswap[3] | (lnswap[2]<<2) | (lnswap[1]<<4) | (lnswap[0]<<6)); 737 738 return PHYMOD_E_NONE; 739 }