phy8806x_tsc_fields.h (207270B)
1 /************************************************************************************* 2 ************************************************************************************* 3 * * 4 * * 5 * Description : Register access macros for PHY8806X_TSC * 6 * * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 10 * No portions of this material may be reproduced in any form without * 11 * the written permission of: * 12 * Broadcom Corporation * 13 * 5300 California Avenue * 14 * Irvine, CA 92617 * 15 * * 16 * All information contained in this document is Broadcom Corporation * 17 * company private proprietary, and trade secret. * 18 */ 19 20 /** @file phy8806x_tsc_fields.h 21 * Register access macros for PHY8806X_TSC 22 */ 23 24 /* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */ 25 26 #ifndef PHY8806X_TSC_FIELDS_H 27 #define PHY8806X_TSC_FIELDS_H 28 #define __ERR &__err 29 30 #define rdc_ams_pll_cal_aux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 0, 12, __ERR) 31 #define wrc_ams_pll_cal_aux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0xf000, 12, wr_val) 32 #define rdc_ams_pll_cal_off() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 4, 15, __ERR) 33 #define wrc_ams_pll_cal_off(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0800, 11, wr_val) 34 #define rdc_ams_pll_imode_iclkidrv1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 5, 15, __ERR) 35 #define wrc_ams_pll_imode_iclkidrv1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0400, 10, wr_val) 36 #define rdc_ams_pll_imax_iclkidrv1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 6, 15, __ERR) 37 #define wrc_ams_pll_imax_iclkidrv1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0200, 9, wr_val) 38 #define rdc_ams_pll_imin_iclkidrv1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 7, 15, __ERR) 39 #define wrc_ams_pll_imin_iclkidrv1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0100, 8, wr_val) 40 #define rdc_ams_pll_spare_7_2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 8, 10, __ERR) 41 #define wrc_ams_pll_spare_7_2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x00fc, 2, wr_val) 42 #define rdc_ams_pll_set_clk4pcs() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd110, 14, 14, __ERR) 43 #define wrc_ams_pll_set_clk4pcs(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0003, 0, wr_val) 44 #define rdc_ams_pll_enable_ftune() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 0, 15, __ERR) 45 #define wrc_ams_pll_enable_ftune(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x8000, 15, wr_val) 46 #define rdc_ams_pll_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 1, 15, __ERR) 47 #define wrc_ams_pll_reset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x4000, 14, wr_val) 48 #define rdc_ams_pll_ivco() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 2, 13, __ERR) 49 #define wrc_ams_pll_ivco(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x3800, 11, wr_val) 50 #define rdc_ams_pll_vco_indicator() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 5, 15, __ERR) 51 #define wrc_ams_pll_vco_indicator(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0400, 10, wr_val) 52 #define rdc_ams_pll_vcoictrl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 6, 14, __ERR) 53 #define wrc_ams_pll_vcoictrl(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0300, 8, wr_val) 54 #define rdc_ams_pll_vco2_15g() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 8, 15, __ERR) 55 #define wrc_ams_pll_vco2_15g(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0080, 7, wr_val) 56 #define rdc_ams_pll_spare_22() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 9, 15, __ERR) 57 #define wrc_ams_pll_spare_22(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0040, 6, wr_val) 58 #define rdc_ams_pll_test_bg_opamp_bias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 10, 14, __ERR) 59 #define wrc_ams_pll_test_bg_opamp_bias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0030, 4, wr_val) 60 #define rdc_ams_pll_drv_hv_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 12, 15, __ERR) 61 #define wrc_ams_pll_drv_hv_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0008, 3, wr_val) 62 #define rdc_ams_pll_imode_ickgen() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 13, 15, __ERR) 63 #define wrc_ams_pll_imode_ickgen(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0004, 2, wr_val) 64 #define rdc_ams_pll_imax_ickgen() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 14, 15, __ERR) 65 #define wrc_ams_pll_imax_ickgen(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0002, 1, wr_val) 66 #define rdc_ams_pll_imin_ickgen() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd111, 15, 15, __ERR) 67 #define wrc_ams_pll_imin_ickgen(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0001, 0, wr_val) 68 #define rdc_ams_pll_imax_ick() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 0, 15, __ERR) 69 #define wrc_ams_pll_imax_ick(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x8000, 15, wr_val) 70 #define rdc_ams_pll_imode_ick() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 1, 15, __ERR) 71 #define wrc_ams_pll_imode_ick(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x4000, 14, wr_val) 72 #define rdc_ams_pll_imin_ick() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 2, 15, __ERR) 73 #define wrc_ams_pll_imin_ick(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x2000, 13, wr_val) 74 #define rdc_ams_pll_imax_icp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 3, 15, __ERR) 75 #define wrc_ams_pll_imax_icp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x1000, 12, wr_val) 76 #define rdc_ams_pll_imode_icp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 4, 15, __ERR) 77 #define wrc_ams_pll_imode_icp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0800, 11, wr_val) 78 #define rdc_ams_pll_imin_icp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 5, 15, __ERR) 79 #define wrc_ams_pll_imin_icp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0400, 10, wr_val) 80 #define rdc_ams_pll_imax_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 6, 15, __ERR) 81 #define wrc_ams_pll_imax_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0200, 9, wr_val) 82 #define rdc_ams_pll_imode_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 7, 15, __ERR) 83 #define wrc_ams_pll_imode_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0100, 8, wr_val) 84 #define rdc_ams_pll_imin_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 8, 15, __ERR) 85 #define wrc_ams_pll_imin_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0080, 7, wr_val) 86 #define rdc_ams_pll_refh_pll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 9, 15, __ERR) 87 #define wrc_ams_pll_refh_pll(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0040, 6, wr_val) 88 #define rdc_ams_pll_refl_pll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 10, 15, __ERR) 89 #define wrc_ams_pll_refl_pll(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0020, 5, wr_val) 90 #define rdc_ams_pll_iqp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 11, 12, __ERR) 91 #define wrc_ams_pll_iqp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x001e, 1, wr_val) 92 #define rdc_ams_pll_en_hrz() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd112, 15, 15, __ERR) 93 #define wrc_ams_pll_en_hrz(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0001, 0, wr_val) 94 #define rdc_ams_pll_test_rx() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 0, 15, __ERR) 95 #define wrc_ams_pll_test_rx(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x8000, 15, wr_val) 96 #define rdc_ams_pll_test_pll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 1, 15, __ERR) 97 #define wrc_ams_pll_test_pll(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x4000, 14, wr_val) 98 #define rdc_ams_pll_test_vc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 2, 15, __ERR) 99 #define wrc_ams_pll_test_vc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x2000, 13, wr_val) 100 #define rdc_ams_pll_test_vref() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 3, 15, __ERR) 101 #define wrc_ams_pll_test_vref(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x1000, 12, wr_val) 102 #define rdc_ams_pll_imax_iop() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 4, 15, __ERR) 103 #define wrc_ams_pll_imax_iop(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0800, 11, wr_val) 104 #define rdc_ams_pll_imode_iop() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 5, 15, __ERR) 105 #define wrc_ams_pll_imode_iop(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0400, 10, wr_val) 106 #define rdc_ams_pll_imin_iop() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 6, 15, __ERR) 107 #define wrc_ams_pll_imin_iop(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0200, 9, wr_val) 108 #define rdc_ams_pll_imax_icomp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 7, 15, __ERR) 109 #define wrc_ams_pll_imax_icomp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0100, 8, wr_val) 110 #define rdc_ams_pll_imode_icomp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 8, 15, __ERR) 111 #define wrc_ams_pll_imode_icomp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0080, 7, wr_val) 112 #define rdc_ams_pll_imin_icomp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 9, 15, __ERR) 113 #define wrc_ams_pll_imin_icomp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0040, 6, wr_val) 114 #define rdc_ams_pll_imax_icmldiv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 10, 15, __ERR) 115 #define wrc_ams_pll_imax_icmldiv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0020, 5, wr_val) 116 #define rdc_ams_pll_imode_icmldiv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 11, 15, __ERR) 117 #define wrc_ams_pll_imode_icmldiv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0010, 4, wr_val) 118 #define rdc_ams_pll_imin_icmldiv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 12, 15, __ERR) 119 #define wrc_ams_pll_imin_icmldiv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0008, 3, wr_val) 120 #define rdc_ams_pll_imax_irxclkbuf() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 13, 15, __ERR) 121 #define wrc_ams_pll_imax_irxclkbuf(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0004, 2, wr_val) 122 #define rdc_ams_pll_imode_irxclkbuf() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 14, 15, __ERR) 123 #define wrc_ams_pll_imode_irxclkbuf(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0002, 1, wr_val) 124 #define rdc_ams_pll_imin_irxclkbuf() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd113, 15, 15, __ERR) 125 #define wrc_ams_pll_imin_irxclkbuf(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0001, 0, wr_val) 126 #define rdc_ams_pll_force_rescal() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 0, 15, __ERR) 127 #define wrc_ams_pll_force_rescal(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x8000, 15, wr_val) 128 #define rdc_ams_pll_force_kvh_bw() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 1, 15, __ERR) 129 #define wrc_ams_pll_force_kvh_bw(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x4000, 14, wr_val) 130 #define rdc_ams_pll_kvh_force() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 2, 14, __ERR) 131 #define wrc_ams_pll_kvh_force(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x3000, 12, wr_val) 132 #define rdc_ams_pll_vddr_bgb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 4, 15, __ERR) 133 #define wrc_ams_pll_vddr_bgb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x0800, 11, wr_val) 134 #define rdc_ams_pll_comp_vth() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 5, 15, __ERR) 135 #define wrc_ams_pll_comp_vth(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x0400, 10, wr_val) 136 #define rdc_ams_pll_pll2rx_clkbw() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 6, 14, __ERR) 137 #define wrc_ams_pll_pll2rx_clkbw(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x0300, 8, wr_val) 138 #define rdc_ams_pll_bgr_ctatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 8, 12, __ERR) 139 #define wrc_ams_pll_bgr_ctatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x00f0, 4, wr_val) 140 #define rdc_ams_pll_bgr_ptatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd114, 12, 12, __ERR) 141 #define wrc_ams_pll_bgr_ptatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x000f, 0, wr_val) 142 #define rdc_ams_pll_mix3p1c_calr_ptatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 0, 11, __ERR) 143 #define wrc_ams_pll_mix3p1c_calr_ptatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0xf800, 11, wr_val) 144 #define rdc_ams_pll_mix3p1c_calr_ctatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 5, 11, __ERR) 145 #define wrc_ams_pll_mix3p1c_calr_ctatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x07c0, 6, wr_val) 146 #define rdc_ams_pll_test_pnp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 10, 14, __ERR) 147 #define wrc_ams_pll_test_pnp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0030, 4, wr_val) 148 #define rdc_ams_pll_vbypass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 12, 15, __ERR) 149 #define wrc_ams_pll_vbypass(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0008, 3, wr_val) 150 #define rdc_ams_pll_bgint() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 13, 15, __ERR) 151 #define wrc_ams_pll_bgint(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0004, 2, wr_val) 152 #define rdc_ams_pll_bgip() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 14, 15, __ERR) 153 #define wrc_ams_pll_bgip(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0002, 1, wr_val) 154 #define rdc_ams_pll_test_port_max_amplitude() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd115, 15, 15, __ERR) 155 #define wrc_ams_pll_test_port_max_amplitude(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0001, 0, wr_val) 156 #define rdc_ams_pll_mix1p2cr_ptatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 0, 11, __ERR) 157 #define wrc_ams_pll_mix1p2cr_ptatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0xf800, 11, wr_val) 158 #define rdc_ams_pll_mix1p2cr_ctatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 5, 11, __ERR) 159 #define wrc_ams_pll_mix1p2cr_ctatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x07c0, 6, wr_val) 160 #define rdc_ams_pll_rtermhiz() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 10, 15, __ERR) 161 #define wrc_ams_pll_rtermhiz(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x0020, 5, wr_val) 162 #define rdc_ams_pll_rterm600() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 11, 15, __ERR) 163 #define wrc_ams_pll_rterm600(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x0010, 4, wr_val) 164 #define rdc_ams_pll_rterm400() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 12, 15, __ERR) 165 #define wrc_ams_pll_rterm400(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x0008, 3, wr_val) 166 #define rdc_ams_pll_div4() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 13, 15, __ERR) 167 #define wrc_ams_pll_div4(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x0004, 2, wr_val) 168 #define rdc_ams_pll_div2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 14, 15, __ERR) 169 #define wrc_ams_pll_div2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x0002, 1, wr_val) 170 #define rdc_ams_pll_rterm200() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd116, 15, 15, __ERR) 171 #define wrc_ams_pll_rterm200(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x0001, 0, wr_val) 172 #define rdc_ams_pll_mix3p1cr_ptatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd117, 0, 11, __ERR) 173 #define wrc_ams_pll_mix3p1cr_ptatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0xf800, 11, wr_val) 174 #define rdc_ams_pll_mix3p1cr_ctatadj() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd117, 5, 11, __ERR) 175 #define wrc_ams_pll_mix3p1cr_ctatadj(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x07c0, 6, wr_val) 176 #define rdc_ams_pll_spare_117_114() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd117, 10, 12, __ERR) 177 #define wrc_ams_pll_spare_117_114(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x003c, 2, wr_val) 178 #define rdc_ams_pll_refclk4com_div4() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd117, 14, 15, __ERR) 179 #define wrc_ams_pll_refclk4com_div4(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x0002, 1, wr_val) 180 #define rdc_ams_pll_refclk4com_div2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd117, 15, 15, __ERR) 181 #define wrc_ams_pll_refclk4com_div2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x0001, 0, wr_val) 182 #define rdc_ams_pll_fracn_div() _phy8806x_tsc_pmd_rde_reg(pa, 0xd118, __ERR) 183 #define wrc_ams_pll_fracn_div(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd118, wr_val) 184 #define rdc_ams_pll_fracn_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd119, 0, 15, __ERR) 185 #define wrc_ams_pll_fracn_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x8000, 15, wr_val) 186 #define rdc_ams_pll_ditheren() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd119, 1, 15, __ERR) 187 #define wrc_ams_pll_ditheren(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x4000, 14, wr_val) 188 #define rdc_ams_pll_fracn_ndiv_int() _phy8806x_tsc_pmd_rde_field(pa, 0xd119, 2, 6, __ERR) 189 #define wrc_ams_pll_fracn_ndiv_int(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd119, 0x3ff0, 4, wr_val) 190 #define rdc_ams_pll_fracn_bypass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd119, 12, 15, __ERR) 191 #define wrc_ams_pll_fracn_bypass(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x0008, 3, wr_val) 192 #define rdc_ams_pll_fracn_divrange() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd119, 13, 15, __ERR) 193 #define wrc_ams_pll_fracn_divrange(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x0004, 2, wr_val) 194 #define rdc_ams_pll_fracn_div_17_16() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd119, 14, 14, __ERR) 195 #define wrc_ams_pll_fracn_div_17_16(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x0003, 0, wr_val) 196 #define rdc_ams_pll_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11b, 13, 15, __ERR) 197 #define wrc_ams_pll_pwrdn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd11b, 0x0004, 2, wr_val) 198 #define rdc_ams_pll_div4_2_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11b, 14, 15, __ERR) 199 #define wrc_ams_pll_div4_2_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd11b, 0x0002, 1, wr_val) 200 #define rdc_ams_pll_rterm_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11b, 15, 15, __ERR) 201 #define wrc_ams_pll_rterm_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd11b, 0x0001, 0, wr_val) 202 #define rdc_ams_pll_kvh() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11c, 0, 14, __ERR) 203 #define rdc_ams_pll_range() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11c, 2, 8, __ERR) 204 #define rdc_ams_pll_low() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11c, 10, 15, __ERR) 205 #define rdc_ams_pll_ndiv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd11c, 11, 11, __ERR) 206 #define rd_ams_rx_peaking_filter_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 0, 13, __ERR) 207 #define wr_ams_rx_peaking_filter_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0xe000, 13, wr_val) 208 #define rd_ams_rx_dc_couple() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 3, 15, __ERR) 209 #define wr_ams_rx_dc_couple(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x1000, 12, wr_val) 210 #define rd_ams_rx_dfe_hgain_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 4, 15, __ERR) 211 #define wr_ams_rx_dfe_hgain_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0800, 11, wr_val) 212 #define rd_ams_rx_eq_lz_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 5, 15, __ERR) 213 #define wr_ams_rx_eq_lz_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0400, 10, wr_val) 214 #define rd_ams_rx_vga_10g_bw() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 6, 15, __ERR) 215 #define wr_ams_rx_vga_10g_bw(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0200, 9, wr_val) 216 #define rd_ams_rx_tport_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 7, 15, __ERR) 217 #define wr_ams_rx_tport_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0100, 8, wr_val) 218 #define rd_ams_rx_sigdet_bypass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 8, 15, __ERR) 219 #define wr_ams_rx_sigdet_bypass(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0080, 7, wr_val) 220 #define rd_ams_rx_sigdet_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 9, 15, __ERR) 221 #define wr_ams_rx_sigdet_pwrdn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0040, 6, wr_val) 222 #define rd_ams_rx_sigdet_threshold() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 10, 13, __ERR) 223 #define wr_ams_rx_sigdet_threshold(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0038, 3, wr_val) 224 #define rd_ams_rx_master_diodes_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c0, 13, 13, __ERR) 225 #define wr_ams_rx_master_diodes_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0007, 0, wr_val) 226 #define rd_ams_rx_cm_voltage_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c1, 0, 13, __ERR) 227 #define wr_ams_rx_cm_voltage_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0xe000, 13, wr_val) 228 #define rd_ams_rx_vga3_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c1, 3, 13, __ERR) 229 #define wr_ams_rx_vga3_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x1c00, 10, wr_val) 230 #define rd_ams_rx_vga2_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c1, 6, 13, __ERR) 231 #define wr_ams_rx_vga2_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0380, 7, wr_val) 232 #define rd_ams_rx_vga1_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c1, 9, 13, __ERR) 233 #define wr_ams_rx_vga1_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0070, 4, wr_val) 234 #define rd_ams_rx_vga0_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c1, 12, 13, __ERR) 235 #define wr_ams_rx_vga0_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x000e, 1, wr_val) 236 #define rd_ams_rx_spare_16() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c1, 15, 15, __ERR) 237 #define wr_ams_rx_spare_16(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0001, 0, wr_val) 238 #define rd_ams_rx_pwrdn_ftap() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 0, 15, __ERR) 239 #define wr_ams_rx_pwrdn_ftap(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x8000, 15, wr_val) 240 #define rd_ams_rx_sigdet_power_save() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 1, 15, __ERR) 241 #define wr_ams_rx_sigdet_power_save(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x4000, 14, wr_val) 242 #define rd_ams_rx_pd_ch_p1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 2, 15, __ERR) 243 #define wr_ams_rx_pd_ch_p1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x2000, 13, wr_val) 244 #define rd_ams_rx_sel_th4dfe() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 3, 14, __ERR) 245 #define wr_ams_rx_sel_th4dfe(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x1800, 11, wr_val) 246 #define rd_ams_rx_sel_ugbw() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 5, 14, __ERR) 247 #define wr_ams_rx_sel_ugbw(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0600, 9, wr_val) 248 #define rd_ams_rx_dfe_tap_weight_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 7, 13, __ERR) 249 #define wr_ams_rx_dfe_tap_weight_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x01c0, 6, wr_val) 250 #define rd_ams_rx_phase_interpolators_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 10, 13, __ERR) 251 #define wr_ams_rx_phase_interpolators_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0038, 3, wr_val) 252 #define rd_ams_rx_sigdet_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c2, 13, 13, __ERR) 253 #define wr_ams_rx_sigdet_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0007, 0, wr_val) 254 #define rd_ams_rx_spare_63() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c3, 0, 15, __ERR) 255 #define wr_ams_rx_spare_63(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x8000, 15, wr_val) 256 #define rd_ams_rx_dfe_slicer_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c3, 1, 13, __ERR) 257 #define wr_ams_rx_dfe_slicer_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x7000, 12, wr_val) 258 #define rd_ams_rx_dfe_sum_buf_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c3, 4, 13, __ERR) 259 #define wr_ams_rx_dfe_sum_buf_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x0e00, 9, wr_val) 260 #define rd_ams_rx_offset_correction_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c3, 7, 13, __ERR) 261 #define wr_ams_rx_offset_correction_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x01c0, 6, wr_val) 262 #define rd_ams_rx_dll_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c3, 10, 13, __ERR) 263 #define wr_ams_rx_dll_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x0038, 3, wr_val) 264 #define rd_ams_rx_met_r_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c3, 13, 13, __ERR) 265 #define wr_ams_rx_met_r_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x0007, 0, wr_val) 266 #define rd_ams_rx_vga1_rescal_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c4, 0, 11, __ERR) 267 #define wr_ams_rx_vga1_rescal_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0xf800, 11, wr_val) 268 #define rd_ams_rx_vga0_rescal_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c4, 5, 11, __ERR) 269 #define wr_ams_rx_vga0_rescal_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0x07c0, 6, wr_val) 270 #define rd_ams_rx_tbd_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c4, 10, 13, __ERR) 271 #define wr_ams_rx_tbd_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0x0038, 3, wr_val) 272 #define rd_ams_rx_dfe_slicer_cal_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c4, 13, 13, __ERR) 273 #define wr_ams_rx_dfe_slicer_cal_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0x0007, 0, wr_val) 274 #define rd_ams_rx_rxclk_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c5, 0, 15, __ERR) 275 #define wr_ams_rx_rxclk_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x8000, 15, wr_val) 276 #define rd_ams_rx_testclk_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c5, 1, 15, __ERR) 277 #define wr_ams_rx_testclk_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x4000, 14, wr_val) 278 #define rd_ams_rx_testclk_div() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c5, 2, 14, __ERR) 279 #define wr_ams_rx_testclk_div(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x3000, 12, wr_val) 280 #define rd_ams_rx_spare_91_90() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c5, 4, 14, __ERR) 281 #define wr_ams_rx_spare_91_90(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x0c00, 10, wr_val) 282 #define rd_ams_rx_vga3_rescal_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c5, 6, 11, __ERR) 283 #define wr_ams_rx_vga3_rescal_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x03e0, 5, wr_val) 284 #define rd_ams_rx_vga2_rescal_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c5, 11, 11, __ERR) 285 #define wr_ams_rx_vga2_rescal_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x001f, 0, wr_val) 286 #define rd_ams_rx_spare_111_104() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c6, 0, 8, __ERR) 287 #define wr_ams_rx_spare_111_104(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c6, 0xff00, 8, wr_val) 288 #define rd_ams_rx_offset_correction_rescal_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c6, 8, 12, __ERR) 289 #define wr_ams_rx_offset_correction_rescal_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c6, 0x00f0, 4, wr_val) 290 #define rd_ams_rx_peaking_filter_rescal_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c6, 12, 12, __ERR) 291 #define wr_ams_rx_peaking_filter_rescal_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c6, 0x000f, 0, wr_val) 292 #define rd_ams_rx_vga_step_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 0, 14, __ERR) 293 #define wr_ams_rx_vga_step_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0xc000, 14, wr_val) 294 #define rd_ams_rx_vga_low_gain() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 2, 14, __ERR) 295 #define wr_ams_rx_vga_low_gain(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x3000, 12, wr_val) 296 #define rd_ams_rx_spare_123() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 4, 15, __ERR) 297 #define wr_ams_rx_spare_123(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0800, 11, wr_val) 298 #define rd_ams_rx_short_vga_output() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 5, 15, __ERR) 299 #define wr_ams_rx_short_vga_output(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0400, 10, wr_val) 300 #define rd_ams_rx_rx_offset_pd() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 6, 15, __ERR) 301 #define wr_ams_rx_rx_offset_pd(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0200, 9, wr_val) 302 #define rd_ams_rx_dc_offset_range() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 7, 15, __ERR) 303 #define wr_ams_rx_dc_offset_range(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0100, 8, wr_val) 304 #define rd_ams_rx_force_dc_offset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 8, 15, __ERR) 305 #define wr_ams_rx_force_dc_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0080, 7, wr_val) 306 #define rd_ams_rx_dc_offset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c7, 9, 9, __ERR) 307 #define wr_ams_rx_dc_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x007f, 0, wr_val) 308 #define rd_ams_rx_spare_143_142() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c8, 0, 14, __ERR) 309 #define wr_ams_rx_spare_143_142(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0xc000, 14, wr_val) 310 #define rd_ams_rx_dac4ck_phs() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c8, 2, 10, __ERR) 311 #define wr_ams_rx_dac4ck_phs(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0x3f00, 8, wr_val) 312 #define rd_ams_rx_spare_135_134() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c8, 8, 14, __ERR) 313 #define wr_ams_rx_spare_135_134(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0x00c0, 6, wr_val) 314 #define rd_ams_rx_dac4ck_lms() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c8, 10, 10, __ERR) 315 #define wr_ams_rx_dac4ck_lms(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0x003f, 0, wr_val) 316 #define rd_ams_rx_data12t_ll_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 0, 15, __ERR) 317 #define wr_ams_rx_data12t_ll_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x8000, 15, wr_val) 318 #define rd_ams_rx_d2c_clkbuf_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 1, 13, __ERR) 319 #define wr_ams_rx_d2c_clkbuf_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x7000, 12, wr_val) 320 #define rd_ams_rx_sel_d2clp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 4, 15, __ERR) 321 #define wr_ams_rx_sel_d2clp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x0800, 11, wr_val) 322 #define rd_ams_rx_en_tap9delay() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 5, 15, __ERR) 323 #define wr_ams_rx_en_tap9delay(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x0400, 10, wr_val) 324 #define rd_ams_rx_clk_bw_ctrl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 6, 14, __ERR) 325 #define wr_ams_rx_clk_bw_ctrl(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x0300, 8, wr_val) 326 #define rd_ams_rx_spare_151_150() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 8, 14, __ERR) 327 #define wr_ams_rx_spare_151_150(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x00c0, 6, wr_val) 328 #define rd_ams_rx_dac4ck_dat() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0c9, 10, 10, __ERR) 329 #define wr_ams_rx_dac4ck_dat(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x003f, 0, wr_val) 330 #define rd_ams_rx_sigdet() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0cb, 0, 15, __ERR) 331 #define rd_ams_rx_pf() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0cb, 1, 12, __ERR) 332 #define rd_ams_rx_tap1_dfe_gray() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0cb, 5, 10, __ERR) 333 #define rd_ams_rx_vga() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0cb, 11, 11, __ERR) 334 #define rd_ams_tx_cal_aux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 0, 12, __ERR) 335 #define wr_ams_tx_cal_aux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0xf000, 12, wr_val) 336 #define rd_ams_tx_cal_off() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 4, 15, __ERR) 337 #define wr_ams_tx_cal_off(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0800, 11, wr_val) 338 #define rd_ams_tx_dcc_dis() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 5, 15, __ERR) 339 #define wr_ams_tx_dcc_dis(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0400, 10, wr_val) 340 #define rd_ams_tx_dcc_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 6, 15, __ERR) 341 #define wr_ams_tx_dcc_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0200, 9, wr_val) 342 #define rd_ams_tx_vddr_bgb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 7, 15, __ERR) 343 #define wr_ams_tx_vddr_bgb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0100, 8, wr_val) 344 #define rd_ams_tx_ticksel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 8, 14, __ERR) 345 #define wr_ams_tx_ticksel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x00c0, 6, wr_val) 346 #define rd_ams_tx_test_data() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 10, 14, __ERR) 347 #define wr_ams_tx_test_data(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0030, 4, wr_val) 348 #define rd_ams_tx_spare_3_1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 12, 13, __ERR) 349 #define wr_ams_tx_spare_3_1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x000e, 1, wr_val) 350 #define rd_ams_tx_txclk_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d0, 15, 15, __ERR) 351 #define wr_ams_tx_txclk_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0001, 0, wr_val) 352 #define rd_ams_tx_clk20_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 0, 15, __ERR) 353 #define wr_ams_tx_clk20_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x8000, 15, wr_val) 354 #define rd_ams_tx_sel_emph_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 1, 15, __ERR) 355 #define wr_ams_tx_sel_emph_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x4000, 14, wr_val) 356 #define rd_ams_tx_ldo_vref() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 2, 14, __ERR) 357 #define wr_ams_tx_ldo_vref(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x3000, 12, wr_val) 358 #define rd_ams_tx_ildo() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 4, 13, __ERR) 359 #define wr_ams_tx_ildo(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0e00, 9, wr_val) 360 #define rd_ams_tx_icml() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 7, 13, __ERR) 361 #define wr_ams_tx_icml(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x01c0, 6, wr_val) 362 #define rd_ams_tx_iphint() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 10, 13, __ERR) 363 #define wr_ams_tx_iphint(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0038, 3, wr_val) 364 #define rd_ams_tx_ibias() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d1, 13, 13, __ERR) 365 #define wr_ams_tx_ibias(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0007, 0, wr_val) 366 #define rd_ams_tx_elec_idle_aux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 0, 15, __ERR) 367 #define wr_ams_tx_elec_idle_aux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x8000, 15, wr_val) 368 #define rd_ams_tx_driver_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 1, 14, __ERR) 369 #define wr_ams_tx_driver_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x6000, 13, wr_val) 370 #define rd_ams_tx_sign_post2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 3, 15, __ERR) 371 #define wr_ams_tx_sign_post2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x1000, 12, wr_val) 372 #define rd_ams_tx_post2_coef() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 4, 12, __ERR) 373 #define wr_ams_tx_post2_coef(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0f00, 8, wr_val) 374 #define rd_ams_tx_sign_post3() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 8, 15, __ERR) 375 #define wr_ams_tx_sign_post3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0080, 7, wr_val) 376 #define rd_ams_tx_post3_coef() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 9, 13, __ERR) 377 #define wr_ams_tx_post3_coef(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0070, 4, wr_val) 378 #define rd_ams_tx_amp_ctl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d2, 12, 12, __ERR) 379 #define wr_ams_tx_amp_ctl(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x000f, 0, wr_val) 380 #define rd_ams_tx_spare_63_57() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 0, 9, __ERR) 381 #define wr_ams_tx_spare_63_57(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0xfe00, 9, wr_val) 382 #define rd_ams_tx_pdet_ll_clk() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 7, 15, __ERR) 383 #define wr_ams_tx_pdet_ll_clk(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0100, 8, wr_val) 384 #define rd_ams_tx_sel_txmaster() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 8, 15, __ERR) 385 #define wr_ams_tx_sel_txmaster(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0080, 7, wr_val) 386 #define rd_ams_tx_sel_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 9, 15, __ERR) 387 #define wr_ams_tx_sel_ll(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0040, 6, wr_val) 388 #define rd_ams_tx_pdet_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 10, 14, __ERR) 389 #define wr_ams_tx_pdet_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0030, 4, wr_val) 390 #define rd_ams_tx_sel_fifo_pol() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 12, 15, __ERR) 391 #define wr_ams_tx_sel_fifo_pol(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0008, 3, wr_val) 392 #define rd_ams_tx_fifo_depth() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d3, 13, 13, __ERR) 393 #define wr_ams_tx_fifo_depth(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0007, 0, wr_val) 394 #define rd_auto_ll_selpath_tx_dis() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d8, 15, 15, __ERR) 395 #define wr_auto_ll_selpath_tx_dis(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0d8, 0x0001, 0, wr_val) 396 #define rd_ams_tx_lane_id() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d9, 0, 14, __ERR) 397 #define rd_ams_tx_spare_sts_13() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d9, 2, 15, __ERR) 398 #define rd_ams_tx_drv_hv_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d9, 3, 15, __ERR) 399 #define rd_ams_tx_ana_rescal() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d9, 4, 12, __ERR) 400 #define rd_ams_tx_version_id() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0d9, 8, 8, __ERR) 401 #define rd_cl93n72_ieee_lp_coeff_update() _phy8806x_tsc_pmd_rde_reg(pa, 0x0098, __ERR) 402 #define rd_cl93n72_ieee_lp_status_report() _phy8806x_tsc_pmd_rde_reg(pa, 0x0099, __ERR) 403 #define rd_cl93n72_ieee_training_enable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x0096, 14, 15, __ERR) 404 #define wr_cl93n72_ieee_training_enable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0x0096, 0x0002, 1, wr_val) 405 #define rd_cl93n72_ieee_restart_training() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x0096, 15, 15, __ERR) 406 #define wr_cl93n72_ieee_restart_training(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0x0096, 0x0001, 0, wr_val) 407 #define rd_cl93n72_ieee_training_failure() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x0097, 12, 15, __ERR) 408 #define rd_cl93n72_ieee_training_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x0097, 13, 15, __ERR) 409 #define rd_cl93n72_ieee_frame_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x0097, 14, 15, __ERR) 410 #define rd_cl93n72_ieee_receiver_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x0097, 15, 15, __ERR) 411 #define rd_cl93n72_ieee_ld_coeff_update() _phy8806x_tsc_pmd_rde_reg(pa, 0x009a, __ERR) 412 #define rd_cl93n72_ieee_ld_status_report() _phy8806x_tsc_pmd_rde_reg(pa, 0x009b, __ERR) 413 #define rd_cl93n72_rx_signal_ok() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd080, 13, 15, __ERR) 414 #define wr_cl93n72_rx_signal_ok(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x0004, 2, wr_val) 415 #define rd_cl93n72_tr_coarse_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd080, 14, 15, __ERR) 416 #define wr_cl93n72_tr_coarse_lock(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x0002, 1, wr_val) 417 #define rd_cl93n72_rx_training_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd080, 15, 15, __ERR) 418 #define wr_cl93n72_rx_training_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x0001, 0, wr_val) 419 #define rd_cl93n72_bad_marker_cnt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd081, 9, 13, __ERR) 420 #define wr_cl93n72_bad_marker_cnt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0070, 4, wr_val) 421 #define rd_cl93n72_good_marker_cnt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd081, 14, 14, __ERR) 422 #define wr_cl93n72_good_marker_cnt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0003, 0, wr_val) 423 #define rd_cl93n72_block_lp_ieee_updates() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 5, 15, __ERR) 424 #define wr_cl93n72_block_lp_ieee_updates(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0400, 10, wr_val) 425 #define rd_cl93n72_frame_consistency_chk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 6, 15, __ERR) 426 #define wr_cl93n72_frame_consistency_chk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0200, 9, wr_val) 427 #define rd_cl93n72_rx_dp_ln_clk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 7, 15, __ERR) 428 #define wr_cl93n72_rx_dp_ln_clk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0100, 8, wr_val) 429 #define rd_cl93n72_ppm_offset_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 8, 15, __ERR) 430 #define wr_cl93n72_ppm_offset_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0080, 7, wr_val) 431 #define rd_cl93n72_strict_marker_chk() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 9, 15, __ERR) 432 #define wr_cl93n72_strict_marker_chk(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0040, 6, wr_val) 433 #define rd_cl93n72_strict_dme_chk() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 10, 15, __ERR) 434 #define wr_cl93n72_strict_dme_chk(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0020, 5, wr_val) 435 #define rd_cl93n72_dme_cell_boundary_chk() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 11, 15, __ERR) 436 #define wr_cl93n72_dme_cell_boundary_chk(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0010, 4, wr_val) 437 #define rd_cl93n72_ctrl_frame_dly() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd082, 12, 12, __ERR) 438 #define wr_cl93n72_ctrl_frame_dly(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x000f, 0, wr_val) 439 #define rd_cl93n72_remote_rx_ready() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd083, 14, 15, __ERR) 440 #define rd_cl93n72_frame_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd083, 15, 15, __ERR) 441 #define rd_cl93n72_micro_status_resp_int_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 4, 15, __ERR) 442 #define wr_cl93n72_micro_status_resp_int_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0800, 11, wr_val) 443 #define rd_cl93n72_micro_status_resp_int_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 5, 15, __ERR) 444 #define wr_cl93n72_micro_status_resp_int_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0400, 10, wr_val) 445 #define rd_cl93n72_micro_update_req_int_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 6, 15, __ERR) 446 #define wr_cl93n72_micro_update_req_int_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0200, 9, wr_val) 447 #define rd_cl93n72_micro_update_req_int_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 7, 15, __ERR) 448 #define wr_cl93n72_micro_update_req_int_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0100, 8, wr_val) 449 #define rd_cl93n72_micro_frame_lock_int_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 13, 15, __ERR) 450 #define wr_cl93n72_micro_frame_lock_int_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0004, 2, wr_val) 451 #define rd_cl93n72_micro_status_chg_int_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 14, 15, __ERR) 452 #define wr_cl93n72_micro_status_chg_int_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0002, 1, wr_val) 453 #define rd_cl93n72_micro_update_chg_int_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd084, 15, 15, __ERR) 454 #define wr_cl93n72_micro_update_chg_int_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0001, 0, wr_val) 455 #define rd_cl93n72_micro_update_chg_lstatus() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd085, 15, 15, __ERR) 456 #define rd_cl93n72_micro_frame_lock_lstatus() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd086, 14, 15, __ERR) 457 #define rd_cl93n72_micro_status_chg_lstatus() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd086, 15, 15, __ERR) 458 #define rd_cl93n72_micro_interrupt_mask_control_page() _phy8806x_tsc_pmd_rde_reg(pa, 0xd08d, __ERR) 459 #define wr_cl93n72_micro_interrupt_mask_control_page(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd08d, wr_val) 460 #define rd_cl93n72_micro_interrupt_mask_status_page() _phy8806x_tsc_pmd_rde_reg(pa, 0xd08e, __ERR) 461 #define wr_cl93n72_micro_interrupt_mask_status_page(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd08e, wr_val) 462 #define rd_cl93n72_rx_fctts_rcvctrl_page() _phy8806x_tsc_pmd_rde_reg(pa, 0xd087, __ERR) 463 #define rd_cl93n72_rx_fctts_rcvsts_page() _phy8806x_tsc_pmd_rde_reg(pa, 0xd088, __ERR) 464 #define rd_cl93n72_pmd_to_pcs_fctts_rx_ln_intr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd089, 0, 15, __ERR) 465 #define wr_cl93n72_pmd_to_pcs_fctts_rx_ln_intr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd089, 0x8000, 15, wr_val) 466 #define rd_cl93n72_rx_fctts_sn_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd089, 1, 15, __ERR) 467 #define wr_cl93n72_rx_fctts_sn_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd089, 0x4000, 14, wr_val) 468 #define rd_cl93n72_rx_fctts_ext_marker_check_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd089, 2, 14, __ERR) 469 #define wr_cl93n72_rx_fctts_ext_marker_check_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd089, 0x3000, 12, wr_val) 470 #define rd_cl93n72_rx_fctts_sync_count_clr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd089, 4, 15, __ERR) 471 #define wr_cl93n72_rx_fctts_sync_count_clr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd089, 0x0800, 11, wr_val) 472 #define rd_cl93n72_rx_fctts_sync_count_chkval() _phy8806x_tsc_pmd_rde_field(pa, 0xd089, 5, 5, __ERR) 473 #define wr_cl93n72_rx_fctts_sync_count_chkval(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd089, 0x07ff, 0, wr_val) 474 #define rd_cl93n72_rx_cdr_coarse_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd08c, 14, 15, __ERR) 475 #define rd_cl93n72_rx_fctts_sn_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd08c, 15, 15, __ERR) 476 #define rd_cl93n72_rx_fctts_sync_count() _phy8806x_tsc_pmd_rde_reg(pa, 0xd08a, __ERR) 477 #define rd_cl93n72_rx_fctts_status0() _phy8806x_tsc_pmd_rde_reg(pa, 0xd08b, __ERR) 478 #define rd_cl93n72_xmt_update_page() _phy8806x_tsc_pmd_rde_reg(pa, 0xd090, __ERR) 479 #define wr_cl93n72_xmt_update_page(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd090, wr_val) 480 #define rd_cl93n72_ld_xmt_status_page() _phy8806x_tsc_pmd_rde_reg(pa, 0xd091, __ERR) 481 #define wr_cl93n72_ld_xmt_status_page(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd091, wr_val) 482 #define rd_cl93n72_ignore_xmt_reg_value() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd092, 12, 15, __ERR) 483 #define wr_cl93n72_ignore_xmt_reg_value(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0008, 3, wr_val) 484 #define rd_cl93n72_sw_remote_rx_ready() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd092, 13, 15, __ERR) 485 #define wr_cl93n72_sw_remote_rx_ready(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0004, 2, wr_val) 486 #define rd_cl93n72_sw_rx_trained() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd092, 15, 15, __ERR) 487 #define wr_cl93n72_sw_rx_trained(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0001, 0, wr_val) 488 #define rd_cl93n72_sw_frame_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd092, 14, 15, __ERR) 489 #define wr_cl93n72_sw_frame_lock(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0002, 1, wr_val) 490 #define rd_cl93n72_timer_value_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd093, 0, 15, __ERR) 491 #define wr_cl93n72_timer_value_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x8000, 15, wr_val) 492 #define rd_cl93n72_tx_dp_ln_clk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd093, 13, 15, __ERR) 493 #define wr_cl93n72_tx_dp_ln_clk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0004, 2, wr_val) 494 #define rd_cl93n72_dis_max_wait_timer() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd093, 14, 15, __ERR) 495 #define wr_cl93n72_dis_max_wait_timer(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0002, 1, wr_val) 496 #define rd_cl93n72_brk_ring_osc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd093, 15, 15, __ERR) 497 #define wr_cl93n72_brk_ring_osc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0001, 0, wr_val) 498 #define rd_cl93n72_txfir_post() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd094, 2, 10, __ERR) 499 #define wr_cl93n72_txfir_post(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x3f00, 8, wr_val) 500 #define rd_cl93n72_txfir_pre() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd094, 11, 11, __ERR) 501 #define wr_cl93n72_txfir_pre(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x001f, 0, wr_val) 502 #define rd_cl93n72_txfir_main() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd095, 9, 9, __ERR) 503 #define wr_cl93n72_txfir_main(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd095, 0x007f, 0, wr_val) 504 #define rd_cl93n72_sm_current_state() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd096, 1, 13, __ERR) 505 #define rd_cl93n72_training_fsm_signal_detect() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd096, 14, 15, __ERR) 506 #define rd_cl93n72_local_rx_ready() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd096, 15, 15, __ERR) 507 #define rd_cl93n72_prbs_seed_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd097, 0, 14, __ERR) 508 #define wr_cl93n72_prbs_seed_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd097, 0xc000, 14, wr_val) 509 #define rd_cl93n72_prbs_mode_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd097, 2, 15, __ERR) 510 #define wr_cl93n72_prbs_mode_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd097, 0x2000, 13, wr_val) 511 #define rd_cl93n72_cl93prbs_poly_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd097, 3, 14, __ERR) 512 #define wr_cl93n72_cl93prbs_poly_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd097, 0x1800, 11, wr_val) 513 #define rd_cl93n72_prbs_seed_val() _phy8806x_tsc_pmd_rde_field(pa, 0xd097, 5, 5, __ERR) 514 #define wr_cl93n72_prbs_seed_val(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd097, 0x07ff, 0, wr_val) 515 #define rd_cl93n72_fctts_info() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09b, 8, 10, __ERR) 516 #define wr_cl93n72_fctts_info(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd09b, 0x00fc, 2, wr_val) 517 #define rd_cl93n72_send_fctts_after_training() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09b, 14, 15, __ERR) 518 #define wr_cl93n72_send_fctts_after_training(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd09b, 0x0002, 1, wr_val) 519 #define rd_cl93n72_fctts_sn_to_trn_req() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09b, 15, 15, __ERR) 520 #define wr_cl93n72_fctts_sn_to_trn_req(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd09b, 0x0001, 0, wr_val) 521 #define rd_cl93n72_tx_fctts_sn_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09c, 15, 15, __ERR) 522 #define rd_cl93n72_fctts_sn_to_trn_req_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09d, 13, 15, __ERR) 523 #define wr_cl93n72_fctts_sn_to_trn_req_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd09d, 0x0004, 2, wr_val) 524 #define rd_cl93n72_tx_fctts_sn_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09d, 15, 15, __ERR) 525 #define wr_cl93n72_tx_fctts_sn_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd09d, 0x0001, 0, wr_val) 526 #define rd_cl93n72_pmd_to_pcs_fctts_tx_ln_intr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd09e, 15, 15, __ERR) 527 #define wr_cl93n72_pmd_to_pcs_fctts_tx_ln_intr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd09e, 0x0001, 0, wr_val) 528 #define rdc_pmd_core_mode() _phy8806x_tsc_pmd_rde_reg(pa, 0xd180, __ERR) 529 #define rdc_afe_s_pll_reset_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 2, 15, __ERR) 530 #define wrc_afe_s_pll_reset_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x2000, 13, wr_val) 531 #define rdc_afe_s_pll_reset_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 3, 15, __ERR) 532 #define wrc_afe_s_pll_reset_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x1000, 12, wr_val) 533 #define rdc_pmd_vcoclk4pcs_vld_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 5, 15, __ERR) 534 #define wrc_pmd_vcoclk4pcs_vld_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x0400, 10, wr_val) 535 #define rdc_pmd_vcoclk4pcs_vld_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 6, 15, __ERR) 536 #define wrc_pmd_vcoclk4pcs_vld_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x0200, 9, wr_val) 537 #define rdc_vcoclk4pcs_s_comclk_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 7, 15, __ERR) 538 #define wrc_vcoclk4pcs_s_comclk_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x0100, 8, wr_val) 539 #define rdc_vcoclk4pcs_s_comclk_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 8, 15, __ERR) 540 #define wrc_vcoclk4pcs_s_comclk_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x0080, 7, wr_val) 541 #define rdc_pmd_core_dp_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd182, 14, 15, __ERR) 542 #define wrc_pmd_core_dp_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd182, 0x0002, 1, wr_val) 543 #define rdc_core_hw_fw_handshake_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd184, 0, 15, __ERR) 544 #define wrc_core_hw_fw_handshake_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd184, 0x8000, 15, wr_val) 545 #define rdc_afe_s_pll_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd184, 1, 15, __ERR) 546 #define wrc_afe_s_pll_pwrdn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd184, 0x4000, 14, wr_val) 547 #define rdc_core_dp_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd184, 2, 15, __ERR) 548 #define wrc_core_dp_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd184, 0x2000, 13, wr_val) 549 #define rdc_uc_ack_core_dp_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd185, 14, 15, __ERR) 550 #define wrc_uc_ack_core_dp_reset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd185, 0x0002, 1, wr_val) 551 #define rdc_uc_ack_core_cfg_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd185, 15, 15, __ERR) 552 #define wrc_uc_ack_core_cfg_done(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd185, 0x0001, 0, wr_val) 553 #define rdc_core_dp_reset_state() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd188, 13, 13, __ERR) 554 #define rdc_pll_pwrdn_or() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd189, 15, 15, __ERR) 555 #define rdc_tx_lane_addr_0() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd190, 3, 11, __ERR) 556 #define wrc_tx_lane_addr_0(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd190, 0x1f00, 8, wr_val) 557 #define rdc_rx_lane_addr_0() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd190, 11, 11, __ERR) 558 #define wrc_rx_lane_addr_0(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd190, 0x001f, 0, wr_val) 559 #define rdc_tx_lane_addr_1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd191, 3, 11, __ERR) 560 #define wrc_tx_lane_addr_1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd191, 0x1f00, 8, wr_val) 561 #define rdc_rx_lane_addr_1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd191, 11, 11, __ERR) 562 #define wrc_rx_lane_addr_1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd191, 0x001f, 0, wr_val) 563 #define rdc_tx_lane_addr_2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd192, 3, 11, __ERR) 564 #define wrc_tx_lane_addr_2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd192, 0x1f00, 8, wr_val) 565 #define rdc_rx_lane_addr_2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd192, 11, 11, __ERR) 566 #define wrc_rx_lane_addr_2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd192, 0x001f, 0, wr_val) 567 #define rdc_tx_lane_addr_3() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd193, 3, 11, __ERR) 568 #define wrc_tx_lane_addr_3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd193, 0x1f00, 8, wr_val) 569 #define rdc_rx_lane_addr_3() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd193, 11, 11, __ERR) 570 #define wrc_rx_lane_addr_3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd193, 0x001f, 0, wr_val) 571 #define rdc_revid_rev_letter() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd100, 0, 14, __ERR) 572 #define rdc_revid_rev_number() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd100, 2, 13, __ERR) 573 #define rdc_revid_bonding() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd100, 5, 14, __ERR) 574 #define rdc_revid_process() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd100, 7, 13, __ERR) 575 #define rdc_revid_model() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd100, 10, 10, __ERR) 576 #define rdc_revid_multiplicity() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 0, 12, __ERR) 577 #define rdc_revid_mdio() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 10, 15, __ERR) 578 #define rdc_revid_micro() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 11, 15, __ERR) 579 #define rdc_revid_cl72() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 12, 15, __ERR) 580 #define rdc_revid_pir() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 13, 15, __ERR) 581 #define rdc_revid_llp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 14, 15, __ERR) 582 #define rdc_revid_eee() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10a, 15, 15, __ERR) 583 #define rdc_revid2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd10e, 12, 12, __ERR) 584 #define rdc_core_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd101, 15, 15, __ERR) 585 #define wrc_core_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd101, 0x0001, 0, wr_val) 586 #define rdc_disable_ack_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd102, 0, 15, __ERR) 587 #define wrc_disable_ack_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x8000, 15, wr_val) 588 #define rdc_pmd_mdio_trans_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd102, 10, 15, __ERR) 589 #define wrc_pmd_mdio_trans_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0020, 5, wr_val) 590 #define rdc_sup_rst_seq_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd102, 11, 15, __ERR) 591 #define wrc_sup_rst_seq_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0010, 4, wr_val) 592 #define rdc_sup_rst_seq_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd102, 12, 15, __ERR) 593 #define wrc_sup_rst_seq_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0008, 3, wr_val) 594 #define rdc_maskdata() _phy8806x_tsc_pmd_rde_reg(pa, 0xd103, __ERR) 595 #define wrc_maskdata(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd103, wr_val) 596 #define rdc_uc_active() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd104, 0, 15, __ERR) 597 #define wrc_uc_active(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd104, 0x8000, 15, wr_val) 598 #define rdc_maskdata_bus_assign() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd104, 4, 14, __ERR) 599 #define wrc_maskdata_bus_assign(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd104, 0x0c00, 10, wr_val) 600 #define rdc_heartbeat_count_1us() _phy8806x_tsc_pmd_rde_field(pa, 0xd104, 6, 6, __ERR) 601 #define wrc_heartbeat_count_1us(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd104, 0x03ff, 0, wr_val) 602 #define rdc_lane_reset_released() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd108, 1, 15, __ERR) 603 #define rdc_lane_reset_released_index() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd108, 3, 11, __ERR) 604 #define rdc_tx_lane_reset_released() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd108, 0, 15, __ERR) 605 #define rdc_tx_lane_reset_released_index() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd108, 8, 11, __ERR) 606 #define rdc_core_reg_reset_occurred() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd106, 15, 15, __ERR) 607 #define wrc_core_reg_reset_occurred(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd106, 0x0001, 0, wr_val) 608 #define rdc_rst_seq_dis_flt_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd107, 0, 14, __ERR) 609 #define wrc_rst_seq_dis_flt_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd107, 0xc000, 14, wr_val) 610 #define rdc_pwrdn_seq_timer() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd107, 5, 13, __ERR) 611 #define wrc_pwrdn_seq_timer(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd107, 0x0700, 8, wr_val) 612 #define rdc_rst_seq_timer() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd107, 13, 13, __ERR) 613 #define wrc_rst_seq_timer(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd107, 0x0007, 0, wr_val) 614 #define rd_uc_dsc_supp_info() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd03d, 0, 8, __ERR) 615 #define wr_uc_dsc_supp_info(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0xff00, 8, wr_val) 616 #define rd_uc_dsc_ready_for_cmd() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd03d, 8, 15, __ERR) 617 #define wr_uc_dsc_ready_for_cmd(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0x0080, 7, wr_val) 618 #define rd_uc_dsc_error_found() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd03d, 9, 15, __ERR) 619 #define wr_uc_dsc_error_found(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0x0040, 6, wr_val) 620 #define rd_uc_dsc_gp_uc_req() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd03d, 10, 10, __ERR) 621 #define wr_uc_dsc_gp_uc_req(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0x003f, 0, wr_val) 622 #define rd_uc_dsc_data() _phy8806x_tsc_pmd_rde_reg(pa, 0xd03e, __ERR) 623 #define wr_uc_dsc_data(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd03e, wr_val) 624 #define rd_rx_pf_ctrl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd000, 1, 12, __ERR) 625 #define wr_rx_pf_ctrl(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd000, 0x7800, 11, wr_val) 626 #define rd_rx_pf2_ctrl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd000, 5, 13, __ERR) 627 #define wr_rx_pf2_ctrl(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd000, 0x0700, 8, wr_val) 628 #define rd_rxa_slicer_offset_adj_dn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd001, 2, 10, __ERR) 629 #define wr_rxa_slicer_offset_adj_dn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x3f00, 8, wr_val) 630 #define rd_rxa_slicer_offset_adj_dp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd001, 10, 10, __ERR) 631 #define wr_rxa_slicer_offset_adj_dp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x003f, 0, wr_val) 632 #define rd_rxa_slicer_offset_adj_zn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd002, 2, 10, __ERR) 633 #define wr_rxa_slicer_offset_adj_zn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd002, 0x3f00, 8, wr_val) 634 #define rd_rxa_slicer_offset_adj_zp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd002, 10, 10, __ERR) 635 #define wr_rxa_slicer_offset_adj_zp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd002, 0x003f, 0, wr_val) 636 #define rd_rxa_slicer_offset_adj_lms() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd003, 2, 10, __ERR) 637 #define wr_rxa_slicer_offset_adj_lms(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x3f00, 8, wr_val) 638 #define rd_rxb_slicer_offset_adj_lms() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd003, 10, 10, __ERR) 639 #define wr_rxb_slicer_offset_adj_lms(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x003f, 0, wr_val) 640 #define rd_rxb_slicer_offset_adj_dn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd004, 2, 10, __ERR) 641 #define wr_rxb_slicer_offset_adj_dn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x3f00, 8, wr_val) 642 #define rd_rxb_slicer_offset_adj_dp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd004, 10, 10, __ERR) 643 #define wr_rxb_slicer_offset_adj_dp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x003f, 0, wr_val) 644 #define rd_rxb_slicer_offset_adj_zn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd005, 2, 10, __ERR) 645 #define wr_rxb_slicer_offset_adj_zn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd005, 0x3f00, 8, wr_val) 646 #define rd_rxb_slicer_offset_adj_zp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd005, 10, 10, __ERR) 647 #define wr_rxb_slicer_offset_adj_zp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd005, 0x003f, 0, wr_val) 648 #define rd_rxc_slicer_offset_adj_dn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd006, 2, 10, __ERR) 649 #define wr_rxc_slicer_offset_adj_dn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd006, 0x3f00, 8, wr_val) 650 #define rd_rxc_slicer_offset_adj_dp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd006, 10, 10, __ERR) 651 #define wr_rxc_slicer_offset_adj_dp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd006, 0x003f, 0, wr_val) 652 #define rd_rxc_slicer_offset_adj_zn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd007, 2, 10, __ERR) 653 #define wr_rxc_slicer_offset_adj_zn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd007, 0x3f00, 8, wr_val) 654 #define rd_rxc_slicer_offset_adj_zp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd007, 10, 10, __ERR) 655 #define wr_rxc_slicer_offset_adj_zp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd007, 0x003f, 0, wr_val) 656 #define rd_rxc_slicer_offset_adj_lms() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd008, 2, 10, __ERR) 657 #define wr_rxc_slicer_offset_adj_lms(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd008, 0x3f00, 8, wr_val) 658 #define rd_rxd_slicer_offset_adj_lms() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd008, 10, 10, __ERR) 659 #define wr_rxd_slicer_offset_adj_lms(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd008, 0x003f, 0, wr_val) 660 #define rd_rxd_slicer_offset_adj_dn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd009, 2, 10, __ERR) 661 #define wr_rxd_slicer_offset_adj_dn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd009, 0x3f00, 8, wr_val) 662 #define rd_rxd_slicer_offset_adj_dp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd009, 10, 10, __ERR) 663 #define wr_rxd_slicer_offset_adj_dp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd009, 0x003f, 0, wr_val) 664 #define rd_rxd_slicer_offset_adj_zn() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd00a, 2, 10, __ERR) 665 #define wr_rxd_slicer_offset_adj_zn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd00a, 0x3f00, 8, wr_val) 666 #define rd_rxd_slicer_offset_adj_zp() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd00a, 10, 10, __ERR) 667 #define wr_rxd_slicer_offset_adj_zp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd00a, 0x003f, 0, wr_val) 668 #define rd_rx_phase_thresh_sel() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd00b, 1, 9, __ERR) 669 #define wr_rx_phase_thresh_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd00b, 0x7f00, 8, wr_val) 670 #define rd_rx_lms_thresh_sel() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd00b, 8, 8, __ERR) 671 #define wr_rx_lms_thresh_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd00b, 0x00ff, 0, wr_val) 672 #define rd_rxa_dfe_tap2() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd010, 3, 11, __ERR) 673 #define wr_rxa_dfe_tap2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x1f00, 8, wr_val) 674 #define rd_rxb_dfe_tap2() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd010, 11, 11, __ERR) 675 #define wr_rxb_dfe_tap2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x001f, 0, wr_val) 676 #define rd_rxc_dfe_tap2() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd011, 3, 11, __ERR) 677 #define wr_rxc_dfe_tap2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x1f00, 8, wr_val) 678 #define rd_rxd_dfe_tap2() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd011, 11, 11, __ERR) 679 #define wr_rxd_dfe_tap2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x001f, 0, wr_val) 680 #define rd_rxa_dfe_tap3() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd012, 3, 11, __ERR) 681 #define wr_rxa_dfe_tap3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd012, 0x1f00, 8, wr_val) 682 #define rd_rxb_dfe_tap3() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd012, 11, 11, __ERR) 683 #define wr_rxb_dfe_tap3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd012, 0x001f, 0, wr_val) 684 #define rd_rxc_dfe_tap3() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd013, 3, 11, __ERR) 685 #define wr_rxc_dfe_tap3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd013, 0x1f00, 8, wr_val) 686 #define rd_rxd_dfe_tap3() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd013, 11, 11, __ERR) 687 #define wr_rxd_dfe_tap3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd013, 0x001f, 0, wr_val) 688 #define rd_rxa_dfe_tap4() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 0, 12, __ERR) 689 #define wr_rxa_dfe_tap4(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0xf000, 12, wr_val) 690 #define rd_rxb_dfe_tap4() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 4, 12, __ERR) 691 #define wr_rxb_dfe_tap4(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x0f00, 8, wr_val) 692 #define rd_rxc_dfe_tap4() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 8, 12, __ERR) 693 #define wr_rxc_dfe_tap4(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x00f0, 4, wr_val) 694 #define rd_rxd_dfe_tap4() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 12, 12, __ERR) 695 #define wr_rxd_dfe_tap4(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x000f, 0, wr_val) 696 #define rd_rxa_dfe_tap5() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 0, 12, __ERR) 697 #define wr_rxa_dfe_tap5(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0xf000, 12, wr_val) 698 #define rd_rxb_dfe_tap5() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 4, 12, __ERR) 699 #define wr_rxb_dfe_tap5(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x0f00, 8, wr_val) 700 #define rd_rxc_dfe_tap5() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 8, 12, __ERR) 701 #define wr_rxc_dfe_tap5(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x00f0, 4, wr_val) 702 #define rd_rxd_dfe_tap5() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 12, 12, __ERR) 703 #define wr_rxd_dfe_tap5(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x000f, 0, wr_val) 704 #define rd_rxa_dfe_tap6() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 0, 12, __ERR) 705 #define wr_rxa_dfe_tap6(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0xf000, 12, wr_val) 706 #define rd_rxb_dfe_tap6() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 4, 12, __ERR) 707 #define wr_rxb_dfe_tap6(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x0f00, 8, wr_val) 708 #define rd_rxc_dfe_tap6() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 8, 12, __ERR) 709 #define wr_rxc_dfe_tap6(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x00f0, 4, wr_val) 710 #define rd_rxd_dfe_tap6() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 12, 12, __ERR) 711 #define wr_rxd_dfe_tap6(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x000f, 0, wr_val) 712 #define rd_rxa_dfe_tap7() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 0, 12, __ERR) 713 #define wr_rxa_dfe_tap7(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0xf000, 12, wr_val) 714 #define rd_rxb_dfe_tap7() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 4, 12, __ERR) 715 #define wr_rxb_dfe_tap7(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x0f00, 8, wr_val) 716 #define rd_rxc_dfe_tap7() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 8, 12, __ERR) 717 #define wr_rxc_dfe_tap7(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x00f0, 4, wr_val) 718 #define rd_rxd_dfe_tap7() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 12, 12, __ERR) 719 #define wr_rxd_dfe_tap7(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x000f, 0, wr_val) 720 #define rd_rxa_dfe_tap8() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 0, 12, __ERR) 721 #define wr_rxa_dfe_tap8(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0xf000, 12, wr_val) 722 #define rd_rxb_dfe_tap8() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 4, 12, __ERR) 723 #define wr_rxb_dfe_tap8(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x0f00, 8, wr_val) 724 #define rd_rxc_dfe_tap8() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 8, 12, __ERR) 725 #define wr_rxc_dfe_tap8(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x00f0, 4, wr_val) 726 #define rd_rxd_dfe_tap8() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 12, 12, __ERR) 727 #define wr_rxd_dfe_tap8(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x000f, 0, wr_val) 728 #define rd_rxa_dfe_tap9() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 0, 12, __ERR) 729 #define wr_rxa_dfe_tap9(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0xf000, 12, wr_val) 730 #define rd_rxb_dfe_tap9() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 4, 12, __ERR) 731 #define wr_rxb_dfe_tap9(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x0f00, 8, wr_val) 732 #define rd_rxc_dfe_tap9() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 8, 12, __ERR) 733 #define wr_rxc_dfe_tap9(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x00f0, 4, wr_val) 734 #define rd_rxd_dfe_tap9() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 12, 12, __ERR) 735 #define wr_rxd_dfe_tap9(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x000f, 0, wr_val) 736 #define rd_rxa_dfe_tap10() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 0, 12, __ERR) 737 #define wr_rxa_dfe_tap10(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0xf000, 12, wr_val) 738 #define rd_rxb_dfe_tap10() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 4, 12, __ERR) 739 #define wr_rxb_dfe_tap10(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x0f00, 8, wr_val) 740 #define rd_rxc_dfe_tap10() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 8, 12, __ERR) 741 #define wr_rxc_dfe_tap10(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x00f0, 4, wr_val) 742 #define rd_rxd_dfe_tap10() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 12, 12, __ERR) 743 #define wr_rxd_dfe_tap10(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x000f, 0, wr_val) 744 #define rd_rxa_dfe_tap11() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 0, 12, __ERR) 745 #define wr_rxa_dfe_tap11(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0xf000, 12, wr_val) 746 #define rd_rxb_dfe_tap11() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 4, 12, __ERR) 747 #define wr_rxb_dfe_tap11(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0f00, 8, wr_val) 748 #define rd_rxc_dfe_tap11() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 8, 12, __ERR) 749 #define wr_rxc_dfe_tap11(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x00f0, 4, wr_val) 750 #define rd_rxd_dfe_tap11() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 12, 12, __ERR) 751 #define wr_rxd_dfe_tap11(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x000f, 0, wr_val) 752 #define rd_rxa_dfe_tap12() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 0, 12, __ERR) 753 #define wr_rxa_dfe_tap12(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0xf000, 12, wr_val) 754 #define rd_rxb_dfe_tap12() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 4, 12, __ERR) 755 #define wr_rxb_dfe_tap12(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x0f00, 8, wr_val) 756 #define rd_rxc_dfe_tap12() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 8, 12, __ERR) 757 #define wr_rxc_dfe_tap12(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x00f0, 4, wr_val) 758 #define rd_rxd_dfe_tap12() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 12, 12, __ERR) 759 #define wr_rxd_dfe_tap12(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x000f, 0, wr_val) 760 #define rd_rxa_dfe_tap13() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 0, 12, __ERR) 761 #define wr_rxa_dfe_tap13(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0xf000, 12, wr_val) 762 #define rd_rxb_dfe_tap13() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 4, 12, __ERR) 763 #define wr_rxb_dfe_tap13(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0f00, 8, wr_val) 764 #define rd_rxc_dfe_tap13() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 8, 12, __ERR) 765 #define wr_rxc_dfe_tap13(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x00f0, 4, wr_val) 766 #define rd_rxd_dfe_tap13() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 12, 12, __ERR) 767 #define wr_rxd_dfe_tap13(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x000f, 0, wr_val) 768 #define rd_rxa_dfe_tap14() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 0, 12, __ERR) 769 #define wr_rxa_dfe_tap14(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0xf000, 12, wr_val) 770 #define rd_rxb_dfe_tap14() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 4, 12, __ERR) 771 #define wr_rxb_dfe_tap14(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x0f00, 8, wr_val) 772 #define rd_rxc_dfe_tap14() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 8, 12, __ERR) 773 #define wr_rxc_dfe_tap14(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x00f0, 4, wr_val) 774 #define rd_rxd_dfe_tap14() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 12, 12, __ERR) 775 #define wr_rxd_dfe_tap14(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x000f, 0, wr_val) 776 #define rd_rxa_dfe_tap7_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 0, 14, __ERR) 777 #define wr_rxa_dfe_tap7_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0xc000, 14, wr_val) 778 #define rd_rxa_dfe_tap8_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 2, 14, __ERR) 779 #define wr_rxa_dfe_tap8_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x3000, 12, wr_val) 780 #define rd_rxb_dfe_tap7_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 4, 14, __ERR) 781 #define wr_rxb_dfe_tap7_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0c00, 10, wr_val) 782 #define rd_rxb_dfe_tap8_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 6, 14, __ERR) 783 #define wr_rxb_dfe_tap8_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0300, 8, wr_val) 784 #define rd_rxc_dfe_tap7_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 8, 14, __ERR) 785 #define wr_rxc_dfe_tap7_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x00c0, 6, wr_val) 786 #define rd_rxc_dfe_tap8_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 10, 14, __ERR) 787 #define wr_rxc_dfe_tap8_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0030, 4, wr_val) 788 #define rd_rxd_dfe_tap7_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 12, 14, __ERR) 789 #define wr_rxd_dfe_tap7_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x000c, 2, wr_val) 790 #define rd_rxd_dfe_tap8_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd025, 14, 14, __ERR) 791 #define wr_rxd_dfe_tap8_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0003, 0, wr_val) 792 #define rd_rxa_dfe_tap9_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 0, 14, __ERR) 793 #define wr_rxa_dfe_tap9_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0xc000, 14, wr_val) 794 #define rd_rxa_dfe_tap10_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 2, 14, __ERR) 795 #define wr_rxa_dfe_tap10_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x3000, 12, wr_val) 796 #define rd_rxb_dfe_tap9_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 4, 14, __ERR) 797 #define wr_rxb_dfe_tap9_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0c00, 10, wr_val) 798 #define rd_rxb_dfe_tap10_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 6, 14, __ERR) 799 #define wr_rxb_dfe_tap10_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0300, 8, wr_val) 800 #define rd_rxc_dfe_tap9_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 8, 14, __ERR) 801 #define wr_rxc_dfe_tap9_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x00c0, 6, wr_val) 802 #define rd_rxc_dfe_tap10_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 10, 14, __ERR) 803 #define wr_rxc_dfe_tap10_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0030, 4, wr_val) 804 #define rd_rxd_dfe_tap9_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 12, 14, __ERR) 805 #define wr_rxd_dfe_tap9_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x000c, 2, wr_val) 806 #define rd_rxd_dfe_tap10_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd026, 14, 14, __ERR) 807 #define wr_rxd_dfe_tap10_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0003, 0, wr_val) 808 #define rd_rxa_dfe_tap11_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 0, 14, __ERR) 809 #define wr_rxa_dfe_tap11_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0xc000, 14, wr_val) 810 #define rd_rxa_dfe_tap12_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 2, 14, __ERR) 811 #define wr_rxa_dfe_tap12_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x3000, 12, wr_val) 812 #define rd_rxb_dfe_tap11_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 4, 14, __ERR) 813 #define wr_rxb_dfe_tap11_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0c00, 10, wr_val) 814 #define rd_rxb_dfe_tap12_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 6, 14, __ERR) 815 #define wr_rxb_dfe_tap12_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0300, 8, wr_val) 816 #define rd_rxc_dfe_tap11_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 8, 14, __ERR) 817 #define wr_rxc_dfe_tap11_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x00c0, 6, wr_val) 818 #define rd_rxc_dfe_tap12_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 10, 14, __ERR) 819 #define wr_rxc_dfe_tap12_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0030, 4, wr_val) 820 #define rd_rxd_dfe_tap11_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 12, 14, __ERR) 821 #define wr_rxd_dfe_tap11_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x000c, 2, wr_val) 822 #define rd_rxd_dfe_tap12_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd027, 14, 14, __ERR) 823 #define wr_rxd_dfe_tap12_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0003, 0, wr_val) 824 #define rd_rxa_dfe_tap13_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 0, 14, __ERR) 825 #define wr_rxa_dfe_tap13_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0xc000, 14, wr_val) 826 #define rd_rxa_dfe_tap14_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 2, 14, __ERR) 827 #define wr_rxa_dfe_tap14_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x3000, 12, wr_val) 828 #define rd_rxb_dfe_tap13_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 4, 14, __ERR) 829 #define wr_rxb_dfe_tap13_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0c00, 10, wr_val) 830 #define rd_rxb_dfe_tap14_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 6, 14, __ERR) 831 #define wr_rxb_dfe_tap14_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0300, 8, wr_val) 832 #define rd_rxc_dfe_tap13_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 8, 14, __ERR) 833 #define wr_rxc_dfe_tap13_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x00c0, 6, wr_val) 834 #define rd_rxc_dfe_tap14_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 10, 14, __ERR) 835 #define wr_rxc_dfe_tap14_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0030, 4, wr_val) 836 #define rd_rxd_dfe_tap13_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 12, 14, __ERR) 837 #define wr_rxd_dfe_tap13_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x000c, 2, wr_val) 838 #define rd_rxd_dfe_tap14_mux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd028, 14, 14, __ERR) 839 #define wr_rxd_dfe_tap14_mux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0003, 0, wr_val) 840 #define rd_preset_dsc_afe_bank() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd029, 15, 15, __ERR) 841 #define wr_preset_dsc_afe_bank(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x0001, 0, wr_val) 842 #define rd_rx_vga_ctrl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd04d, 1, 9, __ERR) 843 #define rd_rx_data_thresh_sel() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd04d, 9, 9, __ERR) 844 #define rd_trnsum_b_low() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd042, 0, 8, __ERR) 845 #define rd_trnsum_c() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd045, 0, 0, __ERR) 846 #define rd_trnsum_b() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd043, 0, 0, __ERR) 847 #define rd_trnsum_a_low() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd040, 0, 8, __ERR) 848 #define rd_trnsum_a() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd041, 0, 0, __ERR) 849 #define rd_trnsum_c_low() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd044, 0, 8, __ERR) 850 #define rd_trnsum_d() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd047, 0, 0, __ERR) 851 #define rd_trnsum_d_low() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd046, 0, 8, __ERR) 852 #define rd_trnsum_low() _phy8806x_tsc_pmd_rde_field(pa, 0xd048, 0, 6, __ERR) 853 #define rd_trnsum() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd049, 0, 0, __ERR) 854 #define rd_dc_offset_bin() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd04c, 9, 9, __ERR) 855 #define rd_rx_pi_manual_strobe() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd053, 4, 15, __ERR) 856 #define wr_rx_pi_manual_strobe(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x0800, 11, wr_val) 857 #define rd_rx_pi_manual_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd053, 5, 15, __ERR) 858 #define wr_rx_pi_manual_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x0400, 10, wr_val) 859 #define rd_rx_pi_phase_step_dir() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd053, 6, 15, __ERR) 860 #define wr_rx_pi_phase_step_dir(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x0200, 9, wr_val) 861 #define rd_rx_pi_phase_step_cnt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd053, 7, 13, __ERR) 862 #define wr_rx_pi_phase_step_cnt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x01c0, 6, wr_val) 863 #define rd_rx_pi_slicers_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd053, 10, 10, __ERR) 864 #define wr_rx_pi_slicers_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x003f, 0, wr_val) 865 #define rd_trnsum_tap_sign() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd058, 0, 8, __ERR) 866 #define wr_trnsum_tap_sign(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd058, 0xff00, 8, wr_val) 867 #define rd_trnsum_tap_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd058, 8, 8, __ERR) 868 #define wr_trnsum_tap_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd058, 0x00ff, 0, wr_val) 869 #define rd_trnsum_inv_pattern_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd056, 0, 15, __ERR) 870 #define wr_trnsum_inv_pattern_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd056, 0x8000, 15, wr_val) 871 #define rd_trnsum_edge_pattern_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd056, 1, 15, __ERR) 872 #define wr_trnsum_edge_pattern_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd056, 0x4000, 14, wr_val) 873 #define rd_trnsum_pattern_full_check_off() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd056, 3, 15, __ERR) 874 #define wr_trnsum_pattern_full_check_off(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd056, 0x1000, 12, wr_val) 875 #define rd_trnsum_pattern() _phy8806x_tsc_pmd_rde_field(pa, 0xd056, 6, 6, __ERR) 876 #define wr_trnsum_pattern(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd056, 0x03ff, 0, wr_val) 877 #define rd_trnsum_pattern_bit_en() _phy8806x_tsc_pmd_rde_field(pa, 0xd057, 6, 6, __ERR) 878 #define wr_trnsum_pattern_bit_en(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd057, 0x03ff, 0, wr_val) 879 #define rd_trnsum_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 0, 15, __ERR) 880 #define wr_trnsum_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x8000, 15, wr_val) 881 #define rd_trnsum_eye_closure_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 1, 15, __ERR) 882 #define wr_trnsum_eye_closure_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x4000, 14, wr_val) 883 #define rd_trnsum_random_tapsel_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 2, 15, __ERR) 884 #define wr_trnsum_random_tapsel_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x2000, 13, wr_val) 885 #define rd_trnsum_qphase_mult_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 3, 15, __ERR) 886 #define wr_trnsum_qphase_mult_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x1000, 12, wr_val) 887 #define rd_trnsum_cor_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 6, 14, __ERR) 888 #define wr_trnsum_cor_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0300, 8, wr_val) 889 #define rd_trnsum_tap_range_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 9, 13, __ERR) 890 #define wr_trnsum_tap_range_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0070, 4, wr_val) 891 #define rd_trnsum_sel_emux() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 13, 15, __ERR) 892 #define wr_trnsum_sel_emux(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0004, 2, wr_val) 893 #define rd_trnsum_gain() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd055, 14, 14, __ERR) 894 #define wr_trnsum_gain(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0003, 0, wr_val) 895 #define rd_trnsum_eye_closure_err_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd054, 10, 15, __ERR) 896 #define wr_trnsum_eye_closure_err_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd054, 0x0020, 5, wr_val) 897 #define rd_trnsum_eye_close_prev_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd054, 11, 15, __ERR) 898 #define wr_trnsum_eye_close_prev_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd054, 0x0010, 4, wr_val) 899 #define rd_trnsum_pattern_match_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd054, 12, 14, __ERR) 900 #define wr_trnsum_pattern_match_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd054, 0x000c, 2, wr_val) 901 #define rd_trnsum_disable_sm_clear() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd054, 14, 15, __ERR) 902 #define wr_trnsum_disable_sm_clear(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd054, 0x0002, 1, wr_val) 903 #define rd_trnsum_clr_sc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd054, 15, 15, __ERR) 904 #define wr_trnsum_clr_sc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd054, 0x0001, 0, wr_val) 905 #define rd_cdr_prop_bw_extend() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 5, 15, __ERR) 906 #define wr_cdr_prop_bw_extend(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0400, 10, wr_val) 907 #define rd_cdr_1g_manual_strobe() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 6, 15, __ERR) 908 #define wr_cdr_1g_manual_strobe(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0200, 9, wr_val) 909 #define rd_cdr_1g_manual_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 7, 15, __ERR) 910 #define wr_cdr_1g_manual_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0100, 8, wr_val) 911 #define rd_phs_sum_ignore_dsc_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 8, 15, __ERR) 912 #define wr_phs_sum_ignore_dsc_lock(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0080, 7, wr_val) 913 #define rd_tx_pi_loop_timing_src_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 9, 15, __ERR) 914 #define wr_tx_pi_loop_timing_src_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0040, 6, wr_val) 915 #define rd_cdr_1g_force_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 10, 15, __ERR) 916 #define wr_cdr_1g_force_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0020, 5, wr_val) 917 #define rd_cdr_1g_swap_pz() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 11, 15, __ERR) 918 #define wr_cdr_1g_swap_pz(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0010, 4, wr_val) 919 #define rd_cdr_lm_thr_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd052, 12, 12, __ERR) 920 #define wr_cdr_lm_thr_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x000f, 0, wr_val) 921 #define rd_cdr_freq_override_val() _phy8806x_tsc_pmd_rde_field(pa, 0xd051, 0, 5, __ERR) 922 #define wr_cdr_freq_override_val(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd051, 0xffe0, 5, wr_val) 923 #define rd_cdr_zero_polarity() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 6, 15, __ERR) 924 #define wr_cdr_zero_polarity(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0200, 9, wr_val) 925 #define rd_cdr_freq_override_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 7, 15, __ERR) 926 #define wr_cdr_freq_override_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0100, 8, wr_val) 927 #define rd_cdr_integ_sat_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 8, 15, __ERR) 928 #define wr_cdr_integ_sat_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0080, 7, wr_val) 929 #define rd_cdr_phase_err_frz() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 9, 15, __ERR) 930 #define wr_cdr_phase_err_frz(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0040, 6, wr_val) 931 #define rd_cdr_integ_reg_clr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 10, 15, __ERR) 932 #define wr_cdr_integ_reg_clr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0020, 5, wr_val) 933 #define rd_cdr_freq_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 12, 15, __ERR) 934 #define wr_cdr_freq_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0008, 3, wr_val) 935 #define rd_os_pattern_enhanced() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 13, 15, __ERR) 936 #define wr_os_pattern_enhanced(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0004, 2, wr_val) 937 #define rd_br_pd_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 14, 15, __ERR) 938 #define wr_br_pd_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0002, 1, wr_val) 939 #define rd_os_all_edges() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd050, 15, 15, __ERR) 940 #define wr_os_all_edges(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0001, 0, wr_val) 941 #define rd_tdt_cycle_bin() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd059, 0, 12, __ERR) 942 #define wr_tdt_cycle_bin(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0xf000, 12, wr_val) 943 #define rd_tdt_cycle_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd059, 4, 12, __ERR) 944 #define wr_tdt_cycle_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x0f00, 8, wr_val) 945 #define rd_tdt_trnsum_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd059, 8, 15, __ERR) 946 #define wr_tdt_trnsum_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x0080, 7, wr_val) 947 #define rd_tdt_prbs_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd059, 9, 15, __ERR) 948 #define wr_tdt_prbs_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x0040, 6, wr_val) 949 #define rd_tdt_bit_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd059, 10, 10, __ERR) 950 #define wr_tdt_bit_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x003f, 0, wr_val) 951 #define rd_cdr_1g_trnsum_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05a, 14, 15, __ERR) 952 #define wr_cdr_1g_trnsum_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05a, 0x0002, 1, wr_val) 953 #define rd_tdt_prbs_slip() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05a, 15, 15, __ERR) 954 #define wr_tdt_prbs_slip(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05a, 0x0001, 0, wr_val) 955 #define rd_vga_write() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 0, 15, __ERR) 956 #define wr_vga_write(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x8000, 15, wr_val) 957 #define rd_rx_vga_ctrl_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 1, 9, __ERR) 958 #define wr_rx_vga_ctrl_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x7f00, 8, wr_val) 959 #define rd_vga_inc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 8, 15, __ERR) 960 #define wr_vga_inc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0080, 7, wr_val) 961 #define rd_vga_dec() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 10, 15, __ERR) 962 #define wr_vga_dec(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0020, 5, wr_val) 963 #define rd_dc_offs_write_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 11, 15, __ERR) 964 #define wr_dc_offs_write_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0010, 4, wr_val) 965 #define rd_uc_trnsum_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 12, 15, __ERR) 966 #define wr_uc_trnsum_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0008, 3, wr_val) 967 #define rd_vga_timer_t2() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05c, 13, 13, __ERR) 968 #define wr_vga_timer_t2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0007, 0, wr_val) 969 #define rd_data_thresh_write() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05d, 0, 15, __ERR) 970 #define wr_data_thresh_write(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x8000, 15, wr_val) 971 #define rd_data_thresh_sel_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05d, 1, 9, __ERR) 972 #define wr_data_thresh_sel_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x7f00, 8, wr_val) 973 #define rd_thresh_step_size() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05d, 10, 14, __ERR) 974 #define wr_thresh_step_size(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x0030, 4, wr_val) 975 #define rd_thresh_timer_t1() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05d, 14, 14, __ERR) 976 #define wr_thresh_timer_t1(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x0003, 0, wr_val) 977 #define rd_dc_offs_write_frc_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 0, 15, __ERR) 978 #define wr_dc_offs_write_frc_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x8000, 15, wr_val) 979 #define rd_dc_offs_write_val() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd05e, 1, 9, __ERR) 980 #define wr_dc_offs_write_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x7f00, 8, wr_val) 981 #define rd_dc_offs_acc_clr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 8, 15, __ERR) 982 #define wr_dc_offs_acc_clr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0080, 7, wr_val) 983 #define rd_dc_offs_gain() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 9, 14, __ERR) 984 #define wr_dc_offs_gain(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0060, 5, wr_val) 985 #define rd_dc_offs_gradient_invert() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 11, 15, __ERR) 986 #define wr_dc_offs_gradient_invert(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0010, 4, wr_val) 987 #define rd_dc_offs_hys_mag() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 12, 15, __ERR) 988 #define wr_dc_offs_hys_mag(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0008, 3, wr_val) 989 #define rd_dc_offs_hys_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 13, 15, __ERR) 990 #define wr_dc_offs_hys_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0004, 2, wr_val) 991 #define rd_dc_offs_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd05e, 15, 15, __ERR) 992 #define wr_dc_offs_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0001, 0, wr_val) 993 #define rd_eee_mode_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 14, 15, __ERR) 994 #define wr_eee_mode_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0002, 1, wr_val) 995 #define rd_eee_quiet_rx_afe_pwrdwn_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 13, 15, __ERR) 996 #define wr_eee_quiet_rx_afe_pwrdwn_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0004, 2, wr_val) 997 #define rd_ignore_rx_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 12, 15, __ERR) 998 #define wr_ignore_rx_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0008, 3, wr_val) 999 #define rd_cl72_timer_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 11, 15, __ERR) 1000 #define wr_cl72_timer_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0010, 4, wr_val) 1001 #define rd_uc_tune_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 10, 15, __ERR) 1002 #define wr_uc_tune_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0020, 5, wr_val) 1003 #define rd_hw_tune_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 9, 15, __ERR) 1004 #define wr_hw_tune_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0040, 6, wr_val) 1005 #define rd_eee_measure_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 7, 15, __ERR) 1006 #define wr_eee_measure_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0100, 8, wr_val) 1007 #define rd_uc_ack_dsc_eee_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 4, 15, __ERR) 1008 #define wr_uc_ack_dsc_eee_done(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0800, 11, wr_val) 1009 #define rd_uc_ack_dsc_restart() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 2, 15, __ERR) 1010 #define wr_uc_ack_dsc_restart(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x2000, 13, wr_val) 1011 #define rd_uc_ack_dsc_config() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 1, 15, __ERR) 1012 #define wr_uc_ack_dsc_config(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x4000, 14, wr_val) 1013 #define rd_set_meas_incomplete() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd060, 0, 15, __ERR) 1014 #define wr_set_meas_incomplete(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x8000, 15, wr_val) 1015 #define rd_rx_dsc_lock_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 15, 15, __ERR) 1016 #define wr_rx_dsc_lock_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0001, 0, wr_val) 1017 #define rd_rx_dsc_lock_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 14, 15, __ERR) 1018 #define wr_rx_dsc_lock_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0002, 1, wr_val) 1019 #define rd_dsc_clr_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 13, 15, __ERR) 1020 #define wr_dsc_clr_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0004, 2, wr_val) 1021 #define rd_dsc_clr_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 12, 15, __ERR) 1022 #define wr_dsc_clr_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0008, 3, wr_val) 1023 #define rd_trnsum_frz_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 11, 15, __ERR) 1024 #define wr_trnsum_frz_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0010, 4, wr_val) 1025 #define rd_trnsum_frz_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 10, 15, __ERR) 1026 #define wr_trnsum_frz_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0020, 5, wr_val) 1027 #define rd_timer_done_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 9, 15, __ERR) 1028 #define wr_timer_done_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0040, 6, wr_val) 1029 #define rd_timer_done_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 8, 15, __ERR) 1030 #define wr_timer_done_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0080, 7, wr_val) 1031 #define rd_freq_upd_en_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 7, 15, __ERR) 1032 #define wr_freq_upd_en_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0100, 8, wr_val) 1033 #define rd_freq_upd_en_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 6, 15, __ERR) 1034 #define wr_freq_upd_en_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0200, 9, wr_val) 1035 #define rd_cdr_frz_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 5, 15, __ERR) 1036 #define wr_cdr_frz_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0400, 10, wr_val) 1037 #define rd_cdr_frz_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 4, 15, __ERR) 1038 #define wr_cdr_frz_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0800, 11, wr_val) 1039 #define rd_trnsum_clr_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 3, 15, __ERR) 1040 #define wr_trnsum_clr_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x1000, 12, wr_val) 1041 #define rd_trnsum_clr_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd061, 2, 15, __ERR) 1042 #define wr_trnsum_clr_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x2000, 13, wr_val) 1043 #define rd_eee_lfsr_cnt() _phy8806x_tsc_pmd_rde_field(pa, 0xd062, 3, 3, __ERR) 1044 #define wr_eee_lfsr_cnt(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd062, 0x1fff, 0, wr_val) 1045 #define rd_measure_lfsr_cnt() _phy8806x_tsc_pmd_rde_field(pa, 0xd063, 3, 3, __ERR) 1046 #define wr_measure_lfsr_cnt(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd063, 0x1fff, 0, wr_val) 1047 #define rd_acq_cdr_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd064, 11, 11, __ERR) 1048 #define wr_acq_cdr_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd064, 0x001f, 0, wr_val) 1049 #define rd_cdr_settle_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd064, 6, 11, __ERR) 1050 #define wr_cdr_settle_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd064, 0x03e0, 5, wr_val) 1051 #define rd_hw_tune_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd064, 1, 11, __ERR) 1052 #define wr_hw_tune_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd064, 0x7c00, 10, wr_val) 1053 #define rd_measure_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd065, 11, 11, __ERR) 1054 #define wr_measure_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd065, 0x001f, 0, wr_val) 1055 #define rd_eee_acq_cdr_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd065, 6, 11, __ERR) 1056 #define wr_eee_acq_cdr_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd065, 0x03e0, 5, wr_val) 1057 #define rd_eee_cdr_settle_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd065, 1, 11, __ERR) 1058 #define wr_eee_cdr_settle_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd065, 0x7c00, 10, wr_val) 1059 #define rd_eee_hw_tune_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd066, 11, 11, __ERR) 1060 #define wr_eee_hw_tune_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd066, 0x001f, 0, wr_val) 1061 #define rd_eee_ana_pwr_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd066, 1, 11, __ERR) 1062 #define wr_eee_ana_pwr_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd066, 0x7c00, 10, wr_val) 1063 #define rd_cdr_bwsel_integ_acqcdr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd067, 12, 12, __ERR) 1064 #define wr_cdr_bwsel_integ_acqcdr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x000f, 0, wr_val) 1065 #define rd_cdr_bwsel_integ_eee_acqcdr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd067, 8, 12, __ERR) 1066 #define wr_cdr_bwsel_integ_eee_acqcdr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x00f0, 4, wr_val) 1067 #define rd_cdr_bwsel_integ_norm() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd067, 4, 12, __ERR) 1068 #define wr_cdr_bwsel_integ_norm(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x0f00, 8, wr_val) 1069 #define rd_cdr_bwsel_prop_acqcdr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd067, 3, 15, __ERR) 1070 #define wr_cdr_bwsel_prop_acqcdr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x1000, 12, wr_val) 1071 #define rd_cdr_bwsel_prop_norm() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd067, 1, 15, __ERR) 1072 #define wr_cdr_bwsel_prop_norm(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x4000, 14, wr_val) 1073 #define rd_phase_err_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd068, 12, 12, __ERR) 1074 #define wr_phase_err_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x000f, 0, wr_val) 1075 #define rd_eee_phase_err_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd068, 8, 12, __ERR) 1076 #define wr_eee_phase_err_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x00f0, 4, wr_val) 1077 #define rd_phase_err_offset_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd068, 6, 14, __ERR) 1078 #define wr_phase_err_offset_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0300, 8, wr_val) 1079 #define rd_eee_phase_err_offset_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd068, 4, 14, __ERR) 1080 #define wr_eee_phase_err_offset_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0c00, 10, wr_val) 1081 #define rd_cdr_bwsel_prop_eee_acqcdr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd068, 1, 15, __ERR) 1082 #define wr_cdr_bwsel_prop_eee_acqcdr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x4000, 14, wr_val) 1083 #define rd_rx_restart_pmd() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd069, 15, 15, __ERR) 1084 #define wr_rx_restart_pmd(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd069, 0x0001, 0, wr_val) 1085 #define rd_rx_restart_pmd_hold() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd069, 14, 15, __ERR) 1086 #define wr_rx_restart_pmd_hold(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd069, 0x0002, 1, wr_val) 1087 #define rd_dsc_state_one_hot() _phy8806x_tsc_pmd_rde_field(pa, 0xd06b, 6, 6, __ERR) 1088 #define rd_dsc_state_eee_one_hot() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06c, 9, 9, __ERR) 1089 #define rd_restart_pi_ext_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06d, 15, 15, __ERR) 1090 #define rd_restart_sigdet() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06d, 14, 15, __ERR) 1091 #define rd_restart_pmd_restart() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06d, 13, 15, __ERR) 1092 #define rd_eee_quiet_from_eee_states() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06d, 12, 15, __ERR) 1093 #define rd_dsc_state() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06e, 0, 11, __ERR) 1094 #define rd_dsc_sm_scratch() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06e, 5, 13, __ERR) 1095 #define rd_cdr_lm_outoflock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06e, 8, 15, __ERR) 1096 #define rd_dsc_sm_gp_uc_req() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06e, 9, 10, __ERR) 1097 #define rd_dsc_sm_ready_for_cmd() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06e, 15, 15, __ERR) 1098 #define rd_eee_measure_cnt() _phy8806x_tsc_pmd_rde_field(pa, 0xd06a, 0, 7, __ERR) 1099 #define rd_meas_incomplete() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06a, 14, 15, __ERR) 1100 #define rd_rx_dsc_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd06a, 15, 15, __ERR) 1101 #define rd_rx_pi_cnt_bin_pq() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd076, 0, 8, __ERR) 1102 #define rd_rx_pi_cnt_bin_p() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd076, 8, 8, __ERR) 1103 #define rd_cdr_vco_reg() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd074, 0, 12, __ERR) 1104 #define rd_cdr_phase_error() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd074, 10, 10, __ERR) 1105 #define rd_rx_pi_cnt_bin_lq() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd077, 0, 8, __ERR) 1106 #define rd_rx_pi_cnt_bin_l() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd077, 8, 8, __ERR) 1107 #define rd_rx_pi_cnt_bin_dq() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd075, 0, 8, __ERR) 1108 #define rd_rx_pi_cnt_bin_d() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd075, 8, 8, __ERR) 1109 #define rd_rx_pi_cnt_bin_d_ld() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd071, 0, 8, __ERR) 1110 #define rd_rx_pi_cnt_bin_l_ld() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd071, 8, 8, __ERR) 1111 #define rd_rx_pi_cnt_bin_d_pd() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd070, 0, 8, __ERR) 1112 #define rd_rx_pi_cnt_bin_p_pd() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd070, 8, 8, __ERR) 1113 #define rd_rx_data_15_to_0() _phy8806x_tsc_pmd_rde_reg(pa, 0xd072, __ERR) 1114 #define rd_rx_data_35_to_20() _phy8806x_tsc_pmd_rde_reg(pa, 0xd073, __ERR) 1115 #define rd_cdr_integ_reg() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd078, 0, 0, __ERR) 1116 #define rd_cdr_1g_phase_pointer() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd07a, 8, 8, __ERR) 1117 #define rd_preset_dsc_a_bank() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd07e, 13, 15, __ERR) 1118 #define wr_preset_dsc_a_bank(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd07e, 0x0004, 2, wr_val) 1119 #define rd_preset_dsc_d_bank() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd07e, 14, 15, __ERR) 1120 #define wr_preset_dsc_d_bank(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd07e, 0x0002, 1, wr_val) 1121 #define rd_preset_dsc_c_bank() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd07e, 15, 15, __ERR) 1122 #define wr_preset_dsc_c_bank(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd07e, 0x0001, 0, wr_val) 1123 #define rdc_mdio_blk_addr() _phy8806x_tsc_pmd_rde_field(pa, 0xffdf, 1, 5, __ERR) 1124 #define wrc_mdio_blk_addr(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xffdf, 0x7ff0, 4, wr_val) 1125 #define rdc_mdio_function() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x000d, 0, 14, __ERR) 1126 #define wrc_mdio_function(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0x000d, 0xc000, 14, wr_val) 1127 #define rdc_mdio_devad() _phy8806x_tsc_pmd_rde_field_byte(pa, 0x000d, 11, 11, __ERR) 1128 #define wrc_mdio_devad(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0x000d, 0x001f, 0, wr_val) 1129 #define rdc_mdio_addr_data() _phy8806x_tsc_pmd_rde_reg(pa, 0x000e, __ERR) 1130 #define wrc_mdio_addr_data(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0x000e, wr_val) 1131 #define rdc_mdio_drv_comclk() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdc, 0, 15, __ERR) 1132 #define wrc_mdio_drv_comclk(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdc, 0x8000, 15, wr_val) 1133 #define rdc_mdio_brcst_port_addr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdc, 11, 11, __ERR) 1134 #define wrc_mdio_brcst_port_addr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdc, 0x001f, 0, wr_val) 1135 #define rdc_mdio_multi_prts_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 0, 15, __ERR) 1136 #define wrc_mdio_multi_prts_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x8000, 15, wr_val) 1137 #define rdc_mdio_multi_mmds_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 1, 15, __ERR) 1138 #define wrc_mdio_multi_mmds_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x4000, 14, wr_val) 1139 #define rdc_mdio_dev_pcs_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 9, 15, __ERR) 1140 #define wrc_mdio_dev_pcs_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0040, 6, wr_val) 1141 #define rdc_mdio_dev_dte_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 10, 15, __ERR) 1142 #define wrc_mdio_dev_dte_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0020, 5, wr_val) 1143 #define rdc_mdio_dev_phy_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 11, 15, __ERR) 1144 #define wrc_mdio_dev_phy_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0010, 4, wr_val) 1145 #define rdc_mdio_dev_an_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 12, 15, __ERR) 1146 #define wrc_mdio_dev_an_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0008, 3, wr_val) 1147 #define rdc_mdio_dev_pmd_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 13, 15, __ERR) 1148 #define wrc_mdio_dev_pmd_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0004, 2, wr_val) 1149 #define rdc_mdio_dev_cl22_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xffdd, 15, 15, __ERR) 1150 #define wrc_mdio_dev_cl22_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0001, 0, wr_val) 1151 #define rdc_mdio_aer() _phy8806x_tsc_pmd_rde_reg(pa, 0xffde, __ERR) 1152 #define wrc_mdio_aer(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xffde, wr_val) 1153 #define rdc_micro_core_clk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd200, 14, 15, __ERR) 1154 #define wrc_micro_core_clk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd200, 0x0002, 1, wr_val) 1155 #define rdc_micro_master_clk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd200, 15, 15, __ERR) 1156 #define wrc_micro_master_clk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd200, 0x0001, 0, wr_val) 1157 #define rdc_micro_pram_if_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd201, 12, 15, __ERR) 1158 #define wrc_micro_pram_if_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd201, 0x0008, 3, wr_val) 1159 #define rdc_micro_core_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd201, 14, 15, __ERR) 1160 #define wrc_micro_core_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd201, 0x0002, 1, wr_val) 1161 #define rdc_micro_master_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd201, 15, 15, __ERR) 1162 #define wrc_micro_master_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd201, 0x0001, 0, wr_val) 1163 #define rdc_micro_autoinc_rdaddr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd202, 2, 15, __ERR) 1164 #define wrc_micro_autoinc_rdaddr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x2000, 13, wr_val) 1165 #define rdc_micro_autoinc_wraddr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd202, 3, 15, __ERR) 1166 #define wrc_micro_autoinc_wraddr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x1000, 12, wr_val) 1167 #define rdc_micro_ra_init() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd202, 6, 14, __ERR) 1168 #define wrc_micro_ra_init(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0300, 8, wr_val) 1169 #define rdc_micro_ra_rddatasize() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd202, 10, 14, __ERR) 1170 #define wrc_micro_ra_rddatasize(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0030, 4, wr_val) 1171 #define rdc_micro_ra_wrdatasize() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd202, 14, 14, __ERR) 1172 #define wrc_micro_ra_wrdatasize(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0003, 0, wr_val) 1173 #define rdc_micro_ra_initdone() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd203, 15, 15, __ERR) 1174 #define rdc_micro_ra_wraddr_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd204, __ERR) 1175 #define wrc_micro_ra_wraddr_lsw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd204, wr_val) 1176 #define rdc_micro_ra_wraddr_msw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd205, __ERR) 1177 #define wrc_micro_ra_wraddr_msw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd205, wr_val) 1178 #define rdc_micro_ra_wrdata_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd206, __ERR) 1179 #define wrc_micro_ra_wrdata_lsw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd206, wr_val) 1180 #define rdc_micro_ra_wrdata_msw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd207, __ERR) 1181 #define wrc_micro_ra_wrdata_msw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd207, wr_val) 1182 #define rdc_micro_ra_rdaddr_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd208, __ERR) 1183 #define wrc_micro_ra_rdaddr_lsw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd208, wr_val) 1184 #define rdc_micro_ra_rdaddr_msw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd209, __ERR) 1185 #define wrc_micro_ra_rdaddr_msw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd209, wr_val) 1186 #define rdc_micro_ra_rddata_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd20a, __ERR) 1187 #define rdc_micro_ra_rddata_msw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd20b, __ERR) 1188 #define rdc_micro_pramif_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd20c, 15, 15, __ERR) 1189 #define wrc_micro_pramif_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0001, 0, wr_val) 1190 #define rdc_micro_pramif_ahb_wraddr_lsw() _phy8806x_tsc_pmd_rde_field(pa, 0xd20d, 0, 2, __ERR) 1191 #define wrc_micro_pramif_ahb_wraddr_lsw(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd20d, 0xfffc, 2, wr_val) 1192 #define rdc_micro_pramif_ahb_wraddr_msw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd20e, __ERR) 1193 #define wrc_micro_pramif_ahb_wraddr_msw(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd20e, wr_val) 1194 #define rdc_micro_pvt_tempdata_rmi() _phy8806x_tsc_pmd_rde_field(pa, 0xd210, 6, 6, __ERR) 1195 #define rdc_micro_rmi_to_micro_mbox0() _phy8806x_tsc_pmd_rde_reg(pa, 0xd211, __ERR) 1196 #define wrc_micro_rmi_to_micro_mbox0(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd211, wr_val) 1197 #define rdc_micro_rmi_to_micro_mbox1() _phy8806x_tsc_pmd_rde_reg(pa, 0xd212, __ERR) 1198 #define wrc_micro_rmi_to_micro_mbox1(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd212, wr_val) 1199 #define rdc_micro_to_rmi_mbox0() _phy8806x_tsc_pmd_rde_reg(pa, 0xd213, __ERR) 1200 #define rdc_micro_to_rmi_mbox1() _phy8806x_tsc_pmd_rde_reg(pa, 0xd214, __ERR) 1201 #define rdc_micro_gen_intr_rmi_mbox1wr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd215, 13, 15, __ERR) 1202 #define wrc_micro_gen_intr_rmi_mbox1wr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd215, 0x0004, 2, wr_val) 1203 #define rdc_micro_gen_intr_rmi_mbox0wr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd215, 14, 15, __ERR) 1204 #define wrc_micro_gen_intr_rmi_mbox0wr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd215, 0x0002, 1, wr_val) 1205 #define rdc_micro_rmi_mbox_send_msgin() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd215, 15, 15, __ERR) 1206 #define wrc_micro_rmi_mbox_send_msgin(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd215, 0x0001, 0, wr_val) 1207 #define rdc_micro_pmi_hp_ext_ack_timeout_dis() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd216, 11, 15, __ERR) 1208 #define wrc_micro_pmi_hp_ext_ack_timeout_dis(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0010, 4, wr_val) 1209 #define rdc_micro_pmi_hp_ack_timeout_dis() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd216, 12, 15, __ERR) 1210 #define wrc_micro_pmi_hp_ack_timeout_dis(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0008, 3, wr_val) 1211 #define rdc_micro_sw_pmi_hp_ext_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd216, 13, 15, __ERR) 1212 #define wrc_micro_sw_pmi_hp_ext_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0004, 2, wr_val) 1213 #define rdc_micro_sw_pmi_hp_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd216, 14, 15, __ERR) 1214 #define wrc_micro_sw_pmi_hp_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0002, 1, wr_val) 1215 #define rdc_micro_m0_hresp_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd216, 15, 15, __ERR) 1216 #define wrc_micro_m0_hresp_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0001, 0, wr_val) 1217 #define rdc_micro_pr_default_slave_error() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd217, 13, 15, __ERR) 1218 #define rdc_micro_rmi_default_slave_error() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd217, 14, 15, __ERR) 1219 #define rdc_micro_m0_default_slave_error() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd217, 15, 15, __ERR) 1220 #define rdc_micro_ra_autoinc_nxt_wraddr_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd218, __ERR) 1221 #define rdc_micro_ra_autoinc_nxt_rdaddr_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd219, __ERR) 1222 #define rdc_micro_pr_autoinc_nxt_wraddr_lsw() _phy8806x_tsc_pmd_rde_reg(pa, 0xd21a, __ERR) 1223 #define rdc_micro_pvt_tempdata_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd21b, 3, 15, __ERR) 1224 #define wrc_micro_pvt_tempdata_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd21b, 0x1000, 12, wr_val) 1225 #define rdc_micro_pvt_tempdata_frcval() _phy8806x_tsc_pmd_rde_field(pa, 0xd21b, 6, 6, __ERR) 1226 #define wrc_micro_pvt_tempdata_frcval(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd21b, 0x03ff, 0, wr_val) 1227 #define rdc_micro_ecc_corrupt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd220, 10, 14, __ERR) 1228 #define wrc_micro_ecc_corrupt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd220, 0x0030, 4, wr_val) 1229 #define rdc_micro_ecc_frc_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd220, 14, 15, __ERR) 1230 #define wrc_micro_ecc_frc_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd220, 0x0002, 1, wr_val) 1231 #define rdc_micro_eccg_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd220, 15, 15, __ERR) 1232 #define wrc_micro_eccg_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd220, 0x0001, 0, wr_val) 1233 #define rdc_micro_ra_ecc_wrdata() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd221, 9, 9, __ERR) 1234 #define wrc_micro_ra_ecc_wrdata(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd221, 0x007f, 0, wr_val) 1235 #define rdc_micro_code_ram_ecc_address() _phy8806x_tsc_pmd_rde_field(pa, 0xd222, 1, 1, __ERR) 1236 #define rdc_micro_ra_ecc_rddata() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd223, 9, 9, __ERR) 1237 #define rdc_micro_code_ram_tm() _phy8806x_tsc_pmd_rde_field(pa, 0xd224, 2, 2, __ERR) 1238 #define wrc_micro_code_ram_tm(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd224, 0x3fff, 0, wr_val) 1239 #define rdc_micro_ignore_m0_code_writes() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd225, 0, 15, __ERR) 1240 #define wrc_micro_ignore_m0_code_writes(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x8000, 15, wr_val) 1241 #define rdc_micro_ramclk_noninv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd225, 1, 15, __ERR) 1242 #define wrc_micro_ramclk_noninv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x4000, 14, wr_val) 1243 #define rdc_micro_dr_size() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd225, 2, 10, __ERR) 1244 #define wrc_micro_dr_size(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x3f00, 8, wr_val) 1245 #define rdc_micro_protect_fwcode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd225, 14, 15, __ERR) 1246 #define wrc_micro_protect_fwcode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x0002, 1, wr_val) 1247 #define rdc_micro_dr_looktab_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd225, 15, 15, __ERR) 1248 #define wrc_micro_dr_looktab_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x0001, 0, wr_val) 1249 #define rdc_micro_rmi_m0_systemresetreq_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd227, 6, 15, __ERR) 1250 #define rdc_micro_rmi_m0_lockup_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd227, 7, 15, __ERR) 1251 #define rdc_micro_rmi_ecc_multirow_err_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd227, 9, 15, __ERR) 1252 #define rdc_micro_rmi_ecc_uncorr_err_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd227, 10, 15, __ERR) 1253 #define rdc_micro_rmi_ecc_corr_err_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd227, 11, 15, __ERR) 1254 #define rdc_micro_rmi_mbox_msgout_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd227, 15, 15, __ERR) 1255 #define rdc_micro_rmi_m0_systemresetreq_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd226, 6, 15, __ERR) 1256 #define wrc_micro_rmi_m0_systemresetreq_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0200, 9, wr_val) 1257 #define rdc_micro_rmi_m0_lockup_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd226, 7, 15, __ERR) 1258 #define wrc_micro_rmi_m0_lockup_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0100, 8, wr_val) 1259 #define rdc_micro_rmi_ecc_multirow_err_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd226, 9, 15, __ERR) 1260 #define wrc_micro_rmi_ecc_multirow_err_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0040, 6, wr_val) 1261 #define rdc_micro_rmi_ecc_uncorr_err_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd226, 10, 15, __ERR) 1262 #define wrc_micro_rmi_ecc_uncorr_err_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0020, 5, wr_val) 1263 #define rdc_micro_rmi_ecc_corr_err_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd226, 11, 15, __ERR) 1264 #define wrc_micro_rmi_ecc_corr_err_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0010, 4, wr_val) 1265 #define rdc_micro_rmi_mbox_msgout_intr_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd226, 15, 15, __ERR) 1266 #define wrc_micro_rmi_mbox_msgout_intr_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0001, 0, wr_val) 1267 #define rdc_micro_pmi_hp_ext_fast_bktobk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd228, 5, 15, __ERR) 1268 #define wrc_micro_pmi_hp_ext_fast_bktobk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd228, 0x0400, 10, wr_val) 1269 #define rdc_micro_pmi_hp_ext_fast_dual_meta_ff_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd228, 6, 15, __ERR) 1270 #define wrc_micro_pmi_hp_ext_fast_dual_meta_ff_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd228, 0x0200, 9, wr_val) 1271 #define rdc_micro_pmi_hp_ext_fast_read_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd228, 7, 15, __ERR) 1272 #define wrc_micro_pmi_hp_ext_fast_read_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd228, 0x0100, 8, wr_val) 1273 #define rdc_micro_pmi_hp_fast_bktobk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd228, 13, 15, __ERR) 1274 #define wrc_micro_pmi_hp_fast_bktobk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd228, 0x0004, 2, wr_val) 1275 #define rdc_micro_pmi_hp_fast_dual_meta_ff_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd228, 14, 15, __ERR) 1276 #define wrc_micro_pmi_hp_fast_dual_meta_ff_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd228, 0x0002, 1, wr_val) 1277 #define rdc_micro_pmi_hp_fast_read_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd228, 15, 15, __ERR) 1278 #define wrc_micro_pmi_hp_fast_read_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd228, 0x0001, 0, wr_val) 1279 #define rdc_micro_silicon_debug_status_mux_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd229, 14, 14, __ERR) 1280 #define wrc_micro_silicon_debug_status_mux_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd229, 0x0003, 0, wr_val) 1281 #define rdc_micro_silicon_debug_status_muxed_data() _phy8806x_tsc_pmd_rde_reg(pa, 0xd22a, __ERR) 1282 #define rdc_patt_gen_seq_0() _phy8806x_tsc_pmd_rde_reg(pa, 0xd120, __ERR) 1283 #define wrc_patt_gen_seq_0(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd120, wr_val) 1284 #define rdc_patt_gen_seq_1() _phy8806x_tsc_pmd_rde_reg(pa, 0xd121, __ERR) 1285 #define wrc_patt_gen_seq_1(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd121, wr_val) 1286 #define rdc_patt_gen_seq_2() _phy8806x_tsc_pmd_rde_reg(pa, 0xd122, __ERR) 1287 #define wrc_patt_gen_seq_2(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd122, wr_val) 1288 #define rdc_patt_gen_seq_3() _phy8806x_tsc_pmd_rde_reg(pa, 0xd123, __ERR) 1289 #define wrc_patt_gen_seq_3(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd123, wr_val) 1290 #define rdc_patt_gen_seq_4() _phy8806x_tsc_pmd_rde_reg(pa, 0xd124, __ERR) 1291 #define wrc_patt_gen_seq_4(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd124, wr_val) 1292 #define rdc_patt_gen_seq_5() _phy8806x_tsc_pmd_rde_reg(pa, 0xd125, __ERR) 1293 #define wrc_patt_gen_seq_5(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd125, wr_val) 1294 #define rdc_patt_gen_seq_6() _phy8806x_tsc_pmd_rde_reg(pa, 0xd126, __ERR) 1295 #define wrc_patt_gen_seq_6(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd126, wr_val) 1296 #define rdc_patt_gen_seq_7() _phy8806x_tsc_pmd_rde_reg(pa, 0xd127, __ERR) 1297 #define wrc_patt_gen_seq_7(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd127, wr_val) 1298 #define rdc_patt_gen_seq_8() _phy8806x_tsc_pmd_rde_reg(pa, 0xd128, __ERR) 1299 #define wrc_patt_gen_seq_8(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd128, wr_val) 1300 #define rdc_patt_gen_seq_9() _phy8806x_tsc_pmd_rde_reg(pa, 0xd129, __ERR) 1301 #define wrc_patt_gen_seq_9(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd129, wr_val) 1302 #define rdc_patt_gen_seq_10() _phy8806x_tsc_pmd_rde_reg(pa, 0xd12a, __ERR) 1303 #define wrc_patt_gen_seq_10(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd12a, wr_val) 1304 #define rdc_patt_gen_seq_11() _phy8806x_tsc_pmd_rde_reg(pa, 0xd12b, __ERR) 1305 #define wrc_patt_gen_seq_11(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd12b, wr_val) 1306 #define rdc_patt_gen_seq_12() _phy8806x_tsc_pmd_rde_reg(pa, 0xd12c, __ERR) 1307 #define wrc_patt_gen_seq_12(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd12c, wr_val) 1308 #define rdc_patt_gen_seq_13() _phy8806x_tsc_pmd_rde_reg(pa, 0xd12d, __ERR) 1309 #define wrc_patt_gen_seq_13(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd12d, wr_val) 1310 #define rdc_patt_gen_seq_14() _phy8806x_tsc_pmd_rde_reg(pa, 0xd12e, __ERR) 1311 #define wrc_patt_gen_seq_14(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd12e, wr_val) 1312 #define rdc_refclk_divcnt_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd146, 13, 13, __ERR) 1313 #define wrc_refclk_divcnt_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd146, 0x0007, 0, wr_val) 1314 #define rdc_rescal_in() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd149, 4, 12, __ERR) 1315 #define rdc_cap_select() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd149, 8, 8, __ERR) 1316 #define rdc_dbg_pll_state_one_hot() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd14a, 0, 8, __ERR) 1317 #define rdc_dbg_cap_state_one_hot() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd14a, 8, 11, __ERR) 1318 #define rdc_dbg_fdbck() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd14a, 13, 15, __ERR) 1319 #define rdc_dbg_slowdn_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd14a, 14, 15, __ERR) 1320 #define rdc_dbg_slowdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd14a, 15, 15, __ERR) 1321 #define rdc_refclk_divcnt() _phy8806x_tsc_pmd_rde_field(pa, 0xd145, 2, 2, __ERR) 1322 #define wrc_refclk_divcnt(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd145, 0x3fff, 0, wr_val) 1323 #define rdc_pll_seq_start() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 0, 15, __ERR) 1324 #define wrc_pll_seq_start(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x8000, 15, wr_val) 1325 #define rdc_vco_done_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 1, 15, __ERR) 1326 #define wrc_vco_done_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x4000, 14, wr_val) 1327 #define rdc_freq_det_retry_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 2, 15, __ERR) 1328 #define wrc_freq_det_retry_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x2000, 13, wr_val) 1329 #define rdc_freq_det_restart_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 3, 15, __ERR) 1330 #define wrc_freq_det_restart_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x1000, 12, wr_val) 1331 #define rdc_freq_monitor_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 4, 15, __ERR) 1332 #define wrc_freq_monitor_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0800, 11, wr_val) 1333 #define rdc_slowdn_xor() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 5, 15, __ERR) 1334 #define wrc_slowdn_xor(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0400, 10, wr_val) 1335 #define rdc_vco_rst_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 6, 15, __ERR) 1336 #define wrc_vco_rst_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0200, 9, wr_val) 1337 #define rdc_pll_force_fdone_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 7, 15, __ERR) 1338 #define wrc_pll_force_fdone_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0100, 8, wr_val) 1339 #define rdc_pll_force_fdone() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 8, 15, __ERR) 1340 #define wrc_pll_force_fdone(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0080, 7, wr_val) 1341 #define rdc_pll_force_fpass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 9, 15, __ERR) 1342 #define wrc_pll_force_fpass(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0040, 6, wr_val) 1343 #define rdc_pll_force_cap_done_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 10, 15, __ERR) 1344 #define wrc_pll_force_cap_done_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0020, 5, wr_val) 1345 #define rdc_pll_force_cap_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 11, 15, __ERR) 1346 #define wrc_pll_force_cap_done(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0010, 4, wr_val) 1347 #define rdc_pll_force_cap_pass_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 12, 15, __ERR) 1348 #define wrc_pll_force_cap_pass_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0008, 3, wr_val) 1349 #define rdc_pll_force_cap_pass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 13, 15, __ERR) 1350 #define wrc_pll_force_cap_pass(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0004, 2, wr_val) 1351 #define rdc_pll_lock_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 14, 15, __ERR) 1352 #define wrc_pll_lock_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0002, 1, wr_val) 1353 #define rdc_pll_lock_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd144, 15, 15, __ERR) 1354 #define wrc_pll_lock_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0001, 0, wr_val) 1355 #define rdc_vco_range_adjust() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd147, 0, 11, __ERR) 1356 #define wrc_vco_range_adjust(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0xf800, 11, wr_val) 1357 #define rdc_rescal_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd147, 5, 15, __ERR) 1358 #define wrc_rescal_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x0400, 10, wr_val) 1359 #define rdc_rescal_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd147, 6, 12, __ERR) 1360 #define wrc_rescal_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x03c0, 6, wr_val) 1361 #define rdc_pll_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd147, 11, 11, __ERR) 1362 #define wrc_pll_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x001f, 0, wr_val) 1363 #define rdc_cap_select_m() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 0, 8, __ERR) 1364 #define wrc_cap_select_m(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0xff00, 8, wr_val) 1365 #define rdc_cap_select_m_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 8, 15, __ERR) 1366 #define wrc_cap_select_m_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0080, 7, wr_val) 1367 #define rdc_cap_force_slowdown_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 9, 15, __ERR) 1368 #define wrc_cap_force_slowdown_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0040, 6, wr_val) 1369 #define rdc_cap_force_slowdown() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 10, 15, __ERR) 1370 #define wrc_cap_force_slowdown(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0020, 5, wr_val) 1371 #define rdc_cap_retry_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 11, 15, __ERR) 1372 #define wrc_cap_retry_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0010, 4, wr_val) 1373 #define rdc_cap_restart() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 12, 15, __ERR) 1374 #define wrc_cap_restart(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0008, 3, wr_val) 1375 #define rdc_cap_seq_cya() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 13, 15, __ERR) 1376 #define wrc_cap_seq_cya(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0004, 2, wr_val) 1377 #define rdc_cap_cnt_mask_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 14, 15, __ERR) 1378 #define wrc_cap_cnt_mask_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0002, 1, wr_val) 1379 #define rdc_fast_search_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd143, 15, 15, __ERR) 1380 #define wrc_fast_search_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0001, 0, wr_val) 1381 #define rdc_lost_pll_lock_sm() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 0, 15, __ERR) 1382 #define rdc_cap_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 1, 15, __ERR) 1383 #define rdc_cap_pass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 2, 15, __ERR) 1384 #define rdc_freq_done_sm() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 3, 15, __ERR) 1385 #define rdc_freq_pass_sm() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 4, 15, __ERR) 1386 #define rdc_pll_seq_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 5, 15, __ERR) 1387 #define rdc_pll_seq_pass() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 6, 15, __ERR) 1388 #define rdc_pll_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 7, 15, __ERR) 1389 #define rdc_cap_done_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 9, 15, __ERR) 1390 #define rdc_cap_pass_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 10, 15, __ERR) 1391 #define rdc_freq_done_sm_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 11, 15, __ERR) 1392 #define rdc_freq_pass_sm_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 12, 15, __ERR) 1393 #define rdc_pll_seq_done_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 13, 15, __ERR) 1394 #define rdc_pll_seq_pass_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 14, 15, __ERR) 1395 #define rdc_pll_lock_lh_ll() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd148, 15, 15, __ERR) 1396 #define rdc_res_cal_cntr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd142, 0, 8, __ERR) 1397 #define wrc_res_cal_cntr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd142, 0xff00, 8, wr_val) 1398 #define rdc_win_cal_cntr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd142, 8, 8, __ERR) 1399 #define wrc_win_cal_cntr(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd142, 0x00ff, 0, wr_val) 1400 #define rdc_pre_freq_det_time() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd141, 0, 8, __ERR) 1401 #define wrc_pre_freq_det_time(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd141, 0xff00, 8, wr_val) 1402 #define rdc_retry_time() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd141, 8, 8, __ERR) 1403 #define wrc_retry_time(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd141, 0x00ff, 0, wr_val) 1404 #define rdc_vco_start_time() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd140, 0, 8, __ERR) 1405 #define wrc_vco_start_time(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd140, 0xff00, 8, wr_val) 1406 #define rdc_vco_step_time() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd140, 8, 8, __ERR) 1407 #define wrc_vco_step_time(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd140, 0x00ff, 0, wr_val) 1408 #define rd_afe_sigdet_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a1, 14, 15, __ERR) 1409 #define wr_afe_sigdet_pwrdn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a1, 0x0002, 1, wr_val) 1410 #define rd_ln_rx_s_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a1, 15, 15, __ERR) 1411 #define wr_ln_rx_s_pwrdn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a1, 0x0001, 0, wr_val) 1412 #define rd_ln_rclk20_s_clkgate_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a7, 10, 15, __ERR) 1413 #define wr_ln_rclk20_s_clkgate_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a7, 0x0020, 5, wr_val) 1414 #define rd_pmd_rx_clk_vld_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a7, 11, 15, __ERR) 1415 #define wr_pmd_rx_clk_vld_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a7, 0x0010, 4, wr_val) 1416 #define rd_pmd_rx_clk_vld_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a7, 12, 15, __ERR) 1417 #define wr_pmd_rx_clk_vld_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a7, 0x0008, 3, wr_val) 1418 #define rd_ln_rx_s_comclk_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a7, 13, 15, __ERR) 1419 #define wr_ln_rx_s_comclk_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a7, 0x0004, 2, wr_val) 1420 #define rd_ln_rx_s_comclk_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a7, 14, 15, __ERR) 1421 #define wr_ln_rx_s_comclk_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a7, 0x0002, 1, wr_val) 1422 #define rd_ln_rx_s_clkgate_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a7, 15, 15, __ERR) 1423 #define wr_ln_rx_s_clkgate_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a7, 0x0001, 0, wr_val) 1424 #define rd_sigdet_dp_rstb_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a4, 13, 15, __ERR) 1425 #define wr_sigdet_dp_rstb_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a4, 0x0004, 2, wr_val) 1426 #define rd_ln_rx_dp_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a4, 14, 15, __ERR) 1427 #define wr_ln_rx_dp_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a4, 0x0002, 1, wr_val) 1428 #define rd_ln_rx_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a4, 15, 15, __ERR) 1429 #define wr_ln_rx_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a4, 0x0001, 0, wr_val) 1430 #define rd_afe_rx_rclk20_pwrdn_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a2, 10, 15, __ERR) 1431 #define wr_afe_rx_rclk20_pwrdn_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a2, 0x0020, 5, wr_val) 1432 #define rd_afe_rx_rclk20_pwrdn_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a2, 11, 15, __ERR) 1433 #define wr_afe_rx_rclk20_pwrdn_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a2, 0x0010, 4, wr_val) 1434 #define rd_afe_rx_reset_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a2, 12, 15, __ERR) 1435 #define wr_afe_rx_reset_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a2, 0x0008, 3, wr_val) 1436 #define rd_afe_rx_reset_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a2, 13, 15, __ERR) 1437 #define wr_afe_rx_reset_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a2, 0x0004, 2, wr_val) 1438 #define rd_afe_rx_pwrdn_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a2, 14, 15, __ERR) 1439 #define wr_afe_rx_pwrdn_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a2, 0x0002, 1, wr_val) 1440 #define rd_afe_rx_pwrdn_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a2, 15, 15, __ERR) 1441 #define wr_afe_rx_pwrdn_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a2, 0x0001, 0, wr_val) 1442 #define rd_pmd_ln_rx_h_pwrdn_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1a3, 15, 15, __ERR) 1443 #define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1a3, 0x0001, 0, wr_val) 1444 #define rd_pmd_rx_lane_mode() _phy8806x_tsc_pmd_rde_reg(pa, 0xd1a8, __ERR) 1445 #define rd_afe_rx_rclk20_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1ac, 13, 15, __ERR) 1446 #define rd_afe_rx_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1ac, 14, 15, __ERR) 1447 #define rd_afe_rx_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1ac, 15, 15, __ERR) 1448 #define rd_rx_osr_mode_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c0, 0, 15, __ERR) 1449 #define wr_rx_osr_mode_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c0, 0x8000, 15, wr_val) 1450 #define rd_rx_osr_mode_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c0, 12, 12, __ERR) 1451 #define wr_rx_osr_mode_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c0, 0x000f, 0, wr_val) 1452 #define rd_rx_ln_dp_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c1, 15, 15, __ERR) 1453 #define wr_rx_ln_dp_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c1, 0x0001, 0, wr_val) 1454 #define rd_rx_pll_select() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c7, 15, 15, __ERR) 1455 #define wr_rx_pll_select(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c7, 0x0001, 0, wr_val) 1456 #define rd_rx_hw_fw_handshake_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1ce, 14, 15, __ERR) 1457 #define wr_rx_hw_fw_handshake_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1ce, 0x0002, 1, wr_val) 1458 #define rd_rx_ln_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1ce, 15, 15, __ERR) 1459 #define wr_rx_ln_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1ce, 0x0001, 0, wr_val) 1460 #define rd_pmd_ln_rx_dp_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c3, 14, 15, __ERR) 1461 #define wr_pmd_ln_rx_dp_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c3, 0x0002, 1, wr_val) 1462 #define rd_pmd_ln_rx_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c3, 15, 15, __ERR) 1463 #define wr_pmd_ln_rx_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c3, 0x0001, 0, wr_val) 1464 #define rd_rx_uc_ack_lane_dp_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c5, 14, 15, __ERR) 1465 #define wr_rx_uc_ack_lane_dp_reset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c5, 0x0002, 1, wr_val) 1466 #define rd_rx_uc_ack_lane_cfg_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c5, 15, 15, __ERR) 1467 #define wr_rx_uc_ack_lane_cfg_done(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c5, 0x0001, 0, wr_val) 1468 #define rd_rx_lane_dp_reset_state() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c9, 13, 13, __ERR) 1469 #define rd_rx_lane_reg_reset_occurred() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1c6, 15, 15, __ERR) 1470 #define wr_rx_lane_reg_reset_occurred(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1c6, 0x0001, 0, wr_val) 1471 #define rd_rx_multicast_mask_control() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1ca, 15, 15, __ERR) 1472 #define wr_rx_multicast_mask_control(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1ca, 0x0001, 0, wr_val) 1473 #define rd_rx_multicast_mask_control_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1cb, 11, 15, __ERR) 1474 #define rd_rx_osr_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1cb, 12, 12, __ERR) 1475 #define rd_rx_osr_mode_pin() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1cc, 12, 12, __ERR) 1476 #define rd_osr_mode_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b0, 0, 15, __ERR) 1477 #define wr_osr_mode_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x8000, 15, wr_val) 1478 #define rd_osr_mode_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b0, 12, 12, __ERR) 1479 #define wr_osr_mode_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x000f, 0, wr_val) 1480 #define rd_ln_dp_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b1, 15, 15, __ERR) 1481 #define wr_ln_dp_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0001, 0, wr_val) 1482 #define rd_pll_select() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b7, 15, 15, __ERR) 1483 #define wr_pll_select(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b7, 0x0001, 0, wr_val) 1484 #define rd_hw_fw_handshake_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0be, 14, 15, __ERR) 1485 #define wr_hw_fw_handshake_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0be, 0x0002, 1, wr_val) 1486 #define rd_ln_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0be, 15, 15, __ERR) 1487 #define wr_ln_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0be, 0x0001, 0, wr_val) 1488 #define rd_pmd_ln_dp_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b3, 14, 15, __ERR) 1489 #define wr_pmd_ln_dp_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0002, 1, wr_val) 1490 #define rd_pmd_ln_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b3, 15, 15, __ERR) 1491 #define wr_pmd_ln_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0001, 0, wr_val) 1492 #define rd_uc_ack_lane_dp_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b5, 14, 15, __ERR) 1493 #define wr_uc_ack_lane_dp_reset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0002, 1, wr_val) 1494 #define rd_uc_ack_lane_cfg_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b5, 15, 15, __ERR) 1495 #define wr_uc_ack_lane_cfg_done(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0001, 0, wr_val) 1496 #define rd_lane_dp_reset_state() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b9, 13, 13, __ERR) 1497 #define rd_lane_reg_reset_occurred() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0b6, 15, 15, __ERR) 1498 #define wr_lane_reg_reset_occurred(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0001, 0, wr_val) 1499 #define rd_multicast_mask_control() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ba, 15, 15, __ERR) 1500 #define wr_multicast_mask_control(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0ba, 0x0001, 0, wr_val) 1501 #define rd_multicast_mask_control_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0bb, 11, 15, __ERR) 1502 #define rd_osr_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0bb, 12, 12, __ERR) 1503 #define rd_osr_mode_pin() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0bc, 12, 12, __ERR) 1504 #define rd_signal_detect_filter_count() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e0, 11, 11, __ERR) 1505 #define wr_signal_detect_filter_count(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0x001f, 0, wr_val) 1506 #define rd_los_filter_count() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e0, 3, 11, __ERR) 1507 #define wr_los_filter_count(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0x1f00, 8, wr_val) 1508 #define rd_energy_detect_mask_count() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 0, 11, __ERR) 1509 #define wr_energy_detect_mask_count(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0xf800, 11, wr_val) 1510 #define rd_afe_signal_detect_dis() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 15, 15, __ERR) 1511 #define wr_afe_signal_detect_dis(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0001, 0, wr_val) 1512 #define rd_ext_los_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 14, 15, __ERR) 1513 #define wr_ext_los_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0002, 1, wr_val) 1514 #define rd_ext_los_inv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 13, 15, __ERR) 1515 #define wr_ext_los_inv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0004, 2, wr_val) 1516 #define rd_ignore_lp_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 12, 15, __ERR) 1517 #define wr_ignore_lp_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0008, 3, wr_val) 1518 #define rd_signal_detect_filter_1us() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 11, 15, __ERR) 1519 #define wr_signal_detect_filter_1us(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0010, 4, wr_val) 1520 #define rd_energy_detect_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 10, 15, __ERR) 1521 #define wr_energy_detect_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0020, 5, wr_val) 1522 #define rd_energy_detect_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 9, 15, __ERR) 1523 #define wr_energy_detect_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0040, 6, wr_val) 1524 #define rd_signal_detect_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 8, 15, __ERR) 1525 #define wr_signal_detect_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0080, 7, wr_val) 1526 #define rd_signal_detect_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e1, 7, 15, __ERR) 1527 #define wr_signal_detect_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0100, 8, wr_val) 1528 #define rd_los_thresh() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e2, 13, 13, __ERR) 1529 #define wr_los_thresh(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0007, 0, wr_val) 1530 #define rd_signal_detect_thresh() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e2, 9, 13, __ERR) 1531 #define wr_signal_detect_thresh(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0070, 4, wr_val) 1532 #define rd_hold_los_count() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e2, 5, 13, __ERR) 1533 #define wr_hold_los_count(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0700, 8, wr_val) 1534 #define rd_hold_sd_count() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e2, 2, 13, __ERR) 1535 #define wr_hold_sd_count(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x3800, 11, wr_val) 1536 #define rd_signal_detect() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 15, 15, __ERR) 1537 #define rd_signal_detect_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 14, 15, __ERR) 1538 #define rd_signal_detect_raw() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 11, 15, __ERR) 1539 #define rd_signal_detect_raw_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 10, 15, __ERR) 1540 #define rd_ext_sigdet() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 9, 15, __ERR) 1541 #define rd_ext_sigdet_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 8, 15, __ERR) 1542 #define rd_afe_sigdet() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 7, 15, __ERR) 1543 #define rd_afe_sigdet_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e8, 6, 15, __ERR) 1544 #define rd_uc_signal_detect() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e9, 15, 15, __ERR) 1545 #define rd_uc_signal_detect_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e9, 14, 15, __ERR) 1546 #define rd_uc_ext_sigdet() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e9, 9, 15, __ERR) 1547 #define rd_uc_ext_sigdet_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e9, 8, 15, __ERR) 1548 #define rd_uc_afe_sigdet() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e9, 7, 15, __ERR) 1549 #define rd_uc_afe_sigdet_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0e9, 6, 15, __ERR) 1550 #define rd_energy_detect() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ea, 15, 15, __ERR) 1551 #define rd_energy_detect_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ea, 14, 15, __ERR) 1552 #define rd_pmd_signal_detect() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0eb, 15, 15, __ERR) 1553 #define rd_afe_sigdet_thresh() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ec, 13, 13, __ERR) 1554 #define rd_prbs_chk_burst_err_cnt_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 0, 15, __ERR) 1555 #define wr_prbs_chk_burst_err_cnt_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x8000, 15, wr_val) 1556 #define rd_prbs_chk_mode_sel_msb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 3, 15, __ERR) 1557 #define wr_prbs_chk_mode_sel_msb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x1000, 12, wr_val) 1558 #define rd_prbs_chk_clk_en_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 4, 15, __ERR) 1559 #define wr_prbs_chk_clk_en_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0800, 11, wr_val) 1560 #define rd_trnsum_error_count_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 5, 15, __ERR) 1561 #define wr_trnsum_error_count_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0400, 10, wr_val) 1562 #define rd_prbs_chk_err_cnt_burst_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 6, 15, __ERR) 1563 #define wr_prbs_chk_err_cnt_burst_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0200, 9, wr_val) 1564 #define rd_prbs_burst_len_chk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 7, 15, __ERR) 1565 #define wr_prbs_burst_len_chk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0100, 8, wr_val) 1566 #define rd_prbs_chk_en_auto_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 8, 15, __ERR) 1567 #define wr_prbs_chk_en_auto_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0080, 7, wr_val) 1568 #define rd_prbs_chk_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 9, 14, __ERR) 1569 #define wr_prbs_chk_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0060, 5, wr_val) 1570 #define rd_prbs_chk_inv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 11, 15, __ERR) 1571 #define wr_prbs_chk_inv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0010, 4, wr_val) 1572 #define rd_prbs_chk_mode_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 12, 13, __ERR) 1573 #define wr_prbs_chk_mode_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x000e, 1, wr_val) 1574 #define rd_prbs_chk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd161, 15, 15, __ERR) 1575 #define wr_prbs_chk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0001, 0, wr_val) 1576 #define rd_prbs_chk_lock_cnt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd160, 11, 11, __ERR) 1577 #define wr_prbs_chk_lock_cnt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd160, 0x001f, 0, wr_val) 1578 #define rd_prbs_chk_ool_cnt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd160, 3, 11, __ERR) 1579 #define wr_prbs_chk_ool_cnt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd160, 0x1f00, 8, wr_val) 1580 #define rd_dig_lpbk_pd_bias_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd162, 12, 15, __ERR) 1581 #define wr_dig_lpbk_pd_bias_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd162, 0x0008, 3, wr_val) 1582 #define rd_dig_lpbk_pd_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd162, 14, 15, __ERR) 1583 #define wr_dig_lpbk_pd_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd162, 0x0002, 1, wr_val) 1584 #define rd_dig_lpbk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd162, 15, 15, __ERR) 1585 #define wr_dig_lpbk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd162, 0x0001, 0, wr_val) 1586 #define rd_tlb_rx_diff_dec_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd163, 12, 15, __ERR) 1587 #define wr_tlb_rx_diff_dec_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd163, 0x0008, 3, wr_val) 1588 #define rd_dbg_mask_dig_lpbk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd163, 13, 15, __ERR) 1589 #define wr_dbg_mask_dig_lpbk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd163, 0x0004, 2, wr_val) 1590 #define rd_rx_pmd_dp_invert() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd163, 15, 15, __ERR) 1591 #define wr_rx_pmd_dp_invert(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd163, 0x0001, 0, wr_val) 1592 #define rd_prbs_chk_en_timeout() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd164, 3, 11, __ERR) 1593 #define wr_prbs_chk_en_timeout(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd164, 0x1f00, 8, wr_val) 1594 #define rd_prbs_chk_en_timer_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd164, 14, 14, __ERR) 1595 #define wr_prbs_chk_en_timer_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd164, 0x0003, 0, wr_val) 1596 #define rd_dig_lpbk_pd_early_ind() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd168, 14, 15, __ERR) 1597 #define rd_dig_lpbk_pd_late_ind() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd168, 15, 15, __ERR) 1598 #define rd_prbs_chk_err_cnt_no_clr() _phy8806x_tsc_pmd_rde_field(pa, 0xd169, 0, 1, __ERR) 1599 #define rd_prbs_chk_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd169, 15, 15, __ERR) 1600 #define rd_prbs_chk_lock_lost_lh() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd16a, 0, 15, __ERR) 1601 #define rd_prbs_chk_err_cnt_msb() _phy8806x_tsc_pmd_rde_field(pa, 0xd16a, 1, 1, __ERR) 1602 #define rd_prbs_chk_err_cnt_lsb() _phy8806x_tsc_pmd_rde_reg(pa, 0xd16b, __ERR) 1603 #define rd_pmd_rx_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd16c, 15, 15, __ERR) 1604 #define rd_pmd_rx_lock_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd16c, 14, 15, __ERR) 1605 #define rd_dbg_pmd_rx_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd166, 15, 15, __ERR) 1606 #define rd_dbg_pmd_rx_lock_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd166, 14, 15, __ERR) 1607 #define rd_uc_pmd_rx_lock() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd167, 15, 15, __ERR) 1608 #define rd_uc_pmd_rx_lock_change() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd167, 14, 15, __ERR) 1609 #define rd_prbs_burst_err_length_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd16d, 10, 10, __ERR) 1610 #define rd_max_prbs_burst_err_length_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd16e, 10, 10, __ERR) 1611 #define rd_prbs_chk_burst_err_cnt() _phy8806x_tsc_pmd_rde_field(pa, 0xd165, 6, 6, __ERR) 1612 #define rd_patt_gen_start_pos() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd170, 0, 12, __ERR) 1613 #define wr_patt_gen_start_pos(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd170, 0xf000, 12, wr_val) 1614 #define rd_patt_gen_stop_pos() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd170, 4, 12, __ERR) 1615 #define wr_patt_gen_stop_pos(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd170, 0x0f00, 8, wr_val) 1616 #define rd_patt_gen_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd170, 15, 15, __ERR) 1617 #define wr_patt_gen_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd170, 0x0001, 0, wr_val) 1618 #define rd_prbs_gen_mode_sel_msb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd171, 3, 15, __ERR) 1619 #define wr_prbs_gen_mode_sel_msb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x1000, 12, wr_val) 1620 #define rd_prbs_gen_err_ins() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd171, 10, 15, __ERR) 1621 #define wr_prbs_gen_err_ins(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x0020, 5, wr_val) 1622 #define rd_prbs_gen_inv() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd171, 11, 15, __ERR) 1623 #define wr_prbs_gen_inv(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x0010, 4, wr_val) 1624 #define rd_prbs_gen_mode_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd171, 12, 13, __ERR) 1625 #define wr_prbs_gen_mode_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x000e, 1, wr_val) 1626 #define rd_prbs_gen_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd171, 15, 15, __ERR) 1627 #define wr_prbs_gen_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x0001, 0, wr_val) 1628 #define rd_rmt_lpbk_pd_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd172, 13, 15, __ERR) 1629 #define wr_rmt_lpbk_pd_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd172, 0x0004, 2, wr_val) 1630 #define rd_rmt_lpbk_pd_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd172, 14, 15, __ERR) 1631 #define wr_rmt_lpbk_pd_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd172, 0x0002, 1, wr_val) 1632 #define rd_rmt_lpbk_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd172, 15, 15, __ERR) 1633 #define wr_rmt_lpbk_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd172, 0x0001, 0, wr_val) 1634 #define rd_tlb_tx_diff_enc_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd173, 12, 15, __ERR) 1635 #define wr_tlb_tx_diff_enc_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0008, 3, wr_val) 1636 #define rd_tx_mux_sel_order() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd173, 13, 15, __ERR) 1637 #define wr_tx_mux_sel_order(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0004, 2, wr_val) 1638 #define rd_tx_pcs_native_ana_frmt_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd173, 14, 15, __ERR) 1639 #define wr_tx_pcs_native_ana_frmt_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0002, 1, wr_val) 1640 #define rd_tx_pmd_dp_invert() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd173, 15, 15, __ERR) 1641 #define wr_tx_pmd_dp_invert(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0001, 0, wr_val) 1642 #define rd_rmt_lpbk_pd_early_ind() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd178, 14, 15, __ERR) 1643 #define rd_rmt_lpbk_pd_late_ind() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd178, 15, 15, __ERR) 1644 #define rd_afe_tx_reset_deassert() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b1, 0, 15, __ERR) 1645 #define wr_afe_tx_reset_deassert(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b1, 0x8000, 15, wr_val) 1646 #define rd_ln_tx_s_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b1, 15, 15, __ERR) 1647 #define wr_ln_tx_s_pwrdn(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b1, 0x0001, 0, wr_val) 1648 #define rd_ln_tclk20_s_clkgate_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b7, 10, 15, __ERR) 1649 #define wr_ln_tclk20_s_clkgate_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b7, 0x0020, 5, wr_val) 1650 #define rd_pmd_tx_clk_vld_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b7, 11, 15, __ERR) 1651 #define wr_pmd_tx_clk_vld_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b7, 0x0010, 4, wr_val) 1652 #define rd_pmd_tx_clk_vld_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b7, 12, 15, __ERR) 1653 #define wr_pmd_tx_clk_vld_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b7, 0x0008, 3, wr_val) 1654 #define rd_ln_tx_s_comclk_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b7, 13, 15, __ERR) 1655 #define wr_ln_tx_s_comclk_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b7, 0x0004, 2, wr_val) 1656 #define rd_ln_tx_s_comclk_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b7, 14, 15, __ERR) 1657 #define wr_ln_tx_s_comclk_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b7, 0x0002, 1, wr_val) 1658 #define rd_ln_tx_s_clkgate_frc_on() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b7, 15, 15, __ERR) 1659 #define wr_ln_tx_s_clkgate_frc_on(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b7, 0x0001, 0, wr_val) 1660 #define rd_ln_tx_dp_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b4, 14, 15, __ERR) 1661 #define wr_ln_tx_dp_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b4, 0x0002, 1, wr_val) 1662 #define rd_ln_tx_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b4, 15, 15, __ERR) 1663 #define wr_ln_tx_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b4, 0x0001, 0, wr_val) 1664 #define rd_afe_tx_reset_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b2, 12, 15, __ERR) 1665 #define wr_afe_tx_reset_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b2, 0x0008, 3, wr_val) 1666 #define rd_afe_tx_reset_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b2, 13, 15, __ERR) 1667 #define wr_afe_tx_reset_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b2, 0x0004, 2, wr_val) 1668 #define rd_afe_tx_pwrdn_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b2, 14, 15, __ERR) 1669 #define wr_afe_tx_pwrdn_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b2, 0x0002, 1, wr_val) 1670 #define rd_afe_tx_pwrdn_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b2, 15, 15, __ERR) 1671 #define wr_afe_tx_pwrdn_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b2, 0x0001, 0, wr_val) 1672 #define rd_pmd_ln_tx_h_pwrdn_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1b3, 15, 15, __ERR) 1673 #define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1b3, 0x0001, 0, wr_val) 1674 #define rd_pmd_tx_lane_mode() _phy8806x_tsc_pmd_rde_reg(pa, 0xd1b8, __ERR) 1675 #define rd_afe_tx_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1bc, 14, 15, __ERR) 1676 #define rd_afe_tx_pwrdn() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1bc, 15, 15, __ERR) 1677 #define rd_tx_pi_loop_filter_stable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1bd, 15, 15, __ERR) 1678 #define wr_tx_pi_loop_filter_stable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1bd, 0x0001, 0, wr_val) 1679 #define rd_txfir_post_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd130, 4, 12, __ERR) 1680 #define wr_txfir_post_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x0f00, 8, wr_val) 1681 #define rd_txfir_main_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd130, 8, 12, __ERR) 1682 #define wr_txfir_main_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x00f0, 4, wr_val) 1683 #define rd_txfir_pre_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd130, 12, 12, __ERR) 1684 #define wr_txfir_pre_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x000f, 0, wr_val) 1685 #define rd_txfir_post3_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd131, 8, 12, __ERR) 1686 #define wr_txfir_post3_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd131, 0x00f0, 4, wr_val) 1687 #define rd_txfir_post2_offset() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd131, 12, 12, __ERR) 1688 #define wr_txfir_post2_offset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd131, 0x000f, 0, wr_val) 1689 #define rd_txfir_post3() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd132, 4, 12, __ERR) 1690 #define wr_txfir_post3(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd132, 0x0f00, 8, wr_val) 1691 #define rd_txfir_post2() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd132, 11, 11, __ERR) 1692 #define wr_txfir_post2(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd132, 0x001f, 0, wr_val) 1693 #define rd_txfir_post_after_ovr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd133, 2, 10, __ERR) 1694 #define rd_txfir_pre_after_ovr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd133, 11, 11, __ERR) 1695 #define rd_txfir_main_after_ovr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd134, 9, 9, __ERR) 1696 #define rd_txfir_post_adjusted() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd135, 2, 10, __ERR) 1697 #define rd_txfir_pre_adjusted() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd135, 11, 11, __ERR) 1698 #define rd_txfir_post2_adjusted() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd136, 3, 11, __ERR) 1699 #define rd_txfir_main_adjusted() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd136, 9, 9, __ERR) 1700 #define rd_txfir_post3_adjusted() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd137, 12, 12, __ERR) 1701 #define rd_tx_eee_alert_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 0, 15, __ERR) 1702 #define wr_tx_eee_alert_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x8000, 15, wr_val) 1703 #define rd_tx_eee_quiet_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 1, 15, __ERR) 1704 #define wr_tx_eee_quiet_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x4000, 14, wr_val) 1705 #define rd_tx_disable_timer_ctrl() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 6, 10, __ERR) 1706 #define wr_tx_disable_timer_ctrl(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x03f0, 4, wr_val) 1707 #define rd_pmd_tx_disable_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 12, 15, __ERR) 1708 #define wr_pmd_tx_disable_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x0008, 3, wr_val) 1709 #define rd_dp_reset_tx_disable_dis() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 13, 15, __ERR) 1710 #define wr_dp_reset_tx_disable_dis(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x0004, 2, wr_val) 1711 #define rd_tx_disable_trigger() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 14, 15, __ERR) 1712 #define wr_tx_disable_trigger(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x0002, 1, wr_val) 1713 #define rd_micro_tx_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13a, 15, 15, __ERR) 1714 #define wr_micro_tx_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13a, 0x0001, 0, wr_val) 1715 #define rd_tx_disable_output_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13b, 12, 14, __ERR) 1716 #define wr_tx_disable_output_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13b, 0x000c, 2, wr_val) 1717 #define rd_sdk_tx_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13b, 15, 15, __ERR) 1718 #define wr_sdk_tx_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd13b, 0x0001, 0, wr_val) 1719 #define rd_tx_elec_idle_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13c, 14, 15, __ERR) 1720 #define rd_tx_disable_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd13c, 15, 15, __ERR) 1721 #define rd_tx_pi_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 15, 15, __ERR) 1722 #define wr_tx_pi_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0001, 0, wr_val) 1723 #define rd_tx_pi_jitter_filter_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 14, 15, __ERR) 1724 #define wr_tx_pi_jitter_filter_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0002, 1, wr_val) 1725 #define rd_tx_pi_ext_ctrl_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 13, 15, __ERR) 1726 #define wr_tx_pi_ext_ctrl_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0004, 2, wr_val) 1727 #define rd_tx_pi_freq_override_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 12, 15, __ERR) 1728 #define wr_tx_pi_freq_override_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0008, 3, wr_val) 1729 #define rd_tx_pi_sj_gen_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 11, 15, __ERR) 1730 #define wr_tx_pi_sj_gen_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0010, 4, wr_val) 1731 #define rd_tx_pi_ssc_gen_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 10, 15, __ERR) 1732 #define wr_tx_pi_ssc_gen_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0020, 5, wr_val) 1733 #define rd_tx_pi_jit_ssc_freq_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 9, 15, __ERR) 1734 #define wr_tx_pi_jit_ssc_freq_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0040, 6, wr_val) 1735 #define rd_tx_pi_second_order_loop_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 8, 15, __ERR) 1736 #define wr_tx_pi_second_order_loop_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0080, 7, wr_val) 1737 #define rd_tx_pi_first_order_bwsel_integ() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 6, 14, __ERR) 1738 #define wr_tx_pi_first_order_bwsel_integ(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0300, 8, wr_val) 1739 #define rd_tx_pi_second_order_bwsel_integ() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 4, 14, __ERR) 1740 #define wr_tx_pi_second_order_bwsel_integ(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0c00, 10, wr_val) 1741 #define rd_tx_pi_ext_phase_bwsel_integ() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a0, 1, 13, __ERR) 1742 #define wr_tx_pi_ext_phase_bwsel_integ(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x7000, 12, wr_val) 1743 #define rd_tx_pi_freq_override_val() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd0a1, 1, 1, __ERR) 1744 #define wr_tx_pi_freq_override_val(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd0a1, 0x7fff, 0, wr_val) 1745 #define rd_tx_pi_jit_freq_idx() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a2, 10, 10, __ERR) 1746 #define wr_tx_pi_jit_freq_idx(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x003f, 0, wr_val) 1747 #define rd_tx_pi_jit_amp() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a2, 2, 10, __ERR) 1748 #define wr_tx_pi_jit_amp(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x3f00, 8, wr_val) 1749 #define rd_tx_pi_phase_override() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a3, 15, 15, __ERR) 1750 #define wr_tx_pi_phase_override(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0001, 0, wr_val) 1751 #define rd_tx_pi_phase_strobe() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a3, 14, 15, __ERR) 1752 #define wr_tx_pi_phase_strobe(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0002, 1, wr_val) 1753 #define rd_tx_pi_phase_step_dir() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a3, 13, 15, __ERR) 1754 #define wr_tx_pi_phase_step_dir(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0004, 2, wr_val) 1755 #define rd_tx_pi_phase_invert() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a3, 11, 15, __ERR) 1756 #define wr_tx_pi_phase_invert(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0010, 4, wr_val) 1757 #define rd_tx_pi_phase_step_num() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a3, 4, 12, __ERR) 1758 #define wr_tx_pi_phase_step_num(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0f00, 8, wr_val) 1759 #define rd_tx_pi_frz_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a4, 15, 15, __ERR) 1760 #define wr_tx_pi_frz_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0001, 0, wr_val) 1761 #define rd_tx_pi_frz_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a4, 14, 15, __ERR) 1762 #define wr_tx_pi_frz_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0002, 1, wr_val) 1763 #define rd_tx_pi_frz_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a4, 13, 15, __ERR) 1764 #define wr_tx_pi_frz_mode(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0004, 2, wr_val) 1765 #define rd_tx_pi_reset_code_dbg() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a4, 12, 15, __ERR) 1766 #define wr_tx_pi_reset_code_dbg(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0008, 3, wr_val) 1767 #define rd_tx_pi_hs_fifo_phserr_invert() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 14, 15, __ERR) 1768 #define wr_tx_pi_hs_fifo_phserr_invert(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0002, 1, wr_val) 1769 #define rd_tx_pi_repeater_mode_en() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 13, 15, __ERR) 1770 #define wr_tx_pi_repeater_mode_en(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0004, 2, wr_val) 1771 #define rd_tx_pi_ext_pd_sel() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 12, 15, __ERR) 1772 #define wr_tx_pi_ext_pd_sel(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0008, 3, wr_val) 1773 #define rd_afe_tx_fifo_resetb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 7, 15, __ERR) 1774 #define wr_afe_tx_fifo_resetb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0100, 8, wr_val) 1775 #define rd_afe_tx_fifo_resetb_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 6, 15, __ERR) 1776 #define wr_afe_tx_fifo_resetb_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0200, 9, wr_val) 1777 #define rd_tx_pi_pd_bypass_flt() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 5, 15, __ERR) 1778 #define wr_tx_pi_pd_bypass_flt(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0400, 10, wr_val) 1779 #define rd_tx_pi_pd_bypass_vco() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0a5, 4, 15, __ERR) 1780 #define wr_tx_pi_pd_bypass_vco(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd0a5, 0x0800, 11, wr_val) 1781 #define rd_tx_pi_phase_cntr() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd0a8, 9, 9, __ERR) 1782 #define rd_tx_pi_integ1_reg() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd0a9, 2, 2, __ERR) 1783 #define rd_tx_pi_integ2_reg() _phy8806x_tsc_pmd_rde_field_signed(pa, 0xd0aa, 1, 1, __ERR) 1784 #define rd_tx_pi_phase_err() _phy8806x_tsc_pmd_rde_field_signed_byte(pa, 0xd0ab, 10, 10, __ERR) 1785 #define rd_st_afe_tx_fifo_resetb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ac, 14, 15, __ERR) 1786 #define rd_tx_pi_hs_fifo_phserr() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ac, 15, 15, __ERR) 1787 #define rd_tx_fifo_ovfb_fall_edge_lh() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ad, 14, 15, __ERR) 1788 #define rd_tx_fifo_ovfb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd0ad, 15, 15, __ERR) 1789 #define rd_tx_osr_mode_frc() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d0, 0, 15, __ERR) 1790 #define wr_tx_osr_mode_frc(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d0, 0x8000, 15, wr_val) 1791 #define rd_tx_osr_mode_frc_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d0, 12, 12, __ERR) 1792 #define wr_tx_osr_mode_frc_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d0, 0x000f, 0, wr_val) 1793 #define rd_tx_ln_dp_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d1, 15, 15, __ERR) 1794 #define wr_tx_ln_dp_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d1, 0x0001, 0, wr_val) 1795 #define rd_tx_pll_select() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d7, 15, 15, __ERR) 1796 #define wr_tx_pll_select(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d7, 0x0001, 0, wr_val) 1797 #define rd_tx_hw_fw_handshake_disable() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1de, 14, 15, __ERR) 1798 #define wr_tx_hw_fw_handshake_disable(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1de, 0x0002, 1, wr_val) 1799 #define rd_tx_ln_s_rstb() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1de, 15, 15, __ERR) 1800 #define wr_tx_ln_s_rstb(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1de, 0x0001, 0, wr_val) 1801 #define rd_pmd_ln_tx_dp_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d3, 14, 15, __ERR) 1802 #define wr_pmd_ln_tx_dp_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d3, 0x0002, 1, wr_val) 1803 #define rd_pmd_ln_tx_h_rstb_pkill() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d3, 15, 15, __ERR) 1804 #define wr_pmd_ln_tx_h_rstb_pkill(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d3, 0x0001, 0, wr_val) 1805 #define rd_tx_uc_ack_lane_dp_reset() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d5, 14, 15, __ERR) 1806 #define wr_tx_uc_ack_lane_dp_reset(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d5, 0x0002, 1, wr_val) 1807 #define rd_tx_uc_ack_lane_cfg_done() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d5, 15, 15, __ERR) 1808 #define wr_tx_uc_ack_lane_cfg_done(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d5, 0x0001, 0, wr_val) 1809 #define rd_tx_lane_dp_reset_state() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d9, 13, 13, __ERR) 1810 #define rd_tx_lane_reg_reset_occurred() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1d6, 15, 15, __ERR) 1811 #define wr_tx_lane_reg_reset_occurred(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1d6, 0x0001, 0, wr_val) 1812 #define rd_tx_multicast_mask_control() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1da, 15, 15, __ERR) 1813 #define wr_tx_multicast_mask_control(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd1da, 0x0001, 0, wr_val) 1814 #define rd_tx_multicast_mask_control_status() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1db, 11, 15, __ERR) 1815 #define rd_tx_osr_mode() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1db, 12, 12, __ERR) 1816 #define rd_tx_osr_mode_pin() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd1dc, 12, 12, __ERR) 1817 #define rdc_txcom_pre_tap_alert_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd150, 3, 11, __ERR) 1818 #define wrc_txcom_pre_tap_alert_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd150, 0x1f00, 8, wr_val) 1819 #define rdc_txcom_post_tap_alert_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd150, 10, 10, __ERR) 1820 #define wrc_txcom_post_tap_alert_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd150, 0x003f, 0, wr_val) 1821 #define rdc_txcom_main_tap_alert_val() _phy8806x_tsc_pmd_rde_field_byte(pa, 0xd151, 9, 9, __ERR) 1822 #define wrc_txcom_main_tap_alert_val(wr_val) _phy8806x_tsc_pmd_mwr_reg_byte(pa, 0xd151, 0x007f, 0, wr_val) 1823 #define rdc_txcom_cl93n72_max_wait_timer_period() _phy8806x_tsc_pmd_rde_reg(pa, 0xd152, __ERR) 1824 #define wrc_txcom_cl93n72_max_wait_timer_period(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd152, wr_val) 1825 #define rdc_txcom_cl93n72_wait_cntr_limit() _phy8806x_tsc_pmd_rde_field(pa, 0xd153, 6, 6, __ERR) 1826 #define wrc_txcom_cl93n72_wait_cntr_limit(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd153, 0x03ff, 0, wr_val) 1827 #define rdc_txcom_cl93n72_max_wait_timer_period_2ndset() _phy8806x_tsc_pmd_rde_reg(pa, 0xd154, __ERR) 1828 #define wrc_txcom_cl93n72_max_wait_timer_period_2ndset(wr_val) phy8806x_tsc_pmd_wr_reg(pa, 0xd154, wr_val) 1829 #define rdc_txcom_cl93n72_wait_cntr_limit_2ndset() _phy8806x_tsc_pmd_rde_field(pa, 0xd155, 6, 6, __ERR) 1830 #define wrc_txcom_cl93n72_wait_cntr_limit_2ndset(wr_val) phy8806x_tsc_pmd_mwr_reg(pa, 0xd155, 0x03ff, 0, wr_val) 1831 1832 #endif