phy8806x_cfg_seq.c (22375B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 8 /* 9 * 10 * 11 * 12 * This program is the proprietary software of Broadcom Corporation 13 * and/or its licensors, and may only be used, duplicated, modified 14 * or distributed pursuant to the terms and conditions of a separate, 15 * written license agreement executed between you and Broadcom 16 * (an "Authorized License"). Except as set forth in an Authorized 17 * License, Broadcom grants no license (express or implied), right 18 * to use, or waiver of any kind with respect to the Software, and 19 * Broadcom expressly reserves all rights in and to the Software 20 * and all intellectual property rights therein. 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THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING 51 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$ 52 */ 53 54 55 #include <phymod/phymod.h> 56 #include "phy8806x_cfg_seq.h" 57 #include "phy8806x_tsc_fields.h" 58 #include "phy8806x_tsc_field_access.h" 59 #include <phymod/chip/bcmi_tscf_xgxs_defs.h> 60 #include "phy8806x_tsc_dependencies.h" 61 #include "phy8806x_tsc_interface.h" 62 63 64 err_code_t phy8806x_tx_rx_polarity_set(const phymod_access_t *pa, uint32_t tx_pol, uint32_t rx_pol) 65 { 66 err_code_t __err; 67 __err=ERR_CODE_NONE; 68 __err = (uint32_t) wr_tx_pmd_dp_invert(tx_pol); 69 if(__err) return(__err); 70 __err = (uint32_t) wr_rx_pmd_dp_invert(rx_pol); 71 if(__err) return(__err); 72 73 return ERR_CODE_NONE; 74 } 75 76 err_code_t phy8806x_tx_rx_polarity_get(const phymod_access_t *pa, uint32_t *tx_pol, uint32_t *rx_pol) 77 { 78 err_code_t __err; 79 __err=ERR_CODE_NONE; 80 *tx_pol = (uint32_t) rd_tx_pmd_dp_invert(); 81 if(__err) return(__err); 82 *rx_pol = (uint32_t) rd_rx_pmd_dp_invert(); 83 if(__err) return(__err); 84 85 return ERR_CODE_NONE; 86 } 87 88 err_code_t phy8806x_uc_active_set(const phymod_access_t *pa, uint32_t enable) 89 { 90 err_code_t __err; 91 __err=ERR_CODE_NONE; 92 __err=wrc_uc_active(enable); 93 if(__err) return(__err); 94 95 return ERR_CODE_NONE; 96 } 97 98 err_code_t phy8806x_uc_active_get(const phymod_access_t *pa, uint32_t *enable) 99 { 100 err_code_t __err; 101 __err=ERR_CODE_NONE; 102 *enable = (uint32_t) rdc_uc_active(); 103 if(__err) return(__err); 104 return ERR_CODE_NONE; 105 } 106 107 108 /* 109 err_code_t phy8806x_uc_reset(const phymod_access_t *pa, uint32_t enable) 110 { 111 return ERR_CODE_NONE; 112 } 113 */ 114 115 err_code_t phy8806x_force_tx_set_rst (const phymod_access_t *pa, uint32_t rst) 116 { 117 /* coverity[check_return] */ 118 wr_afe_tx_reset_frc_val(rst); 119 /* 120 * COVERITY 121 * 122 * The called function already checks return value by wr_afe_tx_reset_frc. 123 */ 124 /* coverity[check_return] */ 125 wr_afe_tx_reset_frc(0x1); 126 return ERR_CODE_NONE; 127 } 128 129 err_code_t phy8806x_force_tx_get_rst (const phymod_access_t *pa, uint32_t *rst) 130 { 131 err_code_t __err; 132 __err=ERR_CODE_NONE; 133 *rst=(uint32_t) rd_afe_tx_reset_frc_val(); 134 return ERR_CODE_NONE; 135 } 136 137 err_code_t phy8806x_force_rx_set_rst (const phymod_access_t *pa, uint32_t rst) 138 { 139 /* coverity[check_return] */ 140 wr_afe_rx_reset_frc_val(rst); 141 /* 142 * COVERITY 143 * 144 * The called function already checks return value by wr_afe_rx_reset_frc. 145 */ 146 /* coverity[check_return] */ 147 wr_afe_rx_reset_frc(0x1); 148 return ERR_CODE_NONE; 149 } 150 151 err_code_t phy8806x_force_rx_get_rst (const phymod_access_t *pa, uint32_t *rst) 152 { 153 err_code_t __err; 154 __err=ERR_CODE_NONE; 155 *rst=(uint32_t) rd_afe_rx_reset_frc_val(); 156 return ERR_CODE_NONE; 157 } 158 159 err_code_t phy8806x_prbs_tx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data) 160 { 161 err_code_t __err; 162 __err=ERR_CODE_NONE; 163 *inv_data = (uint32_t) rd_prbs_gen_inv(); 164 if(__err) return(__err); 165 166 return ERR_CODE_NONE; 167 } 168 169 err_code_t phy8806x_prbs_rx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data) 170 { 171 err_code_t __err; 172 __err=ERR_CODE_NONE; 173 *inv_data = (uint32_t) rd_prbs_gen_inv(); 174 if(__err) return(__err); 175 176 return ERR_CODE_NONE; 177 } 178 179 err_code_t phy8806x_prbs_tx_poly_get(const phymod_access_t *pa, phy8806x_prbs_polynomial_type_t *prbs_poly) 180 { 181 err_code_t __err; 182 __err=ERR_CODE_NONE; 183 *prbs_poly = rd_prbs_gen_mode_sel(); 184 if(__err) return(__err); 185 186 return ERR_CODE_NONE; 187 } 188 189 err_code_t phy8806x_prbs_rx_poly_get(const phymod_access_t *pa, phy8806x_prbs_polynomial_type_t *prbs_poly) 190 { 191 err_code_t __err; 192 __err=ERR_CODE_NONE; 193 *prbs_poly = rd_prbs_gen_mode_sel(); 194 if(__err) return(__err); 195 196 return ERR_CODE_NONE; 197 } 198 199 err_code_t phy8806x_prbs_tx_enable_get(const phymod_access_t *pa, uint32_t *enable) 200 { 201 err_code_t __err; 202 uint8_t val = 0; 203 204 __err=ERR_CODE_NONE; 205 __err = phy8806x_tsc_get_tx_prbs_en(pa, &val); 206 if(__err) return(__err); 207 *enable = val; 208 209 return ERR_CODE_NONE; 210 } 211 212 err_code_t phy8806x_prbs_rx_enable_get(const phymod_access_t *pa, uint32_t *enable) 213 { 214 err_code_t __err; 215 uint8_t val = 0; 216 217 __err=ERR_CODE_NONE; 218 __err = phy8806x_tsc_get_rx_prbs_en(pa, &val); 219 if(__err) return(__err); 220 *enable = val; 221 222 return ERR_CODE_NONE; 223 } 224 225 err_code_t phy8806x_pmd_force_signal_detect(const phymod_access_t *pa, uint32_t enable) 226 { 227 err_code_t __err; 228 __err=ERR_CODE_NONE; 229 __err = wr_signal_detect_frc(enable); if(__err) return(__err); 230 __err = wr_signal_detect_frc_val(enable); if(__err) return(__err); 231 232 return ERR_CODE_NONE; 233 } 234 235 err_code_t phy8806x_pll_mode_set(const phymod_access_t *pa, int pll_mode) 236 { 237 err_code_t __err; 238 __err=ERR_CODE_NONE; 239 __err=wrc_pll_mode(pll_mode); 240 if(__err) return(__err); 241 242 return ERR_CODE_NONE; 243 } 244 245 err_code_t phy8806x_pll_mode_get(const phymod_access_t *pa, uint32_t *pll_mode) 246 { 247 err_code_t __err; 248 __err=ERR_CODE_NONE; 249 *pll_mode=rdc_pll_mode(); 250 if(__err) return(__err); 251 252 return ERR_CODE_NONE; 253 } 254 255 err_code_t phy8806x_osr_mode_set(const phymod_access_t *pa, int osr_mode) 256 { 257 err_code_t __err; 258 __err=ERR_CODE_NONE; 259 __err=wr_osr_mode_frc_val(osr_mode); 260 if(__err) return(__err); 261 __err=wr_osr_mode_frc(1); 262 if(__err) return(__err); 263 264 return ERR_CODE_NONE; 265 } 266 267 err_code_t phy8806x_osr_mode_get(const phymod_access_t *pa, int *osr_mode) 268 { 269 int osr_forced; 270 err_code_t __err; 271 __err=ERR_CODE_NONE; 272 osr_forced = rd_osr_mode_frc(); 273 if(osr_forced) { 274 *osr_mode = rd_osr_mode_frc_val(); 275 if(__err) return(__err); 276 } else { 277 *osr_mode = rd_osr_mode_pin(); 278 if(__err) return(__err); 279 } 280 281 return ERR_CODE_NONE; 282 } 283 284 err_code_t phy8806x_tsc_dig_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk) 285 { 286 err_code_t __err; 287 __err=ERR_CODE_NONE; 288 *lpbk=rd_dig_lpbk_en(); 289 if(__err) return(__err); 290 291 return ERR_CODE_NONE; 292 } 293 294 err_code_t phy8806x_tsc_rmt_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk) 295 { 296 err_code_t __err; 297 __err=ERR_CODE_NONE; 298 *lpbk=rd_rmt_lpbk_en(); 299 if(__err) return(__err); 300 301 return ERR_CODE_NONE; 302 } 303 304 err_code_t phy8806x_core_soft_reset(const phymod_access_t *pa) 305 { 306 err_code_t __err; 307 __err=ERR_CODE_NONE; 308 __err=wrc_core_dp_s_rstb(1); 309 if(__err) return(__err); 310 311 return ERR_CODE_NONE; 312 } 313 314 err_code_t phy8806x_core_soft_reset_release(const phymod_access_t *pa, uint32_t enable) 315 { 316 err_code_t __err; 317 __err=ERR_CODE_NONE; 318 __err=wrc_core_dp_s_rstb(enable); 319 if(__err) return(__err); 320 321 return ERR_CODE_NONE; 322 } 323 324 err_code_t phy8806x_core_soft_reset_read(const phymod_access_t *pa, uint32_t *enable) 325 { 326 err_code_t __err; 327 __err=ERR_CODE_NONE; 328 *enable = rdc_core_dp_s_rstb(); if(__err) return(__err); 329 330 return ERR_CODE_NONE; 331 } 332 333 err_code_t phy8806x_lane_soft_reset_read(const phymod_access_t *pa, uint32_t *enable) 334 { 335 err_code_t __err; 336 __err=ERR_CODE_NONE; 337 *enable = rd_ln_dp_s_rstb(); if(__err) return(__err); 338 339 return ERR_CODE_NONE; 340 } 341 342 /* set powerdown for tx or rx */ 343 /* tx_rx == 1 => disable (enable) power for Tx */ 344 /* tx_rx != 0 => disable (enable) power for Rx */ 345 /* pwrdn == 0 => enable power */ 346 /* pwrdn == 1 => disable power */ 347 err_code_t phy8806x_tsc_pwrdn_set(const phymod_access_t *pa, int tx_rx, int pwrdn) 348 { 349 err_code_t __err; 350 __err=ERR_CODE_NONE; 351 if(tx_rx) { 352 __err = (uint32_t) wr_ln_tx_s_pwrdn(pwrdn); 353 } else { 354 __err = (uint32_t) wr_ln_rx_s_pwrdn(pwrdn); 355 } 356 if(__err) return(__err); 357 358 return ERR_CODE_NONE; 359 } 360 361 err_code_t phy8806x_tsc_pwrdn_get(const phymod_access_t *pa, power_status_t *pwrdn) 362 { 363 err_code_t __err; 364 __err=ERR_CODE_NONE; 365 pwrdn->pll_pwrdn = 0; 366 pwrdn->tx_s_pwrdn = 0; 367 pwrdn->rx_s_pwrdn = 0; 368 pwrdn->pll_pwrdn = rdc_afe_s_pll_pwrdn(); if(__err) return(__err); 369 pwrdn->tx_s_pwrdn = rd_ln_tx_s_pwrdn(); if(__err) return(__err); 370 pwrdn->rx_s_pwrdn = rd_ln_rx_s_pwrdn(); if(__err) return(__err); 371 372 return ERR_CODE_NONE; 373 } 374 375 err_code_t phy8806x_pmd_loopback_get(const phymod_access_t *pa, uint32_t *enable) 376 { 377 err_code_t __err; 378 __err=ERR_CODE_NONE; 379 *enable = rd_dig_lpbk_en(); if(__err) return(__err); 380 return ERR_CODE_NONE; 381 } 382 383 err_code_t phy8806x_pmd_cl72_enable_get(const phymod_access_t *pa, uint32_t *enable) 384 { 385 err_code_t __err; 386 __err=ERR_CODE_NONE; 387 *enable = rd_cl93n72_ieee_training_enable(); if(__err) return(__err); 388 return ERR_CODE_NONE; 389 } 390 391 err_code_t phy8806x_pmd_cl72_receiver_status(const phymod_access_t *pa, uint32_t *status) 392 { 393 err_code_t __err; 394 __err=ERR_CODE_NONE; 395 *status = rd_cl93n72_ieee_receiver_status(); if(__err) return(__err); 396 return ERR_CODE_NONE; 397 } 398 399 err_code_t phy8806x_pram_firmware_enable(const phymod_access_t *pa, int enable, int wait) /* release the pmd core soft reset */ 400 { 401 err_code_t __err; 402 403 __err=ERR_CODE_NONE; 404 if(enable == 1) { 405 __err=wrc_micro_pramif_ahb_wraddr_msw(0); if(__err) return(__err); 406 __err=wrc_micro_pramif_ahb_wraddr_lsw(0); if(__err) return(__err); 407 408 __err=wrc_micro_pram_if_rstb(1); if(__err) return(__err); 409 __err=wrc_micro_pramif_en(1); if(__err) return(__err); 410 411 if(wait) { 412 /* 413 * COVERITY 414 * 415 * Delay doesn't check return value. 416 */ 417 /* coverity[check_return] */ 418 phy8806x_tsc_delay_us(500); 419 } 420 } else { 421 __err=wrc_micro_pramif_en(0); if(__err) return(__err); 422 __err=wrc_micro_core_clk_en(1); if(__err) return(__err); 423 424 } 425 return ERR_CODE_NONE; 426 } 427 428 429 err_code_t phy8806x_tsc_identify(const phymod_access_t *pa, phy8806x_rev_id0_t *rev_id0, phy8806x_rev_id1_t *rev_id1) 430 { 431 err_code_t __err; 432 433 rev_id0->revid_rev_letter =0; 434 rev_id0->revid_rev_number =0; 435 rev_id0->revid_bonding =0; 436 rev_id0->revid_process =0; 437 rev_id0->revid_model =0; 438 439 rev_id1->revid_multiplicity =0; 440 rev_id1->revid_mdio =0; 441 rev_id1->revid_micro =0; 442 rev_id1->revid_cl72 =0; 443 rev_id1->revid_pir =0; 444 rev_id1->revid_llp =0; 445 rev_id1->revid_eee =0; 446 447 __err=ERR_CODE_NONE; 448 449 rev_id0->revid_rev_letter =rdc_revid_rev_letter(); if(__err) return(__err); 450 rev_id0->revid_rev_number =rdc_revid_rev_number(); if(__err) return(__err); 451 rev_id0->revid_bonding =rdc_revid_bonding(); if(__err) return(__err); 452 rev_id0->revid_process =rdc_revid_process(); if(__err) return(__err); 453 rev_id0->revid_model =rdc_revid_model(); if(__err) return(__err); 454 455 rev_id1->revid_multiplicity =rdc_revid_multiplicity(); if(__err) return(__err); 456 rev_id1->revid_mdio =rdc_revid_mdio(); if(__err) return(__err); 457 rev_id1->revid_micro =rdc_revid_micro(); if(__err) return(__err); 458 rev_id1->revid_cl72 =rdc_revid_cl72(); if(__err) return(__err); 459 rev_id1->revid_pir =rdc_revid_pir(); if(__err) return(__err); 460 rev_id1->revid_llp =rdc_revid_llp(); if(__err) return(__err); 461 rev_id1->revid_eee =rdc_revid_eee(); if(__err) return(__err); 462 463 return ERR_CODE_NONE; 464 } 465 466 err_code_t phy8806x_pmd_ln_h_rstb_pkill_override( const phymod_access_t *pa, uint16_t val) 467 { 468 err_code_t __err; 469 /* 470 * Work around per Magesh/Justin 471 * override input from PCS to allow uc_dsc_ready_for_cmd 472 * reg get written by UC 473 */ 474 __err=ERR_CODE_NONE; 475 __err=wr_pmd_ln_h_rstb_pkill(val); if(__err) return(__err); 476 return ERR_CODE_NONE; 477 } 478 479 err_code_t phy8806x_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 480 { 481 err_code_t __err; 482 __err=ERR_CODE_NONE; 483 __err=wr_ln_dp_s_rstb(enable); if(__err) return(__err); 484 485 return ERR_CODE_NONE; 486 } 487 488 err_code_t phy8806x_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable) /* release the pmd core soft reset */ 489 { 490 err_code_t __err; 491 __err=ERR_CODE_NONE; 492 493 *enable=rd_ln_dp_s_rstb(); if(__err) return(__err); 494 495 return ERR_CODE_NONE; 496 } 497 498 499 err_code_t phy8806x_lane_hard_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 500 { 501 err_code_t __err; 502 __err=ERR_CODE_NONE; 503 __err=wr_ln_s_rstb(enable); if(__err) return(__err); 504 505 return ERR_CODE_NONE; 506 } 507 508 err_code_t phy8806x_clause72_control(const phymod_access_t *pa, uint32_t cl_72_en) /* CLAUSE_72_CONTROL */ 509 { 510 err_code_t __err; 511 uint32_t enable; 512 513 __err=ERR_CODE_NONE; 514 515 if (cl_72_en) { 516 __err=wr_cl93n72_ieee_training_enable(1); if(__err) return(__err); 517 518 } else { 519 520 __err=wr_cl93n72_ieee_training_enable(0); if(__err) return(__err); 521 } 522 523 enable=rd_ln_dp_s_rstb(); if(__err) return(__err); 524 if (enable) 525 { 526 __err=wr_ln_dp_s_rstb(0); if(__err) return(__err); 527 __err=wr_ln_dp_s_rstb(1); if(__err) return(__err); 528 } 529 return ERR_CODE_NONE; 530 } 531 532 err_code_t phy8806x_clause72_control_get(const phymod_access_t *pa, uint32_t *cl_72_en) /* CLAUSE_72_CONTROL */ 533 { 534 err_code_t __err; 535 __err=ERR_CODE_NONE; 536 *cl_72_en = rd_cl93n72_ieee_training_enable(); if(__err) return(__err); 537 538 return ERR_CODE_NONE; 539 } 540 541 err_code_t phy8806x_electrical_idle_set(const phymod_access_t *pa, uint32_t en) 542 { 543 err_code_t __err; 544 __err=ERR_CODE_NONE; 545 546 __err = wr_ams_tx_elec_idle_aux(en); if(__err) return(__err); 547 548 return ERR_CODE_NONE; 549 } 550 551 552 /***********************************************/ 553 /* Microcode Init into Program RAM Functions */ 554 /***********************************************/ 555 556 /* uCode Load through Register (MDIO) Interface [Return Val = Error_Code (0 = PASS)] */ 557 err_code_t phy8806x_tsc_ucode_init( const phymod_access_t *pa ) { 558 559 err_code_t __err; 560 uint8_t result; 561 __err=ERR_CODE_NONE; 562 /* coverity[check_return] */ 563 wrc_micro_master_clk_en(0x1); /* Enable clock to microcontroller subsystem */ 564 /* coverity[check_return] */ 565 wrc_micro_master_rstb(0x1); /* De-assert reset to microcontroller sybsystem */ 566 /* coverity[check_return] */ 567 wrc_micro_master_rstb(0x0); /* Assert reset to microcontroller sybsystem - Toggling reset*/ 568 /* coverity[check_return] */ 569 wrc_micro_master_rstb(0x1); /* De-assert reset to microcontroller sybsystem */ 570 571 /* coverity[check_return] */ 572 wrc_micro_ra_init(0x1); /* Set initialization command to initialize code RAM */ 573 /* 574 * COVERITY 575 * 576 * Delay doesn't check return value. 577 */ 578 /* coverity[check_return] */ 579 phy8806x_tsc_delay_us(1000); 580 581 result = rdc_micro_ra_initdone(); /* Poll for micro_ra_initdone = 1 to indicate initialization done */ 582 if (!result) { /* Check if initialization done within 500us time interval */ 583 PHYMOD_DEBUG_ERROR(("ERR_CODE_MICRO_INIT_NOT_DONE\n")); 584 return (ERR_CODE_MICRO_INIT_NOT_DONE); /* Else issue error code */ 585 } 586 587 /* 588 * COVERITY 589 * 590 * The called function already checks return value by wrc_micro_ra_init. 591 */ 592 /* coverity[check_return] */ 593 wrc_micro_ra_init(0x0); 594 595 return (ERR_CODE_NONE); 596 } 597 598 /** 599 @brief Init the PMD 600 @param pmd_touched If the PMD is already initialized 601 @returns The value ERR_CODE_NONE upon successful completion 602 @details Per core PMD resets (both datapath and entire core) 603 We only intend to use this function if the PMD has never been initialized. 604 */ 605 err_code_t phy8806x_pmd_reset_seq(const phymod_access_t *pa, int pmd_touched) 606 { 607 if (pmd_touched == 0) { 608 /* coverity[check_return] */ 609 wrc_core_s_rstb(1); 610 /* 611 * COVERITY 612 * 613 * The called function already checks return value by wrc_core_dp_s_rstb. 614 */ 615 /* coverity[check_return] */ 616 wrc_core_dp_s_rstb(1); 617 } 618 return (ERR_CODE_NONE); 619 } 620 621 622 /** 623 @brief Enable the pll reset bit 624 @param enable Controls whether to reset PLL 625 @returns The value ERR_CODE_NONE upon successful completion 626 @details 627 Resets the PLL 628 */ 629 err_code_t phy8806x_pll_reset_enable_set (const phymod_access_t *pa, int enable) 630 { 631 /* coverity[check_return] */ 632 wrc_afe_s_pll_reset_frc_val(enable); 633 /* 634 * COVERITY 635 * 636 * The called function already checks return value by wrc_afe_s_pll_reset_frc. 637 */ 638 /* coverity[check_return] */ 639 wrc_afe_s_pll_reset_frc(1); 640 return (ERR_CODE_NONE); 641 } 642 643 /** 644 @brief Read PLL range 645 */ 646 err_code_t phy8806x_tsc_read_pll_range (const phymod_access_t *pa, uint32_t *pll_range) 647 { 648 err_code_t __err; 649 __err=ERR_CODE_NONE; 650 *pll_range = rdc_ams_pll_range(); 651 return (ERR_CODE_NONE); 652 } 653 654 655 /** 656 @brief Reag signal detect 657 */ 658 err_code_t phy8806x_tsc_signal_detect (const phymod_access_t *pa, uint32_t *signal_detect) 659 { 660 err_code_t __err; 661 __err=ERR_CODE_NONE; 662 *signal_detect = rd_signal_detect(); 663 return (ERR_CODE_NONE); 664 } 665 666 667 err_code_t phy8806x_tsc_ladder_setting_to_mV(const phymod_access_t *pa, int8_t y, int16_t* level) { 668 669 /* *level = _ladder_setting_to_mV(y,0); */ 670 *level = (y*300)/127; 671 672 return(ERR_CODE_NONE); 673 } 674 675 676 err_code_t phy8806x_tsc_get_vco (const phymod_phy_inf_config_t* config, uint32_t *vco_rate, uint32_t *new_pll_div, int16_t *new_os_mode) { 677 *vco_rate = 0; 678 *new_pll_div=0; 679 *new_os_mode =0; 680 if(config->ref_clock == phymodRefClk156Mhz) { 681 switch (config->data_rate) { 682 case 6250 : /* speed 6.25G */ 683 *new_pll_div = 0x6; *new_os_mode = 2; *vco_rate = 25000; 684 break; 685 686 case 10312: /* speed 10.3125G */ 687 *new_pll_div = 0x4; *new_os_mode = 1; *vco_rate = 20625; 688 break; 689 690 case 10937: /* speed 10.9375G */ 691 *new_pll_div = 0x5; *new_os_mode = 1; *vco_rate = 21875; 692 break; 693 694 case 12500: /* speed 12.5G */ 695 *new_pll_div = 0x6; *new_os_mode = 1; *vco_rate = 25000; 696 break; 697 698 case 20625: /* speed 20.625G */ 699 *new_pll_div = 0x4; *new_os_mode = 0; *vco_rate = 20625; 700 break; 701 702 case 21875: /* speed 21.875G */ 703 *new_pll_div = 0x5; *new_os_mode = 0; *vco_rate = 21875; 704 break; 705 706 case 25000: /* speed 25G */ 707 *new_pll_div = 0x6; *new_os_mode = 0; *vco_rate = 25000; 708 break; 709 710 case 25781: /* speed 25.78125G */ 711 *new_pll_div = 0x7; *new_os_mode = 0; *vco_rate = 25781; 712 break; 713 714 default: 715 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d\n", config->data_rate, config->ref_clock)); 716 return ERR_CODE_DIAG; 717 break; 718 } 719 } else if(config->ref_clock == phymodRefClk125Mhz) { 720 switch (config->data_rate) { 721 722 case 5750: /* speed 5.75G */ 723 *new_pll_div = 0xc; *new_os_mode = 2; *vco_rate = 23000; 724 break; 725 726 case 6250: /* speed 6.25G */ 727 *new_pll_div = 0xd; *new_os_mode = 2; *vco_rate = 25000; 728 break; 729 730 case 10312: /* speed 10.3125G */ 731 *new_pll_div = 0x7; *new_os_mode = 1; *vco_rate = 20625; 732 break; 733 734 case 11250: /* speed 11.25G */ 735 *new_pll_div = 0xb; *new_os_mode = 1; *vco_rate = 22500; 736 break; 737 738 case 11500: /* speed 11.5G */ 739 *new_pll_div = 0xc; *new_os_mode = 1; *vco_rate = 23000; 740 break; 741 742 case 12500: /* speed 12.5G */ 743 *new_pll_div = 0xd; *new_os_mode = 1; *vco_rate = 25000; 744 break; 745 746 case 20625: /* speed 20.625G */ 747 *new_pll_div = 0x7; *new_os_mode = 0; *vco_rate = 20625; 748 break; 749 750 case 22500: /* speed 22.5G */ 751 *new_pll_div = 0xb; *new_os_mode = 0; *vco_rate = 22500; 752 break; 753 754 case 23000: /* speed 23G */ 755 *new_pll_div = 0xc; *new_os_mode = 0; *vco_rate = 23000; 756 break; 757 758 case 25000: /* speed 25G */ 759 *new_pll_div = 0xd; *new_os_mode = 0; *vco_rate = 25000; 760 break; 761 762 default: 763 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d\n", config->data_rate, config->ref_clock)); 764 return ERR_CODE_DIAG; 765 break; 766 } 767 } else { 768 PHYMOD_DEBUG_ERROR(("Unsupported ref clk :: %d\n", config->ref_clock)); 769 return ERR_CODE_DIAG; 770 } 771 return(ERR_CODE_NONE); 772 }