merlin16_fields.h (438264B)
1 /************************************************************************************* 2 ************************************************************************************* 3 * * 4 * Revision : * 5 * * 6 * Description : Register access macros for MERLIN16 7 * * 8 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 9 * 10 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 11 * No portions of this material may be reproduced in any form without * 12 * the written permission of: * 13 * Broadcom Corporation * 14 * 5300 California Avenue * 15 * Irvine, CA 92617 * 16 * * 17 * All information contained in this document is Broadcom Corporation * 18 * company private proprietary, and trade secret. * 19 */ 20 21 /** @file merlin16_fields.h 22 * Register access macros for MERLIN16 23 */ 24 25 /* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */ 26 27 #ifndef MERLIN16_FIELDS_H 28 #define MERLIN16_FIELDS_H 29 30 #define rd_ams_rx_term_lowzvdd() _merlin16_pmd_rde_field_byte(sa__, 0xd090,0,15,__ERR) 31 #define wr_ams_rx_term_lowzvdd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x8000,15,wr_val) 32 #define rd_ams_rx_term_lowzgnd() _merlin16_pmd_rde_field_byte(sa__, 0xd090,1,15,__ERR) 33 #define wr_ams_rx_term_lowzgnd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x4000,14,wr_val) 34 #define rd_ams_rx_term_cmult_ena() _merlin16_pmd_rde_field_byte(sa__, 0xd090,2,15,__ERR) 35 #define wr_ams_rx_term_cmult_ena(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x2000,13,wr_val) 36 #define rd_ams_rx_term_cm_ena() _merlin16_pmd_rde_field_byte(sa__, 0xd090,3,15,__ERR) 37 #define wr_ams_rx_term_cm_ena(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x1000,12,wr_val) 38 #define rd_ams_rx_en_rxck_test() _merlin16_pmd_rde_field_byte(sa__, 0xd090,4,14,__ERR) 39 #define wr_ams_rx_en_rxck_test(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0c00,10,wr_val) 40 #define rd_ams_rx_en_rxck_testport() _merlin16_pmd_rde_field_byte(sa__, 0xd090,6,15,__ERR) 41 #define wr_ams_rx_en_rxck_testport(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0200,9,wr_val) 42 #define rd_ams_rx_spare_0_1() _merlin16_pmd_rde_field_byte(sa__, 0xd090,7,14,__ERR) 43 #define wr_ams_rx_spare_0_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0180,7,wr_val) 44 #define rd_ams_rx_input_cm_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd090,9,15,__ERR) 45 #define wr_ams_rx_input_cm_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0040,6,wr_val) 46 #define rd_ams_rx_vga_cm_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd090,10,15,__ERR) 47 #define wr_ams_rx_vga_cm_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0020,5,wr_val) 48 #define rd_ams_rx_rcm_sum() _merlin16_pmd_rde_field_byte(sa__, 0xd090,11,15,__ERR) 49 #define wr_ams_rx_rcm_sum(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0010,4,wr_val) 50 #define rd_ams_rx_sigdet_bypass() _merlin16_pmd_rde_field_byte(sa__, 0xd090,12,15,__ERR) 51 #define wr_ams_rx_sigdet_bypass(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0008,3,wr_val) 52 #define rd_ams_rx_sigdet_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd090,13,15,__ERR) 53 #define wr_ams_rx_sigdet_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0004,2,wr_val) 54 #define rd_ams_rx_cm_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd090,14,15,__ERR) 55 #define wr_ams_rx_cm_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0002,1,wr_val) 56 #define rd_ams_rx_sum_pseudo_diff() _merlin16_pmd_rde_field_byte(sa__, 0xd090,15,15,__ERR) 57 #define wr_ams_rx_sum_pseudo_diff(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd090,0x0001,0,wr_val) 58 #define rd_ams_rx_curr_dfe_2() _merlin16_pmd_rde_field_byte(sa__, 0xd091,2,13,__ERR) 59 #define wr_ams_rx_curr_dfe_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd091,0x3800,11,wr_val) 60 #define rd_ams_rx_spare_1_0() _merlin16_pmd_rde_field_byte(sa__, 0xd091,5,13,__ERR) 61 #define wr_ams_rx_spare_1_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd091,0x0700,8,wr_val) 62 #define rd_ams_rx_curr_pi() _merlin16_pmd_rde_field_byte(sa__, 0xd091,8,13,__ERR) 63 #define wr_ams_rx_curr_pi(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd091,0x00e0,5,wr_val) 64 #define rd_ams_rx_curr_ctle() _merlin16_pmd_rde_field_byte(sa__, 0xd091,11,13,__ERR) 65 #define wr_ams_rx_curr_ctle(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd091,0x001c,2,wr_val) 66 #define rd_ams_rx_vga_en_hgain() _merlin16_pmd_rde_field_byte(sa__, 0xd091,14,15,__ERR) 67 #define wr_ams_rx_vga_en_hgain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd091,0x0002,1,wr_val) 68 #define rd_ams_rx_vga_out_idle() _merlin16_pmd_rde_field_byte(sa__, 0xd091,15,15,__ERR) 69 #define wr_ams_rx_vga_out_idle(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd091,0x0001,0,wr_val) 70 #define rd_ams_rx_spare_2_0() _merlin16_pmd_rde_field_byte(sa__, 0xd092,0,14,__ERR) 71 #define wr_ams_rx_spare_2_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd092,0xc000,14,wr_val) 72 #define rd_ams_rx_en_dfe_tap_fb() _merlin16_pmd_rde_field_byte(sa__, 0xd092,2,11,__ERR) 73 #define wr_ams_rx_en_dfe_tap_fb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd092,0x3e00,9,wr_val) 74 #define rd_ams_rx_curr_vga() _merlin16_pmd_rde_field_byte(sa__, 0xd092,7,13,__ERR) 75 #define wr_ams_rx_curr_vga(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd092,0x01c0,6,wr_val) 76 #define rd_ams_rx_curr_dfe_summer() _merlin16_pmd_rde_field_byte(sa__, 0xd092,10,13,__ERR) 77 #define wr_ams_rx_curr_dfe_summer(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd092,0x0038,3,wr_val) 78 #define rd_ams_rx_curr_dfe_1() _merlin16_pmd_rde_field_byte(sa__, 0xd092,13,13,__ERR) 79 #define wr_ams_rx_curr_dfe_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd092,0x0007,0,wr_val) 80 #define rd_ams_rx_ll_en() _merlin16_pmd_rde_field_byte(sa__, 0xd093,1,15,__ERR) 81 #define wr_ams_rx_ll_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x4000,14,wr_val) 82 #define rd_ams_rx_seli1p25dfe() _merlin16_pmd_rde_field_byte(sa__, 0xd093,2,15,__ERR) 83 #define wr_ams_rx_seli1p25dfe(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x2000,13,wr_val) 84 #define rd_ams_rx_i4deadzone() _merlin16_pmd_rde_field_byte(sa__, 0xd093,3,15,__ERR) 85 #define wr_ams_rx_i4deadzone(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x1000,12,wr_val) 86 #define rd_ams_rx_curr_sigdet() _merlin16_pmd_rde_field_byte(sa__, 0xd093,4,13,__ERR) 87 #define wr_ams_rx_curr_sigdet(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0e00,9,wr_val) 88 #define rd_ams_rx_curr_vddr_afe() _merlin16_pmd_rde_field_byte(sa__, 0xd093,7,13,__ERR) 89 #define wr_ams_rx_curr_vddr_afe(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x01c0,6,wr_val) 90 #define rd_ams_rx_os2x_mode_even_odd() _merlin16_pmd_rde_field_byte(sa__, 0xd093,10,15,__ERR) 91 #define wr_ams_rx_os2x_mode_even_odd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0020,5,wr_val) 92 #define rd_ams_rx_dfe_os2x_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd093,11,15,__ERR) 93 #define wr_ams_rx_dfe_os2x_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0010,4,wr_val) 94 #define rd_ams_rx_en_20b_demux() _merlin16_pmd_rde_field_byte(sa__, 0xd093,12,15,__ERR) 95 #define wr_ams_rx_en_20b_demux(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0008,3,wr_val) 96 #define rd_ams_rx_en_clk16() _merlin16_pmd_rde_field_byte(sa__, 0xd093,13,15,__ERR) 97 #define wr_ams_rx_en_clk16(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0004,2,wr_val) 98 #define rd_ams_rx_en_clk33() _merlin16_pmd_rde_field_byte(sa__, 0xd093,14,15,__ERR) 99 #define wr_ams_rx_en_clk33(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0002,1,wr_val) 100 #define rd_ams_rx_en_vcctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd093,15,15,__ERR) 101 #define wr_ams_rx_en_vcctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd093,0x0001,0,wr_val) 102 #define rd_ams_rx_vga_pon() _merlin16_pmd_rde_field_byte(sa__, 0xd094,0,12,__ERR) 103 #define wr_ams_rx_vga_pon(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd094,0xf000,12,wr_val) 104 #define rd_ams_rx_oc_2x() _merlin16_pmd_rde_field_byte(sa__, 0xd094,4,15,__ERR) 105 #define wr_ams_rx_oc_2x(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd094,0x0800,11,wr_val) 106 #define rd_ams_rx_spare_4_0() _merlin16_pmd_rde_field_byte(sa__, 0xd094,5,13,__ERR) 107 #define wr_ams_rx_spare_4_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd094,0x0700,8,wr_val) 108 #define rd_ams_rx_en_recclkdiv() _merlin16_pmd_rde_field_byte(sa__, 0xd094,8,15,__ERR) 109 #define wr_ams_rx_en_recclkdiv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd094,0x0080,7,wr_val) 110 #define rd_ams_rx_div3o4o5() _merlin16_pmd_rde_field_byte(sa__, 0xd094,9,14,__ERR) 111 #define wr_ams_rx_div3o4o5(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd094,0x0060,5,wr_val) 112 #define rd_ams_rx_recclkdiv() _merlin16_pmd_rde_field_byte(sa__, 0xd094,11,11,__ERR) 113 #define wr_ams_rx_recclkdiv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd094,0x001f,0,wr_val) 114 #define rd_ams_rx_dcc2_phase_flip() _merlin16_pmd_rde_field_byte(sa__, 0xd095,0,15,__ERR) 115 #define wr_ams_rx_dcc2_phase_flip(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x8000,15,wr_val) 116 #define rd_ams_rx_slcr_calib_range_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd095,1,15,__ERR) 117 #define wr_ams_rx_slcr_calib_range_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x4000,14,wr_val) 118 #define rd_ams_rx_pi_pd() _merlin16_pmd_rde_field_byte(sa__, 0xd095,2,15,__ERR) 119 #define wr_ams_rx_pi_pd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x2000,13,wr_val) 120 #define rd_ams_rx_dcc1_phase_flip() _merlin16_pmd_rde_field_byte(sa__, 0xd095,3,15,__ERR) 121 #define wr_ams_rx_dcc1_phase_flip(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x1000,12,wr_val) 122 #define rd_ams_rx_en_dfeclk() _merlin16_pmd_rde_field_byte(sa__, 0xd095,4,15,__ERR) 123 #define wr_ams_rx_en_dfeclk(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x0800,11,wr_val) 124 #define rd_ams_rx_ctle_gain_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd095,5,12,__ERR) 125 #define wr_ams_rx_ctle_gain_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x0780,7,wr_val) 126 #define rd_ams_rx_curr_in_offset() _merlin16_pmd_rde_field_byte(sa__, 0xd095,9,13,__ERR) 127 #define wr_ams_rx_curr_in_offset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x0070,4,wr_val) 128 #define rd_ams_rx_pon() _merlin16_pmd_rde_field_byte(sa__, 0xd095,12,12,__ERR) 129 #define wr_ams_rx_pon(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd095,0x000f,0,wr_val) 130 #define rd_ams_rx_sigdet_offset_correction_pos() _merlin16_pmd_rde_field_byte(sa__, 0xd096,3,11,__ERR) 131 #define wr_ams_rx_sigdet_offset_correction_pos(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd096,0x1f00,8,wr_val) 132 #define rd_ams_rx_sigdet_calibration_select() _merlin16_pmd_rde_field_byte(sa__, 0xd096,8,15,__ERR) 133 #define wr_ams_rx_sigdet_calibration_select(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd096,0x0080,7,wr_val) 134 #define rd_ams_rx_sum_gain_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd096,9,12,__ERR) 135 #define wr_ams_rx_sum_gain_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd096,0x0078,3,wr_val) 136 #define rd_ams_rx_en_sigdet_calib() _merlin16_pmd_rde_field_byte(sa__, 0xd096,13,15,__ERR) 137 #define wr_ams_rx_en_sigdet_calib(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd096,0x0004,2,wr_val) 138 #define rd_ams_rx_hiz_1() _merlin16_pmd_rde_field_byte(sa__, 0xd096,14,15,__ERR) 139 #define wr_ams_rx_hiz_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd096,0x0002,1,wr_val) 140 #define rd_ams_rx_m1_sign() _merlin16_pmd_rde_field_byte(sa__, 0xd096,15,15,__ERR) 141 #define wr_ams_rx_m1_sign(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd096,0x0001,0,wr_val) 142 #define rd_ams_rx_spare_7_0() _merlin16_pmd_rde_field_byte(sa__, 0xd097,2,12,__ERR) 143 #define wr_ams_rx_spare_7_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd097,0x3c00,10,wr_val) 144 #define rd_ams_rx_sigdet_threshold() _merlin16_pmd_rde_field_byte(sa__, 0xd097,6,11,__ERR) 145 #define wr_ams_rx_sigdet_threshold(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd097,0x03e0,5,wr_val) 146 #define rd_ams_rx_sigdet_offset_correction_neg() _merlin16_pmd_rde_field_byte(sa__, 0xd097,11,11,__ERR) 147 #define wr_ams_rx_sigdet_offset_correction_neg(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd097,0x001f,0,wr_val) 148 #define rd_ams_rx_rxpon_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd098,14,15,__ERR) 149 #define wr_ams_rx_rxpon_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd098,0x0002,1,wr_val) 150 #define rd_ams_rx_vgapon_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd098,15,15,__ERR) 151 #define wr_ams_rx_vgapon_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd098,0x0001,0,wr_val) 152 #define rd_ams_rx_vgapon_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd099,8,12,__ERR) 153 #define rd_ams_rx_rxpon_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd099,12,12,__ERR) 154 #define rd_ams_tx_lowlatency_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,0,15,__ERR) 155 #define wr_ams_tx_lowlatency_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x8000,15,wr_val) 156 #define rd_ams_tx_fifo_resetb() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,1,15,__ERR) 157 #define wr_ams_tx_fifo_resetb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x4000,14,wr_val) 158 #define rd_ams_tx_ll_fifo_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,2,13,__ERR) 159 #define wr_ams_tx_ll_fifo_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x3800,11,wr_val) 160 #define rd_ams_tx_ll_fifo_zero_out() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,5,15,__ERR) 161 #define wr_ams_tx_ll_fifo_zero_out(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0400,10,wr_val) 162 #define rd_ams_tx_ll_polarity_flip() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,6,15,__ERR) 163 #define wr_ams_tx_ll_polarity_flip(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0200,9,wr_val) 164 #define rd_ams_tx_ll_selpath_tx() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,7,15,__ERR) 165 #define wr_ams_tx_ll_selpath_tx(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0100,8,wr_val) 166 #define rd_ams_tx_enable_os_2() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,8,15,__ERR) 167 #define wr_ams_tx_enable_os_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0080,7,wr_val) 168 #define rd_ams_tx_pon() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,9,12,__ERR) 169 #define wr_ams_tx_pon(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0078,3,wr_val) 170 #define rd_ams_tx_ticksel() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,13,14,__ERR) 171 #define wr_ams_tx_ticksel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0006,1,wr_val) 172 #define rd_ams_tx_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd0a0,15,15,__ERR) 173 #define wr_ams_tx_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0001,0,wr_val) 174 #define rd_ams_tx_en_slow() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,1,12,__ERR) 175 #define wr_ams_tx_en_slow(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x7800,11,wr_val) 176 #define rd_ams_tx_en_wclk33() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,5,15,__ERR) 177 #define wr_ams_tx_en_wclk33(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0400,10,wr_val) 178 #define rd_ams_tx_en_wclk20() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,6,15,__ERR) 179 #define wr_ams_tx_en_wclk20(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0200,9,wr_val) 180 #define rd_ams_tx_en_wclk16() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,7,15,__ERR) 181 #define wr_ams_tx_en_wclk16(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0100,8,wr_val) 182 #define rd_ams_tx_testclk_ena() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,8,15,__ERR) 183 #define wr_ams_tx_testclk_ena(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0080,7,wr_val) 184 #define rd_ams_tx_testsel() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,9,14,__ERR) 185 #define wr_ams_tx_testsel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0060,5,wr_val) 186 #define rd_ams_tx_cntrl_rxdetect_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,11,15,__ERR) 187 #define wr_ams_tx_cntrl_rxdetect_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0010,4,wr_val) 188 #define rd_ams_tx_rxdtct_th_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,12,14,__ERR) 189 #define wr_ams_tx_rxdtct_th_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x000c,2,wr_val) 190 #define rd_ams_tx_en_high_current() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,14,15,__ERR) 191 #define wr_ams_tx_en_high_current(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0002,1,wr_val) 192 #define rd_ams_tx_enable_os_4() _merlin16_pmd_rde_field_byte(sa__, 0xd0a1,15,15,__ERR) 193 #define wr_ams_tx_enable_os_4(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0001,0,wr_val) 194 #define rd_ams_tx_fifo_phsdetect_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0a2,1,15,__ERR) 195 #define wr_ams_tx_fifo_phsdetect_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a2,0x4000,14,wr_val) 196 #define rd_ams_tx_ibias_pibuf_cntl() _merlin16_pmd_rde_field_byte(sa__, 0xd0a2,2,13,__ERR) 197 #define wr_ams_tx_ibias_pibuf_cntl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a2,0x3800,11,wr_val) 198 #define rd_ams_tx_ibias_pi_cntl() _merlin16_pmd_rde_field_byte(sa__, 0xd0a2,5,13,__ERR) 199 #define wr_ams_tx_ibias_pi_cntl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a2,0x0700,8,wr_val) 200 #define rd_ams_tx_ibias_opamp_cntl() _merlin16_pmd_rde_field_byte(sa__, 0xd0a2,8,13,__ERR) 201 #define wr_ams_tx_ibias_opamp_cntl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a2,0x00e0,5,wr_val) 202 #define rd_ams_tx_dcc_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0a2,11,15,__ERR) 203 #define wr_ams_tx_dcc_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a2,0x0010,4,wr_val) 204 #define rd_ams_tx_en_hpf() _merlin16_pmd_rde_field_byte(sa__, 0xd0a2,12,12,__ERR) 205 #define wr_ams_tx_en_hpf(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a2,0x000f,0,wr_val) 206 #define rd_ams_tx_refcalm() _merlin16_pmd_rde_field_byte(sa__, 0xd0a3,2,12,__ERR) 207 #define wr_ams_tx_refcalm(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a3,0x3c00,10,wr_val) 208 #define rd_ams_tx_refcalp() _merlin16_pmd_rde_field_byte(sa__, 0xd0a3,6,12,__ERR) 209 #define wr_ams_tx_refcalp(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a3,0x03c0,6,wr_val) 210 #define rd_ams_tx_refcalshunt() _merlin16_pmd_rde_field_byte(sa__, 0xd0a3,10,12,__ERR) 211 #define wr_ams_tx_refcalshunt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a3,0x003c,2,wr_val) 212 #define rd_ams_tx_spare_3_0() _merlin16_pmd_rde_field_byte(sa__, 0xd0a3,14,14,__ERR) 213 #define wr_ams_tx_spare_3_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a3,0x0003,0,wr_val) 214 #define rd_ams_tx_shntpost2_post2() _merlin16_pmd_rde_field_byte(sa__, 0xd0a4,0,12,__ERR) 215 #define wr_ams_tx_shntpost2_post2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a4,0xf000,12,wr_val) 216 #define rd_ams_tx_shntpost1_post1pre() _merlin16_pmd_rde_field_byte(sa__, 0xd0a4,4,10,__ERR) 217 #define wr_ams_tx_shntpost1_post1pre(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a4,0x0fc0,6,wr_val) 218 #define rd_ams_tx_shntpre_post1pre() _merlin16_pmd_rde_field_byte(sa__, 0xd0a4,10,10,__ERR) 219 #define wr_ams_tx_shntpre_post1pre(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a4,0x003f,0,wr_val) 220 #define rd_ams_tx_post2to1() _merlin16_pmd_rde_field_byte(sa__, 0xd0a5,2,15,__ERR) 221 #define wr_ams_tx_post2to1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a5,0x2000,13,wr_val) 222 #define rd_ams_tx_en_pre() _merlin16_pmd_rde_field_byte(sa__, 0xd0a5,3,15,__ERR) 223 #define wr_ams_tx_en_pre(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a5,0x1000,12,wr_val) 224 #define rd_ams_tx_en_post1() _merlin16_pmd_rde_field_byte(sa__, 0xd0a5,4,15,__ERR) 225 #define wr_ams_tx_en_post1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0800,11,wr_val) 226 #define rd_ams_tx_en_post2() _merlin16_pmd_rde_field_byte(sa__, 0xd0a5,5,15,__ERR) 227 #define wr_ams_tx_en_post2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0400,10,wr_val) 228 #define rd_ams_tx_shntmain_post2() _merlin16_pmd_rde_field_byte(sa__, 0xd0a5,6,12,__ERR) 229 #define wr_ams_tx_shntmain_post2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a5,0x03c0,6,wr_val) 230 #define rd_ams_tx_shntmain_post1pre() _merlin16_pmd_rde_field_byte(sa__, 0xd0a5,10,10,__ERR) 231 #define wr_ams_tx_shntmain_post1pre(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a5,0x003f,0,wr_val) 232 #define rd_ams_tx_shntpost1_post1() _merlin16_pmd_rde_field_byte(sa__, 0xd0a6,0,11,__ERR) 233 #define wr_ams_tx_shntpost1_post1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a6,0xf800,11,wr_val) 234 #define rd_ams_tx_dis_cal() _merlin16_pmd_rde_field_byte(sa__, 0xd0a6,5,11,__ERR) 235 #define wr_ams_tx_dis_cal(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a6,0x07c0,6,wr_val) 236 #define rd_ams_tx_spare_6_0() _merlin16_pmd_rde_field_byte(sa__, 0xd0a6,10,12,__ERR) 237 #define wr_ams_tx_spare_6_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a6,0x003c,2,wr_val) 238 #define rd_ams_tx_pd_phasedet() _merlin16_pmd_rde_field_byte(sa__, 0xd0a6,14,15,__ERR) 239 #define wr_ams_tx_pd_phasedet(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a6,0x0002,1,wr_val) 240 #define rd_ams_tx_en_shuntmode() _merlin16_pmd_rde_field_byte(sa__, 0xd0a6,15,15,__ERR) 241 #define wr_ams_tx_en_shuntmode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a6,0x0001,0,wr_val) 242 #define rd_ams_tx_refcalpcs() _merlin16_pmd_rde_field_byte(sa__, 0xd0a7,3,12,__ERR) 243 #define wr_ams_tx_refcalpcs(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a7,0x1e00,9,wr_val) 244 #define rd_ams_tx_refcalmcs() _merlin16_pmd_rde_field_byte(sa__, 0xd0a7,7,12,__ERR) 245 #define wr_ams_tx_refcalmcs(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a7,0x01e0,5,wr_val) 246 #define rd_ams_tx_shntmain_post1() _merlin16_pmd_rde_field_byte(sa__, 0xd0a7,11,11,__ERR) 247 #define wr_ams_tx_shntmain_post1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a7,0x001f,0,wr_val) 248 #define rd_ams_tx_spare_8_0() _merlin16_pmd_rde_field_byte(sa__, 0xd0a8,7,8,__ERR) 249 #define wr_ams_tx_spare_8_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a8,0x01fe,1,wr_val) 250 #define rd_ams_tx_shnten_main() _merlin16_pmd_rde_field_byte(sa__, 0xd0a8,15,15,__ERR) 251 #define wr_ams_tx_shnten_main(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a8,0x0001,0,wr_val) 252 #define rd_ams_tx_sel_txmaster() _merlin16_pmd_rde_field_byte(sa__, 0xd0a9,12,15,__ERR) 253 #define wr_ams_tx_sel_txmaster(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0008,3,wr_val) 254 #define rd_ams_tx_auto_ll_selpath_tx_dis() _merlin16_pmd_rde_field_byte(sa__, 0xd0a9,13,15,__ERR) 255 #define wr_ams_tx_auto_ll_selpath_tx_dis(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0004,2,wr_val) 256 #define rd_ams_tx_txpon_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0a9,14,15,__ERR) 257 #define wr_ams_tx_txpon_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0002,1,wr_val) 258 #define rd_ams_tx_rescal() _merlin16_pmd_rde_field_byte(sa__, 0xd0aa,8,12,__ERR) 259 #define rd_ams_tx_txpon_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd0aa,12,12,__ERR) 260 #define rdc_ams_pll_cpar() _merlin16_pmd_rde_field_byte(sa__, 0xd0b0,0,14,__ERR) 261 #define wrc_ams_pll_cpar(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b0,0xc000,14,wr_val) 262 #define rdc_ams_pll_term_cm_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0b0,2,15,__ERR) 263 #define wrc_ams_pll_term_cm_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b0,0x2000,13,wr_val) 264 #define rdc_ams_pll_spare_0_1() _merlin16_pmd_rde_field_byte(sa__, 0xd0b0,3,15,__ERR) 265 #define wrc_ams_pll_spare_0_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b0,0x1000,12,wr_val) 266 #define rdc_ams_pll_rpar() _merlin16_pmd_rde_field_byte(sa__, 0xd0b0,4,13,__ERR) 267 #define wrc_ams_pll_rpar(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0e00,9,wr_val) 268 #define rdc_ams_pll_lc_refclk_adj_1_0() _merlin16_pmd_rde_field_byte(sa__, 0xd0b0,7,14,__ERR) 269 #define wrc_ams_pll_lc_refclk_adj_1_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0180,7,wr_val) 270 #define rdc_ams_pll_spare_0_0() _merlin16_pmd_rde_field_byte(sa__, 0xd0b0,9,9,__ERR) 271 #define wrc_ams_pll_spare_0_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b0,0x007f,0,wr_val) 272 #define rdc_ams_pll_en_hcur_vco() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,0,15,__ERR) 273 #define wrc_ams_pll_en_hcur_vco(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x8000,15,wr_val) 274 #define rdc_ams_pll_enb_10t() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,1,15,__ERR) 275 #define wrc_ams_pll_enb_10t(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x4000,14,wr_val) 276 #define rdc_ams_pll_enb_8t() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,2,15,__ERR) 277 #define wrc_ams_pll_enb_8t(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x2000,13,wr_val) 278 #define rdc_ams_pll_vco_range() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,3,9,__ERR) 279 #define wrc_ams_pll_vco_range(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x1fc0,6,wr_val) 280 #define rdc_ams_pll_en_8p5g_vco() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,10,15,__ERR) 281 #define wrc_ams_pll_en_8p5g_vco(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0020,5,wr_val) 282 #define rdc_ams_pll_spare_1_0() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,11,15,__ERR) 283 #define wrc_ams_pll_spare_1_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0010,4,wr_val) 284 #define rdc_ams_pll_curr_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b1,12,12,__ERR) 285 #define wrc_ams_pll_curr_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b1,0x000f,0,wr_val) 286 #define rdc_ams_pll_en_i4iqbuf() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,0,14,__ERR) 287 #define wrc_ams_pll_en_i4iqbuf(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0xc000,14,wr_val) 288 #define rdc_ams_pll_vco_buf_pon() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,2,12,__ERR) 289 #define wrc_ams_pll_vco_buf_pon(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0x3c00,10,wr_val) 290 #define rdc_ams_pll_clkvco_cal_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,6,15,__ERR) 291 #define wrc_ams_pll_clkvco_cal_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0200,9,wr_val) 292 #define rdc_ams_pll_en_cmos_refclk_ch_hiz() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,7,15,__ERR) 293 #define wrc_ams_pll_en_cmos_refclk_ch_hiz(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0100,8,wr_val) 294 #define rdc_ams_pll_calib_adj() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,8,13,__ERR) 295 #define wrc_ams_pll_calib_adj(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0x00e0,5,wr_val) 296 #define rdc_ams_pll_en_8p5g() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,11,15,__ERR) 297 #define wrc_ams_pll_en_8p5g(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0010,4,wr_val) 298 #define rdc_ams_pll_vco_pon() _merlin16_pmd_rde_field_byte(sa__, 0xd0b2,12,12,__ERR) 299 #define wrc_ams_pll_vco_pon(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b2,0x000f,0,wr_val) 300 #define rdc_ams_pll_en_mmd_halfrate() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,0,15,__ERR) 301 #define wrc_ams_pll_en_mmd_halfrate(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x8000,15,wr_val) 302 #define rdc_ams_pll_cp_bias() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,1,13,__ERR) 303 #define wrc_ams_pll_cp_bias(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x7000,12,wr_val) 304 #define rdc_ams_pll_ref_cml_curx2() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,4,15,__ERR) 305 #define wrc_ams_pll_ref_cml_curx2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0800,11,wr_val) 306 #define rdc_ams_pll_ref_cmos_hz() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,5,15,__ERR) 307 #define wrc_ams_pll_ref_cmos_hz(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0400,10,wr_val) 308 #define rdc_ams_pll_ref_cml_pd() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,6,15,__ERR) 309 #define wrc_ams_pll_ref_cml_pd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0200,9,wr_val) 310 #define rdc_ams_pll_clksel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,7,15,__ERR) 311 #define wrc_ams_pll_clksel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0100,8,wr_val) 312 #define rdc_ams_pll_en_rclk_refout() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,8,15,__ERR) 313 #define wrc_ams_pll_en_rclk_refout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0080,7,wr_val) 314 #define rdc_ams_pll_en_cmos_refout_overwr() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,9,15,__ERR) 315 #define wrc_ams_pll_en_cmos_refout_overwr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0040,6,wr_val) 316 #define rdc_ams_pll_en_cml_refout_overwr() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,10,15,__ERR) 317 #define wrc_ams_pll_en_cml_refout_overwr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0020,5,wr_val) 318 #define rdc_ams_pll_en_test_frac_clk() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,11,15,__ERR) 319 #define wrc_ams_pll_en_test_frac_clk(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0010,4,wr_val) 320 #define rdc_ams_pll_enb_16t() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,12,15,__ERR) 321 #define wrc_ams_pll_enb_16t(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0008,3,wr_val) 322 #define rdc_ams_pll_band_iqbuf_ctr() _merlin16_pmd_rde_field_byte(sa__, 0xd0b3,13,13,__ERR) 323 #define wrc_ams_pll_band_iqbuf_ctr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0007,0,wr_val) 324 #define rdc_ams_pll_test_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,1,13,__ERR) 325 #define wrc_ams_pll_test_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x7000,12,wr_val) 326 #define rdc_ams_pll_test_amp() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,4,14,__ERR) 327 #define wrc_ams_pll_test_amp(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0c00,10,wr_val) 328 #define rdc_ams_pll_vco_test_clk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,6,15,__ERR) 329 #define wrc_ams_pll_vco_test_clk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0200,9,wr_val) 330 #define rdc_ams_pll_bias_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,7,15,__ERR) 331 #define wrc_ams_pll_bias_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0100,8,wr_val) 332 #define rdc_ams_pll_vco_hkvco() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,8,15,__ERR) 333 #define wrc_ams_pll_vco_hkvco(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0080,7,wr_val) 334 #define rdc_ams_pll_bias_vdd_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,9,14,__ERR) 335 #define wrc_ams_pll_bias_vdd_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0060,5,wr_val) 336 #define rdc_ams_pll_cmos_tport_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,11,15,__ERR) 337 #define wrc_ams_pll_cmos_tport_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0010,4,wr_val) 338 #define rdc_ams_pll_cp_opamp_bias() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,12,14,__ERR) 339 #define wrc_ams_pll_cp_opamp_bias(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x000c,2,wr_val) 340 #define rdc_ams_pll_lc_refclk_adj_3_2() _merlin16_pmd_rde_field_byte(sa__, 0xd0b4,14,14,__ERR) 341 #define wrc_ams_pll_lc_refclk_adj_3_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0003,0,wr_val) 342 #define rdc_ams_pll_refdiv_test_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,3,13,__ERR) 343 #define wrc_ams_pll_refdiv_test_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x1c00,10,wr_val) 344 #define rdc_ams_pll_pwdb_extr_d2c() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,6,15,__ERR) 345 #define wrc_ams_pll_pwdb_extr_d2c(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0200,9,wr_val) 346 #define rdc_ams_pll_en_refout_div() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,7,15,__ERR) 347 #define wrc_ams_pll_en_refout_div(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0100,8,wr_val) 348 #define rdc_ams_pll_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,8,15,__ERR) 349 #define wrc_ams_pll_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0080,7,wr_val) 350 #define rdc_ams_pll_term_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,9,14,__ERR) 351 #define wrc_ams_pll_term_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0060,5,wr_val) 352 #define rdc_ams_pll_test_sel_overwrite() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,11,15,__ERR) 353 #define wrc_ams_pll_test_sel_overwrite(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0010,4,wr_val) 354 #define rdc_ams_pll_test_vc() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,12,15,__ERR) 355 #define wrc_ams_pll_test_vc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0008,3,wr_val) 356 #define rdc_ams_pll_refout_div_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0b5,13,13,__ERR) 357 #define wrc_ams_pll_refout_div_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0007,0,wr_val) 358 #define rdc_ams_pll_i_ndiv_frac_l() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,0,12,__ERR) 359 #define wrc_ams_pll_i_ndiv_frac_l(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0xf000,12,wr_val) 360 #define rdc_ams_pll_i_pfd_offset() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,4,14,__ERR) 361 #define wrc_ams_pll_i_pfd_offset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0c00,10,wr_val) 362 #define rdc_ams_pll_spare6_1() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,6,15,__ERR) 363 #define wrc_ams_pll_spare6_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0200,9,wr_val) 364 #define rdc_ams_pll_i_pfd_offset_enlarge() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,7,15,__ERR) 365 #define wrc_ams_pll_i_pfd_offset_enlarge(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0100,8,wr_val) 366 #define rdc_ams_pll_vco_i_boost() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,8,14,__ERR) 367 #define wrc_ams_pll_vco_i_boost(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0x00c0,6,wr_val) 368 #define rdc_ams_pll_vco_gm_boost() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,10,14,__ERR) 369 #define wrc_ams_pll_vco_gm_boost(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0030,4,wr_val) 370 #define rdc_ams_pll_pon() _merlin16_pmd_rde_field_byte(sa__, 0xd0b6,12,12,__ERR) 371 #define wrc_ams_pll_pon(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b6,0x000f,0,wr_val) 372 #define rdc_ams_pll_i_ndiv_frac_h() _merlin16_pmd_rde_field(sa__, 0xd0b7,2,2,__ERR) 373 #define wrc_ams_pll_i_ndiv_frac_h(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd0b7,0x3fff,0,wr_val) 374 #define rdc_ams_pll_i_ndiv_dither_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0b8,0,15,__ERR) 375 #define wrc_ams_pll_i_ndiv_dither_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b8,0x8000,15,wr_val) 376 #define rdc_ams_pll_i_pll_sdm_pwrdnb() _merlin16_pmd_rde_field_byte(sa__, 0xd0b8,1,15,__ERR) 377 #define wrc_ams_pll_i_pll_sdm_pwrdnb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b8,0x4000,14,wr_val) 378 #define rdc_ams_pll_vcofb_div() _merlin16_pmd_rde_field_byte(sa__, 0xd0b8,2,14,__ERR) 379 #define wrc_ams_pll_vcofb_div(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b8,0x3000,12,wr_val) 380 #define rdc_ams_pll_cml_refclk_bias() _merlin16_pmd_rde_field_byte(sa__, 0xd0b8,4,14,__ERR) 381 #define wrc_ams_pll_cml_refclk_bias(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b8,0x0c00,10,wr_val) 382 #define rdc_ams_pll_i_ndiv_int() _merlin16_pmd_rde_field(sa__, 0xd0b8,6,6,__ERR) 383 #define wrc_ams_pll_i_ndiv_int(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd0b8,0x03ff,0,wr_val) 384 #define rdc_ams_pll_cml_refclk_adj() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,0,14,__ERR) 385 #define wrc_ams_pll_cml_refclk_adj(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0xc000,14,wr_val) 386 #define rdc_ams_pll_bias_iq_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,2,13,__ERR) 387 #define wrc_ams_pll_bias_iq_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0x3800,11,wr_val) 388 #define rdc_ams_pll_bias_div_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,5,13,__ERR) 389 #define wrc_ams_pll_bias_div_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0700,8,wr_val) 390 #define rdc_ams_pll_vco_supply_adj() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,8,15,__ERR) 391 #define wrc_ams_pll_vco_supply_adj(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0080,7,wr_val) 392 #define rdc_ams_pll_sel_fp3cap() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,9,12,__ERR) 393 #define wrc_ams_pll_sel_fp3cap(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0078,3,wr_val) 394 #define rdc_ams_pll_i_pll_frac_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,13,14,__ERR) 395 #define wrc_ams_pll_i_pll_frac_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0006,1,wr_val) 396 #define rdc_ams_pll_mmd_resetb() _merlin16_pmd_rde_field_byte(sa__, 0xd0b9,15,15,__ERR) 397 #define wrc_ams_pll_mmd_resetb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0001,0,wr_val) 398 #define rdc_ams_pll_refclk_in_bias() _merlin16_pmd_rde_field_byte(sa__, 0xd0ba,10,10,__ERR) 399 #define wrc_ams_pll_refclk_in_bias(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0ba,0x003f,0,wr_val) 400 #define rdc_ams_pll_refclk_term_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd0be,12,15,__ERR) 401 #define wrc_ams_pll_refclk_term_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0be,0x0008,3,wr_val) 402 #define rdc_ams_pll_refclk_div_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd0be,13,15,__ERR) 403 #define wrc_ams_pll_refclk_div_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0be,0x0004,2,wr_val) 404 #define rdc_ams_pll_refclk_div2_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd0be,14,15,__ERR) 405 #define wrc_ams_pll_refclk_div2_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0be,0x0002,1,wr_val) 406 #define rdc_ams_pll_refclk_div4_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd0be,15,15,__ERR) 407 #define wrc_ams_pll_refclk_div4_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0be,0x0001,0,wr_val) 408 #define rdc_ams_pll_afe_rev_id() _merlin16_pmd_rde_field_byte(sa__, 0xd0bf,12,12,__ERR) 409 #define rd_cl72_ieee_lp_coeff_update() _merlin16_pmd_rde_reg(sa__, 0x0098,__ERR) 410 #define rd_cl72_ieee_lp_status_report() _merlin16_pmd_rde_reg(sa__, 0x0099,__ERR) 411 #define rd_cl72_ieee_training_enable() _merlin16_pmd_rde_field_byte(sa__, 0x0096,14,15,__ERR) 412 #define wr_cl72_ieee_training_enable(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0x0096,0x0002,1,wr_val) 413 #define rd_cl72_ieee_restart_training() _merlin16_pmd_rde_field_byte(sa__, 0x0096,15,15,__ERR) 414 #define wr_cl72_ieee_restart_training(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0x0096,0x0001,0,wr_val) 415 #define rd_cl72_ieee_training_failure() _merlin16_pmd_rde_field_byte(sa__, 0x0097,12,15,__ERR) 416 #define rd_cl72_ieee_training_status() _merlin16_pmd_rde_field_byte(sa__, 0x0097,13,15,__ERR) 417 #define rd_cl72_ieee_frame_lock() _merlin16_pmd_rde_field_byte(sa__, 0x0097,14,15,__ERR) 418 #define rd_cl72_ieee_receiver_status() _merlin16_pmd_rde_field_byte(sa__, 0x0097,15,15,__ERR) 419 #define rd_cl72_ieee_ld_coeff_update() _merlin16_pmd_rde_reg(sa__, 0x009a,__ERR) 420 #define rd_cl72_ieee_ld_status_report() _merlin16_pmd_rde_reg(sa__, 0x009b,__ERR) 421 #define rd_cl72_rx_signal_ok() _merlin16_pmd_rde_field_byte(sa__, 0xd050,13,15,__ERR) 422 #define wr_cl72_rx_signal_ok(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd050,0x0004,2,wr_val) 423 #define rd_cl72_tr_coarse_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd050,14,15,__ERR) 424 #define wr_cl72_tr_coarse_lock(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd050,0x0002,1,wr_val) 425 #define rd_cl72_rx_training_en() _merlin16_pmd_rde_field_byte(sa__, 0xd050,15,15,__ERR) 426 #define wr_cl72_rx_training_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd050,0x0001,0,wr_val) 427 #define rd_cl72_bad_marker_cnt() _merlin16_pmd_rde_field_byte(sa__, 0xd051,9,13,__ERR) 428 #define wr_cl72_bad_marker_cnt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd051,0x0070,4,wr_val) 429 #define rd_cl72_good_marker_cnt() _merlin16_pmd_rde_field_byte(sa__, 0xd051,14,14,__ERR) 430 #define wr_cl72_good_marker_cnt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd051,0x0003,0,wr_val) 431 #define rd_cl72_frame_consistency_chk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd052,6,15,__ERR) 432 #define wr_cl72_frame_consistency_chk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x0200,9,wr_val) 433 #define rd_cl72_rx_dp_ln_clk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd052,7,15,__ERR) 434 #define wr_cl72_rx_dp_ln_clk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x0100,8,wr_val) 435 #define rd_cl72_ppm_offset_en() _merlin16_pmd_rde_field_byte(sa__, 0xd052,8,15,__ERR) 436 #define wr_cl72_ppm_offset_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x0080,7,wr_val) 437 #define rd_cl72_strict_marker_chk() _merlin16_pmd_rde_field_byte(sa__, 0xd052,9,15,__ERR) 438 #define wr_cl72_strict_marker_chk(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x0040,6,wr_val) 439 #define rd_cl72_strict_dme_chk() _merlin16_pmd_rde_field_byte(sa__, 0xd052,10,15,__ERR) 440 #define wr_cl72_strict_dme_chk(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x0020,5,wr_val) 441 #define rd_cl72_dme_cell_boundary_chk() _merlin16_pmd_rde_field_byte(sa__, 0xd052,11,15,__ERR) 442 #define wr_cl72_dme_cell_boundary_chk(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x0010,4,wr_val) 443 #define rd_cl72_ctrl_frame_dly() _merlin16_pmd_rde_field_byte(sa__, 0xd052,12,12,__ERR) 444 #define wr_cl72_ctrl_frame_dly(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd052,0x000f,0,wr_val) 445 #define rd_cl72_remote_rx_ready() _merlin16_pmd_rde_field_byte(sa__, 0xd053,14,15,__ERR) 446 #define rd_cl72_frame_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd053,15,15,__ERR) 447 #define rd_cl72_micro_status_resp_int_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd054,4,15,__ERR) 448 #define wr_cl72_micro_status_resp_int_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0800,11,wr_val) 449 #define rd_cl72_micro_status_resp_int_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd054,5,15,__ERR) 450 #define wr_cl72_micro_status_resp_int_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0400,10,wr_val) 451 #define rd_cl72_micro_update_req_int_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd054,6,15,__ERR) 452 #define wr_cl72_micro_update_req_int_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0200,9,wr_val) 453 #define rd_cl72_micro_update_req_int_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd054,7,15,__ERR) 454 #define wr_cl72_micro_update_req_int_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0100,8,wr_val) 455 #define rd_cl72_micro_frame_lock_int_en() _merlin16_pmd_rde_field_byte(sa__, 0xd054,13,15,__ERR) 456 #define wr_cl72_micro_frame_lock_int_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0004,2,wr_val) 457 #define rd_cl72_micro_status_chg_int_en() _merlin16_pmd_rde_field_byte(sa__, 0xd054,14,15,__ERR) 458 #define wr_cl72_micro_status_chg_int_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0002,1,wr_val) 459 #define rd_cl72_micro_update_chg_int_en() _merlin16_pmd_rde_field_byte(sa__, 0xd054,15,15,__ERR) 460 #define wr_cl72_micro_update_chg_int_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd054,0x0001,0,wr_val) 461 #define rd_cl72_micro_update_chg_lstatus() _merlin16_pmd_rde_field_byte(sa__, 0xd055,15,15,__ERR) 462 #define rd_cl72_micro_frame_lock_lstatus() _merlin16_pmd_rde_field_byte(sa__, 0xd056,14,15,__ERR) 463 #define rd_cl72_micro_status_chg_lstatus() _merlin16_pmd_rde_field_byte(sa__, 0xd056,15,15,__ERR) 464 #define rd_cl72_xmt_update_page() _merlin16_pmd_rde_reg(sa__, 0xd060,__ERR) 465 #define wr_cl72_xmt_update_page(wr_val) merlin16_pmd_wr_reg(sa__, 0xd060,wr_val) 466 #define rd_cl72_ld_xmt_status_page() _merlin16_pmd_rde_reg(sa__, 0xd061,__ERR) 467 #define wr_cl72_ld_xmt_status_page(wr_val) merlin16_pmd_wr_reg(sa__, 0xd061,wr_val) 468 #define rd_cl72_sw_remote_rx_ready() _merlin16_pmd_rde_field_byte(sa__, 0xd062,13,15,__ERR) 469 #define wr_cl72_sw_remote_rx_ready(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd062,0x0004,2,wr_val) 470 #define rd_cl72_sw_rx_trained() _merlin16_pmd_rde_field_byte(sa__, 0xd062,15,15,__ERR) 471 #define wr_cl72_sw_rx_trained(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd062,0x0001,0,wr_val) 472 #define rd_cl72_sw_frame_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd062,14,15,__ERR) 473 #define wr_cl72_sw_frame_lock(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd062,0x0002,1,wr_val) 474 #define rd_cl72_tx_dp_ln_clk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd063,13,15,__ERR) 475 #define wr_cl72_tx_dp_ln_clk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd063,0x0004,2,wr_val) 476 #define rd_cl72_dis_max_wait_timer() _merlin16_pmd_rde_field_byte(sa__, 0xd063,14,15,__ERR) 477 #define wr_cl72_dis_max_wait_timer(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd063,0x0002,1,wr_val) 478 #define rd_cl72_brk_ring_osc() _merlin16_pmd_rde_field_byte(sa__, 0xd063,15,15,__ERR) 479 #define wr_cl72_brk_ring_osc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd063,0x0001,0,wr_val) 480 #define rd_cl72_txfir_post() _merlin16_pmd_rde_field_byte(sa__, 0xd064,3,11,__ERR) 481 #define wr_cl72_txfir_post(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd064,0x1f00,8,wr_val) 482 #define rd_cl72_txfir_pre() _merlin16_pmd_rde_field_byte(sa__, 0xd064,12,12,__ERR) 483 #define wr_cl72_txfir_pre(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd064,0x000f,0,wr_val) 484 #define rd_cl72_txfir_main() _merlin16_pmd_rde_field_byte(sa__, 0xd065,10,10,__ERR) 485 #define wr_cl72_txfir_main(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd065,0x003f,0,wr_val) 486 #define rd_cl72_training_fsm_signal_detect() _merlin16_pmd_rde_field_byte(sa__, 0xd066,14,15,__ERR) 487 #define rd_cl72_local_rx_ready() _merlin16_pmd_rde_field_byte(sa__, 0xd066,15,15,__ERR) 488 #define rd_cl72_prbs_seed_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd067,0,14,__ERR) 489 #define wr_cl72_prbs_seed_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd067,0xc000,14,wr_val) 490 #define rd_cl72_prbs_mode_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd067,2,15,__ERR) 491 #define wr_cl72_prbs_mode_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd067,0x2000,13,wr_val) 492 #define rd_cl72_cl93prbs_poly_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd067,3,14,__ERR) 493 #define wr_cl72_cl93prbs_poly_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd067,0x1800,11,wr_val) 494 #define rd_cl72_prbs_seed_val() _merlin16_pmd_rde_field(sa__, 0xd067,5,5,__ERR) 495 #define wr_cl72_prbs_seed_val(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd067,0x07ff,0,wr_val) 496 #define rdc_tx_lane_addr_0() _merlin16_pmd_rde_field_byte(sa__, 0xd150,3,11,__ERR) 497 #define wrc_tx_lane_addr_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd150,0x1f00,8,wr_val) 498 #define rdc_rx_lane_addr_0() _merlin16_pmd_rde_field_byte(sa__, 0xd150,11,11,__ERR) 499 #define wrc_rx_lane_addr_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd150,0x001f,0,wr_val) 500 #define rdc_tx_lane_addr_1() _merlin16_pmd_rde_field_byte(sa__, 0xd151,3,11,__ERR) 501 #define wrc_tx_lane_addr_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd151,0x1f00,8,wr_val) 502 #define rdc_rx_lane_addr_1() _merlin16_pmd_rde_field_byte(sa__, 0xd151,11,11,__ERR) 503 #define wrc_rx_lane_addr_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd151,0x001f,0,wr_val) 504 #define rdc_tx_lane_addr_2() _merlin16_pmd_rde_field_byte(sa__, 0xd152,3,11,__ERR) 505 #define wrc_tx_lane_addr_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd152,0x1f00,8,wr_val) 506 #define rdc_rx_lane_addr_2() _merlin16_pmd_rde_field_byte(sa__, 0xd152,11,11,__ERR) 507 #define wrc_rx_lane_addr_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd152,0x001f,0,wr_val) 508 #define rdc_tx_lane_addr_3() _merlin16_pmd_rde_field_byte(sa__, 0xd153,3,11,__ERR) 509 #define wrc_tx_lane_addr_3(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd153,0x1f00,8,wr_val) 510 #define rdc_rx_lane_addr_3() _merlin16_pmd_rde_field_byte(sa__, 0xd153,11,11,__ERR) 511 #define wrc_rx_lane_addr_3(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd153,0x001f,0,wr_val) 512 #define rdc_revid_rev_letter() _merlin16_pmd_rde_field_byte(sa__, 0xd0f0,0,14,__ERR) 513 #define rdc_revid_rev_number() _merlin16_pmd_rde_field_byte(sa__, 0xd0f0,2,13,__ERR) 514 #define rdc_revid_bonding() _merlin16_pmd_rde_field_byte(sa__, 0xd0f0,5,14,__ERR) 515 #define rdc_revid_process() _merlin16_pmd_rde_field_byte(sa__, 0xd0f0,7,13,__ERR) 516 #define rdc_revid_model() _merlin16_pmd_rde_field_byte(sa__, 0xd0f0,10,10,__ERR) 517 #define rdc_revid_multiplicity() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,0,12,__ERR) 518 #define rdc_revid_mdio() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,10,15,__ERR) 519 #define rdc_revid_micro() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,11,15,__ERR) 520 #define rdc_revid_cl72() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,12,15,__ERR) 521 #define rdc_revid_pir() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,13,15,__ERR) 522 #define rdc_revid_llp() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,14,15,__ERR) 523 #define rdc_revid_eee() _merlin16_pmd_rde_field_byte(sa__, 0xd0fa,15,15,__ERR) 524 #define rdc_revid2() _merlin16_pmd_rde_field_byte(sa__, 0xd0fe,12,12,__ERR) 525 #define rdc_core_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd0f1,15,15,__ERR) 526 #define wrc_core_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f1,0x0001,0,wr_val) 527 #define rdc_disable_ack_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,0,15,__ERR) 528 #define wrc_disable_ack_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x8000,15,wr_val) 529 #define rdc_pmd_vcoclk16_vld_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,5,15,__ERR) 530 #define wrc_pmd_vcoclk16_vld_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0400,10,wr_val) 531 #define rdc_pmd_vcoclk16_vld_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,6,15,__ERR) 532 #define wrc_pmd_vcoclk16_vld_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0200,9,wr_val) 533 #define rdc_vcoclk16_s_comclk_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,7,15,__ERR) 534 #define wrc_vcoclk16_s_comclk_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0100,8,wr_val) 535 #define rdc_vcoclk16_s_comclk_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,8,15,__ERR) 536 #define wrc_vcoclk16_s_comclk_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0080,7,wr_val) 537 #define rdc_pmd_mdio_trans_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,10,15,__ERR) 538 #define wrc_pmd_mdio_trans_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0020,5,wr_val) 539 #define rdc_sup_rst_seq_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,11,15,__ERR) 540 #define wrc_sup_rst_seq_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0010,4,wr_val) 541 #define rdc_sup_rst_seq_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,12,15,__ERR) 542 #define wrc_sup_rst_seq_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0008,3,wr_val) 543 #define rdc_pmd_core_dp_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd0f2,14,15,__ERR) 544 #define wrc_pmd_core_dp_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0002,1,wr_val) 545 #define rdc_maskdata() _merlin16_pmd_rde_reg(sa__, 0xd0f3,__ERR) 546 #define wrc_maskdata(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f3,wr_val) 547 #define rdc_uc_active() _merlin16_pmd_rde_field_byte(sa__, 0xd0f4,0,15,__ERR) 548 #define wrc_uc_active(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f4,0x8000,15,wr_val) 549 #define rdc_afe_s_pll_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd0f4,1,15,__ERR) 550 #define wrc_afe_s_pll_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f4,0x4000,14,wr_val) 551 #define rdc_core_dp_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd0f4,2,15,__ERR) 552 #define wrc_core_dp_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f4,0x2000,13,wr_val) 553 #define rdc_maskdata_bus_assign() _merlin16_pmd_rde_field_byte(sa__, 0xd0f4,4,14,__ERR) 554 #define wrc_maskdata_bus_assign(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f4,0x0c00,10,wr_val) 555 #define rdc_heartbeat_count_1us() _merlin16_pmd_rde_field(sa__, 0xd0f4,6,6,__ERR) 556 #define wrc_heartbeat_count_1us(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd0f4,0x03ff,0,wr_val) 557 #define rdc_uc_ack_core_dp_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd0f5,14,15,__ERR) 558 #define wrc_uc_ack_core_dp_reset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f5,0x0002,1,wr_val) 559 #define rdc_uc_ack_core_cfg_done() _merlin16_pmd_rde_field_byte(sa__, 0xd0f5,15,15,__ERR) 560 #define wrc_uc_ack_core_cfg_done(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f5,0x0001,0,wr_val) 561 #define rdc_lane_reset_released() _merlin16_pmd_rde_field_byte(sa__, 0xd0f8,1,15,__ERR) 562 #define rdc_lane_reset_released_index() _merlin16_pmd_rde_field_byte(sa__, 0xd0f8,3,11,__ERR) 563 #define rdc_tx_lane_reset_released() _merlin16_pmd_rde_field_byte(sa__, 0xd0f8,0,15,__ERR) 564 #define rdc_tx_lane_reset_released_index() _merlin16_pmd_rde_field_byte(sa__, 0xd0f8,8,11,__ERR) 565 #define rdc_core_dp_reset_state() _merlin16_pmd_rde_field_byte(sa__, 0xd0f8,13,13,__ERR) 566 #define rdc_core_reg_reset_occurred() _merlin16_pmd_rde_field_byte(sa__, 0xd0f6,15,15,__ERR) 567 #define wrc_core_reg_reset_occurred(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f6,0x0001,0,wr_val) 568 #define rdc_rst_seq_dis_flt_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0f7,0,14,__ERR) 569 #define wrc_rst_seq_dis_flt_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f7,0xc000,14,wr_val) 570 #define rdc_pwrdn_seq_timer() _merlin16_pmd_rde_field_byte(sa__, 0xd0f7,4,13,__ERR) 571 #define wrc_pwrdn_seq_timer(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0e00,9,wr_val) 572 #define rdc_rst_seq_timer() _merlin16_pmd_rde_field_byte(sa__, 0xd0f7,13,13,__ERR) 573 #define wrc_rst_seq_timer(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0007,0,wr_val) 574 #define rdc_pmd_core_mode() _merlin16_pmd_rde_reg(sa__, 0xd0f9,__ERR) 575 #define rd_cdr_integ_reg() _merlin16_pmd_rde_field_signed(sa__, 0xd005,0,0,__ERR) 576 #define rd_cdr_phase_err() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd006,11,11,__ERR) 577 #define rd_cnt_bin_p1_dreg() _merlin16_pmd_rde_field_byte(sa__, 0xd007,1,9,__ERR) 578 #define rd_cnt_bin_d_dreg() _merlin16_pmd_rde_field_byte(sa__, 0xd007,9,9,__ERR) 579 #define rd_cnt_bin_m1_preg() _merlin16_pmd_rde_field_byte(sa__, 0xd008,1,9,__ERR) 580 #define rd_cnt_bin_p1_preg() _merlin16_pmd_rde_field_byte(sa__, 0xd008,9,9,__ERR) 581 #define rd_cnt_bin_d_mreg() _merlin16_pmd_rde_field_byte(sa__, 0xd009,1,9,__ERR) 582 #define rd_cnt_bin_m1_mreg() _merlin16_pmd_rde_field_byte(sa__, 0xd009,9,9,__ERR) 583 #define rd_cnt_d_minus_p1() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd00a,0,8,__ERR) 584 #define rd_cnt_d_minus_m1() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd00a,8,8,__ERR) 585 #define rd_cdr_lm_thr_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd001,5,13,__ERR) 586 #define wr_cdr_lm_thr_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0700,8,wr_val) 587 #define rd_cdr_freq_override_en() _merlin16_pmd_rde_field_byte(sa__, 0xd001,8,15,__ERR) 588 #define wr_cdr_freq_override_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0080,7,wr_val) 589 #define rd_cdr_integ_sat_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd001,9,15,__ERR) 590 #define wr_cdr_integ_sat_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0040,6,wr_val) 591 #define rd_cdr_phase_err_frz() _merlin16_pmd_rde_field_byte(sa__, 0xd001,10,15,__ERR) 592 #define wr_cdr_phase_err_frz(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0020,5,wr_val) 593 #define rd_cdr_integ_reg_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd001,11,15,__ERR) 594 #define wr_cdr_integ_reg_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0010,4,wr_val) 595 #define rd_cdr_freq_en() _merlin16_pmd_rde_field_byte(sa__, 0xd001,13,15,__ERR) 596 #define wr_cdr_freq_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0004,2,wr_val) 597 #define rd_br_pd_en() _merlin16_pmd_rde_field_byte(sa__, 0xd001,14,15,__ERR) 598 #define wr_br_pd_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0002,1,wr_val) 599 #define rd_cdr_phase_sat_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd001,15,15,__ERR) 600 #define wr_cdr_phase_sat_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd001,0x0001,0,wr_val) 601 #define rd_cdr_freq_override_val() _merlin16_pmd_rde_field_signed(sa__, 0xd002,0,1,__ERR) 602 #define wr_cdr_freq_override_val(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd002,0xfffe,1,wr_val) 603 #define rd_dfe_vga_unfreeze() _merlin16_pmd_rde_field_byte(sa__, 0xd002,15,15,__ERR) 604 #define wr_dfe_vga_unfreeze(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd002,0x0001,0,wr_val) 605 #define rd_osx2p_pherr_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd003,6,14,__ERR) 606 #define wr_osx2p_pherr_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd003,0x0300,8,wr_val) 607 #define rd_pattern_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd003,8,12,__ERR) 608 #define wr_pattern_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd003,0x00f0,4,wr_val) 609 #define rd_phase_err_offset_mult_2() _merlin16_pmd_rde_field_byte(sa__, 0xd003,14,15,__ERR) 610 #define wr_phase_err_offset_mult_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd003,0x0002,1,wr_val) 611 #define rd_cdr_zero_polarity() _merlin16_pmd_rde_field_byte(sa__, 0xd003,15,15,__ERR) 612 #define wr_cdr_zero_polarity(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd003,0x0001,0,wr_val) 613 #define rd_edge_count_refless_en() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,0,15,__ERR) 614 #define wr_edge_count_refless_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x8000,15,wr_val) 615 #define rd_trnsum_eye_closure_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,2,14,__ERR) 616 #define wr_trnsum_eye_closure_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x3000,12,wr_val) 617 #define rd_swap_lms_data() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,4,15,__ERR) 618 #define wr_swap_lms_data(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x0800,11,wr_val) 619 #define rd_swap_lms_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,5,15,__ERR) 620 #define wr_swap_lms_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x0400,10,wr_val) 621 #define rd_trnsum_prbs_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,9,14,__ERR) 622 #define wr_trnsum_prbs_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x0060,5,wr_val) 623 #define rd_trnsum_eye_close_prev_en() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,11,15,__ERR) 624 #define wr_trnsum_eye_close_prev_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x0010,4,wr_val) 625 #define rd_trnsum_pattern_match_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,12,14,__ERR) 626 #define wr_trnsum_pattern_match_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x000c,2,wr_val) 627 #define rd_trnsum_disable_sm_clear() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,14,15,__ERR) 628 #define wr_trnsum_disable_sm_clear(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x0002,1,wr_val) 629 #define rd_trnsum_clr_sc() _merlin16_pmd_rde_field_byte(sa__, 0xd00b,15,15,__ERR) 630 #define wr_trnsum_clr_sc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00b,0x0001,0,wr_val) 631 #define rd_rx_pi_manual_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd004,0,15,__ERR) 632 #define wr_rx_pi_manual_reset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd004,0x8000,15,wr_val) 633 #define rd_rx_pi_slicers_en() _merlin16_pmd_rde_field_byte(sa__, 0xd004,1,13,__ERR) 634 #define wr_rx_pi_slicers_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd004,0x7000,12,wr_val) 635 #define rd_rx_pi_manual_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd004,4,15,__ERR) 636 #define wr_rx_pi_manual_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd004,0x0800,11,wr_val) 637 #define rd_rx_pi_phase_step_dir() _merlin16_pmd_rde_field_byte(sa__, 0xd004,5,15,__ERR) 638 #define wr_rx_pi_phase_step_dir(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd004,0x0400,10,wr_val) 639 #define rd_rx_pi_manual_strobe() _merlin16_pmd_rde_field_byte(sa__, 0xd004,6,15,__ERR) 640 #define wr_rx_pi_manual_strobe(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd004,0x0200,9,wr_val) 641 #define rd_rx_pi_phase_step_cnt() _merlin16_pmd_rde_field_byte(sa__, 0xd004,9,9,__ERR) 642 #define wr_rx_pi_phase_step_cnt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd004,0x007f,0,wr_val) 643 #define rd_uc_dsc_supp_info() _merlin16_pmd_rde_field_byte(sa__, 0xd00d,0,8,__ERR) 644 #define wr_uc_dsc_supp_info(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00d,0xff00,8,wr_val) 645 #define rd_uc_dsc_ready_for_cmd() _merlin16_pmd_rde_field_byte(sa__, 0xd00d,8,15,__ERR) 646 #define wr_uc_dsc_ready_for_cmd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00d,0x0080,7,wr_val) 647 #define rd_uc_dsc_error_found() _merlin16_pmd_rde_field_byte(sa__, 0xd00d,9,15,__ERR) 648 #define wr_uc_dsc_error_found(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00d,0x0040,6,wr_val) 649 #define rd_uc_dsc_gp_uc_req() _merlin16_pmd_rde_field_byte(sa__, 0xd00d,10,10,__ERR) 650 #define wr_uc_dsc_gp_uc_req(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd00d,0x003f,0,wr_val) 651 #define rd_uc_dsc_data() _merlin16_pmd_rde_reg(sa__, 0xd00e,__ERR) 652 #define wr_uc_dsc_data(wr_val) merlin16_pmd_wr_reg(sa__, 0xd00e,wr_val) 653 #define rd_eee_mode_en() _merlin16_pmd_rde_field_byte(sa__, 0xd010,14,15,__ERR) 654 #define wr_eee_mode_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0002,1,wr_val) 655 #define rd_eee_quiet_rx_afe_pwrdwn_val() _merlin16_pmd_rde_field_byte(sa__, 0xd010,13,15,__ERR) 656 #define wr_eee_quiet_rx_afe_pwrdwn_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0004,2,wr_val) 657 #define rd_ignore_rx_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd010,12,15,__ERR) 658 #define wr_ignore_rx_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0008,3,wr_val) 659 #define rd_cl72_timer_en() _merlin16_pmd_rde_field_byte(sa__, 0xd010,11,15,__ERR) 660 #define wr_cl72_timer_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0010,4,wr_val) 661 #define rd_uc_tune_en() _merlin16_pmd_rde_field_byte(sa__, 0xd010,10,15,__ERR) 662 #define wr_uc_tune_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0020,5,wr_val) 663 #define rd_hw_tune_en() _merlin16_pmd_rde_field_byte(sa__, 0xd010,9,15,__ERR) 664 #define wr_hw_tune_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0040,6,wr_val) 665 #define rd_uc_trnsum_en() _merlin16_pmd_rde_field_byte(sa__, 0xd010,8,15,__ERR) 666 #define wr_uc_trnsum_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0080,7,wr_val) 667 #define rd_eee_measure_en() _merlin16_pmd_rde_field_byte(sa__, 0xd010,7,15,__ERR) 668 #define wr_eee_measure_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0100,8,wr_val) 669 #define rd_slicer_cal_done_clear() _merlin16_pmd_rde_field_byte(sa__, 0xd010,6,15,__ERR) 670 #define wr_slicer_cal_done_clear(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0200,9,wr_val) 671 #define rd_slicer_cal_bypass() _merlin16_pmd_rde_field_byte(sa__, 0xd010,5,15,__ERR) 672 #define wr_slicer_cal_bypass(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0400,10,wr_val) 673 #define rd_uc_ack_dsc_eee_done() _merlin16_pmd_rde_field_byte(sa__, 0xd010,4,15,__ERR) 674 #define wr_uc_ack_dsc_eee_done(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x0800,11,wr_val) 675 #define rd_uc_ack_dsc_restart() _merlin16_pmd_rde_field_byte(sa__, 0xd010,2,15,__ERR) 676 #define wr_uc_ack_dsc_restart(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x2000,13,wr_val) 677 #define rd_uc_ack_dsc_config() _merlin16_pmd_rde_field_byte(sa__, 0xd010,1,15,__ERR) 678 #define wr_uc_ack_dsc_config(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x4000,14,wr_val) 679 #define rd_set_meas_incomplete() _merlin16_pmd_rde_field_byte(sa__, 0xd010,0,15,__ERR) 680 #define wr_set_meas_incomplete(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd010,0x8000,15,wr_val) 681 #define rd_rx_dsc_lock_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,15,15,__ERR) 682 #define wr_rx_dsc_lock_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0001,0,wr_val) 683 #define rd_rx_dsc_lock_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,14,15,__ERR) 684 #define wr_rx_dsc_lock_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0002,1,wr_val) 685 #define rd_dsc_clr_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,13,15,__ERR) 686 #define wr_dsc_clr_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0004,2,wr_val) 687 #define rd_dsc_clr_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,12,15,__ERR) 688 #define wr_dsc_clr_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0008,3,wr_val) 689 #define rd_trnsum_frz_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,11,15,__ERR) 690 #define wr_trnsum_frz_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0010,4,wr_val) 691 #define rd_trnsum_frz_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,10,15,__ERR) 692 #define wr_trnsum_frz_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0020,5,wr_val) 693 #define rd_timer_done_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,9,15,__ERR) 694 #define wr_timer_done_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0040,6,wr_val) 695 #define rd_timer_done_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,8,15,__ERR) 696 #define wr_timer_done_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0080,7,wr_val) 697 #define rd_freq_upd_en_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,7,15,__ERR) 698 #define wr_freq_upd_en_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0100,8,wr_val) 699 #define rd_freq_upd_en_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,6,15,__ERR) 700 #define wr_freq_upd_en_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0200,9,wr_val) 701 #define rd_cdr_frz_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,5,15,__ERR) 702 #define wr_cdr_frz_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0400,10,wr_val) 703 #define rd_cdr_frz_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,4,15,__ERR) 704 #define wr_cdr_frz_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x0800,11,wr_val) 705 #define rd_trnsum_clr_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd011,3,15,__ERR) 706 #define wr_trnsum_clr_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x1000,12,wr_val) 707 #define rd_trnsum_clr_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd011,2,15,__ERR) 708 #define wr_trnsum_clr_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd011,0x2000,13,wr_val) 709 #define rd_eee_lfsr_cnt() _merlin16_pmd_rde_field(sa__, 0xd012,3,3,__ERR) 710 #define wr_eee_lfsr_cnt(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd012,0x1fff,0,wr_val) 711 #define rd_measure_lfsr_cnt() _merlin16_pmd_rde_field(sa__, 0xd013,3,3,__ERR) 712 #define wr_measure_lfsr_cnt(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd013,0x1fff,0,wr_val) 713 #define rd_acq_cdr_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd014,11,11,__ERR) 714 #define wr_acq_cdr_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd014,0x001f,0,wr_val) 715 #define rd_cdr_settle_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd014,6,11,__ERR) 716 #define wr_cdr_settle_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd014,0x03e0,5,wr_val) 717 #define rd_hw_tune_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd014,1,11,__ERR) 718 #define wr_hw_tune_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd014,0x7c00,10,wr_val) 719 #define rd_measure_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd015,11,11,__ERR) 720 #define wr_measure_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd015,0x001f,0,wr_val) 721 #define rd_eee_acq_cdr_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd015,6,11,__ERR) 722 #define wr_eee_acq_cdr_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd015,0x03e0,5,wr_val) 723 #define rd_eee_cdr_settle_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd015,1,11,__ERR) 724 #define wr_eee_cdr_settle_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd015,0x7c00,10,wr_val) 725 #define rd_eee_hw_tune_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd016,11,11,__ERR) 726 #define wr_eee_hw_tune_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd016,0x001f,0,wr_val) 727 #define rd_eee_ana_pwr_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd016,1,11,__ERR) 728 #define wr_eee_ana_pwr_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd016,0x7c00,10,wr_val) 729 #define rd_slicer_cal_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd016,6,11,__ERR) 730 #define wr_slicer_cal_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd016,0x03e0,5,wr_val) 731 #define rd_cdr_bwsel_integ_acqcdr() _merlin16_pmd_rde_field_byte(sa__, 0xd017,12,12,__ERR) 732 #define wr_cdr_bwsel_integ_acqcdr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd017,0x000f,0,wr_val) 733 #define rd_cdr_bwsel_integ_eee_acqcdr() _merlin16_pmd_rde_field_byte(sa__, 0xd017,8,12,__ERR) 734 #define wr_cdr_bwsel_integ_eee_acqcdr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd017,0x00f0,4,wr_val) 735 #define rd_cdr_bwsel_integ_norm() _merlin16_pmd_rde_field_byte(sa__, 0xd017,4,12,__ERR) 736 #define wr_cdr_bwsel_integ_norm(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd017,0x0f00,8,wr_val) 737 #define rd_cdr_bwsel_prop_acqcdr() _merlin16_pmd_rde_field_byte(sa__, 0xd017,2,14,__ERR) 738 #define wr_cdr_bwsel_prop_acqcdr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd017,0x3000,12,wr_val) 739 #define rd_cdr_bwsel_prop_norm() _merlin16_pmd_rde_field_byte(sa__, 0xd017,0,14,__ERR) 740 #define wr_cdr_bwsel_prop_norm(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd017,0xc000,14,wr_val) 741 #define rd_phase_err_offset() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd018,12,12,__ERR) 742 #define wr_phase_err_offset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd018,0x000f,0,wr_val) 743 #define rd_eee_phase_err_offset() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd018,8,12,__ERR) 744 #define wr_eee_phase_err_offset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd018,0x00f0,4,wr_val) 745 #define rd_phase_err_offset_en() _merlin16_pmd_rde_field_byte(sa__, 0xd018,6,14,__ERR) 746 #define wr_phase_err_offset_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd018,0x0300,8,wr_val) 747 #define rd_eee_phase_err_offset_en() _merlin16_pmd_rde_field_byte(sa__, 0xd018,4,14,__ERR) 748 #define wr_eee_phase_err_offset_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd018,0x0c00,10,wr_val) 749 #define rd_cdr_bwsel_prop_eee_acqcdr() _merlin16_pmd_rde_field_byte(sa__, 0xd018,0,14,__ERR) 750 #define wr_cdr_bwsel_prop_eee_acqcdr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd018,0xc000,14,wr_val) 751 #define rd_dcoff_cal_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd019,1,11,__ERR) 752 #define wr_dcoff_cal_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd019,0x7c00,10,wr_val) 753 #define rd_rx_restart_pmd() _merlin16_pmd_rde_field_byte(sa__, 0xd019,15,15,__ERR) 754 #define wr_rx_restart_pmd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd019,0x0001,0,wr_val) 755 #define rd_rx_restart_pmd_hold() _merlin16_pmd_rde_field_byte(sa__, 0xd019,14,15,__ERR) 756 #define wr_rx_restart_pmd_hold(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd019,0x0002,1,wr_val) 757 #define rd_dsc_state_one_hot() _merlin16_pmd_rde_field(sa__, 0xd01b,4,4,__ERR) 758 #define rd_dsc_state_eee_one_hot() _merlin16_pmd_rde_field_byte(sa__, 0xd01c,9,9,__ERR) 759 #define rd_restart_pi_ext_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd01d,15,15,__ERR) 760 #define rd_restart_sigdet() _merlin16_pmd_rde_field_byte(sa__, 0xd01d,14,15,__ERR) 761 #define rd_restart_pmd_restart() _merlin16_pmd_rde_field_byte(sa__, 0xd01d,13,15,__ERR) 762 #define rd_eee_quiet_from_eee_states() _merlin16_pmd_rde_field_byte(sa__, 0xd01d,12,15,__ERR) 763 #define rd_dsc_state() _merlin16_pmd_rde_field_byte(sa__, 0xd01e,0,11,__ERR) 764 #define rd_dsc_sm_ready_for_cmd() _merlin16_pmd_rde_field_byte(sa__, 0xd01e,8,15,__ERR) 765 #define rd_cdr_lm_outoflock() _merlin16_pmd_rde_field_byte(sa__, 0xd01e,9,15,__ERR) 766 #define rd_dsc_sm_scratch() _merlin16_pmd_rde_field_byte(sa__, 0xd01e,5,13,__ERR) 767 #define rd_dsc_sm_gp_uc_req() _merlin16_pmd_rde_field_byte(sa__, 0xd01e,10,10,__ERR) 768 #define rd_eee_measure_cnt() _merlin16_pmd_rde_field(sa__, 0xd01a,0,7,__ERR) 769 #define rd_slicer_cal_done() _merlin16_pmd_rde_field_byte(sa__, 0xd01a,13,15,__ERR) 770 #define rd_meas_incomplete() _merlin16_pmd_rde_field_byte(sa__, 0xd01a,14,15,__ERR) 771 #define rd_rx_dsc_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd01a,15,15,__ERR) 772 #define rd_dfe_1_en() _merlin16_pmd_rde_field_byte(sa__, 0xd021,0,15,__ERR) 773 #define wr_dfe_1_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x8000,15,wr_val) 774 #define rd_dfe_1_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd021,1,14,__ERR) 775 #define wr_dfe_1_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x6000,13,wr_val) 776 #define rd_dfe_1_gradient_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd021,3,15,__ERR) 777 #define wr_dfe_1_gradient_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x1000,12,wr_val) 778 #define rd_dfe_1_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd021,4,14,__ERR) 779 #define wr_dfe_1_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x0c00,10,wr_val) 780 #define rd_dfe_1_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd021,6,15,__ERR) 781 #define wr_dfe_1_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x0200,9,wr_val) 782 #define rd_dfe_1_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd021,7,15,__ERR) 783 #define wr_dfe_1_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x0100,8,wr_val) 784 #define rd_dfe_1_cmn_only() _merlin16_pmd_rde_field_byte(sa__, 0xd021,14,15,__ERR) 785 #define wr_dfe_1_cmn_only(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x0002,1,wr_val) 786 #define rd_dfe_1_acc_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd021,15,15,__ERR) 787 #define wr_dfe_1_acc_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd021,0x0001,0,wr_val) 788 #define rd_dfe_2_en() _merlin16_pmd_rde_field_byte(sa__, 0xd022,0,15,__ERR) 789 #define wr_dfe_2_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x8000,15,wr_val) 790 #define rd_dfe_2_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd022,1,14,__ERR) 791 #define wr_dfe_2_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x6000,13,wr_val) 792 #define rd_dfe_2_gradient_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd022,3,15,__ERR) 793 #define wr_dfe_2_gradient_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x1000,12,wr_val) 794 #define rd_dfe_2_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd022,4,14,__ERR) 795 #define wr_dfe_2_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x0c00,10,wr_val) 796 #define rd_dfe_2_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd022,6,15,__ERR) 797 #define wr_dfe_2_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x0200,9,wr_val) 798 #define rd_dfe_2_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd022,7,15,__ERR) 799 #define wr_dfe_2_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x0100,8,wr_val) 800 #define rd_dfe_2_cmn_only() _merlin16_pmd_rde_field_byte(sa__, 0xd022,14,15,__ERR) 801 #define wr_dfe_2_cmn_only(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x0002,1,wr_val) 802 #define rd_dfe_2_acc_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd022,15,15,__ERR) 803 #define wr_dfe_2_acc_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd022,0x0001,0,wr_val) 804 #define rd_dfe_3_en() _merlin16_pmd_rde_field_byte(sa__, 0xd023,0,15,__ERR) 805 #define wr_dfe_3_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x8000,15,wr_val) 806 #define rd_dfe_3_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd023,1,14,__ERR) 807 #define wr_dfe_3_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x6000,13,wr_val) 808 #define rd_dfe_3_gradient_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd023,3,15,__ERR) 809 #define wr_dfe_3_gradient_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x1000,12,wr_val) 810 #define rd_dfe_3_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd023,4,14,__ERR) 811 #define wr_dfe_3_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x0c00,10,wr_val) 812 #define rd_dfe_3_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd023,6,15,__ERR) 813 #define wr_dfe_3_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x0200,9,wr_val) 814 #define rd_dfe_3_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd023,7,15,__ERR) 815 #define wr_dfe_3_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x0100,8,wr_val) 816 #define rd_dfe_3_acc_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd023,15,15,__ERR) 817 #define wr_dfe_3_acc_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd023,0x0001,0,wr_val) 818 #define rd_dfe_4_en() _merlin16_pmd_rde_field_byte(sa__, 0xd024,0,15,__ERR) 819 #define wr_dfe_4_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x8000,15,wr_val) 820 #define rd_dfe_4_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd024,1,14,__ERR) 821 #define wr_dfe_4_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x6000,13,wr_val) 822 #define rd_dfe_4_gradient_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd024,3,15,__ERR) 823 #define wr_dfe_4_gradient_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x1000,12,wr_val) 824 #define rd_dfe_4_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd024,4,14,__ERR) 825 #define wr_dfe_4_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x0c00,10,wr_val) 826 #define rd_dfe_4_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd024,6,15,__ERR) 827 #define wr_dfe_4_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x0200,9,wr_val) 828 #define rd_dfe_4_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd024,7,15,__ERR) 829 #define wr_dfe_4_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x0100,8,wr_val) 830 #define rd_dfe_4_acc_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd024,15,15,__ERR) 831 #define wr_dfe_4_acc_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd024,0x0001,0,wr_val) 832 #define rd_dfe_5_en() _merlin16_pmd_rde_field_byte(sa__, 0xd025,0,15,__ERR) 833 #define wr_dfe_5_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x8000,15,wr_val) 834 #define rd_dfe_5_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd025,1,14,__ERR) 835 #define wr_dfe_5_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x6000,13,wr_val) 836 #define rd_dfe_5_gradient_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd025,3,15,__ERR) 837 #define wr_dfe_5_gradient_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x1000,12,wr_val) 838 #define rd_dfe_5_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd025,4,14,__ERR) 839 #define wr_dfe_5_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x0c00,10,wr_val) 840 #define rd_dfe_5_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd025,6,15,__ERR) 841 #define wr_dfe_5_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x0200,9,wr_val) 842 #define rd_dfe_5_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd025,7,15,__ERR) 843 #define wr_dfe_5_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x0100,8,wr_val) 844 #define rd_dfe_5_acc_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd025,15,15,__ERR) 845 #define wr_dfe_5_acc_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd025,0x0001,0,wr_val) 846 #define rd_dfe_pattern_bit_en() _merlin16_pmd_rde_field_byte(sa__, 0xd026,2,10,__ERR) 847 #define wr_dfe_pattern_bit_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd026,0x3f00,8,wr_val) 848 #define rd_dfe_pattern() _merlin16_pmd_rde_field_byte(sa__, 0xd026,10,10,__ERR) 849 #define wr_dfe_pattern(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd026,0x003f,0,wr_val) 850 #define rd_dfe_acc_hys_en() _merlin16_pmd_rde_field_byte(sa__, 0xd020,0,15,__ERR) 851 #define wr_dfe_acc_hys_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x8000,15,wr_val) 852 #define rd_dfe_allow_simult() _merlin16_pmd_rde_field_byte(sa__, 0xd020,1,15,__ERR) 853 #define wr_dfe_allow_simult(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x4000,14,wr_val) 854 #define rd_dfe_update_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd020,2,15,__ERR) 855 #define wr_dfe_update_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x2000,13,wr_val) 856 #define rd_dfe_eye_closure_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd020,8,14,__ERR) 857 #define wr_dfe_eye_closure_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x00c0,6,wr_val) 858 #define rd_dfe_hw_eye_closure_en() _merlin16_pmd_rde_field_byte(sa__, 0xd020,10,15,__ERR) 859 #define wr_dfe_hw_eye_closure_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x0020,5,wr_val) 860 #define rd_dfe_leaky_lms_upd_dur() _merlin16_pmd_rde_field_byte(sa__, 0xd020,11,12,__ERR) 861 #define wr_dfe_leaky_lms_upd_dur(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x001e,1,wr_val) 862 #define rd_dfe_leaky_lms_en() _merlin16_pmd_rde_field_byte(sa__, 0xd020,15,15,__ERR) 863 #define wr_dfe_leaky_lms_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd020,0x0001,0,wr_val) 864 #define rd_hwtune_ovr_write_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02b,0,15,__ERR) 865 #define wr_hwtune_ovr_write_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02b,0x8000,15,wr_val) 866 #define rd_hwtune_ovr_write_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd02b,2,11,__ERR) 867 #define wr_hwtune_ovr_write_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02b,0x3e00,9,wr_val) 868 #define rd_hwtune_ovr_write_val() _merlin16_pmd_rde_field(sa__, 0xd02b,7,7,__ERR) 869 #define wr_hwtune_ovr_write_val(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd02b,0x01ff,0,wr_val) 870 #define rd_vga_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,0,15,__ERR) 871 #define wr_vga_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x8000,15,wr_val) 872 #define rd_vga_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,1,14,__ERR) 873 #define wr_vga_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x6000,13,wr_val) 874 #define rd_vga_p1_gradient_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,3,15,__ERR) 875 #define wr_vga_p1_gradient_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x1000,12,wr_val) 876 #define rd_vga_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,4,14,__ERR) 877 #define wr_vga_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x0c00,10,wr_val) 878 #define rd_vga_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,6,15,__ERR) 879 #define wr_vga_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x0200,9,wr_val) 880 #define rd_vga_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,7,15,__ERR) 881 #define wr_vga_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x0100,8,wr_val) 882 #define rd_vga_update_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,8,14,__ERR) 883 #define wr_vga_update_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x00c0,6,wr_val) 884 #define rd_vga_affected_by_dfe1() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,11,15,__ERR) 885 #define wr_vga_affected_by_dfe1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x0010,4,wr_val) 886 #define rd_vga_update_style() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,12,14,__ERR) 887 #define wr_vga_update_style(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x000c,2,wr_val) 888 #define rd_vga_acc_hys_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,14,15,__ERR) 889 #define wr_vga_acc_hys_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x0002,1,wr_val) 890 #define rd_vga_p1_acc_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd02c,15,15,__ERR) 891 #define wr_vga_p1_acc_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02c,0x0001,0,wr_val) 892 #define rd_p1_eyediag_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02d,0,15,__ERR) 893 #define wr_p1_eyediag_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02d,0x8000,15,wr_val) 894 #define rd_vga_pattern_bit_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02d,8,12,__ERR) 895 #define wr_vga_pattern_bit_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02d,0x00f0,4,wr_val) 896 #define rd_vga_pattern() _merlin16_pmd_rde_field_byte(sa__, 0xd02d,12,12,__ERR) 897 #define wr_vga_pattern(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02d,0x000f,0,wr_val) 898 #define rd_p1_hwtune_max() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd02e,0,10,__ERR) 899 #define wr_p1_hwtune_max(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02e,0xfc00,10,wr_val) 900 #define rd_p1_off_3levelq_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02e,7,15,__ERR) 901 #define wr_p1_off_3levelq_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02e,0x0100,8,wr_val) 902 #define rd_p1_offset_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02e,8,15,__ERR) 903 #define wr_p1_offset_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02e,0x0080,7,wr_val) 904 #define rd_p1_offset() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd02e,9,9,__ERR) 905 #define wr_p1_offset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02e,0x007f,0,wr_val) 906 #define rd_p1_hwtune_min() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd027,0,10,__ERR) 907 #define wr_p1_hwtune_min(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd027,0xfc00,10,wr_val) 908 #define rd_vga_op_short_norm() _merlin16_pmd_rde_field_byte(sa__, 0xd027,8,15,__ERR) 909 #define wr_vga_op_short_norm(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd027,0x0080,7,wr_val) 910 #define rd_vga_op_short_offcal() _merlin16_pmd_rde_field_byte(sa__, 0xd027,9,15,__ERR) 911 #define wr_vga_op_short_offcal(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd027,0x0040,6,wr_val) 912 #define rd_vga_hwtune_min() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd027,10,10,__ERR) 913 #define wr_vga_hwtune_min(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd027,0x003f,0,wr_val) 914 #define rd_hw_slicer_offset_grad_inv() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,8,15,__ERR) 915 #define wr_hw_slicer_offset_grad_inv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x0080,7,wr_val) 916 #define rd_hw_slicer_offset_inv_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,9,15,__ERR) 917 #define wr_hw_slicer_offset_inv_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x0040,6,wr_val) 918 #define rd_hw_slicer_offset_inv_m1() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,10,15,__ERR) 919 #define wr_hw_slicer_offset_inv_m1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x0020,5,wr_val) 920 #define rd_hw_slicer_offset_inv_data() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,11,15,__ERR) 921 #define wr_hw_slicer_offset_inv_data(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x0010,4,wr_val) 922 #define rd_hw_slicer_offset_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,12,14,__ERR) 923 #define wr_hw_slicer_offset_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x000c,2,wr_val) 924 #define rd_hw_slicer_offset_hys_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,14,15,__ERR) 925 #define wr_hw_slicer_offset_hys_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x0002,1,wr_val) 926 #define rd_hw_slicer_offset_en() _merlin16_pmd_rde_field_byte(sa__, 0xd02a,15,15,__ERR) 927 #define wr_hw_slicer_offset_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd02a,0x0001,0,wr_val) 928 #define rd_dc_offset_pattern_bit_en() _merlin16_pmd_rde_field_byte(sa__, 0xd029,0,12,__ERR) 929 #define wr_dc_offset_pattern_bit_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0xf000,12,wr_val) 930 #define rd_dc_offset_pattern() _merlin16_pmd_rde_field_byte(sa__, 0xd029,4,12,__ERR) 931 #define wr_dc_offset_pattern(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x0f00,8,wr_val) 932 #define rd_hw_dc_offset_grad_inv() _merlin16_pmd_rde_field_byte(sa__, 0xd029,9,15,__ERR) 933 #define wr_hw_dc_offset_grad_inv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x0040,6,wr_val) 934 #define rd_dc_offset_pattern_inv_en() _merlin16_pmd_rde_field_byte(sa__, 0xd029,10,15,__ERR) 935 #define wr_dc_offset_pattern_inv_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x0020,5,wr_val) 936 #define rd_dc_offset_inv() _merlin16_pmd_rde_field_byte(sa__, 0xd029,11,15,__ERR) 937 #define wr_dc_offset_inv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x0010,4,wr_val) 938 #define rd_hw_dc_offset_err_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd029,12,14,__ERR) 939 #define wr_hw_dc_offset_err_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x000c,2,wr_val) 940 #define rd_hw_dc_offset_hys_en() _merlin16_pmd_rde_field_byte(sa__, 0xd029,14,15,__ERR) 941 #define wr_hw_dc_offset_hys_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x0002,1,wr_val) 942 #define rd_dc_offset_en() _merlin16_pmd_rde_field_byte(sa__, 0xd029,15,15,__ERR) 943 #define wr_dc_offset_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd029,0x0001,0,wr_val) 944 #define rd_trnsum_en() _merlin16_pmd_rde_field_byte(sa__, 0xd030,0,15,__ERR) 945 #define wr_trnsum_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x8000,15,wr_val) 946 #define rd_trnsum_err_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd030,1,13,__ERR) 947 #define wr_trnsum_err_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x7000,12,wr_val) 948 #define rd_trnsum_random_tapsel_disable() _merlin16_pmd_rde_field_byte(sa__, 0xd030,4,15,__ERR) 949 #define wr_trnsum_random_tapsel_disable(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x0800,11,wr_val) 950 #define rd_trnsum_inv_pattern_en() _merlin16_pmd_rde_field_byte(sa__, 0xd030,5,15,__ERR) 951 #define wr_trnsum_inv_pattern_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x0400,10,wr_val) 952 #define rd_trnsum_pattern_full_check_off() _merlin16_pmd_rde_field_byte(sa__, 0xd030,6,15,__ERR) 953 #define wr_trnsum_pattern_full_check_off(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x0200,9,wr_val) 954 #define rd_trnsum_edge_pattern_en() _merlin16_pmd_rde_field_byte(sa__, 0xd030,7,15,__ERR) 955 #define wr_trnsum_edge_pattern_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x0100,8,wr_val) 956 #define rd_trnsum_gain() _merlin16_pmd_rde_field_byte(sa__, 0xd030,8,14,__ERR) 957 #define wr_trnsum_gain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x00c0,6,wr_val) 958 #define rd_trnsum_eye_closure_en() _merlin16_pmd_rde_field_byte(sa__, 0xd030,10,15,__ERR) 959 #define wr_trnsum_eye_closure_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x0020,5,wr_val) 960 #define rd_cdr_qphase_mult_en() _merlin16_pmd_rde_field_byte(sa__, 0xd030,11,15,__ERR) 961 #define wr_cdr_qphase_mult_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x0010,4,wr_val) 962 #define rd_trnsum_tap_range_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd030,12,14,__ERR) 963 #define wr_trnsum_tap_range_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd030,0x000c,2,wr_val) 964 #define rd_trnsum_pattern() _merlin16_pmd_rde_field_byte(sa__, 0xd031,0,8,__ERR) 965 #define wr_trnsum_pattern(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd031,0xff00,8,wr_val) 966 #define rd_trnsum_pattern_bit_en() _merlin16_pmd_rde_field_byte(sa__, 0xd031,8,8,__ERR) 967 #define wr_trnsum_pattern_bit_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd031,0x00ff,0,wr_val) 968 #define rd_trnsum_tap_en() _merlin16_pmd_rde_field_byte(sa__, 0xd032,0,8,__ERR) 969 #define wr_trnsum_tap_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd032,0xff00,8,wr_val) 970 #define rd_trnsum_tap_sign() _merlin16_pmd_rde_field_byte(sa__, 0xd032,8,8,__ERR) 971 #define wr_trnsum_tap_sign(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd032,0x00ff,0,wr_val) 972 #define rd_tdr_cycle_bin() _merlin16_pmd_rde_field_byte(sa__, 0xd033,0,12,__ERR) 973 #define wr_tdr_cycle_bin(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd033,0xf000,12,wr_val) 974 #define rd_tdr_cycle_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd033,4,12,__ERR) 975 #define wr_tdr_cycle_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd033,0x0f00,8,wr_val) 976 #define rd_tdr_trnsum_en() _merlin16_pmd_rde_field_byte(sa__, 0xd033,8,15,__ERR) 977 #define wr_tdr_trnsum_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd033,0x0080,7,wr_val) 978 #define rd_tdr_bit_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd033,9,11,__ERR) 979 #define wr_tdr_bit_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd033,0x007c,2,wr_val) 980 #define rd_trnsum_unsigned_flip() _merlin16_pmd_rde_field_byte(sa__, 0xd033,14,15,__ERR) 981 #define wr_trnsum_unsigned_flip(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd033,0x0002,1,wr_val) 982 #define rd_trnsum_unsigned_corr() _merlin16_pmd_rde_field_byte(sa__, 0xd033,15,15,__ERR) 983 #define wr_trnsum_unsigned_corr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd033,0x0001,0,wr_val) 984 #define rd_trnsum_e_high() _merlin16_pmd_rde_field_signed(sa__, 0xd034,0,0,__ERR) 985 #define rd_trnsum_e_low() _merlin16_pmd_rde_field_byte(sa__, 0xd035,8,8,__ERR) 986 #define rd_trnsum_o_high() _merlin16_pmd_rde_field_signed(sa__, 0xd036,0,0,__ERR) 987 #define rd_trnsum_o_low() _merlin16_pmd_rde_field_byte(sa__, 0xd037,8,8,__ERR) 988 #define rd_trnsum_high() _merlin16_pmd_rde_field_signed(sa__, 0xd038,0,0,__ERR) 989 #define rd_trnsum_low() _merlin16_pmd_rde_field(sa__, 0xd039,6,6,__ERR) 990 #define rd_p1_wants_to_go_high() _merlin16_pmd_rde_field_byte(sa__, 0xd03a,0,15,__ERR) 991 #define rd_p1_wants_to_go_low() _merlin16_pmd_rde_field_byte(sa__, 0xd03a,1,15,__ERR) 992 #define rd_p1_eyediag_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd03a,2,10,__ERR) 993 #define rd_vga_wants_to_go_low() _merlin16_pmd_rde_field_byte(sa__, 0xd03a,9,15,__ERR) 994 #define rd_vga_bin() _merlin16_pmd_rde_field_byte(sa__, 0xd03a,10,10,__ERR) 995 #define rd_dfe_1_wants_negative() _merlin16_pmd_rde_field_byte(sa__, 0xd03b,0,15,__ERR) 996 #define rd_dfe_1_e() _merlin16_pmd_rde_field_byte(sa__, 0xd03b,2,13,__ERR) 997 #define rd_dfe_1_o() _merlin16_pmd_rde_field_byte(sa__, 0xd03b,5,13,__ERR) 998 #define rd_dfe_1_cmn() _merlin16_pmd_rde_field_byte(sa__, 0xd03b,10,10,__ERR) 999 #define rd_dfe_2_e() _merlin16_pmd_rde_field_byte(sa__, 0xd03c,2,13,__ERR) 1000 #define rd_dfe_2_o() _merlin16_pmd_rde_field_byte(sa__, 0xd03c,5,13,__ERR) 1001 #define rd_dfe_2_se() _merlin16_pmd_rde_field_byte(sa__, 0xd03c,9,15,__ERR) 1002 #define rd_dfe_2_so() _merlin16_pmd_rde_field_byte(sa__, 0xd03c,10,15,__ERR) 1003 #define rd_dfe_2_cmn() _merlin16_pmd_rde_field_byte(sa__, 0xd03c,11,11,__ERR) 1004 #define rd_dfe_5_cmn() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd03d,0,11,__ERR) 1005 #define rd_dfe_4_cmn() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd03d,5,11,__ERR) 1006 #define rd_dfe_3_cmn() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd03d,10,10,__ERR) 1007 #define rd_vga3_ctrl_bin() _merlin16_pmd_rde_field_byte(sa__, 0xd03e,4,12,__ERR) 1008 #define rd_vga2_ctrl_bin() _merlin16_pmd_rde_field_byte(sa__, 0xd03e,8,12,__ERR) 1009 #define rd_vga1_ctrl_bin() _merlin16_pmd_rde_field_byte(sa__, 0xd03e,12,12,__ERR) 1010 #define rd_pf_hiz() _merlin16_pmd_rde_field_byte(sa__, 0xd040,8,15,__ERR) 1011 #define wr_pf_hiz(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0080,7,wr_val) 1012 #define rd_m1_thresh_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd040,9,14,__ERR) 1013 #define wr_m1_thresh_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0060,5,wr_val) 1014 #define rd_m1_thresh_zero() _merlin16_pmd_rde_field_byte(sa__, 0xd040,11,15,__ERR) 1015 #define wr_m1_thresh_zero(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0010,4,wr_val) 1016 #define rd_p1_thresh_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd040,12,15,__ERR) 1017 #define wr_p1_thresh_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0008,3,wr_val) 1018 #define rd_en_hgain() _merlin16_pmd_rde_field_byte(sa__, 0xd040,13,15,__ERR) 1019 #define wr_en_hgain(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0004,2,wr_val) 1020 #define rd_offset_pd() _merlin16_pmd_rde_field_byte(sa__, 0xd040,14,15,__ERR) 1021 #define wr_offset_pd(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0002,1,wr_val) 1022 #define rd_pd_ch_p1() _merlin16_pmd_rde_field_byte(sa__, 0xd040,15,15,__ERR) 1023 #define wr_pd_ch_p1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd040,0x0001,0,wr_val) 1024 #define rd_pf_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd041,12,12,__ERR) 1025 #define wr_pf_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd041,0x000f,0,wr_val) 1026 #define rd_pf2_lowp_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd042,13,13,__ERR) 1027 #define wr_pf2_lowp_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd042,0x0007,0,wr_val) 1028 #define rd_data_offset_odd_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd141,10,10,__ERR) 1029 #define rd_data_offset_evn_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd142,10,10,__ERR) 1030 #define rd_p1_offset_odd_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd143,10,10,__ERR) 1031 #define rd_p1_offset_evn_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd144,10,10,__ERR) 1032 #define rd_m1_offset_odd_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd145,10,10,__ERR) 1033 #define rd_m1_offset_evn_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd146,10,10,__ERR) 1034 #define rd_dc_offset_bin() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd147,9,9,__ERR) 1035 #define rdc_mdio_blk_addr() _merlin16_pmd_rde_field(sa__, 0xffdf,1,5,__ERR) 1036 #define wrc_mdio_blk_addr(wr_val) merlin16_pmd_mwr_reg(sa__, 0xffdf,0x7ff0,4,wr_val) 1037 #define rdc_mdio_function() _merlin16_pmd_rde_field_byte(sa__, 0x000d,0,14,__ERR) 1038 #define wrc_mdio_function(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0x000d,0xc000,14,wr_val) 1039 #define rdc_mdio_devad() _merlin16_pmd_rde_field_byte(sa__, 0x000d,11,11,__ERR) 1040 #define wrc_mdio_devad(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0x000d,0x001f,0,wr_val) 1041 #define rdc_mdio_addr_data() _merlin16_pmd_rde_reg(sa__, 0x000e,__ERR) 1042 #define wrc_mdio_addr_data(wr_val) merlin16_pmd_wr_reg(sa__, 0x000e,wr_val) 1043 #define rdc_mdio_drv_comclk() _merlin16_pmd_rde_field_byte(sa__, 0xffdc,0,15,__ERR) 1044 #define wrc_mdio_drv_comclk(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdc,0x8000,15,wr_val) 1045 #define rdc_mdio_brcst_port_addr() _merlin16_pmd_rde_field_byte(sa__, 0xffdc,11,11,__ERR) 1046 #define wrc_mdio_brcst_port_addr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdc,0x001f,0,wr_val) 1047 #define rdc_mdio_multi_prts_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,0,15,__ERR) 1048 #define wrc_mdio_multi_prts_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x8000,15,wr_val) 1049 #define rdc_mdio_multi_mmds_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,1,15,__ERR) 1050 #define wrc_mdio_multi_mmds_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x4000,14,wr_val) 1051 #define rdc_mdio_dev_pcs_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,9,15,__ERR) 1052 #define wrc_mdio_dev_pcs_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x0040,6,wr_val) 1053 #define rdc_mdio_dev_dte_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,10,15,__ERR) 1054 #define wrc_mdio_dev_dte_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x0020,5,wr_val) 1055 #define rdc_mdio_dev_phy_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,11,15,__ERR) 1056 #define wrc_mdio_dev_phy_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x0010,4,wr_val) 1057 #define rdc_mdio_dev_an_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,12,15,__ERR) 1058 #define wrc_mdio_dev_an_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x0008,3,wr_val) 1059 #define rdc_mdio_dev_pmd_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,13,15,__ERR) 1060 #define wrc_mdio_dev_pmd_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x0004,2,wr_val) 1061 #define rdc_mdio_dev_cl22_en() _merlin16_pmd_rde_field_byte(sa__, 0xffdd,15,15,__ERR) 1062 #define wrc_mdio_dev_cl22_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xffdd,0x0001,0,wr_val) 1063 #define rdc_mdio_aer() _merlin16_pmd_rde_reg(sa__, 0xffde,__ERR) 1064 #define wrc_mdio_aer(wr_val) merlin16_pmd_wr_reg(sa__, 0xffde,wr_val) 1065 #define rdc_micro_core_clk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd200,14,15,__ERR) 1066 #define wrc_micro_core_clk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd200,0x0002,1,wr_val) 1067 #define rdc_micro_master_clk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd200,15,15,__ERR) 1068 #define wrc_micro_master_clk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd200,0x0001,0,wr_val) 1069 #define rdc_micro_pram_if_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd201,12,15,__ERR) 1070 #define wrc_micro_pram_if_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd201,0x0008,3,wr_val) 1071 #define rdc_micro_core_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd201,14,15,__ERR) 1072 #define wrc_micro_core_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd201,0x0002,1,wr_val) 1073 #define rdc_micro_master_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd201,15,15,__ERR) 1074 #define wrc_micro_master_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd201,0x0001,0,wr_val) 1075 #define rdc_micro_autoinc_rdaddr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd202,2,15,__ERR) 1076 #define wrc_micro_autoinc_rdaddr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd202,0x2000,13,wr_val) 1077 #define rdc_micro_autoinc_wraddr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd202,3,15,__ERR) 1078 #define wrc_micro_autoinc_wraddr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd202,0x1000,12,wr_val) 1079 #define rdc_micro_ra_init() _merlin16_pmd_rde_field_byte(sa__, 0xd202,6,14,__ERR) 1080 #define wrc_micro_ra_init(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd202,0x0300,8,wr_val) 1081 #define rdc_micro_ra_rddatasize() _merlin16_pmd_rde_field_byte(sa__, 0xd202,10,14,__ERR) 1082 #define wrc_micro_ra_rddatasize(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd202,0x0030,4,wr_val) 1083 #define rdc_micro_ra_wrdatasize() _merlin16_pmd_rde_field_byte(sa__, 0xd202,14,14,__ERR) 1084 #define wrc_micro_ra_wrdatasize(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd202,0x0003,0,wr_val) 1085 #define rdc_micro_ra_initdone() _merlin16_pmd_rde_field_byte(sa__, 0xd203,15,15,__ERR) 1086 #define rdc_micro_ra_wraddr_lsw() _merlin16_pmd_rde_reg(sa__, 0xd204,__ERR) 1087 #define wrc_micro_ra_wraddr_lsw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd204,wr_val) 1088 #define rdc_micro_ra_wraddr_msw() _merlin16_pmd_rde_reg(sa__, 0xd205,__ERR) 1089 #define wrc_micro_ra_wraddr_msw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd205,wr_val) 1090 #define rdc_micro_ra_wrdata_lsw() _merlin16_pmd_rde_reg(sa__, 0xd206,__ERR) 1091 #define wrc_micro_ra_wrdata_lsw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd206,wr_val) 1092 #define rdc_micro_ra_wrdata_msw() _merlin16_pmd_rde_reg(sa__, 0xd207,__ERR) 1093 #define wrc_micro_ra_wrdata_msw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd207,wr_val) 1094 #define rdc_micro_ra_rdaddr_lsw() _merlin16_pmd_rde_reg(sa__, 0xd208,__ERR) 1095 #define wrc_micro_ra_rdaddr_lsw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd208,wr_val) 1096 #define rdc_micro_ra_rdaddr_msw() _merlin16_pmd_rde_reg(sa__, 0xd209,__ERR) 1097 #define wrc_micro_ra_rdaddr_msw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd209,wr_val) 1098 #define rdc_micro_ra_rddata_lsw() _merlin16_pmd_rde_reg(sa__, 0xd20a,__ERR) 1099 #define rdc_micro_ra_rddata_msw() _merlin16_pmd_rde_reg(sa__, 0xd20b,__ERR) 1100 #define rdc_micro_pramif_en() _merlin16_pmd_rde_field_byte(sa__, 0xd20c,15,15,__ERR) 1101 #define wrc_micro_pramif_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd20c,0x0001,0,wr_val) 1102 #define rdc_micro_pramif_ahb_wraddr_lsw() _merlin16_pmd_rde_field(sa__, 0xd20d,0,2,__ERR) 1103 #define wrc_micro_pramif_ahb_wraddr_lsw(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd20d,0xfffc,2,wr_val) 1104 #define rdc_micro_pramif_ahb_wraddr_msw() _merlin16_pmd_rde_reg(sa__, 0xd20e,__ERR) 1105 #define wrc_micro_pramif_ahb_wraddr_msw(wr_val) merlin16_pmd_wr_reg(sa__, 0xd20e,wr_val) 1106 #define rdc_micro_pvt_tempdata_rmi() _merlin16_pmd_rde_field(sa__, 0xd210,6,6,__ERR) 1107 #define rdc_micro_rmi_to_micro_mbox0() _merlin16_pmd_rde_reg(sa__, 0xd211,__ERR) 1108 #define wrc_micro_rmi_to_micro_mbox0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd211,wr_val) 1109 #define rdc_micro_rmi_to_micro_mbox1() _merlin16_pmd_rde_reg(sa__, 0xd212,__ERR) 1110 #define wrc_micro_rmi_to_micro_mbox1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd212,wr_val) 1111 #define rdc_micro_to_rmi_mbox0() _merlin16_pmd_rde_reg(sa__, 0xd213,__ERR) 1112 #define rdc_micro_to_rmi_mbox1() _merlin16_pmd_rde_reg(sa__, 0xd214,__ERR) 1113 #define rdc_micro_gen_intr_rmi_mbox1wr() _merlin16_pmd_rde_field_byte(sa__, 0xd215,13,15,__ERR) 1114 #define wrc_micro_gen_intr_rmi_mbox1wr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd215,0x0004,2,wr_val) 1115 #define rdc_micro_gen_intr_rmi_mbox0wr() _merlin16_pmd_rde_field_byte(sa__, 0xd215,14,15,__ERR) 1116 #define wrc_micro_gen_intr_rmi_mbox0wr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd215,0x0002,1,wr_val) 1117 #define rdc_micro_rmi_mbox_send_msgin() _merlin16_pmd_rde_field_byte(sa__, 0xd215,15,15,__ERR) 1118 #define wrc_micro_rmi_mbox_send_msgin(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd215,0x0001,0,wr_val) 1119 #define rdc_micro_pmi_hp_ext_ack_timeout_dis() _merlin16_pmd_rde_field_byte(sa__, 0xd216,11,15,__ERR) 1120 #define wrc_micro_pmi_hp_ext_ack_timeout_dis(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd216,0x0010,4,wr_val) 1121 #define rdc_micro_pmi_hp_ack_timeout_dis() _merlin16_pmd_rde_field_byte(sa__, 0xd216,12,15,__ERR) 1122 #define wrc_micro_pmi_hp_ack_timeout_dis(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd216,0x0008,3,wr_val) 1123 #define rdc_micro_sw_pmi_hp_ext_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd216,13,15,__ERR) 1124 #define wrc_micro_sw_pmi_hp_ext_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd216,0x0004,2,wr_val) 1125 #define rdc_micro_sw_pmi_hp_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd216,14,15,__ERR) 1126 #define wrc_micro_sw_pmi_hp_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd216,0x0002,1,wr_val) 1127 #define rdc_micro_m0_hresp_en() _merlin16_pmd_rde_field_byte(sa__, 0xd216,15,15,__ERR) 1128 #define wrc_micro_m0_hresp_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd216,0x0001,0,wr_val) 1129 #define rdc_micro_pr_default_slave_error() _merlin16_pmd_rde_field_byte(sa__, 0xd217,13,15,__ERR) 1130 #define rdc_micro_rmi_default_slave_error() _merlin16_pmd_rde_field_byte(sa__, 0xd217,14,15,__ERR) 1131 #define rdc_micro_m0_default_slave_error() _merlin16_pmd_rde_field_byte(sa__, 0xd217,15,15,__ERR) 1132 #define rdc_micro_ra_autoinc_nxt_wraddr_lsw() _merlin16_pmd_rde_reg(sa__, 0xd218,__ERR) 1133 #define rdc_micro_ra_autoinc_nxt_rdaddr_lsw() _merlin16_pmd_rde_reg(sa__, 0xd219,__ERR) 1134 #define rdc_micro_pr_autoinc_nxt_wraddr_lsw() _merlin16_pmd_rde_reg(sa__, 0xd21a,__ERR) 1135 #define rdc_micro_pvt_tempdata_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd21b,3,15,__ERR) 1136 #define wrc_micro_pvt_tempdata_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd21b,0x1000,12,wr_val) 1137 #define rdc_micro_pvt_tempdata_frcval() _merlin16_pmd_rde_field(sa__, 0xd21b,6,6,__ERR) 1138 #define wrc_micro_pvt_tempdata_frcval(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd21b,0x03ff,0,wr_val) 1139 #define rdc_micro_ecc_corrupt() _merlin16_pmd_rde_field_byte(sa__, 0xd220,10,14,__ERR) 1140 #define wrc_micro_ecc_corrupt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd220,0x0030,4,wr_val) 1141 #define rdc_micro_ecc_frc_disable() _merlin16_pmd_rde_field_byte(sa__, 0xd220,14,15,__ERR) 1142 #define wrc_micro_ecc_frc_disable(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd220,0x0002,1,wr_val) 1143 #define rdc_micro_eccg_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd220,15,15,__ERR) 1144 #define wrc_micro_eccg_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd220,0x0001,0,wr_val) 1145 #define rdc_micro_ra_ecc_wrdata() _merlin16_pmd_rde_field_byte(sa__, 0xd221,9,9,__ERR) 1146 #define wrc_micro_ra_ecc_wrdata(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd221,0x007f,0,wr_val) 1147 #define rdc_micro_code_ram_ecc_address() _merlin16_pmd_rde_field(sa__, 0xd222,1,1,__ERR) 1148 #define rdc_micro_ra_ecc_rddata() _merlin16_pmd_rde_field_byte(sa__, 0xd223,9,9,__ERR) 1149 #define rdc_micro_code_ram_tm() _merlin16_pmd_rde_field_byte(sa__, 0xd224,9,9,__ERR) 1150 #define wrc_micro_code_ram_tm(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd224,0x007f,0,wr_val) 1151 #define rdc_micro_ignore_m0_code_writes() _merlin16_pmd_rde_field_byte(sa__, 0xd225,0,15,__ERR) 1152 #define wrc_micro_ignore_m0_code_writes(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd225,0x8000,15,wr_val) 1153 #define rdc_micro_ramclk_noninv() _merlin16_pmd_rde_field_byte(sa__, 0xd225,1,15,__ERR) 1154 #define wrc_micro_ramclk_noninv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd225,0x4000,14,wr_val) 1155 #define rdc_micro_dr_size() _merlin16_pmd_rde_field_byte(sa__, 0xd225,2,10,__ERR) 1156 #define wrc_micro_dr_size(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd225,0x3f00,8,wr_val) 1157 #define rdc_micro_protect_fwcode() _merlin16_pmd_rde_field_byte(sa__, 0xd225,14,15,__ERR) 1158 #define wrc_micro_protect_fwcode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd225,0x0002,1,wr_val) 1159 #define rdc_micro_dr_looktab_en() _merlin16_pmd_rde_field_byte(sa__, 0xd225,15,15,__ERR) 1160 #define wrc_micro_dr_looktab_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd225,0x0001,0,wr_val) 1161 #define rdc_micro_rmi_m0_systemresetreq_status() _merlin16_pmd_rde_field_byte(sa__, 0xd227,6,15,__ERR) 1162 #define rdc_micro_rmi_m0_lockup_status() _merlin16_pmd_rde_field_byte(sa__, 0xd227,7,15,__ERR) 1163 #define rdc_micro_rmi_ecc_multirow_err_status() _merlin16_pmd_rde_field_byte(sa__, 0xd227,9,15,__ERR) 1164 #define rdc_micro_rmi_ecc_uncorr_err_status() _merlin16_pmd_rde_field_byte(sa__, 0xd227,10,15,__ERR) 1165 #define rdc_micro_rmi_ecc_corr_err_status() _merlin16_pmd_rde_field_byte(sa__, 0xd227,11,15,__ERR) 1166 #define rdc_micro_rmi_mbox_msgout_status() _merlin16_pmd_rde_field_byte(sa__, 0xd227,15,15,__ERR) 1167 #define rdc_micro_rmi_m0_systemresetreq_intr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd226,6,15,__ERR) 1168 #define wrc_micro_rmi_m0_systemresetreq_intr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd226,0x0200,9,wr_val) 1169 #define rdc_micro_rmi_m0_lockup_intr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd226,7,15,__ERR) 1170 #define wrc_micro_rmi_m0_lockup_intr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd226,0x0100,8,wr_val) 1171 #define rdc_micro_rmi_ecc_multirow_err_intr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd226,9,15,__ERR) 1172 #define wrc_micro_rmi_ecc_multirow_err_intr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd226,0x0040,6,wr_val) 1173 #define rdc_micro_rmi_ecc_uncorr_err_intr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd226,10,15,__ERR) 1174 #define wrc_micro_rmi_ecc_uncorr_err_intr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd226,0x0020,5,wr_val) 1175 #define rdc_micro_rmi_ecc_corr_err_intr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd226,11,15,__ERR) 1176 #define wrc_micro_rmi_ecc_corr_err_intr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd226,0x0010,4,wr_val) 1177 #define rdc_micro_rmi_mbox_msgout_intr_en() _merlin16_pmd_rde_field_byte(sa__, 0xd226,15,15,__ERR) 1178 #define wrc_micro_rmi_mbox_msgout_intr_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd226,0x0001,0,wr_val) 1179 #define rdc_micro_pmi_hp_ext_fast_bktobk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd228,5,15,__ERR) 1180 #define wrc_micro_pmi_hp_ext_fast_bktobk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd228,0x0400,10,wr_val) 1181 #define rdc_micro_pmi_hp_ext_fast_dual_meta_ff_en() _merlin16_pmd_rde_field_byte(sa__, 0xd228,6,15,__ERR) 1182 #define wrc_micro_pmi_hp_ext_fast_dual_meta_ff_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd228,0x0200,9,wr_val) 1183 #define rdc_micro_pmi_hp_ext_fast_read_en() _merlin16_pmd_rde_field_byte(sa__, 0xd228,7,15,__ERR) 1184 #define wrc_micro_pmi_hp_ext_fast_read_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd228,0x0100,8,wr_val) 1185 #define rdc_micro_pmi_hp_fast_bktobk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd228,13,15,__ERR) 1186 #define wrc_micro_pmi_hp_fast_bktobk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd228,0x0004,2,wr_val) 1187 #define rdc_micro_pmi_hp_fast_dual_meta_ff_en() _merlin16_pmd_rde_field_byte(sa__, 0xd228,14,15,__ERR) 1188 #define wrc_micro_pmi_hp_fast_dual_meta_ff_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd228,0x0002,1,wr_val) 1189 #define rdc_micro_pmi_hp_fast_read_en() _merlin16_pmd_rde_field_byte(sa__, 0xd228,15,15,__ERR) 1190 #define wrc_micro_pmi_hp_fast_read_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd228,0x0001,0,wr_val) 1191 #define rdc_micro_silicon_debug_status_mux_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd229,14,14,__ERR) 1192 #define wrc_micro_silicon_debug_status_mux_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd229,0x0003,0,wr_val) 1193 #define rdc_micro_silicon_debug_status_muxed_data() _merlin16_pmd_rde_reg(sa__, 0xd22a,__ERR) 1194 #define rdc_patt_gen_seq_0() _merlin16_pmd_rde_reg(sa__, 0xd100,__ERR) 1195 #define wrc_patt_gen_seq_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd100,wr_val) 1196 #define rdc_patt_gen_seq_1() _merlin16_pmd_rde_reg(sa__, 0xd101,__ERR) 1197 #define wrc_patt_gen_seq_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd101,wr_val) 1198 #define rdc_patt_gen_seq_2() _merlin16_pmd_rde_reg(sa__, 0xd102,__ERR) 1199 #define wrc_patt_gen_seq_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd102,wr_val) 1200 #define rdc_patt_gen_seq_3() _merlin16_pmd_rde_reg(sa__, 0xd103,__ERR) 1201 #define wrc_patt_gen_seq_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd103,wr_val) 1202 #define rdc_patt_gen_seq_4() _merlin16_pmd_rde_reg(sa__, 0xd104,__ERR) 1203 #define wrc_patt_gen_seq_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd104,wr_val) 1204 #define rdc_patt_gen_seq_5() _merlin16_pmd_rde_reg(sa__, 0xd105,__ERR) 1205 #define wrc_patt_gen_seq_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd105,wr_val) 1206 #define rdc_patt_gen_seq_6() _merlin16_pmd_rde_reg(sa__, 0xd106,__ERR) 1207 #define wrc_patt_gen_seq_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd106,wr_val) 1208 #define rdc_patt_gen_seq_7() _merlin16_pmd_rde_reg(sa__, 0xd107,__ERR) 1209 #define wrc_patt_gen_seq_7(wr_val) merlin16_pmd_wr_reg(sa__, 0xd107,wr_val) 1210 #define rdc_patt_gen_seq_8() _merlin16_pmd_rde_reg(sa__, 0xd108,__ERR) 1211 #define wrc_patt_gen_seq_8(wr_val) merlin16_pmd_wr_reg(sa__, 0xd108,wr_val) 1212 #define rdc_patt_gen_seq_9() _merlin16_pmd_rde_reg(sa__, 0xd109,__ERR) 1213 #define wrc_patt_gen_seq_9(wr_val) merlin16_pmd_wr_reg(sa__, 0xd109,wr_val) 1214 #define rdc_patt_gen_seq_10() _merlin16_pmd_rde_reg(sa__, 0xd10a,__ERR) 1215 #define wrc_patt_gen_seq_10(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10a,wr_val) 1216 #define rdc_patt_gen_seq_11() _merlin16_pmd_rde_reg(sa__, 0xd10b,__ERR) 1217 #define wrc_patt_gen_seq_11(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10b,wr_val) 1218 #define rdc_patt_gen_seq_12() _merlin16_pmd_rde_reg(sa__, 0xd10c,__ERR) 1219 #define wrc_patt_gen_seq_12(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10c,wr_val) 1220 #define rdc_patt_gen_seq_13() _merlin16_pmd_rde_reg(sa__, 0xd10d,__ERR) 1221 #define wrc_patt_gen_seq_13(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10d,wr_val) 1222 #define rdc_patt_gen_seq_14() _merlin16_pmd_rde_reg(sa__, 0xd10e,__ERR) 1223 #define wrc_patt_gen_seq_14(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10e,wr_val) 1224 #define rdc_cal_th() _merlin16_pmd_rde_field_byte(sa__, 0xd120,0,14,__ERR) 1225 #define wrc_cal_th(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd120,0xc000,14,wr_val) 1226 #define rdc_calib_step_time() _merlin16_pmd_rde_field(sa__, 0xd120,3,3,__ERR) 1227 #define wrc_calib_step_time(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd120,0x1fff,0,wr_val) 1228 #define rdc_freqdet_time() _merlin16_pmd_rde_reg(sa__, 0xd121,__ERR) 1229 #define wrc_freqdet_time(wr_val) merlin16_pmd_wr_reg(sa__, 0xd121,wr_val) 1230 #define rdc_calib_cap_charge_time() _merlin16_pmd_rde_field(sa__, 0xd122,4,4,__ERR) 1231 #define wrc_calib_cap_charge_time(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd122,0x0fff,0,wr_val) 1232 #define rdc_ext_state() _merlin16_pmd_rde_field_byte(sa__, 0xd123,0,12,__ERR) 1233 #define wrc_ext_state(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd123,0xf000,12,wr_val) 1234 #define rdc_accel_en() _merlin16_pmd_rde_field_byte(sa__, 0xd123,4,15,__ERR) 1235 #define wrc_accel_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd123,0x0800,11,wr_val) 1236 #define rdc_debug_clr() _merlin16_pmd_rde_field_byte(sa__, 0xd123,5,15,__ERR) 1237 #define wrc_debug_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd123,0x0400,10,wr_val) 1238 #define rdc_freqdet_time_msb() _merlin16_pmd_rde_field_byte(sa__, 0xd123,6,15,__ERR) 1239 #define wrc_freqdet_time_msb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd123,0x0200,9,wr_val) 1240 #define rdc_freqdet_win() _merlin16_pmd_rde_field_byte(sa__, 0xd123,8,8,__ERR) 1241 #define wrc_freqdet_win(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd123,0x00ff,0,wr_val) 1242 #define rdc_halfstep_en() _merlin16_pmd_rde_field_byte(sa__, 0xd124,0,15,__ERR) 1243 #define wrc_halfstep_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x8000,15,wr_val) 1244 #define rdc_pll_force_cap_pass_en() _merlin16_pmd_rde_field_byte(sa__, 0xd124,1,15,__ERR) 1245 #define wrc_pll_force_cap_pass_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x4000,14,wr_val) 1246 #define rdc_pll_force_cap_pass() _merlin16_pmd_rde_field_byte(sa__, 0xd124,2,15,__ERR) 1247 #define wrc_pll_force_cap_pass(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x2000,13,wr_val) 1248 #define rdc_cal_pause_en() _merlin16_pmd_rde_field_byte(sa__, 0xd124,3,15,__ERR) 1249 #define wrc_cal_pause_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x1000,12,wr_val) 1250 #define rdc_cal_pause_rel() _merlin16_pmd_rde_field_byte(sa__, 0xd124,4,15,__ERR) 1251 #define wrc_cal_pause_rel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x0800,11,wr_val) 1252 #define rdc_cap_delay() _merlin16_pmd_rde_field_byte(sa__, 0xd124,5,15,__ERR) 1253 #define wrc_cap_delay(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x0400,10,wr_val) 1254 #define rdc_calib_start() _merlin16_pmd_rde_field_byte(sa__, 0xd124,6,15,__ERR) 1255 #define wrc_calib_start(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x0200,9,wr_val) 1256 #define rdc_en_calib_n() _merlin16_pmd_rde_field_byte(sa__, 0xd124,7,15,__ERR) 1257 #define wrc_en_calib_n(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x0100,8,wr_val) 1258 #define rdc_ext_range() _merlin16_pmd_rde_field_byte(sa__, 0xd124,9,9,__ERR) 1259 #define wrc_ext_range(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd124,0x007f,0,wr_val) 1260 #define rdc_pll_seq_start() _merlin16_pmd_rde_field_byte(sa__, 0xd125,0,15,__ERR) 1261 #define wrc_pll_seq_start(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x8000,15,wr_val) 1262 #define rdc_lkdt_pause_en() _merlin16_pmd_rde_field_byte(sa__, 0xd125,1,15,__ERR) 1263 #define wrc_lkdt_pause_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x4000,14,wr_val) 1264 #define rdc_lkdt_pause_rel() _merlin16_pmd_rde_field_byte(sa__, 0xd125,2,15,__ERR) 1265 #define wrc_lkdt_pause_rel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x2000,13,wr_val) 1266 #define rdc_vco_rst_en() _merlin16_pmd_rde_field_byte(sa__, 0xd125,3,15,__ERR) 1267 #define wrc_vco_rst_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x1000,12,wr_val) 1268 #define rdc_autocal_en() _merlin16_pmd_rde_field_byte(sa__, 0xd125,7,15,__ERR) 1269 #define wrc_autocal_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x0100,8,wr_val) 1270 #define rdc_autocal_cnt() _merlin16_pmd_rde_field_byte(sa__, 0xd125,8,13,__ERR) 1271 #define wrc_autocal_cnt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x00e0,5,wr_val) 1272 #define rdc_lkdt_byp() _merlin16_pmd_rde_field_byte(sa__, 0xd125,11,15,__ERR) 1273 #define wrc_lkdt_byp(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x0010,4,wr_val) 1274 #define rdc_pll_lock_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd125,12,15,__ERR) 1275 #define wrc_pll_lock_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x0008,3,wr_val) 1276 #define rdc_pll_lock_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd125,13,15,__ERR) 1277 #define wrc_pll_lock_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x0004,2,wr_val) 1278 #define rdc_pllforce_fdone() _merlin16_pmd_rde_field_byte(sa__, 0xd125,14,15,__ERR) 1279 #define wrc_pllforce_fdone(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x0002,1,wr_val) 1280 #define rdc_pllforce_fdone_en() _merlin16_pmd_rde_field_byte(sa__, 0xd125,15,15,__ERR) 1281 #define wrc_pllforce_fdone_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd125,0x0001,0,wr_val) 1282 #define rdc_band_iqbuf_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd126,8,15,__ERR) 1283 #define wrc_band_iqbuf_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd126,0x0080,7,wr_val) 1284 #define rdc_vcorange_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd126,9,15,__ERR) 1285 #define wrc_vcorange_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd126,0x0040,6,wr_val) 1286 #define rdc_vcobufpon_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd126,10,15,__ERR) 1287 #define wrc_vcobufpon_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd126,0x0020,5,wr_val) 1288 #define rdc_vcopon_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd126,12,15,__ERR) 1289 #define wrc_vcopon_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd126,0x0008,3,wr_val) 1290 #define rdc_pllpon_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd126,14,15,__ERR) 1291 #define wrc_pllpon_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd126,0x0002,1,wr_val) 1292 #define rdc_pll_fail_stky() _merlin16_pmd_rde_field_byte(sa__, 0xd128,0,15,__ERR) 1293 #define rdc_cal_state() _merlin16_pmd_rde_field_byte(sa__, 0xd128,1,12,__ERR) 1294 #define rdc_cal_valid() _merlin16_pmd_rde_field_byte(sa__, 0xd128,5,15,__ERR) 1295 #define rdc_pll_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd128,6,15,__ERR) 1296 #define rdc_pll_lock_bar_stky() _merlin16_pmd_rde_field_byte(sa__, 0xd128,7,15,__ERR) 1297 #define rdc_pll_range() _merlin16_pmd_rde_field_byte(sa__, 0xd128,9,9,__ERR) 1298 #define rdc_lkdtref_counter_msb() _merlin16_pmd_rde_field_byte(sa__, 0xd129,0,15,__ERR) 1299 #define rdc_lkdtvco_counter_msb() _merlin16_pmd_rde_field_byte(sa__, 0xd129,1,15,__ERR) 1300 #define rdc_calref_counter() _merlin16_pmd_rde_field(sa__, 0xd129,3,3,__ERR) 1301 #define rdc_band_iqbuf_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd12a,0,13,__ERR) 1302 #define rdc_calvco_counter() _merlin16_pmd_rde_field(sa__, 0xd12a,3,3,__ERR) 1303 #define rdc_lkdtref_counter() _merlin16_pmd_rde_reg(sa__, 0xd12b,__ERR) 1304 #define rdc_lkdtvco_counter() _merlin16_pmd_rde_reg(sa__, 0xd12c,__ERR) 1305 #define rdc_vcobufpon_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd12d,2,12,__ERR) 1306 #define rdc_calstate_onehot() _merlin16_pmd_rde_field(sa__, 0xd12d,6,6,__ERR) 1307 #define rdc_pll_pwrdn_or() _merlin16_pmd_rde_field_byte(sa__, 0xd12e,0,15,__ERR) 1308 #define rdc_vco_range_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd12e,1,9,__ERR) 1309 #define rdc_vcopon_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd12e,8,12,__ERR) 1310 #define rdc_pllpon_mux() _merlin16_pmd_rde_field_byte(sa__, 0xd12e,12,12,__ERR) 1311 #define rd_afe_sigdet_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd161,14,15,__ERR) 1312 #define wr_afe_sigdet_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd161,0x0002,1,wr_val) 1313 #define rd_ln_rx_s_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd161,15,15,__ERR) 1314 #define wr_ln_rx_s_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd161,0x0001,0,wr_val) 1315 #define rd_pmd_rx_clk_vld_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd167,11,15,__ERR) 1316 #define wr_pmd_rx_clk_vld_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd167,0x0010,4,wr_val) 1317 #define rd_pmd_rx_clk_vld_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd167,12,15,__ERR) 1318 #define wr_pmd_rx_clk_vld_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd167,0x0008,3,wr_val) 1319 #define rd_ln_rx_s_comclk_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd167,13,15,__ERR) 1320 #define wr_ln_rx_s_comclk_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd167,0x0004,2,wr_val) 1321 #define rd_ln_rx_s_comclk_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd167,14,15,__ERR) 1322 #define wr_ln_rx_s_comclk_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd167,0x0002,1,wr_val) 1323 #define rd_ln_rx_s_clkgate_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd167,15,15,__ERR) 1324 #define wr_ln_rx_s_clkgate_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd167,0x0001,0,wr_val) 1325 #define rd_sigdet_dp_rstb_en() _merlin16_pmd_rde_field_byte(sa__, 0xd164,13,15,__ERR) 1326 #define wr_sigdet_dp_rstb_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd164,0x0004,2,wr_val) 1327 #define rd_ln_rx_dp_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd164,14,15,__ERR) 1328 #define wr_ln_rx_dp_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd164,0x0002,1,wr_val) 1329 #define rd_ln_rx_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd164,15,15,__ERR) 1330 #define wr_ln_rx_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd164,0x0001,0,wr_val) 1331 #define rd_afe_rx_reset_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd162,12,15,__ERR) 1332 #define wr_afe_rx_reset_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd162,0x0008,3,wr_val) 1333 #define rd_afe_rx_reset_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd162,13,15,__ERR) 1334 #define wr_afe_rx_reset_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd162,0x0004,2,wr_val) 1335 #define rd_afe_rx_pwrdn_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd162,14,15,__ERR) 1336 #define wr_afe_rx_pwrdn_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd162,0x0002,1,wr_val) 1337 #define rd_afe_rx_pwrdn_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd162,15,15,__ERR) 1338 #define wr_afe_rx_pwrdn_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd162,0x0001,0,wr_val) 1339 #define rd_pmd_ln_rx_h_pwrdn_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd163,15,15,__ERR) 1340 #define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd163,0x0001,0,wr_val) 1341 #define rd_pmd_lane_mode() _merlin16_pmd_rde_reg(sa__, 0xd168,__ERR) 1342 #define rd_afe_rx_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd16c,14,15,__ERR) 1343 #define rd_afe_rx_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd16c,15,15,__ERR) 1344 #define rd_rx_osr_mode_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd180,0,15,__ERR) 1345 #define wr_rx_osr_mode_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd180,0x8000,15,wr_val) 1346 #define rd_rx_osr_mode_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd180,12,12,__ERR) 1347 #define wr_rx_osr_mode_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd180,0x000f,0,wr_val) 1348 #define rd_rx_ln_dp_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd181,15,15,__ERR) 1349 #define wr_rx_ln_dp_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd181,0x0001,0,wr_val) 1350 #define rd_rx_ln_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd18e,15,15,__ERR) 1351 #define wr_rx_ln_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd18e,0x0001,0,wr_val) 1352 #define rd_pmd_ln_rx_dp_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd183,14,15,__ERR) 1353 #define wr_pmd_ln_rx_dp_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd183,0x0002,1,wr_val) 1354 #define rd_pmd_ln_rx_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd183,15,15,__ERR) 1355 #define wr_pmd_ln_rx_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd183,0x0001,0,wr_val) 1356 #define rd_rx_uc_ack_lane_dp_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd185,14,15,__ERR) 1357 #define wr_rx_uc_ack_lane_dp_reset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd185,0x0002,1,wr_val) 1358 #define rd_rx_uc_ack_lane_cfg_done() _merlin16_pmd_rde_field_byte(sa__, 0xd185,15,15,__ERR) 1359 #define wr_rx_uc_ack_lane_cfg_done(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd185,0x0001,0,wr_val) 1360 #define rd_rx_lane_dp_reset_state() _merlin16_pmd_rde_field_byte(sa__, 0xd189,13,13,__ERR) 1361 #define rd_rx_lane_reg_reset_occurred() _merlin16_pmd_rde_field_byte(sa__, 0xd186,15,15,__ERR) 1362 #define wr_rx_lane_reg_reset_occurred(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd186,0x0001,0,wr_val) 1363 #define rd_rx_multicast_mask_control() _merlin16_pmd_rde_field_byte(sa__, 0xd18a,15,15,__ERR) 1364 #define wr_rx_multicast_mask_control(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd18a,0x0001,0,wr_val) 1365 #define rd_rx_multicast_mask_control_status() _merlin16_pmd_rde_field_byte(sa__, 0xd18b,11,15,__ERR) 1366 #define rd_rx_osr_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd18b,12,12,__ERR) 1367 #define rd_rx_osr_mode_pin() _merlin16_pmd_rde_field_byte(sa__, 0xd18c,12,12,__ERR) 1368 #define rd_osr_mode_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd080,0,15,__ERR) 1369 #define wr_osr_mode_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd080,0x8000,15,wr_val) 1370 #define rd_osr_mode_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd080,12,12,__ERR) 1371 #define wr_osr_mode_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd080,0x000f,0,wr_val) 1372 #define rd_ln_dp_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd081,15,15,__ERR) 1373 #define wr_ln_dp_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd081,0x0001,0,wr_val) 1374 #define rd_ln_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd08e,15,15,__ERR) 1375 #define wr_ln_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd08e,0x0001,0,wr_val) 1376 #define rd_pmd_ln_dp_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd083,14,15,__ERR) 1377 #define wr_pmd_ln_dp_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd083,0x0002,1,wr_val) 1378 #define rd_pmd_ln_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd083,15,15,__ERR) 1379 #define wr_pmd_ln_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd083,0x0001,0,wr_val) 1380 #define rd_uc_ack_lane_dp_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd085,14,15,__ERR) 1381 #define wr_uc_ack_lane_dp_reset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd085,0x0002,1,wr_val) 1382 #define rd_uc_ack_lane_cfg_done() _merlin16_pmd_rde_field_byte(sa__, 0xd085,15,15,__ERR) 1383 #define wr_uc_ack_lane_cfg_done(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd085,0x0001,0,wr_val) 1384 #define rd_lane_dp_reset_state() _merlin16_pmd_rde_field_byte(sa__, 0xd089,13,13,__ERR) 1385 #define rd_lane_reg_reset_occurred() _merlin16_pmd_rde_field_byte(sa__, 0xd086,15,15,__ERR) 1386 #define wr_lane_reg_reset_occurred(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd086,0x0001,0,wr_val) 1387 #define rd_multicast_mask_control() _merlin16_pmd_rde_field_byte(sa__, 0xd08a,15,15,__ERR) 1388 #define wr_multicast_mask_control(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd08a,0x0001,0,wr_val) 1389 #define rd_multicast_mask_control_status() _merlin16_pmd_rde_field_byte(sa__, 0xd08b,11,15,__ERR) 1390 #define rd_osr_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd08b,12,12,__ERR) 1391 #define rd_osr_mode_pin() _merlin16_pmd_rde_field_byte(sa__, 0xd08c,12,12,__ERR) 1392 #define rd_signal_detect_filter_count() _merlin16_pmd_rde_field_byte(sa__, 0xd0c0,11,11,__ERR) 1393 #define wr_signal_detect_filter_count(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c0,0x001f,0,wr_val) 1394 #define rd_los_filter_count() _merlin16_pmd_rde_field_byte(sa__, 0xd0c0,6,11,__ERR) 1395 #define wr_los_filter_count(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c0,0x03e0,5,wr_val) 1396 #define rd_energy_detect_mask_count() _merlin16_pmd_rde_field_byte(sa__, 0xd0c0,1,11,__ERR) 1397 #define wr_energy_detect_mask_count(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c0,0x7c00,10,wr_val) 1398 #define rd_afe_signal_detect_dis() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,15,15,__ERR) 1399 #define wr_afe_signal_detect_dis(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0001,0,wr_val) 1400 #define rd_ext_los_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,14,15,__ERR) 1401 #define wr_ext_los_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0002,1,wr_val) 1402 #define rd_ext_los_inv() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,13,15,__ERR) 1403 #define wr_ext_los_inv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0004,2,wr_val) 1404 #define rd_ignore_lp_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,12,15,__ERR) 1405 #define wr_ignore_lp_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0008,3,wr_val) 1406 #define rd_signal_detect_filter_1us() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,11,15,__ERR) 1407 #define wr_signal_detect_filter_1us(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0010,4,wr_val) 1408 #define rd_energy_detect_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,10,15,__ERR) 1409 #define wr_energy_detect_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0020,5,wr_val) 1410 #define rd_energy_detect_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,9,15,__ERR) 1411 #define wr_energy_detect_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0040,6,wr_val) 1412 #define rd_signal_detect_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,8,15,__ERR) 1413 #define wr_signal_detect_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0080,7,wr_val) 1414 #define rd_signal_detect_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd0c1,7,15,__ERR) 1415 #define wr_signal_detect_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0100,8,wr_val) 1416 #define rd_los_thresh() _merlin16_pmd_rde_field_byte(sa__, 0xd0c2,11,11,__ERR) 1417 #define wr_los_thresh(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c2,0x001f,0,wr_val) 1418 #define rd_signal_detect_thresh() _merlin16_pmd_rde_field_byte(sa__, 0xd0c2,6,11,__ERR) 1419 #define wr_signal_detect_thresh(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c2,0x03e0,5,wr_val) 1420 #define rd_hold_los_count() _merlin16_pmd_rde_field_byte(sa__, 0xd0c2,3,13,__ERR) 1421 #define wr_hold_los_count(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c2,0x1c00,10,wr_val) 1422 #define rd_hold_sd_count() _merlin16_pmd_rde_field_byte(sa__, 0xd0c2,0,13,__ERR) 1423 #define wr_hold_sd_count(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0c2,0xe000,13,wr_val) 1424 #define rd_signal_detect() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,15,15,__ERR) 1425 #define rd_signal_detect_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,14,15,__ERR) 1426 #define rd_signal_detect_raw() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,11,15,__ERR) 1427 #define rd_signal_detect_raw_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,10,15,__ERR) 1428 #define rd_ext_sigdet() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,9,15,__ERR) 1429 #define rd_ext_sigdet_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,8,15,__ERR) 1430 #define rd_afe_sigdet() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,7,15,__ERR) 1431 #define rd_afe_sigdet_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c8,6,15,__ERR) 1432 #define rd_uc_signal_detect() _merlin16_pmd_rde_field_byte(sa__, 0xd0c9,15,15,__ERR) 1433 #define rd_uc_signal_detect_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c9,14,15,__ERR) 1434 #define rd_uc_ext_sigdet() _merlin16_pmd_rde_field_byte(sa__, 0xd0c9,9,15,__ERR) 1435 #define rd_uc_ext_sigdet_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c9,8,15,__ERR) 1436 #define rd_uc_afe_sigdet() _merlin16_pmd_rde_field_byte(sa__, 0xd0c9,7,15,__ERR) 1437 #define rd_uc_afe_sigdet_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0c9,6,15,__ERR) 1438 #define rd_energy_detect() _merlin16_pmd_rde_field_byte(sa__, 0xd0ca,15,15,__ERR) 1439 #define rd_energy_detect_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0ca,14,15,__ERR) 1440 #define rd_pmd_signal_detect() _merlin16_pmd_rde_field_byte(sa__, 0xd0cb,15,15,__ERR) 1441 #define rd_afe_sigdet_thresh() _merlin16_pmd_rde_field_byte(sa__, 0xd0cc,11,11,__ERR) 1442 #define rdc_test_ctl_ckgt_en() _merlin16_pmd_rde_field_byte(sa__, 0xe000,8,15,__ERR) 1443 #define wrc_test_ctl_ckgt_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xe000,0x0080,7,wr_val) 1444 #define rdc_test_ctl_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xe000,9,15,__ERR) 1445 #define wrc_test_ctl_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xe000,0x0040,6,wr_val) 1446 #define rdc_test_phfifo_err_lh_clr() _merlin16_pmd_rde_field_byte(sa__, 0xe000,11,15,__ERR) 1447 #define wrc_test_phfifo_err_lh_clr(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xe000,0x0010,4,wr_val) 1448 #define rdc_test_phfifo_auto_recenter_en() _merlin16_pmd_rde_field_byte(sa__, 0xe000,13,15,__ERR) 1449 #define wrc_test_phfifo_auto_recenter_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xe000,0x0004,2,wr_val) 1450 #define rdc_test_phfifo_recenter() _merlin16_pmd_rde_field_byte(sa__, 0xe000,14,15,__ERR) 1451 #define wrc_test_phfifo_recenter(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xe000,0x0002,1,wr_val) 1452 #define rdc_test_ext_rmt_lpbk_en() _merlin16_pmd_rde_field_byte(sa__, 0xe000,15,15,__ERR) 1453 #define wrc_test_ext_rmt_lpbk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xe000,0x0001,0,wr_val) 1454 #define rdc_test_sta_phfifo_err() _merlin16_pmd_rde_field_byte(sa__, 0xe001,15,15,__ERR) 1455 #define rd_prbs_chk_burst_err_cnt_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,0,15,__ERR) 1456 #define wr_prbs_chk_burst_err_cnt_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x8000,15,wr_val) 1457 #define rd_prbs_chk_clk_en_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,4,15,__ERR) 1458 #define wr_prbs_chk_clk_en_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0800,11,wr_val) 1459 #define rd_trnsum_error_count_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,5,15,__ERR) 1460 #define wr_trnsum_error_count_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0400,10,wr_val) 1461 #define rd_prbs_chk_err_cnt_burst_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,6,15,__ERR) 1462 #define wr_prbs_chk_err_cnt_burst_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0200,9,wr_val) 1463 #define rd_prbs_chk_en_auto_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,8,15,__ERR) 1464 #define wr_prbs_chk_en_auto_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0080,7,wr_val) 1465 #define rd_prbs_chk_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,9,14,__ERR) 1466 #define wr_prbs_chk_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0060,5,wr_val) 1467 #define rd_prbs_chk_inv() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,11,15,__ERR) 1468 #define wr_prbs_chk_inv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0010,4,wr_val) 1469 #define rd_prbs_chk_mode_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,12,13,__ERR) 1470 #define wr_prbs_chk_mode_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x000e,1,wr_val) 1471 #define rd_prbs_chk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d1,15,15,__ERR) 1472 #define wr_prbs_chk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0001,0,wr_val) 1473 #define rd_prbs_chk_lock_cnt() _merlin16_pmd_rde_field_byte(sa__, 0xd0d0,11,11,__ERR) 1474 #define wr_prbs_chk_lock_cnt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d0,0x001f,0,wr_val) 1475 #define rd_prbs_chk_ool_cnt() _merlin16_pmd_rde_field_byte(sa__, 0xd0d0,3,11,__ERR) 1476 #define wr_prbs_chk_ool_cnt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d0,0x1f00,8,wr_val) 1477 #define rd_dig_lpbk_pd_bias_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d2,12,15,__ERR) 1478 #define wr_dig_lpbk_pd_bias_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0008,3,wr_val) 1479 #define rd_dig_lpbk_pd_flt_bypass() _merlin16_pmd_rde_field_byte(sa__, 0xd0d2,13,15,__ERR) 1480 #define wr_dig_lpbk_pd_flt_bypass(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0004,2,wr_val) 1481 #define rd_dig_lpbk_pd_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0d2,14,15,__ERR) 1482 #define wr_dig_lpbk_pd_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0002,1,wr_val) 1483 #define rd_dig_lpbk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d2,15,15,__ERR) 1484 #define wr_dig_lpbk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0001,0,wr_val) 1485 #define rd_dbg_mask_dig_lpbk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d3,13,15,__ERR) 1486 #define wr_dbg_mask_dig_lpbk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0004,2,wr_val) 1487 #define rd_rx_aggregator_bypass_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0d3,14,15,__ERR) 1488 #define wr_rx_aggregator_bypass_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0002,1,wr_val) 1489 #define rd_rx_pmd_dp_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd0d3,15,15,__ERR) 1490 #define wr_rx_pmd_dp_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0001,0,wr_val) 1491 #define rd_prbs_chk_en_timeout() _merlin16_pmd_rde_field_byte(sa__, 0xd0d4,3,11,__ERR) 1492 #define wr_prbs_chk_en_timeout(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d4,0x1f00,8,wr_val) 1493 #define rd_prbs_chk_en_timer_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0d4,14,14,__ERR) 1494 #define wr_prbs_chk_en_timer_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0d4,0x0003,0,wr_val) 1495 #define rd_dig_lpbk_pd_early_ind() _merlin16_pmd_rde_field_byte(sa__, 0xd0d8,14,15,__ERR) 1496 #define rd_dig_lpbk_pd_late_ind() _merlin16_pmd_rde_field_byte(sa__, 0xd0d8,15,15,__ERR) 1497 #define rd_prbs_chk_err_cnt_no_clr() _merlin16_pmd_rde_field(sa__, 0xd0d9,0,1,__ERR) 1498 #define rd_prbs_chk_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd0d9,15,15,__ERR) 1499 #define rd_prbs_chk_lock_lost_lh() _merlin16_pmd_rde_field_byte(sa__, 0xd0da,0,15,__ERR) 1500 #define rd_prbs_chk_err_cnt_msb() _merlin16_pmd_rde_field(sa__, 0xd0da,1,1,__ERR) 1501 #define rd_prbs_chk_err_cnt_lsb() _merlin16_pmd_rde_reg(sa__, 0xd0db,__ERR) 1502 #define rd_pmd_rx_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd0dc,15,15,__ERR) 1503 #define rd_pmd_rx_lock_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0dc,14,15,__ERR) 1504 #define rd_dbg_pmd_rx_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd0d6,15,15,__ERR) 1505 #define rd_dbg_pmd_rx_lock_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0d6,14,15,__ERR) 1506 #define rd_uc_pmd_rx_lock() _merlin16_pmd_rde_field_byte(sa__, 0xd0d7,15,15,__ERR) 1507 #define rd_uc_pmd_rx_lock_change() _merlin16_pmd_rde_field_byte(sa__, 0xd0d7,14,15,__ERR) 1508 #define rd_prbs_chk_burst_err_cnt() _merlin16_pmd_rde_field(sa__, 0xd0d5,6,6,__ERR) 1509 #define rd_patt_gen_start_pos() _merlin16_pmd_rde_field_byte(sa__, 0xd0e0,0,12,__ERR) 1510 #define wr_patt_gen_start_pos(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e0,0xf000,12,wr_val) 1511 #define rd_patt_gen_stop_pos() _merlin16_pmd_rde_field_byte(sa__, 0xd0e0,4,12,__ERR) 1512 #define wr_patt_gen_stop_pos(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e0,0x0f00,8,wr_val) 1513 #define rd_patt_gen_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0e0,15,15,__ERR) 1514 #define wr_patt_gen_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e0,0x0001,0,wr_val) 1515 #define rd_prbs_gen_err_ins() _merlin16_pmd_rde_field_byte(sa__, 0xd0e1,10,15,__ERR) 1516 #define wr_prbs_gen_err_ins(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0020,5,wr_val) 1517 #define rd_prbs_gen_inv() _merlin16_pmd_rde_field_byte(sa__, 0xd0e1,11,15,__ERR) 1518 #define wr_prbs_gen_inv(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0010,4,wr_val) 1519 #define rd_prbs_gen_mode_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd0e1,12,13,__ERR) 1520 #define wr_prbs_gen_mode_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e1,0x000e,1,wr_val) 1521 #define rd_prbs_gen_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0e1,15,15,__ERR) 1522 #define wr_prbs_gen_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0001,0,wr_val) 1523 #define rd_rmt_lpbk_pd_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd0e2,13,15,__ERR) 1524 #define wr_rmt_lpbk_pd_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0004,2,wr_val) 1525 #define rd_rmt_lpbk_pd_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd0e2,14,15,__ERR) 1526 #define wr_rmt_lpbk_pd_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0002,1,wr_val) 1527 #define rd_rmt_lpbk_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0e2,15,15,__ERR) 1528 #define wr_rmt_lpbk_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0001,0,wr_val) 1529 #define rd_tx_mux_sel_order() _merlin16_pmd_rde_field_byte(sa__, 0xd0e3,13,15,__ERR) 1530 #define wr_tx_mux_sel_order(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0004,2,wr_val) 1531 #define rd_tx_pcs_native_ana_frmt_en() _merlin16_pmd_rde_field_byte(sa__, 0xd0e3,14,15,__ERR) 1532 #define wr_tx_pcs_native_ana_frmt_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0002,1,wr_val) 1533 #define rd_tx_pmd_dp_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd0e3,15,15,__ERR) 1534 #define wr_tx_pmd_dp_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0001,0,wr_val) 1535 #define rd_rmt_lpbk_pd_early_ind() _merlin16_pmd_rde_field_byte(sa__, 0xd0e8,14,15,__ERR) 1536 #define rd_rmt_lpbk_pd_late_ind() _merlin16_pmd_rde_field_byte(sa__, 0xd0e8,15,15,__ERR) 1537 #define rd_afe_tx_reset_deassert() _merlin16_pmd_rde_field_byte(sa__, 0xd171,0,15,__ERR) 1538 #define wr_afe_tx_reset_deassert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd171,0x8000,15,wr_val) 1539 #define rd_ln_tx_s_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd171,15,15,__ERR) 1540 #define wr_ln_tx_s_pwrdn(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd171,0x0001,0,wr_val) 1541 #define rd_pmd_tx_clk_vld_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd177,11,15,__ERR) 1542 #define wr_pmd_tx_clk_vld_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd177,0x0010,4,wr_val) 1543 #define rd_pmd_tx_clk_vld_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd177,12,15,__ERR) 1544 #define wr_pmd_tx_clk_vld_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd177,0x0008,3,wr_val) 1545 #define rd_ln_tx_s_comclk_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd177,13,15,__ERR) 1546 #define wr_ln_tx_s_comclk_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd177,0x0004,2,wr_val) 1547 #define rd_ln_tx_s_comclk_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd177,14,15,__ERR) 1548 #define wr_ln_tx_s_comclk_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd177,0x0002,1,wr_val) 1549 #define rd_ln_tx_s_clkgate_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd177,15,15,__ERR) 1550 #define wr_ln_tx_s_clkgate_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd177,0x0001,0,wr_val) 1551 #define rd_ln_tx_dp_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd174,14,15,__ERR) 1552 #define wr_ln_tx_dp_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd174,0x0002,1,wr_val) 1553 #define rd_ln_tx_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd174,15,15,__ERR) 1554 #define wr_ln_tx_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd174,0x0001,0,wr_val) 1555 #define rd_afe_txclk_reset_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd172,10,15,__ERR) 1556 #define wr_afe_txclk_reset_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd172,0x0020,5,wr_val) 1557 #define rd_afe_txclk_reset_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd172,11,15,__ERR) 1558 #define wr_afe_txclk_reset_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd172,0x0010,4,wr_val) 1559 #define rd_afe_tx_reset_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd172,12,15,__ERR) 1560 #define wr_afe_tx_reset_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd172,0x0008,3,wr_val) 1561 #define rd_afe_tx_reset_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd172,13,15,__ERR) 1562 #define wr_afe_tx_reset_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd172,0x0004,2,wr_val) 1563 #define rd_afe_tx_pwrdn_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd172,14,15,__ERR) 1564 #define wr_afe_tx_pwrdn_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd172,0x0002,1,wr_val) 1565 #define rd_afe_tx_pwrdn_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd172,15,15,__ERR) 1566 #define wr_afe_tx_pwrdn_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd172,0x0001,0,wr_val) 1567 #define rd_pmd_ln_tx_h_pwrdn_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd173,15,15,__ERR) 1568 #define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd173,0x0001,0,wr_val) 1569 #define rd_afe_txclk_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd17c,13,15,__ERR) 1570 #define rd_afe_tx_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd17c,14,15,__ERR) 1571 #define rd_afe_tx_pwrdn() _merlin16_pmd_rde_field_byte(sa__, 0xd17c,15,15,__ERR) 1572 #define rd_tx_pi_loop_filter_stable() _merlin16_pmd_rde_field_byte(sa__, 0xd17d,15,15,__ERR) 1573 #define wr_tx_pi_loop_filter_stable(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd17d,0x0001,0,wr_val) 1574 #define rd_txfir_post2() _merlin16_pmd_rde_field_byte(sa__, 0xd110,12,12,__ERR) 1575 #define wr_txfir_post2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd110,0x000f,0,wr_val) 1576 #define rd_convert_taps_to_afe_error() _merlin16_pmd_rde_field_byte(sa__, 0xd111,9,15,__ERR) 1577 #define wr_convert_taps_to_afe_error(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd111,0x0040,6,wr_val) 1578 #define rd_convert_taps_to_afe_int_en() _merlin16_pmd_rde_field_byte(sa__, 0xd111,10,15,__ERR) 1579 #define wr_convert_taps_to_afe_int_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd111,0x0020,5,wr_val) 1580 #define rd_convert_taps_to_afe() _merlin16_pmd_rde_field_byte(sa__, 0xd111,11,15,__ERR) 1581 #define wr_convert_taps_to_afe(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd111,0x0010,4,wr_val) 1582 #define rd_tx_disable_output_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd111,12,14,__ERR) 1583 #define wr_tx_disable_output_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd111,0x000c,2,wr_val) 1584 #define rd_sdk_tx_disable() _merlin16_pmd_rde_field_byte(sa__, 0xd111,15,15,__ERR) 1585 #define wr_sdk_tx_disable(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd111,0x0001,0,wr_val) 1586 #define rd_tx_elec_idle_status() _merlin16_pmd_rde_field_byte(sa__, 0xd112,14,15,__ERR) 1587 #define rd_tx_disable_status() _merlin16_pmd_rde_field_byte(sa__, 0xd112,15,15,__ERR) 1588 #define rd_tx_eee_alert_en() _merlin16_pmd_rde_field_byte(sa__, 0xd113,0,15,__ERR) 1589 #define wr_tx_eee_alert_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x8000,15,wr_val) 1590 #define rd_tx_eee_quiet_en() _merlin16_pmd_rde_field_byte(sa__, 0xd113,1,15,__ERR) 1591 #define wr_tx_eee_quiet_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x4000,14,wr_val) 1592 #define rd_tx_disable_timer_ctrl() _merlin16_pmd_rde_field_byte(sa__, 0xd113,6,10,__ERR) 1593 #define wr_tx_disable_timer_ctrl(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x03f0,4,wr_val) 1594 #define rd_pmd_tx_disable_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd113,12,15,__ERR) 1595 #define wr_pmd_tx_disable_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x0008,3,wr_val) 1596 #define rd_dp_reset_tx_disable_dis() _merlin16_pmd_rde_field_byte(sa__, 0xd113,13,15,__ERR) 1597 #define wr_dp_reset_tx_disable_dis(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x0004,2,wr_val) 1598 #define rd_tx_disable_trigger() _merlin16_pmd_rde_field_byte(sa__, 0xd113,14,15,__ERR) 1599 #define wr_tx_disable_trigger(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x0002,1,wr_val) 1600 #define rd_micro_tx_disable() _merlin16_pmd_rde_field_byte(sa__, 0xd113,15,15,__ERR) 1601 #define wr_micro_tx_disable(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd113,0x0001,0,wr_val) 1602 #define rd_txfir_dc_level_post2_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,8,15,__ERR) 1603 #define wr_txfir_dc_level_post2_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0080,7,wr_val) 1604 #define rd_txfir_post2_post2_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,9,15,__ERR) 1605 #define wr_txfir_post2_post2_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0040,6,wr_val) 1606 #define rd_txfir_dc_level_post2_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,10,15,__ERR) 1607 #define wr_txfir_dc_level_post2_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0020,5,wr_val) 1608 #define rd_txfir_post2_post2_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,11,15,__ERR) 1609 #define wr_txfir_post2_post2_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0010,4,wr_val) 1610 #define rd_txfir_dc_level_post2_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,12,15,__ERR) 1611 #define wr_txfir_dc_level_post2_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0008,3,wr_val) 1612 #define rd_txfir_post2_post2_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,13,15,__ERR) 1613 #define wr_txfir_post2_post2_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0004,2,wr_val) 1614 #define rd_txfir_dc_level_post2_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,14,15,__ERR) 1615 #define wr_txfir_dc_level_post2_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0002,1,wr_val) 1616 #define rd_txfir_post2_post2_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11b,15,15,__ERR) 1617 #define wr_txfir_post2_post2_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11b,0x0001,0,wr_val) 1618 #define rd_txfir_dc_level_post1pre_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,1,15,__ERR) 1619 #define wr_txfir_dc_level_post1pre_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x4000,14,wr_val) 1620 #define rd_txfir_post1_post1pre_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,2,15,__ERR) 1621 #define wr_txfir_post1_post1pre_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x2000,13,wr_val) 1622 #define rd_txfir_pre_post1pre_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,3,15,__ERR) 1623 #define wr_txfir_pre_post1pre_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x1000,12,wr_val) 1624 #define rd_txfir_dc_level_post1_2x_2() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,6,15,__ERR) 1625 #define wr_txfir_dc_level_post1_2x_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0200,9,wr_val) 1626 #define rd_txfir_post1_post1_2x_2() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,7,15,__ERR) 1627 #define wr_txfir_post1_post1_2x_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0100,8,wr_val) 1628 #define rd_txfir_dc_level_post1_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,8,15,__ERR) 1629 #define wr_txfir_dc_level_post1_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0080,7,wr_val) 1630 #define rd_txfir_post1_post1_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,9,15,__ERR) 1631 #define wr_txfir_post1_post1_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0040,6,wr_val) 1632 #define rd_txfir_dc_level_post1_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,10,15,__ERR) 1633 #define wr_txfir_dc_level_post1_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0020,5,wr_val) 1634 #define rd_txfir_post1_post1_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,11,15,__ERR) 1635 #define wr_txfir_post1_post1_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0010,4,wr_val) 1636 #define rd_txfir_dc_level_post1_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,12,15,__ERR) 1637 #define wr_txfir_dc_level_post1_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0008,3,wr_val) 1638 #define rd_txfir_post1_post1_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,13,15,__ERR) 1639 #define wr_txfir_post1_post1_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0004,2,wr_val) 1640 #define rd_txfir_dc_level_post1_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,14,15,__ERR) 1641 #define wr_txfir_dc_level_post1_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0002,1,wr_val) 1642 #define rd_txfir_post1_post1_1x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11c,15,15,__ERR) 1643 #define wr_txfir_post1_post1_1x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11c,0x0001,0,wr_val) 1644 #define rd_txfir_dc_level_post1pre_2x_3() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,1,15,__ERR) 1645 #define wr_txfir_dc_level_post1pre_2x_3(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x4000,14,wr_val) 1646 #define rd_txfir_post1_post1pre_2x_3() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,2,15,__ERR) 1647 #define wr_txfir_post1_post1pre_2x_3(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x2000,13,wr_val) 1648 #define rd_txfir_pre_post1pre_2x_3() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,3,15,__ERR) 1649 #define wr_txfir_pre_post1pre_2x_3(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x1000,12,wr_val) 1650 #define rd_txfir_dc_level_post1pre_2x_2() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,4,15,__ERR) 1651 #define wr_txfir_dc_level_post1pre_2x_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0800,11,wr_val) 1652 #define rd_txfir_post1_post1pre_2x_2() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,5,15,__ERR) 1653 #define wr_txfir_post1_post1pre_2x_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0400,10,wr_val) 1654 #define rd_txfir_pre_post1pre_2x_2() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,6,15,__ERR) 1655 #define wr_txfir_pre_post1pre_2x_2(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0200,9,wr_val) 1656 #define rd_txfir_dc_level_post1pre_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,7,15,__ERR) 1657 #define wr_txfir_dc_level_post1pre_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0100,8,wr_val) 1658 #define rd_txfir_post1_post1pre_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,8,15,__ERR) 1659 #define wr_txfir_post1_post1pre_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0080,7,wr_val) 1660 #define rd_txfir_pre_post1pre_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,9,15,__ERR) 1661 #define wr_txfir_pre_post1pre_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0040,6,wr_val) 1662 #define rd_txfir_dc_level_post1pre_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,10,15,__ERR) 1663 #define wr_txfir_dc_level_post1pre_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0020,5,wr_val) 1664 #define rd_txfir_post1_post1pre_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,11,15,__ERR) 1665 #define wr_txfir_post1_post1pre_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0010,4,wr_val) 1666 #define rd_txfir_pre_post1pre_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,12,15,__ERR) 1667 #define wr_txfir_pre_post1pre_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0008,3,wr_val) 1668 #define rd_txfir_dc_level_post1pre_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,13,15,__ERR) 1669 #define wr_txfir_dc_level_post1pre_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0004,2,wr_val) 1670 #define rd_txfir_post1_post1pre_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,14,15,__ERR) 1671 #define wr_txfir_post1_post1pre_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0002,1,wr_val) 1672 #define rd_txfir_pre_post1pre_1x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11d,15,15,__ERR) 1673 #define wr_txfir_pre_post1pre_1x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11d,0x0001,0,wr_val) 1674 #define rd_txfir_dc_level_2x_1() _merlin16_pmd_rde_field_byte(sa__, 0xd11e,12,15,__ERR) 1675 #define wr_txfir_dc_level_2x_1(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11e,0x0008,3,wr_val) 1676 #define rd_txfir_dc_level_2x_0() _merlin16_pmd_rde_field_byte(sa__, 0xd11e,13,15,__ERR) 1677 #define wr_txfir_dc_level_2x_0(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11e,0x0004,2,wr_val) 1678 #define rd_txfir_dc_level_1x() _merlin16_pmd_rde_field_byte(sa__, 0xd11e,14,15,__ERR) 1679 #define wr_txfir_dc_level_1x(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11e,0x0002,1,wr_val) 1680 #define rd_txfir_dc_level_0p5x() _merlin16_pmd_rde_field_byte(sa__, 0xd11e,15,15,__ERR) 1681 #define wr_txfir_dc_level_0p5x(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd11e,0x0001,0,wr_val) 1682 #define rd_tx_pi_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,15,15,__ERR) 1683 #define wr_tx_pi_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0001,0,wr_val) 1684 #define rd_tx_pi_jitter_filter_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,14,15,__ERR) 1685 #define wr_tx_pi_jitter_filter_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0002,1,wr_val) 1686 #define rd_tx_pi_ext_ctrl_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,13,15,__ERR) 1687 #define wr_tx_pi_ext_ctrl_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0004,2,wr_val) 1688 #define rd_tx_pi_freq_override_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,12,15,__ERR) 1689 #define wr_tx_pi_freq_override_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0008,3,wr_val) 1690 #define rd_tx_pi_sj_gen_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,11,15,__ERR) 1691 #define wr_tx_pi_sj_gen_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0010,4,wr_val) 1692 #define rd_tx_pi_ssc_gen_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,10,15,__ERR) 1693 #define wr_tx_pi_ssc_gen_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0020,5,wr_val) 1694 #define rd_tx_pi_jit_ssc_freq_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd070,9,15,__ERR) 1695 #define wr_tx_pi_jit_ssc_freq_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0040,6,wr_val) 1696 #define rd_tx_pi_reset_code_dbg() _merlin16_pmd_rde_field_byte(sa__, 0xd070,8,15,__ERR) 1697 #define wr_tx_pi_reset_code_dbg(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0080,7,wr_val) 1698 #define rd_tx_pi_second_order_loop_en() _merlin16_pmd_rde_field_byte(sa__, 0xd070,7,15,__ERR) 1699 #define wr_tx_pi_second_order_loop_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0100,8,wr_val) 1700 #define rd_tx_pi_first_order_bwsel_integ() _merlin16_pmd_rde_field_byte(sa__, 0xd070,4,14,__ERR) 1701 #define wr_tx_pi_first_order_bwsel_integ(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x0c00,10,wr_val) 1702 #define rd_tx_pi_second_order_bwsel_integ() _merlin16_pmd_rde_field_byte(sa__, 0xd070,2,14,__ERR) 1703 #define wr_tx_pi_second_order_bwsel_integ(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x3000,12,wr_val) 1704 #define rd_tx_pi_frc_phase_step_mux_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd070,0,15,__ERR) 1705 #define wr_tx_pi_frc_phase_step_mux_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd070,0x8000,15,wr_val) 1706 #define rd_tx_pi_freq_override_val() _merlin16_pmd_rde_field_signed(sa__, 0xd071,1,1,__ERR) 1707 #define wr_tx_pi_freq_override_val(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd071,0x7fff,0,wr_val) 1708 #define rd_tx_pi_jit_freq_idx() _merlin16_pmd_rde_field_byte(sa__, 0xd072,10,10,__ERR) 1709 #define wr_tx_pi_jit_freq_idx(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd072,0x003f,0,wr_val) 1710 #define rd_tx_pi_jit_amp() _merlin16_pmd_rde_field_byte(sa__, 0xd072,2,10,__ERR) 1711 #define wr_tx_pi_jit_amp(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd072,0x3f00,8,wr_val) 1712 #define rd_tx_pi_phase_override() _merlin16_pmd_rde_field_byte(sa__, 0xd073,15,15,__ERR) 1713 #define wr_tx_pi_phase_override(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd073,0x0001,0,wr_val) 1714 #define rd_tx_pi_phase_strobe() _merlin16_pmd_rde_field_byte(sa__, 0xd073,14,15,__ERR) 1715 #define wr_tx_pi_phase_strobe(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd073,0x0002,1,wr_val) 1716 #define rd_tx_pi_phase_step_dir() _merlin16_pmd_rde_field_byte(sa__, 0xd073,13,15,__ERR) 1717 #define wr_tx_pi_phase_step_dir(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd073,0x0004,2,wr_val) 1718 #define rd_tx_pi_phase_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd073,11,15,__ERR) 1719 #define wr_tx_pi_phase_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd073,0x0010,4,wr_val) 1720 #define rd_tx_pi_phase_step_num() _merlin16_pmd_rde_field_byte(sa__, 0xd073,4,12,__ERR) 1721 #define wr_tx_pi_phase_step_num(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd073,0x0f00,8,wr_val) 1722 #define rd_tx_pi_ext_phase_bwsel_integ() _merlin16_pmd_rde_field_byte(sa__, 0xd073,1,13,__ERR) 1723 #define wr_tx_pi_ext_phase_bwsel_integ(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd073,0x7000,12,wr_val) 1724 #define rd_tx_pi_frz_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd074,15,15,__ERR) 1725 #define wr_tx_pi_frz_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd074,0x0001,0,wr_val) 1726 #define rd_tx_pi_frz_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd074,14,15,__ERR) 1727 #define wr_tx_pi_frz_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd074,0x0002,1,wr_val) 1728 #define rd_tx_pi_frz_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd074,13,15,__ERR) 1729 #define wr_tx_pi_frz_mode(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd074,0x0004,2,wr_val) 1730 #define rd_tx_pi_hs_fifo_phserr_invert() _merlin16_pmd_rde_field_byte(sa__, 0xd075,14,15,__ERR) 1731 #define wr_tx_pi_hs_fifo_phserr_invert(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0002,1,wr_val) 1732 #define rd_tx_pi_repeater_mode_en() _merlin16_pmd_rde_field_byte(sa__, 0xd075,13,15,__ERR) 1733 #define wr_tx_pi_repeater_mode_en(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0004,2,wr_val) 1734 #define rd_tx_pi_ext_pd_sel() _merlin16_pmd_rde_field_byte(sa__, 0xd075,12,15,__ERR) 1735 #define wr_tx_pi_ext_pd_sel(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0008,3,wr_val) 1736 #define rd_afe_tx_fifo_resetb() _merlin16_pmd_rde_field_byte(sa__, 0xd075,7,15,__ERR) 1737 #define wr_afe_tx_fifo_resetb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0100,8,wr_val) 1738 #define rd_afe_tx_fifo_resetb_frc_on() _merlin16_pmd_rde_field_byte(sa__, 0xd075,6,15,__ERR) 1739 #define wr_afe_tx_fifo_resetb_frc_on(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0200,9,wr_val) 1740 #define rd_tx_pi_pd_bypass_flt() _merlin16_pmd_rde_field_byte(sa__, 0xd075,5,15,__ERR) 1741 #define wr_tx_pi_pd_bypass_flt(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0400,10,wr_val) 1742 #define rd_tx_pi_pd_bypass_vco() _merlin16_pmd_rde_field_byte(sa__, 0xd075,4,15,__ERR) 1743 #define wr_tx_pi_pd_bypass_vco(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd075,0x0800,11,wr_val) 1744 #define rd_tx_pi_phase_cntr() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd078,9,9,__ERR) 1745 #define rd_tx_pi_integ1_reg() _merlin16_pmd_rde_field_signed(sa__, 0xd079,2,2,__ERR) 1746 #define rd_tx_pi_integ2_reg() _merlin16_pmd_rde_field_signed(sa__, 0xd07a,1,1,__ERR) 1747 #define rd_tx_pi_phase_err() _merlin16_pmd_rde_field_signed_byte(sa__, 0xd07b,10,10,__ERR) 1748 #define rd_st_afe_tx_fifo_resetb() _merlin16_pmd_rde_field_byte(sa__, 0xd07c,14,15,__ERR) 1749 #define rd_tx_pi_hs_fifo_phserr() _merlin16_pmd_rde_field_byte(sa__, 0xd07c,15,15,__ERR) 1750 #define rd_tx_fifo_ovfb_fall_edge_lh() _merlin16_pmd_rde_field_byte(sa__, 0xd07d,14,15,__ERR) 1751 #define rd_tx_fifo_ovfb() _merlin16_pmd_rde_field_byte(sa__, 0xd07d,15,15,__ERR) 1752 #define rd_tx_osr_mode_frc() _merlin16_pmd_rde_field_byte(sa__, 0xd190,0,15,__ERR) 1753 #define wr_tx_osr_mode_frc(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd190,0x8000,15,wr_val) 1754 #define rd_tx_osr_mode_frc_val() _merlin16_pmd_rde_field_byte(sa__, 0xd190,12,12,__ERR) 1755 #define wr_tx_osr_mode_frc_val(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd190,0x000f,0,wr_val) 1756 #define rd_tx_ln_dp_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd191,15,15,__ERR) 1757 #define wr_tx_ln_dp_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd191,0x0001,0,wr_val) 1758 #define rd_tx_ln_s_rstb() _merlin16_pmd_rde_field_byte(sa__, 0xd19e,15,15,__ERR) 1759 #define wr_tx_ln_s_rstb(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd19e,0x0001,0,wr_val) 1760 #define rd_pmd_ln_tx_dp_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd193,14,15,__ERR) 1761 #define wr_pmd_ln_tx_dp_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd193,0x0002,1,wr_val) 1762 #define rd_pmd_ln_tx_h_rstb_pkill() _merlin16_pmd_rde_field_byte(sa__, 0xd193,15,15,__ERR) 1763 #define wr_pmd_ln_tx_h_rstb_pkill(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd193,0x0001,0,wr_val) 1764 #define rd_tx_uc_ack_lane_dp_reset() _merlin16_pmd_rde_field_byte(sa__, 0xd195,14,15,__ERR) 1765 #define wr_tx_uc_ack_lane_dp_reset(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd195,0x0002,1,wr_val) 1766 #define rd_tx_uc_ack_lane_cfg_done() _merlin16_pmd_rde_field_byte(sa__, 0xd195,15,15,__ERR) 1767 #define wr_tx_uc_ack_lane_cfg_done(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd195,0x0001,0,wr_val) 1768 #define rd_tx_lane_dp_reset_state() _merlin16_pmd_rde_field_byte(sa__, 0xd199,13,13,__ERR) 1769 #define rd_tx_lane_reg_reset_occurred() _merlin16_pmd_rde_field_byte(sa__, 0xd196,15,15,__ERR) 1770 #define wr_tx_lane_reg_reset_occurred(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd196,0x0001,0,wr_val) 1771 #define rd_tx_multicast_mask_control() _merlin16_pmd_rde_field_byte(sa__, 0xd19a,15,15,__ERR) 1772 #define wr_tx_multicast_mask_control(wr_val) _merlin16_pmd_mwr_reg_byte(sa__, 0xd19a,0x0001,0,wr_val) 1773 #define rd_tx_multicast_mask_control_status() _merlin16_pmd_rde_field_byte(sa__, 0xd19b,11,15,__ERR) 1774 #define rd_tx_osr_mode() _merlin16_pmd_rde_field_byte(sa__, 0xd19b,12,12,__ERR) 1775 #define rd_tx_osr_mode_pin() _merlin16_pmd_rde_field_byte(sa__, 0xd19c,12,12,__ERR) 1776 #define rdc_txcom_cl72_max_wait_timer_period() _merlin16_pmd_rde_reg(sa__, 0xd130,__ERR) 1777 #define wrc_txcom_cl72_max_wait_timer_period(wr_val) merlin16_pmd_wr_reg(sa__, 0xd130,wr_val) 1778 #define rdc_txcom_cl72_wait_cntr_limit() _merlin16_pmd_rde_field(sa__, 0xd131,7,7,__ERR) 1779 #define wrc_txcom_cl72_wait_cntr_limit(wr_val) merlin16_pmd_mwr_reg(sa__, 0xd131,0x01ff,0,wr_val) 1780 1781 #define reg_rd_AMS_RX_RXCONTROL_0() _merlin16_pmd_rde_reg(sa__, 0xd090,__ERR) 1782 #define reg_wr_AMS_RX_RXCONTROL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd090,wr_val) 1783 #define reg_rd_AMS_RX_RXCONTROL_1() _merlin16_pmd_rde_reg(sa__, 0xd091,__ERR) 1784 #define reg_wr_AMS_RX_RXCONTROL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd091,wr_val) 1785 #define reg_rd_AMS_RX_RXCONTROL_2() _merlin16_pmd_rde_reg(sa__, 0xd092,__ERR) 1786 #define reg_wr_AMS_RX_RXCONTROL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd092,wr_val) 1787 #define reg_rd_AMS_RX_RXCONTROL_3() _merlin16_pmd_rde_reg(sa__, 0xd093,__ERR) 1788 #define reg_wr_AMS_RX_RXCONTROL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd093,wr_val) 1789 #define reg_rd_AMS_RX_RXCONTROL_4() _merlin16_pmd_rde_reg(sa__, 0xd094,__ERR) 1790 #define reg_wr_AMS_RX_RXCONTROL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd094,wr_val) 1791 #define reg_rd_AMS_RX_RXCONTROL_5() _merlin16_pmd_rde_reg(sa__, 0xd095,__ERR) 1792 #define reg_wr_AMS_RX_RXCONTROL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd095,wr_val) 1793 #define reg_rd_AMS_RX_RXCONTROL_6() _merlin16_pmd_rde_reg(sa__, 0xd096,__ERR) 1794 #define reg_wr_AMS_RX_RXCONTROL_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd096,wr_val) 1795 #define reg_rd_AMS_RX_RXCONTROL_7() _merlin16_pmd_rde_reg(sa__, 0xd097,__ERR) 1796 #define reg_wr_AMS_RX_RXCONTROL_7(wr_val) merlin16_pmd_wr_reg(sa__, 0xd097,wr_val) 1797 #define reg_rd_AMS_RX_RXINTCTRL() _merlin16_pmd_rde_reg(sa__, 0xd098,__ERR) 1798 #define reg_wr_AMS_RX_RXINTCTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd098,wr_val) 1799 #define reg_rd_AMS_RX_RXSTATUS() _merlin16_pmd_rde_reg(sa__, 0xd099,__ERR) 1800 #define reg_wr_AMS_RX_RXSTATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd099,wr_val) 1801 #define reg_rd_AMS_TX_TXCONTROL_0() _merlin16_pmd_rde_reg(sa__, 0xd0a0,__ERR) 1802 #define reg_wr_AMS_TX_TXCONTROL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a0,wr_val) 1803 #define reg_rd_AMS_TX_TXCONTROL_1() _merlin16_pmd_rde_reg(sa__, 0xd0a1,__ERR) 1804 #define reg_wr_AMS_TX_TXCONTROL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a1,wr_val) 1805 #define reg_rd_AMS_TX_TXCONTROL_2() _merlin16_pmd_rde_reg(sa__, 0xd0a2,__ERR) 1806 #define reg_wr_AMS_TX_TXCONTROL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a2,wr_val) 1807 #define reg_rd_AMS_TX_TXCONTROL_3() _merlin16_pmd_rde_reg(sa__, 0xd0a3,__ERR) 1808 #define reg_wr_AMS_TX_TXCONTROL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a3,wr_val) 1809 #define reg_rd_AMS_TX_TXCONTROL_4() _merlin16_pmd_rde_reg(sa__, 0xd0a4,__ERR) 1810 #define reg_wr_AMS_TX_TXCONTROL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a4,wr_val) 1811 #define reg_rd_AMS_TX_TXCONTROL_5() _merlin16_pmd_rde_reg(sa__, 0xd0a5,__ERR) 1812 #define reg_wr_AMS_TX_TXCONTROL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a5,wr_val) 1813 #define reg_rd_AMS_TX_TXCONTROL_6() _merlin16_pmd_rde_reg(sa__, 0xd0a6,__ERR) 1814 #define reg_wr_AMS_TX_TXCONTROL_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a6,wr_val) 1815 #define reg_rd_AMS_TX_TXCONTROL_7() _merlin16_pmd_rde_reg(sa__, 0xd0a7,__ERR) 1816 #define reg_wr_AMS_TX_TXCONTROL_7(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a7,wr_val) 1817 #define reg_rd_AMS_TX_TXCONTROL_8() _merlin16_pmd_rde_reg(sa__, 0xd0a8,__ERR) 1818 #define reg_wr_AMS_TX_TXCONTROL_8(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a8,wr_val) 1819 #define reg_rd_AMS_TX_TXINTCTRL() _merlin16_pmd_rde_reg(sa__, 0xd0a9,__ERR) 1820 #define reg_wr_AMS_TX_TXINTCTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0a9,wr_val) 1821 #define reg_rd_AMS_TX_TXSTATUS() _merlin16_pmd_rde_reg(sa__, 0xd0aa,__ERR) 1822 #define reg_wr_AMS_TX_TXSTATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0aa,wr_val) 1823 #define reg_rdc_AMS_COM_PLL_CTRL_0() _merlin16_pmd_rde_reg(sa__, 0xd0b0,__ERR) 1824 #define reg_wrc_AMS_COM_PLL_CTRL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b0,wr_val) 1825 #define reg_rdc_AMS_COM_PLL_CTRL_1() _merlin16_pmd_rde_reg(sa__, 0xd0b1,__ERR) 1826 #define reg_wrc_AMS_COM_PLL_CTRL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b1,wr_val) 1827 #define reg_rdc_AMS_COM_PLL_CTRL_2() _merlin16_pmd_rde_reg(sa__, 0xd0b2,__ERR) 1828 #define reg_wrc_AMS_COM_PLL_CTRL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b2,wr_val) 1829 #define reg_rdc_AMS_COM_PLL_CTRL_3() _merlin16_pmd_rde_reg(sa__, 0xd0b3,__ERR) 1830 #define reg_wrc_AMS_COM_PLL_CTRL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b3,wr_val) 1831 #define reg_rdc_AMS_COM_PLL_CTRL_4() _merlin16_pmd_rde_reg(sa__, 0xd0b4,__ERR) 1832 #define reg_wrc_AMS_COM_PLL_CTRL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b4,wr_val) 1833 #define reg_rdc_AMS_COM_PLL_CTRL_5() _merlin16_pmd_rde_reg(sa__, 0xd0b5,__ERR) 1834 #define reg_wrc_AMS_COM_PLL_CTRL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b5,wr_val) 1835 #define reg_rdc_AMS_COM_PLL_CTRL_6() _merlin16_pmd_rde_reg(sa__, 0xd0b6,__ERR) 1836 #define reg_wrc_AMS_COM_PLL_CTRL_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b6,wr_val) 1837 #define reg_rdc_AMS_COM_PLL_CTRL_7() _merlin16_pmd_rde_reg(sa__, 0xd0b7,__ERR) 1838 #define reg_wrc_AMS_COM_PLL_CTRL_7(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b7,wr_val) 1839 #define reg_rdc_AMS_COM_PLL_CTRL_8() _merlin16_pmd_rde_reg(sa__, 0xd0b8,__ERR) 1840 #define reg_wrc_AMS_COM_PLL_CTRL_8(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b8,wr_val) 1841 #define reg_rdc_AMS_COM_PLL_CTRL_9() _merlin16_pmd_rde_reg(sa__, 0xd0b9,__ERR) 1842 #define reg_wrc_AMS_COM_PLL_CTRL_9(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0b9,wr_val) 1843 #define reg_rdc_AMS_COM_PLL_CTRL_10() _merlin16_pmd_rde_reg(sa__, 0xd0ba,__ERR) 1844 #define reg_wrc_AMS_COM_PLL_CTRL_10(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0ba,wr_val) 1845 #define reg_rdc_AMS_COM_PLL_INT() _merlin16_pmd_rde_reg(sa__, 0xd0be,__ERR) 1846 #define reg_wrc_AMS_COM_PLL_INT(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0be,wr_val) 1847 #define reg_rdc_AMS_COM_PLL_STS() _merlin16_pmd_rde_reg(sa__, 0xd0bf,__ERR) 1848 #define reg_wrc_AMS_COM_PLL_STS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0bf,wr_val) 1849 #define reg_rd_CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152() _merlin16_pmd_rde_reg(sa__, 0x0098,__ERR) 1850 #define reg_wr_CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152(wr_val) merlin16_pmd_wr_reg(sa__, 0x0098,wr_val) 1851 #define reg_rd_CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153() _merlin16_pmd_rde_reg(sa__, 0x0099,__ERR) 1852 #define reg_wr_CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153(wr_val) merlin16_pmd_wr_reg(sa__, 0x0099,wr_val) 1853 #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150() _merlin16_pmd_rde_reg(sa__, 0x0096,__ERR) 1854 #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150(wr_val) merlin16_pmd_wr_reg(sa__, 0x0096,wr_val) 1855 #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151() _merlin16_pmd_rde_reg(sa__, 0x0097,__ERR) 1856 #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151(wr_val) merlin16_pmd_wr_reg(sa__, 0x0097,wr_val) 1857 #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154() _merlin16_pmd_rde_reg(sa__, 0x009a,__ERR) 1858 #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154(wr_val) merlin16_pmd_wr_reg(sa__, 0x009a,wr_val) 1859 #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155() _merlin16_pmd_rde_reg(sa__, 0x009b,__ERR) 1860 #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155(wr_val) merlin16_pmd_wr_reg(sa__, 0x009b,wr_val) 1861 #define reg_rd_CL72_USER_RX_CL72UR_CONTROL0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd050,__ERR) 1862 #define reg_wr_CL72_USER_RX_CL72UR_CONTROL0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd050,wr_val) 1863 #define reg_rd_CL72_USER_RX_CL72UR_CONTROL1_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd051,__ERR) 1864 #define reg_wr_CL72_USER_RX_CL72UR_CONTROL1_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd051,wr_val) 1865 #define reg_rd_CL72_USER_RX_CL72UR_CONTROL2_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd052,__ERR) 1866 #define reg_wr_CL72_USER_RX_CL72UR_CONTROL2_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd052,wr_val) 1867 #define reg_rd_CL72_USER_RX_CL72UR_STATUS0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd053,__ERR) 1868 #define reg_wr_CL72_USER_RX_CL72UR_STATUS0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd053,wr_val) 1869 #define reg_rd_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd054,__ERR) 1870 #define reg_wr_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd054,wr_val) 1871 #define reg_rd_CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd055,__ERR) 1872 #define reg_wr_CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd055,wr_val) 1873 #define reg_rd_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd056,__ERR) 1874 #define reg_wr_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd056,wr_val) 1875 #define reg_rd_CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd060,__ERR) 1876 #define reg_wr_CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd060,wr_val) 1877 #define reg_rd_CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE() _merlin16_pmd_rde_reg(sa__, 0xd061,__ERR) 1878 #define reg_wr_CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE(wr_val) merlin16_pmd_wr_reg(sa__, 0xd061,wr_val) 1879 #define reg_rd_CL72_USER_TX_CL72UT_CONTROL0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd062,__ERR) 1880 #define reg_wr_CL72_USER_TX_CL72UT_CONTROL0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd062,wr_val) 1881 #define reg_rd_CL72_USER_TX_CL72UT_CONTROL1_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd063,__ERR) 1882 #define reg_wr_CL72_USER_TX_CL72UT_CONTROL1_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd063,wr_val) 1883 #define reg_rd_CL72_USER_TX_CL72UT_CONTROL2_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd064,__ERR) 1884 #define reg_wr_CL72_USER_TX_CL72UT_CONTROL2_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd064,wr_val) 1885 #define reg_rd_CL72_USER_TX_CL72UT_CONTROL3_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd065,__ERR) 1886 #define reg_wr_CL72_USER_TX_CL72UT_CONTROL3_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd065,wr_val) 1887 #define reg_rd_CL72_USER_TX_CL72UT_STATUS0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd066,__ERR) 1888 #define reg_wr_CL72_USER_TX_CL72UT_STATUS0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd066,wr_val) 1889 #define reg_rd_CL72_USER_TX_CL72UT_CONTROL4_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd067,__ERR) 1890 #define reg_wr_CL72_USER_TX_CL72UT_CONTROL4_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd067,wr_val) 1891 #define reg_rdc_DIG_COM_B_LANE_ADDR_0() _merlin16_pmd_rde_reg(sa__, 0xd150,__ERR) 1892 #define reg_wrc_DIG_COM_B_LANE_ADDR_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd150,wr_val) 1893 #define reg_rdc_DIG_COM_B_LANE_ADDR_1() _merlin16_pmd_rde_reg(sa__, 0xd151,__ERR) 1894 #define reg_wrc_DIG_COM_B_LANE_ADDR_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd151,wr_val) 1895 #define reg_rdc_DIG_COM_B_LANE_ADDR_2() _merlin16_pmd_rde_reg(sa__, 0xd152,__ERR) 1896 #define reg_wrc_DIG_COM_B_LANE_ADDR_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd152,wr_val) 1897 #define reg_rdc_DIG_COM_B_LANE_ADDR_3() _merlin16_pmd_rde_reg(sa__, 0xd153,__ERR) 1898 #define reg_wrc_DIG_COM_B_LANE_ADDR_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd153,wr_val) 1899 #define reg_rdc_DIG_COM_REVID0() _merlin16_pmd_rde_reg(sa__, 0xd0f0,__ERR) 1900 #define reg_wrc_DIG_COM_REVID0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f0,wr_val) 1901 #define reg_rdc_DIG_COM_REVID1() _merlin16_pmd_rde_reg(sa__, 0xd0fa,__ERR) 1902 #define reg_wrc_DIG_COM_REVID1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0fa,wr_val) 1903 #define reg_rdc_DIG_COM_REVID2() _merlin16_pmd_rde_reg(sa__, 0xd0fe,__ERR) 1904 #define reg_wrc_DIG_COM_REVID2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0fe,wr_val) 1905 #define reg_rdc_DIG_COM_RESET_CONTROL_PMD() _merlin16_pmd_rde_reg(sa__, 0xd0f1,__ERR) 1906 #define reg_wrc_DIG_COM_RESET_CONTROL_PMD(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f1,wr_val) 1907 #define reg_rdc_DIG_COM_RESET_CONTROL_CORE_DP() _merlin16_pmd_rde_reg(sa__, 0xd0f2,__ERR) 1908 #define reg_wrc_DIG_COM_RESET_CONTROL_CORE_DP(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f2,wr_val) 1909 #define reg_rdc_DIG_COM_MASKDATA_REG() _merlin16_pmd_rde_reg(sa__, 0xd0f3,__ERR) 1910 #define reg_wrc_DIG_COM_MASKDATA_REG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f3,wr_val) 1911 #define reg_rdc_DIG_COM_TOP_USER_CONTROL_0() _merlin16_pmd_rde_reg(sa__, 0xd0f4,__ERR) 1912 #define reg_wrc_DIG_COM_TOP_USER_CONTROL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f4,wr_val) 1913 #define reg_rdc_DIG_COM_UC_ACK_CORE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd0f5,__ERR) 1914 #define reg_wrc_DIG_COM_UC_ACK_CORE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f5,wr_val) 1915 #define reg_rdc_DIG_COM_CORE_DP_RESET_STATE_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0f8,__ERR) 1916 #define reg_wrc_DIG_COM_CORE_DP_RESET_STATE_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f8,wr_val) 1917 #define reg_rdc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd0f6,__ERR) 1918 #define reg_wrc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f6,wr_val) 1919 #define reg_rdc_DIG_COM_RST_SEQ_TIMER_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd0f7,__ERR) 1920 #define reg_wrc_DIG_COM_RST_SEQ_TIMER_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f7,wr_val) 1921 #define reg_rdc_DIG_COM_PMD_CORE_MODE_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0f9,__ERR) 1922 #define reg_wrc_DIG_COM_PMD_CORE_MODE_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0f9,wr_val) 1923 #define reg_rd_DSC_A_CDR_STATUS_INTEG_REG() _merlin16_pmd_rde_reg(sa__, 0xd005,__ERR) 1924 #define reg_wr_DSC_A_CDR_STATUS_INTEG_REG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd005,wr_val) 1925 #define reg_rd_DSC_A_CDR_STATUS_PHASE_ERROR() _merlin16_pmd_rde_reg(sa__, 0xd006,__ERR) 1926 #define reg_wr_DSC_A_CDR_STATUS_PHASE_ERROR(wr_val) merlin16_pmd_wr_reg(sa__, 0xd006,wr_val) 1927 #define reg_rd_DSC_A_RX_PI_CNT_BIN_D() _merlin16_pmd_rde_reg(sa__, 0xd007,__ERR) 1928 #define reg_wr_DSC_A_RX_PI_CNT_BIN_D(wr_val) merlin16_pmd_wr_reg(sa__, 0xd007,wr_val) 1929 #define reg_rd_DSC_A_RX_PI_CNT_BIN_P() _merlin16_pmd_rde_reg(sa__, 0xd008,__ERR) 1930 #define reg_wr_DSC_A_RX_PI_CNT_BIN_P(wr_val) merlin16_pmd_wr_reg(sa__, 0xd008,wr_val) 1931 #define reg_rd_DSC_A_RX_PI_CNT_BIN_M() _merlin16_pmd_rde_reg(sa__, 0xd009,__ERR) 1932 #define reg_wr_DSC_A_RX_PI_CNT_BIN_M(wr_val) merlin16_pmd_wr_reg(sa__, 0xd009,wr_val) 1933 #define reg_rd_DSC_A_RX_PI_DIFF_BIN() _merlin16_pmd_rde_reg(sa__, 0xd00a,__ERR) 1934 #define reg_wr_DSC_A_RX_PI_DIFF_BIN(wr_val) merlin16_pmd_wr_reg(sa__, 0xd00a,wr_val) 1935 #define reg_rd_DSC_A_CDR_CONTROL_0() _merlin16_pmd_rde_reg(sa__, 0xd001,__ERR) 1936 #define reg_wr_DSC_A_CDR_CONTROL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd001,wr_val) 1937 #define reg_rd_DSC_A_CDR_CONTROL_1() _merlin16_pmd_rde_reg(sa__, 0xd002,__ERR) 1938 #define reg_wr_DSC_A_CDR_CONTROL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd002,wr_val) 1939 #define reg_rd_DSC_A_CDR_CONTROL_2() _merlin16_pmd_rde_reg(sa__, 0xd003,__ERR) 1940 #define reg_wr_DSC_A_CDR_CONTROL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd003,wr_val) 1941 #define reg_rd_DSC_A_TRNSUM_CNTL_5() _merlin16_pmd_rde_reg(sa__, 0xd00b,__ERR) 1942 #define reg_wr_DSC_A_TRNSUM_CNTL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd00b,wr_val) 1943 #define reg_rd_DSC_A_RX_PI_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd004,__ERR) 1944 #define reg_wr_DSC_A_RX_PI_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd004,wr_val) 1945 #define reg_rd_DSC_A_DSC_UC_CTRL() _merlin16_pmd_rde_reg(sa__, 0xd00d,__ERR) 1946 #define reg_wr_DSC_A_DSC_UC_CTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd00d,wr_val) 1947 #define reg_rd_DSC_A_DSC_SCRATCH() _merlin16_pmd_rde_reg(sa__, 0xd00e,__ERR) 1948 #define reg_wr_DSC_A_DSC_SCRATCH(wr_val) merlin16_pmd_wr_reg(sa__, 0xd00e,wr_val) 1949 #define reg_rd_DSC_B_DSC_SM_CTRL_0() _merlin16_pmd_rde_reg(sa__, 0xd010,__ERR) 1950 #define reg_wr_DSC_B_DSC_SM_CTRL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd010,wr_val) 1951 #define reg_rd_DSC_B_DSC_SM_CTRL_1() _merlin16_pmd_rde_reg(sa__, 0xd011,__ERR) 1952 #define reg_wr_DSC_B_DSC_SM_CTRL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd011,wr_val) 1953 #define reg_rd_DSC_B_DSC_SM_CTRL_2() _merlin16_pmd_rde_reg(sa__, 0xd012,__ERR) 1954 #define reg_wr_DSC_B_DSC_SM_CTRL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd012,wr_val) 1955 #define reg_rd_DSC_B_DSC_SM_CTRL_3() _merlin16_pmd_rde_reg(sa__, 0xd013,__ERR) 1956 #define reg_wr_DSC_B_DSC_SM_CTRL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd013,wr_val) 1957 #define reg_rd_DSC_B_DSC_SM_CTRL_4() _merlin16_pmd_rde_reg(sa__, 0xd014,__ERR) 1958 #define reg_wr_DSC_B_DSC_SM_CTRL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd014,wr_val) 1959 #define reg_rd_DSC_B_DSC_SM_CTRL_5() _merlin16_pmd_rde_reg(sa__, 0xd015,__ERR) 1960 #define reg_wr_DSC_B_DSC_SM_CTRL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd015,wr_val) 1961 #define reg_rd_DSC_B_DSC_SM_CTRL_6() _merlin16_pmd_rde_reg(sa__, 0xd016,__ERR) 1962 #define reg_wr_DSC_B_DSC_SM_CTRL_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd016,wr_val) 1963 #define reg_rd_DSC_B_DSC_SM_CTRL_7() _merlin16_pmd_rde_reg(sa__, 0xd017,__ERR) 1964 #define reg_wr_DSC_B_DSC_SM_CTRL_7(wr_val) merlin16_pmd_wr_reg(sa__, 0xd017,wr_val) 1965 #define reg_rd_DSC_B_DSC_SM_CTRL_8() _merlin16_pmd_rde_reg(sa__, 0xd018,__ERR) 1966 #define reg_wr_DSC_B_DSC_SM_CTRL_8(wr_val) merlin16_pmd_wr_reg(sa__, 0xd018,wr_val) 1967 #define reg_rd_DSC_B_DSC_SM_CTRL_9() _merlin16_pmd_rde_reg(sa__, 0xd019,__ERR) 1968 #define reg_wr_DSC_B_DSC_SM_CTRL_9(wr_val) merlin16_pmd_wr_reg(sa__, 0xd019,wr_val) 1969 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT() _merlin16_pmd_rde_reg(sa__, 0xd01b,__ERR) 1970 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT(wr_val) merlin16_pmd_wr_reg(sa__, 0xd01b,wr_val) 1971 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT() _merlin16_pmd_rde_reg(sa__, 0xd01c,__ERR) 1972 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT(wr_val) merlin16_pmd_wr_reg(sa__, 0xd01c,wr_val) 1973 #define reg_rd_DSC_B_DSC_SM_STATUS_RESTART() _merlin16_pmd_rde_reg(sa__, 0xd01d,__ERR) 1974 #define reg_wr_DSC_B_DSC_SM_STATUS_RESTART(wr_val) merlin16_pmd_wr_reg(sa__, 0xd01d,wr_val) 1975 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE() _merlin16_pmd_rde_reg(sa__, 0xd01e,__ERR) 1976 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE(wr_val) merlin16_pmd_wr_reg(sa__, 0xd01e,wr_val) 1977 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_LOCK() _merlin16_pmd_rde_reg(sa__, 0xd01a,__ERR) 1978 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_LOCK(wr_val) merlin16_pmd_wr_reg(sa__, 0xd01a,wr_val) 1979 #define reg_rd_DSC_C_DFE_1_CTL() _merlin16_pmd_rde_reg(sa__, 0xd021,__ERR) 1980 #define reg_wr_DSC_C_DFE_1_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd021,wr_val) 1981 #define reg_rd_DSC_C_DFE_2_CTL() _merlin16_pmd_rde_reg(sa__, 0xd022,__ERR) 1982 #define reg_wr_DSC_C_DFE_2_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd022,wr_val) 1983 #define reg_rd_DSC_C_DFE_3_CTL() _merlin16_pmd_rde_reg(sa__, 0xd023,__ERR) 1984 #define reg_wr_DSC_C_DFE_3_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd023,wr_val) 1985 #define reg_rd_DSC_C_DFE_4_CTL() _merlin16_pmd_rde_reg(sa__, 0xd024,__ERR) 1986 #define reg_wr_DSC_C_DFE_4_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd024,wr_val) 1987 #define reg_rd_DSC_C_DFE_5_CTL() _merlin16_pmd_rde_reg(sa__, 0xd025,__ERR) 1988 #define reg_wr_DSC_C_DFE_5_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd025,wr_val) 1989 #define reg_rd_DSC_C_DFE_PAT_CTL() _merlin16_pmd_rde_reg(sa__, 0xd026,__ERR) 1990 #define reg_wr_DSC_C_DFE_PAT_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd026,wr_val) 1991 #define reg_rd_DSC_C_DFE_COMMON_CTL() _merlin16_pmd_rde_reg(sa__, 0xd020,__ERR) 1992 #define reg_wr_DSC_C_DFE_COMMON_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd020,wr_val) 1993 #define reg_rd_DSC_C_HWTUNE_OVR_OVERRIDE() _merlin16_pmd_rde_reg(sa__, 0xd02b,__ERR) 1994 #define reg_wr_DSC_C_HWTUNE_OVR_OVERRIDE(wr_val) merlin16_pmd_wr_reg(sa__, 0xd02b,wr_val) 1995 #define reg_rd_DSC_C_VGA_CTL() _merlin16_pmd_rde_reg(sa__, 0xd02c,__ERR) 1996 #define reg_wr_DSC_C_VGA_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd02c,wr_val) 1997 #define reg_rd_DSC_C_VGA_PAT_EYEDIAG_CTL() _merlin16_pmd_rde_reg(sa__, 0xd02d,__ERR) 1998 #define reg_wr_DSC_C_VGA_PAT_EYEDIAG_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd02d,wr_val) 1999 #define reg_rd_DSC_C_P1_FRAC_OFFS_CTL() _merlin16_pmd_rde_reg(sa__, 0xd02e,__ERR) 2000 #define reg_wr_DSC_C_P1_FRAC_OFFS_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd02e,wr_val) 2001 #define reg_rd_DSC_C_VGA_P1_MISC_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd027,__ERR) 2002 #define reg_wr_DSC_C_VGA_P1_MISC_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd027,wr_val) 2003 #define reg_rd_DSC_C_SLICER_OFFSET_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd02a,__ERR) 2004 #define reg_wr_DSC_C_SLICER_OFFSET_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd02a,wr_val) 2005 #define reg_rd_DSC_C_DC_SLICER_OFFSET_CTL() _merlin16_pmd_rde_reg(sa__, 0xd029,__ERR) 2006 #define reg_wr_DSC_C_DC_SLICER_OFFSET_CTL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd029,wr_val) 2007 #define reg_rd_DSC_D_TRNSUM_CTL_1() _merlin16_pmd_rde_reg(sa__, 0xd030,__ERR) 2008 #define reg_wr_DSC_D_TRNSUM_CTL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd030,wr_val) 2009 #define reg_rd_DSC_D_TRNSUM_CTL_2() _merlin16_pmd_rde_reg(sa__, 0xd031,__ERR) 2010 #define reg_wr_DSC_D_TRNSUM_CTL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd031,wr_val) 2011 #define reg_rd_DSC_D_TRNSUM_CTL_3() _merlin16_pmd_rde_reg(sa__, 0xd032,__ERR) 2012 #define reg_wr_DSC_D_TRNSUM_CTL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd032,wr_val) 2013 #define reg_rd_DSC_D_TRNSUM_CTL_4() _merlin16_pmd_rde_reg(sa__, 0xd033,__ERR) 2014 #define reg_wr_DSC_D_TRNSUM_CTL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd033,wr_val) 2015 #define reg_rd_DSC_D_TRNSUM_STS_1() _merlin16_pmd_rde_reg(sa__, 0xd034,__ERR) 2016 #define reg_wr_DSC_D_TRNSUM_STS_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd034,wr_val) 2017 #define reg_rd_DSC_D_TRNSUM_STS_2() _merlin16_pmd_rde_reg(sa__, 0xd035,__ERR) 2018 #define reg_wr_DSC_D_TRNSUM_STS_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd035,wr_val) 2019 #define reg_rd_DSC_D_TRNSUM_STS_3() _merlin16_pmd_rde_reg(sa__, 0xd036,__ERR) 2020 #define reg_wr_DSC_D_TRNSUM_STS_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd036,wr_val) 2021 #define reg_rd_DSC_D_TRNSUM_STS_4() _merlin16_pmd_rde_reg(sa__, 0xd037,__ERR) 2022 #define reg_wr_DSC_D_TRNSUM_STS_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd037,wr_val) 2023 #define reg_rd_DSC_D_TRNSUM_STS_5() _merlin16_pmd_rde_reg(sa__, 0xd038,__ERR) 2024 #define reg_wr_DSC_D_TRNSUM_STS_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd038,wr_val) 2025 #define reg_rd_DSC_D_TRNSUM_STS_6() _merlin16_pmd_rde_reg(sa__, 0xd039,__ERR) 2026 #define reg_wr_DSC_D_TRNSUM_STS_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd039,wr_val) 2027 #define reg_rd_DSC_D_VGA_P1EYEDIAG_STS() _merlin16_pmd_rde_reg(sa__, 0xd03a,__ERR) 2028 #define reg_wr_DSC_D_VGA_P1EYEDIAG_STS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd03a,wr_val) 2029 #define reg_rd_DSC_D_DFE_1_STS() _merlin16_pmd_rde_reg(sa__, 0xd03b,__ERR) 2030 #define reg_wr_DSC_D_DFE_1_STS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd03b,wr_val) 2031 #define reg_rd_DSC_D_DFE_2_STS() _merlin16_pmd_rde_reg(sa__, 0xd03c,__ERR) 2032 #define reg_wr_DSC_D_DFE_2_STS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd03c,wr_val) 2033 #define reg_rd_DSC_D_DFE_3_4_5_STS() _merlin16_pmd_rde_reg(sa__, 0xd03d,__ERR) 2034 #define reg_wr_DSC_D_DFE_3_4_5_STS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd03d,wr_val) 2035 #define reg_rd_DSC_D_VGA_TAP_BIN() _merlin16_pmd_rde_reg(sa__, 0xd03e,__ERR) 2036 #define reg_wr_DSC_D_VGA_TAP_BIN(wr_val) merlin16_pmd_wr_reg(sa__, 0xd03e,wr_val) 2037 #define reg_rd_DSC_E_CTRL() _merlin16_pmd_rde_reg(sa__, 0xd040,__ERR) 2038 #define reg_wr_DSC_E_CTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd040,wr_val) 2039 #define reg_rd_DSC_E_PF_CTRL() _merlin16_pmd_rde_reg(sa__, 0xd041,__ERR) 2040 #define reg_wr_DSC_E_PF_CTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd041,wr_val) 2041 #define reg_rd_DSC_E_PF2_LOWP_CTRL() _merlin16_pmd_rde_reg(sa__, 0xd042,__ERR) 2042 #define reg_wr_DSC_E_PF2_LOWP_CTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd042,wr_val) 2043 #define reg_rd_DSC_F_DATA_ODD_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd141,__ERR) 2044 #define reg_wr_DSC_F_DATA_ODD_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd141,wr_val) 2045 #define reg_rd_DSC_F_DATA_EVEN_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd142,__ERR) 2046 #define reg_wr_DSC_F_DATA_EVEN_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd142,wr_val) 2047 #define reg_rd_DSC_F_P1_ODD_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd143,__ERR) 2048 #define reg_wr_DSC_F_P1_ODD_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd143,wr_val) 2049 #define reg_rd_DSC_F_P1_EVEN_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd144,__ERR) 2050 #define reg_wr_DSC_F_P1_EVEN_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd144,wr_val) 2051 #define reg_rd_DSC_F_M1_ODD_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd145,__ERR) 2052 #define reg_wr_DSC_F_M1_ODD_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd145,wr_val) 2053 #define reg_rd_DSC_F_M1_EVEN_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd146,__ERR) 2054 #define reg_wr_DSC_F_M1_EVEN_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd146,wr_val) 2055 #define reg_rd_DSC_F_DC_OFFSET() _merlin16_pmd_rde_reg(sa__, 0xd147,__ERR) 2056 #define reg_wr_DSC_F_DC_OFFSET(wr_val) merlin16_pmd_wr_reg(sa__, 0xd147,wr_val) 2057 #define reg_rdc_MDIO_BLK_ADDR_BLK_ADDR() _merlin16_pmd_rde_reg(sa__, 0xffdf,__ERR) 2058 #define reg_wrc_MDIO_BLK_ADDR_BLK_ADDR(wr_val) merlin16_pmd_wr_reg(sa__, 0xffdf,wr_val) 2059 #define reg_rdc_MDIO_CL22_IEEE_ACC_CTRL() _merlin16_pmd_rde_reg(sa__, 0x000d,__ERR) 2060 #define reg_wrc_MDIO_CL22_IEEE_ACC_CTRL(wr_val) merlin16_pmd_wr_reg(sa__, 0x000d,wr_val) 2061 #define reg_rdc_MDIO_CL22_IEEE_ACC_ADDR_DATA() _merlin16_pmd_rde_reg(sa__, 0x000e,__ERR) 2062 #define reg_wrc_MDIO_CL22_IEEE_ACC_ADDR_DATA(wr_val) merlin16_pmd_wr_reg(sa__, 0x000e,wr_val) 2063 #define reg_rdc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR() _merlin16_pmd_rde_reg(sa__, 0xffdc,__ERR) 2064 #define reg_wrc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR(wr_val) merlin16_pmd_wr_reg(sa__, 0xffdc,wr_val) 2065 #define reg_rdc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT() _merlin16_pmd_rde_reg(sa__, 0xffdd,__ERR) 2066 #define reg_wrc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT(wr_val) merlin16_pmd_wr_reg(sa__, 0xffdd,wr_val) 2067 #define reg_rdc_MDIO_MMDSEL_AER_MDIO_AER() _merlin16_pmd_rde_reg(sa__, 0xffde,__ERR) 2068 #define reg_wrc_MDIO_MMDSEL_AER_MDIO_AER(wr_val) merlin16_pmd_wr_reg(sa__, 0xffde,wr_val) 2069 #define reg_rdc_MICRO_A_COM_CLOCK_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd200,__ERR) 2070 #define reg_wrc_MICRO_A_COM_CLOCK_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd200,wr_val) 2071 #define reg_rdc_MICRO_A_COM_RESET_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd201,__ERR) 2072 #define reg_wrc_MICRO_A_COM_RESET_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd201,wr_val) 2073 #define reg_rdc_MICRO_A_COM_AHB_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd202,__ERR) 2074 #define reg_wrc_MICRO_A_COM_AHB_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd202,wr_val) 2075 #define reg_rdc_MICRO_A_COM_AHB_STATUS0() _merlin16_pmd_rde_reg(sa__, 0xd203,__ERR) 2076 #define reg_wrc_MICRO_A_COM_AHB_STATUS0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd203,wr_val) 2077 #define reg_rdc_MICRO_A_COM_AHB_WRADDR_LSW() _merlin16_pmd_rde_reg(sa__, 0xd204,__ERR) 2078 #define reg_wrc_MICRO_A_COM_AHB_WRADDR_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd204,wr_val) 2079 #define reg_rdc_MICRO_A_COM_AHB_WRADDR_MSW() _merlin16_pmd_rde_reg(sa__, 0xd205,__ERR) 2080 #define reg_wrc_MICRO_A_COM_AHB_WRADDR_MSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd205,wr_val) 2081 #define reg_rdc_MICRO_A_COM_AHB_WRDATA_LSW() _merlin16_pmd_rde_reg(sa__, 0xd206,__ERR) 2082 #define reg_wrc_MICRO_A_COM_AHB_WRDATA_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd206,wr_val) 2083 #define reg_rdc_MICRO_A_COM_AHB_WRDATA_MSW() _merlin16_pmd_rde_reg(sa__, 0xd207,__ERR) 2084 #define reg_wrc_MICRO_A_COM_AHB_WRDATA_MSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd207,wr_val) 2085 #define reg_rdc_MICRO_A_COM_AHB_RDADDR_LSW() _merlin16_pmd_rde_reg(sa__, 0xd208,__ERR) 2086 #define reg_wrc_MICRO_A_COM_AHB_RDADDR_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd208,wr_val) 2087 #define reg_rdc_MICRO_A_COM_AHB_RDADDR_MSW() _merlin16_pmd_rde_reg(sa__, 0xd209,__ERR) 2088 #define reg_wrc_MICRO_A_COM_AHB_RDADDR_MSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd209,wr_val) 2089 #define reg_rdc_MICRO_A_COM_AHB_RDDATA_LSW() _merlin16_pmd_rde_reg(sa__, 0xd20a,__ERR) 2090 #define reg_wrc_MICRO_A_COM_AHB_RDDATA_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd20a,wr_val) 2091 #define reg_rdc_MICRO_A_COM_AHB_RDDATA_MSW() _merlin16_pmd_rde_reg(sa__, 0xd20b,__ERR) 2092 #define reg_wrc_MICRO_A_COM_AHB_RDDATA_MSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd20b,wr_val) 2093 #define reg_rdc_MICRO_A_COM_PRAMIF_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd20c,__ERR) 2094 #define reg_wrc_MICRO_A_COM_PRAMIF_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd20c,wr_val) 2095 #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW() _merlin16_pmd_rde_reg(sa__, 0xd20d,__ERR) 2096 #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd20d,wr_val) 2097 #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW() _merlin16_pmd_rde_reg(sa__, 0xd20e,__ERR) 2098 #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd20e,wr_val) 2099 #define reg_rdc_MICRO_B_COM_PVT_STATUS0() _merlin16_pmd_rde_reg(sa__, 0xd210,__ERR) 2100 #define reg_wrc_MICRO_B_COM_PVT_STATUS0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd210,wr_val) 2101 #define reg_rdc_MICRO_B_COM_RMI_TO_MICRO_MBOX0() _merlin16_pmd_rde_reg(sa__, 0xd211,__ERR) 2102 #define reg_wrc_MICRO_B_COM_RMI_TO_MICRO_MBOX0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd211,wr_val) 2103 #define reg_rdc_MICRO_B_COM_RMI_TO_MICRO_MBOX1() _merlin16_pmd_rde_reg(sa__, 0xd212,__ERR) 2104 #define reg_wrc_MICRO_B_COM_RMI_TO_MICRO_MBOX1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd212,wr_val) 2105 #define reg_rdc_MICRO_B_COM_MICRO_TO_RMI_MBOX0() _merlin16_pmd_rde_reg(sa__, 0xd213,__ERR) 2106 #define reg_wrc_MICRO_B_COM_MICRO_TO_RMI_MBOX0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd213,wr_val) 2107 #define reg_rdc_MICRO_B_COM_MICRO_TO_RMI_MBOX1() _merlin16_pmd_rde_reg(sa__, 0xd214,__ERR) 2108 #define reg_wrc_MICRO_B_COM_MICRO_TO_RMI_MBOX1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd214,wr_val) 2109 #define reg_rdc_MICRO_B_COM_RMI_MBOX_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd215,__ERR) 2110 #define reg_wrc_MICRO_B_COM_RMI_MBOX_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd215,wr_val) 2111 #define reg_rdc_MICRO_B_COM_RMI_AHB_CONTROL1() _merlin16_pmd_rde_reg(sa__, 0xd216,__ERR) 2112 #define reg_wrc_MICRO_B_COM_RMI_AHB_CONTROL1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd216,wr_val) 2113 #define reg_rdc_MICRO_B_COM_RMI_AHB_STATUS1() _merlin16_pmd_rde_reg(sa__, 0xd217,__ERR) 2114 #define reg_wrc_MICRO_B_COM_RMI_AHB_STATUS1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd217,wr_val) 2115 #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW() _merlin16_pmd_rde_reg(sa__, 0xd218,__ERR) 2116 #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd218,wr_val) 2117 #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW() _merlin16_pmd_rde_reg(sa__, 0xd219,__ERR) 2118 #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd219,wr_val) 2119 #define reg_rdc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW() _merlin16_pmd_rde_reg(sa__, 0xd21a,__ERR) 2120 #define reg_wrc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW(wr_val) merlin16_pmd_wr_reg(sa__, 0xd21a,wr_val) 2121 #define reg_rdc_MICRO_B_COM_RMI_PVT_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd21b,__ERR) 2122 #define reg_wrc_MICRO_B_COM_RMI_PVT_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd21b,wr_val) 2123 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCCONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd220,__ERR) 2124 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCCONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd220,wr_val) 2125 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCCONTRO1() _merlin16_pmd_rde_reg(sa__, 0xd221,__ERR) 2126 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCCONTRO1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd221,wr_val) 2127 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCSTATUS0() _merlin16_pmd_rde_reg(sa__, 0xd222,__ERR) 2128 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCSTATUS0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd222,wr_val) 2129 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCSTATUS1() _merlin16_pmd_rde_reg(sa__, 0xd223,__ERR) 2130 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCSTATUS1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd223,wr_val) 2131 #define reg_rdc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd224,__ERR) 2132 #define reg_wrc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd224,wr_val) 2133 #define reg_rdc_MICRO_C_COM_RAM_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd225,__ERR) 2134 #define reg_wrc_MICRO_C_COM_RAM_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd225,wr_val) 2135 #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_STATUS0() _merlin16_pmd_rde_reg(sa__, 0xd227,__ERR) 2136 #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_STATUS0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd227,wr_val) 2137 #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd226,__ERR) 2138 #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd226,wr_val) 2139 #define reg_rdc_MICRO_C_COM_RMI_PMI_IF_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd228,__ERR) 2140 #define reg_wrc_MICRO_C_COM_RMI_PMI_IF_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd228,wr_val) 2141 #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd229,__ERR) 2142 #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd229,wr_val) 2143 #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0() _merlin16_pmd_rde_reg(sa__, 0xd22a,__ERR) 2144 #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd22a,wr_val) 2145 #define reg_rdc_PATT_GEN_COM_SEQ_0() _merlin16_pmd_rde_reg(sa__, 0xd100,__ERR) 2146 #define reg_wrc_PATT_GEN_COM_SEQ_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd100,wr_val) 2147 #define reg_rdc_PATT_GEN_COM_SEQ_1() _merlin16_pmd_rde_reg(sa__, 0xd101,__ERR) 2148 #define reg_wrc_PATT_GEN_COM_SEQ_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd101,wr_val) 2149 #define reg_rdc_PATT_GEN_COM_SEQ_2() _merlin16_pmd_rde_reg(sa__, 0xd102,__ERR) 2150 #define reg_wrc_PATT_GEN_COM_SEQ_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd102,wr_val) 2151 #define reg_rdc_PATT_GEN_COM_SEQ_3() _merlin16_pmd_rde_reg(sa__, 0xd103,__ERR) 2152 #define reg_wrc_PATT_GEN_COM_SEQ_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd103,wr_val) 2153 #define reg_rdc_PATT_GEN_COM_SEQ_4() _merlin16_pmd_rde_reg(sa__, 0xd104,__ERR) 2154 #define reg_wrc_PATT_GEN_COM_SEQ_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd104,wr_val) 2155 #define reg_rdc_PATT_GEN_COM_SEQ_5() _merlin16_pmd_rde_reg(sa__, 0xd105,__ERR) 2156 #define reg_wrc_PATT_GEN_COM_SEQ_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd105,wr_val) 2157 #define reg_rdc_PATT_GEN_COM_SEQ_6() _merlin16_pmd_rde_reg(sa__, 0xd106,__ERR) 2158 #define reg_wrc_PATT_GEN_COM_SEQ_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd106,wr_val) 2159 #define reg_rdc_PATT_GEN_COM_SEQ_7() _merlin16_pmd_rde_reg(sa__, 0xd107,__ERR) 2160 #define reg_wrc_PATT_GEN_COM_SEQ_7(wr_val) merlin16_pmd_wr_reg(sa__, 0xd107,wr_val) 2161 #define reg_rdc_PATT_GEN_COM_SEQ_8() _merlin16_pmd_rde_reg(sa__, 0xd108,__ERR) 2162 #define reg_wrc_PATT_GEN_COM_SEQ_8(wr_val) merlin16_pmd_wr_reg(sa__, 0xd108,wr_val) 2163 #define reg_rdc_PATT_GEN_COM_SEQ_9() _merlin16_pmd_rde_reg(sa__, 0xd109,__ERR) 2164 #define reg_wrc_PATT_GEN_COM_SEQ_9(wr_val) merlin16_pmd_wr_reg(sa__, 0xd109,wr_val) 2165 #define reg_rdc_PATT_GEN_COM_SEQ_10() _merlin16_pmd_rde_reg(sa__, 0xd10a,__ERR) 2166 #define reg_wrc_PATT_GEN_COM_SEQ_10(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10a,wr_val) 2167 #define reg_rdc_PATT_GEN_COM_SEQ_11() _merlin16_pmd_rde_reg(sa__, 0xd10b,__ERR) 2168 #define reg_wrc_PATT_GEN_COM_SEQ_11(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10b,wr_val) 2169 #define reg_rdc_PATT_GEN_COM_SEQ_12() _merlin16_pmd_rde_reg(sa__, 0xd10c,__ERR) 2170 #define reg_wrc_PATT_GEN_COM_SEQ_12(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10c,wr_val) 2171 #define reg_rdc_PATT_GEN_COM_SEQ_13() _merlin16_pmd_rde_reg(sa__, 0xd10d,__ERR) 2172 #define reg_wrc_PATT_GEN_COM_SEQ_13(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10d,wr_val) 2173 #define reg_rdc_PATT_GEN_COM_SEQ_14() _merlin16_pmd_rde_reg(sa__, 0xd10e,__ERR) 2174 #define reg_wrc_PATT_GEN_COM_SEQ_14(wr_val) merlin16_pmd_wr_reg(sa__, 0xd10e,wr_val) 2175 #define reg_rdc_PLL_CAL_COM_CTL_0() _merlin16_pmd_rde_reg(sa__, 0xd120,__ERR) 2176 #define reg_wrc_PLL_CAL_COM_CTL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd120,wr_val) 2177 #define reg_rdc_PLL_CAL_COM_CTL_1() _merlin16_pmd_rde_reg(sa__, 0xd121,__ERR) 2178 #define reg_wrc_PLL_CAL_COM_CTL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd121,wr_val) 2179 #define reg_rdc_PLL_CAL_COM_CTL_2() _merlin16_pmd_rde_reg(sa__, 0xd122,__ERR) 2180 #define reg_wrc_PLL_CAL_COM_CTL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd122,wr_val) 2181 #define reg_rdc_PLL_CAL_COM_CTL_3() _merlin16_pmd_rde_reg(sa__, 0xd123,__ERR) 2182 #define reg_wrc_PLL_CAL_COM_CTL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd123,wr_val) 2183 #define reg_rdc_PLL_CAL_COM_CTL_4() _merlin16_pmd_rde_reg(sa__, 0xd124,__ERR) 2184 #define reg_wrc_PLL_CAL_COM_CTL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd124,wr_val) 2185 #define reg_rdc_PLL_CAL_COM_CTL_5() _merlin16_pmd_rde_reg(sa__, 0xd125,__ERR) 2186 #define reg_wrc_PLL_CAL_COM_CTL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd125,wr_val) 2187 #define reg_rdc_PLL_CAL_COM_CTL_6() _merlin16_pmd_rde_reg(sa__, 0xd126,__ERR) 2188 #define reg_wrc_PLL_CAL_COM_CTL_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd126,wr_val) 2189 #define reg_rdc_PLL_CAL_COM_STS_0() _merlin16_pmd_rde_reg(sa__, 0xd128,__ERR) 2190 #define reg_wrc_PLL_CAL_COM_STS_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd128,wr_val) 2191 #define reg_rdc_PLL_CAL_COM_STS_1() _merlin16_pmd_rde_reg(sa__, 0xd129,__ERR) 2192 #define reg_wrc_PLL_CAL_COM_STS_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd129,wr_val) 2193 #define reg_rdc_PLL_CAL_COM_STS_2() _merlin16_pmd_rde_reg(sa__, 0xd12a,__ERR) 2194 #define reg_wrc_PLL_CAL_COM_STS_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd12a,wr_val) 2195 #define reg_rdc_PLL_CAL_COM_STS_3() _merlin16_pmd_rde_reg(sa__, 0xd12b,__ERR) 2196 #define reg_wrc_PLL_CAL_COM_STS_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd12b,wr_val) 2197 #define reg_rdc_PLL_CAL_COM_STS_4() _merlin16_pmd_rde_reg(sa__, 0xd12c,__ERR) 2198 #define reg_wrc_PLL_CAL_COM_STS_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd12c,wr_val) 2199 #define reg_rdc_PLL_CAL_COM_STS_5() _merlin16_pmd_rde_reg(sa__, 0xd12d,__ERR) 2200 #define reg_wrc_PLL_CAL_COM_STS_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd12d,wr_val) 2201 #define reg_rdc_PLL_CAL_COM_STS_6() _merlin16_pmd_rde_reg(sa__, 0xd12e,__ERR) 2202 #define reg_wrc_PLL_CAL_COM_STS_6(wr_val) merlin16_pmd_wr_reg(sa__, 0xd12e,wr_val) 2203 #define reg_rd_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd161,__ERR) 2204 #define reg_wr_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd161,wr_val) 2205 #define reg_rd_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd167,__ERR) 2206 #define reg_wr_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd167,wr_val) 2207 #define reg_rd_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd164,__ERR) 2208 #define reg_wr_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd164,wr_val) 2209 #define reg_rd_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd162,__ERR) 2210 #define reg_wr_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd162,wr_val) 2211 #define reg_rd_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd163,__ERR) 2212 #define reg_wr_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd163,wr_val) 2213 #define reg_rd_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd168,__ERR) 2214 #define reg_wr_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd168,wr_val) 2215 #define reg_rd_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd16c,__ERR) 2216 #define reg_wr_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd16c,wr_val) 2217 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd180,__ERR) 2218 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd180,wr_val) 2219 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd181,__ERR) 2220 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd181,wr_val) 2221 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd18e,__ERR) 2222 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd18e,wr_val) 2223 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd183,__ERR) 2224 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd183,wr_val) 2225 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd185,__ERR) 2226 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd185,wr_val) 2227 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd189,__ERR) 2228 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd189,wr_val) 2229 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd186,__ERR) 2230 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd186,wr_val) 2231 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd18a,__ERR) 2232 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd18a,wr_val) 2233 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_pmd_rde_reg(sa__, 0xd18b,__ERR) 2234 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_pmd_wr_reg(sa__, 0xd18b,wr_val) 2235 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd18c,__ERR) 2236 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd18c,wr_val) 2237 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd080,__ERR) 2238 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd080,wr_val) 2239 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd081,__ERR) 2240 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd081,wr_val) 2241 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd08e,__ERR) 2242 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd08e,wr_val) 2243 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd083,__ERR) 2244 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd083,wr_val) 2245 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd085,__ERR) 2246 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd085,wr_val) 2247 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd089,__ERR) 2248 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd089,wr_val) 2249 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd086,__ERR) 2250 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd086,wr_val) 2251 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd08a,__ERR) 2252 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd08a,wr_val) 2253 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_pmd_rde_reg(sa__, 0xd08b,__ERR) 2254 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_pmd_wr_reg(sa__, 0xd08b,wr_val) 2255 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd08c,__ERR) 2256 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd08c,wr_val) 2257 #define reg_rd_SIGDET_SDCTRL_0() _merlin16_pmd_rde_reg(sa__, 0xd0c0,__ERR) 2258 #define reg_wr_SIGDET_SDCTRL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0c0,wr_val) 2259 #define reg_rd_SIGDET_SDCTRL_1() _merlin16_pmd_rde_reg(sa__, 0xd0c1,__ERR) 2260 #define reg_wr_SIGDET_SDCTRL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0c1,wr_val) 2261 #define reg_rd_SIGDET_SDCTRL_2() _merlin16_pmd_rde_reg(sa__, 0xd0c2,__ERR) 2262 #define reg_wr_SIGDET_SDCTRL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0c2,wr_val) 2263 #define reg_rd_SIGDET_SDSTATUS_0() _merlin16_pmd_rde_reg(sa__, 0xd0c8,__ERR) 2264 #define reg_wr_SIGDET_SDSTATUS_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0c8,wr_val) 2265 #define reg_rd_SIGDET_SDSTATUS_1() _merlin16_pmd_rde_reg(sa__, 0xd0c9,__ERR) 2266 #define reg_wr_SIGDET_SDSTATUS_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0c9,wr_val) 2267 #define reg_rd_SIGDET_SDSTATUS_2() _merlin16_pmd_rde_reg(sa__, 0xd0ca,__ERR) 2268 #define reg_wr_SIGDET_SDSTATUS_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0ca,wr_val) 2269 #define reg_rd_SIGDET_SDSTATUS_3() _merlin16_pmd_rde_reg(sa__, 0xd0cb,__ERR) 2270 #define reg_wr_SIGDET_SDSTATUS_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0cb,wr_val) 2271 #define reg_rd_SIGDET_SDSTATUS_4() _merlin16_pmd_rde_reg(sa__, 0xd0cc,__ERR) 2272 #define reg_wr_SIGDET_SDSTATUS_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0cc,wr_val) 2273 #define reg_rdc_TEST_WRAPPER_CONTROL_0() _merlin16_pmd_rde_reg(sa__, 0xe000,__ERR) 2274 #define reg_wrc_TEST_WRAPPER_CONTROL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xe000,wr_val) 2275 #define reg_rdc_TEST_WRAPPER_STATUS_0() _merlin16_pmd_rde_reg(sa__, 0xe001,__ERR) 2276 #define reg_wrc_TEST_WRAPPER_STATUS_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xe001,wr_val) 2277 #define reg_rd_TLB_RX_RXPRBS_CHK_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0d1,__ERR) 2278 #define reg_wr_TLB_RX_RXPRBS_CHK_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d1,wr_val) 2279 #define reg_rd_TLB_RX_RXPRBS_CHK_CNT_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0d0,__ERR) 2280 #define reg_wr_TLB_RX_RXPRBS_CHK_CNT_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d0,wr_val) 2281 #define reg_rd_TLB_RX_RXDIG_LPBK_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0d2,__ERR) 2282 #define reg_wr_TLB_RX_RXDIG_LPBK_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d2,wr_val) 2283 #define reg_rd_TLB_RX_RXMISC_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0d3,__ERR) 2284 #define reg_wr_TLB_RX_RXMISC_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d3,wr_val) 2285 #define reg_rd_TLB_RX_RXPRBS_CHK_EN_TIMER_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd0d4,__ERR) 2286 #define reg_wr_TLB_RX_RXPRBS_CHK_EN_TIMER_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d4,wr_val) 2287 #define reg_rd_TLB_RX_RXDIG_LPBK_PD_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0d8,__ERR) 2288 #define reg_wr_TLB_RX_RXDIG_LPBK_PD_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d8,wr_val) 2289 #define reg_rd_TLB_RX_RXPRBS_CHK_LOCK_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0d9,__ERR) 2290 #define reg_wr_TLB_RX_RXPRBS_CHK_LOCK_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d9,wr_val) 2291 #define reg_rd_TLB_RX_RXPRBS_CHK_ERR_CNT_MSB_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0da,__ERR) 2292 #define reg_wr_TLB_RX_RXPRBS_CHK_ERR_CNT_MSB_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0da,wr_val) 2293 #define reg_rd_TLB_RX_RXPRBS_CHK_ERR_CNT_LSB_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0db,__ERR) 2294 #define reg_wr_TLB_RX_RXPRBS_CHK_ERR_CNT_LSB_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0db,wr_val) 2295 #define reg_rd_TLB_RX_RXPMD_RX_LOCK_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0dc,__ERR) 2296 #define reg_wr_TLB_RX_RXPMD_RX_LOCK_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0dc,wr_val) 2297 #define reg_rd_TLB_RX_RXDBG_PMD_RX_LOCK_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0d6,__ERR) 2298 #define reg_wr_TLB_RX_RXDBG_PMD_RX_LOCK_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d6,wr_val) 2299 #define reg_rd_TLB_RX_RXUC_PMD_RX_LOCK_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0d7,__ERR) 2300 #define reg_wr_TLB_RX_RXUC_PMD_RX_LOCK_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d7,wr_val) 2301 #define reg_rd_TLB_RX_RXPRBS_CHK_BURST_ERR_CNT_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0d5,__ERR) 2302 #define reg_wr_TLB_RX_RXPRBS_CHK_BURST_ERR_CNT_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0d5,wr_val) 2303 #define reg_rd_TLB_TX_TXPATT_GEN_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0e0,__ERR) 2304 #define reg_wr_TLB_TX_TXPATT_GEN_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0e0,wr_val) 2305 #define reg_rd_TLB_TX_TXPRBS_GEN_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0e1,__ERR) 2306 #define reg_wr_TLB_TX_TXPRBS_GEN_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0e1,wr_val) 2307 #define reg_rd_TLB_TX_TXRMT_LPBK_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0e2,__ERR) 2308 #define reg_wr_TLB_TX_TXRMT_LPBK_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0e2,wr_val) 2309 #define reg_rd_TLB_TX_TXMISC_CONFIG() _merlin16_pmd_rde_reg(sa__, 0xd0e3,__ERR) 2310 #define reg_wr_TLB_TX_TXMISC_CONFIG(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0e3,wr_val) 2311 #define reg_rd_TLB_TX_TXRMT_LPBK_PD_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd0e8,__ERR) 2312 #define reg_wr_TLB_TX_TXRMT_LPBK_PD_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd0e8,wr_val) 2313 #define reg_rd_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd171,__ERR) 2314 #define reg_wr_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd171,wr_val) 2315 #define reg_rd_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd177,__ERR) 2316 #define reg_wr_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd177,wr_val) 2317 #define reg_rd_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd174,__ERR) 2318 #define reg_wr_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd174,wr_val) 2319 #define reg_rd_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd172,__ERR) 2320 #define reg_wr_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd172,wr_val) 2321 #define reg_rd_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd173,__ERR) 2322 #define reg_wr_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd173,wr_val) 2323 #define reg_rd_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd17c,__ERR) 2324 #define reg_wr_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd17c,wr_val) 2325 #define reg_rd_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd17d,__ERR) 2326 #define reg_wr_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd17d,wr_val) 2327 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd110,__ERR) 2328 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd110,wr_val) 2329 #define reg_rd_TX_FED_MISC_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd111,__ERR) 2330 #define reg_wr_TX_FED_MISC_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd111,wr_val) 2331 #define reg_rd_TX_FED_MISC_STATUS0() _merlin16_pmd_rde_reg(sa__, 0xd112,__ERR) 2332 #define reg_wr_TX_FED_MISC_STATUS0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd112,wr_val) 2333 #define reg_rd_TX_FED_MICRO_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd113,__ERR) 2334 #define reg_wr_TX_FED_MICRO_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd113,wr_val) 2335 #define reg_rd_TX_FED_POST2_AFE_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd11b,__ERR) 2336 #define reg_wr_TX_FED_POST2_AFE_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd11b,wr_val) 2337 #define reg_rd_TX_FED_POST1_AFE_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd11c,__ERR) 2338 #define reg_wr_TX_FED_POST1_AFE_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd11c,wr_val) 2339 #define reg_rd_TX_FED_POST1PRE_AFE_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd11d,__ERR) 2340 #define reg_wr_TX_FED_POST1PRE_AFE_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd11d,wr_val) 2341 #define reg_rd_TX_FED_DC_LEVEL_AFE_CONTROL0() _merlin16_pmd_rde_reg(sa__, 0xd11e,__ERR) 2342 #define reg_wr_TX_FED_DC_LEVEL_AFE_CONTROL0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd11e,wr_val) 2343 #define reg_rd_TX_PI_TXPICONTROL_0() _merlin16_pmd_rde_reg(sa__, 0xd070,__ERR) 2344 #define reg_wr_TX_PI_TXPICONTROL_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd070,wr_val) 2345 #define reg_rd_TX_PI_TXPICONTROL_1() _merlin16_pmd_rde_reg(sa__, 0xd071,__ERR) 2346 #define reg_wr_TX_PI_TXPICONTROL_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd071,wr_val) 2347 #define reg_rd_TX_PI_TXPICONTROL_2() _merlin16_pmd_rde_reg(sa__, 0xd072,__ERR) 2348 #define reg_wr_TX_PI_TXPICONTROL_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd072,wr_val) 2349 #define reg_rd_TX_PI_TXPICONTROL_3() _merlin16_pmd_rde_reg(sa__, 0xd073,__ERR) 2350 #define reg_wr_TX_PI_TXPICONTROL_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd073,wr_val) 2351 #define reg_rd_TX_PI_TXPICONTROL_4() _merlin16_pmd_rde_reg(sa__, 0xd074,__ERR) 2352 #define reg_wr_TX_PI_TXPICONTROL_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd074,wr_val) 2353 #define reg_rd_TX_PI_TXPICONTROL_5() _merlin16_pmd_rde_reg(sa__, 0xd075,__ERR) 2354 #define reg_wr_TX_PI_TXPICONTROL_5(wr_val) merlin16_pmd_wr_reg(sa__, 0xd075,wr_val) 2355 #define reg_rd_TX_PI_TXPISTATUS_0() _merlin16_pmd_rde_reg(sa__, 0xd078,__ERR) 2356 #define reg_wr_TX_PI_TXPISTATUS_0(wr_val) merlin16_pmd_wr_reg(sa__, 0xd078,wr_val) 2357 #define reg_rd_TX_PI_TXPISTATUS_1() _merlin16_pmd_rde_reg(sa__, 0xd079,__ERR) 2358 #define reg_wr_TX_PI_TXPISTATUS_1(wr_val) merlin16_pmd_wr_reg(sa__, 0xd079,wr_val) 2359 #define reg_rd_TX_PI_TXPISTATUS_2() _merlin16_pmd_rde_reg(sa__, 0xd07a,__ERR) 2360 #define reg_wr_TX_PI_TXPISTATUS_2(wr_val) merlin16_pmd_wr_reg(sa__, 0xd07a,wr_val) 2361 #define reg_rd_TX_PI_TXPISTATUS_3() _merlin16_pmd_rde_reg(sa__, 0xd07b,__ERR) 2362 #define reg_wr_TX_PI_TXPISTATUS_3(wr_val) merlin16_pmd_wr_reg(sa__, 0xd07b,wr_val) 2363 #define reg_rd_TX_PI_TXPISTATUS_4() _merlin16_pmd_rde_reg(sa__, 0xd07c,__ERR) 2364 #define reg_wr_TX_PI_TXPISTATUS_4(wr_val) merlin16_pmd_wr_reg(sa__, 0xd07c,wr_val) 2365 #define reg_rd_TX_PI_TX_FIFO_OVFB_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd07d,__ERR) 2366 #define reg_wr_TX_PI_TX_FIFO_OVFB_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd07d,wr_val) 2367 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd190,__ERR) 2368 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd190,wr_val) 2369 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd191,__ERR) 2370 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd191,wr_val) 2371 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd19e,__ERR) 2372 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd19e,wr_val) 2373 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd193,__ERR) 2374 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd193,wr_val) 2375 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd195,__ERR) 2376 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd195,wr_val) 2377 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd199,__ERR) 2378 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd199,wr_val) 2379 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd196,__ERR) 2380 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd196,wr_val) 2381 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL() _merlin16_pmd_rde_reg(sa__, 0xd19a,__ERR) 2382 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL(wr_val) merlin16_pmd_wr_reg(sa__, 0xd19a,wr_val) 2383 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_pmd_rde_reg(sa__, 0xd19b,__ERR) 2384 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_pmd_wr_reg(sa__, 0xd19b,wr_val) 2385 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pmd_rde_reg(sa__, 0xd19c,__ERR) 2386 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pmd_wr_reg(sa__, 0xd19c,wr_val) 2387 #define reg_rdc_TX_COM_TXCOM_CONTROL0_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd130,__ERR) 2388 #define reg_wrc_TX_COM_TXCOM_CONTROL0_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd130,wr_val) 2389 #define reg_rdc_TX_COM_TXCOM_CONTROL1_REGISTER() _merlin16_pmd_rde_reg(sa__, 0xd131,__ERR) 2390 #define reg_wrc_TX_COM_TXCOM_CONTROL1_REGISTER(wr_val) merlin16_pmd_wr_reg(sa__, 0xd131,wr_val) 2391 2392 #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_lowzvdd(reg_value) extract_field((reg_value),15,15) 2393 #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_lowzgnd(reg_value) extract_field((reg_value),14,14) 2394 #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_cmult_ena(reg_value) extract_field((reg_value),13,13) 2395 #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_cm_ena(reg_value) extract_field((reg_value),12,12) 2396 #define ex_AMS_RX_RXCONTROL_0__ams_rx_en_rxck_test(reg_value) extract_field((reg_value),11,10) 2397 #define ex_AMS_RX_RXCONTROL_0__ams_rx_en_rxck_testport(reg_value) extract_field((reg_value),9,9) 2398 #define ex_AMS_RX_RXCONTROL_0__ams_rx_spare_0_1(reg_value) extract_field((reg_value),8,7) 2399 #define ex_AMS_RX_RXCONTROL_0__ams_rx_input_cm_sel(reg_value) extract_field((reg_value),6,6) 2400 #define ex_AMS_RX_RXCONTROL_0__ams_rx_vga_cm_sel(reg_value) extract_field((reg_value),5,5) 2401 #define ex_AMS_RX_RXCONTROL_0__ams_rx_rcm_sum(reg_value) extract_field((reg_value),4,4) 2402 #define ex_AMS_RX_RXCONTROL_0__ams_rx_sigdet_bypass(reg_value) extract_field((reg_value),3,3) 2403 #define ex_AMS_RX_RXCONTROL_0__ams_rx_sigdet_pwrdn(reg_value) extract_field((reg_value),2,2) 2404 #define ex_AMS_RX_RXCONTROL_0__ams_rx_cm_sel(reg_value) extract_field((reg_value),1,1) 2405 #define ex_AMS_RX_RXCONTROL_0__ams_rx_sum_pseudo_diff(reg_value) extract_field((reg_value),0,0) 2406 #define ex_AMS_RX_RXCONTROL_1__ams_rx_curr_dfe_2(reg_value) extract_field((reg_value),13,11) 2407 #define ex_AMS_RX_RXCONTROL_1__ams_rx_spare_1_0(reg_value) extract_field((reg_value),10,8) 2408 #define ex_AMS_RX_RXCONTROL_1__ams_rx_curr_pi(reg_value) extract_field((reg_value),7,5) 2409 #define ex_AMS_RX_RXCONTROL_1__ams_rx_curr_ctle(reg_value) extract_field((reg_value),4,2) 2410 #define ex_AMS_RX_RXCONTROL_1__ams_rx_vga_en_hgain(reg_value) extract_field((reg_value),1,1) 2411 #define ex_AMS_RX_RXCONTROL_1__ams_rx_vga_out_idle(reg_value) extract_field((reg_value),0,0) 2412 #define ex_AMS_RX_RXCONTROL_2__ams_rx_spare_2_0(reg_value) extract_field((reg_value),15,14) 2413 #define ex_AMS_RX_RXCONTROL_2__ams_rx_en_dfe_tap_fb(reg_value) extract_field((reg_value),13,9) 2414 #define ex_AMS_RX_RXCONTROL_2__ams_rx_curr_vga(reg_value) extract_field((reg_value),8,6) 2415 #define ex_AMS_RX_RXCONTROL_2__ams_rx_curr_dfe_summer(reg_value) extract_field((reg_value),5,3) 2416 #define ex_AMS_RX_RXCONTROL_2__ams_rx_curr_dfe_1(reg_value) extract_field((reg_value),2,0) 2417 #define ex_AMS_RX_RXCONTROL_3__ams_rx_ll_en(reg_value) extract_field((reg_value),14,14) 2418 #define ex_AMS_RX_RXCONTROL_3__ams_rx_seli1p25dfe(reg_value) extract_field((reg_value),13,13) 2419 #define ex_AMS_RX_RXCONTROL_3__ams_rx_i4deadzone(reg_value) extract_field((reg_value),12,12) 2420 #define ex_AMS_RX_RXCONTROL_3__ams_rx_curr_sigdet(reg_value) extract_field((reg_value),11,9) 2421 #define ex_AMS_RX_RXCONTROL_3__ams_rx_curr_vddr_afe(reg_value) extract_field((reg_value),8,6) 2422 #define ex_AMS_RX_RXCONTROL_3__ams_rx_os2x_mode_even_odd(reg_value) extract_field((reg_value),5,5) 2423 #define ex_AMS_RX_RXCONTROL_3__ams_rx_dfe_os2x_mode(reg_value) extract_field((reg_value),4,4) 2424 #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_20b_demux(reg_value) extract_field((reg_value),3,3) 2425 #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_clk16(reg_value) extract_field((reg_value),2,2) 2426 #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_clk33(reg_value) extract_field((reg_value),1,1) 2427 #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_vcctrl(reg_value) extract_field((reg_value),0,0) 2428 #define ex_AMS_RX_RXCONTROL_4__ams_rx_vga_pon(reg_value) extract_field((reg_value),15,12) 2429 #define ex_AMS_RX_RXCONTROL_4__ams_rx_oc_2x(reg_value) extract_field((reg_value),11,11) 2430 #define ex_AMS_RX_RXCONTROL_4__ams_rx_spare_4_0(reg_value) extract_field((reg_value),10,8) 2431 #define ex_AMS_RX_RXCONTROL_4__ams_rx_en_recclkdiv(reg_value) extract_field((reg_value),7,7) 2432 #define ex_AMS_RX_RXCONTROL_4__ams_rx_div3o4o5(reg_value) extract_field((reg_value),6,5) 2433 #define ex_AMS_RX_RXCONTROL_4__ams_rx_recclkdiv(reg_value) extract_field((reg_value),4,0) 2434 #define ex_AMS_RX_RXCONTROL_5__ams_rx_dcc2_phase_flip(reg_value) extract_field((reg_value),15,15) 2435 #define ex_AMS_RX_RXCONTROL_5__ams_rx_slcr_calib_range_sel(reg_value) extract_field((reg_value),14,14) 2436 #define ex_AMS_RX_RXCONTROL_5__ams_rx_pi_pd(reg_value) extract_field((reg_value),13,13) 2437 #define ex_AMS_RX_RXCONTROL_5__ams_rx_dcc1_phase_flip(reg_value) extract_field((reg_value),12,12) 2438 #define ex_AMS_RX_RXCONTROL_5__ams_rx_en_dfeclk(reg_value) extract_field((reg_value),11,11) 2439 #define ex_AMS_RX_RXCONTROL_5__ams_rx_ctle_gain_ctrl(reg_value) extract_field((reg_value),10,7) 2440 #define ex_AMS_RX_RXCONTROL_5__ams_rx_curr_in_offset(reg_value) extract_field((reg_value),6,4) 2441 #define ex_AMS_RX_RXCONTROL_5__ams_rx_pon(reg_value) extract_field((reg_value),3,0) 2442 #define ex_AMS_RX_RXCONTROL_6__ams_rx_sigdet_offset_correction_pos(reg_value) extract_field((reg_value),12,8) 2443 #define ex_AMS_RX_RXCONTROL_6__ams_rx_sigdet_calibration_select(reg_value) extract_field((reg_value),7,7) 2444 #define ex_AMS_RX_RXCONTROL_6__ams_rx_sum_gain_ctrl(reg_value) extract_field((reg_value),6,3) 2445 #define ex_AMS_RX_RXCONTROL_6__ams_rx_en_sigdet_calib(reg_value) extract_field((reg_value),2,2) 2446 #define ex_AMS_RX_RXCONTROL_6__ams_rx_hiz_1(reg_value) extract_field((reg_value),1,1) 2447 #define ex_AMS_RX_RXCONTROL_6__ams_rx_m1_sign(reg_value) extract_field((reg_value),0,0) 2448 #define ex_AMS_RX_RXCONTROL_7__ams_rx_spare_7_0(reg_value) extract_field((reg_value),13,10) 2449 #define ex_AMS_RX_RXCONTROL_7__ams_rx_sigdet_threshold(reg_value) extract_field((reg_value),9,5) 2450 #define ex_AMS_RX_RXCONTROL_7__ams_rx_sigdet_offset_correction_neg(reg_value) extract_field((reg_value),4,0) 2451 #define ex_AMS_RX_RXINTCTRL__ams_rx_rxpon_sel(reg_value) extract_field((reg_value),1,1) 2452 #define ex_AMS_RX_RXINTCTRL__ams_rx_vgapon_sel(reg_value) extract_field((reg_value),0,0) 2453 #define ex_AMS_RX_RXSTATUS__ams_rx_vgapon_mux(reg_value) extract_field((reg_value),7,4) 2454 #define ex_AMS_RX_RXSTATUS__ams_rx_rxpon_mux(reg_value) extract_field((reg_value),3,0) 2455 #define ex_AMS_TX_TXCONTROL_0__ams_tx_lowlatency_en(reg_value) extract_field((reg_value),15,15) 2456 #define ex_AMS_TX_TXCONTROL_0__ams_tx_fifo_resetb(reg_value) extract_field((reg_value),14,14) 2457 #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_fifo_ctrl(reg_value) extract_field((reg_value),13,11) 2458 #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_fifo_zero_out(reg_value) extract_field((reg_value),10,10) 2459 #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_polarity_flip(reg_value) extract_field((reg_value),9,9) 2460 #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_selpath_tx(reg_value) extract_field((reg_value),8,8) 2461 #define ex_AMS_TX_TXCONTROL_0__ams_tx_enable_os_2(reg_value) extract_field((reg_value),7,7) 2462 #define ex_AMS_TX_TXCONTROL_0__ams_tx_pon(reg_value) extract_field((reg_value),6,3) 2463 #define ex_AMS_TX_TXCONTROL_0__ams_tx_ticksel(reg_value) extract_field((reg_value),2,1) 2464 #define ex_AMS_TX_TXCONTROL_0__ams_tx_pwrdn(reg_value) extract_field((reg_value),0,0) 2465 #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_slow(reg_value) extract_field((reg_value),14,11) 2466 #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_wclk33(reg_value) extract_field((reg_value),10,10) 2467 #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_wclk20(reg_value) extract_field((reg_value),9,9) 2468 #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_wclk16(reg_value) extract_field((reg_value),8,8) 2469 #define ex_AMS_TX_TXCONTROL_1__ams_tx_testclk_ena(reg_value) extract_field((reg_value),7,7) 2470 #define ex_AMS_TX_TXCONTROL_1__ams_tx_testsel(reg_value) extract_field((reg_value),6,5) 2471 #define ex_AMS_TX_TXCONTROL_1__ams_tx_cntrl_rxdetect_en(reg_value) extract_field((reg_value),4,4) 2472 #define ex_AMS_TX_TXCONTROL_1__ams_tx_rxdtct_th_sel(reg_value) extract_field((reg_value),3,2) 2473 #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_high_current(reg_value) extract_field((reg_value),1,1) 2474 #define ex_AMS_TX_TXCONTROL_1__ams_tx_enable_os_4(reg_value) extract_field((reg_value),0,0) 2475 #define ex_AMS_TX_TXCONTROL_2__ams_tx_fifo_phsdetect_mode(reg_value) extract_field((reg_value),14,14) 2476 #define ex_AMS_TX_TXCONTROL_2__ams_tx_ibias_pibuf_cntl(reg_value) extract_field((reg_value),13,11) 2477 #define ex_AMS_TX_TXCONTROL_2__ams_tx_ibias_pi_cntl(reg_value) extract_field((reg_value),10,8) 2478 #define ex_AMS_TX_TXCONTROL_2__ams_tx_ibias_opamp_cntl(reg_value) extract_field((reg_value),7,5) 2479 #define ex_AMS_TX_TXCONTROL_2__ams_tx_dcc_en(reg_value) extract_field((reg_value),4,4) 2480 #define ex_AMS_TX_TXCONTROL_2__ams_tx_en_hpf(reg_value) extract_field((reg_value),3,0) 2481 #define ex_AMS_TX_TXCONTROL_3__ams_tx_refcalm(reg_value) extract_field((reg_value),13,10) 2482 #define ex_AMS_TX_TXCONTROL_3__ams_tx_refcalp(reg_value) extract_field((reg_value),9,6) 2483 #define ex_AMS_TX_TXCONTROL_3__ams_tx_refcalshunt(reg_value) extract_field((reg_value),5,2) 2484 #define ex_AMS_TX_TXCONTROL_3__ams_tx_spare_3_0(reg_value) extract_field((reg_value),1,0) 2485 #define ex_AMS_TX_TXCONTROL_4__ams_tx_shntpost2_post2(reg_value) extract_field((reg_value),15,12) 2486 #define ex_AMS_TX_TXCONTROL_4__ams_tx_shntpost1_post1pre(reg_value) extract_field((reg_value),11,6) 2487 #define ex_AMS_TX_TXCONTROL_4__ams_tx_shntpre_post1pre(reg_value) extract_field((reg_value),5,0) 2488 #define ex_AMS_TX_TXCONTROL_5__ams_tx_post2to1(reg_value) extract_field((reg_value),13,13) 2489 #define ex_AMS_TX_TXCONTROL_5__ams_tx_en_pre(reg_value) extract_field((reg_value),12,12) 2490 #define ex_AMS_TX_TXCONTROL_5__ams_tx_en_post1(reg_value) extract_field((reg_value),11,11) 2491 #define ex_AMS_TX_TXCONTROL_5__ams_tx_en_post2(reg_value) extract_field((reg_value),10,10) 2492 #define ex_AMS_TX_TXCONTROL_5__ams_tx_shntmain_post2(reg_value) extract_field((reg_value),9,6) 2493 #define ex_AMS_TX_TXCONTROL_5__ams_tx_shntmain_post1pre(reg_value) extract_field((reg_value),5,0) 2494 #define ex_AMS_TX_TXCONTROL_6__ams_tx_shntpost1_post1(reg_value) extract_field((reg_value),15,11) 2495 #define ex_AMS_TX_TXCONTROL_6__ams_tx_dis_cal(reg_value) extract_field((reg_value),10,6) 2496 #define ex_AMS_TX_TXCONTROL_6__ams_tx_spare_6_0(reg_value) extract_field((reg_value),5,2) 2497 #define ex_AMS_TX_TXCONTROL_6__ams_tx_pd_phasedet(reg_value) extract_field((reg_value),1,1) 2498 #define ex_AMS_TX_TXCONTROL_6__ams_tx_en_shuntmode(reg_value) extract_field((reg_value),0,0) 2499 #define ex_AMS_TX_TXCONTROL_7__ams_tx_refcalpcs(reg_value) extract_field((reg_value),12,9) 2500 #define ex_AMS_TX_TXCONTROL_7__ams_tx_refcalmcs(reg_value) extract_field((reg_value),8,5) 2501 #define ex_AMS_TX_TXCONTROL_7__ams_tx_shntmain_post1(reg_value) extract_field((reg_value),4,0) 2502 #define ex_AMS_TX_TXCONTROL_8__ams_tx_spare_8_0(reg_value) extract_field((reg_value),8,1) 2503 #define ex_AMS_TX_TXCONTROL_8__ams_tx_shnten_main(reg_value) extract_field((reg_value),0,0) 2504 #define ex_AMS_TX_TXINTCTRL__ams_tx_sel_txmaster(reg_value) extract_field((reg_value),3,3) 2505 #define ex_AMS_TX_TXINTCTRL__ams_tx_auto_ll_selpath_tx_dis(reg_value) extract_field((reg_value),2,2) 2506 #define ex_AMS_TX_TXINTCTRL__ams_tx_txpon_sel(reg_value) extract_field((reg_value),1,1) 2507 #define ex_AMS_TX_TXSTATUS__ams_tx_rescal(reg_value) extract_field((reg_value),7,4) 2508 #define ex_AMS_TX_TXSTATUS__ams_tx_txpon_mux(reg_value) extract_field((reg_value),3,0) 2509 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_cpar(reg_value) extract_field((reg_value),15,14) 2510 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_term_cm_en(reg_value) extract_field((reg_value),13,13) 2511 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_spare_0_1(reg_value) extract_field((reg_value),12,12) 2512 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_rpar(reg_value) extract_field((reg_value),11,9) 2513 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_lc_refclk_adj_1_0(reg_value) extract_field((reg_value),8,7) 2514 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_spare_0_0(reg_value) extract_field((reg_value),6,0) 2515 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_en_hcur_vco(reg_value) extract_field((reg_value),15,15) 2516 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_enb_10t(reg_value) extract_field((reg_value),14,14) 2517 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_enb_8t(reg_value) extract_field((reg_value),13,13) 2518 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_vco_range(reg_value) extract_field((reg_value),12,6) 2519 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_en_8p5g_vco(reg_value) extract_field((reg_value),5,5) 2520 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_spare_1_0(reg_value) extract_field((reg_value),4,4) 2521 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_curr_sel(reg_value) extract_field((reg_value),3,0) 2522 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_i4iqbuf(reg_value) extract_field((reg_value),15,14) 2523 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_vco_buf_pon(reg_value) extract_field((reg_value),13,10) 2524 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_clkvco_cal_invert(reg_value) extract_field((reg_value),9,9) 2525 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_cmos_refclk_ch_hiz(reg_value) extract_field((reg_value),8,8) 2526 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_calib_adj(reg_value) extract_field((reg_value),7,5) 2527 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_8p5g(reg_value) extract_field((reg_value),4,4) 2528 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_vco_pon(reg_value) extract_field((reg_value),3,0) 2529 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_mmd_halfrate(reg_value) extract_field((reg_value),15,15) 2530 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_cp_bias(reg_value) extract_field((reg_value),14,12) 2531 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cml_curx2(reg_value) extract_field((reg_value),11,11) 2532 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cmos_hz(reg_value) extract_field((reg_value),10,10) 2533 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cml_pd(reg_value) extract_field((reg_value),9,9) 2534 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_clksel(reg_value) extract_field((reg_value),8,8) 2535 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_rclk_refout(reg_value) extract_field((reg_value),7,7) 2536 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_cmos_refout_overwr(reg_value) extract_field((reg_value),6,6) 2537 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_cml_refout_overwr(reg_value) extract_field((reg_value),5,5) 2538 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_test_frac_clk(reg_value) extract_field((reg_value),4,4) 2539 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_enb_16t(reg_value) extract_field((reg_value),3,3) 2540 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_band_iqbuf_ctr(reg_value) extract_field((reg_value),2,0) 2541 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_test_sel(reg_value) extract_field((reg_value),14,12) 2542 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_test_amp(reg_value) extract_field((reg_value),11,10) 2543 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_vco_test_clk_en(reg_value) extract_field((reg_value),9,9) 2544 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_bias_en(reg_value) extract_field((reg_value),8,8) 2545 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_vco_hkvco(reg_value) extract_field((reg_value),7,7) 2546 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_bias_vdd_sel(reg_value) extract_field((reg_value),6,5) 2547 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_cmos_tport_en(reg_value) extract_field((reg_value),4,4) 2548 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_cp_opamp_bias(reg_value) extract_field((reg_value),3,2) 2549 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_lc_refclk_adj_3_2(reg_value) extract_field((reg_value),1,0) 2550 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_refdiv_test_sel(reg_value) extract_field((reg_value),12,10) 2551 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_pwdb_extr_d2c(reg_value) extract_field((reg_value),9,9) 2552 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_en_refout_div(reg_value) extract_field((reg_value),8,8) 2553 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_pwrdn(reg_value) extract_field((reg_value),7,7) 2554 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_term_sel(reg_value) extract_field((reg_value),6,5) 2555 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_test_sel_overwrite(reg_value) extract_field((reg_value),4,4) 2556 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_test_vc(reg_value) extract_field((reg_value),3,3) 2557 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_refout_div_sel(reg_value) extract_field((reg_value),2,0) 2558 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_ndiv_frac_l(reg_value) extract_field((reg_value),15,12) 2559 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_pfd_offset(reg_value) extract_field((reg_value),11,10) 2560 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_spare6_1(reg_value) extract_field((reg_value),9,9) 2561 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_pfd_offset_enlarge(reg_value) extract_field((reg_value),8,8) 2562 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_vco_i_boost(reg_value) extract_field((reg_value),7,6) 2563 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_vco_gm_boost(reg_value) extract_field((reg_value),5,4) 2564 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_pon(reg_value) extract_field((reg_value),3,0) 2565 #define exc_AMS_COM_PLL_CTRL_7__ams_pll_i_ndiv_frac_h(reg_value) extract_field((reg_value),13,0) 2566 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_ndiv_dither_en(reg_value) extract_field((reg_value),15,15) 2567 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_pll_sdm_pwrdnb(reg_value) extract_field((reg_value),14,14) 2568 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_vcofb_div(reg_value) extract_field((reg_value),13,12) 2569 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_cml_refclk_bias(reg_value) extract_field((reg_value),11,10) 2570 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_ndiv_int(reg_value) extract_field((reg_value),9,0) 2571 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_cml_refclk_adj(reg_value) extract_field((reg_value),15,14) 2572 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_bias_iq_ctrl(reg_value) extract_field((reg_value),13,11) 2573 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_bias_div_ctrl(reg_value) extract_field((reg_value),10,8) 2574 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_vco_supply_adj(reg_value) extract_field((reg_value),7,7) 2575 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_sel_fp3cap(reg_value) extract_field((reg_value),6,3) 2576 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_i_pll_frac_mode(reg_value) extract_field((reg_value),2,1) 2577 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_mmd_resetb(reg_value) extract_field((reg_value),0,0) 2578 #define exc_AMS_COM_PLL_CTRL_10__ams_pll_refclk_in_bias(reg_value) extract_field((reg_value),5,0) 2579 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_term_frc(reg_value) extract_field((reg_value),3,3) 2580 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div_frc(reg_value) extract_field((reg_value),2,2) 2581 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div2_frc_val(reg_value) extract_field((reg_value),1,1) 2582 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div4_frc_val(reg_value) extract_field((reg_value),0,0) 2583 #define exc_AMS_COM_PLL_STS__ams_pll_afe_rev_id(reg_value) extract_field((reg_value),3,0) 2584 #define ex_CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152__cl72_ieee_lp_coeff_update(reg_value) extract_field((reg_value),15,0) 2585 #define ex_CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153__cl72_ieee_lp_status_report(reg_value) extract_field((reg_value),15,0) 2586 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150__cl72_ieee_training_enable(reg_value) extract_field((reg_value),1,1) 2587 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150__cl72_ieee_restart_training(reg_value) extract_field((reg_value),0,0) 2588 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_training_failure(reg_value) extract_field((reg_value),3,3) 2589 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_training_status(reg_value) extract_field((reg_value),2,2) 2590 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_frame_lock(reg_value) extract_field((reg_value),1,1) 2591 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_receiver_status(reg_value) extract_field((reg_value),0,0) 2592 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154__cl72_ieee_ld_coeff_update(reg_value) extract_field((reg_value),15,0) 2593 #define ex_CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155__cl72_ieee_ld_status_report(reg_value) extract_field((reg_value),15,0) 2594 #define ex_CL72_USER_RX_CL72UR_CONTROL0_REGISTER__cl72_rx_signal_ok(reg_value) extract_field((reg_value),2,2) 2595 #define ex_CL72_USER_RX_CL72UR_CONTROL0_REGISTER__cl72_tr_coarse_lock(reg_value) extract_field((reg_value),1,1) 2596 #define ex_CL72_USER_RX_CL72UR_CONTROL0_REGISTER__cl72_rx_training_en(reg_value) extract_field((reg_value),0,0) 2597 #define ex_CL72_USER_RX_CL72UR_CONTROL1_REGISTER__cl72_bad_marker_cnt(reg_value) extract_field((reg_value),6,4) 2598 #define ex_CL72_USER_RX_CL72UR_CONTROL1_REGISTER__cl72_good_marker_cnt(reg_value) extract_field((reg_value),1,0) 2599 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_frame_consistency_chk_en(reg_value) extract_field((reg_value),9,9) 2600 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_rx_dp_ln_clk_en(reg_value) extract_field((reg_value),8,8) 2601 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_ppm_offset_en(reg_value) extract_field((reg_value),7,7) 2602 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_strict_marker_chk(reg_value) extract_field((reg_value),6,6) 2603 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_strict_dme_chk(reg_value) extract_field((reg_value),5,5) 2604 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_dme_cell_boundary_chk(reg_value) extract_field((reg_value),4,4) 2605 #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_ctrl_frame_dly(reg_value) extract_field((reg_value),3,0) 2606 #define ex_CL72_USER_RX_CL72UR_STATUS0_REGISTER__cl72_remote_rx_ready(reg_value) extract_field((reg_value),1,1) 2607 #define ex_CL72_USER_RX_CL72UR_STATUS0_REGISTER__cl72_frame_lock(reg_value) extract_field((reg_value),0,0) 2608 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_status_resp_int_frc_val(reg_value) extract_field((reg_value),11,11) 2609 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_status_resp_int_frc(reg_value) extract_field((reg_value),10,10) 2610 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_update_req_int_frc_val(reg_value) extract_field((reg_value),9,9) 2611 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_update_req_int_frc(reg_value) extract_field((reg_value),8,8) 2612 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_frame_lock_int_en(reg_value) extract_field((reg_value),2,2) 2613 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_status_chg_int_en(reg_value) extract_field((reg_value),1,1) 2614 #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_update_chg_int_en(reg_value) extract_field((reg_value),0,0) 2615 #define ex_CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER__cl72_micro_update_chg_lstatus(reg_value) extract_field((reg_value),0,0) 2616 #define ex_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER__cl72_micro_frame_lock_lstatus(reg_value) extract_field((reg_value),1,1) 2617 #define ex_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER__cl72_micro_status_chg_lstatus(reg_value) extract_field((reg_value),0,0) 2618 #define ex_CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER__cl72_xmt_update_page(reg_value) extract_field((reg_value),15,0) 2619 #define ex_CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE__cl72_ld_xmt_status_page(reg_value) extract_field((reg_value),15,0) 2620 #define ex_CL72_USER_TX_CL72UT_CONTROL0_REGISTER__cl72_sw_remote_rx_ready(reg_value) extract_field((reg_value),2,2) 2621 #define ex_CL72_USER_TX_CL72UT_CONTROL0_REGISTER__cl72_sw_rx_trained(reg_value) extract_field((reg_value),0,0) 2622 #define ex_CL72_USER_TX_CL72UT_CONTROL0_REGISTER__cl72_sw_frame_lock(reg_value) extract_field((reg_value),1,1) 2623 #define ex_CL72_USER_TX_CL72UT_CONTROL1_REGISTER__cl72_tx_dp_ln_clk_en(reg_value) extract_field((reg_value),2,2) 2624 #define ex_CL72_USER_TX_CL72UT_CONTROL1_REGISTER__cl72_dis_max_wait_timer(reg_value) extract_field((reg_value),1,1) 2625 #define ex_CL72_USER_TX_CL72UT_CONTROL1_REGISTER__cl72_brk_ring_osc(reg_value) extract_field((reg_value),0,0) 2626 #define ex_CL72_USER_TX_CL72UT_CONTROL2_REGISTER__cl72_txfir_post(reg_value) extract_field((reg_value),12,8) 2627 #define ex_CL72_USER_TX_CL72UT_CONTROL2_REGISTER__cl72_txfir_pre(reg_value) extract_field((reg_value),3,0) 2628 #define ex_CL72_USER_TX_CL72UT_CONTROL3_REGISTER__cl72_txfir_main(reg_value) extract_field((reg_value),5,0) 2629 #define ex_CL72_USER_TX_CL72UT_STATUS0_REGISTER__cl72_training_fsm_signal_detect(reg_value) extract_field((reg_value),1,1) 2630 #define ex_CL72_USER_TX_CL72UT_STATUS0_REGISTER__cl72_local_rx_ready(reg_value) extract_field((reg_value),0,0) 2631 #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_prbs_seed_sel(reg_value) extract_field((reg_value),15,14) 2632 #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_prbs_mode_sel(reg_value) extract_field((reg_value),13,13) 2633 #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_cl93prbs_poly_sel(reg_value) extract_field((reg_value),12,11) 2634 #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_prbs_seed_val(reg_value) extract_field((reg_value),10,0) 2635 #define exc_DIG_COM_B_LANE_ADDR_0__tx_lane_addr_0(reg_value) extract_field((reg_value),12,8) 2636 #define exc_DIG_COM_B_LANE_ADDR_0__rx_lane_addr_0(reg_value) extract_field((reg_value),4,0) 2637 #define exc_DIG_COM_B_LANE_ADDR_1__tx_lane_addr_1(reg_value) extract_field((reg_value),12,8) 2638 #define exc_DIG_COM_B_LANE_ADDR_1__rx_lane_addr_1(reg_value) extract_field((reg_value),4,0) 2639 #define exc_DIG_COM_B_LANE_ADDR_2__tx_lane_addr_2(reg_value) extract_field((reg_value),12,8) 2640 #define exc_DIG_COM_B_LANE_ADDR_2__rx_lane_addr_2(reg_value) extract_field((reg_value),4,0) 2641 #define exc_DIG_COM_B_LANE_ADDR_3__tx_lane_addr_3(reg_value) extract_field((reg_value),12,8) 2642 #define exc_DIG_COM_B_LANE_ADDR_3__rx_lane_addr_3(reg_value) extract_field((reg_value),4,0) 2643 #define exc_DIG_COM_REVID0__revid_rev_letter(reg_value) extract_field((reg_value),15,14) 2644 #define exc_DIG_COM_REVID0__revid_rev_number(reg_value) extract_field((reg_value),13,11) 2645 #define exc_DIG_COM_REVID0__revid_bonding(reg_value) extract_field((reg_value),10,9) 2646 #define exc_DIG_COM_REVID0__revid_process(reg_value) extract_field((reg_value),8,6) 2647 #define exc_DIG_COM_REVID0__revid_model(reg_value) extract_field((reg_value),5,0) 2648 #define exc_DIG_COM_REVID1__revid_multiplicity(reg_value) extract_field((reg_value),15,12) 2649 #define exc_DIG_COM_REVID1__revid_mdio(reg_value) extract_field((reg_value),5,5) 2650 #define exc_DIG_COM_REVID1__revid_micro(reg_value) extract_field((reg_value),4,4) 2651 #define exc_DIG_COM_REVID1__revid_cl72(reg_value) extract_field((reg_value),3,3) 2652 #define exc_DIG_COM_REVID1__revid_pir(reg_value) extract_field((reg_value),2,2) 2653 #define exc_DIG_COM_REVID1__revid_llp(reg_value) extract_field((reg_value),1,1) 2654 #define exc_DIG_COM_REVID1__revid_eee(reg_value) extract_field((reg_value),0,0) 2655 #define exc_DIG_COM_REVID2__revid2(reg_value) extract_field((reg_value),3,0) 2656 #define exc_DIG_COM_RESET_CONTROL_PMD__core_s_rstb(reg_value) extract_field((reg_value),0,0) 2657 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__disable_ack_timeout(reg_value) extract_field((reg_value),15,15) 2658 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_vcoclk16_vld_frc_val(reg_value) extract_field((reg_value),10,10) 2659 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_vcoclk16_vld_frc(reg_value) extract_field((reg_value),9,9) 2660 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__vcoclk16_s_comclk_frc_on(reg_value) extract_field((reg_value),8,8) 2661 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__vcoclk16_s_comclk_sel(reg_value) extract_field((reg_value),7,7) 2662 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_mdio_trans_pkill(reg_value) extract_field((reg_value),5,5) 2663 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc(reg_value) extract_field((reg_value),4,4) 2664 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc_val(reg_value) extract_field((reg_value),3,3) 2665 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_core_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 2666 #define exc_DIG_COM_MASKDATA_REG__maskdata(reg_value) extract_field((reg_value),15,0) 2667 #define exc_DIG_COM_TOP_USER_CONTROL_0__uc_active(reg_value) extract_field((reg_value),15,15) 2668 #define exc_DIG_COM_TOP_USER_CONTROL_0__afe_s_pll_pwrdn(reg_value) extract_field((reg_value),14,14) 2669 #define exc_DIG_COM_TOP_USER_CONTROL_0__core_dp_s_rstb(reg_value) extract_field((reg_value),13,13) 2670 #define exc_DIG_COM_TOP_USER_CONTROL_0__maskdata_bus_assign(reg_value) extract_field((reg_value),11,10) 2671 #define exc_DIG_COM_TOP_USER_CONTROL_0__heartbeat_count_1us(reg_value) extract_field((reg_value),9,0) 2672 #define exc_DIG_COM_UC_ACK_CORE_CONTROL__uc_ack_core_dp_reset(reg_value) extract_field((reg_value),1,1) 2673 #define exc_DIG_COM_UC_ACK_CORE_CONTROL__uc_ack_core_cfg_done(reg_value) extract_field((reg_value),0,0) 2674 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released(reg_value) extract_field((reg_value),14,14) 2675 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released_index(reg_value) extract_field((reg_value),12,8) 2676 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released(reg_value) extract_field((reg_value),15,15) 2677 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released_index(reg_value) extract_field((reg_value),7,3) 2678 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__core_dp_reset_state(reg_value) extract_field((reg_value),2,0) 2679 #define exc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL__core_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 2680 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__rst_seq_dis_flt_mode(reg_value) extract_field((reg_value),15,14) 2681 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__pwrdn_seq_timer(reg_value) extract_field((reg_value),11,9) 2682 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__rst_seq_timer(reg_value) extract_field((reg_value),2,0) 2683 #define exc_DIG_COM_PMD_CORE_MODE_STATUS__pmd_core_mode(reg_value) extract_field((reg_value),15,0) 2684 #define ex_DSC_A_CDR_STATUS_INTEG_REG__cdr_integ_reg(reg_value) extract_field_signed((reg_value),15,0) 2685 #define ex_DSC_A_CDR_STATUS_PHASE_ERROR__cdr_phase_err(reg_value) extract_field_signed((reg_value),4,0) 2686 #define ex_DSC_A_RX_PI_CNT_BIN_D__cnt_bin_p1_dreg(reg_value) extract_field((reg_value),14,8) 2687 #define ex_DSC_A_RX_PI_CNT_BIN_D__cnt_bin_d_dreg(reg_value) extract_field((reg_value),6,0) 2688 #define ex_DSC_A_RX_PI_CNT_BIN_P__cnt_bin_m1_preg(reg_value) extract_field((reg_value),14,8) 2689 #define ex_DSC_A_RX_PI_CNT_BIN_P__cnt_bin_p1_preg(reg_value) extract_field((reg_value),6,0) 2690 #define ex_DSC_A_RX_PI_CNT_BIN_M__cnt_bin_d_mreg(reg_value) extract_field((reg_value),14,8) 2691 #define ex_DSC_A_RX_PI_CNT_BIN_M__cnt_bin_m1_mreg(reg_value) extract_field((reg_value),6,0) 2692 #define ex_DSC_A_RX_PI_DIFF_BIN__cnt_d_minus_p1(reg_value) extract_field_signed((reg_value),15,8) 2693 #define ex_DSC_A_RX_PI_DIFF_BIN__cnt_d_minus_m1(reg_value) extract_field_signed((reg_value),7,0) 2694 #define ex_DSC_A_CDR_CONTROL_0__cdr_lm_thr_sel(reg_value) extract_field((reg_value),10,8) 2695 #define ex_DSC_A_CDR_CONTROL_0__cdr_freq_override_en(reg_value) extract_field((reg_value),7,7) 2696 #define ex_DSC_A_CDR_CONTROL_0__cdr_integ_sat_sel(reg_value) extract_field((reg_value),6,6) 2697 #define ex_DSC_A_CDR_CONTROL_0__cdr_phase_err_frz(reg_value) extract_field((reg_value),5,5) 2698 #define ex_DSC_A_CDR_CONTROL_0__cdr_integ_reg_clr(reg_value) extract_field((reg_value),4,4) 2699 #define ex_DSC_A_CDR_CONTROL_0__cdr_freq_en(reg_value) extract_field((reg_value),2,2) 2700 #define ex_DSC_A_CDR_CONTROL_0__br_pd_en(reg_value) extract_field((reg_value),1,1) 2701 #define ex_DSC_A_CDR_CONTROL_0__cdr_phase_sat_ctrl(reg_value) extract_field((reg_value),0,0) 2702 #define ex_DSC_A_CDR_CONTROL_1__cdr_freq_override_val(reg_value) extract_field_signed((reg_value),15,1) 2703 #define ex_DSC_A_CDR_CONTROL_1__dfe_vga_unfreeze(reg_value) extract_field((reg_value),0,0) 2704 #define ex_DSC_A_CDR_CONTROL_2__osx2p_pherr_gain(reg_value) extract_field((reg_value),9,8) 2705 #define ex_DSC_A_CDR_CONTROL_2__pattern_sel(reg_value) extract_field((reg_value),7,4) 2706 #define ex_DSC_A_CDR_CONTROL_2__phase_err_offset_mult_2(reg_value) extract_field((reg_value),1,1) 2707 #define ex_DSC_A_CDR_CONTROL_2__cdr_zero_polarity(reg_value) extract_field((reg_value),0,0) 2708 #define ex_DSC_A_TRNSUM_CNTL_5__edge_count_refless_en(reg_value) extract_field((reg_value),15,15) 2709 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_eye_closure_err_sel(reg_value) extract_field((reg_value),13,12) 2710 #define ex_DSC_A_TRNSUM_CNTL_5__swap_lms_data(reg_value) extract_field((reg_value),11,11) 2711 #define ex_DSC_A_TRNSUM_CNTL_5__swap_lms_m1(reg_value) extract_field((reg_value),10,10) 2712 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_prbs_sel(reg_value) extract_field((reg_value),6,5) 2713 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_eye_close_prev_en(reg_value) extract_field((reg_value),4,4) 2714 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_pattern_match_sel(reg_value) extract_field((reg_value),3,2) 2715 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_disable_sm_clear(reg_value) extract_field((reg_value),1,1) 2716 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_clr_sc(reg_value) extract_field((reg_value),0,0) 2717 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_reset(reg_value) extract_field((reg_value),15,15) 2718 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_slicers_en(reg_value) extract_field((reg_value),14,12) 2719 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_mode(reg_value) extract_field((reg_value),11,11) 2720 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_phase_step_dir(reg_value) extract_field((reg_value),10,10) 2721 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_strobe(reg_value) extract_field((reg_value),9,9) 2722 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_phase_step_cnt(reg_value) extract_field((reg_value),6,0) 2723 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_supp_info(reg_value) extract_field((reg_value),15,8) 2724 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_ready_for_cmd(reg_value) extract_field((reg_value),7,7) 2725 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_error_found(reg_value) extract_field((reg_value),6,6) 2726 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_gp_uc_req(reg_value) extract_field((reg_value),5,0) 2727 #define ex_DSC_A_DSC_SCRATCH__uc_dsc_data(reg_value) extract_field((reg_value),15,0) 2728 #define ex_DSC_B_DSC_SM_CTRL_0__eee_mode_en(reg_value) extract_field((reg_value),1,1) 2729 #define ex_DSC_B_DSC_SM_CTRL_0__eee_quiet_rx_afe_pwrdwn_val(reg_value) extract_field((reg_value),2,2) 2730 #define ex_DSC_B_DSC_SM_CTRL_0__ignore_rx_mode(reg_value) extract_field((reg_value),3,3) 2731 #define ex_DSC_B_DSC_SM_CTRL_0__cl72_timer_en(reg_value) extract_field((reg_value),4,4) 2732 #define ex_DSC_B_DSC_SM_CTRL_0__uc_tune_en(reg_value) extract_field((reg_value),5,5) 2733 #define ex_DSC_B_DSC_SM_CTRL_0__hw_tune_en(reg_value) extract_field((reg_value),6,6) 2734 #define ex_DSC_B_DSC_SM_CTRL_0__uc_trnsum_en(reg_value) extract_field((reg_value),7,7) 2735 #define ex_DSC_B_DSC_SM_CTRL_0__eee_measure_en(reg_value) extract_field((reg_value),8,8) 2736 #define ex_DSC_B_DSC_SM_CTRL_0__slicer_cal_done_clear(reg_value) extract_field((reg_value),9,9) 2737 #define ex_DSC_B_DSC_SM_CTRL_0__slicer_cal_bypass(reg_value) extract_field((reg_value),10,10) 2738 #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_eee_done(reg_value) extract_field((reg_value),11,11) 2739 #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_restart(reg_value) extract_field((reg_value),13,13) 2740 #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_config(reg_value) extract_field((reg_value),14,14) 2741 #define ex_DSC_B_DSC_SM_CTRL_0__set_meas_incomplete(reg_value) extract_field((reg_value),15,15) 2742 #define ex_DSC_B_DSC_SM_CTRL_1__rx_dsc_lock_frc(reg_value) extract_field((reg_value),0,0) 2743 #define ex_DSC_B_DSC_SM_CTRL_1__rx_dsc_lock_frc_val(reg_value) extract_field((reg_value),1,1) 2744 #define ex_DSC_B_DSC_SM_CTRL_1__dsc_clr_frc(reg_value) extract_field((reg_value),2,2) 2745 #define ex_DSC_B_DSC_SM_CTRL_1__dsc_clr_frc_val(reg_value) extract_field((reg_value),3,3) 2746 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_frz_frc(reg_value) extract_field((reg_value),4,4) 2747 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_frz_frc_val(reg_value) extract_field((reg_value),5,5) 2748 #define ex_DSC_B_DSC_SM_CTRL_1__timer_done_frc(reg_value) extract_field((reg_value),6,6) 2749 #define ex_DSC_B_DSC_SM_CTRL_1__timer_done_frc_val(reg_value) extract_field((reg_value),7,7) 2750 #define ex_DSC_B_DSC_SM_CTRL_1__freq_upd_en_frc(reg_value) extract_field((reg_value),8,8) 2751 #define ex_DSC_B_DSC_SM_CTRL_1__freq_upd_en_frc_val(reg_value) extract_field((reg_value),9,9) 2752 #define ex_DSC_B_DSC_SM_CTRL_1__cdr_frz_frc(reg_value) extract_field((reg_value),10,10) 2753 #define ex_DSC_B_DSC_SM_CTRL_1__cdr_frz_frc_val(reg_value) extract_field((reg_value),11,11) 2754 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_clr_frc(reg_value) extract_field((reg_value),12,12) 2755 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_clr_frc_val(reg_value) extract_field((reg_value),13,13) 2756 #define ex_DSC_B_DSC_SM_CTRL_2__eee_lfsr_cnt(reg_value) extract_field((reg_value),12,0) 2757 #define ex_DSC_B_DSC_SM_CTRL_3__measure_lfsr_cnt(reg_value) extract_field((reg_value),12,0) 2758 #define ex_DSC_B_DSC_SM_CTRL_4__acq_cdr_timeout(reg_value) extract_field((reg_value),4,0) 2759 #define ex_DSC_B_DSC_SM_CTRL_4__cdr_settle_timeout(reg_value) extract_field((reg_value),9,5) 2760 #define ex_DSC_B_DSC_SM_CTRL_4__hw_tune_timeout(reg_value) extract_field((reg_value),14,10) 2761 #define ex_DSC_B_DSC_SM_CTRL_5__measure_timeout(reg_value) extract_field((reg_value),4,0) 2762 #define ex_DSC_B_DSC_SM_CTRL_5__eee_acq_cdr_timeout(reg_value) extract_field((reg_value),9,5) 2763 #define ex_DSC_B_DSC_SM_CTRL_5__eee_cdr_settle_timeout(reg_value) extract_field((reg_value),14,10) 2764 #define ex_DSC_B_DSC_SM_CTRL_6__eee_hw_tune_timeout(reg_value) extract_field((reg_value),4,0) 2765 #define ex_DSC_B_DSC_SM_CTRL_6__eee_ana_pwr_timeout(reg_value) extract_field((reg_value),14,10) 2766 #define ex_DSC_B_DSC_SM_CTRL_6__slicer_cal_timeout(reg_value) extract_field((reg_value),9,5) 2767 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_acqcdr(reg_value) extract_field((reg_value),3,0) 2768 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_eee_acqcdr(reg_value) extract_field((reg_value),7,4) 2769 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_norm(reg_value) extract_field((reg_value),11,8) 2770 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_prop_acqcdr(reg_value) extract_field((reg_value),13,12) 2771 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_prop_norm(reg_value) extract_field((reg_value),15,14) 2772 #define ex_DSC_B_DSC_SM_CTRL_8__phase_err_offset(reg_value) extract_field_signed((reg_value),3,0) 2773 #define ex_DSC_B_DSC_SM_CTRL_8__eee_phase_err_offset(reg_value) extract_field_signed((reg_value),7,4) 2774 #define ex_DSC_B_DSC_SM_CTRL_8__phase_err_offset_en(reg_value) extract_field((reg_value),9,8) 2775 #define ex_DSC_B_DSC_SM_CTRL_8__eee_phase_err_offset_en(reg_value) extract_field((reg_value),11,10) 2776 #define ex_DSC_B_DSC_SM_CTRL_8__cdr_bwsel_prop_eee_acqcdr(reg_value) extract_field((reg_value),15,14) 2777 #define ex_DSC_B_DSC_SM_CTRL_9__dcoff_cal_timeout(reg_value) extract_field((reg_value),14,10) 2778 #define ex_DSC_B_DSC_SM_CTRL_9__rx_restart_pmd(reg_value) extract_field((reg_value),0,0) 2779 #define ex_DSC_B_DSC_SM_CTRL_9__rx_restart_pmd_hold(reg_value) extract_field((reg_value),1,1) 2780 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT__dsc_state_one_hot(reg_value) extract_field((reg_value),11,0) 2781 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT__dsc_state_eee_one_hot(reg_value) extract_field((reg_value),6,0) 2782 #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_pi_ext_mode(reg_value) extract_field((reg_value),0,0) 2783 #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_sigdet(reg_value) extract_field((reg_value),1,1) 2784 #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_pmd_restart(reg_value) extract_field((reg_value),2,2) 2785 #define ex_DSC_B_DSC_SM_STATUS_RESTART__eee_quiet_from_eee_states(reg_value) extract_field((reg_value),3,3) 2786 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_state(reg_value) extract_field((reg_value),15,11) 2787 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_ready_for_cmd(reg_value) extract_field((reg_value),7,7) 2788 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__cdr_lm_outoflock(reg_value) extract_field((reg_value),6,6) 2789 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_scratch(reg_value) extract_field((reg_value),10,8) 2790 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_gp_uc_req(reg_value) extract_field((reg_value),5,0) 2791 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__eee_measure_cnt(reg_value) extract_field((reg_value),15,7) 2792 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__slicer_cal_done(reg_value) extract_field((reg_value),2,2) 2793 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__meas_incomplete(reg_value) extract_field((reg_value),1,1) 2794 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__rx_dsc_lock(reg_value) extract_field((reg_value),0,0) 2795 #define ex_DSC_C_DFE_1_CTL__dfe_1_en(reg_value) extract_field((reg_value),15,15) 2796 #define ex_DSC_C_DFE_1_CTL__dfe_1_err_sel(reg_value) extract_field((reg_value),14,13) 2797 #define ex_DSC_C_DFE_1_CTL__dfe_1_gradient_invert(reg_value) extract_field((reg_value),12,12) 2798 #define ex_DSC_C_DFE_1_CTL__dfe_1_err_gain(reg_value) extract_field((reg_value),11,10) 2799 #define ex_DSC_C_DFE_1_CTL__dfe_1_inv_m1(reg_value) extract_field((reg_value),9,9) 2800 #define ex_DSC_C_DFE_1_CTL__dfe_1_inv_p1(reg_value) extract_field((reg_value),8,8) 2801 #define ex_DSC_C_DFE_1_CTL__dfe_1_cmn_only(reg_value) extract_field((reg_value),1,1) 2802 #define ex_DSC_C_DFE_1_CTL__dfe_1_acc_clr(reg_value) extract_field((reg_value),0,0) 2803 #define ex_DSC_C_DFE_2_CTL__dfe_2_en(reg_value) extract_field((reg_value),15,15) 2804 #define ex_DSC_C_DFE_2_CTL__dfe_2_err_sel(reg_value) extract_field((reg_value),14,13) 2805 #define ex_DSC_C_DFE_2_CTL__dfe_2_gradient_invert(reg_value) extract_field((reg_value),12,12) 2806 #define ex_DSC_C_DFE_2_CTL__dfe_2_err_gain(reg_value) extract_field((reg_value),11,10) 2807 #define ex_DSC_C_DFE_2_CTL__dfe_2_inv_m1(reg_value) extract_field((reg_value),9,9) 2808 #define ex_DSC_C_DFE_2_CTL__dfe_2_inv_p1(reg_value) extract_field((reg_value),8,8) 2809 #define ex_DSC_C_DFE_2_CTL__dfe_2_cmn_only(reg_value) extract_field((reg_value),1,1) 2810 #define ex_DSC_C_DFE_2_CTL__dfe_2_acc_clr(reg_value) extract_field((reg_value),0,0) 2811 #define ex_DSC_C_DFE_3_CTL__dfe_3_en(reg_value) extract_field((reg_value),15,15) 2812 #define ex_DSC_C_DFE_3_CTL__dfe_3_err_sel(reg_value) extract_field((reg_value),14,13) 2813 #define ex_DSC_C_DFE_3_CTL__dfe_3_gradient_invert(reg_value) extract_field((reg_value),12,12) 2814 #define ex_DSC_C_DFE_3_CTL__dfe_3_err_gain(reg_value) extract_field((reg_value),11,10) 2815 #define ex_DSC_C_DFE_3_CTL__dfe_3_inv_m1(reg_value) extract_field((reg_value),9,9) 2816 #define ex_DSC_C_DFE_3_CTL__dfe_3_inv_p1(reg_value) extract_field((reg_value),8,8) 2817 #define ex_DSC_C_DFE_3_CTL__dfe_3_acc_clr(reg_value) extract_field((reg_value),0,0) 2818 #define ex_DSC_C_DFE_4_CTL__dfe_4_en(reg_value) extract_field((reg_value),15,15) 2819 #define ex_DSC_C_DFE_4_CTL__dfe_4_err_sel(reg_value) extract_field((reg_value),14,13) 2820 #define ex_DSC_C_DFE_4_CTL__dfe_4_gradient_invert(reg_value) extract_field((reg_value),12,12) 2821 #define ex_DSC_C_DFE_4_CTL__dfe_4_err_gain(reg_value) extract_field((reg_value),11,10) 2822 #define ex_DSC_C_DFE_4_CTL__dfe_4_inv_m1(reg_value) extract_field((reg_value),9,9) 2823 #define ex_DSC_C_DFE_4_CTL__dfe_4_inv_p1(reg_value) extract_field((reg_value),8,8) 2824 #define ex_DSC_C_DFE_4_CTL__dfe_4_acc_clr(reg_value) extract_field((reg_value),0,0) 2825 #define ex_DSC_C_DFE_5_CTL__dfe_5_en(reg_value) extract_field((reg_value),15,15) 2826 #define ex_DSC_C_DFE_5_CTL__dfe_5_err_sel(reg_value) extract_field((reg_value),14,13) 2827 #define ex_DSC_C_DFE_5_CTL__dfe_5_gradient_invert(reg_value) extract_field((reg_value),12,12) 2828 #define ex_DSC_C_DFE_5_CTL__dfe_5_err_gain(reg_value) extract_field((reg_value),11,10) 2829 #define ex_DSC_C_DFE_5_CTL__dfe_5_inv_m1(reg_value) extract_field((reg_value),9,9) 2830 #define ex_DSC_C_DFE_5_CTL__dfe_5_inv_p1(reg_value) extract_field((reg_value),8,8) 2831 #define ex_DSC_C_DFE_5_CTL__dfe_5_acc_clr(reg_value) extract_field((reg_value),0,0) 2832 #define ex_DSC_C_DFE_PAT_CTL__dfe_pattern_bit_en(reg_value) extract_field((reg_value),13,8) 2833 #define ex_DSC_C_DFE_PAT_CTL__dfe_pattern(reg_value) extract_field((reg_value),5,0) 2834 #define ex_DSC_C_DFE_COMMON_CTL__dfe_acc_hys_en(reg_value) extract_field((reg_value),15,15) 2835 #define ex_DSC_C_DFE_COMMON_CTL__dfe_allow_simult(reg_value) extract_field((reg_value),14,14) 2836 #define ex_DSC_C_DFE_COMMON_CTL__dfe_update_gain(reg_value) extract_field((reg_value),13,13) 2837 #define ex_DSC_C_DFE_COMMON_CTL__dfe_eye_closure_err_sel(reg_value) extract_field((reg_value),7,6) 2838 #define ex_DSC_C_DFE_COMMON_CTL__dfe_hw_eye_closure_en(reg_value) extract_field((reg_value),5,5) 2839 #define ex_DSC_C_DFE_COMMON_CTL__dfe_leaky_lms_upd_dur(reg_value) extract_field((reg_value),4,1) 2840 #define ex_DSC_C_DFE_COMMON_CTL__dfe_leaky_lms_en(reg_value) extract_field((reg_value),0,0) 2841 #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_en(reg_value) extract_field((reg_value),15,15) 2842 #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_sel(reg_value) extract_field((reg_value),13,9) 2843 #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_val(reg_value) extract_field((reg_value),8,0) 2844 #define ex_DSC_C_VGA_CTL__vga_en(reg_value) extract_field((reg_value),15,15) 2845 #define ex_DSC_C_VGA_CTL__vga_err_sel(reg_value) extract_field((reg_value),14,13) 2846 #define ex_DSC_C_VGA_CTL__vga_p1_gradient_invert(reg_value) extract_field((reg_value),12,12) 2847 #define ex_DSC_C_VGA_CTL__vga_err_gain(reg_value) extract_field((reg_value),11,10) 2848 #define ex_DSC_C_VGA_CTL__vga_inv_m1(reg_value) extract_field((reg_value),9,9) 2849 #define ex_DSC_C_VGA_CTL__vga_inv_p1(reg_value) extract_field((reg_value),8,8) 2850 #define ex_DSC_C_VGA_CTL__vga_update_gain(reg_value) extract_field((reg_value),7,6) 2851 #define ex_DSC_C_VGA_CTL__vga_affected_by_dfe1(reg_value) extract_field((reg_value),4,4) 2852 #define ex_DSC_C_VGA_CTL__vga_update_style(reg_value) extract_field((reg_value),3,2) 2853 #define ex_DSC_C_VGA_CTL__vga_acc_hys_en(reg_value) extract_field((reg_value),1,1) 2854 #define ex_DSC_C_VGA_CTL__vga_p1_acc_clr(reg_value) extract_field((reg_value),0,0) 2855 #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__p1_eyediag_en(reg_value) extract_field((reg_value),15,15) 2856 #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__vga_pattern_bit_en(reg_value) extract_field((reg_value),7,4) 2857 #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__vga_pattern(reg_value) extract_field((reg_value),3,0) 2858 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_hwtune_max(reg_value) extract_field_signed((reg_value),15,10) 2859 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_off_3levelq_en(reg_value) extract_field((reg_value),8,8) 2860 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_offset_en(reg_value) extract_field((reg_value),7,7) 2861 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_offset(reg_value) extract_field_signed((reg_value),6,0) 2862 #define ex_DSC_C_VGA_P1_MISC_CONTROL__p1_hwtune_min(reg_value) extract_field_signed((reg_value),15,10) 2863 #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_op_short_norm(reg_value) extract_field((reg_value),7,7) 2864 #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_op_short_offcal(reg_value) extract_field((reg_value),6,6) 2865 #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_hwtune_min(reg_value) extract_field_signed((reg_value),5,0) 2866 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_grad_inv(reg_value) extract_field((reg_value),7,7) 2867 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_p1(reg_value) extract_field((reg_value),6,6) 2868 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_m1(reg_value) extract_field((reg_value),5,5) 2869 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_data(reg_value) extract_field((reg_value),4,4) 2870 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_err_gain(reg_value) extract_field((reg_value),3,2) 2871 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_hys_en(reg_value) extract_field((reg_value),1,1) 2872 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_en(reg_value) extract_field((reg_value),0,0) 2873 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern_bit_en(reg_value) extract_field((reg_value),15,12) 2874 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern(reg_value) extract_field((reg_value),11,8) 2875 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_grad_inv(reg_value) extract_field((reg_value),6,6) 2876 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern_inv_en(reg_value) extract_field((reg_value),5,5) 2877 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_inv(reg_value) extract_field((reg_value),4,4) 2878 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_err_gain(reg_value) extract_field((reg_value),3,2) 2879 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_hys_en(reg_value) extract_field((reg_value),1,1) 2880 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_en(reg_value) extract_field((reg_value),0,0) 2881 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_en(reg_value) extract_field((reg_value),15,15) 2882 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_err_sel(reg_value) extract_field((reg_value),14,12) 2883 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_random_tapsel_disable(reg_value) extract_field((reg_value),11,11) 2884 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_inv_pattern_en(reg_value) extract_field((reg_value),10,10) 2885 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_pattern_full_check_off(reg_value) extract_field((reg_value),9,9) 2886 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_edge_pattern_en(reg_value) extract_field((reg_value),8,8) 2887 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_gain(reg_value) extract_field((reg_value),7,6) 2888 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_eye_closure_en(reg_value) extract_field((reg_value),5,5) 2889 #define ex_DSC_D_TRNSUM_CTL_1__cdr_qphase_mult_en(reg_value) extract_field((reg_value),4,4) 2890 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_tap_range_sel(reg_value) extract_field((reg_value),3,2) 2891 #define ex_DSC_D_TRNSUM_CTL_2__trnsum_pattern(reg_value) extract_field((reg_value),15,8) 2892 #define ex_DSC_D_TRNSUM_CTL_2__trnsum_pattern_bit_en(reg_value) extract_field((reg_value),7,0) 2893 #define ex_DSC_D_TRNSUM_CTL_3__trnsum_tap_en(reg_value) extract_field((reg_value),15,8) 2894 #define ex_DSC_D_TRNSUM_CTL_3__trnsum_tap_sign(reg_value) extract_field((reg_value),7,0) 2895 #define ex_DSC_D_TRNSUM_CTL_4__tdr_cycle_bin(reg_value) extract_field((reg_value),15,12) 2896 #define ex_DSC_D_TRNSUM_CTL_4__tdr_cycle_sel(reg_value) extract_field((reg_value),11,8) 2897 #define ex_DSC_D_TRNSUM_CTL_4__tdr_trnsum_en(reg_value) extract_field((reg_value),7,7) 2898 #define ex_DSC_D_TRNSUM_CTL_4__tdr_bit_sel(reg_value) extract_field((reg_value),6,2) 2899 #define ex_DSC_D_TRNSUM_CTL_4__trnsum_unsigned_flip(reg_value) extract_field((reg_value),1,1) 2900 #define ex_DSC_D_TRNSUM_CTL_4__trnsum_unsigned_corr(reg_value) extract_field((reg_value),0,0) 2901 #define ex_DSC_D_TRNSUM_STS_1__trnsum_e_high(reg_value) extract_field_signed((reg_value),15,0) 2902 #define ex_DSC_D_TRNSUM_STS_2__trnsum_e_low(reg_value) extract_field((reg_value),7,0) 2903 #define ex_DSC_D_TRNSUM_STS_3__trnsum_o_high(reg_value) extract_field_signed((reg_value),15,0) 2904 #define ex_DSC_D_TRNSUM_STS_4__trnsum_o_low(reg_value) extract_field((reg_value),7,0) 2905 #define ex_DSC_D_TRNSUM_STS_5__trnsum_high(reg_value) extract_field_signed((reg_value),15,0) 2906 #define ex_DSC_D_TRNSUM_STS_6__trnsum_low(reg_value) extract_field((reg_value),9,0) 2907 #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_wants_to_go_high(reg_value) extract_field((reg_value),15,15) 2908 #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_wants_to_go_low(reg_value) extract_field((reg_value),14,14) 2909 #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_eyediag_bin(reg_value) extract_field_signed((reg_value),13,8) 2910 #define ex_DSC_D_VGA_P1EYEDIAG_STS__vga_wants_to_go_low(reg_value) extract_field((reg_value),6,6) 2911 #define ex_DSC_D_VGA_P1EYEDIAG_STS__vga_bin(reg_value) extract_field((reg_value),5,0) 2912 #define ex_DSC_D_DFE_1_STS__dfe_1_wants_negative(reg_value) extract_field((reg_value),15,15) 2913 #define ex_DSC_D_DFE_1_STS__dfe_1_e(reg_value) extract_field((reg_value),13,11) 2914 #define ex_DSC_D_DFE_1_STS__dfe_1_o(reg_value) extract_field((reg_value),10,8) 2915 #define ex_DSC_D_DFE_1_STS__dfe_1_cmn(reg_value) extract_field((reg_value),5,0) 2916 #define ex_DSC_D_DFE_2_STS__dfe_2_e(reg_value) extract_field((reg_value),13,11) 2917 #define ex_DSC_D_DFE_2_STS__dfe_2_o(reg_value) extract_field((reg_value),10,8) 2918 #define ex_DSC_D_DFE_2_STS__dfe_2_se(reg_value) extract_field((reg_value),6,6) 2919 #define ex_DSC_D_DFE_2_STS__dfe_2_so(reg_value) extract_field((reg_value),5,5) 2920 #define ex_DSC_D_DFE_2_STS__dfe_2_cmn(reg_value) extract_field((reg_value),4,0) 2921 #define ex_DSC_D_DFE_3_4_5_STS__dfe_5_cmn(reg_value) extract_field_signed((reg_value),15,11) 2922 #define ex_DSC_D_DFE_3_4_5_STS__dfe_4_cmn(reg_value) extract_field_signed((reg_value),10,6) 2923 #define ex_DSC_D_DFE_3_4_5_STS__dfe_3_cmn(reg_value) extract_field_signed((reg_value),5,0) 2924 #define ex_DSC_D_VGA_TAP_BIN__vga3_ctrl_bin(reg_value) extract_field((reg_value),11,8) 2925 #define ex_DSC_D_VGA_TAP_BIN__vga2_ctrl_bin(reg_value) extract_field((reg_value),7,4) 2926 #define ex_DSC_D_VGA_TAP_BIN__vga1_ctrl_bin(reg_value) extract_field((reg_value),3,0) 2927 #define ex_DSC_E_CTRL__pf_hiz(reg_value) extract_field((reg_value),7,7) 2928 #define ex_DSC_E_CTRL__m1_thresh_sel(reg_value) extract_field((reg_value),6,5) 2929 #define ex_DSC_E_CTRL__m1_thresh_zero(reg_value) extract_field((reg_value),4,4) 2930 #define ex_DSC_E_CTRL__p1_thresh_sel(reg_value) extract_field((reg_value),3,3) 2931 #define ex_DSC_E_CTRL__en_hgain(reg_value) extract_field((reg_value),2,2) 2932 #define ex_DSC_E_CTRL__offset_pd(reg_value) extract_field((reg_value),1,1) 2933 #define ex_DSC_E_CTRL__pd_ch_p1(reg_value) extract_field((reg_value),0,0) 2934 #define ex_DSC_E_PF_CTRL__pf_ctrl(reg_value) extract_field((reg_value),3,0) 2935 #define ex_DSC_E_PF2_LOWP_CTRL__pf2_lowp_ctrl(reg_value) extract_field((reg_value),2,0) 2936 #define ex_DSC_F_DATA_ODD_OFFSET__data_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) 2937 #define ex_DSC_F_DATA_EVEN_OFFSET__data_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) 2938 #define ex_DSC_F_P1_ODD_OFFSET__p1_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) 2939 #define ex_DSC_F_P1_EVEN_OFFSET__p1_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) 2940 #define ex_DSC_F_M1_ODD_OFFSET__m1_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) 2941 #define ex_DSC_F_M1_EVEN_OFFSET__m1_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) 2942 #define ex_DSC_F_DC_OFFSET__dc_offset_bin(reg_value) extract_field_signed((reg_value),6,0) 2943 #define exc_MDIO_BLK_ADDR_BLK_ADDR__mdio_blk_addr(reg_value) extract_field((reg_value),14,4) 2944 #define exc_MDIO_CL22_IEEE_ACC_CTRL__mdio_function(reg_value) extract_field((reg_value),15,14) 2945 #define exc_MDIO_CL22_IEEE_ACC_CTRL__mdio_devad(reg_value) extract_field((reg_value),4,0) 2946 #define exc_MDIO_CL22_IEEE_ACC_ADDR_DATA__mdio_addr_data(reg_value) extract_field((reg_value),15,0) 2947 #define exc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR__mdio_drv_comclk(reg_value) extract_field((reg_value),15,15) 2948 #define exc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR__mdio_brcst_port_addr(reg_value) extract_field((reg_value),4,0) 2949 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_multi_prts_en(reg_value) extract_field((reg_value),15,15) 2950 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_multi_mmds_en(reg_value) extract_field((reg_value),14,14) 2951 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_pcs_en(reg_value) extract_field((reg_value),6,6) 2952 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_dte_en(reg_value) extract_field((reg_value),5,5) 2953 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_phy_en(reg_value) extract_field((reg_value),4,4) 2954 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_an_en(reg_value) extract_field((reg_value),3,3) 2955 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_pmd_en(reg_value) extract_field((reg_value),2,2) 2956 #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_cl22_en(reg_value) extract_field((reg_value),0,0) 2957 #define exc_MDIO_MMDSEL_AER_MDIO_AER__mdio_aer(reg_value) extract_field((reg_value),15,0) 2958 #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_core_clk_en(reg_value) extract_field((reg_value),1,1) 2959 #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_master_clk_en(reg_value) extract_field((reg_value),0,0) 2960 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_pram_if_rstb(reg_value) extract_field((reg_value),3,3) 2961 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_core_rstb(reg_value) extract_field((reg_value),1,1) 2962 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_master_rstb(reg_value) extract_field((reg_value),0,0) 2963 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_rdaddr_en(reg_value) extract_field((reg_value),13,13) 2964 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_wraddr_en(reg_value) extract_field((reg_value),12,12) 2965 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_init(reg_value) extract_field((reg_value),9,8) 2966 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_rddatasize(reg_value) extract_field((reg_value),5,4) 2967 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_wrdatasize(reg_value) extract_field((reg_value),1,0) 2968 #define exc_MICRO_A_COM_AHB_STATUS0__micro_ra_initdone(reg_value) extract_field((reg_value),0,0) 2969 #define exc_MICRO_A_COM_AHB_WRADDR_LSW__micro_ra_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 2970 #define exc_MICRO_A_COM_AHB_WRADDR_MSW__micro_ra_wraddr_msw(reg_value) extract_field((reg_value),15,0) 2971 #define exc_MICRO_A_COM_AHB_WRDATA_LSW__micro_ra_wrdata_lsw(reg_value) extract_field((reg_value),15,0) 2972 #define exc_MICRO_A_COM_AHB_WRDATA_MSW__micro_ra_wrdata_msw(reg_value) extract_field((reg_value),15,0) 2973 #define exc_MICRO_A_COM_AHB_RDADDR_LSW__micro_ra_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) 2974 #define exc_MICRO_A_COM_AHB_RDADDR_MSW__micro_ra_rdaddr_msw(reg_value) extract_field((reg_value),15,0) 2975 #define exc_MICRO_A_COM_AHB_RDDATA_LSW__micro_ra_rddata_lsw(reg_value) extract_field((reg_value),15,0) 2976 #define exc_MICRO_A_COM_AHB_RDDATA_MSW__micro_ra_rddata_msw(reg_value) extract_field((reg_value),15,0) 2977 #define exc_MICRO_A_COM_PRAMIF_CONTROL0__micro_pramif_en(reg_value) extract_field((reg_value),0,0) 2978 #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW__micro_pramif_ahb_wraddr_lsw(reg_value) extract_field((reg_value),15,2) 2979 #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW__micro_pramif_ahb_wraddr_msw(reg_value) extract_field((reg_value),15,0) 2980 #define exc_MICRO_B_COM_PVT_STATUS0__micro_pvt_tempdata_rmi(reg_value) extract_field((reg_value),9,0) 2981 #define exc_MICRO_B_COM_RMI_TO_MICRO_MBOX0__micro_rmi_to_micro_mbox0(reg_value) extract_field((reg_value),15,0) 2982 #define exc_MICRO_B_COM_RMI_TO_MICRO_MBOX1__micro_rmi_to_micro_mbox1(reg_value) extract_field((reg_value),15,0) 2983 #define exc_MICRO_B_COM_MICRO_TO_RMI_MBOX0__micro_to_rmi_mbox0(reg_value) extract_field((reg_value),15,0) 2984 #define exc_MICRO_B_COM_MICRO_TO_RMI_MBOX1__micro_to_rmi_mbox1(reg_value) extract_field((reg_value),15,0) 2985 #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_gen_intr_rmi_mbox1wr(reg_value) extract_field((reg_value),2,2) 2986 #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_gen_intr_rmi_mbox0wr(reg_value) extract_field((reg_value),1,1) 2987 #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_rmi_mbox_send_msgin(reg_value) extract_field((reg_value),0,0) 2988 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ext_ack_timeout_dis(reg_value) extract_field((reg_value),4,4) 2989 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ack_timeout_dis(reg_value) extract_field((reg_value),3,3) 2990 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_sw_pmi_hp_ext_rstb(reg_value) extract_field((reg_value),2,2) 2991 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_sw_pmi_hp_rstb(reg_value) extract_field((reg_value),1,1) 2992 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_m0_hresp_en(reg_value) extract_field((reg_value),0,0) 2993 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_pr_default_slave_error(reg_value) extract_field((reg_value),2,2) 2994 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_rmi_default_slave_error(reg_value) extract_field((reg_value),1,1) 2995 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_m0_default_slave_error(reg_value) extract_field((reg_value),0,0) 2996 #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW__micro_ra_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 2997 #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW__micro_ra_autoinc_nxt_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) 2998 #define exc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW__micro_pr_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 2999 #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frc(reg_value) extract_field((reg_value),12,12) 3000 #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frcval(reg_value) extract_field((reg_value),9,0) 3001 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_ecc_corrupt(reg_value) extract_field((reg_value),5,4) 3002 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_ecc_frc_disable(reg_value) extract_field((reg_value),1,1) 3003 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_eccg_mode(reg_value) extract_field((reg_value),0,0) 3004 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTRO1__micro_ra_ecc_wrdata(reg_value) extract_field((reg_value),6,0) 3005 #define exc_MICRO_C_COM_CODE_RAM_ECCSTATUS0__micro_code_ram_ecc_address(reg_value) extract_field((reg_value),14,0) 3006 #define exc_MICRO_C_COM_CODE_RAM_ECCSTATUS1__micro_ra_ecc_rddata(reg_value) extract_field((reg_value),6,0) 3007 #define exc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0__micro_code_ram_tm(reg_value) extract_field((reg_value),6,0) 3008 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_ignore_m0_code_writes(reg_value) extract_field((reg_value),15,15) 3009 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_ramclk_noninv(reg_value) extract_field((reg_value),14,14) 3010 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_size(reg_value) extract_field((reg_value),13,8) 3011 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_protect_fwcode(reg_value) extract_field((reg_value),1,1) 3012 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_looktab_en(reg_value) extract_field((reg_value),0,0) 3013 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0_systemresetreq_status(reg_value) extract_field((reg_value),9,9) 3014 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0_lockup_status(reg_value) extract_field((reg_value),8,8) 3015 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_multirow_err_status(reg_value) extract_field((reg_value),6,6) 3016 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_uncorr_err_status(reg_value) extract_field((reg_value),5,5) 3017 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_corr_err_status(reg_value) extract_field((reg_value),4,4) 3018 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_mbox_msgout_status(reg_value) extract_field((reg_value),0,0) 3019 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0_systemresetreq_intr_en(reg_value) extract_field((reg_value),9,9) 3020 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0_lockup_intr_en(reg_value) extract_field((reg_value),8,8) 3021 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_multirow_err_intr_en(reg_value) extract_field((reg_value),6,6) 3022 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_uncorr_err_intr_en(reg_value) extract_field((reg_value),5,5) 3023 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_corr_err_intr_en(reg_value) extract_field((reg_value),4,4) 3024 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_mbox_msgout_intr_en(reg_value) extract_field((reg_value),0,0) 3025 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_bktobk_en(reg_value) extract_field((reg_value),10,10) 3026 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_dual_meta_ff_en(reg_value) extract_field((reg_value),9,9) 3027 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_read_en(reg_value) extract_field((reg_value),8,8) 3028 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_bktobk_en(reg_value) extract_field((reg_value),2,2) 3029 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_dual_meta_ff_en(reg_value) extract_field((reg_value),1,1) 3030 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_read_en(reg_value) extract_field((reg_value),0,0) 3031 #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0__micro_silicon_debug_status_mux_sel(reg_value) extract_field((reg_value),1,0) 3032 #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0__micro_silicon_debug_status_muxed_data(reg_value) extract_field((reg_value),15,0) 3033 #define exc_PATT_GEN_COM_SEQ_0__patt_gen_seq_0(reg_value) extract_field((reg_value),15,0) 3034 #define exc_PATT_GEN_COM_SEQ_1__patt_gen_seq_1(reg_value) extract_field((reg_value),15,0) 3035 #define exc_PATT_GEN_COM_SEQ_2__patt_gen_seq_2(reg_value) extract_field((reg_value),15,0) 3036 #define exc_PATT_GEN_COM_SEQ_3__patt_gen_seq_3(reg_value) extract_field((reg_value),15,0) 3037 #define exc_PATT_GEN_COM_SEQ_4__patt_gen_seq_4(reg_value) extract_field((reg_value),15,0) 3038 #define exc_PATT_GEN_COM_SEQ_5__patt_gen_seq_5(reg_value) extract_field((reg_value),15,0) 3039 #define exc_PATT_GEN_COM_SEQ_6__patt_gen_seq_6(reg_value) extract_field((reg_value),15,0) 3040 #define exc_PATT_GEN_COM_SEQ_7__patt_gen_seq_7(reg_value) extract_field((reg_value),15,0) 3041 #define exc_PATT_GEN_COM_SEQ_8__patt_gen_seq_8(reg_value) extract_field((reg_value),15,0) 3042 #define exc_PATT_GEN_COM_SEQ_9__patt_gen_seq_9(reg_value) extract_field((reg_value),15,0) 3043 #define exc_PATT_GEN_COM_SEQ_10__patt_gen_seq_10(reg_value) extract_field((reg_value),15,0) 3044 #define exc_PATT_GEN_COM_SEQ_11__patt_gen_seq_11(reg_value) extract_field((reg_value),15,0) 3045 #define exc_PATT_GEN_COM_SEQ_12__patt_gen_seq_12(reg_value) extract_field((reg_value),15,0) 3046 #define exc_PATT_GEN_COM_SEQ_13__patt_gen_seq_13(reg_value) extract_field((reg_value),15,0) 3047 #define exc_PATT_GEN_COM_SEQ_14__patt_gen_seq_14(reg_value) extract_field((reg_value),15,0) 3048 #define exc_PLL_CAL_COM_CTL_0__cal_th(reg_value) extract_field((reg_value),15,14) 3049 #define exc_PLL_CAL_COM_CTL_0__calib_step_time(reg_value) extract_field((reg_value),12,0) 3050 #define exc_PLL_CAL_COM_CTL_1__freqdet_time(reg_value) extract_field((reg_value),15,0) 3051 #define exc_PLL_CAL_COM_CTL_2__calib_cap_charge_time(reg_value) extract_field((reg_value),11,0) 3052 #define exc_PLL_CAL_COM_CTL_3__ext_state(reg_value) extract_field((reg_value),15,12) 3053 #define exc_PLL_CAL_COM_CTL_3__accel_en(reg_value) extract_field((reg_value),11,11) 3054 #define exc_PLL_CAL_COM_CTL_3__debug_clr(reg_value) extract_field((reg_value),10,10) 3055 #define exc_PLL_CAL_COM_CTL_3__freqdet_time_msb(reg_value) extract_field((reg_value),9,9) 3056 #define exc_PLL_CAL_COM_CTL_3__freqdet_win(reg_value) extract_field((reg_value),7,0) 3057 #define exc_PLL_CAL_COM_CTL_4__halfstep_en(reg_value) extract_field((reg_value),15,15) 3058 #define exc_PLL_CAL_COM_CTL_4__pll_force_cap_pass_en(reg_value) extract_field((reg_value),14,14) 3059 #define exc_PLL_CAL_COM_CTL_4__pll_force_cap_pass(reg_value) extract_field((reg_value),13,13) 3060 #define exc_PLL_CAL_COM_CTL_4__cal_pause_en(reg_value) extract_field((reg_value),12,12) 3061 #define exc_PLL_CAL_COM_CTL_4__cal_pause_rel(reg_value) extract_field((reg_value),11,11) 3062 #define exc_PLL_CAL_COM_CTL_4__cap_delay(reg_value) extract_field((reg_value),10,10) 3063 #define exc_PLL_CAL_COM_CTL_4__calib_start(reg_value) extract_field((reg_value),9,9) 3064 #define exc_PLL_CAL_COM_CTL_4__en_calib_n(reg_value) extract_field((reg_value),8,8) 3065 #define exc_PLL_CAL_COM_CTL_4__ext_range(reg_value) extract_field((reg_value),6,0) 3066 #define exc_PLL_CAL_COM_CTL_5__pll_seq_start(reg_value) extract_field((reg_value),15,15) 3067 #define exc_PLL_CAL_COM_CTL_5__lkdt_pause_en(reg_value) extract_field((reg_value),14,14) 3068 #define exc_PLL_CAL_COM_CTL_5__lkdt_pause_rel(reg_value) extract_field((reg_value),13,13) 3069 #define exc_PLL_CAL_COM_CTL_5__vco_rst_en(reg_value) extract_field((reg_value),12,12) 3070 #define exc_PLL_CAL_COM_CTL_5__autocal_en(reg_value) extract_field((reg_value),8,8) 3071 #define exc_PLL_CAL_COM_CTL_5__autocal_cnt(reg_value) extract_field((reg_value),7,5) 3072 #define exc_PLL_CAL_COM_CTL_5__lkdt_byp(reg_value) extract_field((reg_value),4,4) 3073 #define exc_PLL_CAL_COM_CTL_5__pll_lock_frc_val(reg_value) extract_field((reg_value),3,3) 3074 #define exc_PLL_CAL_COM_CTL_5__pll_lock_frc(reg_value) extract_field((reg_value),2,2) 3075 #define exc_PLL_CAL_COM_CTL_5__pllforce_fdone(reg_value) extract_field((reg_value),1,1) 3076 #define exc_PLL_CAL_COM_CTL_5__pllforce_fdone_en(reg_value) extract_field((reg_value),0,0) 3077 #define exc_PLL_CAL_COM_CTL_6__band_iqbuf_sel(reg_value) extract_field((reg_value),7,7) 3078 #define exc_PLL_CAL_COM_CTL_6__vcorange_sel(reg_value) extract_field((reg_value),6,6) 3079 #define exc_PLL_CAL_COM_CTL_6__vcobufpon_sel(reg_value) extract_field((reg_value),5,5) 3080 #define exc_PLL_CAL_COM_CTL_6__vcopon_sel(reg_value) extract_field((reg_value),3,3) 3081 #define exc_PLL_CAL_COM_CTL_6__pllpon_sel(reg_value) extract_field((reg_value),1,1) 3082 #define exc_PLL_CAL_COM_STS_0__pll_fail_stky(reg_value) extract_field((reg_value),15,15) 3083 #define exc_PLL_CAL_COM_STS_0__cal_state(reg_value) extract_field((reg_value),14,11) 3084 #define exc_PLL_CAL_COM_STS_0__cal_valid(reg_value) extract_field((reg_value),10,10) 3085 #define exc_PLL_CAL_COM_STS_0__pll_lock(reg_value) extract_field((reg_value),9,9) 3086 #define exc_PLL_CAL_COM_STS_0__pll_lock_bar_stky(reg_value) extract_field((reg_value),8,8) 3087 #define exc_PLL_CAL_COM_STS_0__pll_range(reg_value) extract_field((reg_value),6,0) 3088 #define exc_PLL_CAL_COM_STS_1__lkdtref_counter_msb(reg_value) extract_field((reg_value),15,15) 3089 #define exc_PLL_CAL_COM_STS_1__lkdtvco_counter_msb(reg_value) extract_field((reg_value),14,14) 3090 #define exc_PLL_CAL_COM_STS_1__calref_counter(reg_value) extract_field((reg_value),12,0) 3091 #define exc_PLL_CAL_COM_STS_2__band_iqbuf_mux(reg_value) extract_field((reg_value),15,13) 3092 #define exc_PLL_CAL_COM_STS_2__calvco_counter(reg_value) extract_field((reg_value),12,0) 3093 #define exc_PLL_CAL_COM_STS_3__lkdtref_counter(reg_value) extract_field((reg_value),15,0) 3094 #define exc_PLL_CAL_COM_STS_4__lkdtvco_counter(reg_value) extract_field((reg_value),15,0) 3095 #define exc_PLL_CAL_COM_STS_5__vcobufpon_mux(reg_value) extract_field((reg_value),13,10) 3096 #define exc_PLL_CAL_COM_STS_5__calstate_onehot(reg_value) extract_field((reg_value),9,0) 3097 #define exc_PLL_CAL_COM_STS_6__pll_pwrdn_or(reg_value) extract_field((reg_value),15,15) 3098 #define exc_PLL_CAL_COM_STS_6__vco_range_mux(reg_value) extract_field((reg_value),14,8) 3099 #define exc_PLL_CAL_COM_STS_6__vcopon_mux(reg_value) extract_field((reg_value),7,4) 3100 #define exc_PLL_CAL_COM_STS_6__pllpon_mux(reg_value) extract_field((reg_value),3,0) 3101 #define ex_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_sigdet_pwrdn(reg_value) extract_field((reg_value),1,1) 3102 #define ex_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_rx_s_pwrdn(reg_value) extract_field((reg_value),0,0) 3103 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) 3104 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) 3105 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) 3106 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) 3107 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) 3108 #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__sigdet_dp_rstb_en(reg_value) extract_field((reg_value),2,2) 3109 #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) 3110 #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_s_rstb(reg_value) extract_field((reg_value),0,0) 3111 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc_val(reg_value) extract_field((reg_value),3,3) 3112 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc(reg_value) extract_field((reg_value),2,2) 3113 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) 3114 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) 3115 #define ex_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) 3116 #define ex_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS__pmd_lane_mode(reg_value) extract_field((reg_value),15,0) 3117 #define ex_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_rx_reset(reg_value) extract_field((reg_value),1,1) 3118 #define ex_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_rx_pwrdn(reg_value) extract_field((reg_value),0,0) 3119 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) 3120 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 3121 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__rx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 3122 #define ex_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL__rx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) 3123 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 3124 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 3125 #define ex_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 3126 #define ex_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 3127 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS__rx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 3128 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL__rx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 3129 #define ex_RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL__rx_multicast_mask_control(reg_value) extract_field((reg_value),0,0) 3130 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_multicast_mask_control_status(reg_value) extract_field((reg_value),4,4) 3131 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_osr_mode(reg_value) extract_field((reg_value),3,0) 3132 #define ex_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__rx_osr_mode_pin(reg_value) extract_field((reg_value),3,0) 3133 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc(reg_value) extract_field((reg_value),15,15) 3134 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 3135 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 3136 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL__ln_s_rstb(reg_value) extract_field((reg_value),0,0) 3137 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 3138 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 3139 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 3140 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 3141 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS__lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 3142 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL__lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 3143 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL__multicast_mask_control(reg_value) extract_field((reg_value),0,0) 3144 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK__multicast_mask_control_status(reg_value) extract_field((reg_value),4,4) 3145 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK__osr_mode(reg_value) extract_field((reg_value),3,0) 3146 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__osr_mode_pin(reg_value) extract_field((reg_value),3,0) 3147 #define ex_SIGDET_SDCTRL_0__signal_detect_filter_count(reg_value) extract_field((reg_value),4,0) 3148 #define ex_SIGDET_SDCTRL_0__los_filter_count(reg_value) extract_field((reg_value),9,5) 3149 #define ex_SIGDET_SDCTRL_0__energy_detect_mask_count(reg_value) extract_field((reg_value),14,10) 3150 #define ex_SIGDET_SDCTRL_1__afe_signal_detect_dis(reg_value) extract_field((reg_value),0,0) 3151 #define ex_SIGDET_SDCTRL_1__ext_los_en(reg_value) extract_field((reg_value),1,1) 3152 #define ex_SIGDET_SDCTRL_1__ext_los_inv(reg_value) extract_field((reg_value),2,2) 3153 #define ex_SIGDET_SDCTRL_1__ignore_lp_mode(reg_value) extract_field((reg_value),3,3) 3154 #define ex_SIGDET_SDCTRL_1__signal_detect_filter_1us(reg_value) extract_field((reg_value),4,4) 3155 #define ex_SIGDET_SDCTRL_1__energy_detect_frc(reg_value) extract_field((reg_value),5,5) 3156 #define ex_SIGDET_SDCTRL_1__energy_detect_frc_val(reg_value) extract_field((reg_value),6,6) 3157 #define ex_SIGDET_SDCTRL_1__signal_detect_frc(reg_value) extract_field((reg_value),7,7) 3158 #define ex_SIGDET_SDCTRL_1__signal_detect_frc_val(reg_value) extract_field((reg_value),8,8) 3159 #define ex_SIGDET_SDCTRL_2__los_thresh(reg_value) extract_field((reg_value),4,0) 3160 #define ex_SIGDET_SDCTRL_2__signal_detect_thresh(reg_value) extract_field((reg_value),9,5) 3161 #define ex_SIGDET_SDCTRL_2__hold_los_count(reg_value) extract_field((reg_value),12,10) 3162 #define ex_SIGDET_SDCTRL_2__hold_sd_count(reg_value) extract_field((reg_value),15,13) 3163 #define ex_SIGDET_SDSTATUS_0__signal_detect(reg_value) extract_field((reg_value),0,0) 3164 #define ex_SIGDET_SDSTATUS_0__signal_detect_change(reg_value) extract_field((reg_value),1,1) 3165 #define ex_SIGDET_SDSTATUS_0__signal_detect_raw(reg_value) extract_field((reg_value),4,4) 3166 #define ex_SIGDET_SDSTATUS_0__signal_detect_raw_change(reg_value) extract_field((reg_value),5,5) 3167 #define ex_SIGDET_SDSTATUS_0__ext_sigdet(reg_value) extract_field((reg_value),6,6) 3168 #define ex_SIGDET_SDSTATUS_0__ext_sigdet_change(reg_value) extract_field((reg_value),7,7) 3169 #define ex_SIGDET_SDSTATUS_0__afe_sigdet(reg_value) extract_field((reg_value),8,8) 3170 #define ex_SIGDET_SDSTATUS_0__afe_sigdet_change(reg_value) extract_field((reg_value),9,9) 3171 #define ex_SIGDET_SDSTATUS_1__uc_signal_detect(reg_value) extract_field((reg_value),0,0) 3172 #define ex_SIGDET_SDSTATUS_1__uc_signal_detect_change(reg_value) extract_field((reg_value),1,1) 3173 #define ex_SIGDET_SDSTATUS_1__uc_ext_sigdet(reg_value) extract_field((reg_value),6,6) 3174 #define ex_SIGDET_SDSTATUS_1__uc_ext_sigdet_change(reg_value) extract_field((reg_value),7,7) 3175 #define ex_SIGDET_SDSTATUS_1__uc_afe_sigdet(reg_value) extract_field((reg_value),8,8) 3176 #define ex_SIGDET_SDSTATUS_1__uc_afe_sigdet_change(reg_value) extract_field((reg_value),9,9) 3177 #define ex_SIGDET_SDSTATUS_2__energy_detect(reg_value) extract_field((reg_value),0,0) 3178 #define ex_SIGDET_SDSTATUS_2__energy_detect_change(reg_value) extract_field((reg_value),1,1) 3179 #define ex_SIGDET_SDSTATUS_3__pmd_signal_detect(reg_value) extract_field((reg_value),0,0) 3180 #define ex_SIGDET_SDSTATUS_4__afe_sigdet_thresh(reg_value) extract_field((reg_value),4,0) 3181 #define exc_TEST_WRAPPER_CONTROL_0__test_ctl_ckgt_en(reg_value) extract_field((reg_value),7,7) 3182 #define exc_TEST_WRAPPER_CONTROL_0__test_ctl_rstb(reg_value) extract_field((reg_value),6,6) 3183 #define exc_TEST_WRAPPER_CONTROL_0__test_phfifo_err_lh_clr(reg_value) extract_field((reg_value),4,4) 3184 #define exc_TEST_WRAPPER_CONTROL_0__test_phfifo_auto_recenter_en(reg_value) extract_field((reg_value),2,2) 3185 #define exc_TEST_WRAPPER_CONTROL_0__test_phfifo_recenter(reg_value) extract_field((reg_value),1,1) 3186 #define exc_TEST_WRAPPER_CONTROL_0__test_ext_rmt_lpbk_en(reg_value) extract_field((reg_value),0,0) 3187 #define exc_TEST_WRAPPER_STATUS_0__test_sta_phfifo_err(reg_value) extract_field((reg_value),0,0) 3188 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_burst_err_cnt_en(reg_value) extract_field((reg_value),15,15) 3189 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_clk_en_frc_on(reg_value) extract_field((reg_value),11,11) 3190 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__trnsum_error_count_en(reg_value) extract_field((reg_value),10,10) 3191 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_err_cnt_burst_mode(reg_value) extract_field((reg_value),9,9) 3192 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_en_auto_mode(reg_value) extract_field((reg_value),7,7) 3193 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_mode(reg_value) extract_field((reg_value),6,5) 3194 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_inv(reg_value) extract_field((reg_value),4,4) 3195 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_mode_sel(reg_value) extract_field((reg_value),3,1) 3196 #define ex_TLB_RX_RXPRBS_CHK_CONFIG__prbs_chk_en(reg_value) extract_field((reg_value),0,0) 3197 #define ex_TLB_RX_RXPRBS_CHK_CNT_CONFIG__prbs_chk_lock_cnt(reg_value) extract_field((reg_value),4,0) 3198 #define ex_TLB_RX_RXPRBS_CHK_CNT_CONFIG__prbs_chk_ool_cnt(reg_value) extract_field((reg_value),12,8) 3199 #define ex_TLB_RX_RXDIG_LPBK_CONFIG__dig_lpbk_pd_bias_en(reg_value) extract_field((reg_value),3,3) 3200 #define ex_TLB_RX_RXDIG_LPBK_CONFIG__dig_lpbk_pd_flt_bypass(reg_value) extract_field((reg_value),2,2) 3201 #define ex_TLB_RX_RXDIG_LPBK_CONFIG__dig_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) 3202 #define ex_TLB_RX_RXDIG_LPBK_CONFIG__dig_lpbk_en(reg_value) extract_field((reg_value),0,0) 3203 #define ex_TLB_RX_RXMISC_CONFIG__dbg_mask_dig_lpbk_en(reg_value) extract_field((reg_value),2,2) 3204 #define ex_TLB_RX_RXMISC_CONFIG__rx_aggregator_bypass_en(reg_value) extract_field((reg_value),1,1) 3205 #define ex_TLB_RX_RXMISC_CONFIG__rx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) 3206 #define ex_TLB_RX_RXPRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timeout(reg_value) extract_field((reg_value),12,8) 3207 #define ex_TLB_RX_RXPRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timer_mode(reg_value) extract_field((reg_value),1,0) 3208 #define ex_TLB_RX_RXDIG_LPBK_PD_STATUS__dig_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) 3209 #define ex_TLB_RX_RXDIG_LPBK_PD_STATUS__dig_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) 3210 #define ex_TLB_RX_RXPRBS_CHK_LOCK_STATUS__prbs_chk_err_cnt_no_clr(reg_value) extract_field((reg_value),15,1) 3211 #define ex_TLB_RX_RXPRBS_CHK_LOCK_STATUS__prbs_chk_lock(reg_value) extract_field((reg_value),0,0) 3212 #define ex_TLB_RX_RXPRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_lock_lost_lh(reg_value) extract_field((reg_value),15,15) 3213 #define ex_TLB_RX_RXPRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_err_cnt_msb(reg_value) extract_field((reg_value),14,0) 3214 #define ex_TLB_RX_RXPRBS_CHK_ERR_CNT_LSB_STATUS__prbs_chk_err_cnt_lsb(reg_value) extract_field((reg_value),15,0) 3215 #define ex_TLB_RX_RXPMD_RX_LOCK_STATUS__pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 3216 #define ex_TLB_RX_RXPMD_RX_LOCK_STATUS__pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 3217 #define ex_TLB_RX_RXDBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 3218 #define ex_TLB_RX_RXDBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 3219 #define ex_TLB_RX_RXUC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 3220 #define ex_TLB_RX_RXUC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 3221 #define ex_TLB_RX_RXPRBS_CHK_BURST_ERR_CNT_STATUS__prbs_chk_burst_err_cnt(reg_value) extract_field((reg_value),9,0) 3222 #define ex_TLB_TX_TXPATT_GEN_CONFIG__patt_gen_start_pos(reg_value) extract_field((reg_value),15,12) 3223 #define ex_TLB_TX_TXPATT_GEN_CONFIG__patt_gen_stop_pos(reg_value) extract_field((reg_value),11,8) 3224 #define ex_TLB_TX_TXPATT_GEN_CONFIG__patt_gen_en(reg_value) extract_field((reg_value),0,0) 3225 #define ex_TLB_TX_TXPRBS_GEN_CONFIG__prbs_gen_err_ins(reg_value) extract_field((reg_value),5,5) 3226 #define ex_TLB_TX_TXPRBS_GEN_CONFIG__prbs_gen_inv(reg_value) extract_field((reg_value),4,4) 3227 #define ex_TLB_TX_TXPRBS_GEN_CONFIG__prbs_gen_mode_sel(reg_value) extract_field((reg_value),3,1) 3228 #define ex_TLB_TX_TXPRBS_GEN_CONFIG__prbs_gen_en(reg_value) extract_field((reg_value),0,0) 3229 #define ex_TLB_TX_TXRMT_LPBK_CONFIG__rmt_lpbk_pd_frc_on(reg_value) extract_field((reg_value),2,2) 3230 #define ex_TLB_TX_TXRMT_LPBK_CONFIG__rmt_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) 3231 #define ex_TLB_TX_TXRMT_LPBK_CONFIG__rmt_lpbk_en(reg_value) extract_field((reg_value),0,0) 3232 #define ex_TLB_TX_TXMISC_CONFIG__tx_mux_sel_order(reg_value) extract_field((reg_value),2,2) 3233 #define ex_TLB_TX_TXMISC_CONFIG__tx_pcs_native_ana_frmt_en(reg_value) extract_field((reg_value),1,1) 3234 #define ex_TLB_TX_TXMISC_CONFIG__tx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) 3235 #define ex_TLB_TX_TXRMT_LPBK_PD_STATUS__rmt_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) 3236 #define ex_TLB_TX_TXRMT_LPBK_PD_STATUS__rmt_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) 3237 #define ex_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_tx_reset_deassert(reg_value) extract_field((reg_value),15,15) 3238 #define ex_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_tx_s_pwrdn(reg_value) extract_field((reg_value),0,0) 3239 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) 3240 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) 3241 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) 3242 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) 3243 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) 3244 #define ex_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) 3245 #define ex_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_s_rstb(reg_value) extract_field((reg_value),0,0) 3246 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_txclk_reset_frc_val(reg_value) extract_field((reg_value),5,5) 3247 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_txclk_reset_frc(reg_value) extract_field((reg_value),4,4) 3248 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc_val(reg_value) extract_field((reg_value),3,3) 3249 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc(reg_value) extract_field((reg_value),2,2) 3250 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) 3251 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) 3252 #define ex_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) 3253 #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_txclk_reset(reg_value) extract_field((reg_value),2,2) 3254 #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_tx_reset(reg_value) extract_field((reg_value),1,1) 3255 #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_tx_pwrdn(reg_value) extract_field((reg_value),0,0) 3256 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL__tx_pi_loop_filter_stable(reg_value) extract_field((reg_value),0,0) 3257 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_post2(reg_value) extract_field((reg_value),3,0) 3258 #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe_error(reg_value) extract_field((reg_value),6,6) 3259 #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe_int_en(reg_value) extract_field((reg_value),5,5) 3260 #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe(reg_value) extract_field((reg_value),4,4) 3261 #define ex_TX_FED_MISC_CONTROL0__tx_disable_output_sel(reg_value) extract_field((reg_value),3,2) 3262 #define ex_TX_FED_MISC_CONTROL0__sdk_tx_disable(reg_value) extract_field((reg_value),0,0) 3263 #define ex_TX_FED_MISC_STATUS0__tx_elec_idle_status(reg_value) extract_field((reg_value),1,1) 3264 #define ex_TX_FED_MISC_STATUS0__tx_disable_status(reg_value) extract_field((reg_value),0,0) 3265 #define ex_TX_FED_MICRO_CONTROL0__tx_eee_alert_en(reg_value) extract_field((reg_value),15,15) 3266 #define ex_TX_FED_MICRO_CONTROL0__tx_eee_quiet_en(reg_value) extract_field((reg_value),14,14) 3267 #define ex_TX_FED_MICRO_CONTROL0__tx_disable_timer_ctrl(reg_value) extract_field((reg_value),9,4) 3268 #define ex_TX_FED_MICRO_CONTROL0__pmd_tx_disable_pkill(reg_value) extract_field((reg_value),3,3) 3269 #define ex_TX_FED_MICRO_CONTROL0__dp_reset_tx_disable_dis(reg_value) extract_field((reg_value),2,2) 3270 #define ex_TX_FED_MICRO_CONTROL0__tx_disable_trigger(reg_value) extract_field((reg_value),1,1) 3271 #define ex_TX_FED_MICRO_CONTROL0__micro_tx_disable(reg_value) extract_field((reg_value),0,0) 3272 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_2x_1(reg_value) extract_field((reg_value),7,7) 3273 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_2x_1(reg_value) extract_field((reg_value),6,6) 3274 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_2x_0(reg_value) extract_field((reg_value),5,5) 3275 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_2x_0(reg_value) extract_field((reg_value),4,4) 3276 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_1x_1(reg_value) extract_field((reg_value),3,3) 3277 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_1x_1(reg_value) extract_field((reg_value),2,2) 3278 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_1x_0(reg_value) extract_field((reg_value),1,1) 3279 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_1x_0(reg_value) extract_field((reg_value),0,0) 3280 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1pre_1x_0(reg_value) extract_field((reg_value),14,14) 3281 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1pre_1x_0(reg_value) extract_field((reg_value),13,13) 3282 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_pre_post1pre_1x_0(reg_value) extract_field((reg_value),12,12) 3283 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_2(reg_value) extract_field((reg_value),9,9) 3284 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_2(reg_value) extract_field((reg_value),8,8) 3285 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_1(reg_value) extract_field((reg_value),7,7) 3286 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_1(reg_value) extract_field((reg_value),6,6) 3287 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_0(reg_value) extract_field((reg_value),5,5) 3288 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_0(reg_value) extract_field((reg_value),4,4) 3289 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_1x_1(reg_value) extract_field((reg_value),3,3) 3290 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_1x_1(reg_value) extract_field((reg_value),2,2) 3291 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_1x_0(reg_value) extract_field((reg_value),1,1) 3292 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_1x_0(reg_value) extract_field((reg_value),0,0) 3293 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_3(reg_value) extract_field((reg_value),14,14) 3294 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_3(reg_value) extract_field((reg_value),13,13) 3295 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_3(reg_value) extract_field((reg_value),12,12) 3296 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_2(reg_value) extract_field((reg_value),11,11) 3297 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_2(reg_value) extract_field((reg_value),10,10) 3298 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_2(reg_value) extract_field((reg_value),9,9) 3299 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_1(reg_value) extract_field((reg_value),8,8) 3300 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_1(reg_value) extract_field((reg_value),7,7) 3301 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_1(reg_value) extract_field((reg_value),6,6) 3302 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_0(reg_value) extract_field((reg_value),5,5) 3303 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_0(reg_value) extract_field((reg_value),4,4) 3304 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_0(reg_value) extract_field((reg_value),3,3) 3305 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_1x_1(reg_value) extract_field((reg_value),2,2) 3306 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_1x_1(reg_value) extract_field((reg_value),1,1) 3307 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_1x_1(reg_value) extract_field((reg_value),0,0) 3308 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_2x_1(reg_value) extract_field((reg_value),3,3) 3309 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_2x_0(reg_value) extract_field((reg_value),2,2) 3310 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_1x(reg_value) extract_field((reg_value),1,1) 3311 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_0p5x(reg_value) extract_field((reg_value),0,0) 3312 #define ex_TX_PI_TXPICONTROL_0__tx_pi_en(reg_value) extract_field((reg_value),0,0) 3313 #define ex_TX_PI_TXPICONTROL_0__tx_pi_jitter_filter_en(reg_value) extract_field((reg_value),1,1) 3314 #define ex_TX_PI_TXPICONTROL_0__tx_pi_ext_ctrl_en(reg_value) extract_field((reg_value),2,2) 3315 #define ex_TX_PI_TXPICONTROL_0__tx_pi_freq_override_en(reg_value) extract_field((reg_value),3,3) 3316 #define ex_TX_PI_TXPICONTROL_0__tx_pi_sj_gen_en(reg_value) extract_field((reg_value),4,4) 3317 #define ex_TX_PI_TXPICONTROL_0__tx_pi_ssc_gen_en(reg_value) extract_field((reg_value),5,5) 3318 #define ex_TX_PI_TXPICONTROL_0__tx_pi_jit_ssc_freq_mode(reg_value) extract_field((reg_value),6,6) 3319 #define ex_TX_PI_TXPICONTROL_0__tx_pi_reset_code_dbg(reg_value) extract_field((reg_value),7,7) 3320 #define ex_TX_PI_TXPICONTROL_0__tx_pi_second_order_loop_en(reg_value) extract_field((reg_value),8,8) 3321 #define ex_TX_PI_TXPICONTROL_0__tx_pi_first_order_bwsel_integ(reg_value) extract_field((reg_value),11,10) 3322 #define ex_TX_PI_TXPICONTROL_0__tx_pi_second_order_bwsel_integ(reg_value) extract_field((reg_value),13,12) 3323 #define ex_TX_PI_TXPICONTROL_0__tx_pi_frc_phase_step_mux_sel(reg_value) extract_field((reg_value),15,15) 3324 #define ex_TX_PI_TXPICONTROL_1__tx_pi_freq_override_val(reg_value) extract_field_signed((reg_value),14,0) 3325 #define ex_TX_PI_TXPICONTROL_2__tx_pi_jit_freq_idx(reg_value) extract_field((reg_value),5,0) 3326 #define ex_TX_PI_TXPICONTROL_2__tx_pi_jit_amp(reg_value) extract_field((reg_value),13,8) 3327 #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_override(reg_value) extract_field((reg_value),0,0) 3328 #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_strobe(reg_value) extract_field((reg_value),1,1) 3329 #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_step_dir(reg_value) extract_field((reg_value),2,2) 3330 #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_invert(reg_value) extract_field((reg_value),4,4) 3331 #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_step_num(reg_value) extract_field((reg_value),11,8) 3332 #define ex_TX_PI_TXPICONTROL_3__tx_pi_ext_phase_bwsel_integ(reg_value) extract_field((reg_value),14,12) 3333 #define ex_TX_PI_TXPICONTROL_4__tx_pi_frz_frc(reg_value) extract_field((reg_value),0,0) 3334 #define ex_TX_PI_TXPICONTROL_4__tx_pi_frz_frc_val(reg_value) extract_field((reg_value),1,1) 3335 #define ex_TX_PI_TXPICONTROL_4__tx_pi_frz_mode(reg_value) extract_field((reg_value),2,2) 3336 #define ex_TX_PI_TXPICONTROL_5__tx_pi_hs_fifo_phserr_invert(reg_value) extract_field((reg_value),1,1) 3337 #define ex_TX_PI_TXPICONTROL_5__tx_pi_repeater_mode_en(reg_value) extract_field((reg_value),2,2) 3338 #define ex_TX_PI_TXPICONTROL_5__tx_pi_ext_pd_sel(reg_value) extract_field((reg_value),3,3) 3339 #define ex_TX_PI_TXPICONTROL_5__afe_tx_fifo_resetb(reg_value) extract_field((reg_value),8,8) 3340 #define ex_TX_PI_TXPICONTROL_5__afe_tx_fifo_resetb_frc_on(reg_value) extract_field((reg_value),9,9) 3341 #define ex_TX_PI_TXPICONTROL_5__tx_pi_pd_bypass_flt(reg_value) extract_field((reg_value),10,10) 3342 #define ex_TX_PI_TXPICONTROL_5__tx_pi_pd_bypass_vco(reg_value) extract_field((reg_value),11,11) 3343 #define ex_TX_PI_TXPISTATUS_0__tx_pi_phase_cntr(reg_value) extract_field_signed((reg_value),6,0) 3344 #define ex_TX_PI_TXPISTATUS_1__tx_pi_integ1_reg(reg_value) extract_field_signed((reg_value),13,0) 3345 #define ex_TX_PI_TXPISTATUS_2__tx_pi_integ2_reg(reg_value) extract_field_signed((reg_value),14,0) 3346 #define ex_TX_PI_TXPISTATUS_3__tx_pi_phase_err(reg_value) extract_field_signed((reg_value),5,0) 3347 #define ex_TX_PI_TXPISTATUS_4__st_afe_tx_fifo_resetb(reg_value) extract_field((reg_value),1,1) 3348 #define ex_TX_PI_TXPISTATUS_4__tx_pi_hs_fifo_phserr(reg_value) extract_field((reg_value),0,0) 3349 #define ex_TX_PI_TX_FIFO_OVFB_STATUS__tx_fifo_ovfb_fall_edge_lh(reg_value) extract_field((reg_value),1,1) 3350 #define ex_TX_PI_TX_FIFO_OVFB_STATUS__tx_fifo_ovfb(reg_value) extract_field((reg_value),0,0) 3351 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) 3352 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 3353 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__tx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 3354 #define ex_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL__tx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) 3355 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 3356 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 3357 #define ex_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 3358 #define ex_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 3359 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS__tx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 3360 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL__tx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 3361 #define ex_TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL__tx_multicast_mask_control(reg_value) extract_field((reg_value),0,0) 3362 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_multicast_mask_control_status(reg_value) extract_field((reg_value),4,4) 3363 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_osr_mode(reg_value) extract_field((reg_value),3,0) 3364 #define ex_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__tx_osr_mode_pin(reg_value) extract_field((reg_value),3,0) 3365 #define exc_TX_COM_TXCOM_CONTROL0_REGISTER__txcom_cl72_max_wait_timer_period(reg_value) extract_field((reg_value),15,0) 3366 #define exc_TX_COM_TXCOM_CONTROL1_REGISTER__txcom_cl72_wait_cntr_limit(reg_value) extract_field((reg_value),8,0) 3367 3368 #endif