merlin16_cfg_seq.c (15358B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 /* 10 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 11 * 12 */ 13 14 #include <phymod/phymod.h> 15 #include <phymod/phymod_system.h> 16 #include "merlin16_cfg_seq.h" 17 #include "merlin16_functions.h" 18 #include <phymod/chip/bcmi_tsce16_xgxs_defs.h> 19 #include "merlin16_fields.h" 20 #include "merlin16_dependencies.h" 21 #include "merlin16_field_access.h" 22 #include "merlin16_debug_functions.h" 23 #include "merlin16_internal.h" 24 25 /** Macro to execute a statement with automatic return of error LESTM(Local ESTM) to fix coverity error */ 26 #define LESTM(statement) do {err_code_t __err = ERR_CODE_NONE; statement; if (__err) return(__err); } while(0) 27 /** Macro to invoke a function with automatic return of error */ 28 #define LEFUN(fun) do {err_code_t __err = (fun); if (__err) return(__err); } while(0) 29 30 err_code_t merlin16_uc_active_set(const phymod_access_t *sa__, uint32_t enable) /* set microcontroller active or not */ 31 { 32 err_code_t __err; 33 __err=ERR_CODE_NONE; 34 __err=wrc_uc_active(enable); if (__err) return(__err); 35 36 return ERR_CODE_NONE; 37 } 38 39 err_code_t merlin16_uc_active_get(const phymod_access_t *sa__, uint32_t *enable) /* get microcontroller active or not */ 40 { 41 err_code_t __err; 42 __err=ERR_CODE_NONE; 43 *enable=rdc_uc_active(); 44 if (__err) return(__err); 45 46 return ERR_CODE_NONE; 47 } 48 49 err_code_t merlin16_pmd_ln_h_rstb_pkill_override(const phymod_access_t *sa__, uint16_t val) 50 { 51 err_code_t __err; 52 __err=ERR_CODE_NONE; 53 __err=wr_pmd_ln_h_rstb_pkill(val); if (__err) return(__err); 54 55 return ERR_CODE_NONE; 56 } 57 58 err_code_t merlin16_core_soft_reset_release(const phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 59 { 60 err_code_t __err; 61 __err=ERR_CODE_NONE; 62 __err=wrc_core_dp_s_rstb(enable); if (__err) return(__err); 63 64 return ERR_CODE_NONE; 65 } 66 67 err_code_t merlin16_lane_hard_soft_reset_release(const phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 68 { 69 err_code_t __err; 70 __err=ERR_CODE_NONE; 71 __err=wr_ln_s_rstb(enable); if (__err) return(__err); 72 73 return ERR_CODE_NONE; 74 } 75 76 err_code_t merlin16_lane_soft_reset_release(const phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 77 { 78 err_code_t __err; 79 __err=ERR_CODE_NONE; 80 __err=wr_ln_dp_s_rstb(enable); if (__err) return(__err); 81 82 return ERR_CODE_NONE; 83 } 84 85 err_code_t merlin16_lane_soft_reset_release_get(const phymod_access_t *sa__, uint32_t *enable) /* release the pmd core soft reset */ 86 { 87 err_code_t __err; 88 __err=ERR_CODE_NONE; 89 90 *enable=rd_ln_dp_s_rstb(); if(__err) return(__err); 91 92 return ERR_CODE_NONE; 93 } 94 95 err_code_t merlin16_rx_lane_soft_reset_release(const phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 96 { 97 err_code_t __err; 98 __err=ERR_CODE_NONE; 99 __err=wr_ln_rx_dp_s_rstb(enable); if (__err) return(__err); 100 101 return ERR_CODE_NONE; 102 } 103 104 err_code_t merlin16_tx_lane_soft_reset_release(const phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 105 { 106 err_code_t __err; 107 __err=ERR_CODE_NONE; 108 __err=wr_ln_tx_dp_s_rstb(enable); if (__err) return(__err); 109 110 return ERR_CODE_NONE; 111 } 112 113 err_code_t merlin16_rx_lane_soft_reset_release_get(const phymod_access_t *sa__, uint32_t *enable) /* release the pmd rx lane soft reset */ 114 { 115 err_code_t __err; 116 __err=ERR_CODE_NONE; 117 118 *enable=rd_ln_rx_dp_s_rstb(); if(__err) return(__err); 119 120 return ERR_CODE_NONE; 121 } 122 123 err_code_t merlin16_tx_lane_soft_reset_release_get(const phymod_access_t *sa__, uint32_t *enable) /* release the pmd tx lane soft reset */ 124 { 125 err_code_t __err; 126 __err=ERR_CODE_NONE; 127 128 *enable=rd_ln_tx_dp_s_rstb(); if(__err) return(__err); 129 130 return ERR_CODE_NONE; 131 } 132 133 134 err_code_t merlin16_pmd_tx_disable_pin_dis_set(const phymod_access_t *sa__, uint32_t enable) 135 { 136 err_code_t __err; 137 __err=ERR_CODE_NONE; 138 __err=wr_pmd_tx_disable_pkill(enable); if (__err) return(__err); 139 140 return ERR_CODE_NONE; 141 } 142 143 err_code_t merlin16_pmd_loopback_set(const phymod_access_t *sa__, uint32_t enable) 144 { 145 err_code_t __err; 146 __err=ERR_CODE_NONE; 147 148 __err=merlin16_dig_lpbk(sa__, enable); if (__err) return(__err); 149 __err=wr_signal_detect_frc(1); if (__err) return(__err); 150 __err=wr_signal_detect_frc_val(1); if (__err) return(__err); 151 152 return ERR_CODE_NONE; 153 } 154 155 err_code_t merlin16_pmd_loopback_get(const phymod_access_t *sa__, uint32_t *enable) 156 { 157 err_code_t __err; 158 __err=ERR_CODE_NONE; 159 *enable=rd_dig_lpbk_en(); 160 if (__err) return(__err); 161 162 return ERR_CODE_NONE; 163 } 164 165 err_code_t merlin16_rmt_lpbk_get(const phymod_access_t *sa__, uint32_t *lpbk) 166 { 167 err_code_t __err; 168 __err=ERR_CODE_NONE; 169 *lpbk=rd_rmt_lpbk_en(); 170 if (__err) return(__err); 171 172 return ERR_CODE_NONE; 173 } 174 175 err_code_t merlin16_osr_mode_get(const phymod_access_t *sa__, int *osr_mode) 176 { 177 int osr_forced; 178 err_code_t __err; 179 __err=ERR_CODE_NONE; 180 osr_forced = rd_osr_mode_frc(); 181 if (osr_forced) { 182 *osr_mode = rd_osr_mode_frc_val(); 183 if (__err) 184 return(__err); 185 } else { 186 *osr_mode = rd_osr_mode_pin(); 187 if (__err) 188 return (__err); 189 } 190 191 return ERR_CODE_NONE; 192 } 193 194 int merlin16_osr_mode_to_enum(int osr_mode, phymod_osr_mode_t* osr_mode_en) 195 { 196 switch (osr_mode) { 197 case 0: *osr_mode_en = phymodOversampleMode1; break; 198 case 1: *osr_mode_en = phymodOversampleMode2; break; 199 case 2: *osr_mode_en = phymodOversampleMode3; break; 200 case 3: *osr_mode_en = phymodOversampleMode3P3; break; 201 case 4: *osr_mode_en = phymodOversampleMode4; break; 202 case 5: *osr_mode_en = phymodOversampleMode5; break; 203 case 6: *osr_mode_en = phymodOversampleMode7P5; break; 204 case 7: *osr_mode_en = phymodOversampleMode8; break; 205 case 8: *osr_mode_en = phymodOversampleMode8P25; break; 206 case 9: *osr_mode_en = phymodOversampleMode10; break; 207 default: 208 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("unsupported OS mode %d"), osr_mode)); 209 } 210 return PHYMOD_E_NONE; 211 } 212 213 err_code_t merlin16_pmd_cl72_enable_get(const phymod_access_t* sa__, uint32_t* cl72_en) 214 { 215 err_code_t __err; 216 __err=ERR_CODE_NONE; 217 *cl72_en = rd_cl72_ieee_training_enable(); if (__err) return(__err); 218 return ERR_CODE_NONE; 219 } 220 221 err_code_t merlin16_pmd_cl72_receiver_status(const phymod_access_t* sa__, uint32_t* status) 222 { 223 err_code_t __err; 224 __err=ERR_CODE_NONE; 225 *status = rd_cl72_ieee_receiver_status(); if (__err) return(__err); 226 return ERR_CODE_NONE; 227 } 228 229 err_code_t merlin16_polarity_set(const phymod_access_t *sa__, uint32_t tx_polarity, uint32_t rx_polarity) 230 { 231 err_code_t __err; 232 __err=ERR_CODE_NONE; 233 __err=wr_tx_pmd_dp_invert(tx_polarity); if (__err) return(__err); 234 __err=wr_rx_pmd_dp_invert(rx_polarity); if (__err) return(__err); 235 return ERR_CODE_NONE; 236 } 237 238 err_code_t merlin16_polarity_get(const phymod_access_t *sa__, uint32_t* tx_polarity, uint32_t* rx_polarity) 239 { 240 err_code_t __err; 241 __err=ERR_CODE_NONE; 242 *tx_polarity=rd_tx_pmd_dp_invert(); if (__err) return(__err); 243 *rx_polarity=rd_rx_pmd_dp_invert(); if (__err) return(__err); 244 return ERR_CODE_NONE; 245 } 246 247 err_code_t merlin16_ucode_pram_load_pre(const phymod_access_t *sa__) 248 { 249 err_code_t __err; 250 __err=ERR_CODE_NONE; 251 252 __err = wrc_micro_master_clk_en(0x1); if(__err) return(__err); /* Enable clock to microcontroller subsystem */ 253 __err = wrc_micro_master_rstb(0x1); if(__err) return(__err); /* De-assert reset to microcontroller sybsystem */ 254 __err = wrc_micro_master_rstb(0x0); if(__err) return(__err); /* Assert reset to microcontroller sybsystem - Toggling reset*/ 255 __err = wrc_micro_master_rstb(0x1); if(__err) return(__err); /* De-assert reset to microcontroller sybsystem */ 256 257 __err = wrc_micro_ra_init(0x1); if(__err) return(__err); /* Set initialization command to initialize code RAM */ 258 __err = merlin16_INTERNAL_poll_micro_ra_initdone(sa__, 250); if(__err) return(__err); /* Poll for micro_ra_initdone = 1 to indicate initialization done */ 259 260 __err = wrc_micro_ra_init(0x0); if(__err) return(__err); /* Clear initialization command */ 261 __err = wrc_micro_pramif_ahb_wraddr_msw(0x0000); if(__err) return(__err); 262 __err = wrc_micro_pramif_ahb_wraddr_lsw(0x0000); if(__err) return(__err); 263 __err = wrc_micro_pram_if_rstb(1); if(__err) return(__err); 264 __err = wrc_micro_pramif_en(1); if(__err) return(__err); 265 266 /* Wait 8 pram clocks */ 267 EFUN(USR_DELAY_US(1)); 268 269 return ERR_CODE_NONE; 270 } 271 272 err_code_t merlin16_ucode_pram_load_post(const phymod_access_t *sa__) 273 { 274 err_code_t __err; 275 __err=ERR_CODE_NONE; 276 277 /* Wait 8 pram clocks */ 278 EFUN(USR_DELAY_US(1)); 279 280 __err = wrc_micro_pramif_en(0); if(__err) return(__err); 281 __err = wrc_micro_core_clk_en(1); if(__err) return(__err); 282 283 return ERR_CODE_NONE; 284 } 285 286 err_code_t merlin16_identify(const phymod_access_t *sa__, merlin16_rev_id0_t *rev_id0, merlin16_rev_id1_t *rev_id1) 287 { 288 err_code_t __err; 289 290 rev_id0->revid_rev_letter =0; 291 rev_id0->revid_rev_number =0; 292 rev_id0->revid_bonding =0; 293 rev_id0->revid_process =0; 294 rev_id0->revid_model =0; 295 296 rev_id1->revid_multiplicity =0; 297 rev_id1->revid_mdio =0; 298 rev_id1->revid_micro =0; 299 rev_id1->revid_cl72 =0; 300 rev_id1->revid_pir =0; 301 rev_id1->revid_llp =0; 302 rev_id1->revid_eee =0; 303 304 __err=ERR_CODE_NONE; 305 306 rev_id0->revid_rev_letter =rdc_revid_rev_letter(); if(__err) return(__err); 307 rev_id0->revid_rev_number =rdc_revid_rev_number(); if(__err) return(__err); 308 rev_id0->revid_bonding =rdc_revid_bonding(); if(__err) return(__err); 309 rev_id0->revid_process =rdc_revid_process(); if(__err) return(__err); 310 rev_id0->revid_model =rdc_revid_model(); if(__err) return(__err); 311 312 rev_id1->revid_multiplicity =rdc_revid_multiplicity(); if(__err) return(__err); 313 rev_id1->revid_mdio =rdc_revid_mdio(); if(__err) return(__err); 314 rev_id1->revid_micro =rdc_revid_micro(); if(__err) return(__err); 315 rev_id1->revid_cl72 =rdc_revid_cl72(); if(__err) return(__err); 316 rev_id1->revid_pir =rdc_revid_pir(); if(__err) return(__err); 317 rev_id1->revid_llp =rdc_revid_llp(); if(__err) return(__err); 318 rev_id1->revid_eee =rdc_revid_eee(); if(__err) return(__err); 319 320 return ERR_CODE_NONE; 321 } 322 323 err_code_t merlin16_pwrdn_set(const phymod_access_t *sa__, int tx_rx, int pwrdn) 324 { 325 err_code_t __err; 326 __err=ERR_CODE_NONE; 327 if(tx_rx) { 328 __err = (uint32_t) wr_ln_tx_s_pwrdn(pwrdn); 329 } else { 330 __err = (uint32_t) wr_ln_rx_s_pwrdn(pwrdn); 331 } 332 if(__err) return(__err); 333 334 return ERR_CODE_NONE; 335 } 336 337 err_code_t merlin16_pwrdn_get(const phymod_access_t *sa__, power_status_t *pwrdn) 338 { 339 err_code_t __err; 340 __err=ERR_CODE_NONE; 341 pwrdn->pll_pwrdn = 0; 342 pwrdn->tx_s_pwrdn = 0; 343 pwrdn->rx_s_pwrdn = 0; 344 pwrdn->pll_pwrdn = rdc_afe_s_pll_pwrdn(); if(__err) return(__err); 345 pwrdn->tx_s_pwrdn = rd_ln_tx_s_pwrdn(); if(__err) return(__err); 346 pwrdn->rx_s_pwrdn = rd_ln_rx_s_pwrdn(); if(__err) return(__err); 347 348 return ERR_CODE_NONE; 349 } 350 351 err_code_t merlin16_tx_disable_get(const phymod_access_t *sa__, uint32_t* en) 352 { 353 err_code_t __err; 354 __err=ERR_CODE_NONE; 355 356 *en = rd_sdk_tx_disable(); if(__err) return(__err); 357 358 return ERR_CODE_NONE; 359 } 360 361 err_code_t merlin16_rx_lane_control_set(const phymod_access_t *sa__, uint32_t en) 362 { 363 err_code_t __err; 364 __err=ERR_CODE_NONE; 365 366 if(en) { 367 __err = wr_signal_detect_frc(1); if(__err) return(__err); 368 __err = wr_signal_detect_frc_val(0); if(__err) return(__err); 369 } else { 370 __err = wr_signal_detect_frc(0); if(__err) return(__err); 371 __err = wr_signal_detect_frc_val(0); if(__err) return(__err); 372 } 373 374 return ERR_CODE_NONE; 375 } 376 377 378 err_code_t merlin16_rx_lane_control_get(const phymod_access_t *sa__, uint32_t* en) 379 { 380 err_code_t __err; 381 __err=ERR_CODE_NONE; 382 383 *en = rd_signal_detect_frc(); if(__err) return(__err); 384 385 return ERR_CODE_NONE; 386 } 387 388 err_code_t merlin16_clause72_control(const phymod_access_t* sa__, int cl72_en) /* CLAUSE_72_CONTROL */ 389 { 390 err_code_t __err; 391 392 __err=wr_cl72_ieee_training_enable(cl72_en); if (__err) return(__err); 393 __err=wr_cl72_ieee_restart_training(cl72_en); if (__err) return(__err); 394 395 return PHYMOD_E_NONE; 396 } 397 398 err_code_t merlin16_get_pll_vco_osmode (const phymod_phy_inf_config_t* config, uint32_t *new_pll_div, int16_t *new_os_mode) { 399 *new_pll_div=0; 400 *new_os_mode =0; 401 402 if(config->ref_clock == phymodRefClk156Mhz) { 403 switch (config->data_rate) { 404 case 9375 : /*speed 9.375G*/ 405 *new_pll_div = MERLIN16_PLL_DIV_60; *new_os_mode = 1; 406 break; 407 408 case 10000 : /* speed 10G */ 409 *new_pll_div = MERLIN16_PLL_DIV_64; *new_os_mode = 1; 410 break; 411 412 case 10312: /* speed 10.3125G */ 413 *new_pll_div = MERLIN16_PLL_DIV_66; *new_os_mode = 1; 414 break; 415 416 case 10937: /* speed 10.9375G */ 417 *new_pll_div = MERLIN16_PLL_DIV_70; *new_os_mode = 1; 418 break; 419 420 case 11250: /*speed 11.25G*/ 421 *new_pll_div = MERLIN16_PLL_DIV_72; *new_os_mode = 1; 422 break; 423 424 case 12500: /* speed 12.5G */ 425 *new_pll_div = MERLIN16_PLL_DIV_80; *new_os_mode = 1; 426 break; 427 428 default: 429 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d\n", (int)config->data_rate, config->ref_clock)); 430 return ERR_CODE_DIAG; 431 break; 432 } 433 } 434 return(ERR_CODE_NONE); 435 } 436 437 err_code_t merlin16_osmode_set(const phymod_access_t* sa__, int16_t os_mode) 438 { 439 err_code_t __err; 440 441 __err=wr_osr_mode_frc(1); if (__err) return(__err); 442 __err=wr_osr_mode_frc_val(os_mode); if (__err) return(__err); 443 444 return PHYMOD_E_NONE; 445 } 446 447 err_code_t merlin16_pmd_reset_seq(const phymod_access_t *sa__, int pmd_touched) 448 { 449 err_code_t __err; 450 __err=ERR_CODE_NONE; 451 452 if (pmd_touched == 0) { 453 __err = wrc_core_s_rstb(1); if(__err) return(__err); 454 __err = wrc_core_dp_s_rstb(1); if(__err) return(__err); 455 } 456 return (ERR_CODE_NONE); 457 } 458 459 err_code_t merlin16_refclk_set(const phymod_access_t *sa__, phymod_ref_clk_t ref_clock) 460 { 461 err_code_t __err = ERR_CODE_NONE; 462 463 switch (ref_clock) { 464 case phymodRefClk156Mhz: 465 __err = wrc_heartbeat_count_1us(0x271); 466 break; 467 case phymodRefClk125Mhz: 468 __err = wrc_heartbeat_count_1us(0x1f4); 469 break; 470 default: 471 __err = wrc_heartbeat_count_1us(0x271); 472 break; 473 } 474 475 return __err; 476 } 477 478 err_code_t merlin16_tsc_rx_ppm(const phymod_access_t *sa__, int16_t *rx_ppm) 479 { 480 err_code_t __err; 481 __err=ERR_CODE_NONE; 482 *rx_ppm = rd_cdr_integ_reg() / 84; 483 return (ERR_CODE_NONE); 484 } 485