madura_cfg_seq.h (33919B)
1 /*---------------------------------------------------------------------- 2 * 3 * Broadcom Corporation 4 * Proprietary and Confidential information 5 * All rights reserved 6 * This source file is the property of Broadcom Corporation, and 7 * may not be copied or distributed in any isomorphic form without the 8 * prior written consent of Broadcom Corporation. 9 *--------------------------------------------------------------------- 10 * File : madura_cfg_seq.h 11 * Description: c functions implementing Tier1 12 *---------------------------------------------------------------------*/ 13 /* 14 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 15 * 16 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 17 * 18 */ 19 20 21 #ifndef MADURA_CFG_SEQ_H 22 #define MADURA_CFG_SEQ_H 23 #include <phymod/phymod_acc.h> 24 25 #define MADURA_DEV_PMA_PMD 1 26 #define MADURA_DEV_AN 7 27 #define MADURA_M0_EEPROM_PAGE_SIZE 64 28 #define MADURA_FW_DLOAD_RETRY_CNT 40 29 #define MADURA_AN_SET_RETRY_CNT 20 30 #define MADURA_FORCE_TRAIN_RETRY_CNT 20 31 #define MADURA_ULL_SET_RETRY_CNT 200 32 #define MADURA_RPTR_SET_RETRY_CNT 200 33 #define MADURA_ENABLE 1 34 #define MADURA_DISABLE 0 35 #define MADURA_SPD_100G 100000 36 #define MADURA_SPD_106G 106000 37 #define MADURA_SPD_10G 10000 38 #define MADURA_SPD_11G 11000 39 #define MADURA_SPD_40G 40000 40 #define MADURA_SPD_20G 20000 41 #define MADURA_SPD_42G 42000 42 #define MADURA_SPD_25G 25000 43 #define MADURA_SPD_50G 50000 44 #define MADURA_SPD_1G 1000 45 #define MADURA_MAX_FALCON_LANE 4 46 #define MADURA_MAX_2X_FALCON_LANE 8 47 #define MADURA_MST_INTR_GRP 0 48 #define MADURA_PLL_INTR_GRP 1 49 #define MADURA_CL73_INTR_GRP 2 50 #define MADURA_MISC0_INTR_GRP 3 51 #define MADURA_MISC1_INTR_GRP 4 52 #define MADURA_MCTRL_INTR_GRP 5 53 #define MADURA_FW_ALREADY_DOWNLOADED 0xFAD 54 #define MADURA_PMD_ID0 0xAE02 55 #define MADURA_PMD_ID1 0x52b0 56 #define MADURA_CHIP_ID_82864 0x82864 57 #define DEV1_SLICE_SLICE_ADR 0x8000 58 #define DEV7_SLICE_SLICE_ADR 0x8000 59 #define MADURA_MODULE_CNTRL_RAM_NVR0_ADR 0x8800 60 #define MADURA_MAX_INTRS_SUPPORT 8 61 62 typedef enum { 63 MSGOUT_DONTCARE = 0x0000, 64 MSGOUT_GET_CNT = 0x8888, 65 MSGOUT_GET_LSB = 0xABCD, 66 MSGOUT_GET_MSB = 0x4321, 67 MSGOUT_GET_2B = 0xEEEE, 68 MSGOUT_GET_B = 0xF00D, 69 MSGOUT_ERR = 0x0BAD, 70 MSGOUT_NEXT = 0x2222, 71 MSGOUT_FLASH = 0xF1AC, 72 MSGOUT_NOT_DWNLD = 0x0101, 73 MSGOUT_DWNLD_ALREADY = 0x0202, 74 MSGOUT_DWNLD_DONE = 0x0303, 75 MSGOUT_PRGRM_DONE = 0x0404/*changed from 1414!*/ 76 } MADURA_MSGOUT_E; 77 78 typedef enum { 79 MADURA_2X_FALCON_CORE = 0, 80 MADURA_FALCON_CORE = 1 81 }MADURA_CORE_TYPE; 82 83 /** Madura Device Aux mode structure 84 * This structure is used to set different modes 85 * 86 * @param pass_thru Set this to 1 for pass thru mode and 0 for Demux mode 87 * @param alternate Set this to 1 for pass thru alternate mode 88 * @param pass_thru_dual_lane Set this to 1 for 40G pass thru dual mode 89 * @param passthru_sys_side_core used internally by the drivers 90 */ 91 92 typedef struct { 93 uint16_t pass_thru; 94 uint16_t alternate; 95 uint16_t pass_thru_dual_lane; 96 MADURA_CORE_TYPE passthru_sys_side_core; 97 }MADURA_DEVICE_AUX_MODE_T; 98 99 100 typedef struct { 101 uint32_t an_mst_lane_p0; 102 uint32_t an_mst_lane_p1; 103 }MADURA_DEVICE_STATIC_AUX_MODE_T; 104 105 106 typedef enum { 107 MADURA_SLICE_UNICAST = 0, 108 MADURA_SLICE_MULTICAST = 1, 109 MADURA_SLICE_BROADCAST = 2, 110 MADURA_CAST_INVALID = 3 111 }MADURA_SLICE_CAST_TYPE; 112 113 typedef enum { 114 MADURA_IF_LINE = 0, 115 MADURA_IF_SYS = 1 116 }MADURA_IF_SIDE; 117 118 typedef enum { 119 MADURA_AN_NONE = 0, 120 MADURA_AN_CL73 = 1, 121 MADURA_AN_PROP = 2 122 }MADURA_AN_MODE; 123 124 typedef enum { 125 MADURA_PLL_MODE_64 = 0x0, /*4'b0000*/ 126 MADURA_PLL_MODE_66 = 0x1, /*4'b0001*/ 127 MADURA_PLL_MODE_80 = 0x2, /*4'b0010*/ 128 MADURA_PLL_MODE_128 = 0x3, /*4'b0011*/ 129 MADURA_PLL_MODE_132 = 0x4, /*4'b0100*/ 130 MADURA_PLL_MODE_140 = 0x5, /*4'b0101*/ 131 MADURA_PLL_MODE_160 = 0x6, /*4'b0110*/ 132 MADURA_PLL_MODE_165 = 0x7, /*4'b0111*/ 133 MADURA_PLL_MODE_168 = 0x8, /*4'b1000*/ 134 MADURA_PLL_MODE_170 = 0x9, /*4'b1001*/ 135 MADURA_PLL_MODE_175 = 0xa, /*4'b1010*/ 136 MADURA_PLL_MODE_180 = 0xb, /*4'b1011*/ 137 MADURA_PLL_MODE_184 = 0xc, /*4'b1100*/ 138 MADURA_PLL_MODE_200 = 0xd, /*4'b1101*/ 139 MADURA_PLL_MODE_224 = 0xe, /*4'b1110*/ 140 MADURA_PLL_MODE_264 = 0xf, /*4'b1111*/ 141 MADURA_PLL_MODE_INVALID = -1 142 } MADURA_PLL_MODE_E; 143 144 typedef enum PHY82864_INTERRUPT { 145 INT_TIMESYNC_FRAMESYNC, 146 INT_TIMESYNC_TIMESTAMP, 147 INT_M0_SLV_MISC, 148 INT_M0_MST_MISC, 149 INT_M0_SLV_MSGOUT, 150 INT_M0_MST_MSGOUT, 151 INT_MUX_PMDLOCKLOST, 152 INT_MUX_PMDLOCKFOUND, 153 INT_MUX_SIGDETLOST, 154 INT_MUX_SIGDETFOUND, 155 INT_MUX_PCSMONLOCKLOST, 156 INT_MUX_PCSMONLOCKFOUND, 157 INT_MUX_FIFOERR, 158 INT_MUX_CL73_RESTARTED, 159 INT_MUX_CL73_COMPLETE, 160 INT_MUX_CL73_RESTARTEDP2, 161 INT_MUX_CL73_RESTARTEDP1, 162 INT_MUX_CL73_COMPLETEP2, 163 INT_MUX_CL73_COMPLETEP1, 164 INT_CL73_AN_RESTARTED_L0, 165 INT_CL73_AN_RESTARTED_L1, 166 INT_CL73_AN_RESTARTED_L2, 167 INT_CL73_AN_RESTARTED_L3, 168 INT_CL73_AN_COMPLETE_L0, 169 INT_CL73_AN_COMPLETE_L1, 170 INT_CL73_AN_COMPLETE_L2, 171 INT_CL73_AN_COMPLETE_L3, 172 INT_DEMUX_PMDLOCKLOST, 173 INT_DEMUX_PMDLOCKFOUND, 174 INT_DEMUX_SIGDETLOST, 175 INT_DEMUX_SIGDETFOUND, 176 INT_DEMUX_PCSMONLOCKLOST, 177 INT_DEMUX_PCSMONLOCKFOUND, 178 INT_DEMUX_FIFOERR, 179 INT_DEMUX_CL73_RESTARTED, 180 INT_DEMUX_CL73_COMPLETE, 181 INT_PLL_10G_LOCKLOST, 182 INT_PLL_10G_LOCKFOUND, 183 INT_PLL_25G_LOCKLOST, 184 INT_PLL_25G_LOCKFOUND, 185 INT_SYS_PLL_LOCKLOST, 186 INT_SYS_PLL_LOCKFOUND, 187 INT_LINE_PLL_LOCKLOST, 188 INT_LINE_PLL_LOCKFOUND, 189 PHY82864_MAX_INT 190 }PHY82864_INTERRUPT_T; 191 192 typedef enum { 193 MADURA_INT_MODULE1_INTRB_HIGH, 194 MADURA_INT_MODULE1_INTRB_LOW, 195 MADURA_INT_MODULE2_INTRB_HIGH, 196 MADURA_INT_MODULE2_INTRB_LOW, 197 MADURA_INT_M0_MST_SEC, 198 MADURA_INT_M0_MST_DED, 199 MADURA_INT_M0_MST_MSGOUT_INTR, 200 MADURA_INT_M0_MST_MISC_INTR, 201 MADURA_INT_M0_MST_LOCKUP, 202 MADURA_INT_M0_MST_SYSRESETREQ, 203 MADURA_INT_SYS_FAL_0_PLL0_LOCK_FOUND, 204 MADURA_INT_SYS_FAL_0_PLL0_LOCK_LOST, 205 MADURA_INT_SYS_FAL_0_PLL1_LOCK_FOUND, 206 MADURA_INT_SYS_FAL_0_PLL1_LOCK_LOST, 207 MADURA_INT_SYS_FAL_1_PLL0_LOCK_FOUND, 208 MADURA_INT_SYS_FAL_1_PLL0_LOCK_LOST, 209 MADURA_INT_SYS_FAL_1_PLL1_LOCK_FOUND, 210 MADURA_INT_SYS_FAL_1_PLL1_LOCK_LOST, 211 MADURA_INT_LIN_FAL_0_PLL0_LOCK_FOUND, 212 MADURA_INT_LIN_FAL_0_PLL0_LOCK_LOST, 213 MADURA_INT_LIN_FAL_0_PLL1_LOCK_FOUND, 214 MADURA_INT_LIN_FAL_0_PLL1_LOCK_LOST, 215 MADURA_INT_LIN_FAL_1_PLL0_LOCK_FOUND, 216 MADURA_INT_LIN_FAL_1_PLL0_LOCK_LOST, 217 MADURA_INT_LIN_FAL_1_PLL1_LOCK_FOUND, 218 MADURA_INT_LIN_FAL_1_PLL1_LOCK_LOST, 219 MADURA_INT_SYS_CL73_INCOMPATIBLE_LINK_0, 220 MADURA_INT_SYS_CL73_INCOMPATIBLE_LINK_1, 221 MADURA_INT_SYS_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_0, 222 MADURA_INT_SYS_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_1, 223 MADURA_INT_SYS_CL73_AN_COMPLETE_P1, 224 MADURA_INT_SYS_CL73_AN_RESTARTED_P1, 225 MADURA_INT_SYS_CL73_AN_COMPLETE_P2, 226 MADURA_INT_SYS_CL73_AN_RESTARTED_P2, 227 MADURA_INT_LIN_CL73_INCOMPATIBLE_LINK_0, 228 MADURA_INT_LIN_CL73_INCOMPATIBLE_LINK_1, 229 MADURA_INT_LIN_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_0, 230 MADURA_INT_LIN_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_1, 231 MADURA_INT_LIN_CL73_AN_COMPLETE_P1, 232 MADURA_INT_LIN_CL73_AN_RESTARTED_P1, 233 MADURA_INT_LIN_CL73_AN_COMPLETE_P2, 234 MADURA_INT_LIN_CL73_AN_RESTARTED_P2, 235 MADURA_INT_SYS_SIGDET_FOUND, 236 MADURA_INT_SYS_SIGDET_LOST, 237 MADURA_INT_SYS_PMD_LOCK_FOUND, 238 MADURA_INT_SYS_PMD_LOCK_LOST, 239 MADURA_INT_SYS_FAL_0_PMI_ARB_WDOG_EXP, 240 MADURA_INT_SYS_FAL_1_PMI_ARB_WDOG_EXP, 241 MADURA_INT_LIN_SIGDET_FOUND, 242 MADURA_INT_LIN_SIGDET_LOST, 243 MADURA_INT_LIN_PMD_LOCK_FOUND, 244 MADURA_INT_LIN_PMD_LOCK_LOST, 245 MADURA_INT_LIN_FAL_0_PMI_ARB_WDOG_EXP, 246 MADURA_INT_LIN_FAL_1_PMI_ARB_WDOG_EXP, 247 MADURA_INT_ONEG_INBAND_MSG_LOCK_FOUND, 248 MADURA_INT_ONEG_INBAND_MSG_LOCK_LOST, 249 MADURA_INT_SYS_PCS_MON_LOCK_FOUND, 250 MADURA_INT_SYS_PCS_MON_LOCK_LOST, 251 MADURA_INT_LIN_PCS_MON_LOCK_FOUND, 252 MADURA_INT_LIN_PCS_MON_LOCK_LOST, 253 MADURA_INT_CL91_0_RX_FEC_ALIGN_FOUND, 254 MADURA_INT_CL91_0_RX_FEC_ALIGN_LOST, 255 MADURA_INT_CL91_1_RX_FEC_ALIGN_FOUND, 256 MADURA_INT_CL91_1_RX_FEC_ALIGN_LOST, 257 MADURA_INT_CL91_0_TX_PCS_ALIGN_FOUND, 258 MADURA_INT_CL91_0_TX_PCS_ALIGN_LOST, 259 MADURA_INT_CL91_1_TX_PCS_ALIGN_FOUND, 260 MADURA_INT_CL91_1_TX_PCS_ALIGN_LOST, 261 MADURA_INT_SYS_FIFOERR, 262 MADURA_INT_LIN_FIFOERR 263 } MADURA_INTR_TYPE_E; 264 265 #define MADURA_IF_ERR_RETURN_FREE(B, A) \ 266 do { \ 267 int loc_err ; \ 268 if ((loc_err = (A)) != PHYMOD_E_NONE) \ 269 { if (B) { PHYMOD_FREE(B) ; } ; return loc_err ; } \ 270 } while (0) 271 272 #define READ_MADURA_PMA_PMD_REG(acc, addr, value) \ 273 do { \ 274 uint32_t read_tmp; \ 275 PHYMOD_IF_ERR_RETURN \ 276 (PHYMOD_BUS_READ(acc, ((MADURA_DEV_PMA_PMD << 16) | addr), &read_tmp)); \ 277 value = (read_tmp & 0xffff); \ 278 } while (0); 279 280 #define WRITE_MADURA_PMA_PMD_REG(acc, addr, value) \ 281 PHYMOD_IF_ERR_RETURN \ 282 (PHYMOD_BUS_WRITE(acc, (MADURA_DEV_PMA_PMD << 16) | addr, value)); 283 284 #define READ_MADURA_AN_REG(acc, addr, value) \ 285 do { \ 286 uint32_t an_read_tmp; \ 287 PHYMOD_IF_ERR_RETURN \ 288 (PHYMOD_BUS_READ(acc, ((MADURA_DEV_AN << 16) | addr), &an_read_tmp)); \ 289 value = (an_read_tmp & 0xffff); \ 290 } while (0); 291 292 #define WRITE_MADURA_AN_REG(acc, addr, value) \ 293 PHYMOD_IF_ERR_RETURN \ 294 (PHYMOD_BUS_WRITE(acc, (MADURA_DEV_AN << 16) | addr, value)); 295 296 #define MADURA_GET_CORE(_C, _LT, _ST) \ 297 { \ 298 MADURA_DEVICE_AUX_MODE_T *aux_mode_m; \ 299 aux_mode_m = (MADURA_DEVICE_AUX_MODE_T*)_C.device_aux_modes; \ 300 if (aux_mode_m->pass_thru) { \ 301 _LT = (aux_mode_m->passthru_sys_side_core == MADURA_FALCON_CORE) ? MADURA_2X_FALCON_CORE : MADURA_FALCON_CORE; \ 302 } else { \ 303 _LT = MADURA_2X_FALCON_CORE; \ 304 } \ 305 _ST = (_LT == MADURA_2X_FALCON_CORE) ? MADURA_FALCON_CORE : MADURA_2X_FALCON_CORE; \ 306 } 307 308 #define MADURA_IS_MULTI_BROAD_CAST_SET(_C) (_C == MADURA_SLICE_MULTICAST || _C == MADURA_SLICE_BROADCAST) 309 #define MADURA_GET_INTF_SIDE(pa, if_side) (if_side = (pa->flags >> 31) ? MADURA_IF_SYS : MADURA_IF_LINE) 310 311 #define MADURA_GET_CORE_SLICE_INFO(_ACC, _IP, _CON ) \ 312 do { \ 313 MADURA_CORE_TYPE line_ip_type, sys_ip_type; \ 314 uint16_t intf_side = 0; \ 315 MADURA_GET_INTF_SIDE(_ACC, intf_side); \ 316 MADURA_GET_CORE(_CON, line_ip_type, sys_ip_type); \ 317 _IP = (intf_side == MADURA_IF_LINE) ? line_ip_type : sys_ip_type; \ 318 }while(0); 319 320 #define MADURA_GET_IP(_ACC, _CON, _IP) \ 321 do { \ 322 MADURA_CORE_TYPE line_ip_type, sys_ip_type; \ 323 uint16_t intf_side = 0; \ 324 MADURA_GET_INTF_SIDE(_ACC, intf_side); \ 325 MADURA_GET_CORE(_CON, line_ip_type, sys_ip_type); \ 326 _IP = (intf_side == MADURA_IF_LINE) ? line_ip_type : sys_ip_type; \ 327 }while(0); 328 329 #define MADURA_RESET_SLICE(_P, _DT) \ 330 if (_DT == MADURA_DEV_PMA_PMD) { \ 331 WRITE_MADURA_PMA_PMD_REG(_P, DEV1_SLICE_SLICE_ADR, 0x0); \ 332 } else { \ 333 WRITE_MADURA_AN_REG(_P, DEV7_SLICE_SLICE_ADR, 0x0); \ 334 } 335 336 #define MADURA_GET_PORT_FROM_MODE(_C, _PRT, aux_mode) \ 337 do { \ 338 if (_C->data_rate == MADURA_SPD_100G || \ 339 _C->data_rate == MADURA_SPD_106G) { \ 340 _PRT = 1; \ 341 } else if (_C->data_rate == MADURA_SPD_40G && aux_mode->pass_thru_dual_lane) { \ 342 _PRT = 2; \ 343 } else if (_C->data_rate == MADURA_SPD_50G && aux_mode->pass_thru_dual_lane) { \ 344 _PRT = 2; \ 345 } else if (_C->data_rate == MADURA_SPD_40G && aux_mode->pass_thru) { \ 346 _PRT = 1; \ 347 } else if (_C->data_rate == MADURA_SPD_40G && (!aux_mode->pass_thru)){ \ 348 _PRT = 2; \ 349 } else if (_C->data_rate == MADURA_SPD_42G && aux_mode->pass_thru_dual_lane) { \ 350 _PRT = 2; \ 351 } else if (_C->data_rate == MADURA_SPD_42G && aux_mode->pass_thru) { \ 352 _PRT = 1; \ 353 } else if (_C->data_rate == MADURA_SPD_42G && (!aux_mode->pass_thru)){ \ 354 _PRT = 2; \ 355 } else if (_C->data_rate == MADURA_SPD_10G || \ 356 _C->data_rate == MADURA_SPD_11G || \ 357 _C->data_rate == MADURA_SPD_1G || \ 358 _C->data_rate == MADURA_SPD_25G) { \ 359 _PRT = 4; \ 360 } \ 361 }while(0); 362 363 typedef enum { 364 MADURA_CL73_NO_TECH = 0, 365 MADURA_CL73_1000GBASE_KX = 0x1, 366 MADURA_CL73_10GBASE_KR = 0x4, 367 MADURA_CL73_40GBASE_KR4 = 0x8, 368 MADURA_CL73_40GBASE_CR4 = 0x10, 369 MADURA_CL73_100GBASE_KR4 = 0x80, 370 MADURA_CL73_100GBASE_CR4 = 0x100 371 } MADURA_CL73_SPEED_T; 372 373 typedef enum { 374 MADURA_NO_PAUSE = 0, 375 MADURA_ASYM_PAUSE, 376 MADURA_SYMM_PAUSE, 377 MADURA_ASYM_SYMM_PAUSE, 378 MADURA_AN_PAUSE_COUNT 379 } MADURA_AN_PAUSE_T; 380 381 /* Module controller I2C master commands */ 382 typedef enum { 383 MADURA_FLUSH = 0, 384 MADURA_RANDOM_ADDRESS_READ, 385 MADURA_CURRENT_ADDRESS_READ, 386 MADURA_WRITE 387 } MADURA_I2CM_CMD_E; 388 389 typedef struct MADURA_AN_ADV_ABILITY_S{ 390 MADURA_CL73_SPEED_T an_base_speed; 391 MADURA_AN_PAUSE_T an_pause; 392 uint16_t an_fec; 393 } madura_an_adv_ability_t; 394 395 typedef struct madura_an_ability_s { 396 madura_an_adv_ability_t cl73_adv; /*includes cl73 related */ 397 uint32_t an_master_lane; /* Master lane belongs to port. For 10 lane port[0-9], for 4 lane port [0-3], for 2 lane port [0-1]*/ 398 } madura_an_ability_t; 399 400 typedef enum { 401 MADURA_MIDX_10GPT_0 = 0x80 , 402 MADURA_MIDX_10GPT_0A = 0xC0 , 403 MADURA_MIDX_10HGPT_0 = 0x88 , 404 MADURA_MIDX_10HGPT_0A = 0xC8 , 405 MADURA_MIDX_FC4PT_0 = 0x90 , 406 MADURA_MIDX_FC4PT_0A = 0xD0 , 407 MADURA_MIDX_FC8PT_0 = 0x98 , 408 MADURA_MIDX_FC8PT_0A = 0xD8 , 409 MADURA_MIDX_FC16PT_0 = 0xA0 , 410 MADURA_MIDX_FC16PT_0A = 0xE0 , 411 MADURA_MIDX_FC32PT_0 = 0xA8 , 412 MADURA_MIDX_FC32PT_0A = 0xE8 , 413 MADURA_MIDX_OTU2_1e_2e_PT_0 = 0xB0 , 414 MADURA_MIDX_OTU2_1e_2e_PT_0A = 0xF0 , 415 MADURA_MIDX_10GPT_1 = 0x81 , 416 MADURA_MIDX_10GPT_1A = 0xC1 , 417 MADURA_MIDX_10HGPT_1 = 0x89 , 418 MADURA_MIDX_10HGPT_1A = 0xC9 , 419 MADURA_MIDX_FC4PT_1 = 0x91 , 420 MADURA_MIDX_FC4PT_1A = 0xD1 , 421 MADURA_MIDX_FC8PT_1 = 0x99 , 422 MADURA_MIDX_FC8PT_1A = 0xD9 , 423 MADURA_MIDX_FC16PT_1 = 0xA1 , 424 MADURA_MIDX_FC16PT_1A = 0xE1 , 425 MADURA_MIDX_FC32PT_1 = 0xA9 , 426 MADURA_MIDX_FC32PT_1A = 0xE9 , 427 MADURA_MIDX_OTU2_1e_2e_PT_1 = 0xB1 , 428 MADURA_MIDX_OTU2_1e_2e_PT_1A = 0xF1 , 429 MADURA_MIDX_10GPT_2 = 0x82 , 430 MADURA_MIDX_10GPT_2A = 0xC2 , 431 MADURA_MIDX_10HGPT_2 = 0x8A , 432 MADURA_MIDX_10HGPT_2A = 0xCA , 433 MADURA_MIDX_FC4PT_2 = 0x92 , 434 MADURA_MIDX_FC4PT_2A = 0xD2 , 435 MADURA_MIDX_FC8PT_2 = 0x9A , 436 MADURA_MIDX_FC8PT_2A = 0xDA , 437 MADURA_MIDX_FC16PT_2 = 0xA2 , 438 MADURA_MIDX_FC16PT_2A = 0xE2 , 439 MADURA_MIDX_FC32PT_2 = 0xAA , 440 MADURA_MIDX_FC32PT_2A = 0xEA , 441 MADURA_MIDX_OTU2_1e_2e_PT_2 = 0xB2 , 442 MADURA_MIDX_OTU2_1e_2e_PT_2A = 0xF2 , 443 MADURA_MIDX_10GPT_3 = 0x83 , 444 MADURA_MIDX_10GPT_3A = 0xC3 , 445 MADURA_MIDX_10HGPT_3 = 0x8B , 446 MADURA_MIDX_10HGPT_3A = 0xCB , 447 MADURA_MIDX_FC4PT_3 = 0x93 , 448 MADURA_MIDX_FC4PT_3A = 0xD3 , 449 MADURA_MIDX_FC8PT_3 = 0x9B , 450 MADURA_MIDX_FC8PT_3A = 0xDB , 451 MADURA_MIDX_FC16PT_3 = 0xA3 , 452 MADURA_MIDX_FC16PT_3A = 0xE3 , 453 MADURA_MIDX_FC32PT_3 = 0xAB , 454 MADURA_MIDX_FC32PT_3A = 0xEB , 455 MADURA_MIDX_OTU2_1e_2e_PT_3 = 0xB3 , 456 MADURA_MIDX_OTU2_1e_2e_PT_3A = 0xF3 , 457 MADURA_MIDX_10GPT_4 = 0x84 , 458 MADURA_MIDX_10GPT_4A = 0xC4 , 459 MADURA_MIDX_10HGPT_4 = 0x8C , 460 MADURA_MIDX_10HGPT_4A = 0xCC , 461 MADURA_MIDX_FC4PT_4 = 0x94 , 462 MADURA_MIDX_FC4PT_4A = 0xD4 , 463 MADURA_MIDX_FC8PT_4 = 0x9C , 464 MADURA_MIDX_FC8PT_4A = 0xDC , 465 MADURA_MIDX_FC16PT_4 = 0xA4 , 466 MADURA_MIDX_FC16PT_4A = 0xE4 , 467 MADURA_MIDX_FC32PT_4 = 0xAC , 468 MADURA_MIDX_FC32PT_4A = 0xEC , 469 MADURA_MIDX_OTU2_1e_2e_PT_4 = 0xB4 , 470 MADURA_MIDX_OTU2_1e_2e_PT_4A = 0xF4 , 471 MADURA_MIDX_10GPT_5 = 0x85 , 472 MADURA_MIDX_10GPT_5A = 0xC5 , 473 MADURA_MIDX_10HGPT_5 = 0x8D , 474 MADURA_MIDX_10HGPT_5A = 0xCD , 475 MADURA_MIDX_FC4PT_5 = 0x95 , 476 MADURA_MIDX_FC4PT_5A = 0xD5 , 477 MADURA_MIDX_FC8PT_5 = 0x9D , 478 MADURA_MIDX_FC8PT_5A = 0xDD , 479 MADURA_MIDX_FC16PT_5 = 0xA5 , 480 MADURA_MIDX_FC16PT_5A = 0xE5 , 481 MADURA_MIDX_FC32PT_5 = 0xAD , 482 MADURA_MIDX_FC32PT_5A = 0xED , 483 MADURA_MIDX_OTU2_1e_2e_PT_5 = 0xB5 , 484 MADURA_MIDX_OTU2_1e_2e_PT_5A = 0xF5 , 485 MADURA_MIDX_10GPT_6 = 0x86 , 486 MADURA_MIDX_10GPT_6A = 0xC6 , 487 MADURA_MIDX_10HGPT_6 = 0x8E , 488 MADURA_MIDX_10HGPT_6A = 0xCE , 489 MADURA_MIDX_FC4PT_6 = 0x96 , 490 MADURA_MIDX_FC4PT_6A = 0xD6 , 491 MADURA_MIDX_FC8PT_6 = 0x9E , 492 MADURA_MIDX_FC8PT_6A = 0xDE , 493 MADURA_MIDX_FC16PT_6 = 0xA6 , 494 MADURA_MIDX_FC16PT_6A = 0xE6 , 495 MADURA_MIDX_FC32PT_6 = 0xAE , 496 MADURA_MIDX_FC32PT_6A = 0xEE , 497 MADURA_MIDX_OTU2_1e_2e_PT_6 = 0xB6 , 498 MADURA_MIDX_OTU2_1e_2e_PT_6A = 0xF6 , 499 MADURA_MIDX_10GPT_7 = 0x87 , 500 MADURA_MIDX_10GPT_7A = 0xC7 , 501 MADURA_MIDX_10HGPT_7 = 0x8F , 502 MADURA_MIDX_10HGPT_7A = 0xCF , 503 MADURA_MIDX_FC4PT_7 = 0x97 , 504 MADURA_MIDX_FC4PT_7A = 0xD7 , 505 MADURA_MIDX_FC8PT_7 = 0x9F , 506 MADURA_MIDX_FC8PT_7A = 0xDF , 507 MADURA_MIDX_FC16PT_7 = 0xA7 , 508 MADURA_MIDX_FC16PT_7A = 0xE7 , 509 MADURA_MIDX_FC32PT_7 = 0xAF , 510 MADURA_MIDX_FC32PT_7A = 0xEF , 511 MADURA_MIDX_OTU2_1e_2e_PT_7 = 0xB7 , 512 MADURA_MIDX_OTU2_1e_2e_PT_7A = 0xF7 , 513 MADURA_MIDX_40GPT20_0 = 0x00 , 514 MADURA_MIDX_40GPT20_0A = 0x40 , 515 MADURA_MIDX_40GPT20_1 = 0x01 , 516 MADURA_MIDX_40GPT20_1A = 0x41 , 517 MADURA_MIDX_40GPT20_2 = 0x02 , 518 MADURA_MIDX_40GPT20_2A = 0x42 , 519 MADURA_MIDX_40GPT20_3 = 0x03 , 520 MADURA_MIDX_40GPT20_3A = 0x43 , 521 MADURA_MIDX_40HGPT20_0 = 0x04 , 522 MADURA_MIDX_40HGPT20_0A = 0x44 , 523 MADURA_MIDX_40HGPT20_1 = 0x05 , 524 MADURA_MIDX_40HGPT20_1A = 0x45 , 525 MADURA_MIDX_40HGPT20_2 = 0x06 , 526 MADURA_MIDX_40HGPT20_2A = 0x46 , 527 MADURA_MIDX_40HGPT20_3 = 0x07 , 528 MADURA_MIDX_40HGPT20_3A = 0x47 , 529 MADURA_MIDX_OTU3PT_0 = 0x10 , 530 MADURA_MIDX_OTU3PT_0A = 0x50 , 531 MADURA_MIDX_OTU3PT_1 = 0x11 , 532 MADURA_MIDX_OTU3PT_1A = 0x51 , 533 MADURA_MIDX_OTU4PT_0 = 0x12 , 534 MADURA_MIDX_OTU4PT_0A = 0x52 , 535 MADURA_MIDX_OTU4PT_1 = 0x13 , 536 MADURA_MIDX_OTU4PT_1A = 0x53 , 537 MADURA_MIDX_40GPT10_0 = 0x18 , 538 MADURA_MIDX_40GPT10_0A = 0x58 , 539 MADURA_MIDX_40GPT10_1 = 0x19 , 540 MADURA_MIDX_40GPT10_1A = 0x59 , 541 MADURA_MIDX_100GPT_0 = 0x1A , 542 MADURA_MIDX_100GPT_0A = 0x5A , 543 MADURA_MIDX_100GPT_1 = 0x1B , 544 MADURA_MIDX_100GPT_1A = 0x5B , 545 MADURA_MIDX_40HGPT10_0 = 0x1C , 546 MADURA_MIDX_40HGPT10_0A = 0x5C , 547 MADURA_MIDX_40HGPT10_1 = 0x1D , 548 MADURA_MIDX_40HGPT10_1A = 0x5D , 549 MADURA_MIDX_100HGPT_0 = 0x1E , 550 MADURA_MIDX_100HGPT_0A = 0x5E , 551 MADURA_MIDX_100HGPT_1 = 0x1F , 552 MADURA_MIDX_100HGPT_1A = 0x5F , 553 MADURA_MIDX_40GMX_0 = 0x20 , 554 MADURA_MIDX_40GMX_1 = 0x21 , 555 MADURA_MIDX_40HGMX_0 = 0x24 , 556 MADURA_MIDX_40HGMX_1 = 0x25 , 557 MADURA_MIDX_40GDM_0 = 0x30 , 558 MADURA_MIDX_40GDM_1 = 0x31 , 559 MADURA_MIDX_40HGDM_0 = 0x34 , 560 MADURA_MIDX_40HGDM_1 = 0x35 , 561 MADURA_MIDX_40GDM_0B = 0x38 , 562 MADURA_MIDX_40GDM_1B = 0x39 , 563 MADURA_MIDX_40HGDM_0B = 0x3C , 564 MADURA_MIDX_40HGDM_1B = 0x3D , 565 MADURA_MIDX_MODE_INVALID = -1 566 } MADURA_MIDX_MODE_E; 567 568 #define MADURA_MIDX_IS_4X25G_PLUS(_midx)\ 569 ( \ 570 MADURA_MIDX_100GPT_0 == (_midx) || \ 571 MADURA_MIDX_100GPT_0A == (_midx) || \ 572 MADURA_MIDX_100GPT_1 == (_midx) || \ 573 MADURA_MIDX_100GPT_1A == (_midx) || \ 574 MADURA_MIDX_100HGPT_0 == (_midx) || \ 575 MADURA_MIDX_100HGPT_0A == (_midx) || \ 576 MADURA_MIDX_100HGPT_1 == (_midx) || \ 577 MADURA_MIDX_100HGPT_1A == (_midx) ) 578 579 int madura_get_chipid (const phymod_access_t *pa, uint32_t *chipid, uint32_t *rev); 580 581 int _madura_wait_mst_msgout(const phymod_access_t *pa, 582 MADURA_MSGOUT_E exp_message, 583 int poll_time); 584 585 int _madura_core_init(const phymod_core_access_t* core, 586 const phymod_core_init_config_t* init_config); 587 588 int _madura_set_slice_reg ( 589 const phymod_access_t* pm_acc, 590 uint16_t ip, 591 uint16_t dev_type, 592 uint16_t lane, 593 uint16_t pll_sel); 594 595 void _madura_lane_cast_get(const phymod_access_t *pa, MADURA_CORE_TYPE ip, 596 uint16_t *cast_type, uint16_t *mcast_val); 597 598 int _madura_phy_interface_config_get(const phymod_access_t *pa, 599 uint32_t flags, phymod_phy_inf_config_t *config); 600 601 int _madura_rx_pmd_lock_get(const phymod_access_t* pa, uint32_t* rx_pmd_locked); 602 603 int _madura_config_dut_mode_reg(const phymod_phy_access_t *pa, 604 const phymod_phy_inf_config_t* config); 605 606 int _madura_udms_config(const phymod_phy_access_t *pa, 607 const phymod_phy_inf_config_t* config, 608 MADURA_AN_MODE mode); 609 610 int _madura_phy_interface_config_set(const phymod_phy_access_t* pa, 611 uint32_t flags, const phymod_phy_inf_config_t* config); 612 613 int madura_is_lane_mask_set(const phymod_phy_access_t *pa, uint16_t prt, 614 const phymod_phy_inf_config_t *config); 615 616 int _madura_config_dut_mode_reg(const phymod_phy_access_t *pa, 617 const phymod_phy_inf_config_t* config); 618 619 int _madura_udms_config(const phymod_phy_access_t *pa, const phymod_phy_inf_config_t* config, 620 MADURA_AN_MODE mode); 621 622 int _madura_interface_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config); 623 624 int _madura_autoneg_get_val(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t *AN_get_val); 625 626 int _madura_autoneg_set_val(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t AN_set_val); 627 628 int _madura_force_training_get(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t *training_get); 629 630 int _madura_force_training_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t training_set); 631 632 int _madura_phy_interface_config_set(const phymod_phy_access_t* pa, uint32_t flags, 633 const phymod_phy_inf_config_t* config); 634 635 int _madura_phy_interface_config_get(const phymod_access_t *pa, uint32_t flags, 636 phymod_phy_inf_config_t *config); 637 638 int _madura_phy_pcs_link_get(const phymod_access_t *pa, 639 uint32_t *pcs_link); 640 641 int _madura_configure_ref_clock(const phymod_access_t *pa, 642 phymod_ref_clk_t ref_clk); 643 644 int _madura_get_pll_modes(phymod_ref_clk_t ref_clk, const phymod_phy_inf_config_t *config, 645 uint16_t *fal_pll_mode, uint16_t *fal_2x_pll_mode); 646 647 int _madura_config_pll_div(const phymod_access_t *pa, const phymod_phy_inf_config_t config); 648 649 int _madura_core_dp_rstb(const phymod_access_t *pa, const phymod_phy_inf_config_t cfg); 650 651 int _madura_core_reset_set(const phymod_access_t *pa, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction); 652 653 int _madura_get_pcs_link_status(const phymod_access_t *pa, uint32_t *link_sts); 654 655 int _madura_pcs_link_monitor_enable_set(const phymod_access_t *pa, uint16_t en_dis); 656 657 int _madura_pcs_link_monitor_enable_get(const phymod_access_t *pa, uint32_t *get_pcs); 658 659 int _madura_fw_enable(const phymod_access_t *pa, uint16_t en_dis) ; 660 661 int _madura_loopback_set(const phymod_access_t *pa, phymod_loopback_mode_t loopback, uint32_t enable); 662 663 int _madura_loopback_get(const phymod_access_t *pa, phymod_loopback_mode_t loopback, uint32_t *enable); 664 665 int _madura_tx_rx_polarity_set(const phymod_access_t *pa, uint32_t tx_polarity, uint32_t rx_polarity); 666 667 int _madura_tx_rx_polarity_get(const phymod_access_t *pa, uint32_t *tx_polarity, uint32_t *rx_polarity); 668 669 int _madura_tx_set(const phymod_access_t *pa, const phymod_tx_t* tx); 670 671 int _madura_tx_get(const phymod_access_t *pa, phymod_tx_t* tx); 672 673 int _madura_rx_set(const phymod_access_t* pa, const phymod_rx_t* rx); 674 675 int _madura_rx_adaptation_resume(const phymod_access_t* pa); 676 677 int _madura_rx_get(const phymod_access_t *pa, phymod_rx_t* rx); 678 679 int _madura_tx_power_set(const phymod_access_t *pa, uint32_t power_tx); 680 681 int _madura_rx_power_set(const phymod_access_t *pa, uint32_t power_rx); 682 683 int _madura_tx_rx_power_get(const phymod_access_t *pa, phymod_phy_power_t* power); 684 685 int _madura_force_tx_training_set(const phymod_access_t *pa, uint32_t enable); 686 687 int _madura_force_tx_training_get(const phymod_access_t *pa, uint32_t *enable); 688 689 int _madura_force_tx_training_status_get(const phymod_access_t *pa, phymod_cl72_status_t* status); 690 691 int _madura_phy_reset_set(const phymod_access_t *pa, const phymod_phy_reset_t* reset); 692 693 int _madura_phy_reset_get(const phymod_access_t *pa, phymod_phy_reset_t* reset); 694 695 int _madura_phy_status_dump(const phymod_access_t *pa); 696 697 int _madura_tx_lane_control_set(const phymod_access_t *pa, phymod_phy_tx_lane_control_t tx_control); 698 699 int _madura_rx_lane_control_set(const phymod_access_t *pa, phymod_phy_rx_lane_control_t rx_control); 700 701 int _madura_tx_lane_control_get(const phymod_access_t *pa, phymod_phy_tx_lane_control_t *tx_control); 702 703 int _madura_rx_lane_control_get(const phymod_access_t *pa, phymod_phy_rx_lane_control_t *rx_control); 704 705 int _madura_ext_intr_status_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t* intr_status); 706 707 int _madura_ext_intr_enable_set(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t enable); 708 709 int _madura_ext_intr_enable_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t* enable); 710 711 int _madura_ext_intr_status_clear(const phymod_phy_access_t *phy, uint32_t intr_type); 712 713 int _madura_pll_sequencer_restart(const phymod_core_access_t *core, phymod_sequencer_operation_t operation); 714 715 int _madura_fec_enable_set(const phymod_access_t *pa, uint32_t enable); 716 717 int _madura_fec_enable_get(const phymod_access_t *pa, uint32_t* enable); 718 719 int _madura_config_hcd_link_sts (const phymod_access_t* pa, phymod_phy_inf_config_t config, uint16_t ip, uint16_t port); 720 721 int _madura_autoneg_ability_set(const phymod_access_t* pa, madura_an_ability_t *an_ability); 722 723 int _madura_autoneg_set(const phymod_phy_access_t* pa, const phymod_autoneg_control_t* an); 724 725 int _madura_autoneg_get(const phymod_access_t* pa, phymod_autoneg_control_t* an, uint32_t *an_done); 726 727 int _madura_autoneg_ability_get (const phymod_access_t* pa, madura_an_ability_t *an_ablity); 728 729 int _madura_autoneg_remote_ability_get(const phymod_access_t *pa, phymod_autoneg_ability_t* an_ability_get); 730 731 int _madura_get_pcs_link_status(const phymod_access_t *pa, uint32_t *link_sts); 732 733 int _madura_pcs_link_monitor_enable_get(const phymod_access_t *pa, uint32_t *get_pcs); 734 735 int _madura_pcs_link_monitor_enable_set(const phymod_access_t *pa, uint16_t en_dis); 736 737 int _madura_port_from_lane_map_get(const phymod_access_t *pa, const phymod_phy_inf_config_t* cfg, uint16_t *port, uint16_t *physical_port); 738 739 int _madura_core_cfg_polarity_set(const phymod_access_t *pa, uint32_t tx_polarity, uint32_t rx_polarity); 740 741 int _madura_gpio_config_set(const phymod_access_t *pa, int pin_no, phymod_gpio_mode_t gpio_mode); 742 743 int _madura_gpio_config_get(const phymod_access_t *pa, int pin_no, phymod_gpio_mode_t* gpio_mode); 744 745 int _madura_gpio_pin_value_set(const phymod_access_t *pa, int pin_no, int value); 746 747 int _madura_gpio_pin_value_get(const phymod_access_t *pa, int pin_no, int* value); 748 749 int _madura_module_write(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, uint32_t no_of_bytes, const uint8_t *write_data); 750 751 int _madura_module_read(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, uint32_t no_of_bytes, uint8_t *read_data); 752 753 int _madura_set_module_command(const phymod_access_t *pa, uint16_t xfer_addr, uint32_t slv_addr, unsigned char xfer_cnt, MADURA_I2CM_CMD_E cmd); 754 755 int _madura_cfg_fw_ull_dp(const phymod_access_t* pa, phymod_datapath_t op_datapath); 756 757 int _madura_core_rptr_rtmr_mode_set(const phymod_access_t* pa, uint16_t op_mode); 758 759 int _madura_firmware_lane_config_set(const phymod_access_t* phy, phymod_firmware_lane_config_t fw_config); 760 761 int _madura_firmware_lane_config_get(const phymod_access_t* phy, phymod_firmware_lane_config_t* fw_config); 762 763 int _madura_get_ieee_intf(const phymod_access_t *pa, const phymod_phy_inf_config_t *config, uint16_t *intf); 764 765 int _madura_set_ieee_intf(const phymod_access_t *pa, const phymod_phy_inf_config_t *config, uint16_t intf); 766 767 #endif /* MADURA_CFG_SEQ_H */