madura_cfg_seq.c (334663B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 8 /* 9 * 10 * 11 * This program is the proprietary software of Broadcom Corporation 12 * and/or its licensors, and may only be used, duplicated, modified 13 * or distributed pursuant to the terms and conditions of a separate, 14 * written license agreement executed between you and Broadcom 15 * (an "Authorized License"). Except as set forth in an Authorized 16 * License, Broadcom grants no license (express or implied), right 17 * to use, or waiver of any kind with respect to the Software, and 18 * Broadcom expressly reserves all rights in and to the Software 19 * and all intellectual property rights therein. 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THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING 50 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$ 51 */ 52 53 #include <phymod/phymod.h> 54 #include <phymod/phymod_system.h> 55 #include <phymod/phymod_diagnostics.h> 56 #include <phymod/phymod_reg.h> 57 #include "bcmi_madura_defs.h" 58 #include "madura_cfg_seq.h" 59 #include "madura_sdk_interface.h" 60 #include "madura_serdes/common2/srds_api_enum.h" 61 #include "madura_serdes/falcon2_madura_src/falcon2_madura_functions.h" 62 63 extern unsigned char madura_falcon_ucode[]; 64 extern unsigned char madura_falcon_slave_ucode[]; 65 extern unsigned char madura_falcon_flashing_ucode[]; 66 extern unsigned int madura_falcon_ucode_len; 67 extern unsigned int madura_falcon_ucode_slave_len; 68 extern unsigned int madura_falcon_flashing_ucode_len; 69 70 int read_1G_mode_status(const phymod_access_t *pa, unsigned char mindex, uint16_t *pll_index ); 71 72 int read_madura_pll_mode(const phymod_access_t *pa, uint16_t ip, uint16_t lane_no, unsigned char mindex) 73 { 74 BCMI_MADURA_SLICEr_t slice_reg; 75 BCMI_MADURA_PLL_CAL_CTL7r_t pll_read_val; 76 uint16_t pll_index = 0, rv = 0; 77 78 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 79 PHYMOD_MEMSET(&pll_read_val, 0 , sizeof(BCMI_MADURA_PLL_CAL_CTL7r_t)); 80 81 rv = read_1G_mode_status(pa, mindex, &pll_index ); /*not using the return value. Only using the pll_index */ 82 if(rv){ 83 PHYMOD_DEBUG_VERBOSE((" Speed configured as 1G with mode register value as 0x%x",mindex)); 84 }else{ 85 PHYMOD_DEBUG_VERBOSE((" Speed not configured as 1G with mode register value as 0x%x",mindex)); 86 } 87 PHYMOD_IF_ERR_RETURN ( 88 _madura_set_slice_reg (pa, 89 ip, MADURA_DEV_PMA_PMD,lane_no, pll_index)); 90 PHYMOD_IF_ERR_RETURN ( 91 BCMI_MADURA_READ_PLL_CAL_CTL7r(pa,&pll_read_val)); 92 return (BCMI_MADURA_PLL_CAL_CTL7r_GET(pll_read_val) & 0x7 ); 93 } 94 95 /** This function is to read if 1G is configured and also to check which PLL that mode is using 96 * 97 * @param pa Pointer to phymod access structure 98 * @param mindex mode register value for 1G/10G/25G 99 * @param pll_index Pll used by the mode i.e 0 or 1 100 * 101 * @return 0 or 1 0 if mode is not in 1G and 1 if mode is in 1G 102 */ 103 104 int read_1G_mode_status(const phymod_access_t *pa, unsigned char mindex, uint16_t *pll_index ) 105 { 106 BCMI_MADURA_MST_CFG0r_t mst_cfg0; 107 uint16_t mst_cfg_val = 0 ; 108 int rv = 0; 109 *pll_index = 0; 110 111 PHYMOD_MEMSET(&mst_cfg0, 0 , sizeof(BCMI_MADURA_MST_CFG0r_t)); 112 113 PHYMOD_IF_ERR_RETURN ( 114 BCMI_MADURA_READ_MST_CFG0r(pa,&mst_cfg0)); 115 mst_cfg_val = BCMI_MADURA_MST_CFG0r_GET(mst_cfg0); 116 117 switch( mindex) 118 { 119 case MADURA_MIDX_10GPT_0: 120 case MADURA_MIDX_10GPT_0A: 121 *pll_index = (( mst_cfg_val & 0x1)==0x1 )? 1 : 0 ; 122 rv = (( mst_cfg_val & 0x100)==0x100 )? 1 : 0 ; 123 break; 124 case MADURA_MIDX_10GPT_1: 125 case MADURA_MIDX_10GPT_1A: 126 *pll_index = (( mst_cfg_val & 0x2)==0x2 )? 1 : 0 ; 127 rv = (( mst_cfg_val & 0x200)==0x200 )? 1 : 0 ; 128 break; 129 case MADURA_MIDX_10GPT_2: 130 case MADURA_MIDX_10GPT_2A: 131 *pll_index = (( mst_cfg_val & 0x4)==0x4 )? 1 : 0 ; 132 rv = (( mst_cfg_val & 0x400)==0x400 )? 1 : 0 ; 133 break; 134 case MADURA_MIDX_10GPT_3: 135 case MADURA_MIDX_10GPT_3A: 136 *pll_index = (( mst_cfg_val & 0x8)==0x8 )? 1 : 0 ; 137 rv = (( mst_cfg_val & 0x800)==0x800 )? 1 : 0 ; 138 break; 139 default: 140 break; 141 } 142 143 return rv; 144 } 145 146 147 int madura_get_chipid (const phymod_access_t *pa, uint32_t *chipid, uint32_t *rev) 148 { 149 BCMI_MADURA_CHIP_IDr_t cid; 150 BCMI_MADURA_CHIP_REVISIONr_t rid; 151 152 PHYMOD_IF_ERR_RETURN( 153 BCMI_MADURA_READ_CHIP_IDr(pa, &cid)); 154 PHYMOD_IF_ERR_RETURN( 155 BCMI_MADURA_READ_CHIP_REVISIONr(pa, &rid)); 156 157 *chipid = (BCMI_MADURA_CHIP_REVISIONr_CHIP_ID_19_16f_GET(rid) << 16 ) | 158 BCMI_MADURA_CHIP_IDr_GET(cid); 159 *rev = BCMI_MADURA_CHIP_REVISIONr_CHIP_REVf_GET(rid); 160 161 PHYMOD_DEBUG_VERBOSE(("CHIP ID: %x REv:%x\n", *chipid, *rev)); 162 return PHYMOD_E_NONE; 163 } 164 165 /** Wait master message out 166 * This function is to ensure whether master has sent the previous message 167 * out successfully 168 * 169 * @param pa Pointer to phymod access structure 170 * @param exp_message Expected message specified by user 171 * @param poll_time Poll interval 172 * 173 * @return PHYMOD_E_NONE successful function execution 174 */ 175 int _madura_wait_mst_msgout(const phymod_access_t *pa, 176 MADURA_MSGOUT_E exp_message, 177 int poll_time) 178 { 179 int retry_count = MADURA_FW_DLOAD_RETRY_CNT; 180 MADURA_MSGOUT_E msgout = MSGOUT_DONTCARE;/*0*/ 181 BCMI_MADURA_MST_MSGOUTr_t msgout_t; 182 do { 183 /* Read general control msg out Register */ 184 PHYMOD_IF_ERR_RETURN( 185 BCMI_MADURA_READ_MST_MSGOUTr(pa,&msgout_t)); 186 msgout = BCMI_MADURA_MST_MSGOUTr_MST_MSGOUT_VALf_GET(msgout_t); 187 /* wait before reading again */ 188 if (poll_time != 0) { 189 /* sleep for specified seconds*/ 190 PHYMOD_SLEEP(poll_time); 191 } 192 retry_count --; 193 } while ((msgout != exp_message) && retry_count); 194 195 if (!retry_count) { 196 if (exp_message == MSGOUT_PRGRM_DONE) { 197 PHYMOD_DEBUG_VERBOSE(("MSG OUT:%x \n",msgout)); 198 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, (_PHYMOD_MSG("Fusing Firmware failed"))); 199 } else { 200 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INIT, (_PHYMOD_MSG("Firmware download failed"))); 201 } 202 } 203 return PHYMOD_E_NONE; 204 } 205 206 int _madura_fw_enable(const phymod_access_t *pa, uint16_t en_dis) 207 { 208 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 209 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 210 211 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en,en_dis); 212 PHYMOD_IF_ERR_RETURN( 213 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en)); 214 215 return PHYMOD_E_NONE; 216 } 217 int madura_micro_download(const phymod_access_t *pa, unsigned char *ucode, 218 uint32_t len, uint16_t master, uint16_t *chk_sum) 219 { 220 221 BCMI_MADURA_UC_BOOT_PORr_t boot_por; 222 BCMI_MADURA_MST_MSGINr_t msg_in; 223 BCMI_MADURA_MST_RUNNING_BYTE_CNTr_t mst_byte_cnt; 224 BCMI_MADURA_MST_RUNNING_CHKSUMr_t run_chksum; 225 BCMI_MADURA_SLV1_RUNNING_CHKSUMr_t slv1_chksum; 226 BCMI_MADURA_SLV2_RUNNING_CHKSUMr_t slv2_chksum; 227 BCMI_MADURA_SLV3_RUNNING_CHKSUMr_t slv3_chksum; 228 BCMI_MADURA_SLV4_RUNNING_CHKSUMr_t slv4_chksum; 229 230 uint16_t num_bytes = 0, j = 0; 231 uint16_t num_words = 0; 232 uint16_t check_sum = 0, cnt = MADURA_FW_DLOAD_RETRY_CNT, data = 0; 233 234 PHYMOD_MEMSET(&boot_por, 0 , sizeof(BCMI_MADURA_UC_BOOT_PORr_t)); 235 PHYMOD_MEMSET(&msg_in, 0 , sizeof(BCMI_MADURA_MST_MSGINr_t)); 236 PHYMOD_MEMSET(&mst_byte_cnt, 0 , sizeof(BCMI_MADURA_MST_RUNNING_BYTE_CNTr_t)); 237 PHYMOD_MEMSET(&run_chksum, 0 , sizeof(BCMI_MADURA_MST_RUNNING_CHKSUMr_t)); 238 PHYMOD_MEMSET(&slv1_chksum, 0 , sizeof(BCMI_MADURA_SLV1_RUNNING_CHKSUMr_t)); 239 PHYMOD_MEMSET(&slv2_chksum, 0 , sizeof(BCMI_MADURA_SLV2_RUNNING_CHKSUMr_t)); 240 PHYMOD_MEMSET(&slv3_chksum, 0 , sizeof(BCMI_MADURA_SLV3_RUNNING_CHKSUMr_t)); 241 PHYMOD_MEMSET(&slv4_chksum, 0 , sizeof(BCMI_MADURA_SLV4_RUNNING_CHKSUMr_t)); 242 243 /* Send boot address if master enabled */ 244 if(master){ 245 PHYMOD_IF_ERR_RETURN( 246 _madura_wait_mst_msgout(pa, MSGOUT_NEXT, 0)); 247 248 /* coverity[operator_confusion] */ 249 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,0); 250 PHYMOD_IF_ERR_RETURN( 251 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 252 } 253 PHYMOD_IF_ERR_RETURN( 254 _madura_wait_mst_msgout(pa, MSGOUT_NEXT, 0)); 255 256 /* Calculate the number of words */ 257 num_words = (len) / 2; 258 259 /* Update message in value field with word length */ 260 /* coverity[operator_confusion] */ 261 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,num_words); 262 PHYMOD_IF_ERR_RETURN( 263 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 264 num_bytes = len; 265 for (j = 0; j < num_bytes; j += 2) { 266 /*sending next ucode data*/ 267 data = (ucode[j + 1] << 8) | ucode[j]; 268 check_sum ^= ucode[j] ^ ucode[j + 1]; 269 270 /* Send next word */ 271 /* coverity[operator_confusion] */ 272 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,data); 273 PHYMOD_IF_ERR_RETURN( 274 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 275 } 276 do { 277 /* check download_done flags*/ 278 PHYMOD_IF_ERR_RETURN( 279 BCMI_MADURA_READ_UC_BOOT_PORr(pa,&boot_por)); 280 if (master) { 281 if(BCMI_MADURA_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por)==1){ 282 PHYMOD_DEBUG_VERBOSE(("Master Dload Done\n")); 283 break; 284 } 285 } else { 286 if(BCMI_MADURA_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por)==1){ 287 PHYMOD_DEBUG_VERBOSE(("Slave Dload Done\n")); 288 break; 289 } 290 } 291 } while (cnt --); 292 293 if (!cnt) { 294 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INIT, (_PHYMOD_MSG("Firmware download failed"))); 295 } 296 297 /* check checksum */ 298 check_sum = (check_sum == 0) ? 0x600D : check_sum; 299 if (master) { 300 PHYMOD_IF_ERR_RETURN( 301 BCMI_MADURA_READ_MST_RUNNING_BYTE_CNTr(pa,&mst_byte_cnt)); 302 data=BCMI_MADURA_MST_RUNNING_BYTE_CNTr_MST_RUNNING_BYTE_CNT_VALf_GET(mst_byte_cnt); 303 if (data != num_bytes) { 304 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL,(_PHYMOD_MSG("Master Dload fail:"))); 305 } 306 307 PHYMOD_DEBUG_VERBOSE(("Master Byte Cnt:%d\n", data)); 308 309 PHYMOD_IF_ERR_RETURN( 310 BCMI_MADURA_READ_MST_RUNNING_CHKSUMr(pa,&run_chksum )); 311 312 data=BCMI_MADURA_MST_RUNNING_CHKSUMr_MST_RUNNING_CHKSUM_VALf_GET(run_chksum); 313 if (check_sum != data) { 314 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 315 (_PHYMOD_MSG("Master Dload chksum Fail"))); 316 } 317 PHYMOD_DEBUG_VERBOSE(("Master Chk sum:0x%x\n", data)); 318 *chk_sum = data; 319 } else { 320 /*slave checksum*/ 321 PHYMOD_IF_ERR_RETURN( 322 BCMI_MADURA_READ_SLV1_RUNNING_CHKSUMr(pa,&slv1_chksum)); 323 data=BCMI_MADURA_SLV1_RUNNING_CHKSUMr_SLV1_RUNNING_CHKSUM_VALf_GET(slv1_chksum); 324 if (check_sum != data) { 325 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 326 (_PHYMOD_MSG("Slave1 Dload chksum Fail"))); 327 } 328 PHYMOD_IF_ERR_RETURN( 329 BCMI_MADURA_READ_SLV2_RUNNING_CHKSUMr(pa,&slv2_chksum)); 330 data=BCMI_MADURA_SLV2_RUNNING_CHKSUMr_SLV2_RUNNING_CHKSUM_VALf_GET(slv2_chksum); 331 if (check_sum != data) { 332 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 333 (_PHYMOD_MSG("Slave2 Dload chksum Fail"))); 334 } 335 PHYMOD_IF_ERR_RETURN( 336 BCMI_MADURA_READ_SLV4_RUNNING_CHKSUMr(pa,&slv4_chksum)); 337 data=BCMI_MADURA_SLV4_RUNNING_CHKSUMr_SLV4_RUNNING_CHKSUM_VALf_GET(slv4_chksum); 338 if (check_sum != data) { 339 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 340 (_PHYMOD_MSG("Slave4 Dload chksum Fail"))); 341 } 342 343 } 344 PHYMOD_DEBUG_VERBOSE(("Slave cksum Cnt:0x%x\n", data)); 345 *chk_sum = data; 346 return PHYMOD_E_NONE; 347 } 348 349 350 int madura_eeprom_download(const phymod_access_t *pa, 351 const unsigned char *ucode, 352 uint32_t len, uint16_t master, uint16_t *chk_sum,uint16_t prg_eeprom) 353 { 354 355 BCMI_MADURA_UC_BOOT_PORr_t boot_por; 356 BCMI_MADURA_MST_MSGINr_t msg_in; 357 BCMI_MADURA_MST_RUNNING_BYTE_CNTr_t mst_byte_cnt; 358 BCMI_MADURA_MST_RUNNING_CHKSUMr_t run_chksum; 359 BCMI_MADURA_SLV1_RUNNING_CHKSUMr_t slv1_chksum; 360 BCMI_MADURA_SLV2_RUNNING_CHKSUMr_t slv2_chksum; 361 BCMI_MADURA_SLV3_RUNNING_CHKSUMr_t slv3_chksum; 362 BCMI_MADURA_SLV4_RUNNING_CHKSUMr_t slv4_chksum; 363 364 uint16_t num_bytes = 0, j = 0; 365 uint16_t num_words = 0; 366 uint16_t check_sum = 0 /*, cnt = MADURA_FW_DLOAD_RETRY_CNT*/, data = 0; 367 368 PHYMOD_MEMSET(&boot_por, 0 , sizeof(BCMI_MADURA_UC_BOOT_PORr_t)); 369 PHYMOD_MEMSET(&msg_in, 0 , sizeof(BCMI_MADURA_MST_MSGINr_t)); 370 PHYMOD_MEMSET(&mst_byte_cnt, 0 , sizeof(BCMI_MADURA_MST_RUNNING_BYTE_CNTr_t)); 371 PHYMOD_MEMSET(&run_chksum, 0 , sizeof(BCMI_MADURA_MST_RUNNING_CHKSUMr_t)); 372 PHYMOD_MEMSET(&slv1_chksum, 0 , sizeof(BCMI_MADURA_SLV1_RUNNING_CHKSUMr_t)); 373 PHYMOD_MEMSET(&slv2_chksum, 0 , sizeof(BCMI_MADURA_SLV2_RUNNING_CHKSUMr_t)); 374 PHYMOD_MEMSET(&slv3_chksum, 0 , sizeof(BCMI_MADURA_SLV3_RUNNING_CHKSUMr_t)); 375 PHYMOD_MEMSET(&slv4_chksum, 0 , sizeof(BCMI_MADURA_SLV4_RUNNING_CHKSUMr_t)); 376 377 /* Calculate the number of words */ 378 num_words = (len) / 2; 379 num_bytes = len; 380 if(!prg_eeprom){/*step 1 shawial check !: downloading flashing code to coderam*/ 381 PHYMOD_IF_ERR_RETURN( 382 _madura_wait_mst_msgout(pa, MSGOUT_NEXT, 0)); 383 /* Send data count */ 384 /* coverity[operator_confusion] */ 385 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,num_words); 386 PHYMOD_IF_ERR_RETURN( 387 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 388 /*send data*/ 389 for (j = 0; j < num_bytes; j += 2) { 390 /*sending next ucode data*/ 391 data = (ucode[j + 1] << 8) | ucode[j]; 392 check_sum ^= ucode[j] ^ ucode[j + 1]; 393 394 /* Send next word */ 395 /* coverity[operator_confusion] */ 396 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,data); 397 PHYMOD_IF_ERR_RETURN( 398 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 399 PHYMOD_USLEEP(500); 400 } 401 402 /* check checksum ; hardcoded*/ 403 check_sum = 0x600D ; 404 PHYMOD_IF_ERR_RETURN( 405 BCMI_MADURA_READ_MST_RUNNING_CHKSUMr(pa,&run_chksum )); 406 data=BCMI_MADURA_MST_RUNNING_CHKSUMr_MST_RUNNING_CHKSUM_VALf_GET(run_chksum); 407 if (check_sum != data) { 408 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 409 (_PHYMOD_MSG("Master Dload chksum Fail"))); 410 } 411 412 }else{/*step 2 and 3*/ 413 414 PHYMOD_IF_ERR_RETURN( 415 _madura_wait_mst_msgout(pa, MSGOUT_FLASH, 0)); 416 /* coverity[operator_confusion] */ 417 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,0); 418 PHYMOD_IF_ERR_RETURN( 419 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 420 PHYMOD_USLEEP(20*1000); 421 PHYMOD_IF_ERR_RETURN( 422 _madura_wait_mst_msgout(pa, MSGOUT_GET_CNT, 0)); 423 424 /* Update message in value field with word length */ 425 /* coverity[operator_confusion] */ 426 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,num_words); 427 PHYMOD_IF_ERR_RETURN( 428 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 429 430 PHYMOD_IF_ERR_RETURN( 431 _madura_wait_mst_msgout(pa, MSGOUT_GET_CNT, 0)); 432 if(master){ 433 /* coverity[operator_confusion] */ 434 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,0); 435 PHYMOD_IF_ERR_RETURN( 436 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 437 }else 438 { 439 /* coverity[operator_confusion] */ 440 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,0x4000); 441 PHYMOD_IF_ERR_RETURN( 442 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 443 } 444 445 for (j = 0; j < num_bytes; j += 2) { 446 /*sending next ucode data*/ 447 data = (ucode[j + 1] << 8) | ucode[j]; 448 check_sum ^= ucode[j] ^ ucode[j + 1]; 449 450 if (j % 64 == 0) 451 { 452 PHYMOD_USLEEP(25 * 500); 453 } 454 PHYMOD_IF_ERR_RETURN( 455 _madura_wait_mst_msgout(pa, MSGOUT_NEXT, 0)); 456 457 /* Send next word */ 458 /* coverity[operator_confusion] */ 459 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in,data); 460 PHYMOD_IF_ERR_RETURN( 461 BCMI_MADURA_WRITE_MST_MSGINr(pa,msg_in)); 462 } 463 464 465 /* check checksum */ 466 check_sum = (check_sum == 0) ? 0x600D : check_sum; 467 } 468 return PHYMOD_E_NONE; 469 } 470 471 int madura_download_helper ( 472 const phymod_access_t *pm_acc , 473 const unsigned char *image, 474 int image_len, 475 int master_en, 476 int slave_en, 477 int code_broadcast_en, 478 uint16_t mst_boot_addr, 479 int prg_eeprom, 480 int eeprom_download 481 ) 482 { 483 BCMI_MADURA_BOOTr_t boot; 484 uint16_t data1 = 0, retry_cnt = MADURA_FW_DLOAD_RETRY_CNT; 485 uint16_t mst_checksum_out; 486 uint16_t slv_checksum_out; 487 uint16_t done = 0; 488 BCMI_MADURA_GEN_CTL2r_t gen_ctrl2; 489 BCMI_MADURA_SPI_CODE_LOAD_ENr_t spi_code_load; 490 BCMI_MADURA_MST_MSGINr_t msg_in; 491 BCMI_MADURA_UC_BOOT_PORr_t boot_por; 492 BCMI_MADURA_FIRMWARE_VERSIONr_t fw_ver; 493 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 494 BCMI_MADURA_FIRMWARE_FEATURESr_t firm_features; 495 496 PHYMOD_MEMSET(&firm_features, 0, sizeof(BCMI_MADURA_FIRMWARE_FEATURESr_t)); 497 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 498 PHYMOD_MEMSET(&fw_ver, 0 , sizeof(BCMI_MADURA_FIRMWARE_VERSIONr_t)); 499 PHYMOD_MEMSET(&boot, 0 , sizeof(BCMI_MADURA_BOOTr_t)); 500 PHYMOD_MEMSET(&gen_ctrl2, 0 , sizeof(BCMI_MADURA_GEN_CTL2r_t)); 501 PHYMOD_MEMSET(&spi_code_load, 0 , sizeof(BCMI_MADURA_SPI_CODE_LOAD_ENr_t)); 502 PHYMOD_MEMSET(&msg_in, 0 , sizeof(BCMI_MADURA_MST_MSGINr_t)); 503 PHYMOD_MEMSET(&boot_por, 0 , sizeof(BCMI_MADURA_UC_BOOT_PORr_t)); 504 505 /*validation : cfg die loop for each die L1050*/ 506 if (!prg_eeprom || slave_en) {/*check ! bitor for valid prg_eeprom = 1 for step 2 3 & 4; slave_en=1 for step3*/ 507 /*true for step 1 and 3*/ 508 /* Put Master under Reset */ 509 PHYMOD_IF_ERR_RETURN( 510 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 511 BCMI_MADURA_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2,0);/*resetting M0 micro*/ 512 PHYMOD_IF_ERR_RETURN( 513 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 514 } 515 516 if (!prg_eeprom) { 517 /* Put Master under Reset for step 1*/ 518 PHYMOD_IF_ERR_RETURN( 519 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 520 BCMI_MADURA_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2,0);/*resetting M0 micro perip*/ 521 PHYMOD_IF_ERR_RETURN( 522 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 523 } 524 525 /* Wait for any pending SPI download 526 * SPI download is not interrupted by Master Reset 527 * (this is a safety feature) so we need to wait its 528 * completion before starting the MDIO Download */ 529 do { 530 PHYMOD_IF_ERR_RETURN( 531 BCMI_MADURA_READ_BOOTr(pm_acc,&boot)); 532 data1=BCMI_MADURA_BOOTr_SERBOOT_BUSYf_GET(boot); 533 } while((data1 != 0) && (retry_cnt--)); 534 if (retry_cnt == 0) { 535 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 536 (_PHYMOD_MSG("ERR:SERBOOT BUSY BIT SET"))); 537 return PHYMOD_E_FAIL; 538 } 539 540 /* Madura always supports serial mode if Dload 541 * Master followed by slave 542 * Configure master_code_download_en, slave_code_download_en 543 * and broadcast enable */ 544 if (eeprom_download) { 545 BCMI_MADURA_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_SET(spi_code_load,0xB);/*Only 3 cores are supported for now*/ 546 BCMI_MADURA_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_SET(spi_code_load,1); 547 } else 548 if(slave_en){ 549 BCMI_MADURA_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_SET(spi_code_load,0xB);/*Only 3 cores are supported for now*/ 550 } else if(master_en){ 551 BCMI_MADURA_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_SET(spi_code_load,1); 552 BCMI_MADURA_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_SET(spi_code_load,0);/*0 cores are supported */ 553 } 554 BCMI_MADURA_SPI_CODE_LOAD_ENr_CODE_BROADCAST_ENf_SET(spi_code_load,1); 555 PHYMOD_IF_ERR_RETURN( 556 BCMI_MADURA_WRITE_SPI_CODE_LOAD_ENr(pm_acc,spi_code_load)); 557 558 /*Read values what is set above*/ 559 PHYMOD_IF_ERR_RETURN( 560 BCMI_MADURA_READ_SPI_CODE_LOAD_ENr(pm_acc,&spi_code_load)); 561 if (BCMI_MADURA_SPI_CODE_LOAD_ENr_CODE_BROADCAST_ENf_GET(spi_code_load) != 1 562 && BCMI_MADURA_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_GET(spi_code_load)!= 1 563 && BCMI_MADURA_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_GET(spi_code_load) != 0xB) { 564 /* return PHYMOD_E_INTERNAL; */ 565 } 566 567 568 /* Check the not downloading branch of the flow digram 569 * before writing to serboot. 570 * wait_mst_msgout(chip_cfg, die, MSGOUT_NOT_DWNLD, 1, 0);*/ 571 572 /* Read / Write boot_por 573 * write to mst_dwld_done and slv_dwld_done. 574 * write to spi_port_used 575 * write to serboot */ 576 PHYMOD_IF_ERR_RETURN( 577 BCMI_MADURA_READ_UC_BOOT_PORr(pm_acc,&boot_por)); 578 /* Force Master New Download */ 579 if (master_en) 580 BCMI_MADURA_UC_BOOT_PORr_MST_DWLD_DONEf_SET(boot_por,0); 581 /* Force Slave New Download */ 582 if (slave_en) 583 BCMI_MADURA_UC_BOOT_PORr_SLV_DWLD_DONEf_SET(boot_por,0); 584 BCMI_MADURA_UC_BOOT_PORr_SERBOOTf_SET(boot_por,1); 585 BCMI_MADURA_UC_BOOT_PORr_SPI_PORT_USEDf_SET(boot_por,eeprom_download);/*set to 0 for mdio default download on reset*/ 586 PHYMOD_IF_ERR_RETURN( 587 BCMI_MADURA_WRITE_UC_BOOT_PORr(pm_acc,boot_por)); 588 589 590 /* Releasing Master under Reset */ 591 if (!prg_eeprom) { 592 PHYMOD_IF_ERR_RETURN( 593 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 594 BCMI_MADURA_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2,1);/*release resetting M0 micro perip*/ 595 PHYMOD_IF_ERR_RETURN( 596 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 597 } 598 if (!prg_eeprom || slave_en) { 599 PHYMOD_IF_ERR_RETURN( 600 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 601 BCMI_MADURA_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2,1);/*release resetting M0 micro*/ 602 PHYMOD_IF_ERR_RETURN( 603 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 604 } 605 606 607 /* BEGIN : download_sequence */ 608 609 if (eeprom_download != 0) {/*Step 4*/ 610 PHYMOD_USLEEP(500*1000);/*cant touch this */ 611 PHYMOD_IF_ERR_RETURN( 612 _madura_wait_mst_msgout(pm_acc, MSGOUT_DWNLD_DONE, 0)); 613 614 } else{ 615 /* Send boot address if master enabled */ 616 if(master_en && !prg_eeprom){ 617 PHYMOD_IF_ERR_RETURN( 618 _madura_wait_mst_msgout(pm_acc, MSGOUT_NEXT, 0)); 619 620 /* coverity[operator_confusion] */ 621 BCMI_MADURA_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in, 0 /*mst_boot_addr*/); 622 PHYMOD_IF_ERR_RETURN( 623 BCMI_MADURA_WRITE_MST_MSGINr(pm_acc,msg_in)); 624 } 625 PHYMOD_IF_ERR_RETURN( 626 PHYMOD_BUS_WRITE(pm_acc,0x18000,0x500)); 627 /* Send Image */ 628 if (!prg_eeprom) { /* sending flashing code : step 1*/ 629 630 PHYMOD_IF_ERR_RETURN( 631 madura_eeprom_download( 632 pm_acc, image, image_len, 1, &mst_checksum_out,prg_eeprom)); 633 634 } else { /*step 2 and step 3*/ 635 if (master_en) { 636 PHYMOD_IF_ERR_RETURN( 637 madura_eeprom_download( 638 pm_acc, image, image_len, 1, &mst_checksum_out,prg_eeprom)); 639 640 } else { 641 PHYMOD_IF_ERR_RETURN( 642 madura_eeprom_download( 643 pm_acc, image, image_len, 0, &slv_checksum_out,prg_eeprom)); 644 645 } 646 } 647 /* Wait for Program DONE*/ 648 if ( prg_eeprom ) { 649 PHYMOD_USLEEP(500*1000); 650 _madura_wait_mst_msgout(pm_acc, MSGOUT_PRGRM_DONE,0); 651 }else{ 652 653 do{ 654 PHYMOD_IF_ERR_RETURN( 655 BCMI_MADURA_READ_UC_BOOT_PORr(pm_acc,&boot_por)); 656 /* Force Master New Download */ 657 if (master_en) 658 done = BCMI_MADURA_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por); 659 /* Force Slave New Download */ 660 if (slave_en) 661 done = BCMI_MADURA_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por); 662 }while(done != 1); 663 } 664 } 665 666 /* END : download_sequence */ 667 668 if (prg_eeprom && (eeprom_download == 0) && master_en) { 669 /* Assert SPI Reset*/ 670 PHYMOD_IF_ERR_RETURN( 671 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 672 673 BCMI_MADURA_GEN_CTL2r_SPI2X_RSTBf_SET(gen_ctrl2,0); 674 BCMI_MADURA_GEN_CTL2r_SPI_RSTBf_SET(gen_ctrl2,0); 675 PHYMOD_IF_ERR_RETURN( 676 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 677 } 678 /*copied from validation*/ 679 PHYMOD_IF_ERR_RETURN( 680 BCMI_MADURA_READ_UC_BOOT_PORr(pm_acc,&boot_por)); 681 BCMI_MADURA_UC_BOOT_PORr_SERBOOTf_SET(boot_por,1); 682 BCMI_MADURA_UC_BOOT_PORr_SPI_PORT_USEDf_SET(boot_por,prg_eeprom);/*set to 0 for mdio default download on reset*/ 683 PHYMOD_IF_ERR_RETURN( 684 BCMI_MADURA_WRITE_UC_BOOT_PORr(pm_acc,boot_por)); 685 686 if (eeprom_download != 0) {/*Step 4*/ 687 688 int data1; 689 690 PHYMOD_IF_ERR_RETURN( 691 BCMI_MADURA_READ_FIRMWARE_VERSIONr(pm_acc,&fw_ver)); 692 693 data1=BCMI_MADURA_FIRMWARE_VERSIONr_FIRMWARE_VERSION_VALf_GET(fw_ver); 694 PHYMOD_DEBUG_VERBOSE(("FW Version:0x%x\n", data1)); 695 } 696 return PHYMOD_E_NONE; 697 } 698 699 700 701 int _madura_firmware_download(const phymod_access_t *pm_acc , 702 unsigned char *madura_master_ucode, unsigned int master_len, 703 unsigned char *madura_slave_ucode, unsigned int slave_len, 704 unsigned char prg_eeprom) 705 { 706 uint16_t data1 = 0, retry_cnt = MADURA_FW_DLOAD_RETRY_CNT; 707 uint16_t eeprom_num_of_pages = 0; 708 uint16_t mst_check_sum = 0, slv_check_sum = 0; 709 BCMI_MADURA_SPI_CODE_LOAD_ENr_t spi_code_load; 710 BCMI_MADURA_GEN_CTL2r_t gen_ctrl2; 711 BCMI_MADURA_GEN_CTL3r_t gen_ctrl3; 712 BCMI_MADURA_UC_BOOT_PORr_t boot_por; 713 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 714 BCMI_MADURA_FIRMWARE_VERSIONr_t fw_ver; 715 716 BCMI_MADURA_BOOTr_t boot; 717 BCMI_MADURA_GPREGBr_t gregB; 718 BCMI_MADURA_GPREGCr_t gregC; 719 BCMI_MADURA_GPREGEr_t gregE; 720 BCMI_MADURA_GPREGFr_t gregF; 721 BCMI_MADURA_FIRMWARE_FEATURESr_t firm_features; 722 723 PHYMOD_MEMSET(&firm_features, 0, sizeof(BCMI_MADURA_FIRMWARE_FEATURESr_t)); 724 PHYMOD_MEMSET(&spi_code_load, 0 , sizeof(BCMI_MADURA_SPI_CODE_LOAD_ENr_t)); 725 PHYMOD_MEMSET(&gen_ctrl2, 0 , sizeof(BCMI_MADURA_GEN_CTL2r_t)); 726 PHYMOD_MEMSET(&gen_ctrl3, 0 , sizeof(BCMI_MADURA_GEN_CTL3r_t)); 727 PHYMOD_MEMSET(&boot_por, 0 , sizeof(BCMI_MADURA_UC_BOOT_PORr_t)); 728 PHYMOD_MEMSET(&boot, 0 , sizeof(BCMI_MADURA_BOOTr_t)); 729 PHYMOD_MEMSET(&gregB, 0 , sizeof(BCMI_MADURA_GPREGBr_t)); 730 PHYMOD_MEMSET(&gregC, 0 , sizeof(BCMI_MADURA_GPREGCr_t)); 731 PHYMOD_MEMSET(&gregE, 0 , sizeof(BCMI_MADURA_GPREGEr_t)); 732 PHYMOD_MEMSET(&gregF, 0 , sizeof(BCMI_MADURA_GPREGFr_t)); 733 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 734 PHYMOD_MEMSET(&fw_ver, 0 , sizeof(BCMI_MADURA_FIRMWARE_VERSIONr_t)); 735 736 /* Skip the firmware download 737 * mst_download, slv_dwld_done bits are set 738 */ 739 PHYMOD_IF_ERR_RETURN( 740 BCMI_MADURA_READ_UC_BOOT_PORr(pm_acc,&boot_por)); 741 if((BCMI_MADURA_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por))&& 742 (BCMI_MADURA_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por))){ 743 return PHYMOD_E_NONE; /*force DOWNLOAD*/ 744 } 745 746 747 /* Put Master under Reset */ 748 PHYMOD_IF_ERR_RETURN( 749 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 750 BCMI_MADURA_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2,0);/*resetting M0 micro*/ 751 BCMI_MADURA_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2,0);/*resetting M0 micro perip*/ 752 PHYMOD_IF_ERR_RETURN( 753 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 754 755 /* Wait for any pending SPI download 756 * SPI download is not interrupted by Master Reset 757 * (this is a safety feature) so we need to wait its 758 * completion before starting the MDIO Download */ 759 do { 760 PHYMOD_IF_ERR_RETURN( 761 BCMI_MADURA_READ_BOOTr(pm_acc,&boot)); 762 data1=BCMI_MADURA_BOOTr_SERBOOT_BUSYf_GET(boot); 763 } while((data1 != 0) && (retry_cnt--)); 764 if (retry_cnt == 0) { 765 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 766 (_PHYMOD_MSG("ERR:SERBOOT BUSY BIT SET"))); 767 return PHYMOD_E_FAIL; 768 } 769 770 /* Madura always supports serial mode if Dload 771 * Master followed by slave 772 * Configure master_code_download_en, slave_code_download_en 773 * and broadcast enable */ 774 BCMI_MADURA_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_SET(spi_code_load,0xB);/*Only 3 cores are supported for now*/ 775 BCMI_MADURA_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_SET(spi_code_load,1); 776 BCMI_MADURA_SPI_CODE_LOAD_ENr_CODE_BROADCAST_ENf_SET(spi_code_load,1); 777 778 PHYMOD_IF_ERR_RETURN( 779 BCMI_MADURA_WRITE_SPI_CODE_LOAD_ENr(pm_acc,spi_code_load)); 780 781 /*Read values what is set above*/ 782 PHYMOD_IF_ERR_RETURN( 783 BCMI_MADURA_READ_SPI_CODE_LOAD_ENr(pm_acc,&spi_code_load)); 784 if (BCMI_MADURA_SPI_CODE_LOAD_ENr_CODE_BROADCAST_ENf_GET(spi_code_load) != 1 785 && BCMI_MADURA_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_GET(spi_code_load)!= 1 786 && BCMI_MADURA_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_GET(spi_code_load) != 0xB) { 787 return PHYMOD_E_INTERNAL; 788 } 789 /* Configure GPREG for programming eeprom */ 790 if (prg_eeprom) { 791 eeprom_num_of_pages = (uint16_t)master_len/MADURA_M0_EEPROM_PAGE_SIZE; 792 793 /* Start Page of EEPROM for master*/ 794 BCMI_MADURA_GPREGEr_CLR(gregE); 795 PHYMOD_IF_ERR_RETURN( 796 BCMI_MADURA_WRITE_GPREGEr(pm_acc,gregE));/*set to 0*/ 797 PHYMOD_IF_ERR_RETURN( 798 BCMI_MADURA_READ_GPREGFr(pm_acc,&gregF)); 799 BCMI_MADURA_GPREGFr_GPREGF_DATAf_SET(gregF,eeprom_num_of_pages); 800 PHYMOD_IF_ERR_RETURN( 801 BCMI_MADURA_WRITE_GPREGFr(pm_acc,gregF));/*set to number of pages*/ 802 803 /* Start Page of EEPROM for slave*/ 804 BCMI_MADURA_GPREGBr_CLR(gregB); 805 PHYMOD_IF_ERR_RETURN( 806 BCMI_MADURA_WRITE_GPREGBr(pm_acc,gregB));/*set to 0*/ 807 PHYMOD_IF_ERR_RETURN( 808 BCMI_MADURA_READ_GPREGCr(pm_acc,&gregC)); 809 BCMI_MADURA_GPREGCr_GPREGC_DATAf_SET(gregC,eeprom_num_of_pages); 810 PHYMOD_IF_ERR_RETURN( 811 BCMI_MADURA_WRITE_GPREGCr(pm_acc,gregC));/*set to number of pages*/ 812 813 /* Reset spi */ 814 /* Assert Reset */ 815 PHYMOD_IF_ERR_RETURN( 816 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 817 BCMI_MADURA_GEN_CTL2r_SPI2X_RSTBf_SET(gen_ctrl2,0);/*resetting SPI2x rstb*/ 818 BCMI_MADURA_GEN_CTL2r_SPI_RSTBf_SET(gen_ctrl2,0);/*resetting SPI rstb*/ 819 PHYMOD_IF_ERR_RETURN( 820 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 821 822 /* Deassert Reset */ 823 BCMI_MADURA_GEN_CTL2r_SPI2X_RSTBf_SET(gen_ctrl2,1); 824 BCMI_MADURA_GEN_CTL2r_SPI_RSTBf_SET(gen_ctrl2,1); 825 PHYMOD_IF_ERR_RETURN( 826 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 827 } 828 /* Select SPI Speed*/ 829 PHYMOD_IF_ERR_RETURN( 830 BCMI_MADURA_READ_GEN_CTL3r(pm_acc,&gen_ctrl3)); 831 BCMI_MADURA_GEN_CTL3r_UCSPI_SLOWf_SET(gen_ctrl3,1); 832 PHYMOD_IF_ERR_RETURN( 833 BCMI_MADURA_WRITE_GEN_CTL3r(pm_acc,gen_ctrl3)); 834 835 /* Check the not downloading branch of the flow digram 836 * before writing to serboot. 837 * wait_mst_msgout(chip_cfg, die, MSGOUT_NOT_DWNLD, 1, 0);*/ 838 839 /* Read / Write boot_por 840 * write to mst_dwld_done and slv_dwld_done. 841 * write to spi_port_used 842 * write to serboot */ 843 PHYMOD_IF_ERR_RETURN( 844 BCMI_MADURA_READ_UC_BOOT_PORr(pm_acc,&boot_por)); 845 /* Force Master New Download */ 846 BCMI_MADURA_UC_BOOT_PORr_MST_DWLD_DONEf_SET(boot_por,0); 847 /* Force Slave New Download */ 848 BCMI_MADURA_UC_BOOT_PORr_SLV_DWLD_DONEf_SET(boot_por,0); 849 BCMI_MADURA_UC_BOOT_PORr_SERBOOTf_SET(boot_por,1); 850 BCMI_MADURA_UC_BOOT_PORr_SPI_PORT_USEDf_SET(boot_por,prg_eeprom);/*set to 0 for mdio default download on reset*/ 851 PHYMOD_IF_ERR_RETURN( 852 BCMI_MADURA_WRITE_UC_BOOT_PORr(pm_acc,boot_por)); 853 854 /* RELEASE Master under Reset */ 855 PHYMOD_IF_ERR_RETURN( 856 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 857 BCMI_MADURA_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2,1); 858 BCMI_MADURA_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2,1); 859 PHYMOD_IF_ERR_RETURN( 860 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 861 862 /* MDI/I2C Download */ 863 /* Waiting for serboot_busy */ 864 retry_cnt = MADURA_FW_DLOAD_RETRY_CNT; 865 do { 866 PHYMOD_IF_ERR_RETURN( 867 BCMI_MADURA_READ_BOOTr(pm_acc,&boot)); 868 data1=BCMI_MADURA_BOOTr_SERBOOT_BUSYf_GET(boot); 869 } while ((data1 == 0) && (retry_cnt--)); 870 if (retry_cnt == 0) { 871 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 872 (_PHYMOD_MSG("ERR:SERBOOT BUSY BIT SET"))); 873 return PHYMOD_E_FAIL; 874 } 875 /* Start download sequence */ 876 /* master boot*/ 877 PHYMOD_IF_ERR_RETURN( 878 madura_micro_download(pm_acc, madura_master_ucode, 879 master_len, 1, &mst_check_sum)); 880 881 PHYMOD_IF_ERR_RETURN( 882 madura_micro_download(pm_acc, madura_slave_ucode, 883 slave_len, 0, &slv_check_sum)); 884 PHYMOD_IF_ERR_RETURN ( 885 _madura_wait_mst_msgout(pm_acc, MSGOUT_DWNLD_DONE, 0)); 886 887 /* Check serboot_busy and serboot_done_once*/ 888 PHYMOD_IF_ERR_RETURN( 889 BCMI_MADURA_READ_BOOTr(pm_acc,&boot)); 890 data1=BCMI_MADURA_BOOTr_SERBOOT_BUSYf_GET(boot); 891 if (data1 != 0) { 892 PHYMOD_DEBUG_ERROR(("WARN:SERBOOT BUSY HAS UNEXPECTED VALUE\n")); 893 } 894 data1=BCMI_MADURA_BOOTr_SERBOOT_DONE_ONCEf_GET(boot); 895 if (data1 != 1) { 896 PHYMOD_DEBUG_ERROR(("WARN:SERBOOT DONE ONCE HAS UNEXPECTED VALUE\n")); 897 } 898 899 /* Wait for Program EEPROM*/ 900 if (prg_eeprom) { 901 _madura_wait_mst_msgout(pm_acc, MSGOUT_PRGRM_DONE,0); 902 /* Assert SPI Reset*/ 903 PHYMOD_IF_ERR_RETURN( 904 BCMI_MADURA_READ_GEN_CTL2r(pm_acc,&gen_ctrl2)); 905 BCMI_MADURA_GEN_CTL2r_SPI2X_RSTBf_SET(gen_ctrl2,0);/*resetting SPI2x rstb*/ 906 BCMI_MADURA_GEN_CTL2r_SPI_RSTBf_SET(gen_ctrl2,0);/*resetting SPI rstb*/ 907 PHYMOD_IF_ERR_RETURN( 908 BCMI_MADURA_WRITE_GEN_CTL2r(pm_acc,gen_ctrl2)); 909 } 910 911 PHYMOD_IF_ERR_RETURN( 912 BCMI_MADURA_READ_FIRMWARE_VERSIONr(pm_acc,&fw_ver)); 913 914 data1=BCMI_MADURA_FIRMWARE_VERSIONr_FIRMWARE_VERSION_VALf_GET(fw_ver); 915 PHYMOD_DEBUG_VERBOSE(("FW Version:0x%x\n", data1)); 916 917 return PHYMOD_E_NONE; 918 } 919 920 int _madura_core_init(const phymod_core_access_t* core, 921 const phymod_core_init_config_t* init_config) 922 { 923 int ret_val = 0; 924 uint32_t rev = 0, chip_id = 0; 925 phymod_access_t pa; 926 const phymod_access_t *pm_acc = &core->access; 927 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_t pad_ctrl; 928 BCMI_MADURA_GEN_CTL2r_t gen_ctrl2; 929 BCMI_MADURA_FIRMWARE_FEATURESr_t firm_features; 930 BCMI_MADURA_UC_BOOT_PORr_t boot_por; 931 932 /* Bring second die out of reset */ 933 PHYMOD_MEMCPY(&pa, pm_acc, sizeof(phymod_access_t)); 934 pa.addr &= ~(1U); 935 PHYMOD_IF_ERR_RETURN( 936 PHYMOD_BUS_WRITE(&pa,0x18a50,0xa06)); 937 PHYMOD_MEMCPY(&pa, pm_acc, sizeof(phymod_access_t)); 938 939 /* clear vars */ 940 PHYMOD_MEMSET(&gen_ctrl2, 0, sizeof(BCMI_MADURA_GEN_CTL2r_t)); 941 PHYMOD_MEMSET(&pad_ctrl, 0, sizeof(BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_t)); 942 943 PHYMOD_MEMSET(&firm_features, 0, sizeof(BCMI_MADURA_FIRMWARE_FEATURESr_t)); 944 PHYMOD_MEMSET(&boot_por, 0 , sizeof(BCMI_MADURA_UC_BOOT_PORr_t)); 945 946 PHYMOD_IF_ERR_RETURN( 947 BCMI_MADURA_READ_FIRMWARE_FEATURESr(pm_acc,&firm_features)); 948 949 switch(init_config->firmware_load_method) 950 { 951 case phymodFirmwareLoadMethodInternal: 952 PHYMOD_DEBUG_VERBOSE(( 953 "Starting Firmware download through MDIO, it takes few seconds...\n")); 954 955 /* In case of FW Download is only for second die i.e for odd address of the die 956 * To get the micro out of reset on even die(previous die); for MDIO only 957 * Applicable for only duel die chips; 958 * MADURA_CHIP_ID_82790 is 82790 is single die ingnore the micro out of reset 959 */ 960 PHYMOD_IF_ERR_RETURN(madura_get_chipid(pm_acc, &chip_id, &rev)); 961 PHYMOD_MEMCPY(&pa, pm_acc, sizeof(phymod_access_t)); 962 if (PHYMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD_GET(init_config)) { 963 964 /*if Die B. 965 In case only DIE_B is selected: 966 - put DIE_A M0 under reset 967 - Release reset of DIE_B M0*/ 968 if (((pm_acc->addr & 0x1) == 0x1) && (chip_id != MADURA_CHIP_ID_82864)) { 969 /* modify the mdio address to be even */ 970 pa.addr &= ~(0x1); 971 /* Set the 11th and 9th bit of even die to get the micro out of reset */ 972 973 /* Put DIE_A Master under Reset 974 - This ensures that Die_A is not downloading at the same time of Die_B*/ 975 PHYMOD_IF_ERR_RETURN( 976 BCMI_MADURA_READ_GEN_CTL2r(&pa,&gen_ctrl2)); 977 BCMI_MADURA_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2,0);/*resetting M0 micro*/ 978 BCMI_MADURA_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2,0);/*resetting M0 micro perip*/ 979 PHYMOD_IF_ERR_RETURN( 980 BCMI_MADURA_WRITE_GEN_CTL2r(&pa,gen_ctrl2)); 981 982 /*Release reset of Die_B*/ 983 PHYMOD_IF_ERR_RETURN( 984 BCMI_MADURA_READ_EXT_UC_RSTB_OUT_CTLr(&pa,&pad_ctrl)); 985 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_EXT_UC_RSTB_OUT_OUT_FRCVALf_SET(pad_ctrl,1); 986 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_EXT_UC_RSTB_OUT_IBOFf_SET(pad_ctrl,1); 987 PHYMOD_IF_ERR_RETURN( 988 BCMI_MADURA_WRITE_EXT_UC_RSTB_OUT_CTLr(&pa,pad_ctrl)); 989 }else{ 990 /*ALL Dies*/ 991 /*Restore ext_uc_rstb in die A*/ 992 PHYMOD_IF_ERR_RETURN( 993 BCMI_MADURA_READ_EXT_UC_RSTB_OUT_CTLr(&pa,&pad_ctrl)); 994 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_EXT_UC_RSTB_OUT_OUT_FRCVALf_SET(pad_ctrl,0); 995 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_EXT_UC_RSTB_OUT_IBOFf_SET(pad_ctrl,0); 996 PHYMOD_IF_ERR_RETURN( 997 BCMI_MADURA_WRITE_EXT_UC_RSTB_OUT_CTLr(&pa,pad_ctrl)); 998 } 999 1000 1001 /* Do chip hard reset and Resetting the Cores */ 1002 PHYMOD_IF_ERR_RETURN( 1003 _madura_core_reset_set(pm_acc, phymodResetModeHard, phymodResetDirectionInOut)); 1004 1005 } else if (PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 1006 1007 /* Enable broadcast */ 1008 PHYMOD_IF_ERR_RETURN( 1009 PHYMOD_BUS_WRITE(pm_acc,0x18204,0x1)); 1010 1011 } else if (PHYMOD_CORE_INIT_F_EXECUTE_FW_LOAD_GET(init_config)) { 1012 1013 ret_val = _madura_firmware_download(pm_acc, 1014 madura_falcon_ucode, madura_falcon_ucode_len, 1015 madura_falcon_slave_ucode, madura_falcon_ucode_slave_len, 1016 0); 1017 if ((ret_val != PHYMOD_E_NONE) && (ret_val != MADURA_FW_ALREADY_DOWNLOADED)) { 1018 PHYMOD_RETURN_WITH_ERR 1019 (ret_val, 1020 (_PHYMOD_MSG("firmware download failed"))); 1021 } else { 1022 PHYMOD_DEBUG_VERBOSE(("Firmware download through MDIO success\n")); 1023 } 1024 1025 PHYMOD_IF_ERR_RETURN ( 1026 _madura_cfg_fw_ull_dp(&core->access, init_config->op_datapath)); 1027 1028 } else if (PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 1029 1030 /* Disable broadcast */ 1031 PHYMOD_IF_ERR_RETURN( 1032 PHYMOD_BUS_WRITE(pm_acc,0x18204,0x0)); 1033 1034 /* check download_done flags again */ 1035 PHYMOD_IF_ERR_RETURN( 1036 BCMI_MADURA_READ_UC_BOOT_PORr(pm_acc,&boot_por)); 1037 if (BCMI_MADURA_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por)!= 1 || BCMI_MADURA_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por) != 1) { 1038 PHYMOD_DEBUG_VERBOSE(("FW download successfull \n")); 1039 } 1040 } 1041 1042 break; 1043 case phymodFirmwareLoadMethodExternal: 1044 return PHYMOD_E_UNAVAIL; 1045 break; 1046 case phymodFirmwareLoadMethodNone: 1047 break; 1048 case phymodFirmwareLoadMethodProgEEPROM: 1049 PHYMOD_IF_ERR_RETURN( 1050 madura_download_helper ( 1051 pm_acc , 1052 madura_falcon_flashing_ucode, 1053 madura_falcon_flashing_ucode_len, 1054 1 /* master_en */, 1055 0 /* slave_en */, 1056 0 /* code_broadcast_en */, 1057 0 /* mst_boot_addr */, 1058 0 /* prg_eeprom */, 1059 0 /* eeprom_download */ 1060 )); 1061 PHYMOD_IF_ERR_RETURN( 1062 madura_download_helper ( 1063 pm_acc , 1064 madura_falcon_ucode, 1065 madura_falcon_ucode_len, 1066 1 /* master_en */, 1067 0 /* slave_en */, 1068 0 /* code_broadcast_en */, 1069 0 /* mst_boot_addr */, 1070 1 /* prg_eeprom */, 1071 0 /* eeprom_download */ 1072 )); 1073 1074 PHYMOD_IF_ERR_RETURN( 1075 madura_download_helper ( 1076 pm_acc , 1077 madura_falcon_slave_ucode, 1078 madura_falcon_ucode_slave_len, 1079 0 /* master_en */, 1080 1 /* slave_en */, 1081 0 /* code_broadcast_en */, 1082 0 /* mst_boot_addr */, 1083 1 /* prg_eeprom */, 1084 0 /* eeprom_download */ 1085 )); 1086 /*ALL Dies*/ 1087 /*Restore ext_uc_rstb in die A*/ 1088 PHYMOD_MEMCPY(&pa, pm_acc, sizeof(phymod_access_t)); 1089 PHYMOD_IF_ERR_RETURN( 1090 BCMI_MADURA_READ_EXT_UC_RSTB_OUT_CTLr(&pa,&pad_ctrl)); 1091 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_EXT_UC_RSTB_OUT_OUT_FRCVALf_SET(pad_ctrl,0); 1092 BCMI_MADURA_EXT_UC_RSTB_OUT_CTLr_EXT_UC_RSTB_OUT_IBOFf_SET(pad_ctrl,0); 1093 PHYMOD_IF_ERR_RETURN( 1094 BCMI_MADURA_WRITE_EXT_UC_RSTB_OUT_CTLr(&pa,pad_ctrl)); 1095 1096 PHYMOD_IF_ERR_RETURN( 1097 madura_download_helper ( 1098 pm_acc , 1099 madura_falcon_flashing_ucode, 1100 0 /* madura_falcon_flashing_ucode_len */, 1101 1 /* master_en */, 1102 1 /* slave_en */, 1103 0 /* code_broadcast_en */, 1104 0 /* mst_boot_addr */, 1105 0 /* prg_eeprom : this is 0 in validation application*/, 1106 1 /* eeprom_download */ 1107 )); 1108 1109 1110 break; 1111 default: 1112 PHYMOD_RETURN_WITH_ERR 1113 (PHYMOD_E_CONFIG, 1114 (_PHYMOD_MSG("illegal fw load method"))); 1115 } 1116 /*check if fw runs!*/ 1117 PHYMOD_IF_ERR_RETURN( 1118 BCMI_MADURA_READ_FIRMWARE_FEATURESr(pm_acc,&firm_features)); 1119 1120 /* Force clock to 0 temporarily */ 1121 { 1122 1123 BCMI_MADURA_CLK_SCALER_CTLr_t clk_ctrl; 1124 PHYMOD_MEMSET(&clk_ctrl, 0, sizeof(BCMI_MADURA_CLK_SCALER_CTLr_t)); 1125 1126 BCMI_MADURA_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl,0x800); 1127 PHYMOD_IF_ERR_RETURN( 1128 BCMI_MADURA_WRITE_CLK_SCALER_CTLr(pm_acc,clk_ctrl)); 1129 } 1130 return PHYMOD_E_NONE; 1131 } 1132 1133 int _madura_set_slice_an_reg ( 1134 const phymod_access_t* pm_acc, 1135 uint16_t ip, 1136 uint16_t dev_type, 1137 uint16_t lane, 1138 uint16_t port ) 1139 { 1140 BCMI_MADURA_AN_SLICEr_t slice_an_reg; 1141 uint16_t sys_sel=0,lin_sel=0,slice_0=0,slice_1=0; 1142 1143 PHYMOD_MEMSET(&slice_an_reg, 0 , sizeof(BCMI_MADURA_AN_SLICEr_t)); 1144 1145 /*selecting sys or line side*/ 1146 sys_sel = (ip==MADURA_FALCON_CORE)? 1 : 0; 1147 lin_sel = (ip==MADURA_FALCON_CORE)? 0 : 1; 1148 1149 /*set lane*/ 1150 if(lane<4) 1151 { 1152 slice_0=1; 1153 }else{ 1154 slice_1=1; 1155 } 1156 1157 1158 if (dev_type == MADURA_DEV_AN) { 1159 PHYMOD_IF_ERR_RETURN( 1160 BCMI_MADURA_READ_AN_SLICEr(pm_acc,&slice_an_reg)); 1161 BCMI_MADURA_AN_SLICEr_SYS_SELf_SET(slice_an_reg,sys_sel); 1162 BCMI_MADURA_AN_SLICEr_LIN_SELf_SET(slice_an_reg,lin_sel); 1163 BCMI_MADURA_AN_SLICEr_SLICE_0_SELf_SET(slice_an_reg,slice_0); 1164 BCMI_MADURA_AN_SLICEr_SLICE_1_SELf_SET(slice_an_reg,slice_1); 1165 BCMI_MADURA_AN_SLICEr_REG_TYPE_SELf_SET(slice_an_reg,1); 1166 BCMI_MADURA_AN_SLICEr_PORT_SELf_SET(slice_an_reg,port); 1167 BCMI_MADURA_AN_SLICEr_LANE_SELf_SET(slice_an_reg,0); 1168 PHYMOD_IF_ERR_RETURN( 1169 BCMI_MADURA_WRITE_AN_SLICEr(pm_acc,slice_an_reg)); 1170 } 1171 1172 return PHYMOD_E_NONE; 1173 } 1174 1175 int _madura_set_slice_reg ( 1176 const phymod_access_t* pm_acc, 1177 uint16_t ip, 1178 uint16_t dev_type, 1179 uint16_t lane, 1180 uint16_t pll_sel) 1181 { 1182 BCMI_MADURA_SLICEr_t slice_reg; 1183 uint16_t sys_sel=0,lin_sel=0,lane_no=0,slice_0=0,slice_1=0; 1184 1185 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 1186 1187 /*selecting sys or line side*/ 1188 sys_sel = (ip==MADURA_FALCON_CORE)? 1 : 0; 1189 lin_sel = (ip==MADURA_FALCON_CORE)? 0 : 1; 1190 1191 /*set lane*/ 1192 lane_no=1<<((lane%4)); 1193 if(lane<4) 1194 { 1195 slice_0=1; 1196 }else{ 1197 slice_1=1; 1198 } 1199 1200 if (dev_type == MADURA_DEV_PMA_PMD) { 1201 PHYMOD_IF_ERR_RETURN( 1202 BCMI_MADURA_READ_SLICEr(pm_acc,&slice_reg)); 1203 BCMI_MADURA_SLICEr_PLL_SELf_SET(slice_reg,pll_sel); 1204 BCMI_MADURA_SLICEr_SYS_SELf_SET(slice_reg,sys_sel); 1205 BCMI_MADURA_SLICEr_LIN_SELf_SET(slice_reg,lin_sel); 1206 BCMI_MADURA_SLICEr_SLICE_0_SELf_SET(slice_reg,slice_0); 1207 BCMI_MADURA_SLICEr_SLICE_1_SELf_SET(slice_reg,slice_1); 1208 BCMI_MADURA_SLICEr_LANE_SELf_SET(slice_reg,lane_no); 1209 BCMI_MADURA_SLICEr_REG_TYPE_SELf_SET(slice_reg,0); 1210 PHYMOD_IF_ERR_RETURN( 1211 BCMI_MADURA_WRITE_SLICEr(pm_acc,slice_reg)); 1212 PHYMOD_DEBUG_VERBOSE(("\n[-- ip=%x slice = %x ===]\n",ip,BCMI_MADURA_SLICEr_GET(slice_reg))); 1213 } 1214 1215 return PHYMOD_E_NONE; 1216 } 1217 1218 int _madura_rx_pmd_lock_get(const phymod_access_t* pa, uint32_t* rx_pmd_locked) 1219 { 1220 BCMI_MADURA_TLB_RX_PMD_RX_LOCK_STSr_t rx_lck; 1221 BCMI_MADURA_SLICEr_t slice_reg; 1222 phymod_phy_inf_config_t config; 1223 uint16_t ip = 0; 1224 uint16_t lane = 0; 1225 uint16_t temp = 0,intf_side=0; 1226 uint16_t lane_mask = 0, max_lane = 0; 1227 1228 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 1229 PHYMOD_MEMSET(&rx_lck, 0 , sizeof(BCMI_MADURA_TLB_RX_PMD_RX_LOCK_STSr_t)); 1230 if (rx_pmd_locked) { 1231 *rx_pmd_locked = 0xffff; 1232 } else { 1233 return PHYMOD_E_PARAM; 1234 } 1235 1236 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 1237 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 1238 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 1239 _madura_phy_interface_config_get(pa, 0, &config))); 1240 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1241 MADURA_GET_IP(pa, config, ip); 1242 1243 MADURA_GET_INTF_SIDE(pa, intf_side); 1244 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 1245 for (lane = 0; lane < max_lane; lane ++) { 1246 if (lane_mask & (1 << lane)) { 1247 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 1248 _madura_set_slice_reg (pa, 1249 ip, MADURA_DEV_PMA_PMD, lane, 0))); 1250 1251 /*check pmd rx lock*/ 1252 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 1253 BCMI_MADURA_READ_TLB_RX_PMD_RX_LOCK_STSr(pa,&rx_lck))); 1254 1255 temp=BCMI_MADURA_TLB_RX_PMD_RX_LOCK_STSr_PMD_RX_LOCKf_GET(rx_lck); 1256 1257 *rx_pmd_locked &= temp; 1258 } 1259 } 1260 1261 /*Reset DEV1 slice register*/ 1262 PHYMOD_FREE(config.device_aux_modes); 1263 PHYMOD_IF_ERR_RETURN( 1264 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 1265 1266 return PHYMOD_E_NONE; 1267 } 1268 1269 int madura_is_lane_mask_set(const phymod_phy_access_t *pa, uint16_t prt, 1270 const phymod_phy_inf_config_t *config) 1271 { 1272 phymod_phy_inf_config_t cfg; 1273 uint16_t core = 0; 1274 uint32_t lane_mask = 0; 1275 MADURA_DEVICE_AUX_MODE_T *aux; 1276 const phymod_access_t *acc = &pa->access; 1277 1278 lane_mask = pa->access.lane_mask; 1279 PHYMOD_MEMCPY(&cfg, config, sizeof(phymod_phy_inf_config_t)); 1280 aux = (MADURA_DEVICE_AUX_MODE_T*)config->device_aux_modes; 1281 MADURA_GET_IP(acc, cfg, core) ; 1282 PHYMOD_DEBUG_VERBOSE(("%s :: core:%d port:%d\n", __func__, core, prt)); 1283 if (core == MADURA_2X_FALCON_CORE) { 1284 if ((cfg.data_rate == MADURA_SPD_40G)||(cfg.data_rate == MADURA_SPD_100G) || 1285 (cfg.data_rate == MADURA_SPD_50G)|| 1286 (cfg.data_rate == MADURA_SPD_42G)||(cfg.data_rate == MADURA_SPD_106G)) { 1287 if (prt == 0) { 1288 /* coverity[identical_branches] */ 1289 if (aux->pass_thru_dual_lane) { 1290 if(!aux->alternate){ 1291 return (lane_mask == 0x3) ? 1 : 0; 1292 } else { 1293 return (lane_mask == 0x30) ? 1 : 0; 1294 } 1295 } else if (aux->pass_thru) { 1296 if(!aux->alternate){ 1297 return ((lane_mask & 0xf) == 0xF) ? 1 : 0 ; 1298 }else{ 1299 return ((lane_mask & 0xf0) == 0xF0) ? 1 : 0 ; 1300 } 1301 } else { 1302 return ((lane_mask & 0xF) == 0xF) ? 1 : 0; 1303 } 1304 } else { 1305 if (aux->pass_thru_dual_lane) { 1306 if(!aux->alternate){ 1307 return (lane_mask == 0xC) ? 1 : 0; 1308 } else { 1309 return (lane_mask == 0xC0) ? 1 : 0; 1310 } 1311 } else if (aux->pass_thru) { 1312 return 0; 1313 } else { 1314 return ((lane_mask & 0xF0) == 0xf0) ? 1 : 0; 1315 } 1316 } 1317 } 1318 if (cfg.data_rate == MADURA_SPD_10G || cfg.data_rate == MADURA_SPD_25G || 1319 cfg.data_rate == MADURA_SPD_11G || cfg.data_rate == MADURA_SPD_1G) { 1320 /* For 10G PT and alternate modes*/ 1321 if (prt == 0) { 1322 if (!aux->alternate) { 1323 return (lane_mask & 0x1) ? 1 :0; 1324 }else{ 1325 return (lane_mask & 0x10) ? 1 :0; 1326 } 1327 } else if (prt == 1) { 1328 if (!aux->alternate) { 1329 return (lane_mask & 0x2) ? 1 :0; 1330 }else{ 1331 return (lane_mask & 0x20) ? 1 :0; 1332 } 1333 } else if (prt == 2) { 1334 if (!aux->alternate) { 1335 return (lane_mask & 0x4) ? 1 :0; 1336 } else { 1337 return (lane_mask & 0x40) ? 1 :0; 1338 } 1339 } else if (prt == 3) { 1340 if (!aux->alternate) { 1341 return (lane_mask & 0x8) ? 1 :0; 1342 } else { 1343 return (lane_mask & 0x80) ? 1 :0; 1344 } 1345 } 1346 } 1347 } else { /*System SIDE*/ 1348 if ((cfg.data_rate == MADURA_SPD_40G)||(cfg.data_rate == MADURA_SPD_100G) || 1349 (cfg.data_rate == MADURA_SPD_50G)|| 1350 (cfg.data_rate == MADURA_SPD_42G)||(cfg.data_rate == MADURA_SPD_106G)) { 1351 if (prt == 0) { 1352 if (aux->pass_thru_dual_lane) { 1353 return (lane_mask == 0x3) ? 1 : 0; 1354 } else if (aux->pass_thru) { 1355 return ((lane_mask & 0xf) == 0xF) ? 1 : 0 ; 1356 } else { 1357 return ((lane_mask & 0x3) == 0x3) ? 1 : 0; 1358 } 1359 } else { 1360 if (aux->pass_thru_dual_lane) { 1361 return (lane_mask == 0xC) ? 1 : 0; 1362 } else if (aux->pass_thru) { 1363 return 0; 1364 } else { 1365 return ((lane_mask & 0xc) == 0xc) ? 1 : 0; 1366 } 1367 } 1368 } 1369 if (cfg.data_rate == MADURA_SPD_10G || cfg.data_rate == MADURA_SPD_25G || 1370 cfg.data_rate == MADURA_SPD_11G || cfg.data_rate == MADURA_SPD_1G) { 1371 /* For 10G PT with 1 core disabled */ 1372 if (prt == 0) { 1373 return (lane_mask & 0x1) ? 1 :0; 1374 } else if (prt == 1) { 1375 return (lane_mask & 0x2) ? 1 :0; 1376 } else if (prt == 2) { 1377 return (lane_mask & 0x4) ? 1 :0; 1378 } else if (prt == 3) { 1379 return (lane_mask & 0x8) ? 1 :0; 1380 } 1381 } 1382 } 1383 return 0; 1384 } 1385 /** Configure Dut Mode Register 1386 */ 1387 int _madura_config_dut_mode_reg(const phymod_phy_access_t *pa, const phymod_phy_inf_config_t* config) 1388 { 1389 1390 BCMI_MADURA_P0_MODE_CTLr_t mode_ctrl0; 1391 BCMI_MADURA_P1_MODE_CTLr_t mode_ctrl1; 1392 BCMI_MADURA_P2_MODE_CTLr_t mode_ctrl2; 1393 BCMI_MADURA_P3_MODE_CTLr_t mode_ctrl3; 1394 BCMI_MADURA_MST_CFG0r_t mst_cfg0; 1395 unsigned char mindex0 = 0xFF; 1396 unsigned char mindex1 = 0xFF; 1397 unsigned char mindex2 = 0xFF; 1398 unsigned char mindex3 = 0xFF; 1399 1400 uint32_t alt_off = 0; 1401 uint16_t no_of_ports = 0, port_idx = 0; 1402 MADURA_DEVICE_AUX_MODE_T *aux_mode; 1403 uint16_t core = 0; 1404 uint16_t is_lane_used = 0, mst_cfg0_val = 0; 1405 const phymod_access_t *acc = &pa->access; 1406 phymod_phy_inf_config_t cfg; 1407 1408 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 1409 PHYMOD_MEMSET(&mode_ctrl1, 0, sizeof(BCMI_MADURA_P1_MODE_CTLr_t)); 1410 PHYMOD_MEMSET(&mode_ctrl2, 0, sizeof(BCMI_MADURA_P2_MODE_CTLr_t)); 1411 PHYMOD_MEMSET(&mode_ctrl3, 0, sizeof(BCMI_MADURA_P3_MODE_CTLr_t)); 1412 PHYMOD_MEMSET(&mst_cfg0, 0, sizeof(BCMI_MADURA_MST_CFG0r_t)); 1413 PHYMOD_MEMCPY(&cfg, config, sizeof(phymod_phy_inf_config_t)); 1414 MADURA_GET_IP(acc, cfg, core); 1415 1416 aux_mode = (MADURA_DEVICE_AUX_MODE_T*)config->device_aux_modes; 1417 1418 if ((core == MADURA_2X_FALCON_CORE) && aux_mode->alternate ) { 1419 alt_off = 4; 1420 } 1421 1422 MADURA_GET_PORT_FROM_MODE(config, no_of_ports, aux_mode); 1423 PHYMOD_IF_ERR_RETURN( 1424 BCMI_MADURA_READ_MST_CFG0r(&pa->access, &mst_cfg0)); 1425 1426 mst_cfg0_val = BCMI_MADURA_MST_CFG0r_GET(mst_cfg0); 1427 1428 if(core == MADURA_2X_FALCON_CORE) 1429 { 1430 /*P1 is in Mux mode as set be the fw. SW needs to clear it always during startup*/ 1431 PHYMOD_IF_ERR_RETURN( 1432 BCMI_MADURA_READ_P1_MODE_CTLr(&pa->access, &mode_ctrl1)); 1433 if(MADURA_MIDX_40GDM_1B == BCMI_MADURA_P1_MODE_CTLr_P1_MINDEXf_GET(mode_ctrl1)) 1434 { 1435 PHYMOD_MEMSET(&mode_ctrl1, 0, sizeof(BCMI_MADURA_P1_MODE_CTLr_t)); 1436 PHYMOD_IF_ERR_RETURN( 1437 BCMI_MADURA_WRITE_P1_MODE_CTLr(&pa->access, mode_ctrl1)); 1438 } 1439 switch(pa->access.lane_mask) 1440 { 1441 case 0xF: 1442 mst_cfg0_val = 0; 1443 if(!(!aux_mode->pass_thru && (config->data_rate == MADURA_SPD_40G))) /* for Mux mode 1 3 0 else all */ 1444 { 1445 PHYMOD_IF_ERR_RETURN( 1446 BCMI_MADURA_WRITE_P2_MODE_CTLr(&pa->access, mode_ctrl2)); 1447 }else{ 1448 /*In Mux mode*/ 1449 PHYMOD_IF_ERR_RETURN( 1450 BCMI_MADURA_READ_P2_MODE_CTLr(&pa->access, &mode_ctrl2)); 1451 if(!(MADURA_MIDX_40GDM_1B == BCMI_MADURA_P2_MODE_CTLr_P2_MINDEXf_GET(mode_ctrl2)) ) 1452 { 1453 PHYMOD_MEMSET(&mode_ctrl2, 0, sizeof(BCMI_MADURA_P2_MODE_CTLr_t)); 1454 PHYMOD_IF_ERR_RETURN( 1455 BCMI_MADURA_WRITE_P2_MODE_CTLr(&pa->access, mode_ctrl2)); 1456 } 1457 } 1458 PHYMOD_IF_ERR_RETURN( 1459 BCMI_MADURA_WRITE_P0_MODE_CTLr(&pa->access, mode_ctrl0)); 1460 PHYMOD_IF_ERR_RETURN( 1461 BCMI_MADURA_WRITE_P1_MODE_CTLr(&pa->access, mode_ctrl1)); 1462 PHYMOD_IF_ERR_RETURN( 1463 BCMI_MADURA_WRITE_P3_MODE_CTLr(&pa->access, mode_ctrl3)); 1464 break; 1465 case 0xF0: 1466 mst_cfg0_val = 0; 1467 if(!(!aux_mode->pass_thru && (config->data_rate == MADURA_SPD_40G))) /* for Mux mode 1 3 2 else all */ 1468 { 1469 PHYMOD_IF_ERR_RETURN( 1470 BCMI_MADURA_WRITE_P0_MODE_CTLr(&pa->access, mode_ctrl0)); 1471 }else{ 1472 /*In Mux mode*/ 1473 PHYMOD_IF_ERR_RETURN( 1474 BCMI_MADURA_READ_P0_MODE_CTLr(&pa->access, &mode_ctrl0)); 1475 if(!(MADURA_MIDX_40GDM_0B == BCMI_MADURA_P0_MODE_CTLr_P0_MINDEXf_GET(mode_ctrl0))) 1476 { 1477 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 1478 PHYMOD_IF_ERR_RETURN( 1479 BCMI_MADURA_WRITE_P0_MODE_CTLr(&pa->access, mode_ctrl0)); 1480 } 1481 } 1482 PHYMOD_IF_ERR_RETURN( 1483 BCMI_MADURA_WRITE_P1_MODE_CTLr(&pa->access, mode_ctrl1)); 1484 PHYMOD_IF_ERR_RETURN( 1485 BCMI_MADURA_WRITE_P2_MODE_CTLr(&pa->access, mode_ctrl2)); 1486 PHYMOD_IF_ERR_RETURN( 1487 BCMI_MADURA_WRITE_P3_MODE_CTLr(&pa->access, mode_ctrl3)); 1488 break; 1489 case 0x3: 1490 case 0x30: 1491 mst_cfg0_val = 0; 1492 /*clear 0 1*/ 1493 PHYMOD_IF_ERR_RETURN( 1494 BCMI_MADURA_WRITE_P0_MODE_CTLr(&pa->access, mode_ctrl0)); 1495 PHYMOD_IF_ERR_RETURN( 1496 BCMI_MADURA_WRITE_P1_MODE_CTLr(&pa->access, mode_ctrl1)); 1497 break; 1498 case 0xc: 1499 case 0xc0: 1500 mst_cfg0_val = 0; 1501 /*Clear 2 3*/ 1502 PHYMOD_IF_ERR_RETURN( 1503 BCMI_MADURA_WRITE_P2_MODE_CTLr(&pa->access, mode_ctrl2)); 1504 PHYMOD_IF_ERR_RETURN( 1505 BCMI_MADURA_WRITE_P3_MODE_CTLr(&pa->access, mode_ctrl3)); 1506 break; 1507 1508 default: 1509 break; 1510 } 1511 } 1512 1513 1514 if (config->data_rate != MADURA_SPD_100G && 1515 config->data_rate != MADURA_SPD_106G) { 1516 PHYMOD_IF_ERR_RETURN( 1517 BCMI_MADURA_READ_P0_MODE_CTLr(&pa->access, &mode_ctrl0)); 1518 PHYMOD_IF_ERR_RETURN( 1519 BCMI_MADURA_READ_P2_MODE_CTLr(&pa->access, &mode_ctrl2)); 1520 for (port_idx=0; port_idx < no_of_ports; port_idx++) { 1521 if(config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_25G || 1522 config->data_rate == MADURA_SPD_11G || cfg.data_rate == MADURA_SPD_1G ) { 1523 /* coverity[identical_branches] */ 1524 if (core == MADURA_2X_FALCON_CORE) { 1525 if (pa->access.lane_mask & (1 << (port_idx + alt_off))) { 1526 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1527 } else { 1528 continue; 1529 } 1530 } else { 1531 if (pa->access.lane_mask & (1 << port_idx)) { 1532 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1533 } else { 1534 continue; 1535 } 1536 } 1537 } else if((config->data_rate == MADURA_SPD_40G || config->data_rate == MADURA_SPD_50G || 1538 config->data_rate == MADURA_SPD_42G) && 1539 aux_mode->pass_thru_dual_lane) { 1540 /* coverity[identical_branches] */ 1541 if (core == MADURA_2X_FALCON_CORE) { 1542 if (pa->access.lane_mask & (0x3 << (alt_off + (port_idx * 2)))) { 1543 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1544 } else { 1545 continue; 1546 } 1547 } else { 1548 if (pa->access.lane_mask & (0x3 << (port_idx * 2))) { 1549 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1550 } else { 1551 continue; 1552 } 1553 } 1554 } else if((config->data_rate == MADURA_SPD_40G || config->data_rate == MADURA_SPD_42G) && 1555 (!aux_mode->pass_thru)) { 1556 if (core == MADURA_2X_FALCON_CORE) { 1557 /* MUX Mode*/ 1558 if (pa->access.lane_mask & (0xF << (port_idx*4))) { 1559 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1560 } else { 1561 continue; 1562 } 1563 } else { 1564 if (pa->access.lane_mask & (0x3 << (port_idx * 2))) { 1565 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1566 } else { 1567 continue; 1568 } 1569 } 1570 } else { 1571 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1572 } 1573 if (!is_lane_used) { 1574 return PHYMOD_E_PARAM; 1575 } 1576 1577 /* Program Modes */ 1578 if (((config->data_rate == MADURA_SPD_40G || config->data_rate == MADURA_SPD_42G || config->data_rate == MADURA_SPD_50G ) && (port_idx == 0)) || 1579 ((config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_11G || config->data_rate == MADURA_SPD_25G || cfg.data_rate == MADURA_SPD_1G ) && (port_idx < 2))) { 1580 if (config->data_rate == MADURA_SPD_40G) { 1581 if (!aux_mode->alternate) { 1582 if (aux_mode->pass_thru_dual_lane) { 1583 mindex0 = MADURA_MIDX_40GPT20_0; 1584 mindex3=0; 1585 } else if (aux_mode->pass_thru) { 1586 mindex0 = MADURA_MIDX_40GPT10_0 ; 1587 } else { 1588 mindex0 = MADURA_MIDX_40GDM_0B ; 1589 mindex3=0; 1590 } 1591 } else { 1592 if (aux_mode->pass_thru_dual_lane) { 1593 mindex0 = MADURA_MIDX_40GPT20_0A; 1594 mindex3=0; 1595 } else if (aux_mode->pass_thru) { 1596 mindex0 = MADURA_MIDX_40GPT10_0A; 1597 } else { 1598 mindex0 = MADURA_MIDX_40GDM_0B ; 1599 mindex3=0; 1600 } 1601 } 1602 mindex1 = 0; 1603 } 1604 if (config->data_rate == MADURA_SPD_42G) { 1605 if (!aux_mode->alternate) { 1606 if (aux_mode->pass_thru_dual_lane) { 1607 mindex0 = MADURA_MIDX_40HGPT20_0; 1608 mindex3=0; 1609 } else if (aux_mode->pass_thru) { 1610 mindex0 = MADURA_MIDX_40HGPT10_0 ; 1611 } else { 1612 mindex0 = MADURA_MIDX_40HGDM_0B ; 1613 mindex3=0; 1614 } 1615 } else { 1616 if (aux_mode->pass_thru_dual_lane) { 1617 mindex0 = MADURA_MIDX_40HGPT20_0A; 1618 mindex3=0; 1619 } else if (aux_mode->pass_thru) { 1620 mindex0 = MADURA_MIDX_40HGPT10_0A; 1621 } else { 1622 mindex0 = MADURA_MIDX_40HGDM_0B ; 1623 mindex3=0; 1624 } 1625 } 1626 mindex1 = 0; 1627 } 1628 if (config->data_rate == MADURA_SPD_50G) { 1629 if (!aux_mode->alternate) { 1630 mindex0 = MADURA_MIDX_40GPT20_0; 1631 mindex3=0; 1632 } else { 1633 mindex0 = MADURA_MIDX_40GPT20_0A; 1634 mindex3=0; 1635 } 1636 mindex1 = 0; 1637 } 1638 1639 if ( cfg.data_rate == MADURA_SPD_1G ) { /*same as 10G mode registers */ 1640 if ((pa->access.lane_mask & 0x1) || (pa->access.lane_mask & 0x10)) { 1641 mst_cfg0_val &= ~(0x0001); /* set Pll to 0 by clearing in case of flex from 25G*/ 1642 mst_cfg0_val |= 0x100 ; /*enable 1G with default pll as 132 with pll_index as 0*/ 1643 if (!aux_mode->alternate) { 1644 mindex0 = MADURA_MIDX_10GPT_0 ; 1645 } else { 1646 mindex0 = MADURA_MIDX_10GPT_0A; 1647 } 1648 } 1649 if ((pa->access.lane_mask & 0x2) || (pa->access.lane_mask & 0x20)) { 1650 mst_cfg0_val &= ~(0x0002); /* set Pll to 0 by clearing in case of flex from 25G*/ 1651 mst_cfg0_val |= 0x200 ; /*enable 1G with default pll as 132 with pll_index as 0*/ 1652 if (!aux_mode->alternate) { 1653 mindex1 = MADURA_MIDX_10GPT_1 ; 1654 } else { 1655 mindex1 = MADURA_MIDX_10GPT_1A; 1656 } 1657 } 1658 } 1659 1660 if (config->data_rate == MADURA_SPD_25G || config->data_rate == MADURA_SPD_10G) { 1661 if ((pa->access.lane_mask & 0x1) || (pa->access.lane_mask & 0x10)) { 1662 mst_cfg0_val &= ~(0x100) ; /*cleare 1G */ 1663 if(config->data_rate == MADURA_SPD_25G ){ 1664 mst_cfg0_val |= (0x001) ; /*set pll index to 1 i.e 25G */ 1665 }else{ 1666 mst_cfg0_val &= ~(0x001); /*set pll index to 0 for 10G */ 1667 } 1668 if (!aux_mode->alternate) { 1669 mindex0 = MADURA_MIDX_10GPT_0 ; 1670 } else { 1671 mindex0 = MADURA_MIDX_10GPT_0A; 1672 } 1673 } 1674 if ((pa->access.lane_mask & 0x2) || (pa->access.lane_mask & 0x20)) { 1675 mst_cfg0_val &= ~(0x200) ; /*cleare 1G */ 1676 if(config->data_rate == MADURA_SPD_25G ){ 1677 mst_cfg0_val |= (0x002) ; /*set pll index to 1 i.e 25G */ 1678 } else { 1679 mst_cfg0_val &= ~(0x002); /*set pll index to 0 for 10G */ 1680 } 1681 if (!aux_mode->alternate) { 1682 mindex1 = MADURA_MIDX_10GPT_1 ; 1683 } else { 1684 mindex1 = MADURA_MIDX_10GPT_1A; 1685 } 1686 } 1687 } 1688 if (config->data_rate == MADURA_SPD_11G) { 1689 if ((pa->access.lane_mask & 0x1) || (pa->access.lane_mask & 0x10)) { 1690 if (!aux_mode->alternate) { 1691 mindex0 = MADURA_MIDX_10HGPT_0 ; 1692 } else { 1693 mindex0 = MADURA_MIDX_10HGPT_0A; 1694 } 1695 } 1696 if ((pa->access.lane_mask & 0x2) || (pa->access.lane_mask & 0x20)) { 1697 if (!aux_mode->alternate) { 1698 mindex1 = MADURA_MIDX_10HGPT_1 ; 1699 } else { 1700 mindex1 = MADURA_MIDX_10HGPT_1A; 1701 } 1702 } 1703 } 1704 } else { 1705 if (config->data_rate == MADURA_SPD_40G) { 1706 if (!aux_mode->alternate) { 1707 if (aux_mode->pass_thru_dual_lane) { 1708 mindex2 = MADURA_MIDX_40GPT20_1; 1709 mindex3=0; 1710 } else if (aux_mode->pass_thru) { 1711 mindex2 = MADURA_MIDX_40GPT10_0 ; 1712 } else { 1713 mindex2 = MADURA_MIDX_40GDM_1B ; 1714 mindex3=0; 1715 } 1716 } else { 1717 if (aux_mode->pass_thru_dual_lane) { 1718 mindex2 = MADURA_MIDX_40GPT20_1A; 1719 mindex3=0; 1720 } else if (aux_mode->pass_thru) { 1721 mindex2 = MADURA_MIDX_40GPT10_0A; 1722 } else { 1723 mindex2 = MADURA_MIDX_40GDM_1B ; 1724 mindex3=0; 1725 } 1726 } 1727 } 1728 if (config->data_rate == MADURA_SPD_42G) { 1729 if (!aux_mode->alternate) { 1730 if (aux_mode->pass_thru_dual_lane) { 1731 mindex2 = MADURA_MIDX_40HGPT20_1; 1732 mindex3=0; 1733 } else if (aux_mode->pass_thru) { 1734 mindex2 = MADURA_MIDX_40HGPT10_0 ; 1735 } else { 1736 mindex2 = MADURA_MIDX_40HGDM_1B ; 1737 mindex3=0; 1738 } 1739 } else { 1740 if (aux_mode->pass_thru_dual_lane) { 1741 mindex2 = MADURA_MIDX_40HGPT20_1A; 1742 mindex3=0; 1743 } else if (aux_mode->pass_thru) { 1744 mindex2 = MADURA_MIDX_40HGPT10_0A; 1745 } else { 1746 mindex2 = MADURA_MIDX_40HGDM_1B ; 1747 mindex3=0; 1748 } 1749 } 1750 } 1751 if (config->data_rate == MADURA_SPD_50G) { 1752 if (!aux_mode->alternate) { 1753 if (aux_mode->pass_thru_dual_lane) { 1754 mindex2 = MADURA_MIDX_40GPT20_1; 1755 mindex3=0; 1756 } 1757 } else { 1758 if (aux_mode->pass_thru_dual_lane) { 1759 mindex2 = MADURA_MIDX_40GPT20_1A; 1760 mindex3=0; 1761 } 1762 } 1763 } 1764 1765 if (config->data_rate == MADURA_SPD_25G || config->data_rate == MADURA_SPD_10G) { 1766 if ((pa->access.lane_mask & 0x4) || (pa->access.lane_mask & 0x40)) { 1767 mst_cfg0_val &= ~(0x400) ; /*cleare 1G */ 1768 if(config->data_rate == MADURA_SPD_25G ){ 1769 mst_cfg0_val |= (0x004) ; /*set pll index to 1 i.e 25G */ 1770 } else { 1771 mst_cfg0_val &= ~(0x004); /*set pll index to 0 for 10G */ 1772 } 1773 if (!aux_mode->alternate) { 1774 mindex2 = MADURA_MIDX_10GPT_2 ; 1775 } else { 1776 mindex2 = MADURA_MIDX_10GPT_2A; 1777 } 1778 } 1779 if ((pa->access.lane_mask & 0x8) || (pa->access.lane_mask & 0x80)) { 1780 mst_cfg0_val &= ~(0x800) ; /*cleare 1G */ 1781 if(config->data_rate == MADURA_SPD_25G ){ 1782 mst_cfg0_val |= (0x008) ; /*set pll index to 1 i.e 25G */ 1783 } else { 1784 mst_cfg0_val &= ~(0x008); /*set pll index to 0 for 10G */ 1785 } 1786 if (!aux_mode->alternate) { 1787 mindex3 = MADURA_MIDX_10GPT_3 ; 1788 } else { 1789 mindex3 = MADURA_MIDX_10GPT_3A; 1790 } 1791 } 1792 } 1793 if (config->data_rate == MADURA_SPD_11G) { 1794 if ((pa->access.lane_mask & 0x4) || (pa->access.lane_mask & 0x40)) { 1795 if (!aux_mode->alternate) { 1796 mindex2 = MADURA_MIDX_10HGPT_2 ; 1797 } else { 1798 mindex2 = MADURA_MIDX_10HGPT_2A; 1799 } 1800 } 1801 if ((pa->access.lane_mask & 0x8) || (pa->access.lane_mask & 0x80)) { 1802 if (!aux_mode->alternate) { 1803 mindex3 = MADURA_MIDX_10HGPT_3 ; 1804 } else { 1805 mindex3 = MADURA_MIDX_10HGPT_3A; 1806 } 1807 } 1808 } 1809 if ( cfg.data_rate == MADURA_SPD_1G ) { 1810 if ((pa->access.lane_mask & 0x4) || (pa->access.lane_mask & 0x40)) { 1811 mst_cfg0_val &= ~(0x0004); /* set Pll to 0 by clearing in case of flex from 25G*/ 1812 mst_cfg0_val |= 0x400 ; /*enable 1G with default pll as 132 with pll_index as 0*/ 1813 if (!aux_mode->alternate) { 1814 mindex2 = MADURA_MIDX_10GPT_2 ; 1815 } else { 1816 mindex2 = MADURA_MIDX_10GPT_2A; 1817 } 1818 } 1819 if ((pa->access.lane_mask & 0x8) || (pa->access.lane_mask & 0x80)) { 1820 mst_cfg0_val &= ~(0x0008); /* set Pll to 0 by clearing in case of flex from 25G*/ 1821 mst_cfg0_val |= 0x800 ; /*enable 1G with default pll as 132 with pll_index as 0*/ 1822 if (!aux_mode->alternate) { 1823 mindex3 = MADURA_MIDX_10GPT_3 ; 1824 } else { 1825 mindex3 = MADURA_MIDX_10GPT_3A; 1826 } 1827 } 1828 } 1829 } 1830 } 1831 } 1832 1833 if (mindex0 == 0xFF && mindex2 == 0xFF ) { 1834 if (config->data_rate == MADURA_SPD_100G) { 1835 if (!aux_mode->alternate) { 1836 mindex0 = MADURA_MIDX_100GPT_0; 1837 } else { 1838 mindex0 = MADURA_MIDX_100GPT_0A; 1839 } 1840 mindex1 = 0; 1841 } 1842 if (config->data_rate == MADURA_SPD_106G) { 1843 if (!aux_mode->alternate) { 1844 mindex0 = MADURA_MIDX_100HGPT_0; 1845 } else { 1846 mindex0 = MADURA_MIDX_100HGPT_0A; 1847 } 1848 mindex1 = 0; 1849 } 1850 } 1851 1852 PHYMOD_DEBUG_VERBOSE(("MODE CTRL0 :0x%x\n", mindex0)); 1853 PHYMOD_DEBUG_VERBOSE(("MODE CTRL1 :0x%x\n", mindex1)); 1854 PHYMOD_DEBUG_VERBOSE(("MODE CTRL2 :0x%x\n", mindex2)); 1855 PHYMOD_DEBUG_VERBOSE(("MODE CTRL3 :0x%x\n", mindex3)); 1856 1857 if (mindex0 != 0xFF) { 1858 BCMI_MADURA_P0_MODE_CTLr_P0_PVALIDf_SET(mode_ctrl0, 1); 1859 BCMI_MADURA_P0_MODE_CTLr_P0_MINDEXf_SET(mode_ctrl0, mindex0); 1860 PHYMOD_IF_ERR_RETURN( 1861 BCMI_MADURA_WRITE_P0_MODE_CTLr(&pa->access, mode_ctrl0)); 1862 } 1863 if (mindex1 != 0xFF) { 1864 if (config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_25G || 1865 config->data_rate == MADURA_SPD_11G || cfg.data_rate == MADURA_SPD_1G ) { 1866 BCMI_MADURA_P1_MODE_CTLr_P1_PVALIDf_SET(mode_ctrl1, 1); 1867 }else{ 1868 BCMI_MADURA_P1_MODE_CTLr_P1_PVALIDf_SET(mode_ctrl1, 0); 1869 } 1870 BCMI_MADURA_P1_MODE_CTLr_P1_MINDEXf_SET(mode_ctrl1, mindex1); 1871 PHYMOD_IF_ERR_RETURN( 1872 BCMI_MADURA_WRITE_P1_MODE_CTLr(&pa->access, mode_ctrl1)); 1873 } 1874 if (mindex2 != 0xFF) { 1875 BCMI_MADURA_P2_MODE_CTLr_P2_PVALIDf_SET(mode_ctrl2, 1); 1876 BCMI_MADURA_P2_MODE_CTLr_P2_MINDEXf_SET(mode_ctrl2, mindex2); 1877 PHYMOD_IF_ERR_RETURN( 1878 BCMI_MADURA_WRITE_P2_MODE_CTLr(&pa->access, mode_ctrl2)); 1879 } 1880 if (mindex3 != 0xFF) { 1881 if (config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_25G || 1882 config->data_rate == MADURA_SPD_11G|| cfg.data_rate == MADURA_SPD_1G ) { 1883 BCMI_MADURA_P3_MODE_CTLr_P3_PVALIDf_SET(mode_ctrl3, 1); 1884 }else{ 1885 BCMI_MADURA_P3_MODE_CTLr_P3_PVALIDf_SET(mode_ctrl3, 0); 1886 } 1887 BCMI_MADURA_P3_MODE_CTLr_P3_MINDEXf_SET(mode_ctrl3, mindex3); 1888 PHYMOD_IF_ERR_RETURN( 1889 BCMI_MADURA_WRITE_P3_MODE_CTLr(&pa->access, mode_ctrl3)); 1890 } 1891 1892 BCMI_MADURA_MST_CFG0r_SET(mst_cfg0,mst_cfg0_val); 1893 PHYMOD_IF_ERR_RETURN( 1894 BCMI_MADURA_WRITE_MST_CFG0r(&pa->access, mst_cfg0)); 1895 1896 return PHYMOD_E_NONE; 1897 } 1898 1899 /** Configure Dut Mode Register 1900 */ 1901 int _madura_udms_config(const phymod_phy_access_t *pa, const phymod_phy_inf_config_t* config, 1902 MADURA_AN_MODE mode) 1903 { 1904 BCMI_MADURA_P0_MODE_CTLr_t mode_ctrl0; 1905 BCMI_MADURA_P1_MODE_CTLr_t mode_ctrl1; 1906 BCMI_MADURA_P2_MODE_CTLr_t mode_ctrl2; 1907 BCMI_MADURA_P3_MODE_CTLr_t mode_ctrl3; 1908 unsigned char udmsen0 = 0xFF; 1909 unsigned char udmsen1 = 0xFF; 1910 unsigned char udmsen2 = 0xFF; 1911 unsigned char udmsen3 = 0xFF; 1912 unsigned char dmept0 = 0xFF; 1913 unsigned char dmept2 = 0xFF; 1914 1915 uint32_t alt_off = 0; 1916 uint16_t no_of_ports = 0, port_idx = 0; 1917 MADURA_DEVICE_AUX_MODE_T *aux_mode; 1918 const phymod_access_t *acc; 1919 phymod_phy_inf_config_t cfg; 1920 uint16_t core = 0; 1921 uint16_t is_lane_used = 0; 1922 1923 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 1924 PHYMOD_MEMSET(&mode_ctrl1, 0, sizeof(BCMI_MADURA_P1_MODE_CTLr_t)); 1925 PHYMOD_MEMSET(&mode_ctrl2, 0, sizeof(BCMI_MADURA_P2_MODE_CTLr_t)); 1926 PHYMOD_MEMSET(&mode_ctrl3, 0, sizeof(BCMI_MADURA_P3_MODE_CTLr_t)); 1927 PHYMOD_MEMCPY(&cfg, config, sizeof(phymod_phy_inf_config_t)); 1928 1929 acc = &pa->access; 1930 aux_mode = (MADURA_DEVICE_AUX_MODE_T*)config->device_aux_modes; 1931 1932 if ((core == MADURA_2X_FALCON_CORE) && aux_mode->alternate ) { 1933 alt_off = 4; 1934 } 1935 1936 MADURA_GET_PORT_FROM_MODE(config, no_of_ports, aux_mode); 1937 MADURA_GET_IP(acc, cfg, core); 1938 1939 PHYMOD_IF_ERR_RETURN( 1940 BCMI_MADURA_READ_P0_MODE_CTLr(&pa->access, &mode_ctrl0)); 1941 PHYMOD_IF_ERR_RETURN( 1942 BCMI_MADURA_READ_P1_MODE_CTLr(&pa->access, &mode_ctrl1)); 1943 PHYMOD_IF_ERR_RETURN( 1944 BCMI_MADURA_READ_P2_MODE_CTLr(&pa->access, &mode_ctrl2)); 1945 PHYMOD_IF_ERR_RETURN( 1946 BCMI_MADURA_READ_P3_MODE_CTLr(&pa->access, &mode_ctrl3)); 1947 1948 if (config->data_rate != MADURA_SPD_100G && 1949 config->data_rate != MADURA_SPD_106G) { 1950 for (port_idx=0; port_idx < no_of_ports; port_idx++) { 1951 if(config->data_rate == MADURA_SPD_10G ||config->data_rate == MADURA_SPD_25G || 1952 config->data_rate == MADURA_SPD_11G|| cfg.data_rate == MADURA_SPD_1G ) { 1953 /* coverity[identical_branches] */ 1954 if (core == MADURA_2X_FALCON_CORE) { 1955 if (pa->access.lane_mask & (1 << (port_idx + alt_off))) { 1956 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1957 } else { 1958 continue; 1959 } 1960 } else { 1961 if (pa->access.lane_mask & (1 << port_idx)) { 1962 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1963 } else { 1964 continue; 1965 } 1966 } 1967 } else if((config->data_rate == MADURA_SPD_40G ||config->data_rate == MADURA_SPD_50G || 1968 config->data_rate == MADURA_SPD_42G) && 1969 aux_mode->pass_thru_dual_lane) { 1970 /* coverity[identical_branches] */ 1971 if (core == MADURA_2X_FALCON_CORE) { 1972 if (pa->access.lane_mask & (0x3 << (alt_off + (port_idx * 2)))) { 1973 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1974 } else { 1975 continue; 1976 } 1977 } else { 1978 if (pa->access.lane_mask & (0x3 << (port_idx * 2))) { 1979 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1980 } else { 1981 continue; 1982 } 1983 } 1984 } else if((config->data_rate == MADURA_SPD_40G ||config->data_rate == MADURA_SPD_50G || 1985 config->data_rate == MADURA_SPD_42G) && 1986 (!aux_mode->pass_thru)) { 1987 if (core == MADURA_2X_FALCON_CORE) { 1988 /* MUX Mode*/ 1989 if (pa->access.lane_mask & (0xF << (port_idx*4))) { 1990 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1991 } else { 1992 continue; 1993 } 1994 } else { 1995 if (pa->access.lane_mask & (0x3 << (port_idx * 2))) { 1996 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 1997 } else { 1998 continue; 1999 } 2000 } 2001 } else { 2002 is_lane_used = madura_is_lane_mask_set(pa, port_idx, config); 2003 } 2004 if (!is_lane_used) { 2005 return PHYMOD_E_PARAM; 2006 } 2007 2008 /* Program Modes */ 2009 if (((config->data_rate == MADURA_SPD_40G || config->data_rate == MADURA_SPD_42G || config->data_rate == MADURA_SPD_50G) && (port_idx == 0)) || 2010 ((config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_11G || config->data_rate == MADURA_SPD_25G|| cfg.data_rate == MADURA_SPD_1G ) && (port_idx < 2))) { 2011 udmsen0 = (mode == MADURA_AN_NONE )? 1 : 0; 2012 if (config->data_rate == MADURA_SPD_40G || 2013 config->data_rate == MADURA_SPD_42G) { 2014 dmept0 = (mode == MADURA_AN_PROP) ? 1 : 0; 2015 } else if(config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_25G || 2016 config->data_rate == MADURA_SPD_11G|| cfg.data_rate == MADURA_SPD_1G ) { 2017 if ((pa->access.lane_mask & 0x1) || (pa->access.lane_mask & 0x10)) { 2018 dmept0 = (mode == MADURA_AN_PROP) ? 1 : 0; 2019 } else if ((pa->access.lane_mask & 0x2) || (pa->access.lane_mask & 0x20)) { 2020 udmsen1 = (mode == MADURA_AN_NONE) ? 1 : 0; 2021 dmept0 = (mode == MADURA_AN_PROP) ? 1 : 0; 2022 } 2023 } 2024 } else { 2025 udmsen2 = (mode == MADURA_AN_NONE ) ? 1 : 0; 2026 if (config->data_rate == MADURA_SPD_40G || 2027 config->data_rate == MADURA_SPD_42G) { 2028 dmept2 = (mode == MADURA_AN_PROP) ? 1 : 0; 2029 } else if(config->data_rate == MADURA_SPD_10G || config->data_rate == MADURA_SPD_25G || 2030 config->data_rate == MADURA_SPD_11G|| cfg.data_rate == MADURA_SPD_1G ) { 2031 if ((pa->access.lane_mask & 0x4) || (pa->access.lane_mask & 0x40)) { 2032 dmept2 = (mode == MADURA_AN_PROP) ? 1 : 0; 2033 } else if ((pa->access.lane_mask & 0x8) || (pa->access.lane_mask & 0x80)) { 2034 udmsen3 = (mode == MADURA_AN_NONE) ? 1 : 0; 2035 dmept2 = (mode == MADURA_AN_PROP) ? 1 : 0; 2036 } 2037 } 2038 } 2039 } 2040 } else { 2041 udmsen0 = (mode == MADURA_AN_NONE ) ? 1 : 0; 2042 } 2043 PHYMOD_DEBUG_VERBOSE(("MODE CTRL1 :0x%x\n", udmsen0)); 2044 2045 if (udmsen0 != 0xFF) { 2046 /*MADURA_STANDALONE */ 2047 BCMI_MADURA_P0_MODE_CTLr_P0_PVALIDf_SET(mode_ctrl0, 1); 2048 /*MADURA_STANDALONE */ 2049 BCMI_MADURA_P0_MODE_CTLr_P0_UDMSf_SET(mode_ctrl0, udmsen0); 2050 if (dmept0 != 0xFF) { 2051 BCMI_MADURA_P0_MODE_CTLr_P0_DPTf_SET(mode_ctrl0, dmept0); 2052 } 2053 PHYMOD_IF_ERR_RETURN( 2054 BCMI_MADURA_WRITE_P0_MODE_CTLr(&pa->access, mode_ctrl0)); 2055 } 2056 if (udmsen1 != 0xFF) { 2057 /*MADURA_STANDALONE */ 2058 BCMI_MADURA_P1_MODE_CTLr_P1_PVALIDf_SET(mode_ctrl1, 1); 2059 /*MADURA_STANDALONE */ 2060 BCMI_MADURA_P1_MODE_CTLr_P1_UDMSf_SET(mode_ctrl1, udmsen1); 2061 if (dmept0 != 0xFF) { 2062 BCMI_MADURA_P1_MODE_CTLr_P1_DPTf_SET(mode_ctrl1, dmept0); 2063 } 2064 PHYMOD_IF_ERR_RETURN( 2065 BCMI_MADURA_WRITE_P1_MODE_CTLr(&pa->access, mode_ctrl1)); 2066 } 2067 if (udmsen2 != 0xFF) { 2068 /*MADURA_STANDALONE */ 2069 BCMI_MADURA_P2_MODE_CTLr_P2_PVALIDf_SET(mode_ctrl2, 1); 2070 /*MADURA_STANDALONE */ 2071 BCMI_MADURA_P2_MODE_CTLr_P2_UDMSf_SET(mode_ctrl2, udmsen2); 2072 if (dmept2 != 0xFF) { 2073 BCMI_MADURA_P2_MODE_CTLr_P2_DPTf_SET(mode_ctrl2, dmept2); 2074 } 2075 PHYMOD_IF_ERR_RETURN( 2076 BCMI_MADURA_WRITE_P2_MODE_CTLr(&pa->access, mode_ctrl2)); 2077 } 2078 if (udmsen3 != 0xFF) { 2079 BCMI_MADURA_P3_MODE_CTLr_P3_PVALIDf_SET(mode_ctrl3, 1); 2080 BCMI_MADURA_P3_MODE_CTLr_P3_UDMSf_SET(mode_ctrl3, udmsen3); 2081 if (dmept2 != 0xFF) { 2082 BCMI_MADURA_P3_MODE_CTLr_P3_DPTf_SET(mode_ctrl3, dmept2); 2083 } 2084 PHYMOD_IF_ERR_RETURN( 2085 BCMI_MADURA_WRITE_P3_MODE_CTLr(&pa->access, mode_ctrl3)); 2086 } 2087 return PHYMOD_E_NONE; 2088 } 2089 2090 int _madura_interface_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config) 2091 { 2092 uint16_t DFE_option = SERDES_DFE_OPTION_NO_DFE; /*default to dfe disable*/ 2093 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 2094 uint16_t intf = config->interface_type; 2095 uint16_t config_reg=0; 2096 uint16_t lane_mask = pa->lane_mask; 2097 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2098 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2099 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2100 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2101 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2102 2103 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2104 2105 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2106 if ((config->data_rate != MADURA_SPD_40G && config->data_rate != MADURA_SPD_50G && 2107 config->data_rate != MADURA_SPD_42G) || 2108 aux_mode->pass_thru_dual_lane || 2109 aux_mode->pass_thru ) { 2110 2111 lane_mask >>= 4 ; 2112 } 2113 } 2114 2115 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2116 PHYMOD_IF_ERR_RETURN( 2117 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2118 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2119 } else if (lane_mask == 0x2) { 2120 PHYMOD_IF_ERR_RETURN( 2121 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2122 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2123 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2124 PHYMOD_IF_ERR_RETURN( 2125 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2126 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2127 } else { 2128 PHYMOD_IF_ERR_RETURN( 2129 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2130 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2131 } 2132 2133 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 2134 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 2135 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 2136 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 2137 2138 /*configure media_type and DFE option. SR/ER/LR, CR,KR, CAUI, XFI*/ 2139 if ( intf == phymodInterfaceER4 || intf == phymodInterfaceSR || 2140 intf == phymodInterfaceLR || intf == phymodInterfaceER || 2141 intf == phymodInterfaceSFI || intf == phymodInterfaceXLPPI) { 2142 if (config->interface_modes & PHYMOD_INTF_MODES_UNRELIABLE_LOS) { 2143 media_type = SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS; /*OPTICAL*/ 2144 } else { 2145 media_type = SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS; /*OPTICAL*/ 2146 } 2147 DFE_option = SERDES_DFE_OPTION_NO_DFE; 2148 } else if (intf == phymodInterfaceCR4 || intf == phymodInterfaceCR || intf == phymodInterfaceCR2){ 2149 media_type = SERDES_MEDIA_TYPE_COPPER_CABLE; /*Copper*/ 2150 DFE_option = SERDES_DFE_OPTION_DFE; 2151 } else if (intf == phymodInterfaceKR4 || intf == phymodInterfaceKR || intf == phymodInterfaceKR2){ 2152 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Back plane */ 2153 DFE_option = SERDES_DFE_OPTION_DFE; 2154 } else if (intf == phymodInterfaceCAUI4 || intf == phymodInterfaceVSR || 2155 intf == phymodInterfaceCAUI || intf == phymodInterfaceCAUI4_C2M || 2156 intf == phymodInterfaceCAUI4_C2C) { 2157 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Back plane */ 2158 DFE_option = SERDES_DFE_OPTION_DFE_LP_MODE; 2159 } else if (intf == phymodInterfaceXLAUI || intf == phymodInterfaceXFI|| intf == phymodInterfaceKX){ 2160 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Back plane */ 2161 DFE_option = SERDES_DFE_OPTION_NO_DFE; 2162 } else if (intf == phymodInterfaceSR2 || intf == phymodInterfaceLR2 || 2163 intf == phymodInterfaceSR4 || intf == phymodInterfaceLR4) { 2164 if (config->interface_modes & PHYMOD_INTF_MODES_UNRELIABLE_LOS) { 2165 media_type = SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS; /*OPTICAL*/ 2166 } else { 2167 media_type = SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS; /*OPTICAL*/ 2168 } 2169 DFE_option = SERDES_DFE_OPTION_NO_DFE; 2170 if (config->data_rate == MADURA_SPD_100G || 2171 config->data_rate == MADURA_SPD_106G) { 2172 DFE_option = SERDES_DFE_OPTION_DFE; 2173 } 2174 } else { 2175 PHYMOD_DEBUG_ERROR(("Invalid interface type as %d\n ... setting to default interface as KR\n",intf)); 2176 } 2177 2178 if (ip == MADURA_2X_FALCON_CORE) { 2179 config_reg = config_reg & (0xf0ff); 2180 /*considering sys+line side on the same interface*/ 2181 config_reg |= (( media_type)& 0x3) << 8 ; /*line*/ 2182 /*considering sys+line side on the same DFE settings*/ 2183 config_reg |= (( DFE_option ) & 0x3 ) << 10 ; /*lin*/ 2184 } else { 2185 config_reg = config_reg & (0xfff0); 2186 /*considering sys+line side on the same interface*/ 2187 config_reg |= ( media_type)& 0x3 ; /*sys*/ 2188 /*considering sys+line side on the same DFE settings*/ 2189 config_reg |= (( DFE_option ) & 0x3 ) << 2 ; /*sys */ 2190 } 2191 2192 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2193 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,(config_reg )); 2194 PHYMOD_IF_ERR_RETURN( 2195 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 2196 } else if (lane_mask == 0x2) { 2197 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,(config_reg )); 2198 PHYMOD_IF_ERR_RETURN( 2199 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 2200 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2201 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,(config_reg )); 2202 PHYMOD_IF_ERR_RETURN( 2203 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 2204 } else { 2205 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,(config_reg )); 2206 PHYMOD_IF_ERR_RETURN( 2207 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 2208 } 2209 2210 PHYMOD_IF_ERR_RETURN(_madura_set_ieee_intf(pa, config, intf)); 2211 2212 return PHYMOD_E_NONE; 2213 } 2214 2215 int _madura_interface_set_repeater_retimer_mode_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t Tx_timing_mode) 2216 { 2217 uint16_t config_reg=0; 2218 uint16_t lane_mask = pa->lane_mask; 2219 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2220 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2221 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2222 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2223 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2224 2225 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2226 2227 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2228 if ((config->data_rate != MADURA_SPD_40G && config->data_rate != MADURA_SPD_50G && 2229 config->data_rate != MADURA_SPD_42G) || 2230 aux_mode->pass_thru_dual_lane || 2231 aux_mode->pass_thru ) { 2232 2233 lane_mask >>= 4 ; 2234 } 2235 } 2236 2237 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2238 PHYMOD_IF_ERR_RETURN( 2239 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2240 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2241 } else if (lane_mask == 0x2) { 2242 PHYMOD_IF_ERR_RETURN( 2243 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2244 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2245 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2246 PHYMOD_IF_ERR_RETURN( 2247 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2248 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2249 } else { 2250 PHYMOD_IF_ERR_RETURN( 2251 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2252 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2253 } 2254 2255 if((config_reg & 0x6060 )== 0x6060 ){ 2256 PHYMOD_DEBUG_ERROR(("ULL+Rep already set so cant set Retimer/Repeater only modes. Disable ULL to set other modes\n")); 2257 return PHYMOD_E_NONE; 2258 } 2259 2260 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 2261 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 2262 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 2263 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 2264 2265 /*Tx timing mode */ 2266 config_reg &= ~(0x6060); 2267 config_reg |= ((Tx_timing_mode ) & 3) << 13 ; 2268 config_reg |= ((Tx_timing_mode ) & 3) << 5 ; /*mode sys*/ 2269 2270 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2271 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,config_reg); 2272 PHYMOD_IF_ERR_RETURN( 2273 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 2274 } else if (lane_mask == 0x2) { 2275 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,config_reg); 2276 PHYMOD_IF_ERR_RETURN( 2277 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 2278 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2279 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,config_reg); 2280 PHYMOD_IF_ERR_RETURN( 2281 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 2282 } else { 2283 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,config_reg); 2284 PHYMOD_IF_ERR_RETURN( 2285 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 2286 } 2287 return PHYMOD_E_NONE; 2288 } 2289 2290 2291 int _madura_interface_set_ull_mode_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t Tx_timing_mode) 2292 { 2293 uint16_t Tx_timing_mode_shift = 0; 2294 uint16_t lane_mask = pa->lane_mask; 2295 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2296 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2297 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2298 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2299 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2300 BCMI_MADURA_P0_MODE_CTLr_t mode_ctrl0; 2301 BCMI_MADURA_P1_MODE_CTLr_t mode_ctrl1; 2302 uint16_t config_reg0 = 0, config_reg1 = 0,config_reg2 = 0,config_reg3 = 0; 2303 2304 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 2305 PHYMOD_MEMSET(&mode_ctrl1, 0, sizeof(BCMI_MADURA_P1_MODE_CTLr_t)); 2306 2307 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2308 2309 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2310 if ((config->data_rate != MADURA_SPD_40G && 2311 config->data_rate != MADURA_SPD_42G) || 2312 aux_mode->pass_thru_dual_lane || 2313 aux_mode->pass_thru ) { 2314 lane_mask >>= 4 ; 2315 } 2316 } 2317 2318 Tx_timing_mode_shift = Tx_timing_mode_shift |((Tx_timing_mode ) & 3) << 13; /*Line side*/ 2319 Tx_timing_mode_shift = Tx_timing_mode_shift |((Tx_timing_mode ) & 3) << 5 ; /*sys side*/ 2320 2321 PHYMOD_IF_ERR_RETURN( 2322 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2323 config_reg0 = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2324 /* Update Tx timing mode */ 2325 config_reg0 &= ~(0x6060); 2326 config_reg0 |= Tx_timing_mode_shift ; 2327 PHYMOD_IF_ERR_RETURN( 2328 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2329 config_reg1 = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2330 /* Update Tx timing mode */ 2331 config_reg1 &= ~(0x6060); 2332 config_reg1 |= Tx_timing_mode_shift ; 2333 PHYMOD_IF_ERR_RETURN( 2334 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2335 config_reg2 = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2336 /* Update Tx timing mode */ 2337 config_reg2 &= ~(0x6060); 2338 config_reg2 |= Tx_timing_mode_shift ; 2339 PHYMOD_IF_ERR_RETURN( 2340 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2341 config_reg3 = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2342 /* Update Tx timing mode */ 2343 config_reg3 &= ~(0x6060); 2344 config_reg3 |= Tx_timing_mode_shift ; 2345 2346 /* 2347 * Workaround for firmware issue : 2348 * Leaving MISC registers at init value of zero does not work 2349 * with the current firmware 2350 */ 2351 2352 if (BCMI_MADURA_MST_MISC0r_GET(mst_misc0) == 0) { 2353 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,0x404); 2354 PHYMOD_IF_ERR_RETURN( 2355 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 2356 } 2357 if (BCMI_MADURA_MST_MISC1r_GET(mst_misc1) == 0) { 2358 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,0x404); 2359 PHYMOD_IF_ERR_RETURN( 2360 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 2361 } 2362 if (BCMI_MADURA_MST_MISC2r_GET(mst_misc2) == 0) { 2363 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,0x404); 2364 PHYMOD_IF_ERR_RETURN( 2365 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 2366 } 2367 if (BCMI_MADURA_MST_MISC3r_GET(mst_misc3) == 0) { 2368 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,0x404); 2369 PHYMOD_IF_ERR_RETURN( 2370 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 2371 } 2372 2373 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 2374 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 2375 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 2376 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 2377 2378 2379 /*write ULL on all misc registers in one go*/ 2380 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,config_reg0); 2381 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,config_reg1); 2382 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,config_reg2); 2383 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,config_reg3); 2384 PHYMOD_IF_ERR_RETURN( 2385 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 2386 PHYMOD_IF_ERR_RETURN( 2387 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 2388 PHYMOD_IF_ERR_RETURN( 2389 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 2390 PHYMOD_IF_ERR_RETURN( 2391 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 2392 return PHYMOD_E_NONE; 2393 } 2394 2395 int _madura_force_training_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t training_set) 2396 { 2397 uint16_t config_reg=0; 2398 uint16_t lane_mask = pa->lane_mask; 2399 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2400 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2401 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2402 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2403 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2404 2405 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2406 2407 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2408 if ((config->data_rate != MADURA_SPD_40G && 2409 config->data_rate != MADURA_SPD_42G) || 2410 aux_mode->pass_thru_dual_lane || 2411 aux_mode->pass_thru ) { 2412 2413 lane_mask >>= 4 ; 2414 } 2415 } 2416 2417 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2418 PHYMOD_IF_ERR_RETURN( 2419 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2420 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2421 } else if (lane_mask == 0x2) { 2422 PHYMOD_IF_ERR_RETURN( 2423 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2424 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2425 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2426 PHYMOD_IF_ERR_RETURN( 2427 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2428 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2429 } else { 2430 PHYMOD_IF_ERR_RETURN( 2431 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2432 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2433 } 2434 2435 if (ip == MADURA_2X_FALCON_CORE) { 2436 config_reg &= ~(0x1000); 2437 /* training_en*/ 2438 config_reg |= ((training_set ) & 1) << 12; 2439 } else { 2440 config_reg &= ~(0x0010); 2441 /* training_en*/ 2442 config_reg |= ((training_set ) & 1) << 4; /*enable sys*/ 2443 } 2444 2445 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2446 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,(config_reg )); 2447 PHYMOD_IF_ERR_RETURN( 2448 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 2449 } else if (lane_mask == 0x2) { 2450 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,(config_reg )); 2451 PHYMOD_IF_ERR_RETURN( 2452 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 2453 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2454 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,(config_reg )); 2455 PHYMOD_IF_ERR_RETURN( 2456 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 2457 } else { 2458 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,(config_reg )); 2459 PHYMOD_IF_ERR_RETURN( 2460 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 2461 } 2462 2463 return PHYMOD_E_NONE; 2464 } 2465 2466 int _madura_force_training_get(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t *training_get) 2467 { 2468 uint16_t config_reg=0; 2469 uint16_t lane_mask = pa->lane_mask; 2470 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2471 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2472 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2473 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2474 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2475 2476 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2477 2478 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2479 if ((config->data_rate != MADURA_SPD_40G && 2480 config->data_rate != MADURA_SPD_42G) || 2481 aux_mode->pass_thru_dual_lane || 2482 aux_mode->pass_thru ) { 2483 2484 lane_mask >>= 4 ; 2485 } 2486 } 2487 2488 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2489 PHYMOD_IF_ERR_RETURN( 2490 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2491 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2492 } else if (lane_mask == 0x2) { 2493 PHYMOD_IF_ERR_RETURN( 2494 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2495 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2496 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2497 PHYMOD_IF_ERR_RETURN( 2498 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2499 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2500 } else { 2501 PHYMOD_IF_ERR_RETURN( 2502 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2503 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2504 } 2505 2506 if (ip == MADURA_2X_FALCON_CORE) { 2507 *training_get = (config_reg & 0x1000) >> 12; 2508 } else { 2509 *training_get = (config_reg & 0x10) >> 4; 2510 } 2511 2512 return PHYMOD_E_NONE; 2513 } 2514 2515 int _madura_autoneg_set_val(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t AN_enable) 2516 { 2517 uint16_t config_reg=0; 2518 uint16_t lane_mask = pa->lane_mask; 2519 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2520 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2521 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2522 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2523 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2524 2525 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2526 2527 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2528 if ((config->data_rate != MADURA_SPD_40G && 2529 config->data_rate != MADURA_SPD_42G) || 2530 aux_mode->pass_thru_dual_lane || 2531 aux_mode->pass_thru ) { 2532 2533 lane_mask >>= 4 ; 2534 } 2535 } 2536 2537 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2538 PHYMOD_IF_ERR_RETURN( 2539 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2540 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2541 } else if (lane_mask == 0x2) { 2542 PHYMOD_IF_ERR_RETURN( 2543 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2544 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2545 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2546 PHYMOD_IF_ERR_RETURN( 2547 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2548 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2549 } else { 2550 PHYMOD_IF_ERR_RETURN( 2551 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2552 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2553 } 2554 2555 /*AN enable set on line*/ 2556 config_reg &= ~(0x8000); 2557 config_reg |= ((AN_enable ) & 1) << 15; 2558 2559 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2560 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,config_reg); 2561 PHYMOD_IF_ERR_RETURN( 2562 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 2563 } else if (lane_mask == 0x2) { 2564 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,config_reg); 2565 PHYMOD_IF_ERR_RETURN( 2566 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 2567 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2568 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,config_reg); 2569 PHYMOD_IF_ERR_RETURN( 2570 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 2571 } else { 2572 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,config_reg); 2573 PHYMOD_IF_ERR_RETURN( 2574 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 2575 } 2576 return PHYMOD_E_NONE; 2577 } 2578 2579 int _madura_autoneg_get_val(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, uint16_t *AN_get_val) 2580 { 2581 uint16_t config_reg=0; 2582 uint16_t lane_mask = pa->lane_mask; 2583 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2584 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2585 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2586 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2587 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2588 2589 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2590 2591 2592 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2593 if ((config->data_rate != MADURA_SPD_40G && 2594 config->data_rate != MADURA_SPD_42G) || 2595 aux_mode->pass_thru_dual_lane || 2596 aux_mode->pass_thru ) { 2597 2598 lane_mask >>= 4 ; 2599 } 2600 } 2601 2602 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2603 PHYMOD_IF_ERR_RETURN( 2604 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2605 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2606 } else if (lane_mask == 0x2) { 2607 PHYMOD_IF_ERR_RETURN( 2608 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2609 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2610 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2611 PHYMOD_IF_ERR_RETURN( 2612 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2613 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2614 } else { 2615 PHYMOD_IF_ERR_RETURN( 2616 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2617 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2618 } 2619 2620 /*AN enable get on line*/ 2621 *AN_get_val = (config_reg & 0x8000) >> 15; 2622 2623 return PHYMOD_E_NONE; 2624 } 2625 2626 2627 int _madura_pll_config_state_get(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config, uint16_t *pll_cfg_state) 2628 { 2629 phymod_phy_inf_config_t cfg; 2630 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2631 uint16_t ip = 0, lane_mask = 0; 2632 uint16_t no_of_ports = 0; 2633 uint16_t fal_pll_lock = 0, fal_2x_pll_lock = 0; 2634 const phymod_access_t *pa = &phy->access; 2635 int rv = PHYMOD_E_NONE; 2636 BCMI_MADURA_SLICEr_t slice_reg; 2637 BCMI_MADURA_PMD_PLL_STSr_t pll_sts; 2638 uint16_t pll_sel=0; 2639 2640 /* If clock is zero (ie, First Time) */ 2641 { 2642 2643 BCMI_MADURA_CLK_SCALER_CTLr_t clk_ctrl; 2644 PHYMOD_MEMSET(&clk_ctrl, 0, sizeof(BCMI_MADURA_CLK_SCALER_CTLr_t)); 2645 2646 PHYMOD_IF_ERR_RETURN( 2647 BCMI_MADURA_READ_CLK_SCALER_CTLr(pa,&clk_ctrl)); 2648 2649 if (BCMI_MADURA_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_GET(clk_ctrl)==0x800) 2650 { 2651 *pll_cfg_state = 1; 2652 2653 return rv; 2654 } 2655 } 2656 2657 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 2658 2659 PHYMOD_MEMSET(&cfg, 0, sizeof(phymod_phy_inf_config_t)); 2660 cfg.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 2661 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) cfg.device_aux_modes; 2662 2663 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 2664 2665 2666 MADURA_IF_ERR_RETURN_FREE(cfg.device_aux_modes, ( 2667 _madura_phy_interface_config_get(pa, 0, &cfg))); 2668 2669 if(cfg.data_rate==MADURA_SPD_25G){ 2670 pll_sel=1; 2671 } 2672 2673 for (ip = MADURA_2X_FALCON_CORE; ip <= MADURA_FALCON_CORE; ip++) { 2674 MADURA_IF_ERR_RETURN_FREE(cfg.device_aux_modes, ( 2675 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, 2676 ((ip == MADURA_2X_FALCON_CORE) && (lane_mask & 0xF0)) ? 4 : 0 ,pll_sel))); 2677 2678 PHYMOD_MEMSET(&pll_sts, 0 , sizeof(BCMI_MADURA_PMD_PLL_STSr_t)); 2679 MADURA_IF_ERR_RETURN_FREE(cfg.device_aux_modes, ( 2680 BCMI_MADURA_READ_PMD_PLL_STSr(pa,&pll_sts ))); 2681 2682 if (ip == MADURA_FALCON_CORE) { 2683 fal_pll_lock=(pll_sel==0)?BCMI_MADURA_PMD_PLL_STSr_PMD_PLL0_LOCKf_GET(pll_sts):BCMI_MADURA_PMD_PLL_STSr_PMD_PLL1_LOCKf_GET(pll_sts); 2684 } else { 2685 fal_2x_pll_lock=(pll_sel==0)?BCMI_MADURA_PMD_PLL_STSr_PMD_PLL0_LOCKf_GET(pll_sts):BCMI_MADURA_PMD_PLL_STSr_PMD_PLL1_LOCKf_GET(pll_sts); 2686 } 2687 } 2688 /* 2689 * PLL div is per die and will be programed only when 2690 * 1. if there is no pll lock on falcon 2691 * 2. speed change b/w 100G to 40G/20G/10G 2692 * 3. if ref clock freq changes(pll lock lost) 2693 * 4. On interface_modes changes(IEEE/OTN/HIGIG) 2694 */ 2695 MADURA_GET_PORT_FROM_MODE(config, no_of_ports, aux_mode); 2696 2697 if (((fal_pll_lock != 1) || (fal_2x_pll_lock != 1)) || (config->ref_clock != cfg.ref_clock) || 2698 (config->interface_modes != cfg.interface_modes) || ((no_of_ports == 1) && 2699 (config->data_rate != cfg.data_rate))) { 2700 *pll_cfg_state = 1; 2701 }else if(config->data_rate != cfg.data_rate){ /*1G can use either PLL 132x or 165x */ 2702 if(((config->data_rate == MADURA_SPD_25G) && ((cfg.data_rate==MADURA_SPD_10G) || (cfg.data_rate==MADURA_SPD_11G)))|| 2703 (((config->data_rate == MADURA_SPD_50G) ) && (cfg.data_rate==MADURA_SPD_10G))||/*stand alone default speed is 10G*/ 2704 (((config->data_rate == MADURA_SPD_10G) || (config->data_rate == MADURA_SPD_11G)) && (cfg.data_rate==MADURA_SPD_25G))|| 2705 ((config->data_rate == MADURA_SPD_50G) && (cfg.data_rate==MADURA_SPD_40G || cfg.data_rate==MADURA_SPD_42G))|| 2706 ((config->data_rate == MADURA_SPD_40G || config->data_rate == MADURA_SPD_42G) && (cfg.data_rate==MADURA_SPD_50G))|| 2707 (config->data_rate == MADURA_SPD_25G)){ 2708 *pll_cfg_state = 1; 2709 } 2710 } 2711 2712 PHYMOD_FREE(cfg.device_aux_modes); 2713 PHYMOD_IF_ERR_RETURN( 2714 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 2715 2716 return rv; 2717 } 2718 2719 int _madura_set_ieee_intf(const phymod_access_t *pa, const phymod_phy_inf_config_t *config, uint16_t intf) 2720 { 2721 uint16_t port = 0, physical_port = 0; 2722 uint16_t intf_side = 0; 2723 BCMI_MADURA_GPREG6r_t gpreg6; 2724 BCMI_MADURA_GPREG7r_t gpreg7; 2725 BCMI_MADURA_GPREG4r_t gpreg4; 2726 BCMI_MADURA_GPREG5r_t gpreg5; 2727 2728 PHYMOD_MEMSET(&gpreg6, 0, sizeof(BCMI_MADURA_GPREG6r_t)); 2729 PHYMOD_MEMSET(&gpreg7, 0, sizeof(BCMI_MADURA_GPREG7r_t)); 2730 PHYMOD_MEMSET(&gpreg4, 0, sizeof(BCMI_MADURA_GPREG4r_t)); 2731 PHYMOD_MEMSET(&gpreg5, 0, sizeof(BCMI_MADURA_GPREG5r_t)); 2732 2733 PHYMOD_IF_ERR_RETURN( 2734 _madura_port_from_lane_map_get(pa, config, &port, &physical_port)); 2735 2736 MADURA_GET_INTF_SIDE(pa, intf_side); 2737 2738 if (port == 0) { 2739 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG6r(pa, &gpreg6)); 2740 gpreg6.v[0] = intf_side ? (gpreg6.v[0] & 0xFF) : (gpreg6.v[0] & 0xFF00); 2741 gpreg6.v[0] |= intf_side ? (intf << 8) : (intf); 2742 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_WRITE_GPREG6r(pa, gpreg6)); 2743 } else if (port == 1) { 2744 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG7r(pa, &gpreg7)); 2745 gpreg7.v[0] = intf_side ? (gpreg7.v[0] & 0xFF) : (gpreg7.v[0] & 0xFF00); 2746 gpreg7.v[0] |= intf_side ? (intf << 8) : (intf); 2747 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_WRITE_GPREG7r(pa, gpreg7)); 2748 } else if (port == 2) { 2749 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG4r(pa, &gpreg4)); 2750 gpreg4.v[0] = intf_side ? (gpreg4.v[0] & 0xFF) : (gpreg4.v[0] & 0xFF00); 2751 gpreg4.v[0] |= intf_side ? (intf << 8) : (intf); 2752 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_WRITE_GPREG4r(pa, gpreg4)); 2753 } else { 2754 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG5r(pa, &gpreg5)); 2755 gpreg5.v[0] = intf_side ? (gpreg5.v[0] & 0xFF) : (gpreg5.v[0] & 0xFF00); 2756 gpreg5.v[0] |= intf_side ? (intf << 8) : (intf); 2757 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_WRITE_GPREG5r(pa, gpreg5)); 2758 } 2759 2760 return PHYMOD_E_NONE; 2761 } 2762 2763 int _madura_get_ieee_intf(const phymod_access_t *pa, const phymod_phy_inf_config_t *config, uint16_t *intf) 2764 { 2765 uint16_t port = 0, physical_port = 0; 2766 uint16_t intf_side = 0; 2767 BCMI_MADURA_GPREG6r_t gpreg6; 2768 BCMI_MADURA_GPREG7r_t gpreg7; 2769 BCMI_MADURA_GPREG4r_t gpreg4; 2770 BCMI_MADURA_GPREG5r_t gpreg5; 2771 2772 PHYMOD_MEMSET(&gpreg6, 0, sizeof(BCMI_MADURA_GPREG6r_t)); 2773 PHYMOD_MEMSET(&gpreg7, 0, sizeof(BCMI_MADURA_GPREG7r_t)); 2774 PHYMOD_MEMSET(&gpreg4, 0, sizeof(BCMI_MADURA_GPREG4r_t)); 2775 PHYMOD_MEMSET(&gpreg5, 0, sizeof(BCMI_MADURA_GPREG5r_t)); 2776 2777 PHYMOD_IF_ERR_RETURN( 2778 _madura_port_from_lane_map_get(pa, config, &port, &physical_port)); 2779 2780 MADURA_GET_INTF_SIDE(pa, intf_side); 2781 if (port == 0) { 2782 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG6r(pa, &gpreg6)); 2783 *intf = intf_side ? ((gpreg6.v[0] >> 8) & 0xFF) : (gpreg6.v[0] & 0x00FF); 2784 } else if (port == 1) { 2785 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG7r(pa, &gpreg7)); 2786 *intf = intf_side ? ((gpreg7.v[0] >> 8) & 0xFF) : (gpreg7.v[0] & 0x00FF); 2787 } else if (port == 2) { 2788 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG4r(pa, &gpreg4)); 2789 *intf = intf_side ? ((gpreg4.v[0] >> 8) & 0xFF) : (gpreg4.v[0] & 0x00FF); 2790 } else { 2791 PHYMOD_IF_ERR_RETURN(BCMI_MADURA_READ_GPREG5r(pa, &gpreg5)); 2792 *intf = intf_side ? ((gpreg5.v[0] >> 8) & 0xFF) : (gpreg5.v[0] & 0x00FF); 2793 } 2794 2795 return PHYMOD_E_NONE; 2796 } 2797 2798 int _madura_get_media_type(const phymod_access_t *pa, const phymod_phy_inf_config_t *config, uint16_t *media_type) 2799 { 2800 BCMI_MADURA_MST_MISC0r_t mst_misc0; 2801 BCMI_MADURA_MST_MISC1r_t mst_misc1; 2802 BCMI_MADURA_MST_MISC2r_t mst_misc2; 2803 BCMI_MADURA_MST_MISC3r_t mst_misc3; 2804 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2805 uint16_t config_reg = 0; 2806 uint16_t ip = 0; 2807 uint16_t lane_mask = pa->lane_mask; 2808 phymod_phy_inf_config_t cfg; 2809 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 2810 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 2811 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 2812 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 2813 PHYMOD_MEMCPY(&cfg, config, sizeof(phymod_phy_inf_config_t)); 2814 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2815 2816 MADURA_GET_IP(pa, cfg, ip); 2817 2818 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 2819 if ((config->data_rate != MADURA_SPD_40G && config->data_rate != MADURA_SPD_50G && 2820 config->data_rate != MADURA_SPD_42G) || 2821 aux_mode->pass_thru_dual_lane || 2822 aux_mode->pass_thru ) { 2823 2824 lane_mask >>= 4 ; 2825 } 2826 } 2827 2828 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 2829 PHYMOD_IF_ERR_RETURN( 2830 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 2831 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 2832 } else if (lane_mask == 0x2) { 2833 PHYMOD_IF_ERR_RETURN( 2834 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 2835 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 2836 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 2837 PHYMOD_IF_ERR_RETURN( 2838 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 2839 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 2840 } else { 2841 PHYMOD_IF_ERR_RETURN( 2842 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 2843 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 2844 } 2845 2846 if (ip == MADURA_2X_FALCON_CORE) { /*LINE SIDE*/ 2847 *media_type = (((config_reg & 0xffff) >> 8) & 0x3); 2848 } else { /*SYS SIDE*/ 2849 *media_type = ((config_reg & 0xffff) & 0x3); 2850 } 2851 2852 return PHYMOD_E_NONE; 2853 } 2854 2855 int _madura_phy_interface_config_set(const phymod_phy_access_t* pa, uint32_t flags, const phymod_phy_inf_config_t* config) 2856 { 2857 uint16_t pll_cfg_state = 0; 2858 phymod_phy_inf_config_t cfg; 2859 phymod_phy_inf_config_t cpy_config; 2860 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2861 uint32_t chip_id = 0; 2862 uint32_t rev = 0; 2863 uint16_t ip = 0; 2864 uint8_t clear_flag = 0; 2865 2866 PHYMOD_IF_ERR_RETURN( 2867 _madura_pll_config_state_get(pa, config, &pll_cfg_state)); 2868 2869 PHYMOD_MEMCPY(&cpy_config, config, sizeof(phymod_phy_inf_config_t)); 2870 2871 if (cpy_config.device_aux_modes == NULL) { 2872 cpy_config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 2873 clear_flag = 1; 2874 PHYMOD_MEMSET(cpy_config.device_aux_modes, 0, sizeof(MADURA_DEVICE_AUX_MODE_T)); 2875 } 2876 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) cpy_config.device_aux_modes; 2877 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, 2878 (madura_get_chipid(&pa->access, &chip_id, &rev))); 2879 2880 if (aux_mode->pass_thru == 1 || aux_mode->pass_thru_dual_lane == 1) { 2881 aux_mode->passthru_sys_side_core = MADURA_FALCON_CORE ; 2882 } 2883 2884 PHYMOD_DEBUG_VERBOSE(("Configuring interface\n")); 2885 PHYMOD_MEMSET(&cfg, 0, sizeof(phymod_phy_inf_config_t)); 2886 cfg.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 2887 2888 do { 2889 int loc_err ; 2890 2891 loc_err = _madura_phy_interface_config_get(&pa->access, 0, &cfg); 2892 2893 MADURA_GET_IP((&pa->access), cfg, ip); 2894 2895 PHYMOD_FREE(cfg.device_aux_modes); 2896 2897 if (loc_err != PHYMOD_E_NONE) { 2898 if (clear_flag) { 2899 PHYMOD_FREE(cpy_config.device_aux_modes); 2900 } 2901 return loc_err ; 2902 } 2903 } while (0); 2904 2905 /* Configure Ref Clock*/ 2906 PHYMOD_DEBUG_VERBOSE(("Configuring REF clock %d\n",config->ref_clock)); 2907 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, ( 2908 _madura_configure_ref_clock(&pa->access, config->ref_clock))); 2909 2910 /* Configure DUT MODE */ 2911 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, ( 2912 _madura_config_dut_mode_reg(pa, &cpy_config))); 2913 2914 /* Enable UDMS for non-an MODE */ 2915 PHYMOD_DEBUG_VERBOSE(("Configuring UDMS\n")); 2916 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, ( 2917 _madura_udms_config(pa, &cpy_config, MADURA_AN_NONE))); 2918 2919 /* Configure PLL Divider*/ 2920 if (pll_cfg_state) { 2921 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, ( 2922 _madura_config_pll_div(&pa->access, cpy_config))); 2923 } 2924 2925 /* Configure Interface.*/ 2926 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, ( 2927 _madura_interface_set(&pa->access, ip, &cpy_config))); 2928 2929 /* Disable fec in speed other than 100G when prev speed is 100G */ 2930 if(cpy_config.data_rate!=MADURA_SPD_100G /*Cur speed*/ && cfg.data_rate==MADURA_SPD_100G/* Prev speed*/){ 2931 MADURA_IF_ERR_RETURN_FREE( (clear_flag) ? aux_mode : NULL, ( 2932 _madura_fec_enable_set(&pa->access, 0))); 2933 } 2934 2935 if (clear_flag) { 2936 PHYMOD_FREE(cpy_config.device_aux_modes); 2937 } 2938 2939 return PHYMOD_E_NONE; 2940 } 2941 2942 int _madura_phy_interface_config_get(const phymod_access_t *pa, uint32_t flags, phymod_phy_inf_config_t *config) 2943 { 2944 /*get datarate,passthru, gearbox, get refclock,get intf side*/ 2945 BCMI_MADURA_P0_MODE_CTLr_t mode_ctrl0; 2946 BCMI_MADURA_P1_MODE_CTLr_t mode_ctrl1; 2947 BCMI_MADURA_P2_MODE_CTLr_t mode_ctrl2; 2948 BCMI_MADURA_P3_MODE_CTLr_t mode_ctrl3; 2949 unsigned char mindex0 = 0xFF; 2950 unsigned char mindex1 = 0xFF; 2951 unsigned char mindex2 = 0xFF; 2952 unsigned char mindex3 = 0xFF; 2953 2954 BCMI_MADURA_CLK_SCALER_CTLr_t clk_ctrl; 2955 MADURA_DEVICE_AUX_MODE_T *aux_mode; 2956 uint16_t ip = 0, intf_side = 0; 2957 uint16_t clock_ratio = 0; 2958 uint16_t lane_mask = pa->lane_mask; 2959 uint16_t intf; 2960 uint16_t pll_1G_index; 2961 uint16_t media_type = 0; 2962 2963 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 2964 PHYMOD_MEMSET(&mode_ctrl2, 0, sizeof(BCMI_MADURA_P2_MODE_CTLr_t)); 2965 2966 PHYMOD_MEMSET(&clk_ctrl, 0, sizeof(BCMI_MADURA_CLK_SCALER_CTLr_t)); 2967 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 2968 if (aux_mode == NULL) { 2969 PHYMOD_DEBUG_VERBOSE(("AUX MODE MEM NOT ALLOC\n")); 2970 return PHYMOD_E_PARAM; 2971 } 2972 PHYMOD_MEMSET(aux_mode, 0, sizeof(MADURA_DEVICE_AUX_MODE_T)); 2973 2974 if (!lane_mask) { 2975 PHYMOD_DEBUG_ERROR(("Invalid Lanemap as %x. Setting to default lane map as 0xF\n",lane_mask)); 2976 lane_mask = 0xf; 2977 /* return PHYMOD_E_PARAM;*/ 2978 } 2979 2980 PHYMOD_IF_ERR_RETURN( 2981 BCMI_MADURA_READ_P0_MODE_CTLr(pa , &mode_ctrl0)); 2982 mindex0 = BCMI_MADURA_P0_MODE_CTLr_P0_MINDEXf_GET(mode_ctrl0); 2983 2984 PHYMOD_IF_ERR_RETURN( 2985 BCMI_MADURA_READ_P1_MODE_CTLr(pa , &mode_ctrl1)); 2986 mindex1 = BCMI_MADURA_P1_MODE_CTLr_P1_MINDEXf_GET(mode_ctrl1); 2987 2988 PHYMOD_IF_ERR_RETURN( 2989 BCMI_MADURA_READ_P2_MODE_CTLr(pa , &mode_ctrl2)); 2990 mindex2 = BCMI_MADURA_P2_MODE_CTLr_P2_MINDEXf_GET(mode_ctrl2); 2991 2992 PHYMOD_IF_ERR_RETURN( 2993 BCMI_MADURA_READ_P3_MODE_CTLr(pa , &mode_ctrl3)); 2994 mindex3 = BCMI_MADURA_P3_MODE_CTLr_P3_MINDEXf_GET(mode_ctrl3); 2995 2996 PHYMOD_DEBUG_VERBOSE(("MODE STS:%x\n", mindex0)); 2997 2998 MADURA_GET_INTF_SIDE(pa, intf_side); 2999 3000 if (intf_side == MADURA_IF_LINE) { 3001 ip = MADURA_2X_FALCON_CORE; 3002 } else { 3003 ip = MADURA_FALCON_CORE; 3004 } 3005 aux_mode->alternate = 0; 3006 if (ip == MADURA_FALCON_CORE) { 3007 if (MADURA_MIDX_IS_4X25G_PLUS(mindex0)) { 3008 config->data_rate = MADURA_SPD_100G; 3009 switch(mindex0) { 3010 case MADURA_MIDX_100HGPT_0A: 3011 aux_mode->alternate = 1; 3012 /* coverity[fallthrough] */ 3013 case MADURA_MIDX_100HGPT_0: 3014 config->data_rate = MADURA_SPD_106G; 3015 break; 3016 case MADURA_MIDX_100GPT_0A: 3017 aux_mode->alternate = 1; 3018 break; 3019 } 3020 aux_mode->pass_thru = 1; 3021 } else if (lane_mask == 0x2) { 3022 switch(mindex1) { 3023 case MADURA_MIDX_10HGPT_1A: 3024 aux_mode->alternate = 1; 3025 /* coverity[fallthrough] */ 3026 case MADURA_MIDX_10HGPT_1: 3027 config->data_rate = MADURA_SPD_11G; 3028 aux_mode->pass_thru = 1; 3029 break; 3030 case MADURA_MIDX_10GPT_1A: 3031 aux_mode->alternate = 1; 3032 /* coverity[fallthrough] */ 3033 case MADURA_MIDX_10GPT_1: 3034 if(read_1G_mode_status(pa,mindex1,&pll_1G_index)){ 3035 config->data_rate = MADURA_SPD_1G; 3036 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,1, mindex1 )){ 3037 config->data_rate = MADURA_SPD_25G; 3038 }else{ 3039 config->data_rate = MADURA_SPD_10G; 3040 } 3041 aux_mode->pass_thru = 1; 3042 break; 3043 } 3044 } else if (lane_mask & 0x3) { 3045 switch(mindex0) { 3046 case MADURA_MIDX_40HGPT10_0A: 3047 aux_mode->alternate = 1; 3048 /* coverity[fallthrough] */ 3049 case MADURA_MIDX_40HGPT10_0: 3050 config->data_rate = MADURA_SPD_42G; 3051 aux_mode->pass_thru = 1; 3052 break; 3053 case MADURA_MIDX_40GPT10_0A: 3054 aux_mode->alternate = 1; 3055 /* coverity[fallthrough] */ 3056 case MADURA_MIDX_40GPT10_0: 3057 config->data_rate = MADURA_SPD_40G; 3058 aux_mode->pass_thru = 1; 3059 break; 3060 3061 case MADURA_MIDX_40GDM_0: 3062 case MADURA_MIDX_40GDM_1: 3063 case MADURA_MIDX_40GDM_0B: 3064 case MADURA_MIDX_40GDM_1B: 3065 config->data_rate = MADURA_SPD_40G; 3066 aux_mode->pass_thru = 0; 3067 break; 3068 case MADURA_MIDX_40HGDM_0: 3069 case MADURA_MIDX_40HGDM_1: 3070 case MADURA_MIDX_40HGDM_0B: 3071 case MADURA_MIDX_40HGDM_1B: 3072 config->data_rate = MADURA_SPD_42G; 3073 aux_mode->pass_thru = 0; 3074 break; 3075 3076 case MADURA_MIDX_40HGPT20_0A: 3077 aux_mode->alternate = 1; 3078 /* coverity[fallthrough] */ 3079 case MADURA_MIDX_40HGPT20_0: 3080 config->data_rate = MADURA_SPD_42G; 3081 aux_mode->pass_thru_dual_lane = 1; 3082 break; 3083 case MADURA_MIDX_40GPT20_0A: 3084 aux_mode->alternate = 1; 3085 /* coverity[fallthrough] */ 3086 case MADURA_MIDX_40GPT20_0: 3087 if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,0, mindex0 )){ 3088 config->data_rate = MADURA_SPD_50G; 3089 }else{ 3090 config->data_rate = MADURA_SPD_40G; 3091 } 3092 aux_mode->pass_thru_dual_lane = 1; 3093 break; 3094 3095 case MADURA_MIDX_10HGPT_0A: 3096 aux_mode->alternate = 1; 3097 /* coverity[fallthrough] */ 3098 case MADURA_MIDX_10HGPT_0: 3099 config->data_rate = MADURA_SPD_11G; 3100 aux_mode->pass_thru = 1; 3101 break; 3102 case MADURA_MIDX_10GPT_0A: 3103 aux_mode->alternate = 1; 3104 /* coverity[fallthrough] */ 3105 case MADURA_MIDX_10GPT_0: 3106 if(read_1G_mode_status(pa,mindex0,&pll_1G_index)){ 3107 config->data_rate = MADURA_SPD_1G; 3108 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,0, mindex0)){ 3109 config->data_rate = MADURA_SPD_25G; 3110 }else{ 3111 config->data_rate = MADURA_SPD_10G; 3112 } 3113 aux_mode->pass_thru = 1; 3114 break; 3115 } 3116 3117 3118 } else if (lane_mask == 0x8) { 3119 switch(mindex3) { 3120 case MADURA_MIDX_10HGPT_3A: 3121 aux_mode->alternate = 1; 3122 /* coverity[fallthrough] */ 3123 case MADURA_MIDX_10HGPT_3: 3124 config->data_rate = MADURA_SPD_11G; 3125 aux_mode->pass_thru = 1; 3126 break; 3127 case MADURA_MIDX_10GPT_3A: 3128 aux_mode->alternate = 1; 3129 /* coverity[fallthrough] */ 3130 case MADURA_MIDX_10GPT_3: 3131 if(read_1G_mode_status(pa,mindex3,&pll_1G_index)){ 3132 config->data_rate = MADURA_SPD_1G; 3133 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,3, mindex3 )){ 3134 config->data_rate = MADURA_SPD_25G; 3135 }else{ 3136 config->data_rate = MADURA_SPD_10G; 3137 } 3138 aux_mode->pass_thru = 1; 3139 break; 3140 } 3141 } else if (lane_mask & 0xc) { 3142 switch(mindex2) { 3143 case MADURA_MIDX_40GPT10_0: 3144 case MADURA_MIDX_40GPT10_0A: 3145 case MADURA_MIDX_40GPT10_1: 3146 case MADURA_MIDX_40GPT10_1A: 3147 case MADURA_MIDX_40HGPT10_0: 3148 case MADURA_MIDX_40HGPT10_0A: 3149 case MADURA_MIDX_40HGPT10_1: 3150 case MADURA_MIDX_40HGPT10_1A: 3151 config->data_rate = MADURA_SPD_40G; 3152 aux_mode->pass_thru = 1; 3153 break; 3154 3155 case MADURA_MIDX_40GDM_0: 3156 case MADURA_MIDX_40GDM_1: 3157 case MADURA_MIDX_40GDM_0B: 3158 case MADURA_MIDX_40GDM_1B: 3159 config->data_rate = MADURA_SPD_40G; 3160 aux_mode->pass_thru = 0; 3161 break; 3162 case MADURA_MIDX_40HGDM_0: 3163 case MADURA_MIDX_40HGDM_1: 3164 case MADURA_MIDX_40HGDM_0B: 3165 case MADURA_MIDX_40HGDM_1B: 3166 config->data_rate = MADURA_SPD_42G; 3167 aux_mode->pass_thru = 0; 3168 break; 3169 3170 case MADURA_MIDX_40HGPT20_1A: 3171 aux_mode->alternate = 1; 3172 /* coverity[fallthrough] */ 3173 case MADURA_MIDX_40HGPT20_1: 3174 config->data_rate = MADURA_SPD_42G; 3175 aux_mode->pass_thru_dual_lane = 1; 3176 break; 3177 case MADURA_MIDX_40GPT20_1A: 3178 aux_mode->alternate = 1; 3179 /* coverity[fallthrough] */ 3180 case MADURA_MIDX_40GPT20_1: 3181 if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,2,mindex2 )){ 3182 config->data_rate = MADURA_SPD_50G; 3183 }else{ 3184 config->data_rate = MADURA_SPD_40G; 3185 } 3186 aux_mode->pass_thru_dual_lane = 1; 3187 break; 3188 3189 case MADURA_MIDX_10HGPT_2A: 3190 aux_mode->alternate = 1; 3191 /* coverity[fallthrough] */ 3192 case MADURA_MIDX_10HGPT_2: 3193 config->data_rate = MADURA_SPD_11G; 3194 aux_mode->pass_thru = 1; 3195 break; 3196 case MADURA_MIDX_10GPT_2A: 3197 aux_mode->alternate = 1; 3198 /* coverity[fallthrough] */ 3199 case MADURA_MIDX_10GPT_2: 3200 if(read_1G_mode_status(pa,mindex2,&pll_1G_index)){ 3201 config->data_rate = MADURA_SPD_1G; 3202 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,2, mindex2)){ 3203 config->data_rate = MADURA_SPD_25G; 3204 }else{ 3205 config->data_rate = MADURA_SPD_10G; 3206 } 3207 aux_mode->pass_thru = 1; 3208 break; 3209 } 3210 3211 } 3212 if (aux_mode->pass_thru == 1 || aux_mode->pass_thru_dual_lane == 1) { 3213 aux_mode->passthru_sys_side_core = MADURA_FALCON_CORE ; 3214 aux_mode->pass_thru = 1 ; 3215 } 3216 } else { /* ip = MADURA_2X_FALCON_CORE */ 3217 if (MADURA_MIDX_IS_4X25G_PLUS(mindex0)) { 3218 config->data_rate = MADURA_SPD_100G; 3219 switch(mindex0) { 3220 case MADURA_MIDX_100HGPT_0A: 3221 aux_mode->alternate = 1; 3222 /* coverity[fallthrough] */ 3223 case MADURA_MIDX_100HGPT_0: 3224 config->data_rate = MADURA_SPD_106G; 3225 break; 3226 case MADURA_MIDX_100GPT_0A: 3227 aux_mode->alternate = 1; 3228 break; 3229 } 3230 aux_mode->pass_thru = 1; 3231 } else if (lane_mask == 0x2) { 3232 switch(mindex1) { 3233 case MADURA_MIDX_10HGPT_1A: 3234 aux_mode->alternate = 1; 3235 /* coverity[fallthrough] */ 3236 case MADURA_MIDX_10HGPT_1: 3237 config->data_rate = MADURA_SPD_11G; 3238 aux_mode->pass_thru = 1; 3239 break; 3240 case MADURA_MIDX_10GPT_1A: 3241 aux_mode->alternate = 1; 3242 /* coverity[fallthrough] */ 3243 case MADURA_MIDX_10GPT_1: 3244 if(read_1G_mode_status(pa,mindex1,&pll_1G_index)){ 3245 config->data_rate = MADURA_SPD_1G; 3246 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex1==MADURA_MIDX_10GPT_1A )?5:1, mindex1)){ 3247 config->data_rate = MADURA_SPD_25G; 3248 }else{ 3249 config->data_rate = MADURA_SPD_10G; 3250 } 3251 aux_mode->pass_thru = 1; 3252 break; 3253 } 3254 } else if (lane_mask & 0x3) { 3255 switch(mindex0) { 3256 case MADURA_MIDX_40HGPT10_0A: 3257 aux_mode->alternate = 1; 3258 /* coverity[fallthrough] */ 3259 case MADURA_MIDX_40HGPT10_0: 3260 config->data_rate = MADURA_SPD_42G; 3261 aux_mode->pass_thru = 1; 3262 break; 3263 case MADURA_MIDX_40GPT10_0A: 3264 aux_mode->alternate = 1; 3265 /* coverity[fallthrough] */ 3266 case MADURA_MIDX_40GPT10_0: 3267 config->data_rate = MADURA_SPD_40G; 3268 aux_mode->pass_thru = 1; 3269 break; 3270 3271 case MADURA_MIDX_40GDM_0: 3272 case MADURA_MIDX_40GDM_1: 3273 case MADURA_MIDX_40GDM_0B: 3274 case MADURA_MIDX_40GDM_1B: 3275 config->data_rate = MADURA_SPD_40G; 3276 aux_mode->pass_thru = 0; 3277 break; 3278 case MADURA_MIDX_40HGDM_0: 3279 case MADURA_MIDX_40HGDM_1: 3280 case MADURA_MIDX_40HGDM_0B: 3281 case MADURA_MIDX_40HGDM_1B: 3282 config->data_rate = MADURA_SPD_42G; 3283 aux_mode->pass_thru = 0; 3284 break; 3285 3286 case MADURA_MIDX_40HGPT20_0A: 3287 aux_mode->alternate = 1; 3288 /* coverity[fallthrough] */ 3289 case MADURA_MIDX_40HGPT20_0: 3290 config->data_rate = MADURA_SPD_42G; 3291 aux_mode->pass_thru_dual_lane = 1; 3292 break; 3293 case MADURA_MIDX_40GPT20_0A: 3294 aux_mode->alternate = 1; 3295 /* coverity[fallthrough] */ 3296 case MADURA_MIDX_40GPT20_0: 3297 if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,(mindex0==MADURA_MIDX_40GPT20_0A)? 4:0, mindex0)){ 3298 config->data_rate = MADURA_SPD_50G; 3299 }else{ 3300 config->data_rate = MADURA_SPD_40G; 3301 } 3302 aux_mode->pass_thru_dual_lane = 1; 3303 break; 3304 3305 case MADURA_MIDX_10HGPT_0A: 3306 aux_mode->alternate = 1; 3307 /* coverity[fallthrough] */ 3308 case MADURA_MIDX_10HGPT_0: 3309 config->data_rate = MADURA_SPD_11G; 3310 aux_mode->pass_thru = 1; 3311 break; 3312 case MADURA_MIDX_10GPT_0A: 3313 aux_mode->alternate = 1; 3314 /* coverity[fallthrough] */ 3315 case MADURA_MIDX_10GPT_0: 3316 if(read_1G_mode_status(pa,mindex0,&pll_1G_index)){ 3317 config->data_rate = MADURA_SPD_1G; 3318 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex0 == MADURA_MIDX_10GPT_0A)? 4:0, mindex0)){ 3319 config->data_rate = MADURA_SPD_25G; 3320 }else{ 3321 config->data_rate = MADURA_SPD_10G; 3322 } 3323 aux_mode->pass_thru = 1; 3324 break; 3325 } 3326 3327 } else if (lane_mask == 0x8) { 3328 switch(mindex3) { 3329 case MADURA_MIDX_10HGPT_3A: 3330 aux_mode->alternate = 1; 3331 /* coverity[fallthrough] */ 3332 case MADURA_MIDX_10HGPT_3: 3333 config->data_rate = MADURA_SPD_11G; 3334 aux_mode->pass_thru = 1; 3335 break; 3336 case MADURA_MIDX_10GPT_3A: 3337 aux_mode->alternate = 1; 3338 /* coverity[fallthrough] */ 3339 case MADURA_MIDX_10GPT_3: 3340 if(read_1G_mode_status(pa,mindex3,&pll_1G_index)){ 3341 config->data_rate = MADURA_SPD_1G; 3342 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex3 == MADURA_MIDX_10GPT_3A )?7:3, mindex3 )){ 3343 config->data_rate = MADURA_SPD_25G; 3344 }else{ 3345 config->data_rate = MADURA_SPD_10G; 3346 } 3347 aux_mode->pass_thru = 1; 3348 break; 3349 } 3350 } else if (lane_mask & 0xc) { 3351 switch(mindex2) { 3352 case MADURA_MIDX_40GPT10_0A: 3353 aux_mode->alternate = 1; 3354 /* coverity[fallthrough] */ 3355 case MADURA_MIDX_40GPT10_0: 3356 case MADURA_MIDX_40GPT10_1: 3357 case MADURA_MIDX_40GPT10_1A: 3358 case MADURA_MIDX_40HGPT10_0: 3359 case MADURA_MIDX_40HGPT10_0A: 3360 case MADURA_MIDX_40HGPT10_1: 3361 case MADURA_MIDX_40HGPT10_1A: 3362 config->data_rate = MADURA_SPD_40G; 3363 aux_mode->pass_thru = 1; 3364 break; 3365 3366 case MADURA_MIDX_40GDM_0: 3367 case MADURA_MIDX_40GDM_1: 3368 case MADURA_MIDX_40GDM_0B: 3369 case MADURA_MIDX_40GDM_1B: 3370 config->data_rate = MADURA_SPD_40G; 3371 aux_mode->pass_thru = 0; 3372 break; 3373 case MADURA_MIDX_40HGDM_0: 3374 case MADURA_MIDX_40HGDM_1: 3375 case MADURA_MIDX_40HGDM_0B: 3376 case MADURA_MIDX_40HGDM_1B: 3377 config->data_rate = MADURA_SPD_42G; 3378 aux_mode->pass_thru = 0; 3379 break; 3380 3381 case MADURA_MIDX_40HGPT20_1A: 3382 aux_mode->alternate = 1; 3383 /* coverity[fallthrough] */ 3384 case MADURA_MIDX_40HGPT20_1: 3385 config->data_rate = MADURA_SPD_42G; 3386 aux_mode->pass_thru_dual_lane = 1; 3387 break; 3388 case MADURA_MIDX_40GPT20_1A: 3389 aux_mode->alternate = 1; 3390 /* coverity[fallthrough] */ 3391 case MADURA_MIDX_40GPT20_1: 3392 if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex2 == MADURA_MIDX_40GPT20_1A )? 6:2, mindex2 )){ 3393 config->data_rate = MADURA_SPD_50G; 3394 }else{ 3395 config->data_rate = MADURA_SPD_40G; 3396 } 3397 aux_mode->pass_thru_dual_lane = 1; 3398 break; 3399 3400 case MADURA_MIDX_10HGPT_2A: 3401 aux_mode->alternate = 1; 3402 /* coverity[fallthrough] */ 3403 case MADURA_MIDX_10HGPT_2: 3404 config->data_rate = MADURA_SPD_11G; 3405 aux_mode->pass_thru = 1; 3406 break; 3407 case MADURA_MIDX_10GPT_2A: 3408 aux_mode->alternate = 1; 3409 /* coverity[fallthrough] */ 3410 case MADURA_MIDX_10GPT_2: 3411 if(read_1G_mode_status(pa,mindex2,&pll_1G_index)){ 3412 config->data_rate = MADURA_SPD_1G; 3413 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex2 == MADURA_MIDX_10GPT_2A )? 6:2 , mindex2 )){ 3414 config->data_rate = MADURA_SPD_25G; 3415 }else{ 3416 config->data_rate = MADURA_SPD_10G; 3417 } 3418 aux_mode->pass_thru = 1; 3419 break; 3420 } 3421 } else if (lane_mask == 0xF0) { 3422 switch(mindex2) { 3423 case MADURA_MIDX_40GDM_0: 3424 case MADURA_MIDX_40GDM_1: 3425 case MADURA_MIDX_40GDM_0B: 3426 case MADURA_MIDX_40GDM_1B: 3427 config->data_rate = MADURA_SPD_40G; 3428 aux_mode->pass_thru = 0; 3429 break; 3430 case MADURA_MIDX_40HGDM_0: 3431 case MADURA_MIDX_40HGDM_1: 3432 case MADURA_MIDX_40HGDM_0B: 3433 case MADURA_MIDX_40HGDM_1B: 3434 config->data_rate = MADURA_SPD_42G; 3435 aux_mode->pass_thru = 0; 3436 break; 3437 3438 default: 3439 switch(mindex0) { 3440 case MADURA_MIDX_40HGPT10_0A: 3441 aux_mode->alternate = 1; 3442 /* coverity[fallthrough] */ 3443 case MADURA_MIDX_40HGPT10_0: 3444 config->data_rate = MADURA_SPD_42G; 3445 aux_mode->pass_thru = 1; 3446 break; 3447 case MADURA_MIDX_40GPT10_0A: 3448 aux_mode->alternate = 1; 3449 /* coverity[fallthrough] */ 3450 case MADURA_MIDX_40GPT10_0: 3451 config->data_rate = MADURA_SPD_40G; 3452 aux_mode->pass_thru = 1; 3453 break; 3454 } 3455 break; 3456 } 3457 3458 } else if (lane_mask == 0x20) { 3459 switch(mindex1) { 3460 case MADURA_MIDX_10HGPT_1A: 3461 aux_mode->alternate = 1; 3462 /* coverity[fallthrough] */ 3463 case MADURA_MIDX_10HGPT_1: 3464 config->data_rate = MADURA_SPD_11G; 3465 aux_mode->pass_thru = 1; 3466 break; 3467 case MADURA_MIDX_10GPT_1A: 3468 aux_mode->alternate = 1; 3469 /* coverity[fallthrough] */ 3470 case MADURA_MIDX_10GPT_1: 3471 if(read_1G_mode_status(pa,mindex1,&pll_1G_index)){ 3472 config->data_rate = MADURA_SPD_1G; 3473 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip, ( mindex1 == MADURA_MIDX_10GPT_1A ) ? 5 : 1, mindex1 )){ 3474 config->data_rate = MADURA_SPD_25G; 3475 }else{ 3476 config->data_rate = MADURA_SPD_10G; 3477 } 3478 aux_mode->pass_thru = 1; 3479 break; 3480 } 3481 } else if (lane_mask & 0x30 ) { 3482 switch(mindex0) { 3483 case MADURA_MIDX_40HGPT10_0A: 3484 aux_mode->alternate = 1; 3485 /* coverity[fallthrough] */ 3486 case MADURA_MIDX_40HGPT10_0: 3487 config->data_rate = MADURA_SPD_42G; 3488 aux_mode->pass_thru = 1; 3489 break; 3490 case MADURA_MIDX_40GPT10_0A: 3491 aux_mode->alternate = 1; 3492 /* coverity[fallthrough] */ 3493 case MADURA_MIDX_40GPT10_0: 3494 config->data_rate = MADURA_SPD_40G; 3495 aux_mode->pass_thru = 1; 3496 break; 3497 3498 case MADURA_MIDX_40GDM_0: 3499 case MADURA_MIDX_40GDM_1: 3500 case MADURA_MIDX_40GDM_0B: 3501 case MADURA_MIDX_40GDM_1B: 3502 config->data_rate = MADURA_SPD_40G; 3503 aux_mode->pass_thru = 0; 3504 break; 3505 case MADURA_MIDX_40HGDM_0: 3506 case MADURA_MIDX_40HGDM_1: 3507 case MADURA_MIDX_40HGDM_0B: 3508 case MADURA_MIDX_40HGDM_1B: 3509 config->data_rate = MADURA_SPD_42G; 3510 aux_mode->pass_thru = 0; 3511 break; 3512 3513 case MADURA_MIDX_40HGPT20_0A: 3514 aux_mode->alternate = 1; 3515 /* coverity[fallthrough] */ 3516 case MADURA_MIDX_40HGPT20_0: 3517 config->data_rate = MADURA_SPD_42G; 3518 aux_mode->pass_thru_dual_lane = 1; 3519 break; 3520 case MADURA_MIDX_40GPT20_0A: 3521 aux_mode->alternate = 1; 3522 /* coverity[fallthrough] */ 3523 case MADURA_MIDX_40GPT20_0: 3524 if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,0, mindex0 )){ 3525 config->data_rate = MADURA_SPD_50G; 3526 }else{ 3527 config->data_rate = MADURA_SPD_40G; 3528 } 3529 aux_mode->pass_thru_dual_lane = 1; 3530 break; 3531 3532 case MADURA_MIDX_10HGPT_0A: 3533 aux_mode->alternate = 1; 3534 /* coverity[fallthrough] */ 3535 case MADURA_MIDX_10HGPT_0: 3536 config->data_rate = MADURA_SPD_11G; 3537 aux_mode->pass_thru = 1; 3538 break; 3539 case MADURA_MIDX_10GPT_0A: 3540 aux_mode->alternate = 1; 3541 /* coverity[fallthrough] */ 3542 case MADURA_MIDX_10GPT_0: 3543 if(read_1G_mode_status(pa,mindex0,&pll_1G_index)){ 3544 config->data_rate = MADURA_SPD_1G; 3545 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip, ( mindex0 == MADURA_MIDX_10GPT_0A )? 4:0, mindex0 )){ 3546 config->data_rate = MADURA_SPD_25G; 3547 }else{ 3548 config->data_rate = MADURA_SPD_10G; 3549 } 3550 aux_mode->pass_thru = 1; 3551 break; 3552 } 3553 } else if (lane_mask == 0x80) { 3554 switch(mindex3) { 3555 case MADURA_MIDX_10HGPT_3A: 3556 aux_mode->alternate = 1; 3557 /* coverity[fallthrough] */ 3558 case MADURA_MIDX_10HGPT_3: 3559 config->data_rate = MADURA_SPD_11G; 3560 aux_mode->pass_thru = 1; 3561 break; 3562 case MADURA_MIDX_10GPT_3A: 3563 aux_mode->alternate = 1; 3564 /* coverity[fallthrough] */ 3565 case MADURA_MIDX_10GPT_3: 3566 if(read_1G_mode_status(pa,mindex3,&pll_1G_index)){ 3567 config->data_rate = MADURA_SPD_1G; 3568 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex3 == MADURA_MIDX_10GPT_3A )? 7:3, mindex3 )){ 3569 config->data_rate = MADURA_SPD_25G; 3570 }else{ 3571 config->data_rate = MADURA_SPD_10G; 3572 } 3573 aux_mode->pass_thru = 1; 3574 break; 3575 } 3576 } else if (lane_mask & 0xC0) { 3577 switch(mindex2) { 3578 case MADURA_MIDX_40GPT10_0A: 3579 aux_mode->alternate = 1; 3580 /* coverity[fallthrough] */ 3581 case MADURA_MIDX_40GPT10_0: 3582 case MADURA_MIDX_40GPT10_1: 3583 case MADURA_MIDX_40GPT10_1A: 3584 case MADURA_MIDX_40HGPT10_0: 3585 case MADURA_MIDX_40HGPT10_0A: 3586 case MADURA_MIDX_40HGPT10_1: 3587 case MADURA_MIDX_40HGPT10_1A: 3588 config->data_rate = MADURA_SPD_40G; 3589 aux_mode->pass_thru = 1; 3590 break; 3591 3592 case MADURA_MIDX_40GDM_0: 3593 case MADURA_MIDX_40GDM_1: 3594 case MADURA_MIDX_40GDM_0B: 3595 case MADURA_MIDX_40GDM_1B: 3596 config->data_rate = MADURA_SPD_40G; 3597 aux_mode->pass_thru = 0; 3598 break; 3599 case MADURA_MIDX_40HGDM_0: 3600 case MADURA_MIDX_40HGDM_1: 3601 case MADURA_MIDX_40HGDM_0B: 3602 case MADURA_MIDX_40HGDM_1B: 3603 config->data_rate = MADURA_SPD_42G; 3604 aux_mode->pass_thru = 0; 3605 break; 3606 3607 case MADURA_MIDX_40HGPT20_1A: 3608 aux_mode->alternate = 1; 3609 /* coverity[fallthrough] */ 3610 case MADURA_MIDX_40HGPT20_1: 3611 config->data_rate = MADURA_SPD_42G; 3612 aux_mode->pass_thru_dual_lane = 1; 3613 break; 3614 case MADURA_MIDX_40GPT20_1A: 3615 aux_mode->alternate = 1; 3616 /* coverity[fallthrough] */ 3617 case MADURA_MIDX_40GPT20_1: 3618 if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex2 == MADURA_MIDX_40GPT20_1A )? 6:2, mindex2 )){ 3619 config->data_rate = MADURA_SPD_50G; 3620 }else{ 3621 config->data_rate = MADURA_SPD_40G; 3622 } 3623 aux_mode->pass_thru_dual_lane = 1; 3624 break; 3625 3626 case MADURA_MIDX_10HGPT_2A: 3627 aux_mode->alternate = 1; 3628 /* coverity[fallthrough] */ 3629 case MADURA_MIDX_10HGPT_2: 3630 config->data_rate = MADURA_SPD_11G; 3631 aux_mode->pass_thru = 1; 3632 break; 3633 case MADURA_MIDX_10GPT_2A: 3634 aux_mode->alternate = 1; 3635 /* coverity[fallthrough] */ 3636 case MADURA_MIDX_10GPT_2: 3637 if(read_1G_mode_status(pa,mindex2,&pll_1G_index)){ 3638 config->data_rate = MADURA_SPD_1G; 3639 }else if(MADURA_PLL_MODE_165 == read_madura_pll_mode(pa,ip,( mindex2 == MADURA_MIDX_10GPT_2A )? 6:2, mindex2 )){ 3640 config->data_rate = MADURA_SPD_25G; 3641 }else{ 3642 config->data_rate = MADURA_SPD_10G; 3643 } 3644 aux_mode->pass_thru = 1; 3645 break; 3646 } 3647 } 3648 if (aux_mode->pass_thru == 1 || aux_mode->pass_thru_dual_lane == 1) { 3649 aux_mode->passthru_sys_side_core = MADURA_FALCON_CORE ; 3650 aux_mode->pass_thru = 1; 3651 } 3652 } 3653 3654 if (config->data_rate == MADURA_SPD_11G || 3655 config->data_rate == MADURA_SPD_42G || 3656 config->data_rate == MADURA_SPD_106G ) { 3657 PHYMOD_INTF_MODES_HIGIG_SET(config); 3658 } else { 3659 config->interface_modes = 0; /*Ethernet*/ 3660 } 3661 3662 /*CLOCK_SCALEr*/ 3663 PHYMOD_IF_ERR_RETURN( 3664 BCMI_MADURA_READ_CLK_SCALER_CTLr(pa,&clk_ctrl)); 3665 clock_ratio = BCMI_MADURA_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_GET(clk_ctrl); 3666 if (clock_ratio == 0x640) { 3667 config->ref_clock = phymodRefClk156Mhz; 3668 } else if (clock_ratio == 0x672) { 3669 config->ref_clock = phymodRefClk161Mhz; 3670 } else if (clock_ratio == 0x800) { 3671 config->ref_clock = 0 ;/* set to 0 in reset value 0x800. Is it fine?*/ 3672 } 3673 3674 PHYMOD_IF_ERR_RETURN(_madura_get_ieee_intf(pa, config, &intf)); 3675 config->interface_type = intf; 3676 PHYMOD_IF_ERR_RETURN(_madura_get_media_type(pa, config, &media_type)); 3677 if (media_type == SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS) { 3678 PHYMOD_INTF_MODES_UNRELIABLE_LOS_SET(config); 3679 } else { 3680 PHYMOD_INTF_MODES_UNRELIABLE_LOS_CLR(config); 3681 } 3682 3683 return PHYMOD_E_NONE; 3684 } 3685 3686 int _madura_phy_pcs_link_get(const phymod_access_t *pa, uint32_t *pcs_link) 3687 { 3688 if (pcs_link) { 3689 *pcs_link = 0xffff; 3690 } else { 3691 return PHYMOD_E_PARAM; 3692 } 3693 PHYMOD_IF_ERR_RETURN(_madura_get_pcs_link_status(pa, pcs_link)); 3694 3695 return PHYMOD_E_NONE; 3696 } 3697 3698 int _madura_configure_ref_clock(const phymod_access_t *pa, phymod_ref_clk_t ref_clk) 3699 { 3700 BCMI_MADURA_CLK_SCALER_CTLr_t clk_ctrl; 3701 PHYMOD_MEMSET(&clk_ctrl, 0, sizeof(BCMI_MADURA_CLK_SCALER_CTLr_t)); 3702 3703 /* uint16_t clk_scalar_code = 0x0; */ 3704 switch (ref_clk) { 3705 case phymodRefClk156Mhz: 3706 case phymodRefClk312Mhz: 3707 /* case phymodRefClk625Mhz: */ 3708 BCMI_MADURA_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl,0x640); 3709 PHYMOD_IF_ERR_RETURN( 3710 BCMI_MADURA_WRITE_CLK_SCALER_CTLr(pa,clk_ctrl)); 3711 break; 3712 case phymodRefClk161Mhz: 3713 case phymodRefClk322Mhz: 3714 case phymodRefClk644Mhz: 3715 BCMI_MADURA_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl,0x672); 3716 PHYMOD_IF_ERR_RETURN( 3717 BCMI_MADURA_WRITE_CLK_SCALER_CTLr(pa,clk_ctrl)); 3718 break; 3719 default: 3720 return PHYMOD_E_PARAM; 3721 } 3722 3723 return PHYMOD_E_NONE; 3724 } 3725 3726 int _madura_get_pll_modes(phymod_ref_clk_t ref_clk,const phymod_phy_inf_config_t *config, uint16_t *fal_pll_mode, uint16_t *fal_2x_pll_mode) 3727 { 3728 uint32_t speed = config->data_rate; 3729 switch (ref_clk) { 3730 case phymodRefClk156Mhz: 3731 case phymodRefClk312Mhz: 3732 if (speed == MADURA_SPD_100G || 3733 speed == MADURA_SPD_106G) { 3734 if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 3735 *fal_pll_mode = MADURA_PLL_MODE_175; 3736 } else { 3737 *fal_pll_mode = MADURA_PLL_MODE_165; 3738 } 3739 } else if( speed == MADURA_SPD_25G || 3740 speed == MADURA_SPD_50G ){ 3741 *fal_pll_mode = MADURA_PLL_MODE_165; 3742 } else { 3743 /*-- Falcon Line Rate is 10G/20G*/ 3744 if (!PHYMOD_INTF_MODES_HIGIG_GET(config)) { /*IEEE MODE*/ 3745 *fal_pll_mode = MADURA_PLL_MODE_132; 3746 } else if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 3747 *fal_pll_mode = MADURA_PLL_MODE_140; 3748 } else { 3749 return PHYMOD_E_PARAM; 3750 } 3751 } 3752 break; 3753 case phymodRefClk161Mhz: 3754 case phymodRefClk322Mhz: 3755 case phymodRefClk644Mhz: 3756 if (speed == MADURA_SPD_100G || 3757 speed == MADURA_SPD_106G) { 3758 if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 3759 return PHYMOD_E_PARAM; 3760 } else { 3761 *fal_pll_mode = MADURA_PLL_MODE_160; 3762 } 3763 } else { 3764 if (!PHYMOD_INTF_MODES_HIGIG_GET(config)) {/*IEEE MODE*/ 3765 *fal_pll_mode = MADURA_PLL_MODE_128; 3766 } else { 3767 return PHYMOD_E_PARAM; 3768 } 3769 } 3770 break; 3771 case phymodRefClk174Mhz: 3772 case phymodRefClk349Mhz: 3773 case phymodRefClk698Mhz: 3774 if (speed == MADURA_SPD_100G || 3775 speed == MADURA_SPD_106G) { 3776 if (config->interface_type == phymodInterfaceOTN) { 3777 *fal_pll_mode = MADURA_PLL_MODE_160; 3778 } else { 3779 return PHYMOD_E_PARAM; 3780 } 3781 } else { 3782 if (config->interface_type == phymodInterfaceOTN) { 3783 *fal_pll_mode = MADURA_PLL_MODE_128; 3784 } else { 3785 return PHYMOD_E_PARAM; 3786 } 3787 } 3788 break; 3789 default: 3790 return PHYMOD_E_PARAM; 3791 } 3792 return PHYMOD_E_NONE; 3793 } 3794 3795 int _madura_configure_pll(const phymod_access_t *pa, const uint16_t pll_val) 3796 { 3797 3798 PHYMOD_IF_ERR_RETURN( 3799 wrc_falcon2_madura_ams_pll_pwrdn(0)); 3800 PHYMOD_IF_ERR_RETURN( 3801 wrc_falcon2_madura_core_dp_s_rstb(0)); 3802 PHYMOD_IF_ERR_RETURN ( 3803 falcon2_madura_configure_pll(pa, pll_val)); 3804 PHYMOD_IF_ERR_RETURN( 3805 wrc_falcon2_madura_core_dp_s_rstb(1)); 3806 3807 return PHYMOD_E_NONE; 3808 } 3809 3810 int _madura_config_pll_div(const phymod_access_t *pa, const phymod_phy_inf_config_t config) 3811 { 3812 uint16_t ip = 0, fal_2x_pll_mode = 0, falcon_pll_mode = 0, lane_mask=0; 3813 phymod_ref_clk_t ref_clk = config.ref_clock; 3814 uint16_t data = 0, retry_cnt = 5; 3815 BCMI_MADURA_SLICEr_t slice_reg; 3816 BCMI_MADURA_PMD_PLL_STSr_t pll_sts; 3817 uint16_t lane=0, max_lane=0, pll_sel=0 ; 3818 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 3819 uint32_t programmed_pll=0; 3820 err_code_t __err=ERR_CODE_NONE; 3821 3822 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 3823 PHYMOD_MEMSET(&pll_sts, 0 , sizeof(BCMI_MADURA_PMD_PLL_STSr_t)); 3824 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 3825 3826 /*Program PLL div of all dies*/ 3827 /* Set pll_mode */ 3828 PHYMOD_IF_ERR_RETURN( 3829 _madura_get_pll_modes(ref_clk, &config, &falcon_pll_mode, &fal_2x_pll_mode)); 3830 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 3831 3832 3833 for (ip = MADURA_2X_FALCON_CORE ; ip <= MADURA_FALCON_CORE ;ip++) { 3834 max_lane = ( ip == MADURA_2X_FALCON_CORE)? 8:4 ; 3835 for( lane =0; lane < max_lane ; lane ++) 3836 { 3837 if(1<<lane & lane_mask){ 3838 pll_sel = (config.data_rate == 25000) ? 1:0 ; 3839 PHYMOD_IF_ERR_RETURN ( 3840 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane , pll_sel )); 3841 3842 programmed_pll = rdc_falcon2_madura_pll_mode() ; 3843 if(__err!=ERR_CODE_NONE){ 3844 PHYMOD_DEBUG_ERROR(("PLL read failed for pll\n")); 3845 return PHYMOD_E_FAIL; 3846 } 3847 3848 /* Set PLL div for 156Mhz clock*/ 3849 switch (falcon_pll_mode) { 3850 case MADURA_PLL_MODE_132: 3851 if(programmed_pll!=MADURA_PLL_MODE_132){ 3852 PHYMOD_IF_ERR_RETURN ( 3853 _madura_configure_pll(pa, FALCON2_MADURA_pll_div_132x)); 3854 } 3855 break; 3856 case MADURA_PLL_MODE_140: 3857 if(programmed_pll!=MADURA_PLL_MODE_140){ 3858 PHYMOD_IF_ERR_RETURN ( 3859 _madura_configure_pll(pa, FALCON2_MADURA_pll_div_140x)); 3860 } 3861 break; 3862 case MADURA_PLL_MODE_165: /*PLL is 165 for 100G and 25G*/ 3863 if(programmed_pll!=MADURA_PLL_MODE_165){ 3864 PHYMOD_IF_ERR_RETURN ( 3865 _madura_configure_pll(pa, FALCON2_MADURA_pll_div_165x)); 3866 } 3867 break; 3868 case MADURA_PLL_MODE_175: 3869 if(programmed_pll!=MADURA_PLL_MODE_175){ 3870 PHYMOD_IF_ERR_RETURN ( 3871 _madura_configure_pll(pa, FALCON2_MADURA_pll_div_175x)); 3872 } 3873 break; 3874 default: 3875 return PHYMOD_E_PARAM; 3876 } 3877 } 3878 } 3879 } 3880 3881 /* Set FW_ENABLE = 1 */ 3882 PHYMOD_IF_ERR_RETURN( 3883 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en)); 3884 /* coverity[operator_confusion] */ 3885 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en,1); 3886 PHYMOD_IF_ERR_RETURN( 3887 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en)); 3888 do { 3889 PHYMOD_IF_ERR_RETURN( 3890 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en)); 3891 data=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 3892 PHYMOD_USLEEP(100); 3893 } while ((data != 0) && (retry_cnt --)); 3894 if (retry_cnt == 0) { 3895 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 3896 (_PHYMOD_MSG("PLL config failed, micro controller is busy.."))); 3897 } 3898 3899 PHYMOD_USLEEP(100000);/*100 milsec*/ 3900 /*check pll lock */ 3901 do { 3902 PHYMOD_IF_ERR_RETURN( 3903 BCMI_MADURA_READ_PMD_PLL_STSr(pa,&pll_sts )); 3904 data=(pll_sel==0)?BCMI_MADURA_PMD_PLL_STSr_PMD_PLL0_LOCKf_GET(pll_sts):BCMI_MADURA_PMD_PLL_STSr_PMD_PLL1_LOCKf_GET(pll_sts); 3905 PHYMOD_USLEEP(100); 3906 } while((data != 0) && (retry_cnt--)); 3907 if (retry_cnt == 0) { 3908 PHYMOD_DEBUG_ERROR(("PLL LOCK failed for pll\n")); 3909 return PHYMOD_E_FAIL; 3910 } 3911 3912 /*Reset DEV1 slice register*/ 3913 PHYMOD_IF_ERR_RETURN( 3914 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 3915 return PHYMOD_E_NONE; 3916 } 3917 3918 int _madura_core_dp_rstb(const phymod_access_t *pa, const phymod_phy_inf_config_t config) 3919 { 3920 return PHYMOD_E_NONE; 3921 } 3922 3923 int _madura_core_reset_set(const phymod_access_t *pa, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 3924 { 3925 uint16_t cores=3,ip=0; 3926 uint16_t lane=0; 3927 BCMI_MADURA_GEN_CTL1r_t gen_ctrl; 3928 BCMI_MADURA_COMMON_CTLr_t fal_cmn_ctrl; 3929 BCMI_MADURA_RXTX_LN_S_RSTB_CTLr_t ln_s_rstb; 3930 3931 PHYMOD_MEMSET(&gen_ctrl, 0, sizeof(BCMI_MADURA_GEN_CTL1r_t)); 3932 PHYMOD_MEMSET(&fal_cmn_ctrl, 0, sizeof(BCMI_MADURA_COMMON_CTLr_t)); 3933 PHYMOD_MEMSET(&ln_s_rstb, 0, sizeof(BCMI_MADURA_RXTX_LN_S_RSTB_CTLr_t)); 3934 3935 PHYMOD_IF_ERR_RETURN( 3936 BCMI_MADURA_READ_GEN_CTL1r(pa,&gen_ctrl)); 3937 if (reset_mode == phymodResetModeHard) { 3938 /*Reset for chip*/ 3939 BCMI_MADURA_GEN_CTL1r_RESETBf_SET(gen_ctrl,0); 3940 /*Reset registers*/ 3941 BCMI_MADURA_GEN_CTL1r_REG_RSTBf_SET(gen_ctrl,0); 3942 PHYMOD_IF_ERR_RETURN( 3943 BCMI_MADURA_WRITE_GEN_CTL1r(pa,gen_ctrl)); 3944 /*Above chip reset resets the cores also !*/ 3945 PHYMOD_USLEEP(10000); 3946 } else { 3947 /*Reset registers*/ 3948 BCMI_MADURA_GEN_CTL1r_REG_RSTBf_SET(gen_ctrl,0); 3949 PHYMOD_IF_ERR_RETURN( 3950 BCMI_MADURA_WRITE_GEN_CTL1r(pa,gen_ctrl)); 3951 /* Reset per falcon of 4 falcons*/ 3952 while(cores>0) 3953 { 3954 PHYMOD_IF_ERR_RETURN( 3955 _madura_set_slice_reg (pa, 3956 ip, MADURA_DEV_PMA_PMD, lane, 0)); 3957 /*Lane soft reset*/ 3958 PHYMOD_IF_ERR_RETURN( 3959 BCMI_MADURA_READ_RXTX_LN_S_RSTB_CTLr(pa,&ln_s_rstb)); 3960 BCMI_MADURA_RXTX_LN_S_RSTB_CTLr_LN_S_RSTBf_SET(ln_s_rstb,0); 3961 PHYMOD_IF_ERR_RETURN( 3962 BCMI_MADURA_WRITE_RXTX_LN_S_RSTB_CTLr(pa,ln_s_rstb)); 3963 PHYMOD_USLEEP(10000); 3964 BCMI_MADURA_RXTX_LN_S_RSTB_CTLr_LN_S_RSTBf_SET(ln_s_rstb,1); 3965 PHYMOD_IF_ERR_RETURN( 3966 BCMI_MADURA_WRITE_RXTX_LN_S_RSTB_CTLr(pa,ln_s_rstb)); 3967 3968 ip=(cores==2)?1:0;/*toggle ip for 3rd iteration*/ 3969 lane=(ip==1)?0:4;/*toggle ip for 3rd iteration*/ 3970 cores--; 3971 } 3972 3973 } 3974 3975 /* Force clock to 0 temporarily */ 3976 { 3977 3978 BCMI_MADURA_CLK_SCALER_CTLr_t clk_ctrl; 3979 PHYMOD_MEMSET(&clk_ctrl, 0, sizeof(BCMI_MADURA_CLK_SCALER_CTLr_t)); 3980 3981 BCMI_MADURA_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl,0x800); 3982 PHYMOD_IF_ERR_RETURN( 3983 BCMI_MADURA_WRITE_CLK_SCALER_CTLr(pa,clk_ctrl)); 3984 } 3985 3986 return PHYMOD_E_NONE; 3987 } 3988 3989 int _madura_pcs_link_monitor_enable_set(const phymod_access_t *pa, uint16_t en_dis) 3990 { 3991 uint16_t lane = 0; 3992 uint16_t ip = 0; 3993 phymod_phy_inf_config_t config; 3994 uint16_t max_lane = 0, lane_mask=0; 3995 BCMI_MADURA_PATT_MON_GEN_CTLr_t mon_ctrl; 3996 3997 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 3998 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 3999 PHYMOD_MEMSET(&mon_ctrl, 0, sizeof(BCMI_MADURA_PATT_MON_GEN_CTLr_t)); 4000 4001 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4002 _madura_phy_interface_config_get(pa, 0, &config))); 4003 4004 MADURA_GET_IP(pa, config, ip); 4005 4006 lane_mask = (pa->lane_mask) ? pa->lane_mask : 0xf; 4007 max_lane = (ip == MADURA_FALCON_CORE) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4008 4009 for (lane = 0; lane < max_lane; lane ++) { 4010 if ((lane_mask & (1 << lane))) { 4011 /*config slice reg */ 4012 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4013 _madura_set_slice_reg (pa, 4014 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4015 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4016 BCMI_MADURA_READ_PATT_MON_GEN_CTLr(pa,&mon_ctrl))); 4017 BCMI_MADURA_PATT_MON_GEN_CTLr_RX_MON_CTRLf_SET(mon_ctrl,(en_dis<<1)); 4018 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4019 BCMI_MADURA_WRITE_PATT_MON_GEN_CTLr(pa,mon_ctrl))); 4020 PHYMOD_DEBUG_VERBOSE(("Falcon Set Link monitor for Lane:%d \n", 4021 lane)); 4022 } 4023 } 4024 4025 PHYMOD_FREE(config.device_aux_modes); 4026 return PHYMOD_E_NONE; 4027 } 4028 4029 int _madura_pcs_link_monitor_enable_get(const phymod_access_t *pa, uint32_t *get_pcs) 4030 { 4031 uint16_t lane = 0; 4032 uint16_t ip = 0; 4033 phymod_phy_inf_config_t config; 4034 uint16_t max_lane = 0, lane_mask=0; 4035 BCMI_MADURA_PATT_MON_GEN_CTLr_t mon_ctrl; 4036 4037 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4038 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4039 PHYMOD_MEMSET(&mon_ctrl, 0, sizeof(BCMI_MADURA_PATT_MON_GEN_CTLr_t)); 4040 4041 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4042 _madura_phy_interface_config_get(pa, 0, &config))); 4043 4044 MADURA_GET_IP(pa, config, ip); 4045 /*MADURA_GET_INTF_SIDE(pa,intf_side); */ 4046 4047 lane_mask = (pa->lane_mask) ? pa->lane_mask : 0xf; 4048 max_lane = (ip == MADURA_FALCON_CORE) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4049 4050 for (lane = 0; lane < max_lane; lane ++) { 4051 if ((lane_mask & (1 << lane))) { 4052 /*config slice reg */ 4053 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4054 _madura_set_slice_reg (pa, 4055 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4056 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4057 BCMI_MADURA_READ_PATT_MON_GEN_CTLr(pa,&mon_ctrl))); 4058 *get_pcs |= ((BCMI_MADURA_PATT_MON_GEN_CTLr_RX_MON_CTRLf_GET(mon_ctrl))>>1)<<lane; 4059 PHYMOD_DEBUG_VERBOSE(("Falcon Get Link monitor for Lane:%d Data:0x%x\n", 4060 lane, *get_pcs)); 4061 }else{ 4062 PHYMOD_DEBUG_VERBOSE(("lane %x not matching with lanemask %x get_pcs=%x\n",lane,lane_mask,*get_pcs)); 4063 } 4064 } 4065 4066 if(( *get_pcs != 0 ) && ( *get_pcs == lane_mask )) 4067 { *get_pcs = 1 ; } 4068 else 4069 { *get_pcs = 0 ; } 4070 4071 PHYMOD_FREE(config.device_aux_modes); 4072 return PHYMOD_E_NONE; 4073 } 4074 4075 int _madura_get_pcs_link_status(const phymod_access_t *pa, uint32_t *link_sts) 4076 { 4077 uint16_t lane = 0; 4078 uint16_t ip = 0; 4079 phymod_phy_inf_config_t config; 4080 uint16_t max_lane = 0, lane_mask=0 ; 4081 uint32_t err_cnt = 0, get_pcs = 0; 4082 BCMI_MADURA_CL49_BER_STSr_t ber_status; 4083 BCMI_MADURA_CL82_BER_CNTr_t ber_cnt; 4084 BCMI_MADURA_SLICEr_t slice_reg; 4085 BCMI_MADURA_PCS_MON_LIVE_STSr_t pcs_mon_liv_sts; 4086 BCMI_MADURA_PCS_MON_STSr_t pcs_mon_sts; 4087 4088 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4089 PHYMOD_MEMSET(&ber_status, 0, sizeof(BCMI_MADURA_CL49_BER_STSr_t)); 4090 PHYMOD_MEMSET(&slice_reg, 0, sizeof(BCMI_MADURA_SLICEr_t)); 4091 PHYMOD_MEMSET(&ber_cnt, 0, sizeof(BCMI_MADURA_CL82_BER_CNTr_t)); 4092 PHYMOD_MEMSET(&pcs_mon_liv_sts, 0, sizeof(BCMI_MADURA_PCS_MON_LIVE_STSr_t)); 4093 PHYMOD_MEMSET(&pcs_mon_sts, 0, sizeof(BCMI_MADURA_PCS_MON_STSr_t)); 4094 4095 *link_sts = 0xffff; 4096 4097 PHYMOD_IF_ERR_RETURN( 4098 _madura_pcs_link_monitor_enable_get(pa, &get_pcs)); 4099 4100 if (get_pcs) { 4101 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4102 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4103 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4104 _madura_phy_interface_config_get(pa, 0, &config))); 4105 4106 MADURA_GET_IP(pa, config, ip); 4107 4108 lane_mask = (pa->lane_mask) ? pa->lane_mask : 0xf; 4109 max_lane = (ip == MADURA_FALCON_CORE) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4110 4111 PHYMOD_DEBUG_VERBOSE((" Max_lane:%d lanemask:0x%x\n", 4112 max_lane, lane_mask)); 4113 4114 PHYMOD_DEBUG_VERBOSE(("Getting PCS Status\n")); 4115 for (lane = 0; lane < max_lane; lane ++) { 4116 if ((lane_mask & (1 << lane))) { 4117 /*Program Slice register dev1*/ 4118 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4119 _madura_set_slice_reg (pa, 4120 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4121 /*Check PCS live status*/ 4122 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4123 BCMI_MADURA_READ_PCS_MON_LIVE_STSr(pa,&pcs_mon_liv_sts))); 4124 if(BCMI_MADURA_PCS_MON_LIVE_STSr_PCS_STATUSf_GET(pcs_mon_liv_sts)){ 4125 *link_sts &= 1; 4126 /* Check PCS lock*/ 4127 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4128 BCMI_MADURA_READ_PCS_MON_STSr(pa,&pcs_mon_sts))); 4129 4130 if(!BCMI_MADURA_PCS_MON_STSr_BLOCK_LOCK_LLf_GET(pcs_mon_sts)){ 4131 /* Loss of link : read error cntr*/ 4132 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4133 BCMI_MADURA_READ_CL49_BER_STSr(pa,&ber_status))); 4134 err_cnt = BCMI_MADURA_CL49_BER_STSr_BER_COUNTf_GET(ber_status); 4135 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4136 BCMI_MADURA_READ_CL82_BER_CNTr(pa,&ber_cnt))); 4137 4138 err_cnt=BCMI_MADURA_CL82_BER_CNTr_BER_COUNT_MSBf_GET(ber_cnt); 4139 *link_sts &= 0; 4140 PHYMOD_DEBUG_VERBOSE(("Lane:%d Loss of lock: 1 Error Cnt:0x%x\n", 4141 lane, err_cnt)); 4142 } 4143 } else { 4144 *link_sts &= 0; 4145 } 4146 } 4147 } 4148 PHYMOD_FREE(config.device_aux_modes); 4149 } else { 4150 PHYMOD_DEBUG_VERBOSE(("PCS MON not Enabled, Reading PMD Status\n")); 4151 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4152 _madura_rx_pmd_lock_get(pa, link_sts))); 4153 } 4154 /*Reset DEV1 slice register*/ 4155 PHYMOD_IF_ERR_RETURN( 4156 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 4157 return PHYMOD_E_NONE; 4158 } 4159 4160 int _madura_fal_2x_falcon_lane_map_get( 4161 const phymod_access_t *pa, 4162 const phymod_phy_inf_config_t *cfg, 4163 uint32_t* fal_2x_lane_map, 4164 uint32_t* fal_lane_map) 4165 { 4166 4167 phymod_phy_inf_config_t config; 4168 uint16_t core = 0; 4169 uint32_t lane_mask = 0; 4170 MADURA_DEVICE_AUX_MODE_T *aux_mode; 4171 4172 lane_mask = (pa->lane_mask) ? pa->lane_mask : 0xf; 4173 PHYMOD_MEMCPY(&config, cfg, sizeof(phymod_phy_inf_config_t)); 4174 aux_mode = (MADURA_DEVICE_AUX_MODE_T*)cfg->device_aux_modes; 4175 MADURA_GET_IP(pa, config, core); 4176 PHYMOD_DEBUG_VERBOSE(("%s :: core:%d\n", __func__, core)); 4177 4178 if (config.data_rate == MADURA_SPD_100G || 4179 config.data_rate == MADURA_SPD_106G) { 4180 if(!aux_mode->alternate){ 4181 *fal_2x_lane_map = 0xF; 4182 *fal_lane_map = 0xF; 4183 } else { /*alternate*/ 4184 *fal_2x_lane_map = 0xF0; 4185 *fal_lane_map = 0xF; 4186 } 4187 } else if (core == MADURA_2X_FALCON_CORE) { 4188 if (config.data_rate == MADURA_SPD_40G || config.data_rate == MADURA_SPD_50G || 4189 config.data_rate == MADURA_SPD_42G) { 4190 if ((aux_mode->pass_thru_dual_lane) && (!aux_mode->alternate)) { 4191 *fal_2x_lane_map = lane_mask; 4192 *fal_lane_map = lane_mask; 4193 } else if ((aux_mode->pass_thru_dual_lane) && (aux_mode->alternate)) { 4194 *fal_2x_lane_map = lane_mask; 4195 *fal_lane_map = lane_mask >> 4; 4196 } else if ((aux_mode->pass_thru) && (!aux_mode->alternate)) { 4197 *fal_2x_lane_map = 0xf; 4198 *fal_lane_map = 0xF; 4199 } else if ((aux_mode->pass_thru) && (aux_mode->alternate)) { 4200 *fal_2x_lane_map = 0xF0; 4201 *fal_lane_map = 0xF; 4202 } 4203 else { 4204 *fal_2x_lane_map = lane_mask; 4205 if (lane_mask == 0xF) 4206 *fal_lane_map = 0x3; 4207 else if(lane_mask == 0xF0) 4208 *fal_lane_map = 0xC; 4209 else 4210 *fal_lane_map = 0xF; 4211 } 4212 } else { /* 10G/11G */ 4213 if (!aux_mode->alternate) {/*passthru*/ 4214 *fal_2x_lane_map = lane_mask; 4215 *fal_lane_map = lane_mask; 4216 } else { 4217 *fal_2x_lane_map = lane_mask; 4218 *fal_lane_map = lane_mask >> 4; 4219 } 4220 } 4221 } 4222 else { 4223 if (config.data_rate == MADURA_SPD_40G || config.data_rate == MADURA_SPD_50G || 4224 config.data_rate == MADURA_SPD_42G) { 4225 if ((aux_mode->pass_thru_dual_lane) && (!aux_mode->alternate)) { 4226 *fal_lane_map = lane_mask; 4227 *fal_2x_lane_map = lane_mask; 4228 } else if ((aux_mode->pass_thru_dual_lane) && (aux_mode->alternate)) { 4229 *fal_lane_map = lane_mask; 4230 *fal_2x_lane_map = lane_mask << 4;; 4231 } else if ((aux_mode->pass_thru) && (!aux_mode->alternate)) { 4232 *fal_2x_lane_map = 0xf; 4233 *fal_lane_map = 0xF; 4234 } else if ((aux_mode->pass_thru) && (aux_mode->alternate)) { 4235 *fal_2x_lane_map = 0xF0; 4236 *fal_lane_map = 0xF; 4237 } 4238 else { 4239 *fal_lane_map = lane_mask; 4240 if (lane_mask == 0x3) 4241 *fal_2x_lane_map = 0xF; 4242 else if(lane_mask == 0xC) 4243 *fal_2x_lane_map = 0xF0; 4244 else 4245 *fal_2x_lane_map = 0xFF; 4246 } 4247 } else { /* 10G/11G */ 4248 if (!aux_mode->alternate) { 4249 *fal_lane_map = lane_mask; 4250 *fal_2x_lane_map = lane_mask; 4251 } else { 4252 *fal_lane_map = lane_mask; 4253 *fal_2x_lane_map = lane_mask << 4; 4254 } 4255 } 4256 } 4257 return PHYMOD_E_NONE; 4258 } 4259 4260 int _madura_falcon_lpbk_get( 4261 const phymod_access_t *pa, 4262 phymod_loopback_mode_t loopback, 4263 uint32_t* enable, 4264 uint16_t ip) 4265 { 4266 4267 BCMI_MADURA_TLB_RX_DIG_LPBK_CFGr_t dig_lpbk; 4268 BCMI_MADURA_TLB_TX_RMT_LPBK_CFGr_t rmt_lpbk; 4269 PHYMOD_MEMSET(&dig_lpbk, 0, sizeof(BCMI_MADURA_TLB_RX_DIG_LPBK_CFGr_t)); 4270 PHYMOD_MEMSET(&rmt_lpbk, 0, sizeof(BCMI_MADURA_TLB_TX_RMT_LPBK_CFGr_t)); 4271 switch (loopback) { 4272 case phymodLoopbackGlobal: 4273 if(ip == MADURA_FALCON_CORE) 4274 { 4275 return PHYMOD_E_PARAM; 4276 } 4277 /* coverity[fallthrough] */ 4278 case phymodLoopbackGlobalPMD: 4279 /* Falcon Digital loopback get */ 4280 PHYMOD_IF_ERR_RETURN( 4281 BCMI_MADURA_READ_TLB_RX_DIG_LPBK_CFGr(pa,&dig_lpbk)); 4282 *enable=BCMI_MADURA_TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(dig_lpbk); 4283 break; 4284 case phymodLoopbackRemotePMD: /* Falcon Remote loopback get */ 4285 PHYMOD_IF_ERR_RETURN( 4286 BCMI_MADURA_READ_TLB_TX_RMT_LPBK_CFGr(pa,&rmt_lpbk)); 4287 *enable=BCMI_MADURA_TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(rmt_lpbk); 4288 break; 4289 case phymodLoopbackRemotePCS: 4290 return PHYMOD_E_UNAVAIL; 4291 default: 4292 break; 4293 } 4294 4295 return PHYMOD_E_NONE; 4296 } 4297 4298 int _madura_loopback_get(const phymod_access_t *pa, phymod_loopback_mode_t loopback, uint32_t* enable) 4299 { 4300 phymod_phy_inf_config_t config; 4301 uint16_t ip = 0; 4302 uint16_t lane = 0; 4303 uint16_t lane_mask = 0, max_lane = 0; 4304 4305 *enable = 1; 4306 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4307 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4308 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4309 _madura_phy_interface_config_get(pa, 0, &config))); 4310 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4311 MADURA_GET_IP(pa, config, ip); 4312 4313 max_lane = (ip == MADURA_FALCON_CORE) ? 4314 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4315 4316 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 4317 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 4318 4319 for (lane = 0; lane < max_lane; lane ++) { 4320 if (lane_mask & (1 << lane)) { 4321 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4322 _madura_set_slice_reg (pa, 4323 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4324 4325 /* FALCON core loopback get */ 4326 PHYMOD_DEBUG_VERBOSE(("Falcon loopback get\n")); 4327 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4328 _madura_falcon_lpbk_get(pa, loopback, enable,ip))); 4329 break; 4330 } 4331 } 4332 MADURA_RESET_SLICE(pa, MADURA_DEV_PMA_PMD); 4333 PHYMOD_FREE(config.device_aux_modes); 4334 4335 return PHYMOD_E_NONE; 4336 } 4337 4338 int _madura_falcon_lpbk_set(const phymod_access_t* pa, const phymod_phy_inf_config_t *config, 4339 phymod_loopback_mode_t loopback, uint32_t enable) 4340 { 4341 /*This function sets loop of all types for both sides*/ 4342 uint16_t lane = 0,max_lane=0; 4343 uint16_t ip = 0; 4344 uint32_t fal_2x_lane_mask = 0; 4345 uint32_t fal_lane_mask = 0; 4346 uint32_t main_lane_mask = 0,otherside_lane_mask = 0; 4347 #ifdef DEB 4348 uint32_t data1; 4349 #endif 4350 4351 MADURA_GET_IP(pa, (*config), ip); 4352 max_lane = (ip == MADURA_FALCON_CORE) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4353 4354 PHYMOD_IF_ERR_RETURN( 4355 _madura_fal_2x_falcon_lane_map_get(pa, config, &fal_2x_lane_mask, &fal_lane_mask)); 4356 main_lane_mask = (ip == MADURA_FALCON_CORE) ? fal_lane_mask : fal_2x_lane_mask; 4357 otherside_lane_mask = (ip == MADURA_FALCON_CORE) ? fal_2x_lane_mask : fal_lane_mask; 4358 4359 PHYMOD_DEBUG_VERBOSE(("%s at %d : main_lane_mask=%x otherside_lane_mask=%x\n",__FUNCTION__,__LINE__,main_lane_mask,otherside_lane_mask)); 4360 PHYMOD_DEBUG_VERBOSE(("Falcon loopback set\n")); 4361 4362 switch (loopback) { 4363 case phymodLoopbackGlobal: 4364 if( ip == MADURA_FALCON_CORE) 4365 { 4366 return PHYMOD_E_PARAM; 4367 } 4368 /* coverity[fallthrough] */ 4369 case phymodLoopbackRemotePMD: /* Falcon remote loopback set */ 4370 for(lane = 0; lane < max_lane; lane ++) { 4371 if (main_lane_mask & (1 << lane)) { 4372 PHYMOD_IF_ERR_RETURN( 4373 _madura_set_slice_reg (pa, 4374 ip, MADURA_DEV_PMA_PMD, 4375 lane, 0)); 4376 #ifdef DEB 4377 PHYMOD_BUS_READ(pa,0x1d172,&data1); 4378 printf("[--d172-%x--]\n",data1); 4379 #endif 4380 PHYMOD_IF_ERR_RETURN(falcon2_madura_rmt_lpbk(pa, enable)); 4381 #ifdef DEB 4382 PHYMOD_BUS_READ(pa,0x1d172,&data1); 4383 printf("[--d172-%x--]\n",data1); 4384 #endif 4385 } 4386 } 4387 MADURA_RESET_SLICE(pa, MADURA_DEV_PMA_PMD); 4388 break; 4389 case phymodLoopbackRemotePCS: 4390 return PHYMOD_E_UNAVAIL; 4391 break; 4392 case phymodLoopbackGlobalPMD: /* Falcon digital loopback set */ 4393 { 4394 4395 /*Flipping ip,maxlane and lanemask*/ 4396 for(lane = 0; lane < ((max_lane%8) +4)/*if 4 then 8 and vice versa*/; lane ++) { 4397 if (otherside_lane_mask & (1 << lane)) { 4398 PHYMOD_IF_ERR_RETURN( 4399 _madura_set_slice_reg (pa, 4400 ((ip==0)?1:0), MADURA_DEV_PMA_PMD, lane, 0));/*send toggled value of IP*/ 4401 4402 #ifdef DEB 4403 PHYMOD_BUS_READ(pa,0x1d162,&data1); 4404 printf("[--d162-%x--]\n",data1); 4405 #endif 4406 PHYMOD_IF_ERR_RETURN(falcon2_madura_dig_lpbk_rptr(pa, enable, DATA_IN_SIDE)); 4407 #ifdef DEB 4408 PHYMOD_BUS_READ(pa,0x1d162,&data1); 4409 printf("[+-d162-%x--]\n",data1); 4410 #endif 4411 } 4412 } 4413 MADURA_RESET_SLICE(pa, MADURA_DEV_PMA_PMD); 4414 4415 for(lane = 0; lane < max_lane; lane ++) { 4416 if (main_lane_mask & (1 << lane)) { 4417 PHYMOD_IF_ERR_RETURN( 4418 _madura_set_slice_reg (pa, 4419 ip, MADURA_DEV_PMA_PMD, 4420 lane, 0)); 4421 #ifdef DEB 4422 PHYMOD_BUS_READ(pa,0x1d162,&data1); 4423 printf("[--d162-%x--]\n",data1); 4424 #endif 4425 PHYMOD_IF_ERR_RETURN(falcon2_madura_dig_lpbk_rptr(pa, enable, DIG_LPBK_SIDE)); 4426 /* Disable the prbs_chk_en_auto_mode while seting digital loopback. Below is also not in validation.Keeping for now */ 4427 PHYMOD_IF_ERR_RETURN(wr_falcon2_madura_prbs_chk_en_auto_mode((!enable))); 4428 #ifdef DEB 4429 PHYMOD_BUS_READ(pa,0x1d162,&data1); 4430 printf("[--d162-%x--]\n",data1); 4431 #endif 4432 PHYMOD_IF_ERR_RETURN(wr_falcon2_madura_sdk_tx_disable(enable)); 4433 if (!enable) { 4434 PHYMOD_IF_ERR_RETURN(wr_falcon2_madura_ln_dp_s_rstb(0)); 4435 PHYMOD_USLEEP(10); 4436 PHYMOD_IF_ERR_RETURN(wr_falcon2_madura_ln_dp_s_rstb(1)); 4437 } 4438 } 4439 } 4440 PHYMOD_USLEEP(1000); 4441 4442 MADURA_RESET_SLICE(pa, MADURA_DEV_PMA_PMD); 4443 } 4444 break; 4445 default : 4446 break; 4447 } 4448 4449 return PHYMOD_E_NONE; 4450 } 4451 4452 int _madura_loopback_set(const phymod_access_t *pa, phymod_loopback_mode_t loopback, uint32_t enable) 4453 { 4454 phymod_phy_inf_config_t config; 4455 uint16_t ip = 0; 4456 uint16_t lp_bck_val_misc = 0; 4457 uint16_t data = 0, retry_cnt = 5; 4458 MADURA_DEVICE_AUX_MODE_T aux_mode; 4459 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 4460 uint16_t lane_mask = pa->lane_mask; 4461 BCMI_MADURA_MST_MISC0r_t mst_misc0; 4462 BCMI_MADURA_MST_MISC1r_t mst_misc1; 4463 BCMI_MADURA_MST_MISC2r_t mst_misc2; 4464 BCMI_MADURA_MST_MISC3r_t mst_misc3; 4465 4466 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 4467 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 4468 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 4469 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 4470 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 4471 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4472 config.device_aux_modes = &aux_mode; 4473 PHYMOD_IF_ERR_RETURN( 4474 _madura_phy_interface_config_get(pa, 0, &config)); 4475 MADURA_GET_IP(pa, config, ip); 4476 PHYMOD_DEBUG_VERBOSE(("%s:: IP:%s \n", __func__, 4477 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON")); 4478 4479 PHYMOD_DEBUG_VERBOSE(("madura looopback set\n")); 4480 do { 4481 PHYMOD_IF_ERR_RETURN( 4482 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en)); 4483 data=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 4484 PHYMOD_USLEEP(100); 4485 } while ((data != 0) && (retry_cnt --)); 4486 if (retry_cnt == 0) { 4487 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 4488 (_PHYMOD_MSG("loopback config failed, micro controller is busy.."))); 4489 } 4490 4491 /* FALCON core loopback set */ 4492 PHYMOD_IF_ERR_RETURN( 4493 _madura_falcon_lpbk_set(pa, &config, loopback, enable)); 4494 4495 /* Set bit 1 for loopback change */ 4496 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 4497 PHYMOD_IF_ERR_RETURN( 4498 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 4499 lp_bck_val_misc = BCMI_MADURA_MST_MISC0r_MISC0f_GET(mst_misc0); 4500 lp_bck_val_misc = lp_bck_val_misc | 0x80 ;/*enable loopback as 1*/ 4501 BCMI_MADURA_MST_MISC0r_MISC0f_SET(mst_misc0,lp_bck_val_misc); 4502 PHYMOD_IF_ERR_RETURN( 4503 BCMI_MADURA_WRITE_MST_MISC0r(pa, mst_misc0)); 4504 } else if (lane_mask == 0x2) { 4505 PHYMOD_IF_ERR_RETURN( 4506 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 4507 lp_bck_val_misc = BCMI_MADURA_MST_MISC1r_MISC1f_GET(mst_misc1); 4508 lp_bck_val_misc = lp_bck_val_misc | 0x80 ;/*enable loopback as 1*/ 4509 BCMI_MADURA_MST_MISC1r_MISC1f_SET(mst_misc1,lp_bck_val_misc); 4510 PHYMOD_IF_ERR_RETURN( 4511 BCMI_MADURA_WRITE_MST_MISC1r(pa, mst_misc1)); 4512 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 4513 PHYMOD_IF_ERR_RETURN( 4514 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 4515 lp_bck_val_misc = BCMI_MADURA_MST_MISC2r_MISC2f_GET(mst_misc2); 4516 lp_bck_val_misc = lp_bck_val_misc | 0x80 ;/*enable loopback as 1*/ 4517 BCMI_MADURA_MST_MISC2r_MISC2f_SET(mst_misc2,lp_bck_val_misc); 4518 PHYMOD_IF_ERR_RETURN( 4519 BCMI_MADURA_WRITE_MST_MISC2r(pa, mst_misc2)); 4520 } else { 4521 PHYMOD_IF_ERR_RETURN( 4522 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 4523 lp_bck_val_misc = BCMI_MADURA_MST_MISC3r_MISC3f_GET(mst_misc3); 4524 lp_bck_val_misc = lp_bck_val_misc | 0x80 ;/*enable loopback as 1*/ 4525 BCMI_MADURA_MST_MISC3r_MISC3f_SET(mst_misc3,lp_bck_val_misc); 4526 PHYMOD_IF_ERR_RETURN( 4527 BCMI_MADURA_WRITE_MST_MISC3r(pa, mst_misc3)); 4528 } 4529 4530 /* Set FW_ENABLE = 1 */ 4531 PHYMOD_IF_ERR_RETURN( 4532 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en)); 4533 /* coverity[operator_confusion] */ 4534 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en,1); 4535 PHYMOD_IF_ERR_RETURN( 4536 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en)); 4537 do { 4538 PHYMOD_IF_ERR_RETURN( 4539 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en)); 4540 data=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 4541 PHYMOD_USLEEP(100); 4542 } while ((data != 0) && (retry_cnt --)); 4543 if (retry_cnt == 0) { 4544 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 4545 (_PHYMOD_MSG("loopback config failed, micro controller is busy.."))); 4546 } 4547 4548 return PHYMOD_E_NONE; 4549 } 4550 4551 4552 int _madura_falcon_phy_reset_set(const phymod_access_t *pa, const phymod_phy_reset_t* reset) 4553 { 4554 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_t pwrdwn_ctrl_tx; 4555 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_t pwrdwn_ctrl_rx; 4556 PHYMOD_MEMSET(&pwrdwn_ctrl_tx, 0, sizeof(BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_t)); 4557 PHYMOD_MEMSET(&pwrdwn_ctrl_rx, 0, sizeof(BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_t)); 4558 /* TX AFE Lane Reset */ 4559 switch (reset->tx) { 4560 /* In Reset */ 4561 case phymodResetDirectionIn: 4562 PHYMOD_IF_ERR_RETURN( 4563 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx)); 4564 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRC_VALf_SET(pwrdwn_ctrl_tx,1); 4565 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,1); 4566 PHYMOD_IF_ERR_RETURN( 4567 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx)); 4568 break; 4569 /* Out Reset */ 4570 case phymodResetDirectionOut: 4571 PHYMOD_IF_ERR_RETURN( 4572 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx)); 4573 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRC_VALf_SET(pwrdwn_ctrl_tx,0); 4574 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,1); 4575 PHYMOD_IF_ERR_RETURN( 4576 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx)); 4577 /* -- Releasing forces -- */ 4578 PHYMOD_IF_ERR_RETURN( 4579 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx)); 4580 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,0); 4581 PHYMOD_IF_ERR_RETURN( 4582 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx)); 4583 break; 4584 /* Toggle Reset */ 4585 case phymodResetDirectionInOut: 4586 PHYMOD_IF_ERR_RETURN( 4587 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx)); 4588 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRC_VALf_SET(pwrdwn_ctrl_tx,1); 4589 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,1); 4590 PHYMOD_IF_ERR_RETURN( 4591 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx)); 4592 PHYMOD_USLEEP(10); 4593 PHYMOD_IF_ERR_RETURN( 4594 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx)); 4595 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRC_VALf_SET(pwrdwn_ctrl_tx,0); 4596 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,1); 4597 PHYMOD_IF_ERR_RETURN( 4598 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx)); 4599 /* -- Releasing forces -- */ 4600 PHYMOD_IF_ERR_RETURN( 4601 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx)); 4602 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,0); 4603 PHYMOD_IF_ERR_RETURN( 4604 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx)); 4605 break; 4606 default: 4607 break; 4608 } 4609 /* RX AFE Lane Reset */ 4610 switch (reset->rx) { 4611 /* In Reset */ 4612 case phymodResetDirectionIn: 4613 PHYMOD_IF_ERR_RETURN( 4614 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx)); 4615 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRC_VALf_SET(pwrdwn_ctrl_rx,1); 4616 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,1); 4617 PHYMOD_IF_ERR_RETURN( 4618 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx)); 4619 break; 4620 /* Out Reset */ 4621 case phymodResetDirectionOut: 4622 PHYMOD_IF_ERR_RETURN( 4623 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx)); 4624 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRC_VALf_SET(pwrdwn_ctrl_rx,0); 4625 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,1); 4626 PHYMOD_IF_ERR_RETURN( 4627 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx)); 4628 /* -- Releasing forces -- */ 4629 PHYMOD_IF_ERR_RETURN( 4630 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx)); 4631 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,0); 4632 PHYMOD_IF_ERR_RETURN( 4633 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx)); 4634 break; 4635 /* Toggle Reset */ 4636 case phymodResetDirectionInOut: 4637 PHYMOD_IF_ERR_RETURN( 4638 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx)); 4639 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRC_VALf_SET(pwrdwn_ctrl_rx,1); 4640 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,1); 4641 PHYMOD_IF_ERR_RETURN( 4642 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx)); 4643 PHYMOD_USLEEP(10); 4644 PHYMOD_IF_ERR_RETURN( 4645 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx)); 4646 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRC_VALf_SET(pwrdwn_ctrl_rx,0); 4647 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,1); 4648 PHYMOD_IF_ERR_RETURN( 4649 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx)); 4650 /* -- Releasing forces -- */ 4651 PHYMOD_IF_ERR_RETURN( 4652 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx)); 4653 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,0); 4654 PHYMOD_IF_ERR_RETURN( 4655 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx)); 4656 break; 4657 default: 4658 break; 4659 } 4660 4661 return PHYMOD_E_NONE; 4662 } 4663 4664 4665 int _madura_fal_2x_phy_reset_set(const phymod_access_t *pa, const phymod_phy_reset_t* reset) 4666 { 4667 return PHYMOD_E_NONE; 4668 } 4669 4670 int _madura_phy_reset_set(const phymod_access_t *phy, const phymod_phy_reset_t* reset) 4671 { 4672 phymod_phy_inf_config_t config; 4673 uint16_t ip = 0; 4674 uint16_t lane = 0; 4675 uint16_t lane_mask = 0, max_lane = 0; 4676 4677 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4678 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4679 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4680 _madura_phy_interface_config_get(phy, 0, &config))); 4681 lane_mask = PHYMOD_ACC_LANE_MASK(phy); 4682 MADURA_GET_IP(phy, config, ip); 4683 4684 max_lane = (ip == MADURA_FALCON_CORE) ? 4685 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4686 4687 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 4688 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 4689 4690 4691 for (lane = 0; lane < max_lane; lane ++) { 4692 if (lane_mask & (1 << lane)) { 4693 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4694 _madura_set_slice_reg (phy, 4695 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4696 /* FALCON TX/RX Reset */ 4697 PHYMOD_DEBUG_VERBOSE(("Falcon TX/RX Reset set\n")); 4698 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4699 _madura_falcon_phy_reset_set(phy, reset))); 4700 } 4701 } 4702 4703 MADURA_RESET_SLICE(phy, MADURA_DEV_PMA_PMD); 4704 PHYMOD_FREE(config.device_aux_modes); 4705 4706 return PHYMOD_E_NONE; 4707 } 4708 int _madura_phy_reset_get(const phymod_access_t *pa, phymod_phy_reset_t* reset) 4709 { 4710 phymod_phy_inf_config_t config; 4711 uint16_t ip = 0; 4712 uint16_t rst = 0; 4713 uint16_t lane = 0; 4714 uint16_t lane_mask = 0, max_lane = 0; 4715 BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr_t rx_get; 4716 BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr_t tx_get; 4717 4718 PHYMOD_MEMSET(&rx_get, 0, sizeof(BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr_t)); 4719 PHYMOD_MEMSET(&tx_get, 0, sizeof(BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr_t)); 4720 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4721 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4722 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4723 _madura_phy_interface_config_get(pa, 0, &config))); 4724 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4725 MADURA_GET_IP(pa, config, ip); 4726 4727 max_lane = (ip == MADURA_FALCON_CORE) ? 4728 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4729 4730 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 4731 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 4732 4733 4734 for (lane = 0; lane < max_lane; lane ++) { 4735 if (lane_mask & (1 << lane)) { 4736 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4737 _madura_set_slice_reg (pa, 4738 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4739 /* FALCON TX/RX Reset */ 4740 PHYMOD_DEBUG_VERBOSE(("Falcon TX/RX Reset get\n")); 4741 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4742 BCMI_MADURA_READ_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr(pa,&tx_get))); 4743 rst=BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr_AFE_TX_RESETf_GET(tx_get); 4744 if(rst == 0) { 4745 /* Out of Reset */ 4746 reset->tx = phymodResetDirectionOut; 4747 } else { 4748 /* In Reset */ 4749 reset->tx = phymodResetDirectionIn; 4750 } 4751 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4752 BCMI_MADURA_READ_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr(pa,&rx_get))); 4753 rst=BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr_AFE_RX_RESETf_GET(rx_get); 4754 if(rst == 0) { 4755 /* Out of Reset */ 4756 reset->rx = phymodResetDirectionOut; 4757 } else { 4758 /* In Reset */ 4759 reset->rx = phymodResetDirectionIn; 4760 } 4761 4762 } 4763 } 4764 MADURA_RESET_SLICE(pa, MADURA_DEV_PMA_PMD); 4765 PHYMOD_FREE(config.device_aux_modes); 4766 return PHYMOD_E_NONE; 4767 } 4768 4769 4770 int _madura_force_tx_training_set(const phymod_access_t *pa, uint32_t enable) 4771 { 4772 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 4773 phymod_phy_inf_config_t config; 4774 uint16_t ip = 0; 4775 uint16_t data1 = 0, retry_cnt = MADURA_FORCE_TRAIN_RETRY_CNT; 4776 4777 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4778 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 4779 4780 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4781 4782 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4783 _madura_phy_interface_config_get(pa, 0, &config))); 4784 4785 MADURA_GET_IP(pa, config, ip); 4786 4787 /* Wait for Firmware Ready */ 4788 retry_cnt = MADURA_FORCE_TRAIN_RETRY_CNT; 4789 do { 4790 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4791 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 4792 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 4793 PHYMOD_USLEEP(100); 4794 } while ((data1 != 0) && (retry_cnt --)); 4795 if (retry_cnt == 0) { 4796 PHYMOD_FREE(config.device_aux_modes); 4797 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 4798 (_PHYMOD_MSG("Firmware is busy.."))); 4799 } 4800 4801 /* Set TX training en */ 4802 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4803 _madura_force_training_set(pa, ip, &config, (uint16_t)enable ))); 4804 4805 /* Set FW en */ 4806 /* coverity[operator_confusion] */ 4807 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en, 1); 4808 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4809 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en))); 4810 4811 /* Wait for Firmware Ready */ 4812 retry_cnt = MADURA_FORCE_TRAIN_RETRY_CNT; 4813 do { 4814 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4815 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 4816 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 4817 PHYMOD_USLEEP(100); 4818 } while ((data1 != 0) && (retry_cnt --)); 4819 if (retry_cnt == 0) { 4820 PHYMOD_FREE(config.device_aux_modes); 4821 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 4822 (_PHYMOD_MSG("Firmware is busy.."))); 4823 } 4824 4825 PHYMOD_FREE(config.device_aux_modes); 4826 4827 return PHYMOD_E_NONE; 4828 } 4829 4830 int _madura_force_tx_training_get(const phymod_access_t *pa, uint32_t *enable) 4831 { 4832 phymod_phy_inf_config_t config; 4833 uint16_t ip = 0, training_en = 0; 4834 4835 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4836 4837 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4838 4839 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4840 _madura_phy_interface_config_get(pa, 0, &config))); 4841 MADURA_GET_IP(pa, config, ip); 4842 /* Get TX training en */ 4843 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 4844 _madura_force_training_get(pa, ip, &config, &training_en))); 4845 4846 *enable = training_en ? 1 : 0 ; 4847 4848 PHYMOD_FREE(config.device_aux_modes); 4849 4850 return PHYMOD_E_NONE; 4851 } 4852 4853 int _madura_force_tx_training_status_get(const phymod_access_t *pa, phymod_cl72_status_t* status) 4854 { 4855 4856 phymod_phy_inf_config_t config; 4857 uint16_t ip = 0; 4858 uint16_t lane = 0, max_lane = 0; 4859 uint16_t lane_mask = 0; 4860 BCMI_MADURA_CL93N72_UR_CTL0r_t ur_ctrl0; 4861 BCMI_MADURA_CL93N72_UT_CTL0r_t ut_ctrl0; 4862 BCMI_MADURA_SLICEr_t slice_reg; 4863 4864 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 4865 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4866 PHYMOD_MEMSET(&ur_ctrl0, 0, sizeof(BCMI_MADURA_CL93N72_UR_CTL0r_t)); 4867 PHYMOD_MEMSET(&ut_ctrl0, 0, sizeof(BCMI_MADURA_CL93N72_UT_CTL0r_t)); 4868 4869 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4870 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4871 _madura_phy_interface_config_get(pa, 0, &config))); 4872 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4873 MADURA_GET_IP(pa, config, ip); 4874 4875 max_lane = (ip == MADURA_FALCON_CORE) ? 4876 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4877 4878 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 4879 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 4880 4881 /* init status */ 4882 status->enabled = 0x1; 4883 status->locked = 0x1; 4884 for (lane = 0; lane < max_lane; lane ++) { 4885 if (lane_mask & (1 << lane)) { 4886 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4887 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 4888 4889 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4890 BCMI_MADURA_READ_CL93N72_UR_CTL0r(pa, &ur_ctrl0))); 4891 4892 status->enabled &= 4893 BCMI_MADURA_CL93N72_UR_CTL0r_CL93N72_RX_TRAINING_ENf_GET(ur_ctrl0); 4894 4895 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4896 BCMI_MADURA_READ_CL93N72_UT_CTL0r(pa, &ut_ctrl0))); 4897 4898 status->locked &= 4899 BCMI_MADURA_CL93N72_UT_CTL0r_CL93N72_SW_RX_TRAINEDf_GET(ut_ctrl0); 4900 } 4901 } 4902 4903 PHYMOD_FREE(config.device_aux_modes); 4904 PHYMOD_IF_ERR_RETURN( 4905 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 4906 return PHYMOD_E_NONE; 4907 4908 } 4909 int _madura_phy_status_dump(const phymod_access_t *pa) 4910 { 4911 phymod_phy_inf_config_t config; 4912 uint16_t ip = 0; 4913 uint16_t lane = 0, max_lane = 0; 4914 uint16_t lane_mask = 0; 4915 4916 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4917 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4918 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4919 _madura_phy_interface_config_get(pa, 0, &config))); 4920 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4921 MADURA_GET_IP(pa, config, ip); 4922 4923 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s lanemask:0x%x\n", __func__, 4924 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", lane_mask)); 4925 4926 USR_PRINTF(("**********************************************\n")); 4927 USR_PRINTF(("******* PHY status dump for PHY ID:0x%x ********\n",pa->addr)); 4928 USR_PRINTF(("**********************************************\n")); 4929 USR_PRINTF(("**** PHY status dump for interface side:%d ****\n",ip)); 4930 USR_PRINTF(("***********************************************\n")); 4931 4932 max_lane = (ip == MADURA_FALCON_CORE) ? 4933 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4934 4935 for(lane = 0; lane < max_lane; lane ++) { 4936 if (lane_mask & (1 << lane)) { 4937 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4938 _madura_set_slice_reg (pa, 4939 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4940 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (falcon2_madura_display_core_config(pa))); 4941 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (falcon2_madura_display_core_state(pa))); 4942 break; 4943 } 4944 } 4945 for(lane = 0; lane < max_lane ; lane ++) { 4946 if (lane_mask & (1 << lane)) { 4947 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4948 _madura_set_slice_reg (pa, 4949 ip, MADURA_DEV_PMA_PMD, lane, 0))); 4950 PHYMOD_DEBUG_VERBOSE(("Falcon Status dump\n")); 4951 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (falcon2_madura_display_lane_state_hdr(pa))); 4952 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (falcon2_madura_display_lane_state(pa))); 4953 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (falcon2_madura_display_lane_config(pa))); 4954 } 4955 } 4956 4957 PHYMOD_FREE(config.device_aux_modes); 4958 return PHYMOD_E_NONE; 4959 } 4960 4961 int _madura_tx_enable_set(const phymod_access_t *pa, int16_t enable) 4962 { 4963 4964 phymod_phy_inf_config_t config; 4965 uint16_t ip = 0; 4966 uint16_t lane = 0, max_lane = 0; 4967 uint16_t lane_mask = 0; 4968 BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_t fal_ctrl1; 4969 BCMI_MADURA_SLICEr_t slice_reg; 4970 4971 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 4972 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4973 PHYMOD_MEMSET(&fal_ctrl1, 0, sizeof(BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_t)); 4974 4975 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 4976 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4977 _madura_phy_interface_config_get(pa, 0, &config))); 4978 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4979 MADURA_GET_IP(pa, config, ip); 4980 4981 max_lane = (ip == MADURA_FALCON_CORE) ? 4982 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 4983 4984 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 4985 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 4986 4987 /* TX squelch set with pmd_tx_disable_0_frcval */ 4988 for (lane = 0; lane < max_lane; lane ++) { 4989 if (lane_mask & (1 << lane)) { 4990 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4991 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 4992 4993 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4994 BCMI_MADURA_READ_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, &fal_ctrl1))); 4995 4996 BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_SET(fal_ctrl1, 1); 4997 BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_SET(fal_ctrl1, enable == MADURA_DISABLE ? 1 : 0); 4998 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 4999 BCMI_MADURA_WRITE_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, fal_ctrl1))); 5000 } 5001 } 5002 5003 PHYMOD_FREE(config.device_aux_modes); 5004 PHYMOD_IF_ERR_RETURN( 5005 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5006 5007 return PHYMOD_E_NONE; 5008 } 5009 5010 int _madura_tx_enable_get(const phymod_access_t *pa, int16_t *enable) 5011 { 5012 5013 phymod_phy_inf_config_t config; 5014 uint16_t ip = 0; 5015 uint16_t lane = 0, max_lane = 0; 5016 uint16_t lane_mask = 0; 5017 BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_t fal_ctrl1; 5018 BCMI_MADURA_SLICEr_t slice_reg; 5019 5020 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 5021 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5022 PHYMOD_MEMSET(&fal_ctrl1, 0, sizeof(BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_t)); 5023 5024 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5025 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5026 _madura_phy_interface_config_get(pa, 0, &config))); 5027 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5028 MADURA_GET_IP(pa, config, ip); 5029 5030 max_lane = (ip == MADURA_FALCON_CORE) ? 5031 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 5032 5033 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 5034 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 5035 5036 /* TX squelch get with pmd_tx_disable_0_frcval */ 5037 *enable = MADURA_ENABLE; 5038 for (lane = 0; lane < max_lane; lane ++) { 5039 if (lane_mask & (1 << lane)) { 5040 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5041 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 5042 5043 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5044 BCMI_MADURA_READ_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, &fal_ctrl1))); 5045 5046 if (BCMI_MADURA_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_GET(fal_ctrl1) ) { 5047 *enable = MADURA_DISABLE ; 5048 break; 5049 } 5050 5051 } 5052 } 5053 5054 PHYMOD_FREE(config.device_aux_modes); 5055 PHYMOD_IF_ERR_RETURN( 5056 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5057 5058 return PHYMOD_E_NONE; 5059 } 5060 5061 5062 int _madura_tx_dp_reset(const phymod_access_t *pa) 5063 { 5064 5065 phymod_phy_inf_config_t config; 5066 uint16_t ip = 0; 5067 uint16_t lane = 0, max_lane = 0; 5068 uint16_t lane_mask = 0; 5069 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_t pwrdwn_ctrl_tx; 5070 BCMI_MADURA_SLICEr_t slice_reg; 5071 5072 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 5073 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5074 PHYMOD_MEMSET(&pwrdwn_ctrl_tx, 0, sizeof(pwrdwn_ctrl_tx)); 5075 5076 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5077 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5078 _madura_phy_interface_config_get(pa, 0, &config))); 5079 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5080 MADURA_GET_IP(pa, config, ip); 5081 5082 max_lane = (ip == MADURA_FALCON_CORE) ? 5083 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 5084 5085 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 5086 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 5087 5088 /* TX reset with tx_reset_frcval */ 5089 for (lane = 0; lane < max_lane; lane ++) { 5090 if (lane_mask & (1 << lane)) { 5091 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5092 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 5093 5094 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5095 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx))); 5096 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRC_VALf_SET(pwrdwn_ctrl_tx,1); 5097 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,1); 5098 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5099 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx))); 5100 PHYMOD_USLEEP(10); 5101 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5102 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx))); 5103 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRC_VALf_SET(pwrdwn_ctrl_tx,0); 5104 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,1); 5105 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5106 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx))); 5107 /* -- Releasing forces -- */ 5108 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5109 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,&pwrdwn_ctrl_tx))); 5110 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_TXr_AFE_TX_RESET_FRCf_SET(pwrdwn_ctrl_tx,0); 5111 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5112 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_TXr(pa,pwrdwn_ctrl_tx))); 5113 } 5114 } 5115 5116 PHYMOD_FREE(config.device_aux_modes); 5117 PHYMOD_IF_ERR_RETURN( 5118 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5119 return PHYMOD_E_NONE; 5120 } 5121 5122 int _madura_rx_enable_set(const phymod_access_t *pa, int16_t enable) 5123 { 5124 5125 phymod_phy_inf_config_t config; 5126 uint16_t ip = 0; 5127 uint16_t lane = 0, max_lane = 0; 5128 uint16_t lane_mask = 0; 5129 BCMI_MADURA_SIGDET_CTL1r_t fal_ctrl1; 5130 BCMI_MADURA_SLICEr_t slice_reg; 5131 5132 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 5133 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5134 PHYMOD_MEMSET(&fal_ctrl1, 0, sizeof(BCMI_MADURA_SIGDET_CTL1r_t)); 5135 5136 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5137 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5138 _madura_phy_interface_config_get(pa, 0, &config))); 5139 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5140 MADURA_GET_IP(pa, config, ip); 5141 5142 max_lane = (ip == MADURA_FALCON_CORE) ? 5143 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 5144 5145 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 5146 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 5147 5148 /* TX squelch set with pmd_tx_disable_0_frcval */ 5149 for (lane = 0; lane < max_lane; lane ++) { 5150 if (lane_mask & (1 << lane)) { 5151 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5152 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 5153 5154 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5155 BCMI_MADURA_READ_SIGDET_CTL1r(pa, &fal_ctrl1))); 5156 5157 BCMI_MADURA_SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(fal_ctrl1, 1); 5158 BCMI_MADURA_SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(fal_ctrl1, enable == MADURA_DISABLE ? 0 : 1); 5159 5160 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5161 BCMI_MADURA_WRITE_SIGDET_CTL1r(pa, fal_ctrl1))); 5162 } 5163 } 5164 5165 PHYMOD_FREE(config.device_aux_modes); 5166 PHYMOD_IF_ERR_RETURN( 5167 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5168 return PHYMOD_E_NONE; 5169 } 5170 5171 int _madura_rx_enable_get(const phymod_access_t *pa, int16_t *enable) 5172 { 5173 5174 phymod_phy_inf_config_t config; 5175 uint16_t ip = 0; 5176 uint16_t lane = 0, max_lane = 0; 5177 uint16_t lane_mask = 0; 5178 BCMI_MADURA_SIGDET_CTL1r_t fal_ctrl1; 5179 BCMI_MADURA_SLICEr_t slice_reg; 5180 5181 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 5182 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5183 PHYMOD_MEMSET(&fal_ctrl1, 0, sizeof(BCMI_MADURA_SIGDET_CTL1r_t)); 5184 5185 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5186 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5187 _madura_phy_interface_config_get(pa, 0, &config))); 5188 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5189 MADURA_GET_IP(pa, config, ip); 5190 5191 max_lane = (ip == MADURA_FALCON_CORE) ? 5192 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 5193 5194 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 5195 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 5196 5197 /* RX _frcval */ 5198 *enable = MADURA_ENABLE; 5199 for (lane = 0; lane < max_lane; lane ++) { 5200 if (lane_mask & (1 << lane)) { 5201 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5202 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 5203 5204 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5205 BCMI_MADURA_READ_SIGDET_CTL1r(pa, &fal_ctrl1))); 5206 5207 if( 5208 (BCMI_MADURA_SIGDET_CTL1r_SIGNAL_DETECT_FRCf_GET(fal_ctrl1)==1)&& 5209 (BCMI_MADURA_SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_GET(fal_ctrl1)==0)) { 5210 *enable = MADURA_DISABLE; 5211 break; 5212 } 5213 } 5214 } 5215 5216 PHYMOD_FREE(config.device_aux_modes); 5217 PHYMOD_IF_ERR_RETURN( 5218 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5219 return PHYMOD_E_NONE; 5220 } 5221 5222 int _madura_rx_dp_reset(const phymod_access_t *pa) 5223 { 5224 5225 phymod_phy_inf_config_t config; 5226 uint16_t ip = 0; 5227 uint16_t lane = 0, max_lane = 0; 5228 uint16_t lane_mask = 0; 5229 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_t pwrdwn_ctrl_rx; 5230 BCMI_MADURA_SLICEr_t slice_reg; 5231 5232 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 5233 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5234 PHYMOD_MEMSET(&pwrdwn_ctrl_rx, 0, sizeof(pwrdwn_ctrl_rx)); 5235 5236 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5237 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5238 _madura_phy_interface_config_get(pa, 0, &config))); 5239 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5240 MADURA_GET_IP(pa, config, ip); 5241 5242 max_lane = (ip == MADURA_FALCON_CORE) ? 5243 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 5244 5245 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 5246 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 5247 5248 /* RX reset with rx_reset_frcval */ 5249 for (lane = 0; lane < max_lane; lane ++) { 5250 if (lane_mask & (1 << lane)) { 5251 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5252 _madura_set_slice_reg (pa, ip, MADURA_DEV_PMA_PMD, lane, 0))); 5253 5254 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5255 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx))); 5256 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRC_VALf_SET(pwrdwn_ctrl_rx,1); 5257 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,1); 5258 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5259 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx))); 5260 PHYMOD_USLEEP(10); 5261 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5262 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx))); 5263 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRC_VALf_SET(pwrdwn_ctrl_rx,0); 5264 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,1); 5265 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5266 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx))); 5267 /* -- Releasing forces -- */ 5268 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5269 BCMI_MADURA_READ_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,&pwrdwn_ctrl_rx))); 5270 BCMI_MADURA_LN_AFE_RST_PWRDWN_CTL_CTL_RXr_AFE_RX_RESET_FRCf_SET(pwrdwn_ctrl_rx,0); 5271 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5272 BCMI_MADURA_WRITE_LN_AFE_RST_PWRDWN_CTL_CTL_RXr(pa,pwrdwn_ctrl_rx))); 5273 } 5274 } 5275 5276 PHYMOD_FREE(config.device_aux_modes); 5277 PHYMOD_IF_ERR_RETURN( 5278 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5279 return PHYMOD_E_NONE; 5280 } 5281 5282 5283 int _madura_tx_lane_control_set(const phymod_access_t *pa, phymod_phy_tx_lane_control_t tx_control) 5284 { 5285 switch (tx_control) { 5286 case phymodTxTrafficDisable: /* disable tx traffic */ 5287 case phymodTxTrafficEnable: /* enable tx traffic */ 5288 return PHYMOD_E_UNAVAIL; 5289 case phymodTxReset: /* reset tx data path */ 5290 PHYMOD_IF_ERR_RETURN(_madura_tx_dp_reset(pa)); 5291 break; 5292 case phymodTxSquelchOn: /* squelch tx */ 5293 PHYMOD_IF_ERR_RETURN(_madura_tx_enable_set(pa, MADURA_DISABLE)); 5294 break; 5295 case phymodTxSquelchOff: /* squelch tx off */ 5296 PHYMOD_IF_ERR_RETURN(_madura_tx_enable_set(pa, MADURA_ENABLE)); 5297 break; 5298 default: 5299 return PHYMOD_E_PARAM; 5300 } 5301 return PHYMOD_E_NONE; 5302 } 5303 int _madura_rx_lane_control_set(const phymod_access_t *pa, phymod_phy_rx_lane_control_t rx_control) 5304 { 5305 switch (rx_control) { 5306 case phymodRxReset: /* reset rx data path */ 5307 PHYMOD_IF_ERR_RETURN(_madura_rx_dp_reset(pa)); 5308 break; 5309 case phymodRxSquelchOn: /* squelch rx */ 5310 PHYMOD_IF_ERR_RETURN(_madura_rx_enable_set(pa, MADURA_DISABLE)); 5311 break; 5312 case phymodRxSquelchOff: /* squelch rx off */ 5313 PHYMOD_IF_ERR_RETURN(_madura_rx_enable_set(pa, MADURA_ENABLE)); 5314 break; 5315 default: 5316 return PHYMOD_E_PARAM; 5317 } 5318 return PHYMOD_E_NONE; 5319 } 5320 5321 int _madura_tx_lane_control_get(const phymod_access_t *pa, phymod_phy_tx_lane_control_t *tx_control) 5322 { 5323 int16_t tx_ctrl = 0; 5324 switch (*tx_control) { 5325 case phymodTxTrafficDisable: /* disable tx traffic */ 5326 case phymodTxTrafficEnable: /* enable tx traffic */ 5327 case phymodTxReset: /* reset tx data path */ 5328 return PHYMOD_E_UNAVAIL; 5329 break; 5330 case phymodTxSquelchOn: /* squelch tx */ 5331 PHYMOD_IF_ERR_RETURN(_madura_tx_enable_get(pa, &tx_ctrl)); 5332 *tx_control = tx_ctrl ? phymodTxSquelchOff: phymodTxSquelchOn; 5333 break; 5334 case phymodTxSquelchOff: /* squelch tx off */ 5335 PHYMOD_IF_ERR_RETURN(_madura_tx_enable_get(pa, &tx_ctrl)); 5336 *tx_control = tx_ctrl ? phymodTxSquelchOff: phymodTxSquelchOn; 5337 break; 5338 default: 5339 return PHYMOD_E_PARAM; 5340 } 5341 return PHYMOD_E_NONE; 5342 } 5343 int _madura_rx_lane_control_get(const phymod_access_t *pa, phymod_phy_rx_lane_control_t *rx_control) 5344 { 5345 int16_t rx_ctrl = 0; 5346 switch (*rx_control) { 5347 case phymodRxReset: /* reset rx data path */ 5348 return PHYMOD_E_UNAVAIL; 5349 case phymodRxSquelchOn: /* squelch rx */ 5350 PHYMOD_IF_ERR_RETURN(_madura_rx_enable_get(pa, &rx_ctrl)); 5351 *rx_control = rx_ctrl ? phymodRxSquelchOff: phymodRxSquelchOn; 5352 break; 5353 case phymodRxSquelchOff: /* squelch rx off */ 5354 PHYMOD_IF_ERR_RETURN(_madura_rx_enable_get(pa, &rx_ctrl)); 5355 *rx_control = rx_ctrl ? phymodRxSquelchOff: phymodRxSquelchOn; 5356 break; 5357 default: 5358 return PHYMOD_E_PARAM; 5359 } 5360 return PHYMOD_E_NONE; 5361 } 5362 5363 5364 int _madura_config_hcd_link_sts (const phymod_access_t* pa, phymod_phy_inf_config_t config, uint16_t ip, uint16_t port ) 5365 { 5366 BCMI_MADURA_ANARXCTL3r_t ana_rxctl3; 5367 5368 PHYMOD_MEMSET(&ana_rxctl3, 0, sizeof(BCMI_MADURA_ANARXCTL3r_t)); 5369 5370 if (pa->lane_mask & 0xF) { 5371 PHYMOD_IF_ERR_RETURN( 5372 _madura_set_slice_an_reg (pa,ip, 5373 MADURA_DEV_AN, 0, port)); 5374 } else { 5375 PHYMOD_IF_ERR_RETURN( 5376 _madura_set_slice_an_reg (pa,ip, 5377 MADURA_DEV_AN, 4, port)); 5378 } 5379 5380 /* HCD_LINK_REG_WR */ 5381 PHYMOD_IF_ERR_RETURN( 5382 BCMI_MADURA_READ_ANARXCTL3r(pa,&ana_rxctl3)); 5383 BCMI_MADURA_ANARXCTL3r_USE_KR4_PMD_LOCK_SMf_SET(ana_rxctl3,1); 5384 PHYMOD_IF_ERR_RETURN( 5385 BCMI_MADURA_WRITE_ANARXCTL3r(pa,ana_rxctl3)); 5386 5387 return PHYMOD_E_NONE; 5388 } 5389 5390 int _madura_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 5391 { 5392 const phymod_access_t* pa = &phy->access; 5393 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 5394 phymod_phy_inf_config_t config; 5395 uint16_t ip = 0; 5396 uint16_t data1 = 0, retry_cnt = MADURA_AN_SET_RETRY_CNT; 5397 5398 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5399 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 5400 5401 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5402 5403 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5404 _madura_phy_interface_config_get(pa, 0, &config))); 5405 5406 MADURA_GET_IP(pa, config, ip); 5407 5408 if (ip == MADURA_FALCON_CORE) { 5409 PHYMOD_FREE(config.device_aux_modes); 5410 /* AN can performed only on line side */ 5411 return PHYMOD_E_PARAM; 5412 } 5413 5414 if (an->an_mode != phymod_AN_MODE_CL73) { 5415 PHYMOD_FREE(config.device_aux_modes); 5416 /* AN mode not supported */ 5417 return PHYMOD_E_PARAM; 5418 } 5419 5420 /* Wait for Firmware Ready */ 5421 retry_cnt = MADURA_AN_SET_RETRY_CNT; 5422 do { 5423 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5424 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 5425 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 5426 PHYMOD_USLEEP(100); 5427 } while ((data1 != 0) && (retry_cnt --)); 5428 if (retry_cnt == 0) { 5429 PHYMOD_FREE(config.device_aux_modes); 5430 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 5431 (_PHYMOD_MSG("Firmware is busy.."))); 5432 } 5433 5434 /* Set AN en */ 5435 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5436 _madura_autoneg_set_val(pa, ip, &config, an->enable ? 1 : 0))); 5437 5438 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5439 _madura_udms_config(phy, &config, 5440 an->enable ? MADURA_AN_CL73 : MADURA_AN_NONE))); 5441 5442 /* Set FW en */ 5443 /* coverity[operator_confusion] */ 5444 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en, 1); 5445 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5446 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en))); 5447 5448 /* Wait for Firmware Ready */ 5449 retry_cnt = MADURA_AN_SET_RETRY_CNT; 5450 do { 5451 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5452 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 5453 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 5454 PHYMOD_USLEEP(100); 5455 } while ((data1 != 0) && (retry_cnt --)); 5456 if (retry_cnt == 0) { 5457 PHYMOD_FREE(config.device_aux_modes); 5458 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 5459 (_PHYMOD_MSG("Firmware is busy.."))); 5460 } 5461 5462 PHYMOD_FREE(config.device_aux_modes); 5463 return PHYMOD_E_NONE; 5464 } 5465 5466 int _madura_autoneg_get(const phymod_access_t* pa, phymod_autoneg_control_t* an, uint32_t *an_done) 5467 { 5468 BCMI_MADURA_AN_STSr_t an_status; 5469 phymod_phy_inf_config_t config; 5470 uint16_t ip = 0, an_enable = 0; 5471 uint16_t port = 0, physical_port = 0; 5472 5473 /* Init default values */ 5474 an->enable = 0; 5475 *an_done = 0; 5476 5477 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5478 PHYMOD_MEMSET(&an_status, 0, sizeof(BCMI_MADURA_AN_STSr_t)); 5479 5480 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5481 5482 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5483 _madura_phy_interface_config_get(pa, 0, &config))); 5484 5485 MADURA_GET_IP(pa, config, ip); 5486 5487 if (ip == MADURA_FALCON_CORE) { 5488 PHYMOD_FREE(config.device_aux_modes); 5489 /* AN can performed only on line side */ 5490 return PHYMOD_E_PARAM; 5491 } 5492 5493 /* Get AN en */ 5494 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5495 _madura_autoneg_get_val(pa, ip, &config, &an_enable ))); 5496 5497 /* Get AN en */ 5498 an->enable = an_enable ? 1 : 0 ; 5499 5500 /* AN Mode */ 5501 an->an_mode = phymod_AN_MODE_CL73; 5502 5503 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5504 _madura_port_from_lane_map_get(pa, &config, &port, &physical_port))); 5505 if (pa->lane_mask & 0xF) { 5506 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5507 _madura_set_slice_an_reg (pa,ip, 5508 MADURA_DEV_AN, 0, physical_port))); 5509 } else { 5510 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5511 _madura_set_slice_an_reg (pa,ip, 5512 MADURA_DEV_AN, 4, physical_port))); 5513 } 5514 5515 5516 /* AN done */ 5517 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5518 BCMI_MADURA_READ_AN_STSr(pa, &an_status))); 5519 5520 *an_done = 5521 BCMI_MADURA_AN_STSr_AUTO_NEGOTIATIONCOMPLETEf_GET(an_status) ? 1 : 0; 5522 5523 5524 PHYMOD_FREE(config.device_aux_modes); 5525 5526 return PHYMOD_E_NONE; 5527 } 5528 5529 int _madura_autoneg_ability_set(const phymod_access_t* pa, madura_an_ability_t *an_ability) 5530 { 5531 phymod_phy_inf_config_t config; 5532 uint16_t ip = 0, port = 0, physical_port = 0; 5533 BCMI_MADURA_AN_ADVERTISEMENT1r_t adv1; 5534 BCMI_MADURA_AN_ADVERTISEMENT2r_t adv2; 5535 BCMI_MADURA_AN_ADVERTISEMENT3r_t adv3; 5536 BCMI_MADURA_AN_SLICEr_t slice_reg; 5537 BCMI_MADURA_P0_MODE_CTLr_t p0_ctl; 5538 BCMI_MADURA_P2_MODE_CTLr_t p2_ctl; 5539 5540 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_AN_SLICEr_t)); 5541 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5542 PHYMOD_MEMSET(&adv1, 0, sizeof(BCMI_MADURA_AN_ADVERTISEMENT1r_t)); 5543 PHYMOD_MEMSET(&adv2, 0, sizeof(BCMI_MADURA_AN_ADVERTISEMENT2r_t)); 5544 PHYMOD_MEMSET(&adv3, 0, sizeof(BCMI_MADURA_AN_ADVERTISEMENT3r_t)); 5545 PHYMOD_MEMSET(&p0_ctl, 0, sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 5546 PHYMOD_MEMSET(&p2_ctl, 0, sizeof(BCMI_MADURA_P2_MODE_CTLr_t)); 5547 5548 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5549 5550 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5551 _madura_phy_interface_config_get(pa, 0, &config))); 5552 5553 5554 MADURA_GET_IP(pa, config, ip); 5555 5556 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5557 _madura_port_from_lane_map_get(pa, &config, &port, &physical_port))); 5558 5559 if (ip == MADURA_FALCON_CORE) { 5560 PHYMOD_FREE(config.device_aux_modes); 5561 /* AN can performed only on line side */ 5562 return PHYMOD_E_PARAM; 5563 } 5564 if (pa->lane_mask & 0xF) { 5565 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5566 _madura_set_slice_an_reg (pa, 5567 ip, MADURA_DEV_AN, 0, physical_port))); 5568 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (BCMI_MADURA_READ_P0_MODE_CTLr(pa, &p0_ctl))); 5569 if (an_ability->an_master_lane < 4) { 5570 BCMI_MADURA_P0_MODE_CTLr_P0_LALf_SET(p0_ctl, an_ability->an_master_lane); 5571 } 5572 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (BCMI_MADURA_WRITE_P0_MODE_CTLr(pa, p0_ctl))); 5573 } else { 5574 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5575 _madura_set_slice_an_reg (pa, 5576 ip, MADURA_DEV_AN, 4 , physical_port))); 5577 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (BCMI_MADURA_READ_P2_MODE_CTLr(pa, &p2_ctl))); 5578 if (an_ability->an_master_lane < 4) { 5579 BCMI_MADURA_P2_MODE_CTLr_P2_LALf_SET(p2_ctl, an_ability->an_master_lane); 5580 } 5581 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, (BCMI_MADURA_WRITE_P2_MODE_CTLr(pa, p2_ctl))); 5582 5583 } 5584 5585 5586 /* Adv1 */ 5587 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5588 BCMI_MADURA_READ_AN_ADVERTISEMENT1r(pa, &adv1))); 5589 5590 BCMI_MADURA_AN_ADVERTISEMENT1r_PAUSEf_SET(adv1, 5591 an_ability->cl73_adv.an_pause); 5592 5593 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5594 BCMI_MADURA_WRITE_AN_ADVERTISEMENT1r(pa, adv1))); 5595 5596 /* Adv2 */ 5597 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5598 BCMI_MADURA_READ_AN_ADVERTISEMENT2r(pa, &adv2))); 5599 5600 BCMI_MADURA_AN_ADVERTISEMENT2r_TECHABILITYf_SET( 5601 adv2, 5602 an_ability->cl73_adv.an_base_speed); 5603 5604 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5605 BCMI_MADURA_WRITE_AN_ADVERTISEMENT2r(pa, adv2))); 5606 5607 /* Adv3 */ 5608 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5609 BCMI_MADURA_READ_AN_ADVERTISEMENT3r(pa, &adv3))); 5610 5611 BCMI_MADURA_AN_ADVERTISEMENT3r_FEC_REQUESTEDf_SET( 5612 adv3, 5613 an_ability->cl73_adv.an_fec); 5614 5615 BCMI_MADURA_AN_ADVERTISEMENT3r_AN_ADV_D45_D32f_SET(adv3, 0); 5616 5617 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5618 BCMI_MADURA_WRITE_AN_ADVERTISEMENT3r(pa, adv3))); 5619 5620 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5621 _madura_config_hcd_link_sts (pa, config, ip, physical_port))); 5622 5623 PHYMOD_FREE(config.device_aux_modes); 5624 5625 PHYMOD_IF_ERR_RETURN( 5626 BCMI_MADURA_WRITE_AN_SLICEr(pa,slice_reg)); 5627 5628 return PHYMOD_E_NONE; 5629 } 5630 5631 int _madura_autoneg_ability_get(const phymod_access_t* pa, madura_an_ability_t *an_ability) 5632 { 5633 phymod_phy_inf_config_t config; 5634 uint16_t ip = 0, port = 0, physical_port = 0 ; 5635 BCMI_MADURA_AN_ADVERTISEMENT1r_t adv1; 5636 BCMI_MADURA_AN_ADVERTISEMENT2r_t adv2; 5637 BCMI_MADURA_AN_ADVERTISEMENT3r_t adv3; 5638 BCMI_MADURA_AN_SLICEr_t slice_reg; 5639 BCMI_MADURA_P0_MODE_CTLr_t p0_mod; 5640 BCMI_MADURA_P2_MODE_CTLr_t p2_mod; 5641 5642 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_AN_SLICEr_t)); 5643 PHYMOD_MEMSET(&p0_mod, 0 , sizeof(BCMI_MADURA_P0_MODE_CTLr_t)); 5644 PHYMOD_MEMSET(&p2_mod, 0 , sizeof(BCMI_MADURA_P2_MODE_CTLr_t)); 5645 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5646 PHYMOD_MEMSET(&adv1, 0, sizeof(BCMI_MADURA_AN_ADVERTISEMENT1r_t)); 5647 PHYMOD_MEMSET(&adv2, 0, sizeof(BCMI_MADURA_AN_ADVERTISEMENT2r_t)); 5648 PHYMOD_MEMSET(&adv3, 0, sizeof(BCMI_MADURA_AN_ADVERTISEMENT3r_t)); 5649 5650 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5651 5652 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5653 _madura_phy_interface_config_get(pa, 0, &config))); 5654 5655 MADURA_GET_IP(pa, config, ip); 5656 5657 if (ip == MADURA_FALCON_CORE) { 5658 PHYMOD_FREE(config.device_aux_modes); 5659 /* AN can performed only on line side */ 5660 return PHYMOD_E_PARAM; 5661 } 5662 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5663 _madura_port_from_lane_map_get(pa, &config, &port, &physical_port))); 5664 5665 if (pa->lane_mask & 0xF) { 5666 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5667 _madura_set_slice_an_reg (pa, 5668 ip, MADURA_DEV_AN, 0, physical_port ))); 5669 } else { 5670 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5671 _madura_set_slice_an_reg (pa, 5672 ip, MADURA_DEV_AN, 0, physical_port ))); 5673 } 5674 5675 5676 /* Adv1 */ 5677 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5678 BCMI_MADURA_READ_AN_ADVERTISEMENT1r(pa, &adv1))); 5679 5680 an_ability->cl73_adv.an_pause = 5681 BCMI_MADURA_AN_ADVERTISEMENT1r_PAUSEf_GET(adv1); 5682 5683 /* Adv2 */ 5684 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5685 BCMI_MADURA_READ_AN_ADVERTISEMENT2r(pa, &adv2))); 5686 5687 an_ability->cl73_adv.an_base_speed = 5688 BCMI_MADURA_AN_ADVERTISEMENT2r_TECHABILITYf_GET(adv2); 5689 5690 /* Adv3 */ 5691 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5692 BCMI_MADURA_READ_AN_ADVERTISEMENT3r(pa, &adv3))); 5693 5694 an_ability->cl73_adv.an_fec = 5695 BCMI_MADURA_AN_ADVERTISEMENT3r_FEC_REQUESTEDf_GET(adv3); 5696 if (pa->lane_mask & 0xF) { 5697 if (an_ability->an_master_lane < 4) { 5698 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5699 BCMI_MADURA_READ_P0_MODE_CTLr(pa,&p0_mod))); 5700 an_ability->an_master_lane = BCMI_MADURA_P0_MODE_CTLr_P0_LALf_GET(p0_mod); 5701 } 5702 } else { 5703 if (an_ability->an_master_lane < 4) { 5704 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5705 BCMI_MADURA_READ_P2_MODE_CTLr(pa,&p2_mod))); 5706 an_ability->an_master_lane = BCMI_MADURA_P2_MODE_CTLr_P2_LALf_GET(p2_mod); 5707 } 5708 } 5709 5710 PHYMOD_FREE(config.device_aux_modes); 5711 5712 PHYMOD_IF_ERR_RETURN( 5713 BCMI_MADURA_WRITE_AN_SLICEr(pa,slice_reg)); 5714 5715 return PHYMOD_E_NONE; 5716 } 5717 5718 5719 int _madura_autoneg_remote_ability_get( 5720 const phymod_access_t *pa, 5721 phymod_autoneg_ability_t* an_ability) 5722 { 5723 5724 phymod_phy_inf_config_t config; 5725 uint16_t ip = 0, port = 0, physical_port = 0; 5726 BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_1r_t adv1; 5727 BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_2r_t adv2; 5728 BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_3r_t adv3; 5729 BCMI_MADURA_AN_SLICEr_t slice_reg; 5730 5731 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_AN_SLICEr_t)); 5732 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5733 PHYMOD_MEMSET(&adv1, 0, sizeof(BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_1r_t)); 5734 PHYMOD_MEMSET(&adv2, 0, sizeof(BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_2r_t)); 5735 PHYMOD_MEMSET(&adv3, 0, sizeof(BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_3r_t)); 5736 5737 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5738 5739 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5740 _madura_phy_interface_config_get(pa, 0, &config))); 5741 5742 MADURA_GET_IP(pa, config, ip); 5743 5744 if (ip == MADURA_FALCON_CORE) { 5745 PHYMOD_FREE(config.device_aux_modes); 5746 /* AN can performed only on line side */ 5747 return PHYMOD_E_PARAM; 5748 } 5749 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 5750 _madura_port_from_lane_map_get(pa, &config, &port, &physical_port))); 5751 5752 if (pa->lane_mask & 0xF) { 5753 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5754 _madura_set_slice_an_reg (pa, 5755 ip, MADURA_DEV_AN, 0 , physical_port))); 5756 } else { 5757 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5758 _madura_set_slice_an_reg (pa, 5759 ip, MADURA_DEV_AN, 4 , physical_port))); 5760 } 5761 5762 /* Adv1 */ 5763 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5764 BCMI_MADURA_READ_AN_LP_BASE_PAGE_ABIL_1r(pa, &adv1))); 5765 5766 if (BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_1r_D15_D0f_GET(adv1) & 0x400) { 5767 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability); 5768 } else if (BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_1r_D15_D0f_GET(adv1) & 0x800) { 5769 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability); 5770 } 5771 5772 5773 /* Adv2 */ 5774 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5775 BCMI_MADURA_READ_AN_LP_BASE_PAGE_ABIL_2r(pa, &adv2))); 5776 5777 switch ((BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_2r_GET(adv2) & 0xFFE0) >> 5) { 5778 case MADURA_CL73_40GBASE_CR4: 5779 PHYMOD_AN_CAP_40G_CR4_SET(an_ability->an_cap); 5780 break; 5781 case MADURA_CL73_40GBASE_KR4: 5782 PHYMOD_AN_CAP_40G_KR4_SET(an_ability->an_cap); 5783 break; 5784 case MADURA_CL73_100GBASE_CR4: 5785 PHYMOD_AN_CAP_100G_CR4_SET(an_ability->an_cap); 5786 break; 5787 case MADURA_CL73_100GBASE_KR4: 5788 PHYMOD_AN_CAP_100G_KR4_SET(an_ability->an_cap); 5789 break; 5790 default: 5791 break; 5792 } 5793 5794 /* Adv3 */ 5795 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5796 BCMI_MADURA_READ_AN_LP_BASE_PAGE_ABIL_3r(pa, &adv3))); 5797 5798 an_ability->an_fec = 5799 (BCMI_MADURA_AN_LP_BASE_PAGE_ABIL_3r_GET(adv3) & 0xC000 ) >> 15 ; 5800 5801 PHYMOD_FREE(config.device_aux_modes); 5802 5803 PHYMOD_IF_ERR_RETURN( 5804 BCMI_MADURA_WRITE_AN_SLICEr(pa, slice_reg)); 5805 5806 return PHYMOD_E_NONE; 5807 } 5808 5809 int _madura_port_from_lane_map_get(const phymod_access_t *pa, const phymod_phy_inf_config_t* cfg, uint16_t *port, uint16_t *physical_port) 5810 { 5811 phymod_phy_inf_config_t config; 5812 uint16_t ip = 0; 5813 uint16_t lane_mask = 0; 5814 MADURA_DEVICE_AUX_MODE_T *aux_mode; 5815 5816 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5817 PHYMOD_MEMCPY(&config, cfg, sizeof(phymod_phy_inf_config_t)); 5818 aux_mode = (MADURA_DEVICE_AUX_MODE_T*)cfg->device_aux_modes; 5819 MADURA_GET_IP(pa, config, ip); 5820 5821 PHYMOD_DEBUG_VERBOSE(("%s:: IP:%s \n", __func__, 5822 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON")); 5823 5824 if (config.data_rate == MADURA_SPD_100G || 5825 config.data_rate == MADURA_SPD_106G) { 5826 *port = 0; 5827 *physical_port = 0; 5828 } else if (config.data_rate == MADURA_SPD_40G || config.data_rate == MADURA_SPD_50G || 5829 config.data_rate == MADURA_SPD_42G) { 5830 if (ip == MADURA_FALCON_CORE) { 5831 if (aux_mode->pass_thru_dual_lane ){ 5832 if (lane_mask == 0x3) { /* port 0 */ 5833 *port = 0; 5834 } else if (lane_mask == 0xC) { /* port 1 */ 5835 *port = 1; 5836 } 5837 } else if (aux_mode->pass_thru ){ 5838 if (lane_mask == 0xF) { /*port 0 */ 5839 *port = 0; 5840 } 5841 } else { /* 40G MUX */ 5842 if (lane_mask == 0x3) { /* port 0 */ 5843 *port = 0; 5844 } else if (lane_mask == 0xC) { /* port 1 */ 5845 *port = 1; 5846 } 5847 } 5848 } else {/*Line side*/ 5849 if (aux_mode->pass_thru_dual_lane ){ 5850 if (!aux_mode->alternate){ 5851 if (lane_mask == 0x3) { /* port 0 */ 5852 *port = 0; 5853 *physical_port = 0; 5854 } else if (lane_mask == 0xC) { /* port 1 */ 5855 *port = 1; 5856 *physical_port = 2; 5857 } 5858 } else { 5859 if (lane_mask == 0x30) { /* port 0 */ 5860 *port = 0; 5861 *physical_port = 0; 5862 } else if (lane_mask == 0xC0) { /* port 1 */ 5863 *port = 1; 5864 *physical_port = 2; 5865 } 5866 } 5867 } else if (aux_mode->pass_thru ) { 5868 if (lane_mask == 0xf0) { /* port 0 . alternate*/ 5869 *port = 0; 5870 *physical_port = 0; 5871 } 5872 else if (lane_mask == 0xF) { /* port 0 */ 5873 *port = 0; 5874 *physical_port = 0; 5875 } 5876 } else { /* 40G MUX */ 5877 if (lane_mask == 0xF) { /* port 0 */ 5878 *port = 0; 5879 *physical_port = 0; 5880 } else if (lane_mask == 0xF0) { /* port 1 */ 5881 *port = 1; 5882 *physical_port = 2; 5883 } 5884 } 5885 } 5886 } else /* 10G/11G if (config.data_rate == MADURA_SPD_10G)*/ { 5887 if (ip == MADURA_FALCON_CORE) { 5888 if (lane_mask == 0x1) { /* port 0 */ 5889 *port = 0; 5890 } else if (lane_mask == 0x2) { /* port 1 */ 5891 *port = 1; 5892 } else if (lane_mask == 0x4) { /* port 2 */ 5893 *port = 2; 5894 } else if (lane_mask == 0x8) { /* port 3 */ 5895 *port = 3; 5896 } 5897 } else { 5898 if (lane_mask == 0x1) { /* port 0 */ 5899 *port = 0; 5900 } else if (lane_mask == 0x2) { /* port 1 */ 5901 *port = 1; 5902 } else if (lane_mask == 0x4) { /* port 2 */ 5903 *port = 2; 5904 } else if (lane_mask == 0x8) { /* port 3 */ 5905 *port = 3; 5906 } else if ((lane_mask == 0x10) && (aux_mode->alternate)){ 5907 *port = 0; 5908 } else if ((lane_mask == 0x20) && (aux_mode->alternate)){ 5909 *port = 1; 5910 } else if ((lane_mask == 0x40) && (aux_mode->alternate)){ 5911 *port = 2; 5912 } else if ((lane_mask == 0x80) && (aux_mode->alternate)){ 5913 *port = 3; 5914 } 5915 } 5916 } 5917 5918 return PHYMOD_E_NONE; 5919 } 5920 5921 int _madura_tx_rx_polarity_set(const phymod_access_t *pa, uint32_t tx_polarity, uint32_t rx_polarity) 5922 { 5923 BCMI_MADURA_SLICEr_t slice_reg; 5924 BCMI_MADURA_TLB_TX_TLB_TX_MISC_CFGr_t tx_pl_cfg; 5925 BCMI_MADURA_TLB_RX_TLB_RX_MISC_CFGr_t rx_pl_cfg; 5926 phymod_phy_inf_config_t config; 5927 uint16_t ip = 0,intf_side=0; 5928 uint16_t lane = 0; 5929 uint16_t lane_mask = 0, max_lane = 0; 5930 uint32_t rx_lane_polarity = 0; 5931 uint32_t tx_lane_polarity = 0; 5932 5933 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 5934 PHYMOD_MEMSET(&tx_pl_cfg, 0 , sizeof(BCMI_MADURA_TLB_TX_TLB_TX_MISC_CFGr_t)); 5935 PHYMOD_MEMSET(&rx_pl_cfg, 0 , sizeof(BCMI_MADURA_TLB_RX_TLB_RX_MISC_CFGr_t)); 5936 if (rx_polarity == 0xFFFF && tx_polarity == 0xFFFF) { 5937 return PHYMOD_E_NONE; 5938 } 5939 5940 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5941 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 5942 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5943 _madura_phy_interface_config_get(pa, 0, &config))); 5944 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5945 MADURA_GET_IP(pa, config, ip); 5946 MADURA_GET_INTF_SIDE(pa, intf_side); 5947 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 5948 5949 5950 /* FALCON polarity inversion */ 5951 PHYMOD_DEBUG_VERBOSE(("Falcon polarity inversion set tx=%x rx=%xat %d\n",tx_polarity,rx_polarity,__LINE__)); 5952 for (lane = 0; lane < max_lane; lane ++) { 5953 if (lane_mask & (1 << lane)) { 5954 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5955 _madura_set_slice_reg (pa, 5956 ip, MADURA_DEV_PMA_PMD, lane, 0))); 5957 if (rx_polarity != 0xFFFF) { 5958 rx_lane_polarity = (rx_polarity >> lane) & 0x1; 5959 /* Write to Rx misc config register */ 5960 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5961 BCMI_MADURA_READ_TLB_RX_TLB_RX_MISC_CFGr(pa,&rx_pl_cfg))); 5962 BCMI_MADURA_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(rx_pl_cfg,rx_lane_polarity); 5963 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5964 BCMI_MADURA_WRITE_TLB_RX_TLB_RX_MISC_CFGr(pa,rx_pl_cfg))); 5965 } 5966 if (tx_polarity != 0xFFFF) { 5967 tx_lane_polarity = (tx_polarity >> lane) & 0x1; 5968 /* Write to Tx misc config register */ 5969 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5970 BCMI_MADURA_READ_TLB_TX_TLB_TX_MISC_CFGr(pa,&tx_pl_cfg))); 5971 BCMI_MADURA_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(tx_pl_cfg,tx_lane_polarity); 5972 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 5973 BCMI_MADURA_WRITE_TLB_TX_TLB_TX_MISC_CFGr(pa,tx_pl_cfg))); 5974 } 5975 } 5976 } 5977 /*Reset DEV1 slice register*/ 5978 PHYMOD_FREE(config.device_aux_modes); 5979 PHYMOD_IF_ERR_RETURN( 5980 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 5981 5982 return PHYMOD_E_NONE; 5983 } 5984 5985 int _madura_tx_rx_polarity_get(const phymod_access_t *phy, uint32_t *tx_polarity, uint32_t *rx_polarity) 5986 { 5987 phymod_phy_inf_config_t config; 5988 uint16_t ip = 0; 5989 uint16_t lane = 0; 5990 uint16_t lane_mask = 0, max_lane = 0; 5991 const phymod_access_t *pa = phy; 5992 BCMI_MADURA_TLB_TX_TLB_TX_MISC_CFGr_t tx_pl_cfg; 5993 BCMI_MADURA_TLB_RX_TLB_RX_MISC_CFGr_t rx_pl_cfg; 5994 5995 *tx_polarity = 0; 5996 *rx_polarity = 0; 5997 5998 PHYMOD_MEMSET(&tx_pl_cfg, 0 , sizeof(BCMI_MADURA_TLB_TX_TLB_TX_MISC_CFGr_t)); 5999 PHYMOD_MEMSET(&rx_pl_cfg, 0 , sizeof(BCMI_MADURA_TLB_RX_TLB_RX_MISC_CFGr_t)); 6000 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6001 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6002 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6003 _madura_phy_interface_config_get(phy, 0, &config))); 6004 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6005 MADURA_GET_IP(phy, config, ip); 6006 6007 max_lane = (ip == MADURA_FALCON_CORE) ? 6008 MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE; 6009 6010 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6011 (ip == MADURA_2X_FALCON_CORE)?"2X_FALCON":"FALCON", max_lane, lane_mask)); 6012 6013 for (lane = 0; lane < max_lane; lane ++) { 6014 if (lane_mask & (1 << lane)) { 6015 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6016 _madura_set_slice_reg (pa, 6017 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6018 /* FALCON polarity */ 6019 PHYMOD_DEBUG_VERBOSE(("Falcon polarity get\n")); 6020 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6021 BCMI_MADURA_READ_TLB_TX_TLB_TX_MISC_CFGr(pa,&tx_pl_cfg))); 6022 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6023 BCMI_MADURA_READ_TLB_RX_TLB_RX_MISC_CFGr(pa,&rx_pl_cfg))); 6024 /* Read to Tx misc config register */ 6025 *tx_polarity|=(BCMI_MADURA_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(tx_pl_cfg))<<lane; 6026 /* Read to Rx misc config register */ 6027 *rx_polarity|=(BCMI_MADURA_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(rx_pl_cfg))<<lane; 6028 } 6029 } 6030 6031 MADURA_RESET_SLICE(pa, MADURA_DEV_PMA_PMD); 6032 PHYMOD_FREE(config.device_aux_modes); 6033 6034 return PHYMOD_E_NONE; 6035 } 6036 6037 int _madura_pll_sequencer_restart(const phymod_core_access_t *core, phymod_sequencer_operation_t operation) 6038 { 6039 const phymod_access_t *pa = &core->access; 6040 BCMI_MADURA_CORE_PLL_TOP_USER_CTLr_t pll_seq; 6041 BCMI_MADURA_SLICEr_t slice_reg; 6042 unsigned int alt = 0,lane = 0; 6043 6044 PHYMOD_MEMSET(&pll_seq, 0 , sizeof(BCMI_MADURA_CORE_PLL_TOP_USER_CTLr_t)); 6045 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6046 6047 alt = ( pa->lane_mask & 0xf0 )? 1 : 0; 6048 lane = ( alt == 0 )? 1 : 4 ; 6049 6050 switch(operation) { 6051 case phymodSeqOpStop: 6052 case phymodSeqOpStart: 6053 return PHYMOD_E_UNAVAIL; 6054 /* Toggle PLL Sequencer with pmd_core_dp_h_rstb_frcval */ 6055 case phymodSeqOpRestart: 6056 PHYMOD_IF_ERR_RETURN(_madura_set_slice_reg (pa, 6057 0, MADURA_DEV_PMA_PMD, lane ,0)); 6058 PHYMOD_IF_ERR_RETURN( 6059 BCMI_MADURA_READ_CORE_PLL_TOP_USER_CTLr(pa,&pll_seq)); 6060 BCMI_MADURA_CORE_PLL_TOP_USER_CTLr_CORE_DP_S_RSTBf_SET(pll_seq,0); 6061 PHYMOD_IF_ERR_RETURN( 6062 BCMI_MADURA_WRITE_CORE_PLL_TOP_USER_CTLr(pa,pll_seq)); 6063 PHYMOD_IF_ERR_RETURN(_madura_set_slice_reg (pa, 6064 1, MADURA_DEV_PMA_PMD, 0x1, 0)); 6065 PHYMOD_IF_ERR_RETURN( 6066 BCMI_MADURA_READ_CORE_PLL_TOP_USER_CTLr(pa,&pll_seq)); 6067 BCMI_MADURA_CORE_PLL_TOP_USER_CTLr_CORE_DP_S_RSTBf_SET(pll_seq,0); 6068 PHYMOD_IF_ERR_RETURN( 6069 BCMI_MADURA_WRITE_CORE_PLL_TOP_USER_CTLr(pa,pll_seq)); 6070 6071 PHYMOD_USLEEP(1000); 6072 PHYMOD_IF_ERR_RETURN(_madura_set_slice_reg (pa, 6073 0, MADURA_DEV_PMA_PMD, lane, 0)); 6074 PHYMOD_IF_ERR_RETURN( 6075 BCMI_MADURA_READ_CORE_PLL_TOP_USER_CTLr(pa,&pll_seq)); 6076 BCMI_MADURA_CORE_PLL_TOP_USER_CTLr_CORE_DP_S_RSTBf_SET(pll_seq,1); 6077 PHYMOD_IF_ERR_RETURN( 6078 BCMI_MADURA_WRITE_CORE_PLL_TOP_USER_CTLr(pa,pll_seq)); 6079 PHYMOD_IF_ERR_RETURN(_madura_set_slice_reg (pa, 6080 1, MADURA_DEV_PMA_PMD, 0x1, 0)); 6081 PHYMOD_IF_ERR_RETURN( 6082 BCMI_MADURA_READ_CORE_PLL_TOP_USER_CTLr(pa,&pll_seq)); 6083 BCMI_MADURA_CORE_PLL_TOP_USER_CTLr_CORE_DP_S_RSTBf_SET(pll_seq,1); 6084 PHYMOD_IF_ERR_RETURN( 6085 BCMI_MADURA_WRITE_CORE_PLL_TOP_USER_CTLr(pa,pll_seq)); 6086 6087 break; 6088 default: 6089 break; 6090 } 6091 6092 return PHYMOD_E_NONE; 6093 } 6094 6095 int _madura_fec_enable_set(const phymod_access_t *phy, uint32_t enable) 6096 { 6097 const phymod_access_t *pa = phy; 6098 BCMI_MADURA_DP_CTL0r_t fec_ctl; 6099 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 6100 uint16_t lane_mask = 0, retry_cnt = 5, data1 = 0; 6101 phymod_phy_inf_config_t config; 6102 6103 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6104 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6105 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6106 _madura_phy_interface_config_get(phy, 0, &config))); 6107 6108 PHYMOD_MEMSET(&fec_ctl, 0, sizeof(BCMI_MADURA_DP_CTL0r_t)); 6109 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 6110 6111 lane_mask = pa->lane_mask; 6112 6113 PHYMOD_IF_ERR_RETURN( 6114 BCMI_MADURA_READ_DP_CTL0r(pa,&fec_ctl)); 6115 if(lane_mask == 0xF){ 6116 BCMI_MADURA_DP_CTL0r_CL91_EN_0f_SET(fec_ctl,enable); 6117 if(config.data_rate == MADURA_SPD_100G){ 6118 BCMI_MADURA_DP_CTL0r_AN_AUTO_CL91_0_DISf_SET(fec_ctl,((enable & 0x1)?0:1));/*enable value can be 65536 and 65537 for 0&1 resp . PHY-3042*/ 6119 } 6120 }else{ 6121 BCMI_MADURA_DP_CTL0r_CL91_EN_1f_SET(fec_ctl,enable); 6122 if(config.data_rate == MADURA_SPD_100G){ 6123 BCMI_MADURA_DP_CTL0r_AN_AUTO_CL91_1_DISf_SET(fec_ctl,((enable & 0x1)?0:1)); 6124 } 6125 } 6126 6127 /* If !100G speed and fec disable then do*/ 6128 if((config.data_rate!=MADURA_SPD_100G) && ((enable & 0x1)==0)){ 6129 BCMI_MADURA_DP_CTL0r_CL91_EN_0f_SET(fec_ctl,0); 6130 BCMI_MADURA_DP_CTL0r_CL91_EN_1f_SET(fec_ctl,0); 6131 BCMI_MADURA_DP_CTL0r_AN_AUTO_CL91_0_DISf_SET(fec_ctl,0); 6132 BCMI_MADURA_DP_CTL0r_AN_AUTO_CL91_1_DISf_SET(fec_ctl,0); 6133 } 6134 6135 PHYMOD_IF_ERR_RETURN( 6136 BCMI_MADURA_WRITE_DP_CTL0r(pa,fec_ctl)); 6137 6138 /* Set FW en */ 6139 /* coverity[operator_confusion] */ 6140 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en, 1); 6141 PHYMOD_IF_ERR_RETURN( 6142 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en)); 6143 6144 /* Wait for Firmware Ready */ 6145 do { 6146 PHYMOD_IF_ERR_RETURN( 6147 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en)); 6148 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 6149 PHYMOD_USLEEP(100); 6150 } while ((data1 != 0) && (retry_cnt --)); 6151 if (retry_cnt == 0) { 6152 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 6153 (_PHYMOD_MSG("Firmware is busy.."))); 6154 } 6155 6156 BCMI_MADURA_DP_CTL0r_DP_RSTBf_SET(fec_ctl,0x0); 6157 PHYMOD_USLEEP(100); 6158 BCMI_MADURA_DP_CTL0r_DP_RSTBf_SET(fec_ctl,0x3); 6159 PHYMOD_IF_ERR_RETURN( 6160 BCMI_MADURA_WRITE_DP_CTL0r(pa,fec_ctl)); 6161 6162 PHYMOD_FREE(config.device_aux_modes); 6163 return PHYMOD_E_NONE; 6164 } 6165 6166 6167 int _madura_fec_enable_get(const phymod_access_t *phy, uint32_t* enable) 6168 { 6169 const phymod_access_t *pa = phy; 6170 BCMI_MADURA_DP_CTL0r_t fec_ctl; 6171 uint16_t lane_mask = 0; 6172 6173 PHYMOD_MEMSET(&fec_ctl, 0, sizeof(BCMI_MADURA_DP_CTL0r_t)); 6174 6175 lane_mask = pa->lane_mask; 6176 6177 PHYMOD_IF_ERR_RETURN( 6178 BCMI_MADURA_READ_DP_CTL0r(pa,&fec_ctl)); 6179 if(lane_mask == 0xF){ 6180 *enable=BCMI_MADURA_DP_CTL0r_CL91_EN_0f_GET(fec_ctl); 6181 }else{ 6182 *enable=BCMI_MADURA_DP_CTL0r_CL91_EN_1f_GET(fec_ctl); 6183 } 6184 6185 return PHYMOD_E_NONE; 6186 } 6187 6188 6189 int _madura_tx_power_set(const phymod_access_t *phy, uint32_t power_tx) 6190 { 6191 phymod_phy_inf_config_t config; 6192 uint16_t ip = 0; 6193 uint16_t lane = 0,max_lane=0,intf_side=0; 6194 uint16_t lane_mask = 0; 6195 const phymod_access_t *pa = phy; 6196 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_TXr_t tx_pwr_dwn; 6197 BCMI_MADURA_SLICEr_t slice_reg; 6198 6199 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6200 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6201 PHYMOD_MEMSET(&tx_pwr_dwn, 0, sizeof(BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_TXr_t)); 6202 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6203 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6204 _madura_phy_interface_config_get(phy, 0, &config))); 6205 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6206 MADURA_GET_IP(phy, config, ip); 6207 6208 MADURA_GET_INTF_SIDE(pa, intf_side); 6209 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6210 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6211 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6212 6213 for(lane = 0; lane < max_lane; lane ++) { 6214 if (lane_mask & (1 << lane)) { 6215 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6216 _madura_set_slice_reg (pa, 6217 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6218 /* FALCON TX Power Set */ 6219 PHYMOD_DEBUG_VERBOSE(("Falcon TX Power set\n")); 6220 switch (power_tx) { 6221 case phymodPowerOff: /* Turn off power */ 6222 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6223 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,&tx_pwr_dwn))); 6224 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_TXr_LN_TX_S_PWRDNf_SET(tx_pwr_dwn,1); 6225 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6226 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,tx_pwr_dwn))); 6227 break; 6228 case phymodPowerOn: /* Turn on power */ 6229 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6230 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,&tx_pwr_dwn))); 6231 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_TXr_LN_TX_S_PWRDNf_SET(tx_pwr_dwn,0); 6232 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6233 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,tx_pwr_dwn))); 6234 break; 6235 case phymodPowerOffOn: /* Toggle power */ 6236 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6237 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,&tx_pwr_dwn))); 6238 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_TXr_LN_TX_S_PWRDNf_SET(tx_pwr_dwn,1); 6239 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6240 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,tx_pwr_dwn))); 6241 PHYMOD_USLEEP(10000); 6242 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_TXr_LN_TX_S_PWRDNf_SET(tx_pwr_dwn,0); 6243 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6244 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_TXr(pa,tx_pwr_dwn))); 6245 break; 6246 case phymodPowerNoChange: /* Stay where you are */ 6247 break; 6248 default: 6249 break; 6250 } 6251 } 6252 } 6253 6254 PHYMOD_FREE(config.device_aux_modes); 6255 6256 /*Reset DEV1 slice register*/ 6257 PHYMOD_IF_ERR_RETURN( 6258 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6259 return PHYMOD_E_NONE; 6260 } 6261 6262 6263 int _madura_rx_power_set(const phymod_access_t *phy, uint32_t power_rx) 6264 { 6265 phymod_phy_inf_config_t config; 6266 uint16_t ip = 0; 6267 uint16_t lane = 0; 6268 uint16_t lane_mask = 0,max_lane=0,intf_side=0; 6269 const phymod_access_t *pa = phy; 6270 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_RXr_t rx_pwr_dwn; 6271 BCMI_MADURA_SLICEr_t slice_reg; 6272 6273 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6274 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6275 PHYMOD_MEMSET(&rx_pwr_dwn, 0, sizeof(BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_RXr_t)); 6276 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6277 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6278 _madura_phy_interface_config_get(phy, 0, &config))); 6279 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6280 6281 MADURA_GET_IP(phy, config, ip); 6282 MADURA_GET_INTF_SIDE(pa, intf_side); 6283 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6284 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6285 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6286 6287 for(lane = 0; lane < max_lane; lane ++) { 6288 if (lane_mask & (1 << lane)) { 6289 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6290 _madura_set_slice_reg (pa, 6291 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6292 /* FALCON RX Power Set */ 6293 PHYMOD_DEBUG_VERBOSE(("Falcon RX Power set\n")); 6294 switch (power_rx) { 6295 case phymodPowerOff: /* Turn off power */ 6296 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6297 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,&rx_pwr_dwn))); 6298 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_RXr_LN_RX_S_PWRDNf_SET(rx_pwr_dwn,1); 6299 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6300 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,rx_pwr_dwn))); 6301 break; 6302 case phymodPowerOn: /* Turn on power */ 6303 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6304 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,&rx_pwr_dwn))); 6305 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_RXr_LN_RX_S_PWRDNf_SET(rx_pwr_dwn,0); 6306 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6307 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,rx_pwr_dwn))); 6308 break; 6309 case phymodPowerOffOn: /* Toggle power */ 6310 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6311 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,&rx_pwr_dwn))); 6312 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_RXr_LN_RX_S_PWRDNf_SET(rx_pwr_dwn,1); 6313 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6314 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,rx_pwr_dwn))); 6315 PHYMOD_USLEEP(10000); 6316 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6317 BCMI_MADURA_READ_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,&rx_pwr_dwn))); 6318 BCMI_MADURA_LN_CLK_RST_N_PWRDWN_CTL_RXr_LN_RX_S_PWRDNf_SET(rx_pwr_dwn,0); 6319 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6320 BCMI_MADURA_WRITE_LN_CLK_RST_N_PWRDWN_CTL_RXr(pa,rx_pwr_dwn))); 6321 break; 6322 case phymodPowerNoChange: /* Stay where you are */ 6323 break; 6324 default: 6325 break; 6326 } 6327 } 6328 } 6329 6330 PHYMOD_FREE(config.device_aux_modes); 6331 6332 /*Reset DEV1 slice register*/ 6333 PHYMOD_IF_ERR_RETURN( 6334 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6335 6336 return PHYMOD_E_NONE; 6337 } 6338 6339 int _madura_tx_rx_power_get(const phymod_access_t *phy, phymod_phy_power_t* power) 6340 { 6341 phymod_phy_inf_config_t config; 6342 uint16_t ip = 0; 6343 uint16_t lane = 0,intf_side=0; 6344 uint16_t lane_mask = 0, max_lane = 0; 6345 const phymod_access_t *pa = phy; 6346 BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr_t rx_pwr_get; 6347 BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr_t tx_pwr_get; 6348 BCMI_MADURA_SLICEr_t slice_reg; 6349 6350 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6351 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6352 PHYMOD_MEMSET(&rx_pwr_get, 0, sizeof(BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr_t)); 6353 PHYMOD_MEMSET(&tx_pwr_get, 0, sizeof(BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr_t)); 6354 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6355 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6356 _madura_phy_interface_config_get(phy, 0, &config))); 6357 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6358 MADURA_GET_IP(phy, config, ip); 6359 6360 MADURA_GET_INTF_SIDE(pa, intf_side); 6361 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6362 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6363 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6364 6365 for (lane = 0; lane < max_lane; lane ++) { 6366 if (lane_mask & (1 << lane)) { 6367 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6368 _madura_set_slice_reg (pa, 6369 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6370 /* FALCON TX/RX Power Get */ 6371 PHYMOD_DEBUG_VERBOSE(("Falcon TX/RX Power get\n")); 6372 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6373 BCMI_MADURA_READ_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr(pa,&rx_pwr_get))); 6374 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6375 BCMI_MADURA_READ_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr(pa,&tx_pwr_get))); 6376 power->rx = !BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_RXr_AFE_RX_PWRDNf_GET(rx_pwr_get); 6377 power->tx = !BCMI_MADURA_AFE_RST_PWRDN_OSR_MODE_PIN_STS_TXr_AFE_TX_PWRDNf_GET(tx_pwr_get); 6378 } 6379 } 6380 PHYMOD_DEBUG_VERBOSE(("pwr tx=%d rx=%d\n",power->tx,power->rx)); 6381 PHYMOD_FREE(config.device_aux_modes); 6382 6383 PHYMOD_IF_ERR_RETURN( 6384 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6385 return PHYMOD_E_NONE; 6386 } 6387 6388 6389 int _madura_tx_set(const phymod_access_t *phy, const phymod_tx_t* tx) 6390 { 6391 phymod_phy_inf_config_t config; 6392 uint16_t ip = 0; 6393 uint16_t lane = 0,max_lane=0,intf_side=0; 6394 uint16_t lane_mask = 0; 6395 const phymod_access_t *pa = phy; 6396 BCMI_MADURA_SLICEr_t slice_reg; 6397 6398 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6399 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6400 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6401 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6402 _madura_phy_interface_config_get(phy, 0, &config))); 6403 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6404 MADURA_GET_IP(phy, config, ip); 6405 6406 MADURA_GET_INTF_SIDE(pa, intf_side); 6407 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6408 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6409 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6410 6411 for(lane = 0; lane < max_lane; lane ++) { 6412 if (lane_mask & (1 << lane)) { 6413 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6414 _madura_set_slice_reg (pa, 6415 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6416 PHYMOD_DEBUG_VERBOSE(("Falcon TXFIR set\n")); 6417 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6418 falcon2_madura_write_tx_afe(pa, TX_AFE_PRE, (int8_t)tx->pre))); 6419 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6420 falcon2_madura_write_tx_afe(pa, TX_AFE_MAIN, (int8_t)tx->main))); 6421 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6422 falcon2_madura_write_tx_afe(pa, TX_AFE_POST1, (int8_t)tx->post))); 6423 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6424 falcon2_madura_write_tx_afe(pa, TX_AFE_POST2, (int8_t)tx->post2))); 6425 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6426 falcon2_madura_write_tx_afe(pa, TX_AFE_POST3, (int8_t)tx->post3))); 6427 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6428 falcon2_madura_write_tx_afe(pa, TX_AFE_AMP, (int8_t)tx->amp))); 6429 6430 } 6431 } 6432 /*Reset DEV1 slice register*/ 6433 PHYMOD_FREE(config.device_aux_modes); 6434 PHYMOD_IF_ERR_RETURN( 6435 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6436 return PHYMOD_E_NONE; 6437 } 6438 6439 6440 int _madura_tx_get(const phymod_access_t *phy, phymod_tx_t* tx) 6441 { 6442 phymod_phy_inf_config_t config; 6443 uint16_t ip = 0; 6444 uint16_t lane = 0,max_lane=0,intf_side=0; 6445 uint16_t lane_mask = 0; 6446 int8_t value = 0; 6447 const phymod_access_t *pa = phy; 6448 BCMI_MADURA_SLICEr_t slice_reg; 6449 6450 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6451 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6452 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6453 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6454 _madura_phy_interface_config_get(phy, 0, &config))); 6455 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6456 MADURA_GET_IP(phy, config, ip); 6457 6458 MADURA_GET_INTF_SIDE(pa, intf_side); 6459 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6460 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6461 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6462 6463 for(lane = 0; lane < max_lane; lane ++) { 6464 if (lane_mask & (1 << lane)) { 6465 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6466 _madura_set_slice_reg (pa, 6467 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6468 PHYMOD_DEBUG_VERBOSE(("Falcon TXFIR get\n")); 6469 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6470 falcon2_madura_read_tx_afe(pa, TX_AFE_PRE, &value))); 6471 tx->pre = value; 6472 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6473 falcon2_madura_read_tx_afe(pa, TX_AFE_MAIN, &value))); 6474 tx->main = value; 6475 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6476 falcon2_madura_read_tx_afe(pa, TX_AFE_POST1, &value))); 6477 tx->post = value; 6478 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6479 falcon2_madura_read_tx_afe(pa, TX_AFE_POST2, &value))); 6480 tx->post2 = value; 6481 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6482 falcon2_madura_read_tx_afe(pa, TX_AFE_POST3, &value))); 6483 tx->post3 = value; 6484 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6485 falcon2_madura_read_tx_afe(pa, TX_AFE_AMP, &value))); 6486 tx->amp = value; 6487 } 6488 } 6489 /*Reset DEV1 slice register*/ 6490 PHYMOD_FREE(config.device_aux_modes); 6491 PHYMOD_IF_ERR_RETURN( 6492 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6493 return PHYMOD_E_NONE; 6494 } 6495 6496 int _madura_rx_set(const phymod_access_t *phy, const phymod_rx_t* rx) 6497 { 6498 phymod_phy_inf_config_t config; 6499 uint16_t ip = 0; 6500 uint16_t lane = 0,max_lane=0,intf_side=0; 6501 uint16_t lane_mask = 0; 6502 const phymod_access_t *pa = phy; 6503 BCMI_MADURA_SLICEr_t slice_reg; 6504 uint16_t indx = 0; 6505 6506 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6507 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6508 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6509 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6510 _madura_phy_interface_config_get(phy, 0, &config))); 6511 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6512 MADURA_GET_IP(phy, config, ip); 6513 6514 MADURA_GET_INTF_SIDE(pa, intf_side); 6515 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6516 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6517 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6518 6519 for(lane = 0; lane < max_lane; lane ++) { 6520 if (lane_mask & (1 << lane)) { 6521 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6522 _madura_set_slice_reg (pa, 6523 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6524 6525 /* FALCON RXFIR set */ 6526 PHYMOD_DEBUG_VERBOSE(("Falcon RXFIR set\n")); 6527 6528 /*params check*/ 6529 for (indx = 0 ; indx < PHYMOD_NUM_DFE_TAPS; indx++){ 6530 if(rx->dfe[indx].enable && (rx->num_of_dfe_taps > PHYMOD_NUM_DFE_TAPS)) { 6531 PHYMOD_DEBUG_ERROR(("illegal number of DFEs to set")); 6532 } 6533 } 6534 /*vga set*/ 6535 /* first stop the rx adaption */ 6536 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6537 falcon2_madura_stop_rx_adaptation(pa, 1))); 6538 if (rx->vga.enable) { 6539 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6540 falcon2_madura_write_rx_afe(pa, RX_AFE_VGA, rx->vga.value))); 6541 } 6542 /*dfe set*/ 6543 for (indx = 0 ; indx < PHYMOD_NUM_DFE_TAPS; indx++){ 6544 if(rx->dfe[indx].enable){ 6545 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6546 falcon2_madura_write_rx_afe(pa, RX_AFE_DFE1+indx, rx->dfe[indx].value))); 6547 } 6548 } 6549 6550 /*peaking filter set*/ 6551 if(rx->peaking_filter.enable){ 6552 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6553 falcon2_madura_write_rx_afe(pa, RX_AFE_PF, rx->peaking_filter.value))); 6554 } 6555 6556 if(rx->low_freq_peaking_filter.enable){ 6557 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6558 falcon2_madura_write_rx_afe(pa, RX_AFE_PF2, rx->low_freq_peaking_filter.value))); 6559 } 6560 6561 } 6562 } 6563 6564 /*Reset DEV1 slice register*/ 6565 PHYMOD_FREE(config.device_aux_modes); 6566 PHYMOD_IF_ERR_RETURN( 6567 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6568 return PHYMOD_E_NONE; 6569 } 6570 6571 int _madura_rx_adaptation_resume(const phymod_access_t* pa) 6572 { 6573 phymod_phy_inf_config_t config; 6574 uint16_t ip = 0 , intf_side = 0; 6575 uint16_t lane = 0; 6576 uint16_t lane_mask = 0, max_lane = 0; 6577 int rv = PHYMOD_E_NONE; 6578 BCMI_MADURA_SLICEr_t slice_reg; 6579 6580 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6581 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6582 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6583 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6584 _madura_phy_interface_config_get(pa, 0, &config))); 6585 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6586 MADURA_GET_IP(pa, config, ip); 6587 6588 MADURA_GET_INTF_SIDE(pa, intf_side); 6589 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6590 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6591 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6592 6593 for (lane = 0; lane < max_lane; lane ++) { 6594 if (lane_mask & (1 << lane)) { 6595 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6596 _madura_set_slice_reg (pa, 6597 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6598 6599 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6600 (falcon2_madura_stop_rx_adaptation(pa, 0)))); 6601 } 6602 } 6603 6604 PHYMOD_FREE(config.device_aux_modes); 6605 PHYMOD_IF_ERR_RETURN( 6606 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6607 6608 return rv; 6609 } 6610 6611 int _madura_rx_get(const phymod_access_t *phy, phymod_rx_t* rx) 6612 { 6613 phymod_phy_inf_config_t config; 6614 uint16_t ip = 0; 6615 uint16_t lane = 0,max_lane=0,intf_side=0; 6616 uint16_t lane_mask = 0; 6617 const phymod_access_t *pa = phy; 6618 BCMI_MADURA_SLICEr_t slice_reg; 6619 uint16_t indx = 0; 6620 int8_t dfe = 0; 6621 int8_t vga = 0; 6622 int8_t pf = 0; 6623 int8_t low_freq_pf = 0; 6624 uint32_t rx_adaptation; 6625 6626 PHYMOD_MEMSET(&slice_reg, 0 , sizeof(BCMI_MADURA_SLICEr_t)); 6627 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 6628 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 6629 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6630 _madura_phy_interface_config_get(phy, 0, &config))); 6631 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6632 MADURA_GET_IP(phy, config, ip); 6633 6634 MADURA_GET_INTF_SIDE(pa, intf_side); 6635 max_lane = (intf_side == MADURA_IF_SYS) ? MADURA_MAX_FALCON_LANE : MADURA_MAX_2X_FALCON_LANE ; 6636 PHYMOD_DEBUG_VERBOSE(("%s ::IP:%s Max_lane:%d lanemask:0x%x\n", __func__, 6637 (ip == MADURA_2X_FALCON_CORE)?"FALCON2X":"FALCON", max_lane, lane_mask)); 6638 6639 for(lane = 0; lane < max_lane; lane ++) { 6640 if (lane_mask & (1 << lane)) { 6641 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6642 _madura_set_slice_reg (pa, 6643 ip, MADURA_DEV_PMA_PMD, lane, 0))); 6644 6645 /* FALCON RXFIR get */ 6646 PHYMOD_DEBUG_VERBOSE(("Falcon RXFIR get\n")); 6647 6648 rx_adaptation = PHYMOD_RX_ADAPTATION_ON_GET(rx); 6649 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6650 falcon2_madura_stop_rx_adaptation(phy, 1))); 6651 6652 /*vga get*/ 6653 rx->num_of_dfe_taps = PHYMOD_NUM_DFE_TAPS; 6654 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6655 falcon2_madura_read_rx_afe(pa, RX_AFE_VGA, &vga))); 6656 rx->vga.value = vga; 6657 6658 /*dfe get*/ 6659 for (indx = 0 ; indx < PHYMOD_NUM_DFE_TAPS; indx++){ 6660 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6661 falcon2_madura_read_rx_afe(pa, (RX_AFE_DFE1+indx), &dfe))); 6662 rx->dfe[indx].value = dfe; 6663 rx->dfe[indx].enable = 1; 6664 } 6665 6666 /*peaking filter get*/ 6667 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6668 falcon2_madura_read_rx_afe(pa, RX_AFE_PF, &pf))); 6669 rx->peaking_filter.value = pf; 6670 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6671 falcon2_madura_read_rx_afe(pa, RX_AFE_PF2, &low_freq_pf))); 6672 rx->low_freq_peaking_filter.value = low_freq_pf; 6673 6674 if (rx_adaptation) { 6675 MADURA_IF_ERR_RETURN_FREE(config.device_aux_modes, ( 6676 falcon2_madura_stop_rx_adaptation(phy, 0))); 6677 } 6678 6679 } 6680 } 6681 6682 6683 /*Reset DEV1 slice register*/ 6684 PHYMOD_FREE(config.device_aux_modes); 6685 PHYMOD_IF_ERR_RETURN( 6686 BCMI_MADURA_WRITE_SLICEr(pa,slice_reg)); 6687 return PHYMOD_E_NONE; 6688 } 6689 6690 /** Get madura interrupt type number from PHYMOD intr type 6691 * 6692 * @param intr_type Select the interrupt type. 6693 * 6694 * Return val: Furia Interrupt type Number 6695 */ 6696 MADURA_INTR_TYPE_E convert_phymod_to_madura( uint16_t intr_type, uint16_t intf_side, uint16_t lane_mask) 6697 { 6698 uint16_t converted_val=99; /*some junk value*/ 6699 6700 switch(intr_type) { 6701 case PHYMOD_INTR_PLL_EVENT: 6702 if( intf_side == MADURA_IF_SYS){ 6703 converted_val = MADURA_INT_SYS_FAL_0_PLL0_LOCK_LOST; 6704 }else{/*line side*/ 6705 if( lane_mask & 0XF ){/* lower falcon*/ 6706 converted_val = MADURA_INT_LIN_FAL_0_PLL0_LOCK_LOST; 6707 }else{ /* upper falcon */ 6708 converted_val = MADURA_INT_LIN_FAL_1_PLL0_LOCK_LOST; 6709 } 6710 } 6711 break; 6712 case PHYMOD_INTR_AUTONEG_EVENT: 6713 if( intf_side == MADURA_IF_SYS){ 6714 converted_val = MADURA_INT_SYS_CL73_AN_COMPLETE_P1; 6715 }else{/*line side*/ 6716 if( lane_mask & 0XF ){/* lower falcon*/ 6717 converted_val = MADURA_INT_LIN_CL73_AN_COMPLETE_P1; 6718 }else{ /* upper falcon */ 6719 converted_val = MADURA_INT_LIN_CL73_AN_COMPLETE_P2; 6720 } 6721 } 6722 break; 6723 case PHYMOD_INTR_EMON_EVENT: 6724 converted_val = ( intf_side == MADURA_IF_SYS ) ? MADURA_INT_SYS_PCS_MON_LOCK_LOST : MADURA_INT_LIN_PCS_MON_LOCK_LOST ; 6725 break; 6726 case PHYMOD_INTR_LINK_EVENT: 6727 converted_val = ( intf_side == MADURA_IF_SYS ) ? MADURA_INT_SYS_PMD_LOCK_LOST : MADURA_INT_LIN_PMD_LOCK_LOST ; 6728 break; 6729 default: 6730 return PHYMOD_E_PARAM; 6731 } 6732 return converted_val; 6733 } 6734 6735 int _madura_get_intr_reg ( const phymod_phy_access_t *phy, uint32_t intr_type, uint16_t *bit_pos, uint16_t *int_grp) 6736 { 6737 uint16_t lane_mask = 0; 6738 uint16_t intf_side = 0; 6739 const phymod_access_t *acc = &phy->access; 6740 6741 MADURA_GET_INTF_SIDE(acc, intf_side); 6742 lane_mask = PHYMOD_ACC_LANE_MASK(acc); 6743 intr_type = convert_phymod_to_madura(intr_type,intf_side,lane_mask); 6744 /* Get the interrupt bit postion in the reg and interrupt group */ 6745 switch (intr_type) { 6746 case MADURA_INT_M0_MST_SEC : *bit_pos = 5; *int_grp = 0; break; 6747 case MADURA_INT_M0_MST_DED : *bit_pos = 4; *int_grp = 0; break; 6748 case MADURA_INT_M0_MST_MSGOUT_INTR : *bit_pos = 3; *int_grp = 0; break; 6749 case MADURA_INT_M0_MST_MISC_INTR: *bit_pos = 2; *int_grp = 0; break; 6750 case MADURA_INT_M0_MST_LOCKUP: *bit_pos = 1; *int_grp = 0; break; 6751 case MADURA_INT_M0_MST_SYSRESETREQ: *bit_pos = 0; *int_grp = 0; break; 6752 case MADURA_INT_SYS_FAL_0_PLL0_LOCK_FOUND: *bit_pos = 15; *int_grp = 1; break; 6753 case MADURA_INT_SYS_FAL_0_PLL0_LOCK_LOST: *bit_pos = 14; *int_grp = 1; break; 6754 case MADURA_INT_SYS_FAL_0_PLL1_LOCK_FOUND: *bit_pos = 13; *int_grp = 1; break; 6755 case MADURA_INT_SYS_FAL_0_PLL1_LOCK_LOST: *bit_pos = 12; *int_grp = 1; break; 6756 case MADURA_INT_SYS_FAL_1_PLL0_LOCK_FOUND: *bit_pos = 11; *int_grp = 1; break; 6757 case MADURA_INT_SYS_FAL_1_PLL0_LOCK_LOST: *bit_pos = 10; *int_grp = 1; break; 6758 case MADURA_INT_SYS_FAL_1_PLL1_LOCK_FOUND: *bit_pos = 9; *int_grp = 1; break; 6759 case MADURA_INT_SYS_FAL_1_PLL1_LOCK_LOST: *bit_pos = 8; *int_grp = 1; break; 6760 case MADURA_INT_LIN_FAL_0_PLL0_LOCK_FOUND: *bit_pos = 7; *int_grp = 1; break; 6761 case MADURA_INT_LIN_FAL_0_PLL0_LOCK_LOST: *bit_pos = 6; *int_grp = 1; break; 6762 case MADURA_INT_LIN_FAL_0_PLL1_LOCK_FOUND: *bit_pos = 5; *int_grp = 1; break; 6763 case MADURA_INT_LIN_FAL_0_PLL1_LOCK_LOST: *bit_pos = 4; *int_grp = 1; break; 6764 case MADURA_INT_LIN_FAL_1_PLL0_LOCK_FOUND: *bit_pos = 3; *int_grp = 1; break; 6765 case MADURA_INT_LIN_FAL_1_PLL0_LOCK_LOST: *bit_pos = 2; *int_grp = 1; break; 6766 case MADURA_INT_LIN_FAL_1_PLL1_LOCK_FOUND: *bit_pos = 1; *int_grp = 1; break; 6767 case MADURA_INT_LIN_FAL_1_PLL1_LOCK_LOST: *bit_pos = 0; *int_grp = 1; break; 6768 case MADURA_INT_SYS_CL73_INCOMPATIBLE_LINK_0: *bit_pos = 15; *int_grp = 2; break; 6769 case MADURA_INT_SYS_CL73_INCOMPATIBLE_LINK_1: *bit_pos = 14; *int_grp = 2; break; 6770 case MADURA_INT_SYS_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_0: *bit_pos = 13; *int_grp = 2; break; 6771 case MADURA_INT_SYS_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_1: *bit_pos = 12; *int_grp = 2; break; 6772 case MADURA_INT_SYS_CL73_AN_COMPLETE_P1: *bit_pos = 11; *int_grp = 2; break; 6773 case MADURA_INT_SYS_CL73_AN_RESTARTED_P1: *bit_pos = 10; *int_grp = 2; break; 6774 case MADURA_INT_SYS_CL73_AN_COMPLETE_P2: *bit_pos = 9; *int_grp = 2; break; 6775 case MADURA_INT_SYS_CL73_AN_RESTARTED_P2: *bit_pos = 8; *int_grp = 2; break; 6776 case MADURA_INT_LIN_CL73_INCOMPATIBLE_LINK_0: *bit_pos = 7; *int_grp = 2; break; 6777 case MADURA_INT_LIN_CL73_INCOMPATIBLE_LINK_1: *bit_pos = 6; *int_grp = 2; break; 6778 case MADURA_INT_LIN_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_0: *bit_pos = 5; *int_grp = 2; break; 6779 case MADURA_INT_LIN_CL73_LINK_FAIL_INHIBIT_TIMER_DONE_1: *bit_pos = 4; *int_grp = 2; break; 6780 case MADURA_INT_LIN_CL73_AN_COMPLETE_P1: *bit_pos = 3; *int_grp = 2; break; 6781 case MADURA_INT_LIN_CL73_AN_RESTARTED_P1: *bit_pos = 2; *int_grp = 2; break; 6782 case MADURA_INT_LIN_CL73_AN_COMPLETE_P2: *bit_pos = 1; *int_grp = 2; break; 6783 case MADURA_INT_LIN_CL73_AN_RESTARTED_P2: *bit_pos = 0; *int_grp = 2; break; 6784 case MADURA_INT_SYS_SIGDET_FOUND: *bit_pos = 11; *int_grp = 3; break; 6785 case MADURA_INT_SYS_SIGDET_LOST: *bit_pos = 10; *int_grp = 3; break; 6786 case MADURA_INT_SYS_PMD_LOCK_FOUND: *bit_pos = 9; *int_grp = 3; break; 6787 case MADURA_INT_SYS_PMD_LOCK_LOST: *bit_pos = 8; *int_grp = 3; break; 6788 case MADURA_INT_SYS_FAL_0_PMI_ARB_WDOG_EXP: *bit_pos = 7; *int_grp = 3; break; 6789 case MADURA_INT_SYS_FAL_1_PMI_ARB_WDOG_EXP: *bit_pos = 6; *int_grp = 3; break; 6790 case MADURA_INT_LIN_SIGDET_FOUND: *bit_pos = 5; *int_grp = 3; break; 6791 case MADURA_INT_LIN_SIGDET_LOST: *bit_pos = 4; *int_grp = 3; break; 6792 case MADURA_INT_LIN_PMD_LOCK_FOUND: *bit_pos = 3; *int_grp = 3; break; 6793 case MADURA_INT_LIN_PMD_LOCK_LOST: *bit_pos = 2; *int_grp = 3; break; 6794 case MADURA_INT_LIN_FAL_0_PMI_ARB_WDOG_EXP: *bit_pos = 1; *int_grp = 3; break; 6795 case MADURA_INT_LIN_FAL_1_PMI_ARB_WDOG_EXP: *bit_pos = 0; *int_grp = 3; break; 6796 case MADURA_INT_ONEG_INBAND_MSG_LOCK_FOUND: *bit_pos = 15; *int_grp = 4; break; 6797 case MADURA_INT_ONEG_INBAND_MSG_LOCK_LOST: *bit_pos = 14; *int_grp = 4; break; 6798 case MADURA_INT_SYS_PCS_MON_LOCK_FOUND: *bit_pos = 13; *int_grp = 4; break; 6799 case MADURA_INT_SYS_PCS_MON_LOCK_LOST: *bit_pos = 12; *int_grp = 4; break; 6800 case MADURA_INT_LIN_PCS_MON_LOCK_FOUND: *bit_pos = 11; *int_grp = 4; break; 6801 case MADURA_INT_LIN_PCS_MON_LOCK_LOST: *bit_pos = 10; *int_grp = 4; break; 6802 case MADURA_INT_CL91_0_RX_FEC_ALIGN_FOUND: *bit_pos = 9; *int_grp = 4; break; 6803 case MADURA_INT_CL91_0_RX_FEC_ALIGN_LOST: *bit_pos = 8; *int_grp = 4; break; 6804 case MADURA_INT_CL91_1_RX_FEC_ALIGN_FOUND: *bit_pos = 7; *int_grp = 4; break; 6805 case MADURA_INT_CL91_1_RX_FEC_ALIGN_LOST: *bit_pos = 6; *int_grp = 4; break; 6806 case MADURA_INT_CL91_0_TX_PCS_ALIGN_FOUND: *bit_pos = 5; *int_grp = 4; break; 6807 case MADURA_INT_CL91_0_TX_PCS_ALIGN_LOST: *bit_pos = 4; *int_grp = 4; break; 6808 case MADURA_INT_CL91_1_TX_PCS_ALIGN_FOUND: *bit_pos = 3; *int_grp = 4; break; 6809 case MADURA_INT_CL91_1_TX_PCS_ALIGN_LOST: *bit_pos = 2; *int_grp = 4; break; 6810 case MADURA_INT_SYS_FIFOERR: *bit_pos = 1; *int_grp = 4; break; 6811 case MADURA_INT_LIN_FIFOERR: *bit_pos = 0; *int_grp = 4; break; 6812 case MADURA_INT_MODULE1_INTRB_HIGH: *bit_pos = 3; *int_grp = 5; break; 6813 case MADURA_INT_MODULE1_INTRB_LOW: *bit_pos = 2; *int_grp = 5; break; 6814 case MADURA_INT_MODULE2_INTRB_HIGH: *bit_pos = 1; *int_grp = 5; break; 6815 case MADURA_INT_MODULE2_INTRB_LOW: *bit_pos = 0; *int_grp = 5; break; 6816 default: 6817 return PHYMOD_E_PARAM; 6818 } 6819 return PHYMOD_E_NONE; 6820 } 6821 6822 int _madura_ext_intr_enable_set(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t enable) 6823 { 6824 uint16_t intr_grp = 0; 6825 uint16_t bit_pos = 0; 6826 uint16_t intr_mask = 0; 6827 uint16_t data = 0; 6828 BCMI_MADURA_MST_EIERr_t m0_eier; 6829 BCMI_MADURA_PLL_EIERr_t pll_eier; 6830 BCMI_MADURA_CL73_EIERr_t cl73_eier; 6831 BCMI_MADURA_MISC0_EIERr_t misc0_eier; 6832 BCMI_MADURA_MISC1_EIERr_t misc1_eier; 6833 BCMI_MADURA_MCTL_EIERr_t mctrl_eier; 6834 const phymod_access_t *pa = &phy->access; 6835 6836 PHYMOD_MEMSET(&m0_eier, 0, sizeof(BCMI_MADURA_MST_EIERr_t)); 6837 PHYMOD_MEMSET(&pll_eier, 0, sizeof(BCMI_MADURA_PLL_EIERr_t)); 6838 PHYMOD_MEMSET(&cl73_eier, 0, sizeof(BCMI_MADURA_CL73_EIERr_t)); 6839 PHYMOD_MEMSET(&misc0_eier, 0, sizeof(BCMI_MADURA_MISC0_EIERr_t)); 6840 PHYMOD_MEMSET(&misc1_eier, 0, sizeof(BCMI_MADURA_MISC1_EIERr_t)); 6841 PHYMOD_MEMSET(&mctrl_eier, 0, sizeof(BCMI_MADURA_MCTL_EIERr_t)); 6842 6843 /* Get the interrupt bit postion in the reg and interrupt group */ 6844 _madura_get_intr_reg(phy,intr_type, &bit_pos, &intr_grp); 6845 intr_mask = enable ? (0x1 << bit_pos) : (~(0x1 << bit_pos)); 6846 6847 /* Interrupt enable get on specified interrupt group */ 6848 switch(intr_grp) { 6849 case MADURA_MST_INTR_GRP: 6850 PHYMOD_IF_ERR_RETURN( 6851 BCMI_MADURA_READ_MST_EIERr(pa,&m0_eier)); 6852 data = (enable ? intr_mask | BCMI_MADURA_MST_EIERr_GET(m0_eier) : intr_mask & BCMI_MADURA_MST_EIERr_GET(m0_eier)); 6853 BCMI_MADURA_MST_EIERr_SET(m0_eier,data); 6854 PHYMOD_IF_ERR_RETURN( 6855 BCMI_MADURA_WRITE_MST_EIERr(pa,m0_eier)); 6856 break; 6857 case MADURA_PLL_INTR_GRP: 6858 PHYMOD_IF_ERR_RETURN( 6859 BCMI_MADURA_READ_PLL_EIERr(pa,&pll_eier)); 6860 data = (enable ? intr_mask | BCMI_MADURA_PLL_EIERr_GET(pll_eier) : intr_mask & BCMI_MADURA_PLL_EIERr_GET(pll_eier)); 6861 BCMI_MADURA_PLL_EIERr_SET(pll_eier,data); 6862 PHYMOD_IF_ERR_RETURN( 6863 BCMI_MADURA_WRITE_PLL_EIERr(pa,pll_eier)); 6864 break; 6865 case MADURA_CL73_INTR_GRP: 6866 PHYMOD_IF_ERR_RETURN( 6867 BCMI_MADURA_READ_CL73_EIERr(pa,&cl73_eier)); 6868 data = (enable ? intr_mask | BCMI_MADURA_CL73_EIERr_GET(cl73_eier) : intr_mask & BCMI_MADURA_CL73_EIERr_GET(cl73_eier)); 6869 BCMI_MADURA_CL73_EIERr_SET(cl73_eier,data); 6870 PHYMOD_IF_ERR_RETURN( 6871 BCMI_MADURA_WRITE_CL73_EIERr(pa,cl73_eier)); 6872 break; 6873 case MADURA_MISC0_INTR_GRP: 6874 PHYMOD_IF_ERR_RETURN( 6875 BCMI_MADURA_READ_MISC0_EIERr(pa,&misc0_eier)); 6876 data = (enable ? intr_mask | BCMI_MADURA_MISC0_EIERr_GET(misc0_eier) : intr_mask & BCMI_MADURA_MISC0_EIERr_GET(misc0_eier)); 6877 BCMI_MADURA_MISC0_EIERr_SET(misc0_eier,data); 6878 PHYMOD_IF_ERR_RETURN( 6879 BCMI_MADURA_WRITE_MISC0_EIERr(pa,misc0_eier)); 6880 break; 6881 case MADURA_MISC1_INTR_GRP: 6882 PHYMOD_IF_ERR_RETURN( 6883 BCMI_MADURA_READ_MISC1_EIERr(pa,&misc1_eier)); 6884 data = (enable ? intr_mask | BCMI_MADURA_MISC1_EIERr_GET(misc1_eier) : intr_mask & BCMI_MADURA_MISC1_EIERr_GET(misc1_eier)); 6885 BCMI_MADURA_MISC1_EIERr_SET(misc1_eier,data); 6886 PHYMOD_IF_ERR_RETURN( 6887 BCMI_MADURA_WRITE_MISC1_EIERr(pa,misc1_eier)); 6888 break; 6889 case MADURA_MCTRL_INTR_GRP: 6890 PHYMOD_IF_ERR_RETURN( 6891 BCMI_MADURA_READ_MCTL_EIERr(pa,&mctrl_eier)); 6892 data = (enable ? intr_mask | BCMI_MADURA_MCTL_EIERr_GET(mctrl_eier) : intr_mask & BCMI_MADURA_MCTL_EIERr_GET(mctrl_eier)); 6893 BCMI_MADURA_MCTL_EIERr_SET(mctrl_eier,data); 6894 PHYMOD_IF_ERR_RETURN( 6895 BCMI_MADURA_WRITE_MCTL_EIERr(pa,mctrl_eier)); 6896 break; 6897 default: 6898 return PHYMOD_E_PARAM; 6899 } 6900 6901 return PHYMOD_E_NONE; 6902 } 6903 6904 6905 int _madura_ext_intr_enable_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t *enable) 6906 { 6907 uint16_t intr_grp = 0; 6908 uint16_t bit_pos = 0; 6909 uint16_t data = 0; 6910 BCMI_MADURA_MST_EIERr_t m0_eier; 6911 BCMI_MADURA_PLL_EIERr_t pll_eier; 6912 BCMI_MADURA_CL73_EIERr_t cl73_eier; 6913 BCMI_MADURA_MISC0_EIERr_t misc0_eier; 6914 BCMI_MADURA_MISC1_EIERr_t misc1_eier; 6915 BCMI_MADURA_MCTL_EIERr_t mctrl_eier; 6916 const phymod_access_t *pa = &phy->access; 6917 6918 PHYMOD_MEMSET(&m0_eier, 0, sizeof(BCMI_MADURA_MST_EIERr_t)); 6919 PHYMOD_MEMSET(&pll_eier, 0, sizeof(BCMI_MADURA_PLL_EIERr_t)); 6920 PHYMOD_MEMSET(&cl73_eier, 0, sizeof(BCMI_MADURA_CL73_EIERr_t)); 6921 PHYMOD_MEMSET(&misc0_eier, 0, sizeof(BCMI_MADURA_MISC0_EIERr_t)); 6922 PHYMOD_MEMSET(&misc1_eier, 0, sizeof(BCMI_MADURA_MISC1_EIERr_t)); 6923 PHYMOD_MEMSET(&mctrl_eier, 0, sizeof(BCMI_MADURA_MCTL_EIERr_t)); 6924 6925 6926 /* Get the interrupt bit postion in the reg and interrupt group */ 6927 _madura_get_intr_reg(phy,intr_type, &bit_pos, &intr_grp); 6928 6929 /* Interrupt enable get on specified interrupt group */ 6930 switch(intr_grp) { 6931 case MADURA_MST_INTR_GRP: 6932 PHYMOD_IF_ERR_RETURN( 6933 BCMI_MADURA_READ_MST_EIERr(pa,&m0_eier)); 6934 data = BCMI_MADURA_MST_EIERr_GET(m0_eier); 6935 break; 6936 case MADURA_PLL_INTR_GRP: 6937 PHYMOD_IF_ERR_RETURN( 6938 BCMI_MADURA_READ_PLL_EIERr(pa,&pll_eier)); 6939 data = BCMI_MADURA_PLL_EIERr_GET(pll_eier); 6940 break; 6941 case MADURA_CL73_INTR_GRP: 6942 PHYMOD_IF_ERR_RETURN( 6943 BCMI_MADURA_READ_CL73_EIERr(pa,&cl73_eier)); 6944 data = BCMI_MADURA_CL73_EIERr_GET(cl73_eier); 6945 break; 6946 case MADURA_MISC0_INTR_GRP: 6947 PHYMOD_IF_ERR_RETURN( 6948 BCMI_MADURA_READ_MISC0_EIERr(pa,&misc0_eier)); 6949 data = BCMI_MADURA_MISC0_EIERr_GET(misc0_eier); 6950 break; 6951 case MADURA_MISC1_INTR_GRP: 6952 PHYMOD_IF_ERR_RETURN( 6953 BCMI_MADURA_READ_MISC1_EIERr(pa,&misc1_eier)); 6954 data = BCMI_MADURA_MISC1_EIERr_GET(misc1_eier); 6955 break; 6956 case MADURA_MCTRL_INTR_GRP: 6957 PHYMOD_IF_ERR_RETURN( 6958 BCMI_MADURA_READ_MCTL_EIERr(pa,&mctrl_eier)); 6959 data = BCMI_MADURA_MCTL_EIERr_GET(mctrl_eier); 6960 break; 6961 default: 6962 return PHYMOD_E_PARAM; 6963 } 6964 *enable = (data & (0x1 << bit_pos)) ? 1 : 0; 6965 6966 return PHYMOD_E_NONE; 6967 } 6968 6969 6970 int _madura_ext_intr_status_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t *intr_status) 6971 { 6972 uint16_t intr_grp = 0; 6973 uint16_t bit_pos = 0; 6974 uint16_t data = 0; 6975 BCMI_MADURA_MST_EISRr_t m0_eisr; 6976 BCMI_MADURA_PLL_EISRr_t pll_eisr; 6977 BCMI_MADURA_CL73_EISRr_t cl73_eisr; 6978 BCMI_MADURA_MISC0_EISRr_t misc0_eisr; 6979 BCMI_MADURA_MISC1_EISRr_t misc1_eisr; 6980 BCMI_MADURA_MCTL_EISRr_t mctrl_eisr; 6981 const phymod_access_t *pa = &phy->access; 6982 6983 PHYMOD_MEMSET(&m0_eisr, 0, sizeof(BCMI_MADURA_MST_EISRr_t)); 6984 PHYMOD_MEMSET(&pll_eisr, 0, sizeof(BCMI_MADURA_PLL_EISRr_t)); 6985 PHYMOD_MEMSET(&cl73_eisr, 0, sizeof(BCMI_MADURA_CL73_EISRr_t)); 6986 PHYMOD_MEMSET(&misc0_eisr, 0, sizeof(BCMI_MADURA_MISC0_EISRr_t)); 6987 PHYMOD_MEMSET(&misc1_eisr, 0, sizeof(BCMI_MADURA_MISC1_EISRr_t)); 6988 PHYMOD_MEMSET(&mctrl_eisr, 0, sizeof(BCMI_MADURA_MCTL_EISRr_t)); 6989 6990 /* Get the interrupt bit postion in the reg and interrupt group */ 6991 _madura_get_intr_reg(phy,intr_type, &bit_pos, &intr_grp); 6992 6993 /* Interrupt status get on specified interrupt group */ 6994 switch(intr_grp) { 6995 case MADURA_MST_INTR_GRP: 6996 PHYMOD_IF_ERR_RETURN( 6997 BCMI_MADURA_READ_MST_EISRr(pa,&m0_eisr)); 6998 data = BCMI_MADURA_MST_EISRr_GET(m0_eisr); 6999 break; 7000 case MADURA_PLL_INTR_GRP: 7001 PHYMOD_IF_ERR_RETURN( 7002 BCMI_MADURA_READ_PLL_EISRr(pa,&pll_eisr)); 7003 data = BCMI_MADURA_PLL_EISRr_GET(pll_eisr); 7004 break; 7005 case MADURA_CL73_INTR_GRP: 7006 PHYMOD_IF_ERR_RETURN( 7007 BCMI_MADURA_READ_CL73_EISRr(pa,&cl73_eisr)); 7008 data = BCMI_MADURA_CL73_EISRr_GET(cl73_eisr); 7009 break; 7010 case MADURA_MISC0_INTR_GRP: 7011 PHYMOD_IF_ERR_RETURN( 7012 BCMI_MADURA_READ_MISC0_EISRr(pa,&misc0_eisr)); 7013 data = BCMI_MADURA_MISC0_EISRr_GET(misc0_eisr); 7014 break; 7015 case MADURA_MISC1_INTR_GRP: 7016 PHYMOD_IF_ERR_RETURN( 7017 BCMI_MADURA_READ_MISC1_EISRr(pa,&misc1_eisr)); 7018 data = BCMI_MADURA_MISC1_EISRr_GET(misc1_eisr); 7019 break; 7020 case MADURA_MCTRL_INTR_GRP: 7021 PHYMOD_IF_ERR_RETURN( 7022 BCMI_MADURA_READ_MCTL_EISRr(pa,&mctrl_eisr)); 7023 data = BCMI_MADURA_MCTL_EISRr_GET(mctrl_eisr); 7024 break; 7025 default: 7026 return PHYMOD_E_PARAM; 7027 } 7028 *intr_status = (data & (0x1 << bit_pos)) ? 1 : 0; 7029 7030 return PHYMOD_E_NONE; 7031 } 7032 7033 int _madura_ext_intr_status_clear(const phymod_phy_access_t *phy, uint32_t intr_type) 7034 { 7035 uint16_t intr_grp = 0; 7036 uint16_t bit_pos = 0; 7037 uint16_t intr_mask = 0; 7038 BCMI_MADURA_MST_EISRr_t m0_eisr; 7039 BCMI_MADURA_PLL_EISRr_t pll_eisr; 7040 BCMI_MADURA_CL73_EISRr_t cl73_eisr; 7041 BCMI_MADURA_MISC0_EISRr_t misc0_eisr; 7042 BCMI_MADURA_MISC1_EISRr_t misc1_eisr; 7043 BCMI_MADURA_MCTL_EISRr_t mctrl_eisr; 7044 const phymod_access_t *pa = &phy->access; 7045 7046 PHYMOD_MEMSET(&m0_eisr, 0, sizeof(BCMI_MADURA_MST_EISRr_t)); 7047 PHYMOD_MEMSET(&pll_eisr, 0, sizeof(BCMI_MADURA_PLL_EISRr_t)); 7048 PHYMOD_MEMSET(&cl73_eisr, 0, sizeof(BCMI_MADURA_CL73_EISRr_t)); 7049 PHYMOD_MEMSET(&misc0_eisr, 0, sizeof(BCMI_MADURA_MISC0_EISRr_t)); 7050 PHYMOD_MEMSET(&misc1_eisr, 0, sizeof(BCMI_MADURA_MISC1_EISRr_t)); 7051 PHYMOD_MEMSET(&mctrl_eisr, 0, sizeof(BCMI_MADURA_MCTL_EISRr_t)); 7052 7053 /* Get the interrupt bit postion in the reg and interrupt group */ 7054 _madura_get_intr_reg(phy,intr_type, &bit_pos, &intr_grp); 7055 intr_mask = 0x1 << bit_pos; 7056 7057 /* Interrupt status get on specified interrupt group */ 7058 switch(intr_grp) { 7059 case MADURA_MST_INTR_GRP: 7060 PHYMOD_IF_ERR_RETURN( 7061 BCMI_MADURA_READ_MST_EISRr(pa,&m0_eisr)); 7062 BCMI_MADURA_MST_EISRr_SET(m0_eisr, intr_mask ); 7063 PHYMOD_IF_ERR_RETURN( 7064 BCMI_MADURA_WRITE_MST_EISRr(pa,m0_eisr)); 7065 break; 7066 case MADURA_PLL_INTR_GRP: 7067 PHYMOD_IF_ERR_RETURN( 7068 BCMI_MADURA_READ_PLL_EISRr(pa,&pll_eisr)); 7069 BCMI_MADURA_PLL_EISRr_SET(pll_eisr, intr_mask ); 7070 PHYMOD_IF_ERR_RETURN( 7071 BCMI_MADURA_WRITE_PLL_EISRr(pa,pll_eisr)); 7072 break; 7073 case MADURA_CL73_INTR_GRP: 7074 PHYMOD_IF_ERR_RETURN( 7075 BCMI_MADURA_READ_CL73_EISRr(pa,&cl73_eisr)); 7076 BCMI_MADURA_CL73_EISRr_SET(cl73_eisr, intr_mask ); 7077 PHYMOD_IF_ERR_RETURN( 7078 BCMI_MADURA_WRITE_CL73_EISRr(pa,cl73_eisr)); 7079 break; 7080 case MADURA_MISC0_INTR_GRP: 7081 PHYMOD_IF_ERR_RETURN( 7082 BCMI_MADURA_READ_MISC0_EISRr(pa,&misc0_eisr)); 7083 BCMI_MADURA_MISC0_EISRr_SET(misc0_eisr, intr_mask ); 7084 PHYMOD_IF_ERR_RETURN( 7085 BCMI_MADURA_WRITE_MISC0_EISRr(pa,misc0_eisr)); 7086 break; 7087 case MADURA_MISC1_INTR_GRP: 7088 PHYMOD_IF_ERR_RETURN( 7089 BCMI_MADURA_READ_MISC1_EISRr(pa,&misc1_eisr)); 7090 BCMI_MADURA_MISC1_EISRr_SET(misc1_eisr, intr_mask ); 7091 PHYMOD_IF_ERR_RETURN( 7092 BCMI_MADURA_WRITE_MISC1_EISRr(pa,misc1_eisr)); 7093 break; 7094 case MADURA_MCTRL_INTR_GRP: 7095 PHYMOD_IF_ERR_RETURN( 7096 BCMI_MADURA_READ_MCTL_EISRr(pa,&mctrl_eisr)); 7097 BCMI_MADURA_MCTL_EISRr_SET(mctrl_eisr, intr_mask ); 7098 PHYMOD_IF_ERR_RETURN( 7099 BCMI_MADURA_WRITE_MCTL_EISRr(pa,mctrl_eisr)); 7100 break; 7101 default: 7102 return PHYMOD_E_PARAM; 7103 } 7104 7105 return PHYMOD_E_NONE; 7106 } 7107 7108 int _madura_module_write(const phymod_access_t *pa, uint32_t slv_dev_addr, uint32_t start_addr, 7109 uint32_t no_of_bytes, const uint8_t *write_data) 7110 { 7111 uint16_t lane_mask = 0; 7112 uint32_t index = 0; 7113 uint32_t lower_page_bytes = 0; 7114 uint32_t upper_page_bytes = 0; 7115 uint32_t upper_page_flag = 0; 7116 uint32_t lower_page_flag = 0; 7117 uint32_t lower_page_start_addr = 0; 7118 uint32_t upper_page_start_addr = 0; 7119 uint16_t START_OF_NVRAM = 0x0; 7120 BCMI_MADURA_GEN_CTL3r_t gen_ctrl3; 7121 BCMI_MADURA_GEN_CTL1r_t gen_ctrl1; 7122 BCMI_MADURA_DEV_IDr_t dev_id; 7123 BCMI_MADURA_XFER_ADDRr_t mod_xfer_add; 7124 BCMI_MADURA_GPIO_1_CTLr_t gpio1_ctrl; 7125 BCMI_MADURA_GPIO_3_CTLr_t gpio3_ctrl; 7126 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL0r_t io_ctrl0; 7127 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL1r_t io_ctrl1; 7128 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL2r_t io_ctrl2; 7129 7130 PHYMOD_MEMSET(&gpio1_ctrl, 0, sizeof(BCMI_MADURA_GPIO_1_CTLr_t)); 7131 PHYMOD_MEMSET(&gpio3_ctrl, 0, sizeof(BCMI_MADURA_GPIO_3_CTLr_t)); 7132 PHYMOD_MEMSET(&io_ctrl0, 0, sizeof(BCMI_MADURA_GENERAL_PURPOSE_IO_CTL0r_t)); 7133 PHYMOD_MEMSET(&io_ctrl1, 0, sizeof(BCMI_MADURA_GENERAL_PURPOSE_IO_CTL1r_t)); 7134 PHYMOD_MEMSET(&io_ctrl2, 0, sizeof(BCMI_MADURA_GENERAL_PURPOSE_IO_CTL2r_t)); 7135 PHYMOD_MEMSET(&gen_ctrl3, 0, sizeof(BCMI_MADURA_GEN_CTL3r_t)); 7136 PHYMOD_MEMSET(&gen_ctrl1, 0, sizeof(BCMI_MADURA_GEN_CTL1r_t)); 7137 PHYMOD_MEMSET(&dev_id, 0, sizeof(BCMI_MADURA_DEV_IDr_t)); 7138 PHYMOD_MEMSET(&mod_xfer_add, 0, sizeof(BCMI_MADURA_XFER_ADDRr_t)); 7139 7140 if(start_addr > 255) { 7141 return PHYMOD_E_PARAM; 7142 } 7143 7144 /*setting gpio workaround for Madura I2C*/ 7145 BCMI_MADURA_GPIO_3_CTLr_SET(gpio3_ctrl,0x00e2); 7146 BCMI_MADURA_GPIO_1_CTLr_SET(gpio1_ctrl,0x00e2); 7147 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL0r_SET(io_ctrl0,0x10); 7148 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL1r_SET(io_ctrl1,0x1); 7149 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL2r_SET(io_ctrl2,0x31); 7150 PHYMOD_IF_ERR_RETURN( 7151 BCMI_MADURA_WRITE_GPIO_1_CTLr(pa,gpio1_ctrl)); 7152 PHYMOD_IF_ERR_RETURN( 7153 BCMI_MADURA_WRITE_GPIO_3_CTLr(pa,gpio3_ctrl)); 7154 PHYMOD_IF_ERR_RETURN( 7155 BCMI_MADURA_WRITE_GENERAL_PURPOSE_IO_CTL0r(pa,io_ctrl0)); 7156 PHYMOD_IF_ERR_RETURN( 7157 BCMI_MADURA_WRITE_GENERAL_PURPOSE_IO_CTL1r(pa,io_ctrl1)); 7158 PHYMOD_IF_ERR_RETURN( 7159 BCMI_MADURA_WRITE_GENERAL_PURPOSE_IO_CTL2r(pa,io_ctrl2)); 7160 7161 /* qsfp mode or legacy mode */ 7162 PHYMOD_IF_ERR_RETURN( 7163 BCMI_MADURA_READ_GEN_CTL3r(pa, &gen_ctrl3)); 7164 BCMI_MADURA_GEN_CTL3r_QSFP_MODEf_SET(gen_ctrl3,1); 7165 BCMI_MADURA_GEN_CTL3r_UCSPI_SLOWf_SET(gen_ctrl3,0); 7166 PHYMOD_IF_ERR_RETURN( 7167 BCMI_MADURA_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 7168 7169 /* qsfp mode reset at begining */ 7170 PHYMOD_IF_ERR_RETURN( 7171 BCMI_MADURA_READ_GEN_CTL1r(pa, &gen_ctrl1)); 7172 BCMI_MADURA_GEN_CTL1r_MODCTRL_RSTBf_SET(gen_ctrl1,0); 7173 PHYMOD_IF_ERR_RETURN( 7174 BCMI_MADURA_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 7175 BCMI_MADURA_GEN_CTL1r_MODCTRL_RSTBf_SET(gen_ctrl1,1); 7176 PHYMOD_IF_ERR_RETURN( 7177 BCMI_MADURA_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 7178 7179 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 7180 7181 if (lane_mask <= 0xF) { /* QSFP module 0 */ 7182 /* Active Low Select to read NVRAM for QSFP module 0 */ 7183 PHYMOD_IF_ERR_RETURN( 7184 BCMI_MADURA_READ_GEN_CTL3r(pa, &gen_ctrl3)); 7185 BCMI_MADURA_GEN_CTL3r_QSFP_SEL0Bf_SET(gen_ctrl3,0); 7186 BCMI_MADURA_GEN_CTL3r_QSFP_SEL1Bf_SET(gen_ctrl3,1); 7187 PHYMOD_IF_ERR_RETURN( 7188 BCMI_MADURA_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 7189 /* Module 0 NVRAM ADDR is MADURA_MODULE_CNTRL_RAM_NVR0_ADR */ 7190 START_OF_NVRAM = 0x0; 7191 } else if (lane_mask <= 0xF0) { /* QSFP module 1 */ 7192 /* Active Low Select to read NVRAM for QSFP module 1 */ 7193 PHYMOD_IF_ERR_RETURN( 7194 BCMI_MADURA_READ_GEN_CTL3r(pa, &gen_ctrl3)); 7195 BCMI_MADURA_GEN_CTL3r_QSFP_SEL0Bf_SET(gen_ctrl3,1); 7196 BCMI_MADURA_GEN_CTL3r_QSFP_SEL1Bf_SET(gen_ctrl3,0); 7197 PHYMOD_IF_ERR_RETURN( 7198 BCMI_MADURA_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 7199 /* Module 1 NVRAM ADDR is MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM*/ 7200 START_OF_NVRAM = 0x100; 7201 } 7202 7203 /* Configure the slave device ID default is 0x50 */ 7204 PHYMOD_IF_ERR_RETURN( 7205 BCMI_MADURA_READ_DEV_IDr(pa,&dev_id)); 7206 BCMI_MADURA_DEV_IDr_SL_DEV_ADDf_SET(dev_id,slv_dev_addr); 7207 PHYMOD_IF_ERR_RETURN( 7208 BCMI_MADURA_WRITE_DEV_IDr(pa,dev_id)); 7209 7210 if(no_of_bytes == 0) { 7211 /* Perform module controller reset and FLUSH */ 7212 PHYMOD_IF_ERR_RETURN( 7213 _madura_set_module_command(pa, 0, 0, 0, MADURA_FLUSH)); 7214 } 7215 /* if requested number of bytes are not within the boundary (0- 255) 7216 * need to calculate what maximum number of bytes can be taken into 7217 * account for reading or writing to module 7218 */ 7219 if ((no_of_bytes + start_addr) >= 256) { 7220 no_of_bytes = 255 - start_addr + 1; 7221 } 7222 7223 /* To determine page to be written is lower page or upper page or 7224 * both lower and upper page 7225 */ 7226 if ((start_addr + no_of_bytes - 1) > 127) { 7227 /* lower page */ 7228 if (start_addr <= 127) { 7229 lower_page_bytes = 127 - start_addr + 1; 7230 lower_page_flag = 1; 7231 lower_page_start_addr = start_addr; 7232 } 7233 /* upper page */ 7234 if ((start_addr + no_of_bytes) > 127) { 7235 upper_page_flag = 1; 7236 upper_page_bytes = no_of_bytes - lower_page_bytes; 7237 if(start_addr > 128) { 7238 upper_page_start_addr = start_addr; 7239 } else { 7240 upper_page_start_addr = 128; 7241 } 7242 } 7243 } else { /* only lower page */ 7244 lower_page_bytes = no_of_bytes; 7245 lower_page_flag = 1; 7246 lower_page_start_addr = start_addr; 7247 } 7248 7249 /* Write data to NVRAM */ 7250 for (index = 0; index < no_of_bytes; index++) { 7251 PHYMOD_IF_ERR_RETURN( 7252 PHYMOD_BUS_WRITE(pa,0x10000 + MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + start_addr + index, write_data[index])); 7253 } 7254 7255 if(lower_page_flag) { 7256 PHYMOD_IF_ERR_RETURN( 7257 _madura_set_module_command(pa, 0, 0, 0, MADURA_FLUSH)); 7258 for (index = 0; index < (lower_page_bytes / 4); index ++) { 7259 PHYMOD_IF_ERR_RETURN( 7260 _madura_set_module_command(pa, MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 7261 lower_page_start_addr + (4 * index), lower_page_start_addr + (4 * index), 3, MADURA_WRITE)); 7262 } 7263 if ((lower_page_bytes % 4) > 0) { 7264 PHYMOD_IF_ERR_RETURN( 7265 _madura_set_module_command(pa, MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 7266 lower_page_start_addr + (4 * index), lower_page_start_addr + (4 * index), 7267 ((lower_page_bytes % 4) - 1), MADURA_WRITE)); 7268 } 7269 lower_page_flag = 0; 7270 } 7271 7272 if(upper_page_flag) { 7273 PHYMOD_IF_ERR_RETURN( 7274 _madura_set_module_command(pa, 0, 0, 0, MADURA_FLUSH)); 7275 for (index = 0; index < (upper_page_bytes / 4); index++) { 7276 PHYMOD_IF_ERR_RETURN( 7277 _madura_set_module_command(pa, (MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 7278 upper_page_start_addr + (4 * index)), upper_page_start_addr + (4 * index), 3, MADURA_WRITE)); 7279 } 7280 if ((upper_page_bytes%4) > 0) { 7281 PHYMOD_IF_ERR_RETURN( 7282 _madura_set_module_command(pa, (MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 7283 upper_page_start_addr + (4 * index)), upper_page_start_addr + (4 * index), 7284 ((upper_page_bytes % 4) - 1), MADURA_WRITE)); 7285 } 7286 upper_page_flag = 0; 7287 } 7288 return PHYMOD_E_NONE; 7289 } 7290 7291 int _madura_module_read(const phymod_access_t *pa, uint32_t slv_dev_addr, uint32_t start_addr, 7292 uint32_t no_of_bytes, uint8_t *read_data) 7293 { 7294 uint32_t index = 0; 7295 uint16_t lane_mask = 0; 7296 uint32_t rd_data = 0; 7297 uint32_t lower_page_bytes = 0; 7298 uint32_t upper_page_bytes = 0; 7299 uint32_t upper_page_flag = 0; 7300 uint32_t lower_page_start_addr = 0; 7301 uint32_t upper_page_start_addr = 0; 7302 uint32_t lower_page_flag = 0; 7303 uint16_t START_OF_NVRAM = 0x0; 7304 BCMI_MADURA_GEN_CTL3r_t gen_ctrl3; 7305 BCMI_MADURA_GEN_CTL1r_t gen_ctrl1; 7306 BCMI_MADURA_DEV_IDr_t dev_id; 7307 BCMI_MADURA_XFER_ADDRr_t mod_xfer_add; 7308 BCMI_MADURA_GPIO_1_CTLr_t gpio1_ctrl; 7309 BCMI_MADURA_GPIO_3_CTLr_t gpio3_ctrl; 7310 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL0r_t io_ctrl0; 7311 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL1r_t io_ctrl1; 7312 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL2r_t io_ctrl2; 7313 7314 PHYMOD_MEMSET(&gpio1_ctrl, 0, sizeof(BCMI_MADURA_GPIO_1_CTLr_t)); 7315 PHYMOD_MEMSET(&gpio3_ctrl, 0, sizeof(BCMI_MADURA_GPIO_3_CTLr_t)); 7316 PHYMOD_MEMSET(&io_ctrl0, 0, sizeof(BCMI_MADURA_GENERAL_PURPOSE_IO_CTL0r_t)); 7317 PHYMOD_MEMSET(&io_ctrl1, 0, sizeof(BCMI_MADURA_GENERAL_PURPOSE_IO_CTL1r_t)); 7318 PHYMOD_MEMSET(&io_ctrl2, 0, sizeof(BCMI_MADURA_GENERAL_PURPOSE_IO_CTL2r_t)); 7319 PHYMOD_MEMSET(&gen_ctrl3, 0, sizeof(BCMI_MADURA_GEN_CTL3r_t)); 7320 PHYMOD_MEMSET(&gen_ctrl1, 0, sizeof(BCMI_MADURA_GEN_CTL1r_t)); 7321 PHYMOD_MEMSET(&dev_id, 0, sizeof(BCMI_MADURA_DEV_IDr_t)); 7322 PHYMOD_MEMSET(&mod_xfer_add, 0, sizeof(BCMI_MADURA_XFER_ADDRr_t)); 7323 7324 if(start_addr > 255) { 7325 return PHYMOD_E_PARAM; 7326 } 7327 7328 /*setting gpio workaround for Madura I2C*/ 7329 BCMI_MADURA_GPIO_3_CTLr_SET(gpio3_ctrl,0x00e2); 7330 BCMI_MADURA_GPIO_1_CTLr_SET(gpio1_ctrl,0x00e2); 7331 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL0r_SET(io_ctrl0,0x10); 7332 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL1r_SET(io_ctrl1,0x1); 7333 BCMI_MADURA_GENERAL_PURPOSE_IO_CTL2r_SET(io_ctrl2,0x31); 7334 PHYMOD_IF_ERR_RETURN( 7335 BCMI_MADURA_WRITE_GPIO_1_CTLr(pa,gpio1_ctrl)); 7336 PHYMOD_IF_ERR_RETURN( 7337 BCMI_MADURA_WRITE_GPIO_3_CTLr(pa,gpio3_ctrl)); 7338 PHYMOD_IF_ERR_RETURN( 7339 BCMI_MADURA_WRITE_GENERAL_PURPOSE_IO_CTL0r(pa,io_ctrl0)); 7340 PHYMOD_IF_ERR_RETURN( 7341 BCMI_MADURA_WRITE_GENERAL_PURPOSE_IO_CTL1r(pa,io_ctrl1)); 7342 PHYMOD_IF_ERR_RETURN( 7343 BCMI_MADURA_WRITE_GENERAL_PURPOSE_IO_CTL2r(pa,io_ctrl2)); 7344 7345 /* qsfp mode or legacy mode */ 7346 PHYMOD_IF_ERR_RETURN( 7347 BCMI_MADURA_READ_GEN_CTL3r(pa, &gen_ctrl3)); 7348 BCMI_MADURA_GEN_CTL3r_QSFP_MODEf_SET(gen_ctrl3,1); 7349 BCMI_MADURA_GEN_CTL3r_UCSPI_SLOWf_SET(gen_ctrl3,0); 7350 PHYMOD_IF_ERR_RETURN( 7351 BCMI_MADURA_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 7352 7353 /* qsfp mode reset at begining */ 7354 PHYMOD_IF_ERR_RETURN( 7355 BCMI_MADURA_READ_GEN_CTL1r(pa, &gen_ctrl1)); 7356 BCMI_MADURA_GEN_CTL1r_MODCTRL_RSTBf_SET(gen_ctrl1,0); 7357 PHYMOD_IF_ERR_RETURN( 7358 BCMI_MADURA_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 7359 BCMI_MADURA_GEN_CTL1r_MODCTRL_RSTBf_SET(gen_ctrl1,1); 7360 PHYMOD_IF_ERR_RETURN( 7361 BCMI_MADURA_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 7362 7363 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 7364 if (lane_mask <= 0xF) { /* QSFP module 0 */ 7365 /* Active Low Select to read NVRAM for QSFP module 0 */ 7366 PHYMOD_IF_ERR_RETURN( 7367 BCMI_MADURA_READ_GEN_CTL3r(pa, &gen_ctrl3)); 7368 BCMI_MADURA_GEN_CTL3r_QSFP_SEL0Bf_SET(gen_ctrl3,0); 7369 BCMI_MADURA_GEN_CTL3r_QSFP_SEL1Bf_SET(gen_ctrl3,1); 7370 PHYMOD_IF_ERR_RETURN( 7371 BCMI_MADURA_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 7372 /* Module 0 NVRAM ADDR is MADURA_MODULE_CNTRL_RAM_NVR0_ADR */ 7373 START_OF_NVRAM = 0x0; 7374 } else if (lane_mask <= 0xF0) { /* QSFP module 1 */ 7375 /* Active Low Select to read NVRAM for QSFP module 1 */ 7376 PHYMOD_IF_ERR_RETURN( 7377 BCMI_MADURA_READ_GEN_CTL3r(pa, &gen_ctrl3)); 7378 BCMI_MADURA_GEN_CTL3r_QSFP_SEL0Bf_SET(gen_ctrl3,1); 7379 BCMI_MADURA_GEN_CTL3r_QSFP_SEL1Bf_SET(gen_ctrl3,0); 7380 PHYMOD_IF_ERR_RETURN( 7381 BCMI_MADURA_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 7382 /* Module 1 NVRAM ADDR is MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM*/ 7383 START_OF_NVRAM = 0x100; 7384 } 7385 7386 /* Configure the slave device ID default is 0x50 */ 7387 PHYMOD_IF_ERR_RETURN( 7388 BCMI_MADURA_READ_DEV_IDr(pa,&dev_id)); 7389 BCMI_MADURA_DEV_IDr_SL_DEV_ADDf_SET(dev_id,slv_dev_addr); 7390 PHYMOD_IF_ERR_RETURN( 7391 BCMI_MADURA_WRITE_DEV_IDr(pa,dev_id)); 7392 7393 if(no_of_bytes == 0) { 7394 /* Perform module controller reset and FLUSH */ 7395 PHYMOD_IF_ERR_RETURN( 7396 _madura_set_module_command(pa, 0, 0, 0, MADURA_FLUSH)); 7397 } 7398 if ((no_of_bytes + start_addr) >= 256) { 7399 no_of_bytes = 255 - start_addr + 1; 7400 } 7401 7402 /* To determine page to be written is lower page or upper page or 7403 * both lower and upper page 7404 */ 7405 if ((start_addr+no_of_bytes - 1) > 127) { 7406 /* lower page */ 7407 if (start_addr <= 127) { 7408 lower_page_bytes = 127 - start_addr + 1; 7409 lower_page_flag = 1; 7410 lower_page_start_addr = start_addr; 7411 } 7412 /* upper page */ 7413 if ((start_addr + no_of_bytes) > 127) { 7414 upper_page_flag = 1; 7415 upper_page_bytes = no_of_bytes - lower_page_bytes; 7416 if(start_addr > 128) { 7417 upper_page_start_addr = start_addr; 7418 } else { 7419 upper_page_start_addr = 128; 7420 } 7421 } 7422 } else { /* only lower page */ 7423 lower_page_bytes = no_of_bytes; 7424 lower_page_flag = 1; 7425 lower_page_start_addr = start_addr; 7426 } 7427 7428 if (lower_page_flag) { 7429 PHYMOD_IF_ERR_RETURN( 7430 _madura_set_module_command(pa, 0, 0, 0, MADURA_FLUSH)); 7431 PHYMOD_IF_ERR_RETURN( 7432 _madura_set_module_command(pa, MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 7433 lower_page_start_addr, lower_page_start_addr, lower_page_bytes - 1, MADURA_RANDOM_ADDRESS_READ)); 7434 lower_page_flag = 0; 7435 } 7436 7437 /* Need to check with chip team how we can read upper page */ 7438 if (upper_page_flag) { 7439 PHYMOD_IF_ERR_RETURN( 7440 _madura_set_module_command(pa, 0, 0, 0, MADURA_FLUSH)); 7441 PHYMOD_IF_ERR_RETURN( 7442 _madura_set_module_command(pa, MADURA_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 7443 upper_page_start_addr, upper_page_start_addr, upper_page_bytes - 1, MADURA_RANDOM_ADDRESS_READ)); 7444 upper_page_flag = 0; 7445 } 7446 /* Read data from NVRAM using I2C*/ 7447 for (index = 0; index < no_of_bytes; index++) { 7448 PHYMOD_IF_ERR_RETURN( 7449 PHYMOD_BUS_READ(pa,0x10000 + MADURA_MODULE_CNTRL_RAM_NVR0_ADR + start_addr + index , &rd_data)); 7450 read_data[index] = (unsigned char) (rd_data & 0xff); 7451 } 7452 7453 return PHYMOD_E_NONE; 7454 } 7455 7456 int _madura_set_module_command(const phymod_access_t *pa, uint16_t xfer_addr, 7457 uint32_t slv_addr, unsigned char xfer_cnt, MADURA_I2CM_CMD_E cmd) 7458 { 7459 BCMI_MADURA_MODULE_CTL_CTLr_t module_ctrl; 7460 BCMI_MADURA_MODULE_CTL_STSr_t mctrl_status; 7461 BCMI_MADURA_XFER_CNTr_t mod_xfer_cnt; 7462 BCMI_MADURA_ADDRr_t mod_add; 7463 BCMI_MADURA_XFER_ADDRr_t mod_xfer_add; 7464 uint16_t retry_count = 500, data = 0; 7465 uint32_t wait_timeout_us = 0; 7466 wait_timeout_us = ((2*(xfer_cnt+1))*100)/5; 7467 7468 PHYMOD_MEMSET(&module_ctrl, 0, sizeof(BCMI_MADURA_MODULE_CTL_CTLr_t)); 7469 PHYMOD_MEMSET(&mod_xfer_add, 0, sizeof(BCMI_MADURA_XFER_ADDRr_t)); 7470 PHYMOD_MEMSET(&mod_xfer_cnt, 0, sizeof(BCMI_MADURA_XFER_CNTr_t)); 7471 PHYMOD_MEMSET(&mctrl_status, 0, sizeof(BCMI_MADURA_MODULE_CTL_STSr_t)); 7472 PHYMOD_MEMSET(&mod_add, 0, sizeof(BCMI_MADURA_ADDRr_t)); 7473 if (cmd == MADURA_FLUSH) { 7474 BCMI_MADURA_MODULE_CTL_CTLr_SET(module_ctrl,0xC000); 7475 PHYMOD_IF_ERR_RETURN( 7476 BCMI_MADURA_WRITE_MODULE_CTL_CTLr(pa,module_ctrl)); 7477 } else { 7478 BCMI_MADURA_XFER_ADDRr_SET(mod_xfer_add,xfer_addr); 7479 BCMI_MADURA_XFER_CNTr_XFER_CNTf_SET(mod_xfer_cnt,xfer_cnt); 7480 PHYMOD_IF_ERR_RETURN( 7481 BCMI_MADURA_WRITE_XFER_ADDRr(pa,mod_xfer_add)); 7482 PHYMOD_IF_ERR_RETURN( 7483 BCMI_MADURA_WRITE_XFER_CNTr(pa,mod_xfer_cnt)); 7484 if (cmd == MADURA_CURRENT_ADDRESS_READ) { 7485 BCMI_MADURA_MODULE_CTL_CTLr_SET(module_ctrl,0x8001); 7486 PHYMOD_IF_ERR_RETURN( 7487 BCMI_MADURA_WRITE_MODULE_CTL_CTLr(pa,module_ctrl)); 7488 } else if (cmd == MADURA_RANDOM_ADDRESS_READ ) { 7489 BCMI_MADURA_ADDRr_SET(mod_add, slv_addr); 7490 BCMI_MADURA_MODULE_CTL_CTLr_SET(module_ctrl,0x8003); 7491 PHYMOD_IF_ERR_RETURN( 7492 BCMI_MADURA_WRITE_ADDRr(pa,mod_add)); 7493 PHYMOD_IF_ERR_RETURN( 7494 BCMI_MADURA_WRITE_MODULE_CTL_CTLr(pa,module_ctrl)); 7495 } else { 7496 BCMI_MADURA_ADDRr_SET(mod_add, slv_addr); 7497 BCMI_MADURA_MODULE_CTL_CTLr_SET(module_ctrl,0x8022); 7498 PHYMOD_IF_ERR_RETURN( 7499 BCMI_MADURA_WRITE_ADDRr(pa,mod_add)); 7500 PHYMOD_IF_ERR_RETURN( 7501 BCMI_MADURA_WRITE_MODULE_CTL_CTLr(pa,module_ctrl)); 7502 } 7503 } 7504 7505 if ((cmd == MADURA_CURRENT_ADDRESS_READ) || 7506 (cmd == MADURA_RANDOM_ADDRESS_READ) || 7507 (cmd == MADURA_WRITE)) { 7508 do { 7509 PHYMOD_IF_ERR_RETURN( 7510 BCMI_MADURA_READ_MODULE_CTL_STSr(pa,&mctrl_status)); 7511 data = BCMI_MADURA_MODULE_CTL_STSr_XACTION_DONEf_GET(mctrl_status); 7512 PHYMOD_USLEEP(wait_timeout_us); 7513 } while((data == 0) && --retry_count); 7514 if(!retry_count) { 7515 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_TIMEOUT, (_PHYMOD_MSG("Module controller: I2C transaction failed.."))); 7516 } 7517 } 7518 7519 BCMI_MADURA_MODULE_CTL_CTLr_SET(module_ctrl,0x3); 7520 PHYMOD_IF_ERR_RETURN( 7521 BCMI_MADURA_WRITE_MODULE_CTL_CTLr(pa,module_ctrl)); 7522 7523 return PHYMOD_E_NONE; 7524 } 7525 7526 int _madura_gpio_config_set(const phymod_access_t *pa, int pin_number, phymod_gpio_mode_t gpio_mode) 7527 { 7528 uint16_t data = 0; 7529 BCMI_MADURA_GPIO_0_CTLr_t pad_ctrl_gpio_0_ctrl; 7530 BCMI_MADURA_GPIO_1_CTLr_t pad_ctrl_gpio_1_ctrl; 7531 BCMI_MADURA_GPIO_2_CTLr_t pad_ctrl_gpio_2_ctrl; 7532 BCMI_MADURA_GPIO_3_CTLr_t pad_ctrl_gpio_3_ctrl; 7533 7534 PHYMOD_MEMSET(&pad_ctrl_gpio_0_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_0_CTLr_t)); 7535 PHYMOD_MEMSET(&pad_ctrl_gpio_1_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_1_CTLr_t)); 7536 PHYMOD_MEMSET(&pad_ctrl_gpio_2_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_2_CTLr_t)); 7537 PHYMOD_MEMSET(&pad_ctrl_gpio_3_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_3_CTLr_t)); 7538 if (pin_number > 3) { 7539 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7540 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 3)"))); 7541 } 7542 7543 switch(pin_number) 7544 { 7545 case 0: 7546 PHYMOD_IF_ERR_RETURN( 7547 BCMI_MADURA_READ_GPIO_0_CTLr(pa,&pad_ctrl_gpio_0_ctrl)); 7548 break; 7549 case 1: 7550 PHYMOD_IF_ERR_RETURN( 7551 BCMI_MADURA_READ_GPIO_1_CTLr(pa,&pad_ctrl_gpio_1_ctrl)); 7552 break; 7553 case 2: 7554 PHYMOD_IF_ERR_RETURN( 7555 BCMI_MADURA_READ_GPIO_2_CTLr(pa,&pad_ctrl_gpio_2_ctrl)); 7556 break; 7557 case 3: 7558 PHYMOD_IF_ERR_RETURN( 7559 BCMI_MADURA_READ_GPIO_3_CTLr(pa,&pad_ctrl_gpio_3_ctrl)); 7560 break; 7561 default: 7562 return PHYMOD_E_PARAM; 7563 } 7564 7565 switch (gpio_mode) { 7566 case phymodGpioModeDisabled: 7567 return PHYMOD_E_NONE; 7568 case phymodGpioModeOutput: 7569 data = 0; 7570 break; 7571 case phymodGpioModeInput: 7572 data = 1; 7573 break; 7574 default: 7575 return PHYMOD_E_PARAM; 7576 } 7577 7578 switch(pin_number) 7579 { 7580 case 0: 7581 BCMI_MADURA_GPIO_0_CTLr_GPIO_0_OEBf_SET(pad_ctrl_gpio_0_ctrl,data); 7582 PHYMOD_IF_ERR_RETURN( 7583 BCMI_MADURA_WRITE_GPIO_0_CTLr(pa,pad_ctrl_gpio_0_ctrl)); 7584 break; 7585 case 1: 7586 BCMI_MADURA_GPIO_1_CTLr_GPIO_1_OEBf_SET(pad_ctrl_gpio_1_ctrl,data); 7587 PHYMOD_IF_ERR_RETURN( 7588 BCMI_MADURA_WRITE_GPIO_1_CTLr(pa,pad_ctrl_gpio_1_ctrl)); 7589 break; 7590 case 2: 7591 BCMI_MADURA_GPIO_2_CTLr_GPIO_2_OEBf_SET(pad_ctrl_gpio_2_ctrl,data); 7592 PHYMOD_IF_ERR_RETURN( 7593 BCMI_MADURA_WRITE_GPIO_2_CTLr(pa,pad_ctrl_gpio_2_ctrl)); 7594 break; 7595 case 3: 7596 BCMI_MADURA_GPIO_3_CTLr_GPIO_3_OEBf_SET(pad_ctrl_gpio_3_ctrl,data); 7597 PHYMOD_IF_ERR_RETURN( 7598 BCMI_MADURA_WRITE_GPIO_3_CTLr(pa,pad_ctrl_gpio_3_ctrl)); 7599 break; 7600 } 7601 7602 7603 return PHYMOD_E_NONE; 7604 } 7605 7606 int _madura_gpio_config_get(const phymod_access_t *pa, int pin_number, phymod_gpio_mode_t* gpio_mode) 7607 { 7608 uint16_t data = 0; 7609 BCMI_MADURA_GPIO_0_CTLr_t pad_ctrl_gpio_0_ctrl; 7610 BCMI_MADURA_GPIO_1_CTLr_t pad_ctrl_gpio_1_ctrl; 7611 BCMI_MADURA_GPIO_2_CTLr_t pad_ctrl_gpio_2_ctrl; 7612 BCMI_MADURA_GPIO_3_CTLr_t pad_ctrl_gpio_3_ctrl; 7613 7614 PHYMOD_MEMSET(&pad_ctrl_gpio_0_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_0_CTLr_t)); 7615 PHYMOD_MEMSET(&pad_ctrl_gpio_1_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_1_CTLr_t)); 7616 PHYMOD_MEMSET(&pad_ctrl_gpio_2_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_2_CTLr_t)); 7617 PHYMOD_MEMSET(&pad_ctrl_gpio_3_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_3_CTLr_t)); 7618 7619 if (pin_number > 3) { 7620 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7621 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 3)"))); 7622 } 7623 7624 switch(pin_number) 7625 { 7626 case 0: 7627 PHYMOD_IF_ERR_RETURN( 7628 BCMI_MADURA_READ_GPIO_0_CTLr(pa,&pad_ctrl_gpio_0_ctrl)); 7629 data = BCMI_MADURA_GPIO_0_CTLr_GPIO_0_OEBf_GET(pad_ctrl_gpio_0_ctrl); 7630 break; 7631 case 1: 7632 PHYMOD_IF_ERR_RETURN( 7633 BCMI_MADURA_READ_GPIO_1_CTLr(pa,&pad_ctrl_gpio_1_ctrl)); 7634 data = BCMI_MADURA_GPIO_1_CTLr_GPIO_1_OEBf_GET(pad_ctrl_gpio_1_ctrl); 7635 break; 7636 case 2: 7637 PHYMOD_IF_ERR_RETURN( 7638 BCMI_MADURA_READ_GPIO_2_CTLr(pa,&pad_ctrl_gpio_2_ctrl)); 7639 data = BCMI_MADURA_GPIO_2_CTLr_GPIO_2_OEBf_GET(pad_ctrl_gpio_2_ctrl); 7640 break; 7641 case 3: 7642 PHYMOD_IF_ERR_RETURN( 7643 BCMI_MADURA_READ_GPIO_3_CTLr(pa,&pad_ctrl_gpio_3_ctrl)); 7644 data = BCMI_MADURA_GPIO_3_CTLr_GPIO_3_OEBf_GET(pad_ctrl_gpio_3_ctrl); 7645 break; 7646 default: 7647 return PHYMOD_E_PARAM; 7648 } 7649 7650 switch(data) { 7651 case 0: 7652 *gpio_mode = phymodGpioModeOutput; 7653 break; 7654 case 1: 7655 *gpio_mode = phymodGpioModeInput; 7656 break; 7657 /* coverity[dead_error_begin] */ 7658 default: 7659 break; 7660 } 7661 7662 return PHYMOD_E_NONE; 7663 } 7664 7665 int _madura_gpio_pin_value_set(const phymod_access_t *pa, int pin_number, int value) 7666 { 7667 BCMI_MADURA_GPIO_0_CTLr_t pad_ctrl_gpio_0_ctrl; 7668 BCMI_MADURA_GPIO_1_CTLr_t pad_ctrl_gpio_1_ctrl; 7669 BCMI_MADURA_GPIO_2_CTLr_t pad_ctrl_gpio_2_ctrl; 7670 BCMI_MADURA_GPIO_3_CTLr_t pad_ctrl_gpio_3_ctrl; 7671 7672 PHYMOD_MEMSET(&pad_ctrl_gpio_0_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_0_CTLr_t)); 7673 PHYMOD_MEMSET(&pad_ctrl_gpio_1_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_1_CTLr_t)); 7674 PHYMOD_MEMSET(&pad_ctrl_gpio_2_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_2_CTLr_t)); 7675 PHYMOD_MEMSET(&pad_ctrl_gpio_3_ctrl, 0 , sizeof(BCMI_MADURA_GPIO_3_CTLr_t)); 7676 if (pin_number > 3) { 7677 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7678 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 3)"))); 7679 } 7680 7681 switch(pin_number) 7682 { 7683 case 0: 7684 PHYMOD_IF_ERR_RETURN( 7685 BCMI_MADURA_READ_GPIO_0_CTLr(pa,&pad_ctrl_gpio_0_ctrl)); 7686 BCMI_MADURA_GPIO_0_CTLr_GPIO_0_IBOFf_SET(pad_ctrl_gpio_0_ctrl,1); 7687 BCMI_MADURA_GPIO_0_CTLr_GPIO_0_OUT_FRCVALf_SET(pad_ctrl_gpio_0_ctrl,value ? 1 : 0 ); 7688 PHYMOD_IF_ERR_RETURN( 7689 BCMI_MADURA_WRITE_GPIO_0_CTLr(pa,pad_ctrl_gpio_0_ctrl)); 7690 break; 7691 case 1: 7692 PHYMOD_IF_ERR_RETURN( 7693 BCMI_MADURA_READ_GPIO_1_CTLr(pa,&pad_ctrl_gpio_1_ctrl)); 7694 BCMI_MADURA_GPIO_1_CTLr_GPIO_1_IBOFf_SET(pad_ctrl_gpio_1_ctrl,1); 7695 BCMI_MADURA_GPIO_1_CTLr_GPIO_1_OUT_FRCVALf_SET(pad_ctrl_gpio_1_ctrl,value ? 1 : 0 ); 7696 PHYMOD_IF_ERR_RETURN( 7697 BCMI_MADURA_WRITE_GPIO_1_CTLr(pa,pad_ctrl_gpio_1_ctrl)); 7698 break; 7699 case 2: 7700 PHYMOD_IF_ERR_RETURN( 7701 BCMI_MADURA_READ_GPIO_2_CTLr(pa,&pad_ctrl_gpio_2_ctrl)); 7702 BCMI_MADURA_GPIO_2_CTLr_GPIO_2_IBOFf_SET(pad_ctrl_gpio_2_ctrl,1); 7703 BCMI_MADURA_GPIO_2_CTLr_GPIO_2_OUT_FRCVALf_SET(pad_ctrl_gpio_2_ctrl,value ? 1 : 0 ); 7704 PHYMOD_IF_ERR_RETURN( 7705 BCMI_MADURA_WRITE_GPIO_2_CTLr(pa,pad_ctrl_gpio_2_ctrl)); 7706 break; 7707 case 3: 7708 PHYMOD_IF_ERR_RETURN( 7709 BCMI_MADURA_READ_GPIO_3_CTLr(pa,&pad_ctrl_gpio_3_ctrl)); 7710 BCMI_MADURA_GPIO_3_CTLr_GPIO_3_IBOFf_SET(pad_ctrl_gpio_3_ctrl,1); 7711 BCMI_MADURA_GPIO_3_CTLr_GPIO_3_OUT_FRCVALf_SET(pad_ctrl_gpio_3_ctrl,value ? 1 : 0 ); 7712 PHYMOD_IF_ERR_RETURN( 7713 BCMI_MADURA_WRITE_GPIO_3_CTLr(pa,pad_ctrl_gpio_3_ctrl)); 7714 break; 7715 default: 7716 return PHYMOD_E_PARAM; 7717 } 7718 7719 return PHYMOD_E_NONE; 7720 } 7721 7722 int _madura_gpio_pin_value_get(const phymod_access_t *pa, int pin_number, int* value) 7723 { 7724 7725 BCMI_MADURA_GPIO_0_STSr_t pad_sts_gpio_0; 7726 BCMI_MADURA_GPIO_1_STSr_t pad_sts_gpio_1; 7727 BCMI_MADURA_GPIO_2_STSr_t pad_sts_gpio_2; 7728 BCMI_MADURA_GPIO_3_STSr_t pad_sts_gpio_3; 7729 7730 PHYMOD_MEMSET(&pad_sts_gpio_0, 0 , sizeof(BCMI_MADURA_GPIO_0_STSr_t)); 7731 PHYMOD_MEMSET(&pad_sts_gpio_1, 0 , sizeof(BCMI_MADURA_GPIO_1_STSr_t)); 7732 PHYMOD_MEMSET(&pad_sts_gpio_2, 0 , sizeof(BCMI_MADURA_GPIO_2_STSr_t)); 7733 PHYMOD_MEMSET(&pad_sts_gpio_3, 0 , sizeof(BCMI_MADURA_GPIO_3_STSr_t)); 7734 if (pin_number > 3) { 7735 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7736 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 3)"))); 7737 } 7738 7739 switch(pin_number) 7740 { 7741 case 0: 7742 PHYMOD_IF_ERR_RETURN( 7743 BCMI_MADURA_READ_GPIO_0_STSr(pa,&pad_sts_gpio_0)); 7744 *value = BCMI_MADURA_GPIO_0_STSr_GPIO_0_DINf_GET(pad_sts_gpio_0); 7745 break; 7746 case 1: 7747 PHYMOD_IF_ERR_RETURN( 7748 BCMI_MADURA_READ_GPIO_1_STSr(pa,&pad_sts_gpio_1)); 7749 *value = BCMI_MADURA_GPIO_1_STSr_GPIO_1_DINf_GET(pad_sts_gpio_1); 7750 break; 7751 case 2: 7752 PHYMOD_IF_ERR_RETURN( 7753 BCMI_MADURA_READ_GPIO_2_STSr(pa,&pad_sts_gpio_2)); 7754 *value = BCMI_MADURA_GPIO_2_STSr_GPIO_2_DINf_GET(pad_sts_gpio_2); 7755 break; 7756 case 3: 7757 PHYMOD_IF_ERR_RETURN( 7758 BCMI_MADURA_READ_GPIO_3_STSr(pa,&pad_sts_gpio_3)); 7759 *value = BCMI_MADURA_GPIO_3_STSr_GPIO_3_DINf_GET(pad_sts_gpio_3); 7760 break; 7761 default: 7762 return PHYMOD_E_PARAM; 7763 } 7764 7765 return PHYMOD_E_NONE; 7766 } 7767 7768 int _madura_cfg_fw_ull_dp(const phymod_access_t* pa, phymod_datapath_t op_datapath) 7769 { 7770 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 7771 phymod_phy_inf_config_t config_cpy; 7772 uint16_t ip = 0, Tx_timing_mode = MADURA_TX_REPEATER_ULL; 7773 uint16_t data1 = 0, retry_cnt = MADURA_ULL_SET_RETRY_CNT; 7774 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 7775 PHYMOD_MEMSET(&config_cpy, 0, sizeof(phymod_phy_inf_config_t)); 7776 config_cpy.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 7777 MADURA_IF_ERR_RETURN_FREE(config_cpy.device_aux_modes, ( 7778 _madura_phy_interface_config_get(pa, 0, &config_cpy))); 7779 7780 if (op_datapath == phymodDatapathNormal) { 7781 Tx_timing_mode = MADURA_TX_REPEATER; 7782 7783 } 7784 MADURA_GET_IP(pa, (config_cpy), ip); 7785 7786 /* Wait for Firmware Ready */ 7787 do { 7788 MADURA_IF_ERR_RETURN_FREE( config_cpy.device_aux_modes, ( 7789 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 7790 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 7791 PHYMOD_USLEEP(100); 7792 } while ((data1 != 0) && (retry_cnt --)); 7793 if (retry_cnt == 0) { 7794 PHYMOD_FREE(config_cpy.device_aux_modes); 7795 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7796 (_PHYMOD_MSG("Firmware is busy.."))); 7797 } 7798 7799 /* Set TX timing mode */ 7800 MADURA_IF_ERR_RETURN_FREE( config_cpy.device_aux_modes, ( 7801 _madura_interface_set_ull_mode_set(pa, ip, &config_cpy, 7802 Tx_timing_mode))); 7803 7804 /*not toggling the firmware En here . It will be done once config set is performed. Ull will start working after that*/ 7805 7806 PHYMOD_FREE(config_cpy.device_aux_modes); 7807 return PHYMOD_E_NONE; 7808 } 7809 7810 int _madura_core_rptr_rtmr_mode_set(const phymod_access_t* pa, uint16_t op_mode) 7811 { 7812 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 7813 phymod_phy_inf_config_t config_cpy; 7814 uint16_t ip = 0, rptr_rtmr_mode = 0; 7815 uint16_t data1 = 0, retry_cnt = 0; 7816 7817 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 7818 PHYMOD_MEMSET(&config_cpy, 0, sizeof(phymod_phy_inf_config_t)); 7819 config_cpy.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 7820 MADURA_IF_ERR_RETURN_FREE(config_cpy.device_aux_modes, ( 7821 _madura_phy_interface_config_get(pa, 0, &config_cpy))); 7822 7823 rptr_rtmr_mode = (op_mode == phymodOperationModeRetimer) ? MADURA_TX_RETIMER : MADURA_TX_REPEATER ; 7824 MADURA_GET_IP(pa, (config_cpy), ip); 7825 7826 7827 /* Wait for Firmware Ready */ 7828 retry_cnt = MADURA_RPTR_SET_RETRY_CNT; 7829 do { 7830 MADURA_IF_ERR_RETURN_FREE( config_cpy.device_aux_modes, ( 7831 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 7832 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 7833 PHYMOD_USLEEP(100); 7834 } while ((data1 != 0) && (retry_cnt --)); 7835 if (retry_cnt == 0) { 7836 PHYMOD_FREE(config_cpy.device_aux_modes); 7837 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("Firmware is busy.."))); 7838 } 7839 7840 /* Set TX timing mode */ 7841 MADURA_IF_ERR_RETURN_FREE( config_cpy.device_aux_modes, ( 7842 _madura_interface_set_repeater_retimer_mode_set(pa, ip, &config_cpy, 7843 rptr_rtmr_mode))); 7844 7845 /* Set FW en */ 7846 /* coverity[operator_confusion] */ 7847 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en, 1); 7848 PHYMOD_IF_ERR_RETURN( 7849 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en)); 7850 7851 /* Wait for Firmware Ready */ 7852 retry_cnt = MADURA_RPTR_SET_RETRY_CNT; 7853 do { 7854 MADURA_IF_ERR_RETURN_FREE( config_cpy.device_aux_modes, ( 7855 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 7856 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 7857 PHYMOD_USLEEP(100); 7858 } while ((data1 != 0) && (retry_cnt --)); 7859 if (retry_cnt == 0) { 7860 PHYMOD_FREE(config_cpy.device_aux_modes); 7861 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7862 (_PHYMOD_MSG("Firmware is busy.."))); 7863 } 7864 7865 PHYMOD_FREE(config_cpy.device_aux_modes); 7866 return PHYMOD_E_NONE; 7867 } 7868 7869 int _madura_lane_config_DfeAndMedia_set(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t* config, phymod_firmware_lane_config_t* fw_config) 7870 { 7871 uint16_t DFE_option = SERDES_DFE_OPTION_NO_DFE; /*default to dfe disable*/ 7872 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 7873 uint16_t config_reg=0; 7874 uint16_t lane_mask = pa->lane_mask; 7875 BCMI_MADURA_MST_MISC0r_t mst_misc0; 7876 BCMI_MADURA_MST_MISC1r_t mst_misc1; 7877 BCMI_MADURA_MST_MISC2r_t mst_misc2; 7878 BCMI_MADURA_MST_MISC3r_t mst_misc3; 7879 MADURA_DEVICE_AUX_MODE_T *aux_mode; 7880 7881 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 7882 7883 7884 if ((ip == MADURA_2X_FALCON_CORE) && aux_mode->alternate) { 7885 if ((config->data_rate != MADURA_SPD_40G && config->data_rate != MADURA_SPD_50G && 7886 config->data_rate != MADURA_SPD_42G) || 7887 aux_mode->pass_thru_dual_lane || 7888 aux_mode->pass_thru ) { 7889 7890 lane_mask >>= 4 ; 7891 } 7892 } 7893 7894 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 7895 PHYMOD_IF_ERR_RETURN( 7896 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 7897 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 7898 } else if (lane_mask == 0x2) { 7899 PHYMOD_IF_ERR_RETURN( 7900 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 7901 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 7902 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 7903 PHYMOD_IF_ERR_RETURN( 7904 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 7905 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 7906 } else { 7907 PHYMOD_IF_ERR_RETURN( 7908 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 7909 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 7910 } 7911 7912 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 7913 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 7914 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 7915 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 7916 7917 if (fw_config != NULL) { 7918 if (fw_config->DfeOn == 0){ 7919 DFE_option = SERDES_DFE_OPTION_NO_DFE; 7920 } 7921 if (fw_config->DfeOn == 1 && 7922 fw_config->LpDfeOn == 0 && 7923 fw_config->ForceBrDfe == 0) { 7924 DFE_option = SERDES_DFE_OPTION_DFE; 7925 } 7926 if (fw_config->DfeOn == 1 && 7927 fw_config->LpDfeOn == 0 && 7928 fw_config->ForceBrDfe == 1) { 7929 DFE_option = SERDES_DFE_OPTION_BRDEF; 7930 } 7931 if (fw_config->DfeOn == 1 && 7932 fw_config->LpDfeOn == 1 && 7933 fw_config->ForceBrDfe == 0) { 7934 DFE_option = SERDES_DFE_OPTION_DFE_LP_MODE; 7935 } 7936 7937 switch(fw_config->MediaType) { 7938 case phymodFirmwareMediaTypeOptics: 7939 if (fw_config->UnreliableLos) { 7940 media_type = SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS; 7941 } else { 7942 media_type = SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS; 7943 } 7944 break; 7945 case phymodFirmwareMediaTypeCopperCable: 7946 media_type = SERDES_MEDIA_TYPE_COPPER_CABLE; 7947 break; 7948 case phymodFirmwareMediaTypePcbTraceBackPlane: 7949 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; 7950 break; 7951 default: 7952 break; 7953 } 7954 } 7955 7956 7957 if (ip == MADURA_2X_FALCON_CORE) { 7958 config_reg &= ~(0xf00); 7959 /*considering sys+line side on the same interface*/ 7960 config_reg |= (( media_type)& 0x3) << 8 ; /*line*/ 7961 /*considering sys+line side on the same DFE settings*/ 7962 config_reg |= (( DFE_option ) & 0x3 ) << 10 ; /*lin*/ 7963 } else { 7964 config_reg &= ~(0x000f); 7965 /*considering sys+line side on the same interface*/ 7966 config_reg |= ( media_type)& 0x3 ; /*sys*/ 7967 /*considering sys+line side on the same DFE settings*/ 7968 config_reg |= (( DFE_option ) & 0x3 ) << 2 ; /*sys */ 7969 } 7970 7971 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 7972 BCMI_MADURA_MST_MISC0r_SET(mst_misc0,(config_reg )); 7973 PHYMOD_IF_ERR_RETURN( 7974 BCMI_MADURA_WRITE_MST_MISC0r(pa,mst_misc0)); 7975 } else if (lane_mask == 0x2) { 7976 BCMI_MADURA_MST_MISC1r_SET(mst_misc1,(config_reg )); 7977 PHYMOD_IF_ERR_RETURN( 7978 BCMI_MADURA_WRITE_MST_MISC1r(pa,mst_misc1)); 7979 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 7980 BCMI_MADURA_MST_MISC2r_SET(mst_misc2,(config_reg )); 7981 PHYMOD_IF_ERR_RETURN( 7982 BCMI_MADURA_WRITE_MST_MISC2r(pa,mst_misc2)); 7983 } else { 7984 BCMI_MADURA_MST_MISC3r_SET(mst_misc3,(config_reg )); 7985 PHYMOD_IF_ERR_RETURN( 7986 BCMI_MADURA_WRITE_MST_MISC3r(pa,mst_misc3)); 7987 } 7988 7989 return PHYMOD_E_NONE; 7990 } 7991 7992 int _madura_lane_config_DfeAndMedia_get(const phymod_access_t *pa, uint16_t ip, const phymod_phy_inf_config_t *config, phymod_firmware_lane_config_t* fw_config) 7993 { 7994 uint16_t DFE_option = SERDES_DFE_OPTION_NO_DFE; /*default to dfe disable*/ 7995 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 7996 uint16_t config_reg=0; 7997 uint16_t lane_mask = pa->lane_mask; 7998 BCMI_MADURA_MST_MISC0r_t mst_misc0; 7999 BCMI_MADURA_MST_MISC1r_t mst_misc1; 8000 BCMI_MADURA_MST_MISC2r_t mst_misc2; 8001 BCMI_MADURA_MST_MISC3r_t mst_misc3; 8002 MADURA_DEVICE_AUX_MODE_T *aux_mode; 8003 8004 aux_mode = (MADURA_DEVICE_AUX_MODE_T*) config->device_aux_modes; 8005 8006 if (ip == MADURA_2X_FALCON_CORE && aux_mode->alternate) { 8007 if ((config->data_rate != MADURA_SPD_40G && config->data_rate != MADURA_SPD_50G && 8008 config->data_rate != MADURA_SPD_42G) || 8009 aux_mode->pass_thru_dual_lane || 8010 aux_mode->pass_thru ) { 8011 8012 lane_mask >>= 4 ; 8013 } 8014 } 8015 8016 PHYMOD_MEMSET(&mst_misc0, 0, sizeof(BCMI_MADURA_MST_MISC0r_t)); 8017 PHYMOD_MEMSET(&mst_misc1, 0, sizeof(BCMI_MADURA_MST_MISC1r_t)); 8018 PHYMOD_MEMSET(&mst_misc2, 0, sizeof(BCMI_MADURA_MST_MISC2r_t)); 8019 PHYMOD_MEMSET(&mst_misc3, 0, sizeof(BCMI_MADURA_MST_MISC3r_t)); 8020 8021 if (lane_mask == 0xF || lane_mask == 0x3 || lane_mask == 0x1 ) { 8022 PHYMOD_IF_ERR_RETURN( 8023 BCMI_MADURA_READ_MST_MISC0r(pa, &mst_misc0)); 8024 config_reg = BCMI_MADURA_MST_MISC0r_GET(mst_misc0); 8025 } else if (lane_mask == 0x2) { 8026 PHYMOD_IF_ERR_RETURN( 8027 BCMI_MADURA_READ_MST_MISC1r(pa, &mst_misc1)); 8028 config_reg = BCMI_MADURA_MST_MISC1r_GET(mst_misc1); 8029 } else if (lane_mask == 0xF0 || lane_mask == 0xC || lane_mask == 0x4 ) { 8030 PHYMOD_IF_ERR_RETURN( 8031 BCMI_MADURA_READ_MST_MISC2r(pa, &mst_misc2)); 8032 config_reg = BCMI_MADURA_MST_MISC2r_GET(mst_misc2); 8033 } else { 8034 PHYMOD_IF_ERR_RETURN( 8035 BCMI_MADURA_READ_MST_MISC3r(pa, &mst_misc3)); 8036 config_reg = BCMI_MADURA_MST_MISC3r_GET(mst_misc3); 8037 } 8038 8039 if (ip == MADURA_2X_FALCON_CORE) { 8040 config_reg &= (0xf00); 8041 /*considering sys+line side on the same interface*/ 8042 media_type = (config_reg & 0x300)>> 8 ; 8043 /*considering sys+line side on the same DFE settings*/ 8044 DFE_option = (config_reg & 0xc00)>> 10; 8045 } else { 8046 config_reg &= (0x0f); 8047 media_type = (config_reg & 0x3); 8048 /*considering sys+line side on the same DFE settings*/ 8049 DFE_option = (config_reg & 0xc)>> 2; 8050 } 8051 8052 if (fw_config != NULL) { 8053 8054 switch(DFE_option) { 8055 case SERDES_DFE_OPTION_NO_DFE: 8056 fw_config->DfeOn = 0; 8057 fw_config->LpDfeOn = 0; 8058 fw_config->ForceBrDfe = 0; 8059 break; 8060 case SERDES_DFE_OPTION_DFE: 8061 fw_config->DfeOn = 1; 8062 fw_config->LpDfeOn = 0; 8063 fw_config->ForceBrDfe = 0; 8064 break; 8065 case SERDES_DFE_OPTION_BRDEF: 8066 fw_config->DfeOn = 1; 8067 fw_config->LpDfeOn = 0; 8068 fw_config->ForceBrDfe = 1; 8069 break; 8070 case SERDES_DFE_OPTION_DFE_LP_MODE: 8071 fw_config->DfeOn = 1; 8072 fw_config->LpDfeOn = 1; 8073 fw_config->ForceBrDfe = 0; 8074 break; 8075 } 8076 8077 fw_config->UnreliableLos = 0; 8078 switch(media_type) { 8079 case SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS: 8080 fw_config->MediaType = phymodFirmwareMediaTypeOptics; 8081 break; 8082 case SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS: 8083 fw_config->MediaType = phymodFirmwareMediaTypeOptics; 8084 fw_config->UnreliableLos = 1; 8085 break; 8086 case SERDES_MEDIA_TYPE_COPPER_CABLE: 8087 fw_config->MediaType = phymodFirmwareMediaTypeCopperCable; 8088 break; 8089 case SERDES_MEDIA_TYPE_BACK_PLANE: 8090 fw_config->MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 8091 break; 8092 } 8093 } 8094 8095 return PHYMOD_E_NONE; 8096 } 8097 8098 int _madura_firmware_lane_config_set(const phymod_access_t* pa, phymod_firmware_lane_config_t fw_config) 8099 { 8100 BCMI_MADURA_FIRMWARE_ENr_t fw_en; 8101 phymod_phy_inf_config_t config; 8102 uint16_t ip = 0; 8103 uint16_t data1 = 0, retry_cnt = MADURA_FORCE_TRAIN_RETRY_CNT; 8104 8105 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 8106 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_MADURA_FIRMWARE_ENr_t)); 8107 8108 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 8109 8110 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8111 _madura_phy_interface_config_get(pa, 0, &config))); 8112 8113 MADURA_GET_IP(pa, config, ip); 8114 8115 /* Wait for Firmware Ready */ 8116 retry_cnt = MADURA_FORCE_TRAIN_RETRY_CNT; 8117 do { 8118 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8119 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 8120 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 8121 PHYMOD_USLEEP(100); 8122 } while ((data1 != 0) && (retry_cnt --)); 8123 if (retry_cnt == 0) { 8124 PHYMOD_FREE(config.device_aux_modes); 8125 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 8126 (_PHYMOD_MSG("Firmware is busy.."))); 8127 } 8128 8129 /* Set DFE & Media */ 8130 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8131 _madura_lane_config_DfeAndMedia_set(pa, ip, &config, &fw_config))); 8132 8133 /* Set FW en */ 8134 /* coverity[operator_confusion] */ 8135 BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en, 1); 8136 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8137 BCMI_MADURA_WRITE_FIRMWARE_ENr(pa,fw_en))); 8138 8139 /* Wait for Firmware Ready */ 8140 retry_cnt = MADURA_FORCE_TRAIN_RETRY_CNT; 8141 do { 8142 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8143 BCMI_MADURA_READ_FIRMWARE_ENr(pa,&fw_en))); 8144 data1=BCMI_MADURA_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 8145 PHYMOD_USLEEP(100); 8146 } while ((data1 != 0) && (retry_cnt --)); 8147 if (retry_cnt == 0) { 8148 PHYMOD_FREE(config.device_aux_modes); 8149 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 8150 (_PHYMOD_MSG("Firmware is busy.."))); 8151 } 8152 8153 PHYMOD_FREE(config.device_aux_modes); 8154 8155 return PHYMOD_E_NONE; 8156 } 8157 8158 int _madura_firmware_lane_config_get(const phymod_access_t* pa, phymod_firmware_lane_config_t* fw_config) 8159 { 8160 uint16_t ip = 0; 8161 phymod_phy_inf_config_t config; 8162 8163 PHYMOD_MEMSET(fw_config, 0, sizeof(phymod_firmware_lane_config_t)); 8164 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 8165 8166 config.device_aux_modes = PHYMOD_MALLOC(sizeof(MADURA_DEVICE_AUX_MODE_T), "madura_device_aux_mode"); 8167 8168 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8169 _madura_phy_interface_config_get(pa, 0, &config))); 8170 8171 MADURA_GET_IP(pa, config, ip); 8172 8173 MADURA_IF_ERR_RETURN_FREE( config.device_aux_modes, ( 8174 _madura_lane_config_DfeAndMedia_get(pa, ip, &config, fw_config))); 8175 8176 PHYMOD_FREE(config.device_aux_modes); 8177 8178 return PHYMOD_E_NONE; 8179 } 8180 8181