bcmi_huracan_defs.h (1595344B)
1 #ifndef __BCMI_HURACAN_DEFS_H__ 2 #define __BCMI_HURACAN_DEFS_H__ 3 /******************************************************************************* 4 * 5 * 6 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 7 * 8 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 9 * 10 * DO NOT EDIT THIS FILE! 11 * This file is auto-generated from the registers file. 12 * Edits to this file will be lost when it is regenerated. 13 * 14 * Definition file for the BCMI_HURACAN. 15 * This file provides all basic definitions required to program the BCMI_HURACAN. 16 * 17 * This file is autogenerated. Please do not edit. 18 */ 19 20 #ifndef _DV_TB_ 21 #include <phymod/phymod_types.h> 22 #endif /* _DV_TB_ */ 23 24 /******************************************************************************* 25 * 26 * CHIP DEFINITIONS BEGIN HERE 27 */ 28 29 30 31 /******************************************************************************* 32 * CHIP: BCMI_HURACAN 33 * REGISTER: ANA_LANE_0_QUAD_A_CTRL0 34 * BLOCKS: ANA_LANE_0_QUAD_A 35 * REGADDR: 0x8100 36 * DEVAD: 1 37 * DESC: control registers 0 38 * RESETVAL: 0x0 (0) 39 * ACCESS: R/W 40 * FIELDS: 41 * RXTX_PWRDN 42 * RX_SIGDET_BYPASS 43 * RX_SIGDET_PWRDN 44 * RX_SIGDECT_12GMODE 45 * DC_COUPLE 46 */ 47 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r (0x00018100 | PHYMOD_REG_ACC_RAW) 48 49 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_SIZE 4 50 51 /* 52 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL0. 53 */ 54 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_s { 55 uint32_t v[1]; 56 uint32_t ana_lane_0_quad_a_ctrl0[1]; 57 uint32_t _ana_lane_0_quad_a_ctrl0; 58 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_t; 59 60 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_CLR(r) (r).ana_lane_0_quad_a_ctrl0[0] = 0 61 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_SET(r,d) (r).ana_lane_0_quad_a_ctrl0[0] = d 62 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_GET(r) (r).ana_lane_0_quad_a_ctrl0[0] 63 64 /* 65 * These macros can be used to access individual fields. 66 */ 67 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_0_quad_a_ctrl0[0]) >> 4) & 0x1) 68 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_0_quad_a_ctrl0[0]=(((r).ana_lane_0_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 69 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_0_quad_a_ctrl0[0]) >> 3) & 0x1) 70 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_0_quad_a_ctrl0[0]=(((r).ana_lane_0_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 71 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_0_quad_a_ctrl0[0]) >> 2) & 0x1) 72 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_0_quad_a_ctrl0[0]=(((r).ana_lane_0_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 73 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_0_quad_a_ctrl0[0]) >> 1) & 0x1) 74 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_0_quad_a_ctrl0[0]=(((r).ana_lane_0_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 75 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_0_quad_a_ctrl0[0]) & 0x1) 76 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_0_quad_a_ctrl0[0]=(((r).ana_lane_0_quad_a_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 77 78 /* 79 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL0. 80 */ 81 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r,_r._ana_lane_0_quad_a_ctrl0) 82 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r,_r._ana_lane_0_quad_a_ctrl0) 83 84 /* 85 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 86 * will be redefined without the chip prefix for easier programming. 87 * If multiple chips will be programmed in the same source file, then you should 88 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 89 * and refer to the fully qualified versions. 90 */ 91 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 92 93 #define ANA_LANE_0_QUAD_A_CTRL0r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r 94 #define ANA_LANE_0_QUAD_A_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_SIZE 95 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_t ANA_LANE_0_QUAD_A_CTRL0r_t; 96 #define ANA_LANE_0_QUAD_A_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_CLR 97 #define ANA_LANE_0_QUAD_A_CTRL0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_SET 98 #define ANA_LANE_0_QUAD_A_CTRL0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_GET 99 #define ANA_LANE_0_QUAD_A_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_DC_COUPLEf_GET 100 #define ANA_LANE_0_QUAD_A_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_DC_COUPLEf_SET 101 #define ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET 102 #define ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET 103 #define ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET 104 #define ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET 105 #define ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET 106 #define ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET 107 #define ANA_LANE_0_QUAD_A_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RXTX_PWRDNf_GET 108 #define ANA_LANE_0_QUAD_A_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r_RXTX_PWRDNf_SET 109 #define READ_ANA_LANE_0_QUAD_A_CTRL0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL0r 110 #define WRITE_ANA_LANE_0_QUAD_A_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL0r 111 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL0r 112 113 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 114 /******************************************************************************* 115 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL0r' 116 */ 117 118 119 120 121 /******************************************************************************* 122 * CHIP: BCMI_HURACAN 123 * REGISTER: ANA_LANE_0_QUAD_A_CTRL1 124 * BLOCKS: ANA_LANE_0_QUAD_A 125 * REGADDR: 0x8101 126 * DEVAD: 1 127 * DESC: control registers 0 128 * RESETVAL: 0x0 (0) 129 * ACCESS: R/W 130 * FIELDS: 131 * RX_SIGDET_THRESHOLD 132 * REF_OCL 133 * OCL_PWRDN 134 * OCL_DISABLE_LOOP 135 * RXTX_RESERVED_FOR_15_12 136 */ 137 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r (0x00018101 | PHYMOD_REG_ACC_RAW) 138 139 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_SIZE 4 140 141 /* 142 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL1. 143 */ 144 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_s { 145 uint32_t v[1]; 146 uint32_t ana_lane_0_quad_a_ctrl1[1]; 147 uint32_t _ana_lane_0_quad_a_ctrl1; 148 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_t; 149 150 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_CLR(r) (r).ana_lane_0_quad_a_ctrl1[0] = 0 151 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_SET(r,d) (r).ana_lane_0_quad_a_ctrl1[0] = d 152 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_GET(r) (r).ana_lane_0_quad_a_ctrl1[0] 153 154 /* 155 * These macros can be used to access individual fields. 156 */ 157 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_0_quad_a_ctrl1[0]) >> 12) & 0xf) 158 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_0_quad_a_ctrl1[0]=(((r).ana_lane_0_quad_a_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 159 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_0_quad_a_ctrl1[0]) >> 9) & 0x1) 160 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_0_quad_a_ctrl1[0]=(((r).ana_lane_0_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 161 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_0_quad_a_ctrl1[0]) >> 8) & 0x1) 162 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_0_quad_a_ctrl1[0]=(((r).ana_lane_0_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 163 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_0_quad_a_ctrl1[0]) >> 4) & 0x3) 164 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_0_quad_a_ctrl1[0]=(((r).ana_lane_0_quad_a_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 165 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_0_quad_a_ctrl1[0]) & 0x7) 166 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_0_quad_a_ctrl1[0]=(((r).ana_lane_0_quad_a_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 167 168 /* 169 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL1. 170 */ 171 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r,_r._ana_lane_0_quad_a_ctrl1) 172 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r,_r._ana_lane_0_quad_a_ctrl1) 173 174 /* 175 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 176 * will be redefined without the chip prefix for easier programming. 177 * If multiple chips will be programmed in the same source file, then you should 178 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 179 * and refer to the fully qualified versions. 180 */ 181 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 182 183 #define ANA_LANE_0_QUAD_A_CTRL1r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r 184 #define ANA_LANE_0_QUAD_A_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_SIZE 185 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_t ANA_LANE_0_QUAD_A_CTRL1r_t; 186 #define ANA_LANE_0_QUAD_A_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_CLR 187 #define ANA_LANE_0_QUAD_A_CTRL1r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_SET 188 #define ANA_LANE_0_QUAD_A_CTRL1r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_GET 189 #define ANA_LANE_0_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 190 #define ANA_LANE_0_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 191 #define ANA_LANE_0_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET 192 #define ANA_LANE_0_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET 193 #define ANA_LANE_0_QUAD_A_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_PWRDNf_GET 194 #define ANA_LANE_0_QUAD_A_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_OCL_PWRDNf_SET 195 #define ANA_LANE_0_QUAD_A_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_REF_OCLf_GET 196 #define ANA_LANE_0_QUAD_A_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_REF_OCLf_SET 197 #define ANA_LANE_0_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET 198 #define ANA_LANE_0_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET 199 #define READ_ANA_LANE_0_QUAD_A_CTRL1r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL1r 200 #define WRITE_ANA_LANE_0_QUAD_A_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL1r 201 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL1r 202 203 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 204 /******************************************************************************* 205 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL1r' 206 */ 207 208 209 210 211 /******************************************************************************* 212 * CHIP: BCMI_HURACAN 213 * REGISTER: ANA_LANE_0_QUAD_A_CTRL2 214 * BLOCKS: ANA_LANE_0_QUAD_A 215 * REGADDR: 0x8102 216 * DEVAD: 1 217 * DESC: control registers 0 218 * RESETVAL: 0x0 (0) 219 * ACCESS: R/W 220 * FIELDS: 221 * CTLE_ENB_NEGIMP 222 * CTLE_ENB_NEGCAP 223 */ 224 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r (0x00018102 | PHYMOD_REG_ACC_RAW) 225 226 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_SIZE 4 227 228 /* 229 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL2. 230 */ 231 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_s { 232 uint32_t v[1]; 233 uint32_t ana_lane_0_quad_a_ctrl2[1]; 234 uint32_t _ana_lane_0_quad_a_ctrl2; 235 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_t; 236 237 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CLR(r) (r).ana_lane_0_quad_a_ctrl2[0] = 0 238 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_SET(r,d) (r).ana_lane_0_quad_a_ctrl2[0] = d 239 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_GET(r) (r).ana_lane_0_quad_a_ctrl2[0] 240 241 /* 242 * These macros can be used to access individual fields. 243 */ 244 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_0_quad_a_ctrl2[0]) >> 8) & 0x7f) 245 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_0_quad_a_ctrl2[0]=(((r).ana_lane_0_quad_a_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 246 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_0_quad_a_ctrl2[0]) & 0x7f) 247 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_0_quad_a_ctrl2[0]=(((r).ana_lane_0_quad_a_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 248 249 /* 250 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL2. 251 */ 252 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r,_r._ana_lane_0_quad_a_ctrl2) 253 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r,_r._ana_lane_0_quad_a_ctrl2) 254 255 /* 256 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 257 * will be redefined without the chip prefix for easier programming. 258 * If multiple chips will be programmed in the same source file, then you should 259 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 260 * and refer to the fully qualified versions. 261 */ 262 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 263 264 #define ANA_LANE_0_QUAD_A_CTRL2r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r 265 #define ANA_LANE_0_QUAD_A_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_SIZE 266 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_t ANA_LANE_0_QUAD_A_CTRL2r_t; 267 #define ANA_LANE_0_QUAD_A_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CLR 268 #define ANA_LANE_0_QUAD_A_CTRL2r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_SET 269 #define ANA_LANE_0_QUAD_A_CTRL2r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_GET 270 #define ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET 271 #define ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET 272 #define ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET 273 #define ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET 274 #define READ_ANA_LANE_0_QUAD_A_CTRL2r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL2r 275 #define WRITE_ANA_LANE_0_QUAD_A_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL2r 276 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL2r 277 278 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 279 /******************************************************************************* 280 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL2r' 281 */ 282 283 284 285 286 /******************************************************************************* 287 * CHIP: BCMI_HURACAN 288 * REGISTER: ANA_LANE_0_QUAD_A_CTRL3 289 * BLOCKS: ANA_LANE_0_QUAD_A 290 * REGADDR: 0x8103 291 * DEVAD: 1 292 * DESC: control registers 0 293 * RESETVAL: 0x0 (0) 294 * ACCESS: R/W 295 * FIELDS: 296 * CTLE_EN_NEGRES 297 * CTLE_EQSEL 298 */ 299 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r (0x00018103 | PHYMOD_REG_ACC_RAW) 300 301 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_SIZE 4 302 303 /* 304 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL3. 305 */ 306 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_s { 307 uint32_t v[1]; 308 uint32_t ana_lane_0_quad_a_ctrl3[1]; 309 uint32_t _ana_lane_0_quad_a_ctrl3; 310 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_t; 311 312 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CLR(r) (r).ana_lane_0_quad_a_ctrl3[0] = 0 313 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_SET(r,d) (r).ana_lane_0_quad_a_ctrl3[0] = d 314 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_GET(r) (r).ana_lane_0_quad_a_ctrl3[0] 315 316 /* 317 * These macros can be used to access individual fields. 318 */ 319 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_0_quad_a_ctrl3[0]) >> 8) & 0xff) 320 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_0_quad_a_ctrl3[0]=(((r).ana_lane_0_quad_a_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 321 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_0_quad_a_ctrl3[0]) & 0x7f) 322 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_0_quad_a_ctrl3[0]=(((r).ana_lane_0_quad_a_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 323 324 /* 325 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL3. 326 */ 327 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r,_r._ana_lane_0_quad_a_ctrl3) 328 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r,_r._ana_lane_0_quad_a_ctrl3) 329 330 /* 331 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 332 * will be redefined without the chip prefix for easier programming. 333 * If multiple chips will be programmed in the same source file, then you should 334 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 335 * and refer to the fully qualified versions. 336 */ 337 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 338 339 #define ANA_LANE_0_QUAD_A_CTRL3r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r 340 #define ANA_LANE_0_QUAD_A_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_SIZE 341 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_t ANA_LANE_0_QUAD_A_CTRL3r_t; 342 #define ANA_LANE_0_QUAD_A_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CLR 343 #define ANA_LANE_0_QUAD_A_CTRL3r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_SET 344 #define ANA_LANE_0_QUAD_A_CTRL3r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_GET 345 #define ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EQSELf_GET 346 #define ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EQSELf_SET 347 #define ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET 348 #define ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET 349 #define READ_ANA_LANE_0_QUAD_A_CTRL3r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL3r 350 #define WRITE_ANA_LANE_0_QUAD_A_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL3r 351 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL3r 352 353 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 354 /******************************************************************************* 355 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL3r' 356 */ 357 358 359 360 361 /******************************************************************************* 362 * CHIP: BCMI_HURACAN 363 * REGISTER: ANA_LANE_0_QUAD_A_CTRL4 364 * BLOCKS: ANA_LANE_0_QUAD_A 365 * REGADDR: 0x8104 366 * DEVAD: 1 367 * DESC: control registers 0 368 * RESETVAL: 0x0 (0) 369 * ACCESS: R/W 370 * FIELDS: 371 * CTLE_LZEN 372 * RXTX_RESERVED_FOR_59_52 373 */ 374 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r (0x00018104 | PHYMOD_REG_ACC_RAW) 375 376 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_SIZE 4 377 378 /* 379 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL4. 380 */ 381 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_s { 382 uint32_t v[1]; 383 uint32_t ana_lane_0_quad_a_ctrl4[1]; 384 uint32_t _ana_lane_0_quad_a_ctrl4; 385 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_t; 386 387 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_CLR(r) (r).ana_lane_0_quad_a_ctrl4[0] = 0 388 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_SET(r,d) (r).ana_lane_0_quad_a_ctrl4[0] = d 389 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_GET(r) (r).ana_lane_0_quad_a_ctrl4[0] 390 391 /* 392 * These macros can be used to access individual fields. 393 */ 394 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_0_quad_a_ctrl4[0]) >> 4) & 0xff) 395 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_0_quad_a_ctrl4[0]=(((r).ana_lane_0_quad_a_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 396 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_0_quad_a_ctrl4[0]) & 0x1) 397 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_0_quad_a_ctrl4[0]=(((r).ana_lane_0_quad_a_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 398 399 /* 400 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL4. 401 */ 402 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r,_r._ana_lane_0_quad_a_ctrl4) 403 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r,_r._ana_lane_0_quad_a_ctrl4) 404 405 /* 406 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 407 * will be redefined without the chip prefix for easier programming. 408 * If multiple chips will be programmed in the same source file, then you should 409 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 410 * and refer to the fully qualified versions. 411 */ 412 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 413 414 #define ANA_LANE_0_QUAD_A_CTRL4r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r 415 #define ANA_LANE_0_QUAD_A_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_SIZE 416 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_t ANA_LANE_0_QUAD_A_CTRL4r_t; 417 #define ANA_LANE_0_QUAD_A_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_CLR 418 #define ANA_LANE_0_QUAD_A_CTRL4r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_SET 419 #define ANA_LANE_0_QUAD_A_CTRL4r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_GET 420 #define ANA_LANE_0_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 421 #define ANA_LANE_0_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 422 #define ANA_LANE_0_QUAD_A_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_CTLE_LZENf_GET 423 #define ANA_LANE_0_QUAD_A_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r_CTLE_LZENf_SET 424 #define READ_ANA_LANE_0_QUAD_A_CTRL4r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL4r 425 #define WRITE_ANA_LANE_0_QUAD_A_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL4r 426 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL4r 427 428 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 429 /******************************************************************************* 430 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL4r' 431 */ 432 433 434 435 436 /******************************************************************************* 437 * CHIP: BCMI_HURACAN 438 * REGISTER: ANA_LANE_0_QUAD_A_CTRL5 439 * BLOCKS: ANA_LANE_0_QUAD_A 440 * REGADDR: 0x8105 441 * DEVAD: 1 442 * DESC: control registers 0 443 * RESETVAL: 0x0 (0) 444 * ACCESS: R/W 445 * FIELDS: 446 * CTLE_LOPEAKING 447 * CTLE_PD 448 * LA_GCTRL 449 */ 450 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r (0x00018105 | PHYMOD_REG_ACC_RAW) 451 452 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_SIZE 4 453 454 /* 455 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL5. 456 */ 457 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_s { 458 uint32_t v[1]; 459 uint32_t ana_lane_0_quad_a_ctrl5[1]; 460 uint32_t _ana_lane_0_quad_a_ctrl5; 461 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_t; 462 463 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CLR(r) (r).ana_lane_0_quad_a_ctrl5[0] = 0 464 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_SET(r,d) (r).ana_lane_0_quad_a_ctrl5[0] = d 465 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_GET(r) (r).ana_lane_0_quad_a_ctrl5[0] 466 467 /* 468 * These macros can be used to access individual fields. 469 */ 470 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_0_quad_a_ctrl5[0]) >> 4) & 0x3ff) 471 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_0_quad_a_ctrl5[0]=(((r).ana_lane_0_quad_a_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 472 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_0_quad_a_ctrl5[0]) >> 1) & 0x1) 473 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_0_quad_a_ctrl5[0]=(((r).ana_lane_0_quad_a_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 474 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_0_quad_a_ctrl5[0]) & 0x1) 475 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_0_quad_a_ctrl5[0]=(((r).ana_lane_0_quad_a_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 476 477 /* 478 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL5. 479 */ 480 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r,_r._ana_lane_0_quad_a_ctrl5) 481 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r,_r._ana_lane_0_quad_a_ctrl5) 482 483 /* 484 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 485 * will be redefined without the chip prefix for easier programming. 486 * If multiple chips will be programmed in the same source file, then you should 487 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 488 * and refer to the fully qualified versions. 489 */ 490 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 491 492 #define ANA_LANE_0_QUAD_A_CTRL5r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r 493 #define ANA_LANE_0_QUAD_A_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_SIZE 494 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_t ANA_LANE_0_QUAD_A_CTRL5r_t; 495 #define ANA_LANE_0_QUAD_A_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CLR 496 #define ANA_LANE_0_QUAD_A_CTRL5r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_SET 497 #define ANA_LANE_0_QUAD_A_CTRL5r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_GET 498 #define ANA_LANE_0_QUAD_A_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_LA_GCTRLf_GET 499 #define ANA_LANE_0_QUAD_A_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_LA_GCTRLf_SET 500 #define ANA_LANE_0_QUAD_A_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_PDf_GET 501 #define ANA_LANE_0_QUAD_A_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_PDf_SET 502 #define ANA_LANE_0_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET 503 #define ANA_LANE_0_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET 504 #define READ_ANA_LANE_0_QUAD_A_CTRL5r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL5r 505 #define WRITE_ANA_LANE_0_QUAD_A_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL5r 506 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL5r 507 508 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 509 /******************************************************************************* 510 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL5r' 511 */ 512 513 514 515 516 /******************************************************************************* 517 * CHIP: BCMI_HURACAN 518 * REGISTER: ANA_LANE_0_QUAD_A_CTRL6 519 * BLOCKS: ANA_LANE_0_QUAD_A 520 * REGADDR: 0x8106 521 * DEVAD: 1 522 * DESC: control registers 0 523 * RESETVAL: 0x0 (0) 524 * ACCESS: R/W 525 * FIELDS: 526 * LA_DEGAIN 527 * LA_DETUNE 528 */ 529 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r (0x00018106 | PHYMOD_REG_ACC_RAW) 530 531 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_SIZE 4 532 533 /* 534 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL6. 535 */ 536 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_s { 537 uint32_t v[1]; 538 uint32_t ana_lane_0_quad_a_ctrl6[1]; 539 uint32_t _ana_lane_0_quad_a_ctrl6; 540 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_t; 541 542 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_CLR(r) (r).ana_lane_0_quad_a_ctrl6[0] = 0 543 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_SET(r,d) (r).ana_lane_0_quad_a_ctrl6[0] = d 544 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_GET(r) (r).ana_lane_0_quad_a_ctrl6[0] 545 546 /* 547 * These macros can be used to access individual fields. 548 */ 549 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_0_quad_a_ctrl6[0]) >> 8) & 0xff) 550 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_0_quad_a_ctrl6[0]=(((r).ana_lane_0_quad_a_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 551 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_0_quad_a_ctrl6[0]) & 0x1f) 552 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_0_quad_a_ctrl6[0]=(((r).ana_lane_0_quad_a_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 553 554 /* 555 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL6. 556 */ 557 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r,_r._ana_lane_0_quad_a_ctrl6) 558 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r,_r._ana_lane_0_quad_a_ctrl6) 559 560 /* 561 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 562 * will be redefined without the chip prefix for easier programming. 563 * If multiple chips will be programmed in the same source file, then you should 564 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 565 * and refer to the fully qualified versions. 566 */ 567 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 568 569 #define ANA_LANE_0_QUAD_A_CTRL6r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r 570 #define ANA_LANE_0_QUAD_A_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_SIZE 571 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_t ANA_LANE_0_QUAD_A_CTRL6r_t; 572 #define ANA_LANE_0_QUAD_A_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_CLR 573 #define ANA_LANE_0_QUAD_A_CTRL6r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_SET 574 #define ANA_LANE_0_QUAD_A_CTRL6r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_GET 575 #define ANA_LANE_0_QUAD_A_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DETUNEf_GET 576 #define ANA_LANE_0_QUAD_A_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DETUNEf_SET 577 #define ANA_LANE_0_QUAD_A_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DEGAINf_GET 578 #define ANA_LANE_0_QUAD_A_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r_LA_DEGAINf_SET 579 #define READ_ANA_LANE_0_QUAD_A_CTRL6r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL6r 580 #define WRITE_ANA_LANE_0_QUAD_A_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL6r 581 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL6r 582 583 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 584 /******************************************************************************* 585 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL6r' 586 */ 587 588 589 590 591 /******************************************************************************* 592 * CHIP: BCMI_HURACAN 593 * REGISTER: ANA_LANE_0_QUAD_A_CTRL7 594 * BLOCKS: ANA_LANE_0_QUAD_A 595 * REGADDR: 0x8107 596 * DEVAD: 1 597 * DESC: control registers 0 598 * RESETVAL: 0x0 (0) 599 * ACCESS: R/W 600 * FIELDS: 601 * LA_LIN_MODE 602 * RX_BIAS_FB_PDN 603 */ 604 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r (0x00018107 | PHYMOD_REG_ACC_RAW) 605 606 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_SIZE 4 607 608 /* 609 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL7. 610 */ 611 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_s { 612 uint32_t v[1]; 613 uint32_t ana_lane_0_quad_a_ctrl7[1]; 614 uint32_t _ana_lane_0_quad_a_ctrl7; 615 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_t; 616 617 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_CLR(r) (r).ana_lane_0_quad_a_ctrl7[0] = 0 618 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_SET(r,d) (r).ana_lane_0_quad_a_ctrl7[0] = d 619 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_GET(r) (r).ana_lane_0_quad_a_ctrl7[0] 620 621 /* 622 * These macros can be used to access individual fields. 623 */ 624 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_0_quad_a_ctrl7[0]) >> 8) & 0x1) 625 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_0_quad_a_ctrl7[0]=(((r).ana_lane_0_quad_a_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 626 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_0_quad_a_ctrl7[0]) & 0x1f) 627 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_0_quad_a_ctrl7[0]=(((r).ana_lane_0_quad_a_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 628 629 /* 630 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL7. 631 */ 632 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r,_r._ana_lane_0_quad_a_ctrl7) 633 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r,_r._ana_lane_0_quad_a_ctrl7) 634 635 /* 636 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 637 * will be redefined without the chip prefix for easier programming. 638 * If multiple chips will be programmed in the same source file, then you should 639 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 640 * and refer to the fully qualified versions. 641 */ 642 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 643 644 #define ANA_LANE_0_QUAD_A_CTRL7r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r 645 #define ANA_LANE_0_QUAD_A_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_SIZE 646 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_t ANA_LANE_0_QUAD_A_CTRL7r_t; 647 #define ANA_LANE_0_QUAD_A_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_CLR 648 #define ANA_LANE_0_QUAD_A_CTRL7r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_SET 649 #define ANA_LANE_0_QUAD_A_CTRL7r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_GET 650 #define ANA_LANE_0_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET 651 #define ANA_LANE_0_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET 652 #define ANA_LANE_0_QUAD_A_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_LA_LIN_MODEf_GET 653 #define ANA_LANE_0_QUAD_A_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r_LA_LIN_MODEf_SET 654 #define READ_ANA_LANE_0_QUAD_A_CTRL7r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL7r 655 #define WRITE_ANA_LANE_0_QUAD_A_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL7r 656 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL7r 657 658 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 659 /******************************************************************************* 660 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL7r' 661 */ 662 663 664 665 666 /******************************************************************************* 667 * CHIP: BCMI_HURACAN 668 * REGISTER: ANA_LANE_0_QUAD_A_CTRL8 669 * BLOCKS: ANA_LANE_0_QUAD_A 670 * REGADDR: 0x8108 671 * DEVAD: 1 672 * DESC: control registers 0 673 * RESETVAL: 0x0 (0) 674 * ACCESS: R/W 675 * FIELDS: 676 * LA_PD 677 * LA_PD_IDLE 678 * RXTX_RESERVED_FOR_99_95 679 */ 680 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r (0x00018108 | PHYMOD_REG_ACC_RAW) 681 682 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_SIZE 4 683 684 /* 685 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL8. 686 */ 687 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_s { 688 uint32_t v[1]; 689 uint32_t ana_lane_0_quad_a_ctrl8[1]; 690 uint32_t _ana_lane_0_quad_a_ctrl8; 691 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_t; 692 693 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_CLR(r) (r).ana_lane_0_quad_a_ctrl8[0] = 0 694 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_SET(r,d) (r).ana_lane_0_quad_a_ctrl8[0] = d 695 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_GET(r) (r).ana_lane_0_quad_a_ctrl8[0] 696 697 /* 698 * These macros can be used to access individual fields. 699 */ 700 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_0_quad_a_ctrl8[0]) >> 4) & 0x1f) 701 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_0_quad_a_ctrl8[0]=(((r).ana_lane_0_quad_a_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 702 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_0_quad_a_ctrl8[0]) >> 1) & 0x1) 703 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_0_quad_a_ctrl8[0]=(((r).ana_lane_0_quad_a_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 704 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_0_quad_a_ctrl8[0]) & 0x1) 705 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_0_quad_a_ctrl8[0]=(((r).ana_lane_0_quad_a_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 706 707 /* 708 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL8. 709 */ 710 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r,_r._ana_lane_0_quad_a_ctrl8) 711 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r,_r._ana_lane_0_quad_a_ctrl8) 712 713 /* 714 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 715 * will be redefined without the chip prefix for easier programming. 716 * If multiple chips will be programmed in the same source file, then you should 717 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 718 * and refer to the fully qualified versions. 719 */ 720 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 721 722 #define ANA_LANE_0_QUAD_A_CTRL8r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r 723 #define ANA_LANE_0_QUAD_A_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_SIZE 724 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_t ANA_LANE_0_QUAD_A_CTRL8r_t; 725 #define ANA_LANE_0_QUAD_A_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_CLR 726 #define ANA_LANE_0_QUAD_A_CTRL8r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_SET 727 #define ANA_LANE_0_QUAD_A_CTRL8r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_GET 728 #define ANA_LANE_0_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 729 #define ANA_LANE_0_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 730 #define ANA_LANE_0_QUAD_A_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PD_IDLEf_GET 731 #define ANA_LANE_0_QUAD_A_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PD_IDLEf_SET 732 #define ANA_LANE_0_QUAD_A_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PDf_GET 733 #define ANA_LANE_0_QUAD_A_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r_LA_PDf_SET 734 #define READ_ANA_LANE_0_QUAD_A_CTRL8r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL8r 735 #define WRITE_ANA_LANE_0_QUAD_A_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL8r 736 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL8r 737 738 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 739 /******************************************************************************* 740 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL8r' 741 */ 742 743 744 745 746 /******************************************************************************* 747 * CHIP: BCMI_HURACAN 748 * REGISTER: ANA_LANE_0_QUAD_A_CTRL9 749 * BLOCKS: ANA_LANE_0_QUAD_A 750 * REGADDR: 0x8109 751 * DEVAD: 1 752 * DESC: control registers 0 753 * RESETVAL: 0x0 (0) 754 * ACCESS: R/W 755 * FIELDS: 756 * DRV_POST1 757 * DLINE_SWING_1 758 * DLINE_SWING_2 759 * DLINE_DELAY_CTRL 760 */ 761 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r (0x00018109 | PHYMOD_REG_ACC_RAW) 762 763 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_SIZE 4 764 765 /* 766 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL9. 767 */ 768 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_s { 769 uint32_t v[1]; 770 uint32_t ana_lane_0_quad_a_ctrl9[1]; 771 uint32_t _ana_lane_0_quad_a_ctrl9; 772 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_t; 773 774 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_CLR(r) (r).ana_lane_0_quad_a_ctrl9[0] = 0 775 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_SET(r,d) (r).ana_lane_0_quad_a_ctrl9[0] = d 776 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_GET(r) (r).ana_lane_0_quad_a_ctrl9[0] 777 778 /* 779 * These macros can be used to access individual fields. 780 */ 781 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_0_quad_a_ctrl9[0]) >> 12) & 0x7) 782 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_0_quad_a_ctrl9[0]=(((r).ana_lane_0_quad_a_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 783 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_0_quad_a_ctrl9[0]) >> 8) & 0x3) 784 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_0_quad_a_ctrl9[0]=(((r).ana_lane_0_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 785 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_0_quad_a_ctrl9[0]) >> 4) & 0x3) 786 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_0_quad_a_ctrl9[0]=(((r).ana_lane_0_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 787 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_0_quad_a_ctrl9[0]) & 0xf) 788 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_0_quad_a_ctrl9[0]=(((r).ana_lane_0_quad_a_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 789 790 /* 791 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL9. 792 */ 793 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r,_r._ana_lane_0_quad_a_ctrl9) 794 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r,_r._ana_lane_0_quad_a_ctrl9) 795 796 /* 797 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 798 * will be redefined without the chip prefix for easier programming. 799 * If multiple chips will be programmed in the same source file, then you should 800 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 801 * and refer to the fully qualified versions. 802 */ 803 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 804 805 #define ANA_LANE_0_QUAD_A_CTRL9r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r 806 #define ANA_LANE_0_QUAD_A_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_SIZE 807 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_t ANA_LANE_0_QUAD_A_CTRL9r_t; 808 #define ANA_LANE_0_QUAD_A_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_CLR 809 #define ANA_LANE_0_QUAD_A_CTRL9r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_SET 810 #define ANA_LANE_0_QUAD_A_CTRL9r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_GET 811 #define ANA_LANE_0_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET 812 #define ANA_LANE_0_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET 813 #define ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_2f_GET 814 #define ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_2f_SET 815 #define ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_1f_GET 816 #define ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DLINE_SWING_1f_SET 817 #define ANA_LANE_0_QUAD_A_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DRV_POST1f_GET 818 #define ANA_LANE_0_QUAD_A_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r_DRV_POST1f_SET 819 #define READ_ANA_LANE_0_QUAD_A_CTRL9r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL9r 820 #define WRITE_ANA_LANE_0_QUAD_A_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL9r 821 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL9r 822 823 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 824 /******************************************************************************* 825 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL9r' 826 */ 827 828 829 830 831 /******************************************************************************* 832 * CHIP: BCMI_HURACAN 833 * REGISTER: ANA_LANE_0_QUAD_A_CTRL10 834 * BLOCKS: ANA_LANE_0_QUAD_A 835 * REGADDR: 0x810a 836 * DEVAD: 1 837 * DESC: control registers 0 838 * RESETVAL: 0x0 (0) 839 * ACCESS: R/W 840 * FIELDS: 841 * DRV_PWD 842 * DLINE_PWD 843 * DRV_VBSEL 844 * DRV_MAIN 845 * DRV_MAIN_PU 846 */ 847 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r (0x0001810a | PHYMOD_REG_ACC_RAW) 848 849 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_SIZE 4 850 851 /* 852 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL10. 853 */ 854 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_s { 855 uint32_t v[1]; 856 uint32_t ana_lane_0_quad_a_ctrl10[1]; 857 uint32_t _ana_lane_0_quad_a_ctrl10; 858 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_t; 859 860 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_CLR(r) (r).ana_lane_0_quad_a_ctrl10[0] = 0 861 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_SET(r,d) (r).ana_lane_0_quad_a_ctrl10[0] = d 862 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_GET(r) (r).ana_lane_0_quad_a_ctrl10[0] 863 864 /* 865 * These macros can be used to access individual fields. 866 */ 867 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_0_quad_a_ctrl10[0]) >> 12) & 0xf) 868 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_0_quad_a_ctrl10[0]=(((r).ana_lane_0_quad_a_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 869 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_0_quad_a_ctrl10[0]) >> 4) & 0x3f) 870 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_0_quad_a_ctrl10[0]=(((r).ana_lane_0_quad_a_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 871 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_0_quad_a_ctrl10[0]) >> 2) & 0x1) 872 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_0_quad_a_ctrl10[0]=(((r).ana_lane_0_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 873 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_0_quad_a_ctrl10[0]) >> 1) & 0x1) 874 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_0_quad_a_ctrl10[0]=(((r).ana_lane_0_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 875 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_0_quad_a_ctrl10[0]) & 0x1) 876 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_0_quad_a_ctrl10[0]=(((r).ana_lane_0_quad_a_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 877 878 /* 879 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL10. 880 */ 881 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r,_r._ana_lane_0_quad_a_ctrl10) 882 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r,_r._ana_lane_0_quad_a_ctrl10) 883 884 /* 885 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 886 * will be redefined without the chip prefix for easier programming. 887 * If multiple chips will be programmed in the same source file, then you should 888 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 889 * and refer to the fully qualified versions. 890 */ 891 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 892 893 #define ANA_LANE_0_QUAD_A_CTRL10r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r 894 #define ANA_LANE_0_QUAD_A_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_SIZE 895 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_t ANA_LANE_0_QUAD_A_CTRL10r_t; 896 #define ANA_LANE_0_QUAD_A_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_CLR 897 #define ANA_LANE_0_QUAD_A_CTRL10r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_SET 898 #define ANA_LANE_0_QUAD_A_CTRL10r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_GET 899 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET 900 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET 901 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAINf_GET 902 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_MAINf_SET 903 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_VBSELf_GET 904 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_VBSELf_SET 905 #define ANA_LANE_0_QUAD_A_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DLINE_PWDf_GET 906 #define ANA_LANE_0_QUAD_A_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DLINE_PWDf_SET 907 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_PWDf_GET 908 #define ANA_LANE_0_QUAD_A_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r_DRV_PWDf_SET 909 #define READ_ANA_LANE_0_QUAD_A_CTRL10r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL10r 910 #define WRITE_ANA_LANE_0_QUAD_A_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL10r 911 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL10r 912 913 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 914 /******************************************************************************* 915 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL10r' 916 */ 917 918 919 920 921 /******************************************************************************* 922 * CHIP: BCMI_HURACAN 923 * REGISTER: ANA_LANE_0_QUAD_A_CTRL11 924 * BLOCKS: ANA_LANE_0_QUAD_A 925 * REGADDR: 0x810b 926 * DEVAD: 1 927 * DESC: control registers 0 928 * RESETVAL: 0x0 (0) 929 * ACCESS: R/W 930 * FIELDS: 931 * RXTX_RESERVED_FOR_143_128 932 */ 933 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r (0x0001810b | PHYMOD_REG_ACC_RAW) 934 935 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_SIZE 4 936 937 /* 938 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL11. 939 */ 940 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_s { 941 uint32_t v[1]; 942 uint32_t ana_lane_0_quad_a_ctrl11[1]; 943 uint32_t _ana_lane_0_quad_a_ctrl11; 944 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_t; 945 946 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_CLR(r) (r).ana_lane_0_quad_a_ctrl11[0] = 0 947 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_SET(r,d) (r).ana_lane_0_quad_a_ctrl11[0] = d 948 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_GET(r) (r).ana_lane_0_quad_a_ctrl11[0] 949 950 /* 951 * These macros can be used to access individual fields. 952 */ 953 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_0_quad_a_ctrl11[0]) & 0xffff) 954 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_0_quad_a_ctrl11[0]=(((r).ana_lane_0_quad_a_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 955 956 /* 957 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL11. 958 */ 959 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r,_r._ana_lane_0_quad_a_ctrl11) 960 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r,_r._ana_lane_0_quad_a_ctrl11) 961 962 /* 963 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 964 * will be redefined without the chip prefix for easier programming. 965 * If multiple chips will be programmed in the same source file, then you should 966 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 967 * and refer to the fully qualified versions. 968 */ 969 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 970 971 #define ANA_LANE_0_QUAD_A_CTRL11r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r 972 #define ANA_LANE_0_QUAD_A_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_SIZE 973 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_t ANA_LANE_0_QUAD_A_CTRL11r_t; 974 #define ANA_LANE_0_QUAD_A_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_CLR 975 #define ANA_LANE_0_QUAD_A_CTRL11r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_SET 976 #define ANA_LANE_0_QUAD_A_CTRL11r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_GET 977 #define ANA_LANE_0_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 978 #define ANA_LANE_0_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 979 #define READ_ANA_LANE_0_QUAD_A_CTRL11r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL11r 980 #define WRITE_ANA_LANE_0_QUAD_A_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL11r 981 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL11r 982 983 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 984 /******************************************************************************* 985 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL11r' 986 */ 987 988 989 990 991 /******************************************************************************* 992 * CHIP: BCMI_HURACAN 993 * REGISTER: ANA_LANE_0_QUAD_A_CTRL12 994 * BLOCKS: ANA_LANE_0_QUAD_A 995 * REGADDR: 0x810c 996 * DEVAD: 1 997 * DESC: control registers 0 998 * RESETVAL: 0x0 (0) 999 * ACCESS: R/W 1000 * FIELDS: 1001 * LA_RESCAL_FRC_VAL 1002 * LA_RESCAL_FRC 1003 * DRV_RESCAL_FRC_VAL 1004 * DRV_RESCAL_FRC 1005 */ 1006 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r (0x0001810c | PHYMOD_REG_ACC_RAW) 1007 1008 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_SIZE 4 1009 1010 /* 1011 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL12. 1012 */ 1013 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_s { 1014 uint32_t v[1]; 1015 uint32_t ana_lane_0_quad_a_ctrl12[1]; 1016 uint32_t _ana_lane_0_quad_a_ctrl12; 1017 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_t; 1018 1019 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_CLR(r) (r).ana_lane_0_quad_a_ctrl12[0] = 0 1020 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_SET(r,d) (r).ana_lane_0_quad_a_ctrl12[0] = d 1021 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_GET(r) (r).ana_lane_0_quad_a_ctrl12[0] 1022 1023 /* 1024 * These macros can be used to access individual fields. 1025 */ 1026 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_a_ctrl12[0]) >> 12) & 0x1) 1027 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_a_ctrl12[0]=(((r).ana_lane_0_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 1028 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_a_ctrl12[0]) >> 8) & 0xf) 1029 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_a_ctrl12[0]=(((r).ana_lane_0_quad_a_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 1030 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_a_ctrl12[0]) >> 4) & 0x1) 1031 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_a_ctrl12[0]=(((r).ana_lane_0_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 1032 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_a_ctrl12[0]) & 0xf) 1033 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_a_ctrl12[0]=(((r).ana_lane_0_quad_a_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 1034 1035 /* 1036 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL12. 1037 */ 1038 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r,_r._ana_lane_0_quad_a_ctrl12) 1039 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r,_r._ana_lane_0_quad_a_ctrl12) 1040 1041 /* 1042 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1043 * will be redefined without the chip prefix for easier programming. 1044 * If multiple chips will be programmed in the same source file, then you should 1045 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1046 * and refer to the fully qualified versions. 1047 */ 1048 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1049 1050 #define ANA_LANE_0_QUAD_A_CTRL12r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r 1051 #define ANA_LANE_0_QUAD_A_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_SIZE 1052 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_t ANA_LANE_0_QUAD_A_CTRL12r_t; 1053 #define ANA_LANE_0_QUAD_A_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_CLR 1054 #define ANA_LANE_0_QUAD_A_CTRL12r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_SET 1055 #define ANA_LANE_0_QUAD_A_CTRL12r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_GET 1056 #define ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET 1057 #define ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET 1058 #define ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET 1059 #define ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET 1060 #define ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET 1061 #define ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET 1062 #define ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET 1063 #define ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET 1064 #define READ_ANA_LANE_0_QUAD_A_CTRL12r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL12r 1065 #define WRITE_ANA_LANE_0_QUAD_A_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL12r 1066 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL12r 1067 1068 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1069 /******************************************************************************* 1070 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL12r' 1071 */ 1072 1073 1074 1075 1076 /******************************************************************************* 1077 * CHIP: BCMI_HURACAN 1078 * REGISTER: ANA_LANE_0_QUAD_A_CTRL13 1079 * BLOCKS: ANA_LANE_0_QUAD_A 1080 * REGADDR: 0x810d 1081 * DEVAD: 1 1082 * DESC: control registers 0 1083 * RESETVAL: 0x0 (0) 1084 * ACCESS: R/W 1085 * FIELDS: 1086 * CTLE_RESCAL_FRC_VAL 1087 * CTLE_RESCAL_FRC 1088 */ 1089 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r (0x0001810d | PHYMOD_REG_ACC_RAW) 1090 1091 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_SIZE 4 1092 1093 /* 1094 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL13. 1095 */ 1096 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_s { 1097 uint32_t v[1]; 1098 uint32_t ana_lane_0_quad_a_ctrl13[1]; 1099 uint32_t _ana_lane_0_quad_a_ctrl13; 1100 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_t; 1101 1102 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CLR(r) (r).ana_lane_0_quad_a_ctrl13[0] = 0 1103 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_SET(r,d) (r).ana_lane_0_quad_a_ctrl13[0] = d 1104 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_GET(r) (r).ana_lane_0_quad_a_ctrl13[0] 1105 1106 /* 1107 * These macros can be used to access individual fields. 1108 */ 1109 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_a_ctrl13[0]) >> 4) & 0x1) 1110 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_a_ctrl13[0]=(((r).ana_lane_0_quad_a_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 1111 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_a_ctrl13[0]) & 0xf) 1112 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_a_ctrl13[0]=(((r).ana_lane_0_quad_a_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 1113 1114 /* 1115 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL13. 1116 */ 1117 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r,_r._ana_lane_0_quad_a_ctrl13) 1118 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r,_r._ana_lane_0_quad_a_ctrl13) 1119 1120 /* 1121 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1122 * will be redefined without the chip prefix for easier programming. 1123 * If multiple chips will be programmed in the same source file, then you should 1124 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1125 * and refer to the fully qualified versions. 1126 */ 1127 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1128 1129 #define ANA_LANE_0_QUAD_A_CTRL13r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r 1130 #define ANA_LANE_0_QUAD_A_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_SIZE 1131 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_t ANA_LANE_0_QUAD_A_CTRL13r_t; 1132 #define ANA_LANE_0_QUAD_A_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CLR 1133 #define ANA_LANE_0_QUAD_A_CTRL13r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_SET 1134 #define ANA_LANE_0_QUAD_A_CTRL13r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_GET 1135 #define ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET 1136 #define ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET 1137 #define ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 1138 #define ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 1139 #define READ_ANA_LANE_0_QUAD_A_CTRL13r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL13r 1140 #define WRITE_ANA_LANE_0_QUAD_A_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL13r 1141 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL13r 1142 1143 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1144 /******************************************************************************* 1145 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL13r' 1146 */ 1147 1148 1149 1150 1151 /******************************************************************************* 1152 * CHIP: BCMI_HURACAN 1153 * REGISTER: ANA_LANE_0_QUAD_A_CTRL14 1154 * BLOCKS: ANA_LANE_0_QUAD_A 1155 * REGADDR: 0x810e 1156 * DEVAD: 1 1157 * DESC: control registers 0 1158 * RESETVAL: 0x0 (0) 1159 * ACCESS: R/W 1160 * FIELDS: 1161 * TX_IDLE_FRC_VAL 1162 * TX_IDLE_FRC 1163 * RXSD_IDLE_OVRD 1164 */ 1165 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r (0x0001810e | PHYMOD_REG_ACC_RAW) 1166 1167 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_SIZE 4 1168 1169 /* 1170 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL14. 1171 */ 1172 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_s { 1173 uint32_t v[1]; 1174 uint32_t ana_lane_0_quad_a_ctrl14[1]; 1175 uint32_t _ana_lane_0_quad_a_ctrl14; 1176 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_t; 1177 1178 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_CLR(r) (r).ana_lane_0_quad_a_ctrl14[0] = 0 1179 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_SET(r,d) (r).ana_lane_0_quad_a_ctrl14[0] = d 1180 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_GET(r) (r).ana_lane_0_quad_a_ctrl14[0] 1181 1182 /* 1183 * These macros can be used to access individual fields. 1184 */ 1185 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_0_quad_a_ctrl14[0]) >> 4) & 0x1) 1186 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_0_quad_a_ctrl14[0]=(((r).ana_lane_0_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 1187 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_0_quad_a_ctrl14[0]) >> 1) & 0x1) 1188 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_0_quad_a_ctrl14[0]=(((r).ana_lane_0_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 1189 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_0_quad_a_ctrl14[0]) & 0x1) 1190 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_a_ctrl14[0]=(((r).ana_lane_0_quad_a_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 1191 1192 /* 1193 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL14. 1194 */ 1195 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r,_r._ana_lane_0_quad_a_ctrl14) 1196 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r,_r._ana_lane_0_quad_a_ctrl14) 1197 1198 /* 1199 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1200 * will be redefined without the chip prefix for easier programming. 1201 * If multiple chips will be programmed in the same source file, then you should 1202 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1203 * and refer to the fully qualified versions. 1204 */ 1205 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1206 1207 #define ANA_LANE_0_QUAD_A_CTRL14r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r 1208 #define ANA_LANE_0_QUAD_A_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_SIZE 1209 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_t ANA_LANE_0_QUAD_A_CTRL14r_t; 1210 #define ANA_LANE_0_QUAD_A_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_CLR 1211 #define ANA_LANE_0_QUAD_A_CTRL14r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_SET 1212 #define ANA_LANE_0_QUAD_A_CTRL14r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_GET 1213 #define ANA_LANE_0_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET 1214 #define ANA_LANE_0_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET 1215 #define ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET 1216 #define ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET 1217 #define ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET 1218 #define ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET 1219 #define READ_ANA_LANE_0_QUAD_A_CTRL14r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL14r 1220 #define WRITE_ANA_LANE_0_QUAD_A_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL14r 1221 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL14r 1222 1223 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1224 /******************************************************************************* 1225 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL14r' 1226 */ 1227 1228 1229 1230 1231 /******************************************************************************* 1232 * CHIP: BCMI_HURACAN 1233 * REGISTER: ANA_LANE_0_QUAD_A_CTRL15 1234 * BLOCKS: ANA_LANE_0_QUAD_A 1235 * REGADDR: 0x810f 1236 * DEVAD: 1 1237 * DESC: sigdet filter settings 0 1238 * RESETVAL: 0x0 (0) 1239 * ACCESS: R/W 1240 * FIELDS: 1241 * SIGDET_DIS 1242 * SIGDET_1US_EN 1243 * SIGDET_FRC_VAL 1244 * SIGDET_FRC 1245 * HOLD_LOS_COUNT 1246 * HOLD_SD_COUNT 1247 */ 1248 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r (0x0001810f | PHYMOD_REG_ACC_RAW) 1249 1250 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIZE 4 1251 1252 /* 1253 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL15. 1254 */ 1255 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_s { 1256 uint32_t v[1]; 1257 uint32_t ana_lane_0_quad_a_ctrl15[1]; 1258 uint32_t _ana_lane_0_quad_a_ctrl15; 1259 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_t; 1260 1261 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_CLR(r) (r).ana_lane_0_quad_a_ctrl15[0] = 0 1262 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SET(r,d) (r).ana_lane_0_quad_a_ctrl15[0] = d 1263 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_GET(r) (r).ana_lane_0_quad_a_ctrl15[0] 1264 1265 /* 1266 * These macros can be used to access individual fields. 1267 */ 1268 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_a_ctrl15[0]) >> 8) & 0x7) 1269 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_a_ctrl15[0]=(((r).ana_lane_0_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 1270 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_0_quad_a_ctrl15[0]) >> 4) & 0x7) 1271 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_a_ctrl15[0]=(((r).ana_lane_0_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 1272 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_0_quad_a_ctrl15[0]) >> 3) & 0x1) 1273 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_0_quad_a_ctrl15[0]=(((r).ana_lane_0_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 1274 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_a_ctrl15[0]) >> 2) & 0x1) 1275 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_a_ctrl15[0]=(((r).ana_lane_0_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 1276 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_0_quad_a_ctrl15[0]) >> 1) & 0x1) 1277 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_0_quad_a_ctrl15[0]=(((r).ana_lane_0_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 1278 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_0_quad_a_ctrl15[0]) & 0x1) 1279 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_0_quad_a_ctrl15[0]=(((r).ana_lane_0_quad_a_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 1280 1281 /* 1282 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL15. 1283 */ 1284 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r,_r._ana_lane_0_quad_a_ctrl15) 1285 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r,_r._ana_lane_0_quad_a_ctrl15) 1286 1287 /* 1288 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1289 * will be redefined without the chip prefix for easier programming. 1290 * If multiple chips will be programmed in the same source file, then you should 1291 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1292 * and refer to the fully qualified versions. 1293 */ 1294 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1295 1296 #define ANA_LANE_0_QUAD_A_CTRL15r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r 1297 #define ANA_LANE_0_QUAD_A_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIZE 1298 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_t ANA_LANE_0_QUAD_A_CTRL15r_t; 1299 #define ANA_LANE_0_QUAD_A_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_CLR 1300 #define ANA_LANE_0_QUAD_A_CTRL15r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SET 1301 #define ANA_LANE_0_QUAD_A_CTRL15r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_GET 1302 #define ANA_LANE_0_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET 1303 #define ANA_LANE_0_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET 1304 #define ANA_LANE_0_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET 1305 #define ANA_LANE_0_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET 1306 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRCf_GET 1307 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRCf_SET 1308 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET 1309 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET 1310 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET 1311 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET 1312 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_DISf_GET 1313 #define ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r_SIGDET_DISf_SET 1314 #define READ_ANA_LANE_0_QUAD_A_CTRL15r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL15r 1315 #define WRITE_ANA_LANE_0_QUAD_A_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL15r 1316 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL15r 1317 1318 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1319 /******************************************************************************* 1320 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL15r' 1321 */ 1322 1323 1324 1325 1326 /******************************************************************************* 1327 * CHIP: BCMI_HURACAN 1328 * REGISTER: ANA_LANE_0_QUAD_A_CTRL16 1329 * BLOCKS: ANA_LANE_0_QUAD_A 1330 * REGADDR: 0x8110 1331 * DEVAD: 1 1332 * DESC: sigdet filter settings 1 1333 * RESETVAL: 0x0 (0) 1334 * ACCESS: R/W 1335 * FIELDS: 1336 * LOS_COUNT 1337 * SD_COUNT 1338 */ 1339 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r (0x00018110 | PHYMOD_REG_ACC_RAW) 1340 1341 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SIZE 4 1342 1343 /* 1344 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_CTRL16. 1345 */ 1346 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_s { 1347 uint32_t v[1]; 1348 uint32_t ana_lane_0_quad_a_ctrl16[1]; 1349 uint32_t _ana_lane_0_quad_a_ctrl16; 1350 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_t; 1351 1352 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_CLR(r) (r).ana_lane_0_quad_a_ctrl16[0] = 0 1353 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SET(r,d) (r).ana_lane_0_quad_a_ctrl16[0] = d 1354 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_GET(r) (r).ana_lane_0_quad_a_ctrl16[0] 1355 1356 /* 1357 * These macros can be used to access individual fields. 1358 */ 1359 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_a_ctrl16[0]) >> 8) & 0x1f) 1360 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_a_ctrl16[0]=(((r).ana_lane_0_quad_a_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 1361 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_0_quad_a_ctrl16[0]) & 0x1f) 1362 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_a_ctrl16[0]=(((r).ana_lane_0_quad_a_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 1363 1364 /* 1365 * These macros can be used to access ANA_LANE_0_QUAD_A_CTRL16. 1366 */ 1367 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r,_r._ana_lane_0_quad_a_ctrl16) 1368 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r,_r._ana_lane_0_quad_a_ctrl16) 1369 1370 /* 1371 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1372 * will be redefined without the chip prefix for easier programming. 1373 * If multiple chips will be programmed in the same source file, then you should 1374 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1375 * and refer to the fully qualified versions. 1376 */ 1377 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1378 1379 #define ANA_LANE_0_QUAD_A_CTRL16r BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r 1380 #define ANA_LANE_0_QUAD_A_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SIZE 1381 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_t ANA_LANE_0_QUAD_A_CTRL16r_t; 1382 #define ANA_LANE_0_QUAD_A_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_CLR 1383 #define ANA_LANE_0_QUAD_A_CTRL16r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SET 1384 #define ANA_LANE_0_QUAD_A_CTRL16r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_GET 1385 #define ANA_LANE_0_QUAD_A_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SD_COUNTf_GET 1386 #define ANA_LANE_0_QUAD_A_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_SD_COUNTf_SET 1387 #define ANA_LANE_0_QUAD_A_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_LOS_COUNTf_GET 1388 #define ANA_LANE_0_QUAD_A_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r_LOS_COUNTf_SET 1389 #define READ_ANA_LANE_0_QUAD_A_CTRL16r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_CTRL16r 1390 #define WRITE_ANA_LANE_0_QUAD_A_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_CTRL16r 1391 #define MODIFY_ANA_LANE_0_QUAD_A_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_CTRL16r 1392 1393 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1394 /******************************************************************************* 1395 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_CTRL16r' 1396 */ 1397 1398 1399 1400 1401 /******************************************************************************* 1402 * CHIP: BCMI_HURACAN 1403 * REGISTER: ANA_LANE_0_QUAD_A_STATUS0 1404 * BLOCKS: ANA_LANE_0_QUAD_A 1405 * REGADDR: 0x8120 1406 * DEVAD: 1 1407 * DESC: status registers 0 1408 * RESETVAL: 0x0 (0) 1409 * ACCESS: R/W 1410 * FIELDS: 1411 * O_RX_SIGDET 1412 * DG_RX_SIGDET 1413 */ 1414 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r (0x00018120 | PHYMOD_REG_ACC_RAW) 1415 1416 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_SIZE 4 1417 1418 /* 1419 * This structure should be used to declare and program ANA_LANE_0_QUAD_A_STATUS0. 1420 */ 1421 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_s { 1422 uint32_t v[1]; 1423 uint32_t ana_lane_0_quad_a_status0[1]; 1424 uint32_t _ana_lane_0_quad_a_status0; 1425 } BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_t; 1426 1427 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_CLR(r) (r).ana_lane_0_quad_a_status0[0] = 0 1428 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_SET(r,d) (r).ana_lane_0_quad_a_status0[0] = d 1429 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_GET(r) (r).ana_lane_0_quad_a_status0[0] 1430 1431 /* 1432 * These macros can be used to access individual fields. 1433 */ 1434 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_0_quad_a_status0[0]) >> 1) & 0x1) 1435 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_a_status0[0]=(((r).ana_lane_0_quad_a_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 1436 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_0_quad_a_status0[0]) & 0x1) 1437 #define BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_a_status0[0]=(((r).ana_lane_0_quad_a_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 1438 1439 /* 1440 * These macros can be used to access ANA_LANE_0_QUAD_A_STATUS0. 1441 */ 1442 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r,_r._ana_lane_0_quad_a_status0) 1443 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r,_r._ana_lane_0_quad_a_status0) 1444 1445 /* 1446 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1447 * will be redefined without the chip prefix for easier programming. 1448 * If multiple chips will be programmed in the same source file, then you should 1449 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1450 * and refer to the fully qualified versions. 1451 */ 1452 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1453 1454 #define ANA_LANE_0_QUAD_A_STATUS0r BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r 1455 #define ANA_LANE_0_QUAD_A_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_SIZE 1456 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_t ANA_LANE_0_QUAD_A_STATUS0r_t; 1457 #define ANA_LANE_0_QUAD_A_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_CLR 1458 #define ANA_LANE_0_QUAD_A_STATUS0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_SET 1459 #define ANA_LANE_0_QUAD_A_STATUS0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_GET 1460 #define ANA_LANE_0_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET 1461 #define ANA_LANE_0_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET 1462 #define ANA_LANE_0_QUAD_A_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_O_RX_SIGDETf_GET 1463 #define ANA_LANE_0_QUAD_A_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r_O_RX_SIGDETf_SET 1464 #define READ_ANA_LANE_0_QUAD_A_STATUS0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_A_STATUS0r 1465 #define WRITE_ANA_LANE_0_QUAD_A_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_A_STATUS0r 1466 #define MODIFY_ANA_LANE_0_QUAD_A_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_A_STATUS0r 1467 1468 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1469 /******************************************************************************* 1470 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_A_STATUS0r' 1471 */ 1472 1473 1474 1475 1476 /******************************************************************************* 1477 * CHIP: BCMI_HURACAN 1478 * REGISTER: ANA_LANE_1_QUAD_A_CTRL0 1479 * BLOCKS: ANA_LANE_1_QUAD_A 1480 * REGADDR: 0x8200 1481 * DEVAD: 1 1482 * DESC: control registers 0 1483 * RESETVAL: 0x0 (0) 1484 * ACCESS: R/W 1485 * FIELDS: 1486 * RXTX_PWRDN 1487 * RX_SIGDET_BYPASS 1488 * RX_SIGDET_PWRDN 1489 * RX_SIGDECT_12GMODE 1490 * DC_COUPLE 1491 */ 1492 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r (0x00018200 | PHYMOD_REG_ACC_RAW) 1493 1494 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_SIZE 4 1495 1496 /* 1497 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL0. 1498 */ 1499 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_s { 1500 uint32_t v[1]; 1501 uint32_t ana_lane_1_quad_a_ctrl0[1]; 1502 uint32_t _ana_lane_1_quad_a_ctrl0; 1503 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_t; 1504 1505 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_CLR(r) (r).ana_lane_1_quad_a_ctrl0[0] = 0 1506 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_SET(r,d) (r).ana_lane_1_quad_a_ctrl0[0] = d 1507 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_GET(r) (r).ana_lane_1_quad_a_ctrl0[0] 1508 1509 /* 1510 * These macros can be used to access individual fields. 1511 */ 1512 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_1_quad_a_ctrl0[0]) >> 4) & 0x1) 1513 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_1_quad_a_ctrl0[0]=(((r).ana_lane_1_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 1514 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_1_quad_a_ctrl0[0]) >> 3) & 0x1) 1515 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_1_quad_a_ctrl0[0]=(((r).ana_lane_1_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 1516 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_1_quad_a_ctrl0[0]) >> 2) & 0x1) 1517 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_1_quad_a_ctrl0[0]=(((r).ana_lane_1_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 1518 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_1_quad_a_ctrl0[0]) >> 1) & 0x1) 1519 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_1_quad_a_ctrl0[0]=(((r).ana_lane_1_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 1520 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_1_quad_a_ctrl0[0]) & 0x1) 1521 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_1_quad_a_ctrl0[0]=(((r).ana_lane_1_quad_a_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 1522 1523 /* 1524 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL0. 1525 */ 1526 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r,_r._ana_lane_1_quad_a_ctrl0) 1527 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r,_r._ana_lane_1_quad_a_ctrl0) 1528 1529 /* 1530 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1531 * will be redefined without the chip prefix for easier programming. 1532 * If multiple chips will be programmed in the same source file, then you should 1533 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1534 * and refer to the fully qualified versions. 1535 */ 1536 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1537 1538 #define ANA_LANE_1_QUAD_A_CTRL0r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r 1539 #define ANA_LANE_1_QUAD_A_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_SIZE 1540 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_t ANA_LANE_1_QUAD_A_CTRL0r_t; 1541 #define ANA_LANE_1_QUAD_A_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_CLR 1542 #define ANA_LANE_1_QUAD_A_CTRL0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_SET 1543 #define ANA_LANE_1_QUAD_A_CTRL0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_GET 1544 #define ANA_LANE_1_QUAD_A_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_DC_COUPLEf_GET 1545 #define ANA_LANE_1_QUAD_A_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_DC_COUPLEf_SET 1546 #define ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET 1547 #define ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET 1548 #define ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET 1549 #define ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET 1550 #define ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET 1551 #define ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET 1552 #define ANA_LANE_1_QUAD_A_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RXTX_PWRDNf_GET 1553 #define ANA_LANE_1_QUAD_A_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r_RXTX_PWRDNf_SET 1554 #define READ_ANA_LANE_1_QUAD_A_CTRL0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL0r 1555 #define WRITE_ANA_LANE_1_QUAD_A_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL0r 1556 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL0r 1557 1558 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1559 /******************************************************************************* 1560 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL0r' 1561 */ 1562 1563 1564 1565 1566 /******************************************************************************* 1567 * CHIP: BCMI_HURACAN 1568 * REGISTER: ANA_LANE_1_QUAD_A_CTRL1 1569 * BLOCKS: ANA_LANE_1_QUAD_A 1570 * REGADDR: 0x8201 1571 * DEVAD: 1 1572 * DESC: control registers 0 1573 * RESETVAL: 0x0 (0) 1574 * ACCESS: R/W 1575 * FIELDS: 1576 * RX_SIGDET_THRESHOLD 1577 * REF_OCL 1578 * OCL_PWRDN 1579 * OCL_DISABLE_LOOP 1580 * RXTX_RESERVED_FOR_15_12 1581 */ 1582 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r (0x00018201 | PHYMOD_REG_ACC_RAW) 1583 1584 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_SIZE 4 1585 1586 /* 1587 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL1. 1588 */ 1589 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_s { 1590 uint32_t v[1]; 1591 uint32_t ana_lane_1_quad_a_ctrl1[1]; 1592 uint32_t _ana_lane_1_quad_a_ctrl1; 1593 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_t; 1594 1595 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_CLR(r) (r).ana_lane_1_quad_a_ctrl1[0] = 0 1596 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_SET(r,d) (r).ana_lane_1_quad_a_ctrl1[0] = d 1597 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_GET(r) (r).ana_lane_1_quad_a_ctrl1[0] 1598 1599 /* 1600 * These macros can be used to access individual fields. 1601 */ 1602 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_1_quad_a_ctrl1[0]) >> 12) & 0xf) 1603 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_1_quad_a_ctrl1[0]=(((r).ana_lane_1_quad_a_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 1604 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_1_quad_a_ctrl1[0]) >> 9) & 0x1) 1605 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_1_quad_a_ctrl1[0]=(((r).ana_lane_1_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 1606 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_1_quad_a_ctrl1[0]) >> 8) & 0x1) 1607 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_1_quad_a_ctrl1[0]=(((r).ana_lane_1_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 1608 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_1_quad_a_ctrl1[0]) >> 4) & 0x3) 1609 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_1_quad_a_ctrl1[0]=(((r).ana_lane_1_quad_a_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 1610 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_1_quad_a_ctrl1[0]) & 0x7) 1611 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_1_quad_a_ctrl1[0]=(((r).ana_lane_1_quad_a_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 1612 1613 /* 1614 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL1. 1615 */ 1616 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r,_r._ana_lane_1_quad_a_ctrl1) 1617 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r,_r._ana_lane_1_quad_a_ctrl1) 1618 1619 /* 1620 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1621 * will be redefined without the chip prefix for easier programming. 1622 * If multiple chips will be programmed in the same source file, then you should 1623 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1624 * and refer to the fully qualified versions. 1625 */ 1626 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1627 1628 #define ANA_LANE_1_QUAD_A_CTRL1r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r 1629 #define ANA_LANE_1_QUAD_A_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_SIZE 1630 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_t ANA_LANE_1_QUAD_A_CTRL1r_t; 1631 #define ANA_LANE_1_QUAD_A_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_CLR 1632 #define ANA_LANE_1_QUAD_A_CTRL1r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_SET 1633 #define ANA_LANE_1_QUAD_A_CTRL1r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_GET 1634 #define ANA_LANE_1_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 1635 #define ANA_LANE_1_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 1636 #define ANA_LANE_1_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET 1637 #define ANA_LANE_1_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET 1638 #define ANA_LANE_1_QUAD_A_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_PWRDNf_GET 1639 #define ANA_LANE_1_QUAD_A_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_OCL_PWRDNf_SET 1640 #define ANA_LANE_1_QUAD_A_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_REF_OCLf_GET 1641 #define ANA_LANE_1_QUAD_A_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_REF_OCLf_SET 1642 #define ANA_LANE_1_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET 1643 #define ANA_LANE_1_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET 1644 #define READ_ANA_LANE_1_QUAD_A_CTRL1r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL1r 1645 #define WRITE_ANA_LANE_1_QUAD_A_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL1r 1646 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL1r 1647 1648 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1649 /******************************************************************************* 1650 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL1r' 1651 */ 1652 1653 1654 1655 1656 /******************************************************************************* 1657 * CHIP: BCMI_HURACAN 1658 * REGISTER: ANA_LANE_1_QUAD_A_CTRL2 1659 * BLOCKS: ANA_LANE_1_QUAD_A 1660 * REGADDR: 0x8202 1661 * DEVAD: 1 1662 * DESC: control registers 0 1663 * RESETVAL: 0x0 (0) 1664 * ACCESS: R/W 1665 * FIELDS: 1666 * CTLE_ENB_NEGIMP 1667 * CTLE_ENB_NEGCAP 1668 */ 1669 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r (0x00018202 | PHYMOD_REG_ACC_RAW) 1670 1671 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_SIZE 4 1672 1673 /* 1674 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL2. 1675 */ 1676 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_s { 1677 uint32_t v[1]; 1678 uint32_t ana_lane_1_quad_a_ctrl2[1]; 1679 uint32_t _ana_lane_1_quad_a_ctrl2; 1680 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_t; 1681 1682 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CLR(r) (r).ana_lane_1_quad_a_ctrl2[0] = 0 1683 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_SET(r,d) (r).ana_lane_1_quad_a_ctrl2[0] = d 1684 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_GET(r) (r).ana_lane_1_quad_a_ctrl2[0] 1685 1686 /* 1687 * These macros can be used to access individual fields. 1688 */ 1689 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_1_quad_a_ctrl2[0]) >> 8) & 0x7f) 1690 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_1_quad_a_ctrl2[0]=(((r).ana_lane_1_quad_a_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 1691 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_1_quad_a_ctrl2[0]) & 0x7f) 1692 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_1_quad_a_ctrl2[0]=(((r).ana_lane_1_quad_a_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 1693 1694 /* 1695 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL2. 1696 */ 1697 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r,_r._ana_lane_1_quad_a_ctrl2) 1698 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r,_r._ana_lane_1_quad_a_ctrl2) 1699 1700 /* 1701 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1702 * will be redefined without the chip prefix for easier programming. 1703 * If multiple chips will be programmed in the same source file, then you should 1704 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1705 * and refer to the fully qualified versions. 1706 */ 1707 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1708 1709 #define ANA_LANE_1_QUAD_A_CTRL2r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r 1710 #define ANA_LANE_1_QUAD_A_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_SIZE 1711 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_t ANA_LANE_1_QUAD_A_CTRL2r_t; 1712 #define ANA_LANE_1_QUAD_A_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CLR 1713 #define ANA_LANE_1_QUAD_A_CTRL2r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_SET 1714 #define ANA_LANE_1_QUAD_A_CTRL2r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_GET 1715 #define ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET 1716 #define ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET 1717 #define ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET 1718 #define ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET 1719 #define READ_ANA_LANE_1_QUAD_A_CTRL2r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL2r 1720 #define WRITE_ANA_LANE_1_QUAD_A_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL2r 1721 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL2r 1722 1723 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1724 /******************************************************************************* 1725 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL2r' 1726 */ 1727 1728 1729 1730 1731 /******************************************************************************* 1732 * CHIP: BCMI_HURACAN 1733 * REGISTER: ANA_LANE_1_QUAD_A_CTRL3 1734 * BLOCKS: ANA_LANE_1_QUAD_A 1735 * REGADDR: 0x8203 1736 * DEVAD: 1 1737 * DESC: control registers 0 1738 * RESETVAL: 0x0 (0) 1739 * ACCESS: R/W 1740 * FIELDS: 1741 * CTLE_EN_NEGRES 1742 * CTLE_EQSEL 1743 */ 1744 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r (0x00018203 | PHYMOD_REG_ACC_RAW) 1745 1746 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_SIZE 4 1747 1748 /* 1749 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL3. 1750 */ 1751 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_s { 1752 uint32_t v[1]; 1753 uint32_t ana_lane_1_quad_a_ctrl3[1]; 1754 uint32_t _ana_lane_1_quad_a_ctrl3; 1755 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_t; 1756 1757 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CLR(r) (r).ana_lane_1_quad_a_ctrl3[0] = 0 1758 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_SET(r,d) (r).ana_lane_1_quad_a_ctrl3[0] = d 1759 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_GET(r) (r).ana_lane_1_quad_a_ctrl3[0] 1760 1761 /* 1762 * These macros can be used to access individual fields. 1763 */ 1764 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_1_quad_a_ctrl3[0]) >> 8) & 0xff) 1765 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_1_quad_a_ctrl3[0]=(((r).ana_lane_1_quad_a_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 1766 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_1_quad_a_ctrl3[0]) & 0x7f) 1767 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_1_quad_a_ctrl3[0]=(((r).ana_lane_1_quad_a_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 1768 1769 /* 1770 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL3. 1771 */ 1772 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r,_r._ana_lane_1_quad_a_ctrl3) 1773 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r,_r._ana_lane_1_quad_a_ctrl3) 1774 1775 /* 1776 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1777 * will be redefined without the chip prefix for easier programming. 1778 * If multiple chips will be programmed in the same source file, then you should 1779 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1780 * and refer to the fully qualified versions. 1781 */ 1782 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1783 1784 #define ANA_LANE_1_QUAD_A_CTRL3r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r 1785 #define ANA_LANE_1_QUAD_A_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_SIZE 1786 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_t ANA_LANE_1_QUAD_A_CTRL3r_t; 1787 #define ANA_LANE_1_QUAD_A_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CLR 1788 #define ANA_LANE_1_QUAD_A_CTRL3r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_SET 1789 #define ANA_LANE_1_QUAD_A_CTRL3r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_GET 1790 #define ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EQSELf_GET 1791 #define ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EQSELf_SET 1792 #define ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET 1793 #define ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET 1794 #define READ_ANA_LANE_1_QUAD_A_CTRL3r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL3r 1795 #define WRITE_ANA_LANE_1_QUAD_A_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL3r 1796 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL3r 1797 1798 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1799 /******************************************************************************* 1800 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL3r' 1801 */ 1802 1803 1804 1805 1806 /******************************************************************************* 1807 * CHIP: BCMI_HURACAN 1808 * REGISTER: ANA_LANE_1_QUAD_A_CTRL4 1809 * BLOCKS: ANA_LANE_1_QUAD_A 1810 * REGADDR: 0x8204 1811 * DEVAD: 1 1812 * DESC: control registers 0 1813 * RESETVAL: 0x0 (0) 1814 * ACCESS: R/W 1815 * FIELDS: 1816 * CTLE_LZEN 1817 * RXTX_RESERVED_FOR_59_52 1818 */ 1819 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r (0x00018204 | PHYMOD_REG_ACC_RAW) 1820 1821 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_SIZE 4 1822 1823 /* 1824 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL4. 1825 */ 1826 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_s { 1827 uint32_t v[1]; 1828 uint32_t ana_lane_1_quad_a_ctrl4[1]; 1829 uint32_t _ana_lane_1_quad_a_ctrl4; 1830 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_t; 1831 1832 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_CLR(r) (r).ana_lane_1_quad_a_ctrl4[0] = 0 1833 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_SET(r,d) (r).ana_lane_1_quad_a_ctrl4[0] = d 1834 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_GET(r) (r).ana_lane_1_quad_a_ctrl4[0] 1835 1836 /* 1837 * These macros can be used to access individual fields. 1838 */ 1839 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_1_quad_a_ctrl4[0]) >> 4) & 0xff) 1840 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_1_quad_a_ctrl4[0]=(((r).ana_lane_1_quad_a_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 1841 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_1_quad_a_ctrl4[0]) & 0x1) 1842 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_1_quad_a_ctrl4[0]=(((r).ana_lane_1_quad_a_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 1843 1844 /* 1845 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL4. 1846 */ 1847 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r,_r._ana_lane_1_quad_a_ctrl4) 1848 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r,_r._ana_lane_1_quad_a_ctrl4) 1849 1850 /* 1851 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1852 * will be redefined without the chip prefix for easier programming. 1853 * If multiple chips will be programmed in the same source file, then you should 1854 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1855 * and refer to the fully qualified versions. 1856 */ 1857 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1858 1859 #define ANA_LANE_1_QUAD_A_CTRL4r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r 1860 #define ANA_LANE_1_QUAD_A_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_SIZE 1861 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_t ANA_LANE_1_QUAD_A_CTRL4r_t; 1862 #define ANA_LANE_1_QUAD_A_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_CLR 1863 #define ANA_LANE_1_QUAD_A_CTRL4r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_SET 1864 #define ANA_LANE_1_QUAD_A_CTRL4r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_GET 1865 #define ANA_LANE_1_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 1866 #define ANA_LANE_1_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 1867 #define ANA_LANE_1_QUAD_A_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_CTLE_LZENf_GET 1868 #define ANA_LANE_1_QUAD_A_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r_CTLE_LZENf_SET 1869 #define READ_ANA_LANE_1_QUAD_A_CTRL4r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL4r 1870 #define WRITE_ANA_LANE_1_QUAD_A_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL4r 1871 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL4r 1872 1873 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1874 /******************************************************************************* 1875 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL4r' 1876 */ 1877 1878 1879 1880 1881 /******************************************************************************* 1882 * CHIP: BCMI_HURACAN 1883 * REGISTER: ANA_LANE_1_QUAD_A_CTRL5 1884 * BLOCKS: ANA_LANE_1_QUAD_A 1885 * REGADDR: 0x8205 1886 * DEVAD: 1 1887 * DESC: control registers 0 1888 * RESETVAL: 0x0 (0) 1889 * ACCESS: R/W 1890 * FIELDS: 1891 * CTLE_LOPEAKING 1892 * CTLE_PD 1893 * LA_GCTRL 1894 */ 1895 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r (0x00018205 | PHYMOD_REG_ACC_RAW) 1896 1897 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_SIZE 4 1898 1899 /* 1900 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL5. 1901 */ 1902 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_s { 1903 uint32_t v[1]; 1904 uint32_t ana_lane_1_quad_a_ctrl5[1]; 1905 uint32_t _ana_lane_1_quad_a_ctrl5; 1906 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_t; 1907 1908 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CLR(r) (r).ana_lane_1_quad_a_ctrl5[0] = 0 1909 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_SET(r,d) (r).ana_lane_1_quad_a_ctrl5[0] = d 1910 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_GET(r) (r).ana_lane_1_quad_a_ctrl5[0] 1911 1912 /* 1913 * These macros can be used to access individual fields. 1914 */ 1915 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_1_quad_a_ctrl5[0]) >> 4) & 0x3ff) 1916 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_1_quad_a_ctrl5[0]=(((r).ana_lane_1_quad_a_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 1917 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_1_quad_a_ctrl5[0]) >> 1) & 0x1) 1918 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_1_quad_a_ctrl5[0]=(((r).ana_lane_1_quad_a_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 1919 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_1_quad_a_ctrl5[0]) & 0x1) 1920 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_1_quad_a_ctrl5[0]=(((r).ana_lane_1_quad_a_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 1921 1922 /* 1923 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL5. 1924 */ 1925 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r,_r._ana_lane_1_quad_a_ctrl5) 1926 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r,_r._ana_lane_1_quad_a_ctrl5) 1927 1928 /* 1929 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 1930 * will be redefined without the chip prefix for easier programming. 1931 * If multiple chips will be programmed in the same source file, then you should 1932 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 1933 * and refer to the fully qualified versions. 1934 */ 1935 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 1936 1937 #define ANA_LANE_1_QUAD_A_CTRL5r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r 1938 #define ANA_LANE_1_QUAD_A_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_SIZE 1939 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_t ANA_LANE_1_QUAD_A_CTRL5r_t; 1940 #define ANA_LANE_1_QUAD_A_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CLR 1941 #define ANA_LANE_1_QUAD_A_CTRL5r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_SET 1942 #define ANA_LANE_1_QUAD_A_CTRL5r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_GET 1943 #define ANA_LANE_1_QUAD_A_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_LA_GCTRLf_GET 1944 #define ANA_LANE_1_QUAD_A_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_LA_GCTRLf_SET 1945 #define ANA_LANE_1_QUAD_A_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_PDf_GET 1946 #define ANA_LANE_1_QUAD_A_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_PDf_SET 1947 #define ANA_LANE_1_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET 1948 #define ANA_LANE_1_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET 1949 #define READ_ANA_LANE_1_QUAD_A_CTRL5r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL5r 1950 #define WRITE_ANA_LANE_1_QUAD_A_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL5r 1951 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL5r 1952 1953 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 1954 /******************************************************************************* 1955 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL5r' 1956 */ 1957 1958 1959 1960 1961 /******************************************************************************* 1962 * CHIP: BCMI_HURACAN 1963 * REGISTER: ANA_LANE_1_QUAD_A_CTRL6 1964 * BLOCKS: ANA_LANE_1_QUAD_A 1965 * REGADDR: 0x8206 1966 * DEVAD: 1 1967 * DESC: control registers 0 1968 * RESETVAL: 0x0 (0) 1969 * ACCESS: R/W 1970 * FIELDS: 1971 * LA_DEGAIN 1972 * LA_DETUNE 1973 */ 1974 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r (0x00018206 | PHYMOD_REG_ACC_RAW) 1975 1976 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_SIZE 4 1977 1978 /* 1979 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL6. 1980 */ 1981 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_s { 1982 uint32_t v[1]; 1983 uint32_t ana_lane_1_quad_a_ctrl6[1]; 1984 uint32_t _ana_lane_1_quad_a_ctrl6; 1985 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_t; 1986 1987 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_CLR(r) (r).ana_lane_1_quad_a_ctrl6[0] = 0 1988 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_SET(r,d) (r).ana_lane_1_quad_a_ctrl6[0] = d 1989 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_GET(r) (r).ana_lane_1_quad_a_ctrl6[0] 1990 1991 /* 1992 * These macros can be used to access individual fields. 1993 */ 1994 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_1_quad_a_ctrl6[0]) >> 8) & 0xff) 1995 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_1_quad_a_ctrl6[0]=(((r).ana_lane_1_quad_a_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 1996 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_1_quad_a_ctrl6[0]) & 0x1f) 1997 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_1_quad_a_ctrl6[0]=(((r).ana_lane_1_quad_a_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 1998 1999 /* 2000 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL6. 2001 */ 2002 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r,_r._ana_lane_1_quad_a_ctrl6) 2003 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r,_r._ana_lane_1_quad_a_ctrl6) 2004 2005 /* 2006 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2007 * will be redefined without the chip prefix for easier programming. 2008 * If multiple chips will be programmed in the same source file, then you should 2009 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2010 * and refer to the fully qualified versions. 2011 */ 2012 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2013 2014 #define ANA_LANE_1_QUAD_A_CTRL6r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r 2015 #define ANA_LANE_1_QUAD_A_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_SIZE 2016 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_t ANA_LANE_1_QUAD_A_CTRL6r_t; 2017 #define ANA_LANE_1_QUAD_A_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_CLR 2018 #define ANA_LANE_1_QUAD_A_CTRL6r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_SET 2019 #define ANA_LANE_1_QUAD_A_CTRL6r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_GET 2020 #define ANA_LANE_1_QUAD_A_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DETUNEf_GET 2021 #define ANA_LANE_1_QUAD_A_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DETUNEf_SET 2022 #define ANA_LANE_1_QUAD_A_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DEGAINf_GET 2023 #define ANA_LANE_1_QUAD_A_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r_LA_DEGAINf_SET 2024 #define READ_ANA_LANE_1_QUAD_A_CTRL6r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL6r 2025 #define WRITE_ANA_LANE_1_QUAD_A_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL6r 2026 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL6r 2027 2028 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2029 /******************************************************************************* 2030 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL6r' 2031 */ 2032 2033 2034 2035 2036 /******************************************************************************* 2037 * CHIP: BCMI_HURACAN 2038 * REGISTER: ANA_LANE_1_QUAD_A_CTRL7 2039 * BLOCKS: ANA_LANE_1_QUAD_A 2040 * REGADDR: 0x8207 2041 * DEVAD: 1 2042 * DESC: control registers 0 2043 * RESETVAL: 0x0 (0) 2044 * ACCESS: R/W 2045 * FIELDS: 2046 * LA_LIN_MODE 2047 * RX_BIAS_FB_PDN 2048 */ 2049 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r (0x00018207 | PHYMOD_REG_ACC_RAW) 2050 2051 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_SIZE 4 2052 2053 /* 2054 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL7. 2055 */ 2056 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_s { 2057 uint32_t v[1]; 2058 uint32_t ana_lane_1_quad_a_ctrl7[1]; 2059 uint32_t _ana_lane_1_quad_a_ctrl7; 2060 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_t; 2061 2062 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_CLR(r) (r).ana_lane_1_quad_a_ctrl7[0] = 0 2063 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_SET(r,d) (r).ana_lane_1_quad_a_ctrl7[0] = d 2064 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_GET(r) (r).ana_lane_1_quad_a_ctrl7[0] 2065 2066 /* 2067 * These macros can be used to access individual fields. 2068 */ 2069 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_1_quad_a_ctrl7[0]) >> 8) & 0x1) 2070 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_1_quad_a_ctrl7[0]=(((r).ana_lane_1_quad_a_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 2071 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_1_quad_a_ctrl7[0]) & 0x1f) 2072 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_1_quad_a_ctrl7[0]=(((r).ana_lane_1_quad_a_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 2073 2074 /* 2075 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL7. 2076 */ 2077 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r,_r._ana_lane_1_quad_a_ctrl7) 2078 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r,_r._ana_lane_1_quad_a_ctrl7) 2079 2080 /* 2081 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2082 * will be redefined without the chip prefix for easier programming. 2083 * If multiple chips will be programmed in the same source file, then you should 2084 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2085 * and refer to the fully qualified versions. 2086 */ 2087 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2088 2089 #define ANA_LANE_1_QUAD_A_CTRL7r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r 2090 #define ANA_LANE_1_QUAD_A_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_SIZE 2091 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_t ANA_LANE_1_QUAD_A_CTRL7r_t; 2092 #define ANA_LANE_1_QUAD_A_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_CLR 2093 #define ANA_LANE_1_QUAD_A_CTRL7r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_SET 2094 #define ANA_LANE_1_QUAD_A_CTRL7r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_GET 2095 #define ANA_LANE_1_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET 2096 #define ANA_LANE_1_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET 2097 #define ANA_LANE_1_QUAD_A_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_LA_LIN_MODEf_GET 2098 #define ANA_LANE_1_QUAD_A_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r_LA_LIN_MODEf_SET 2099 #define READ_ANA_LANE_1_QUAD_A_CTRL7r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL7r 2100 #define WRITE_ANA_LANE_1_QUAD_A_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL7r 2101 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL7r 2102 2103 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2104 /******************************************************************************* 2105 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL7r' 2106 */ 2107 2108 2109 2110 2111 /******************************************************************************* 2112 * CHIP: BCMI_HURACAN 2113 * REGISTER: ANA_LANE_1_QUAD_A_CTRL8 2114 * BLOCKS: ANA_LANE_1_QUAD_A 2115 * REGADDR: 0x8208 2116 * DEVAD: 1 2117 * DESC: control registers 0 2118 * RESETVAL: 0x0 (0) 2119 * ACCESS: R/W 2120 * FIELDS: 2121 * LA_PD 2122 * LA_PD_IDLE 2123 * RXTX_RESERVED_FOR_99_95 2124 */ 2125 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r (0x00018208 | PHYMOD_REG_ACC_RAW) 2126 2127 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_SIZE 4 2128 2129 /* 2130 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL8. 2131 */ 2132 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_s { 2133 uint32_t v[1]; 2134 uint32_t ana_lane_1_quad_a_ctrl8[1]; 2135 uint32_t _ana_lane_1_quad_a_ctrl8; 2136 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_t; 2137 2138 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_CLR(r) (r).ana_lane_1_quad_a_ctrl8[0] = 0 2139 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_SET(r,d) (r).ana_lane_1_quad_a_ctrl8[0] = d 2140 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_GET(r) (r).ana_lane_1_quad_a_ctrl8[0] 2141 2142 /* 2143 * These macros can be used to access individual fields. 2144 */ 2145 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_1_quad_a_ctrl8[0]) >> 4) & 0x1f) 2146 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_1_quad_a_ctrl8[0]=(((r).ana_lane_1_quad_a_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 2147 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_1_quad_a_ctrl8[0]) >> 1) & 0x1) 2148 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_1_quad_a_ctrl8[0]=(((r).ana_lane_1_quad_a_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 2149 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_1_quad_a_ctrl8[0]) & 0x1) 2150 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_1_quad_a_ctrl8[0]=(((r).ana_lane_1_quad_a_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 2151 2152 /* 2153 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL8. 2154 */ 2155 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r,_r._ana_lane_1_quad_a_ctrl8) 2156 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r,_r._ana_lane_1_quad_a_ctrl8) 2157 2158 /* 2159 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2160 * will be redefined without the chip prefix for easier programming. 2161 * If multiple chips will be programmed in the same source file, then you should 2162 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2163 * and refer to the fully qualified versions. 2164 */ 2165 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2166 2167 #define ANA_LANE_1_QUAD_A_CTRL8r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r 2168 #define ANA_LANE_1_QUAD_A_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_SIZE 2169 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_t ANA_LANE_1_QUAD_A_CTRL8r_t; 2170 #define ANA_LANE_1_QUAD_A_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_CLR 2171 #define ANA_LANE_1_QUAD_A_CTRL8r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_SET 2172 #define ANA_LANE_1_QUAD_A_CTRL8r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_GET 2173 #define ANA_LANE_1_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 2174 #define ANA_LANE_1_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 2175 #define ANA_LANE_1_QUAD_A_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PD_IDLEf_GET 2176 #define ANA_LANE_1_QUAD_A_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PD_IDLEf_SET 2177 #define ANA_LANE_1_QUAD_A_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PDf_GET 2178 #define ANA_LANE_1_QUAD_A_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r_LA_PDf_SET 2179 #define READ_ANA_LANE_1_QUAD_A_CTRL8r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL8r 2180 #define WRITE_ANA_LANE_1_QUAD_A_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL8r 2181 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL8r 2182 2183 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2184 /******************************************************************************* 2185 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL8r' 2186 */ 2187 2188 2189 2190 2191 /******************************************************************************* 2192 * CHIP: BCMI_HURACAN 2193 * REGISTER: ANA_LANE_1_QUAD_A_CTRL9 2194 * BLOCKS: ANA_LANE_1_QUAD_A 2195 * REGADDR: 0x8209 2196 * DEVAD: 1 2197 * DESC: control registers 0 2198 * RESETVAL: 0x0 (0) 2199 * ACCESS: R/W 2200 * FIELDS: 2201 * DRV_POST1 2202 * DLINE_SWING_1 2203 * DLINE_SWING_2 2204 * DLINE_DELAY_CTRL 2205 */ 2206 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r (0x00018209 | PHYMOD_REG_ACC_RAW) 2207 2208 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_SIZE 4 2209 2210 /* 2211 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL9. 2212 */ 2213 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_s { 2214 uint32_t v[1]; 2215 uint32_t ana_lane_1_quad_a_ctrl9[1]; 2216 uint32_t _ana_lane_1_quad_a_ctrl9; 2217 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_t; 2218 2219 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_CLR(r) (r).ana_lane_1_quad_a_ctrl9[0] = 0 2220 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_SET(r,d) (r).ana_lane_1_quad_a_ctrl9[0] = d 2221 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_GET(r) (r).ana_lane_1_quad_a_ctrl9[0] 2222 2223 /* 2224 * These macros can be used to access individual fields. 2225 */ 2226 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_1_quad_a_ctrl9[0]) >> 12) & 0x7) 2227 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_1_quad_a_ctrl9[0]=(((r).ana_lane_1_quad_a_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 2228 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_1_quad_a_ctrl9[0]) >> 8) & 0x3) 2229 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_1_quad_a_ctrl9[0]=(((r).ana_lane_1_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 2230 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_1_quad_a_ctrl9[0]) >> 4) & 0x3) 2231 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_1_quad_a_ctrl9[0]=(((r).ana_lane_1_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 2232 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_1_quad_a_ctrl9[0]) & 0xf) 2233 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_1_quad_a_ctrl9[0]=(((r).ana_lane_1_quad_a_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 2234 2235 /* 2236 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL9. 2237 */ 2238 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r,_r._ana_lane_1_quad_a_ctrl9) 2239 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r,_r._ana_lane_1_quad_a_ctrl9) 2240 2241 /* 2242 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2243 * will be redefined without the chip prefix for easier programming. 2244 * If multiple chips will be programmed in the same source file, then you should 2245 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2246 * and refer to the fully qualified versions. 2247 */ 2248 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2249 2250 #define ANA_LANE_1_QUAD_A_CTRL9r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r 2251 #define ANA_LANE_1_QUAD_A_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_SIZE 2252 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_t ANA_LANE_1_QUAD_A_CTRL9r_t; 2253 #define ANA_LANE_1_QUAD_A_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_CLR 2254 #define ANA_LANE_1_QUAD_A_CTRL9r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_SET 2255 #define ANA_LANE_1_QUAD_A_CTRL9r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_GET 2256 #define ANA_LANE_1_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET 2257 #define ANA_LANE_1_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET 2258 #define ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_2f_GET 2259 #define ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_2f_SET 2260 #define ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_1f_GET 2261 #define ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DLINE_SWING_1f_SET 2262 #define ANA_LANE_1_QUAD_A_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DRV_POST1f_GET 2263 #define ANA_LANE_1_QUAD_A_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r_DRV_POST1f_SET 2264 #define READ_ANA_LANE_1_QUAD_A_CTRL9r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL9r 2265 #define WRITE_ANA_LANE_1_QUAD_A_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL9r 2266 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL9r 2267 2268 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2269 /******************************************************************************* 2270 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL9r' 2271 */ 2272 2273 2274 2275 2276 /******************************************************************************* 2277 * CHIP: BCMI_HURACAN 2278 * REGISTER: ANA_LANE_1_QUAD_A_CTRL10 2279 * BLOCKS: ANA_LANE_1_QUAD_A 2280 * REGADDR: 0x820a 2281 * DEVAD: 1 2282 * DESC: control registers 0 2283 * RESETVAL: 0x0 (0) 2284 * ACCESS: R/W 2285 * FIELDS: 2286 * DRV_PWD 2287 * DLINE_PWD 2288 * DRV_VBSEL 2289 * DRV_MAIN 2290 * DRV_MAIN_PU 2291 */ 2292 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r (0x0001820a | PHYMOD_REG_ACC_RAW) 2293 2294 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_SIZE 4 2295 2296 /* 2297 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL10. 2298 */ 2299 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_s { 2300 uint32_t v[1]; 2301 uint32_t ana_lane_1_quad_a_ctrl10[1]; 2302 uint32_t _ana_lane_1_quad_a_ctrl10; 2303 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_t; 2304 2305 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_CLR(r) (r).ana_lane_1_quad_a_ctrl10[0] = 0 2306 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_SET(r,d) (r).ana_lane_1_quad_a_ctrl10[0] = d 2307 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_GET(r) (r).ana_lane_1_quad_a_ctrl10[0] 2308 2309 /* 2310 * These macros can be used to access individual fields. 2311 */ 2312 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_1_quad_a_ctrl10[0]) >> 12) & 0xf) 2313 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_1_quad_a_ctrl10[0]=(((r).ana_lane_1_quad_a_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 2314 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_1_quad_a_ctrl10[0]) >> 4) & 0x3f) 2315 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_1_quad_a_ctrl10[0]=(((r).ana_lane_1_quad_a_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 2316 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_1_quad_a_ctrl10[0]) >> 2) & 0x1) 2317 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_1_quad_a_ctrl10[0]=(((r).ana_lane_1_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 2318 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_1_quad_a_ctrl10[0]) >> 1) & 0x1) 2319 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_1_quad_a_ctrl10[0]=(((r).ana_lane_1_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 2320 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_1_quad_a_ctrl10[0]) & 0x1) 2321 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_1_quad_a_ctrl10[0]=(((r).ana_lane_1_quad_a_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 2322 2323 /* 2324 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL10. 2325 */ 2326 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r,_r._ana_lane_1_quad_a_ctrl10) 2327 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r,_r._ana_lane_1_quad_a_ctrl10) 2328 2329 /* 2330 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2331 * will be redefined without the chip prefix for easier programming. 2332 * If multiple chips will be programmed in the same source file, then you should 2333 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2334 * and refer to the fully qualified versions. 2335 */ 2336 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2337 2338 #define ANA_LANE_1_QUAD_A_CTRL10r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r 2339 #define ANA_LANE_1_QUAD_A_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_SIZE 2340 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_t ANA_LANE_1_QUAD_A_CTRL10r_t; 2341 #define ANA_LANE_1_QUAD_A_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_CLR 2342 #define ANA_LANE_1_QUAD_A_CTRL10r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_SET 2343 #define ANA_LANE_1_QUAD_A_CTRL10r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_GET 2344 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET 2345 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET 2346 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAINf_GET 2347 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_MAINf_SET 2348 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_VBSELf_GET 2349 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_VBSELf_SET 2350 #define ANA_LANE_1_QUAD_A_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DLINE_PWDf_GET 2351 #define ANA_LANE_1_QUAD_A_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DLINE_PWDf_SET 2352 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_PWDf_GET 2353 #define ANA_LANE_1_QUAD_A_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r_DRV_PWDf_SET 2354 #define READ_ANA_LANE_1_QUAD_A_CTRL10r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL10r 2355 #define WRITE_ANA_LANE_1_QUAD_A_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL10r 2356 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL10r 2357 2358 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2359 /******************************************************************************* 2360 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL10r' 2361 */ 2362 2363 2364 2365 2366 /******************************************************************************* 2367 * CHIP: BCMI_HURACAN 2368 * REGISTER: ANA_LANE_1_QUAD_A_CTRL11 2369 * BLOCKS: ANA_LANE_1_QUAD_A 2370 * REGADDR: 0x820b 2371 * DEVAD: 1 2372 * DESC: control registers 0 2373 * RESETVAL: 0x0 (0) 2374 * ACCESS: R/W 2375 * FIELDS: 2376 * RXTX_RESERVED_FOR_143_128 2377 */ 2378 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r (0x0001820b | PHYMOD_REG_ACC_RAW) 2379 2380 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_SIZE 4 2381 2382 /* 2383 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL11. 2384 */ 2385 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_s { 2386 uint32_t v[1]; 2387 uint32_t ana_lane_1_quad_a_ctrl11[1]; 2388 uint32_t _ana_lane_1_quad_a_ctrl11; 2389 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_t; 2390 2391 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_CLR(r) (r).ana_lane_1_quad_a_ctrl11[0] = 0 2392 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_SET(r,d) (r).ana_lane_1_quad_a_ctrl11[0] = d 2393 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_GET(r) (r).ana_lane_1_quad_a_ctrl11[0] 2394 2395 /* 2396 * These macros can be used to access individual fields. 2397 */ 2398 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_1_quad_a_ctrl11[0]) & 0xffff) 2399 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_1_quad_a_ctrl11[0]=(((r).ana_lane_1_quad_a_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 2400 2401 /* 2402 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL11. 2403 */ 2404 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r,_r._ana_lane_1_quad_a_ctrl11) 2405 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r,_r._ana_lane_1_quad_a_ctrl11) 2406 2407 /* 2408 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2409 * will be redefined without the chip prefix for easier programming. 2410 * If multiple chips will be programmed in the same source file, then you should 2411 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2412 * and refer to the fully qualified versions. 2413 */ 2414 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2415 2416 #define ANA_LANE_1_QUAD_A_CTRL11r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r 2417 #define ANA_LANE_1_QUAD_A_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_SIZE 2418 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_t ANA_LANE_1_QUAD_A_CTRL11r_t; 2419 #define ANA_LANE_1_QUAD_A_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_CLR 2420 #define ANA_LANE_1_QUAD_A_CTRL11r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_SET 2421 #define ANA_LANE_1_QUAD_A_CTRL11r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_GET 2422 #define ANA_LANE_1_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 2423 #define ANA_LANE_1_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 2424 #define READ_ANA_LANE_1_QUAD_A_CTRL11r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL11r 2425 #define WRITE_ANA_LANE_1_QUAD_A_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL11r 2426 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL11r 2427 2428 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2429 /******************************************************************************* 2430 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL11r' 2431 */ 2432 2433 2434 2435 2436 /******************************************************************************* 2437 * CHIP: BCMI_HURACAN 2438 * REGISTER: ANA_LANE_1_QUAD_A_CTRL12 2439 * BLOCKS: ANA_LANE_1_QUAD_A 2440 * REGADDR: 0x820c 2441 * DEVAD: 1 2442 * DESC: control registers 0 2443 * RESETVAL: 0x0 (0) 2444 * ACCESS: R/W 2445 * FIELDS: 2446 * LA_RESCAL_FRC_VAL 2447 * LA_RESCAL_FRC 2448 * DRV_RESCAL_FRC_VAL 2449 * DRV_RESCAL_FRC 2450 */ 2451 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r (0x0001820c | PHYMOD_REG_ACC_RAW) 2452 2453 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_SIZE 4 2454 2455 /* 2456 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL12. 2457 */ 2458 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_s { 2459 uint32_t v[1]; 2460 uint32_t ana_lane_1_quad_a_ctrl12[1]; 2461 uint32_t _ana_lane_1_quad_a_ctrl12; 2462 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_t; 2463 2464 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_CLR(r) (r).ana_lane_1_quad_a_ctrl12[0] = 0 2465 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_SET(r,d) (r).ana_lane_1_quad_a_ctrl12[0] = d 2466 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_GET(r) (r).ana_lane_1_quad_a_ctrl12[0] 2467 2468 /* 2469 * These macros can be used to access individual fields. 2470 */ 2471 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_a_ctrl12[0]) >> 12) & 0x1) 2472 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_a_ctrl12[0]=(((r).ana_lane_1_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 2473 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_a_ctrl12[0]) >> 8) & 0xf) 2474 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_a_ctrl12[0]=(((r).ana_lane_1_quad_a_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 2475 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_a_ctrl12[0]) >> 4) & 0x1) 2476 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_a_ctrl12[0]=(((r).ana_lane_1_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 2477 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_a_ctrl12[0]) & 0xf) 2478 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_a_ctrl12[0]=(((r).ana_lane_1_quad_a_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 2479 2480 /* 2481 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL12. 2482 */ 2483 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r,_r._ana_lane_1_quad_a_ctrl12) 2484 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r,_r._ana_lane_1_quad_a_ctrl12) 2485 2486 /* 2487 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2488 * will be redefined without the chip prefix for easier programming. 2489 * If multiple chips will be programmed in the same source file, then you should 2490 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2491 * and refer to the fully qualified versions. 2492 */ 2493 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2494 2495 #define ANA_LANE_1_QUAD_A_CTRL12r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r 2496 #define ANA_LANE_1_QUAD_A_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_SIZE 2497 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_t ANA_LANE_1_QUAD_A_CTRL12r_t; 2498 #define ANA_LANE_1_QUAD_A_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_CLR 2499 #define ANA_LANE_1_QUAD_A_CTRL12r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_SET 2500 #define ANA_LANE_1_QUAD_A_CTRL12r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_GET 2501 #define ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET 2502 #define ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET 2503 #define ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET 2504 #define ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET 2505 #define ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET 2506 #define ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET 2507 #define ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET 2508 #define ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET 2509 #define READ_ANA_LANE_1_QUAD_A_CTRL12r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL12r 2510 #define WRITE_ANA_LANE_1_QUAD_A_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL12r 2511 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL12r 2512 2513 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2514 /******************************************************************************* 2515 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL12r' 2516 */ 2517 2518 2519 2520 2521 /******************************************************************************* 2522 * CHIP: BCMI_HURACAN 2523 * REGISTER: ANA_LANE_1_QUAD_A_CTRL13 2524 * BLOCKS: ANA_LANE_1_QUAD_A 2525 * REGADDR: 0x820d 2526 * DEVAD: 1 2527 * DESC: control registers 0 2528 * RESETVAL: 0x0 (0) 2529 * ACCESS: R/W 2530 * FIELDS: 2531 * CTLE_RESCAL_FRC_VAL 2532 * CTLE_RESCAL_FRC 2533 */ 2534 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r (0x0001820d | PHYMOD_REG_ACC_RAW) 2535 2536 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_SIZE 4 2537 2538 /* 2539 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL13. 2540 */ 2541 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_s { 2542 uint32_t v[1]; 2543 uint32_t ana_lane_1_quad_a_ctrl13[1]; 2544 uint32_t _ana_lane_1_quad_a_ctrl13; 2545 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_t; 2546 2547 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CLR(r) (r).ana_lane_1_quad_a_ctrl13[0] = 0 2548 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_SET(r,d) (r).ana_lane_1_quad_a_ctrl13[0] = d 2549 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_GET(r) (r).ana_lane_1_quad_a_ctrl13[0] 2550 2551 /* 2552 * These macros can be used to access individual fields. 2553 */ 2554 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_a_ctrl13[0]) >> 4) & 0x1) 2555 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_a_ctrl13[0]=(((r).ana_lane_1_quad_a_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 2556 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_a_ctrl13[0]) & 0xf) 2557 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_a_ctrl13[0]=(((r).ana_lane_1_quad_a_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 2558 2559 /* 2560 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL13. 2561 */ 2562 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r,_r._ana_lane_1_quad_a_ctrl13) 2563 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r,_r._ana_lane_1_quad_a_ctrl13) 2564 2565 /* 2566 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2567 * will be redefined without the chip prefix for easier programming. 2568 * If multiple chips will be programmed in the same source file, then you should 2569 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2570 * and refer to the fully qualified versions. 2571 */ 2572 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2573 2574 #define ANA_LANE_1_QUAD_A_CTRL13r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r 2575 #define ANA_LANE_1_QUAD_A_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_SIZE 2576 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_t ANA_LANE_1_QUAD_A_CTRL13r_t; 2577 #define ANA_LANE_1_QUAD_A_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CLR 2578 #define ANA_LANE_1_QUAD_A_CTRL13r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_SET 2579 #define ANA_LANE_1_QUAD_A_CTRL13r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_GET 2580 #define ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET 2581 #define ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET 2582 #define ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 2583 #define ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 2584 #define READ_ANA_LANE_1_QUAD_A_CTRL13r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL13r 2585 #define WRITE_ANA_LANE_1_QUAD_A_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL13r 2586 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL13r 2587 2588 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2589 /******************************************************************************* 2590 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL13r' 2591 */ 2592 2593 2594 2595 2596 /******************************************************************************* 2597 * CHIP: BCMI_HURACAN 2598 * REGISTER: ANA_LANE_1_QUAD_A_CTRL14 2599 * BLOCKS: ANA_LANE_1_QUAD_A 2600 * REGADDR: 0x820e 2601 * DEVAD: 1 2602 * DESC: control registers 0 2603 * RESETVAL: 0x0 (0) 2604 * ACCESS: R/W 2605 * FIELDS: 2606 * TX_IDLE_FRC_VAL 2607 * TX_IDLE_FRC 2608 * RXSD_IDLE_OVRD 2609 */ 2610 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r (0x0001820e | PHYMOD_REG_ACC_RAW) 2611 2612 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_SIZE 4 2613 2614 /* 2615 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL14. 2616 */ 2617 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_s { 2618 uint32_t v[1]; 2619 uint32_t ana_lane_1_quad_a_ctrl14[1]; 2620 uint32_t _ana_lane_1_quad_a_ctrl14; 2621 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_t; 2622 2623 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_CLR(r) (r).ana_lane_1_quad_a_ctrl14[0] = 0 2624 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_SET(r,d) (r).ana_lane_1_quad_a_ctrl14[0] = d 2625 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_GET(r) (r).ana_lane_1_quad_a_ctrl14[0] 2626 2627 /* 2628 * These macros can be used to access individual fields. 2629 */ 2630 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_1_quad_a_ctrl14[0]) >> 4) & 0x1) 2631 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_1_quad_a_ctrl14[0]=(((r).ana_lane_1_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 2632 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_1_quad_a_ctrl14[0]) >> 1) & 0x1) 2633 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_1_quad_a_ctrl14[0]=(((r).ana_lane_1_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 2634 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_1_quad_a_ctrl14[0]) & 0x1) 2635 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_a_ctrl14[0]=(((r).ana_lane_1_quad_a_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 2636 2637 /* 2638 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL14. 2639 */ 2640 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r,_r._ana_lane_1_quad_a_ctrl14) 2641 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r,_r._ana_lane_1_quad_a_ctrl14) 2642 2643 /* 2644 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2645 * will be redefined without the chip prefix for easier programming. 2646 * If multiple chips will be programmed in the same source file, then you should 2647 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2648 * and refer to the fully qualified versions. 2649 */ 2650 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2651 2652 #define ANA_LANE_1_QUAD_A_CTRL14r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r 2653 #define ANA_LANE_1_QUAD_A_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_SIZE 2654 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_t ANA_LANE_1_QUAD_A_CTRL14r_t; 2655 #define ANA_LANE_1_QUAD_A_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_CLR 2656 #define ANA_LANE_1_QUAD_A_CTRL14r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_SET 2657 #define ANA_LANE_1_QUAD_A_CTRL14r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_GET 2658 #define ANA_LANE_1_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET 2659 #define ANA_LANE_1_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET 2660 #define ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET 2661 #define ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET 2662 #define ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET 2663 #define ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET 2664 #define READ_ANA_LANE_1_QUAD_A_CTRL14r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL14r 2665 #define WRITE_ANA_LANE_1_QUAD_A_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL14r 2666 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL14r 2667 2668 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2669 /******************************************************************************* 2670 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL14r' 2671 */ 2672 2673 2674 2675 2676 /******************************************************************************* 2677 * CHIP: BCMI_HURACAN 2678 * REGISTER: ANA_LANE_1_QUAD_A_CTRL15 2679 * BLOCKS: ANA_LANE_1_QUAD_A 2680 * REGADDR: 0x820f 2681 * DEVAD: 1 2682 * DESC: sigdet filter settings 0 2683 * RESETVAL: 0x0 (0) 2684 * ACCESS: R/W 2685 * FIELDS: 2686 * SIGDET_DIS 2687 * SIGDET_1US_EN 2688 * SIGDET_FRC_VAL 2689 * SIGDET_FRC 2690 * HOLD_LOS_COUNT 2691 * HOLD_SD_COUNT 2692 */ 2693 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r (0x0001820f | PHYMOD_REG_ACC_RAW) 2694 2695 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIZE 4 2696 2697 /* 2698 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL15. 2699 */ 2700 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_s { 2701 uint32_t v[1]; 2702 uint32_t ana_lane_1_quad_a_ctrl15[1]; 2703 uint32_t _ana_lane_1_quad_a_ctrl15; 2704 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_t; 2705 2706 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_CLR(r) (r).ana_lane_1_quad_a_ctrl15[0] = 0 2707 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SET(r,d) (r).ana_lane_1_quad_a_ctrl15[0] = d 2708 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_GET(r) (r).ana_lane_1_quad_a_ctrl15[0] 2709 2710 /* 2711 * These macros can be used to access individual fields. 2712 */ 2713 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_a_ctrl15[0]) >> 8) & 0x7) 2714 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_a_ctrl15[0]=(((r).ana_lane_1_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 2715 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_1_quad_a_ctrl15[0]) >> 4) & 0x7) 2716 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_a_ctrl15[0]=(((r).ana_lane_1_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 2717 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_1_quad_a_ctrl15[0]) >> 3) & 0x1) 2718 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_1_quad_a_ctrl15[0]=(((r).ana_lane_1_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 2719 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_a_ctrl15[0]) >> 2) & 0x1) 2720 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_a_ctrl15[0]=(((r).ana_lane_1_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 2721 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_1_quad_a_ctrl15[0]) >> 1) & 0x1) 2722 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_1_quad_a_ctrl15[0]=(((r).ana_lane_1_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 2723 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_1_quad_a_ctrl15[0]) & 0x1) 2724 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_1_quad_a_ctrl15[0]=(((r).ana_lane_1_quad_a_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 2725 2726 /* 2727 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL15. 2728 */ 2729 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r,_r._ana_lane_1_quad_a_ctrl15) 2730 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r,_r._ana_lane_1_quad_a_ctrl15) 2731 2732 /* 2733 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2734 * will be redefined without the chip prefix for easier programming. 2735 * If multiple chips will be programmed in the same source file, then you should 2736 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2737 * and refer to the fully qualified versions. 2738 */ 2739 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2740 2741 #define ANA_LANE_1_QUAD_A_CTRL15r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r 2742 #define ANA_LANE_1_QUAD_A_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIZE 2743 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_t ANA_LANE_1_QUAD_A_CTRL15r_t; 2744 #define ANA_LANE_1_QUAD_A_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_CLR 2745 #define ANA_LANE_1_QUAD_A_CTRL15r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SET 2746 #define ANA_LANE_1_QUAD_A_CTRL15r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_GET 2747 #define ANA_LANE_1_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET 2748 #define ANA_LANE_1_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET 2749 #define ANA_LANE_1_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET 2750 #define ANA_LANE_1_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET 2751 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRCf_GET 2752 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRCf_SET 2753 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET 2754 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET 2755 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET 2756 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET 2757 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_DISf_GET 2758 #define ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r_SIGDET_DISf_SET 2759 #define READ_ANA_LANE_1_QUAD_A_CTRL15r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL15r 2760 #define WRITE_ANA_LANE_1_QUAD_A_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL15r 2761 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL15r 2762 2763 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2764 /******************************************************************************* 2765 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL15r' 2766 */ 2767 2768 2769 2770 2771 /******************************************************************************* 2772 * CHIP: BCMI_HURACAN 2773 * REGISTER: ANA_LANE_1_QUAD_A_CTRL16 2774 * BLOCKS: ANA_LANE_1_QUAD_A 2775 * REGADDR: 0x8210 2776 * DEVAD: 1 2777 * DESC: sigdet filter settings 1 2778 * RESETVAL: 0x0 (0) 2779 * ACCESS: R/W 2780 * FIELDS: 2781 * LOS_COUNT 2782 * SD_COUNT 2783 */ 2784 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r (0x00018210 | PHYMOD_REG_ACC_RAW) 2785 2786 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SIZE 4 2787 2788 /* 2789 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_CTRL16. 2790 */ 2791 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_s { 2792 uint32_t v[1]; 2793 uint32_t ana_lane_1_quad_a_ctrl16[1]; 2794 uint32_t _ana_lane_1_quad_a_ctrl16; 2795 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_t; 2796 2797 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_CLR(r) (r).ana_lane_1_quad_a_ctrl16[0] = 0 2798 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SET(r,d) (r).ana_lane_1_quad_a_ctrl16[0] = d 2799 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_GET(r) (r).ana_lane_1_quad_a_ctrl16[0] 2800 2801 /* 2802 * These macros can be used to access individual fields. 2803 */ 2804 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_a_ctrl16[0]) >> 8) & 0x1f) 2805 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_a_ctrl16[0]=(((r).ana_lane_1_quad_a_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 2806 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_1_quad_a_ctrl16[0]) & 0x1f) 2807 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_a_ctrl16[0]=(((r).ana_lane_1_quad_a_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 2808 2809 /* 2810 * These macros can be used to access ANA_LANE_1_QUAD_A_CTRL16. 2811 */ 2812 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r,_r._ana_lane_1_quad_a_ctrl16) 2813 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r,_r._ana_lane_1_quad_a_ctrl16) 2814 2815 /* 2816 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2817 * will be redefined without the chip prefix for easier programming. 2818 * If multiple chips will be programmed in the same source file, then you should 2819 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2820 * and refer to the fully qualified versions. 2821 */ 2822 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2823 2824 #define ANA_LANE_1_QUAD_A_CTRL16r BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r 2825 #define ANA_LANE_1_QUAD_A_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SIZE 2826 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_t ANA_LANE_1_QUAD_A_CTRL16r_t; 2827 #define ANA_LANE_1_QUAD_A_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_CLR 2828 #define ANA_LANE_1_QUAD_A_CTRL16r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SET 2829 #define ANA_LANE_1_QUAD_A_CTRL16r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_GET 2830 #define ANA_LANE_1_QUAD_A_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SD_COUNTf_GET 2831 #define ANA_LANE_1_QUAD_A_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_SD_COUNTf_SET 2832 #define ANA_LANE_1_QUAD_A_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_LOS_COUNTf_GET 2833 #define ANA_LANE_1_QUAD_A_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r_LOS_COUNTf_SET 2834 #define READ_ANA_LANE_1_QUAD_A_CTRL16r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_CTRL16r 2835 #define WRITE_ANA_LANE_1_QUAD_A_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_CTRL16r 2836 #define MODIFY_ANA_LANE_1_QUAD_A_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_CTRL16r 2837 2838 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2839 /******************************************************************************* 2840 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_CTRL16r' 2841 */ 2842 2843 2844 2845 2846 /******************************************************************************* 2847 * CHIP: BCMI_HURACAN 2848 * REGISTER: ANA_LANE_1_QUAD_A_STATUS0 2849 * BLOCKS: ANA_LANE_1_QUAD_A 2850 * REGADDR: 0x8220 2851 * DEVAD: 1 2852 * DESC: status registers 0 2853 * RESETVAL: 0x0 (0) 2854 * ACCESS: R/W 2855 * FIELDS: 2856 * O_RX_SIGDET 2857 * DG_RX_SIGDET 2858 */ 2859 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r (0x00018220 | PHYMOD_REG_ACC_RAW) 2860 2861 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_SIZE 4 2862 2863 /* 2864 * This structure should be used to declare and program ANA_LANE_1_QUAD_A_STATUS0. 2865 */ 2866 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_s { 2867 uint32_t v[1]; 2868 uint32_t ana_lane_1_quad_a_status0[1]; 2869 uint32_t _ana_lane_1_quad_a_status0; 2870 } BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_t; 2871 2872 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_CLR(r) (r).ana_lane_1_quad_a_status0[0] = 0 2873 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_SET(r,d) (r).ana_lane_1_quad_a_status0[0] = d 2874 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_GET(r) (r).ana_lane_1_quad_a_status0[0] 2875 2876 /* 2877 * These macros can be used to access individual fields. 2878 */ 2879 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_1_quad_a_status0[0]) >> 1) & 0x1) 2880 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_a_status0[0]=(((r).ana_lane_1_quad_a_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 2881 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_1_quad_a_status0[0]) & 0x1) 2882 #define BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_a_status0[0]=(((r).ana_lane_1_quad_a_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 2883 2884 /* 2885 * These macros can be used to access ANA_LANE_1_QUAD_A_STATUS0. 2886 */ 2887 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r,_r._ana_lane_1_quad_a_status0) 2888 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r,_r._ana_lane_1_quad_a_status0) 2889 2890 /* 2891 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2892 * will be redefined without the chip prefix for easier programming. 2893 * If multiple chips will be programmed in the same source file, then you should 2894 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2895 * and refer to the fully qualified versions. 2896 */ 2897 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2898 2899 #define ANA_LANE_1_QUAD_A_STATUS0r BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r 2900 #define ANA_LANE_1_QUAD_A_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_SIZE 2901 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_t ANA_LANE_1_QUAD_A_STATUS0r_t; 2902 #define ANA_LANE_1_QUAD_A_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_CLR 2903 #define ANA_LANE_1_QUAD_A_STATUS0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_SET 2904 #define ANA_LANE_1_QUAD_A_STATUS0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_GET 2905 #define ANA_LANE_1_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET 2906 #define ANA_LANE_1_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET 2907 #define ANA_LANE_1_QUAD_A_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_O_RX_SIGDETf_GET 2908 #define ANA_LANE_1_QUAD_A_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r_O_RX_SIGDETf_SET 2909 #define READ_ANA_LANE_1_QUAD_A_STATUS0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_A_STATUS0r 2910 #define WRITE_ANA_LANE_1_QUAD_A_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_A_STATUS0r 2911 #define MODIFY_ANA_LANE_1_QUAD_A_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_A_STATUS0r 2912 2913 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 2914 /******************************************************************************* 2915 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_A_STATUS0r' 2916 */ 2917 2918 2919 2920 2921 /******************************************************************************* 2922 * CHIP: BCMI_HURACAN 2923 * REGISTER: ANA_LANE_2_QUAD_A_CTRL0 2924 * BLOCKS: ANA_LANE_2_QUAD_A 2925 * REGADDR: 0x8400 2926 * DEVAD: 1 2927 * DESC: control registers 0 2928 * RESETVAL: 0x0 (0) 2929 * ACCESS: R/W 2930 * FIELDS: 2931 * RXTX_PWRDN 2932 * RX_SIGDET_BYPASS 2933 * RX_SIGDET_PWRDN 2934 * RX_SIGDECT_12GMODE 2935 * DC_COUPLE 2936 */ 2937 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r (0x00018400 | PHYMOD_REG_ACC_RAW) 2938 2939 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_SIZE 4 2940 2941 /* 2942 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL0. 2943 */ 2944 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_s { 2945 uint32_t v[1]; 2946 uint32_t ana_lane_2_quad_a_ctrl0[1]; 2947 uint32_t _ana_lane_2_quad_a_ctrl0; 2948 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_t; 2949 2950 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_CLR(r) (r).ana_lane_2_quad_a_ctrl0[0] = 0 2951 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_SET(r,d) (r).ana_lane_2_quad_a_ctrl0[0] = d 2952 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_GET(r) (r).ana_lane_2_quad_a_ctrl0[0] 2953 2954 /* 2955 * These macros can be used to access individual fields. 2956 */ 2957 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_2_quad_a_ctrl0[0]) >> 4) & 0x1) 2958 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_2_quad_a_ctrl0[0]=(((r).ana_lane_2_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 2959 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_2_quad_a_ctrl0[0]) >> 3) & 0x1) 2960 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_2_quad_a_ctrl0[0]=(((r).ana_lane_2_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 2961 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_2_quad_a_ctrl0[0]) >> 2) & 0x1) 2962 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_2_quad_a_ctrl0[0]=(((r).ana_lane_2_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 2963 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_2_quad_a_ctrl0[0]) >> 1) & 0x1) 2964 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_2_quad_a_ctrl0[0]=(((r).ana_lane_2_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 2965 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_2_quad_a_ctrl0[0]) & 0x1) 2966 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_2_quad_a_ctrl0[0]=(((r).ana_lane_2_quad_a_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 2967 2968 /* 2969 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL0. 2970 */ 2971 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r,_r._ana_lane_2_quad_a_ctrl0) 2972 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r,_r._ana_lane_2_quad_a_ctrl0) 2973 2974 /* 2975 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 2976 * will be redefined without the chip prefix for easier programming. 2977 * If multiple chips will be programmed in the same source file, then you should 2978 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 2979 * and refer to the fully qualified versions. 2980 */ 2981 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 2982 2983 #define ANA_LANE_2_QUAD_A_CTRL0r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r 2984 #define ANA_LANE_2_QUAD_A_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_SIZE 2985 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_t ANA_LANE_2_QUAD_A_CTRL0r_t; 2986 #define ANA_LANE_2_QUAD_A_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_CLR 2987 #define ANA_LANE_2_QUAD_A_CTRL0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_SET 2988 #define ANA_LANE_2_QUAD_A_CTRL0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_GET 2989 #define ANA_LANE_2_QUAD_A_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_DC_COUPLEf_GET 2990 #define ANA_LANE_2_QUAD_A_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_DC_COUPLEf_SET 2991 #define ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET 2992 #define ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET 2993 #define ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET 2994 #define ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET 2995 #define ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET 2996 #define ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET 2997 #define ANA_LANE_2_QUAD_A_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RXTX_PWRDNf_GET 2998 #define ANA_LANE_2_QUAD_A_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r_RXTX_PWRDNf_SET 2999 #define READ_ANA_LANE_2_QUAD_A_CTRL0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL0r 3000 #define WRITE_ANA_LANE_2_QUAD_A_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL0r 3001 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL0r 3002 3003 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3004 /******************************************************************************* 3005 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL0r' 3006 */ 3007 3008 3009 3010 3011 /******************************************************************************* 3012 * CHIP: BCMI_HURACAN 3013 * REGISTER: ANA_LANE_2_QUAD_A_CTRL1 3014 * BLOCKS: ANA_LANE_2_QUAD_A 3015 * REGADDR: 0x8401 3016 * DEVAD: 1 3017 * DESC: control registers 0 3018 * RESETVAL: 0x0 (0) 3019 * ACCESS: R/W 3020 * FIELDS: 3021 * RX_SIGDET_THRESHOLD 3022 * REF_OCL 3023 * OCL_PWRDN 3024 * OCL_DISABLE_LOOP 3025 * RXTX_RESERVED_FOR_15_12 3026 */ 3027 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r (0x00018401 | PHYMOD_REG_ACC_RAW) 3028 3029 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_SIZE 4 3030 3031 /* 3032 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL1. 3033 */ 3034 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_s { 3035 uint32_t v[1]; 3036 uint32_t ana_lane_2_quad_a_ctrl1[1]; 3037 uint32_t _ana_lane_2_quad_a_ctrl1; 3038 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_t; 3039 3040 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_CLR(r) (r).ana_lane_2_quad_a_ctrl1[0] = 0 3041 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_SET(r,d) (r).ana_lane_2_quad_a_ctrl1[0] = d 3042 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_GET(r) (r).ana_lane_2_quad_a_ctrl1[0] 3043 3044 /* 3045 * These macros can be used to access individual fields. 3046 */ 3047 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_2_quad_a_ctrl1[0]) >> 12) & 0xf) 3048 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_2_quad_a_ctrl1[0]=(((r).ana_lane_2_quad_a_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 3049 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_2_quad_a_ctrl1[0]) >> 9) & 0x1) 3050 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_2_quad_a_ctrl1[0]=(((r).ana_lane_2_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 3051 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_2_quad_a_ctrl1[0]) >> 8) & 0x1) 3052 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_2_quad_a_ctrl1[0]=(((r).ana_lane_2_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 3053 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_2_quad_a_ctrl1[0]) >> 4) & 0x3) 3054 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_2_quad_a_ctrl1[0]=(((r).ana_lane_2_quad_a_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 3055 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_2_quad_a_ctrl1[0]) & 0x7) 3056 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_2_quad_a_ctrl1[0]=(((r).ana_lane_2_quad_a_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 3057 3058 /* 3059 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL1. 3060 */ 3061 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r,_r._ana_lane_2_quad_a_ctrl1) 3062 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r,_r._ana_lane_2_quad_a_ctrl1) 3063 3064 /* 3065 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3066 * will be redefined without the chip prefix for easier programming. 3067 * If multiple chips will be programmed in the same source file, then you should 3068 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3069 * and refer to the fully qualified versions. 3070 */ 3071 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3072 3073 #define ANA_LANE_2_QUAD_A_CTRL1r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r 3074 #define ANA_LANE_2_QUAD_A_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_SIZE 3075 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_t ANA_LANE_2_QUAD_A_CTRL1r_t; 3076 #define ANA_LANE_2_QUAD_A_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_CLR 3077 #define ANA_LANE_2_QUAD_A_CTRL1r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_SET 3078 #define ANA_LANE_2_QUAD_A_CTRL1r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_GET 3079 #define ANA_LANE_2_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 3080 #define ANA_LANE_2_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 3081 #define ANA_LANE_2_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET 3082 #define ANA_LANE_2_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET 3083 #define ANA_LANE_2_QUAD_A_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_PWRDNf_GET 3084 #define ANA_LANE_2_QUAD_A_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_OCL_PWRDNf_SET 3085 #define ANA_LANE_2_QUAD_A_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_REF_OCLf_GET 3086 #define ANA_LANE_2_QUAD_A_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_REF_OCLf_SET 3087 #define ANA_LANE_2_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET 3088 #define ANA_LANE_2_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET 3089 #define READ_ANA_LANE_2_QUAD_A_CTRL1r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL1r 3090 #define WRITE_ANA_LANE_2_QUAD_A_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL1r 3091 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL1r 3092 3093 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3094 /******************************************************************************* 3095 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL1r' 3096 */ 3097 3098 3099 3100 3101 /******************************************************************************* 3102 * CHIP: BCMI_HURACAN 3103 * REGISTER: ANA_LANE_2_QUAD_A_CTRL2 3104 * BLOCKS: ANA_LANE_2_QUAD_A 3105 * REGADDR: 0x8402 3106 * DEVAD: 1 3107 * DESC: control registers 0 3108 * RESETVAL: 0x0 (0) 3109 * ACCESS: R/W 3110 * FIELDS: 3111 * CTLE_ENB_NEGIMP 3112 * CTLE_ENB_NEGCAP 3113 */ 3114 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r (0x00018402 | PHYMOD_REG_ACC_RAW) 3115 3116 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_SIZE 4 3117 3118 /* 3119 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL2. 3120 */ 3121 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_s { 3122 uint32_t v[1]; 3123 uint32_t ana_lane_2_quad_a_ctrl2[1]; 3124 uint32_t _ana_lane_2_quad_a_ctrl2; 3125 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_t; 3126 3127 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CLR(r) (r).ana_lane_2_quad_a_ctrl2[0] = 0 3128 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_SET(r,d) (r).ana_lane_2_quad_a_ctrl2[0] = d 3129 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_GET(r) (r).ana_lane_2_quad_a_ctrl2[0] 3130 3131 /* 3132 * These macros can be used to access individual fields. 3133 */ 3134 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_2_quad_a_ctrl2[0]) >> 8) & 0x7f) 3135 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_2_quad_a_ctrl2[0]=(((r).ana_lane_2_quad_a_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 3136 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_2_quad_a_ctrl2[0]) & 0x7f) 3137 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_2_quad_a_ctrl2[0]=(((r).ana_lane_2_quad_a_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 3138 3139 /* 3140 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL2. 3141 */ 3142 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r,_r._ana_lane_2_quad_a_ctrl2) 3143 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r,_r._ana_lane_2_quad_a_ctrl2) 3144 3145 /* 3146 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3147 * will be redefined without the chip prefix for easier programming. 3148 * If multiple chips will be programmed in the same source file, then you should 3149 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3150 * and refer to the fully qualified versions. 3151 */ 3152 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3153 3154 #define ANA_LANE_2_QUAD_A_CTRL2r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r 3155 #define ANA_LANE_2_QUAD_A_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_SIZE 3156 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_t ANA_LANE_2_QUAD_A_CTRL2r_t; 3157 #define ANA_LANE_2_QUAD_A_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CLR 3158 #define ANA_LANE_2_QUAD_A_CTRL2r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_SET 3159 #define ANA_LANE_2_QUAD_A_CTRL2r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_GET 3160 #define ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET 3161 #define ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET 3162 #define ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET 3163 #define ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET 3164 #define READ_ANA_LANE_2_QUAD_A_CTRL2r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL2r 3165 #define WRITE_ANA_LANE_2_QUAD_A_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL2r 3166 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL2r 3167 3168 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3169 /******************************************************************************* 3170 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL2r' 3171 */ 3172 3173 3174 3175 3176 /******************************************************************************* 3177 * CHIP: BCMI_HURACAN 3178 * REGISTER: ANA_LANE_2_QUAD_A_CTRL3 3179 * BLOCKS: ANA_LANE_2_QUAD_A 3180 * REGADDR: 0x8403 3181 * DEVAD: 1 3182 * DESC: control registers 0 3183 * RESETVAL: 0x0 (0) 3184 * ACCESS: R/W 3185 * FIELDS: 3186 * CTLE_EN_NEGRES 3187 * CTLE_EQSEL 3188 */ 3189 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r (0x00018403 | PHYMOD_REG_ACC_RAW) 3190 3191 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_SIZE 4 3192 3193 /* 3194 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL3. 3195 */ 3196 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_s { 3197 uint32_t v[1]; 3198 uint32_t ana_lane_2_quad_a_ctrl3[1]; 3199 uint32_t _ana_lane_2_quad_a_ctrl3; 3200 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_t; 3201 3202 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CLR(r) (r).ana_lane_2_quad_a_ctrl3[0] = 0 3203 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_SET(r,d) (r).ana_lane_2_quad_a_ctrl3[0] = d 3204 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_GET(r) (r).ana_lane_2_quad_a_ctrl3[0] 3205 3206 /* 3207 * These macros can be used to access individual fields. 3208 */ 3209 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_2_quad_a_ctrl3[0]) >> 8) & 0xff) 3210 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_2_quad_a_ctrl3[0]=(((r).ana_lane_2_quad_a_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 3211 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_2_quad_a_ctrl3[0]) & 0x7f) 3212 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_2_quad_a_ctrl3[0]=(((r).ana_lane_2_quad_a_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 3213 3214 /* 3215 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL3. 3216 */ 3217 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r,_r._ana_lane_2_quad_a_ctrl3) 3218 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r,_r._ana_lane_2_quad_a_ctrl3) 3219 3220 /* 3221 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3222 * will be redefined without the chip prefix for easier programming. 3223 * If multiple chips will be programmed in the same source file, then you should 3224 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3225 * and refer to the fully qualified versions. 3226 */ 3227 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3228 3229 #define ANA_LANE_2_QUAD_A_CTRL3r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r 3230 #define ANA_LANE_2_QUAD_A_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_SIZE 3231 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_t ANA_LANE_2_QUAD_A_CTRL3r_t; 3232 #define ANA_LANE_2_QUAD_A_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CLR 3233 #define ANA_LANE_2_QUAD_A_CTRL3r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_SET 3234 #define ANA_LANE_2_QUAD_A_CTRL3r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_GET 3235 #define ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EQSELf_GET 3236 #define ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EQSELf_SET 3237 #define ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET 3238 #define ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET 3239 #define READ_ANA_LANE_2_QUAD_A_CTRL3r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL3r 3240 #define WRITE_ANA_LANE_2_QUAD_A_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL3r 3241 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL3r 3242 3243 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3244 /******************************************************************************* 3245 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL3r' 3246 */ 3247 3248 3249 3250 3251 /******************************************************************************* 3252 * CHIP: BCMI_HURACAN 3253 * REGISTER: ANA_LANE_2_QUAD_A_CTRL4 3254 * BLOCKS: ANA_LANE_2_QUAD_A 3255 * REGADDR: 0x8404 3256 * DEVAD: 1 3257 * DESC: control registers 0 3258 * RESETVAL: 0x0 (0) 3259 * ACCESS: R/W 3260 * FIELDS: 3261 * CTLE_LZEN 3262 * RXTX_RESERVED_FOR_59_52 3263 */ 3264 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r (0x00018404 | PHYMOD_REG_ACC_RAW) 3265 3266 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_SIZE 4 3267 3268 /* 3269 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL4. 3270 */ 3271 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_s { 3272 uint32_t v[1]; 3273 uint32_t ana_lane_2_quad_a_ctrl4[1]; 3274 uint32_t _ana_lane_2_quad_a_ctrl4; 3275 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_t; 3276 3277 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_CLR(r) (r).ana_lane_2_quad_a_ctrl4[0] = 0 3278 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_SET(r,d) (r).ana_lane_2_quad_a_ctrl4[0] = d 3279 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_GET(r) (r).ana_lane_2_quad_a_ctrl4[0] 3280 3281 /* 3282 * These macros can be used to access individual fields. 3283 */ 3284 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_2_quad_a_ctrl4[0]) >> 4) & 0xff) 3285 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_2_quad_a_ctrl4[0]=(((r).ana_lane_2_quad_a_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 3286 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_2_quad_a_ctrl4[0]) & 0x1) 3287 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_2_quad_a_ctrl4[0]=(((r).ana_lane_2_quad_a_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 3288 3289 /* 3290 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL4. 3291 */ 3292 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r,_r._ana_lane_2_quad_a_ctrl4) 3293 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r,_r._ana_lane_2_quad_a_ctrl4) 3294 3295 /* 3296 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3297 * will be redefined without the chip prefix for easier programming. 3298 * If multiple chips will be programmed in the same source file, then you should 3299 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3300 * and refer to the fully qualified versions. 3301 */ 3302 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3303 3304 #define ANA_LANE_2_QUAD_A_CTRL4r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r 3305 #define ANA_LANE_2_QUAD_A_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_SIZE 3306 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_t ANA_LANE_2_QUAD_A_CTRL4r_t; 3307 #define ANA_LANE_2_QUAD_A_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_CLR 3308 #define ANA_LANE_2_QUAD_A_CTRL4r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_SET 3309 #define ANA_LANE_2_QUAD_A_CTRL4r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_GET 3310 #define ANA_LANE_2_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 3311 #define ANA_LANE_2_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 3312 #define ANA_LANE_2_QUAD_A_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_CTLE_LZENf_GET 3313 #define ANA_LANE_2_QUAD_A_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r_CTLE_LZENf_SET 3314 #define READ_ANA_LANE_2_QUAD_A_CTRL4r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL4r 3315 #define WRITE_ANA_LANE_2_QUAD_A_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL4r 3316 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL4r 3317 3318 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3319 /******************************************************************************* 3320 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL4r' 3321 */ 3322 3323 3324 3325 3326 /******************************************************************************* 3327 * CHIP: BCMI_HURACAN 3328 * REGISTER: ANA_LANE_2_QUAD_A_CTRL5 3329 * BLOCKS: ANA_LANE_2_QUAD_A 3330 * REGADDR: 0x8405 3331 * DEVAD: 1 3332 * DESC: control registers 0 3333 * RESETVAL: 0x0 (0) 3334 * ACCESS: R/W 3335 * FIELDS: 3336 * CTLE_LOPEAKING 3337 * CTLE_PD 3338 * LA_GCTRL 3339 */ 3340 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r (0x00018405 | PHYMOD_REG_ACC_RAW) 3341 3342 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_SIZE 4 3343 3344 /* 3345 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL5. 3346 */ 3347 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_s { 3348 uint32_t v[1]; 3349 uint32_t ana_lane_2_quad_a_ctrl5[1]; 3350 uint32_t _ana_lane_2_quad_a_ctrl5; 3351 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_t; 3352 3353 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CLR(r) (r).ana_lane_2_quad_a_ctrl5[0] = 0 3354 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_SET(r,d) (r).ana_lane_2_quad_a_ctrl5[0] = d 3355 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_GET(r) (r).ana_lane_2_quad_a_ctrl5[0] 3356 3357 /* 3358 * These macros can be used to access individual fields. 3359 */ 3360 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_2_quad_a_ctrl5[0]) >> 4) & 0x3ff) 3361 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_2_quad_a_ctrl5[0]=(((r).ana_lane_2_quad_a_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 3362 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_2_quad_a_ctrl5[0]) >> 1) & 0x1) 3363 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_2_quad_a_ctrl5[0]=(((r).ana_lane_2_quad_a_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 3364 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_2_quad_a_ctrl5[0]) & 0x1) 3365 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_2_quad_a_ctrl5[0]=(((r).ana_lane_2_quad_a_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 3366 3367 /* 3368 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL5. 3369 */ 3370 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r,_r._ana_lane_2_quad_a_ctrl5) 3371 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r,_r._ana_lane_2_quad_a_ctrl5) 3372 3373 /* 3374 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3375 * will be redefined without the chip prefix for easier programming. 3376 * If multiple chips will be programmed in the same source file, then you should 3377 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3378 * and refer to the fully qualified versions. 3379 */ 3380 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3381 3382 #define ANA_LANE_2_QUAD_A_CTRL5r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r 3383 #define ANA_LANE_2_QUAD_A_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_SIZE 3384 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_t ANA_LANE_2_QUAD_A_CTRL5r_t; 3385 #define ANA_LANE_2_QUAD_A_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CLR 3386 #define ANA_LANE_2_QUAD_A_CTRL5r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_SET 3387 #define ANA_LANE_2_QUAD_A_CTRL5r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_GET 3388 #define ANA_LANE_2_QUAD_A_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_LA_GCTRLf_GET 3389 #define ANA_LANE_2_QUAD_A_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_LA_GCTRLf_SET 3390 #define ANA_LANE_2_QUAD_A_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_PDf_GET 3391 #define ANA_LANE_2_QUAD_A_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_PDf_SET 3392 #define ANA_LANE_2_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET 3393 #define ANA_LANE_2_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET 3394 #define READ_ANA_LANE_2_QUAD_A_CTRL5r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL5r 3395 #define WRITE_ANA_LANE_2_QUAD_A_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL5r 3396 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL5r 3397 3398 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3399 /******************************************************************************* 3400 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL5r' 3401 */ 3402 3403 3404 3405 3406 /******************************************************************************* 3407 * CHIP: BCMI_HURACAN 3408 * REGISTER: ANA_LANE_2_QUAD_A_CTRL6 3409 * BLOCKS: ANA_LANE_2_QUAD_A 3410 * REGADDR: 0x8406 3411 * DEVAD: 1 3412 * DESC: control registers 0 3413 * RESETVAL: 0x0 (0) 3414 * ACCESS: R/W 3415 * FIELDS: 3416 * LA_DEGAIN 3417 * LA_DETUNE 3418 */ 3419 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r (0x00018406 | PHYMOD_REG_ACC_RAW) 3420 3421 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_SIZE 4 3422 3423 /* 3424 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL6. 3425 */ 3426 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_s { 3427 uint32_t v[1]; 3428 uint32_t ana_lane_2_quad_a_ctrl6[1]; 3429 uint32_t _ana_lane_2_quad_a_ctrl6; 3430 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_t; 3431 3432 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_CLR(r) (r).ana_lane_2_quad_a_ctrl6[0] = 0 3433 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_SET(r,d) (r).ana_lane_2_quad_a_ctrl6[0] = d 3434 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_GET(r) (r).ana_lane_2_quad_a_ctrl6[0] 3435 3436 /* 3437 * These macros can be used to access individual fields. 3438 */ 3439 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_2_quad_a_ctrl6[0]) >> 8) & 0xff) 3440 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_2_quad_a_ctrl6[0]=(((r).ana_lane_2_quad_a_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 3441 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_2_quad_a_ctrl6[0]) & 0x1f) 3442 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_2_quad_a_ctrl6[0]=(((r).ana_lane_2_quad_a_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 3443 3444 /* 3445 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL6. 3446 */ 3447 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r,_r._ana_lane_2_quad_a_ctrl6) 3448 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r,_r._ana_lane_2_quad_a_ctrl6) 3449 3450 /* 3451 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3452 * will be redefined without the chip prefix for easier programming. 3453 * If multiple chips will be programmed in the same source file, then you should 3454 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3455 * and refer to the fully qualified versions. 3456 */ 3457 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3458 3459 #define ANA_LANE_2_QUAD_A_CTRL6r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r 3460 #define ANA_LANE_2_QUAD_A_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_SIZE 3461 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_t ANA_LANE_2_QUAD_A_CTRL6r_t; 3462 #define ANA_LANE_2_QUAD_A_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_CLR 3463 #define ANA_LANE_2_QUAD_A_CTRL6r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_SET 3464 #define ANA_LANE_2_QUAD_A_CTRL6r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_GET 3465 #define ANA_LANE_2_QUAD_A_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DETUNEf_GET 3466 #define ANA_LANE_2_QUAD_A_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DETUNEf_SET 3467 #define ANA_LANE_2_QUAD_A_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DEGAINf_GET 3468 #define ANA_LANE_2_QUAD_A_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r_LA_DEGAINf_SET 3469 #define READ_ANA_LANE_2_QUAD_A_CTRL6r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL6r 3470 #define WRITE_ANA_LANE_2_QUAD_A_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL6r 3471 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL6r 3472 3473 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3474 /******************************************************************************* 3475 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL6r' 3476 */ 3477 3478 3479 3480 3481 /******************************************************************************* 3482 * CHIP: BCMI_HURACAN 3483 * REGISTER: ANA_LANE_2_QUAD_A_CTRL7 3484 * BLOCKS: ANA_LANE_2_QUAD_A 3485 * REGADDR: 0x8407 3486 * DEVAD: 1 3487 * DESC: control registers 0 3488 * RESETVAL: 0x0 (0) 3489 * ACCESS: R/W 3490 * FIELDS: 3491 * LA_LIN_MODE 3492 * RX_BIAS_FB_PDN 3493 */ 3494 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r (0x00018407 | PHYMOD_REG_ACC_RAW) 3495 3496 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_SIZE 4 3497 3498 /* 3499 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL7. 3500 */ 3501 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_s { 3502 uint32_t v[1]; 3503 uint32_t ana_lane_2_quad_a_ctrl7[1]; 3504 uint32_t _ana_lane_2_quad_a_ctrl7; 3505 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_t; 3506 3507 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_CLR(r) (r).ana_lane_2_quad_a_ctrl7[0] = 0 3508 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_SET(r,d) (r).ana_lane_2_quad_a_ctrl7[0] = d 3509 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_GET(r) (r).ana_lane_2_quad_a_ctrl7[0] 3510 3511 /* 3512 * These macros can be used to access individual fields. 3513 */ 3514 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_2_quad_a_ctrl7[0]) >> 8) & 0x1) 3515 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_2_quad_a_ctrl7[0]=(((r).ana_lane_2_quad_a_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 3516 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_2_quad_a_ctrl7[0]) & 0x1f) 3517 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_2_quad_a_ctrl7[0]=(((r).ana_lane_2_quad_a_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 3518 3519 /* 3520 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL7. 3521 */ 3522 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r,_r._ana_lane_2_quad_a_ctrl7) 3523 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r,_r._ana_lane_2_quad_a_ctrl7) 3524 3525 /* 3526 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3527 * will be redefined without the chip prefix for easier programming. 3528 * If multiple chips will be programmed in the same source file, then you should 3529 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3530 * and refer to the fully qualified versions. 3531 */ 3532 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3533 3534 #define ANA_LANE_2_QUAD_A_CTRL7r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r 3535 #define ANA_LANE_2_QUAD_A_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_SIZE 3536 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_t ANA_LANE_2_QUAD_A_CTRL7r_t; 3537 #define ANA_LANE_2_QUAD_A_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_CLR 3538 #define ANA_LANE_2_QUAD_A_CTRL7r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_SET 3539 #define ANA_LANE_2_QUAD_A_CTRL7r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_GET 3540 #define ANA_LANE_2_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET 3541 #define ANA_LANE_2_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET 3542 #define ANA_LANE_2_QUAD_A_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_LA_LIN_MODEf_GET 3543 #define ANA_LANE_2_QUAD_A_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r_LA_LIN_MODEf_SET 3544 #define READ_ANA_LANE_2_QUAD_A_CTRL7r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL7r 3545 #define WRITE_ANA_LANE_2_QUAD_A_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL7r 3546 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL7r 3547 3548 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3549 /******************************************************************************* 3550 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL7r' 3551 */ 3552 3553 3554 3555 3556 /******************************************************************************* 3557 * CHIP: BCMI_HURACAN 3558 * REGISTER: ANA_LANE_2_QUAD_A_CTRL8 3559 * BLOCKS: ANA_LANE_2_QUAD_A 3560 * REGADDR: 0x8408 3561 * DEVAD: 1 3562 * DESC: control registers 0 3563 * RESETVAL: 0x0 (0) 3564 * ACCESS: R/W 3565 * FIELDS: 3566 * LA_PD 3567 * LA_PD_IDLE 3568 * RXTX_RESERVED_FOR_99_95 3569 */ 3570 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r (0x00018408 | PHYMOD_REG_ACC_RAW) 3571 3572 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_SIZE 4 3573 3574 /* 3575 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL8. 3576 */ 3577 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_s { 3578 uint32_t v[1]; 3579 uint32_t ana_lane_2_quad_a_ctrl8[1]; 3580 uint32_t _ana_lane_2_quad_a_ctrl8; 3581 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_t; 3582 3583 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_CLR(r) (r).ana_lane_2_quad_a_ctrl8[0] = 0 3584 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_SET(r,d) (r).ana_lane_2_quad_a_ctrl8[0] = d 3585 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_GET(r) (r).ana_lane_2_quad_a_ctrl8[0] 3586 3587 /* 3588 * These macros can be used to access individual fields. 3589 */ 3590 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_2_quad_a_ctrl8[0]) >> 4) & 0x1f) 3591 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_2_quad_a_ctrl8[0]=(((r).ana_lane_2_quad_a_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 3592 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_2_quad_a_ctrl8[0]) >> 1) & 0x1) 3593 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_2_quad_a_ctrl8[0]=(((r).ana_lane_2_quad_a_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 3594 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_2_quad_a_ctrl8[0]) & 0x1) 3595 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_2_quad_a_ctrl8[0]=(((r).ana_lane_2_quad_a_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 3596 3597 /* 3598 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL8. 3599 */ 3600 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r,_r._ana_lane_2_quad_a_ctrl8) 3601 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r,_r._ana_lane_2_quad_a_ctrl8) 3602 3603 /* 3604 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3605 * will be redefined without the chip prefix for easier programming. 3606 * If multiple chips will be programmed in the same source file, then you should 3607 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3608 * and refer to the fully qualified versions. 3609 */ 3610 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3611 3612 #define ANA_LANE_2_QUAD_A_CTRL8r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r 3613 #define ANA_LANE_2_QUAD_A_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_SIZE 3614 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_t ANA_LANE_2_QUAD_A_CTRL8r_t; 3615 #define ANA_LANE_2_QUAD_A_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_CLR 3616 #define ANA_LANE_2_QUAD_A_CTRL8r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_SET 3617 #define ANA_LANE_2_QUAD_A_CTRL8r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_GET 3618 #define ANA_LANE_2_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 3619 #define ANA_LANE_2_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 3620 #define ANA_LANE_2_QUAD_A_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PD_IDLEf_GET 3621 #define ANA_LANE_2_QUAD_A_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PD_IDLEf_SET 3622 #define ANA_LANE_2_QUAD_A_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PDf_GET 3623 #define ANA_LANE_2_QUAD_A_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r_LA_PDf_SET 3624 #define READ_ANA_LANE_2_QUAD_A_CTRL8r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL8r 3625 #define WRITE_ANA_LANE_2_QUAD_A_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL8r 3626 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL8r 3627 3628 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3629 /******************************************************************************* 3630 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL8r' 3631 */ 3632 3633 3634 3635 3636 /******************************************************************************* 3637 * CHIP: BCMI_HURACAN 3638 * REGISTER: ANA_LANE_2_QUAD_A_CTRL9 3639 * BLOCKS: ANA_LANE_2_QUAD_A 3640 * REGADDR: 0x8409 3641 * DEVAD: 1 3642 * DESC: control registers 0 3643 * RESETVAL: 0x0 (0) 3644 * ACCESS: R/W 3645 * FIELDS: 3646 * DRV_POST1 3647 * DLINE_SWING_1 3648 * DLINE_SWING_2 3649 * DLINE_DELAY_CTRL 3650 */ 3651 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r (0x00018409 | PHYMOD_REG_ACC_RAW) 3652 3653 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_SIZE 4 3654 3655 /* 3656 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL9. 3657 */ 3658 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_s { 3659 uint32_t v[1]; 3660 uint32_t ana_lane_2_quad_a_ctrl9[1]; 3661 uint32_t _ana_lane_2_quad_a_ctrl9; 3662 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_t; 3663 3664 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_CLR(r) (r).ana_lane_2_quad_a_ctrl9[0] = 0 3665 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_SET(r,d) (r).ana_lane_2_quad_a_ctrl9[0] = d 3666 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_GET(r) (r).ana_lane_2_quad_a_ctrl9[0] 3667 3668 /* 3669 * These macros can be used to access individual fields. 3670 */ 3671 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_2_quad_a_ctrl9[0]) >> 12) & 0x7) 3672 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_2_quad_a_ctrl9[0]=(((r).ana_lane_2_quad_a_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 3673 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_2_quad_a_ctrl9[0]) >> 8) & 0x3) 3674 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_2_quad_a_ctrl9[0]=(((r).ana_lane_2_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 3675 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_2_quad_a_ctrl9[0]) >> 4) & 0x3) 3676 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_2_quad_a_ctrl9[0]=(((r).ana_lane_2_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 3677 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_2_quad_a_ctrl9[0]) & 0xf) 3678 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_2_quad_a_ctrl9[0]=(((r).ana_lane_2_quad_a_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 3679 3680 /* 3681 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL9. 3682 */ 3683 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r,_r._ana_lane_2_quad_a_ctrl9) 3684 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r,_r._ana_lane_2_quad_a_ctrl9) 3685 3686 /* 3687 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3688 * will be redefined without the chip prefix for easier programming. 3689 * If multiple chips will be programmed in the same source file, then you should 3690 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3691 * and refer to the fully qualified versions. 3692 */ 3693 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3694 3695 #define ANA_LANE_2_QUAD_A_CTRL9r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r 3696 #define ANA_LANE_2_QUAD_A_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_SIZE 3697 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_t ANA_LANE_2_QUAD_A_CTRL9r_t; 3698 #define ANA_LANE_2_QUAD_A_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_CLR 3699 #define ANA_LANE_2_QUAD_A_CTRL9r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_SET 3700 #define ANA_LANE_2_QUAD_A_CTRL9r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_GET 3701 #define ANA_LANE_2_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET 3702 #define ANA_LANE_2_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET 3703 #define ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_2f_GET 3704 #define ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_2f_SET 3705 #define ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_1f_GET 3706 #define ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DLINE_SWING_1f_SET 3707 #define ANA_LANE_2_QUAD_A_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DRV_POST1f_GET 3708 #define ANA_LANE_2_QUAD_A_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r_DRV_POST1f_SET 3709 #define READ_ANA_LANE_2_QUAD_A_CTRL9r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL9r 3710 #define WRITE_ANA_LANE_2_QUAD_A_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL9r 3711 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL9r 3712 3713 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3714 /******************************************************************************* 3715 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL9r' 3716 */ 3717 3718 3719 3720 3721 /******************************************************************************* 3722 * CHIP: BCMI_HURACAN 3723 * REGISTER: ANA_LANE_2_QUAD_A_CTRL10 3724 * BLOCKS: ANA_LANE_2_QUAD_A 3725 * REGADDR: 0x840a 3726 * DEVAD: 1 3727 * DESC: control registers 0 3728 * RESETVAL: 0x0 (0) 3729 * ACCESS: R/W 3730 * FIELDS: 3731 * DRV_PWD 3732 * DLINE_PWD 3733 * DRV_VBSEL 3734 * DRV_MAIN 3735 * DRV_MAIN_PU 3736 */ 3737 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r (0x0001840a | PHYMOD_REG_ACC_RAW) 3738 3739 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_SIZE 4 3740 3741 /* 3742 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL10. 3743 */ 3744 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_s { 3745 uint32_t v[1]; 3746 uint32_t ana_lane_2_quad_a_ctrl10[1]; 3747 uint32_t _ana_lane_2_quad_a_ctrl10; 3748 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_t; 3749 3750 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_CLR(r) (r).ana_lane_2_quad_a_ctrl10[0] = 0 3751 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_SET(r,d) (r).ana_lane_2_quad_a_ctrl10[0] = d 3752 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_GET(r) (r).ana_lane_2_quad_a_ctrl10[0] 3753 3754 /* 3755 * These macros can be used to access individual fields. 3756 */ 3757 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_2_quad_a_ctrl10[0]) >> 12) & 0xf) 3758 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_2_quad_a_ctrl10[0]=(((r).ana_lane_2_quad_a_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 3759 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_2_quad_a_ctrl10[0]) >> 4) & 0x3f) 3760 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_2_quad_a_ctrl10[0]=(((r).ana_lane_2_quad_a_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 3761 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_2_quad_a_ctrl10[0]) >> 2) & 0x1) 3762 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_2_quad_a_ctrl10[0]=(((r).ana_lane_2_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 3763 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_2_quad_a_ctrl10[0]) >> 1) & 0x1) 3764 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_2_quad_a_ctrl10[0]=(((r).ana_lane_2_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 3765 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_2_quad_a_ctrl10[0]) & 0x1) 3766 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_2_quad_a_ctrl10[0]=(((r).ana_lane_2_quad_a_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 3767 3768 /* 3769 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL10. 3770 */ 3771 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r,_r._ana_lane_2_quad_a_ctrl10) 3772 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r,_r._ana_lane_2_quad_a_ctrl10) 3773 3774 /* 3775 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3776 * will be redefined without the chip prefix for easier programming. 3777 * If multiple chips will be programmed in the same source file, then you should 3778 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3779 * and refer to the fully qualified versions. 3780 */ 3781 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3782 3783 #define ANA_LANE_2_QUAD_A_CTRL10r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r 3784 #define ANA_LANE_2_QUAD_A_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_SIZE 3785 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_t ANA_LANE_2_QUAD_A_CTRL10r_t; 3786 #define ANA_LANE_2_QUAD_A_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_CLR 3787 #define ANA_LANE_2_QUAD_A_CTRL10r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_SET 3788 #define ANA_LANE_2_QUAD_A_CTRL10r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_GET 3789 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET 3790 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET 3791 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAINf_GET 3792 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_MAINf_SET 3793 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_VBSELf_GET 3794 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_VBSELf_SET 3795 #define ANA_LANE_2_QUAD_A_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DLINE_PWDf_GET 3796 #define ANA_LANE_2_QUAD_A_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DLINE_PWDf_SET 3797 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_PWDf_GET 3798 #define ANA_LANE_2_QUAD_A_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r_DRV_PWDf_SET 3799 #define READ_ANA_LANE_2_QUAD_A_CTRL10r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL10r 3800 #define WRITE_ANA_LANE_2_QUAD_A_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL10r 3801 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL10r 3802 3803 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3804 /******************************************************************************* 3805 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL10r' 3806 */ 3807 3808 3809 3810 3811 /******************************************************************************* 3812 * CHIP: BCMI_HURACAN 3813 * REGISTER: ANA_LANE_2_QUAD_A_CTRL11 3814 * BLOCKS: ANA_LANE_2_QUAD_A 3815 * REGADDR: 0x840b 3816 * DEVAD: 1 3817 * DESC: control registers 0 3818 * RESETVAL: 0x0 (0) 3819 * ACCESS: R/W 3820 * FIELDS: 3821 * RXTX_RESERVED_FOR_143_128 3822 */ 3823 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r (0x0001840b | PHYMOD_REG_ACC_RAW) 3824 3825 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_SIZE 4 3826 3827 /* 3828 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL11. 3829 */ 3830 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_s { 3831 uint32_t v[1]; 3832 uint32_t ana_lane_2_quad_a_ctrl11[1]; 3833 uint32_t _ana_lane_2_quad_a_ctrl11; 3834 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_t; 3835 3836 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_CLR(r) (r).ana_lane_2_quad_a_ctrl11[0] = 0 3837 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_SET(r,d) (r).ana_lane_2_quad_a_ctrl11[0] = d 3838 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_GET(r) (r).ana_lane_2_quad_a_ctrl11[0] 3839 3840 /* 3841 * These macros can be used to access individual fields. 3842 */ 3843 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_2_quad_a_ctrl11[0]) & 0xffff) 3844 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_2_quad_a_ctrl11[0]=(((r).ana_lane_2_quad_a_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 3845 3846 /* 3847 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL11. 3848 */ 3849 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r,_r._ana_lane_2_quad_a_ctrl11) 3850 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r,_r._ana_lane_2_quad_a_ctrl11) 3851 3852 /* 3853 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3854 * will be redefined without the chip prefix for easier programming. 3855 * If multiple chips will be programmed in the same source file, then you should 3856 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3857 * and refer to the fully qualified versions. 3858 */ 3859 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3860 3861 #define ANA_LANE_2_QUAD_A_CTRL11r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r 3862 #define ANA_LANE_2_QUAD_A_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_SIZE 3863 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_t ANA_LANE_2_QUAD_A_CTRL11r_t; 3864 #define ANA_LANE_2_QUAD_A_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_CLR 3865 #define ANA_LANE_2_QUAD_A_CTRL11r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_SET 3866 #define ANA_LANE_2_QUAD_A_CTRL11r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_GET 3867 #define ANA_LANE_2_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 3868 #define ANA_LANE_2_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 3869 #define READ_ANA_LANE_2_QUAD_A_CTRL11r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL11r 3870 #define WRITE_ANA_LANE_2_QUAD_A_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL11r 3871 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL11r 3872 3873 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3874 /******************************************************************************* 3875 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL11r' 3876 */ 3877 3878 3879 3880 3881 /******************************************************************************* 3882 * CHIP: BCMI_HURACAN 3883 * REGISTER: ANA_LANE_2_QUAD_A_CTRL12 3884 * BLOCKS: ANA_LANE_2_QUAD_A 3885 * REGADDR: 0x840c 3886 * DEVAD: 1 3887 * DESC: control registers 0 3888 * RESETVAL: 0x0 (0) 3889 * ACCESS: R/W 3890 * FIELDS: 3891 * LA_RESCAL_FRC_VAL 3892 * LA_RESCAL_FRC 3893 * DRV_RESCAL_FRC_VAL 3894 * DRV_RESCAL_FRC 3895 */ 3896 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r (0x0001840c | PHYMOD_REG_ACC_RAW) 3897 3898 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_SIZE 4 3899 3900 /* 3901 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL12. 3902 */ 3903 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_s { 3904 uint32_t v[1]; 3905 uint32_t ana_lane_2_quad_a_ctrl12[1]; 3906 uint32_t _ana_lane_2_quad_a_ctrl12; 3907 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_t; 3908 3909 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_CLR(r) (r).ana_lane_2_quad_a_ctrl12[0] = 0 3910 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_SET(r,d) (r).ana_lane_2_quad_a_ctrl12[0] = d 3911 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_GET(r) (r).ana_lane_2_quad_a_ctrl12[0] 3912 3913 /* 3914 * These macros can be used to access individual fields. 3915 */ 3916 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_a_ctrl12[0]) >> 12) & 0x1) 3917 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_a_ctrl12[0]=(((r).ana_lane_2_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 3918 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_a_ctrl12[0]) >> 8) & 0xf) 3919 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_a_ctrl12[0]=(((r).ana_lane_2_quad_a_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 3920 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_a_ctrl12[0]) >> 4) & 0x1) 3921 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_a_ctrl12[0]=(((r).ana_lane_2_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 3922 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_a_ctrl12[0]) & 0xf) 3923 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_a_ctrl12[0]=(((r).ana_lane_2_quad_a_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 3924 3925 /* 3926 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL12. 3927 */ 3928 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r,_r._ana_lane_2_quad_a_ctrl12) 3929 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r,_r._ana_lane_2_quad_a_ctrl12) 3930 3931 /* 3932 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 3933 * will be redefined without the chip prefix for easier programming. 3934 * If multiple chips will be programmed in the same source file, then you should 3935 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 3936 * and refer to the fully qualified versions. 3937 */ 3938 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 3939 3940 #define ANA_LANE_2_QUAD_A_CTRL12r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r 3941 #define ANA_LANE_2_QUAD_A_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_SIZE 3942 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_t ANA_LANE_2_QUAD_A_CTRL12r_t; 3943 #define ANA_LANE_2_QUAD_A_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_CLR 3944 #define ANA_LANE_2_QUAD_A_CTRL12r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_SET 3945 #define ANA_LANE_2_QUAD_A_CTRL12r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_GET 3946 #define ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET 3947 #define ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET 3948 #define ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET 3949 #define ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET 3950 #define ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET 3951 #define ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET 3952 #define ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET 3953 #define ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET 3954 #define READ_ANA_LANE_2_QUAD_A_CTRL12r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL12r 3955 #define WRITE_ANA_LANE_2_QUAD_A_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL12r 3956 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL12r 3957 3958 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 3959 /******************************************************************************* 3960 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL12r' 3961 */ 3962 3963 3964 3965 3966 /******************************************************************************* 3967 * CHIP: BCMI_HURACAN 3968 * REGISTER: ANA_LANE_2_QUAD_A_CTRL13 3969 * BLOCKS: ANA_LANE_2_QUAD_A 3970 * REGADDR: 0x840d 3971 * DEVAD: 1 3972 * DESC: control registers 0 3973 * RESETVAL: 0x0 (0) 3974 * ACCESS: R/W 3975 * FIELDS: 3976 * CTLE_RESCAL_FRC_VAL 3977 * CTLE_RESCAL_FRC 3978 */ 3979 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r (0x0001840d | PHYMOD_REG_ACC_RAW) 3980 3981 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_SIZE 4 3982 3983 /* 3984 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL13. 3985 */ 3986 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_s { 3987 uint32_t v[1]; 3988 uint32_t ana_lane_2_quad_a_ctrl13[1]; 3989 uint32_t _ana_lane_2_quad_a_ctrl13; 3990 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_t; 3991 3992 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CLR(r) (r).ana_lane_2_quad_a_ctrl13[0] = 0 3993 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_SET(r,d) (r).ana_lane_2_quad_a_ctrl13[0] = d 3994 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_GET(r) (r).ana_lane_2_quad_a_ctrl13[0] 3995 3996 /* 3997 * These macros can be used to access individual fields. 3998 */ 3999 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_a_ctrl13[0]) >> 4) & 0x1) 4000 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_a_ctrl13[0]=(((r).ana_lane_2_quad_a_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 4001 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_a_ctrl13[0]) & 0xf) 4002 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_a_ctrl13[0]=(((r).ana_lane_2_quad_a_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 4003 4004 /* 4005 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL13. 4006 */ 4007 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r,_r._ana_lane_2_quad_a_ctrl13) 4008 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r,_r._ana_lane_2_quad_a_ctrl13) 4009 4010 /* 4011 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4012 * will be redefined without the chip prefix for easier programming. 4013 * If multiple chips will be programmed in the same source file, then you should 4014 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4015 * and refer to the fully qualified versions. 4016 */ 4017 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4018 4019 #define ANA_LANE_2_QUAD_A_CTRL13r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r 4020 #define ANA_LANE_2_QUAD_A_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_SIZE 4021 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_t ANA_LANE_2_QUAD_A_CTRL13r_t; 4022 #define ANA_LANE_2_QUAD_A_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CLR 4023 #define ANA_LANE_2_QUAD_A_CTRL13r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_SET 4024 #define ANA_LANE_2_QUAD_A_CTRL13r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_GET 4025 #define ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET 4026 #define ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET 4027 #define ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 4028 #define ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 4029 #define READ_ANA_LANE_2_QUAD_A_CTRL13r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL13r 4030 #define WRITE_ANA_LANE_2_QUAD_A_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL13r 4031 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL13r 4032 4033 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4034 /******************************************************************************* 4035 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL13r' 4036 */ 4037 4038 4039 4040 4041 /******************************************************************************* 4042 * CHIP: BCMI_HURACAN 4043 * REGISTER: ANA_LANE_2_QUAD_A_CTRL14 4044 * BLOCKS: ANA_LANE_2_QUAD_A 4045 * REGADDR: 0x840e 4046 * DEVAD: 1 4047 * DESC: control registers 0 4048 * RESETVAL: 0x0 (0) 4049 * ACCESS: R/W 4050 * FIELDS: 4051 * TX_IDLE_FRC_VAL 4052 * TX_IDLE_FRC 4053 * RXSD_IDLE_OVRD 4054 */ 4055 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r (0x0001840e | PHYMOD_REG_ACC_RAW) 4056 4057 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_SIZE 4 4058 4059 /* 4060 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL14. 4061 */ 4062 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_s { 4063 uint32_t v[1]; 4064 uint32_t ana_lane_2_quad_a_ctrl14[1]; 4065 uint32_t _ana_lane_2_quad_a_ctrl14; 4066 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_t; 4067 4068 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_CLR(r) (r).ana_lane_2_quad_a_ctrl14[0] = 0 4069 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_SET(r,d) (r).ana_lane_2_quad_a_ctrl14[0] = d 4070 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_GET(r) (r).ana_lane_2_quad_a_ctrl14[0] 4071 4072 /* 4073 * These macros can be used to access individual fields. 4074 */ 4075 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_2_quad_a_ctrl14[0]) >> 4) & 0x1) 4076 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_2_quad_a_ctrl14[0]=(((r).ana_lane_2_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 4077 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_2_quad_a_ctrl14[0]) >> 1) & 0x1) 4078 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_2_quad_a_ctrl14[0]=(((r).ana_lane_2_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 4079 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_2_quad_a_ctrl14[0]) & 0x1) 4080 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_a_ctrl14[0]=(((r).ana_lane_2_quad_a_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 4081 4082 /* 4083 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL14. 4084 */ 4085 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r,_r._ana_lane_2_quad_a_ctrl14) 4086 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r,_r._ana_lane_2_quad_a_ctrl14) 4087 4088 /* 4089 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4090 * will be redefined without the chip prefix for easier programming. 4091 * If multiple chips will be programmed in the same source file, then you should 4092 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4093 * and refer to the fully qualified versions. 4094 */ 4095 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4096 4097 #define ANA_LANE_2_QUAD_A_CTRL14r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r 4098 #define ANA_LANE_2_QUAD_A_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_SIZE 4099 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_t ANA_LANE_2_QUAD_A_CTRL14r_t; 4100 #define ANA_LANE_2_QUAD_A_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_CLR 4101 #define ANA_LANE_2_QUAD_A_CTRL14r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_SET 4102 #define ANA_LANE_2_QUAD_A_CTRL14r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_GET 4103 #define ANA_LANE_2_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET 4104 #define ANA_LANE_2_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET 4105 #define ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET 4106 #define ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET 4107 #define ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET 4108 #define ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET 4109 #define READ_ANA_LANE_2_QUAD_A_CTRL14r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL14r 4110 #define WRITE_ANA_LANE_2_QUAD_A_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL14r 4111 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL14r 4112 4113 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4114 /******************************************************************************* 4115 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL14r' 4116 */ 4117 4118 4119 4120 4121 /******************************************************************************* 4122 * CHIP: BCMI_HURACAN 4123 * REGISTER: ANA_LANE_2_QUAD_A_CTRL15 4124 * BLOCKS: ANA_LANE_2_QUAD_A 4125 * REGADDR: 0x840f 4126 * DEVAD: 1 4127 * DESC: sigdet filter settings 0 4128 * RESETVAL: 0x0 (0) 4129 * ACCESS: R/W 4130 * FIELDS: 4131 * SIGDET_DIS 4132 * SIGDET_1US_EN 4133 * SIGDET_FRC_VAL 4134 * SIGDET_FRC 4135 * HOLD_LOS_COUNT 4136 * HOLD_SD_COUNT 4137 */ 4138 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r (0x0001840f | PHYMOD_REG_ACC_RAW) 4139 4140 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIZE 4 4141 4142 /* 4143 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL15. 4144 */ 4145 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_s { 4146 uint32_t v[1]; 4147 uint32_t ana_lane_2_quad_a_ctrl15[1]; 4148 uint32_t _ana_lane_2_quad_a_ctrl15; 4149 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_t; 4150 4151 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_CLR(r) (r).ana_lane_2_quad_a_ctrl15[0] = 0 4152 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SET(r,d) (r).ana_lane_2_quad_a_ctrl15[0] = d 4153 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_GET(r) (r).ana_lane_2_quad_a_ctrl15[0] 4154 4155 /* 4156 * These macros can be used to access individual fields. 4157 */ 4158 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_a_ctrl15[0]) >> 8) & 0x7) 4159 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_a_ctrl15[0]=(((r).ana_lane_2_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 4160 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_2_quad_a_ctrl15[0]) >> 4) & 0x7) 4161 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_a_ctrl15[0]=(((r).ana_lane_2_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 4162 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_2_quad_a_ctrl15[0]) >> 3) & 0x1) 4163 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_2_quad_a_ctrl15[0]=(((r).ana_lane_2_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 4164 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_a_ctrl15[0]) >> 2) & 0x1) 4165 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_a_ctrl15[0]=(((r).ana_lane_2_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 4166 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_2_quad_a_ctrl15[0]) >> 1) & 0x1) 4167 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_2_quad_a_ctrl15[0]=(((r).ana_lane_2_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 4168 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_2_quad_a_ctrl15[0]) & 0x1) 4169 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_2_quad_a_ctrl15[0]=(((r).ana_lane_2_quad_a_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 4170 4171 /* 4172 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL15. 4173 */ 4174 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r,_r._ana_lane_2_quad_a_ctrl15) 4175 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r,_r._ana_lane_2_quad_a_ctrl15) 4176 4177 /* 4178 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4179 * will be redefined without the chip prefix for easier programming. 4180 * If multiple chips will be programmed in the same source file, then you should 4181 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4182 * and refer to the fully qualified versions. 4183 */ 4184 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4185 4186 #define ANA_LANE_2_QUAD_A_CTRL15r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r 4187 #define ANA_LANE_2_QUAD_A_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIZE 4188 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_t ANA_LANE_2_QUAD_A_CTRL15r_t; 4189 #define ANA_LANE_2_QUAD_A_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_CLR 4190 #define ANA_LANE_2_QUAD_A_CTRL15r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SET 4191 #define ANA_LANE_2_QUAD_A_CTRL15r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_GET 4192 #define ANA_LANE_2_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET 4193 #define ANA_LANE_2_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET 4194 #define ANA_LANE_2_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET 4195 #define ANA_LANE_2_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET 4196 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRCf_GET 4197 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRCf_SET 4198 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET 4199 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET 4200 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET 4201 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET 4202 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_DISf_GET 4203 #define ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r_SIGDET_DISf_SET 4204 #define READ_ANA_LANE_2_QUAD_A_CTRL15r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL15r 4205 #define WRITE_ANA_LANE_2_QUAD_A_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL15r 4206 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL15r 4207 4208 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4209 /******************************************************************************* 4210 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL15r' 4211 */ 4212 4213 4214 4215 4216 /******************************************************************************* 4217 * CHIP: BCMI_HURACAN 4218 * REGISTER: ANA_LANE_2_QUAD_A_CTRL16 4219 * BLOCKS: ANA_LANE_2_QUAD_A 4220 * REGADDR: 0x8410 4221 * DEVAD: 1 4222 * DESC: sigdet filter settings 1 4223 * RESETVAL: 0x0 (0) 4224 * ACCESS: R/W 4225 * FIELDS: 4226 * LOS_COUNT 4227 * SD_COUNT 4228 */ 4229 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r (0x00018410 | PHYMOD_REG_ACC_RAW) 4230 4231 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SIZE 4 4232 4233 /* 4234 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_CTRL16. 4235 */ 4236 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_s { 4237 uint32_t v[1]; 4238 uint32_t ana_lane_2_quad_a_ctrl16[1]; 4239 uint32_t _ana_lane_2_quad_a_ctrl16; 4240 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_t; 4241 4242 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_CLR(r) (r).ana_lane_2_quad_a_ctrl16[0] = 0 4243 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SET(r,d) (r).ana_lane_2_quad_a_ctrl16[0] = d 4244 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_GET(r) (r).ana_lane_2_quad_a_ctrl16[0] 4245 4246 /* 4247 * These macros can be used to access individual fields. 4248 */ 4249 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_a_ctrl16[0]) >> 8) & 0x1f) 4250 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_a_ctrl16[0]=(((r).ana_lane_2_quad_a_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 4251 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_2_quad_a_ctrl16[0]) & 0x1f) 4252 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_a_ctrl16[0]=(((r).ana_lane_2_quad_a_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 4253 4254 /* 4255 * These macros can be used to access ANA_LANE_2_QUAD_A_CTRL16. 4256 */ 4257 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r,_r._ana_lane_2_quad_a_ctrl16) 4258 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r,_r._ana_lane_2_quad_a_ctrl16) 4259 4260 /* 4261 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4262 * will be redefined without the chip prefix for easier programming. 4263 * If multiple chips will be programmed in the same source file, then you should 4264 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4265 * and refer to the fully qualified versions. 4266 */ 4267 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4268 4269 #define ANA_LANE_2_QUAD_A_CTRL16r BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r 4270 #define ANA_LANE_2_QUAD_A_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SIZE 4271 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_t ANA_LANE_2_QUAD_A_CTRL16r_t; 4272 #define ANA_LANE_2_QUAD_A_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_CLR 4273 #define ANA_LANE_2_QUAD_A_CTRL16r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SET 4274 #define ANA_LANE_2_QUAD_A_CTRL16r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_GET 4275 #define ANA_LANE_2_QUAD_A_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SD_COUNTf_GET 4276 #define ANA_LANE_2_QUAD_A_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_SD_COUNTf_SET 4277 #define ANA_LANE_2_QUAD_A_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_LOS_COUNTf_GET 4278 #define ANA_LANE_2_QUAD_A_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r_LOS_COUNTf_SET 4279 #define READ_ANA_LANE_2_QUAD_A_CTRL16r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_CTRL16r 4280 #define WRITE_ANA_LANE_2_QUAD_A_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_CTRL16r 4281 #define MODIFY_ANA_LANE_2_QUAD_A_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_CTRL16r 4282 4283 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4284 /******************************************************************************* 4285 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_CTRL16r' 4286 */ 4287 4288 4289 4290 4291 /******************************************************************************* 4292 * CHIP: BCMI_HURACAN 4293 * REGISTER: ANA_LANE_2_QUAD_A_STATUS0 4294 * BLOCKS: ANA_LANE_2_QUAD_A 4295 * REGADDR: 0x8420 4296 * DEVAD: 1 4297 * DESC: status registers 0 4298 * RESETVAL: 0x0 (0) 4299 * ACCESS: R/W 4300 * FIELDS: 4301 * O_RX_SIGDET 4302 * DG_RX_SIGDET 4303 */ 4304 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r (0x00018420 | PHYMOD_REG_ACC_RAW) 4305 4306 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_SIZE 4 4307 4308 /* 4309 * This structure should be used to declare and program ANA_LANE_2_QUAD_A_STATUS0. 4310 */ 4311 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_s { 4312 uint32_t v[1]; 4313 uint32_t ana_lane_2_quad_a_status0[1]; 4314 uint32_t _ana_lane_2_quad_a_status0; 4315 } BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_t; 4316 4317 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_CLR(r) (r).ana_lane_2_quad_a_status0[0] = 0 4318 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_SET(r,d) (r).ana_lane_2_quad_a_status0[0] = d 4319 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_GET(r) (r).ana_lane_2_quad_a_status0[0] 4320 4321 /* 4322 * These macros can be used to access individual fields. 4323 */ 4324 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_2_quad_a_status0[0]) >> 1) & 0x1) 4325 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_a_status0[0]=(((r).ana_lane_2_quad_a_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 4326 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_2_quad_a_status0[0]) & 0x1) 4327 #define BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_a_status0[0]=(((r).ana_lane_2_quad_a_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 4328 4329 /* 4330 * These macros can be used to access ANA_LANE_2_QUAD_A_STATUS0. 4331 */ 4332 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r,_r._ana_lane_2_quad_a_status0) 4333 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r,_r._ana_lane_2_quad_a_status0) 4334 4335 /* 4336 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4337 * will be redefined without the chip prefix for easier programming. 4338 * If multiple chips will be programmed in the same source file, then you should 4339 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4340 * and refer to the fully qualified versions. 4341 */ 4342 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4343 4344 #define ANA_LANE_2_QUAD_A_STATUS0r BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r 4345 #define ANA_LANE_2_QUAD_A_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_SIZE 4346 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_t ANA_LANE_2_QUAD_A_STATUS0r_t; 4347 #define ANA_LANE_2_QUAD_A_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_CLR 4348 #define ANA_LANE_2_QUAD_A_STATUS0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_SET 4349 #define ANA_LANE_2_QUAD_A_STATUS0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_GET 4350 #define ANA_LANE_2_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET 4351 #define ANA_LANE_2_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET 4352 #define ANA_LANE_2_QUAD_A_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_O_RX_SIGDETf_GET 4353 #define ANA_LANE_2_QUAD_A_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r_O_RX_SIGDETf_SET 4354 #define READ_ANA_LANE_2_QUAD_A_STATUS0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_A_STATUS0r 4355 #define WRITE_ANA_LANE_2_QUAD_A_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_A_STATUS0r 4356 #define MODIFY_ANA_LANE_2_QUAD_A_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_A_STATUS0r 4357 4358 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4359 /******************************************************************************* 4360 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_A_STATUS0r' 4361 */ 4362 4363 4364 4365 4366 /******************************************************************************* 4367 * CHIP: BCMI_HURACAN 4368 * REGISTER: ANA_LANE_3_QUAD_A_CTRL0 4369 * BLOCKS: ANA_LANE_3_QUAD_A 4370 * REGADDR: 0x8800 4371 * DEVAD: 1 4372 * DESC: control registers 0 4373 * RESETVAL: 0x0 (0) 4374 * ACCESS: R/W 4375 * FIELDS: 4376 * RXTX_PWRDN 4377 * RX_SIGDET_BYPASS 4378 * RX_SIGDET_PWRDN 4379 * RX_SIGDECT_12GMODE 4380 * DC_COUPLE 4381 */ 4382 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r (0x00018800 | PHYMOD_REG_ACC_RAW) 4383 4384 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_SIZE 4 4385 4386 /* 4387 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL0. 4388 */ 4389 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_s { 4390 uint32_t v[1]; 4391 uint32_t ana_lane_3_quad_a_ctrl0[1]; 4392 uint32_t _ana_lane_3_quad_a_ctrl0; 4393 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_t; 4394 4395 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_CLR(r) (r).ana_lane_3_quad_a_ctrl0[0] = 0 4396 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_SET(r,d) (r).ana_lane_3_quad_a_ctrl0[0] = d 4397 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_GET(r) (r).ana_lane_3_quad_a_ctrl0[0] 4398 4399 /* 4400 * These macros can be used to access individual fields. 4401 */ 4402 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_3_quad_a_ctrl0[0]) >> 4) & 0x1) 4403 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_3_quad_a_ctrl0[0]=(((r).ana_lane_3_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 4404 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_3_quad_a_ctrl0[0]) >> 3) & 0x1) 4405 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_3_quad_a_ctrl0[0]=(((r).ana_lane_3_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 4406 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_3_quad_a_ctrl0[0]) >> 2) & 0x1) 4407 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_3_quad_a_ctrl0[0]=(((r).ana_lane_3_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 4408 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_3_quad_a_ctrl0[0]) >> 1) & 0x1) 4409 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_3_quad_a_ctrl0[0]=(((r).ana_lane_3_quad_a_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 4410 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_3_quad_a_ctrl0[0]) & 0x1) 4411 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_3_quad_a_ctrl0[0]=(((r).ana_lane_3_quad_a_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 4412 4413 /* 4414 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL0. 4415 */ 4416 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r,_r._ana_lane_3_quad_a_ctrl0) 4417 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r,_r._ana_lane_3_quad_a_ctrl0) 4418 4419 /* 4420 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4421 * will be redefined without the chip prefix for easier programming. 4422 * If multiple chips will be programmed in the same source file, then you should 4423 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4424 * and refer to the fully qualified versions. 4425 */ 4426 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4427 4428 #define ANA_LANE_3_QUAD_A_CTRL0r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r 4429 #define ANA_LANE_3_QUAD_A_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_SIZE 4430 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_t ANA_LANE_3_QUAD_A_CTRL0r_t; 4431 #define ANA_LANE_3_QUAD_A_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_CLR 4432 #define ANA_LANE_3_QUAD_A_CTRL0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_SET 4433 #define ANA_LANE_3_QUAD_A_CTRL0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_GET 4434 #define ANA_LANE_3_QUAD_A_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_DC_COUPLEf_GET 4435 #define ANA_LANE_3_QUAD_A_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_DC_COUPLEf_SET 4436 #define ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_GET 4437 #define ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDECT_12GMODEf_SET 4438 #define ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_GET 4439 #define ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_PWRDNf_SET 4440 #define ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_GET 4441 #define ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RX_SIGDET_BYPASSf_SET 4442 #define ANA_LANE_3_QUAD_A_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RXTX_PWRDNf_GET 4443 #define ANA_LANE_3_QUAD_A_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r_RXTX_PWRDNf_SET 4444 #define READ_ANA_LANE_3_QUAD_A_CTRL0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL0r 4445 #define WRITE_ANA_LANE_3_QUAD_A_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL0r 4446 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL0r 4447 4448 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4449 /******************************************************************************* 4450 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL0r' 4451 */ 4452 4453 4454 4455 4456 /******************************************************************************* 4457 * CHIP: BCMI_HURACAN 4458 * REGISTER: ANA_LANE_3_QUAD_A_CTRL1 4459 * BLOCKS: ANA_LANE_3_QUAD_A 4460 * REGADDR: 0x8801 4461 * DEVAD: 1 4462 * DESC: control registers 0 4463 * RESETVAL: 0x0 (0) 4464 * ACCESS: R/W 4465 * FIELDS: 4466 * RX_SIGDET_THRESHOLD 4467 * REF_OCL 4468 * OCL_PWRDN 4469 * OCL_DISABLE_LOOP 4470 * RXTX_RESERVED_FOR_15_12 4471 */ 4472 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r (0x00018801 | PHYMOD_REG_ACC_RAW) 4473 4474 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_SIZE 4 4475 4476 /* 4477 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL1. 4478 */ 4479 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_s { 4480 uint32_t v[1]; 4481 uint32_t ana_lane_3_quad_a_ctrl1[1]; 4482 uint32_t _ana_lane_3_quad_a_ctrl1; 4483 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_t; 4484 4485 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_CLR(r) (r).ana_lane_3_quad_a_ctrl1[0] = 0 4486 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_SET(r,d) (r).ana_lane_3_quad_a_ctrl1[0] = d 4487 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_GET(r) (r).ana_lane_3_quad_a_ctrl1[0] 4488 4489 /* 4490 * These macros can be used to access individual fields. 4491 */ 4492 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_3_quad_a_ctrl1[0]) >> 12) & 0xf) 4493 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_3_quad_a_ctrl1[0]=(((r).ana_lane_3_quad_a_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 4494 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_3_quad_a_ctrl1[0]) >> 9) & 0x1) 4495 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_3_quad_a_ctrl1[0]=(((r).ana_lane_3_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 4496 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_3_quad_a_ctrl1[0]) >> 8) & 0x1) 4497 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_3_quad_a_ctrl1[0]=(((r).ana_lane_3_quad_a_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 4498 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_3_quad_a_ctrl1[0]) >> 4) & 0x3) 4499 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_3_quad_a_ctrl1[0]=(((r).ana_lane_3_quad_a_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 4500 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_3_quad_a_ctrl1[0]) & 0x7) 4501 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_3_quad_a_ctrl1[0]=(((r).ana_lane_3_quad_a_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 4502 4503 /* 4504 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL1. 4505 */ 4506 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r,_r._ana_lane_3_quad_a_ctrl1) 4507 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r,_r._ana_lane_3_quad_a_ctrl1) 4508 4509 /* 4510 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4511 * will be redefined without the chip prefix for easier programming. 4512 * If multiple chips will be programmed in the same source file, then you should 4513 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4514 * and refer to the fully qualified versions. 4515 */ 4516 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4517 4518 #define ANA_LANE_3_QUAD_A_CTRL1r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r 4519 #define ANA_LANE_3_QUAD_A_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_SIZE 4520 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_t ANA_LANE_3_QUAD_A_CTRL1r_t; 4521 #define ANA_LANE_3_QUAD_A_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_CLR 4522 #define ANA_LANE_3_QUAD_A_CTRL1r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_SET 4523 #define ANA_LANE_3_QUAD_A_CTRL1r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_GET 4524 #define ANA_LANE_3_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 4525 #define ANA_LANE_3_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 4526 #define ANA_LANE_3_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_GET 4527 #define ANA_LANE_3_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_DISABLE_LOOPf_SET 4528 #define ANA_LANE_3_QUAD_A_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_PWRDNf_GET 4529 #define ANA_LANE_3_QUAD_A_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_OCL_PWRDNf_SET 4530 #define ANA_LANE_3_QUAD_A_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_REF_OCLf_GET 4531 #define ANA_LANE_3_QUAD_A_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_REF_OCLf_SET 4532 #define ANA_LANE_3_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_GET 4533 #define ANA_LANE_3_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r_RX_SIGDET_THRESHOLDf_SET 4534 #define READ_ANA_LANE_3_QUAD_A_CTRL1r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL1r 4535 #define WRITE_ANA_LANE_3_QUAD_A_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL1r 4536 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL1r 4537 4538 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4539 /******************************************************************************* 4540 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL1r' 4541 */ 4542 4543 4544 4545 4546 /******************************************************************************* 4547 * CHIP: BCMI_HURACAN 4548 * REGISTER: ANA_LANE_3_QUAD_A_CTRL2 4549 * BLOCKS: ANA_LANE_3_QUAD_A 4550 * REGADDR: 0x8802 4551 * DEVAD: 1 4552 * DESC: control registers 0 4553 * RESETVAL: 0x0 (0) 4554 * ACCESS: R/W 4555 * FIELDS: 4556 * CTLE_ENB_NEGIMP 4557 * CTLE_ENB_NEGCAP 4558 */ 4559 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r (0x00018802 | PHYMOD_REG_ACC_RAW) 4560 4561 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_SIZE 4 4562 4563 /* 4564 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL2. 4565 */ 4566 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_s { 4567 uint32_t v[1]; 4568 uint32_t ana_lane_3_quad_a_ctrl2[1]; 4569 uint32_t _ana_lane_3_quad_a_ctrl2; 4570 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_t; 4571 4572 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CLR(r) (r).ana_lane_3_quad_a_ctrl2[0] = 0 4573 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_SET(r,d) (r).ana_lane_3_quad_a_ctrl2[0] = d 4574 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_GET(r) (r).ana_lane_3_quad_a_ctrl2[0] 4575 4576 /* 4577 * These macros can be used to access individual fields. 4578 */ 4579 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_3_quad_a_ctrl2[0]) >> 8) & 0x7f) 4580 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_3_quad_a_ctrl2[0]=(((r).ana_lane_3_quad_a_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 4581 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_3_quad_a_ctrl2[0]) & 0x7f) 4582 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_3_quad_a_ctrl2[0]=(((r).ana_lane_3_quad_a_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 4583 4584 /* 4585 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL2. 4586 */ 4587 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r,_r._ana_lane_3_quad_a_ctrl2) 4588 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r,_r._ana_lane_3_quad_a_ctrl2) 4589 4590 /* 4591 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4592 * will be redefined without the chip prefix for easier programming. 4593 * If multiple chips will be programmed in the same source file, then you should 4594 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4595 * and refer to the fully qualified versions. 4596 */ 4597 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4598 4599 #define ANA_LANE_3_QUAD_A_CTRL2r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r 4600 #define ANA_LANE_3_QUAD_A_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_SIZE 4601 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_t ANA_LANE_3_QUAD_A_CTRL2r_t; 4602 #define ANA_LANE_3_QUAD_A_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CLR 4603 #define ANA_LANE_3_QUAD_A_CTRL2r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_SET 4604 #define ANA_LANE_3_QUAD_A_CTRL2r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_GET 4605 #define ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_GET 4606 #define ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGCAPf_SET 4607 #define ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_GET 4608 #define ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r_CTLE_ENB_NEGIMPf_SET 4609 #define READ_ANA_LANE_3_QUAD_A_CTRL2r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL2r 4610 #define WRITE_ANA_LANE_3_QUAD_A_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL2r 4611 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL2r 4612 4613 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4614 /******************************************************************************* 4615 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL2r' 4616 */ 4617 4618 4619 4620 4621 /******************************************************************************* 4622 * CHIP: BCMI_HURACAN 4623 * REGISTER: ANA_LANE_3_QUAD_A_CTRL3 4624 * BLOCKS: ANA_LANE_3_QUAD_A 4625 * REGADDR: 0x8803 4626 * DEVAD: 1 4627 * DESC: control registers 0 4628 * RESETVAL: 0x0 (0) 4629 * ACCESS: R/W 4630 * FIELDS: 4631 * CTLE_EN_NEGRES 4632 * CTLE_EQSEL 4633 */ 4634 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r (0x00018803 | PHYMOD_REG_ACC_RAW) 4635 4636 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_SIZE 4 4637 4638 /* 4639 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL3. 4640 */ 4641 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_s { 4642 uint32_t v[1]; 4643 uint32_t ana_lane_3_quad_a_ctrl3[1]; 4644 uint32_t _ana_lane_3_quad_a_ctrl3; 4645 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_t; 4646 4647 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CLR(r) (r).ana_lane_3_quad_a_ctrl3[0] = 0 4648 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_SET(r,d) (r).ana_lane_3_quad_a_ctrl3[0] = d 4649 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_GET(r) (r).ana_lane_3_quad_a_ctrl3[0] 4650 4651 /* 4652 * These macros can be used to access individual fields. 4653 */ 4654 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_3_quad_a_ctrl3[0]) >> 8) & 0xff) 4655 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_3_quad_a_ctrl3[0]=(((r).ana_lane_3_quad_a_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 4656 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_3_quad_a_ctrl3[0]) & 0x7f) 4657 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_3_quad_a_ctrl3[0]=(((r).ana_lane_3_quad_a_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 4658 4659 /* 4660 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL3. 4661 */ 4662 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r,_r._ana_lane_3_quad_a_ctrl3) 4663 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r,_r._ana_lane_3_quad_a_ctrl3) 4664 4665 /* 4666 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4667 * will be redefined without the chip prefix for easier programming. 4668 * If multiple chips will be programmed in the same source file, then you should 4669 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4670 * and refer to the fully qualified versions. 4671 */ 4672 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4673 4674 #define ANA_LANE_3_QUAD_A_CTRL3r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r 4675 #define ANA_LANE_3_QUAD_A_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_SIZE 4676 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_t ANA_LANE_3_QUAD_A_CTRL3r_t; 4677 #define ANA_LANE_3_QUAD_A_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CLR 4678 #define ANA_LANE_3_QUAD_A_CTRL3r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_SET 4679 #define ANA_LANE_3_QUAD_A_CTRL3r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_GET 4680 #define ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EQSELf_GET 4681 #define ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EQSELf_SET 4682 #define ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_GET 4683 #define ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r_CTLE_EN_NEGRESf_SET 4684 #define READ_ANA_LANE_3_QUAD_A_CTRL3r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL3r 4685 #define WRITE_ANA_LANE_3_QUAD_A_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL3r 4686 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL3r 4687 4688 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4689 /******************************************************************************* 4690 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL3r' 4691 */ 4692 4693 4694 4695 4696 /******************************************************************************* 4697 * CHIP: BCMI_HURACAN 4698 * REGISTER: ANA_LANE_3_QUAD_A_CTRL4 4699 * BLOCKS: ANA_LANE_3_QUAD_A 4700 * REGADDR: 0x8804 4701 * DEVAD: 1 4702 * DESC: control registers 0 4703 * RESETVAL: 0x0 (0) 4704 * ACCESS: R/W 4705 * FIELDS: 4706 * CTLE_LZEN 4707 * RXTX_RESERVED_FOR_59_52 4708 */ 4709 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r (0x00018804 | PHYMOD_REG_ACC_RAW) 4710 4711 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_SIZE 4 4712 4713 /* 4714 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL4. 4715 */ 4716 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_s { 4717 uint32_t v[1]; 4718 uint32_t ana_lane_3_quad_a_ctrl4[1]; 4719 uint32_t _ana_lane_3_quad_a_ctrl4; 4720 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_t; 4721 4722 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_CLR(r) (r).ana_lane_3_quad_a_ctrl4[0] = 0 4723 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_SET(r,d) (r).ana_lane_3_quad_a_ctrl4[0] = d 4724 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_GET(r) (r).ana_lane_3_quad_a_ctrl4[0] 4725 4726 /* 4727 * These macros can be used to access individual fields. 4728 */ 4729 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_3_quad_a_ctrl4[0]) >> 4) & 0xff) 4730 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_3_quad_a_ctrl4[0]=(((r).ana_lane_3_quad_a_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 4731 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_3_quad_a_ctrl4[0]) & 0x1) 4732 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_3_quad_a_ctrl4[0]=(((r).ana_lane_3_quad_a_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 4733 4734 /* 4735 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL4. 4736 */ 4737 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r,_r._ana_lane_3_quad_a_ctrl4) 4738 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r,_r._ana_lane_3_quad_a_ctrl4) 4739 4740 /* 4741 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4742 * will be redefined without the chip prefix for easier programming. 4743 * If multiple chips will be programmed in the same source file, then you should 4744 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4745 * and refer to the fully qualified versions. 4746 */ 4747 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4748 4749 #define ANA_LANE_3_QUAD_A_CTRL4r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r 4750 #define ANA_LANE_3_QUAD_A_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_SIZE 4751 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_t ANA_LANE_3_QUAD_A_CTRL4r_t; 4752 #define ANA_LANE_3_QUAD_A_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_CLR 4753 #define ANA_LANE_3_QUAD_A_CTRL4r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_SET 4754 #define ANA_LANE_3_QUAD_A_CTRL4r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_GET 4755 #define ANA_LANE_3_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 4756 #define ANA_LANE_3_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 4757 #define ANA_LANE_3_QUAD_A_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_CTLE_LZENf_GET 4758 #define ANA_LANE_3_QUAD_A_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r_CTLE_LZENf_SET 4759 #define READ_ANA_LANE_3_QUAD_A_CTRL4r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL4r 4760 #define WRITE_ANA_LANE_3_QUAD_A_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL4r 4761 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL4r 4762 4763 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4764 /******************************************************************************* 4765 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL4r' 4766 */ 4767 4768 4769 4770 4771 /******************************************************************************* 4772 * CHIP: BCMI_HURACAN 4773 * REGISTER: ANA_LANE_3_QUAD_A_CTRL5 4774 * BLOCKS: ANA_LANE_3_QUAD_A 4775 * REGADDR: 0x8805 4776 * DEVAD: 1 4777 * DESC: control registers 0 4778 * RESETVAL: 0x0 (0) 4779 * ACCESS: R/W 4780 * FIELDS: 4781 * CTLE_LOPEAKING 4782 * CTLE_PD 4783 * LA_GCTRL 4784 */ 4785 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r (0x00018805 | PHYMOD_REG_ACC_RAW) 4786 4787 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_SIZE 4 4788 4789 /* 4790 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL5. 4791 */ 4792 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_s { 4793 uint32_t v[1]; 4794 uint32_t ana_lane_3_quad_a_ctrl5[1]; 4795 uint32_t _ana_lane_3_quad_a_ctrl5; 4796 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_t; 4797 4798 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CLR(r) (r).ana_lane_3_quad_a_ctrl5[0] = 0 4799 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_SET(r,d) (r).ana_lane_3_quad_a_ctrl5[0] = d 4800 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_GET(r) (r).ana_lane_3_quad_a_ctrl5[0] 4801 4802 /* 4803 * These macros can be used to access individual fields. 4804 */ 4805 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_3_quad_a_ctrl5[0]) >> 4) & 0x3ff) 4806 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_3_quad_a_ctrl5[0]=(((r).ana_lane_3_quad_a_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 4807 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_3_quad_a_ctrl5[0]) >> 1) & 0x1) 4808 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_3_quad_a_ctrl5[0]=(((r).ana_lane_3_quad_a_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 4809 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_3_quad_a_ctrl5[0]) & 0x1) 4810 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_3_quad_a_ctrl5[0]=(((r).ana_lane_3_quad_a_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 4811 4812 /* 4813 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL5. 4814 */ 4815 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r,_r._ana_lane_3_quad_a_ctrl5) 4816 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r,_r._ana_lane_3_quad_a_ctrl5) 4817 4818 /* 4819 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4820 * will be redefined without the chip prefix for easier programming. 4821 * If multiple chips will be programmed in the same source file, then you should 4822 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4823 * and refer to the fully qualified versions. 4824 */ 4825 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4826 4827 #define ANA_LANE_3_QUAD_A_CTRL5r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r 4828 #define ANA_LANE_3_QUAD_A_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_SIZE 4829 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_t ANA_LANE_3_QUAD_A_CTRL5r_t; 4830 #define ANA_LANE_3_QUAD_A_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CLR 4831 #define ANA_LANE_3_QUAD_A_CTRL5r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_SET 4832 #define ANA_LANE_3_QUAD_A_CTRL5r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_GET 4833 #define ANA_LANE_3_QUAD_A_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_LA_GCTRLf_GET 4834 #define ANA_LANE_3_QUAD_A_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_LA_GCTRLf_SET 4835 #define ANA_LANE_3_QUAD_A_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_PDf_GET 4836 #define ANA_LANE_3_QUAD_A_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_PDf_SET 4837 #define ANA_LANE_3_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_GET 4838 #define ANA_LANE_3_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r_CTLE_LOPEAKINGf_SET 4839 #define READ_ANA_LANE_3_QUAD_A_CTRL5r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL5r 4840 #define WRITE_ANA_LANE_3_QUAD_A_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL5r 4841 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL5r 4842 4843 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4844 /******************************************************************************* 4845 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL5r' 4846 */ 4847 4848 4849 4850 4851 /******************************************************************************* 4852 * CHIP: BCMI_HURACAN 4853 * REGISTER: ANA_LANE_3_QUAD_A_CTRL6 4854 * BLOCKS: ANA_LANE_3_QUAD_A 4855 * REGADDR: 0x8806 4856 * DEVAD: 1 4857 * DESC: control registers 0 4858 * RESETVAL: 0x0 (0) 4859 * ACCESS: R/W 4860 * FIELDS: 4861 * LA_DEGAIN 4862 * LA_DETUNE 4863 */ 4864 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r (0x00018806 | PHYMOD_REG_ACC_RAW) 4865 4866 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_SIZE 4 4867 4868 /* 4869 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL6. 4870 */ 4871 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_s { 4872 uint32_t v[1]; 4873 uint32_t ana_lane_3_quad_a_ctrl6[1]; 4874 uint32_t _ana_lane_3_quad_a_ctrl6; 4875 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_t; 4876 4877 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_CLR(r) (r).ana_lane_3_quad_a_ctrl6[0] = 0 4878 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_SET(r,d) (r).ana_lane_3_quad_a_ctrl6[0] = d 4879 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_GET(r) (r).ana_lane_3_quad_a_ctrl6[0] 4880 4881 /* 4882 * These macros can be used to access individual fields. 4883 */ 4884 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_3_quad_a_ctrl6[0]) >> 8) & 0xff) 4885 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_3_quad_a_ctrl6[0]=(((r).ana_lane_3_quad_a_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 4886 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_3_quad_a_ctrl6[0]) & 0x1f) 4887 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_3_quad_a_ctrl6[0]=(((r).ana_lane_3_quad_a_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 4888 4889 /* 4890 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL6. 4891 */ 4892 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r,_r._ana_lane_3_quad_a_ctrl6) 4893 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r,_r._ana_lane_3_quad_a_ctrl6) 4894 4895 /* 4896 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4897 * will be redefined without the chip prefix for easier programming. 4898 * If multiple chips will be programmed in the same source file, then you should 4899 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4900 * and refer to the fully qualified versions. 4901 */ 4902 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4903 4904 #define ANA_LANE_3_QUAD_A_CTRL6r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r 4905 #define ANA_LANE_3_QUAD_A_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_SIZE 4906 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_t ANA_LANE_3_QUAD_A_CTRL6r_t; 4907 #define ANA_LANE_3_QUAD_A_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_CLR 4908 #define ANA_LANE_3_QUAD_A_CTRL6r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_SET 4909 #define ANA_LANE_3_QUAD_A_CTRL6r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_GET 4910 #define ANA_LANE_3_QUAD_A_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DETUNEf_GET 4911 #define ANA_LANE_3_QUAD_A_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DETUNEf_SET 4912 #define ANA_LANE_3_QUAD_A_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DEGAINf_GET 4913 #define ANA_LANE_3_QUAD_A_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r_LA_DEGAINf_SET 4914 #define READ_ANA_LANE_3_QUAD_A_CTRL6r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL6r 4915 #define WRITE_ANA_LANE_3_QUAD_A_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL6r 4916 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL6r 4917 4918 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4919 /******************************************************************************* 4920 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL6r' 4921 */ 4922 4923 4924 4925 4926 /******************************************************************************* 4927 * CHIP: BCMI_HURACAN 4928 * REGISTER: ANA_LANE_3_QUAD_A_CTRL7 4929 * BLOCKS: ANA_LANE_3_QUAD_A 4930 * REGADDR: 0x8807 4931 * DEVAD: 1 4932 * DESC: control registers 0 4933 * RESETVAL: 0x0 (0) 4934 * ACCESS: R/W 4935 * FIELDS: 4936 * LA_LIN_MODE 4937 * RX_BIAS_FB_PDN 4938 */ 4939 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r (0x00018807 | PHYMOD_REG_ACC_RAW) 4940 4941 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_SIZE 4 4942 4943 /* 4944 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL7. 4945 */ 4946 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_s { 4947 uint32_t v[1]; 4948 uint32_t ana_lane_3_quad_a_ctrl7[1]; 4949 uint32_t _ana_lane_3_quad_a_ctrl7; 4950 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_t; 4951 4952 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_CLR(r) (r).ana_lane_3_quad_a_ctrl7[0] = 0 4953 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_SET(r,d) (r).ana_lane_3_quad_a_ctrl7[0] = d 4954 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_GET(r) (r).ana_lane_3_quad_a_ctrl7[0] 4955 4956 /* 4957 * These macros can be used to access individual fields. 4958 */ 4959 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_3_quad_a_ctrl7[0]) >> 8) & 0x1) 4960 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_3_quad_a_ctrl7[0]=(((r).ana_lane_3_quad_a_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 4961 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_3_quad_a_ctrl7[0]) & 0x1f) 4962 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_3_quad_a_ctrl7[0]=(((r).ana_lane_3_quad_a_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 4963 4964 /* 4965 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL7. 4966 */ 4967 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r,_r._ana_lane_3_quad_a_ctrl7) 4968 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r,_r._ana_lane_3_quad_a_ctrl7) 4969 4970 /* 4971 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 4972 * will be redefined without the chip prefix for easier programming. 4973 * If multiple chips will be programmed in the same source file, then you should 4974 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 4975 * and refer to the fully qualified versions. 4976 */ 4977 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 4978 4979 #define ANA_LANE_3_QUAD_A_CTRL7r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r 4980 #define ANA_LANE_3_QUAD_A_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_SIZE 4981 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_t ANA_LANE_3_QUAD_A_CTRL7r_t; 4982 #define ANA_LANE_3_QUAD_A_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_CLR 4983 #define ANA_LANE_3_QUAD_A_CTRL7r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_SET 4984 #define ANA_LANE_3_QUAD_A_CTRL7r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_GET 4985 #define ANA_LANE_3_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_GET 4986 #define ANA_LANE_3_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_RX_BIAS_FB_PDNf_SET 4987 #define ANA_LANE_3_QUAD_A_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_LA_LIN_MODEf_GET 4988 #define ANA_LANE_3_QUAD_A_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r_LA_LIN_MODEf_SET 4989 #define READ_ANA_LANE_3_QUAD_A_CTRL7r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL7r 4990 #define WRITE_ANA_LANE_3_QUAD_A_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL7r 4991 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL7r 4992 4993 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 4994 /******************************************************************************* 4995 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL7r' 4996 */ 4997 4998 4999 5000 5001 /******************************************************************************* 5002 * CHIP: BCMI_HURACAN 5003 * REGISTER: ANA_LANE_3_QUAD_A_CTRL8 5004 * BLOCKS: ANA_LANE_3_QUAD_A 5005 * REGADDR: 0x8808 5006 * DEVAD: 1 5007 * DESC: control registers 0 5008 * RESETVAL: 0x0 (0) 5009 * ACCESS: R/W 5010 * FIELDS: 5011 * LA_PD 5012 * LA_PD_IDLE 5013 * RXTX_RESERVED_FOR_99_95 5014 */ 5015 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r (0x00018808 | PHYMOD_REG_ACC_RAW) 5016 5017 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_SIZE 4 5018 5019 /* 5020 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL8. 5021 */ 5022 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_s { 5023 uint32_t v[1]; 5024 uint32_t ana_lane_3_quad_a_ctrl8[1]; 5025 uint32_t _ana_lane_3_quad_a_ctrl8; 5026 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_t; 5027 5028 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_CLR(r) (r).ana_lane_3_quad_a_ctrl8[0] = 0 5029 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_SET(r,d) (r).ana_lane_3_quad_a_ctrl8[0] = d 5030 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_GET(r) (r).ana_lane_3_quad_a_ctrl8[0] 5031 5032 /* 5033 * These macros can be used to access individual fields. 5034 */ 5035 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_3_quad_a_ctrl8[0]) >> 4) & 0x1f) 5036 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_3_quad_a_ctrl8[0]=(((r).ana_lane_3_quad_a_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 5037 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_3_quad_a_ctrl8[0]) >> 1) & 0x1) 5038 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_3_quad_a_ctrl8[0]=(((r).ana_lane_3_quad_a_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 5039 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_3_quad_a_ctrl8[0]) & 0x1) 5040 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_3_quad_a_ctrl8[0]=(((r).ana_lane_3_quad_a_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 5041 5042 /* 5043 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL8. 5044 */ 5045 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r,_r._ana_lane_3_quad_a_ctrl8) 5046 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r,_r._ana_lane_3_quad_a_ctrl8) 5047 5048 /* 5049 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5050 * will be redefined without the chip prefix for easier programming. 5051 * If multiple chips will be programmed in the same source file, then you should 5052 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5053 * and refer to the fully qualified versions. 5054 */ 5055 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5056 5057 #define ANA_LANE_3_QUAD_A_CTRL8r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r 5058 #define ANA_LANE_3_QUAD_A_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_SIZE 5059 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_t ANA_LANE_3_QUAD_A_CTRL8r_t; 5060 #define ANA_LANE_3_QUAD_A_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_CLR 5061 #define ANA_LANE_3_QUAD_A_CTRL8r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_SET 5062 #define ANA_LANE_3_QUAD_A_CTRL8r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_GET 5063 #define ANA_LANE_3_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 5064 #define ANA_LANE_3_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 5065 #define ANA_LANE_3_QUAD_A_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PD_IDLEf_GET 5066 #define ANA_LANE_3_QUAD_A_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PD_IDLEf_SET 5067 #define ANA_LANE_3_QUAD_A_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PDf_GET 5068 #define ANA_LANE_3_QUAD_A_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r_LA_PDf_SET 5069 #define READ_ANA_LANE_3_QUAD_A_CTRL8r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL8r 5070 #define WRITE_ANA_LANE_3_QUAD_A_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL8r 5071 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL8r 5072 5073 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5074 /******************************************************************************* 5075 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL8r' 5076 */ 5077 5078 5079 5080 5081 /******************************************************************************* 5082 * CHIP: BCMI_HURACAN 5083 * REGISTER: ANA_LANE_3_QUAD_A_CTRL9 5084 * BLOCKS: ANA_LANE_3_QUAD_A 5085 * REGADDR: 0x8809 5086 * DEVAD: 1 5087 * DESC: control registers 0 5088 * RESETVAL: 0x0 (0) 5089 * ACCESS: R/W 5090 * FIELDS: 5091 * DRV_POST1 5092 * DLINE_SWING_1 5093 * DLINE_SWING_2 5094 * DLINE_DELAY_CTRL 5095 */ 5096 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r (0x00018809 | PHYMOD_REG_ACC_RAW) 5097 5098 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_SIZE 4 5099 5100 /* 5101 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL9. 5102 */ 5103 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_s { 5104 uint32_t v[1]; 5105 uint32_t ana_lane_3_quad_a_ctrl9[1]; 5106 uint32_t _ana_lane_3_quad_a_ctrl9; 5107 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_t; 5108 5109 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_CLR(r) (r).ana_lane_3_quad_a_ctrl9[0] = 0 5110 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_SET(r,d) (r).ana_lane_3_quad_a_ctrl9[0] = d 5111 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_GET(r) (r).ana_lane_3_quad_a_ctrl9[0] 5112 5113 /* 5114 * These macros can be used to access individual fields. 5115 */ 5116 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_3_quad_a_ctrl9[0]) >> 12) & 0x7) 5117 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_3_quad_a_ctrl9[0]=(((r).ana_lane_3_quad_a_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 5118 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_3_quad_a_ctrl9[0]) >> 8) & 0x3) 5119 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_3_quad_a_ctrl9[0]=(((r).ana_lane_3_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 5120 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_3_quad_a_ctrl9[0]) >> 4) & 0x3) 5121 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_3_quad_a_ctrl9[0]=(((r).ana_lane_3_quad_a_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 5122 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_3_quad_a_ctrl9[0]) & 0xf) 5123 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_3_quad_a_ctrl9[0]=(((r).ana_lane_3_quad_a_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 5124 5125 /* 5126 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL9. 5127 */ 5128 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r,_r._ana_lane_3_quad_a_ctrl9) 5129 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r,_r._ana_lane_3_quad_a_ctrl9) 5130 5131 /* 5132 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5133 * will be redefined without the chip prefix for easier programming. 5134 * If multiple chips will be programmed in the same source file, then you should 5135 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5136 * and refer to the fully qualified versions. 5137 */ 5138 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5139 5140 #define ANA_LANE_3_QUAD_A_CTRL9r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r 5141 #define ANA_LANE_3_QUAD_A_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_SIZE 5142 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_t ANA_LANE_3_QUAD_A_CTRL9r_t; 5143 #define ANA_LANE_3_QUAD_A_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_CLR 5144 #define ANA_LANE_3_QUAD_A_CTRL9r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_SET 5145 #define ANA_LANE_3_QUAD_A_CTRL9r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_GET 5146 #define ANA_LANE_3_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_GET 5147 #define ANA_LANE_3_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_DELAY_CTRLf_SET 5148 #define ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_2f_GET 5149 #define ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_2f_SET 5150 #define ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_1f_GET 5151 #define ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DLINE_SWING_1f_SET 5152 #define ANA_LANE_3_QUAD_A_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DRV_POST1f_GET 5153 #define ANA_LANE_3_QUAD_A_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r_DRV_POST1f_SET 5154 #define READ_ANA_LANE_3_QUAD_A_CTRL9r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL9r 5155 #define WRITE_ANA_LANE_3_QUAD_A_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL9r 5156 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL9r 5157 5158 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5159 /******************************************************************************* 5160 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL9r' 5161 */ 5162 5163 5164 5165 5166 /******************************************************************************* 5167 * CHIP: BCMI_HURACAN 5168 * REGISTER: ANA_LANE_3_QUAD_A_CTRL10 5169 * BLOCKS: ANA_LANE_3_QUAD_A 5170 * REGADDR: 0x880a 5171 * DEVAD: 1 5172 * DESC: control registers 0 5173 * RESETVAL: 0x0 (0) 5174 * ACCESS: R/W 5175 * FIELDS: 5176 * DRV_PWD 5177 * DLINE_PWD 5178 * DRV_VBSEL 5179 * DRV_MAIN 5180 * DRV_MAIN_PU 5181 */ 5182 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r (0x0001880a | PHYMOD_REG_ACC_RAW) 5183 5184 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_SIZE 4 5185 5186 /* 5187 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL10. 5188 */ 5189 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_s { 5190 uint32_t v[1]; 5191 uint32_t ana_lane_3_quad_a_ctrl10[1]; 5192 uint32_t _ana_lane_3_quad_a_ctrl10; 5193 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_t; 5194 5195 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_CLR(r) (r).ana_lane_3_quad_a_ctrl10[0] = 0 5196 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_SET(r,d) (r).ana_lane_3_quad_a_ctrl10[0] = d 5197 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_GET(r) (r).ana_lane_3_quad_a_ctrl10[0] 5198 5199 /* 5200 * These macros can be used to access individual fields. 5201 */ 5202 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_3_quad_a_ctrl10[0]) >> 12) & 0xf) 5203 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_3_quad_a_ctrl10[0]=(((r).ana_lane_3_quad_a_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 5204 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_3_quad_a_ctrl10[0]) >> 4) & 0x3f) 5205 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_3_quad_a_ctrl10[0]=(((r).ana_lane_3_quad_a_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 5206 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_3_quad_a_ctrl10[0]) >> 2) & 0x1) 5207 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_3_quad_a_ctrl10[0]=(((r).ana_lane_3_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 5208 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_3_quad_a_ctrl10[0]) >> 1) & 0x1) 5209 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_3_quad_a_ctrl10[0]=(((r).ana_lane_3_quad_a_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 5210 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_3_quad_a_ctrl10[0]) & 0x1) 5211 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_3_quad_a_ctrl10[0]=(((r).ana_lane_3_quad_a_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 5212 5213 /* 5214 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL10. 5215 */ 5216 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r,_r._ana_lane_3_quad_a_ctrl10) 5217 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r,_r._ana_lane_3_quad_a_ctrl10) 5218 5219 /* 5220 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5221 * will be redefined without the chip prefix for easier programming. 5222 * If multiple chips will be programmed in the same source file, then you should 5223 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5224 * and refer to the fully qualified versions. 5225 */ 5226 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5227 5228 #define ANA_LANE_3_QUAD_A_CTRL10r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r 5229 #define ANA_LANE_3_QUAD_A_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_SIZE 5230 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_t ANA_LANE_3_QUAD_A_CTRL10r_t; 5231 #define ANA_LANE_3_QUAD_A_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_CLR 5232 #define ANA_LANE_3_QUAD_A_CTRL10r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_SET 5233 #define ANA_LANE_3_QUAD_A_CTRL10r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_GET 5234 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAIN_PUf_GET 5235 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAIN_PUf_SET 5236 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAINf_GET 5237 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_MAINf_SET 5238 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_VBSELf_GET 5239 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_VBSELf_SET 5240 #define ANA_LANE_3_QUAD_A_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DLINE_PWDf_GET 5241 #define ANA_LANE_3_QUAD_A_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DLINE_PWDf_SET 5242 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_PWDf_GET 5243 #define ANA_LANE_3_QUAD_A_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r_DRV_PWDf_SET 5244 #define READ_ANA_LANE_3_QUAD_A_CTRL10r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL10r 5245 #define WRITE_ANA_LANE_3_QUAD_A_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL10r 5246 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL10r 5247 5248 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5249 /******************************************************************************* 5250 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL10r' 5251 */ 5252 5253 5254 5255 5256 /******************************************************************************* 5257 * CHIP: BCMI_HURACAN 5258 * REGISTER: ANA_LANE_3_QUAD_A_CTRL11 5259 * BLOCKS: ANA_LANE_3_QUAD_A 5260 * REGADDR: 0x880b 5261 * DEVAD: 1 5262 * DESC: control registers 0 5263 * RESETVAL: 0x0 (0) 5264 * ACCESS: R/W 5265 * FIELDS: 5266 * RXTX_RESERVED_FOR_143_128 5267 */ 5268 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r (0x0001880b | PHYMOD_REG_ACC_RAW) 5269 5270 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_SIZE 4 5271 5272 /* 5273 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL11. 5274 */ 5275 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_s { 5276 uint32_t v[1]; 5277 uint32_t ana_lane_3_quad_a_ctrl11[1]; 5278 uint32_t _ana_lane_3_quad_a_ctrl11; 5279 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_t; 5280 5281 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_CLR(r) (r).ana_lane_3_quad_a_ctrl11[0] = 0 5282 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_SET(r,d) (r).ana_lane_3_quad_a_ctrl11[0] = d 5283 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_GET(r) (r).ana_lane_3_quad_a_ctrl11[0] 5284 5285 /* 5286 * These macros can be used to access individual fields. 5287 */ 5288 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_3_quad_a_ctrl11[0]) & 0xffff) 5289 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_3_quad_a_ctrl11[0]=(((r).ana_lane_3_quad_a_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 5290 5291 /* 5292 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL11. 5293 */ 5294 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r,_r._ana_lane_3_quad_a_ctrl11) 5295 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r,_r._ana_lane_3_quad_a_ctrl11) 5296 5297 /* 5298 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5299 * will be redefined without the chip prefix for easier programming. 5300 * If multiple chips will be programmed in the same source file, then you should 5301 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5302 * and refer to the fully qualified versions. 5303 */ 5304 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5305 5306 #define ANA_LANE_3_QUAD_A_CTRL11r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r 5307 #define ANA_LANE_3_QUAD_A_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_SIZE 5308 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_t ANA_LANE_3_QUAD_A_CTRL11r_t; 5309 #define ANA_LANE_3_QUAD_A_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_CLR 5310 #define ANA_LANE_3_QUAD_A_CTRL11r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_SET 5311 #define ANA_LANE_3_QUAD_A_CTRL11r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_GET 5312 #define ANA_LANE_3_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 5313 #define ANA_LANE_3_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 5314 #define READ_ANA_LANE_3_QUAD_A_CTRL11r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL11r 5315 #define WRITE_ANA_LANE_3_QUAD_A_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL11r 5316 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL11r 5317 5318 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5319 /******************************************************************************* 5320 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL11r' 5321 */ 5322 5323 5324 5325 5326 /******************************************************************************* 5327 * CHIP: BCMI_HURACAN 5328 * REGISTER: ANA_LANE_3_QUAD_A_CTRL12 5329 * BLOCKS: ANA_LANE_3_QUAD_A 5330 * REGADDR: 0x880c 5331 * DEVAD: 1 5332 * DESC: control registers 0 5333 * RESETVAL: 0x0 (0) 5334 * ACCESS: R/W 5335 * FIELDS: 5336 * LA_RESCAL_FRC_VAL 5337 * LA_RESCAL_FRC 5338 * DRV_RESCAL_FRC_VAL 5339 * DRV_RESCAL_FRC 5340 */ 5341 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r (0x0001880c | PHYMOD_REG_ACC_RAW) 5342 5343 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_SIZE 4 5344 5345 /* 5346 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL12. 5347 */ 5348 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_s { 5349 uint32_t v[1]; 5350 uint32_t ana_lane_3_quad_a_ctrl12[1]; 5351 uint32_t _ana_lane_3_quad_a_ctrl12; 5352 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_t; 5353 5354 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_CLR(r) (r).ana_lane_3_quad_a_ctrl12[0] = 0 5355 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_SET(r,d) (r).ana_lane_3_quad_a_ctrl12[0] = d 5356 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_GET(r) (r).ana_lane_3_quad_a_ctrl12[0] 5357 5358 /* 5359 * These macros can be used to access individual fields. 5360 */ 5361 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_a_ctrl12[0]) >> 12) & 0x1) 5362 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_a_ctrl12[0]=(((r).ana_lane_3_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 5363 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_a_ctrl12[0]) >> 8) & 0xf) 5364 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_a_ctrl12[0]=(((r).ana_lane_3_quad_a_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 5365 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_a_ctrl12[0]) >> 4) & 0x1) 5366 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_a_ctrl12[0]=(((r).ana_lane_3_quad_a_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 5367 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_a_ctrl12[0]) & 0xf) 5368 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_a_ctrl12[0]=(((r).ana_lane_3_quad_a_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 5369 5370 /* 5371 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL12. 5372 */ 5373 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r,_r._ana_lane_3_quad_a_ctrl12) 5374 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r,_r._ana_lane_3_quad_a_ctrl12) 5375 5376 /* 5377 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5378 * will be redefined without the chip prefix for easier programming. 5379 * If multiple chips will be programmed in the same source file, then you should 5380 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5381 * and refer to the fully qualified versions. 5382 */ 5383 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5384 5385 #define ANA_LANE_3_QUAD_A_CTRL12r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r 5386 #define ANA_LANE_3_QUAD_A_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_SIZE 5387 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_t ANA_LANE_3_QUAD_A_CTRL12r_t; 5388 #define ANA_LANE_3_QUAD_A_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_CLR 5389 #define ANA_LANE_3_QUAD_A_CTRL12r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_SET 5390 #define ANA_LANE_3_QUAD_A_CTRL12r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_GET 5391 #define ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_GET 5392 #define ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRCf_SET 5393 #define ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_GET 5394 #define ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_DRV_RESCAL_FRC_VALf_SET 5395 #define ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRCf_GET 5396 #define ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRCf_SET 5397 #define ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_GET 5398 #define ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r_LA_RESCAL_FRC_VALf_SET 5399 #define READ_ANA_LANE_3_QUAD_A_CTRL12r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL12r 5400 #define WRITE_ANA_LANE_3_QUAD_A_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL12r 5401 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL12r 5402 5403 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5404 /******************************************************************************* 5405 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL12r' 5406 */ 5407 5408 5409 5410 5411 /******************************************************************************* 5412 * CHIP: BCMI_HURACAN 5413 * REGISTER: ANA_LANE_3_QUAD_A_CTRL13 5414 * BLOCKS: ANA_LANE_3_QUAD_A 5415 * REGADDR: 0x880d 5416 * DEVAD: 1 5417 * DESC: control registers 0 5418 * RESETVAL: 0x0 (0) 5419 * ACCESS: R/W 5420 * FIELDS: 5421 * CTLE_RESCAL_FRC_VAL 5422 * CTLE_RESCAL_FRC 5423 */ 5424 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r (0x0001880d | PHYMOD_REG_ACC_RAW) 5425 5426 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_SIZE 4 5427 5428 /* 5429 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL13. 5430 */ 5431 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_s { 5432 uint32_t v[1]; 5433 uint32_t ana_lane_3_quad_a_ctrl13[1]; 5434 uint32_t _ana_lane_3_quad_a_ctrl13; 5435 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_t; 5436 5437 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CLR(r) (r).ana_lane_3_quad_a_ctrl13[0] = 0 5438 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_SET(r,d) (r).ana_lane_3_quad_a_ctrl13[0] = d 5439 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_GET(r) (r).ana_lane_3_quad_a_ctrl13[0] 5440 5441 /* 5442 * These macros can be used to access individual fields. 5443 */ 5444 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_a_ctrl13[0]) >> 4) & 0x1) 5445 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_a_ctrl13[0]=(((r).ana_lane_3_quad_a_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 5446 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_a_ctrl13[0]) & 0xf) 5447 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_a_ctrl13[0]=(((r).ana_lane_3_quad_a_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 5448 5449 /* 5450 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL13. 5451 */ 5452 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r,_r._ana_lane_3_quad_a_ctrl13) 5453 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r,_r._ana_lane_3_quad_a_ctrl13) 5454 5455 /* 5456 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5457 * will be redefined without the chip prefix for easier programming. 5458 * If multiple chips will be programmed in the same source file, then you should 5459 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5460 * and refer to the fully qualified versions. 5461 */ 5462 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5463 5464 #define ANA_LANE_3_QUAD_A_CTRL13r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r 5465 #define ANA_LANE_3_QUAD_A_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_SIZE 5466 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_t ANA_LANE_3_QUAD_A_CTRL13r_t; 5467 #define ANA_LANE_3_QUAD_A_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CLR 5468 #define ANA_LANE_3_QUAD_A_CTRL13r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_SET 5469 #define ANA_LANE_3_QUAD_A_CTRL13r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_GET 5470 #define ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_GET 5471 #define ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRCf_SET 5472 #define ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 5473 #define ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 5474 #define READ_ANA_LANE_3_QUAD_A_CTRL13r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL13r 5475 #define WRITE_ANA_LANE_3_QUAD_A_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL13r 5476 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL13r 5477 5478 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5479 /******************************************************************************* 5480 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL13r' 5481 */ 5482 5483 5484 5485 5486 /******************************************************************************* 5487 * CHIP: BCMI_HURACAN 5488 * REGISTER: ANA_LANE_3_QUAD_A_CTRL14 5489 * BLOCKS: ANA_LANE_3_QUAD_A 5490 * REGADDR: 0x880e 5491 * DEVAD: 1 5492 * DESC: control registers 0 5493 * RESETVAL: 0x0 (0) 5494 * ACCESS: R/W 5495 * FIELDS: 5496 * TX_IDLE_FRC_VAL 5497 * TX_IDLE_FRC 5498 * RXSD_IDLE_OVRD 5499 */ 5500 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r (0x0001880e | PHYMOD_REG_ACC_RAW) 5501 5502 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_SIZE 4 5503 5504 /* 5505 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL14. 5506 */ 5507 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_s { 5508 uint32_t v[1]; 5509 uint32_t ana_lane_3_quad_a_ctrl14[1]; 5510 uint32_t _ana_lane_3_quad_a_ctrl14; 5511 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_t; 5512 5513 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_CLR(r) (r).ana_lane_3_quad_a_ctrl14[0] = 0 5514 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_SET(r,d) (r).ana_lane_3_quad_a_ctrl14[0] = d 5515 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_GET(r) (r).ana_lane_3_quad_a_ctrl14[0] 5516 5517 /* 5518 * These macros can be used to access individual fields. 5519 */ 5520 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_3_quad_a_ctrl14[0]) >> 4) & 0x1) 5521 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_3_quad_a_ctrl14[0]=(((r).ana_lane_3_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 5522 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_3_quad_a_ctrl14[0]) >> 1) & 0x1) 5523 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_3_quad_a_ctrl14[0]=(((r).ana_lane_3_quad_a_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 5524 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_3_quad_a_ctrl14[0]) & 0x1) 5525 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_a_ctrl14[0]=(((r).ana_lane_3_quad_a_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 5526 5527 /* 5528 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL14. 5529 */ 5530 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r,_r._ana_lane_3_quad_a_ctrl14) 5531 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r,_r._ana_lane_3_quad_a_ctrl14) 5532 5533 /* 5534 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5535 * will be redefined without the chip prefix for easier programming. 5536 * If multiple chips will be programmed in the same source file, then you should 5537 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5538 * and refer to the fully qualified versions. 5539 */ 5540 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5541 5542 #define ANA_LANE_3_QUAD_A_CTRL14r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r 5543 #define ANA_LANE_3_QUAD_A_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_SIZE 5544 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_t ANA_LANE_3_QUAD_A_CTRL14r_t; 5545 #define ANA_LANE_3_QUAD_A_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_CLR 5546 #define ANA_LANE_3_QUAD_A_CTRL14r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_SET 5547 #define ANA_LANE_3_QUAD_A_CTRL14r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_GET 5548 #define ANA_LANE_3_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_GET 5549 #define ANA_LANE_3_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_RXSD_IDLE_OVRDf_SET 5550 #define ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRCf_GET 5551 #define ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRCf_SET 5552 #define ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_GET 5553 #define ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r_TX_IDLE_FRC_VALf_SET 5554 #define READ_ANA_LANE_3_QUAD_A_CTRL14r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL14r 5555 #define WRITE_ANA_LANE_3_QUAD_A_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL14r 5556 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL14r 5557 5558 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5559 /******************************************************************************* 5560 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL14r' 5561 */ 5562 5563 5564 5565 5566 /******************************************************************************* 5567 * CHIP: BCMI_HURACAN 5568 * REGISTER: ANA_LANE_3_QUAD_A_CTRL15 5569 * BLOCKS: ANA_LANE_3_QUAD_A 5570 * REGADDR: 0x880f 5571 * DEVAD: 1 5572 * DESC: sigdet filter settings 0 5573 * RESETVAL: 0x0 (0) 5574 * ACCESS: R/W 5575 * FIELDS: 5576 * SIGDET_DIS 5577 * SIGDET_1US_EN 5578 * SIGDET_FRC_VAL 5579 * SIGDET_FRC 5580 * HOLD_LOS_COUNT 5581 * HOLD_SD_COUNT 5582 */ 5583 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r (0x0001880f | PHYMOD_REG_ACC_RAW) 5584 5585 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIZE 4 5586 5587 /* 5588 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL15. 5589 */ 5590 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_s { 5591 uint32_t v[1]; 5592 uint32_t ana_lane_3_quad_a_ctrl15[1]; 5593 uint32_t _ana_lane_3_quad_a_ctrl15; 5594 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_t; 5595 5596 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_CLR(r) (r).ana_lane_3_quad_a_ctrl15[0] = 0 5597 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SET(r,d) (r).ana_lane_3_quad_a_ctrl15[0] = d 5598 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_GET(r) (r).ana_lane_3_quad_a_ctrl15[0] 5599 5600 /* 5601 * These macros can be used to access individual fields. 5602 */ 5603 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_a_ctrl15[0]) >> 8) & 0x7) 5604 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_a_ctrl15[0]=(((r).ana_lane_3_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 5605 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_3_quad_a_ctrl15[0]) >> 4) & 0x7) 5606 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_a_ctrl15[0]=(((r).ana_lane_3_quad_a_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 5607 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_3_quad_a_ctrl15[0]) >> 3) & 0x1) 5608 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_3_quad_a_ctrl15[0]=(((r).ana_lane_3_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 5609 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_a_ctrl15[0]) >> 2) & 0x1) 5610 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_a_ctrl15[0]=(((r).ana_lane_3_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 5611 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_3_quad_a_ctrl15[0]) >> 1) & 0x1) 5612 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_3_quad_a_ctrl15[0]=(((r).ana_lane_3_quad_a_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 5613 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_3_quad_a_ctrl15[0]) & 0x1) 5614 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_3_quad_a_ctrl15[0]=(((r).ana_lane_3_quad_a_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 5615 5616 /* 5617 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL15. 5618 */ 5619 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r,_r._ana_lane_3_quad_a_ctrl15) 5620 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r,_r._ana_lane_3_quad_a_ctrl15) 5621 5622 /* 5623 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5624 * will be redefined without the chip prefix for easier programming. 5625 * If multiple chips will be programmed in the same source file, then you should 5626 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5627 * and refer to the fully qualified versions. 5628 */ 5629 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5630 5631 #define ANA_LANE_3_QUAD_A_CTRL15r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r 5632 #define ANA_LANE_3_QUAD_A_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIZE 5633 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_t ANA_LANE_3_QUAD_A_CTRL15r_t; 5634 #define ANA_LANE_3_QUAD_A_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_CLR 5635 #define ANA_LANE_3_QUAD_A_CTRL15r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SET 5636 #define ANA_LANE_3_QUAD_A_CTRL15r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_GET 5637 #define ANA_LANE_3_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_SD_COUNTf_GET 5638 #define ANA_LANE_3_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_SD_COUNTf_SET 5639 #define ANA_LANE_3_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_GET 5640 #define ANA_LANE_3_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_HOLD_LOS_COUNTf_SET 5641 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRCf_GET 5642 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRCf_SET 5643 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRC_VALf_GET 5644 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_FRC_VALf_SET 5645 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_1US_ENf_GET 5646 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_1US_ENf_SET 5647 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_DISf_GET 5648 #define ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r_SIGDET_DISf_SET 5649 #define READ_ANA_LANE_3_QUAD_A_CTRL15r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL15r 5650 #define WRITE_ANA_LANE_3_QUAD_A_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL15r 5651 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL15r 5652 5653 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5654 /******************************************************************************* 5655 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL15r' 5656 */ 5657 5658 5659 5660 5661 /******************************************************************************* 5662 * CHIP: BCMI_HURACAN 5663 * REGISTER: ANA_LANE_3_QUAD_A_CTRL16 5664 * BLOCKS: ANA_LANE_3_QUAD_A 5665 * REGADDR: 0x8810 5666 * DEVAD: 1 5667 * DESC: sigdet filter settings 1 5668 * RESETVAL: 0x0 (0) 5669 * ACCESS: R/W 5670 * FIELDS: 5671 * LOS_COUNT 5672 * SD_COUNT 5673 */ 5674 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r (0x00018810 | PHYMOD_REG_ACC_RAW) 5675 5676 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SIZE 4 5677 5678 /* 5679 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_CTRL16. 5680 */ 5681 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_s { 5682 uint32_t v[1]; 5683 uint32_t ana_lane_3_quad_a_ctrl16[1]; 5684 uint32_t _ana_lane_3_quad_a_ctrl16; 5685 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_t; 5686 5687 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_CLR(r) (r).ana_lane_3_quad_a_ctrl16[0] = 0 5688 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SET(r,d) (r).ana_lane_3_quad_a_ctrl16[0] = d 5689 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_GET(r) (r).ana_lane_3_quad_a_ctrl16[0] 5690 5691 /* 5692 * These macros can be used to access individual fields. 5693 */ 5694 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_a_ctrl16[0]) >> 8) & 0x1f) 5695 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_a_ctrl16[0]=(((r).ana_lane_3_quad_a_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 5696 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_3_quad_a_ctrl16[0]) & 0x1f) 5697 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_a_ctrl16[0]=(((r).ana_lane_3_quad_a_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 5698 5699 /* 5700 * These macros can be used to access ANA_LANE_3_QUAD_A_CTRL16. 5701 */ 5702 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r,_r._ana_lane_3_quad_a_ctrl16) 5703 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r,_r._ana_lane_3_quad_a_ctrl16) 5704 5705 /* 5706 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5707 * will be redefined without the chip prefix for easier programming. 5708 * If multiple chips will be programmed in the same source file, then you should 5709 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5710 * and refer to the fully qualified versions. 5711 */ 5712 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5713 5714 #define ANA_LANE_3_QUAD_A_CTRL16r BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r 5715 #define ANA_LANE_3_QUAD_A_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SIZE 5716 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_t ANA_LANE_3_QUAD_A_CTRL16r_t; 5717 #define ANA_LANE_3_QUAD_A_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_CLR 5718 #define ANA_LANE_3_QUAD_A_CTRL16r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SET 5719 #define ANA_LANE_3_QUAD_A_CTRL16r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_GET 5720 #define ANA_LANE_3_QUAD_A_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SD_COUNTf_GET 5721 #define ANA_LANE_3_QUAD_A_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_SD_COUNTf_SET 5722 #define ANA_LANE_3_QUAD_A_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_LOS_COUNTf_GET 5723 #define ANA_LANE_3_QUAD_A_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r_LOS_COUNTf_SET 5724 #define READ_ANA_LANE_3_QUAD_A_CTRL16r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_CTRL16r 5725 #define WRITE_ANA_LANE_3_QUAD_A_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_CTRL16r 5726 #define MODIFY_ANA_LANE_3_QUAD_A_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_CTRL16r 5727 5728 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5729 /******************************************************************************* 5730 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_CTRL16r' 5731 */ 5732 5733 5734 5735 5736 /******************************************************************************* 5737 * CHIP: BCMI_HURACAN 5738 * REGISTER: ANA_LANE_3_QUAD_A_STATUS0 5739 * BLOCKS: ANA_LANE_3_QUAD_A 5740 * REGADDR: 0x8820 5741 * DEVAD: 1 5742 * DESC: status registers 0 5743 * RESETVAL: 0x0 (0) 5744 * ACCESS: R/W 5745 * FIELDS: 5746 * O_RX_SIGDET 5747 * DG_RX_SIGDET 5748 */ 5749 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r (0x00018820 | PHYMOD_REG_ACC_RAW) 5750 5751 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_SIZE 4 5752 5753 /* 5754 * This structure should be used to declare and program ANA_LANE_3_QUAD_A_STATUS0. 5755 */ 5756 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_s { 5757 uint32_t v[1]; 5758 uint32_t ana_lane_3_quad_a_status0[1]; 5759 uint32_t _ana_lane_3_quad_a_status0; 5760 } BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_t; 5761 5762 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_CLR(r) (r).ana_lane_3_quad_a_status0[0] = 0 5763 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_SET(r,d) (r).ana_lane_3_quad_a_status0[0] = d 5764 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_GET(r) (r).ana_lane_3_quad_a_status0[0] 5765 5766 /* 5767 * These macros can be used to access individual fields. 5768 */ 5769 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_3_quad_a_status0[0]) >> 1) & 0x1) 5770 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_a_status0[0]=(((r).ana_lane_3_quad_a_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 5771 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_3_quad_a_status0[0]) & 0x1) 5772 #define BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_a_status0[0]=(((r).ana_lane_3_quad_a_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 5773 5774 /* 5775 * These macros can be used to access ANA_LANE_3_QUAD_A_STATUS0. 5776 */ 5777 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r,_r._ana_lane_3_quad_a_status0) 5778 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r,_r._ana_lane_3_quad_a_status0) 5779 5780 /* 5781 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5782 * will be redefined without the chip prefix for easier programming. 5783 * If multiple chips will be programmed in the same source file, then you should 5784 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5785 * and refer to the fully qualified versions. 5786 */ 5787 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5788 5789 #define ANA_LANE_3_QUAD_A_STATUS0r BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r 5790 #define ANA_LANE_3_QUAD_A_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_SIZE 5791 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_t ANA_LANE_3_QUAD_A_STATUS0r_t; 5792 #define ANA_LANE_3_QUAD_A_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_CLR 5793 #define ANA_LANE_3_QUAD_A_STATUS0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_SET 5794 #define ANA_LANE_3_QUAD_A_STATUS0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_GET 5795 #define ANA_LANE_3_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_DG_RX_SIGDETf_GET 5796 #define ANA_LANE_3_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_DG_RX_SIGDETf_SET 5797 #define ANA_LANE_3_QUAD_A_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_O_RX_SIGDETf_GET 5798 #define ANA_LANE_3_QUAD_A_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r_O_RX_SIGDETf_SET 5799 #define READ_ANA_LANE_3_QUAD_A_STATUS0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_A_STATUS0r 5800 #define WRITE_ANA_LANE_3_QUAD_A_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_A_STATUS0r 5801 #define MODIFY_ANA_LANE_3_QUAD_A_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_A_STATUS0r 5802 5803 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5804 /******************************************************************************* 5805 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_A_STATUS0r' 5806 */ 5807 5808 5809 5810 5811 /******************************************************************************* 5812 * CHIP: BCMI_HURACAN 5813 * REGISTER: ANA_LANE_0_QUAD_B_CTRL0 5814 * BLOCKS: ANA_LANE_0_QUAD_B 5815 * REGADDR: 0x9100 5816 * DEVAD: 1 5817 * DESC: control registers 0 5818 * RESETVAL: 0x0 (0) 5819 * ACCESS: R/W 5820 * FIELDS: 5821 * RXTX_PWRDN 5822 * RX_SIGDET_BYPASS 5823 * RX_SIGDET_PWRDN 5824 * RX_SIGDECT_12GMODE 5825 * DC_COUPLE 5826 */ 5827 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r (0x00019100 | PHYMOD_REG_ACC_RAW) 5828 5829 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_SIZE 4 5830 5831 /* 5832 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL0. 5833 */ 5834 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_s { 5835 uint32_t v[1]; 5836 uint32_t ana_lane_0_quad_b_ctrl0[1]; 5837 uint32_t _ana_lane_0_quad_b_ctrl0; 5838 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_t; 5839 5840 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_CLR(r) (r).ana_lane_0_quad_b_ctrl0[0] = 0 5841 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_SET(r,d) (r).ana_lane_0_quad_b_ctrl0[0] = d 5842 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_GET(r) (r).ana_lane_0_quad_b_ctrl0[0] 5843 5844 /* 5845 * These macros can be used to access individual fields. 5846 */ 5847 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_0_quad_b_ctrl0[0]) >> 4) & 0x1) 5848 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_0_quad_b_ctrl0[0]=(((r).ana_lane_0_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 5849 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_0_quad_b_ctrl0[0]) >> 3) & 0x1) 5850 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_0_quad_b_ctrl0[0]=(((r).ana_lane_0_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 5851 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_0_quad_b_ctrl0[0]) >> 2) & 0x1) 5852 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_0_quad_b_ctrl0[0]=(((r).ana_lane_0_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 5853 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_0_quad_b_ctrl0[0]) >> 1) & 0x1) 5854 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_0_quad_b_ctrl0[0]=(((r).ana_lane_0_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 5855 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_0_quad_b_ctrl0[0]) & 0x1) 5856 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_0_quad_b_ctrl0[0]=(((r).ana_lane_0_quad_b_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 5857 5858 /* 5859 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL0. 5860 */ 5861 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r,_r._ana_lane_0_quad_b_ctrl0) 5862 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r,_r._ana_lane_0_quad_b_ctrl0) 5863 5864 /* 5865 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5866 * will be redefined without the chip prefix for easier programming. 5867 * If multiple chips will be programmed in the same source file, then you should 5868 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5869 * and refer to the fully qualified versions. 5870 */ 5871 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5872 5873 #define ANA_LANE_0_QUAD_B_CTRL0r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r 5874 #define ANA_LANE_0_QUAD_B_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_SIZE 5875 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_t ANA_LANE_0_QUAD_B_CTRL0r_t; 5876 #define ANA_LANE_0_QUAD_B_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_CLR 5877 #define ANA_LANE_0_QUAD_B_CTRL0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_SET 5878 #define ANA_LANE_0_QUAD_B_CTRL0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_GET 5879 #define ANA_LANE_0_QUAD_B_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_DC_COUPLEf_GET 5880 #define ANA_LANE_0_QUAD_B_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_DC_COUPLEf_SET 5881 #define ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET 5882 #define ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET 5883 #define ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET 5884 #define ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET 5885 #define ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET 5886 #define ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET 5887 #define ANA_LANE_0_QUAD_B_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RXTX_PWRDNf_GET 5888 #define ANA_LANE_0_QUAD_B_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r_RXTX_PWRDNf_SET 5889 #define READ_ANA_LANE_0_QUAD_B_CTRL0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL0r 5890 #define WRITE_ANA_LANE_0_QUAD_B_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL0r 5891 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL0r 5892 5893 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5894 /******************************************************************************* 5895 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL0r' 5896 */ 5897 5898 5899 5900 5901 /******************************************************************************* 5902 * CHIP: BCMI_HURACAN 5903 * REGISTER: ANA_LANE_0_QUAD_B_CTRL1 5904 * BLOCKS: ANA_LANE_0_QUAD_B 5905 * REGADDR: 0x9101 5906 * DEVAD: 1 5907 * DESC: control registers 0 5908 * RESETVAL: 0x0 (0) 5909 * ACCESS: R/W 5910 * FIELDS: 5911 * RX_SIGDET_THRESHOLD 5912 * REF_OCL 5913 * OCL_PWRDN 5914 * OCL_DISABLE_LOOP 5915 * RXTX_RESERVED_FOR_15_12 5916 */ 5917 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r (0x00019101 | PHYMOD_REG_ACC_RAW) 5918 5919 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_SIZE 4 5920 5921 /* 5922 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL1. 5923 */ 5924 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_s { 5925 uint32_t v[1]; 5926 uint32_t ana_lane_0_quad_b_ctrl1[1]; 5927 uint32_t _ana_lane_0_quad_b_ctrl1; 5928 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_t; 5929 5930 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_CLR(r) (r).ana_lane_0_quad_b_ctrl1[0] = 0 5931 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_SET(r,d) (r).ana_lane_0_quad_b_ctrl1[0] = d 5932 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_GET(r) (r).ana_lane_0_quad_b_ctrl1[0] 5933 5934 /* 5935 * These macros can be used to access individual fields. 5936 */ 5937 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_0_quad_b_ctrl1[0]) >> 12) & 0xf) 5938 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_0_quad_b_ctrl1[0]=(((r).ana_lane_0_quad_b_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 5939 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_0_quad_b_ctrl1[0]) >> 9) & 0x1) 5940 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_0_quad_b_ctrl1[0]=(((r).ana_lane_0_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 5941 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_0_quad_b_ctrl1[0]) >> 8) & 0x1) 5942 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_0_quad_b_ctrl1[0]=(((r).ana_lane_0_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 5943 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_0_quad_b_ctrl1[0]) >> 4) & 0x3) 5944 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_0_quad_b_ctrl1[0]=(((r).ana_lane_0_quad_b_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 5945 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_0_quad_b_ctrl1[0]) & 0x7) 5946 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_0_quad_b_ctrl1[0]=(((r).ana_lane_0_quad_b_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 5947 5948 /* 5949 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL1. 5950 */ 5951 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r,_r._ana_lane_0_quad_b_ctrl1) 5952 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r,_r._ana_lane_0_quad_b_ctrl1) 5953 5954 /* 5955 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 5956 * will be redefined without the chip prefix for easier programming. 5957 * If multiple chips will be programmed in the same source file, then you should 5958 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 5959 * and refer to the fully qualified versions. 5960 */ 5961 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 5962 5963 #define ANA_LANE_0_QUAD_B_CTRL1r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r 5964 #define ANA_LANE_0_QUAD_B_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_SIZE 5965 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_t ANA_LANE_0_QUAD_B_CTRL1r_t; 5966 #define ANA_LANE_0_QUAD_B_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_CLR 5967 #define ANA_LANE_0_QUAD_B_CTRL1r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_SET 5968 #define ANA_LANE_0_QUAD_B_CTRL1r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_GET 5969 #define ANA_LANE_0_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 5970 #define ANA_LANE_0_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 5971 #define ANA_LANE_0_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET 5972 #define ANA_LANE_0_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET 5973 #define ANA_LANE_0_QUAD_B_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_PWRDNf_GET 5974 #define ANA_LANE_0_QUAD_B_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_OCL_PWRDNf_SET 5975 #define ANA_LANE_0_QUAD_B_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_REF_OCLf_GET 5976 #define ANA_LANE_0_QUAD_B_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_REF_OCLf_SET 5977 #define ANA_LANE_0_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET 5978 #define ANA_LANE_0_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET 5979 #define READ_ANA_LANE_0_QUAD_B_CTRL1r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL1r 5980 #define WRITE_ANA_LANE_0_QUAD_B_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL1r 5981 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL1r 5982 5983 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 5984 /******************************************************************************* 5985 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL1r' 5986 */ 5987 5988 5989 5990 5991 /******************************************************************************* 5992 * CHIP: BCMI_HURACAN 5993 * REGISTER: ANA_LANE_0_QUAD_B_CTRL2 5994 * BLOCKS: ANA_LANE_0_QUAD_B 5995 * REGADDR: 0x9102 5996 * DEVAD: 1 5997 * DESC: control registers 0 5998 * RESETVAL: 0x0 (0) 5999 * ACCESS: R/W 6000 * FIELDS: 6001 * CTLE_ENB_NEGIMP 6002 * CTLE_ENB_NEGCAP 6003 */ 6004 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r (0x00019102 | PHYMOD_REG_ACC_RAW) 6005 6006 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_SIZE 4 6007 6008 /* 6009 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL2. 6010 */ 6011 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_s { 6012 uint32_t v[1]; 6013 uint32_t ana_lane_0_quad_b_ctrl2[1]; 6014 uint32_t _ana_lane_0_quad_b_ctrl2; 6015 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_t; 6016 6017 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CLR(r) (r).ana_lane_0_quad_b_ctrl2[0] = 0 6018 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_SET(r,d) (r).ana_lane_0_quad_b_ctrl2[0] = d 6019 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_GET(r) (r).ana_lane_0_quad_b_ctrl2[0] 6020 6021 /* 6022 * These macros can be used to access individual fields. 6023 */ 6024 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_0_quad_b_ctrl2[0]) >> 8) & 0x7f) 6025 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_0_quad_b_ctrl2[0]=(((r).ana_lane_0_quad_b_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 6026 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_0_quad_b_ctrl2[0]) & 0x7f) 6027 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_0_quad_b_ctrl2[0]=(((r).ana_lane_0_quad_b_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 6028 6029 /* 6030 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL2. 6031 */ 6032 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r,_r._ana_lane_0_quad_b_ctrl2) 6033 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r,_r._ana_lane_0_quad_b_ctrl2) 6034 6035 /* 6036 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6037 * will be redefined without the chip prefix for easier programming. 6038 * If multiple chips will be programmed in the same source file, then you should 6039 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6040 * and refer to the fully qualified versions. 6041 */ 6042 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6043 6044 #define ANA_LANE_0_QUAD_B_CTRL2r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r 6045 #define ANA_LANE_0_QUAD_B_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_SIZE 6046 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_t ANA_LANE_0_QUAD_B_CTRL2r_t; 6047 #define ANA_LANE_0_QUAD_B_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CLR 6048 #define ANA_LANE_0_QUAD_B_CTRL2r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_SET 6049 #define ANA_LANE_0_QUAD_B_CTRL2r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_GET 6050 #define ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET 6051 #define ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET 6052 #define ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET 6053 #define ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET 6054 #define READ_ANA_LANE_0_QUAD_B_CTRL2r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL2r 6055 #define WRITE_ANA_LANE_0_QUAD_B_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL2r 6056 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL2r 6057 6058 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6059 /******************************************************************************* 6060 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL2r' 6061 */ 6062 6063 6064 6065 6066 /******************************************************************************* 6067 * CHIP: BCMI_HURACAN 6068 * REGISTER: ANA_LANE_0_QUAD_B_CTRL3 6069 * BLOCKS: ANA_LANE_0_QUAD_B 6070 * REGADDR: 0x9103 6071 * DEVAD: 1 6072 * DESC: control registers 0 6073 * RESETVAL: 0x0 (0) 6074 * ACCESS: R/W 6075 * FIELDS: 6076 * CTLE_EN_NEGRES 6077 * CTLE_EQSEL 6078 */ 6079 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r (0x00019103 | PHYMOD_REG_ACC_RAW) 6080 6081 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_SIZE 4 6082 6083 /* 6084 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL3. 6085 */ 6086 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_s { 6087 uint32_t v[1]; 6088 uint32_t ana_lane_0_quad_b_ctrl3[1]; 6089 uint32_t _ana_lane_0_quad_b_ctrl3; 6090 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_t; 6091 6092 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CLR(r) (r).ana_lane_0_quad_b_ctrl3[0] = 0 6093 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_SET(r,d) (r).ana_lane_0_quad_b_ctrl3[0] = d 6094 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_GET(r) (r).ana_lane_0_quad_b_ctrl3[0] 6095 6096 /* 6097 * These macros can be used to access individual fields. 6098 */ 6099 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_0_quad_b_ctrl3[0]) >> 8) & 0xff) 6100 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_0_quad_b_ctrl3[0]=(((r).ana_lane_0_quad_b_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 6101 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_0_quad_b_ctrl3[0]) & 0x7f) 6102 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_0_quad_b_ctrl3[0]=(((r).ana_lane_0_quad_b_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 6103 6104 /* 6105 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL3. 6106 */ 6107 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r,_r._ana_lane_0_quad_b_ctrl3) 6108 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r,_r._ana_lane_0_quad_b_ctrl3) 6109 6110 /* 6111 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6112 * will be redefined without the chip prefix for easier programming. 6113 * If multiple chips will be programmed in the same source file, then you should 6114 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6115 * and refer to the fully qualified versions. 6116 */ 6117 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6118 6119 #define ANA_LANE_0_QUAD_B_CTRL3r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r 6120 #define ANA_LANE_0_QUAD_B_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_SIZE 6121 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_t ANA_LANE_0_QUAD_B_CTRL3r_t; 6122 #define ANA_LANE_0_QUAD_B_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CLR 6123 #define ANA_LANE_0_QUAD_B_CTRL3r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_SET 6124 #define ANA_LANE_0_QUAD_B_CTRL3r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_GET 6125 #define ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EQSELf_GET 6126 #define ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EQSELf_SET 6127 #define ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET 6128 #define ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET 6129 #define READ_ANA_LANE_0_QUAD_B_CTRL3r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL3r 6130 #define WRITE_ANA_LANE_0_QUAD_B_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL3r 6131 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL3r 6132 6133 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6134 /******************************************************************************* 6135 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL3r' 6136 */ 6137 6138 6139 6140 6141 /******************************************************************************* 6142 * CHIP: BCMI_HURACAN 6143 * REGISTER: ANA_LANE_0_QUAD_B_CTRL4 6144 * BLOCKS: ANA_LANE_0_QUAD_B 6145 * REGADDR: 0x9104 6146 * DEVAD: 1 6147 * DESC: control registers 0 6148 * RESETVAL: 0x0 (0) 6149 * ACCESS: R/W 6150 * FIELDS: 6151 * CTLE_LZEN 6152 * RXTX_RESERVED_FOR_59_52 6153 */ 6154 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r (0x00019104 | PHYMOD_REG_ACC_RAW) 6155 6156 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_SIZE 4 6157 6158 /* 6159 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL4. 6160 */ 6161 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_s { 6162 uint32_t v[1]; 6163 uint32_t ana_lane_0_quad_b_ctrl4[1]; 6164 uint32_t _ana_lane_0_quad_b_ctrl4; 6165 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_t; 6166 6167 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_CLR(r) (r).ana_lane_0_quad_b_ctrl4[0] = 0 6168 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_SET(r,d) (r).ana_lane_0_quad_b_ctrl4[0] = d 6169 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_GET(r) (r).ana_lane_0_quad_b_ctrl4[0] 6170 6171 /* 6172 * These macros can be used to access individual fields. 6173 */ 6174 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_0_quad_b_ctrl4[0]) >> 4) & 0xff) 6175 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_0_quad_b_ctrl4[0]=(((r).ana_lane_0_quad_b_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 6176 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_0_quad_b_ctrl4[0]) & 0x1) 6177 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_0_quad_b_ctrl4[0]=(((r).ana_lane_0_quad_b_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 6178 6179 /* 6180 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL4. 6181 */ 6182 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r,_r._ana_lane_0_quad_b_ctrl4) 6183 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r,_r._ana_lane_0_quad_b_ctrl4) 6184 6185 /* 6186 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6187 * will be redefined without the chip prefix for easier programming. 6188 * If multiple chips will be programmed in the same source file, then you should 6189 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6190 * and refer to the fully qualified versions. 6191 */ 6192 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6193 6194 #define ANA_LANE_0_QUAD_B_CTRL4r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r 6195 #define ANA_LANE_0_QUAD_B_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_SIZE 6196 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_t ANA_LANE_0_QUAD_B_CTRL4r_t; 6197 #define ANA_LANE_0_QUAD_B_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_CLR 6198 #define ANA_LANE_0_QUAD_B_CTRL4r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_SET 6199 #define ANA_LANE_0_QUAD_B_CTRL4r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_GET 6200 #define ANA_LANE_0_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 6201 #define ANA_LANE_0_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 6202 #define ANA_LANE_0_QUAD_B_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_CTLE_LZENf_GET 6203 #define ANA_LANE_0_QUAD_B_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r_CTLE_LZENf_SET 6204 #define READ_ANA_LANE_0_QUAD_B_CTRL4r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL4r 6205 #define WRITE_ANA_LANE_0_QUAD_B_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL4r 6206 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL4r 6207 6208 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6209 /******************************************************************************* 6210 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL4r' 6211 */ 6212 6213 6214 6215 6216 /******************************************************************************* 6217 * CHIP: BCMI_HURACAN 6218 * REGISTER: ANA_LANE_0_QUAD_B_CTRL5 6219 * BLOCKS: ANA_LANE_0_QUAD_B 6220 * REGADDR: 0x9105 6221 * DEVAD: 1 6222 * DESC: control registers 0 6223 * RESETVAL: 0x0 (0) 6224 * ACCESS: R/W 6225 * FIELDS: 6226 * CTLE_LOPEAKING 6227 * CTLE_PD 6228 * LA_GCTRL 6229 */ 6230 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r (0x00019105 | PHYMOD_REG_ACC_RAW) 6231 6232 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_SIZE 4 6233 6234 /* 6235 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL5. 6236 */ 6237 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_s { 6238 uint32_t v[1]; 6239 uint32_t ana_lane_0_quad_b_ctrl5[1]; 6240 uint32_t _ana_lane_0_quad_b_ctrl5; 6241 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_t; 6242 6243 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CLR(r) (r).ana_lane_0_quad_b_ctrl5[0] = 0 6244 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_SET(r,d) (r).ana_lane_0_quad_b_ctrl5[0] = d 6245 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_GET(r) (r).ana_lane_0_quad_b_ctrl5[0] 6246 6247 /* 6248 * These macros can be used to access individual fields. 6249 */ 6250 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_0_quad_b_ctrl5[0]) >> 4) & 0x3ff) 6251 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_0_quad_b_ctrl5[0]=(((r).ana_lane_0_quad_b_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 6252 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_0_quad_b_ctrl5[0]) >> 1) & 0x1) 6253 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_0_quad_b_ctrl5[0]=(((r).ana_lane_0_quad_b_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 6254 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_0_quad_b_ctrl5[0]) & 0x1) 6255 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_0_quad_b_ctrl5[0]=(((r).ana_lane_0_quad_b_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 6256 6257 /* 6258 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL5. 6259 */ 6260 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r,_r._ana_lane_0_quad_b_ctrl5) 6261 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r,_r._ana_lane_0_quad_b_ctrl5) 6262 6263 /* 6264 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6265 * will be redefined without the chip prefix for easier programming. 6266 * If multiple chips will be programmed in the same source file, then you should 6267 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6268 * and refer to the fully qualified versions. 6269 */ 6270 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6271 6272 #define ANA_LANE_0_QUAD_B_CTRL5r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r 6273 #define ANA_LANE_0_QUAD_B_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_SIZE 6274 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_t ANA_LANE_0_QUAD_B_CTRL5r_t; 6275 #define ANA_LANE_0_QUAD_B_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CLR 6276 #define ANA_LANE_0_QUAD_B_CTRL5r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_SET 6277 #define ANA_LANE_0_QUAD_B_CTRL5r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_GET 6278 #define ANA_LANE_0_QUAD_B_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_LA_GCTRLf_GET 6279 #define ANA_LANE_0_QUAD_B_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_LA_GCTRLf_SET 6280 #define ANA_LANE_0_QUAD_B_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_PDf_GET 6281 #define ANA_LANE_0_QUAD_B_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_PDf_SET 6282 #define ANA_LANE_0_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET 6283 #define ANA_LANE_0_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET 6284 #define READ_ANA_LANE_0_QUAD_B_CTRL5r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL5r 6285 #define WRITE_ANA_LANE_0_QUAD_B_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL5r 6286 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL5r 6287 6288 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6289 /******************************************************************************* 6290 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL5r' 6291 */ 6292 6293 6294 6295 6296 /******************************************************************************* 6297 * CHIP: BCMI_HURACAN 6298 * REGISTER: ANA_LANE_0_QUAD_B_CTRL6 6299 * BLOCKS: ANA_LANE_0_QUAD_B 6300 * REGADDR: 0x9106 6301 * DEVAD: 1 6302 * DESC: control registers 0 6303 * RESETVAL: 0x0 (0) 6304 * ACCESS: R/W 6305 * FIELDS: 6306 * LA_DEGAIN 6307 * LA_DETUNE 6308 */ 6309 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r (0x00019106 | PHYMOD_REG_ACC_RAW) 6310 6311 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_SIZE 4 6312 6313 /* 6314 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL6. 6315 */ 6316 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_s { 6317 uint32_t v[1]; 6318 uint32_t ana_lane_0_quad_b_ctrl6[1]; 6319 uint32_t _ana_lane_0_quad_b_ctrl6; 6320 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_t; 6321 6322 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_CLR(r) (r).ana_lane_0_quad_b_ctrl6[0] = 0 6323 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_SET(r,d) (r).ana_lane_0_quad_b_ctrl6[0] = d 6324 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_GET(r) (r).ana_lane_0_quad_b_ctrl6[0] 6325 6326 /* 6327 * These macros can be used to access individual fields. 6328 */ 6329 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_0_quad_b_ctrl6[0]) >> 8) & 0xff) 6330 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_0_quad_b_ctrl6[0]=(((r).ana_lane_0_quad_b_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 6331 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_0_quad_b_ctrl6[0]) & 0x1f) 6332 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_0_quad_b_ctrl6[0]=(((r).ana_lane_0_quad_b_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 6333 6334 /* 6335 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL6. 6336 */ 6337 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r,_r._ana_lane_0_quad_b_ctrl6) 6338 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r,_r._ana_lane_0_quad_b_ctrl6) 6339 6340 /* 6341 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6342 * will be redefined without the chip prefix for easier programming. 6343 * If multiple chips will be programmed in the same source file, then you should 6344 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6345 * and refer to the fully qualified versions. 6346 */ 6347 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6348 6349 #define ANA_LANE_0_QUAD_B_CTRL6r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r 6350 #define ANA_LANE_0_QUAD_B_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_SIZE 6351 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_t ANA_LANE_0_QUAD_B_CTRL6r_t; 6352 #define ANA_LANE_0_QUAD_B_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_CLR 6353 #define ANA_LANE_0_QUAD_B_CTRL6r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_SET 6354 #define ANA_LANE_0_QUAD_B_CTRL6r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_GET 6355 #define ANA_LANE_0_QUAD_B_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DETUNEf_GET 6356 #define ANA_LANE_0_QUAD_B_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DETUNEf_SET 6357 #define ANA_LANE_0_QUAD_B_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DEGAINf_GET 6358 #define ANA_LANE_0_QUAD_B_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r_LA_DEGAINf_SET 6359 #define READ_ANA_LANE_0_QUAD_B_CTRL6r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL6r 6360 #define WRITE_ANA_LANE_0_QUAD_B_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL6r 6361 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL6r 6362 6363 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6364 /******************************************************************************* 6365 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL6r' 6366 */ 6367 6368 6369 6370 6371 /******************************************************************************* 6372 * CHIP: BCMI_HURACAN 6373 * REGISTER: ANA_LANE_0_QUAD_B_CTRL7 6374 * BLOCKS: ANA_LANE_0_QUAD_B 6375 * REGADDR: 0x9107 6376 * DEVAD: 1 6377 * DESC: control registers 0 6378 * RESETVAL: 0x0 (0) 6379 * ACCESS: R/W 6380 * FIELDS: 6381 * LA_LIN_MODE 6382 * RX_BIAS_FB_PDN 6383 */ 6384 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r (0x00019107 | PHYMOD_REG_ACC_RAW) 6385 6386 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_SIZE 4 6387 6388 /* 6389 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL7. 6390 */ 6391 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_s { 6392 uint32_t v[1]; 6393 uint32_t ana_lane_0_quad_b_ctrl7[1]; 6394 uint32_t _ana_lane_0_quad_b_ctrl7; 6395 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_t; 6396 6397 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_CLR(r) (r).ana_lane_0_quad_b_ctrl7[0] = 0 6398 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_SET(r,d) (r).ana_lane_0_quad_b_ctrl7[0] = d 6399 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_GET(r) (r).ana_lane_0_quad_b_ctrl7[0] 6400 6401 /* 6402 * These macros can be used to access individual fields. 6403 */ 6404 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_0_quad_b_ctrl7[0]) >> 8) & 0x1) 6405 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_0_quad_b_ctrl7[0]=(((r).ana_lane_0_quad_b_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 6406 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_0_quad_b_ctrl7[0]) & 0x1f) 6407 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_0_quad_b_ctrl7[0]=(((r).ana_lane_0_quad_b_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 6408 6409 /* 6410 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL7. 6411 */ 6412 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r,_r._ana_lane_0_quad_b_ctrl7) 6413 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r,_r._ana_lane_0_quad_b_ctrl7) 6414 6415 /* 6416 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6417 * will be redefined without the chip prefix for easier programming. 6418 * If multiple chips will be programmed in the same source file, then you should 6419 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6420 * and refer to the fully qualified versions. 6421 */ 6422 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6423 6424 #define ANA_LANE_0_QUAD_B_CTRL7r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r 6425 #define ANA_LANE_0_QUAD_B_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_SIZE 6426 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_t ANA_LANE_0_QUAD_B_CTRL7r_t; 6427 #define ANA_LANE_0_QUAD_B_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_CLR 6428 #define ANA_LANE_0_QUAD_B_CTRL7r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_SET 6429 #define ANA_LANE_0_QUAD_B_CTRL7r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_GET 6430 #define ANA_LANE_0_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET 6431 #define ANA_LANE_0_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET 6432 #define ANA_LANE_0_QUAD_B_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_LA_LIN_MODEf_GET 6433 #define ANA_LANE_0_QUAD_B_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r_LA_LIN_MODEf_SET 6434 #define READ_ANA_LANE_0_QUAD_B_CTRL7r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL7r 6435 #define WRITE_ANA_LANE_0_QUAD_B_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL7r 6436 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL7r 6437 6438 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6439 /******************************************************************************* 6440 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL7r' 6441 */ 6442 6443 6444 6445 6446 /******************************************************************************* 6447 * CHIP: BCMI_HURACAN 6448 * REGISTER: ANA_LANE_0_QUAD_B_CTRL8 6449 * BLOCKS: ANA_LANE_0_QUAD_B 6450 * REGADDR: 0x9108 6451 * DEVAD: 1 6452 * DESC: control registers 0 6453 * RESETVAL: 0x0 (0) 6454 * ACCESS: R/W 6455 * FIELDS: 6456 * LA_PD 6457 * LA_PD_IDLE 6458 * RXTX_RESERVED_FOR_99_95 6459 */ 6460 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r (0x00019108 | PHYMOD_REG_ACC_RAW) 6461 6462 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_SIZE 4 6463 6464 /* 6465 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL8. 6466 */ 6467 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_s { 6468 uint32_t v[1]; 6469 uint32_t ana_lane_0_quad_b_ctrl8[1]; 6470 uint32_t _ana_lane_0_quad_b_ctrl8; 6471 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_t; 6472 6473 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_CLR(r) (r).ana_lane_0_quad_b_ctrl8[0] = 0 6474 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_SET(r,d) (r).ana_lane_0_quad_b_ctrl8[0] = d 6475 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_GET(r) (r).ana_lane_0_quad_b_ctrl8[0] 6476 6477 /* 6478 * These macros can be used to access individual fields. 6479 */ 6480 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_0_quad_b_ctrl8[0]) >> 4) & 0x1f) 6481 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_0_quad_b_ctrl8[0]=(((r).ana_lane_0_quad_b_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 6482 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_0_quad_b_ctrl8[0]) >> 1) & 0x1) 6483 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_0_quad_b_ctrl8[0]=(((r).ana_lane_0_quad_b_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 6484 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_0_quad_b_ctrl8[0]) & 0x1) 6485 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_0_quad_b_ctrl8[0]=(((r).ana_lane_0_quad_b_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 6486 6487 /* 6488 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL8. 6489 */ 6490 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r,_r._ana_lane_0_quad_b_ctrl8) 6491 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r,_r._ana_lane_0_quad_b_ctrl8) 6492 6493 /* 6494 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6495 * will be redefined without the chip prefix for easier programming. 6496 * If multiple chips will be programmed in the same source file, then you should 6497 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6498 * and refer to the fully qualified versions. 6499 */ 6500 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6501 6502 #define ANA_LANE_0_QUAD_B_CTRL8r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r 6503 #define ANA_LANE_0_QUAD_B_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_SIZE 6504 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_t ANA_LANE_0_QUAD_B_CTRL8r_t; 6505 #define ANA_LANE_0_QUAD_B_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_CLR 6506 #define ANA_LANE_0_QUAD_B_CTRL8r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_SET 6507 #define ANA_LANE_0_QUAD_B_CTRL8r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_GET 6508 #define ANA_LANE_0_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 6509 #define ANA_LANE_0_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 6510 #define ANA_LANE_0_QUAD_B_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PD_IDLEf_GET 6511 #define ANA_LANE_0_QUAD_B_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PD_IDLEf_SET 6512 #define ANA_LANE_0_QUAD_B_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PDf_GET 6513 #define ANA_LANE_0_QUAD_B_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r_LA_PDf_SET 6514 #define READ_ANA_LANE_0_QUAD_B_CTRL8r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL8r 6515 #define WRITE_ANA_LANE_0_QUAD_B_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL8r 6516 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL8r 6517 6518 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6519 /******************************************************************************* 6520 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL8r' 6521 */ 6522 6523 6524 6525 6526 /******************************************************************************* 6527 * CHIP: BCMI_HURACAN 6528 * REGISTER: ANA_LANE_0_QUAD_B_CTRL9 6529 * BLOCKS: ANA_LANE_0_QUAD_B 6530 * REGADDR: 0x9109 6531 * DEVAD: 1 6532 * DESC: control registers 0 6533 * RESETVAL: 0x0 (0) 6534 * ACCESS: R/W 6535 * FIELDS: 6536 * DRV_POST1 6537 * DLINE_SWING_1 6538 * DLINE_SWING_2 6539 * DLINE_DELAY_CTRL 6540 */ 6541 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r (0x00019109 | PHYMOD_REG_ACC_RAW) 6542 6543 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_SIZE 4 6544 6545 /* 6546 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL9. 6547 */ 6548 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_s { 6549 uint32_t v[1]; 6550 uint32_t ana_lane_0_quad_b_ctrl9[1]; 6551 uint32_t _ana_lane_0_quad_b_ctrl9; 6552 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_t; 6553 6554 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_CLR(r) (r).ana_lane_0_quad_b_ctrl9[0] = 0 6555 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_SET(r,d) (r).ana_lane_0_quad_b_ctrl9[0] = d 6556 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_GET(r) (r).ana_lane_0_quad_b_ctrl9[0] 6557 6558 /* 6559 * These macros can be used to access individual fields. 6560 */ 6561 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_0_quad_b_ctrl9[0]) >> 12) & 0x7) 6562 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_0_quad_b_ctrl9[0]=(((r).ana_lane_0_quad_b_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 6563 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_0_quad_b_ctrl9[0]) >> 8) & 0x3) 6564 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_0_quad_b_ctrl9[0]=(((r).ana_lane_0_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 6565 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_0_quad_b_ctrl9[0]) >> 4) & 0x3) 6566 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_0_quad_b_ctrl9[0]=(((r).ana_lane_0_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 6567 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_0_quad_b_ctrl9[0]) & 0xf) 6568 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_0_quad_b_ctrl9[0]=(((r).ana_lane_0_quad_b_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 6569 6570 /* 6571 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL9. 6572 */ 6573 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r,_r._ana_lane_0_quad_b_ctrl9) 6574 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r,_r._ana_lane_0_quad_b_ctrl9) 6575 6576 /* 6577 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6578 * will be redefined without the chip prefix for easier programming. 6579 * If multiple chips will be programmed in the same source file, then you should 6580 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6581 * and refer to the fully qualified versions. 6582 */ 6583 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6584 6585 #define ANA_LANE_0_QUAD_B_CTRL9r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r 6586 #define ANA_LANE_0_QUAD_B_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_SIZE 6587 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_t ANA_LANE_0_QUAD_B_CTRL9r_t; 6588 #define ANA_LANE_0_QUAD_B_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_CLR 6589 #define ANA_LANE_0_QUAD_B_CTRL9r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_SET 6590 #define ANA_LANE_0_QUAD_B_CTRL9r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_GET 6591 #define ANA_LANE_0_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET 6592 #define ANA_LANE_0_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET 6593 #define ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_2f_GET 6594 #define ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_2f_SET 6595 #define ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_1f_GET 6596 #define ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DLINE_SWING_1f_SET 6597 #define ANA_LANE_0_QUAD_B_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DRV_POST1f_GET 6598 #define ANA_LANE_0_QUAD_B_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r_DRV_POST1f_SET 6599 #define READ_ANA_LANE_0_QUAD_B_CTRL9r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL9r 6600 #define WRITE_ANA_LANE_0_QUAD_B_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL9r 6601 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL9r 6602 6603 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6604 /******************************************************************************* 6605 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL9r' 6606 */ 6607 6608 6609 6610 6611 /******************************************************************************* 6612 * CHIP: BCMI_HURACAN 6613 * REGISTER: ANA_LANE_0_QUAD_B_CTRL10 6614 * BLOCKS: ANA_LANE_0_QUAD_B 6615 * REGADDR: 0x910a 6616 * DEVAD: 1 6617 * DESC: control registers 0 6618 * RESETVAL: 0x0 (0) 6619 * ACCESS: R/W 6620 * FIELDS: 6621 * DRV_PWD 6622 * DLINE_PWD 6623 * DRV_VBSEL 6624 * DRV_MAIN 6625 * DRV_MAIN_PU 6626 */ 6627 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r (0x0001910a | PHYMOD_REG_ACC_RAW) 6628 6629 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_SIZE 4 6630 6631 /* 6632 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL10. 6633 */ 6634 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_s { 6635 uint32_t v[1]; 6636 uint32_t ana_lane_0_quad_b_ctrl10[1]; 6637 uint32_t _ana_lane_0_quad_b_ctrl10; 6638 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_t; 6639 6640 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_CLR(r) (r).ana_lane_0_quad_b_ctrl10[0] = 0 6641 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_SET(r,d) (r).ana_lane_0_quad_b_ctrl10[0] = d 6642 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_GET(r) (r).ana_lane_0_quad_b_ctrl10[0] 6643 6644 /* 6645 * These macros can be used to access individual fields. 6646 */ 6647 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_0_quad_b_ctrl10[0]) >> 12) & 0xf) 6648 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_0_quad_b_ctrl10[0]=(((r).ana_lane_0_quad_b_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 6649 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_0_quad_b_ctrl10[0]) >> 4) & 0x3f) 6650 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_0_quad_b_ctrl10[0]=(((r).ana_lane_0_quad_b_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 6651 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_0_quad_b_ctrl10[0]) >> 2) & 0x1) 6652 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_0_quad_b_ctrl10[0]=(((r).ana_lane_0_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 6653 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_0_quad_b_ctrl10[0]) >> 1) & 0x1) 6654 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_0_quad_b_ctrl10[0]=(((r).ana_lane_0_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 6655 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_0_quad_b_ctrl10[0]) & 0x1) 6656 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_0_quad_b_ctrl10[0]=(((r).ana_lane_0_quad_b_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 6657 6658 /* 6659 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL10. 6660 */ 6661 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r,_r._ana_lane_0_quad_b_ctrl10) 6662 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r,_r._ana_lane_0_quad_b_ctrl10) 6663 6664 /* 6665 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6666 * will be redefined without the chip prefix for easier programming. 6667 * If multiple chips will be programmed in the same source file, then you should 6668 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6669 * and refer to the fully qualified versions. 6670 */ 6671 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6672 6673 #define ANA_LANE_0_QUAD_B_CTRL10r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r 6674 #define ANA_LANE_0_QUAD_B_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_SIZE 6675 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_t ANA_LANE_0_QUAD_B_CTRL10r_t; 6676 #define ANA_LANE_0_QUAD_B_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_CLR 6677 #define ANA_LANE_0_QUAD_B_CTRL10r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_SET 6678 #define ANA_LANE_0_QUAD_B_CTRL10r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_GET 6679 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET 6680 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET 6681 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAINf_GET 6682 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_MAINf_SET 6683 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_VBSELf_GET 6684 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_VBSELf_SET 6685 #define ANA_LANE_0_QUAD_B_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DLINE_PWDf_GET 6686 #define ANA_LANE_0_QUAD_B_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DLINE_PWDf_SET 6687 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_PWDf_GET 6688 #define ANA_LANE_0_QUAD_B_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r_DRV_PWDf_SET 6689 #define READ_ANA_LANE_0_QUAD_B_CTRL10r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL10r 6690 #define WRITE_ANA_LANE_0_QUAD_B_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL10r 6691 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL10r 6692 6693 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6694 /******************************************************************************* 6695 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL10r' 6696 */ 6697 6698 6699 6700 6701 /******************************************************************************* 6702 * CHIP: BCMI_HURACAN 6703 * REGISTER: ANA_LANE_0_QUAD_B_CTRL11 6704 * BLOCKS: ANA_LANE_0_QUAD_B 6705 * REGADDR: 0x910b 6706 * DEVAD: 1 6707 * DESC: control registers 0 6708 * RESETVAL: 0x0 (0) 6709 * ACCESS: R/W 6710 * FIELDS: 6711 * RXTX_RESERVED_FOR_143_128 6712 */ 6713 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r (0x0001910b | PHYMOD_REG_ACC_RAW) 6714 6715 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_SIZE 4 6716 6717 /* 6718 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL11. 6719 */ 6720 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_s { 6721 uint32_t v[1]; 6722 uint32_t ana_lane_0_quad_b_ctrl11[1]; 6723 uint32_t _ana_lane_0_quad_b_ctrl11; 6724 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_t; 6725 6726 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_CLR(r) (r).ana_lane_0_quad_b_ctrl11[0] = 0 6727 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_SET(r,d) (r).ana_lane_0_quad_b_ctrl11[0] = d 6728 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_GET(r) (r).ana_lane_0_quad_b_ctrl11[0] 6729 6730 /* 6731 * These macros can be used to access individual fields. 6732 */ 6733 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_0_quad_b_ctrl11[0]) & 0xffff) 6734 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_0_quad_b_ctrl11[0]=(((r).ana_lane_0_quad_b_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 6735 6736 /* 6737 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL11. 6738 */ 6739 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r,_r._ana_lane_0_quad_b_ctrl11) 6740 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r,_r._ana_lane_0_quad_b_ctrl11) 6741 6742 /* 6743 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6744 * will be redefined without the chip prefix for easier programming. 6745 * If multiple chips will be programmed in the same source file, then you should 6746 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6747 * and refer to the fully qualified versions. 6748 */ 6749 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6750 6751 #define ANA_LANE_0_QUAD_B_CTRL11r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r 6752 #define ANA_LANE_0_QUAD_B_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_SIZE 6753 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_t ANA_LANE_0_QUAD_B_CTRL11r_t; 6754 #define ANA_LANE_0_QUAD_B_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_CLR 6755 #define ANA_LANE_0_QUAD_B_CTRL11r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_SET 6756 #define ANA_LANE_0_QUAD_B_CTRL11r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_GET 6757 #define ANA_LANE_0_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 6758 #define ANA_LANE_0_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 6759 #define READ_ANA_LANE_0_QUAD_B_CTRL11r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL11r 6760 #define WRITE_ANA_LANE_0_QUAD_B_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL11r 6761 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL11r 6762 6763 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6764 /******************************************************************************* 6765 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL11r' 6766 */ 6767 6768 6769 6770 6771 /******************************************************************************* 6772 * CHIP: BCMI_HURACAN 6773 * REGISTER: ANA_LANE_0_QUAD_B_CTRL12 6774 * BLOCKS: ANA_LANE_0_QUAD_B 6775 * REGADDR: 0x910c 6776 * DEVAD: 1 6777 * DESC: control registers 0 6778 * RESETVAL: 0x0 (0) 6779 * ACCESS: R/W 6780 * FIELDS: 6781 * LA_RESCAL_FRC_VAL 6782 * LA_RESCAL_FRC 6783 * DRV_RESCAL_FRC_VAL 6784 * DRV_RESCAL_FRC 6785 */ 6786 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r (0x0001910c | PHYMOD_REG_ACC_RAW) 6787 6788 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_SIZE 4 6789 6790 /* 6791 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL12. 6792 */ 6793 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_s { 6794 uint32_t v[1]; 6795 uint32_t ana_lane_0_quad_b_ctrl12[1]; 6796 uint32_t _ana_lane_0_quad_b_ctrl12; 6797 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_t; 6798 6799 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_CLR(r) (r).ana_lane_0_quad_b_ctrl12[0] = 0 6800 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_SET(r,d) (r).ana_lane_0_quad_b_ctrl12[0] = d 6801 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_GET(r) (r).ana_lane_0_quad_b_ctrl12[0] 6802 6803 /* 6804 * These macros can be used to access individual fields. 6805 */ 6806 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_b_ctrl12[0]) >> 12) & 0x1) 6807 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_b_ctrl12[0]=(((r).ana_lane_0_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 6808 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_b_ctrl12[0]) >> 8) & 0xf) 6809 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_b_ctrl12[0]=(((r).ana_lane_0_quad_b_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 6810 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_b_ctrl12[0]) >> 4) & 0x1) 6811 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_b_ctrl12[0]=(((r).ana_lane_0_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 6812 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_b_ctrl12[0]) & 0xf) 6813 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_b_ctrl12[0]=(((r).ana_lane_0_quad_b_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 6814 6815 /* 6816 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL12. 6817 */ 6818 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r,_r._ana_lane_0_quad_b_ctrl12) 6819 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r,_r._ana_lane_0_quad_b_ctrl12) 6820 6821 /* 6822 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6823 * will be redefined without the chip prefix for easier programming. 6824 * If multiple chips will be programmed in the same source file, then you should 6825 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6826 * and refer to the fully qualified versions. 6827 */ 6828 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6829 6830 #define ANA_LANE_0_QUAD_B_CTRL12r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r 6831 #define ANA_LANE_0_QUAD_B_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_SIZE 6832 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_t ANA_LANE_0_QUAD_B_CTRL12r_t; 6833 #define ANA_LANE_0_QUAD_B_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_CLR 6834 #define ANA_LANE_0_QUAD_B_CTRL12r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_SET 6835 #define ANA_LANE_0_QUAD_B_CTRL12r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_GET 6836 #define ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET 6837 #define ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET 6838 #define ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET 6839 #define ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET 6840 #define ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET 6841 #define ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET 6842 #define ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET 6843 #define ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET 6844 #define READ_ANA_LANE_0_QUAD_B_CTRL12r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL12r 6845 #define WRITE_ANA_LANE_0_QUAD_B_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL12r 6846 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL12r 6847 6848 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6849 /******************************************************************************* 6850 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL12r' 6851 */ 6852 6853 6854 6855 6856 /******************************************************************************* 6857 * CHIP: BCMI_HURACAN 6858 * REGISTER: ANA_LANE_0_QUAD_B_CTRL13 6859 * BLOCKS: ANA_LANE_0_QUAD_B 6860 * REGADDR: 0x910d 6861 * DEVAD: 1 6862 * DESC: control registers 0 6863 * RESETVAL: 0x0 (0) 6864 * ACCESS: R/W 6865 * FIELDS: 6866 * CTLE_RESCAL_FRC_VAL 6867 * CTLE_RESCAL_FRC 6868 */ 6869 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r (0x0001910d | PHYMOD_REG_ACC_RAW) 6870 6871 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_SIZE 4 6872 6873 /* 6874 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL13. 6875 */ 6876 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_s { 6877 uint32_t v[1]; 6878 uint32_t ana_lane_0_quad_b_ctrl13[1]; 6879 uint32_t _ana_lane_0_quad_b_ctrl13; 6880 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_t; 6881 6882 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CLR(r) (r).ana_lane_0_quad_b_ctrl13[0] = 0 6883 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_SET(r,d) (r).ana_lane_0_quad_b_ctrl13[0] = d 6884 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_GET(r) (r).ana_lane_0_quad_b_ctrl13[0] 6885 6886 /* 6887 * These macros can be used to access individual fields. 6888 */ 6889 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_b_ctrl13[0]) >> 4) & 0x1) 6890 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_b_ctrl13[0]=(((r).ana_lane_0_quad_b_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 6891 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_b_ctrl13[0]) & 0xf) 6892 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_b_ctrl13[0]=(((r).ana_lane_0_quad_b_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 6893 6894 /* 6895 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL13. 6896 */ 6897 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r,_r._ana_lane_0_quad_b_ctrl13) 6898 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r,_r._ana_lane_0_quad_b_ctrl13) 6899 6900 /* 6901 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6902 * will be redefined without the chip prefix for easier programming. 6903 * If multiple chips will be programmed in the same source file, then you should 6904 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6905 * and refer to the fully qualified versions. 6906 */ 6907 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6908 6909 #define ANA_LANE_0_QUAD_B_CTRL13r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r 6910 #define ANA_LANE_0_QUAD_B_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_SIZE 6911 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_t ANA_LANE_0_QUAD_B_CTRL13r_t; 6912 #define ANA_LANE_0_QUAD_B_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CLR 6913 #define ANA_LANE_0_QUAD_B_CTRL13r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_SET 6914 #define ANA_LANE_0_QUAD_B_CTRL13r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_GET 6915 #define ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET 6916 #define ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET 6917 #define ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 6918 #define ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 6919 #define READ_ANA_LANE_0_QUAD_B_CTRL13r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL13r 6920 #define WRITE_ANA_LANE_0_QUAD_B_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL13r 6921 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL13r 6922 6923 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 6924 /******************************************************************************* 6925 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL13r' 6926 */ 6927 6928 6929 6930 6931 /******************************************************************************* 6932 * CHIP: BCMI_HURACAN 6933 * REGISTER: ANA_LANE_0_QUAD_B_CTRL14 6934 * BLOCKS: ANA_LANE_0_QUAD_B 6935 * REGADDR: 0x910e 6936 * DEVAD: 1 6937 * DESC: control registers 0 6938 * RESETVAL: 0x0 (0) 6939 * ACCESS: R/W 6940 * FIELDS: 6941 * TX_IDLE_FRC_VAL 6942 * TX_IDLE_FRC 6943 * RXSD_IDLE_OVRD 6944 */ 6945 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r (0x0001910e | PHYMOD_REG_ACC_RAW) 6946 6947 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_SIZE 4 6948 6949 /* 6950 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL14. 6951 */ 6952 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_s { 6953 uint32_t v[1]; 6954 uint32_t ana_lane_0_quad_b_ctrl14[1]; 6955 uint32_t _ana_lane_0_quad_b_ctrl14; 6956 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_t; 6957 6958 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_CLR(r) (r).ana_lane_0_quad_b_ctrl14[0] = 0 6959 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_SET(r,d) (r).ana_lane_0_quad_b_ctrl14[0] = d 6960 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_GET(r) (r).ana_lane_0_quad_b_ctrl14[0] 6961 6962 /* 6963 * These macros can be used to access individual fields. 6964 */ 6965 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_0_quad_b_ctrl14[0]) >> 4) & 0x1) 6966 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_0_quad_b_ctrl14[0]=(((r).ana_lane_0_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 6967 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_0_quad_b_ctrl14[0]) >> 1) & 0x1) 6968 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_0_quad_b_ctrl14[0]=(((r).ana_lane_0_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 6969 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_0_quad_b_ctrl14[0]) & 0x1) 6970 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_b_ctrl14[0]=(((r).ana_lane_0_quad_b_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 6971 6972 /* 6973 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL14. 6974 */ 6975 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r,_r._ana_lane_0_quad_b_ctrl14) 6976 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r,_r._ana_lane_0_quad_b_ctrl14) 6977 6978 /* 6979 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 6980 * will be redefined without the chip prefix for easier programming. 6981 * If multiple chips will be programmed in the same source file, then you should 6982 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 6983 * and refer to the fully qualified versions. 6984 */ 6985 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 6986 6987 #define ANA_LANE_0_QUAD_B_CTRL14r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r 6988 #define ANA_LANE_0_QUAD_B_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_SIZE 6989 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_t ANA_LANE_0_QUAD_B_CTRL14r_t; 6990 #define ANA_LANE_0_QUAD_B_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_CLR 6991 #define ANA_LANE_0_QUAD_B_CTRL14r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_SET 6992 #define ANA_LANE_0_QUAD_B_CTRL14r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_GET 6993 #define ANA_LANE_0_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET 6994 #define ANA_LANE_0_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET 6995 #define ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET 6996 #define ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET 6997 #define ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET 6998 #define ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET 6999 #define READ_ANA_LANE_0_QUAD_B_CTRL14r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL14r 7000 #define WRITE_ANA_LANE_0_QUAD_B_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL14r 7001 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL14r 7002 7003 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7004 /******************************************************************************* 7005 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL14r' 7006 */ 7007 7008 7009 7010 7011 /******************************************************************************* 7012 * CHIP: BCMI_HURACAN 7013 * REGISTER: ANA_LANE_0_QUAD_B_CTRL15 7014 * BLOCKS: ANA_LANE_0_QUAD_B 7015 * REGADDR: 0x910f 7016 * DEVAD: 1 7017 * DESC: sigdet filter settings 0 7018 * RESETVAL: 0x0 (0) 7019 * ACCESS: R/W 7020 * FIELDS: 7021 * SIGDET_DIS 7022 * SIGDET_1US_EN 7023 * SIGDET_FRC_VAL 7024 * SIGDET_FRC 7025 * HOLD_LOS_COUNT 7026 * HOLD_SD_COUNT 7027 */ 7028 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r (0x0001910f | PHYMOD_REG_ACC_RAW) 7029 7030 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIZE 4 7031 7032 /* 7033 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL15. 7034 */ 7035 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_s { 7036 uint32_t v[1]; 7037 uint32_t ana_lane_0_quad_b_ctrl15[1]; 7038 uint32_t _ana_lane_0_quad_b_ctrl15; 7039 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_t; 7040 7041 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_CLR(r) (r).ana_lane_0_quad_b_ctrl15[0] = 0 7042 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SET(r,d) (r).ana_lane_0_quad_b_ctrl15[0] = d 7043 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_GET(r) (r).ana_lane_0_quad_b_ctrl15[0] 7044 7045 /* 7046 * These macros can be used to access individual fields. 7047 */ 7048 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_b_ctrl15[0]) >> 8) & 0x7) 7049 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_b_ctrl15[0]=(((r).ana_lane_0_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 7050 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_0_quad_b_ctrl15[0]) >> 4) & 0x7) 7051 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_b_ctrl15[0]=(((r).ana_lane_0_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 7052 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_0_quad_b_ctrl15[0]) >> 3) & 0x1) 7053 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_0_quad_b_ctrl15[0]=(((r).ana_lane_0_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 7054 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_b_ctrl15[0]) >> 2) & 0x1) 7055 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_b_ctrl15[0]=(((r).ana_lane_0_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 7056 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_0_quad_b_ctrl15[0]) >> 1) & 0x1) 7057 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_0_quad_b_ctrl15[0]=(((r).ana_lane_0_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 7058 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_0_quad_b_ctrl15[0]) & 0x1) 7059 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_0_quad_b_ctrl15[0]=(((r).ana_lane_0_quad_b_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 7060 7061 /* 7062 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL15. 7063 */ 7064 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r,_r._ana_lane_0_quad_b_ctrl15) 7065 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r,_r._ana_lane_0_quad_b_ctrl15) 7066 7067 /* 7068 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7069 * will be redefined without the chip prefix for easier programming. 7070 * If multiple chips will be programmed in the same source file, then you should 7071 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7072 * and refer to the fully qualified versions. 7073 */ 7074 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7075 7076 #define ANA_LANE_0_QUAD_B_CTRL15r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r 7077 #define ANA_LANE_0_QUAD_B_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIZE 7078 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_t ANA_LANE_0_QUAD_B_CTRL15r_t; 7079 #define ANA_LANE_0_QUAD_B_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_CLR 7080 #define ANA_LANE_0_QUAD_B_CTRL15r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SET 7081 #define ANA_LANE_0_QUAD_B_CTRL15r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_GET 7082 #define ANA_LANE_0_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET 7083 #define ANA_LANE_0_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET 7084 #define ANA_LANE_0_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET 7085 #define ANA_LANE_0_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET 7086 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRCf_GET 7087 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRCf_SET 7088 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET 7089 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET 7090 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET 7091 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET 7092 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_DISf_GET 7093 #define ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r_SIGDET_DISf_SET 7094 #define READ_ANA_LANE_0_QUAD_B_CTRL15r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL15r 7095 #define WRITE_ANA_LANE_0_QUAD_B_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL15r 7096 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL15r 7097 7098 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7099 /******************************************************************************* 7100 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL15r' 7101 */ 7102 7103 7104 7105 7106 /******************************************************************************* 7107 * CHIP: BCMI_HURACAN 7108 * REGISTER: ANA_LANE_0_QUAD_B_CTRL16 7109 * BLOCKS: ANA_LANE_0_QUAD_B 7110 * REGADDR: 0x9110 7111 * DEVAD: 1 7112 * DESC: sigdet filter settings 1 7113 * RESETVAL: 0x0 (0) 7114 * ACCESS: R/W 7115 * FIELDS: 7116 * LOS_COUNT 7117 * SD_COUNT 7118 */ 7119 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r (0x00019110 | PHYMOD_REG_ACC_RAW) 7120 7121 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SIZE 4 7122 7123 /* 7124 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_CTRL16. 7125 */ 7126 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_s { 7127 uint32_t v[1]; 7128 uint32_t ana_lane_0_quad_b_ctrl16[1]; 7129 uint32_t _ana_lane_0_quad_b_ctrl16; 7130 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_t; 7131 7132 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_CLR(r) (r).ana_lane_0_quad_b_ctrl16[0] = 0 7133 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SET(r,d) (r).ana_lane_0_quad_b_ctrl16[0] = d 7134 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_GET(r) (r).ana_lane_0_quad_b_ctrl16[0] 7135 7136 /* 7137 * These macros can be used to access individual fields. 7138 */ 7139 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_b_ctrl16[0]) >> 8) & 0x1f) 7140 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_b_ctrl16[0]=(((r).ana_lane_0_quad_b_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 7141 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_0_quad_b_ctrl16[0]) & 0x1f) 7142 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_b_ctrl16[0]=(((r).ana_lane_0_quad_b_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 7143 7144 /* 7145 * These macros can be used to access ANA_LANE_0_QUAD_B_CTRL16. 7146 */ 7147 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r,_r._ana_lane_0_quad_b_ctrl16) 7148 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r,_r._ana_lane_0_quad_b_ctrl16) 7149 7150 /* 7151 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7152 * will be redefined without the chip prefix for easier programming. 7153 * If multiple chips will be programmed in the same source file, then you should 7154 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7155 * and refer to the fully qualified versions. 7156 */ 7157 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7158 7159 #define ANA_LANE_0_QUAD_B_CTRL16r BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r 7160 #define ANA_LANE_0_QUAD_B_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SIZE 7161 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_t ANA_LANE_0_QUAD_B_CTRL16r_t; 7162 #define ANA_LANE_0_QUAD_B_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_CLR 7163 #define ANA_LANE_0_QUAD_B_CTRL16r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SET 7164 #define ANA_LANE_0_QUAD_B_CTRL16r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_GET 7165 #define ANA_LANE_0_QUAD_B_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SD_COUNTf_GET 7166 #define ANA_LANE_0_QUAD_B_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_SD_COUNTf_SET 7167 #define ANA_LANE_0_QUAD_B_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_LOS_COUNTf_GET 7168 #define ANA_LANE_0_QUAD_B_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r_LOS_COUNTf_SET 7169 #define READ_ANA_LANE_0_QUAD_B_CTRL16r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_CTRL16r 7170 #define WRITE_ANA_LANE_0_QUAD_B_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_CTRL16r 7171 #define MODIFY_ANA_LANE_0_QUAD_B_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_CTRL16r 7172 7173 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7174 /******************************************************************************* 7175 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_CTRL16r' 7176 */ 7177 7178 7179 7180 7181 /******************************************************************************* 7182 * CHIP: BCMI_HURACAN 7183 * REGISTER: ANA_LANE_0_QUAD_B_STATUS0 7184 * BLOCKS: ANA_LANE_0_QUAD_B 7185 * REGADDR: 0x9120 7186 * DEVAD: 1 7187 * DESC: status registers 0 7188 * RESETVAL: 0x0 (0) 7189 * ACCESS: R/W 7190 * FIELDS: 7191 * O_RX_SIGDET 7192 * DG_RX_SIGDET 7193 */ 7194 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r (0x00019120 | PHYMOD_REG_ACC_RAW) 7195 7196 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_SIZE 4 7197 7198 /* 7199 * This structure should be used to declare and program ANA_LANE_0_QUAD_B_STATUS0. 7200 */ 7201 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_s { 7202 uint32_t v[1]; 7203 uint32_t ana_lane_0_quad_b_status0[1]; 7204 uint32_t _ana_lane_0_quad_b_status0; 7205 } BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_t; 7206 7207 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_CLR(r) (r).ana_lane_0_quad_b_status0[0] = 0 7208 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_SET(r,d) (r).ana_lane_0_quad_b_status0[0] = d 7209 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_GET(r) (r).ana_lane_0_quad_b_status0[0] 7210 7211 /* 7212 * These macros can be used to access individual fields. 7213 */ 7214 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_0_quad_b_status0[0]) >> 1) & 0x1) 7215 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_b_status0[0]=(((r).ana_lane_0_quad_b_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 7216 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_0_quad_b_status0[0]) & 0x1) 7217 #define BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_b_status0[0]=(((r).ana_lane_0_quad_b_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 7218 7219 /* 7220 * These macros can be used to access ANA_LANE_0_QUAD_B_STATUS0. 7221 */ 7222 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r,_r._ana_lane_0_quad_b_status0) 7223 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r,_r._ana_lane_0_quad_b_status0) 7224 7225 /* 7226 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7227 * will be redefined without the chip prefix for easier programming. 7228 * If multiple chips will be programmed in the same source file, then you should 7229 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7230 * and refer to the fully qualified versions. 7231 */ 7232 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7233 7234 #define ANA_LANE_0_QUAD_B_STATUS0r BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r 7235 #define ANA_LANE_0_QUAD_B_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_SIZE 7236 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_t ANA_LANE_0_QUAD_B_STATUS0r_t; 7237 #define ANA_LANE_0_QUAD_B_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_CLR 7238 #define ANA_LANE_0_QUAD_B_STATUS0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_SET 7239 #define ANA_LANE_0_QUAD_B_STATUS0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_GET 7240 #define ANA_LANE_0_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET 7241 #define ANA_LANE_0_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET 7242 #define ANA_LANE_0_QUAD_B_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_O_RX_SIGDETf_GET 7243 #define ANA_LANE_0_QUAD_B_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r_O_RX_SIGDETf_SET 7244 #define READ_ANA_LANE_0_QUAD_B_STATUS0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_B_STATUS0r 7245 #define WRITE_ANA_LANE_0_QUAD_B_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_B_STATUS0r 7246 #define MODIFY_ANA_LANE_0_QUAD_B_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_B_STATUS0r 7247 7248 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7249 /******************************************************************************* 7250 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_B_STATUS0r' 7251 */ 7252 7253 7254 7255 7256 /******************************************************************************* 7257 * CHIP: BCMI_HURACAN 7258 * REGISTER: ANA_LANE_1_QUAD_B_CTRL0 7259 * BLOCKS: ANA_LANE_1_QUAD_B 7260 * REGADDR: 0x9200 7261 * DEVAD: 1 7262 * DESC: control registers 0 7263 * RESETVAL: 0x0 (0) 7264 * ACCESS: R/W 7265 * FIELDS: 7266 * RXTX_PWRDN 7267 * RX_SIGDET_BYPASS 7268 * RX_SIGDET_PWRDN 7269 * RX_SIGDECT_12GMODE 7270 * DC_COUPLE 7271 */ 7272 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r (0x00019200 | PHYMOD_REG_ACC_RAW) 7273 7274 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_SIZE 4 7275 7276 /* 7277 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL0. 7278 */ 7279 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_s { 7280 uint32_t v[1]; 7281 uint32_t ana_lane_1_quad_b_ctrl0[1]; 7282 uint32_t _ana_lane_1_quad_b_ctrl0; 7283 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_t; 7284 7285 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_CLR(r) (r).ana_lane_1_quad_b_ctrl0[0] = 0 7286 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_SET(r,d) (r).ana_lane_1_quad_b_ctrl0[0] = d 7287 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_GET(r) (r).ana_lane_1_quad_b_ctrl0[0] 7288 7289 /* 7290 * These macros can be used to access individual fields. 7291 */ 7292 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_1_quad_b_ctrl0[0]) >> 4) & 0x1) 7293 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_1_quad_b_ctrl0[0]=(((r).ana_lane_1_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 7294 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_1_quad_b_ctrl0[0]) >> 3) & 0x1) 7295 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_1_quad_b_ctrl0[0]=(((r).ana_lane_1_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 7296 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_1_quad_b_ctrl0[0]) >> 2) & 0x1) 7297 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_1_quad_b_ctrl0[0]=(((r).ana_lane_1_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 7298 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_1_quad_b_ctrl0[0]) >> 1) & 0x1) 7299 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_1_quad_b_ctrl0[0]=(((r).ana_lane_1_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 7300 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_1_quad_b_ctrl0[0]) & 0x1) 7301 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_1_quad_b_ctrl0[0]=(((r).ana_lane_1_quad_b_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 7302 7303 /* 7304 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL0. 7305 */ 7306 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r,_r._ana_lane_1_quad_b_ctrl0) 7307 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r,_r._ana_lane_1_quad_b_ctrl0) 7308 7309 /* 7310 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7311 * will be redefined without the chip prefix for easier programming. 7312 * If multiple chips will be programmed in the same source file, then you should 7313 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7314 * and refer to the fully qualified versions. 7315 */ 7316 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7317 7318 #define ANA_LANE_1_QUAD_B_CTRL0r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r 7319 #define ANA_LANE_1_QUAD_B_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_SIZE 7320 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_t ANA_LANE_1_QUAD_B_CTRL0r_t; 7321 #define ANA_LANE_1_QUAD_B_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_CLR 7322 #define ANA_LANE_1_QUAD_B_CTRL0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_SET 7323 #define ANA_LANE_1_QUAD_B_CTRL0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_GET 7324 #define ANA_LANE_1_QUAD_B_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_DC_COUPLEf_GET 7325 #define ANA_LANE_1_QUAD_B_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_DC_COUPLEf_SET 7326 #define ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET 7327 #define ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET 7328 #define ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET 7329 #define ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET 7330 #define ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET 7331 #define ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET 7332 #define ANA_LANE_1_QUAD_B_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RXTX_PWRDNf_GET 7333 #define ANA_LANE_1_QUAD_B_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r_RXTX_PWRDNf_SET 7334 #define READ_ANA_LANE_1_QUAD_B_CTRL0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL0r 7335 #define WRITE_ANA_LANE_1_QUAD_B_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL0r 7336 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL0r 7337 7338 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7339 /******************************************************************************* 7340 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL0r' 7341 */ 7342 7343 7344 7345 7346 /******************************************************************************* 7347 * CHIP: BCMI_HURACAN 7348 * REGISTER: ANA_LANE_1_QUAD_B_CTRL1 7349 * BLOCKS: ANA_LANE_1_QUAD_B 7350 * REGADDR: 0x9201 7351 * DEVAD: 1 7352 * DESC: control registers 0 7353 * RESETVAL: 0x0 (0) 7354 * ACCESS: R/W 7355 * FIELDS: 7356 * RX_SIGDET_THRESHOLD 7357 * REF_OCL 7358 * OCL_PWRDN 7359 * OCL_DISABLE_LOOP 7360 * RXTX_RESERVED_FOR_15_12 7361 */ 7362 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r (0x00019201 | PHYMOD_REG_ACC_RAW) 7363 7364 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_SIZE 4 7365 7366 /* 7367 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL1. 7368 */ 7369 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_s { 7370 uint32_t v[1]; 7371 uint32_t ana_lane_1_quad_b_ctrl1[1]; 7372 uint32_t _ana_lane_1_quad_b_ctrl1; 7373 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_t; 7374 7375 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_CLR(r) (r).ana_lane_1_quad_b_ctrl1[0] = 0 7376 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_SET(r,d) (r).ana_lane_1_quad_b_ctrl1[0] = d 7377 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_GET(r) (r).ana_lane_1_quad_b_ctrl1[0] 7378 7379 /* 7380 * These macros can be used to access individual fields. 7381 */ 7382 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_1_quad_b_ctrl1[0]) >> 12) & 0xf) 7383 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_1_quad_b_ctrl1[0]=(((r).ana_lane_1_quad_b_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 7384 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_1_quad_b_ctrl1[0]) >> 9) & 0x1) 7385 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_1_quad_b_ctrl1[0]=(((r).ana_lane_1_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 7386 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_1_quad_b_ctrl1[0]) >> 8) & 0x1) 7387 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_1_quad_b_ctrl1[0]=(((r).ana_lane_1_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 7388 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_1_quad_b_ctrl1[0]) >> 4) & 0x3) 7389 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_1_quad_b_ctrl1[0]=(((r).ana_lane_1_quad_b_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 7390 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_1_quad_b_ctrl1[0]) & 0x7) 7391 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_1_quad_b_ctrl1[0]=(((r).ana_lane_1_quad_b_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 7392 7393 /* 7394 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL1. 7395 */ 7396 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r,_r._ana_lane_1_quad_b_ctrl1) 7397 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r,_r._ana_lane_1_quad_b_ctrl1) 7398 7399 /* 7400 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7401 * will be redefined without the chip prefix for easier programming. 7402 * If multiple chips will be programmed in the same source file, then you should 7403 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7404 * and refer to the fully qualified versions. 7405 */ 7406 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7407 7408 #define ANA_LANE_1_QUAD_B_CTRL1r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r 7409 #define ANA_LANE_1_QUAD_B_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_SIZE 7410 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_t ANA_LANE_1_QUAD_B_CTRL1r_t; 7411 #define ANA_LANE_1_QUAD_B_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_CLR 7412 #define ANA_LANE_1_QUAD_B_CTRL1r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_SET 7413 #define ANA_LANE_1_QUAD_B_CTRL1r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_GET 7414 #define ANA_LANE_1_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 7415 #define ANA_LANE_1_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 7416 #define ANA_LANE_1_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET 7417 #define ANA_LANE_1_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET 7418 #define ANA_LANE_1_QUAD_B_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_PWRDNf_GET 7419 #define ANA_LANE_1_QUAD_B_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_OCL_PWRDNf_SET 7420 #define ANA_LANE_1_QUAD_B_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_REF_OCLf_GET 7421 #define ANA_LANE_1_QUAD_B_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_REF_OCLf_SET 7422 #define ANA_LANE_1_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET 7423 #define ANA_LANE_1_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET 7424 #define READ_ANA_LANE_1_QUAD_B_CTRL1r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL1r 7425 #define WRITE_ANA_LANE_1_QUAD_B_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL1r 7426 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL1r 7427 7428 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7429 /******************************************************************************* 7430 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL1r' 7431 */ 7432 7433 7434 7435 7436 /******************************************************************************* 7437 * CHIP: BCMI_HURACAN 7438 * REGISTER: ANA_LANE_1_QUAD_B_CTRL2 7439 * BLOCKS: ANA_LANE_1_QUAD_B 7440 * REGADDR: 0x9202 7441 * DEVAD: 1 7442 * DESC: control registers 0 7443 * RESETVAL: 0x0 (0) 7444 * ACCESS: R/W 7445 * FIELDS: 7446 * CTLE_ENB_NEGIMP 7447 * CTLE_ENB_NEGCAP 7448 */ 7449 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r (0x00019202 | PHYMOD_REG_ACC_RAW) 7450 7451 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_SIZE 4 7452 7453 /* 7454 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL2. 7455 */ 7456 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_s { 7457 uint32_t v[1]; 7458 uint32_t ana_lane_1_quad_b_ctrl2[1]; 7459 uint32_t _ana_lane_1_quad_b_ctrl2; 7460 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_t; 7461 7462 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CLR(r) (r).ana_lane_1_quad_b_ctrl2[0] = 0 7463 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_SET(r,d) (r).ana_lane_1_quad_b_ctrl2[0] = d 7464 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_GET(r) (r).ana_lane_1_quad_b_ctrl2[0] 7465 7466 /* 7467 * These macros can be used to access individual fields. 7468 */ 7469 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_1_quad_b_ctrl2[0]) >> 8) & 0x7f) 7470 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_1_quad_b_ctrl2[0]=(((r).ana_lane_1_quad_b_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 7471 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_1_quad_b_ctrl2[0]) & 0x7f) 7472 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_1_quad_b_ctrl2[0]=(((r).ana_lane_1_quad_b_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 7473 7474 /* 7475 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL2. 7476 */ 7477 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r,_r._ana_lane_1_quad_b_ctrl2) 7478 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r,_r._ana_lane_1_quad_b_ctrl2) 7479 7480 /* 7481 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7482 * will be redefined without the chip prefix for easier programming. 7483 * If multiple chips will be programmed in the same source file, then you should 7484 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7485 * and refer to the fully qualified versions. 7486 */ 7487 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7488 7489 #define ANA_LANE_1_QUAD_B_CTRL2r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r 7490 #define ANA_LANE_1_QUAD_B_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_SIZE 7491 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_t ANA_LANE_1_QUAD_B_CTRL2r_t; 7492 #define ANA_LANE_1_QUAD_B_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CLR 7493 #define ANA_LANE_1_QUAD_B_CTRL2r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_SET 7494 #define ANA_LANE_1_QUAD_B_CTRL2r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_GET 7495 #define ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET 7496 #define ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET 7497 #define ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET 7498 #define ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET 7499 #define READ_ANA_LANE_1_QUAD_B_CTRL2r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL2r 7500 #define WRITE_ANA_LANE_1_QUAD_B_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL2r 7501 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL2r 7502 7503 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7504 /******************************************************************************* 7505 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL2r' 7506 */ 7507 7508 7509 7510 7511 /******************************************************************************* 7512 * CHIP: BCMI_HURACAN 7513 * REGISTER: ANA_LANE_1_QUAD_B_CTRL3 7514 * BLOCKS: ANA_LANE_1_QUAD_B 7515 * REGADDR: 0x9203 7516 * DEVAD: 1 7517 * DESC: control registers 0 7518 * RESETVAL: 0x0 (0) 7519 * ACCESS: R/W 7520 * FIELDS: 7521 * CTLE_EN_NEGRES 7522 * CTLE_EQSEL 7523 */ 7524 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r (0x00019203 | PHYMOD_REG_ACC_RAW) 7525 7526 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_SIZE 4 7527 7528 /* 7529 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL3. 7530 */ 7531 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_s { 7532 uint32_t v[1]; 7533 uint32_t ana_lane_1_quad_b_ctrl3[1]; 7534 uint32_t _ana_lane_1_quad_b_ctrl3; 7535 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_t; 7536 7537 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CLR(r) (r).ana_lane_1_quad_b_ctrl3[0] = 0 7538 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_SET(r,d) (r).ana_lane_1_quad_b_ctrl3[0] = d 7539 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_GET(r) (r).ana_lane_1_quad_b_ctrl3[0] 7540 7541 /* 7542 * These macros can be used to access individual fields. 7543 */ 7544 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_1_quad_b_ctrl3[0]) >> 8) & 0xff) 7545 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_1_quad_b_ctrl3[0]=(((r).ana_lane_1_quad_b_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 7546 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_1_quad_b_ctrl3[0]) & 0x7f) 7547 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_1_quad_b_ctrl3[0]=(((r).ana_lane_1_quad_b_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 7548 7549 /* 7550 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL3. 7551 */ 7552 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r,_r._ana_lane_1_quad_b_ctrl3) 7553 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r,_r._ana_lane_1_quad_b_ctrl3) 7554 7555 /* 7556 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7557 * will be redefined without the chip prefix for easier programming. 7558 * If multiple chips will be programmed in the same source file, then you should 7559 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7560 * and refer to the fully qualified versions. 7561 */ 7562 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7563 7564 #define ANA_LANE_1_QUAD_B_CTRL3r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r 7565 #define ANA_LANE_1_QUAD_B_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_SIZE 7566 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_t ANA_LANE_1_QUAD_B_CTRL3r_t; 7567 #define ANA_LANE_1_QUAD_B_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CLR 7568 #define ANA_LANE_1_QUAD_B_CTRL3r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_SET 7569 #define ANA_LANE_1_QUAD_B_CTRL3r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_GET 7570 #define ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EQSELf_GET 7571 #define ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EQSELf_SET 7572 #define ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET 7573 #define ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET 7574 #define READ_ANA_LANE_1_QUAD_B_CTRL3r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL3r 7575 #define WRITE_ANA_LANE_1_QUAD_B_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL3r 7576 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL3r 7577 7578 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7579 /******************************************************************************* 7580 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL3r' 7581 */ 7582 7583 7584 7585 7586 /******************************************************************************* 7587 * CHIP: BCMI_HURACAN 7588 * REGISTER: ANA_LANE_1_QUAD_B_CTRL4 7589 * BLOCKS: ANA_LANE_1_QUAD_B 7590 * REGADDR: 0x9204 7591 * DEVAD: 1 7592 * DESC: control registers 0 7593 * RESETVAL: 0x0 (0) 7594 * ACCESS: R/W 7595 * FIELDS: 7596 * CTLE_LZEN 7597 * RXTX_RESERVED_FOR_59_52 7598 */ 7599 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r (0x00019204 | PHYMOD_REG_ACC_RAW) 7600 7601 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_SIZE 4 7602 7603 /* 7604 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL4. 7605 */ 7606 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_s { 7607 uint32_t v[1]; 7608 uint32_t ana_lane_1_quad_b_ctrl4[1]; 7609 uint32_t _ana_lane_1_quad_b_ctrl4; 7610 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_t; 7611 7612 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_CLR(r) (r).ana_lane_1_quad_b_ctrl4[0] = 0 7613 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_SET(r,d) (r).ana_lane_1_quad_b_ctrl4[0] = d 7614 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_GET(r) (r).ana_lane_1_quad_b_ctrl4[0] 7615 7616 /* 7617 * These macros can be used to access individual fields. 7618 */ 7619 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_1_quad_b_ctrl4[0]) >> 4) & 0xff) 7620 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_1_quad_b_ctrl4[0]=(((r).ana_lane_1_quad_b_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 7621 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_1_quad_b_ctrl4[0]) & 0x1) 7622 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_1_quad_b_ctrl4[0]=(((r).ana_lane_1_quad_b_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 7623 7624 /* 7625 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL4. 7626 */ 7627 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r,_r._ana_lane_1_quad_b_ctrl4) 7628 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r,_r._ana_lane_1_quad_b_ctrl4) 7629 7630 /* 7631 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7632 * will be redefined without the chip prefix for easier programming. 7633 * If multiple chips will be programmed in the same source file, then you should 7634 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7635 * and refer to the fully qualified versions. 7636 */ 7637 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7638 7639 #define ANA_LANE_1_QUAD_B_CTRL4r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r 7640 #define ANA_LANE_1_QUAD_B_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_SIZE 7641 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_t ANA_LANE_1_QUAD_B_CTRL4r_t; 7642 #define ANA_LANE_1_QUAD_B_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_CLR 7643 #define ANA_LANE_1_QUAD_B_CTRL4r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_SET 7644 #define ANA_LANE_1_QUAD_B_CTRL4r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_GET 7645 #define ANA_LANE_1_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 7646 #define ANA_LANE_1_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 7647 #define ANA_LANE_1_QUAD_B_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_CTLE_LZENf_GET 7648 #define ANA_LANE_1_QUAD_B_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r_CTLE_LZENf_SET 7649 #define READ_ANA_LANE_1_QUAD_B_CTRL4r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL4r 7650 #define WRITE_ANA_LANE_1_QUAD_B_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL4r 7651 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL4r 7652 7653 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7654 /******************************************************************************* 7655 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL4r' 7656 */ 7657 7658 7659 7660 7661 /******************************************************************************* 7662 * CHIP: BCMI_HURACAN 7663 * REGISTER: ANA_LANE_1_QUAD_B_CTRL5 7664 * BLOCKS: ANA_LANE_1_QUAD_B 7665 * REGADDR: 0x9205 7666 * DEVAD: 1 7667 * DESC: control registers 0 7668 * RESETVAL: 0x0 (0) 7669 * ACCESS: R/W 7670 * FIELDS: 7671 * CTLE_LOPEAKING 7672 * CTLE_PD 7673 * LA_GCTRL 7674 */ 7675 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r (0x00019205 | PHYMOD_REG_ACC_RAW) 7676 7677 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_SIZE 4 7678 7679 /* 7680 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL5. 7681 */ 7682 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_s { 7683 uint32_t v[1]; 7684 uint32_t ana_lane_1_quad_b_ctrl5[1]; 7685 uint32_t _ana_lane_1_quad_b_ctrl5; 7686 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_t; 7687 7688 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CLR(r) (r).ana_lane_1_quad_b_ctrl5[0] = 0 7689 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_SET(r,d) (r).ana_lane_1_quad_b_ctrl5[0] = d 7690 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_GET(r) (r).ana_lane_1_quad_b_ctrl5[0] 7691 7692 /* 7693 * These macros can be used to access individual fields. 7694 */ 7695 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_1_quad_b_ctrl5[0]) >> 4) & 0x3ff) 7696 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_1_quad_b_ctrl5[0]=(((r).ana_lane_1_quad_b_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 7697 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_1_quad_b_ctrl5[0]) >> 1) & 0x1) 7698 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_1_quad_b_ctrl5[0]=(((r).ana_lane_1_quad_b_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 7699 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_1_quad_b_ctrl5[0]) & 0x1) 7700 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_1_quad_b_ctrl5[0]=(((r).ana_lane_1_quad_b_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 7701 7702 /* 7703 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL5. 7704 */ 7705 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r,_r._ana_lane_1_quad_b_ctrl5) 7706 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r,_r._ana_lane_1_quad_b_ctrl5) 7707 7708 /* 7709 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7710 * will be redefined without the chip prefix for easier programming. 7711 * If multiple chips will be programmed in the same source file, then you should 7712 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7713 * and refer to the fully qualified versions. 7714 */ 7715 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7716 7717 #define ANA_LANE_1_QUAD_B_CTRL5r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r 7718 #define ANA_LANE_1_QUAD_B_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_SIZE 7719 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_t ANA_LANE_1_QUAD_B_CTRL5r_t; 7720 #define ANA_LANE_1_QUAD_B_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CLR 7721 #define ANA_LANE_1_QUAD_B_CTRL5r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_SET 7722 #define ANA_LANE_1_QUAD_B_CTRL5r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_GET 7723 #define ANA_LANE_1_QUAD_B_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_LA_GCTRLf_GET 7724 #define ANA_LANE_1_QUAD_B_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_LA_GCTRLf_SET 7725 #define ANA_LANE_1_QUAD_B_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_PDf_GET 7726 #define ANA_LANE_1_QUAD_B_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_PDf_SET 7727 #define ANA_LANE_1_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET 7728 #define ANA_LANE_1_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET 7729 #define READ_ANA_LANE_1_QUAD_B_CTRL5r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL5r 7730 #define WRITE_ANA_LANE_1_QUAD_B_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL5r 7731 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL5r 7732 7733 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7734 /******************************************************************************* 7735 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL5r' 7736 */ 7737 7738 7739 7740 7741 /******************************************************************************* 7742 * CHIP: BCMI_HURACAN 7743 * REGISTER: ANA_LANE_1_QUAD_B_CTRL6 7744 * BLOCKS: ANA_LANE_1_QUAD_B 7745 * REGADDR: 0x9206 7746 * DEVAD: 1 7747 * DESC: control registers 0 7748 * RESETVAL: 0x0 (0) 7749 * ACCESS: R/W 7750 * FIELDS: 7751 * LA_DEGAIN 7752 * LA_DETUNE 7753 */ 7754 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r (0x00019206 | PHYMOD_REG_ACC_RAW) 7755 7756 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_SIZE 4 7757 7758 /* 7759 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL6. 7760 */ 7761 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_s { 7762 uint32_t v[1]; 7763 uint32_t ana_lane_1_quad_b_ctrl6[1]; 7764 uint32_t _ana_lane_1_quad_b_ctrl6; 7765 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_t; 7766 7767 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_CLR(r) (r).ana_lane_1_quad_b_ctrl6[0] = 0 7768 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_SET(r,d) (r).ana_lane_1_quad_b_ctrl6[0] = d 7769 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_GET(r) (r).ana_lane_1_quad_b_ctrl6[0] 7770 7771 /* 7772 * These macros can be used to access individual fields. 7773 */ 7774 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_1_quad_b_ctrl6[0]) >> 8) & 0xff) 7775 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_1_quad_b_ctrl6[0]=(((r).ana_lane_1_quad_b_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 7776 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_1_quad_b_ctrl6[0]) & 0x1f) 7777 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_1_quad_b_ctrl6[0]=(((r).ana_lane_1_quad_b_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 7778 7779 /* 7780 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL6. 7781 */ 7782 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r,_r._ana_lane_1_quad_b_ctrl6) 7783 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r,_r._ana_lane_1_quad_b_ctrl6) 7784 7785 /* 7786 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7787 * will be redefined without the chip prefix for easier programming. 7788 * If multiple chips will be programmed in the same source file, then you should 7789 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7790 * and refer to the fully qualified versions. 7791 */ 7792 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7793 7794 #define ANA_LANE_1_QUAD_B_CTRL6r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r 7795 #define ANA_LANE_1_QUAD_B_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_SIZE 7796 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_t ANA_LANE_1_QUAD_B_CTRL6r_t; 7797 #define ANA_LANE_1_QUAD_B_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_CLR 7798 #define ANA_LANE_1_QUAD_B_CTRL6r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_SET 7799 #define ANA_LANE_1_QUAD_B_CTRL6r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_GET 7800 #define ANA_LANE_1_QUAD_B_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DETUNEf_GET 7801 #define ANA_LANE_1_QUAD_B_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DETUNEf_SET 7802 #define ANA_LANE_1_QUAD_B_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DEGAINf_GET 7803 #define ANA_LANE_1_QUAD_B_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r_LA_DEGAINf_SET 7804 #define READ_ANA_LANE_1_QUAD_B_CTRL6r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL6r 7805 #define WRITE_ANA_LANE_1_QUAD_B_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL6r 7806 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL6r 7807 7808 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7809 /******************************************************************************* 7810 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL6r' 7811 */ 7812 7813 7814 7815 7816 /******************************************************************************* 7817 * CHIP: BCMI_HURACAN 7818 * REGISTER: ANA_LANE_1_QUAD_B_CTRL7 7819 * BLOCKS: ANA_LANE_1_QUAD_B 7820 * REGADDR: 0x9207 7821 * DEVAD: 1 7822 * DESC: control registers 0 7823 * RESETVAL: 0x0 (0) 7824 * ACCESS: R/W 7825 * FIELDS: 7826 * LA_LIN_MODE 7827 * RX_BIAS_FB_PDN 7828 */ 7829 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r (0x00019207 | PHYMOD_REG_ACC_RAW) 7830 7831 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_SIZE 4 7832 7833 /* 7834 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL7. 7835 */ 7836 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_s { 7837 uint32_t v[1]; 7838 uint32_t ana_lane_1_quad_b_ctrl7[1]; 7839 uint32_t _ana_lane_1_quad_b_ctrl7; 7840 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_t; 7841 7842 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_CLR(r) (r).ana_lane_1_quad_b_ctrl7[0] = 0 7843 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_SET(r,d) (r).ana_lane_1_quad_b_ctrl7[0] = d 7844 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_GET(r) (r).ana_lane_1_quad_b_ctrl7[0] 7845 7846 /* 7847 * These macros can be used to access individual fields. 7848 */ 7849 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_1_quad_b_ctrl7[0]) >> 8) & 0x1) 7850 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_1_quad_b_ctrl7[0]=(((r).ana_lane_1_quad_b_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 7851 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_1_quad_b_ctrl7[0]) & 0x1f) 7852 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_1_quad_b_ctrl7[0]=(((r).ana_lane_1_quad_b_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 7853 7854 /* 7855 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL7. 7856 */ 7857 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r,_r._ana_lane_1_quad_b_ctrl7) 7858 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r,_r._ana_lane_1_quad_b_ctrl7) 7859 7860 /* 7861 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7862 * will be redefined without the chip prefix for easier programming. 7863 * If multiple chips will be programmed in the same source file, then you should 7864 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7865 * and refer to the fully qualified versions. 7866 */ 7867 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7868 7869 #define ANA_LANE_1_QUAD_B_CTRL7r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r 7870 #define ANA_LANE_1_QUAD_B_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_SIZE 7871 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_t ANA_LANE_1_QUAD_B_CTRL7r_t; 7872 #define ANA_LANE_1_QUAD_B_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_CLR 7873 #define ANA_LANE_1_QUAD_B_CTRL7r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_SET 7874 #define ANA_LANE_1_QUAD_B_CTRL7r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_GET 7875 #define ANA_LANE_1_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET 7876 #define ANA_LANE_1_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET 7877 #define ANA_LANE_1_QUAD_B_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_LA_LIN_MODEf_GET 7878 #define ANA_LANE_1_QUAD_B_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r_LA_LIN_MODEf_SET 7879 #define READ_ANA_LANE_1_QUAD_B_CTRL7r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL7r 7880 #define WRITE_ANA_LANE_1_QUAD_B_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL7r 7881 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL7r 7882 7883 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7884 /******************************************************************************* 7885 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL7r' 7886 */ 7887 7888 7889 7890 7891 /******************************************************************************* 7892 * CHIP: BCMI_HURACAN 7893 * REGISTER: ANA_LANE_1_QUAD_B_CTRL8 7894 * BLOCKS: ANA_LANE_1_QUAD_B 7895 * REGADDR: 0x9208 7896 * DEVAD: 1 7897 * DESC: control registers 0 7898 * RESETVAL: 0x0 (0) 7899 * ACCESS: R/W 7900 * FIELDS: 7901 * LA_PD 7902 * LA_PD_IDLE 7903 * RXTX_RESERVED_FOR_99_95 7904 */ 7905 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r (0x00019208 | PHYMOD_REG_ACC_RAW) 7906 7907 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_SIZE 4 7908 7909 /* 7910 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL8. 7911 */ 7912 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_s { 7913 uint32_t v[1]; 7914 uint32_t ana_lane_1_quad_b_ctrl8[1]; 7915 uint32_t _ana_lane_1_quad_b_ctrl8; 7916 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_t; 7917 7918 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_CLR(r) (r).ana_lane_1_quad_b_ctrl8[0] = 0 7919 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_SET(r,d) (r).ana_lane_1_quad_b_ctrl8[0] = d 7920 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_GET(r) (r).ana_lane_1_quad_b_ctrl8[0] 7921 7922 /* 7923 * These macros can be used to access individual fields. 7924 */ 7925 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_1_quad_b_ctrl8[0]) >> 4) & 0x1f) 7926 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_1_quad_b_ctrl8[0]=(((r).ana_lane_1_quad_b_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 7927 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_1_quad_b_ctrl8[0]) >> 1) & 0x1) 7928 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_1_quad_b_ctrl8[0]=(((r).ana_lane_1_quad_b_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 7929 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_1_quad_b_ctrl8[0]) & 0x1) 7930 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_1_quad_b_ctrl8[0]=(((r).ana_lane_1_quad_b_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 7931 7932 /* 7933 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL8. 7934 */ 7935 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r,_r._ana_lane_1_quad_b_ctrl8) 7936 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r,_r._ana_lane_1_quad_b_ctrl8) 7937 7938 /* 7939 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 7940 * will be redefined without the chip prefix for easier programming. 7941 * If multiple chips will be programmed in the same source file, then you should 7942 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 7943 * and refer to the fully qualified versions. 7944 */ 7945 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 7946 7947 #define ANA_LANE_1_QUAD_B_CTRL8r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r 7948 #define ANA_LANE_1_QUAD_B_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_SIZE 7949 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_t ANA_LANE_1_QUAD_B_CTRL8r_t; 7950 #define ANA_LANE_1_QUAD_B_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_CLR 7951 #define ANA_LANE_1_QUAD_B_CTRL8r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_SET 7952 #define ANA_LANE_1_QUAD_B_CTRL8r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_GET 7953 #define ANA_LANE_1_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 7954 #define ANA_LANE_1_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 7955 #define ANA_LANE_1_QUAD_B_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PD_IDLEf_GET 7956 #define ANA_LANE_1_QUAD_B_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PD_IDLEf_SET 7957 #define ANA_LANE_1_QUAD_B_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PDf_GET 7958 #define ANA_LANE_1_QUAD_B_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r_LA_PDf_SET 7959 #define READ_ANA_LANE_1_QUAD_B_CTRL8r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL8r 7960 #define WRITE_ANA_LANE_1_QUAD_B_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL8r 7961 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL8r 7962 7963 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 7964 /******************************************************************************* 7965 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL8r' 7966 */ 7967 7968 7969 7970 7971 /******************************************************************************* 7972 * CHIP: BCMI_HURACAN 7973 * REGISTER: ANA_LANE_1_QUAD_B_CTRL9 7974 * BLOCKS: ANA_LANE_1_QUAD_B 7975 * REGADDR: 0x9209 7976 * DEVAD: 1 7977 * DESC: control registers 0 7978 * RESETVAL: 0x0 (0) 7979 * ACCESS: R/W 7980 * FIELDS: 7981 * DRV_POST1 7982 * DLINE_SWING_1 7983 * DLINE_SWING_2 7984 * DLINE_DELAY_CTRL 7985 */ 7986 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r (0x00019209 | PHYMOD_REG_ACC_RAW) 7987 7988 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_SIZE 4 7989 7990 /* 7991 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL9. 7992 */ 7993 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_s { 7994 uint32_t v[1]; 7995 uint32_t ana_lane_1_quad_b_ctrl9[1]; 7996 uint32_t _ana_lane_1_quad_b_ctrl9; 7997 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_t; 7998 7999 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_CLR(r) (r).ana_lane_1_quad_b_ctrl9[0] = 0 8000 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_SET(r,d) (r).ana_lane_1_quad_b_ctrl9[0] = d 8001 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_GET(r) (r).ana_lane_1_quad_b_ctrl9[0] 8002 8003 /* 8004 * These macros can be used to access individual fields. 8005 */ 8006 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_1_quad_b_ctrl9[0]) >> 12) & 0x7) 8007 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_1_quad_b_ctrl9[0]=(((r).ana_lane_1_quad_b_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 8008 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_1_quad_b_ctrl9[0]) >> 8) & 0x3) 8009 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_1_quad_b_ctrl9[0]=(((r).ana_lane_1_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 8010 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_1_quad_b_ctrl9[0]) >> 4) & 0x3) 8011 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_1_quad_b_ctrl9[0]=(((r).ana_lane_1_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 8012 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_1_quad_b_ctrl9[0]) & 0xf) 8013 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_1_quad_b_ctrl9[0]=(((r).ana_lane_1_quad_b_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 8014 8015 /* 8016 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL9. 8017 */ 8018 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r,_r._ana_lane_1_quad_b_ctrl9) 8019 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r,_r._ana_lane_1_quad_b_ctrl9) 8020 8021 /* 8022 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8023 * will be redefined without the chip prefix for easier programming. 8024 * If multiple chips will be programmed in the same source file, then you should 8025 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8026 * and refer to the fully qualified versions. 8027 */ 8028 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8029 8030 #define ANA_LANE_1_QUAD_B_CTRL9r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r 8031 #define ANA_LANE_1_QUAD_B_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_SIZE 8032 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_t ANA_LANE_1_QUAD_B_CTRL9r_t; 8033 #define ANA_LANE_1_QUAD_B_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_CLR 8034 #define ANA_LANE_1_QUAD_B_CTRL9r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_SET 8035 #define ANA_LANE_1_QUAD_B_CTRL9r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_GET 8036 #define ANA_LANE_1_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET 8037 #define ANA_LANE_1_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET 8038 #define ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_2f_GET 8039 #define ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_2f_SET 8040 #define ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_1f_GET 8041 #define ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DLINE_SWING_1f_SET 8042 #define ANA_LANE_1_QUAD_B_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DRV_POST1f_GET 8043 #define ANA_LANE_1_QUAD_B_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r_DRV_POST1f_SET 8044 #define READ_ANA_LANE_1_QUAD_B_CTRL9r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL9r 8045 #define WRITE_ANA_LANE_1_QUAD_B_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL9r 8046 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL9r 8047 8048 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8049 /******************************************************************************* 8050 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL9r' 8051 */ 8052 8053 8054 8055 8056 /******************************************************************************* 8057 * CHIP: BCMI_HURACAN 8058 * REGISTER: ANA_LANE_1_QUAD_B_CTRL10 8059 * BLOCKS: ANA_LANE_1_QUAD_B 8060 * REGADDR: 0x920a 8061 * DEVAD: 1 8062 * DESC: control registers 0 8063 * RESETVAL: 0x0 (0) 8064 * ACCESS: R/W 8065 * FIELDS: 8066 * DRV_PWD 8067 * DLINE_PWD 8068 * DRV_VBSEL 8069 * DRV_MAIN 8070 * DRV_MAIN_PU 8071 */ 8072 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r (0x0001920a | PHYMOD_REG_ACC_RAW) 8073 8074 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_SIZE 4 8075 8076 /* 8077 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL10. 8078 */ 8079 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_s { 8080 uint32_t v[1]; 8081 uint32_t ana_lane_1_quad_b_ctrl10[1]; 8082 uint32_t _ana_lane_1_quad_b_ctrl10; 8083 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_t; 8084 8085 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_CLR(r) (r).ana_lane_1_quad_b_ctrl10[0] = 0 8086 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_SET(r,d) (r).ana_lane_1_quad_b_ctrl10[0] = d 8087 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_GET(r) (r).ana_lane_1_quad_b_ctrl10[0] 8088 8089 /* 8090 * These macros can be used to access individual fields. 8091 */ 8092 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_1_quad_b_ctrl10[0]) >> 12) & 0xf) 8093 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_1_quad_b_ctrl10[0]=(((r).ana_lane_1_quad_b_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 8094 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_1_quad_b_ctrl10[0]) >> 4) & 0x3f) 8095 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_1_quad_b_ctrl10[0]=(((r).ana_lane_1_quad_b_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 8096 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_1_quad_b_ctrl10[0]) >> 2) & 0x1) 8097 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_1_quad_b_ctrl10[0]=(((r).ana_lane_1_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 8098 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_1_quad_b_ctrl10[0]) >> 1) & 0x1) 8099 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_1_quad_b_ctrl10[0]=(((r).ana_lane_1_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 8100 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_1_quad_b_ctrl10[0]) & 0x1) 8101 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_1_quad_b_ctrl10[0]=(((r).ana_lane_1_quad_b_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 8102 8103 /* 8104 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL10. 8105 */ 8106 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r,_r._ana_lane_1_quad_b_ctrl10) 8107 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r,_r._ana_lane_1_quad_b_ctrl10) 8108 8109 /* 8110 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8111 * will be redefined without the chip prefix for easier programming. 8112 * If multiple chips will be programmed in the same source file, then you should 8113 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8114 * and refer to the fully qualified versions. 8115 */ 8116 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8117 8118 #define ANA_LANE_1_QUAD_B_CTRL10r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r 8119 #define ANA_LANE_1_QUAD_B_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_SIZE 8120 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_t ANA_LANE_1_QUAD_B_CTRL10r_t; 8121 #define ANA_LANE_1_QUAD_B_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_CLR 8122 #define ANA_LANE_1_QUAD_B_CTRL10r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_SET 8123 #define ANA_LANE_1_QUAD_B_CTRL10r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_GET 8124 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET 8125 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET 8126 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAINf_GET 8127 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_MAINf_SET 8128 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_VBSELf_GET 8129 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_VBSELf_SET 8130 #define ANA_LANE_1_QUAD_B_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DLINE_PWDf_GET 8131 #define ANA_LANE_1_QUAD_B_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DLINE_PWDf_SET 8132 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_PWDf_GET 8133 #define ANA_LANE_1_QUAD_B_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r_DRV_PWDf_SET 8134 #define READ_ANA_LANE_1_QUAD_B_CTRL10r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL10r 8135 #define WRITE_ANA_LANE_1_QUAD_B_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL10r 8136 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL10r 8137 8138 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8139 /******************************************************************************* 8140 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL10r' 8141 */ 8142 8143 8144 8145 8146 /******************************************************************************* 8147 * CHIP: BCMI_HURACAN 8148 * REGISTER: ANA_LANE_1_QUAD_B_CTRL11 8149 * BLOCKS: ANA_LANE_1_QUAD_B 8150 * REGADDR: 0x920b 8151 * DEVAD: 1 8152 * DESC: control registers 0 8153 * RESETVAL: 0x0 (0) 8154 * ACCESS: R/W 8155 * FIELDS: 8156 * RXTX_RESERVED_FOR_143_128 8157 */ 8158 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r (0x0001920b | PHYMOD_REG_ACC_RAW) 8159 8160 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_SIZE 4 8161 8162 /* 8163 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL11. 8164 */ 8165 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_s { 8166 uint32_t v[1]; 8167 uint32_t ana_lane_1_quad_b_ctrl11[1]; 8168 uint32_t _ana_lane_1_quad_b_ctrl11; 8169 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_t; 8170 8171 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_CLR(r) (r).ana_lane_1_quad_b_ctrl11[0] = 0 8172 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_SET(r,d) (r).ana_lane_1_quad_b_ctrl11[0] = d 8173 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_GET(r) (r).ana_lane_1_quad_b_ctrl11[0] 8174 8175 /* 8176 * These macros can be used to access individual fields. 8177 */ 8178 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_1_quad_b_ctrl11[0]) & 0xffff) 8179 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_1_quad_b_ctrl11[0]=(((r).ana_lane_1_quad_b_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 8180 8181 /* 8182 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL11. 8183 */ 8184 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r,_r._ana_lane_1_quad_b_ctrl11) 8185 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r,_r._ana_lane_1_quad_b_ctrl11) 8186 8187 /* 8188 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8189 * will be redefined without the chip prefix for easier programming. 8190 * If multiple chips will be programmed in the same source file, then you should 8191 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8192 * and refer to the fully qualified versions. 8193 */ 8194 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8195 8196 #define ANA_LANE_1_QUAD_B_CTRL11r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r 8197 #define ANA_LANE_1_QUAD_B_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_SIZE 8198 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_t ANA_LANE_1_QUAD_B_CTRL11r_t; 8199 #define ANA_LANE_1_QUAD_B_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_CLR 8200 #define ANA_LANE_1_QUAD_B_CTRL11r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_SET 8201 #define ANA_LANE_1_QUAD_B_CTRL11r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_GET 8202 #define ANA_LANE_1_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 8203 #define ANA_LANE_1_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 8204 #define READ_ANA_LANE_1_QUAD_B_CTRL11r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL11r 8205 #define WRITE_ANA_LANE_1_QUAD_B_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL11r 8206 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL11r 8207 8208 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8209 /******************************************************************************* 8210 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL11r' 8211 */ 8212 8213 8214 8215 8216 /******************************************************************************* 8217 * CHIP: BCMI_HURACAN 8218 * REGISTER: ANA_LANE_1_QUAD_B_CTRL12 8219 * BLOCKS: ANA_LANE_1_QUAD_B 8220 * REGADDR: 0x920c 8221 * DEVAD: 1 8222 * DESC: control registers 0 8223 * RESETVAL: 0x0 (0) 8224 * ACCESS: R/W 8225 * FIELDS: 8226 * LA_RESCAL_FRC_VAL 8227 * LA_RESCAL_FRC 8228 * DRV_RESCAL_FRC_VAL 8229 * DRV_RESCAL_FRC 8230 */ 8231 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r (0x0001920c | PHYMOD_REG_ACC_RAW) 8232 8233 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_SIZE 4 8234 8235 /* 8236 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL12. 8237 */ 8238 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_s { 8239 uint32_t v[1]; 8240 uint32_t ana_lane_1_quad_b_ctrl12[1]; 8241 uint32_t _ana_lane_1_quad_b_ctrl12; 8242 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_t; 8243 8244 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_CLR(r) (r).ana_lane_1_quad_b_ctrl12[0] = 0 8245 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_SET(r,d) (r).ana_lane_1_quad_b_ctrl12[0] = d 8246 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_GET(r) (r).ana_lane_1_quad_b_ctrl12[0] 8247 8248 /* 8249 * These macros can be used to access individual fields. 8250 */ 8251 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_b_ctrl12[0]) >> 12) & 0x1) 8252 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_b_ctrl12[0]=(((r).ana_lane_1_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 8253 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_b_ctrl12[0]) >> 8) & 0xf) 8254 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_b_ctrl12[0]=(((r).ana_lane_1_quad_b_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 8255 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_b_ctrl12[0]) >> 4) & 0x1) 8256 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_b_ctrl12[0]=(((r).ana_lane_1_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 8257 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_b_ctrl12[0]) & 0xf) 8258 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_b_ctrl12[0]=(((r).ana_lane_1_quad_b_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 8259 8260 /* 8261 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL12. 8262 */ 8263 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r,_r._ana_lane_1_quad_b_ctrl12) 8264 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r,_r._ana_lane_1_quad_b_ctrl12) 8265 8266 /* 8267 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8268 * will be redefined without the chip prefix for easier programming. 8269 * If multiple chips will be programmed in the same source file, then you should 8270 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8271 * and refer to the fully qualified versions. 8272 */ 8273 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8274 8275 #define ANA_LANE_1_QUAD_B_CTRL12r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r 8276 #define ANA_LANE_1_QUAD_B_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_SIZE 8277 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_t ANA_LANE_1_QUAD_B_CTRL12r_t; 8278 #define ANA_LANE_1_QUAD_B_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_CLR 8279 #define ANA_LANE_1_QUAD_B_CTRL12r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_SET 8280 #define ANA_LANE_1_QUAD_B_CTRL12r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_GET 8281 #define ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET 8282 #define ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET 8283 #define ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET 8284 #define ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET 8285 #define ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET 8286 #define ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET 8287 #define ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET 8288 #define ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET 8289 #define READ_ANA_LANE_1_QUAD_B_CTRL12r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL12r 8290 #define WRITE_ANA_LANE_1_QUAD_B_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL12r 8291 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL12r 8292 8293 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8294 /******************************************************************************* 8295 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL12r' 8296 */ 8297 8298 8299 8300 8301 /******************************************************************************* 8302 * CHIP: BCMI_HURACAN 8303 * REGISTER: ANA_LANE_1_QUAD_B_CTRL13 8304 * BLOCKS: ANA_LANE_1_QUAD_B 8305 * REGADDR: 0x920d 8306 * DEVAD: 1 8307 * DESC: control registers 0 8308 * RESETVAL: 0x0 (0) 8309 * ACCESS: R/W 8310 * FIELDS: 8311 * CTLE_RESCAL_FRC_VAL 8312 * CTLE_RESCAL_FRC 8313 */ 8314 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r (0x0001920d | PHYMOD_REG_ACC_RAW) 8315 8316 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_SIZE 4 8317 8318 /* 8319 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL13. 8320 */ 8321 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_s { 8322 uint32_t v[1]; 8323 uint32_t ana_lane_1_quad_b_ctrl13[1]; 8324 uint32_t _ana_lane_1_quad_b_ctrl13; 8325 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_t; 8326 8327 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CLR(r) (r).ana_lane_1_quad_b_ctrl13[0] = 0 8328 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_SET(r,d) (r).ana_lane_1_quad_b_ctrl13[0] = d 8329 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_GET(r) (r).ana_lane_1_quad_b_ctrl13[0] 8330 8331 /* 8332 * These macros can be used to access individual fields. 8333 */ 8334 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_b_ctrl13[0]) >> 4) & 0x1) 8335 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_b_ctrl13[0]=(((r).ana_lane_1_quad_b_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 8336 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_b_ctrl13[0]) & 0xf) 8337 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_b_ctrl13[0]=(((r).ana_lane_1_quad_b_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 8338 8339 /* 8340 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL13. 8341 */ 8342 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r,_r._ana_lane_1_quad_b_ctrl13) 8343 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r,_r._ana_lane_1_quad_b_ctrl13) 8344 8345 /* 8346 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8347 * will be redefined without the chip prefix for easier programming. 8348 * If multiple chips will be programmed in the same source file, then you should 8349 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8350 * and refer to the fully qualified versions. 8351 */ 8352 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8353 8354 #define ANA_LANE_1_QUAD_B_CTRL13r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r 8355 #define ANA_LANE_1_QUAD_B_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_SIZE 8356 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_t ANA_LANE_1_QUAD_B_CTRL13r_t; 8357 #define ANA_LANE_1_QUAD_B_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CLR 8358 #define ANA_LANE_1_QUAD_B_CTRL13r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_SET 8359 #define ANA_LANE_1_QUAD_B_CTRL13r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_GET 8360 #define ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET 8361 #define ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET 8362 #define ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 8363 #define ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 8364 #define READ_ANA_LANE_1_QUAD_B_CTRL13r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL13r 8365 #define WRITE_ANA_LANE_1_QUAD_B_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL13r 8366 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL13r 8367 8368 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8369 /******************************************************************************* 8370 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL13r' 8371 */ 8372 8373 8374 8375 8376 /******************************************************************************* 8377 * CHIP: BCMI_HURACAN 8378 * REGISTER: ANA_LANE_1_QUAD_B_CTRL14 8379 * BLOCKS: ANA_LANE_1_QUAD_B 8380 * REGADDR: 0x920e 8381 * DEVAD: 1 8382 * DESC: control registers 0 8383 * RESETVAL: 0x0 (0) 8384 * ACCESS: R/W 8385 * FIELDS: 8386 * TX_IDLE_FRC_VAL 8387 * TX_IDLE_FRC 8388 * RXSD_IDLE_OVRD 8389 */ 8390 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r (0x0001920e | PHYMOD_REG_ACC_RAW) 8391 8392 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_SIZE 4 8393 8394 /* 8395 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL14. 8396 */ 8397 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_s { 8398 uint32_t v[1]; 8399 uint32_t ana_lane_1_quad_b_ctrl14[1]; 8400 uint32_t _ana_lane_1_quad_b_ctrl14; 8401 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_t; 8402 8403 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_CLR(r) (r).ana_lane_1_quad_b_ctrl14[0] = 0 8404 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_SET(r,d) (r).ana_lane_1_quad_b_ctrl14[0] = d 8405 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_GET(r) (r).ana_lane_1_quad_b_ctrl14[0] 8406 8407 /* 8408 * These macros can be used to access individual fields. 8409 */ 8410 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_1_quad_b_ctrl14[0]) >> 4) & 0x1) 8411 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_1_quad_b_ctrl14[0]=(((r).ana_lane_1_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 8412 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_1_quad_b_ctrl14[0]) >> 1) & 0x1) 8413 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_1_quad_b_ctrl14[0]=(((r).ana_lane_1_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 8414 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_1_quad_b_ctrl14[0]) & 0x1) 8415 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_b_ctrl14[0]=(((r).ana_lane_1_quad_b_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 8416 8417 /* 8418 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL14. 8419 */ 8420 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r,_r._ana_lane_1_quad_b_ctrl14) 8421 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r,_r._ana_lane_1_quad_b_ctrl14) 8422 8423 /* 8424 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8425 * will be redefined without the chip prefix for easier programming. 8426 * If multiple chips will be programmed in the same source file, then you should 8427 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8428 * and refer to the fully qualified versions. 8429 */ 8430 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8431 8432 #define ANA_LANE_1_QUAD_B_CTRL14r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r 8433 #define ANA_LANE_1_QUAD_B_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_SIZE 8434 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_t ANA_LANE_1_QUAD_B_CTRL14r_t; 8435 #define ANA_LANE_1_QUAD_B_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_CLR 8436 #define ANA_LANE_1_QUAD_B_CTRL14r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_SET 8437 #define ANA_LANE_1_QUAD_B_CTRL14r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_GET 8438 #define ANA_LANE_1_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET 8439 #define ANA_LANE_1_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET 8440 #define ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET 8441 #define ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET 8442 #define ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET 8443 #define ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET 8444 #define READ_ANA_LANE_1_QUAD_B_CTRL14r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL14r 8445 #define WRITE_ANA_LANE_1_QUAD_B_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL14r 8446 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL14r 8447 8448 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8449 /******************************************************************************* 8450 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL14r' 8451 */ 8452 8453 8454 8455 8456 /******************************************************************************* 8457 * CHIP: BCMI_HURACAN 8458 * REGISTER: ANA_LANE_1_QUAD_B_CTRL15 8459 * BLOCKS: ANA_LANE_1_QUAD_B 8460 * REGADDR: 0x920f 8461 * DEVAD: 1 8462 * DESC: sigdet filter settings 0 8463 * RESETVAL: 0x0 (0) 8464 * ACCESS: R/W 8465 * FIELDS: 8466 * SIGDET_DIS 8467 * SIGDET_1US_EN 8468 * SIGDET_FRC_VAL 8469 * SIGDET_FRC 8470 * HOLD_LOS_COUNT 8471 * HOLD_SD_COUNT 8472 */ 8473 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r (0x0001920f | PHYMOD_REG_ACC_RAW) 8474 8475 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIZE 4 8476 8477 /* 8478 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL15. 8479 */ 8480 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_s { 8481 uint32_t v[1]; 8482 uint32_t ana_lane_1_quad_b_ctrl15[1]; 8483 uint32_t _ana_lane_1_quad_b_ctrl15; 8484 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_t; 8485 8486 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_CLR(r) (r).ana_lane_1_quad_b_ctrl15[0] = 0 8487 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SET(r,d) (r).ana_lane_1_quad_b_ctrl15[0] = d 8488 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_GET(r) (r).ana_lane_1_quad_b_ctrl15[0] 8489 8490 /* 8491 * These macros can be used to access individual fields. 8492 */ 8493 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_b_ctrl15[0]) >> 8) & 0x7) 8494 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_b_ctrl15[0]=(((r).ana_lane_1_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 8495 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_1_quad_b_ctrl15[0]) >> 4) & 0x7) 8496 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_b_ctrl15[0]=(((r).ana_lane_1_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 8497 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_1_quad_b_ctrl15[0]) >> 3) & 0x1) 8498 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_1_quad_b_ctrl15[0]=(((r).ana_lane_1_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 8499 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_b_ctrl15[0]) >> 2) & 0x1) 8500 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_b_ctrl15[0]=(((r).ana_lane_1_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 8501 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_1_quad_b_ctrl15[0]) >> 1) & 0x1) 8502 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_1_quad_b_ctrl15[0]=(((r).ana_lane_1_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 8503 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_1_quad_b_ctrl15[0]) & 0x1) 8504 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_1_quad_b_ctrl15[0]=(((r).ana_lane_1_quad_b_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 8505 8506 /* 8507 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL15. 8508 */ 8509 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r,_r._ana_lane_1_quad_b_ctrl15) 8510 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r,_r._ana_lane_1_quad_b_ctrl15) 8511 8512 /* 8513 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8514 * will be redefined without the chip prefix for easier programming. 8515 * If multiple chips will be programmed in the same source file, then you should 8516 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8517 * and refer to the fully qualified versions. 8518 */ 8519 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8520 8521 #define ANA_LANE_1_QUAD_B_CTRL15r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r 8522 #define ANA_LANE_1_QUAD_B_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIZE 8523 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_t ANA_LANE_1_QUAD_B_CTRL15r_t; 8524 #define ANA_LANE_1_QUAD_B_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_CLR 8525 #define ANA_LANE_1_QUAD_B_CTRL15r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SET 8526 #define ANA_LANE_1_QUAD_B_CTRL15r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_GET 8527 #define ANA_LANE_1_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET 8528 #define ANA_LANE_1_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET 8529 #define ANA_LANE_1_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET 8530 #define ANA_LANE_1_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET 8531 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRCf_GET 8532 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRCf_SET 8533 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET 8534 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET 8535 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET 8536 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET 8537 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_DISf_GET 8538 #define ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r_SIGDET_DISf_SET 8539 #define READ_ANA_LANE_1_QUAD_B_CTRL15r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL15r 8540 #define WRITE_ANA_LANE_1_QUAD_B_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL15r 8541 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL15r 8542 8543 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8544 /******************************************************************************* 8545 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL15r' 8546 */ 8547 8548 8549 8550 8551 /******************************************************************************* 8552 * CHIP: BCMI_HURACAN 8553 * REGISTER: ANA_LANE_1_QUAD_B_CTRL16 8554 * BLOCKS: ANA_LANE_1_QUAD_B 8555 * REGADDR: 0x9210 8556 * DEVAD: 1 8557 * DESC: sigdet filter settings 1 8558 * RESETVAL: 0x0 (0) 8559 * ACCESS: R/W 8560 * FIELDS: 8561 * LOS_COUNT 8562 * SD_COUNT 8563 */ 8564 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r (0x00019210 | PHYMOD_REG_ACC_RAW) 8565 8566 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SIZE 4 8567 8568 /* 8569 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_CTRL16. 8570 */ 8571 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_s { 8572 uint32_t v[1]; 8573 uint32_t ana_lane_1_quad_b_ctrl16[1]; 8574 uint32_t _ana_lane_1_quad_b_ctrl16; 8575 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_t; 8576 8577 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_CLR(r) (r).ana_lane_1_quad_b_ctrl16[0] = 0 8578 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SET(r,d) (r).ana_lane_1_quad_b_ctrl16[0] = d 8579 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_GET(r) (r).ana_lane_1_quad_b_ctrl16[0] 8580 8581 /* 8582 * These macros can be used to access individual fields. 8583 */ 8584 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_b_ctrl16[0]) >> 8) & 0x1f) 8585 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_b_ctrl16[0]=(((r).ana_lane_1_quad_b_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 8586 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_1_quad_b_ctrl16[0]) & 0x1f) 8587 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_b_ctrl16[0]=(((r).ana_lane_1_quad_b_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 8588 8589 /* 8590 * These macros can be used to access ANA_LANE_1_QUAD_B_CTRL16. 8591 */ 8592 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r,_r._ana_lane_1_quad_b_ctrl16) 8593 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r,_r._ana_lane_1_quad_b_ctrl16) 8594 8595 /* 8596 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8597 * will be redefined without the chip prefix for easier programming. 8598 * If multiple chips will be programmed in the same source file, then you should 8599 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8600 * and refer to the fully qualified versions. 8601 */ 8602 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8603 8604 #define ANA_LANE_1_QUAD_B_CTRL16r BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r 8605 #define ANA_LANE_1_QUAD_B_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SIZE 8606 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_t ANA_LANE_1_QUAD_B_CTRL16r_t; 8607 #define ANA_LANE_1_QUAD_B_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_CLR 8608 #define ANA_LANE_1_QUAD_B_CTRL16r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SET 8609 #define ANA_LANE_1_QUAD_B_CTRL16r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_GET 8610 #define ANA_LANE_1_QUAD_B_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SD_COUNTf_GET 8611 #define ANA_LANE_1_QUAD_B_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_SD_COUNTf_SET 8612 #define ANA_LANE_1_QUAD_B_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_LOS_COUNTf_GET 8613 #define ANA_LANE_1_QUAD_B_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r_LOS_COUNTf_SET 8614 #define READ_ANA_LANE_1_QUAD_B_CTRL16r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_CTRL16r 8615 #define WRITE_ANA_LANE_1_QUAD_B_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_CTRL16r 8616 #define MODIFY_ANA_LANE_1_QUAD_B_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_CTRL16r 8617 8618 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8619 /******************************************************************************* 8620 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_CTRL16r' 8621 */ 8622 8623 8624 8625 8626 /******************************************************************************* 8627 * CHIP: BCMI_HURACAN 8628 * REGISTER: ANA_LANE_1_QUAD_B_STATUS0 8629 * BLOCKS: ANA_LANE_1_QUAD_B 8630 * REGADDR: 0x9220 8631 * DEVAD: 1 8632 * DESC: status registers 0 8633 * RESETVAL: 0x0 (0) 8634 * ACCESS: R/W 8635 * FIELDS: 8636 * O_RX_SIGDET 8637 * DG_RX_SIGDET 8638 */ 8639 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r (0x00019220 | PHYMOD_REG_ACC_RAW) 8640 8641 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_SIZE 4 8642 8643 /* 8644 * This structure should be used to declare and program ANA_LANE_1_QUAD_B_STATUS0. 8645 */ 8646 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_s { 8647 uint32_t v[1]; 8648 uint32_t ana_lane_1_quad_b_status0[1]; 8649 uint32_t _ana_lane_1_quad_b_status0; 8650 } BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_t; 8651 8652 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_CLR(r) (r).ana_lane_1_quad_b_status0[0] = 0 8653 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_SET(r,d) (r).ana_lane_1_quad_b_status0[0] = d 8654 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_GET(r) (r).ana_lane_1_quad_b_status0[0] 8655 8656 /* 8657 * These macros can be used to access individual fields. 8658 */ 8659 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_1_quad_b_status0[0]) >> 1) & 0x1) 8660 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_b_status0[0]=(((r).ana_lane_1_quad_b_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 8661 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_1_quad_b_status0[0]) & 0x1) 8662 #define BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_b_status0[0]=(((r).ana_lane_1_quad_b_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 8663 8664 /* 8665 * These macros can be used to access ANA_LANE_1_QUAD_B_STATUS0. 8666 */ 8667 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r,_r._ana_lane_1_quad_b_status0) 8668 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r,_r._ana_lane_1_quad_b_status0) 8669 8670 /* 8671 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8672 * will be redefined without the chip prefix for easier programming. 8673 * If multiple chips will be programmed in the same source file, then you should 8674 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8675 * and refer to the fully qualified versions. 8676 */ 8677 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8678 8679 #define ANA_LANE_1_QUAD_B_STATUS0r BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r 8680 #define ANA_LANE_1_QUAD_B_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_SIZE 8681 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_t ANA_LANE_1_QUAD_B_STATUS0r_t; 8682 #define ANA_LANE_1_QUAD_B_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_CLR 8683 #define ANA_LANE_1_QUAD_B_STATUS0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_SET 8684 #define ANA_LANE_1_QUAD_B_STATUS0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_GET 8685 #define ANA_LANE_1_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET 8686 #define ANA_LANE_1_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET 8687 #define ANA_LANE_1_QUAD_B_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_O_RX_SIGDETf_GET 8688 #define ANA_LANE_1_QUAD_B_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r_O_RX_SIGDETf_SET 8689 #define READ_ANA_LANE_1_QUAD_B_STATUS0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_B_STATUS0r 8690 #define WRITE_ANA_LANE_1_QUAD_B_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_B_STATUS0r 8691 #define MODIFY_ANA_LANE_1_QUAD_B_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_B_STATUS0r 8692 8693 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8694 /******************************************************************************* 8695 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_B_STATUS0r' 8696 */ 8697 8698 8699 8700 8701 /******************************************************************************* 8702 * CHIP: BCMI_HURACAN 8703 * REGISTER: ANA_LANE_2_QUAD_B_CTRL0 8704 * BLOCKS: ANA_LANE_2_QUAD_B 8705 * REGADDR: 0x9400 8706 * DEVAD: 1 8707 * DESC: control registers 0 8708 * RESETVAL: 0x0 (0) 8709 * ACCESS: R/W 8710 * FIELDS: 8711 * RXTX_PWRDN 8712 * RX_SIGDET_BYPASS 8713 * RX_SIGDET_PWRDN 8714 * RX_SIGDECT_12GMODE 8715 * DC_COUPLE 8716 */ 8717 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r (0x00019400 | PHYMOD_REG_ACC_RAW) 8718 8719 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_SIZE 4 8720 8721 /* 8722 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL0. 8723 */ 8724 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_s { 8725 uint32_t v[1]; 8726 uint32_t ana_lane_2_quad_b_ctrl0[1]; 8727 uint32_t _ana_lane_2_quad_b_ctrl0; 8728 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_t; 8729 8730 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_CLR(r) (r).ana_lane_2_quad_b_ctrl0[0] = 0 8731 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_SET(r,d) (r).ana_lane_2_quad_b_ctrl0[0] = d 8732 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_GET(r) (r).ana_lane_2_quad_b_ctrl0[0] 8733 8734 /* 8735 * These macros can be used to access individual fields. 8736 */ 8737 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_2_quad_b_ctrl0[0]) >> 4) & 0x1) 8738 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_2_quad_b_ctrl0[0]=(((r).ana_lane_2_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 8739 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_2_quad_b_ctrl0[0]) >> 3) & 0x1) 8740 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_2_quad_b_ctrl0[0]=(((r).ana_lane_2_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 8741 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_2_quad_b_ctrl0[0]) >> 2) & 0x1) 8742 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_2_quad_b_ctrl0[0]=(((r).ana_lane_2_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 8743 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_2_quad_b_ctrl0[0]) >> 1) & 0x1) 8744 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_2_quad_b_ctrl0[0]=(((r).ana_lane_2_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 8745 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_2_quad_b_ctrl0[0]) & 0x1) 8746 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_2_quad_b_ctrl0[0]=(((r).ana_lane_2_quad_b_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 8747 8748 /* 8749 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL0. 8750 */ 8751 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r,_r._ana_lane_2_quad_b_ctrl0) 8752 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r,_r._ana_lane_2_quad_b_ctrl0) 8753 8754 /* 8755 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8756 * will be redefined without the chip prefix for easier programming. 8757 * If multiple chips will be programmed in the same source file, then you should 8758 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8759 * and refer to the fully qualified versions. 8760 */ 8761 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8762 8763 #define ANA_LANE_2_QUAD_B_CTRL0r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r 8764 #define ANA_LANE_2_QUAD_B_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_SIZE 8765 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_t ANA_LANE_2_QUAD_B_CTRL0r_t; 8766 #define ANA_LANE_2_QUAD_B_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_CLR 8767 #define ANA_LANE_2_QUAD_B_CTRL0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_SET 8768 #define ANA_LANE_2_QUAD_B_CTRL0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_GET 8769 #define ANA_LANE_2_QUAD_B_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_DC_COUPLEf_GET 8770 #define ANA_LANE_2_QUAD_B_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_DC_COUPLEf_SET 8771 #define ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET 8772 #define ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET 8773 #define ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET 8774 #define ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET 8775 #define ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET 8776 #define ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET 8777 #define ANA_LANE_2_QUAD_B_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RXTX_PWRDNf_GET 8778 #define ANA_LANE_2_QUAD_B_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r_RXTX_PWRDNf_SET 8779 #define READ_ANA_LANE_2_QUAD_B_CTRL0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL0r 8780 #define WRITE_ANA_LANE_2_QUAD_B_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL0r 8781 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL0r 8782 8783 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8784 /******************************************************************************* 8785 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL0r' 8786 */ 8787 8788 8789 8790 8791 /******************************************************************************* 8792 * CHIP: BCMI_HURACAN 8793 * REGISTER: ANA_LANE_2_QUAD_B_CTRL1 8794 * BLOCKS: ANA_LANE_2_QUAD_B 8795 * REGADDR: 0x9401 8796 * DEVAD: 1 8797 * DESC: control registers 0 8798 * RESETVAL: 0x0 (0) 8799 * ACCESS: R/W 8800 * FIELDS: 8801 * RX_SIGDET_THRESHOLD 8802 * REF_OCL 8803 * OCL_PWRDN 8804 * OCL_DISABLE_LOOP 8805 * RXTX_RESERVED_FOR_15_12 8806 */ 8807 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r (0x00019401 | PHYMOD_REG_ACC_RAW) 8808 8809 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_SIZE 4 8810 8811 /* 8812 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL1. 8813 */ 8814 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_s { 8815 uint32_t v[1]; 8816 uint32_t ana_lane_2_quad_b_ctrl1[1]; 8817 uint32_t _ana_lane_2_quad_b_ctrl1; 8818 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_t; 8819 8820 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_CLR(r) (r).ana_lane_2_quad_b_ctrl1[0] = 0 8821 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_SET(r,d) (r).ana_lane_2_quad_b_ctrl1[0] = d 8822 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_GET(r) (r).ana_lane_2_quad_b_ctrl1[0] 8823 8824 /* 8825 * These macros can be used to access individual fields. 8826 */ 8827 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_2_quad_b_ctrl1[0]) >> 12) & 0xf) 8828 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_2_quad_b_ctrl1[0]=(((r).ana_lane_2_quad_b_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 8829 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_2_quad_b_ctrl1[0]) >> 9) & 0x1) 8830 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_2_quad_b_ctrl1[0]=(((r).ana_lane_2_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 8831 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_2_quad_b_ctrl1[0]) >> 8) & 0x1) 8832 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_2_quad_b_ctrl1[0]=(((r).ana_lane_2_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 8833 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_2_quad_b_ctrl1[0]) >> 4) & 0x3) 8834 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_2_quad_b_ctrl1[0]=(((r).ana_lane_2_quad_b_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 8835 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_2_quad_b_ctrl1[0]) & 0x7) 8836 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_2_quad_b_ctrl1[0]=(((r).ana_lane_2_quad_b_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 8837 8838 /* 8839 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL1. 8840 */ 8841 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r,_r._ana_lane_2_quad_b_ctrl1) 8842 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r,_r._ana_lane_2_quad_b_ctrl1) 8843 8844 /* 8845 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8846 * will be redefined without the chip prefix for easier programming. 8847 * If multiple chips will be programmed in the same source file, then you should 8848 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8849 * and refer to the fully qualified versions. 8850 */ 8851 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8852 8853 #define ANA_LANE_2_QUAD_B_CTRL1r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r 8854 #define ANA_LANE_2_QUAD_B_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_SIZE 8855 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_t ANA_LANE_2_QUAD_B_CTRL1r_t; 8856 #define ANA_LANE_2_QUAD_B_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_CLR 8857 #define ANA_LANE_2_QUAD_B_CTRL1r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_SET 8858 #define ANA_LANE_2_QUAD_B_CTRL1r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_GET 8859 #define ANA_LANE_2_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 8860 #define ANA_LANE_2_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 8861 #define ANA_LANE_2_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET 8862 #define ANA_LANE_2_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET 8863 #define ANA_LANE_2_QUAD_B_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_PWRDNf_GET 8864 #define ANA_LANE_2_QUAD_B_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_OCL_PWRDNf_SET 8865 #define ANA_LANE_2_QUAD_B_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_REF_OCLf_GET 8866 #define ANA_LANE_2_QUAD_B_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_REF_OCLf_SET 8867 #define ANA_LANE_2_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET 8868 #define ANA_LANE_2_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET 8869 #define READ_ANA_LANE_2_QUAD_B_CTRL1r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL1r 8870 #define WRITE_ANA_LANE_2_QUAD_B_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL1r 8871 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL1r 8872 8873 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8874 /******************************************************************************* 8875 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL1r' 8876 */ 8877 8878 8879 8880 8881 /******************************************************************************* 8882 * CHIP: BCMI_HURACAN 8883 * REGISTER: ANA_LANE_2_QUAD_B_CTRL2 8884 * BLOCKS: ANA_LANE_2_QUAD_B 8885 * REGADDR: 0x9402 8886 * DEVAD: 1 8887 * DESC: control registers 0 8888 * RESETVAL: 0x0 (0) 8889 * ACCESS: R/W 8890 * FIELDS: 8891 * CTLE_ENB_NEGIMP 8892 * CTLE_ENB_NEGCAP 8893 */ 8894 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r (0x00019402 | PHYMOD_REG_ACC_RAW) 8895 8896 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_SIZE 4 8897 8898 /* 8899 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL2. 8900 */ 8901 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_s { 8902 uint32_t v[1]; 8903 uint32_t ana_lane_2_quad_b_ctrl2[1]; 8904 uint32_t _ana_lane_2_quad_b_ctrl2; 8905 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_t; 8906 8907 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CLR(r) (r).ana_lane_2_quad_b_ctrl2[0] = 0 8908 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_SET(r,d) (r).ana_lane_2_quad_b_ctrl2[0] = d 8909 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_GET(r) (r).ana_lane_2_quad_b_ctrl2[0] 8910 8911 /* 8912 * These macros can be used to access individual fields. 8913 */ 8914 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_2_quad_b_ctrl2[0]) >> 8) & 0x7f) 8915 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_2_quad_b_ctrl2[0]=(((r).ana_lane_2_quad_b_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 8916 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_2_quad_b_ctrl2[0]) & 0x7f) 8917 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_2_quad_b_ctrl2[0]=(((r).ana_lane_2_quad_b_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 8918 8919 /* 8920 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL2. 8921 */ 8922 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r,_r._ana_lane_2_quad_b_ctrl2) 8923 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r,_r._ana_lane_2_quad_b_ctrl2) 8924 8925 /* 8926 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 8927 * will be redefined without the chip prefix for easier programming. 8928 * If multiple chips will be programmed in the same source file, then you should 8929 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 8930 * and refer to the fully qualified versions. 8931 */ 8932 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 8933 8934 #define ANA_LANE_2_QUAD_B_CTRL2r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r 8935 #define ANA_LANE_2_QUAD_B_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_SIZE 8936 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_t ANA_LANE_2_QUAD_B_CTRL2r_t; 8937 #define ANA_LANE_2_QUAD_B_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CLR 8938 #define ANA_LANE_2_QUAD_B_CTRL2r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_SET 8939 #define ANA_LANE_2_QUAD_B_CTRL2r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_GET 8940 #define ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET 8941 #define ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET 8942 #define ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET 8943 #define ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET 8944 #define READ_ANA_LANE_2_QUAD_B_CTRL2r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL2r 8945 #define WRITE_ANA_LANE_2_QUAD_B_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL2r 8946 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL2r 8947 8948 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 8949 /******************************************************************************* 8950 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL2r' 8951 */ 8952 8953 8954 8955 8956 /******************************************************************************* 8957 * CHIP: BCMI_HURACAN 8958 * REGISTER: ANA_LANE_2_QUAD_B_CTRL3 8959 * BLOCKS: ANA_LANE_2_QUAD_B 8960 * REGADDR: 0x9403 8961 * DEVAD: 1 8962 * DESC: control registers 0 8963 * RESETVAL: 0x0 (0) 8964 * ACCESS: R/W 8965 * FIELDS: 8966 * CTLE_EN_NEGRES 8967 * CTLE_EQSEL 8968 */ 8969 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r (0x00019403 | PHYMOD_REG_ACC_RAW) 8970 8971 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_SIZE 4 8972 8973 /* 8974 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL3. 8975 */ 8976 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_s { 8977 uint32_t v[1]; 8978 uint32_t ana_lane_2_quad_b_ctrl3[1]; 8979 uint32_t _ana_lane_2_quad_b_ctrl3; 8980 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_t; 8981 8982 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CLR(r) (r).ana_lane_2_quad_b_ctrl3[0] = 0 8983 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_SET(r,d) (r).ana_lane_2_quad_b_ctrl3[0] = d 8984 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_GET(r) (r).ana_lane_2_quad_b_ctrl3[0] 8985 8986 /* 8987 * These macros can be used to access individual fields. 8988 */ 8989 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_2_quad_b_ctrl3[0]) >> 8) & 0xff) 8990 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_2_quad_b_ctrl3[0]=(((r).ana_lane_2_quad_b_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 8991 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_2_quad_b_ctrl3[0]) & 0x7f) 8992 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_2_quad_b_ctrl3[0]=(((r).ana_lane_2_quad_b_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 8993 8994 /* 8995 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL3. 8996 */ 8997 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r,_r._ana_lane_2_quad_b_ctrl3) 8998 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r,_r._ana_lane_2_quad_b_ctrl3) 8999 9000 /* 9001 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9002 * will be redefined without the chip prefix for easier programming. 9003 * If multiple chips will be programmed in the same source file, then you should 9004 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9005 * and refer to the fully qualified versions. 9006 */ 9007 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9008 9009 #define ANA_LANE_2_QUAD_B_CTRL3r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r 9010 #define ANA_LANE_2_QUAD_B_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_SIZE 9011 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_t ANA_LANE_2_QUAD_B_CTRL3r_t; 9012 #define ANA_LANE_2_QUAD_B_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CLR 9013 #define ANA_LANE_2_QUAD_B_CTRL3r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_SET 9014 #define ANA_LANE_2_QUAD_B_CTRL3r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_GET 9015 #define ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EQSELf_GET 9016 #define ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EQSELf_SET 9017 #define ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET 9018 #define ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET 9019 #define READ_ANA_LANE_2_QUAD_B_CTRL3r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL3r 9020 #define WRITE_ANA_LANE_2_QUAD_B_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL3r 9021 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL3r 9022 9023 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9024 /******************************************************************************* 9025 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL3r' 9026 */ 9027 9028 9029 9030 9031 /******************************************************************************* 9032 * CHIP: BCMI_HURACAN 9033 * REGISTER: ANA_LANE_2_QUAD_B_CTRL4 9034 * BLOCKS: ANA_LANE_2_QUAD_B 9035 * REGADDR: 0x9404 9036 * DEVAD: 1 9037 * DESC: control registers 0 9038 * RESETVAL: 0x0 (0) 9039 * ACCESS: R/W 9040 * FIELDS: 9041 * CTLE_LZEN 9042 * RXTX_RESERVED_FOR_59_52 9043 */ 9044 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r (0x00019404 | PHYMOD_REG_ACC_RAW) 9045 9046 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_SIZE 4 9047 9048 /* 9049 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL4. 9050 */ 9051 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_s { 9052 uint32_t v[1]; 9053 uint32_t ana_lane_2_quad_b_ctrl4[1]; 9054 uint32_t _ana_lane_2_quad_b_ctrl4; 9055 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_t; 9056 9057 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_CLR(r) (r).ana_lane_2_quad_b_ctrl4[0] = 0 9058 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_SET(r,d) (r).ana_lane_2_quad_b_ctrl4[0] = d 9059 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_GET(r) (r).ana_lane_2_quad_b_ctrl4[0] 9060 9061 /* 9062 * These macros can be used to access individual fields. 9063 */ 9064 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_2_quad_b_ctrl4[0]) >> 4) & 0xff) 9065 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_2_quad_b_ctrl4[0]=(((r).ana_lane_2_quad_b_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 9066 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_2_quad_b_ctrl4[0]) & 0x1) 9067 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_2_quad_b_ctrl4[0]=(((r).ana_lane_2_quad_b_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 9068 9069 /* 9070 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL4. 9071 */ 9072 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r,_r._ana_lane_2_quad_b_ctrl4) 9073 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r,_r._ana_lane_2_quad_b_ctrl4) 9074 9075 /* 9076 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9077 * will be redefined without the chip prefix for easier programming. 9078 * If multiple chips will be programmed in the same source file, then you should 9079 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9080 * and refer to the fully qualified versions. 9081 */ 9082 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9083 9084 #define ANA_LANE_2_QUAD_B_CTRL4r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r 9085 #define ANA_LANE_2_QUAD_B_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_SIZE 9086 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_t ANA_LANE_2_QUAD_B_CTRL4r_t; 9087 #define ANA_LANE_2_QUAD_B_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_CLR 9088 #define ANA_LANE_2_QUAD_B_CTRL4r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_SET 9089 #define ANA_LANE_2_QUAD_B_CTRL4r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_GET 9090 #define ANA_LANE_2_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 9091 #define ANA_LANE_2_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 9092 #define ANA_LANE_2_QUAD_B_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_CTLE_LZENf_GET 9093 #define ANA_LANE_2_QUAD_B_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r_CTLE_LZENf_SET 9094 #define READ_ANA_LANE_2_QUAD_B_CTRL4r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL4r 9095 #define WRITE_ANA_LANE_2_QUAD_B_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL4r 9096 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL4r 9097 9098 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9099 /******************************************************************************* 9100 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL4r' 9101 */ 9102 9103 9104 9105 9106 /******************************************************************************* 9107 * CHIP: BCMI_HURACAN 9108 * REGISTER: ANA_LANE_2_QUAD_B_CTRL5 9109 * BLOCKS: ANA_LANE_2_QUAD_B 9110 * REGADDR: 0x9405 9111 * DEVAD: 1 9112 * DESC: control registers 0 9113 * RESETVAL: 0x0 (0) 9114 * ACCESS: R/W 9115 * FIELDS: 9116 * CTLE_LOPEAKING 9117 * CTLE_PD 9118 * LA_GCTRL 9119 */ 9120 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r (0x00019405 | PHYMOD_REG_ACC_RAW) 9121 9122 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_SIZE 4 9123 9124 /* 9125 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL5. 9126 */ 9127 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_s { 9128 uint32_t v[1]; 9129 uint32_t ana_lane_2_quad_b_ctrl5[1]; 9130 uint32_t _ana_lane_2_quad_b_ctrl5; 9131 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_t; 9132 9133 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CLR(r) (r).ana_lane_2_quad_b_ctrl5[0] = 0 9134 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_SET(r,d) (r).ana_lane_2_quad_b_ctrl5[0] = d 9135 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_GET(r) (r).ana_lane_2_quad_b_ctrl5[0] 9136 9137 /* 9138 * These macros can be used to access individual fields. 9139 */ 9140 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_2_quad_b_ctrl5[0]) >> 4) & 0x3ff) 9141 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_2_quad_b_ctrl5[0]=(((r).ana_lane_2_quad_b_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 9142 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_2_quad_b_ctrl5[0]) >> 1) & 0x1) 9143 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_2_quad_b_ctrl5[0]=(((r).ana_lane_2_quad_b_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 9144 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_2_quad_b_ctrl5[0]) & 0x1) 9145 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_2_quad_b_ctrl5[0]=(((r).ana_lane_2_quad_b_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 9146 9147 /* 9148 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL5. 9149 */ 9150 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r,_r._ana_lane_2_quad_b_ctrl5) 9151 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r,_r._ana_lane_2_quad_b_ctrl5) 9152 9153 /* 9154 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9155 * will be redefined without the chip prefix for easier programming. 9156 * If multiple chips will be programmed in the same source file, then you should 9157 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9158 * and refer to the fully qualified versions. 9159 */ 9160 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9161 9162 #define ANA_LANE_2_QUAD_B_CTRL5r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r 9163 #define ANA_LANE_2_QUAD_B_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_SIZE 9164 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_t ANA_LANE_2_QUAD_B_CTRL5r_t; 9165 #define ANA_LANE_2_QUAD_B_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CLR 9166 #define ANA_LANE_2_QUAD_B_CTRL5r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_SET 9167 #define ANA_LANE_2_QUAD_B_CTRL5r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_GET 9168 #define ANA_LANE_2_QUAD_B_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_LA_GCTRLf_GET 9169 #define ANA_LANE_2_QUAD_B_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_LA_GCTRLf_SET 9170 #define ANA_LANE_2_QUAD_B_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_PDf_GET 9171 #define ANA_LANE_2_QUAD_B_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_PDf_SET 9172 #define ANA_LANE_2_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET 9173 #define ANA_LANE_2_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET 9174 #define READ_ANA_LANE_2_QUAD_B_CTRL5r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL5r 9175 #define WRITE_ANA_LANE_2_QUAD_B_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL5r 9176 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL5r 9177 9178 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9179 /******************************************************************************* 9180 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL5r' 9181 */ 9182 9183 9184 9185 9186 /******************************************************************************* 9187 * CHIP: BCMI_HURACAN 9188 * REGISTER: ANA_LANE_2_QUAD_B_CTRL6 9189 * BLOCKS: ANA_LANE_2_QUAD_B 9190 * REGADDR: 0x9406 9191 * DEVAD: 1 9192 * DESC: control registers 0 9193 * RESETVAL: 0x0 (0) 9194 * ACCESS: R/W 9195 * FIELDS: 9196 * LA_DEGAIN 9197 * LA_DETUNE 9198 */ 9199 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r (0x00019406 | PHYMOD_REG_ACC_RAW) 9200 9201 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_SIZE 4 9202 9203 /* 9204 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL6. 9205 */ 9206 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_s { 9207 uint32_t v[1]; 9208 uint32_t ana_lane_2_quad_b_ctrl6[1]; 9209 uint32_t _ana_lane_2_quad_b_ctrl6; 9210 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_t; 9211 9212 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_CLR(r) (r).ana_lane_2_quad_b_ctrl6[0] = 0 9213 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_SET(r,d) (r).ana_lane_2_quad_b_ctrl6[0] = d 9214 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_GET(r) (r).ana_lane_2_quad_b_ctrl6[0] 9215 9216 /* 9217 * These macros can be used to access individual fields. 9218 */ 9219 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_2_quad_b_ctrl6[0]) >> 8) & 0xff) 9220 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_2_quad_b_ctrl6[0]=(((r).ana_lane_2_quad_b_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 9221 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_2_quad_b_ctrl6[0]) & 0x1f) 9222 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_2_quad_b_ctrl6[0]=(((r).ana_lane_2_quad_b_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 9223 9224 /* 9225 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL6. 9226 */ 9227 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r,_r._ana_lane_2_quad_b_ctrl6) 9228 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r,_r._ana_lane_2_quad_b_ctrl6) 9229 9230 /* 9231 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9232 * will be redefined without the chip prefix for easier programming. 9233 * If multiple chips will be programmed in the same source file, then you should 9234 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9235 * and refer to the fully qualified versions. 9236 */ 9237 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9238 9239 #define ANA_LANE_2_QUAD_B_CTRL6r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r 9240 #define ANA_LANE_2_QUAD_B_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_SIZE 9241 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_t ANA_LANE_2_QUAD_B_CTRL6r_t; 9242 #define ANA_LANE_2_QUAD_B_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_CLR 9243 #define ANA_LANE_2_QUAD_B_CTRL6r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_SET 9244 #define ANA_LANE_2_QUAD_B_CTRL6r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_GET 9245 #define ANA_LANE_2_QUAD_B_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DETUNEf_GET 9246 #define ANA_LANE_2_QUAD_B_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DETUNEf_SET 9247 #define ANA_LANE_2_QUAD_B_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DEGAINf_GET 9248 #define ANA_LANE_2_QUAD_B_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r_LA_DEGAINf_SET 9249 #define READ_ANA_LANE_2_QUAD_B_CTRL6r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL6r 9250 #define WRITE_ANA_LANE_2_QUAD_B_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL6r 9251 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL6r 9252 9253 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9254 /******************************************************************************* 9255 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL6r' 9256 */ 9257 9258 9259 9260 9261 /******************************************************************************* 9262 * CHIP: BCMI_HURACAN 9263 * REGISTER: ANA_LANE_2_QUAD_B_CTRL7 9264 * BLOCKS: ANA_LANE_2_QUAD_B 9265 * REGADDR: 0x9407 9266 * DEVAD: 1 9267 * DESC: control registers 0 9268 * RESETVAL: 0x0 (0) 9269 * ACCESS: R/W 9270 * FIELDS: 9271 * LA_LIN_MODE 9272 * RX_BIAS_FB_PDN 9273 */ 9274 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r (0x00019407 | PHYMOD_REG_ACC_RAW) 9275 9276 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_SIZE 4 9277 9278 /* 9279 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL7. 9280 */ 9281 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_s { 9282 uint32_t v[1]; 9283 uint32_t ana_lane_2_quad_b_ctrl7[1]; 9284 uint32_t _ana_lane_2_quad_b_ctrl7; 9285 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_t; 9286 9287 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_CLR(r) (r).ana_lane_2_quad_b_ctrl7[0] = 0 9288 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_SET(r,d) (r).ana_lane_2_quad_b_ctrl7[0] = d 9289 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_GET(r) (r).ana_lane_2_quad_b_ctrl7[0] 9290 9291 /* 9292 * These macros can be used to access individual fields. 9293 */ 9294 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_2_quad_b_ctrl7[0]) >> 8) & 0x1) 9295 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_2_quad_b_ctrl7[0]=(((r).ana_lane_2_quad_b_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 9296 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_2_quad_b_ctrl7[0]) & 0x1f) 9297 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_2_quad_b_ctrl7[0]=(((r).ana_lane_2_quad_b_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 9298 9299 /* 9300 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL7. 9301 */ 9302 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r,_r._ana_lane_2_quad_b_ctrl7) 9303 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r,_r._ana_lane_2_quad_b_ctrl7) 9304 9305 /* 9306 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9307 * will be redefined without the chip prefix for easier programming. 9308 * If multiple chips will be programmed in the same source file, then you should 9309 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9310 * and refer to the fully qualified versions. 9311 */ 9312 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9313 9314 #define ANA_LANE_2_QUAD_B_CTRL7r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r 9315 #define ANA_LANE_2_QUAD_B_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_SIZE 9316 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_t ANA_LANE_2_QUAD_B_CTRL7r_t; 9317 #define ANA_LANE_2_QUAD_B_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_CLR 9318 #define ANA_LANE_2_QUAD_B_CTRL7r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_SET 9319 #define ANA_LANE_2_QUAD_B_CTRL7r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_GET 9320 #define ANA_LANE_2_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET 9321 #define ANA_LANE_2_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET 9322 #define ANA_LANE_2_QUAD_B_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_LA_LIN_MODEf_GET 9323 #define ANA_LANE_2_QUAD_B_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r_LA_LIN_MODEf_SET 9324 #define READ_ANA_LANE_2_QUAD_B_CTRL7r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL7r 9325 #define WRITE_ANA_LANE_2_QUAD_B_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL7r 9326 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL7r 9327 9328 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9329 /******************************************************************************* 9330 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL7r' 9331 */ 9332 9333 9334 9335 9336 /******************************************************************************* 9337 * CHIP: BCMI_HURACAN 9338 * REGISTER: ANA_LANE_2_QUAD_B_CTRL8 9339 * BLOCKS: ANA_LANE_2_QUAD_B 9340 * REGADDR: 0x9408 9341 * DEVAD: 1 9342 * DESC: control registers 0 9343 * RESETVAL: 0x0 (0) 9344 * ACCESS: R/W 9345 * FIELDS: 9346 * LA_PD 9347 * LA_PD_IDLE 9348 * RXTX_RESERVED_FOR_99_95 9349 */ 9350 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r (0x00019408 | PHYMOD_REG_ACC_RAW) 9351 9352 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_SIZE 4 9353 9354 /* 9355 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL8. 9356 */ 9357 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_s { 9358 uint32_t v[1]; 9359 uint32_t ana_lane_2_quad_b_ctrl8[1]; 9360 uint32_t _ana_lane_2_quad_b_ctrl8; 9361 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_t; 9362 9363 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_CLR(r) (r).ana_lane_2_quad_b_ctrl8[0] = 0 9364 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_SET(r,d) (r).ana_lane_2_quad_b_ctrl8[0] = d 9365 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_GET(r) (r).ana_lane_2_quad_b_ctrl8[0] 9366 9367 /* 9368 * These macros can be used to access individual fields. 9369 */ 9370 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_2_quad_b_ctrl8[0]) >> 4) & 0x1f) 9371 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_2_quad_b_ctrl8[0]=(((r).ana_lane_2_quad_b_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 9372 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_2_quad_b_ctrl8[0]) >> 1) & 0x1) 9373 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_2_quad_b_ctrl8[0]=(((r).ana_lane_2_quad_b_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 9374 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_2_quad_b_ctrl8[0]) & 0x1) 9375 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_2_quad_b_ctrl8[0]=(((r).ana_lane_2_quad_b_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 9376 9377 /* 9378 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL8. 9379 */ 9380 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r,_r._ana_lane_2_quad_b_ctrl8) 9381 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r,_r._ana_lane_2_quad_b_ctrl8) 9382 9383 /* 9384 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9385 * will be redefined without the chip prefix for easier programming. 9386 * If multiple chips will be programmed in the same source file, then you should 9387 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9388 * and refer to the fully qualified versions. 9389 */ 9390 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9391 9392 #define ANA_LANE_2_QUAD_B_CTRL8r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r 9393 #define ANA_LANE_2_QUAD_B_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_SIZE 9394 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_t ANA_LANE_2_QUAD_B_CTRL8r_t; 9395 #define ANA_LANE_2_QUAD_B_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_CLR 9396 #define ANA_LANE_2_QUAD_B_CTRL8r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_SET 9397 #define ANA_LANE_2_QUAD_B_CTRL8r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_GET 9398 #define ANA_LANE_2_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 9399 #define ANA_LANE_2_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 9400 #define ANA_LANE_2_QUAD_B_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PD_IDLEf_GET 9401 #define ANA_LANE_2_QUAD_B_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PD_IDLEf_SET 9402 #define ANA_LANE_2_QUAD_B_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PDf_GET 9403 #define ANA_LANE_2_QUAD_B_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r_LA_PDf_SET 9404 #define READ_ANA_LANE_2_QUAD_B_CTRL8r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL8r 9405 #define WRITE_ANA_LANE_2_QUAD_B_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL8r 9406 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL8r 9407 9408 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9409 /******************************************************************************* 9410 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL8r' 9411 */ 9412 9413 9414 9415 9416 /******************************************************************************* 9417 * CHIP: BCMI_HURACAN 9418 * REGISTER: ANA_LANE_2_QUAD_B_CTRL9 9419 * BLOCKS: ANA_LANE_2_QUAD_B 9420 * REGADDR: 0x9409 9421 * DEVAD: 1 9422 * DESC: control registers 0 9423 * RESETVAL: 0x0 (0) 9424 * ACCESS: R/W 9425 * FIELDS: 9426 * DRV_POST1 9427 * DLINE_SWING_1 9428 * DLINE_SWING_2 9429 * DLINE_DELAY_CTRL 9430 */ 9431 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r (0x00019409 | PHYMOD_REG_ACC_RAW) 9432 9433 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_SIZE 4 9434 9435 /* 9436 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL9. 9437 */ 9438 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_s { 9439 uint32_t v[1]; 9440 uint32_t ana_lane_2_quad_b_ctrl9[1]; 9441 uint32_t _ana_lane_2_quad_b_ctrl9; 9442 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_t; 9443 9444 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_CLR(r) (r).ana_lane_2_quad_b_ctrl9[0] = 0 9445 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_SET(r,d) (r).ana_lane_2_quad_b_ctrl9[0] = d 9446 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_GET(r) (r).ana_lane_2_quad_b_ctrl9[0] 9447 9448 /* 9449 * These macros can be used to access individual fields. 9450 */ 9451 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_2_quad_b_ctrl9[0]) >> 12) & 0x7) 9452 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_2_quad_b_ctrl9[0]=(((r).ana_lane_2_quad_b_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 9453 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_2_quad_b_ctrl9[0]) >> 8) & 0x3) 9454 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_2_quad_b_ctrl9[0]=(((r).ana_lane_2_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 9455 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_2_quad_b_ctrl9[0]) >> 4) & 0x3) 9456 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_2_quad_b_ctrl9[0]=(((r).ana_lane_2_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 9457 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_2_quad_b_ctrl9[0]) & 0xf) 9458 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_2_quad_b_ctrl9[0]=(((r).ana_lane_2_quad_b_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 9459 9460 /* 9461 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL9. 9462 */ 9463 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r,_r._ana_lane_2_quad_b_ctrl9) 9464 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r,_r._ana_lane_2_quad_b_ctrl9) 9465 9466 /* 9467 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9468 * will be redefined without the chip prefix for easier programming. 9469 * If multiple chips will be programmed in the same source file, then you should 9470 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9471 * and refer to the fully qualified versions. 9472 */ 9473 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9474 9475 #define ANA_LANE_2_QUAD_B_CTRL9r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r 9476 #define ANA_LANE_2_QUAD_B_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_SIZE 9477 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_t ANA_LANE_2_QUAD_B_CTRL9r_t; 9478 #define ANA_LANE_2_QUAD_B_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_CLR 9479 #define ANA_LANE_2_QUAD_B_CTRL9r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_SET 9480 #define ANA_LANE_2_QUAD_B_CTRL9r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_GET 9481 #define ANA_LANE_2_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET 9482 #define ANA_LANE_2_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET 9483 #define ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_2f_GET 9484 #define ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_2f_SET 9485 #define ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_1f_GET 9486 #define ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DLINE_SWING_1f_SET 9487 #define ANA_LANE_2_QUAD_B_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DRV_POST1f_GET 9488 #define ANA_LANE_2_QUAD_B_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r_DRV_POST1f_SET 9489 #define READ_ANA_LANE_2_QUAD_B_CTRL9r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL9r 9490 #define WRITE_ANA_LANE_2_QUAD_B_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL9r 9491 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL9r 9492 9493 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9494 /******************************************************************************* 9495 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL9r' 9496 */ 9497 9498 9499 9500 9501 /******************************************************************************* 9502 * CHIP: BCMI_HURACAN 9503 * REGISTER: ANA_LANE_2_QUAD_B_CTRL10 9504 * BLOCKS: ANA_LANE_2_QUAD_B 9505 * REGADDR: 0x940a 9506 * DEVAD: 1 9507 * DESC: control registers 0 9508 * RESETVAL: 0x0 (0) 9509 * ACCESS: R/W 9510 * FIELDS: 9511 * DRV_PWD 9512 * DLINE_PWD 9513 * DRV_VBSEL 9514 * DRV_MAIN 9515 * DRV_MAIN_PU 9516 */ 9517 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r (0x0001940a | PHYMOD_REG_ACC_RAW) 9518 9519 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_SIZE 4 9520 9521 /* 9522 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL10. 9523 */ 9524 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_s { 9525 uint32_t v[1]; 9526 uint32_t ana_lane_2_quad_b_ctrl10[1]; 9527 uint32_t _ana_lane_2_quad_b_ctrl10; 9528 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_t; 9529 9530 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_CLR(r) (r).ana_lane_2_quad_b_ctrl10[0] = 0 9531 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_SET(r,d) (r).ana_lane_2_quad_b_ctrl10[0] = d 9532 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_GET(r) (r).ana_lane_2_quad_b_ctrl10[0] 9533 9534 /* 9535 * These macros can be used to access individual fields. 9536 */ 9537 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_2_quad_b_ctrl10[0]) >> 12) & 0xf) 9538 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_2_quad_b_ctrl10[0]=(((r).ana_lane_2_quad_b_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 9539 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_2_quad_b_ctrl10[0]) >> 4) & 0x3f) 9540 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_2_quad_b_ctrl10[0]=(((r).ana_lane_2_quad_b_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 9541 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_2_quad_b_ctrl10[0]) >> 2) & 0x1) 9542 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_2_quad_b_ctrl10[0]=(((r).ana_lane_2_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 9543 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_2_quad_b_ctrl10[0]) >> 1) & 0x1) 9544 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_2_quad_b_ctrl10[0]=(((r).ana_lane_2_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 9545 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_2_quad_b_ctrl10[0]) & 0x1) 9546 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_2_quad_b_ctrl10[0]=(((r).ana_lane_2_quad_b_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 9547 9548 /* 9549 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL10. 9550 */ 9551 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r,_r._ana_lane_2_quad_b_ctrl10) 9552 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r,_r._ana_lane_2_quad_b_ctrl10) 9553 9554 /* 9555 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9556 * will be redefined without the chip prefix for easier programming. 9557 * If multiple chips will be programmed in the same source file, then you should 9558 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9559 * and refer to the fully qualified versions. 9560 */ 9561 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9562 9563 #define ANA_LANE_2_QUAD_B_CTRL10r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r 9564 #define ANA_LANE_2_QUAD_B_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_SIZE 9565 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_t ANA_LANE_2_QUAD_B_CTRL10r_t; 9566 #define ANA_LANE_2_QUAD_B_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_CLR 9567 #define ANA_LANE_2_QUAD_B_CTRL10r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_SET 9568 #define ANA_LANE_2_QUAD_B_CTRL10r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_GET 9569 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET 9570 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET 9571 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAINf_GET 9572 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_MAINf_SET 9573 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_VBSELf_GET 9574 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_VBSELf_SET 9575 #define ANA_LANE_2_QUAD_B_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DLINE_PWDf_GET 9576 #define ANA_LANE_2_QUAD_B_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DLINE_PWDf_SET 9577 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_PWDf_GET 9578 #define ANA_LANE_2_QUAD_B_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r_DRV_PWDf_SET 9579 #define READ_ANA_LANE_2_QUAD_B_CTRL10r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL10r 9580 #define WRITE_ANA_LANE_2_QUAD_B_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL10r 9581 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL10r 9582 9583 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9584 /******************************************************************************* 9585 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL10r' 9586 */ 9587 9588 9589 9590 9591 /******************************************************************************* 9592 * CHIP: BCMI_HURACAN 9593 * REGISTER: ANA_LANE_2_QUAD_B_CTRL11 9594 * BLOCKS: ANA_LANE_2_QUAD_B 9595 * REGADDR: 0x940b 9596 * DEVAD: 1 9597 * DESC: control registers 0 9598 * RESETVAL: 0x0 (0) 9599 * ACCESS: R/W 9600 * FIELDS: 9601 * RXTX_RESERVED_FOR_143_128 9602 */ 9603 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r (0x0001940b | PHYMOD_REG_ACC_RAW) 9604 9605 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_SIZE 4 9606 9607 /* 9608 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL11. 9609 */ 9610 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_s { 9611 uint32_t v[1]; 9612 uint32_t ana_lane_2_quad_b_ctrl11[1]; 9613 uint32_t _ana_lane_2_quad_b_ctrl11; 9614 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_t; 9615 9616 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_CLR(r) (r).ana_lane_2_quad_b_ctrl11[0] = 0 9617 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_SET(r,d) (r).ana_lane_2_quad_b_ctrl11[0] = d 9618 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_GET(r) (r).ana_lane_2_quad_b_ctrl11[0] 9619 9620 /* 9621 * These macros can be used to access individual fields. 9622 */ 9623 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_2_quad_b_ctrl11[0]) & 0xffff) 9624 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_2_quad_b_ctrl11[0]=(((r).ana_lane_2_quad_b_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 9625 9626 /* 9627 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL11. 9628 */ 9629 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r,_r._ana_lane_2_quad_b_ctrl11) 9630 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r,_r._ana_lane_2_quad_b_ctrl11) 9631 9632 /* 9633 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9634 * will be redefined without the chip prefix for easier programming. 9635 * If multiple chips will be programmed in the same source file, then you should 9636 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9637 * and refer to the fully qualified versions. 9638 */ 9639 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9640 9641 #define ANA_LANE_2_QUAD_B_CTRL11r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r 9642 #define ANA_LANE_2_QUAD_B_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_SIZE 9643 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_t ANA_LANE_2_QUAD_B_CTRL11r_t; 9644 #define ANA_LANE_2_QUAD_B_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_CLR 9645 #define ANA_LANE_2_QUAD_B_CTRL11r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_SET 9646 #define ANA_LANE_2_QUAD_B_CTRL11r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_GET 9647 #define ANA_LANE_2_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 9648 #define ANA_LANE_2_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 9649 #define READ_ANA_LANE_2_QUAD_B_CTRL11r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL11r 9650 #define WRITE_ANA_LANE_2_QUAD_B_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL11r 9651 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL11r 9652 9653 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9654 /******************************************************************************* 9655 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL11r' 9656 */ 9657 9658 9659 9660 9661 /******************************************************************************* 9662 * CHIP: BCMI_HURACAN 9663 * REGISTER: ANA_LANE_2_QUAD_B_CTRL12 9664 * BLOCKS: ANA_LANE_2_QUAD_B 9665 * REGADDR: 0x940c 9666 * DEVAD: 1 9667 * DESC: control registers 0 9668 * RESETVAL: 0x0 (0) 9669 * ACCESS: R/W 9670 * FIELDS: 9671 * LA_RESCAL_FRC_VAL 9672 * LA_RESCAL_FRC 9673 * DRV_RESCAL_FRC_VAL 9674 * DRV_RESCAL_FRC 9675 */ 9676 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r (0x0001940c | PHYMOD_REG_ACC_RAW) 9677 9678 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_SIZE 4 9679 9680 /* 9681 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL12. 9682 */ 9683 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_s { 9684 uint32_t v[1]; 9685 uint32_t ana_lane_2_quad_b_ctrl12[1]; 9686 uint32_t _ana_lane_2_quad_b_ctrl12; 9687 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_t; 9688 9689 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_CLR(r) (r).ana_lane_2_quad_b_ctrl12[0] = 0 9690 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_SET(r,d) (r).ana_lane_2_quad_b_ctrl12[0] = d 9691 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_GET(r) (r).ana_lane_2_quad_b_ctrl12[0] 9692 9693 /* 9694 * These macros can be used to access individual fields. 9695 */ 9696 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_b_ctrl12[0]) >> 12) & 0x1) 9697 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_b_ctrl12[0]=(((r).ana_lane_2_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 9698 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_b_ctrl12[0]) >> 8) & 0xf) 9699 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_b_ctrl12[0]=(((r).ana_lane_2_quad_b_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 9700 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_b_ctrl12[0]) >> 4) & 0x1) 9701 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_b_ctrl12[0]=(((r).ana_lane_2_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 9702 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_b_ctrl12[0]) & 0xf) 9703 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_b_ctrl12[0]=(((r).ana_lane_2_quad_b_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 9704 9705 /* 9706 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL12. 9707 */ 9708 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r,_r._ana_lane_2_quad_b_ctrl12) 9709 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r,_r._ana_lane_2_quad_b_ctrl12) 9710 9711 /* 9712 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9713 * will be redefined without the chip prefix for easier programming. 9714 * If multiple chips will be programmed in the same source file, then you should 9715 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9716 * and refer to the fully qualified versions. 9717 */ 9718 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9719 9720 #define ANA_LANE_2_QUAD_B_CTRL12r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r 9721 #define ANA_LANE_2_QUAD_B_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_SIZE 9722 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_t ANA_LANE_2_QUAD_B_CTRL12r_t; 9723 #define ANA_LANE_2_QUAD_B_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_CLR 9724 #define ANA_LANE_2_QUAD_B_CTRL12r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_SET 9725 #define ANA_LANE_2_QUAD_B_CTRL12r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_GET 9726 #define ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET 9727 #define ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET 9728 #define ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET 9729 #define ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET 9730 #define ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET 9731 #define ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET 9732 #define ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET 9733 #define ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET 9734 #define READ_ANA_LANE_2_QUAD_B_CTRL12r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL12r 9735 #define WRITE_ANA_LANE_2_QUAD_B_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL12r 9736 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL12r 9737 9738 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9739 /******************************************************************************* 9740 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL12r' 9741 */ 9742 9743 9744 9745 9746 /******************************************************************************* 9747 * CHIP: BCMI_HURACAN 9748 * REGISTER: ANA_LANE_2_QUAD_B_CTRL13 9749 * BLOCKS: ANA_LANE_2_QUAD_B 9750 * REGADDR: 0x940d 9751 * DEVAD: 1 9752 * DESC: control registers 0 9753 * RESETVAL: 0x0 (0) 9754 * ACCESS: R/W 9755 * FIELDS: 9756 * CTLE_RESCAL_FRC_VAL 9757 * CTLE_RESCAL_FRC 9758 */ 9759 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r (0x0001940d | PHYMOD_REG_ACC_RAW) 9760 9761 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_SIZE 4 9762 9763 /* 9764 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL13. 9765 */ 9766 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_s { 9767 uint32_t v[1]; 9768 uint32_t ana_lane_2_quad_b_ctrl13[1]; 9769 uint32_t _ana_lane_2_quad_b_ctrl13; 9770 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_t; 9771 9772 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CLR(r) (r).ana_lane_2_quad_b_ctrl13[0] = 0 9773 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_SET(r,d) (r).ana_lane_2_quad_b_ctrl13[0] = d 9774 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_GET(r) (r).ana_lane_2_quad_b_ctrl13[0] 9775 9776 /* 9777 * These macros can be used to access individual fields. 9778 */ 9779 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_b_ctrl13[0]) >> 4) & 0x1) 9780 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_b_ctrl13[0]=(((r).ana_lane_2_quad_b_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 9781 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_b_ctrl13[0]) & 0xf) 9782 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_b_ctrl13[0]=(((r).ana_lane_2_quad_b_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 9783 9784 /* 9785 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL13. 9786 */ 9787 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r,_r._ana_lane_2_quad_b_ctrl13) 9788 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r,_r._ana_lane_2_quad_b_ctrl13) 9789 9790 /* 9791 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9792 * will be redefined without the chip prefix for easier programming. 9793 * If multiple chips will be programmed in the same source file, then you should 9794 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9795 * and refer to the fully qualified versions. 9796 */ 9797 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9798 9799 #define ANA_LANE_2_QUAD_B_CTRL13r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r 9800 #define ANA_LANE_2_QUAD_B_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_SIZE 9801 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_t ANA_LANE_2_QUAD_B_CTRL13r_t; 9802 #define ANA_LANE_2_QUAD_B_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CLR 9803 #define ANA_LANE_2_QUAD_B_CTRL13r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_SET 9804 #define ANA_LANE_2_QUAD_B_CTRL13r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_GET 9805 #define ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET 9806 #define ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET 9807 #define ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 9808 #define ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 9809 #define READ_ANA_LANE_2_QUAD_B_CTRL13r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL13r 9810 #define WRITE_ANA_LANE_2_QUAD_B_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL13r 9811 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL13r 9812 9813 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9814 /******************************************************************************* 9815 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL13r' 9816 */ 9817 9818 9819 9820 9821 /******************************************************************************* 9822 * CHIP: BCMI_HURACAN 9823 * REGISTER: ANA_LANE_2_QUAD_B_CTRL14 9824 * BLOCKS: ANA_LANE_2_QUAD_B 9825 * REGADDR: 0x940e 9826 * DEVAD: 1 9827 * DESC: control registers 0 9828 * RESETVAL: 0x0 (0) 9829 * ACCESS: R/W 9830 * FIELDS: 9831 * TX_IDLE_FRC_VAL 9832 * TX_IDLE_FRC 9833 * RXSD_IDLE_OVRD 9834 */ 9835 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r (0x0001940e | PHYMOD_REG_ACC_RAW) 9836 9837 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_SIZE 4 9838 9839 /* 9840 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL14. 9841 */ 9842 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_s { 9843 uint32_t v[1]; 9844 uint32_t ana_lane_2_quad_b_ctrl14[1]; 9845 uint32_t _ana_lane_2_quad_b_ctrl14; 9846 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_t; 9847 9848 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_CLR(r) (r).ana_lane_2_quad_b_ctrl14[0] = 0 9849 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_SET(r,d) (r).ana_lane_2_quad_b_ctrl14[0] = d 9850 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_GET(r) (r).ana_lane_2_quad_b_ctrl14[0] 9851 9852 /* 9853 * These macros can be used to access individual fields. 9854 */ 9855 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_2_quad_b_ctrl14[0]) >> 4) & 0x1) 9856 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_2_quad_b_ctrl14[0]=(((r).ana_lane_2_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 9857 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_2_quad_b_ctrl14[0]) >> 1) & 0x1) 9858 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_2_quad_b_ctrl14[0]=(((r).ana_lane_2_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 9859 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_2_quad_b_ctrl14[0]) & 0x1) 9860 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_b_ctrl14[0]=(((r).ana_lane_2_quad_b_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 9861 9862 /* 9863 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL14. 9864 */ 9865 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r,_r._ana_lane_2_quad_b_ctrl14) 9866 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r,_r._ana_lane_2_quad_b_ctrl14) 9867 9868 /* 9869 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9870 * will be redefined without the chip prefix for easier programming. 9871 * If multiple chips will be programmed in the same source file, then you should 9872 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9873 * and refer to the fully qualified versions. 9874 */ 9875 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9876 9877 #define ANA_LANE_2_QUAD_B_CTRL14r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r 9878 #define ANA_LANE_2_QUAD_B_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_SIZE 9879 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_t ANA_LANE_2_QUAD_B_CTRL14r_t; 9880 #define ANA_LANE_2_QUAD_B_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_CLR 9881 #define ANA_LANE_2_QUAD_B_CTRL14r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_SET 9882 #define ANA_LANE_2_QUAD_B_CTRL14r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_GET 9883 #define ANA_LANE_2_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET 9884 #define ANA_LANE_2_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET 9885 #define ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET 9886 #define ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET 9887 #define ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET 9888 #define ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET 9889 #define READ_ANA_LANE_2_QUAD_B_CTRL14r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL14r 9890 #define WRITE_ANA_LANE_2_QUAD_B_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL14r 9891 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL14r 9892 9893 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9894 /******************************************************************************* 9895 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL14r' 9896 */ 9897 9898 9899 9900 9901 /******************************************************************************* 9902 * CHIP: BCMI_HURACAN 9903 * REGISTER: ANA_LANE_2_QUAD_B_CTRL15 9904 * BLOCKS: ANA_LANE_2_QUAD_B 9905 * REGADDR: 0x940f 9906 * DEVAD: 1 9907 * DESC: sigdet filter settings 0 9908 * RESETVAL: 0x0 (0) 9909 * ACCESS: R/W 9910 * FIELDS: 9911 * SIGDET_DIS 9912 * SIGDET_1US_EN 9913 * SIGDET_FRC_VAL 9914 * SIGDET_FRC 9915 * HOLD_LOS_COUNT 9916 * HOLD_SD_COUNT 9917 */ 9918 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r (0x0001940f | PHYMOD_REG_ACC_RAW) 9919 9920 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIZE 4 9921 9922 /* 9923 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL15. 9924 */ 9925 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_s { 9926 uint32_t v[1]; 9927 uint32_t ana_lane_2_quad_b_ctrl15[1]; 9928 uint32_t _ana_lane_2_quad_b_ctrl15; 9929 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_t; 9930 9931 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_CLR(r) (r).ana_lane_2_quad_b_ctrl15[0] = 0 9932 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SET(r,d) (r).ana_lane_2_quad_b_ctrl15[0] = d 9933 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_GET(r) (r).ana_lane_2_quad_b_ctrl15[0] 9934 9935 /* 9936 * These macros can be used to access individual fields. 9937 */ 9938 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_b_ctrl15[0]) >> 8) & 0x7) 9939 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_b_ctrl15[0]=(((r).ana_lane_2_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 9940 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_2_quad_b_ctrl15[0]) >> 4) & 0x7) 9941 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_b_ctrl15[0]=(((r).ana_lane_2_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 9942 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_2_quad_b_ctrl15[0]) >> 3) & 0x1) 9943 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_2_quad_b_ctrl15[0]=(((r).ana_lane_2_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 9944 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_b_ctrl15[0]) >> 2) & 0x1) 9945 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_b_ctrl15[0]=(((r).ana_lane_2_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 9946 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_2_quad_b_ctrl15[0]) >> 1) & 0x1) 9947 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_2_quad_b_ctrl15[0]=(((r).ana_lane_2_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 9948 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_2_quad_b_ctrl15[0]) & 0x1) 9949 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_2_quad_b_ctrl15[0]=(((r).ana_lane_2_quad_b_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 9950 9951 /* 9952 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL15. 9953 */ 9954 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r,_r._ana_lane_2_quad_b_ctrl15) 9955 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r,_r._ana_lane_2_quad_b_ctrl15) 9956 9957 /* 9958 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 9959 * will be redefined without the chip prefix for easier programming. 9960 * If multiple chips will be programmed in the same source file, then you should 9961 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 9962 * and refer to the fully qualified versions. 9963 */ 9964 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 9965 9966 #define ANA_LANE_2_QUAD_B_CTRL15r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r 9967 #define ANA_LANE_2_QUAD_B_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIZE 9968 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_t ANA_LANE_2_QUAD_B_CTRL15r_t; 9969 #define ANA_LANE_2_QUAD_B_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_CLR 9970 #define ANA_LANE_2_QUAD_B_CTRL15r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SET 9971 #define ANA_LANE_2_QUAD_B_CTRL15r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_GET 9972 #define ANA_LANE_2_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET 9973 #define ANA_LANE_2_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET 9974 #define ANA_LANE_2_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET 9975 #define ANA_LANE_2_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET 9976 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRCf_GET 9977 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRCf_SET 9978 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET 9979 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET 9980 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET 9981 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET 9982 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_DISf_GET 9983 #define ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r_SIGDET_DISf_SET 9984 #define READ_ANA_LANE_2_QUAD_B_CTRL15r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL15r 9985 #define WRITE_ANA_LANE_2_QUAD_B_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL15r 9986 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL15r 9987 9988 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 9989 /******************************************************************************* 9990 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL15r' 9991 */ 9992 9993 9994 9995 9996 /******************************************************************************* 9997 * CHIP: BCMI_HURACAN 9998 * REGISTER: ANA_LANE_2_QUAD_B_CTRL16 9999 * BLOCKS: ANA_LANE_2_QUAD_B 10000 * REGADDR: 0x9410 10001 * DEVAD: 1 10002 * DESC: sigdet filter settings 1 10003 * RESETVAL: 0x0 (0) 10004 * ACCESS: R/W 10005 * FIELDS: 10006 * LOS_COUNT 10007 * SD_COUNT 10008 */ 10009 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r (0x00019410 | PHYMOD_REG_ACC_RAW) 10010 10011 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SIZE 4 10012 10013 /* 10014 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_CTRL16. 10015 */ 10016 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_s { 10017 uint32_t v[1]; 10018 uint32_t ana_lane_2_quad_b_ctrl16[1]; 10019 uint32_t _ana_lane_2_quad_b_ctrl16; 10020 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_t; 10021 10022 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_CLR(r) (r).ana_lane_2_quad_b_ctrl16[0] = 0 10023 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SET(r,d) (r).ana_lane_2_quad_b_ctrl16[0] = d 10024 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_GET(r) (r).ana_lane_2_quad_b_ctrl16[0] 10025 10026 /* 10027 * These macros can be used to access individual fields. 10028 */ 10029 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_b_ctrl16[0]) >> 8) & 0x1f) 10030 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_b_ctrl16[0]=(((r).ana_lane_2_quad_b_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 10031 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_2_quad_b_ctrl16[0]) & 0x1f) 10032 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_b_ctrl16[0]=(((r).ana_lane_2_quad_b_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 10033 10034 /* 10035 * These macros can be used to access ANA_LANE_2_QUAD_B_CTRL16. 10036 */ 10037 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r,_r._ana_lane_2_quad_b_ctrl16) 10038 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r,_r._ana_lane_2_quad_b_ctrl16) 10039 10040 /* 10041 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10042 * will be redefined without the chip prefix for easier programming. 10043 * If multiple chips will be programmed in the same source file, then you should 10044 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10045 * and refer to the fully qualified versions. 10046 */ 10047 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10048 10049 #define ANA_LANE_2_QUAD_B_CTRL16r BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r 10050 #define ANA_LANE_2_QUAD_B_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SIZE 10051 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_t ANA_LANE_2_QUAD_B_CTRL16r_t; 10052 #define ANA_LANE_2_QUAD_B_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_CLR 10053 #define ANA_LANE_2_QUAD_B_CTRL16r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SET 10054 #define ANA_LANE_2_QUAD_B_CTRL16r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_GET 10055 #define ANA_LANE_2_QUAD_B_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SD_COUNTf_GET 10056 #define ANA_LANE_2_QUAD_B_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_SD_COUNTf_SET 10057 #define ANA_LANE_2_QUAD_B_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_LOS_COUNTf_GET 10058 #define ANA_LANE_2_QUAD_B_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r_LOS_COUNTf_SET 10059 #define READ_ANA_LANE_2_QUAD_B_CTRL16r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_CTRL16r 10060 #define WRITE_ANA_LANE_2_QUAD_B_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_CTRL16r 10061 #define MODIFY_ANA_LANE_2_QUAD_B_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_CTRL16r 10062 10063 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10064 /******************************************************************************* 10065 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_CTRL16r' 10066 */ 10067 10068 10069 10070 10071 /******************************************************************************* 10072 * CHIP: BCMI_HURACAN 10073 * REGISTER: ANA_LANE_2_QUAD_B_STATUS0 10074 * BLOCKS: ANA_LANE_2_QUAD_B 10075 * REGADDR: 0x9420 10076 * DEVAD: 1 10077 * DESC: status registers 0 10078 * RESETVAL: 0x0 (0) 10079 * ACCESS: R/W 10080 * FIELDS: 10081 * O_RX_SIGDET 10082 * DG_RX_SIGDET 10083 */ 10084 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r (0x00019420 | PHYMOD_REG_ACC_RAW) 10085 10086 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_SIZE 4 10087 10088 /* 10089 * This structure should be used to declare and program ANA_LANE_2_QUAD_B_STATUS0. 10090 */ 10091 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_s { 10092 uint32_t v[1]; 10093 uint32_t ana_lane_2_quad_b_status0[1]; 10094 uint32_t _ana_lane_2_quad_b_status0; 10095 } BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_t; 10096 10097 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_CLR(r) (r).ana_lane_2_quad_b_status0[0] = 0 10098 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_SET(r,d) (r).ana_lane_2_quad_b_status0[0] = d 10099 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_GET(r) (r).ana_lane_2_quad_b_status0[0] 10100 10101 /* 10102 * These macros can be used to access individual fields. 10103 */ 10104 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_2_quad_b_status0[0]) >> 1) & 0x1) 10105 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_b_status0[0]=(((r).ana_lane_2_quad_b_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 10106 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_2_quad_b_status0[0]) & 0x1) 10107 #define BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_b_status0[0]=(((r).ana_lane_2_quad_b_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 10108 10109 /* 10110 * These macros can be used to access ANA_LANE_2_QUAD_B_STATUS0. 10111 */ 10112 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r,_r._ana_lane_2_quad_b_status0) 10113 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r,_r._ana_lane_2_quad_b_status0) 10114 10115 /* 10116 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10117 * will be redefined without the chip prefix for easier programming. 10118 * If multiple chips will be programmed in the same source file, then you should 10119 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10120 * and refer to the fully qualified versions. 10121 */ 10122 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10123 10124 #define ANA_LANE_2_QUAD_B_STATUS0r BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r 10125 #define ANA_LANE_2_QUAD_B_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_SIZE 10126 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_t ANA_LANE_2_QUAD_B_STATUS0r_t; 10127 #define ANA_LANE_2_QUAD_B_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_CLR 10128 #define ANA_LANE_2_QUAD_B_STATUS0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_SET 10129 #define ANA_LANE_2_QUAD_B_STATUS0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_GET 10130 #define ANA_LANE_2_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET 10131 #define ANA_LANE_2_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET 10132 #define ANA_LANE_2_QUAD_B_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_O_RX_SIGDETf_GET 10133 #define ANA_LANE_2_QUAD_B_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r_O_RX_SIGDETf_SET 10134 #define READ_ANA_LANE_2_QUAD_B_STATUS0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_B_STATUS0r 10135 #define WRITE_ANA_LANE_2_QUAD_B_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_B_STATUS0r 10136 #define MODIFY_ANA_LANE_2_QUAD_B_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_B_STATUS0r 10137 10138 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10139 /******************************************************************************* 10140 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_B_STATUS0r' 10141 */ 10142 10143 10144 10145 10146 /******************************************************************************* 10147 * CHIP: BCMI_HURACAN 10148 * REGISTER: ANA_LANE_3_QUAD_B_CTRL0 10149 * BLOCKS: ANA_LANE_3_QUAD_B 10150 * REGADDR: 0x9800 10151 * DEVAD: 1 10152 * DESC: control registers 0 10153 * RESETVAL: 0x0 (0) 10154 * ACCESS: R/W 10155 * FIELDS: 10156 * RXTX_PWRDN 10157 * RX_SIGDET_BYPASS 10158 * RX_SIGDET_PWRDN 10159 * RX_SIGDECT_12GMODE 10160 * DC_COUPLE 10161 */ 10162 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r (0x00019800 | PHYMOD_REG_ACC_RAW) 10163 10164 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_SIZE 4 10165 10166 /* 10167 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL0. 10168 */ 10169 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_s { 10170 uint32_t v[1]; 10171 uint32_t ana_lane_3_quad_b_ctrl0[1]; 10172 uint32_t _ana_lane_3_quad_b_ctrl0; 10173 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_t; 10174 10175 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_CLR(r) (r).ana_lane_3_quad_b_ctrl0[0] = 0 10176 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_SET(r,d) (r).ana_lane_3_quad_b_ctrl0[0] = d 10177 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_GET(r) (r).ana_lane_3_quad_b_ctrl0[0] 10178 10179 /* 10180 * These macros can be used to access individual fields. 10181 */ 10182 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_3_quad_b_ctrl0[0]) >> 4) & 0x1) 10183 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_3_quad_b_ctrl0[0]=(((r).ana_lane_3_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 10184 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_3_quad_b_ctrl0[0]) >> 3) & 0x1) 10185 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_3_quad_b_ctrl0[0]=(((r).ana_lane_3_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 10186 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_3_quad_b_ctrl0[0]) >> 2) & 0x1) 10187 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_3_quad_b_ctrl0[0]=(((r).ana_lane_3_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 10188 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_3_quad_b_ctrl0[0]) >> 1) & 0x1) 10189 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_3_quad_b_ctrl0[0]=(((r).ana_lane_3_quad_b_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 10190 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_3_quad_b_ctrl0[0]) & 0x1) 10191 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_3_quad_b_ctrl0[0]=(((r).ana_lane_3_quad_b_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 10192 10193 /* 10194 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL0. 10195 */ 10196 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r,_r._ana_lane_3_quad_b_ctrl0) 10197 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r,_r._ana_lane_3_quad_b_ctrl0) 10198 10199 /* 10200 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10201 * will be redefined without the chip prefix for easier programming. 10202 * If multiple chips will be programmed in the same source file, then you should 10203 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10204 * and refer to the fully qualified versions. 10205 */ 10206 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10207 10208 #define ANA_LANE_3_QUAD_B_CTRL0r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r 10209 #define ANA_LANE_3_QUAD_B_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_SIZE 10210 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_t ANA_LANE_3_QUAD_B_CTRL0r_t; 10211 #define ANA_LANE_3_QUAD_B_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_CLR 10212 #define ANA_LANE_3_QUAD_B_CTRL0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_SET 10213 #define ANA_LANE_3_QUAD_B_CTRL0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_GET 10214 #define ANA_LANE_3_QUAD_B_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_DC_COUPLEf_GET 10215 #define ANA_LANE_3_QUAD_B_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_DC_COUPLEf_SET 10216 #define ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_GET 10217 #define ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDECT_12GMODEf_SET 10218 #define ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_GET 10219 #define ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_PWRDNf_SET 10220 #define ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_GET 10221 #define ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RX_SIGDET_BYPASSf_SET 10222 #define ANA_LANE_3_QUAD_B_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RXTX_PWRDNf_GET 10223 #define ANA_LANE_3_QUAD_B_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r_RXTX_PWRDNf_SET 10224 #define READ_ANA_LANE_3_QUAD_B_CTRL0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL0r 10225 #define WRITE_ANA_LANE_3_QUAD_B_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL0r 10226 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL0r 10227 10228 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10229 /******************************************************************************* 10230 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL0r' 10231 */ 10232 10233 10234 10235 10236 /******************************************************************************* 10237 * CHIP: BCMI_HURACAN 10238 * REGISTER: ANA_LANE_3_QUAD_B_CTRL1 10239 * BLOCKS: ANA_LANE_3_QUAD_B 10240 * REGADDR: 0x9801 10241 * DEVAD: 1 10242 * DESC: control registers 0 10243 * RESETVAL: 0x0 (0) 10244 * ACCESS: R/W 10245 * FIELDS: 10246 * RX_SIGDET_THRESHOLD 10247 * REF_OCL 10248 * OCL_PWRDN 10249 * OCL_DISABLE_LOOP 10250 * RXTX_RESERVED_FOR_15_12 10251 */ 10252 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r (0x00019801 | PHYMOD_REG_ACC_RAW) 10253 10254 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_SIZE 4 10255 10256 /* 10257 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL1. 10258 */ 10259 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_s { 10260 uint32_t v[1]; 10261 uint32_t ana_lane_3_quad_b_ctrl1[1]; 10262 uint32_t _ana_lane_3_quad_b_ctrl1; 10263 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_t; 10264 10265 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_CLR(r) (r).ana_lane_3_quad_b_ctrl1[0] = 0 10266 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_SET(r,d) (r).ana_lane_3_quad_b_ctrl1[0] = d 10267 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_GET(r) (r).ana_lane_3_quad_b_ctrl1[0] 10268 10269 /* 10270 * These macros can be used to access individual fields. 10271 */ 10272 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_3_quad_b_ctrl1[0]) >> 12) & 0xf) 10273 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_3_quad_b_ctrl1[0]=(((r).ana_lane_3_quad_b_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 10274 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_3_quad_b_ctrl1[0]) >> 9) & 0x1) 10275 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_3_quad_b_ctrl1[0]=(((r).ana_lane_3_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 10276 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_3_quad_b_ctrl1[0]) >> 8) & 0x1) 10277 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_3_quad_b_ctrl1[0]=(((r).ana_lane_3_quad_b_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 10278 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_3_quad_b_ctrl1[0]) >> 4) & 0x3) 10279 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_3_quad_b_ctrl1[0]=(((r).ana_lane_3_quad_b_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 10280 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_3_quad_b_ctrl1[0]) & 0x7) 10281 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_3_quad_b_ctrl1[0]=(((r).ana_lane_3_quad_b_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 10282 10283 /* 10284 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL1. 10285 */ 10286 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r,_r._ana_lane_3_quad_b_ctrl1) 10287 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r,_r._ana_lane_3_quad_b_ctrl1) 10288 10289 /* 10290 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10291 * will be redefined without the chip prefix for easier programming. 10292 * If multiple chips will be programmed in the same source file, then you should 10293 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10294 * and refer to the fully qualified versions. 10295 */ 10296 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10297 10298 #define ANA_LANE_3_QUAD_B_CTRL1r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r 10299 #define ANA_LANE_3_QUAD_B_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_SIZE 10300 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_t ANA_LANE_3_QUAD_B_CTRL1r_t; 10301 #define ANA_LANE_3_QUAD_B_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_CLR 10302 #define ANA_LANE_3_QUAD_B_CTRL1r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_SET 10303 #define ANA_LANE_3_QUAD_B_CTRL1r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_GET 10304 #define ANA_LANE_3_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 10305 #define ANA_LANE_3_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 10306 #define ANA_LANE_3_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_GET 10307 #define ANA_LANE_3_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_DISABLE_LOOPf_SET 10308 #define ANA_LANE_3_QUAD_B_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_PWRDNf_GET 10309 #define ANA_LANE_3_QUAD_B_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_OCL_PWRDNf_SET 10310 #define ANA_LANE_3_QUAD_B_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_REF_OCLf_GET 10311 #define ANA_LANE_3_QUAD_B_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_REF_OCLf_SET 10312 #define ANA_LANE_3_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_GET 10313 #define ANA_LANE_3_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r_RX_SIGDET_THRESHOLDf_SET 10314 #define READ_ANA_LANE_3_QUAD_B_CTRL1r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL1r 10315 #define WRITE_ANA_LANE_3_QUAD_B_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL1r 10316 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL1r 10317 10318 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10319 /******************************************************************************* 10320 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL1r' 10321 */ 10322 10323 10324 10325 10326 /******************************************************************************* 10327 * CHIP: BCMI_HURACAN 10328 * REGISTER: ANA_LANE_3_QUAD_B_CTRL2 10329 * BLOCKS: ANA_LANE_3_QUAD_B 10330 * REGADDR: 0x9802 10331 * DEVAD: 1 10332 * DESC: control registers 0 10333 * RESETVAL: 0x0 (0) 10334 * ACCESS: R/W 10335 * FIELDS: 10336 * CTLE_ENB_NEGIMP 10337 * CTLE_ENB_NEGCAP 10338 */ 10339 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r (0x00019802 | PHYMOD_REG_ACC_RAW) 10340 10341 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_SIZE 4 10342 10343 /* 10344 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL2. 10345 */ 10346 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_s { 10347 uint32_t v[1]; 10348 uint32_t ana_lane_3_quad_b_ctrl2[1]; 10349 uint32_t _ana_lane_3_quad_b_ctrl2; 10350 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_t; 10351 10352 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CLR(r) (r).ana_lane_3_quad_b_ctrl2[0] = 0 10353 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_SET(r,d) (r).ana_lane_3_quad_b_ctrl2[0] = d 10354 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_GET(r) (r).ana_lane_3_quad_b_ctrl2[0] 10355 10356 /* 10357 * These macros can be used to access individual fields. 10358 */ 10359 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_3_quad_b_ctrl2[0]) >> 8) & 0x7f) 10360 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_3_quad_b_ctrl2[0]=(((r).ana_lane_3_quad_b_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 10361 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_3_quad_b_ctrl2[0]) & 0x7f) 10362 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_3_quad_b_ctrl2[0]=(((r).ana_lane_3_quad_b_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 10363 10364 /* 10365 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL2. 10366 */ 10367 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r,_r._ana_lane_3_quad_b_ctrl2) 10368 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r,_r._ana_lane_3_quad_b_ctrl2) 10369 10370 /* 10371 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10372 * will be redefined without the chip prefix for easier programming. 10373 * If multiple chips will be programmed in the same source file, then you should 10374 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10375 * and refer to the fully qualified versions. 10376 */ 10377 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10378 10379 #define ANA_LANE_3_QUAD_B_CTRL2r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r 10380 #define ANA_LANE_3_QUAD_B_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_SIZE 10381 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_t ANA_LANE_3_QUAD_B_CTRL2r_t; 10382 #define ANA_LANE_3_QUAD_B_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CLR 10383 #define ANA_LANE_3_QUAD_B_CTRL2r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_SET 10384 #define ANA_LANE_3_QUAD_B_CTRL2r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_GET 10385 #define ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_GET 10386 #define ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGCAPf_SET 10387 #define ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_GET 10388 #define ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r_CTLE_ENB_NEGIMPf_SET 10389 #define READ_ANA_LANE_3_QUAD_B_CTRL2r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL2r 10390 #define WRITE_ANA_LANE_3_QUAD_B_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL2r 10391 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL2r 10392 10393 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10394 /******************************************************************************* 10395 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL2r' 10396 */ 10397 10398 10399 10400 10401 /******************************************************************************* 10402 * CHIP: BCMI_HURACAN 10403 * REGISTER: ANA_LANE_3_QUAD_B_CTRL3 10404 * BLOCKS: ANA_LANE_3_QUAD_B 10405 * REGADDR: 0x9803 10406 * DEVAD: 1 10407 * DESC: control registers 0 10408 * RESETVAL: 0x0 (0) 10409 * ACCESS: R/W 10410 * FIELDS: 10411 * CTLE_EN_NEGRES 10412 * CTLE_EQSEL 10413 */ 10414 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r (0x00019803 | PHYMOD_REG_ACC_RAW) 10415 10416 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_SIZE 4 10417 10418 /* 10419 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL3. 10420 */ 10421 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_s { 10422 uint32_t v[1]; 10423 uint32_t ana_lane_3_quad_b_ctrl3[1]; 10424 uint32_t _ana_lane_3_quad_b_ctrl3; 10425 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_t; 10426 10427 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CLR(r) (r).ana_lane_3_quad_b_ctrl3[0] = 0 10428 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_SET(r,d) (r).ana_lane_3_quad_b_ctrl3[0] = d 10429 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_GET(r) (r).ana_lane_3_quad_b_ctrl3[0] 10430 10431 /* 10432 * These macros can be used to access individual fields. 10433 */ 10434 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_3_quad_b_ctrl3[0]) >> 8) & 0xff) 10435 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_3_quad_b_ctrl3[0]=(((r).ana_lane_3_quad_b_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 10436 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_3_quad_b_ctrl3[0]) & 0x7f) 10437 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_3_quad_b_ctrl3[0]=(((r).ana_lane_3_quad_b_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 10438 10439 /* 10440 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL3. 10441 */ 10442 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r,_r._ana_lane_3_quad_b_ctrl3) 10443 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r,_r._ana_lane_3_quad_b_ctrl3) 10444 10445 /* 10446 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10447 * will be redefined without the chip prefix for easier programming. 10448 * If multiple chips will be programmed in the same source file, then you should 10449 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10450 * and refer to the fully qualified versions. 10451 */ 10452 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10453 10454 #define ANA_LANE_3_QUAD_B_CTRL3r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r 10455 #define ANA_LANE_3_QUAD_B_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_SIZE 10456 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_t ANA_LANE_3_QUAD_B_CTRL3r_t; 10457 #define ANA_LANE_3_QUAD_B_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CLR 10458 #define ANA_LANE_3_QUAD_B_CTRL3r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_SET 10459 #define ANA_LANE_3_QUAD_B_CTRL3r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_GET 10460 #define ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EQSELf_GET 10461 #define ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EQSELf_SET 10462 #define ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_GET 10463 #define ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r_CTLE_EN_NEGRESf_SET 10464 #define READ_ANA_LANE_3_QUAD_B_CTRL3r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL3r 10465 #define WRITE_ANA_LANE_3_QUAD_B_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL3r 10466 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL3r 10467 10468 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10469 /******************************************************************************* 10470 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL3r' 10471 */ 10472 10473 10474 10475 10476 /******************************************************************************* 10477 * CHIP: BCMI_HURACAN 10478 * REGISTER: ANA_LANE_3_QUAD_B_CTRL4 10479 * BLOCKS: ANA_LANE_3_QUAD_B 10480 * REGADDR: 0x9804 10481 * DEVAD: 1 10482 * DESC: control registers 0 10483 * RESETVAL: 0x0 (0) 10484 * ACCESS: R/W 10485 * FIELDS: 10486 * CTLE_LZEN 10487 * RXTX_RESERVED_FOR_59_52 10488 */ 10489 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r (0x00019804 | PHYMOD_REG_ACC_RAW) 10490 10491 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_SIZE 4 10492 10493 /* 10494 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL4. 10495 */ 10496 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_s { 10497 uint32_t v[1]; 10498 uint32_t ana_lane_3_quad_b_ctrl4[1]; 10499 uint32_t _ana_lane_3_quad_b_ctrl4; 10500 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_t; 10501 10502 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_CLR(r) (r).ana_lane_3_quad_b_ctrl4[0] = 0 10503 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_SET(r,d) (r).ana_lane_3_quad_b_ctrl4[0] = d 10504 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_GET(r) (r).ana_lane_3_quad_b_ctrl4[0] 10505 10506 /* 10507 * These macros can be used to access individual fields. 10508 */ 10509 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_3_quad_b_ctrl4[0]) >> 4) & 0xff) 10510 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_3_quad_b_ctrl4[0]=(((r).ana_lane_3_quad_b_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 10511 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_3_quad_b_ctrl4[0]) & 0x1) 10512 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_3_quad_b_ctrl4[0]=(((r).ana_lane_3_quad_b_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 10513 10514 /* 10515 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL4. 10516 */ 10517 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r,_r._ana_lane_3_quad_b_ctrl4) 10518 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r,_r._ana_lane_3_quad_b_ctrl4) 10519 10520 /* 10521 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10522 * will be redefined without the chip prefix for easier programming. 10523 * If multiple chips will be programmed in the same source file, then you should 10524 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10525 * and refer to the fully qualified versions. 10526 */ 10527 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10528 10529 #define ANA_LANE_3_QUAD_B_CTRL4r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r 10530 #define ANA_LANE_3_QUAD_B_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_SIZE 10531 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_t ANA_LANE_3_QUAD_B_CTRL4r_t; 10532 #define ANA_LANE_3_QUAD_B_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_CLR 10533 #define ANA_LANE_3_QUAD_B_CTRL4r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_SET 10534 #define ANA_LANE_3_QUAD_B_CTRL4r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_GET 10535 #define ANA_LANE_3_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 10536 #define ANA_LANE_3_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 10537 #define ANA_LANE_3_QUAD_B_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_CTLE_LZENf_GET 10538 #define ANA_LANE_3_QUAD_B_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r_CTLE_LZENf_SET 10539 #define READ_ANA_LANE_3_QUAD_B_CTRL4r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL4r 10540 #define WRITE_ANA_LANE_3_QUAD_B_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL4r 10541 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL4r 10542 10543 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10544 /******************************************************************************* 10545 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL4r' 10546 */ 10547 10548 10549 10550 10551 /******************************************************************************* 10552 * CHIP: BCMI_HURACAN 10553 * REGISTER: ANA_LANE_3_QUAD_B_CTRL5 10554 * BLOCKS: ANA_LANE_3_QUAD_B 10555 * REGADDR: 0x9805 10556 * DEVAD: 1 10557 * DESC: control registers 0 10558 * RESETVAL: 0x0 (0) 10559 * ACCESS: R/W 10560 * FIELDS: 10561 * CTLE_LOPEAKING 10562 * CTLE_PD 10563 * LA_GCTRL 10564 */ 10565 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r (0x00019805 | PHYMOD_REG_ACC_RAW) 10566 10567 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_SIZE 4 10568 10569 /* 10570 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL5. 10571 */ 10572 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_s { 10573 uint32_t v[1]; 10574 uint32_t ana_lane_3_quad_b_ctrl5[1]; 10575 uint32_t _ana_lane_3_quad_b_ctrl5; 10576 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_t; 10577 10578 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CLR(r) (r).ana_lane_3_quad_b_ctrl5[0] = 0 10579 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_SET(r,d) (r).ana_lane_3_quad_b_ctrl5[0] = d 10580 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_GET(r) (r).ana_lane_3_quad_b_ctrl5[0] 10581 10582 /* 10583 * These macros can be used to access individual fields. 10584 */ 10585 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_3_quad_b_ctrl5[0]) >> 4) & 0x3ff) 10586 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_3_quad_b_ctrl5[0]=(((r).ana_lane_3_quad_b_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 10587 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_3_quad_b_ctrl5[0]) >> 1) & 0x1) 10588 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_3_quad_b_ctrl5[0]=(((r).ana_lane_3_quad_b_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 10589 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_3_quad_b_ctrl5[0]) & 0x1) 10590 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_3_quad_b_ctrl5[0]=(((r).ana_lane_3_quad_b_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 10591 10592 /* 10593 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL5. 10594 */ 10595 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r,_r._ana_lane_3_quad_b_ctrl5) 10596 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r,_r._ana_lane_3_quad_b_ctrl5) 10597 10598 /* 10599 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10600 * will be redefined without the chip prefix for easier programming. 10601 * If multiple chips will be programmed in the same source file, then you should 10602 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10603 * and refer to the fully qualified versions. 10604 */ 10605 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10606 10607 #define ANA_LANE_3_QUAD_B_CTRL5r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r 10608 #define ANA_LANE_3_QUAD_B_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_SIZE 10609 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_t ANA_LANE_3_QUAD_B_CTRL5r_t; 10610 #define ANA_LANE_3_QUAD_B_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CLR 10611 #define ANA_LANE_3_QUAD_B_CTRL5r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_SET 10612 #define ANA_LANE_3_QUAD_B_CTRL5r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_GET 10613 #define ANA_LANE_3_QUAD_B_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_LA_GCTRLf_GET 10614 #define ANA_LANE_3_QUAD_B_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_LA_GCTRLf_SET 10615 #define ANA_LANE_3_QUAD_B_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_PDf_GET 10616 #define ANA_LANE_3_QUAD_B_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_PDf_SET 10617 #define ANA_LANE_3_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_GET 10618 #define ANA_LANE_3_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r_CTLE_LOPEAKINGf_SET 10619 #define READ_ANA_LANE_3_QUAD_B_CTRL5r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL5r 10620 #define WRITE_ANA_LANE_3_QUAD_B_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL5r 10621 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL5r 10622 10623 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10624 /******************************************************************************* 10625 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL5r' 10626 */ 10627 10628 10629 10630 10631 /******************************************************************************* 10632 * CHIP: BCMI_HURACAN 10633 * REGISTER: ANA_LANE_3_QUAD_B_CTRL6 10634 * BLOCKS: ANA_LANE_3_QUAD_B 10635 * REGADDR: 0x9806 10636 * DEVAD: 1 10637 * DESC: control registers 0 10638 * RESETVAL: 0x0 (0) 10639 * ACCESS: R/W 10640 * FIELDS: 10641 * LA_DEGAIN 10642 * LA_DETUNE 10643 */ 10644 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r (0x00019806 | PHYMOD_REG_ACC_RAW) 10645 10646 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_SIZE 4 10647 10648 /* 10649 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL6. 10650 */ 10651 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_s { 10652 uint32_t v[1]; 10653 uint32_t ana_lane_3_quad_b_ctrl6[1]; 10654 uint32_t _ana_lane_3_quad_b_ctrl6; 10655 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_t; 10656 10657 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_CLR(r) (r).ana_lane_3_quad_b_ctrl6[0] = 0 10658 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_SET(r,d) (r).ana_lane_3_quad_b_ctrl6[0] = d 10659 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_GET(r) (r).ana_lane_3_quad_b_ctrl6[0] 10660 10661 /* 10662 * These macros can be used to access individual fields. 10663 */ 10664 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_3_quad_b_ctrl6[0]) >> 8) & 0xff) 10665 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_3_quad_b_ctrl6[0]=(((r).ana_lane_3_quad_b_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 10666 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_3_quad_b_ctrl6[0]) & 0x1f) 10667 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_3_quad_b_ctrl6[0]=(((r).ana_lane_3_quad_b_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 10668 10669 /* 10670 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL6. 10671 */ 10672 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r,_r._ana_lane_3_quad_b_ctrl6) 10673 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r,_r._ana_lane_3_quad_b_ctrl6) 10674 10675 /* 10676 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10677 * will be redefined without the chip prefix for easier programming. 10678 * If multiple chips will be programmed in the same source file, then you should 10679 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10680 * and refer to the fully qualified versions. 10681 */ 10682 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10683 10684 #define ANA_LANE_3_QUAD_B_CTRL6r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r 10685 #define ANA_LANE_3_QUAD_B_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_SIZE 10686 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_t ANA_LANE_3_QUAD_B_CTRL6r_t; 10687 #define ANA_LANE_3_QUAD_B_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_CLR 10688 #define ANA_LANE_3_QUAD_B_CTRL6r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_SET 10689 #define ANA_LANE_3_QUAD_B_CTRL6r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_GET 10690 #define ANA_LANE_3_QUAD_B_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DETUNEf_GET 10691 #define ANA_LANE_3_QUAD_B_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DETUNEf_SET 10692 #define ANA_LANE_3_QUAD_B_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DEGAINf_GET 10693 #define ANA_LANE_3_QUAD_B_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r_LA_DEGAINf_SET 10694 #define READ_ANA_LANE_3_QUAD_B_CTRL6r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL6r 10695 #define WRITE_ANA_LANE_3_QUAD_B_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL6r 10696 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL6r 10697 10698 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10699 /******************************************************************************* 10700 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL6r' 10701 */ 10702 10703 10704 10705 10706 /******************************************************************************* 10707 * CHIP: BCMI_HURACAN 10708 * REGISTER: ANA_LANE_3_QUAD_B_CTRL7 10709 * BLOCKS: ANA_LANE_3_QUAD_B 10710 * REGADDR: 0x9807 10711 * DEVAD: 1 10712 * DESC: control registers 0 10713 * RESETVAL: 0x0 (0) 10714 * ACCESS: R/W 10715 * FIELDS: 10716 * LA_LIN_MODE 10717 * RX_BIAS_FB_PDN 10718 */ 10719 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r (0x00019807 | PHYMOD_REG_ACC_RAW) 10720 10721 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_SIZE 4 10722 10723 /* 10724 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL7. 10725 */ 10726 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_s { 10727 uint32_t v[1]; 10728 uint32_t ana_lane_3_quad_b_ctrl7[1]; 10729 uint32_t _ana_lane_3_quad_b_ctrl7; 10730 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_t; 10731 10732 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_CLR(r) (r).ana_lane_3_quad_b_ctrl7[0] = 0 10733 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_SET(r,d) (r).ana_lane_3_quad_b_ctrl7[0] = d 10734 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_GET(r) (r).ana_lane_3_quad_b_ctrl7[0] 10735 10736 /* 10737 * These macros can be used to access individual fields. 10738 */ 10739 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_3_quad_b_ctrl7[0]) >> 8) & 0x1) 10740 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_3_quad_b_ctrl7[0]=(((r).ana_lane_3_quad_b_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 10741 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_3_quad_b_ctrl7[0]) & 0x1f) 10742 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_3_quad_b_ctrl7[0]=(((r).ana_lane_3_quad_b_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 10743 10744 /* 10745 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL7. 10746 */ 10747 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r,_r._ana_lane_3_quad_b_ctrl7) 10748 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r,_r._ana_lane_3_quad_b_ctrl7) 10749 10750 /* 10751 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10752 * will be redefined without the chip prefix for easier programming. 10753 * If multiple chips will be programmed in the same source file, then you should 10754 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10755 * and refer to the fully qualified versions. 10756 */ 10757 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10758 10759 #define ANA_LANE_3_QUAD_B_CTRL7r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r 10760 #define ANA_LANE_3_QUAD_B_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_SIZE 10761 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_t ANA_LANE_3_QUAD_B_CTRL7r_t; 10762 #define ANA_LANE_3_QUAD_B_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_CLR 10763 #define ANA_LANE_3_QUAD_B_CTRL7r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_SET 10764 #define ANA_LANE_3_QUAD_B_CTRL7r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_GET 10765 #define ANA_LANE_3_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_GET 10766 #define ANA_LANE_3_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_RX_BIAS_FB_PDNf_SET 10767 #define ANA_LANE_3_QUAD_B_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_LA_LIN_MODEf_GET 10768 #define ANA_LANE_3_QUAD_B_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r_LA_LIN_MODEf_SET 10769 #define READ_ANA_LANE_3_QUAD_B_CTRL7r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL7r 10770 #define WRITE_ANA_LANE_3_QUAD_B_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL7r 10771 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL7r 10772 10773 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10774 /******************************************************************************* 10775 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL7r' 10776 */ 10777 10778 10779 10780 10781 /******************************************************************************* 10782 * CHIP: BCMI_HURACAN 10783 * REGISTER: ANA_LANE_3_QUAD_B_CTRL8 10784 * BLOCKS: ANA_LANE_3_QUAD_B 10785 * REGADDR: 0x9808 10786 * DEVAD: 1 10787 * DESC: control registers 0 10788 * RESETVAL: 0x0 (0) 10789 * ACCESS: R/W 10790 * FIELDS: 10791 * LA_PD 10792 * LA_PD_IDLE 10793 * RXTX_RESERVED_FOR_99_95 10794 */ 10795 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r (0x00019808 | PHYMOD_REG_ACC_RAW) 10796 10797 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_SIZE 4 10798 10799 /* 10800 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL8. 10801 */ 10802 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_s { 10803 uint32_t v[1]; 10804 uint32_t ana_lane_3_quad_b_ctrl8[1]; 10805 uint32_t _ana_lane_3_quad_b_ctrl8; 10806 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_t; 10807 10808 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_CLR(r) (r).ana_lane_3_quad_b_ctrl8[0] = 0 10809 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_SET(r,d) (r).ana_lane_3_quad_b_ctrl8[0] = d 10810 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_GET(r) (r).ana_lane_3_quad_b_ctrl8[0] 10811 10812 /* 10813 * These macros can be used to access individual fields. 10814 */ 10815 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_3_quad_b_ctrl8[0]) >> 4) & 0x1f) 10816 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_3_quad_b_ctrl8[0]=(((r).ana_lane_3_quad_b_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 10817 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_3_quad_b_ctrl8[0]) >> 1) & 0x1) 10818 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_3_quad_b_ctrl8[0]=(((r).ana_lane_3_quad_b_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 10819 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_3_quad_b_ctrl8[0]) & 0x1) 10820 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_3_quad_b_ctrl8[0]=(((r).ana_lane_3_quad_b_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 10821 10822 /* 10823 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL8. 10824 */ 10825 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r,_r._ana_lane_3_quad_b_ctrl8) 10826 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r,_r._ana_lane_3_quad_b_ctrl8) 10827 10828 /* 10829 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10830 * will be redefined without the chip prefix for easier programming. 10831 * If multiple chips will be programmed in the same source file, then you should 10832 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10833 * and refer to the fully qualified versions. 10834 */ 10835 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10836 10837 #define ANA_LANE_3_QUAD_B_CTRL8r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r 10838 #define ANA_LANE_3_QUAD_B_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_SIZE 10839 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_t ANA_LANE_3_QUAD_B_CTRL8r_t; 10840 #define ANA_LANE_3_QUAD_B_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_CLR 10841 #define ANA_LANE_3_QUAD_B_CTRL8r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_SET 10842 #define ANA_LANE_3_QUAD_B_CTRL8r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_GET 10843 #define ANA_LANE_3_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 10844 #define ANA_LANE_3_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 10845 #define ANA_LANE_3_QUAD_B_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PD_IDLEf_GET 10846 #define ANA_LANE_3_QUAD_B_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PD_IDLEf_SET 10847 #define ANA_LANE_3_QUAD_B_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PDf_GET 10848 #define ANA_LANE_3_QUAD_B_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r_LA_PDf_SET 10849 #define READ_ANA_LANE_3_QUAD_B_CTRL8r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL8r 10850 #define WRITE_ANA_LANE_3_QUAD_B_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL8r 10851 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL8r 10852 10853 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10854 /******************************************************************************* 10855 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL8r' 10856 */ 10857 10858 10859 10860 10861 /******************************************************************************* 10862 * CHIP: BCMI_HURACAN 10863 * REGISTER: ANA_LANE_3_QUAD_B_CTRL9 10864 * BLOCKS: ANA_LANE_3_QUAD_B 10865 * REGADDR: 0x9809 10866 * DEVAD: 1 10867 * DESC: control registers 0 10868 * RESETVAL: 0x0 (0) 10869 * ACCESS: R/W 10870 * FIELDS: 10871 * DRV_POST1 10872 * DLINE_SWING_1 10873 * DLINE_SWING_2 10874 * DLINE_DELAY_CTRL 10875 */ 10876 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r (0x00019809 | PHYMOD_REG_ACC_RAW) 10877 10878 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_SIZE 4 10879 10880 /* 10881 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL9. 10882 */ 10883 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_s { 10884 uint32_t v[1]; 10885 uint32_t ana_lane_3_quad_b_ctrl9[1]; 10886 uint32_t _ana_lane_3_quad_b_ctrl9; 10887 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_t; 10888 10889 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_CLR(r) (r).ana_lane_3_quad_b_ctrl9[0] = 0 10890 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_SET(r,d) (r).ana_lane_3_quad_b_ctrl9[0] = d 10891 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_GET(r) (r).ana_lane_3_quad_b_ctrl9[0] 10892 10893 /* 10894 * These macros can be used to access individual fields. 10895 */ 10896 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_3_quad_b_ctrl9[0]) >> 12) & 0x7) 10897 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_3_quad_b_ctrl9[0]=(((r).ana_lane_3_quad_b_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 10898 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_3_quad_b_ctrl9[0]) >> 8) & 0x3) 10899 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_3_quad_b_ctrl9[0]=(((r).ana_lane_3_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 10900 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_3_quad_b_ctrl9[0]) >> 4) & 0x3) 10901 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_3_quad_b_ctrl9[0]=(((r).ana_lane_3_quad_b_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 10902 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_3_quad_b_ctrl9[0]) & 0xf) 10903 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_3_quad_b_ctrl9[0]=(((r).ana_lane_3_quad_b_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 10904 10905 /* 10906 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL9. 10907 */ 10908 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r,_r._ana_lane_3_quad_b_ctrl9) 10909 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r,_r._ana_lane_3_quad_b_ctrl9) 10910 10911 /* 10912 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 10913 * will be redefined without the chip prefix for easier programming. 10914 * If multiple chips will be programmed in the same source file, then you should 10915 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 10916 * and refer to the fully qualified versions. 10917 */ 10918 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 10919 10920 #define ANA_LANE_3_QUAD_B_CTRL9r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r 10921 #define ANA_LANE_3_QUAD_B_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_SIZE 10922 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_t ANA_LANE_3_QUAD_B_CTRL9r_t; 10923 #define ANA_LANE_3_QUAD_B_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_CLR 10924 #define ANA_LANE_3_QUAD_B_CTRL9r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_SET 10925 #define ANA_LANE_3_QUAD_B_CTRL9r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_GET 10926 #define ANA_LANE_3_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_GET 10927 #define ANA_LANE_3_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_DELAY_CTRLf_SET 10928 #define ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_2f_GET 10929 #define ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_2f_SET 10930 #define ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_1f_GET 10931 #define ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DLINE_SWING_1f_SET 10932 #define ANA_LANE_3_QUAD_B_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DRV_POST1f_GET 10933 #define ANA_LANE_3_QUAD_B_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r_DRV_POST1f_SET 10934 #define READ_ANA_LANE_3_QUAD_B_CTRL9r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL9r 10935 #define WRITE_ANA_LANE_3_QUAD_B_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL9r 10936 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL9r 10937 10938 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 10939 /******************************************************************************* 10940 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL9r' 10941 */ 10942 10943 10944 10945 10946 /******************************************************************************* 10947 * CHIP: BCMI_HURACAN 10948 * REGISTER: ANA_LANE_3_QUAD_B_CTRL10 10949 * BLOCKS: ANA_LANE_3_QUAD_B 10950 * REGADDR: 0x980a 10951 * DEVAD: 1 10952 * DESC: control registers 0 10953 * RESETVAL: 0x0 (0) 10954 * ACCESS: R/W 10955 * FIELDS: 10956 * DRV_PWD 10957 * DLINE_PWD 10958 * DRV_VBSEL 10959 * DRV_MAIN 10960 * DRV_MAIN_PU 10961 */ 10962 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r (0x0001980a | PHYMOD_REG_ACC_RAW) 10963 10964 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_SIZE 4 10965 10966 /* 10967 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL10. 10968 */ 10969 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_s { 10970 uint32_t v[1]; 10971 uint32_t ana_lane_3_quad_b_ctrl10[1]; 10972 uint32_t _ana_lane_3_quad_b_ctrl10; 10973 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_t; 10974 10975 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_CLR(r) (r).ana_lane_3_quad_b_ctrl10[0] = 0 10976 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_SET(r,d) (r).ana_lane_3_quad_b_ctrl10[0] = d 10977 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_GET(r) (r).ana_lane_3_quad_b_ctrl10[0] 10978 10979 /* 10980 * These macros can be used to access individual fields. 10981 */ 10982 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_3_quad_b_ctrl10[0]) >> 12) & 0xf) 10983 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_3_quad_b_ctrl10[0]=(((r).ana_lane_3_quad_b_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 10984 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_3_quad_b_ctrl10[0]) >> 4) & 0x3f) 10985 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_3_quad_b_ctrl10[0]=(((r).ana_lane_3_quad_b_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 10986 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_3_quad_b_ctrl10[0]) >> 2) & 0x1) 10987 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_3_quad_b_ctrl10[0]=(((r).ana_lane_3_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 10988 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_3_quad_b_ctrl10[0]) >> 1) & 0x1) 10989 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_3_quad_b_ctrl10[0]=(((r).ana_lane_3_quad_b_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 10990 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_3_quad_b_ctrl10[0]) & 0x1) 10991 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_3_quad_b_ctrl10[0]=(((r).ana_lane_3_quad_b_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 10992 10993 /* 10994 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL10. 10995 */ 10996 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r,_r._ana_lane_3_quad_b_ctrl10) 10997 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r,_r._ana_lane_3_quad_b_ctrl10) 10998 10999 /* 11000 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11001 * will be redefined without the chip prefix for easier programming. 11002 * If multiple chips will be programmed in the same source file, then you should 11003 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11004 * and refer to the fully qualified versions. 11005 */ 11006 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11007 11008 #define ANA_LANE_3_QUAD_B_CTRL10r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r 11009 #define ANA_LANE_3_QUAD_B_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_SIZE 11010 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_t ANA_LANE_3_QUAD_B_CTRL10r_t; 11011 #define ANA_LANE_3_QUAD_B_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_CLR 11012 #define ANA_LANE_3_QUAD_B_CTRL10r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_SET 11013 #define ANA_LANE_3_QUAD_B_CTRL10r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_GET 11014 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAIN_PUf_GET 11015 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAIN_PUf_SET 11016 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAINf_GET 11017 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_MAINf_SET 11018 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_VBSELf_GET 11019 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_VBSELf_SET 11020 #define ANA_LANE_3_QUAD_B_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DLINE_PWDf_GET 11021 #define ANA_LANE_3_QUAD_B_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DLINE_PWDf_SET 11022 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_PWDf_GET 11023 #define ANA_LANE_3_QUAD_B_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r_DRV_PWDf_SET 11024 #define READ_ANA_LANE_3_QUAD_B_CTRL10r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL10r 11025 #define WRITE_ANA_LANE_3_QUAD_B_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL10r 11026 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL10r 11027 11028 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11029 /******************************************************************************* 11030 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL10r' 11031 */ 11032 11033 11034 11035 11036 /******************************************************************************* 11037 * CHIP: BCMI_HURACAN 11038 * REGISTER: ANA_LANE_3_QUAD_B_CTRL11 11039 * BLOCKS: ANA_LANE_3_QUAD_B 11040 * REGADDR: 0x980b 11041 * DEVAD: 1 11042 * DESC: control registers 0 11043 * RESETVAL: 0x0 (0) 11044 * ACCESS: R/W 11045 * FIELDS: 11046 * RXTX_RESERVED_FOR_143_128 11047 */ 11048 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r (0x0001980b | PHYMOD_REG_ACC_RAW) 11049 11050 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_SIZE 4 11051 11052 /* 11053 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL11. 11054 */ 11055 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_s { 11056 uint32_t v[1]; 11057 uint32_t ana_lane_3_quad_b_ctrl11[1]; 11058 uint32_t _ana_lane_3_quad_b_ctrl11; 11059 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_t; 11060 11061 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_CLR(r) (r).ana_lane_3_quad_b_ctrl11[0] = 0 11062 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_SET(r,d) (r).ana_lane_3_quad_b_ctrl11[0] = d 11063 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_GET(r) (r).ana_lane_3_quad_b_ctrl11[0] 11064 11065 /* 11066 * These macros can be used to access individual fields. 11067 */ 11068 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_3_quad_b_ctrl11[0]) & 0xffff) 11069 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_3_quad_b_ctrl11[0]=(((r).ana_lane_3_quad_b_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 11070 11071 /* 11072 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL11. 11073 */ 11074 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r,_r._ana_lane_3_quad_b_ctrl11) 11075 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r,_r._ana_lane_3_quad_b_ctrl11) 11076 11077 /* 11078 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11079 * will be redefined without the chip prefix for easier programming. 11080 * If multiple chips will be programmed in the same source file, then you should 11081 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11082 * and refer to the fully qualified versions. 11083 */ 11084 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11085 11086 #define ANA_LANE_3_QUAD_B_CTRL11r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r 11087 #define ANA_LANE_3_QUAD_B_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_SIZE 11088 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_t ANA_LANE_3_QUAD_B_CTRL11r_t; 11089 #define ANA_LANE_3_QUAD_B_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_CLR 11090 #define ANA_LANE_3_QUAD_B_CTRL11r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_SET 11091 #define ANA_LANE_3_QUAD_B_CTRL11r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_GET 11092 #define ANA_LANE_3_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 11093 #define ANA_LANE_3_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 11094 #define READ_ANA_LANE_3_QUAD_B_CTRL11r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL11r 11095 #define WRITE_ANA_LANE_3_QUAD_B_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL11r 11096 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL11r 11097 11098 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11099 /******************************************************************************* 11100 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL11r' 11101 */ 11102 11103 11104 11105 11106 /******************************************************************************* 11107 * CHIP: BCMI_HURACAN 11108 * REGISTER: ANA_LANE_3_QUAD_B_CTRL12 11109 * BLOCKS: ANA_LANE_3_QUAD_B 11110 * REGADDR: 0x980c 11111 * DEVAD: 1 11112 * DESC: control registers 0 11113 * RESETVAL: 0x0 (0) 11114 * ACCESS: R/W 11115 * FIELDS: 11116 * LA_RESCAL_FRC_VAL 11117 * LA_RESCAL_FRC 11118 * DRV_RESCAL_FRC_VAL 11119 * DRV_RESCAL_FRC 11120 */ 11121 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r (0x0001980c | PHYMOD_REG_ACC_RAW) 11122 11123 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_SIZE 4 11124 11125 /* 11126 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL12. 11127 */ 11128 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_s { 11129 uint32_t v[1]; 11130 uint32_t ana_lane_3_quad_b_ctrl12[1]; 11131 uint32_t _ana_lane_3_quad_b_ctrl12; 11132 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_t; 11133 11134 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_CLR(r) (r).ana_lane_3_quad_b_ctrl12[0] = 0 11135 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_SET(r,d) (r).ana_lane_3_quad_b_ctrl12[0] = d 11136 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_GET(r) (r).ana_lane_3_quad_b_ctrl12[0] 11137 11138 /* 11139 * These macros can be used to access individual fields. 11140 */ 11141 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_b_ctrl12[0]) >> 12) & 0x1) 11142 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_b_ctrl12[0]=(((r).ana_lane_3_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 11143 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_b_ctrl12[0]) >> 8) & 0xf) 11144 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_b_ctrl12[0]=(((r).ana_lane_3_quad_b_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 11145 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_b_ctrl12[0]) >> 4) & 0x1) 11146 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_b_ctrl12[0]=(((r).ana_lane_3_quad_b_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 11147 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_b_ctrl12[0]) & 0xf) 11148 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_b_ctrl12[0]=(((r).ana_lane_3_quad_b_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 11149 11150 /* 11151 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL12. 11152 */ 11153 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r,_r._ana_lane_3_quad_b_ctrl12) 11154 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r,_r._ana_lane_3_quad_b_ctrl12) 11155 11156 /* 11157 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11158 * will be redefined without the chip prefix for easier programming. 11159 * If multiple chips will be programmed in the same source file, then you should 11160 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11161 * and refer to the fully qualified versions. 11162 */ 11163 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11164 11165 #define ANA_LANE_3_QUAD_B_CTRL12r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r 11166 #define ANA_LANE_3_QUAD_B_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_SIZE 11167 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_t ANA_LANE_3_QUAD_B_CTRL12r_t; 11168 #define ANA_LANE_3_QUAD_B_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_CLR 11169 #define ANA_LANE_3_QUAD_B_CTRL12r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_SET 11170 #define ANA_LANE_3_QUAD_B_CTRL12r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_GET 11171 #define ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_GET 11172 #define ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRCf_SET 11173 #define ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_GET 11174 #define ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_DRV_RESCAL_FRC_VALf_SET 11175 #define ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRCf_GET 11176 #define ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRCf_SET 11177 #define ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_GET 11178 #define ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r_LA_RESCAL_FRC_VALf_SET 11179 #define READ_ANA_LANE_3_QUAD_B_CTRL12r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL12r 11180 #define WRITE_ANA_LANE_3_QUAD_B_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL12r 11181 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL12r 11182 11183 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11184 /******************************************************************************* 11185 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL12r' 11186 */ 11187 11188 11189 11190 11191 /******************************************************************************* 11192 * CHIP: BCMI_HURACAN 11193 * REGISTER: ANA_LANE_3_QUAD_B_CTRL13 11194 * BLOCKS: ANA_LANE_3_QUAD_B 11195 * REGADDR: 0x980d 11196 * DEVAD: 1 11197 * DESC: control registers 0 11198 * RESETVAL: 0x0 (0) 11199 * ACCESS: R/W 11200 * FIELDS: 11201 * CTLE_RESCAL_FRC_VAL 11202 * CTLE_RESCAL_FRC 11203 */ 11204 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r (0x0001980d | PHYMOD_REG_ACC_RAW) 11205 11206 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_SIZE 4 11207 11208 /* 11209 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL13. 11210 */ 11211 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_s { 11212 uint32_t v[1]; 11213 uint32_t ana_lane_3_quad_b_ctrl13[1]; 11214 uint32_t _ana_lane_3_quad_b_ctrl13; 11215 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_t; 11216 11217 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CLR(r) (r).ana_lane_3_quad_b_ctrl13[0] = 0 11218 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_SET(r,d) (r).ana_lane_3_quad_b_ctrl13[0] = d 11219 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_GET(r) (r).ana_lane_3_quad_b_ctrl13[0] 11220 11221 /* 11222 * These macros can be used to access individual fields. 11223 */ 11224 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_b_ctrl13[0]) >> 4) & 0x1) 11225 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_b_ctrl13[0]=(((r).ana_lane_3_quad_b_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 11226 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_b_ctrl13[0]) & 0xf) 11227 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_b_ctrl13[0]=(((r).ana_lane_3_quad_b_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 11228 11229 /* 11230 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL13. 11231 */ 11232 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r,_r._ana_lane_3_quad_b_ctrl13) 11233 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r,_r._ana_lane_3_quad_b_ctrl13) 11234 11235 /* 11236 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11237 * will be redefined without the chip prefix for easier programming. 11238 * If multiple chips will be programmed in the same source file, then you should 11239 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11240 * and refer to the fully qualified versions. 11241 */ 11242 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11243 11244 #define ANA_LANE_3_QUAD_B_CTRL13r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r 11245 #define ANA_LANE_3_QUAD_B_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_SIZE 11246 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_t ANA_LANE_3_QUAD_B_CTRL13r_t; 11247 #define ANA_LANE_3_QUAD_B_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CLR 11248 #define ANA_LANE_3_QUAD_B_CTRL13r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_SET 11249 #define ANA_LANE_3_QUAD_B_CTRL13r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_GET 11250 #define ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_GET 11251 #define ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRCf_SET 11252 #define ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 11253 #define ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 11254 #define READ_ANA_LANE_3_QUAD_B_CTRL13r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL13r 11255 #define WRITE_ANA_LANE_3_QUAD_B_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL13r 11256 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL13r 11257 11258 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11259 /******************************************************************************* 11260 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL13r' 11261 */ 11262 11263 11264 11265 11266 /******************************************************************************* 11267 * CHIP: BCMI_HURACAN 11268 * REGISTER: ANA_LANE_3_QUAD_B_CTRL14 11269 * BLOCKS: ANA_LANE_3_QUAD_B 11270 * REGADDR: 0x980e 11271 * DEVAD: 1 11272 * DESC: control registers 0 11273 * RESETVAL: 0x0 (0) 11274 * ACCESS: R/W 11275 * FIELDS: 11276 * TX_IDLE_FRC_VAL 11277 * TX_IDLE_FRC 11278 * RXSD_IDLE_OVRD 11279 */ 11280 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r (0x0001980e | PHYMOD_REG_ACC_RAW) 11281 11282 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_SIZE 4 11283 11284 /* 11285 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL14. 11286 */ 11287 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_s { 11288 uint32_t v[1]; 11289 uint32_t ana_lane_3_quad_b_ctrl14[1]; 11290 uint32_t _ana_lane_3_quad_b_ctrl14; 11291 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_t; 11292 11293 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_CLR(r) (r).ana_lane_3_quad_b_ctrl14[0] = 0 11294 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_SET(r,d) (r).ana_lane_3_quad_b_ctrl14[0] = d 11295 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_GET(r) (r).ana_lane_3_quad_b_ctrl14[0] 11296 11297 /* 11298 * These macros can be used to access individual fields. 11299 */ 11300 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_3_quad_b_ctrl14[0]) >> 4) & 0x1) 11301 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_3_quad_b_ctrl14[0]=(((r).ana_lane_3_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 11302 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_3_quad_b_ctrl14[0]) >> 1) & 0x1) 11303 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_3_quad_b_ctrl14[0]=(((r).ana_lane_3_quad_b_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 11304 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_3_quad_b_ctrl14[0]) & 0x1) 11305 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_b_ctrl14[0]=(((r).ana_lane_3_quad_b_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 11306 11307 /* 11308 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL14. 11309 */ 11310 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r,_r._ana_lane_3_quad_b_ctrl14) 11311 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r,_r._ana_lane_3_quad_b_ctrl14) 11312 11313 /* 11314 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11315 * will be redefined without the chip prefix for easier programming. 11316 * If multiple chips will be programmed in the same source file, then you should 11317 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11318 * and refer to the fully qualified versions. 11319 */ 11320 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11321 11322 #define ANA_LANE_3_QUAD_B_CTRL14r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r 11323 #define ANA_LANE_3_QUAD_B_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_SIZE 11324 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_t ANA_LANE_3_QUAD_B_CTRL14r_t; 11325 #define ANA_LANE_3_QUAD_B_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_CLR 11326 #define ANA_LANE_3_QUAD_B_CTRL14r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_SET 11327 #define ANA_LANE_3_QUAD_B_CTRL14r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_GET 11328 #define ANA_LANE_3_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_GET 11329 #define ANA_LANE_3_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_RXSD_IDLE_OVRDf_SET 11330 #define ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRCf_GET 11331 #define ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRCf_SET 11332 #define ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_GET 11333 #define ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r_TX_IDLE_FRC_VALf_SET 11334 #define READ_ANA_LANE_3_QUAD_B_CTRL14r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL14r 11335 #define WRITE_ANA_LANE_3_QUAD_B_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL14r 11336 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL14r 11337 11338 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11339 /******************************************************************************* 11340 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL14r' 11341 */ 11342 11343 11344 11345 11346 /******************************************************************************* 11347 * CHIP: BCMI_HURACAN 11348 * REGISTER: ANA_LANE_3_QUAD_B_CTRL15 11349 * BLOCKS: ANA_LANE_3_QUAD_B 11350 * REGADDR: 0x980f 11351 * DEVAD: 1 11352 * DESC: sigdet filter settings 0 11353 * RESETVAL: 0x0 (0) 11354 * ACCESS: R/W 11355 * FIELDS: 11356 * SIGDET_DIS 11357 * SIGDET_1US_EN 11358 * SIGDET_FRC_VAL 11359 * SIGDET_FRC 11360 * HOLD_LOS_COUNT 11361 * HOLD_SD_COUNT 11362 */ 11363 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r (0x0001980f | PHYMOD_REG_ACC_RAW) 11364 11365 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIZE 4 11366 11367 /* 11368 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL15. 11369 */ 11370 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_s { 11371 uint32_t v[1]; 11372 uint32_t ana_lane_3_quad_b_ctrl15[1]; 11373 uint32_t _ana_lane_3_quad_b_ctrl15; 11374 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_t; 11375 11376 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_CLR(r) (r).ana_lane_3_quad_b_ctrl15[0] = 0 11377 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SET(r,d) (r).ana_lane_3_quad_b_ctrl15[0] = d 11378 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_GET(r) (r).ana_lane_3_quad_b_ctrl15[0] 11379 11380 /* 11381 * These macros can be used to access individual fields. 11382 */ 11383 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_b_ctrl15[0]) >> 8) & 0x7) 11384 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_b_ctrl15[0]=(((r).ana_lane_3_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 11385 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_3_quad_b_ctrl15[0]) >> 4) & 0x7) 11386 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_b_ctrl15[0]=(((r).ana_lane_3_quad_b_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 11387 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_3_quad_b_ctrl15[0]) >> 3) & 0x1) 11388 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_3_quad_b_ctrl15[0]=(((r).ana_lane_3_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 11389 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_b_ctrl15[0]) >> 2) & 0x1) 11390 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_b_ctrl15[0]=(((r).ana_lane_3_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 11391 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_3_quad_b_ctrl15[0]) >> 1) & 0x1) 11392 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_3_quad_b_ctrl15[0]=(((r).ana_lane_3_quad_b_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 11393 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_3_quad_b_ctrl15[0]) & 0x1) 11394 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_3_quad_b_ctrl15[0]=(((r).ana_lane_3_quad_b_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 11395 11396 /* 11397 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL15. 11398 */ 11399 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r,_r._ana_lane_3_quad_b_ctrl15) 11400 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r,_r._ana_lane_3_quad_b_ctrl15) 11401 11402 /* 11403 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11404 * will be redefined without the chip prefix for easier programming. 11405 * If multiple chips will be programmed in the same source file, then you should 11406 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11407 * and refer to the fully qualified versions. 11408 */ 11409 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11410 11411 #define ANA_LANE_3_QUAD_B_CTRL15r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r 11412 #define ANA_LANE_3_QUAD_B_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIZE 11413 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_t ANA_LANE_3_QUAD_B_CTRL15r_t; 11414 #define ANA_LANE_3_QUAD_B_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_CLR 11415 #define ANA_LANE_3_QUAD_B_CTRL15r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SET 11416 #define ANA_LANE_3_QUAD_B_CTRL15r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_GET 11417 #define ANA_LANE_3_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_SD_COUNTf_GET 11418 #define ANA_LANE_3_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_SD_COUNTf_SET 11419 #define ANA_LANE_3_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_GET 11420 #define ANA_LANE_3_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_HOLD_LOS_COUNTf_SET 11421 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRCf_GET 11422 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRCf_SET 11423 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRC_VALf_GET 11424 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_FRC_VALf_SET 11425 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_1US_ENf_GET 11426 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_1US_ENf_SET 11427 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_DISf_GET 11428 #define ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r_SIGDET_DISf_SET 11429 #define READ_ANA_LANE_3_QUAD_B_CTRL15r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL15r 11430 #define WRITE_ANA_LANE_3_QUAD_B_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL15r 11431 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL15r 11432 11433 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11434 /******************************************************************************* 11435 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL15r' 11436 */ 11437 11438 11439 11440 11441 /******************************************************************************* 11442 * CHIP: BCMI_HURACAN 11443 * REGISTER: ANA_LANE_3_QUAD_B_CTRL16 11444 * BLOCKS: ANA_LANE_3_QUAD_B 11445 * REGADDR: 0x9810 11446 * DEVAD: 1 11447 * DESC: sigdet filter settings 1 11448 * RESETVAL: 0x0 (0) 11449 * ACCESS: R/W 11450 * FIELDS: 11451 * LOS_COUNT 11452 * SD_COUNT 11453 */ 11454 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r (0x00019810 | PHYMOD_REG_ACC_RAW) 11455 11456 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SIZE 4 11457 11458 /* 11459 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_CTRL16. 11460 */ 11461 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_s { 11462 uint32_t v[1]; 11463 uint32_t ana_lane_3_quad_b_ctrl16[1]; 11464 uint32_t _ana_lane_3_quad_b_ctrl16; 11465 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_t; 11466 11467 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_CLR(r) (r).ana_lane_3_quad_b_ctrl16[0] = 0 11468 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SET(r,d) (r).ana_lane_3_quad_b_ctrl16[0] = d 11469 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_GET(r) (r).ana_lane_3_quad_b_ctrl16[0] 11470 11471 /* 11472 * These macros can be used to access individual fields. 11473 */ 11474 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_b_ctrl16[0]) >> 8) & 0x1f) 11475 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_b_ctrl16[0]=(((r).ana_lane_3_quad_b_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 11476 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_3_quad_b_ctrl16[0]) & 0x1f) 11477 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_b_ctrl16[0]=(((r).ana_lane_3_quad_b_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 11478 11479 /* 11480 * These macros can be used to access ANA_LANE_3_QUAD_B_CTRL16. 11481 */ 11482 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r,_r._ana_lane_3_quad_b_ctrl16) 11483 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r,_r._ana_lane_3_quad_b_ctrl16) 11484 11485 /* 11486 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11487 * will be redefined without the chip prefix for easier programming. 11488 * If multiple chips will be programmed in the same source file, then you should 11489 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11490 * and refer to the fully qualified versions. 11491 */ 11492 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11493 11494 #define ANA_LANE_3_QUAD_B_CTRL16r BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r 11495 #define ANA_LANE_3_QUAD_B_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SIZE 11496 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_t ANA_LANE_3_QUAD_B_CTRL16r_t; 11497 #define ANA_LANE_3_QUAD_B_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_CLR 11498 #define ANA_LANE_3_QUAD_B_CTRL16r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SET 11499 #define ANA_LANE_3_QUAD_B_CTRL16r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_GET 11500 #define ANA_LANE_3_QUAD_B_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SD_COUNTf_GET 11501 #define ANA_LANE_3_QUAD_B_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_SD_COUNTf_SET 11502 #define ANA_LANE_3_QUAD_B_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_LOS_COUNTf_GET 11503 #define ANA_LANE_3_QUAD_B_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r_LOS_COUNTf_SET 11504 #define READ_ANA_LANE_3_QUAD_B_CTRL16r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_CTRL16r 11505 #define WRITE_ANA_LANE_3_QUAD_B_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_CTRL16r 11506 #define MODIFY_ANA_LANE_3_QUAD_B_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_CTRL16r 11507 11508 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11509 /******************************************************************************* 11510 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_CTRL16r' 11511 */ 11512 11513 11514 11515 11516 /******************************************************************************* 11517 * CHIP: BCMI_HURACAN 11518 * REGISTER: ANA_LANE_3_QUAD_B_STATUS0 11519 * BLOCKS: ANA_LANE_3_QUAD_B 11520 * REGADDR: 0x9820 11521 * DEVAD: 1 11522 * DESC: status registers 0 11523 * RESETVAL: 0x0 (0) 11524 * ACCESS: R/W 11525 * FIELDS: 11526 * O_RX_SIGDET 11527 * DG_RX_SIGDET 11528 */ 11529 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r (0x00019820 | PHYMOD_REG_ACC_RAW) 11530 11531 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_SIZE 4 11532 11533 /* 11534 * This structure should be used to declare and program ANA_LANE_3_QUAD_B_STATUS0. 11535 */ 11536 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_s { 11537 uint32_t v[1]; 11538 uint32_t ana_lane_3_quad_b_status0[1]; 11539 uint32_t _ana_lane_3_quad_b_status0; 11540 } BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_t; 11541 11542 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_CLR(r) (r).ana_lane_3_quad_b_status0[0] = 0 11543 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_SET(r,d) (r).ana_lane_3_quad_b_status0[0] = d 11544 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_GET(r) (r).ana_lane_3_quad_b_status0[0] 11545 11546 /* 11547 * These macros can be used to access individual fields. 11548 */ 11549 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_3_quad_b_status0[0]) >> 1) & 0x1) 11550 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_b_status0[0]=(((r).ana_lane_3_quad_b_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 11551 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_3_quad_b_status0[0]) & 0x1) 11552 #define BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_b_status0[0]=(((r).ana_lane_3_quad_b_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 11553 11554 /* 11555 * These macros can be used to access ANA_LANE_3_QUAD_B_STATUS0. 11556 */ 11557 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r,_r._ana_lane_3_quad_b_status0) 11558 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r,_r._ana_lane_3_quad_b_status0) 11559 11560 /* 11561 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11562 * will be redefined without the chip prefix for easier programming. 11563 * If multiple chips will be programmed in the same source file, then you should 11564 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11565 * and refer to the fully qualified versions. 11566 */ 11567 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11568 11569 #define ANA_LANE_3_QUAD_B_STATUS0r BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r 11570 #define ANA_LANE_3_QUAD_B_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_SIZE 11571 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_t ANA_LANE_3_QUAD_B_STATUS0r_t; 11572 #define ANA_LANE_3_QUAD_B_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_CLR 11573 #define ANA_LANE_3_QUAD_B_STATUS0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_SET 11574 #define ANA_LANE_3_QUAD_B_STATUS0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_GET 11575 #define ANA_LANE_3_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_DG_RX_SIGDETf_GET 11576 #define ANA_LANE_3_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_DG_RX_SIGDETf_SET 11577 #define ANA_LANE_3_QUAD_B_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_O_RX_SIGDETf_GET 11578 #define ANA_LANE_3_QUAD_B_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r_O_RX_SIGDETf_SET 11579 #define READ_ANA_LANE_3_QUAD_B_STATUS0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_B_STATUS0r 11580 #define WRITE_ANA_LANE_3_QUAD_B_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_B_STATUS0r 11581 #define MODIFY_ANA_LANE_3_QUAD_B_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_B_STATUS0r 11582 11583 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11584 /******************************************************************************* 11585 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_B_STATUS0r' 11586 */ 11587 11588 11589 11590 11591 /******************************************************************************* 11592 * CHIP: BCMI_HURACAN 11593 * REGISTER: ANA_LANE_0_QUAD_C_CTRL0 11594 * BLOCKS: ANA_LANE_0_QUAD_C 11595 * REGADDR: 0xa100 11596 * DEVAD: 1 11597 * DESC: control registers 0 11598 * RESETVAL: 0x0 (0) 11599 * ACCESS: R/W 11600 * FIELDS: 11601 * RXTX_PWRDN 11602 * RX_SIGDET_BYPASS 11603 * RX_SIGDET_PWRDN 11604 * RX_SIGDECT_12GMODE 11605 * DC_COUPLE 11606 */ 11607 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r (0x0001a100 | PHYMOD_REG_ACC_RAW) 11608 11609 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_SIZE 4 11610 11611 /* 11612 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL0. 11613 */ 11614 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_s { 11615 uint32_t v[1]; 11616 uint32_t ana_lane_0_quad_c_ctrl0[1]; 11617 uint32_t _ana_lane_0_quad_c_ctrl0; 11618 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_t; 11619 11620 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_CLR(r) (r).ana_lane_0_quad_c_ctrl0[0] = 0 11621 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_SET(r,d) (r).ana_lane_0_quad_c_ctrl0[0] = d 11622 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_GET(r) (r).ana_lane_0_quad_c_ctrl0[0] 11623 11624 /* 11625 * These macros can be used to access individual fields. 11626 */ 11627 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_0_quad_c_ctrl0[0]) >> 4) & 0x1) 11628 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_0_quad_c_ctrl0[0]=(((r).ana_lane_0_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 11629 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_0_quad_c_ctrl0[0]) >> 3) & 0x1) 11630 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_0_quad_c_ctrl0[0]=(((r).ana_lane_0_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 11631 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_0_quad_c_ctrl0[0]) >> 2) & 0x1) 11632 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_0_quad_c_ctrl0[0]=(((r).ana_lane_0_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 11633 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_0_quad_c_ctrl0[0]) >> 1) & 0x1) 11634 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_0_quad_c_ctrl0[0]=(((r).ana_lane_0_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 11635 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_0_quad_c_ctrl0[0]) & 0x1) 11636 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_0_quad_c_ctrl0[0]=(((r).ana_lane_0_quad_c_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 11637 11638 /* 11639 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL0. 11640 */ 11641 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r,_r._ana_lane_0_quad_c_ctrl0) 11642 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r,_r._ana_lane_0_quad_c_ctrl0) 11643 11644 /* 11645 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11646 * will be redefined without the chip prefix for easier programming. 11647 * If multiple chips will be programmed in the same source file, then you should 11648 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11649 * and refer to the fully qualified versions. 11650 */ 11651 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11652 11653 #define ANA_LANE_0_QUAD_C_CTRL0r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r 11654 #define ANA_LANE_0_QUAD_C_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_SIZE 11655 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_t ANA_LANE_0_QUAD_C_CTRL0r_t; 11656 #define ANA_LANE_0_QUAD_C_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_CLR 11657 #define ANA_LANE_0_QUAD_C_CTRL0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_SET 11658 #define ANA_LANE_0_QUAD_C_CTRL0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_GET 11659 #define ANA_LANE_0_QUAD_C_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_DC_COUPLEf_GET 11660 #define ANA_LANE_0_QUAD_C_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_DC_COUPLEf_SET 11661 #define ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET 11662 #define ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET 11663 #define ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET 11664 #define ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET 11665 #define ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET 11666 #define ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET 11667 #define ANA_LANE_0_QUAD_C_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RXTX_PWRDNf_GET 11668 #define ANA_LANE_0_QUAD_C_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r_RXTX_PWRDNf_SET 11669 #define READ_ANA_LANE_0_QUAD_C_CTRL0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL0r 11670 #define WRITE_ANA_LANE_0_QUAD_C_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL0r 11671 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL0r 11672 11673 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11674 /******************************************************************************* 11675 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL0r' 11676 */ 11677 11678 11679 11680 11681 /******************************************************************************* 11682 * CHIP: BCMI_HURACAN 11683 * REGISTER: ANA_LANE_0_QUAD_C_CTRL1 11684 * BLOCKS: ANA_LANE_0_QUAD_C 11685 * REGADDR: 0xa101 11686 * DEVAD: 1 11687 * DESC: control registers 0 11688 * RESETVAL: 0x0 (0) 11689 * ACCESS: R/W 11690 * FIELDS: 11691 * RX_SIGDET_THRESHOLD 11692 * REF_OCL 11693 * OCL_PWRDN 11694 * OCL_DISABLE_LOOP 11695 * RXTX_RESERVED_FOR_15_12 11696 */ 11697 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r (0x0001a101 | PHYMOD_REG_ACC_RAW) 11698 11699 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_SIZE 4 11700 11701 /* 11702 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL1. 11703 */ 11704 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_s { 11705 uint32_t v[1]; 11706 uint32_t ana_lane_0_quad_c_ctrl1[1]; 11707 uint32_t _ana_lane_0_quad_c_ctrl1; 11708 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_t; 11709 11710 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_CLR(r) (r).ana_lane_0_quad_c_ctrl1[0] = 0 11711 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_SET(r,d) (r).ana_lane_0_quad_c_ctrl1[0] = d 11712 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_GET(r) (r).ana_lane_0_quad_c_ctrl1[0] 11713 11714 /* 11715 * These macros can be used to access individual fields. 11716 */ 11717 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_0_quad_c_ctrl1[0]) >> 12) & 0xf) 11718 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_0_quad_c_ctrl1[0]=(((r).ana_lane_0_quad_c_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 11719 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_0_quad_c_ctrl1[0]) >> 9) & 0x1) 11720 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_0_quad_c_ctrl1[0]=(((r).ana_lane_0_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 11721 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_0_quad_c_ctrl1[0]) >> 8) & 0x1) 11722 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_0_quad_c_ctrl1[0]=(((r).ana_lane_0_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 11723 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_0_quad_c_ctrl1[0]) >> 4) & 0x3) 11724 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_0_quad_c_ctrl1[0]=(((r).ana_lane_0_quad_c_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 11725 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_0_quad_c_ctrl1[0]) & 0x7) 11726 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_0_quad_c_ctrl1[0]=(((r).ana_lane_0_quad_c_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 11727 11728 /* 11729 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL1. 11730 */ 11731 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r,_r._ana_lane_0_quad_c_ctrl1) 11732 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r,_r._ana_lane_0_quad_c_ctrl1) 11733 11734 /* 11735 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11736 * will be redefined without the chip prefix for easier programming. 11737 * If multiple chips will be programmed in the same source file, then you should 11738 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11739 * and refer to the fully qualified versions. 11740 */ 11741 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11742 11743 #define ANA_LANE_0_QUAD_C_CTRL1r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r 11744 #define ANA_LANE_0_QUAD_C_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_SIZE 11745 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_t ANA_LANE_0_QUAD_C_CTRL1r_t; 11746 #define ANA_LANE_0_QUAD_C_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_CLR 11747 #define ANA_LANE_0_QUAD_C_CTRL1r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_SET 11748 #define ANA_LANE_0_QUAD_C_CTRL1r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_GET 11749 #define ANA_LANE_0_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 11750 #define ANA_LANE_0_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 11751 #define ANA_LANE_0_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET 11752 #define ANA_LANE_0_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET 11753 #define ANA_LANE_0_QUAD_C_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_PWRDNf_GET 11754 #define ANA_LANE_0_QUAD_C_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_OCL_PWRDNf_SET 11755 #define ANA_LANE_0_QUAD_C_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_REF_OCLf_GET 11756 #define ANA_LANE_0_QUAD_C_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_REF_OCLf_SET 11757 #define ANA_LANE_0_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET 11758 #define ANA_LANE_0_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET 11759 #define READ_ANA_LANE_0_QUAD_C_CTRL1r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL1r 11760 #define WRITE_ANA_LANE_0_QUAD_C_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL1r 11761 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL1r 11762 11763 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11764 /******************************************************************************* 11765 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL1r' 11766 */ 11767 11768 11769 11770 11771 /******************************************************************************* 11772 * CHIP: BCMI_HURACAN 11773 * REGISTER: ANA_LANE_0_QUAD_C_CTRL2 11774 * BLOCKS: ANA_LANE_0_QUAD_C 11775 * REGADDR: 0xa102 11776 * DEVAD: 1 11777 * DESC: control registers 0 11778 * RESETVAL: 0x0 (0) 11779 * ACCESS: R/W 11780 * FIELDS: 11781 * CTLE_ENB_NEGIMP 11782 * CTLE_ENB_NEGCAP 11783 */ 11784 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r (0x0001a102 | PHYMOD_REG_ACC_RAW) 11785 11786 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_SIZE 4 11787 11788 /* 11789 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL2. 11790 */ 11791 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_s { 11792 uint32_t v[1]; 11793 uint32_t ana_lane_0_quad_c_ctrl2[1]; 11794 uint32_t _ana_lane_0_quad_c_ctrl2; 11795 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_t; 11796 11797 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CLR(r) (r).ana_lane_0_quad_c_ctrl2[0] = 0 11798 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_SET(r,d) (r).ana_lane_0_quad_c_ctrl2[0] = d 11799 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_GET(r) (r).ana_lane_0_quad_c_ctrl2[0] 11800 11801 /* 11802 * These macros can be used to access individual fields. 11803 */ 11804 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_0_quad_c_ctrl2[0]) >> 8) & 0x7f) 11805 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_0_quad_c_ctrl2[0]=(((r).ana_lane_0_quad_c_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 11806 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_0_quad_c_ctrl2[0]) & 0x7f) 11807 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_0_quad_c_ctrl2[0]=(((r).ana_lane_0_quad_c_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 11808 11809 /* 11810 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL2. 11811 */ 11812 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r,_r._ana_lane_0_quad_c_ctrl2) 11813 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r,_r._ana_lane_0_quad_c_ctrl2) 11814 11815 /* 11816 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11817 * will be redefined without the chip prefix for easier programming. 11818 * If multiple chips will be programmed in the same source file, then you should 11819 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11820 * and refer to the fully qualified versions. 11821 */ 11822 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11823 11824 #define ANA_LANE_0_QUAD_C_CTRL2r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r 11825 #define ANA_LANE_0_QUAD_C_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_SIZE 11826 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_t ANA_LANE_0_QUAD_C_CTRL2r_t; 11827 #define ANA_LANE_0_QUAD_C_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CLR 11828 #define ANA_LANE_0_QUAD_C_CTRL2r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_SET 11829 #define ANA_LANE_0_QUAD_C_CTRL2r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_GET 11830 #define ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET 11831 #define ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET 11832 #define ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET 11833 #define ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET 11834 #define READ_ANA_LANE_0_QUAD_C_CTRL2r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL2r 11835 #define WRITE_ANA_LANE_0_QUAD_C_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL2r 11836 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL2r 11837 11838 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11839 /******************************************************************************* 11840 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL2r' 11841 */ 11842 11843 11844 11845 11846 /******************************************************************************* 11847 * CHIP: BCMI_HURACAN 11848 * REGISTER: ANA_LANE_0_QUAD_C_CTRL3 11849 * BLOCKS: ANA_LANE_0_QUAD_C 11850 * REGADDR: 0xa103 11851 * DEVAD: 1 11852 * DESC: control registers 0 11853 * RESETVAL: 0x0 (0) 11854 * ACCESS: R/W 11855 * FIELDS: 11856 * CTLE_EN_NEGRES 11857 * CTLE_EQSEL 11858 */ 11859 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r (0x0001a103 | PHYMOD_REG_ACC_RAW) 11860 11861 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_SIZE 4 11862 11863 /* 11864 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL3. 11865 */ 11866 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_s { 11867 uint32_t v[1]; 11868 uint32_t ana_lane_0_quad_c_ctrl3[1]; 11869 uint32_t _ana_lane_0_quad_c_ctrl3; 11870 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_t; 11871 11872 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CLR(r) (r).ana_lane_0_quad_c_ctrl3[0] = 0 11873 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_SET(r,d) (r).ana_lane_0_quad_c_ctrl3[0] = d 11874 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_GET(r) (r).ana_lane_0_quad_c_ctrl3[0] 11875 11876 /* 11877 * These macros can be used to access individual fields. 11878 */ 11879 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_0_quad_c_ctrl3[0]) >> 8) & 0xff) 11880 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_0_quad_c_ctrl3[0]=(((r).ana_lane_0_quad_c_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 11881 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_0_quad_c_ctrl3[0]) & 0x7f) 11882 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_0_quad_c_ctrl3[0]=(((r).ana_lane_0_quad_c_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 11883 11884 /* 11885 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL3. 11886 */ 11887 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r,_r._ana_lane_0_quad_c_ctrl3) 11888 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r,_r._ana_lane_0_quad_c_ctrl3) 11889 11890 /* 11891 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11892 * will be redefined without the chip prefix for easier programming. 11893 * If multiple chips will be programmed in the same source file, then you should 11894 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11895 * and refer to the fully qualified versions. 11896 */ 11897 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11898 11899 #define ANA_LANE_0_QUAD_C_CTRL3r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r 11900 #define ANA_LANE_0_QUAD_C_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_SIZE 11901 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_t ANA_LANE_0_QUAD_C_CTRL3r_t; 11902 #define ANA_LANE_0_QUAD_C_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CLR 11903 #define ANA_LANE_0_QUAD_C_CTRL3r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_SET 11904 #define ANA_LANE_0_QUAD_C_CTRL3r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_GET 11905 #define ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EQSELf_GET 11906 #define ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EQSELf_SET 11907 #define ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET 11908 #define ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET 11909 #define READ_ANA_LANE_0_QUAD_C_CTRL3r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL3r 11910 #define WRITE_ANA_LANE_0_QUAD_C_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL3r 11911 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL3r 11912 11913 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11914 /******************************************************************************* 11915 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL3r' 11916 */ 11917 11918 11919 11920 11921 /******************************************************************************* 11922 * CHIP: BCMI_HURACAN 11923 * REGISTER: ANA_LANE_0_QUAD_C_CTRL4 11924 * BLOCKS: ANA_LANE_0_QUAD_C 11925 * REGADDR: 0xa104 11926 * DEVAD: 1 11927 * DESC: control registers 0 11928 * RESETVAL: 0x0 (0) 11929 * ACCESS: R/W 11930 * FIELDS: 11931 * CTLE_LZEN 11932 * RXTX_RESERVED_FOR_59_52 11933 */ 11934 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r (0x0001a104 | PHYMOD_REG_ACC_RAW) 11935 11936 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_SIZE 4 11937 11938 /* 11939 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL4. 11940 */ 11941 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_s { 11942 uint32_t v[1]; 11943 uint32_t ana_lane_0_quad_c_ctrl4[1]; 11944 uint32_t _ana_lane_0_quad_c_ctrl4; 11945 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_t; 11946 11947 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_CLR(r) (r).ana_lane_0_quad_c_ctrl4[0] = 0 11948 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_SET(r,d) (r).ana_lane_0_quad_c_ctrl4[0] = d 11949 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_GET(r) (r).ana_lane_0_quad_c_ctrl4[0] 11950 11951 /* 11952 * These macros can be used to access individual fields. 11953 */ 11954 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_0_quad_c_ctrl4[0]) >> 4) & 0xff) 11955 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_0_quad_c_ctrl4[0]=(((r).ana_lane_0_quad_c_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 11956 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_0_quad_c_ctrl4[0]) & 0x1) 11957 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_0_quad_c_ctrl4[0]=(((r).ana_lane_0_quad_c_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 11958 11959 /* 11960 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL4. 11961 */ 11962 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r,_r._ana_lane_0_quad_c_ctrl4) 11963 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r,_r._ana_lane_0_quad_c_ctrl4) 11964 11965 /* 11966 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 11967 * will be redefined without the chip prefix for easier programming. 11968 * If multiple chips will be programmed in the same source file, then you should 11969 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 11970 * and refer to the fully qualified versions. 11971 */ 11972 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 11973 11974 #define ANA_LANE_0_QUAD_C_CTRL4r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r 11975 #define ANA_LANE_0_QUAD_C_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_SIZE 11976 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_t ANA_LANE_0_QUAD_C_CTRL4r_t; 11977 #define ANA_LANE_0_QUAD_C_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_CLR 11978 #define ANA_LANE_0_QUAD_C_CTRL4r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_SET 11979 #define ANA_LANE_0_QUAD_C_CTRL4r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_GET 11980 #define ANA_LANE_0_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 11981 #define ANA_LANE_0_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 11982 #define ANA_LANE_0_QUAD_C_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_CTLE_LZENf_GET 11983 #define ANA_LANE_0_QUAD_C_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r_CTLE_LZENf_SET 11984 #define READ_ANA_LANE_0_QUAD_C_CTRL4r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL4r 11985 #define WRITE_ANA_LANE_0_QUAD_C_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL4r 11986 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL4r 11987 11988 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 11989 /******************************************************************************* 11990 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL4r' 11991 */ 11992 11993 11994 11995 11996 /******************************************************************************* 11997 * CHIP: BCMI_HURACAN 11998 * REGISTER: ANA_LANE_0_QUAD_C_CTRL5 11999 * BLOCKS: ANA_LANE_0_QUAD_C 12000 * REGADDR: 0xa105 12001 * DEVAD: 1 12002 * DESC: control registers 0 12003 * RESETVAL: 0x0 (0) 12004 * ACCESS: R/W 12005 * FIELDS: 12006 * CTLE_LOPEAKING 12007 * CTLE_PD 12008 * LA_GCTRL 12009 */ 12010 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r (0x0001a105 | PHYMOD_REG_ACC_RAW) 12011 12012 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_SIZE 4 12013 12014 /* 12015 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL5. 12016 */ 12017 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_s { 12018 uint32_t v[1]; 12019 uint32_t ana_lane_0_quad_c_ctrl5[1]; 12020 uint32_t _ana_lane_0_quad_c_ctrl5; 12021 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_t; 12022 12023 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CLR(r) (r).ana_lane_0_quad_c_ctrl5[0] = 0 12024 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_SET(r,d) (r).ana_lane_0_quad_c_ctrl5[0] = d 12025 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_GET(r) (r).ana_lane_0_quad_c_ctrl5[0] 12026 12027 /* 12028 * These macros can be used to access individual fields. 12029 */ 12030 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_0_quad_c_ctrl5[0]) >> 4) & 0x3ff) 12031 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_0_quad_c_ctrl5[0]=(((r).ana_lane_0_quad_c_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 12032 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_0_quad_c_ctrl5[0]) >> 1) & 0x1) 12033 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_0_quad_c_ctrl5[0]=(((r).ana_lane_0_quad_c_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 12034 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_0_quad_c_ctrl5[0]) & 0x1) 12035 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_0_quad_c_ctrl5[0]=(((r).ana_lane_0_quad_c_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 12036 12037 /* 12038 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL5. 12039 */ 12040 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r,_r._ana_lane_0_quad_c_ctrl5) 12041 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r,_r._ana_lane_0_quad_c_ctrl5) 12042 12043 /* 12044 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12045 * will be redefined without the chip prefix for easier programming. 12046 * If multiple chips will be programmed in the same source file, then you should 12047 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12048 * and refer to the fully qualified versions. 12049 */ 12050 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12051 12052 #define ANA_LANE_0_QUAD_C_CTRL5r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r 12053 #define ANA_LANE_0_QUAD_C_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_SIZE 12054 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_t ANA_LANE_0_QUAD_C_CTRL5r_t; 12055 #define ANA_LANE_0_QUAD_C_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CLR 12056 #define ANA_LANE_0_QUAD_C_CTRL5r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_SET 12057 #define ANA_LANE_0_QUAD_C_CTRL5r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_GET 12058 #define ANA_LANE_0_QUAD_C_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_LA_GCTRLf_GET 12059 #define ANA_LANE_0_QUAD_C_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_LA_GCTRLf_SET 12060 #define ANA_LANE_0_QUAD_C_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_PDf_GET 12061 #define ANA_LANE_0_QUAD_C_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_PDf_SET 12062 #define ANA_LANE_0_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET 12063 #define ANA_LANE_0_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET 12064 #define READ_ANA_LANE_0_QUAD_C_CTRL5r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL5r 12065 #define WRITE_ANA_LANE_0_QUAD_C_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL5r 12066 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL5r 12067 12068 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12069 /******************************************************************************* 12070 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL5r' 12071 */ 12072 12073 12074 12075 12076 /******************************************************************************* 12077 * CHIP: BCMI_HURACAN 12078 * REGISTER: ANA_LANE_0_QUAD_C_CTRL6 12079 * BLOCKS: ANA_LANE_0_QUAD_C 12080 * REGADDR: 0xa106 12081 * DEVAD: 1 12082 * DESC: control registers 0 12083 * RESETVAL: 0x0 (0) 12084 * ACCESS: R/W 12085 * FIELDS: 12086 * LA_DEGAIN 12087 * LA_DETUNE 12088 */ 12089 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r (0x0001a106 | PHYMOD_REG_ACC_RAW) 12090 12091 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_SIZE 4 12092 12093 /* 12094 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL6. 12095 */ 12096 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_s { 12097 uint32_t v[1]; 12098 uint32_t ana_lane_0_quad_c_ctrl6[1]; 12099 uint32_t _ana_lane_0_quad_c_ctrl6; 12100 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_t; 12101 12102 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_CLR(r) (r).ana_lane_0_quad_c_ctrl6[0] = 0 12103 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_SET(r,d) (r).ana_lane_0_quad_c_ctrl6[0] = d 12104 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_GET(r) (r).ana_lane_0_quad_c_ctrl6[0] 12105 12106 /* 12107 * These macros can be used to access individual fields. 12108 */ 12109 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_0_quad_c_ctrl6[0]) >> 8) & 0xff) 12110 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_0_quad_c_ctrl6[0]=(((r).ana_lane_0_quad_c_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 12111 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_0_quad_c_ctrl6[0]) & 0x1f) 12112 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_0_quad_c_ctrl6[0]=(((r).ana_lane_0_quad_c_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 12113 12114 /* 12115 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL6. 12116 */ 12117 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r,_r._ana_lane_0_quad_c_ctrl6) 12118 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r,_r._ana_lane_0_quad_c_ctrl6) 12119 12120 /* 12121 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12122 * will be redefined without the chip prefix for easier programming. 12123 * If multiple chips will be programmed in the same source file, then you should 12124 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12125 * and refer to the fully qualified versions. 12126 */ 12127 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12128 12129 #define ANA_LANE_0_QUAD_C_CTRL6r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r 12130 #define ANA_LANE_0_QUAD_C_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_SIZE 12131 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_t ANA_LANE_0_QUAD_C_CTRL6r_t; 12132 #define ANA_LANE_0_QUAD_C_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_CLR 12133 #define ANA_LANE_0_QUAD_C_CTRL6r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_SET 12134 #define ANA_LANE_0_QUAD_C_CTRL6r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_GET 12135 #define ANA_LANE_0_QUAD_C_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DETUNEf_GET 12136 #define ANA_LANE_0_QUAD_C_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DETUNEf_SET 12137 #define ANA_LANE_0_QUAD_C_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DEGAINf_GET 12138 #define ANA_LANE_0_QUAD_C_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r_LA_DEGAINf_SET 12139 #define READ_ANA_LANE_0_QUAD_C_CTRL6r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL6r 12140 #define WRITE_ANA_LANE_0_QUAD_C_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL6r 12141 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL6r 12142 12143 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12144 /******************************************************************************* 12145 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL6r' 12146 */ 12147 12148 12149 12150 12151 /******************************************************************************* 12152 * CHIP: BCMI_HURACAN 12153 * REGISTER: ANA_LANE_0_QUAD_C_CTRL7 12154 * BLOCKS: ANA_LANE_0_QUAD_C 12155 * REGADDR: 0xa107 12156 * DEVAD: 1 12157 * DESC: control registers 0 12158 * RESETVAL: 0x0 (0) 12159 * ACCESS: R/W 12160 * FIELDS: 12161 * LA_LIN_MODE 12162 * RX_BIAS_FB_PDN 12163 */ 12164 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r (0x0001a107 | PHYMOD_REG_ACC_RAW) 12165 12166 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_SIZE 4 12167 12168 /* 12169 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL7. 12170 */ 12171 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_s { 12172 uint32_t v[1]; 12173 uint32_t ana_lane_0_quad_c_ctrl7[1]; 12174 uint32_t _ana_lane_0_quad_c_ctrl7; 12175 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_t; 12176 12177 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_CLR(r) (r).ana_lane_0_quad_c_ctrl7[0] = 0 12178 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_SET(r,d) (r).ana_lane_0_quad_c_ctrl7[0] = d 12179 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_GET(r) (r).ana_lane_0_quad_c_ctrl7[0] 12180 12181 /* 12182 * These macros can be used to access individual fields. 12183 */ 12184 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_0_quad_c_ctrl7[0]) >> 8) & 0x1) 12185 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_0_quad_c_ctrl7[0]=(((r).ana_lane_0_quad_c_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 12186 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_0_quad_c_ctrl7[0]) & 0x1f) 12187 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_0_quad_c_ctrl7[0]=(((r).ana_lane_0_quad_c_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 12188 12189 /* 12190 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL7. 12191 */ 12192 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r,_r._ana_lane_0_quad_c_ctrl7) 12193 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r,_r._ana_lane_0_quad_c_ctrl7) 12194 12195 /* 12196 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12197 * will be redefined without the chip prefix for easier programming. 12198 * If multiple chips will be programmed in the same source file, then you should 12199 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12200 * and refer to the fully qualified versions. 12201 */ 12202 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12203 12204 #define ANA_LANE_0_QUAD_C_CTRL7r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r 12205 #define ANA_LANE_0_QUAD_C_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_SIZE 12206 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_t ANA_LANE_0_QUAD_C_CTRL7r_t; 12207 #define ANA_LANE_0_QUAD_C_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_CLR 12208 #define ANA_LANE_0_QUAD_C_CTRL7r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_SET 12209 #define ANA_LANE_0_QUAD_C_CTRL7r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_GET 12210 #define ANA_LANE_0_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET 12211 #define ANA_LANE_0_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET 12212 #define ANA_LANE_0_QUAD_C_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_LA_LIN_MODEf_GET 12213 #define ANA_LANE_0_QUAD_C_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r_LA_LIN_MODEf_SET 12214 #define READ_ANA_LANE_0_QUAD_C_CTRL7r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL7r 12215 #define WRITE_ANA_LANE_0_QUAD_C_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL7r 12216 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL7r 12217 12218 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12219 /******************************************************************************* 12220 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL7r' 12221 */ 12222 12223 12224 12225 12226 /******************************************************************************* 12227 * CHIP: BCMI_HURACAN 12228 * REGISTER: ANA_LANE_0_QUAD_C_CTRL8 12229 * BLOCKS: ANA_LANE_0_QUAD_C 12230 * REGADDR: 0xa108 12231 * DEVAD: 1 12232 * DESC: control registers 0 12233 * RESETVAL: 0x0 (0) 12234 * ACCESS: R/W 12235 * FIELDS: 12236 * LA_PD 12237 * LA_PD_IDLE 12238 * RXTX_RESERVED_FOR_99_95 12239 */ 12240 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r (0x0001a108 | PHYMOD_REG_ACC_RAW) 12241 12242 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_SIZE 4 12243 12244 /* 12245 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL8. 12246 */ 12247 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_s { 12248 uint32_t v[1]; 12249 uint32_t ana_lane_0_quad_c_ctrl8[1]; 12250 uint32_t _ana_lane_0_quad_c_ctrl8; 12251 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_t; 12252 12253 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_CLR(r) (r).ana_lane_0_quad_c_ctrl8[0] = 0 12254 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_SET(r,d) (r).ana_lane_0_quad_c_ctrl8[0] = d 12255 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_GET(r) (r).ana_lane_0_quad_c_ctrl8[0] 12256 12257 /* 12258 * These macros can be used to access individual fields. 12259 */ 12260 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_0_quad_c_ctrl8[0]) >> 4) & 0x1f) 12261 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_0_quad_c_ctrl8[0]=(((r).ana_lane_0_quad_c_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 12262 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_0_quad_c_ctrl8[0]) >> 1) & 0x1) 12263 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_0_quad_c_ctrl8[0]=(((r).ana_lane_0_quad_c_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 12264 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_0_quad_c_ctrl8[0]) & 0x1) 12265 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_0_quad_c_ctrl8[0]=(((r).ana_lane_0_quad_c_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 12266 12267 /* 12268 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL8. 12269 */ 12270 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r,_r._ana_lane_0_quad_c_ctrl8) 12271 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r,_r._ana_lane_0_quad_c_ctrl8) 12272 12273 /* 12274 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12275 * will be redefined without the chip prefix for easier programming. 12276 * If multiple chips will be programmed in the same source file, then you should 12277 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12278 * and refer to the fully qualified versions. 12279 */ 12280 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12281 12282 #define ANA_LANE_0_QUAD_C_CTRL8r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r 12283 #define ANA_LANE_0_QUAD_C_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_SIZE 12284 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_t ANA_LANE_0_QUAD_C_CTRL8r_t; 12285 #define ANA_LANE_0_QUAD_C_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_CLR 12286 #define ANA_LANE_0_QUAD_C_CTRL8r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_SET 12287 #define ANA_LANE_0_QUAD_C_CTRL8r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_GET 12288 #define ANA_LANE_0_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 12289 #define ANA_LANE_0_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 12290 #define ANA_LANE_0_QUAD_C_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PD_IDLEf_GET 12291 #define ANA_LANE_0_QUAD_C_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PD_IDLEf_SET 12292 #define ANA_LANE_0_QUAD_C_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PDf_GET 12293 #define ANA_LANE_0_QUAD_C_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r_LA_PDf_SET 12294 #define READ_ANA_LANE_0_QUAD_C_CTRL8r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL8r 12295 #define WRITE_ANA_LANE_0_QUAD_C_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL8r 12296 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL8r 12297 12298 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12299 /******************************************************************************* 12300 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL8r' 12301 */ 12302 12303 12304 12305 12306 /******************************************************************************* 12307 * CHIP: BCMI_HURACAN 12308 * REGISTER: ANA_LANE_0_QUAD_C_CTRL9 12309 * BLOCKS: ANA_LANE_0_QUAD_C 12310 * REGADDR: 0xa109 12311 * DEVAD: 1 12312 * DESC: control registers 0 12313 * RESETVAL: 0x0 (0) 12314 * ACCESS: R/W 12315 * FIELDS: 12316 * DRV_POST1 12317 * DLINE_SWING_1 12318 * DLINE_SWING_2 12319 * DLINE_DELAY_CTRL 12320 */ 12321 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r (0x0001a109 | PHYMOD_REG_ACC_RAW) 12322 12323 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_SIZE 4 12324 12325 /* 12326 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL9. 12327 */ 12328 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_s { 12329 uint32_t v[1]; 12330 uint32_t ana_lane_0_quad_c_ctrl9[1]; 12331 uint32_t _ana_lane_0_quad_c_ctrl9; 12332 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_t; 12333 12334 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_CLR(r) (r).ana_lane_0_quad_c_ctrl9[0] = 0 12335 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_SET(r,d) (r).ana_lane_0_quad_c_ctrl9[0] = d 12336 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_GET(r) (r).ana_lane_0_quad_c_ctrl9[0] 12337 12338 /* 12339 * These macros can be used to access individual fields. 12340 */ 12341 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_0_quad_c_ctrl9[0]) >> 12) & 0x7) 12342 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_0_quad_c_ctrl9[0]=(((r).ana_lane_0_quad_c_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 12343 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_0_quad_c_ctrl9[0]) >> 8) & 0x3) 12344 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_0_quad_c_ctrl9[0]=(((r).ana_lane_0_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 12345 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_0_quad_c_ctrl9[0]) >> 4) & 0x3) 12346 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_0_quad_c_ctrl9[0]=(((r).ana_lane_0_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 12347 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_0_quad_c_ctrl9[0]) & 0xf) 12348 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_0_quad_c_ctrl9[0]=(((r).ana_lane_0_quad_c_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 12349 12350 /* 12351 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL9. 12352 */ 12353 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r,_r._ana_lane_0_quad_c_ctrl9) 12354 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r,_r._ana_lane_0_quad_c_ctrl9) 12355 12356 /* 12357 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12358 * will be redefined without the chip prefix for easier programming. 12359 * If multiple chips will be programmed in the same source file, then you should 12360 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12361 * and refer to the fully qualified versions. 12362 */ 12363 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12364 12365 #define ANA_LANE_0_QUAD_C_CTRL9r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r 12366 #define ANA_LANE_0_QUAD_C_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_SIZE 12367 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_t ANA_LANE_0_QUAD_C_CTRL9r_t; 12368 #define ANA_LANE_0_QUAD_C_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_CLR 12369 #define ANA_LANE_0_QUAD_C_CTRL9r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_SET 12370 #define ANA_LANE_0_QUAD_C_CTRL9r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_GET 12371 #define ANA_LANE_0_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET 12372 #define ANA_LANE_0_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET 12373 #define ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_2f_GET 12374 #define ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_2f_SET 12375 #define ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_1f_GET 12376 #define ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DLINE_SWING_1f_SET 12377 #define ANA_LANE_0_QUAD_C_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DRV_POST1f_GET 12378 #define ANA_LANE_0_QUAD_C_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r_DRV_POST1f_SET 12379 #define READ_ANA_LANE_0_QUAD_C_CTRL9r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL9r 12380 #define WRITE_ANA_LANE_0_QUAD_C_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL9r 12381 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL9r 12382 12383 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12384 /******************************************************************************* 12385 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL9r' 12386 */ 12387 12388 12389 12390 12391 /******************************************************************************* 12392 * CHIP: BCMI_HURACAN 12393 * REGISTER: ANA_LANE_0_QUAD_C_CTRL10 12394 * BLOCKS: ANA_LANE_0_QUAD_C 12395 * REGADDR: 0xa10a 12396 * DEVAD: 1 12397 * DESC: control registers 0 12398 * RESETVAL: 0x0 (0) 12399 * ACCESS: R/W 12400 * FIELDS: 12401 * DRV_PWD 12402 * DLINE_PWD 12403 * DRV_VBSEL 12404 * DRV_MAIN 12405 * DRV_MAIN_PU 12406 */ 12407 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r (0x0001a10a | PHYMOD_REG_ACC_RAW) 12408 12409 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_SIZE 4 12410 12411 /* 12412 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL10. 12413 */ 12414 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_s { 12415 uint32_t v[1]; 12416 uint32_t ana_lane_0_quad_c_ctrl10[1]; 12417 uint32_t _ana_lane_0_quad_c_ctrl10; 12418 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_t; 12419 12420 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_CLR(r) (r).ana_lane_0_quad_c_ctrl10[0] = 0 12421 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_SET(r,d) (r).ana_lane_0_quad_c_ctrl10[0] = d 12422 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_GET(r) (r).ana_lane_0_quad_c_ctrl10[0] 12423 12424 /* 12425 * These macros can be used to access individual fields. 12426 */ 12427 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_0_quad_c_ctrl10[0]) >> 12) & 0xf) 12428 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_0_quad_c_ctrl10[0]=(((r).ana_lane_0_quad_c_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 12429 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_0_quad_c_ctrl10[0]) >> 4) & 0x3f) 12430 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_0_quad_c_ctrl10[0]=(((r).ana_lane_0_quad_c_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 12431 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_0_quad_c_ctrl10[0]) >> 2) & 0x1) 12432 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_0_quad_c_ctrl10[0]=(((r).ana_lane_0_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 12433 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_0_quad_c_ctrl10[0]) >> 1) & 0x1) 12434 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_0_quad_c_ctrl10[0]=(((r).ana_lane_0_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 12435 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_0_quad_c_ctrl10[0]) & 0x1) 12436 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_0_quad_c_ctrl10[0]=(((r).ana_lane_0_quad_c_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 12437 12438 /* 12439 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL10. 12440 */ 12441 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r,_r._ana_lane_0_quad_c_ctrl10) 12442 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r,_r._ana_lane_0_quad_c_ctrl10) 12443 12444 /* 12445 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12446 * will be redefined without the chip prefix for easier programming. 12447 * If multiple chips will be programmed in the same source file, then you should 12448 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12449 * and refer to the fully qualified versions. 12450 */ 12451 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12452 12453 #define ANA_LANE_0_QUAD_C_CTRL10r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r 12454 #define ANA_LANE_0_QUAD_C_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_SIZE 12455 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_t ANA_LANE_0_QUAD_C_CTRL10r_t; 12456 #define ANA_LANE_0_QUAD_C_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_CLR 12457 #define ANA_LANE_0_QUAD_C_CTRL10r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_SET 12458 #define ANA_LANE_0_QUAD_C_CTRL10r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_GET 12459 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET 12460 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET 12461 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAINf_GET 12462 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_MAINf_SET 12463 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_VBSELf_GET 12464 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_VBSELf_SET 12465 #define ANA_LANE_0_QUAD_C_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DLINE_PWDf_GET 12466 #define ANA_LANE_0_QUAD_C_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DLINE_PWDf_SET 12467 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_PWDf_GET 12468 #define ANA_LANE_0_QUAD_C_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r_DRV_PWDf_SET 12469 #define READ_ANA_LANE_0_QUAD_C_CTRL10r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL10r 12470 #define WRITE_ANA_LANE_0_QUAD_C_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL10r 12471 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL10r 12472 12473 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12474 /******************************************************************************* 12475 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL10r' 12476 */ 12477 12478 12479 12480 12481 /******************************************************************************* 12482 * CHIP: BCMI_HURACAN 12483 * REGISTER: ANA_LANE_0_QUAD_C_CTRL11 12484 * BLOCKS: ANA_LANE_0_QUAD_C 12485 * REGADDR: 0xa10b 12486 * DEVAD: 1 12487 * DESC: control registers 0 12488 * RESETVAL: 0x0 (0) 12489 * ACCESS: R/W 12490 * FIELDS: 12491 * RXTX_RESERVED_FOR_143_128 12492 */ 12493 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r (0x0001a10b | PHYMOD_REG_ACC_RAW) 12494 12495 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_SIZE 4 12496 12497 /* 12498 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL11. 12499 */ 12500 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_s { 12501 uint32_t v[1]; 12502 uint32_t ana_lane_0_quad_c_ctrl11[1]; 12503 uint32_t _ana_lane_0_quad_c_ctrl11; 12504 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_t; 12505 12506 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_CLR(r) (r).ana_lane_0_quad_c_ctrl11[0] = 0 12507 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_SET(r,d) (r).ana_lane_0_quad_c_ctrl11[0] = d 12508 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_GET(r) (r).ana_lane_0_quad_c_ctrl11[0] 12509 12510 /* 12511 * These macros can be used to access individual fields. 12512 */ 12513 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_0_quad_c_ctrl11[0]) & 0xffff) 12514 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_0_quad_c_ctrl11[0]=(((r).ana_lane_0_quad_c_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 12515 12516 /* 12517 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL11. 12518 */ 12519 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r,_r._ana_lane_0_quad_c_ctrl11) 12520 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r,_r._ana_lane_0_quad_c_ctrl11) 12521 12522 /* 12523 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12524 * will be redefined without the chip prefix for easier programming. 12525 * If multiple chips will be programmed in the same source file, then you should 12526 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12527 * and refer to the fully qualified versions. 12528 */ 12529 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12530 12531 #define ANA_LANE_0_QUAD_C_CTRL11r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r 12532 #define ANA_LANE_0_QUAD_C_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_SIZE 12533 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_t ANA_LANE_0_QUAD_C_CTRL11r_t; 12534 #define ANA_LANE_0_QUAD_C_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_CLR 12535 #define ANA_LANE_0_QUAD_C_CTRL11r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_SET 12536 #define ANA_LANE_0_QUAD_C_CTRL11r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_GET 12537 #define ANA_LANE_0_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 12538 #define ANA_LANE_0_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 12539 #define READ_ANA_LANE_0_QUAD_C_CTRL11r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL11r 12540 #define WRITE_ANA_LANE_0_QUAD_C_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL11r 12541 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL11r 12542 12543 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12544 /******************************************************************************* 12545 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL11r' 12546 */ 12547 12548 12549 12550 12551 /******************************************************************************* 12552 * CHIP: BCMI_HURACAN 12553 * REGISTER: ANA_LANE_0_QUAD_C_CTRL12 12554 * BLOCKS: ANA_LANE_0_QUAD_C 12555 * REGADDR: 0xa10c 12556 * DEVAD: 1 12557 * DESC: control registers 0 12558 * RESETVAL: 0x0 (0) 12559 * ACCESS: R/W 12560 * FIELDS: 12561 * LA_RESCAL_FRC_VAL 12562 * LA_RESCAL_FRC 12563 * DRV_RESCAL_FRC_VAL 12564 * DRV_RESCAL_FRC 12565 */ 12566 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r (0x0001a10c | PHYMOD_REG_ACC_RAW) 12567 12568 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_SIZE 4 12569 12570 /* 12571 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL12. 12572 */ 12573 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_s { 12574 uint32_t v[1]; 12575 uint32_t ana_lane_0_quad_c_ctrl12[1]; 12576 uint32_t _ana_lane_0_quad_c_ctrl12; 12577 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_t; 12578 12579 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_CLR(r) (r).ana_lane_0_quad_c_ctrl12[0] = 0 12580 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_SET(r,d) (r).ana_lane_0_quad_c_ctrl12[0] = d 12581 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_GET(r) (r).ana_lane_0_quad_c_ctrl12[0] 12582 12583 /* 12584 * These macros can be used to access individual fields. 12585 */ 12586 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_c_ctrl12[0]) >> 12) & 0x1) 12587 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_c_ctrl12[0]=(((r).ana_lane_0_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 12588 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_c_ctrl12[0]) >> 8) & 0xf) 12589 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_c_ctrl12[0]=(((r).ana_lane_0_quad_c_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 12590 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_c_ctrl12[0]) >> 4) & 0x1) 12591 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_c_ctrl12[0]=(((r).ana_lane_0_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 12592 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_c_ctrl12[0]) & 0xf) 12593 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_c_ctrl12[0]=(((r).ana_lane_0_quad_c_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 12594 12595 /* 12596 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL12. 12597 */ 12598 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r,_r._ana_lane_0_quad_c_ctrl12) 12599 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r,_r._ana_lane_0_quad_c_ctrl12) 12600 12601 /* 12602 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12603 * will be redefined without the chip prefix for easier programming. 12604 * If multiple chips will be programmed in the same source file, then you should 12605 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12606 * and refer to the fully qualified versions. 12607 */ 12608 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12609 12610 #define ANA_LANE_0_QUAD_C_CTRL12r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r 12611 #define ANA_LANE_0_QUAD_C_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_SIZE 12612 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_t ANA_LANE_0_QUAD_C_CTRL12r_t; 12613 #define ANA_LANE_0_QUAD_C_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_CLR 12614 #define ANA_LANE_0_QUAD_C_CTRL12r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_SET 12615 #define ANA_LANE_0_QUAD_C_CTRL12r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_GET 12616 #define ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET 12617 #define ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET 12618 #define ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET 12619 #define ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET 12620 #define ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET 12621 #define ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET 12622 #define ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET 12623 #define ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET 12624 #define READ_ANA_LANE_0_QUAD_C_CTRL12r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL12r 12625 #define WRITE_ANA_LANE_0_QUAD_C_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL12r 12626 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL12r 12627 12628 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12629 /******************************************************************************* 12630 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL12r' 12631 */ 12632 12633 12634 12635 12636 /******************************************************************************* 12637 * CHIP: BCMI_HURACAN 12638 * REGISTER: ANA_LANE_0_QUAD_C_CTRL13 12639 * BLOCKS: ANA_LANE_0_QUAD_C 12640 * REGADDR: 0xa10d 12641 * DEVAD: 1 12642 * DESC: control registers 0 12643 * RESETVAL: 0x0 (0) 12644 * ACCESS: R/W 12645 * FIELDS: 12646 * CTLE_RESCAL_FRC_VAL 12647 * CTLE_RESCAL_FRC 12648 */ 12649 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r (0x0001a10d | PHYMOD_REG_ACC_RAW) 12650 12651 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_SIZE 4 12652 12653 /* 12654 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL13. 12655 */ 12656 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_s { 12657 uint32_t v[1]; 12658 uint32_t ana_lane_0_quad_c_ctrl13[1]; 12659 uint32_t _ana_lane_0_quad_c_ctrl13; 12660 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_t; 12661 12662 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CLR(r) (r).ana_lane_0_quad_c_ctrl13[0] = 0 12663 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_SET(r,d) (r).ana_lane_0_quad_c_ctrl13[0] = d 12664 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_GET(r) (r).ana_lane_0_quad_c_ctrl13[0] 12665 12666 /* 12667 * These macros can be used to access individual fields. 12668 */ 12669 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_c_ctrl13[0]) >> 4) & 0x1) 12670 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_c_ctrl13[0]=(((r).ana_lane_0_quad_c_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 12671 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_c_ctrl13[0]) & 0xf) 12672 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_c_ctrl13[0]=(((r).ana_lane_0_quad_c_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 12673 12674 /* 12675 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL13. 12676 */ 12677 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r,_r._ana_lane_0_quad_c_ctrl13) 12678 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r,_r._ana_lane_0_quad_c_ctrl13) 12679 12680 /* 12681 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12682 * will be redefined without the chip prefix for easier programming. 12683 * If multiple chips will be programmed in the same source file, then you should 12684 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12685 * and refer to the fully qualified versions. 12686 */ 12687 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12688 12689 #define ANA_LANE_0_QUAD_C_CTRL13r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r 12690 #define ANA_LANE_0_QUAD_C_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_SIZE 12691 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_t ANA_LANE_0_QUAD_C_CTRL13r_t; 12692 #define ANA_LANE_0_QUAD_C_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CLR 12693 #define ANA_LANE_0_QUAD_C_CTRL13r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_SET 12694 #define ANA_LANE_0_QUAD_C_CTRL13r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_GET 12695 #define ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET 12696 #define ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET 12697 #define ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 12698 #define ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 12699 #define READ_ANA_LANE_0_QUAD_C_CTRL13r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL13r 12700 #define WRITE_ANA_LANE_0_QUAD_C_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL13r 12701 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL13r 12702 12703 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12704 /******************************************************************************* 12705 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL13r' 12706 */ 12707 12708 12709 12710 12711 /******************************************************************************* 12712 * CHIP: BCMI_HURACAN 12713 * REGISTER: ANA_LANE_0_QUAD_C_CTRL14 12714 * BLOCKS: ANA_LANE_0_QUAD_C 12715 * REGADDR: 0xa10e 12716 * DEVAD: 1 12717 * DESC: control registers 0 12718 * RESETVAL: 0x0 (0) 12719 * ACCESS: R/W 12720 * FIELDS: 12721 * TX_IDLE_FRC_VAL 12722 * TX_IDLE_FRC 12723 * RXSD_IDLE_OVRD 12724 */ 12725 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r (0x0001a10e | PHYMOD_REG_ACC_RAW) 12726 12727 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_SIZE 4 12728 12729 /* 12730 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL14. 12731 */ 12732 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_s { 12733 uint32_t v[1]; 12734 uint32_t ana_lane_0_quad_c_ctrl14[1]; 12735 uint32_t _ana_lane_0_quad_c_ctrl14; 12736 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_t; 12737 12738 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_CLR(r) (r).ana_lane_0_quad_c_ctrl14[0] = 0 12739 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_SET(r,d) (r).ana_lane_0_quad_c_ctrl14[0] = d 12740 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_GET(r) (r).ana_lane_0_quad_c_ctrl14[0] 12741 12742 /* 12743 * These macros can be used to access individual fields. 12744 */ 12745 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_0_quad_c_ctrl14[0]) >> 4) & 0x1) 12746 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_0_quad_c_ctrl14[0]=(((r).ana_lane_0_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 12747 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_0_quad_c_ctrl14[0]) >> 1) & 0x1) 12748 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_0_quad_c_ctrl14[0]=(((r).ana_lane_0_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 12749 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_0_quad_c_ctrl14[0]) & 0x1) 12750 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_c_ctrl14[0]=(((r).ana_lane_0_quad_c_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 12751 12752 /* 12753 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL14. 12754 */ 12755 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r,_r._ana_lane_0_quad_c_ctrl14) 12756 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r,_r._ana_lane_0_quad_c_ctrl14) 12757 12758 /* 12759 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12760 * will be redefined without the chip prefix for easier programming. 12761 * If multiple chips will be programmed in the same source file, then you should 12762 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12763 * and refer to the fully qualified versions. 12764 */ 12765 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12766 12767 #define ANA_LANE_0_QUAD_C_CTRL14r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r 12768 #define ANA_LANE_0_QUAD_C_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_SIZE 12769 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_t ANA_LANE_0_QUAD_C_CTRL14r_t; 12770 #define ANA_LANE_0_QUAD_C_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_CLR 12771 #define ANA_LANE_0_QUAD_C_CTRL14r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_SET 12772 #define ANA_LANE_0_QUAD_C_CTRL14r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_GET 12773 #define ANA_LANE_0_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET 12774 #define ANA_LANE_0_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET 12775 #define ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET 12776 #define ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET 12777 #define ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET 12778 #define ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET 12779 #define READ_ANA_LANE_0_QUAD_C_CTRL14r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL14r 12780 #define WRITE_ANA_LANE_0_QUAD_C_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL14r 12781 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL14r 12782 12783 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12784 /******************************************************************************* 12785 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL14r' 12786 */ 12787 12788 12789 12790 12791 /******************************************************************************* 12792 * CHIP: BCMI_HURACAN 12793 * REGISTER: ANA_LANE_0_QUAD_C_CTRL15 12794 * BLOCKS: ANA_LANE_0_QUAD_C 12795 * REGADDR: 0xa10f 12796 * DEVAD: 1 12797 * DESC: sigdet filter settings 0 12798 * RESETVAL: 0x0 (0) 12799 * ACCESS: R/W 12800 * FIELDS: 12801 * SIGDET_DIS 12802 * SIGDET_1US_EN 12803 * SIGDET_FRC_VAL 12804 * SIGDET_FRC 12805 * HOLD_LOS_COUNT 12806 * HOLD_SD_COUNT 12807 */ 12808 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r (0x0001a10f | PHYMOD_REG_ACC_RAW) 12809 12810 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIZE 4 12811 12812 /* 12813 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL15. 12814 */ 12815 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_s { 12816 uint32_t v[1]; 12817 uint32_t ana_lane_0_quad_c_ctrl15[1]; 12818 uint32_t _ana_lane_0_quad_c_ctrl15; 12819 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_t; 12820 12821 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_CLR(r) (r).ana_lane_0_quad_c_ctrl15[0] = 0 12822 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SET(r,d) (r).ana_lane_0_quad_c_ctrl15[0] = d 12823 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_GET(r) (r).ana_lane_0_quad_c_ctrl15[0] 12824 12825 /* 12826 * These macros can be used to access individual fields. 12827 */ 12828 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_c_ctrl15[0]) >> 8) & 0x7) 12829 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_c_ctrl15[0]=(((r).ana_lane_0_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 12830 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_0_quad_c_ctrl15[0]) >> 4) & 0x7) 12831 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_c_ctrl15[0]=(((r).ana_lane_0_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 12832 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_0_quad_c_ctrl15[0]) >> 3) & 0x1) 12833 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_0_quad_c_ctrl15[0]=(((r).ana_lane_0_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 12834 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_c_ctrl15[0]) >> 2) & 0x1) 12835 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_c_ctrl15[0]=(((r).ana_lane_0_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 12836 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_0_quad_c_ctrl15[0]) >> 1) & 0x1) 12837 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_0_quad_c_ctrl15[0]=(((r).ana_lane_0_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 12838 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_0_quad_c_ctrl15[0]) & 0x1) 12839 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_0_quad_c_ctrl15[0]=(((r).ana_lane_0_quad_c_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 12840 12841 /* 12842 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL15. 12843 */ 12844 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r,_r._ana_lane_0_quad_c_ctrl15) 12845 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r,_r._ana_lane_0_quad_c_ctrl15) 12846 12847 /* 12848 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12849 * will be redefined without the chip prefix for easier programming. 12850 * If multiple chips will be programmed in the same source file, then you should 12851 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12852 * and refer to the fully qualified versions. 12853 */ 12854 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12855 12856 #define ANA_LANE_0_QUAD_C_CTRL15r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r 12857 #define ANA_LANE_0_QUAD_C_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIZE 12858 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_t ANA_LANE_0_QUAD_C_CTRL15r_t; 12859 #define ANA_LANE_0_QUAD_C_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_CLR 12860 #define ANA_LANE_0_QUAD_C_CTRL15r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SET 12861 #define ANA_LANE_0_QUAD_C_CTRL15r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_GET 12862 #define ANA_LANE_0_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET 12863 #define ANA_LANE_0_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET 12864 #define ANA_LANE_0_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET 12865 #define ANA_LANE_0_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET 12866 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRCf_GET 12867 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRCf_SET 12868 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET 12869 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET 12870 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET 12871 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET 12872 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_DISf_GET 12873 #define ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r_SIGDET_DISf_SET 12874 #define READ_ANA_LANE_0_QUAD_C_CTRL15r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL15r 12875 #define WRITE_ANA_LANE_0_QUAD_C_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL15r 12876 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL15r 12877 12878 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12879 /******************************************************************************* 12880 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL15r' 12881 */ 12882 12883 12884 12885 12886 /******************************************************************************* 12887 * CHIP: BCMI_HURACAN 12888 * REGISTER: ANA_LANE_0_QUAD_C_CTRL16 12889 * BLOCKS: ANA_LANE_0_QUAD_C 12890 * REGADDR: 0xa110 12891 * DEVAD: 1 12892 * DESC: sigdet filter settings 1 12893 * RESETVAL: 0x0 (0) 12894 * ACCESS: R/W 12895 * FIELDS: 12896 * LOS_COUNT 12897 * SD_COUNT 12898 */ 12899 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r (0x0001a110 | PHYMOD_REG_ACC_RAW) 12900 12901 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SIZE 4 12902 12903 /* 12904 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_CTRL16. 12905 */ 12906 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_s { 12907 uint32_t v[1]; 12908 uint32_t ana_lane_0_quad_c_ctrl16[1]; 12909 uint32_t _ana_lane_0_quad_c_ctrl16; 12910 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_t; 12911 12912 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_CLR(r) (r).ana_lane_0_quad_c_ctrl16[0] = 0 12913 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SET(r,d) (r).ana_lane_0_quad_c_ctrl16[0] = d 12914 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_GET(r) (r).ana_lane_0_quad_c_ctrl16[0] 12915 12916 /* 12917 * These macros can be used to access individual fields. 12918 */ 12919 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_c_ctrl16[0]) >> 8) & 0x1f) 12920 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_c_ctrl16[0]=(((r).ana_lane_0_quad_c_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 12921 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_0_quad_c_ctrl16[0]) & 0x1f) 12922 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_c_ctrl16[0]=(((r).ana_lane_0_quad_c_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 12923 12924 /* 12925 * These macros can be used to access ANA_LANE_0_QUAD_C_CTRL16. 12926 */ 12927 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r,_r._ana_lane_0_quad_c_ctrl16) 12928 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r,_r._ana_lane_0_quad_c_ctrl16) 12929 12930 /* 12931 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 12932 * will be redefined without the chip prefix for easier programming. 12933 * If multiple chips will be programmed in the same source file, then you should 12934 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 12935 * and refer to the fully qualified versions. 12936 */ 12937 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 12938 12939 #define ANA_LANE_0_QUAD_C_CTRL16r BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r 12940 #define ANA_LANE_0_QUAD_C_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SIZE 12941 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_t ANA_LANE_0_QUAD_C_CTRL16r_t; 12942 #define ANA_LANE_0_QUAD_C_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_CLR 12943 #define ANA_LANE_0_QUAD_C_CTRL16r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SET 12944 #define ANA_LANE_0_QUAD_C_CTRL16r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_GET 12945 #define ANA_LANE_0_QUAD_C_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SD_COUNTf_GET 12946 #define ANA_LANE_0_QUAD_C_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_SD_COUNTf_SET 12947 #define ANA_LANE_0_QUAD_C_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_LOS_COUNTf_GET 12948 #define ANA_LANE_0_QUAD_C_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r_LOS_COUNTf_SET 12949 #define READ_ANA_LANE_0_QUAD_C_CTRL16r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_CTRL16r 12950 #define WRITE_ANA_LANE_0_QUAD_C_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_CTRL16r 12951 #define MODIFY_ANA_LANE_0_QUAD_C_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_CTRL16r 12952 12953 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 12954 /******************************************************************************* 12955 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_CTRL16r' 12956 */ 12957 12958 12959 12960 12961 /******************************************************************************* 12962 * CHIP: BCMI_HURACAN 12963 * REGISTER: ANA_LANE_0_QUAD_C_STATUS0 12964 * BLOCKS: ANA_LANE_0_QUAD_C 12965 * REGADDR: 0xa120 12966 * DEVAD: 1 12967 * DESC: status registers 0 12968 * RESETVAL: 0x0 (0) 12969 * ACCESS: R/W 12970 * FIELDS: 12971 * O_RX_SIGDET 12972 * DG_RX_SIGDET 12973 */ 12974 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r (0x0001a120 | PHYMOD_REG_ACC_RAW) 12975 12976 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_SIZE 4 12977 12978 /* 12979 * This structure should be used to declare and program ANA_LANE_0_QUAD_C_STATUS0. 12980 */ 12981 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_s { 12982 uint32_t v[1]; 12983 uint32_t ana_lane_0_quad_c_status0[1]; 12984 uint32_t _ana_lane_0_quad_c_status0; 12985 } BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_t; 12986 12987 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_CLR(r) (r).ana_lane_0_quad_c_status0[0] = 0 12988 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_SET(r,d) (r).ana_lane_0_quad_c_status0[0] = d 12989 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_GET(r) (r).ana_lane_0_quad_c_status0[0] 12990 12991 /* 12992 * These macros can be used to access individual fields. 12993 */ 12994 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_0_quad_c_status0[0]) >> 1) & 0x1) 12995 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_c_status0[0]=(((r).ana_lane_0_quad_c_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 12996 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_0_quad_c_status0[0]) & 0x1) 12997 #define BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_c_status0[0]=(((r).ana_lane_0_quad_c_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 12998 12999 /* 13000 * These macros can be used to access ANA_LANE_0_QUAD_C_STATUS0. 13001 */ 13002 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r,_r._ana_lane_0_quad_c_status0) 13003 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r,_r._ana_lane_0_quad_c_status0) 13004 13005 /* 13006 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13007 * will be redefined without the chip prefix for easier programming. 13008 * If multiple chips will be programmed in the same source file, then you should 13009 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13010 * and refer to the fully qualified versions. 13011 */ 13012 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13013 13014 #define ANA_LANE_0_QUAD_C_STATUS0r BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r 13015 #define ANA_LANE_0_QUAD_C_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_SIZE 13016 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_t ANA_LANE_0_QUAD_C_STATUS0r_t; 13017 #define ANA_LANE_0_QUAD_C_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_CLR 13018 #define ANA_LANE_0_QUAD_C_STATUS0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_SET 13019 #define ANA_LANE_0_QUAD_C_STATUS0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_GET 13020 #define ANA_LANE_0_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET 13021 #define ANA_LANE_0_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET 13022 #define ANA_LANE_0_QUAD_C_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_O_RX_SIGDETf_GET 13023 #define ANA_LANE_0_QUAD_C_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r_O_RX_SIGDETf_SET 13024 #define READ_ANA_LANE_0_QUAD_C_STATUS0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_C_STATUS0r 13025 #define WRITE_ANA_LANE_0_QUAD_C_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_C_STATUS0r 13026 #define MODIFY_ANA_LANE_0_QUAD_C_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_C_STATUS0r 13027 13028 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13029 /******************************************************************************* 13030 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_C_STATUS0r' 13031 */ 13032 13033 13034 13035 13036 /******************************************************************************* 13037 * CHIP: BCMI_HURACAN 13038 * REGISTER: ANA_LANE_1_QUAD_C_CTRL0 13039 * BLOCKS: ANA_LANE_1_QUAD_C 13040 * REGADDR: 0xa200 13041 * DEVAD: 1 13042 * DESC: control registers 0 13043 * RESETVAL: 0x0 (0) 13044 * ACCESS: R/W 13045 * FIELDS: 13046 * RXTX_PWRDN 13047 * RX_SIGDET_BYPASS 13048 * RX_SIGDET_PWRDN 13049 * RX_SIGDECT_12GMODE 13050 * DC_COUPLE 13051 */ 13052 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r (0x0001a200 | PHYMOD_REG_ACC_RAW) 13053 13054 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_SIZE 4 13055 13056 /* 13057 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL0. 13058 */ 13059 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_s { 13060 uint32_t v[1]; 13061 uint32_t ana_lane_1_quad_c_ctrl0[1]; 13062 uint32_t _ana_lane_1_quad_c_ctrl0; 13063 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_t; 13064 13065 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_CLR(r) (r).ana_lane_1_quad_c_ctrl0[0] = 0 13066 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_SET(r,d) (r).ana_lane_1_quad_c_ctrl0[0] = d 13067 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_GET(r) (r).ana_lane_1_quad_c_ctrl0[0] 13068 13069 /* 13070 * These macros can be used to access individual fields. 13071 */ 13072 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_1_quad_c_ctrl0[0]) >> 4) & 0x1) 13073 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_1_quad_c_ctrl0[0]=(((r).ana_lane_1_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 13074 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_1_quad_c_ctrl0[0]) >> 3) & 0x1) 13075 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_1_quad_c_ctrl0[0]=(((r).ana_lane_1_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 13076 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_1_quad_c_ctrl0[0]) >> 2) & 0x1) 13077 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_1_quad_c_ctrl0[0]=(((r).ana_lane_1_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 13078 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_1_quad_c_ctrl0[0]) >> 1) & 0x1) 13079 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_1_quad_c_ctrl0[0]=(((r).ana_lane_1_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 13080 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_1_quad_c_ctrl0[0]) & 0x1) 13081 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_1_quad_c_ctrl0[0]=(((r).ana_lane_1_quad_c_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 13082 13083 /* 13084 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL0. 13085 */ 13086 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r,_r._ana_lane_1_quad_c_ctrl0) 13087 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r,_r._ana_lane_1_quad_c_ctrl0) 13088 13089 /* 13090 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13091 * will be redefined without the chip prefix for easier programming. 13092 * If multiple chips will be programmed in the same source file, then you should 13093 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13094 * and refer to the fully qualified versions. 13095 */ 13096 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13097 13098 #define ANA_LANE_1_QUAD_C_CTRL0r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r 13099 #define ANA_LANE_1_QUAD_C_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_SIZE 13100 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_t ANA_LANE_1_QUAD_C_CTRL0r_t; 13101 #define ANA_LANE_1_QUAD_C_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_CLR 13102 #define ANA_LANE_1_QUAD_C_CTRL0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_SET 13103 #define ANA_LANE_1_QUAD_C_CTRL0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_GET 13104 #define ANA_LANE_1_QUAD_C_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_DC_COUPLEf_GET 13105 #define ANA_LANE_1_QUAD_C_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_DC_COUPLEf_SET 13106 #define ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET 13107 #define ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET 13108 #define ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET 13109 #define ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET 13110 #define ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET 13111 #define ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET 13112 #define ANA_LANE_1_QUAD_C_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RXTX_PWRDNf_GET 13113 #define ANA_LANE_1_QUAD_C_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r_RXTX_PWRDNf_SET 13114 #define READ_ANA_LANE_1_QUAD_C_CTRL0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL0r 13115 #define WRITE_ANA_LANE_1_QUAD_C_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL0r 13116 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL0r 13117 13118 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13119 /******************************************************************************* 13120 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL0r' 13121 */ 13122 13123 13124 13125 13126 /******************************************************************************* 13127 * CHIP: BCMI_HURACAN 13128 * REGISTER: ANA_LANE_1_QUAD_C_CTRL1 13129 * BLOCKS: ANA_LANE_1_QUAD_C 13130 * REGADDR: 0xa201 13131 * DEVAD: 1 13132 * DESC: control registers 0 13133 * RESETVAL: 0x0 (0) 13134 * ACCESS: R/W 13135 * FIELDS: 13136 * RX_SIGDET_THRESHOLD 13137 * REF_OCL 13138 * OCL_PWRDN 13139 * OCL_DISABLE_LOOP 13140 * RXTX_RESERVED_FOR_15_12 13141 */ 13142 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r (0x0001a201 | PHYMOD_REG_ACC_RAW) 13143 13144 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_SIZE 4 13145 13146 /* 13147 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL1. 13148 */ 13149 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_s { 13150 uint32_t v[1]; 13151 uint32_t ana_lane_1_quad_c_ctrl1[1]; 13152 uint32_t _ana_lane_1_quad_c_ctrl1; 13153 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_t; 13154 13155 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_CLR(r) (r).ana_lane_1_quad_c_ctrl1[0] = 0 13156 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_SET(r,d) (r).ana_lane_1_quad_c_ctrl1[0] = d 13157 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_GET(r) (r).ana_lane_1_quad_c_ctrl1[0] 13158 13159 /* 13160 * These macros can be used to access individual fields. 13161 */ 13162 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_1_quad_c_ctrl1[0]) >> 12) & 0xf) 13163 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_1_quad_c_ctrl1[0]=(((r).ana_lane_1_quad_c_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 13164 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_1_quad_c_ctrl1[0]) >> 9) & 0x1) 13165 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_1_quad_c_ctrl1[0]=(((r).ana_lane_1_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 13166 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_1_quad_c_ctrl1[0]) >> 8) & 0x1) 13167 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_1_quad_c_ctrl1[0]=(((r).ana_lane_1_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 13168 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_1_quad_c_ctrl1[0]) >> 4) & 0x3) 13169 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_1_quad_c_ctrl1[0]=(((r).ana_lane_1_quad_c_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 13170 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_1_quad_c_ctrl1[0]) & 0x7) 13171 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_1_quad_c_ctrl1[0]=(((r).ana_lane_1_quad_c_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 13172 13173 /* 13174 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL1. 13175 */ 13176 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r,_r._ana_lane_1_quad_c_ctrl1) 13177 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r,_r._ana_lane_1_quad_c_ctrl1) 13178 13179 /* 13180 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13181 * will be redefined without the chip prefix for easier programming. 13182 * If multiple chips will be programmed in the same source file, then you should 13183 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13184 * and refer to the fully qualified versions. 13185 */ 13186 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13187 13188 #define ANA_LANE_1_QUAD_C_CTRL1r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r 13189 #define ANA_LANE_1_QUAD_C_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_SIZE 13190 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_t ANA_LANE_1_QUAD_C_CTRL1r_t; 13191 #define ANA_LANE_1_QUAD_C_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_CLR 13192 #define ANA_LANE_1_QUAD_C_CTRL1r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_SET 13193 #define ANA_LANE_1_QUAD_C_CTRL1r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_GET 13194 #define ANA_LANE_1_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 13195 #define ANA_LANE_1_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 13196 #define ANA_LANE_1_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET 13197 #define ANA_LANE_1_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET 13198 #define ANA_LANE_1_QUAD_C_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_PWRDNf_GET 13199 #define ANA_LANE_1_QUAD_C_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_OCL_PWRDNf_SET 13200 #define ANA_LANE_1_QUAD_C_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_REF_OCLf_GET 13201 #define ANA_LANE_1_QUAD_C_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_REF_OCLf_SET 13202 #define ANA_LANE_1_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET 13203 #define ANA_LANE_1_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET 13204 #define READ_ANA_LANE_1_QUAD_C_CTRL1r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL1r 13205 #define WRITE_ANA_LANE_1_QUAD_C_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL1r 13206 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL1r 13207 13208 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13209 /******************************************************************************* 13210 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL1r' 13211 */ 13212 13213 13214 13215 13216 /******************************************************************************* 13217 * CHIP: BCMI_HURACAN 13218 * REGISTER: ANA_LANE_1_QUAD_C_CTRL2 13219 * BLOCKS: ANA_LANE_1_QUAD_C 13220 * REGADDR: 0xa202 13221 * DEVAD: 1 13222 * DESC: control registers 0 13223 * RESETVAL: 0x0 (0) 13224 * ACCESS: R/W 13225 * FIELDS: 13226 * CTLE_ENB_NEGIMP 13227 * CTLE_ENB_NEGCAP 13228 */ 13229 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r (0x0001a202 | PHYMOD_REG_ACC_RAW) 13230 13231 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_SIZE 4 13232 13233 /* 13234 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL2. 13235 */ 13236 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_s { 13237 uint32_t v[1]; 13238 uint32_t ana_lane_1_quad_c_ctrl2[1]; 13239 uint32_t _ana_lane_1_quad_c_ctrl2; 13240 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_t; 13241 13242 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CLR(r) (r).ana_lane_1_quad_c_ctrl2[0] = 0 13243 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_SET(r,d) (r).ana_lane_1_quad_c_ctrl2[0] = d 13244 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_GET(r) (r).ana_lane_1_quad_c_ctrl2[0] 13245 13246 /* 13247 * These macros can be used to access individual fields. 13248 */ 13249 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_1_quad_c_ctrl2[0]) >> 8) & 0x7f) 13250 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_1_quad_c_ctrl2[0]=(((r).ana_lane_1_quad_c_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 13251 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_1_quad_c_ctrl2[0]) & 0x7f) 13252 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_1_quad_c_ctrl2[0]=(((r).ana_lane_1_quad_c_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 13253 13254 /* 13255 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL2. 13256 */ 13257 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r,_r._ana_lane_1_quad_c_ctrl2) 13258 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r,_r._ana_lane_1_quad_c_ctrl2) 13259 13260 /* 13261 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13262 * will be redefined without the chip prefix for easier programming. 13263 * If multiple chips will be programmed in the same source file, then you should 13264 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13265 * and refer to the fully qualified versions. 13266 */ 13267 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13268 13269 #define ANA_LANE_1_QUAD_C_CTRL2r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r 13270 #define ANA_LANE_1_QUAD_C_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_SIZE 13271 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_t ANA_LANE_1_QUAD_C_CTRL2r_t; 13272 #define ANA_LANE_1_QUAD_C_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CLR 13273 #define ANA_LANE_1_QUAD_C_CTRL2r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_SET 13274 #define ANA_LANE_1_QUAD_C_CTRL2r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_GET 13275 #define ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET 13276 #define ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET 13277 #define ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET 13278 #define ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET 13279 #define READ_ANA_LANE_1_QUAD_C_CTRL2r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL2r 13280 #define WRITE_ANA_LANE_1_QUAD_C_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL2r 13281 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL2r 13282 13283 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13284 /******************************************************************************* 13285 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL2r' 13286 */ 13287 13288 13289 13290 13291 /******************************************************************************* 13292 * CHIP: BCMI_HURACAN 13293 * REGISTER: ANA_LANE_1_QUAD_C_CTRL3 13294 * BLOCKS: ANA_LANE_1_QUAD_C 13295 * REGADDR: 0xa203 13296 * DEVAD: 1 13297 * DESC: control registers 0 13298 * RESETVAL: 0x0 (0) 13299 * ACCESS: R/W 13300 * FIELDS: 13301 * CTLE_EN_NEGRES 13302 * CTLE_EQSEL 13303 */ 13304 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r (0x0001a203 | PHYMOD_REG_ACC_RAW) 13305 13306 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_SIZE 4 13307 13308 /* 13309 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL3. 13310 */ 13311 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_s { 13312 uint32_t v[1]; 13313 uint32_t ana_lane_1_quad_c_ctrl3[1]; 13314 uint32_t _ana_lane_1_quad_c_ctrl3; 13315 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_t; 13316 13317 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CLR(r) (r).ana_lane_1_quad_c_ctrl3[0] = 0 13318 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_SET(r,d) (r).ana_lane_1_quad_c_ctrl3[0] = d 13319 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_GET(r) (r).ana_lane_1_quad_c_ctrl3[0] 13320 13321 /* 13322 * These macros can be used to access individual fields. 13323 */ 13324 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_1_quad_c_ctrl3[0]) >> 8) & 0xff) 13325 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_1_quad_c_ctrl3[0]=(((r).ana_lane_1_quad_c_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 13326 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_1_quad_c_ctrl3[0]) & 0x7f) 13327 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_1_quad_c_ctrl3[0]=(((r).ana_lane_1_quad_c_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 13328 13329 /* 13330 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL3. 13331 */ 13332 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r,_r._ana_lane_1_quad_c_ctrl3) 13333 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r,_r._ana_lane_1_quad_c_ctrl3) 13334 13335 /* 13336 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13337 * will be redefined without the chip prefix for easier programming. 13338 * If multiple chips will be programmed in the same source file, then you should 13339 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13340 * and refer to the fully qualified versions. 13341 */ 13342 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13343 13344 #define ANA_LANE_1_QUAD_C_CTRL3r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r 13345 #define ANA_LANE_1_QUAD_C_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_SIZE 13346 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_t ANA_LANE_1_QUAD_C_CTRL3r_t; 13347 #define ANA_LANE_1_QUAD_C_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CLR 13348 #define ANA_LANE_1_QUAD_C_CTRL3r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_SET 13349 #define ANA_LANE_1_QUAD_C_CTRL3r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_GET 13350 #define ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EQSELf_GET 13351 #define ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EQSELf_SET 13352 #define ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET 13353 #define ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET 13354 #define READ_ANA_LANE_1_QUAD_C_CTRL3r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL3r 13355 #define WRITE_ANA_LANE_1_QUAD_C_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL3r 13356 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL3r 13357 13358 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13359 /******************************************************************************* 13360 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL3r' 13361 */ 13362 13363 13364 13365 13366 /******************************************************************************* 13367 * CHIP: BCMI_HURACAN 13368 * REGISTER: ANA_LANE_1_QUAD_C_CTRL4 13369 * BLOCKS: ANA_LANE_1_QUAD_C 13370 * REGADDR: 0xa204 13371 * DEVAD: 1 13372 * DESC: control registers 0 13373 * RESETVAL: 0x0 (0) 13374 * ACCESS: R/W 13375 * FIELDS: 13376 * CTLE_LZEN 13377 * RXTX_RESERVED_FOR_59_52 13378 */ 13379 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r (0x0001a204 | PHYMOD_REG_ACC_RAW) 13380 13381 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_SIZE 4 13382 13383 /* 13384 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL4. 13385 */ 13386 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_s { 13387 uint32_t v[1]; 13388 uint32_t ana_lane_1_quad_c_ctrl4[1]; 13389 uint32_t _ana_lane_1_quad_c_ctrl4; 13390 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_t; 13391 13392 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_CLR(r) (r).ana_lane_1_quad_c_ctrl4[0] = 0 13393 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_SET(r,d) (r).ana_lane_1_quad_c_ctrl4[0] = d 13394 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_GET(r) (r).ana_lane_1_quad_c_ctrl4[0] 13395 13396 /* 13397 * These macros can be used to access individual fields. 13398 */ 13399 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_1_quad_c_ctrl4[0]) >> 4) & 0xff) 13400 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_1_quad_c_ctrl4[0]=(((r).ana_lane_1_quad_c_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 13401 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_1_quad_c_ctrl4[0]) & 0x1) 13402 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_1_quad_c_ctrl4[0]=(((r).ana_lane_1_quad_c_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 13403 13404 /* 13405 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL4. 13406 */ 13407 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r,_r._ana_lane_1_quad_c_ctrl4) 13408 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r,_r._ana_lane_1_quad_c_ctrl4) 13409 13410 /* 13411 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13412 * will be redefined without the chip prefix for easier programming. 13413 * If multiple chips will be programmed in the same source file, then you should 13414 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13415 * and refer to the fully qualified versions. 13416 */ 13417 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13418 13419 #define ANA_LANE_1_QUAD_C_CTRL4r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r 13420 #define ANA_LANE_1_QUAD_C_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_SIZE 13421 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_t ANA_LANE_1_QUAD_C_CTRL4r_t; 13422 #define ANA_LANE_1_QUAD_C_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_CLR 13423 #define ANA_LANE_1_QUAD_C_CTRL4r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_SET 13424 #define ANA_LANE_1_QUAD_C_CTRL4r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_GET 13425 #define ANA_LANE_1_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 13426 #define ANA_LANE_1_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 13427 #define ANA_LANE_1_QUAD_C_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_CTLE_LZENf_GET 13428 #define ANA_LANE_1_QUAD_C_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r_CTLE_LZENf_SET 13429 #define READ_ANA_LANE_1_QUAD_C_CTRL4r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL4r 13430 #define WRITE_ANA_LANE_1_QUAD_C_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL4r 13431 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL4r 13432 13433 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13434 /******************************************************************************* 13435 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL4r' 13436 */ 13437 13438 13439 13440 13441 /******************************************************************************* 13442 * CHIP: BCMI_HURACAN 13443 * REGISTER: ANA_LANE_1_QUAD_C_CTRL5 13444 * BLOCKS: ANA_LANE_1_QUAD_C 13445 * REGADDR: 0xa205 13446 * DEVAD: 1 13447 * DESC: control registers 0 13448 * RESETVAL: 0x0 (0) 13449 * ACCESS: R/W 13450 * FIELDS: 13451 * CTLE_LOPEAKING 13452 * CTLE_PD 13453 * LA_GCTRL 13454 */ 13455 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r (0x0001a205 | PHYMOD_REG_ACC_RAW) 13456 13457 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_SIZE 4 13458 13459 /* 13460 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL5. 13461 */ 13462 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_s { 13463 uint32_t v[1]; 13464 uint32_t ana_lane_1_quad_c_ctrl5[1]; 13465 uint32_t _ana_lane_1_quad_c_ctrl5; 13466 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_t; 13467 13468 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CLR(r) (r).ana_lane_1_quad_c_ctrl5[0] = 0 13469 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_SET(r,d) (r).ana_lane_1_quad_c_ctrl5[0] = d 13470 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_GET(r) (r).ana_lane_1_quad_c_ctrl5[0] 13471 13472 /* 13473 * These macros can be used to access individual fields. 13474 */ 13475 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_1_quad_c_ctrl5[0]) >> 4) & 0x3ff) 13476 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_1_quad_c_ctrl5[0]=(((r).ana_lane_1_quad_c_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 13477 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_1_quad_c_ctrl5[0]) >> 1) & 0x1) 13478 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_1_quad_c_ctrl5[0]=(((r).ana_lane_1_quad_c_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 13479 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_1_quad_c_ctrl5[0]) & 0x1) 13480 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_1_quad_c_ctrl5[0]=(((r).ana_lane_1_quad_c_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 13481 13482 /* 13483 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL5. 13484 */ 13485 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r,_r._ana_lane_1_quad_c_ctrl5) 13486 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r,_r._ana_lane_1_quad_c_ctrl5) 13487 13488 /* 13489 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13490 * will be redefined without the chip prefix for easier programming. 13491 * If multiple chips will be programmed in the same source file, then you should 13492 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13493 * and refer to the fully qualified versions. 13494 */ 13495 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13496 13497 #define ANA_LANE_1_QUAD_C_CTRL5r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r 13498 #define ANA_LANE_1_QUAD_C_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_SIZE 13499 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_t ANA_LANE_1_QUAD_C_CTRL5r_t; 13500 #define ANA_LANE_1_QUAD_C_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CLR 13501 #define ANA_LANE_1_QUAD_C_CTRL5r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_SET 13502 #define ANA_LANE_1_QUAD_C_CTRL5r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_GET 13503 #define ANA_LANE_1_QUAD_C_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_LA_GCTRLf_GET 13504 #define ANA_LANE_1_QUAD_C_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_LA_GCTRLf_SET 13505 #define ANA_LANE_1_QUAD_C_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_PDf_GET 13506 #define ANA_LANE_1_QUAD_C_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_PDf_SET 13507 #define ANA_LANE_1_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET 13508 #define ANA_LANE_1_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET 13509 #define READ_ANA_LANE_1_QUAD_C_CTRL5r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL5r 13510 #define WRITE_ANA_LANE_1_QUAD_C_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL5r 13511 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL5r 13512 13513 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13514 /******************************************************************************* 13515 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL5r' 13516 */ 13517 13518 13519 13520 13521 /******************************************************************************* 13522 * CHIP: BCMI_HURACAN 13523 * REGISTER: ANA_LANE_1_QUAD_C_CTRL6 13524 * BLOCKS: ANA_LANE_1_QUAD_C 13525 * REGADDR: 0xa206 13526 * DEVAD: 1 13527 * DESC: control registers 0 13528 * RESETVAL: 0x0 (0) 13529 * ACCESS: R/W 13530 * FIELDS: 13531 * LA_DEGAIN 13532 * LA_DETUNE 13533 */ 13534 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r (0x0001a206 | PHYMOD_REG_ACC_RAW) 13535 13536 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_SIZE 4 13537 13538 /* 13539 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL6. 13540 */ 13541 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_s { 13542 uint32_t v[1]; 13543 uint32_t ana_lane_1_quad_c_ctrl6[1]; 13544 uint32_t _ana_lane_1_quad_c_ctrl6; 13545 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_t; 13546 13547 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_CLR(r) (r).ana_lane_1_quad_c_ctrl6[0] = 0 13548 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_SET(r,d) (r).ana_lane_1_quad_c_ctrl6[0] = d 13549 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_GET(r) (r).ana_lane_1_quad_c_ctrl6[0] 13550 13551 /* 13552 * These macros can be used to access individual fields. 13553 */ 13554 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_1_quad_c_ctrl6[0]) >> 8) & 0xff) 13555 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_1_quad_c_ctrl6[0]=(((r).ana_lane_1_quad_c_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 13556 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_1_quad_c_ctrl6[0]) & 0x1f) 13557 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_1_quad_c_ctrl6[0]=(((r).ana_lane_1_quad_c_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 13558 13559 /* 13560 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL6. 13561 */ 13562 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r,_r._ana_lane_1_quad_c_ctrl6) 13563 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r,_r._ana_lane_1_quad_c_ctrl6) 13564 13565 /* 13566 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13567 * will be redefined without the chip prefix for easier programming. 13568 * If multiple chips will be programmed in the same source file, then you should 13569 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13570 * and refer to the fully qualified versions. 13571 */ 13572 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13573 13574 #define ANA_LANE_1_QUAD_C_CTRL6r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r 13575 #define ANA_LANE_1_QUAD_C_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_SIZE 13576 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_t ANA_LANE_1_QUAD_C_CTRL6r_t; 13577 #define ANA_LANE_1_QUAD_C_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_CLR 13578 #define ANA_LANE_1_QUAD_C_CTRL6r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_SET 13579 #define ANA_LANE_1_QUAD_C_CTRL6r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_GET 13580 #define ANA_LANE_1_QUAD_C_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DETUNEf_GET 13581 #define ANA_LANE_1_QUAD_C_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DETUNEf_SET 13582 #define ANA_LANE_1_QUAD_C_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DEGAINf_GET 13583 #define ANA_LANE_1_QUAD_C_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r_LA_DEGAINf_SET 13584 #define READ_ANA_LANE_1_QUAD_C_CTRL6r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL6r 13585 #define WRITE_ANA_LANE_1_QUAD_C_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL6r 13586 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL6r 13587 13588 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13589 /******************************************************************************* 13590 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL6r' 13591 */ 13592 13593 13594 13595 13596 /******************************************************************************* 13597 * CHIP: BCMI_HURACAN 13598 * REGISTER: ANA_LANE_1_QUAD_C_CTRL7 13599 * BLOCKS: ANA_LANE_1_QUAD_C 13600 * REGADDR: 0xa207 13601 * DEVAD: 1 13602 * DESC: control registers 0 13603 * RESETVAL: 0x0 (0) 13604 * ACCESS: R/W 13605 * FIELDS: 13606 * LA_LIN_MODE 13607 * RX_BIAS_FB_PDN 13608 */ 13609 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r (0x0001a207 | PHYMOD_REG_ACC_RAW) 13610 13611 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_SIZE 4 13612 13613 /* 13614 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL7. 13615 */ 13616 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_s { 13617 uint32_t v[1]; 13618 uint32_t ana_lane_1_quad_c_ctrl7[1]; 13619 uint32_t _ana_lane_1_quad_c_ctrl7; 13620 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_t; 13621 13622 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_CLR(r) (r).ana_lane_1_quad_c_ctrl7[0] = 0 13623 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_SET(r,d) (r).ana_lane_1_quad_c_ctrl7[0] = d 13624 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_GET(r) (r).ana_lane_1_quad_c_ctrl7[0] 13625 13626 /* 13627 * These macros can be used to access individual fields. 13628 */ 13629 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_1_quad_c_ctrl7[0]) >> 8) & 0x1) 13630 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_1_quad_c_ctrl7[0]=(((r).ana_lane_1_quad_c_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 13631 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_1_quad_c_ctrl7[0]) & 0x1f) 13632 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_1_quad_c_ctrl7[0]=(((r).ana_lane_1_quad_c_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 13633 13634 /* 13635 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL7. 13636 */ 13637 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r,_r._ana_lane_1_quad_c_ctrl7) 13638 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r,_r._ana_lane_1_quad_c_ctrl7) 13639 13640 /* 13641 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13642 * will be redefined without the chip prefix for easier programming. 13643 * If multiple chips will be programmed in the same source file, then you should 13644 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13645 * and refer to the fully qualified versions. 13646 */ 13647 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13648 13649 #define ANA_LANE_1_QUAD_C_CTRL7r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r 13650 #define ANA_LANE_1_QUAD_C_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_SIZE 13651 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_t ANA_LANE_1_QUAD_C_CTRL7r_t; 13652 #define ANA_LANE_1_QUAD_C_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_CLR 13653 #define ANA_LANE_1_QUAD_C_CTRL7r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_SET 13654 #define ANA_LANE_1_QUAD_C_CTRL7r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_GET 13655 #define ANA_LANE_1_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET 13656 #define ANA_LANE_1_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET 13657 #define ANA_LANE_1_QUAD_C_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_LA_LIN_MODEf_GET 13658 #define ANA_LANE_1_QUAD_C_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r_LA_LIN_MODEf_SET 13659 #define READ_ANA_LANE_1_QUAD_C_CTRL7r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL7r 13660 #define WRITE_ANA_LANE_1_QUAD_C_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL7r 13661 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL7r 13662 13663 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13664 /******************************************************************************* 13665 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL7r' 13666 */ 13667 13668 13669 13670 13671 /******************************************************************************* 13672 * CHIP: BCMI_HURACAN 13673 * REGISTER: ANA_LANE_1_QUAD_C_CTRL8 13674 * BLOCKS: ANA_LANE_1_QUAD_C 13675 * REGADDR: 0xa208 13676 * DEVAD: 1 13677 * DESC: control registers 0 13678 * RESETVAL: 0x0 (0) 13679 * ACCESS: R/W 13680 * FIELDS: 13681 * LA_PD 13682 * LA_PD_IDLE 13683 * RXTX_RESERVED_FOR_99_95 13684 */ 13685 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r (0x0001a208 | PHYMOD_REG_ACC_RAW) 13686 13687 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_SIZE 4 13688 13689 /* 13690 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL8. 13691 */ 13692 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_s { 13693 uint32_t v[1]; 13694 uint32_t ana_lane_1_quad_c_ctrl8[1]; 13695 uint32_t _ana_lane_1_quad_c_ctrl8; 13696 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_t; 13697 13698 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_CLR(r) (r).ana_lane_1_quad_c_ctrl8[0] = 0 13699 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_SET(r,d) (r).ana_lane_1_quad_c_ctrl8[0] = d 13700 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_GET(r) (r).ana_lane_1_quad_c_ctrl8[0] 13701 13702 /* 13703 * These macros can be used to access individual fields. 13704 */ 13705 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_1_quad_c_ctrl8[0]) >> 4) & 0x1f) 13706 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_1_quad_c_ctrl8[0]=(((r).ana_lane_1_quad_c_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 13707 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_1_quad_c_ctrl8[0]) >> 1) & 0x1) 13708 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_1_quad_c_ctrl8[0]=(((r).ana_lane_1_quad_c_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 13709 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_1_quad_c_ctrl8[0]) & 0x1) 13710 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_1_quad_c_ctrl8[0]=(((r).ana_lane_1_quad_c_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 13711 13712 /* 13713 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL8. 13714 */ 13715 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r,_r._ana_lane_1_quad_c_ctrl8) 13716 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r,_r._ana_lane_1_quad_c_ctrl8) 13717 13718 /* 13719 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13720 * will be redefined without the chip prefix for easier programming. 13721 * If multiple chips will be programmed in the same source file, then you should 13722 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13723 * and refer to the fully qualified versions. 13724 */ 13725 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13726 13727 #define ANA_LANE_1_QUAD_C_CTRL8r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r 13728 #define ANA_LANE_1_QUAD_C_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_SIZE 13729 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_t ANA_LANE_1_QUAD_C_CTRL8r_t; 13730 #define ANA_LANE_1_QUAD_C_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_CLR 13731 #define ANA_LANE_1_QUAD_C_CTRL8r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_SET 13732 #define ANA_LANE_1_QUAD_C_CTRL8r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_GET 13733 #define ANA_LANE_1_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 13734 #define ANA_LANE_1_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 13735 #define ANA_LANE_1_QUAD_C_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PD_IDLEf_GET 13736 #define ANA_LANE_1_QUAD_C_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PD_IDLEf_SET 13737 #define ANA_LANE_1_QUAD_C_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PDf_GET 13738 #define ANA_LANE_1_QUAD_C_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r_LA_PDf_SET 13739 #define READ_ANA_LANE_1_QUAD_C_CTRL8r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL8r 13740 #define WRITE_ANA_LANE_1_QUAD_C_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL8r 13741 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL8r 13742 13743 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13744 /******************************************************************************* 13745 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL8r' 13746 */ 13747 13748 13749 13750 13751 /******************************************************************************* 13752 * CHIP: BCMI_HURACAN 13753 * REGISTER: ANA_LANE_1_QUAD_C_CTRL9 13754 * BLOCKS: ANA_LANE_1_QUAD_C 13755 * REGADDR: 0xa209 13756 * DEVAD: 1 13757 * DESC: control registers 0 13758 * RESETVAL: 0x0 (0) 13759 * ACCESS: R/W 13760 * FIELDS: 13761 * DRV_POST1 13762 * DLINE_SWING_1 13763 * DLINE_SWING_2 13764 * DLINE_DELAY_CTRL 13765 */ 13766 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r (0x0001a209 | PHYMOD_REG_ACC_RAW) 13767 13768 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_SIZE 4 13769 13770 /* 13771 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL9. 13772 */ 13773 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_s { 13774 uint32_t v[1]; 13775 uint32_t ana_lane_1_quad_c_ctrl9[1]; 13776 uint32_t _ana_lane_1_quad_c_ctrl9; 13777 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_t; 13778 13779 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_CLR(r) (r).ana_lane_1_quad_c_ctrl9[0] = 0 13780 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_SET(r,d) (r).ana_lane_1_quad_c_ctrl9[0] = d 13781 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_GET(r) (r).ana_lane_1_quad_c_ctrl9[0] 13782 13783 /* 13784 * These macros can be used to access individual fields. 13785 */ 13786 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_1_quad_c_ctrl9[0]) >> 12) & 0x7) 13787 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_1_quad_c_ctrl9[0]=(((r).ana_lane_1_quad_c_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 13788 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_1_quad_c_ctrl9[0]) >> 8) & 0x3) 13789 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_1_quad_c_ctrl9[0]=(((r).ana_lane_1_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 13790 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_1_quad_c_ctrl9[0]) >> 4) & 0x3) 13791 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_1_quad_c_ctrl9[0]=(((r).ana_lane_1_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 13792 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_1_quad_c_ctrl9[0]) & 0xf) 13793 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_1_quad_c_ctrl9[0]=(((r).ana_lane_1_quad_c_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 13794 13795 /* 13796 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL9. 13797 */ 13798 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r,_r._ana_lane_1_quad_c_ctrl9) 13799 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r,_r._ana_lane_1_quad_c_ctrl9) 13800 13801 /* 13802 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13803 * will be redefined without the chip prefix for easier programming. 13804 * If multiple chips will be programmed in the same source file, then you should 13805 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13806 * and refer to the fully qualified versions. 13807 */ 13808 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13809 13810 #define ANA_LANE_1_QUAD_C_CTRL9r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r 13811 #define ANA_LANE_1_QUAD_C_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_SIZE 13812 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_t ANA_LANE_1_QUAD_C_CTRL9r_t; 13813 #define ANA_LANE_1_QUAD_C_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_CLR 13814 #define ANA_LANE_1_QUAD_C_CTRL9r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_SET 13815 #define ANA_LANE_1_QUAD_C_CTRL9r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_GET 13816 #define ANA_LANE_1_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET 13817 #define ANA_LANE_1_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET 13818 #define ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_2f_GET 13819 #define ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_2f_SET 13820 #define ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_1f_GET 13821 #define ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DLINE_SWING_1f_SET 13822 #define ANA_LANE_1_QUAD_C_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DRV_POST1f_GET 13823 #define ANA_LANE_1_QUAD_C_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r_DRV_POST1f_SET 13824 #define READ_ANA_LANE_1_QUAD_C_CTRL9r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL9r 13825 #define WRITE_ANA_LANE_1_QUAD_C_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL9r 13826 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL9r 13827 13828 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13829 /******************************************************************************* 13830 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL9r' 13831 */ 13832 13833 13834 13835 13836 /******************************************************************************* 13837 * CHIP: BCMI_HURACAN 13838 * REGISTER: ANA_LANE_1_QUAD_C_CTRL10 13839 * BLOCKS: ANA_LANE_1_QUAD_C 13840 * REGADDR: 0xa20a 13841 * DEVAD: 1 13842 * DESC: control registers 0 13843 * RESETVAL: 0x0 (0) 13844 * ACCESS: R/W 13845 * FIELDS: 13846 * DRV_PWD 13847 * DLINE_PWD 13848 * DRV_VBSEL 13849 * DRV_MAIN 13850 * DRV_MAIN_PU 13851 */ 13852 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r (0x0001a20a | PHYMOD_REG_ACC_RAW) 13853 13854 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_SIZE 4 13855 13856 /* 13857 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL10. 13858 */ 13859 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_s { 13860 uint32_t v[1]; 13861 uint32_t ana_lane_1_quad_c_ctrl10[1]; 13862 uint32_t _ana_lane_1_quad_c_ctrl10; 13863 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_t; 13864 13865 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_CLR(r) (r).ana_lane_1_quad_c_ctrl10[0] = 0 13866 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_SET(r,d) (r).ana_lane_1_quad_c_ctrl10[0] = d 13867 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_GET(r) (r).ana_lane_1_quad_c_ctrl10[0] 13868 13869 /* 13870 * These macros can be used to access individual fields. 13871 */ 13872 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_1_quad_c_ctrl10[0]) >> 12) & 0xf) 13873 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_1_quad_c_ctrl10[0]=(((r).ana_lane_1_quad_c_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 13874 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_1_quad_c_ctrl10[0]) >> 4) & 0x3f) 13875 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_1_quad_c_ctrl10[0]=(((r).ana_lane_1_quad_c_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 13876 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_1_quad_c_ctrl10[0]) >> 2) & 0x1) 13877 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_1_quad_c_ctrl10[0]=(((r).ana_lane_1_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 13878 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_1_quad_c_ctrl10[0]) >> 1) & 0x1) 13879 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_1_quad_c_ctrl10[0]=(((r).ana_lane_1_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 13880 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_1_quad_c_ctrl10[0]) & 0x1) 13881 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_1_quad_c_ctrl10[0]=(((r).ana_lane_1_quad_c_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 13882 13883 /* 13884 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL10. 13885 */ 13886 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r,_r._ana_lane_1_quad_c_ctrl10) 13887 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r,_r._ana_lane_1_quad_c_ctrl10) 13888 13889 /* 13890 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13891 * will be redefined without the chip prefix for easier programming. 13892 * If multiple chips will be programmed in the same source file, then you should 13893 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13894 * and refer to the fully qualified versions. 13895 */ 13896 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13897 13898 #define ANA_LANE_1_QUAD_C_CTRL10r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r 13899 #define ANA_LANE_1_QUAD_C_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_SIZE 13900 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_t ANA_LANE_1_QUAD_C_CTRL10r_t; 13901 #define ANA_LANE_1_QUAD_C_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_CLR 13902 #define ANA_LANE_1_QUAD_C_CTRL10r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_SET 13903 #define ANA_LANE_1_QUAD_C_CTRL10r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_GET 13904 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET 13905 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET 13906 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAINf_GET 13907 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_MAINf_SET 13908 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_VBSELf_GET 13909 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_VBSELf_SET 13910 #define ANA_LANE_1_QUAD_C_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DLINE_PWDf_GET 13911 #define ANA_LANE_1_QUAD_C_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DLINE_PWDf_SET 13912 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_PWDf_GET 13913 #define ANA_LANE_1_QUAD_C_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r_DRV_PWDf_SET 13914 #define READ_ANA_LANE_1_QUAD_C_CTRL10r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL10r 13915 #define WRITE_ANA_LANE_1_QUAD_C_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL10r 13916 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL10r 13917 13918 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13919 /******************************************************************************* 13920 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL10r' 13921 */ 13922 13923 13924 13925 13926 /******************************************************************************* 13927 * CHIP: BCMI_HURACAN 13928 * REGISTER: ANA_LANE_1_QUAD_C_CTRL11 13929 * BLOCKS: ANA_LANE_1_QUAD_C 13930 * REGADDR: 0xa20b 13931 * DEVAD: 1 13932 * DESC: control registers 0 13933 * RESETVAL: 0x0 (0) 13934 * ACCESS: R/W 13935 * FIELDS: 13936 * RXTX_RESERVED_FOR_143_128 13937 */ 13938 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r (0x0001a20b | PHYMOD_REG_ACC_RAW) 13939 13940 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_SIZE 4 13941 13942 /* 13943 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL11. 13944 */ 13945 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_s { 13946 uint32_t v[1]; 13947 uint32_t ana_lane_1_quad_c_ctrl11[1]; 13948 uint32_t _ana_lane_1_quad_c_ctrl11; 13949 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_t; 13950 13951 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_CLR(r) (r).ana_lane_1_quad_c_ctrl11[0] = 0 13952 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_SET(r,d) (r).ana_lane_1_quad_c_ctrl11[0] = d 13953 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_GET(r) (r).ana_lane_1_quad_c_ctrl11[0] 13954 13955 /* 13956 * These macros can be used to access individual fields. 13957 */ 13958 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_1_quad_c_ctrl11[0]) & 0xffff) 13959 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_1_quad_c_ctrl11[0]=(((r).ana_lane_1_quad_c_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 13960 13961 /* 13962 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL11. 13963 */ 13964 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r,_r._ana_lane_1_quad_c_ctrl11) 13965 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r,_r._ana_lane_1_quad_c_ctrl11) 13966 13967 /* 13968 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 13969 * will be redefined without the chip prefix for easier programming. 13970 * If multiple chips will be programmed in the same source file, then you should 13971 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 13972 * and refer to the fully qualified versions. 13973 */ 13974 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 13975 13976 #define ANA_LANE_1_QUAD_C_CTRL11r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r 13977 #define ANA_LANE_1_QUAD_C_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_SIZE 13978 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_t ANA_LANE_1_QUAD_C_CTRL11r_t; 13979 #define ANA_LANE_1_QUAD_C_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_CLR 13980 #define ANA_LANE_1_QUAD_C_CTRL11r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_SET 13981 #define ANA_LANE_1_QUAD_C_CTRL11r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_GET 13982 #define ANA_LANE_1_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 13983 #define ANA_LANE_1_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 13984 #define READ_ANA_LANE_1_QUAD_C_CTRL11r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL11r 13985 #define WRITE_ANA_LANE_1_QUAD_C_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL11r 13986 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL11r 13987 13988 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 13989 /******************************************************************************* 13990 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL11r' 13991 */ 13992 13993 13994 13995 13996 /******************************************************************************* 13997 * CHIP: BCMI_HURACAN 13998 * REGISTER: ANA_LANE_1_QUAD_C_CTRL12 13999 * BLOCKS: ANA_LANE_1_QUAD_C 14000 * REGADDR: 0xa20c 14001 * DEVAD: 1 14002 * DESC: control registers 0 14003 * RESETVAL: 0x0 (0) 14004 * ACCESS: R/W 14005 * FIELDS: 14006 * LA_RESCAL_FRC_VAL 14007 * LA_RESCAL_FRC 14008 * DRV_RESCAL_FRC_VAL 14009 * DRV_RESCAL_FRC 14010 */ 14011 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r (0x0001a20c | PHYMOD_REG_ACC_RAW) 14012 14013 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_SIZE 4 14014 14015 /* 14016 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL12. 14017 */ 14018 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_s { 14019 uint32_t v[1]; 14020 uint32_t ana_lane_1_quad_c_ctrl12[1]; 14021 uint32_t _ana_lane_1_quad_c_ctrl12; 14022 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_t; 14023 14024 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_CLR(r) (r).ana_lane_1_quad_c_ctrl12[0] = 0 14025 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_SET(r,d) (r).ana_lane_1_quad_c_ctrl12[0] = d 14026 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_GET(r) (r).ana_lane_1_quad_c_ctrl12[0] 14027 14028 /* 14029 * These macros can be used to access individual fields. 14030 */ 14031 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_c_ctrl12[0]) >> 12) & 0x1) 14032 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_c_ctrl12[0]=(((r).ana_lane_1_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 14033 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_c_ctrl12[0]) >> 8) & 0xf) 14034 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_c_ctrl12[0]=(((r).ana_lane_1_quad_c_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 14035 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_c_ctrl12[0]) >> 4) & 0x1) 14036 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_c_ctrl12[0]=(((r).ana_lane_1_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 14037 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_c_ctrl12[0]) & 0xf) 14038 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_c_ctrl12[0]=(((r).ana_lane_1_quad_c_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 14039 14040 /* 14041 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL12. 14042 */ 14043 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r,_r._ana_lane_1_quad_c_ctrl12) 14044 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r,_r._ana_lane_1_quad_c_ctrl12) 14045 14046 /* 14047 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14048 * will be redefined without the chip prefix for easier programming. 14049 * If multiple chips will be programmed in the same source file, then you should 14050 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14051 * and refer to the fully qualified versions. 14052 */ 14053 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14054 14055 #define ANA_LANE_1_QUAD_C_CTRL12r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r 14056 #define ANA_LANE_1_QUAD_C_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_SIZE 14057 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_t ANA_LANE_1_QUAD_C_CTRL12r_t; 14058 #define ANA_LANE_1_QUAD_C_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_CLR 14059 #define ANA_LANE_1_QUAD_C_CTRL12r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_SET 14060 #define ANA_LANE_1_QUAD_C_CTRL12r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_GET 14061 #define ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET 14062 #define ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET 14063 #define ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET 14064 #define ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET 14065 #define ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET 14066 #define ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET 14067 #define ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET 14068 #define ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET 14069 #define READ_ANA_LANE_1_QUAD_C_CTRL12r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL12r 14070 #define WRITE_ANA_LANE_1_QUAD_C_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL12r 14071 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL12r 14072 14073 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14074 /******************************************************************************* 14075 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL12r' 14076 */ 14077 14078 14079 14080 14081 /******************************************************************************* 14082 * CHIP: BCMI_HURACAN 14083 * REGISTER: ANA_LANE_1_QUAD_C_CTRL13 14084 * BLOCKS: ANA_LANE_1_QUAD_C 14085 * REGADDR: 0xa20d 14086 * DEVAD: 1 14087 * DESC: control registers 0 14088 * RESETVAL: 0x0 (0) 14089 * ACCESS: R/W 14090 * FIELDS: 14091 * CTLE_RESCAL_FRC_VAL 14092 * CTLE_RESCAL_FRC 14093 */ 14094 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r (0x0001a20d | PHYMOD_REG_ACC_RAW) 14095 14096 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_SIZE 4 14097 14098 /* 14099 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL13. 14100 */ 14101 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_s { 14102 uint32_t v[1]; 14103 uint32_t ana_lane_1_quad_c_ctrl13[1]; 14104 uint32_t _ana_lane_1_quad_c_ctrl13; 14105 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_t; 14106 14107 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CLR(r) (r).ana_lane_1_quad_c_ctrl13[0] = 0 14108 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_SET(r,d) (r).ana_lane_1_quad_c_ctrl13[0] = d 14109 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_GET(r) (r).ana_lane_1_quad_c_ctrl13[0] 14110 14111 /* 14112 * These macros can be used to access individual fields. 14113 */ 14114 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_c_ctrl13[0]) >> 4) & 0x1) 14115 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_c_ctrl13[0]=(((r).ana_lane_1_quad_c_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 14116 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_c_ctrl13[0]) & 0xf) 14117 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_c_ctrl13[0]=(((r).ana_lane_1_quad_c_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 14118 14119 /* 14120 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL13. 14121 */ 14122 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r,_r._ana_lane_1_quad_c_ctrl13) 14123 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r,_r._ana_lane_1_quad_c_ctrl13) 14124 14125 /* 14126 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14127 * will be redefined without the chip prefix for easier programming. 14128 * If multiple chips will be programmed in the same source file, then you should 14129 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14130 * and refer to the fully qualified versions. 14131 */ 14132 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14133 14134 #define ANA_LANE_1_QUAD_C_CTRL13r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r 14135 #define ANA_LANE_1_QUAD_C_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_SIZE 14136 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_t ANA_LANE_1_QUAD_C_CTRL13r_t; 14137 #define ANA_LANE_1_QUAD_C_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CLR 14138 #define ANA_LANE_1_QUAD_C_CTRL13r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_SET 14139 #define ANA_LANE_1_QUAD_C_CTRL13r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_GET 14140 #define ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET 14141 #define ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET 14142 #define ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 14143 #define ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 14144 #define READ_ANA_LANE_1_QUAD_C_CTRL13r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL13r 14145 #define WRITE_ANA_LANE_1_QUAD_C_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL13r 14146 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL13r 14147 14148 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14149 /******************************************************************************* 14150 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL13r' 14151 */ 14152 14153 14154 14155 14156 /******************************************************************************* 14157 * CHIP: BCMI_HURACAN 14158 * REGISTER: ANA_LANE_1_QUAD_C_CTRL14 14159 * BLOCKS: ANA_LANE_1_QUAD_C 14160 * REGADDR: 0xa20e 14161 * DEVAD: 1 14162 * DESC: control registers 0 14163 * RESETVAL: 0x0 (0) 14164 * ACCESS: R/W 14165 * FIELDS: 14166 * TX_IDLE_FRC_VAL 14167 * TX_IDLE_FRC 14168 * RXSD_IDLE_OVRD 14169 */ 14170 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r (0x0001a20e | PHYMOD_REG_ACC_RAW) 14171 14172 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_SIZE 4 14173 14174 /* 14175 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL14. 14176 */ 14177 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_s { 14178 uint32_t v[1]; 14179 uint32_t ana_lane_1_quad_c_ctrl14[1]; 14180 uint32_t _ana_lane_1_quad_c_ctrl14; 14181 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_t; 14182 14183 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_CLR(r) (r).ana_lane_1_quad_c_ctrl14[0] = 0 14184 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_SET(r,d) (r).ana_lane_1_quad_c_ctrl14[0] = d 14185 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_GET(r) (r).ana_lane_1_quad_c_ctrl14[0] 14186 14187 /* 14188 * These macros can be used to access individual fields. 14189 */ 14190 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_1_quad_c_ctrl14[0]) >> 4) & 0x1) 14191 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_1_quad_c_ctrl14[0]=(((r).ana_lane_1_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 14192 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_1_quad_c_ctrl14[0]) >> 1) & 0x1) 14193 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_1_quad_c_ctrl14[0]=(((r).ana_lane_1_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 14194 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_1_quad_c_ctrl14[0]) & 0x1) 14195 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_c_ctrl14[0]=(((r).ana_lane_1_quad_c_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 14196 14197 /* 14198 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL14. 14199 */ 14200 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r,_r._ana_lane_1_quad_c_ctrl14) 14201 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r,_r._ana_lane_1_quad_c_ctrl14) 14202 14203 /* 14204 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14205 * will be redefined without the chip prefix for easier programming. 14206 * If multiple chips will be programmed in the same source file, then you should 14207 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14208 * and refer to the fully qualified versions. 14209 */ 14210 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14211 14212 #define ANA_LANE_1_QUAD_C_CTRL14r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r 14213 #define ANA_LANE_1_QUAD_C_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_SIZE 14214 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_t ANA_LANE_1_QUAD_C_CTRL14r_t; 14215 #define ANA_LANE_1_QUAD_C_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_CLR 14216 #define ANA_LANE_1_QUAD_C_CTRL14r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_SET 14217 #define ANA_LANE_1_QUAD_C_CTRL14r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_GET 14218 #define ANA_LANE_1_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET 14219 #define ANA_LANE_1_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET 14220 #define ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET 14221 #define ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET 14222 #define ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET 14223 #define ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET 14224 #define READ_ANA_LANE_1_QUAD_C_CTRL14r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL14r 14225 #define WRITE_ANA_LANE_1_QUAD_C_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL14r 14226 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL14r 14227 14228 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14229 /******************************************************************************* 14230 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL14r' 14231 */ 14232 14233 14234 14235 14236 /******************************************************************************* 14237 * CHIP: BCMI_HURACAN 14238 * REGISTER: ANA_LANE_1_QUAD_C_CTRL15 14239 * BLOCKS: ANA_LANE_1_QUAD_C 14240 * REGADDR: 0xa20f 14241 * DEVAD: 1 14242 * DESC: sigdet filter settings 0 14243 * RESETVAL: 0x0 (0) 14244 * ACCESS: R/W 14245 * FIELDS: 14246 * SIGDET_DIS 14247 * SIGDET_1US_EN 14248 * SIGDET_FRC_VAL 14249 * SIGDET_FRC 14250 * HOLD_LOS_COUNT 14251 * HOLD_SD_COUNT 14252 */ 14253 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r (0x0001a20f | PHYMOD_REG_ACC_RAW) 14254 14255 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIZE 4 14256 14257 /* 14258 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL15. 14259 */ 14260 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_s { 14261 uint32_t v[1]; 14262 uint32_t ana_lane_1_quad_c_ctrl15[1]; 14263 uint32_t _ana_lane_1_quad_c_ctrl15; 14264 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_t; 14265 14266 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_CLR(r) (r).ana_lane_1_quad_c_ctrl15[0] = 0 14267 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SET(r,d) (r).ana_lane_1_quad_c_ctrl15[0] = d 14268 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_GET(r) (r).ana_lane_1_quad_c_ctrl15[0] 14269 14270 /* 14271 * These macros can be used to access individual fields. 14272 */ 14273 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_c_ctrl15[0]) >> 8) & 0x7) 14274 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_c_ctrl15[0]=(((r).ana_lane_1_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 14275 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_1_quad_c_ctrl15[0]) >> 4) & 0x7) 14276 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_c_ctrl15[0]=(((r).ana_lane_1_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 14277 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_1_quad_c_ctrl15[0]) >> 3) & 0x1) 14278 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_1_quad_c_ctrl15[0]=(((r).ana_lane_1_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 14279 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_c_ctrl15[0]) >> 2) & 0x1) 14280 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_c_ctrl15[0]=(((r).ana_lane_1_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 14281 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_1_quad_c_ctrl15[0]) >> 1) & 0x1) 14282 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_1_quad_c_ctrl15[0]=(((r).ana_lane_1_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 14283 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_1_quad_c_ctrl15[0]) & 0x1) 14284 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_1_quad_c_ctrl15[0]=(((r).ana_lane_1_quad_c_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 14285 14286 /* 14287 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL15. 14288 */ 14289 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r,_r._ana_lane_1_quad_c_ctrl15) 14290 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r,_r._ana_lane_1_quad_c_ctrl15) 14291 14292 /* 14293 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14294 * will be redefined without the chip prefix for easier programming. 14295 * If multiple chips will be programmed in the same source file, then you should 14296 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14297 * and refer to the fully qualified versions. 14298 */ 14299 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14300 14301 #define ANA_LANE_1_QUAD_C_CTRL15r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r 14302 #define ANA_LANE_1_QUAD_C_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIZE 14303 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_t ANA_LANE_1_QUAD_C_CTRL15r_t; 14304 #define ANA_LANE_1_QUAD_C_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_CLR 14305 #define ANA_LANE_1_QUAD_C_CTRL15r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SET 14306 #define ANA_LANE_1_QUAD_C_CTRL15r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_GET 14307 #define ANA_LANE_1_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET 14308 #define ANA_LANE_1_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET 14309 #define ANA_LANE_1_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET 14310 #define ANA_LANE_1_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET 14311 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRCf_GET 14312 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRCf_SET 14313 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET 14314 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET 14315 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET 14316 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET 14317 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_DISf_GET 14318 #define ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r_SIGDET_DISf_SET 14319 #define READ_ANA_LANE_1_QUAD_C_CTRL15r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL15r 14320 #define WRITE_ANA_LANE_1_QUAD_C_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL15r 14321 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL15r 14322 14323 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14324 /******************************************************************************* 14325 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL15r' 14326 */ 14327 14328 14329 14330 14331 /******************************************************************************* 14332 * CHIP: BCMI_HURACAN 14333 * REGISTER: ANA_LANE_1_QUAD_C_CTRL16 14334 * BLOCKS: ANA_LANE_1_QUAD_C 14335 * REGADDR: 0xa210 14336 * DEVAD: 1 14337 * DESC: sigdet filter settings 1 14338 * RESETVAL: 0x0 (0) 14339 * ACCESS: R/W 14340 * FIELDS: 14341 * LOS_COUNT 14342 * SD_COUNT 14343 */ 14344 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r (0x0001a210 | PHYMOD_REG_ACC_RAW) 14345 14346 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SIZE 4 14347 14348 /* 14349 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_CTRL16. 14350 */ 14351 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_s { 14352 uint32_t v[1]; 14353 uint32_t ana_lane_1_quad_c_ctrl16[1]; 14354 uint32_t _ana_lane_1_quad_c_ctrl16; 14355 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_t; 14356 14357 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_CLR(r) (r).ana_lane_1_quad_c_ctrl16[0] = 0 14358 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SET(r,d) (r).ana_lane_1_quad_c_ctrl16[0] = d 14359 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_GET(r) (r).ana_lane_1_quad_c_ctrl16[0] 14360 14361 /* 14362 * These macros can be used to access individual fields. 14363 */ 14364 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_c_ctrl16[0]) >> 8) & 0x1f) 14365 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_c_ctrl16[0]=(((r).ana_lane_1_quad_c_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 14366 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_1_quad_c_ctrl16[0]) & 0x1f) 14367 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_c_ctrl16[0]=(((r).ana_lane_1_quad_c_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 14368 14369 /* 14370 * These macros can be used to access ANA_LANE_1_QUAD_C_CTRL16. 14371 */ 14372 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r,_r._ana_lane_1_quad_c_ctrl16) 14373 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r,_r._ana_lane_1_quad_c_ctrl16) 14374 14375 /* 14376 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14377 * will be redefined without the chip prefix for easier programming. 14378 * If multiple chips will be programmed in the same source file, then you should 14379 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14380 * and refer to the fully qualified versions. 14381 */ 14382 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14383 14384 #define ANA_LANE_1_QUAD_C_CTRL16r BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r 14385 #define ANA_LANE_1_QUAD_C_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SIZE 14386 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_t ANA_LANE_1_QUAD_C_CTRL16r_t; 14387 #define ANA_LANE_1_QUAD_C_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_CLR 14388 #define ANA_LANE_1_QUAD_C_CTRL16r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SET 14389 #define ANA_LANE_1_QUAD_C_CTRL16r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_GET 14390 #define ANA_LANE_1_QUAD_C_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SD_COUNTf_GET 14391 #define ANA_LANE_1_QUAD_C_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_SD_COUNTf_SET 14392 #define ANA_LANE_1_QUAD_C_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_LOS_COUNTf_GET 14393 #define ANA_LANE_1_QUAD_C_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r_LOS_COUNTf_SET 14394 #define READ_ANA_LANE_1_QUAD_C_CTRL16r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_CTRL16r 14395 #define WRITE_ANA_LANE_1_QUAD_C_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_CTRL16r 14396 #define MODIFY_ANA_LANE_1_QUAD_C_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_CTRL16r 14397 14398 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14399 /******************************************************************************* 14400 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_CTRL16r' 14401 */ 14402 14403 14404 14405 14406 /******************************************************************************* 14407 * CHIP: BCMI_HURACAN 14408 * REGISTER: ANA_LANE_1_QUAD_C_STATUS0 14409 * BLOCKS: ANA_LANE_1_QUAD_C 14410 * REGADDR: 0xa220 14411 * DEVAD: 1 14412 * DESC: status registers 0 14413 * RESETVAL: 0x0 (0) 14414 * ACCESS: R/W 14415 * FIELDS: 14416 * O_RX_SIGDET 14417 * DG_RX_SIGDET 14418 */ 14419 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r (0x0001a220 | PHYMOD_REG_ACC_RAW) 14420 14421 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_SIZE 4 14422 14423 /* 14424 * This structure should be used to declare and program ANA_LANE_1_QUAD_C_STATUS0. 14425 */ 14426 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_s { 14427 uint32_t v[1]; 14428 uint32_t ana_lane_1_quad_c_status0[1]; 14429 uint32_t _ana_lane_1_quad_c_status0; 14430 } BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_t; 14431 14432 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_CLR(r) (r).ana_lane_1_quad_c_status0[0] = 0 14433 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_SET(r,d) (r).ana_lane_1_quad_c_status0[0] = d 14434 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_GET(r) (r).ana_lane_1_quad_c_status0[0] 14435 14436 /* 14437 * These macros can be used to access individual fields. 14438 */ 14439 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_1_quad_c_status0[0]) >> 1) & 0x1) 14440 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_c_status0[0]=(((r).ana_lane_1_quad_c_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 14441 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_1_quad_c_status0[0]) & 0x1) 14442 #define BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_c_status0[0]=(((r).ana_lane_1_quad_c_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 14443 14444 /* 14445 * These macros can be used to access ANA_LANE_1_QUAD_C_STATUS0. 14446 */ 14447 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r,_r._ana_lane_1_quad_c_status0) 14448 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r,_r._ana_lane_1_quad_c_status0) 14449 14450 /* 14451 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14452 * will be redefined without the chip prefix for easier programming. 14453 * If multiple chips will be programmed in the same source file, then you should 14454 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14455 * and refer to the fully qualified versions. 14456 */ 14457 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14458 14459 #define ANA_LANE_1_QUAD_C_STATUS0r BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r 14460 #define ANA_LANE_1_QUAD_C_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_SIZE 14461 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_t ANA_LANE_1_QUAD_C_STATUS0r_t; 14462 #define ANA_LANE_1_QUAD_C_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_CLR 14463 #define ANA_LANE_1_QUAD_C_STATUS0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_SET 14464 #define ANA_LANE_1_QUAD_C_STATUS0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_GET 14465 #define ANA_LANE_1_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET 14466 #define ANA_LANE_1_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET 14467 #define ANA_LANE_1_QUAD_C_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_O_RX_SIGDETf_GET 14468 #define ANA_LANE_1_QUAD_C_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r_O_RX_SIGDETf_SET 14469 #define READ_ANA_LANE_1_QUAD_C_STATUS0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_C_STATUS0r 14470 #define WRITE_ANA_LANE_1_QUAD_C_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_C_STATUS0r 14471 #define MODIFY_ANA_LANE_1_QUAD_C_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_C_STATUS0r 14472 14473 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14474 /******************************************************************************* 14475 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_C_STATUS0r' 14476 */ 14477 14478 14479 14480 14481 /******************************************************************************* 14482 * CHIP: BCMI_HURACAN 14483 * REGISTER: ANA_LANE_2_QUAD_C_CTRL0 14484 * BLOCKS: ANA_LANE_2_QUAD_C 14485 * REGADDR: 0xa400 14486 * DEVAD: 1 14487 * DESC: control registers 0 14488 * RESETVAL: 0x0 (0) 14489 * ACCESS: R/W 14490 * FIELDS: 14491 * RXTX_PWRDN 14492 * RX_SIGDET_BYPASS 14493 * RX_SIGDET_PWRDN 14494 * RX_SIGDECT_12GMODE 14495 * DC_COUPLE 14496 */ 14497 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r (0x0001a400 | PHYMOD_REG_ACC_RAW) 14498 14499 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_SIZE 4 14500 14501 /* 14502 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL0. 14503 */ 14504 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_s { 14505 uint32_t v[1]; 14506 uint32_t ana_lane_2_quad_c_ctrl0[1]; 14507 uint32_t _ana_lane_2_quad_c_ctrl0; 14508 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_t; 14509 14510 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_CLR(r) (r).ana_lane_2_quad_c_ctrl0[0] = 0 14511 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_SET(r,d) (r).ana_lane_2_quad_c_ctrl0[0] = d 14512 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_GET(r) (r).ana_lane_2_quad_c_ctrl0[0] 14513 14514 /* 14515 * These macros can be used to access individual fields. 14516 */ 14517 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_2_quad_c_ctrl0[0]) >> 4) & 0x1) 14518 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_2_quad_c_ctrl0[0]=(((r).ana_lane_2_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 14519 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_2_quad_c_ctrl0[0]) >> 3) & 0x1) 14520 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_2_quad_c_ctrl0[0]=(((r).ana_lane_2_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 14521 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_2_quad_c_ctrl0[0]) >> 2) & 0x1) 14522 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_2_quad_c_ctrl0[0]=(((r).ana_lane_2_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 14523 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_2_quad_c_ctrl0[0]) >> 1) & 0x1) 14524 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_2_quad_c_ctrl0[0]=(((r).ana_lane_2_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 14525 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_2_quad_c_ctrl0[0]) & 0x1) 14526 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_2_quad_c_ctrl0[0]=(((r).ana_lane_2_quad_c_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 14527 14528 /* 14529 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL0. 14530 */ 14531 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r,_r._ana_lane_2_quad_c_ctrl0) 14532 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r,_r._ana_lane_2_quad_c_ctrl0) 14533 14534 /* 14535 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14536 * will be redefined without the chip prefix for easier programming. 14537 * If multiple chips will be programmed in the same source file, then you should 14538 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14539 * and refer to the fully qualified versions. 14540 */ 14541 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14542 14543 #define ANA_LANE_2_QUAD_C_CTRL0r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r 14544 #define ANA_LANE_2_QUAD_C_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_SIZE 14545 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_t ANA_LANE_2_QUAD_C_CTRL0r_t; 14546 #define ANA_LANE_2_QUAD_C_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_CLR 14547 #define ANA_LANE_2_QUAD_C_CTRL0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_SET 14548 #define ANA_LANE_2_QUAD_C_CTRL0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_GET 14549 #define ANA_LANE_2_QUAD_C_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_DC_COUPLEf_GET 14550 #define ANA_LANE_2_QUAD_C_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_DC_COUPLEf_SET 14551 #define ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET 14552 #define ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET 14553 #define ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET 14554 #define ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET 14555 #define ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET 14556 #define ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET 14557 #define ANA_LANE_2_QUAD_C_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RXTX_PWRDNf_GET 14558 #define ANA_LANE_2_QUAD_C_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r_RXTX_PWRDNf_SET 14559 #define READ_ANA_LANE_2_QUAD_C_CTRL0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL0r 14560 #define WRITE_ANA_LANE_2_QUAD_C_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL0r 14561 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL0r 14562 14563 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14564 /******************************************************************************* 14565 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL0r' 14566 */ 14567 14568 14569 14570 14571 /******************************************************************************* 14572 * CHIP: BCMI_HURACAN 14573 * REGISTER: ANA_LANE_2_QUAD_C_CTRL1 14574 * BLOCKS: ANA_LANE_2_QUAD_C 14575 * REGADDR: 0xa401 14576 * DEVAD: 1 14577 * DESC: control registers 0 14578 * RESETVAL: 0x0 (0) 14579 * ACCESS: R/W 14580 * FIELDS: 14581 * RX_SIGDET_THRESHOLD 14582 * REF_OCL 14583 * OCL_PWRDN 14584 * OCL_DISABLE_LOOP 14585 * RXTX_RESERVED_FOR_15_12 14586 */ 14587 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r (0x0001a401 | PHYMOD_REG_ACC_RAW) 14588 14589 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_SIZE 4 14590 14591 /* 14592 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL1. 14593 */ 14594 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_s { 14595 uint32_t v[1]; 14596 uint32_t ana_lane_2_quad_c_ctrl1[1]; 14597 uint32_t _ana_lane_2_quad_c_ctrl1; 14598 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_t; 14599 14600 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_CLR(r) (r).ana_lane_2_quad_c_ctrl1[0] = 0 14601 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_SET(r,d) (r).ana_lane_2_quad_c_ctrl1[0] = d 14602 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_GET(r) (r).ana_lane_2_quad_c_ctrl1[0] 14603 14604 /* 14605 * These macros can be used to access individual fields. 14606 */ 14607 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_2_quad_c_ctrl1[0]) >> 12) & 0xf) 14608 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_2_quad_c_ctrl1[0]=(((r).ana_lane_2_quad_c_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 14609 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_2_quad_c_ctrl1[0]) >> 9) & 0x1) 14610 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_2_quad_c_ctrl1[0]=(((r).ana_lane_2_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 14611 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_2_quad_c_ctrl1[0]) >> 8) & 0x1) 14612 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_2_quad_c_ctrl1[0]=(((r).ana_lane_2_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 14613 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_2_quad_c_ctrl1[0]) >> 4) & 0x3) 14614 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_2_quad_c_ctrl1[0]=(((r).ana_lane_2_quad_c_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 14615 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_2_quad_c_ctrl1[0]) & 0x7) 14616 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_2_quad_c_ctrl1[0]=(((r).ana_lane_2_quad_c_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 14617 14618 /* 14619 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL1. 14620 */ 14621 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r,_r._ana_lane_2_quad_c_ctrl1) 14622 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r,_r._ana_lane_2_quad_c_ctrl1) 14623 14624 /* 14625 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14626 * will be redefined without the chip prefix for easier programming. 14627 * If multiple chips will be programmed in the same source file, then you should 14628 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14629 * and refer to the fully qualified versions. 14630 */ 14631 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14632 14633 #define ANA_LANE_2_QUAD_C_CTRL1r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r 14634 #define ANA_LANE_2_QUAD_C_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_SIZE 14635 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_t ANA_LANE_2_QUAD_C_CTRL1r_t; 14636 #define ANA_LANE_2_QUAD_C_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_CLR 14637 #define ANA_LANE_2_QUAD_C_CTRL1r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_SET 14638 #define ANA_LANE_2_QUAD_C_CTRL1r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_GET 14639 #define ANA_LANE_2_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 14640 #define ANA_LANE_2_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 14641 #define ANA_LANE_2_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET 14642 #define ANA_LANE_2_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET 14643 #define ANA_LANE_2_QUAD_C_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_PWRDNf_GET 14644 #define ANA_LANE_2_QUAD_C_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_OCL_PWRDNf_SET 14645 #define ANA_LANE_2_QUAD_C_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_REF_OCLf_GET 14646 #define ANA_LANE_2_QUAD_C_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_REF_OCLf_SET 14647 #define ANA_LANE_2_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET 14648 #define ANA_LANE_2_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET 14649 #define READ_ANA_LANE_2_QUAD_C_CTRL1r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL1r 14650 #define WRITE_ANA_LANE_2_QUAD_C_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL1r 14651 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL1r 14652 14653 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14654 /******************************************************************************* 14655 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL1r' 14656 */ 14657 14658 14659 14660 14661 /******************************************************************************* 14662 * CHIP: BCMI_HURACAN 14663 * REGISTER: ANA_LANE_2_QUAD_C_CTRL2 14664 * BLOCKS: ANA_LANE_2_QUAD_C 14665 * REGADDR: 0xa402 14666 * DEVAD: 1 14667 * DESC: control registers 0 14668 * RESETVAL: 0x0 (0) 14669 * ACCESS: R/W 14670 * FIELDS: 14671 * CTLE_ENB_NEGIMP 14672 * CTLE_ENB_NEGCAP 14673 */ 14674 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r (0x0001a402 | PHYMOD_REG_ACC_RAW) 14675 14676 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_SIZE 4 14677 14678 /* 14679 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL2. 14680 */ 14681 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_s { 14682 uint32_t v[1]; 14683 uint32_t ana_lane_2_quad_c_ctrl2[1]; 14684 uint32_t _ana_lane_2_quad_c_ctrl2; 14685 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_t; 14686 14687 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CLR(r) (r).ana_lane_2_quad_c_ctrl2[0] = 0 14688 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_SET(r,d) (r).ana_lane_2_quad_c_ctrl2[0] = d 14689 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_GET(r) (r).ana_lane_2_quad_c_ctrl2[0] 14690 14691 /* 14692 * These macros can be used to access individual fields. 14693 */ 14694 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_2_quad_c_ctrl2[0]) >> 8) & 0x7f) 14695 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_2_quad_c_ctrl2[0]=(((r).ana_lane_2_quad_c_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 14696 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_2_quad_c_ctrl2[0]) & 0x7f) 14697 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_2_quad_c_ctrl2[0]=(((r).ana_lane_2_quad_c_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 14698 14699 /* 14700 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL2. 14701 */ 14702 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r,_r._ana_lane_2_quad_c_ctrl2) 14703 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r,_r._ana_lane_2_quad_c_ctrl2) 14704 14705 /* 14706 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14707 * will be redefined without the chip prefix for easier programming. 14708 * If multiple chips will be programmed in the same source file, then you should 14709 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14710 * and refer to the fully qualified versions. 14711 */ 14712 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14713 14714 #define ANA_LANE_2_QUAD_C_CTRL2r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r 14715 #define ANA_LANE_2_QUAD_C_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_SIZE 14716 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_t ANA_LANE_2_QUAD_C_CTRL2r_t; 14717 #define ANA_LANE_2_QUAD_C_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CLR 14718 #define ANA_LANE_2_QUAD_C_CTRL2r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_SET 14719 #define ANA_LANE_2_QUAD_C_CTRL2r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_GET 14720 #define ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET 14721 #define ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET 14722 #define ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET 14723 #define ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET 14724 #define READ_ANA_LANE_2_QUAD_C_CTRL2r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL2r 14725 #define WRITE_ANA_LANE_2_QUAD_C_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL2r 14726 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL2r 14727 14728 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14729 /******************************************************************************* 14730 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL2r' 14731 */ 14732 14733 14734 14735 14736 /******************************************************************************* 14737 * CHIP: BCMI_HURACAN 14738 * REGISTER: ANA_LANE_2_QUAD_C_CTRL3 14739 * BLOCKS: ANA_LANE_2_QUAD_C 14740 * REGADDR: 0xa403 14741 * DEVAD: 1 14742 * DESC: control registers 0 14743 * RESETVAL: 0x0 (0) 14744 * ACCESS: R/W 14745 * FIELDS: 14746 * CTLE_EN_NEGRES 14747 * CTLE_EQSEL 14748 */ 14749 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r (0x0001a403 | PHYMOD_REG_ACC_RAW) 14750 14751 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_SIZE 4 14752 14753 /* 14754 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL3. 14755 */ 14756 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_s { 14757 uint32_t v[1]; 14758 uint32_t ana_lane_2_quad_c_ctrl3[1]; 14759 uint32_t _ana_lane_2_quad_c_ctrl3; 14760 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_t; 14761 14762 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CLR(r) (r).ana_lane_2_quad_c_ctrl3[0] = 0 14763 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_SET(r,d) (r).ana_lane_2_quad_c_ctrl3[0] = d 14764 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_GET(r) (r).ana_lane_2_quad_c_ctrl3[0] 14765 14766 /* 14767 * These macros can be used to access individual fields. 14768 */ 14769 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_2_quad_c_ctrl3[0]) >> 8) & 0xff) 14770 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_2_quad_c_ctrl3[0]=(((r).ana_lane_2_quad_c_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 14771 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_2_quad_c_ctrl3[0]) & 0x7f) 14772 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_2_quad_c_ctrl3[0]=(((r).ana_lane_2_quad_c_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 14773 14774 /* 14775 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL3. 14776 */ 14777 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r,_r._ana_lane_2_quad_c_ctrl3) 14778 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r,_r._ana_lane_2_quad_c_ctrl3) 14779 14780 /* 14781 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14782 * will be redefined without the chip prefix for easier programming. 14783 * If multiple chips will be programmed in the same source file, then you should 14784 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14785 * and refer to the fully qualified versions. 14786 */ 14787 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14788 14789 #define ANA_LANE_2_QUAD_C_CTRL3r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r 14790 #define ANA_LANE_2_QUAD_C_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_SIZE 14791 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_t ANA_LANE_2_QUAD_C_CTRL3r_t; 14792 #define ANA_LANE_2_QUAD_C_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CLR 14793 #define ANA_LANE_2_QUAD_C_CTRL3r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_SET 14794 #define ANA_LANE_2_QUAD_C_CTRL3r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_GET 14795 #define ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EQSELf_GET 14796 #define ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EQSELf_SET 14797 #define ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET 14798 #define ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET 14799 #define READ_ANA_LANE_2_QUAD_C_CTRL3r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL3r 14800 #define WRITE_ANA_LANE_2_QUAD_C_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL3r 14801 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL3r 14802 14803 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14804 /******************************************************************************* 14805 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL3r' 14806 */ 14807 14808 14809 14810 14811 /******************************************************************************* 14812 * CHIP: BCMI_HURACAN 14813 * REGISTER: ANA_LANE_2_QUAD_C_CTRL4 14814 * BLOCKS: ANA_LANE_2_QUAD_C 14815 * REGADDR: 0xa404 14816 * DEVAD: 1 14817 * DESC: control registers 0 14818 * RESETVAL: 0x0 (0) 14819 * ACCESS: R/W 14820 * FIELDS: 14821 * CTLE_LZEN 14822 * RXTX_RESERVED_FOR_59_52 14823 */ 14824 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r (0x0001a404 | PHYMOD_REG_ACC_RAW) 14825 14826 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_SIZE 4 14827 14828 /* 14829 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL4. 14830 */ 14831 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_s { 14832 uint32_t v[1]; 14833 uint32_t ana_lane_2_quad_c_ctrl4[1]; 14834 uint32_t _ana_lane_2_quad_c_ctrl4; 14835 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_t; 14836 14837 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_CLR(r) (r).ana_lane_2_quad_c_ctrl4[0] = 0 14838 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_SET(r,d) (r).ana_lane_2_quad_c_ctrl4[0] = d 14839 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_GET(r) (r).ana_lane_2_quad_c_ctrl4[0] 14840 14841 /* 14842 * These macros can be used to access individual fields. 14843 */ 14844 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_2_quad_c_ctrl4[0]) >> 4) & 0xff) 14845 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_2_quad_c_ctrl4[0]=(((r).ana_lane_2_quad_c_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 14846 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_2_quad_c_ctrl4[0]) & 0x1) 14847 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_2_quad_c_ctrl4[0]=(((r).ana_lane_2_quad_c_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 14848 14849 /* 14850 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL4. 14851 */ 14852 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r,_r._ana_lane_2_quad_c_ctrl4) 14853 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r,_r._ana_lane_2_quad_c_ctrl4) 14854 14855 /* 14856 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14857 * will be redefined without the chip prefix for easier programming. 14858 * If multiple chips will be programmed in the same source file, then you should 14859 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14860 * and refer to the fully qualified versions. 14861 */ 14862 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14863 14864 #define ANA_LANE_2_QUAD_C_CTRL4r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r 14865 #define ANA_LANE_2_QUAD_C_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_SIZE 14866 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_t ANA_LANE_2_QUAD_C_CTRL4r_t; 14867 #define ANA_LANE_2_QUAD_C_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_CLR 14868 #define ANA_LANE_2_QUAD_C_CTRL4r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_SET 14869 #define ANA_LANE_2_QUAD_C_CTRL4r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_GET 14870 #define ANA_LANE_2_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 14871 #define ANA_LANE_2_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 14872 #define ANA_LANE_2_QUAD_C_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_CTLE_LZENf_GET 14873 #define ANA_LANE_2_QUAD_C_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r_CTLE_LZENf_SET 14874 #define READ_ANA_LANE_2_QUAD_C_CTRL4r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL4r 14875 #define WRITE_ANA_LANE_2_QUAD_C_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL4r 14876 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL4r 14877 14878 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14879 /******************************************************************************* 14880 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL4r' 14881 */ 14882 14883 14884 14885 14886 /******************************************************************************* 14887 * CHIP: BCMI_HURACAN 14888 * REGISTER: ANA_LANE_2_QUAD_C_CTRL5 14889 * BLOCKS: ANA_LANE_2_QUAD_C 14890 * REGADDR: 0xa405 14891 * DEVAD: 1 14892 * DESC: control registers 0 14893 * RESETVAL: 0x0 (0) 14894 * ACCESS: R/W 14895 * FIELDS: 14896 * CTLE_LOPEAKING 14897 * CTLE_PD 14898 * LA_GCTRL 14899 */ 14900 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r (0x0001a405 | PHYMOD_REG_ACC_RAW) 14901 14902 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_SIZE 4 14903 14904 /* 14905 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL5. 14906 */ 14907 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_s { 14908 uint32_t v[1]; 14909 uint32_t ana_lane_2_quad_c_ctrl5[1]; 14910 uint32_t _ana_lane_2_quad_c_ctrl5; 14911 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_t; 14912 14913 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CLR(r) (r).ana_lane_2_quad_c_ctrl5[0] = 0 14914 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_SET(r,d) (r).ana_lane_2_quad_c_ctrl5[0] = d 14915 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_GET(r) (r).ana_lane_2_quad_c_ctrl5[0] 14916 14917 /* 14918 * These macros can be used to access individual fields. 14919 */ 14920 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_2_quad_c_ctrl5[0]) >> 4) & 0x3ff) 14921 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_2_quad_c_ctrl5[0]=(((r).ana_lane_2_quad_c_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 14922 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_2_quad_c_ctrl5[0]) >> 1) & 0x1) 14923 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_2_quad_c_ctrl5[0]=(((r).ana_lane_2_quad_c_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 14924 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_2_quad_c_ctrl5[0]) & 0x1) 14925 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_2_quad_c_ctrl5[0]=(((r).ana_lane_2_quad_c_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 14926 14927 /* 14928 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL5. 14929 */ 14930 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r,_r._ana_lane_2_quad_c_ctrl5) 14931 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r,_r._ana_lane_2_quad_c_ctrl5) 14932 14933 /* 14934 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 14935 * will be redefined without the chip prefix for easier programming. 14936 * If multiple chips will be programmed in the same source file, then you should 14937 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 14938 * and refer to the fully qualified versions. 14939 */ 14940 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 14941 14942 #define ANA_LANE_2_QUAD_C_CTRL5r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r 14943 #define ANA_LANE_2_QUAD_C_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_SIZE 14944 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_t ANA_LANE_2_QUAD_C_CTRL5r_t; 14945 #define ANA_LANE_2_QUAD_C_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CLR 14946 #define ANA_LANE_2_QUAD_C_CTRL5r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_SET 14947 #define ANA_LANE_2_QUAD_C_CTRL5r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_GET 14948 #define ANA_LANE_2_QUAD_C_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_LA_GCTRLf_GET 14949 #define ANA_LANE_2_QUAD_C_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_LA_GCTRLf_SET 14950 #define ANA_LANE_2_QUAD_C_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_PDf_GET 14951 #define ANA_LANE_2_QUAD_C_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_PDf_SET 14952 #define ANA_LANE_2_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET 14953 #define ANA_LANE_2_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET 14954 #define READ_ANA_LANE_2_QUAD_C_CTRL5r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL5r 14955 #define WRITE_ANA_LANE_2_QUAD_C_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL5r 14956 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL5r 14957 14958 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 14959 /******************************************************************************* 14960 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL5r' 14961 */ 14962 14963 14964 14965 14966 /******************************************************************************* 14967 * CHIP: BCMI_HURACAN 14968 * REGISTER: ANA_LANE_2_QUAD_C_CTRL6 14969 * BLOCKS: ANA_LANE_2_QUAD_C 14970 * REGADDR: 0xa406 14971 * DEVAD: 1 14972 * DESC: control registers 0 14973 * RESETVAL: 0x0 (0) 14974 * ACCESS: R/W 14975 * FIELDS: 14976 * LA_DEGAIN 14977 * LA_DETUNE 14978 */ 14979 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r (0x0001a406 | PHYMOD_REG_ACC_RAW) 14980 14981 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_SIZE 4 14982 14983 /* 14984 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL6. 14985 */ 14986 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_s { 14987 uint32_t v[1]; 14988 uint32_t ana_lane_2_quad_c_ctrl6[1]; 14989 uint32_t _ana_lane_2_quad_c_ctrl6; 14990 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_t; 14991 14992 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_CLR(r) (r).ana_lane_2_quad_c_ctrl6[0] = 0 14993 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_SET(r,d) (r).ana_lane_2_quad_c_ctrl6[0] = d 14994 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_GET(r) (r).ana_lane_2_quad_c_ctrl6[0] 14995 14996 /* 14997 * These macros can be used to access individual fields. 14998 */ 14999 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_2_quad_c_ctrl6[0]) >> 8) & 0xff) 15000 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_2_quad_c_ctrl6[0]=(((r).ana_lane_2_quad_c_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 15001 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_2_quad_c_ctrl6[0]) & 0x1f) 15002 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_2_quad_c_ctrl6[0]=(((r).ana_lane_2_quad_c_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 15003 15004 /* 15005 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL6. 15006 */ 15007 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r,_r._ana_lane_2_quad_c_ctrl6) 15008 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r,_r._ana_lane_2_quad_c_ctrl6) 15009 15010 /* 15011 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15012 * will be redefined without the chip prefix for easier programming. 15013 * If multiple chips will be programmed in the same source file, then you should 15014 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15015 * and refer to the fully qualified versions. 15016 */ 15017 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15018 15019 #define ANA_LANE_2_QUAD_C_CTRL6r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r 15020 #define ANA_LANE_2_QUAD_C_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_SIZE 15021 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_t ANA_LANE_2_QUAD_C_CTRL6r_t; 15022 #define ANA_LANE_2_QUAD_C_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_CLR 15023 #define ANA_LANE_2_QUAD_C_CTRL6r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_SET 15024 #define ANA_LANE_2_QUAD_C_CTRL6r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_GET 15025 #define ANA_LANE_2_QUAD_C_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DETUNEf_GET 15026 #define ANA_LANE_2_QUAD_C_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DETUNEf_SET 15027 #define ANA_LANE_2_QUAD_C_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DEGAINf_GET 15028 #define ANA_LANE_2_QUAD_C_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r_LA_DEGAINf_SET 15029 #define READ_ANA_LANE_2_QUAD_C_CTRL6r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL6r 15030 #define WRITE_ANA_LANE_2_QUAD_C_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL6r 15031 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL6r 15032 15033 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15034 /******************************************************************************* 15035 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL6r' 15036 */ 15037 15038 15039 15040 15041 /******************************************************************************* 15042 * CHIP: BCMI_HURACAN 15043 * REGISTER: ANA_LANE_2_QUAD_C_CTRL7 15044 * BLOCKS: ANA_LANE_2_QUAD_C 15045 * REGADDR: 0xa407 15046 * DEVAD: 1 15047 * DESC: control registers 0 15048 * RESETVAL: 0x0 (0) 15049 * ACCESS: R/W 15050 * FIELDS: 15051 * LA_LIN_MODE 15052 * RX_BIAS_FB_PDN 15053 */ 15054 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r (0x0001a407 | PHYMOD_REG_ACC_RAW) 15055 15056 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_SIZE 4 15057 15058 /* 15059 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL7. 15060 */ 15061 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_s { 15062 uint32_t v[1]; 15063 uint32_t ana_lane_2_quad_c_ctrl7[1]; 15064 uint32_t _ana_lane_2_quad_c_ctrl7; 15065 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_t; 15066 15067 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_CLR(r) (r).ana_lane_2_quad_c_ctrl7[0] = 0 15068 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_SET(r,d) (r).ana_lane_2_quad_c_ctrl7[0] = d 15069 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_GET(r) (r).ana_lane_2_quad_c_ctrl7[0] 15070 15071 /* 15072 * These macros can be used to access individual fields. 15073 */ 15074 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_2_quad_c_ctrl7[0]) >> 8) & 0x1) 15075 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_2_quad_c_ctrl7[0]=(((r).ana_lane_2_quad_c_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 15076 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_2_quad_c_ctrl7[0]) & 0x1f) 15077 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_2_quad_c_ctrl7[0]=(((r).ana_lane_2_quad_c_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 15078 15079 /* 15080 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL7. 15081 */ 15082 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r,_r._ana_lane_2_quad_c_ctrl7) 15083 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r,_r._ana_lane_2_quad_c_ctrl7) 15084 15085 /* 15086 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15087 * will be redefined without the chip prefix for easier programming. 15088 * If multiple chips will be programmed in the same source file, then you should 15089 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15090 * and refer to the fully qualified versions. 15091 */ 15092 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15093 15094 #define ANA_LANE_2_QUAD_C_CTRL7r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r 15095 #define ANA_LANE_2_QUAD_C_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_SIZE 15096 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_t ANA_LANE_2_QUAD_C_CTRL7r_t; 15097 #define ANA_LANE_2_QUAD_C_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_CLR 15098 #define ANA_LANE_2_QUAD_C_CTRL7r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_SET 15099 #define ANA_LANE_2_QUAD_C_CTRL7r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_GET 15100 #define ANA_LANE_2_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET 15101 #define ANA_LANE_2_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET 15102 #define ANA_LANE_2_QUAD_C_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_LA_LIN_MODEf_GET 15103 #define ANA_LANE_2_QUAD_C_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r_LA_LIN_MODEf_SET 15104 #define READ_ANA_LANE_2_QUAD_C_CTRL7r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL7r 15105 #define WRITE_ANA_LANE_2_QUAD_C_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL7r 15106 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL7r 15107 15108 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15109 /******************************************************************************* 15110 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL7r' 15111 */ 15112 15113 15114 15115 15116 /******************************************************************************* 15117 * CHIP: BCMI_HURACAN 15118 * REGISTER: ANA_LANE_2_QUAD_C_CTRL8 15119 * BLOCKS: ANA_LANE_2_QUAD_C 15120 * REGADDR: 0xa408 15121 * DEVAD: 1 15122 * DESC: control registers 0 15123 * RESETVAL: 0x0 (0) 15124 * ACCESS: R/W 15125 * FIELDS: 15126 * LA_PD 15127 * LA_PD_IDLE 15128 * RXTX_RESERVED_FOR_99_95 15129 */ 15130 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r (0x0001a408 | PHYMOD_REG_ACC_RAW) 15131 15132 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_SIZE 4 15133 15134 /* 15135 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL8. 15136 */ 15137 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_s { 15138 uint32_t v[1]; 15139 uint32_t ana_lane_2_quad_c_ctrl8[1]; 15140 uint32_t _ana_lane_2_quad_c_ctrl8; 15141 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_t; 15142 15143 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_CLR(r) (r).ana_lane_2_quad_c_ctrl8[0] = 0 15144 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_SET(r,d) (r).ana_lane_2_quad_c_ctrl8[0] = d 15145 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_GET(r) (r).ana_lane_2_quad_c_ctrl8[0] 15146 15147 /* 15148 * These macros can be used to access individual fields. 15149 */ 15150 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_2_quad_c_ctrl8[0]) >> 4) & 0x1f) 15151 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_2_quad_c_ctrl8[0]=(((r).ana_lane_2_quad_c_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 15152 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_2_quad_c_ctrl8[0]) >> 1) & 0x1) 15153 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_2_quad_c_ctrl8[0]=(((r).ana_lane_2_quad_c_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 15154 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_2_quad_c_ctrl8[0]) & 0x1) 15155 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_2_quad_c_ctrl8[0]=(((r).ana_lane_2_quad_c_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 15156 15157 /* 15158 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL8. 15159 */ 15160 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r,_r._ana_lane_2_quad_c_ctrl8) 15161 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r,_r._ana_lane_2_quad_c_ctrl8) 15162 15163 /* 15164 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15165 * will be redefined without the chip prefix for easier programming. 15166 * If multiple chips will be programmed in the same source file, then you should 15167 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15168 * and refer to the fully qualified versions. 15169 */ 15170 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15171 15172 #define ANA_LANE_2_QUAD_C_CTRL8r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r 15173 #define ANA_LANE_2_QUAD_C_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_SIZE 15174 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_t ANA_LANE_2_QUAD_C_CTRL8r_t; 15175 #define ANA_LANE_2_QUAD_C_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_CLR 15176 #define ANA_LANE_2_QUAD_C_CTRL8r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_SET 15177 #define ANA_LANE_2_QUAD_C_CTRL8r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_GET 15178 #define ANA_LANE_2_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 15179 #define ANA_LANE_2_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 15180 #define ANA_LANE_2_QUAD_C_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PD_IDLEf_GET 15181 #define ANA_LANE_2_QUAD_C_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PD_IDLEf_SET 15182 #define ANA_LANE_2_QUAD_C_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PDf_GET 15183 #define ANA_LANE_2_QUAD_C_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r_LA_PDf_SET 15184 #define READ_ANA_LANE_2_QUAD_C_CTRL8r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL8r 15185 #define WRITE_ANA_LANE_2_QUAD_C_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL8r 15186 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL8r 15187 15188 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15189 /******************************************************************************* 15190 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL8r' 15191 */ 15192 15193 15194 15195 15196 /******************************************************************************* 15197 * CHIP: BCMI_HURACAN 15198 * REGISTER: ANA_LANE_2_QUAD_C_CTRL9 15199 * BLOCKS: ANA_LANE_2_QUAD_C 15200 * REGADDR: 0xa409 15201 * DEVAD: 1 15202 * DESC: control registers 0 15203 * RESETVAL: 0x0 (0) 15204 * ACCESS: R/W 15205 * FIELDS: 15206 * DRV_POST1 15207 * DLINE_SWING_1 15208 * DLINE_SWING_2 15209 * DLINE_DELAY_CTRL 15210 */ 15211 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r (0x0001a409 | PHYMOD_REG_ACC_RAW) 15212 15213 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_SIZE 4 15214 15215 /* 15216 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL9. 15217 */ 15218 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_s { 15219 uint32_t v[1]; 15220 uint32_t ana_lane_2_quad_c_ctrl9[1]; 15221 uint32_t _ana_lane_2_quad_c_ctrl9; 15222 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_t; 15223 15224 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_CLR(r) (r).ana_lane_2_quad_c_ctrl9[0] = 0 15225 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_SET(r,d) (r).ana_lane_2_quad_c_ctrl9[0] = d 15226 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_GET(r) (r).ana_lane_2_quad_c_ctrl9[0] 15227 15228 /* 15229 * These macros can be used to access individual fields. 15230 */ 15231 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_2_quad_c_ctrl9[0]) >> 12) & 0x7) 15232 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_2_quad_c_ctrl9[0]=(((r).ana_lane_2_quad_c_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 15233 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_2_quad_c_ctrl9[0]) >> 8) & 0x3) 15234 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_2_quad_c_ctrl9[0]=(((r).ana_lane_2_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 15235 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_2_quad_c_ctrl9[0]) >> 4) & 0x3) 15236 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_2_quad_c_ctrl9[0]=(((r).ana_lane_2_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 15237 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_2_quad_c_ctrl9[0]) & 0xf) 15238 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_2_quad_c_ctrl9[0]=(((r).ana_lane_2_quad_c_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 15239 15240 /* 15241 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL9. 15242 */ 15243 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r,_r._ana_lane_2_quad_c_ctrl9) 15244 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r,_r._ana_lane_2_quad_c_ctrl9) 15245 15246 /* 15247 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15248 * will be redefined without the chip prefix for easier programming. 15249 * If multiple chips will be programmed in the same source file, then you should 15250 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15251 * and refer to the fully qualified versions. 15252 */ 15253 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15254 15255 #define ANA_LANE_2_QUAD_C_CTRL9r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r 15256 #define ANA_LANE_2_QUAD_C_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_SIZE 15257 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_t ANA_LANE_2_QUAD_C_CTRL9r_t; 15258 #define ANA_LANE_2_QUAD_C_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_CLR 15259 #define ANA_LANE_2_QUAD_C_CTRL9r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_SET 15260 #define ANA_LANE_2_QUAD_C_CTRL9r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_GET 15261 #define ANA_LANE_2_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET 15262 #define ANA_LANE_2_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET 15263 #define ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_2f_GET 15264 #define ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_2f_SET 15265 #define ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_1f_GET 15266 #define ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DLINE_SWING_1f_SET 15267 #define ANA_LANE_2_QUAD_C_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DRV_POST1f_GET 15268 #define ANA_LANE_2_QUAD_C_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r_DRV_POST1f_SET 15269 #define READ_ANA_LANE_2_QUAD_C_CTRL9r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL9r 15270 #define WRITE_ANA_LANE_2_QUAD_C_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL9r 15271 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL9r 15272 15273 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15274 /******************************************************************************* 15275 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL9r' 15276 */ 15277 15278 15279 15280 15281 /******************************************************************************* 15282 * CHIP: BCMI_HURACAN 15283 * REGISTER: ANA_LANE_2_QUAD_C_CTRL10 15284 * BLOCKS: ANA_LANE_2_QUAD_C 15285 * REGADDR: 0xa40a 15286 * DEVAD: 1 15287 * DESC: control registers 0 15288 * RESETVAL: 0x0 (0) 15289 * ACCESS: R/W 15290 * FIELDS: 15291 * DRV_PWD 15292 * DLINE_PWD 15293 * DRV_VBSEL 15294 * DRV_MAIN 15295 * DRV_MAIN_PU 15296 */ 15297 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r (0x0001a40a | PHYMOD_REG_ACC_RAW) 15298 15299 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_SIZE 4 15300 15301 /* 15302 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL10. 15303 */ 15304 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_s { 15305 uint32_t v[1]; 15306 uint32_t ana_lane_2_quad_c_ctrl10[1]; 15307 uint32_t _ana_lane_2_quad_c_ctrl10; 15308 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_t; 15309 15310 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_CLR(r) (r).ana_lane_2_quad_c_ctrl10[0] = 0 15311 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_SET(r,d) (r).ana_lane_2_quad_c_ctrl10[0] = d 15312 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_GET(r) (r).ana_lane_2_quad_c_ctrl10[0] 15313 15314 /* 15315 * These macros can be used to access individual fields. 15316 */ 15317 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_2_quad_c_ctrl10[0]) >> 12) & 0xf) 15318 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_2_quad_c_ctrl10[0]=(((r).ana_lane_2_quad_c_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 15319 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_2_quad_c_ctrl10[0]) >> 4) & 0x3f) 15320 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_2_quad_c_ctrl10[0]=(((r).ana_lane_2_quad_c_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 15321 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_2_quad_c_ctrl10[0]) >> 2) & 0x1) 15322 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_2_quad_c_ctrl10[0]=(((r).ana_lane_2_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 15323 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_2_quad_c_ctrl10[0]) >> 1) & 0x1) 15324 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_2_quad_c_ctrl10[0]=(((r).ana_lane_2_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 15325 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_2_quad_c_ctrl10[0]) & 0x1) 15326 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_2_quad_c_ctrl10[0]=(((r).ana_lane_2_quad_c_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 15327 15328 /* 15329 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL10. 15330 */ 15331 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r,_r._ana_lane_2_quad_c_ctrl10) 15332 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r,_r._ana_lane_2_quad_c_ctrl10) 15333 15334 /* 15335 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15336 * will be redefined without the chip prefix for easier programming. 15337 * If multiple chips will be programmed in the same source file, then you should 15338 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15339 * and refer to the fully qualified versions. 15340 */ 15341 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15342 15343 #define ANA_LANE_2_QUAD_C_CTRL10r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r 15344 #define ANA_LANE_2_QUAD_C_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_SIZE 15345 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_t ANA_LANE_2_QUAD_C_CTRL10r_t; 15346 #define ANA_LANE_2_QUAD_C_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_CLR 15347 #define ANA_LANE_2_QUAD_C_CTRL10r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_SET 15348 #define ANA_LANE_2_QUAD_C_CTRL10r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_GET 15349 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET 15350 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET 15351 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAINf_GET 15352 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_MAINf_SET 15353 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_VBSELf_GET 15354 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_VBSELf_SET 15355 #define ANA_LANE_2_QUAD_C_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DLINE_PWDf_GET 15356 #define ANA_LANE_2_QUAD_C_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DLINE_PWDf_SET 15357 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_PWDf_GET 15358 #define ANA_LANE_2_QUAD_C_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r_DRV_PWDf_SET 15359 #define READ_ANA_LANE_2_QUAD_C_CTRL10r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL10r 15360 #define WRITE_ANA_LANE_2_QUAD_C_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL10r 15361 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL10r 15362 15363 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15364 /******************************************************************************* 15365 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL10r' 15366 */ 15367 15368 15369 15370 15371 /******************************************************************************* 15372 * CHIP: BCMI_HURACAN 15373 * REGISTER: ANA_LANE_2_QUAD_C_CTRL11 15374 * BLOCKS: ANA_LANE_2_QUAD_C 15375 * REGADDR: 0xa40b 15376 * DEVAD: 1 15377 * DESC: control registers 0 15378 * RESETVAL: 0x0 (0) 15379 * ACCESS: R/W 15380 * FIELDS: 15381 * RXTX_RESERVED_FOR_143_128 15382 */ 15383 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r (0x0001a40b | PHYMOD_REG_ACC_RAW) 15384 15385 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_SIZE 4 15386 15387 /* 15388 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL11. 15389 */ 15390 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_s { 15391 uint32_t v[1]; 15392 uint32_t ana_lane_2_quad_c_ctrl11[1]; 15393 uint32_t _ana_lane_2_quad_c_ctrl11; 15394 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_t; 15395 15396 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_CLR(r) (r).ana_lane_2_quad_c_ctrl11[0] = 0 15397 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_SET(r,d) (r).ana_lane_2_quad_c_ctrl11[0] = d 15398 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_GET(r) (r).ana_lane_2_quad_c_ctrl11[0] 15399 15400 /* 15401 * These macros can be used to access individual fields. 15402 */ 15403 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_2_quad_c_ctrl11[0]) & 0xffff) 15404 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_2_quad_c_ctrl11[0]=(((r).ana_lane_2_quad_c_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 15405 15406 /* 15407 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL11. 15408 */ 15409 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r,_r._ana_lane_2_quad_c_ctrl11) 15410 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r,_r._ana_lane_2_quad_c_ctrl11) 15411 15412 /* 15413 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15414 * will be redefined without the chip prefix for easier programming. 15415 * If multiple chips will be programmed in the same source file, then you should 15416 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15417 * and refer to the fully qualified versions. 15418 */ 15419 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15420 15421 #define ANA_LANE_2_QUAD_C_CTRL11r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r 15422 #define ANA_LANE_2_QUAD_C_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_SIZE 15423 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_t ANA_LANE_2_QUAD_C_CTRL11r_t; 15424 #define ANA_LANE_2_QUAD_C_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_CLR 15425 #define ANA_LANE_2_QUAD_C_CTRL11r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_SET 15426 #define ANA_LANE_2_QUAD_C_CTRL11r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_GET 15427 #define ANA_LANE_2_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 15428 #define ANA_LANE_2_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 15429 #define READ_ANA_LANE_2_QUAD_C_CTRL11r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL11r 15430 #define WRITE_ANA_LANE_2_QUAD_C_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL11r 15431 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL11r 15432 15433 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15434 /******************************************************************************* 15435 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL11r' 15436 */ 15437 15438 15439 15440 15441 /******************************************************************************* 15442 * CHIP: BCMI_HURACAN 15443 * REGISTER: ANA_LANE_2_QUAD_C_CTRL12 15444 * BLOCKS: ANA_LANE_2_QUAD_C 15445 * REGADDR: 0xa40c 15446 * DEVAD: 1 15447 * DESC: control registers 0 15448 * RESETVAL: 0x0 (0) 15449 * ACCESS: R/W 15450 * FIELDS: 15451 * LA_RESCAL_FRC_VAL 15452 * LA_RESCAL_FRC 15453 * DRV_RESCAL_FRC_VAL 15454 * DRV_RESCAL_FRC 15455 */ 15456 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r (0x0001a40c | PHYMOD_REG_ACC_RAW) 15457 15458 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_SIZE 4 15459 15460 /* 15461 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL12. 15462 */ 15463 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_s { 15464 uint32_t v[1]; 15465 uint32_t ana_lane_2_quad_c_ctrl12[1]; 15466 uint32_t _ana_lane_2_quad_c_ctrl12; 15467 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_t; 15468 15469 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_CLR(r) (r).ana_lane_2_quad_c_ctrl12[0] = 0 15470 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_SET(r,d) (r).ana_lane_2_quad_c_ctrl12[0] = d 15471 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_GET(r) (r).ana_lane_2_quad_c_ctrl12[0] 15472 15473 /* 15474 * These macros can be used to access individual fields. 15475 */ 15476 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_c_ctrl12[0]) >> 12) & 0x1) 15477 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_c_ctrl12[0]=(((r).ana_lane_2_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 15478 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_c_ctrl12[0]) >> 8) & 0xf) 15479 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_c_ctrl12[0]=(((r).ana_lane_2_quad_c_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 15480 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_c_ctrl12[0]) >> 4) & 0x1) 15481 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_c_ctrl12[0]=(((r).ana_lane_2_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 15482 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_c_ctrl12[0]) & 0xf) 15483 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_c_ctrl12[0]=(((r).ana_lane_2_quad_c_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 15484 15485 /* 15486 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL12. 15487 */ 15488 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r,_r._ana_lane_2_quad_c_ctrl12) 15489 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r,_r._ana_lane_2_quad_c_ctrl12) 15490 15491 /* 15492 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15493 * will be redefined without the chip prefix for easier programming. 15494 * If multiple chips will be programmed in the same source file, then you should 15495 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15496 * and refer to the fully qualified versions. 15497 */ 15498 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15499 15500 #define ANA_LANE_2_QUAD_C_CTRL12r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r 15501 #define ANA_LANE_2_QUAD_C_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_SIZE 15502 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_t ANA_LANE_2_QUAD_C_CTRL12r_t; 15503 #define ANA_LANE_2_QUAD_C_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_CLR 15504 #define ANA_LANE_2_QUAD_C_CTRL12r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_SET 15505 #define ANA_LANE_2_QUAD_C_CTRL12r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_GET 15506 #define ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET 15507 #define ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET 15508 #define ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET 15509 #define ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET 15510 #define ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET 15511 #define ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET 15512 #define ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET 15513 #define ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET 15514 #define READ_ANA_LANE_2_QUAD_C_CTRL12r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL12r 15515 #define WRITE_ANA_LANE_2_QUAD_C_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL12r 15516 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL12r 15517 15518 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15519 /******************************************************************************* 15520 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL12r' 15521 */ 15522 15523 15524 15525 15526 /******************************************************************************* 15527 * CHIP: BCMI_HURACAN 15528 * REGISTER: ANA_LANE_2_QUAD_C_CTRL13 15529 * BLOCKS: ANA_LANE_2_QUAD_C 15530 * REGADDR: 0xa40d 15531 * DEVAD: 1 15532 * DESC: control registers 0 15533 * RESETVAL: 0x0 (0) 15534 * ACCESS: R/W 15535 * FIELDS: 15536 * CTLE_RESCAL_FRC_VAL 15537 * CTLE_RESCAL_FRC 15538 */ 15539 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r (0x0001a40d | PHYMOD_REG_ACC_RAW) 15540 15541 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_SIZE 4 15542 15543 /* 15544 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL13. 15545 */ 15546 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_s { 15547 uint32_t v[1]; 15548 uint32_t ana_lane_2_quad_c_ctrl13[1]; 15549 uint32_t _ana_lane_2_quad_c_ctrl13; 15550 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_t; 15551 15552 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CLR(r) (r).ana_lane_2_quad_c_ctrl13[0] = 0 15553 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_SET(r,d) (r).ana_lane_2_quad_c_ctrl13[0] = d 15554 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_GET(r) (r).ana_lane_2_quad_c_ctrl13[0] 15555 15556 /* 15557 * These macros can be used to access individual fields. 15558 */ 15559 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_c_ctrl13[0]) >> 4) & 0x1) 15560 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_c_ctrl13[0]=(((r).ana_lane_2_quad_c_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 15561 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_c_ctrl13[0]) & 0xf) 15562 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_c_ctrl13[0]=(((r).ana_lane_2_quad_c_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 15563 15564 /* 15565 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL13. 15566 */ 15567 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r,_r._ana_lane_2_quad_c_ctrl13) 15568 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r,_r._ana_lane_2_quad_c_ctrl13) 15569 15570 /* 15571 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15572 * will be redefined without the chip prefix for easier programming. 15573 * If multiple chips will be programmed in the same source file, then you should 15574 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15575 * and refer to the fully qualified versions. 15576 */ 15577 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15578 15579 #define ANA_LANE_2_QUAD_C_CTRL13r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r 15580 #define ANA_LANE_2_QUAD_C_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_SIZE 15581 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_t ANA_LANE_2_QUAD_C_CTRL13r_t; 15582 #define ANA_LANE_2_QUAD_C_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CLR 15583 #define ANA_LANE_2_QUAD_C_CTRL13r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_SET 15584 #define ANA_LANE_2_QUAD_C_CTRL13r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_GET 15585 #define ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET 15586 #define ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET 15587 #define ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 15588 #define ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 15589 #define READ_ANA_LANE_2_QUAD_C_CTRL13r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL13r 15590 #define WRITE_ANA_LANE_2_QUAD_C_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL13r 15591 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL13r 15592 15593 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15594 /******************************************************************************* 15595 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL13r' 15596 */ 15597 15598 15599 15600 15601 /******************************************************************************* 15602 * CHIP: BCMI_HURACAN 15603 * REGISTER: ANA_LANE_2_QUAD_C_CTRL14 15604 * BLOCKS: ANA_LANE_2_QUAD_C 15605 * REGADDR: 0xa40e 15606 * DEVAD: 1 15607 * DESC: control registers 0 15608 * RESETVAL: 0x0 (0) 15609 * ACCESS: R/W 15610 * FIELDS: 15611 * TX_IDLE_FRC_VAL 15612 * TX_IDLE_FRC 15613 * RXSD_IDLE_OVRD 15614 */ 15615 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r (0x0001a40e | PHYMOD_REG_ACC_RAW) 15616 15617 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_SIZE 4 15618 15619 /* 15620 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL14. 15621 */ 15622 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_s { 15623 uint32_t v[1]; 15624 uint32_t ana_lane_2_quad_c_ctrl14[1]; 15625 uint32_t _ana_lane_2_quad_c_ctrl14; 15626 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_t; 15627 15628 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_CLR(r) (r).ana_lane_2_quad_c_ctrl14[0] = 0 15629 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_SET(r,d) (r).ana_lane_2_quad_c_ctrl14[0] = d 15630 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_GET(r) (r).ana_lane_2_quad_c_ctrl14[0] 15631 15632 /* 15633 * These macros can be used to access individual fields. 15634 */ 15635 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_2_quad_c_ctrl14[0]) >> 4) & 0x1) 15636 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_2_quad_c_ctrl14[0]=(((r).ana_lane_2_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 15637 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_2_quad_c_ctrl14[0]) >> 1) & 0x1) 15638 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_2_quad_c_ctrl14[0]=(((r).ana_lane_2_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 15639 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_2_quad_c_ctrl14[0]) & 0x1) 15640 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_c_ctrl14[0]=(((r).ana_lane_2_quad_c_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 15641 15642 /* 15643 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL14. 15644 */ 15645 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r,_r._ana_lane_2_quad_c_ctrl14) 15646 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r,_r._ana_lane_2_quad_c_ctrl14) 15647 15648 /* 15649 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15650 * will be redefined without the chip prefix for easier programming. 15651 * If multiple chips will be programmed in the same source file, then you should 15652 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15653 * and refer to the fully qualified versions. 15654 */ 15655 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15656 15657 #define ANA_LANE_2_QUAD_C_CTRL14r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r 15658 #define ANA_LANE_2_QUAD_C_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_SIZE 15659 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_t ANA_LANE_2_QUAD_C_CTRL14r_t; 15660 #define ANA_LANE_2_QUAD_C_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_CLR 15661 #define ANA_LANE_2_QUAD_C_CTRL14r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_SET 15662 #define ANA_LANE_2_QUAD_C_CTRL14r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_GET 15663 #define ANA_LANE_2_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET 15664 #define ANA_LANE_2_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET 15665 #define ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET 15666 #define ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET 15667 #define ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET 15668 #define ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET 15669 #define READ_ANA_LANE_2_QUAD_C_CTRL14r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL14r 15670 #define WRITE_ANA_LANE_2_QUAD_C_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL14r 15671 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL14r 15672 15673 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15674 /******************************************************************************* 15675 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL14r' 15676 */ 15677 15678 15679 15680 15681 /******************************************************************************* 15682 * CHIP: BCMI_HURACAN 15683 * REGISTER: ANA_LANE_2_QUAD_C_CTRL15 15684 * BLOCKS: ANA_LANE_2_QUAD_C 15685 * REGADDR: 0xa40f 15686 * DEVAD: 1 15687 * DESC: sigdet filter settings 0 15688 * RESETVAL: 0x0 (0) 15689 * ACCESS: R/W 15690 * FIELDS: 15691 * SIGDET_DIS 15692 * SIGDET_1US_EN 15693 * SIGDET_FRC_VAL 15694 * SIGDET_FRC 15695 * HOLD_LOS_COUNT 15696 * HOLD_SD_COUNT 15697 */ 15698 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r (0x0001a40f | PHYMOD_REG_ACC_RAW) 15699 15700 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIZE 4 15701 15702 /* 15703 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL15. 15704 */ 15705 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_s { 15706 uint32_t v[1]; 15707 uint32_t ana_lane_2_quad_c_ctrl15[1]; 15708 uint32_t _ana_lane_2_quad_c_ctrl15; 15709 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_t; 15710 15711 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_CLR(r) (r).ana_lane_2_quad_c_ctrl15[0] = 0 15712 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SET(r,d) (r).ana_lane_2_quad_c_ctrl15[0] = d 15713 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_GET(r) (r).ana_lane_2_quad_c_ctrl15[0] 15714 15715 /* 15716 * These macros can be used to access individual fields. 15717 */ 15718 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_c_ctrl15[0]) >> 8) & 0x7) 15719 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_c_ctrl15[0]=(((r).ana_lane_2_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 15720 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_2_quad_c_ctrl15[0]) >> 4) & 0x7) 15721 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_c_ctrl15[0]=(((r).ana_lane_2_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 15722 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_2_quad_c_ctrl15[0]) >> 3) & 0x1) 15723 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_2_quad_c_ctrl15[0]=(((r).ana_lane_2_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 15724 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_c_ctrl15[0]) >> 2) & 0x1) 15725 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_c_ctrl15[0]=(((r).ana_lane_2_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 15726 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_2_quad_c_ctrl15[0]) >> 1) & 0x1) 15727 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_2_quad_c_ctrl15[0]=(((r).ana_lane_2_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 15728 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_2_quad_c_ctrl15[0]) & 0x1) 15729 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_2_quad_c_ctrl15[0]=(((r).ana_lane_2_quad_c_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 15730 15731 /* 15732 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL15. 15733 */ 15734 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r,_r._ana_lane_2_quad_c_ctrl15) 15735 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r,_r._ana_lane_2_quad_c_ctrl15) 15736 15737 /* 15738 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15739 * will be redefined without the chip prefix for easier programming. 15740 * If multiple chips will be programmed in the same source file, then you should 15741 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15742 * and refer to the fully qualified versions. 15743 */ 15744 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15745 15746 #define ANA_LANE_2_QUAD_C_CTRL15r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r 15747 #define ANA_LANE_2_QUAD_C_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIZE 15748 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_t ANA_LANE_2_QUAD_C_CTRL15r_t; 15749 #define ANA_LANE_2_QUAD_C_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_CLR 15750 #define ANA_LANE_2_QUAD_C_CTRL15r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SET 15751 #define ANA_LANE_2_QUAD_C_CTRL15r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_GET 15752 #define ANA_LANE_2_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET 15753 #define ANA_LANE_2_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET 15754 #define ANA_LANE_2_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET 15755 #define ANA_LANE_2_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET 15756 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRCf_GET 15757 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRCf_SET 15758 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET 15759 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET 15760 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET 15761 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET 15762 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_DISf_GET 15763 #define ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r_SIGDET_DISf_SET 15764 #define READ_ANA_LANE_2_QUAD_C_CTRL15r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL15r 15765 #define WRITE_ANA_LANE_2_QUAD_C_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL15r 15766 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL15r 15767 15768 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15769 /******************************************************************************* 15770 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL15r' 15771 */ 15772 15773 15774 15775 15776 /******************************************************************************* 15777 * CHIP: BCMI_HURACAN 15778 * REGISTER: ANA_LANE_2_QUAD_C_CTRL16 15779 * BLOCKS: ANA_LANE_2_QUAD_C 15780 * REGADDR: 0xa410 15781 * DEVAD: 1 15782 * DESC: sigdet filter settings 1 15783 * RESETVAL: 0x0 (0) 15784 * ACCESS: R/W 15785 * FIELDS: 15786 * LOS_COUNT 15787 * SD_COUNT 15788 */ 15789 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r (0x0001a410 | PHYMOD_REG_ACC_RAW) 15790 15791 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SIZE 4 15792 15793 /* 15794 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_CTRL16. 15795 */ 15796 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_s { 15797 uint32_t v[1]; 15798 uint32_t ana_lane_2_quad_c_ctrl16[1]; 15799 uint32_t _ana_lane_2_quad_c_ctrl16; 15800 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_t; 15801 15802 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_CLR(r) (r).ana_lane_2_quad_c_ctrl16[0] = 0 15803 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SET(r,d) (r).ana_lane_2_quad_c_ctrl16[0] = d 15804 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_GET(r) (r).ana_lane_2_quad_c_ctrl16[0] 15805 15806 /* 15807 * These macros can be used to access individual fields. 15808 */ 15809 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_c_ctrl16[0]) >> 8) & 0x1f) 15810 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_c_ctrl16[0]=(((r).ana_lane_2_quad_c_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 15811 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_2_quad_c_ctrl16[0]) & 0x1f) 15812 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_c_ctrl16[0]=(((r).ana_lane_2_quad_c_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 15813 15814 /* 15815 * These macros can be used to access ANA_LANE_2_QUAD_C_CTRL16. 15816 */ 15817 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r,_r._ana_lane_2_quad_c_ctrl16) 15818 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r,_r._ana_lane_2_quad_c_ctrl16) 15819 15820 /* 15821 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15822 * will be redefined without the chip prefix for easier programming. 15823 * If multiple chips will be programmed in the same source file, then you should 15824 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15825 * and refer to the fully qualified versions. 15826 */ 15827 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15828 15829 #define ANA_LANE_2_QUAD_C_CTRL16r BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r 15830 #define ANA_LANE_2_QUAD_C_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SIZE 15831 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_t ANA_LANE_2_QUAD_C_CTRL16r_t; 15832 #define ANA_LANE_2_QUAD_C_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_CLR 15833 #define ANA_LANE_2_QUAD_C_CTRL16r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SET 15834 #define ANA_LANE_2_QUAD_C_CTRL16r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_GET 15835 #define ANA_LANE_2_QUAD_C_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SD_COUNTf_GET 15836 #define ANA_LANE_2_QUAD_C_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_SD_COUNTf_SET 15837 #define ANA_LANE_2_QUAD_C_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_LOS_COUNTf_GET 15838 #define ANA_LANE_2_QUAD_C_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r_LOS_COUNTf_SET 15839 #define READ_ANA_LANE_2_QUAD_C_CTRL16r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_CTRL16r 15840 #define WRITE_ANA_LANE_2_QUAD_C_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_CTRL16r 15841 #define MODIFY_ANA_LANE_2_QUAD_C_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_CTRL16r 15842 15843 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15844 /******************************************************************************* 15845 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_CTRL16r' 15846 */ 15847 15848 15849 15850 15851 /******************************************************************************* 15852 * CHIP: BCMI_HURACAN 15853 * REGISTER: ANA_LANE_2_QUAD_C_STATUS0 15854 * BLOCKS: ANA_LANE_2_QUAD_C 15855 * REGADDR: 0xa420 15856 * DEVAD: 1 15857 * DESC: status registers 0 15858 * RESETVAL: 0x0 (0) 15859 * ACCESS: R/W 15860 * FIELDS: 15861 * O_RX_SIGDET 15862 * DG_RX_SIGDET 15863 */ 15864 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r (0x0001a420 | PHYMOD_REG_ACC_RAW) 15865 15866 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_SIZE 4 15867 15868 /* 15869 * This structure should be used to declare and program ANA_LANE_2_QUAD_C_STATUS0. 15870 */ 15871 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_s { 15872 uint32_t v[1]; 15873 uint32_t ana_lane_2_quad_c_status0[1]; 15874 uint32_t _ana_lane_2_quad_c_status0; 15875 } BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_t; 15876 15877 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_CLR(r) (r).ana_lane_2_quad_c_status0[0] = 0 15878 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_SET(r,d) (r).ana_lane_2_quad_c_status0[0] = d 15879 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_GET(r) (r).ana_lane_2_quad_c_status0[0] 15880 15881 /* 15882 * These macros can be used to access individual fields. 15883 */ 15884 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_2_quad_c_status0[0]) >> 1) & 0x1) 15885 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_c_status0[0]=(((r).ana_lane_2_quad_c_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 15886 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_2_quad_c_status0[0]) & 0x1) 15887 #define BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_c_status0[0]=(((r).ana_lane_2_quad_c_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 15888 15889 /* 15890 * These macros can be used to access ANA_LANE_2_QUAD_C_STATUS0. 15891 */ 15892 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r,_r._ana_lane_2_quad_c_status0) 15893 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r,_r._ana_lane_2_quad_c_status0) 15894 15895 /* 15896 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15897 * will be redefined without the chip prefix for easier programming. 15898 * If multiple chips will be programmed in the same source file, then you should 15899 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15900 * and refer to the fully qualified versions. 15901 */ 15902 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15903 15904 #define ANA_LANE_2_QUAD_C_STATUS0r BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r 15905 #define ANA_LANE_2_QUAD_C_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_SIZE 15906 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_t ANA_LANE_2_QUAD_C_STATUS0r_t; 15907 #define ANA_LANE_2_QUAD_C_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_CLR 15908 #define ANA_LANE_2_QUAD_C_STATUS0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_SET 15909 #define ANA_LANE_2_QUAD_C_STATUS0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_GET 15910 #define ANA_LANE_2_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET 15911 #define ANA_LANE_2_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET 15912 #define ANA_LANE_2_QUAD_C_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_O_RX_SIGDETf_GET 15913 #define ANA_LANE_2_QUAD_C_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r_O_RX_SIGDETf_SET 15914 #define READ_ANA_LANE_2_QUAD_C_STATUS0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_C_STATUS0r 15915 #define WRITE_ANA_LANE_2_QUAD_C_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_C_STATUS0r 15916 #define MODIFY_ANA_LANE_2_QUAD_C_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_C_STATUS0r 15917 15918 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 15919 /******************************************************************************* 15920 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_C_STATUS0r' 15921 */ 15922 15923 15924 15925 15926 /******************************************************************************* 15927 * CHIP: BCMI_HURACAN 15928 * REGISTER: ANA_LANE_3_QUAD_C_CTRL0 15929 * BLOCKS: ANA_LANE_3_QUAD_C 15930 * REGADDR: 0xa800 15931 * DEVAD: 1 15932 * DESC: control registers 0 15933 * RESETVAL: 0x0 (0) 15934 * ACCESS: R/W 15935 * FIELDS: 15936 * RXTX_PWRDN 15937 * RX_SIGDET_BYPASS 15938 * RX_SIGDET_PWRDN 15939 * RX_SIGDECT_12GMODE 15940 * DC_COUPLE 15941 */ 15942 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r (0x0001a800 | PHYMOD_REG_ACC_RAW) 15943 15944 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_SIZE 4 15945 15946 /* 15947 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL0. 15948 */ 15949 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_s { 15950 uint32_t v[1]; 15951 uint32_t ana_lane_3_quad_c_ctrl0[1]; 15952 uint32_t _ana_lane_3_quad_c_ctrl0; 15953 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_t; 15954 15955 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_CLR(r) (r).ana_lane_3_quad_c_ctrl0[0] = 0 15956 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_SET(r,d) (r).ana_lane_3_quad_c_ctrl0[0] = d 15957 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_GET(r) (r).ana_lane_3_quad_c_ctrl0[0] 15958 15959 /* 15960 * These macros can be used to access individual fields. 15961 */ 15962 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_3_quad_c_ctrl0[0]) >> 4) & 0x1) 15963 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_3_quad_c_ctrl0[0]=(((r).ana_lane_3_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 15964 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_3_quad_c_ctrl0[0]) >> 3) & 0x1) 15965 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_3_quad_c_ctrl0[0]=(((r).ana_lane_3_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 15966 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_3_quad_c_ctrl0[0]) >> 2) & 0x1) 15967 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_3_quad_c_ctrl0[0]=(((r).ana_lane_3_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 15968 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_3_quad_c_ctrl0[0]) >> 1) & 0x1) 15969 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_3_quad_c_ctrl0[0]=(((r).ana_lane_3_quad_c_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 15970 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_3_quad_c_ctrl0[0]) & 0x1) 15971 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_3_quad_c_ctrl0[0]=(((r).ana_lane_3_quad_c_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 15972 15973 /* 15974 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL0. 15975 */ 15976 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r,_r._ana_lane_3_quad_c_ctrl0) 15977 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r,_r._ana_lane_3_quad_c_ctrl0) 15978 15979 /* 15980 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 15981 * will be redefined without the chip prefix for easier programming. 15982 * If multiple chips will be programmed in the same source file, then you should 15983 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 15984 * and refer to the fully qualified versions. 15985 */ 15986 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 15987 15988 #define ANA_LANE_3_QUAD_C_CTRL0r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r 15989 #define ANA_LANE_3_QUAD_C_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_SIZE 15990 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_t ANA_LANE_3_QUAD_C_CTRL0r_t; 15991 #define ANA_LANE_3_QUAD_C_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_CLR 15992 #define ANA_LANE_3_QUAD_C_CTRL0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_SET 15993 #define ANA_LANE_3_QUAD_C_CTRL0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_GET 15994 #define ANA_LANE_3_QUAD_C_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_DC_COUPLEf_GET 15995 #define ANA_LANE_3_QUAD_C_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_DC_COUPLEf_SET 15996 #define ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_GET 15997 #define ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDECT_12GMODEf_SET 15998 #define ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_GET 15999 #define ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_PWRDNf_SET 16000 #define ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_GET 16001 #define ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RX_SIGDET_BYPASSf_SET 16002 #define ANA_LANE_3_QUAD_C_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RXTX_PWRDNf_GET 16003 #define ANA_LANE_3_QUAD_C_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r_RXTX_PWRDNf_SET 16004 #define READ_ANA_LANE_3_QUAD_C_CTRL0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL0r 16005 #define WRITE_ANA_LANE_3_QUAD_C_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL0r 16006 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL0r 16007 16008 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16009 /******************************************************************************* 16010 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL0r' 16011 */ 16012 16013 16014 16015 16016 /******************************************************************************* 16017 * CHIP: BCMI_HURACAN 16018 * REGISTER: ANA_LANE_3_QUAD_C_CTRL1 16019 * BLOCKS: ANA_LANE_3_QUAD_C 16020 * REGADDR: 0xa801 16021 * DEVAD: 1 16022 * DESC: control registers 0 16023 * RESETVAL: 0x0 (0) 16024 * ACCESS: R/W 16025 * FIELDS: 16026 * RX_SIGDET_THRESHOLD 16027 * REF_OCL 16028 * OCL_PWRDN 16029 * OCL_DISABLE_LOOP 16030 * RXTX_RESERVED_FOR_15_12 16031 */ 16032 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r (0x0001a801 | PHYMOD_REG_ACC_RAW) 16033 16034 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_SIZE 4 16035 16036 /* 16037 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL1. 16038 */ 16039 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_s { 16040 uint32_t v[1]; 16041 uint32_t ana_lane_3_quad_c_ctrl1[1]; 16042 uint32_t _ana_lane_3_quad_c_ctrl1; 16043 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_t; 16044 16045 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_CLR(r) (r).ana_lane_3_quad_c_ctrl1[0] = 0 16046 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_SET(r,d) (r).ana_lane_3_quad_c_ctrl1[0] = d 16047 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_GET(r) (r).ana_lane_3_quad_c_ctrl1[0] 16048 16049 /* 16050 * These macros can be used to access individual fields. 16051 */ 16052 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_3_quad_c_ctrl1[0]) >> 12) & 0xf) 16053 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_3_quad_c_ctrl1[0]=(((r).ana_lane_3_quad_c_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 16054 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_3_quad_c_ctrl1[0]) >> 9) & 0x1) 16055 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_3_quad_c_ctrl1[0]=(((r).ana_lane_3_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 16056 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_3_quad_c_ctrl1[0]) >> 8) & 0x1) 16057 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_3_quad_c_ctrl1[0]=(((r).ana_lane_3_quad_c_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 16058 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_3_quad_c_ctrl1[0]) >> 4) & 0x3) 16059 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_3_quad_c_ctrl1[0]=(((r).ana_lane_3_quad_c_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 16060 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_3_quad_c_ctrl1[0]) & 0x7) 16061 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_3_quad_c_ctrl1[0]=(((r).ana_lane_3_quad_c_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 16062 16063 /* 16064 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL1. 16065 */ 16066 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r,_r._ana_lane_3_quad_c_ctrl1) 16067 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r,_r._ana_lane_3_quad_c_ctrl1) 16068 16069 /* 16070 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16071 * will be redefined without the chip prefix for easier programming. 16072 * If multiple chips will be programmed in the same source file, then you should 16073 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16074 * and refer to the fully qualified versions. 16075 */ 16076 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16077 16078 #define ANA_LANE_3_QUAD_C_CTRL1r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r 16079 #define ANA_LANE_3_QUAD_C_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_SIZE 16080 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_t ANA_LANE_3_QUAD_C_CTRL1r_t; 16081 #define ANA_LANE_3_QUAD_C_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_CLR 16082 #define ANA_LANE_3_QUAD_C_CTRL1r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_SET 16083 #define ANA_LANE_3_QUAD_C_CTRL1r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_GET 16084 #define ANA_LANE_3_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 16085 #define ANA_LANE_3_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 16086 #define ANA_LANE_3_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_GET 16087 #define ANA_LANE_3_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_DISABLE_LOOPf_SET 16088 #define ANA_LANE_3_QUAD_C_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_PWRDNf_GET 16089 #define ANA_LANE_3_QUAD_C_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_OCL_PWRDNf_SET 16090 #define ANA_LANE_3_QUAD_C_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_REF_OCLf_GET 16091 #define ANA_LANE_3_QUAD_C_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_REF_OCLf_SET 16092 #define ANA_LANE_3_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_GET 16093 #define ANA_LANE_3_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r_RX_SIGDET_THRESHOLDf_SET 16094 #define READ_ANA_LANE_3_QUAD_C_CTRL1r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL1r 16095 #define WRITE_ANA_LANE_3_QUAD_C_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL1r 16096 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL1r 16097 16098 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16099 /******************************************************************************* 16100 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL1r' 16101 */ 16102 16103 16104 16105 16106 /******************************************************************************* 16107 * CHIP: BCMI_HURACAN 16108 * REGISTER: ANA_LANE_3_QUAD_C_CTRL2 16109 * BLOCKS: ANA_LANE_3_QUAD_C 16110 * REGADDR: 0xa802 16111 * DEVAD: 1 16112 * DESC: control registers 0 16113 * RESETVAL: 0x0 (0) 16114 * ACCESS: R/W 16115 * FIELDS: 16116 * CTLE_ENB_NEGIMP 16117 * CTLE_ENB_NEGCAP 16118 */ 16119 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r (0x0001a802 | PHYMOD_REG_ACC_RAW) 16120 16121 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_SIZE 4 16122 16123 /* 16124 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL2. 16125 */ 16126 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_s { 16127 uint32_t v[1]; 16128 uint32_t ana_lane_3_quad_c_ctrl2[1]; 16129 uint32_t _ana_lane_3_quad_c_ctrl2; 16130 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_t; 16131 16132 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CLR(r) (r).ana_lane_3_quad_c_ctrl2[0] = 0 16133 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_SET(r,d) (r).ana_lane_3_quad_c_ctrl2[0] = d 16134 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_GET(r) (r).ana_lane_3_quad_c_ctrl2[0] 16135 16136 /* 16137 * These macros can be used to access individual fields. 16138 */ 16139 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_3_quad_c_ctrl2[0]) >> 8) & 0x7f) 16140 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_3_quad_c_ctrl2[0]=(((r).ana_lane_3_quad_c_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 16141 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_3_quad_c_ctrl2[0]) & 0x7f) 16142 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_3_quad_c_ctrl2[0]=(((r).ana_lane_3_quad_c_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 16143 16144 /* 16145 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL2. 16146 */ 16147 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r,_r._ana_lane_3_quad_c_ctrl2) 16148 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r,_r._ana_lane_3_quad_c_ctrl2) 16149 16150 /* 16151 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16152 * will be redefined without the chip prefix for easier programming. 16153 * If multiple chips will be programmed in the same source file, then you should 16154 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16155 * and refer to the fully qualified versions. 16156 */ 16157 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16158 16159 #define ANA_LANE_3_QUAD_C_CTRL2r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r 16160 #define ANA_LANE_3_QUAD_C_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_SIZE 16161 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_t ANA_LANE_3_QUAD_C_CTRL2r_t; 16162 #define ANA_LANE_3_QUAD_C_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CLR 16163 #define ANA_LANE_3_QUAD_C_CTRL2r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_SET 16164 #define ANA_LANE_3_QUAD_C_CTRL2r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_GET 16165 #define ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_GET 16166 #define ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGCAPf_SET 16167 #define ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_GET 16168 #define ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r_CTLE_ENB_NEGIMPf_SET 16169 #define READ_ANA_LANE_3_QUAD_C_CTRL2r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL2r 16170 #define WRITE_ANA_LANE_3_QUAD_C_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL2r 16171 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL2r 16172 16173 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16174 /******************************************************************************* 16175 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL2r' 16176 */ 16177 16178 16179 16180 16181 /******************************************************************************* 16182 * CHIP: BCMI_HURACAN 16183 * REGISTER: ANA_LANE_3_QUAD_C_CTRL3 16184 * BLOCKS: ANA_LANE_3_QUAD_C 16185 * REGADDR: 0xa803 16186 * DEVAD: 1 16187 * DESC: control registers 0 16188 * RESETVAL: 0x0 (0) 16189 * ACCESS: R/W 16190 * FIELDS: 16191 * CTLE_EN_NEGRES 16192 * CTLE_EQSEL 16193 */ 16194 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r (0x0001a803 | PHYMOD_REG_ACC_RAW) 16195 16196 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_SIZE 4 16197 16198 /* 16199 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL3. 16200 */ 16201 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_s { 16202 uint32_t v[1]; 16203 uint32_t ana_lane_3_quad_c_ctrl3[1]; 16204 uint32_t _ana_lane_3_quad_c_ctrl3; 16205 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_t; 16206 16207 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CLR(r) (r).ana_lane_3_quad_c_ctrl3[0] = 0 16208 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_SET(r,d) (r).ana_lane_3_quad_c_ctrl3[0] = d 16209 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_GET(r) (r).ana_lane_3_quad_c_ctrl3[0] 16210 16211 /* 16212 * These macros can be used to access individual fields. 16213 */ 16214 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_3_quad_c_ctrl3[0]) >> 8) & 0xff) 16215 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_3_quad_c_ctrl3[0]=(((r).ana_lane_3_quad_c_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 16216 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_3_quad_c_ctrl3[0]) & 0x7f) 16217 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_3_quad_c_ctrl3[0]=(((r).ana_lane_3_quad_c_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 16218 16219 /* 16220 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL3. 16221 */ 16222 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r,_r._ana_lane_3_quad_c_ctrl3) 16223 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r,_r._ana_lane_3_quad_c_ctrl3) 16224 16225 /* 16226 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16227 * will be redefined without the chip prefix for easier programming. 16228 * If multiple chips will be programmed in the same source file, then you should 16229 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16230 * and refer to the fully qualified versions. 16231 */ 16232 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16233 16234 #define ANA_LANE_3_QUAD_C_CTRL3r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r 16235 #define ANA_LANE_3_QUAD_C_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_SIZE 16236 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_t ANA_LANE_3_QUAD_C_CTRL3r_t; 16237 #define ANA_LANE_3_QUAD_C_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CLR 16238 #define ANA_LANE_3_QUAD_C_CTRL3r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_SET 16239 #define ANA_LANE_3_QUAD_C_CTRL3r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_GET 16240 #define ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EQSELf_GET 16241 #define ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EQSELf_SET 16242 #define ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_GET 16243 #define ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r_CTLE_EN_NEGRESf_SET 16244 #define READ_ANA_LANE_3_QUAD_C_CTRL3r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL3r 16245 #define WRITE_ANA_LANE_3_QUAD_C_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL3r 16246 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL3r 16247 16248 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16249 /******************************************************************************* 16250 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL3r' 16251 */ 16252 16253 16254 16255 16256 /******************************************************************************* 16257 * CHIP: BCMI_HURACAN 16258 * REGISTER: ANA_LANE_3_QUAD_C_CTRL4 16259 * BLOCKS: ANA_LANE_3_QUAD_C 16260 * REGADDR: 0xa804 16261 * DEVAD: 1 16262 * DESC: control registers 0 16263 * RESETVAL: 0x0 (0) 16264 * ACCESS: R/W 16265 * FIELDS: 16266 * CTLE_LZEN 16267 * RXTX_RESERVED_FOR_59_52 16268 */ 16269 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r (0x0001a804 | PHYMOD_REG_ACC_RAW) 16270 16271 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_SIZE 4 16272 16273 /* 16274 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL4. 16275 */ 16276 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_s { 16277 uint32_t v[1]; 16278 uint32_t ana_lane_3_quad_c_ctrl4[1]; 16279 uint32_t _ana_lane_3_quad_c_ctrl4; 16280 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_t; 16281 16282 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_CLR(r) (r).ana_lane_3_quad_c_ctrl4[0] = 0 16283 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_SET(r,d) (r).ana_lane_3_quad_c_ctrl4[0] = d 16284 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_GET(r) (r).ana_lane_3_quad_c_ctrl4[0] 16285 16286 /* 16287 * These macros can be used to access individual fields. 16288 */ 16289 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_3_quad_c_ctrl4[0]) >> 4) & 0xff) 16290 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_3_quad_c_ctrl4[0]=(((r).ana_lane_3_quad_c_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 16291 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_3_quad_c_ctrl4[0]) & 0x1) 16292 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_3_quad_c_ctrl4[0]=(((r).ana_lane_3_quad_c_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 16293 16294 /* 16295 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL4. 16296 */ 16297 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r,_r._ana_lane_3_quad_c_ctrl4) 16298 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r,_r._ana_lane_3_quad_c_ctrl4) 16299 16300 /* 16301 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16302 * will be redefined without the chip prefix for easier programming. 16303 * If multiple chips will be programmed in the same source file, then you should 16304 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16305 * and refer to the fully qualified versions. 16306 */ 16307 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16308 16309 #define ANA_LANE_3_QUAD_C_CTRL4r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r 16310 #define ANA_LANE_3_QUAD_C_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_SIZE 16311 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_t ANA_LANE_3_QUAD_C_CTRL4r_t; 16312 #define ANA_LANE_3_QUAD_C_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_CLR 16313 #define ANA_LANE_3_QUAD_C_CTRL4r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_SET 16314 #define ANA_LANE_3_QUAD_C_CTRL4r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_GET 16315 #define ANA_LANE_3_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 16316 #define ANA_LANE_3_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 16317 #define ANA_LANE_3_QUAD_C_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_CTLE_LZENf_GET 16318 #define ANA_LANE_3_QUAD_C_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r_CTLE_LZENf_SET 16319 #define READ_ANA_LANE_3_QUAD_C_CTRL4r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL4r 16320 #define WRITE_ANA_LANE_3_QUAD_C_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL4r 16321 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL4r 16322 16323 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16324 /******************************************************************************* 16325 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL4r' 16326 */ 16327 16328 16329 16330 16331 /******************************************************************************* 16332 * CHIP: BCMI_HURACAN 16333 * REGISTER: ANA_LANE_3_QUAD_C_CTRL5 16334 * BLOCKS: ANA_LANE_3_QUAD_C 16335 * REGADDR: 0xa805 16336 * DEVAD: 1 16337 * DESC: control registers 0 16338 * RESETVAL: 0x0 (0) 16339 * ACCESS: R/W 16340 * FIELDS: 16341 * CTLE_LOPEAKING 16342 * CTLE_PD 16343 * LA_GCTRL 16344 */ 16345 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r (0x0001a805 | PHYMOD_REG_ACC_RAW) 16346 16347 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_SIZE 4 16348 16349 /* 16350 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL5. 16351 */ 16352 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_s { 16353 uint32_t v[1]; 16354 uint32_t ana_lane_3_quad_c_ctrl5[1]; 16355 uint32_t _ana_lane_3_quad_c_ctrl5; 16356 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_t; 16357 16358 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CLR(r) (r).ana_lane_3_quad_c_ctrl5[0] = 0 16359 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_SET(r,d) (r).ana_lane_3_quad_c_ctrl5[0] = d 16360 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_GET(r) (r).ana_lane_3_quad_c_ctrl5[0] 16361 16362 /* 16363 * These macros can be used to access individual fields. 16364 */ 16365 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_3_quad_c_ctrl5[0]) >> 4) & 0x3ff) 16366 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_3_quad_c_ctrl5[0]=(((r).ana_lane_3_quad_c_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 16367 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_3_quad_c_ctrl5[0]) >> 1) & 0x1) 16368 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_3_quad_c_ctrl5[0]=(((r).ana_lane_3_quad_c_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 16369 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_3_quad_c_ctrl5[0]) & 0x1) 16370 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_3_quad_c_ctrl5[0]=(((r).ana_lane_3_quad_c_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 16371 16372 /* 16373 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL5. 16374 */ 16375 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r,_r._ana_lane_3_quad_c_ctrl5) 16376 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r,_r._ana_lane_3_quad_c_ctrl5) 16377 16378 /* 16379 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16380 * will be redefined without the chip prefix for easier programming. 16381 * If multiple chips will be programmed in the same source file, then you should 16382 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16383 * and refer to the fully qualified versions. 16384 */ 16385 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16386 16387 #define ANA_LANE_3_QUAD_C_CTRL5r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r 16388 #define ANA_LANE_3_QUAD_C_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_SIZE 16389 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_t ANA_LANE_3_QUAD_C_CTRL5r_t; 16390 #define ANA_LANE_3_QUAD_C_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CLR 16391 #define ANA_LANE_3_QUAD_C_CTRL5r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_SET 16392 #define ANA_LANE_3_QUAD_C_CTRL5r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_GET 16393 #define ANA_LANE_3_QUAD_C_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_LA_GCTRLf_GET 16394 #define ANA_LANE_3_QUAD_C_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_LA_GCTRLf_SET 16395 #define ANA_LANE_3_QUAD_C_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_PDf_GET 16396 #define ANA_LANE_3_QUAD_C_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_PDf_SET 16397 #define ANA_LANE_3_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_GET 16398 #define ANA_LANE_3_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r_CTLE_LOPEAKINGf_SET 16399 #define READ_ANA_LANE_3_QUAD_C_CTRL5r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL5r 16400 #define WRITE_ANA_LANE_3_QUAD_C_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL5r 16401 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL5r 16402 16403 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16404 /******************************************************************************* 16405 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL5r' 16406 */ 16407 16408 16409 16410 16411 /******************************************************************************* 16412 * CHIP: BCMI_HURACAN 16413 * REGISTER: ANA_LANE_3_QUAD_C_CTRL6 16414 * BLOCKS: ANA_LANE_3_QUAD_C 16415 * REGADDR: 0xa806 16416 * DEVAD: 1 16417 * DESC: control registers 0 16418 * RESETVAL: 0x0 (0) 16419 * ACCESS: R/W 16420 * FIELDS: 16421 * LA_DEGAIN 16422 * LA_DETUNE 16423 */ 16424 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r (0x0001a806 | PHYMOD_REG_ACC_RAW) 16425 16426 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_SIZE 4 16427 16428 /* 16429 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL6. 16430 */ 16431 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_s { 16432 uint32_t v[1]; 16433 uint32_t ana_lane_3_quad_c_ctrl6[1]; 16434 uint32_t _ana_lane_3_quad_c_ctrl6; 16435 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_t; 16436 16437 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_CLR(r) (r).ana_lane_3_quad_c_ctrl6[0] = 0 16438 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_SET(r,d) (r).ana_lane_3_quad_c_ctrl6[0] = d 16439 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_GET(r) (r).ana_lane_3_quad_c_ctrl6[0] 16440 16441 /* 16442 * These macros can be used to access individual fields. 16443 */ 16444 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_3_quad_c_ctrl6[0]) >> 8) & 0xff) 16445 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_3_quad_c_ctrl6[0]=(((r).ana_lane_3_quad_c_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 16446 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_3_quad_c_ctrl6[0]) & 0x1f) 16447 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_3_quad_c_ctrl6[0]=(((r).ana_lane_3_quad_c_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 16448 16449 /* 16450 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL6. 16451 */ 16452 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r,_r._ana_lane_3_quad_c_ctrl6) 16453 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r,_r._ana_lane_3_quad_c_ctrl6) 16454 16455 /* 16456 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16457 * will be redefined without the chip prefix for easier programming. 16458 * If multiple chips will be programmed in the same source file, then you should 16459 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16460 * and refer to the fully qualified versions. 16461 */ 16462 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16463 16464 #define ANA_LANE_3_QUAD_C_CTRL6r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r 16465 #define ANA_LANE_3_QUAD_C_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_SIZE 16466 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_t ANA_LANE_3_QUAD_C_CTRL6r_t; 16467 #define ANA_LANE_3_QUAD_C_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_CLR 16468 #define ANA_LANE_3_QUAD_C_CTRL6r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_SET 16469 #define ANA_LANE_3_QUAD_C_CTRL6r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_GET 16470 #define ANA_LANE_3_QUAD_C_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DETUNEf_GET 16471 #define ANA_LANE_3_QUAD_C_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DETUNEf_SET 16472 #define ANA_LANE_3_QUAD_C_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DEGAINf_GET 16473 #define ANA_LANE_3_QUAD_C_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r_LA_DEGAINf_SET 16474 #define READ_ANA_LANE_3_QUAD_C_CTRL6r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL6r 16475 #define WRITE_ANA_LANE_3_QUAD_C_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL6r 16476 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL6r 16477 16478 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16479 /******************************************************************************* 16480 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL6r' 16481 */ 16482 16483 16484 16485 16486 /******************************************************************************* 16487 * CHIP: BCMI_HURACAN 16488 * REGISTER: ANA_LANE_3_QUAD_C_CTRL7 16489 * BLOCKS: ANA_LANE_3_QUAD_C 16490 * REGADDR: 0xa807 16491 * DEVAD: 1 16492 * DESC: control registers 0 16493 * RESETVAL: 0x0 (0) 16494 * ACCESS: R/W 16495 * FIELDS: 16496 * LA_LIN_MODE 16497 * RX_BIAS_FB_PDN 16498 */ 16499 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r (0x0001a807 | PHYMOD_REG_ACC_RAW) 16500 16501 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_SIZE 4 16502 16503 /* 16504 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL7. 16505 */ 16506 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_s { 16507 uint32_t v[1]; 16508 uint32_t ana_lane_3_quad_c_ctrl7[1]; 16509 uint32_t _ana_lane_3_quad_c_ctrl7; 16510 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_t; 16511 16512 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_CLR(r) (r).ana_lane_3_quad_c_ctrl7[0] = 0 16513 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_SET(r,d) (r).ana_lane_3_quad_c_ctrl7[0] = d 16514 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_GET(r) (r).ana_lane_3_quad_c_ctrl7[0] 16515 16516 /* 16517 * These macros can be used to access individual fields. 16518 */ 16519 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_3_quad_c_ctrl7[0]) >> 8) & 0x1) 16520 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_3_quad_c_ctrl7[0]=(((r).ana_lane_3_quad_c_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 16521 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_3_quad_c_ctrl7[0]) & 0x1f) 16522 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_3_quad_c_ctrl7[0]=(((r).ana_lane_3_quad_c_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 16523 16524 /* 16525 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL7. 16526 */ 16527 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r,_r._ana_lane_3_quad_c_ctrl7) 16528 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r,_r._ana_lane_3_quad_c_ctrl7) 16529 16530 /* 16531 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16532 * will be redefined without the chip prefix for easier programming. 16533 * If multiple chips will be programmed in the same source file, then you should 16534 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16535 * and refer to the fully qualified versions. 16536 */ 16537 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16538 16539 #define ANA_LANE_3_QUAD_C_CTRL7r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r 16540 #define ANA_LANE_3_QUAD_C_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_SIZE 16541 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_t ANA_LANE_3_QUAD_C_CTRL7r_t; 16542 #define ANA_LANE_3_QUAD_C_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_CLR 16543 #define ANA_LANE_3_QUAD_C_CTRL7r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_SET 16544 #define ANA_LANE_3_QUAD_C_CTRL7r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_GET 16545 #define ANA_LANE_3_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_GET 16546 #define ANA_LANE_3_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_RX_BIAS_FB_PDNf_SET 16547 #define ANA_LANE_3_QUAD_C_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_LA_LIN_MODEf_GET 16548 #define ANA_LANE_3_QUAD_C_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r_LA_LIN_MODEf_SET 16549 #define READ_ANA_LANE_3_QUAD_C_CTRL7r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL7r 16550 #define WRITE_ANA_LANE_3_QUAD_C_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL7r 16551 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL7r 16552 16553 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16554 /******************************************************************************* 16555 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL7r' 16556 */ 16557 16558 16559 16560 16561 /******************************************************************************* 16562 * CHIP: BCMI_HURACAN 16563 * REGISTER: ANA_LANE_3_QUAD_C_CTRL8 16564 * BLOCKS: ANA_LANE_3_QUAD_C 16565 * REGADDR: 0xa808 16566 * DEVAD: 1 16567 * DESC: control registers 0 16568 * RESETVAL: 0x0 (0) 16569 * ACCESS: R/W 16570 * FIELDS: 16571 * LA_PD 16572 * LA_PD_IDLE 16573 * RXTX_RESERVED_FOR_99_95 16574 */ 16575 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r (0x0001a808 | PHYMOD_REG_ACC_RAW) 16576 16577 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_SIZE 4 16578 16579 /* 16580 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL8. 16581 */ 16582 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_s { 16583 uint32_t v[1]; 16584 uint32_t ana_lane_3_quad_c_ctrl8[1]; 16585 uint32_t _ana_lane_3_quad_c_ctrl8; 16586 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_t; 16587 16588 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_CLR(r) (r).ana_lane_3_quad_c_ctrl8[0] = 0 16589 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_SET(r,d) (r).ana_lane_3_quad_c_ctrl8[0] = d 16590 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_GET(r) (r).ana_lane_3_quad_c_ctrl8[0] 16591 16592 /* 16593 * These macros can be used to access individual fields. 16594 */ 16595 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_3_quad_c_ctrl8[0]) >> 4) & 0x1f) 16596 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_3_quad_c_ctrl8[0]=(((r).ana_lane_3_quad_c_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 16597 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_3_quad_c_ctrl8[0]) >> 1) & 0x1) 16598 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_3_quad_c_ctrl8[0]=(((r).ana_lane_3_quad_c_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 16599 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_3_quad_c_ctrl8[0]) & 0x1) 16600 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_3_quad_c_ctrl8[0]=(((r).ana_lane_3_quad_c_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 16601 16602 /* 16603 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL8. 16604 */ 16605 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r,_r._ana_lane_3_quad_c_ctrl8) 16606 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r,_r._ana_lane_3_quad_c_ctrl8) 16607 16608 /* 16609 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16610 * will be redefined without the chip prefix for easier programming. 16611 * If multiple chips will be programmed in the same source file, then you should 16612 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16613 * and refer to the fully qualified versions. 16614 */ 16615 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16616 16617 #define ANA_LANE_3_QUAD_C_CTRL8r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r 16618 #define ANA_LANE_3_QUAD_C_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_SIZE 16619 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_t ANA_LANE_3_QUAD_C_CTRL8r_t; 16620 #define ANA_LANE_3_QUAD_C_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_CLR 16621 #define ANA_LANE_3_QUAD_C_CTRL8r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_SET 16622 #define ANA_LANE_3_QUAD_C_CTRL8r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_GET 16623 #define ANA_LANE_3_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 16624 #define ANA_LANE_3_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 16625 #define ANA_LANE_3_QUAD_C_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PD_IDLEf_GET 16626 #define ANA_LANE_3_QUAD_C_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PD_IDLEf_SET 16627 #define ANA_LANE_3_QUAD_C_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PDf_GET 16628 #define ANA_LANE_3_QUAD_C_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r_LA_PDf_SET 16629 #define READ_ANA_LANE_3_QUAD_C_CTRL8r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL8r 16630 #define WRITE_ANA_LANE_3_QUAD_C_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL8r 16631 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL8r 16632 16633 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16634 /******************************************************************************* 16635 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL8r' 16636 */ 16637 16638 16639 16640 16641 /******************************************************************************* 16642 * CHIP: BCMI_HURACAN 16643 * REGISTER: ANA_LANE_3_QUAD_C_CTRL9 16644 * BLOCKS: ANA_LANE_3_QUAD_C 16645 * REGADDR: 0xa809 16646 * DEVAD: 1 16647 * DESC: control registers 0 16648 * RESETVAL: 0x0 (0) 16649 * ACCESS: R/W 16650 * FIELDS: 16651 * DRV_POST1 16652 * DLINE_SWING_1 16653 * DLINE_SWING_2 16654 * DLINE_DELAY_CTRL 16655 */ 16656 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r (0x0001a809 | PHYMOD_REG_ACC_RAW) 16657 16658 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_SIZE 4 16659 16660 /* 16661 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL9. 16662 */ 16663 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_s { 16664 uint32_t v[1]; 16665 uint32_t ana_lane_3_quad_c_ctrl9[1]; 16666 uint32_t _ana_lane_3_quad_c_ctrl9; 16667 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_t; 16668 16669 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_CLR(r) (r).ana_lane_3_quad_c_ctrl9[0] = 0 16670 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_SET(r,d) (r).ana_lane_3_quad_c_ctrl9[0] = d 16671 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_GET(r) (r).ana_lane_3_quad_c_ctrl9[0] 16672 16673 /* 16674 * These macros can be used to access individual fields. 16675 */ 16676 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_3_quad_c_ctrl9[0]) >> 12) & 0x7) 16677 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_3_quad_c_ctrl9[0]=(((r).ana_lane_3_quad_c_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 16678 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_3_quad_c_ctrl9[0]) >> 8) & 0x3) 16679 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_3_quad_c_ctrl9[0]=(((r).ana_lane_3_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 16680 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_3_quad_c_ctrl9[0]) >> 4) & 0x3) 16681 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_3_quad_c_ctrl9[0]=(((r).ana_lane_3_quad_c_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 16682 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_3_quad_c_ctrl9[0]) & 0xf) 16683 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_3_quad_c_ctrl9[0]=(((r).ana_lane_3_quad_c_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 16684 16685 /* 16686 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL9. 16687 */ 16688 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r,_r._ana_lane_3_quad_c_ctrl9) 16689 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r,_r._ana_lane_3_quad_c_ctrl9) 16690 16691 /* 16692 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16693 * will be redefined without the chip prefix for easier programming. 16694 * If multiple chips will be programmed in the same source file, then you should 16695 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16696 * and refer to the fully qualified versions. 16697 */ 16698 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16699 16700 #define ANA_LANE_3_QUAD_C_CTRL9r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r 16701 #define ANA_LANE_3_QUAD_C_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_SIZE 16702 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_t ANA_LANE_3_QUAD_C_CTRL9r_t; 16703 #define ANA_LANE_3_QUAD_C_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_CLR 16704 #define ANA_LANE_3_QUAD_C_CTRL9r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_SET 16705 #define ANA_LANE_3_QUAD_C_CTRL9r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_GET 16706 #define ANA_LANE_3_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_GET 16707 #define ANA_LANE_3_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_DELAY_CTRLf_SET 16708 #define ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_2f_GET 16709 #define ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_2f_SET 16710 #define ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_1f_GET 16711 #define ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DLINE_SWING_1f_SET 16712 #define ANA_LANE_3_QUAD_C_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DRV_POST1f_GET 16713 #define ANA_LANE_3_QUAD_C_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r_DRV_POST1f_SET 16714 #define READ_ANA_LANE_3_QUAD_C_CTRL9r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL9r 16715 #define WRITE_ANA_LANE_3_QUAD_C_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL9r 16716 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL9r 16717 16718 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16719 /******************************************************************************* 16720 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL9r' 16721 */ 16722 16723 16724 16725 16726 /******************************************************************************* 16727 * CHIP: BCMI_HURACAN 16728 * REGISTER: ANA_LANE_3_QUAD_C_CTRL10 16729 * BLOCKS: ANA_LANE_3_QUAD_C 16730 * REGADDR: 0xa80a 16731 * DEVAD: 1 16732 * DESC: control registers 0 16733 * RESETVAL: 0x0 (0) 16734 * ACCESS: R/W 16735 * FIELDS: 16736 * DRV_PWD 16737 * DLINE_PWD 16738 * DRV_VBSEL 16739 * DRV_MAIN 16740 * DRV_MAIN_PU 16741 */ 16742 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r (0x0001a80a | PHYMOD_REG_ACC_RAW) 16743 16744 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_SIZE 4 16745 16746 /* 16747 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL10. 16748 */ 16749 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_s { 16750 uint32_t v[1]; 16751 uint32_t ana_lane_3_quad_c_ctrl10[1]; 16752 uint32_t _ana_lane_3_quad_c_ctrl10; 16753 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_t; 16754 16755 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_CLR(r) (r).ana_lane_3_quad_c_ctrl10[0] = 0 16756 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_SET(r,d) (r).ana_lane_3_quad_c_ctrl10[0] = d 16757 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_GET(r) (r).ana_lane_3_quad_c_ctrl10[0] 16758 16759 /* 16760 * These macros can be used to access individual fields. 16761 */ 16762 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_3_quad_c_ctrl10[0]) >> 12) & 0xf) 16763 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_3_quad_c_ctrl10[0]=(((r).ana_lane_3_quad_c_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 16764 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_3_quad_c_ctrl10[0]) >> 4) & 0x3f) 16765 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_3_quad_c_ctrl10[0]=(((r).ana_lane_3_quad_c_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 16766 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_3_quad_c_ctrl10[0]) >> 2) & 0x1) 16767 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_3_quad_c_ctrl10[0]=(((r).ana_lane_3_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 16768 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_3_quad_c_ctrl10[0]) >> 1) & 0x1) 16769 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_3_quad_c_ctrl10[0]=(((r).ana_lane_3_quad_c_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 16770 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_3_quad_c_ctrl10[0]) & 0x1) 16771 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_3_quad_c_ctrl10[0]=(((r).ana_lane_3_quad_c_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 16772 16773 /* 16774 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL10. 16775 */ 16776 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r,_r._ana_lane_3_quad_c_ctrl10) 16777 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r,_r._ana_lane_3_quad_c_ctrl10) 16778 16779 /* 16780 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16781 * will be redefined without the chip prefix for easier programming. 16782 * If multiple chips will be programmed in the same source file, then you should 16783 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16784 * and refer to the fully qualified versions. 16785 */ 16786 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16787 16788 #define ANA_LANE_3_QUAD_C_CTRL10r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r 16789 #define ANA_LANE_3_QUAD_C_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_SIZE 16790 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_t ANA_LANE_3_QUAD_C_CTRL10r_t; 16791 #define ANA_LANE_3_QUAD_C_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_CLR 16792 #define ANA_LANE_3_QUAD_C_CTRL10r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_SET 16793 #define ANA_LANE_3_QUAD_C_CTRL10r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_GET 16794 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAIN_PUf_GET 16795 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAIN_PUf_SET 16796 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAINf_GET 16797 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_MAINf_SET 16798 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_VBSELf_GET 16799 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_VBSELf_SET 16800 #define ANA_LANE_3_QUAD_C_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DLINE_PWDf_GET 16801 #define ANA_LANE_3_QUAD_C_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DLINE_PWDf_SET 16802 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_PWDf_GET 16803 #define ANA_LANE_3_QUAD_C_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r_DRV_PWDf_SET 16804 #define READ_ANA_LANE_3_QUAD_C_CTRL10r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL10r 16805 #define WRITE_ANA_LANE_3_QUAD_C_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL10r 16806 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL10r 16807 16808 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16809 /******************************************************************************* 16810 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL10r' 16811 */ 16812 16813 16814 16815 16816 /******************************************************************************* 16817 * CHIP: BCMI_HURACAN 16818 * REGISTER: ANA_LANE_3_QUAD_C_CTRL11 16819 * BLOCKS: ANA_LANE_3_QUAD_C 16820 * REGADDR: 0xa80b 16821 * DEVAD: 1 16822 * DESC: control registers 0 16823 * RESETVAL: 0x0 (0) 16824 * ACCESS: R/W 16825 * FIELDS: 16826 * RXTX_RESERVED_FOR_143_128 16827 */ 16828 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r (0x0001a80b | PHYMOD_REG_ACC_RAW) 16829 16830 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_SIZE 4 16831 16832 /* 16833 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL11. 16834 */ 16835 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_s { 16836 uint32_t v[1]; 16837 uint32_t ana_lane_3_quad_c_ctrl11[1]; 16838 uint32_t _ana_lane_3_quad_c_ctrl11; 16839 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_t; 16840 16841 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_CLR(r) (r).ana_lane_3_quad_c_ctrl11[0] = 0 16842 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_SET(r,d) (r).ana_lane_3_quad_c_ctrl11[0] = d 16843 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_GET(r) (r).ana_lane_3_quad_c_ctrl11[0] 16844 16845 /* 16846 * These macros can be used to access individual fields. 16847 */ 16848 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_3_quad_c_ctrl11[0]) & 0xffff) 16849 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_3_quad_c_ctrl11[0]=(((r).ana_lane_3_quad_c_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 16850 16851 /* 16852 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL11. 16853 */ 16854 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r,_r._ana_lane_3_quad_c_ctrl11) 16855 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r,_r._ana_lane_3_quad_c_ctrl11) 16856 16857 /* 16858 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16859 * will be redefined without the chip prefix for easier programming. 16860 * If multiple chips will be programmed in the same source file, then you should 16861 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16862 * and refer to the fully qualified versions. 16863 */ 16864 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16865 16866 #define ANA_LANE_3_QUAD_C_CTRL11r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r 16867 #define ANA_LANE_3_QUAD_C_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_SIZE 16868 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_t ANA_LANE_3_QUAD_C_CTRL11r_t; 16869 #define ANA_LANE_3_QUAD_C_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_CLR 16870 #define ANA_LANE_3_QUAD_C_CTRL11r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_SET 16871 #define ANA_LANE_3_QUAD_C_CTRL11r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_GET 16872 #define ANA_LANE_3_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 16873 #define ANA_LANE_3_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 16874 #define READ_ANA_LANE_3_QUAD_C_CTRL11r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL11r 16875 #define WRITE_ANA_LANE_3_QUAD_C_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL11r 16876 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL11r 16877 16878 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16879 /******************************************************************************* 16880 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL11r' 16881 */ 16882 16883 16884 16885 16886 /******************************************************************************* 16887 * CHIP: BCMI_HURACAN 16888 * REGISTER: ANA_LANE_3_QUAD_C_CTRL12 16889 * BLOCKS: ANA_LANE_3_QUAD_C 16890 * REGADDR: 0xa80c 16891 * DEVAD: 1 16892 * DESC: control registers 0 16893 * RESETVAL: 0x0 (0) 16894 * ACCESS: R/W 16895 * FIELDS: 16896 * LA_RESCAL_FRC_VAL 16897 * LA_RESCAL_FRC 16898 * DRV_RESCAL_FRC_VAL 16899 * DRV_RESCAL_FRC 16900 */ 16901 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r (0x0001a80c | PHYMOD_REG_ACC_RAW) 16902 16903 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_SIZE 4 16904 16905 /* 16906 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL12. 16907 */ 16908 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_s { 16909 uint32_t v[1]; 16910 uint32_t ana_lane_3_quad_c_ctrl12[1]; 16911 uint32_t _ana_lane_3_quad_c_ctrl12; 16912 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_t; 16913 16914 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_CLR(r) (r).ana_lane_3_quad_c_ctrl12[0] = 0 16915 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_SET(r,d) (r).ana_lane_3_quad_c_ctrl12[0] = d 16916 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_GET(r) (r).ana_lane_3_quad_c_ctrl12[0] 16917 16918 /* 16919 * These macros can be used to access individual fields. 16920 */ 16921 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_c_ctrl12[0]) >> 12) & 0x1) 16922 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_c_ctrl12[0]=(((r).ana_lane_3_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 16923 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_c_ctrl12[0]) >> 8) & 0xf) 16924 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_c_ctrl12[0]=(((r).ana_lane_3_quad_c_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 16925 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_c_ctrl12[0]) >> 4) & 0x1) 16926 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_c_ctrl12[0]=(((r).ana_lane_3_quad_c_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 16927 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_c_ctrl12[0]) & 0xf) 16928 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_c_ctrl12[0]=(((r).ana_lane_3_quad_c_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 16929 16930 /* 16931 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL12. 16932 */ 16933 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r,_r._ana_lane_3_quad_c_ctrl12) 16934 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r,_r._ana_lane_3_quad_c_ctrl12) 16935 16936 /* 16937 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 16938 * will be redefined without the chip prefix for easier programming. 16939 * If multiple chips will be programmed in the same source file, then you should 16940 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 16941 * and refer to the fully qualified versions. 16942 */ 16943 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 16944 16945 #define ANA_LANE_3_QUAD_C_CTRL12r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r 16946 #define ANA_LANE_3_QUAD_C_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_SIZE 16947 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_t ANA_LANE_3_QUAD_C_CTRL12r_t; 16948 #define ANA_LANE_3_QUAD_C_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_CLR 16949 #define ANA_LANE_3_QUAD_C_CTRL12r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_SET 16950 #define ANA_LANE_3_QUAD_C_CTRL12r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_GET 16951 #define ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_GET 16952 #define ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRCf_SET 16953 #define ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_GET 16954 #define ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_DRV_RESCAL_FRC_VALf_SET 16955 #define ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRCf_GET 16956 #define ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRCf_SET 16957 #define ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_GET 16958 #define ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r_LA_RESCAL_FRC_VALf_SET 16959 #define READ_ANA_LANE_3_QUAD_C_CTRL12r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL12r 16960 #define WRITE_ANA_LANE_3_QUAD_C_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL12r 16961 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL12r 16962 16963 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 16964 /******************************************************************************* 16965 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL12r' 16966 */ 16967 16968 16969 16970 16971 /******************************************************************************* 16972 * CHIP: BCMI_HURACAN 16973 * REGISTER: ANA_LANE_3_QUAD_C_CTRL13 16974 * BLOCKS: ANA_LANE_3_QUAD_C 16975 * REGADDR: 0xa80d 16976 * DEVAD: 1 16977 * DESC: control registers 0 16978 * RESETVAL: 0x0 (0) 16979 * ACCESS: R/W 16980 * FIELDS: 16981 * CTLE_RESCAL_FRC_VAL 16982 * CTLE_RESCAL_FRC 16983 */ 16984 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r (0x0001a80d | PHYMOD_REG_ACC_RAW) 16985 16986 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_SIZE 4 16987 16988 /* 16989 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL13. 16990 */ 16991 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_s { 16992 uint32_t v[1]; 16993 uint32_t ana_lane_3_quad_c_ctrl13[1]; 16994 uint32_t _ana_lane_3_quad_c_ctrl13; 16995 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_t; 16996 16997 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CLR(r) (r).ana_lane_3_quad_c_ctrl13[0] = 0 16998 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_SET(r,d) (r).ana_lane_3_quad_c_ctrl13[0] = d 16999 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_GET(r) (r).ana_lane_3_quad_c_ctrl13[0] 17000 17001 /* 17002 * These macros can be used to access individual fields. 17003 */ 17004 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_c_ctrl13[0]) >> 4) & 0x1) 17005 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_c_ctrl13[0]=(((r).ana_lane_3_quad_c_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 17006 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_c_ctrl13[0]) & 0xf) 17007 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_c_ctrl13[0]=(((r).ana_lane_3_quad_c_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 17008 17009 /* 17010 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL13. 17011 */ 17012 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r,_r._ana_lane_3_quad_c_ctrl13) 17013 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r,_r._ana_lane_3_quad_c_ctrl13) 17014 17015 /* 17016 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17017 * will be redefined without the chip prefix for easier programming. 17018 * If multiple chips will be programmed in the same source file, then you should 17019 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17020 * and refer to the fully qualified versions. 17021 */ 17022 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17023 17024 #define ANA_LANE_3_QUAD_C_CTRL13r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r 17025 #define ANA_LANE_3_QUAD_C_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_SIZE 17026 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_t ANA_LANE_3_QUAD_C_CTRL13r_t; 17027 #define ANA_LANE_3_QUAD_C_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CLR 17028 #define ANA_LANE_3_QUAD_C_CTRL13r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_SET 17029 #define ANA_LANE_3_QUAD_C_CTRL13r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_GET 17030 #define ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_GET 17031 #define ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRCf_SET 17032 #define ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 17033 #define ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 17034 #define READ_ANA_LANE_3_QUAD_C_CTRL13r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL13r 17035 #define WRITE_ANA_LANE_3_QUAD_C_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL13r 17036 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL13r 17037 17038 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17039 /******************************************************************************* 17040 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL13r' 17041 */ 17042 17043 17044 17045 17046 /******************************************************************************* 17047 * CHIP: BCMI_HURACAN 17048 * REGISTER: ANA_LANE_3_QUAD_C_CTRL14 17049 * BLOCKS: ANA_LANE_3_QUAD_C 17050 * REGADDR: 0xa80e 17051 * DEVAD: 1 17052 * DESC: control registers 0 17053 * RESETVAL: 0x0 (0) 17054 * ACCESS: R/W 17055 * FIELDS: 17056 * TX_IDLE_FRC_VAL 17057 * TX_IDLE_FRC 17058 * RXSD_IDLE_OVRD 17059 */ 17060 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r (0x0001a80e | PHYMOD_REG_ACC_RAW) 17061 17062 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_SIZE 4 17063 17064 /* 17065 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL14. 17066 */ 17067 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_s { 17068 uint32_t v[1]; 17069 uint32_t ana_lane_3_quad_c_ctrl14[1]; 17070 uint32_t _ana_lane_3_quad_c_ctrl14; 17071 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_t; 17072 17073 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_CLR(r) (r).ana_lane_3_quad_c_ctrl14[0] = 0 17074 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_SET(r,d) (r).ana_lane_3_quad_c_ctrl14[0] = d 17075 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_GET(r) (r).ana_lane_3_quad_c_ctrl14[0] 17076 17077 /* 17078 * These macros can be used to access individual fields. 17079 */ 17080 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_3_quad_c_ctrl14[0]) >> 4) & 0x1) 17081 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_3_quad_c_ctrl14[0]=(((r).ana_lane_3_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 17082 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_3_quad_c_ctrl14[0]) >> 1) & 0x1) 17083 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_3_quad_c_ctrl14[0]=(((r).ana_lane_3_quad_c_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 17084 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_3_quad_c_ctrl14[0]) & 0x1) 17085 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_c_ctrl14[0]=(((r).ana_lane_3_quad_c_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17086 17087 /* 17088 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL14. 17089 */ 17090 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r,_r._ana_lane_3_quad_c_ctrl14) 17091 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r,_r._ana_lane_3_quad_c_ctrl14) 17092 17093 /* 17094 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17095 * will be redefined without the chip prefix for easier programming. 17096 * If multiple chips will be programmed in the same source file, then you should 17097 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17098 * and refer to the fully qualified versions. 17099 */ 17100 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17101 17102 #define ANA_LANE_3_QUAD_C_CTRL14r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r 17103 #define ANA_LANE_3_QUAD_C_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_SIZE 17104 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_t ANA_LANE_3_QUAD_C_CTRL14r_t; 17105 #define ANA_LANE_3_QUAD_C_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_CLR 17106 #define ANA_LANE_3_QUAD_C_CTRL14r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_SET 17107 #define ANA_LANE_3_QUAD_C_CTRL14r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_GET 17108 #define ANA_LANE_3_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_GET 17109 #define ANA_LANE_3_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_RXSD_IDLE_OVRDf_SET 17110 #define ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRCf_GET 17111 #define ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRCf_SET 17112 #define ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_GET 17113 #define ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r_TX_IDLE_FRC_VALf_SET 17114 #define READ_ANA_LANE_3_QUAD_C_CTRL14r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL14r 17115 #define WRITE_ANA_LANE_3_QUAD_C_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL14r 17116 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL14r 17117 17118 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17119 /******************************************************************************* 17120 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL14r' 17121 */ 17122 17123 17124 17125 17126 /******************************************************************************* 17127 * CHIP: BCMI_HURACAN 17128 * REGISTER: ANA_LANE_3_QUAD_C_CTRL15 17129 * BLOCKS: ANA_LANE_3_QUAD_C 17130 * REGADDR: 0xa80f 17131 * DEVAD: 1 17132 * DESC: sigdet filter settings 0 17133 * RESETVAL: 0x0 (0) 17134 * ACCESS: R/W 17135 * FIELDS: 17136 * SIGDET_DIS 17137 * SIGDET_1US_EN 17138 * SIGDET_FRC_VAL 17139 * SIGDET_FRC 17140 * HOLD_LOS_COUNT 17141 * HOLD_SD_COUNT 17142 */ 17143 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r (0x0001a80f | PHYMOD_REG_ACC_RAW) 17144 17145 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIZE 4 17146 17147 /* 17148 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL15. 17149 */ 17150 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_s { 17151 uint32_t v[1]; 17152 uint32_t ana_lane_3_quad_c_ctrl15[1]; 17153 uint32_t _ana_lane_3_quad_c_ctrl15; 17154 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_t; 17155 17156 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_CLR(r) (r).ana_lane_3_quad_c_ctrl15[0] = 0 17157 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SET(r,d) (r).ana_lane_3_quad_c_ctrl15[0] = d 17158 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_GET(r) (r).ana_lane_3_quad_c_ctrl15[0] 17159 17160 /* 17161 * These macros can be used to access individual fields. 17162 */ 17163 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_c_ctrl15[0]) >> 8) & 0x7) 17164 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_c_ctrl15[0]=(((r).ana_lane_3_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 17165 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_3_quad_c_ctrl15[0]) >> 4) & 0x7) 17166 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_c_ctrl15[0]=(((r).ana_lane_3_quad_c_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 17167 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_3_quad_c_ctrl15[0]) >> 3) & 0x1) 17168 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_3_quad_c_ctrl15[0]=(((r).ana_lane_3_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 17169 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_c_ctrl15[0]) >> 2) & 0x1) 17170 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_c_ctrl15[0]=(((r).ana_lane_3_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 17171 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_3_quad_c_ctrl15[0]) >> 1) & 0x1) 17172 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_3_quad_c_ctrl15[0]=(((r).ana_lane_3_quad_c_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 17173 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_3_quad_c_ctrl15[0]) & 0x1) 17174 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_3_quad_c_ctrl15[0]=(((r).ana_lane_3_quad_c_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17175 17176 /* 17177 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL15. 17178 */ 17179 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r,_r._ana_lane_3_quad_c_ctrl15) 17180 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r,_r._ana_lane_3_quad_c_ctrl15) 17181 17182 /* 17183 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17184 * will be redefined without the chip prefix for easier programming. 17185 * If multiple chips will be programmed in the same source file, then you should 17186 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17187 * and refer to the fully qualified versions. 17188 */ 17189 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17190 17191 #define ANA_LANE_3_QUAD_C_CTRL15r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r 17192 #define ANA_LANE_3_QUAD_C_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIZE 17193 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_t ANA_LANE_3_QUAD_C_CTRL15r_t; 17194 #define ANA_LANE_3_QUAD_C_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_CLR 17195 #define ANA_LANE_3_QUAD_C_CTRL15r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SET 17196 #define ANA_LANE_3_QUAD_C_CTRL15r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_GET 17197 #define ANA_LANE_3_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_SD_COUNTf_GET 17198 #define ANA_LANE_3_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_SD_COUNTf_SET 17199 #define ANA_LANE_3_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_GET 17200 #define ANA_LANE_3_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_HOLD_LOS_COUNTf_SET 17201 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRCf_GET 17202 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRCf_SET 17203 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRC_VALf_GET 17204 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_FRC_VALf_SET 17205 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_1US_ENf_GET 17206 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_1US_ENf_SET 17207 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_DISf_GET 17208 #define ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r_SIGDET_DISf_SET 17209 #define READ_ANA_LANE_3_QUAD_C_CTRL15r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL15r 17210 #define WRITE_ANA_LANE_3_QUAD_C_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL15r 17211 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL15r 17212 17213 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17214 /******************************************************************************* 17215 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL15r' 17216 */ 17217 17218 17219 17220 17221 /******************************************************************************* 17222 * CHIP: BCMI_HURACAN 17223 * REGISTER: ANA_LANE_3_QUAD_C_CTRL16 17224 * BLOCKS: ANA_LANE_3_QUAD_C 17225 * REGADDR: 0xa810 17226 * DEVAD: 1 17227 * DESC: sigdet filter settings 1 17228 * RESETVAL: 0x0 (0) 17229 * ACCESS: R/W 17230 * FIELDS: 17231 * LOS_COUNT 17232 * SD_COUNT 17233 */ 17234 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r (0x0001a810 | PHYMOD_REG_ACC_RAW) 17235 17236 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SIZE 4 17237 17238 /* 17239 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_CTRL16. 17240 */ 17241 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_s { 17242 uint32_t v[1]; 17243 uint32_t ana_lane_3_quad_c_ctrl16[1]; 17244 uint32_t _ana_lane_3_quad_c_ctrl16; 17245 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_t; 17246 17247 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_CLR(r) (r).ana_lane_3_quad_c_ctrl16[0] = 0 17248 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SET(r,d) (r).ana_lane_3_quad_c_ctrl16[0] = d 17249 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_GET(r) (r).ana_lane_3_quad_c_ctrl16[0] 17250 17251 /* 17252 * These macros can be used to access individual fields. 17253 */ 17254 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_c_ctrl16[0]) >> 8) & 0x1f) 17255 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_c_ctrl16[0]=(((r).ana_lane_3_quad_c_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 17256 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_3_quad_c_ctrl16[0]) & 0x1f) 17257 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_c_ctrl16[0]=(((r).ana_lane_3_quad_c_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 17258 17259 /* 17260 * These macros can be used to access ANA_LANE_3_QUAD_C_CTRL16. 17261 */ 17262 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r,_r._ana_lane_3_quad_c_ctrl16) 17263 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r,_r._ana_lane_3_quad_c_ctrl16) 17264 17265 /* 17266 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17267 * will be redefined without the chip prefix for easier programming. 17268 * If multiple chips will be programmed in the same source file, then you should 17269 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17270 * and refer to the fully qualified versions. 17271 */ 17272 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17273 17274 #define ANA_LANE_3_QUAD_C_CTRL16r BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r 17275 #define ANA_LANE_3_QUAD_C_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SIZE 17276 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_t ANA_LANE_3_QUAD_C_CTRL16r_t; 17277 #define ANA_LANE_3_QUAD_C_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_CLR 17278 #define ANA_LANE_3_QUAD_C_CTRL16r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SET 17279 #define ANA_LANE_3_QUAD_C_CTRL16r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_GET 17280 #define ANA_LANE_3_QUAD_C_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SD_COUNTf_GET 17281 #define ANA_LANE_3_QUAD_C_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_SD_COUNTf_SET 17282 #define ANA_LANE_3_QUAD_C_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_LOS_COUNTf_GET 17283 #define ANA_LANE_3_QUAD_C_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r_LOS_COUNTf_SET 17284 #define READ_ANA_LANE_3_QUAD_C_CTRL16r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_CTRL16r 17285 #define WRITE_ANA_LANE_3_QUAD_C_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_CTRL16r 17286 #define MODIFY_ANA_LANE_3_QUAD_C_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_CTRL16r 17287 17288 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17289 /******************************************************************************* 17290 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_CTRL16r' 17291 */ 17292 17293 17294 17295 17296 /******************************************************************************* 17297 * CHIP: BCMI_HURACAN 17298 * REGISTER: ANA_LANE_3_QUAD_C_STATUS0 17299 * BLOCKS: ANA_LANE_3_QUAD_C 17300 * REGADDR: 0xa820 17301 * DEVAD: 1 17302 * DESC: status registers 0 17303 * RESETVAL: 0x0 (0) 17304 * ACCESS: R/W 17305 * FIELDS: 17306 * O_RX_SIGDET 17307 * DG_RX_SIGDET 17308 */ 17309 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r (0x0001a820 | PHYMOD_REG_ACC_RAW) 17310 17311 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_SIZE 4 17312 17313 /* 17314 * This structure should be used to declare and program ANA_LANE_3_QUAD_C_STATUS0. 17315 */ 17316 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_s { 17317 uint32_t v[1]; 17318 uint32_t ana_lane_3_quad_c_status0[1]; 17319 uint32_t _ana_lane_3_quad_c_status0; 17320 } BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_t; 17321 17322 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_CLR(r) (r).ana_lane_3_quad_c_status0[0] = 0 17323 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_SET(r,d) (r).ana_lane_3_quad_c_status0[0] = d 17324 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_GET(r) (r).ana_lane_3_quad_c_status0[0] 17325 17326 /* 17327 * These macros can be used to access individual fields. 17328 */ 17329 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_3_quad_c_status0[0]) >> 1) & 0x1) 17330 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_c_status0[0]=(((r).ana_lane_3_quad_c_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 17331 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_3_quad_c_status0[0]) & 0x1) 17332 #define BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_c_status0[0]=(((r).ana_lane_3_quad_c_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17333 17334 /* 17335 * These macros can be used to access ANA_LANE_3_QUAD_C_STATUS0. 17336 */ 17337 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r,_r._ana_lane_3_quad_c_status0) 17338 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r,_r._ana_lane_3_quad_c_status0) 17339 17340 /* 17341 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17342 * will be redefined without the chip prefix for easier programming. 17343 * If multiple chips will be programmed in the same source file, then you should 17344 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17345 * and refer to the fully qualified versions. 17346 */ 17347 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17348 17349 #define ANA_LANE_3_QUAD_C_STATUS0r BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r 17350 #define ANA_LANE_3_QUAD_C_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_SIZE 17351 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_t ANA_LANE_3_QUAD_C_STATUS0r_t; 17352 #define ANA_LANE_3_QUAD_C_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_CLR 17353 #define ANA_LANE_3_QUAD_C_STATUS0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_SET 17354 #define ANA_LANE_3_QUAD_C_STATUS0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_GET 17355 #define ANA_LANE_3_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_DG_RX_SIGDETf_GET 17356 #define ANA_LANE_3_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_DG_RX_SIGDETf_SET 17357 #define ANA_LANE_3_QUAD_C_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_O_RX_SIGDETf_GET 17358 #define ANA_LANE_3_QUAD_C_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r_O_RX_SIGDETf_SET 17359 #define READ_ANA_LANE_3_QUAD_C_STATUS0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_C_STATUS0r 17360 #define WRITE_ANA_LANE_3_QUAD_C_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_C_STATUS0r 17361 #define MODIFY_ANA_LANE_3_QUAD_C_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_C_STATUS0r 17362 17363 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17364 /******************************************************************************* 17365 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_C_STATUS0r' 17366 */ 17367 17368 17369 17370 17371 /******************************************************************************* 17372 * CHIP: BCMI_HURACAN 17373 * REGISTER: CHIP_ID 17374 * BLOCKS: CTRL_QUAD_D 17375 * REGADDR: 0xb000 17376 * DEVAD: 1 17377 * DESC: Chip ID for Huracan 17378 * RESETVAL: 0x0 (0) 17379 * ACCESS: R/W 17380 * FIELDS: 17381 * CHIP_ID_15_0 17382 */ 17383 #define BCMI_HURACAN_CHIP_IDr (0x0001b000 | PHYMOD_REG_ACC_RAW) 17384 17385 #define BCMI_HURACAN_CHIP_IDr_SIZE 4 17386 17387 /* 17388 * This structure should be used to declare and program CHIP_ID. 17389 */ 17390 typedef union BCMI_HURACAN_CHIP_IDr_s { 17391 uint32_t v[1]; 17392 uint32_t chip_id[1]; 17393 uint32_t _chip_id; 17394 } BCMI_HURACAN_CHIP_IDr_t; 17395 17396 #define BCMI_HURACAN_CHIP_IDr_CLR(r) (r).chip_id[0] = 0 17397 #define BCMI_HURACAN_CHIP_IDr_SET(r,d) (r).chip_id[0] = d 17398 #define BCMI_HURACAN_CHIP_IDr_GET(r) (r).chip_id[0] 17399 17400 /* 17401 * These macros can be used to access individual fields. 17402 */ 17403 #define BCMI_HURACAN_CHIP_IDr_CHIP_ID_15_0f_GET(r) (((r).chip_id[0]) & 0xffff) 17404 #define BCMI_HURACAN_CHIP_IDr_CHIP_ID_15_0f_SET(r,f) (r).chip_id[0]=(((r).chip_id[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 17405 17406 /* 17407 * These macros can be used to access CHIP_ID. 17408 */ 17409 #define BCMI_HURACAN_READ_CHIP_IDr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_CHIP_IDr,_r._chip_id) 17410 #define BCMI_HURACAN_WRITE_CHIP_IDr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_CHIP_IDr,_r._chip_id) 17411 17412 /* 17413 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17414 * will be redefined without the chip prefix for easier programming. 17415 * If multiple chips will be programmed in the same source file, then you should 17416 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17417 * and refer to the fully qualified versions. 17418 */ 17419 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17420 17421 #define CHIP_IDr BCMI_HURACAN_CHIP_IDr 17422 #define CHIP_IDr_SIZE BCMI_HURACAN_CHIP_IDr_SIZE 17423 typedef BCMI_HURACAN_CHIP_IDr_t CHIP_IDr_t; 17424 #define CHIP_IDr_CLR BCMI_HURACAN_CHIP_IDr_CLR 17425 #define CHIP_IDr_SET BCMI_HURACAN_CHIP_IDr_SET 17426 #define CHIP_IDr_GET BCMI_HURACAN_CHIP_IDr_GET 17427 #define CHIP_IDr_CHIP_ID_15_0f_GET BCMI_HURACAN_CHIP_IDr_CHIP_ID_15_0f_GET 17428 #define CHIP_IDr_CHIP_ID_15_0f_SET BCMI_HURACAN_CHIP_IDr_CHIP_ID_15_0f_SET 17429 #define READ_CHIP_IDr BCMI_HURACAN_READ_CHIP_IDr 17430 #define WRITE_CHIP_IDr BCMI_HURACAN_WRITE_CHIP_IDr 17431 #define MODIFY_CHIP_IDr BCMI_HURACAN_MODIFY_CHIP_IDr 17432 17433 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17434 /******************************************************************************* 17435 * End of 'BCMI_HURACAN_CHIP_IDr' 17436 */ 17437 17438 17439 17440 17441 /******************************************************************************* 17442 * CHIP: BCMI_HURACAN 17443 * REGISTER: CHIP_REVISION 17444 * BLOCKS: CTRL_QUAD_D 17445 * REGADDR: 0xb001 17446 * DEVAD: 1 17447 * DESC: Rev ID for Huracan 17448 * RESETVAL: 0x0 (0) 17449 * ACCESS: R/W 17450 * FIELDS: 17451 * CHIP_REV 17452 * CHIP_ID_19_16 17453 */ 17454 #define BCMI_HURACAN_CHIP_REVISIONr (0x0001b001 | PHYMOD_REG_ACC_RAW) 17455 17456 #define BCMI_HURACAN_CHIP_REVISIONr_SIZE 4 17457 17458 /* 17459 * This structure should be used to declare and program CHIP_REVISION. 17460 */ 17461 typedef union BCMI_HURACAN_CHIP_REVISIONr_s { 17462 uint32_t v[1]; 17463 uint32_t chip_revision[1]; 17464 uint32_t _chip_revision; 17465 } BCMI_HURACAN_CHIP_REVISIONr_t; 17466 17467 #define BCMI_HURACAN_CHIP_REVISIONr_CLR(r) (r).chip_revision[0] = 0 17468 #define BCMI_HURACAN_CHIP_REVISIONr_SET(r,d) (r).chip_revision[0] = d 17469 #define BCMI_HURACAN_CHIP_REVISIONr_GET(r) (r).chip_revision[0] 17470 17471 /* 17472 * These macros can be used to access individual fields. 17473 */ 17474 #define BCMI_HURACAN_CHIP_REVISIONr_CHIP_ID_19_16f_GET(r) ((((r).chip_revision[0]) >> 12) & 0xf) 17475 #define BCMI_HURACAN_CHIP_REVISIONr_CHIP_ID_19_16f_SET(r,f) (r).chip_revision[0]=(((r).chip_revision[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 17476 #define BCMI_HURACAN_CHIP_REVISIONr_CHIP_REVf_GET(r) (((r).chip_revision[0]) & 0xff) 17477 #define BCMI_HURACAN_CHIP_REVISIONr_CHIP_REVf_SET(r,f) (r).chip_revision[0]=(((r).chip_revision[0] & ~((uint32_t)0xff)) | (((uint32_t)f) & 0xff)) | (0xff << 16) 17478 17479 /* 17480 * These macros can be used to access CHIP_REVISION. 17481 */ 17482 #define BCMI_HURACAN_READ_CHIP_REVISIONr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_CHIP_REVISIONr,_r._chip_revision) 17483 #define BCMI_HURACAN_WRITE_CHIP_REVISIONr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_CHIP_REVISIONr,_r._chip_revision) 17484 17485 /* 17486 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17487 * will be redefined without the chip prefix for easier programming. 17488 * If multiple chips will be programmed in the same source file, then you should 17489 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17490 * and refer to the fully qualified versions. 17491 */ 17492 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17493 17494 #define CHIP_REVISIONr BCMI_HURACAN_CHIP_REVISIONr 17495 #define CHIP_REVISIONr_SIZE BCMI_HURACAN_CHIP_REVISIONr_SIZE 17496 typedef BCMI_HURACAN_CHIP_REVISIONr_t CHIP_REVISIONr_t; 17497 #define CHIP_REVISIONr_CLR BCMI_HURACAN_CHIP_REVISIONr_CLR 17498 #define CHIP_REVISIONr_SET BCMI_HURACAN_CHIP_REVISIONr_SET 17499 #define CHIP_REVISIONr_GET BCMI_HURACAN_CHIP_REVISIONr_GET 17500 #define CHIP_REVISIONr_CHIP_ID_19_16f_GET BCMI_HURACAN_CHIP_REVISIONr_CHIP_ID_19_16f_GET 17501 #define CHIP_REVISIONr_CHIP_ID_19_16f_SET BCMI_HURACAN_CHIP_REVISIONr_CHIP_ID_19_16f_SET 17502 #define CHIP_REVISIONr_CHIP_REVf_GET BCMI_HURACAN_CHIP_REVISIONr_CHIP_REVf_GET 17503 #define CHIP_REVISIONr_CHIP_REVf_SET BCMI_HURACAN_CHIP_REVISIONr_CHIP_REVf_SET 17504 #define READ_CHIP_REVISIONr BCMI_HURACAN_READ_CHIP_REVISIONr 17505 #define WRITE_CHIP_REVISIONr BCMI_HURACAN_WRITE_CHIP_REVISIONr 17506 #define MODIFY_CHIP_REVISIONr BCMI_HURACAN_MODIFY_CHIP_REVISIONr 17507 17508 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17509 /******************************************************************************* 17510 * End of 'BCMI_HURACAN_CHIP_REVISIONr' 17511 */ 17512 17513 17514 17515 17516 /******************************************************************************* 17517 * CHIP: BCMI_HURACAN 17518 * REGISTER: GEN_CONTROL1 17519 * BLOCKS: CTRL_QUAD_D 17520 * REGADDR: 0xb002 17521 * DEVAD: 1 17522 * DESC: General control register 1. 17523 * RESETVAL: 0x0 (0) 17524 * ACCESS: R/W 17525 * FIELDS: 17526 * RESETB 17527 * ARB_RSTB 17528 * RESCAL_RSTB 17529 * RESCAL_RSTB_SC 17530 * OTP_RSTB 17531 * PVTMON_RSTB 17532 * REG_RSTB 17533 */ 17534 #define BCMI_HURACAN_GEN_CONTROL1r (0x00018002 | PHYMOD_REG_ACC_RAW) 17535 17536 #define BCMI_HURACAN_GEN_CONTROL1r_SIZE 4 17537 17538 /* 17539 * This structure should be used to declare and program GEN_CONTROL1. 17540 */ 17541 typedef union BCMI_HURACAN_GEN_CONTROL1r_s { 17542 uint32_t v[1]; 17543 uint32_t gen_control1[1]; 17544 uint32_t _gen_control1; 17545 } BCMI_HURACAN_GEN_CONTROL1r_t; 17546 17547 #define BCMI_HURACAN_GEN_CONTROL1r_CLR(r) (r).gen_control1[0] = 0 17548 #define BCMI_HURACAN_GEN_CONTROL1r_SET(r,d) (r).gen_control1[0] = d 17549 #define BCMI_HURACAN_GEN_CONTROL1r_GET(r) (r).gen_control1[0] 17550 17551 /* 17552 * These macros can be used to access individual fields. 17553 */ 17554 #define BCMI_HURACAN_GEN_CONTROL1r_REG_RSTBf_GET(r) ((((r).gen_control1[0]) >> 6) & 0x1) 17555 #define BCMI_HURACAN_GEN_CONTROL1r_REG_RSTBf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) | (1 << (16 + 6)) 17556 #define BCMI_HURACAN_GEN_CONTROL1r_PVTMON_RSTBf_GET(r) ((((r).gen_control1[0]) >> 5) & 0x1) 17557 #define BCMI_HURACAN_GEN_CONTROL1r_PVTMON_RSTBf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) | (1 << (16 + 5)) 17558 #define BCMI_HURACAN_GEN_CONTROL1r_OTP_RSTBf_GET(r) ((((r).gen_control1[0]) >> 4) & 0x1) 17559 #define BCMI_HURACAN_GEN_CONTROL1r_OTP_RSTBf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 17560 #define BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTB_SCf_GET(r) ((((r).gen_control1[0]) >> 3) & 0x1) 17561 #define BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTB_SCf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 17562 #define BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTBf_GET(r) ((((r).gen_control1[0]) >> 2) & 0x1) 17563 #define BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTBf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 17564 #define BCMI_HURACAN_GEN_CONTROL1r_ARB_RSTBf_GET(r) ((((r).gen_control1[0]) >> 1) & 0x1) 17565 #define BCMI_HURACAN_GEN_CONTROL1r_ARB_RSTBf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 17566 #define BCMI_HURACAN_GEN_CONTROL1r_RESETBf_GET(r) (((r).gen_control1[0]) & 0x1) 17567 #define BCMI_HURACAN_GEN_CONTROL1r_RESETBf_SET(r,f) (r).gen_control1[0]=(((r).gen_control1[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17568 17569 /* 17570 * These macros can be used to access GEN_CONTROL1. 17571 */ 17572 #define BCMI_HURACAN_READ_GEN_CONTROL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_GEN_CONTROL1r,_r._gen_control1) 17573 #define BCMI_HURACAN_WRITE_GEN_CONTROL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_GEN_CONTROL1r,_r._gen_control1) 17574 17575 /* 17576 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17577 * will be redefined without the chip prefix for easier programming. 17578 * If multiple chips will be programmed in the same source file, then you should 17579 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17580 * and refer to the fully qualified versions. 17581 */ 17582 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17583 17584 #define GEN_CONTROL1r BCMI_HURACAN_GEN_CONTROL1r 17585 #define GEN_CONTROL1r_SIZE BCMI_HURACAN_GEN_CONTROL1r_SIZE 17586 typedef BCMI_HURACAN_GEN_CONTROL1r_t GEN_CONTROL1r_t; 17587 #define GEN_CONTROL1r_CLR BCMI_HURACAN_GEN_CONTROL1r_CLR 17588 #define GEN_CONTROL1r_SET BCMI_HURACAN_GEN_CONTROL1r_SET 17589 #define GEN_CONTROL1r_GET BCMI_HURACAN_GEN_CONTROL1r_GET 17590 #define GEN_CONTROL1r_REG_RSTBf_GET BCMI_HURACAN_GEN_CONTROL1r_REG_RSTBf_GET 17591 #define GEN_CONTROL1r_REG_RSTBf_SET BCMI_HURACAN_GEN_CONTROL1r_REG_RSTBf_SET 17592 #define GEN_CONTROL1r_PVTMON_RSTBf_GET BCMI_HURACAN_GEN_CONTROL1r_PVTMON_RSTBf_GET 17593 #define GEN_CONTROL1r_PVTMON_RSTBf_SET BCMI_HURACAN_GEN_CONTROL1r_PVTMON_RSTBf_SET 17594 #define GEN_CONTROL1r_OTP_RSTBf_GET BCMI_HURACAN_GEN_CONTROL1r_OTP_RSTBf_GET 17595 #define GEN_CONTROL1r_OTP_RSTBf_SET BCMI_HURACAN_GEN_CONTROL1r_OTP_RSTBf_SET 17596 #define GEN_CONTROL1r_RESCAL_RSTB_SCf_GET BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTB_SCf_GET 17597 #define GEN_CONTROL1r_RESCAL_RSTB_SCf_SET BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTB_SCf_SET 17598 #define GEN_CONTROL1r_RESCAL_RSTBf_GET BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTBf_GET 17599 #define GEN_CONTROL1r_RESCAL_RSTBf_SET BCMI_HURACAN_GEN_CONTROL1r_RESCAL_RSTBf_SET 17600 #define GEN_CONTROL1r_ARB_RSTBf_GET BCMI_HURACAN_GEN_CONTROL1r_ARB_RSTBf_GET 17601 #define GEN_CONTROL1r_ARB_RSTBf_SET BCMI_HURACAN_GEN_CONTROL1r_ARB_RSTBf_SET 17602 #define GEN_CONTROL1r_RESETBf_GET BCMI_HURACAN_GEN_CONTROL1r_RESETBf_GET 17603 #define GEN_CONTROL1r_RESETBf_SET BCMI_HURACAN_GEN_CONTROL1r_RESETBf_SET 17604 #define READ_GEN_CONTROL1r BCMI_HURACAN_READ_GEN_CONTROL1r 17605 #define WRITE_GEN_CONTROL1r BCMI_HURACAN_WRITE_GEN_CONTROL1r 17606 #define MODIFY_GEN_CONTROL1r BCMI_HURACAN_MODIFY_GEN_CONTROL1r 17607 17608 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17609 /******************************************************************************* 17610 * End of 'BCMI_HURACAN_GEN_CONTROL1r' 17611 */ 17612 17613 17614 17615 17616 /******************************************************************************* 17617 * CHIP: BCMI_HURACAN 17618 * REGISTER: MDIO_PHYAD_CTRL 17619 * BLOCKS: CTRL_QUAD_D 17620 * REGADDR: 0xb003 17621 * DEVAD: 1 17622 * DESC: MDIO Phy Address Control 17623 * RESETVAL: 0x0 (0) 17624 * ACCESS: R/W 17625 * FIELDS: 17626 * MDIO_BRDCST_EN 17627 * MDIO_MULTI_EN 17628 * MULTI_PORT_PHYAD 17629 */ 17630 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr (0x0001b003 | PHYMOD_REG_ACC_RAW) 17631 17632 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_SIZE 4 17633 17634 /* 17635 * This structure should be used to declare and program MDIO_PHYAD_CTRL. 17636 */ 17637 typedef union BCMI_HURACAN_MDIO_PHYAD_CTRLr_s { 17638 uint32_t v[1]; 17639 uint32_t mdio_phyad_ctrl[1]; 17640 uint32_t _mdio_phyad_ctrl; 17641 } BCMI_HURACAN_MDIO_PHYAD_CTRLr_t; 17642 17643 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_CLR(r) (r).mdio_phyad_ctrl[0] = 0 17644 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_SET(r,d) (r).mdio_phyad_ctrl[0] = d 17645 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_GET(r) (r).mdio_phyad_ctrl[0] 17646 17647 /* 17648 * These macros can be used to access individual fields. 17649 */ 17650 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_MULTI_PORT_PHYADf_GET(r) ((((r).mdio_phyad_ctrl[0]) >> 2) & 0x1f) 17651 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_MULTI_PORT_PHYADf_SET(r,f) (r).mdio_phyad_ctrl[0]=(((r).mdio_phyad_ctrl[0] & ~((uint32_t)0x1f << 2)) | ((((uint32_t)f) & 0x1f) << 2)) | (31 << (16 + 2)) 17652 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_MULTI_ENf_GET(r) ((((r).mdio_phyad_ctrl[0]) >> 1) & 0x1) 17653 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_MULTI_ENf_SET(r,f) (r).mdio_phyad_ctrl[0]=(((r).mdio_phyad_ctrl[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 17654 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_BRDCST_ENf_GET(r) (((r).mdio_phyad_ctrl[0]) & 0x1) 17655 #define BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_BRDCST_ENf_SET(r,f) (r).mdio_phyad_ctrl[0]=(((r).mdio_phyad_ctrl[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17656 17657 /* 17658 * These macros can be used to access MDIO_PHYAD_CTRL. 17659 */ 17660 #define BCMI_HURACAN_READ_MDIO_PHYAD_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDIO_PHYAD_CTRLr,_r._mdio_phyad_ctrl) 17661 #define BCMI_HURACAN_WRITE_MDIO_PHYAD_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDIO_PHYAD_CTRLr,_r._mdio_phyad_ctrl) 17662 17663 /* 17664 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17665 * will be redefined without the chip prefix for easier programming. 17666 * If multiple chips will be programmed in the same source file, then you should 17667 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17668 * and refer to the fully qualified versions. 17669 */ 17670 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17671 17672 #define MDIO_PHYAD_CTRLr BCMI_HURACAN_MDIO_PHYAD_CTRLr 17673 #define MDIO_PHYAD_CTRLr_SIZE BCMI_HURACAN_MDIO_PHYAD_CTRLr_SIZE 17674 typedef BCMI_HURACAN_MDIO_PHYAD_CTRLr_t MDIO_PHYAD_CTRLr_t; 17675 #define MDIO_PHYAD_CTRLr_CLR BCMI_HURACAN_MDIO_PHYAD_CTRLr_CLR 17676 #define MDIO_PHYAD_CTRLr_SET BCMI_HURACAN_MDIO_PHYAD_CTRLr_SET 17677 #define MDIO_PHYAD_CTRLr_GET BCMI_HURACAN_MDIO_PHYAD_CTRLr_GET 17678 #define MDIO_PHYAD_CTRLr_MULTI_PORT_PHYADf_GET BCMI_HURACAN_MDIO_PHYAD_CTRLr_MULTI_PORT_PHYADf_GET 17679 #define MDIO_PHYAD_CTRLr_MULTI_PORT_PHYADf_SET BCMI_HURACAN_MDIO_PHYAD_CTRLr_MULTI_PORT_PHYADf_SET 17680 #define MDIO_PHYAD_CTRLr_MDIO_MULTI_ENf_GET BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_MULTI_ENf_GET 17681 #define MDIO_PHYAD_CTRLr_MDIO_MULTI_ENf_SET BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_MULTI_ENf_SET 17682 #define MDIO_PHYAD_CTRLr_MDIO_BRDCST_ENf_GET BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_BRDCST_ENf_GET 17683 #define MDIO_PHYAD_CTRLr_MDIO_BRDCST_ENf_SET BCMI_HURACAN_MDIO_PHYAD_CTRLr_MDIO_BRDCST_ENf_SET 17684 #define READ_MDIO_PHYAD_CTRLr BCMI_HURACAN_READ_MDIO_PHYAD_CTRLr 17685 #define WRITE_MDIO_PHYAD_CTRLr BCMI_HURACAN_WRITE_MDIO_PHYAD_CTRLr 17686 #define MODIFY_MDIO_PHYAD_CTRLr BCMI_HURACAN_MODIFY_MDIO_PHYAD_CTRLr 17687 17688 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17689 /******************************************************************************* 17690 * End of 'BCMI_HURACAN_MDIO_PHYAD_CTRLr' 17691 */ 17692 17693 17694 17695 17696 /******************************************************************************* 17697 * CHIP: BCMI_HURACAN 17698 * REGISTER: GPIO_CTRL 17699 * BLOCKS: CTRL_QUAD_D 17700 * REGADDR: 0xb004 17701 * DEVAD: 1 17702 * DESC: GPIO overload control 17703 * RESETVAL: 0x0 (0) 17704 * ACCESS: R/W 17705 * FIELDS: 17706 * GPIO_1_OUT_SEL 17707 */ 17708 #define BCMI_HURACAN_GPIO_CTRLr (0x0001b004 | PHYMOD_REG_ACC_RAW) 17709 17710 #define BCMI_HURACAN_GPIO_CTRLr_SIZE 4 17711 17712 /* 17713 * This structure should be used to declare and program GPIO_CTRL. 17714 */ 17715 typedef union BCMI_HURACAN_GPIO_CTRLr_s { 17716 uint32_t v[1]; 17717 uint32_t gpio_ctrl[1]; 17718 uint32_t _gpio_ctrl; 17719 } BCMI_HURACAN_GPIO_CTRLr_t; 17720 17721 #define BCMI_HURACAN_GPIO_CTRLr_CLR(r) (r).gpio_ctrl[0] = 0 17722 #define BCMI_HURACAN_GPIO_CTRLr_SET(r,d) (r).gpio_ctrl[0] = d 17723 #define BCMI_HURACAN_GPIO_CTRLr_GET(r) (r).gpio_ctrl[0] 17724 17725 /* 17726 * These macros can be used to access individual fields. 17727 */ 17728 #define BCMI_HURACAN_GPIO_CTRLr_GPIO_1_OUT_SELf_GET(r) (((r).gpio_ctrl[0]) & 0x7) 17729 #define BCMI_HURACAN_GPIO_CTRLr_GPIO_1_OUT_SELf_SET(r,f) (r).gpio_ctrl[0]=(((r).gpio_ctrl[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 17730 17731 /* 17732 * These macros can be used to access GPIO_CTRL. 17733 */ 17734 #define BCMI_HURACAN_READ_GPIO_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_GPIO_CTRLr,_r._gpio_ctrl) 17735 #define BCMI_HURACAN_WRITE_GPIO_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_GPIO_CTRLr,_r._gpio_ctrl) 17736 17737 /* 17738 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17739 * will be redefined without the chip prefix for easier programming. 17740 * If multiple chips will be programmed in the same source file, then you should 17741 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17742 * and refer to the fully qualified versions. 17743 */ 17744 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17745 17746 #define GPIO_CTRLr BCMI_HURACAN_GPIO_CTRLr 17747 #define GPIO_CTRLr_SIZE BCMI_HURACAN_GPIO_CTRLr_SIZE 17748 typedef BCMI_HURACAN_GPIO_CTRLr_t GPIO_CTRLr_t; 17749 #define GPIO_CTRLr_CLR BCMI_HURACAN_GPIO_CTRLr_CLR 17750 #define GPIO_CTRLr_SET BCMI_HURACAN_GPIO_CTRLr_SET 17751 #define GPIO_CTRLr_GET BCMI_HURACAN_GPIO_CTRLr_GET 17752 #define GPIO_CTRLr_GPIO_1_OUT_SELf_GET BCMI_HURACAN_GPIO_CTRLr_GPIO_1_OUT_SELf_GET 17753 #define GPIO_CTRLr_GPIO_1_OUT_SELf_SET BCMI_HURACAN_GPIO_CTRLr_GPIO_1_OUT_SELf_SET 17754 #define READ_GPIO_CTRLr BCMI_HURACAN_READ_GPIO_CTRLr 17755 #define WRITE_GPIO_CTRLr BCMI_HURACAN_WRITE_GPIO_CTRLr 17756 #define MODIFY_GPIO_CTRLr BCMI_HURACAN_MODIFY_GPIO_CTRLr 17757 17758 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17759 /******************************************************************************* 17760 * End of 'BCMI_HURACAN_GPIO_CTRLr' 17761 */ 17762 17763 17764 17765 17766 /******************************************************************************* 17767 * CHIP: BCMI_HURACAN 17768 * REGISTER: HEARTBEAT_CTRL 17769 * BLOCKS: CTRL_QUAD_D 17770 * REGADDR: 0xb005 17771 * DEVAD: 1 17772 * DESC: 1us heartbeat Control 17773 * RESETVAL: 0x0 (0) 17774 * ACCESS: R/W 17775 * FIELDS: 17776 * HEARTBEAT_1US_COUNT 17777 */ 17778 #define BCMI_HURACAN_HEARTBEAT_CTRLr (0x0001b005 | PHYMOD_REG_ACC_RAW) 17779 17780 #define BCMI_HURACAN_HEARTBEAT_CTRLr_SIZE 4 17781 17782 /* 17783 * This structure should be used to declare and program HEARTBEAT_CTRL. 17784 */ 17785 typedef union BCMI_HURACAN_HEARTBEAT_CTRLr_s { 17786 uint32_t v[1]; 17787 uint32_t heartbeat_ctrl[1]; 17788 uint32_t _heartbeat_ctrl; 17789 } BCMI_HURACAN_HEARTBEAT_CTRLr_t; 17790 17791 #define BCMI_HURACAN_HEARTBEAT_CTRLr_CLR(r) (r).heartbeat_ctrl[0] = 0 17792 #define BCMI_HURACAN_HEARTBEAT_CTRLr_SET(r,d) (r).heartbeat_ctrl[0] = d 17793 #define BCMI_HURACAN_HEARTBEAT_CTRLr_GET(r) (r).heartbeat_ctrl[0] 17794 17795 /* 17796 * These macros can be used to access individual fields. 17797 */ 17798 #define BCMI_HURACAN_HEARTBEAT_CTRLr_HEARTBEAT_1US_COUNTf_GET(r) (((r).heartbeat_ctrl[0]) & 0xff) 17799 #define BCMI_HURACAN_HEARTBEAT_CTRLr_HEARTBEAT_1US_COUNTf_SET(r,f) (r).heartbeat_ctrl[0]=(((r).heartbeat_ctrl[0] & ~((uint32_t)0xff)) | (((uint32_t)f) & 0xff)) | (0xff << 16) 17800 17801 /* 17802 * These macros can be used to access HEARTBEAT_CTRL. 17803 */ 17804 #define BCMI_HURACAN_READ_HEARTBEAT_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_HEARTBEAT_CTRLr,_r._heartbeat_ctrl) 17805 #define BCMI_HURACAN_WRITE_HEARTBEAT_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_HEARTBEAT_CTRLr,_r._heartbeat_ctrl) 17806 17807 /* 17808 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17809 * will be redefined without the chip prefix for easier programming. 17810 * If multiple chips will be programmed in the same source file, then you should 17811 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17812 * and refer to the fully qualified versions. 17813 */ 17814 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17815 17816 #define HEARTBEAT_CTRLr BCMI_HURACAN_HEARTBEAT_CTRLr 17817 #define HEARTBEAT_CTRLr_SIZE BCMI_HURACAN_HEARTBEAT_CTRLr_SIZE 17818 typedef BCMI_HURACAN_HEARTBEAT_CTRLr_t HEARTBEAT_CTRLr_t; 17819 #define HEARTBEAT_CTRLr_CLR BCMI_HURACAN_HEARTBEAT_CTRLr_CLR 17820 #define HEARTBEAT_CTRLr_SET BCMI_HURACAN_HEARTBEAT_CTRLr_SET 17821 #define HEARTBEAT_CTRLr_GET BCMI_HURACAN_HEARTBEAT_CTRLr_GET 17822 #define HEARTBEAT_CTRLr_HEARTBEAT_1US_COUNTf_GET BCMI_HURACAN_HEARTBEAT_CTRLr_HEARTBEAT_1US_COUNTf_GET 17823 #define HEARTBEAT_CTRLr_HEARTBEAT_1US_COUNTf_SET BCMI_HURACAN_HEARTBEAT_CTRLr_HEARTBEAT_1US_COUNTf_SET 17824 #define READ_HEARTBEAT_CTRLr BCMI_HURACAN_READ_HEARTBEAT_CTRLr 17825 #define WRITE_HEARTBEAT_CTRLr BCMI_HURACAN_WRITE_HEARTBEAT_CTRLr 17826 #define MODIFY_HEARTBEAT_CTRLr BCMI_HURACAN_MODIFY_HEARTBEAT_CTRLr 17827 17828 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17829 /******************************************************************************* 17830 * End of 'BCMI_HURACAN_HEARTBEAT_CTRLr' 17831 */ 17832 17833 17834 17835 17836 /******************************************************************************* 17837 * CHIP: BCMI_HURACAN 17838 * REGISTER: OTP_CON_CTL 17839 * BLOCKS: HARD_IP_QUAD_D 17840 * REGADDR: 0xb010 17841 * DEVAD: 1 17842 * DESC: one time programmable controller register 17843 * RESETVAL: 0x0 (0) 17844 * ACCESS: R/W 17845 * FIELDS: 17846 * I_OTP_SFT_RESET 17847 */ 17848 #define BCMI_HURACAN_OTP_CON_CTLr (0x0001b010 | PHYMOD_REG_ACC_RAW) 17849 17850 #define BCMI_HURACAN_OTP_CON_CTLr_SIZE 4 17851 17852 /* 17853 * This structure should be used to declare and program OTP_CON_CTL. 17854 */ 17855 typedef union BCMI_HURACAN_OTP_CON_CTLr_s { 17856 uint32_t v[1]; 17857 uint32_t otp_con_ctl[1]; 17858 uint32_t _otp_con_ctl; 17859 } BCMI_HURACAN_OTP_CON_CTLr_t; 17860 17861 #define BCMI_HURACAN_OTP_CON_CTLr_CLR(r) (r).otp_con_ctl[0] = 0 17862 #define BCMI_HURACAN_OTP_CON_CTLr_SET(r,d) (r).otp_con_ctl[0] = d 17863 #define BCMI_HURACAN_OTP_CON_CTLr_GET(r) (r).otp_con_ctl[0] 17864 17865 /* 17866 * These macros can be used to access individual fields. 17867 */ 17868 #define BCMI_HURACAN_OTP_CON_CTLr_I_OTP_SFT_RESETf_GET(r) (((r).otp_con_ctl[0]) & 0x1) 17869 #define BCMI_HURACAN_OTP_CON_CTLr_I_OTP_SFT_RESETf_SET(r,f) (r).otp_con_ctl[0]=(((r).otp_con_ctl[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17870 17871 /* 17872 * These macros can be used to access OTP_CON_CTL. 17873 */ 17874 #define BCMI_HURACAN_READ_OTP_CON_CTLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_OTP_CON_CTLr,_r._otp_con_ctl) 17875 #define BCMI_HURACAN_WRITE_OTP_CON_CTLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_OTP_CON_CTLr,_r._otp_con_ctl) 17876 17877 /* 17878 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17879 * will be redefined without the chip prefix for easier programming. 17880 * If multiple chips will be programmed in the same source file, then you should 17881 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17882 * and refer to the fully qualified versions. 17883 */ 17884 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17885 17886 #define OTP_CON_CTLr BCMI_HURACAN_OTP_CON_CTLr 17887 #define OTP_CON_CTLr_SIZE BCMI_HURACAN_OTP_CON_CTLr_SIZE 17888 typedef BCMI_HURACAN_OTP_CON_CTLr_t OTP_CON_CTLr_t; 17889 #define OTP_CON_CTLr_CLR BCMI_HURACAN_OTP_CON_CTLr_CLR 17890 #define OTP_CON_CTLr_SET BCMI_HURACAN_OTP_CON_CTLr_SET 17891 #define OTP_CON_CTLr_GET BCMI_HURACAN_OTP_CON_CTLr_GET 17892 #define OTP_CON_CTLr_I_OTP_SFT_RESETf_GET BCMI_HURACAN_OTP_CON_CTLr_I_OTP_SFT_RESETf_GET 17893 #define OTP_CON_CTLr_I_OTP_SFT_RESETf_SET BCMI_HURACAN_OTP_CON_CTLr_I_OTP_SFT_RESETf_SET 17894 #define READ_OTP_CON_CTLr BCMI_HURACAN_READ_OTP_CON_CTLr 17895 #define WRITE_OTP_CON_CTLr BCMI_HURACAN_WRITE_OTP_CON_CTLr 17896 #define MODIFY_OTP_CON_CTLr BCMI_HURACAN_MODIFY_OTP_CON_CTLr 17897 17898 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17899 /******************************************************************************* 17900 * End of 'BCMI_HURACAN_OTP_CON_CTLr' 17901 */ 17902 17903 17904 17905 17906 /******************************************************************************* 17907 * CHIP: BCMI_HURACAN 17908 * REGISTER: OTP_CON_STS 17909 * BLOCKS: HARD_IP_QUAD_D 17910 * REGADDR: 0xb011 17911 * DEVAD: 1 17912 * DESC: one time programmable memory status 17913 * RESETVAL: 0x0 (0) 17914 * ACCESS: R/W 17915 * FIELDS: 17916 * OTP_FOUT_DONE 17917 */ 17918 #define BCMI_HURACAN_OTP_CON_STSr (0x0001b011 | PHYMOD_REG_ACC_RAW) 17919 17920 #define BCMI_HURACAN_OTP_CON_STSr_SIZE 4 17921 17922 /* 17923 * This structure should be used to declare and program OTP_CON_STS. 17924 */ 17925 typedef union BCMI_HURACAN_OTP_CON_STSr_s { 17926 uint32_t v[1]; 17927 uint32_t otp_con_sts[1]; 17928 uint32_t _otp_con_sts; 17929 } BCMI_HURACAN_OTP_CON_STSr_t; 17930 17931 #define BCMI_HURACAN_OTP_CON_STSr_CLR(r) (r).otp_con_sts[0] = 0 17932 #define BCMI_HURACAN_OTP_CON_STSr_SET(r,d) (r).otp_con_sts[0] = d 17933 #define BCMI_HURACAN_OTP_CON_STSr_GET(r) (r).otp_con_sts[0] 17934 17935 /* 17936 * These macros can be used to access individual fields. 17937 */ 17938 #define BCMI_HURACAN_OTP_CON_STSr_OTP_FOUT_DONEf_GET(r) (((r).otp_con_sts[0]) & 0x1) 17939 #define BCMI_HURACAN_OTP_CON_STSr_OTP_FOUT_DONEf_SET(r,f) (r).otp_con_sts[0]=(((r).otp_con_sts[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 17940 17941 /* 17942 * These macros can be used to access OTP_CON_STS. 17943 */ 17944 #define BCMI_HURACAN_READ_OTP_CON_STSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_OTP_CON_STSr,_r._otp_con_sts) 17945 #define BCMI_HURACAN_WRITE_OTP_CON_STSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_OTP_CON_STSr,_r._otp_con_sts) 17946 17947 /* 17948 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 17949 * will be redefined without the chip prefix for easier programming. 17950 * If multiple chips will be programmed in the same source file, then you should 17951 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 17952 * and refer to the fully qualified versions. 17953 */ 17954 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 17955 17956 #define OTP_CON_STSr BCMI_HURACAN_OTP_CON_STSr 17957 #define OTP_CON_STSr_SIZE BCMI_HURACAN_OTP_CON_STSr_SIZE 17958 typedef BCMI_HURACAN_OTP_CON_STSr_t OTP_CON_STSr_t; 17959 #define OTP_CON_STSr_CLR BCMI_HURACAN_OTP_CON_STSr_CLR 17960 #define OTP_CON_STSr_SET BCMI_HURACAN_OTP_CON_STSr_SET 17961 #define OTP_CON_STSr_GET BCMI_HURACAN_OTP_CON_STSr_GET 17962 #define OTP_CON_STSr_OTP_FOUT_DONEf_GET BCMI_HURACAN_OTP_CON_STSr_OTP_FOUT_DONEf_GET 17963 #define OTP_CON_STSr_OTP_FOUT_DONEf_SET BCMI_HURACAN_OTP_CON_STSr_OTP_FOUT_DONEf_SET 17964 #define READ_OTP_CON_STSr BCMI_HURACAN_READ_OTP_CON_STSr 17965 #define WRITE_OTP_CON_STSr BCMI_HURACAN_WRITE_OTP_CON_STSr 17966 #define MODIFY_OTP_CON_STSr BCMI_HURACAN_MODIFY_OTP_CON_STSr 17967 17968 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 17969 /******************************************************************************* 17970 * End of 'BCMI_HURACAN_OTP_CON_STSr' 17971 */ 17972 17973 17974 17975 17976 /******************************************************************************* 17977 * CHIP: BCMI_HURACAN 17978 * REGISTER: OTP_FOUT0 17979 * BLOCKS: HARD_IP_QUAD_D 17980 * REGADDR: 0xb012 17981 * DEVAD: 1 17982 * DESC: the fout bits from OTP memory, debug related 17983 * RESETVAL: 0x0 (0) 17984 * ACCESS: R/W 17985 * FIELDS: 17986 * FOUT_15_0 17987 */ 17988 #define BCMI_HURACAN_OTP_FOUT0r (0x0001b012 | PHYMOD_REG_ACC_RAW) 17989 17990 #define BCMI_HURACAN_OTP_FOUT0r_SIZE 4 17991 17992 /* 17993 * This structure should be used to declare and program OTP_FOUT0. 17994 */ 17995 typedef union BCMI_HURACAN_OTP_FOUT0r_s { 17996 uint32_t v[1]; 17997 uint32_t otp_fout0[1]; 17998 uint32_t _otp_fout0; 17999 } BCMI_HURACAN_OTP_FOUT0r_t; 18000 18001 #define BCMI_HURACAN_OTP_FOUT0r_CLR(r) (r).otp_fout0[0] = 0 18002 #define BCMI_HURACAN_OTP_FOUT0r_SET(r,d) (r).otp_fout0[0] = d 18003 #define BCMI_HURACAN_OTP_FOUT0r_GET(r) (r).otp_fout0[0] 18004 18005 /* 18006 * These macros can be used to access individual fields. 18007 */ 18008 #define BCMI_HURACAN_OTP_FOUT0r_FOUT_15_0f_GET(r) (((r).otp_fout0[0]) & 0xffff) 18009 #define BCMI_HURACAN_OTP_FOUT0r_FOUT_15_0f_SET(r,f) (r).otp_fout0[0]=(((r).otp_fout0[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 18010 18011 /* 18012 * These macros can be used to access OTP_FOUT0. 18013 */ 18014 #define BCMI_HURACAN_READ_OTP_FOUT0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_OTP_FOUT0r,_r._otp_fout0) 18015 #define BCMI_HURACAN_WRITE_OTP_FOUT0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_OTP_FOUT0r,_r._otp_fout0) 18016 18017 /* 18018 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18019 * will be redefined without the chip prefix for easier programming. 18020 * If multiple chips will be programmed in the same source file, then you should 18021 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18022 * and refer to the fully qualified versions. 18023 */ 18024 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18025 18026 #define OTP_FOUT0r BCMI_HURACAN_OTP_FOUT0r 18027 #define OTP_FOUT0r_SIZE BCMI_HURACAN_OTP_FOUT0r_SIZE 18028 typedef BCMI_HURACAN_OTP_FOUT0r_t OTP_FOUT0r_t; 18029 #define OTP_FOUT0r_CLR BCMI_HURACAN_OTP_FOUT0r_CLR 18030 #define OTP_FOUT0r_SET BCMI_HURACAN_OTP_FOUT0r_SET 18031 #define OTP_FOUT0r_GET BCMI_HURACAN_OTP_FOUT0r_GET 18032 #define OTP_FOUT0r_FOUT_15_0f_GET BCMI_HURACAN_OTP_FOUT0r_FOUT_15_0f_GET 18033 #define OTP_FOUT0r_FOUT_15_0f_SET BCMI_HURACAN_OTP_FOUT0r_FOUT_15_0f_SET 18034 #define READ_OTP_FOUT0r BCMI_HURACAN_READ_OTP_FOUT0r 18035 #define WRITE_OTP_FOUT0r BCMI_HURACAN_WRITE_OTP_FOUT0r 18036 #define MODIFY_OTP_FOUT0r BCMI_HURACAN_MODIFY_OTP_FOUT0r 18037 18038 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18039 /******************************************************************************* 18040 * End of 'BCMI_HURACAN_OTP_FOUT0r' 18041 */ 18042 18043 18044 18045 18046 /******************************************************************************* 18047 * CHIP: BCMI_HURACAN 18048 * REGISTER: OTP_FOUT1 18049 * BLOCKS: HARD_IP_QUAD_D 18050 * REGADDR: 0xb013 18051 * DEVAD: 1 18052 * DESC: the fout bits from OTP memory, debug related 18053 * RESETVAL: 0x0 (0) 18054 * ACCESS: R/W 18055 * FIELDS: 18056 * FOUT_31_16 18057 */ 18058 #define BCMI_HURACAN_OTP_FOUT1r (0x0001b013 | PHYMOD_REG_ACC_RAW) 18059 18060 #define BCMI_HURACAN_OTP_FOUT1r_SIZE 4 18061 18062 /* 18063 * This structure should be used to declare and program OTP_FOUT1. 18064 */ 18065 typedef union BCMI_HURACAN_OTP_FOUT1r_s { 18066 uint32_t v[1]; 18067 uint32_t otp_fout1[1]; 18068 uint32_t _otp_fout1; 18069 } BCMI_HURACAN_OTP_FOUT1r_t; 18070 18071 #define BCMI_HURACAN_OTP_FOUT1r_CLR(r) (r).otp_fout1[0] = 0 18072 #define BCMI_HURACAN_OTP_FOUT1r_SET(r,d) (r).otp_fout1[0] = d 18073 #define BCMI_HURACAN_OTP_FOUT1r_GET(r) (r).otp_fout1[0] 18074 18075 /* 18076 * These macros can be used to access individual fields. 18077 */ 18078 #define BCMI_HURACAN_OTP_FOUT1r_FOUT_31_16f_GET(r) (((r).otp_fout1[0]) & 0xffff) 18079 #define BCMI_HURACAN_OTP_FOUT1r_FOUT_31_16f_SET(r,f) (r).otp_fout1[0]=(((r).otp_fout1[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 18080 18081 /* 18082 * These macros can be used to access OTP_FOUT1. 18083 */ 18084 #define BCMI_HURACAN_READ_OTP_FOUT1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_OTP_FOUT1r,_r._otp_fout1) 18085 #define BCMI_HURACAN_WRITE_OTP_FOUT1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_OTP_FOUT1r,_r._otp_fout1) 18086 18087 /* 18088 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18089 * will be redefined without the chip prefix for easier programming. 18090 * If multiple chips will be programmed in the same source file, then you should 18091 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18092 * and refer to the fully qualified versions. 18093 */ 18094 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18095 18096 #define OTP_FOUT1r BCMI_HURACAN_OTP_FOUT1r 18097 #define OTP_FOUT1r_SIZE BCMI_HURACAN_OTP_FOUT1r_SIZE 18098 typedef BCMI_HURACAN_OTP_FOUT1r_t OTP_FOUT1r_t; 18099 #define OTP_FOUT1r_CLR BCMI_HURACAN_OTP_FOUT1r_CLR 18100 #define OTP_FOUT1r_SET BCMI_HURACAN_OTP_FOUT1r_SET 18101 #define OTP_FOUT1r_GET BCMI_HURACAN_OTP_FOUT1r_GET 18102 #define OTP_FOUT1r_FOUT_31_16f_GET BCMI_HURACAN_OTP_FOUT1r_FOUT_31_16f_GET 18103 #define OTP_FOUT1r_FOUT_31_16f_SET BCMI_HURACAN_OTP_FOUT1r_FOUT_31_16f_SET 18104 #define READ_OTP_FOUT1r BCMI_HURACAN_READ_OTP_FOUT1r 18105 #define WRITE_OTP_FOUT1r BCMI_HURACAN_WRITE_OTP_FOUT1r 18106 #define MODIFY_OTP_FOUT1r BCMI_HURACAN_MODIFY_OTP_FOUT1r 18107 18108 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18109 /******************************************************************************* 18110 * End of 'BCMI_HURACAN_OTP_FOUT1r' 18111 */ 18112 18113 18114 18115 18116 /******************************************************************************* 18117 * CHIP: BCMI_HURACAN 18118 * REGISTER: PVTMON_CNTL0 18119 * BLOCKS: HARD_IP_QUAD_D 18120 * REGADDR: 0xb020 18121 * DEVAD: 1 18122 * DESC: process voltage temperature sensor controls 18123 * RESETVAL: 0x0 (0) 18124 * ACCESS: R/W 18125 * FIELDS: 18126 * CTRL_I_PWRDN 18127 * CTRL_I_VAVSMON 18128 * CTRL_I_ADC_RESETB 18129 * CTRL_I_PVTMON_SEL 18130 */ 18131 #define BCMI_HURACAN_PVTMON_CNTL0r (0x0001b020 | PHYMOD_REG_ACC_RAW) 18132 18133 #define BCMI_HURACAN_PVTMON_CNTL0r_SIZE 4 18134 18135 /* 18136 * This structure should be used to declare and program PVTMON_CNTL0. 18137 */ 18138 typedef union BCMI_HURACAN_PVTMON_CNTL0r_s { 18139 uint32_t v[1]; 18140 uint32_t pvtmon_cntl0[1]; 18141 uint32_t _pvtmon_cntl0; 18142 } BCMI_HURACAN_PVTMON_CNTL0r_t; 18143 18144 #define BCMI_HURACAN_PVTMON_CNTL0r_CLR(r) (r).pvtmon_cntl0[0] = 0 18145 #define BCMI_HURACAN_PVTMON_CNTL0r_SET(r,d) (r).pvtmon_cntl0[0] = d 18146 #define BCMI_HURACAN_PVTMON_CNTL0r_GET(r) (r).pvtmon_cntl0[0] 18147 18148 /* 18149 * These macros can be used to access individual fields. 18150 */ 18151 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PVTMON_SELf_GET(r) ((((r).pvtmon_cntl0[0]) >> 4) & 0x7) 18152 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PVTMON_SELf_SET(r,f) (r).pvtmon_cntl0[0]=(((r).pvtmon_cntl0[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 18153 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_ADC_RESETBf_GET(r) ((((r).pvtmon_cntl0[0]) >> 2) & 0x1) 18154 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_ADC_RESETBf_SET(r,f) (r).pvtmon_cntl0[0]=(((r).pvtmon_cntl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 18155 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_VAVSMONf_GET(r) ((((r).pvtmon_cntl0[0]) >> 1) & 0x1) 18156 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_VAVSMONf_SET(r,f) (r).pvtmon_cntl0[0]=(((r).pvtmon_cntl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 18157 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PWRDNf_GET(r) (((r).pvtmon_cntl0[0]) & 0x1) 18158 #define BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PWRDNf_SET(r,f) (r).pvtmon_cntl0[0]=(((r).pvtmon_cntl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 18159 18160 /* 18161 * These macros can be used to access PVTMON_CNTL0. 18162 */ 18163 #define BCMI_HURACAN_READ_PVTMON_CNTL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_CNTL0r,_r._pvtmon_cntl0) 18164 #define BCMI_HURACAN_WRITE_PVTMON_CNTL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_CNTL0r,_r._pvtmon_cntl0) 18165 18166 /* 18167 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18168 * will be redefined without the chip prefix for easier programming. 18169 * If multiple chips will be programmed in the same source file, then you should 18170 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18171 * and refer to the fully qualified versions. 18172 */ 18173 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18174 18175 #define PVTMON_CNTL0r BCMI_HURACAN_PVTMON_CNTL0r 18176 #define PVTMON_CNTL0r_SIZE BCMI_HURACAN_PVTMON_CNTL0r_SIZE 18177 typedef BCMI_HURACAN_PVTMON_CNTL0r_t PVTMON_CNTL0r_t; 18178 #define PVTMON_CNTL0r_CLR BCMI_HURACAN_PVTMON_CNTL0r_CLR 18179 #define PVTMON_CNTL0r_SET BCMI_HURACAN_PVTMON_CNTL0r_SET 18180 #define PVTMON_CNTL0r_GET BCMI_HURACAN_PVTMON_CNTL0r_GET 18181 #define PVTMON_CNTL0r_CTRL_I_PVTMON_SELf_GET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PVTMON_SELf_GET 18182 #define PVTMON_CNTL0r_CTRL_I_PVTMON_SELf_SET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PVTMON_SELf_SET 18183 #define PVTMON_CNTL0r_CTRL_I_ADC_RESETBf_GET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_ADC_RESETBf_GET 18184 #define PVTMON_CNTL0r_CTRL_I_ADC_RESETBf_SET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_ADC_RESETBf_SET 18185 #define PVTMON_CNTL0r_CTRL_I_VAVSMONf_GET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_VAVSMONf_GET 18186 #define PVTMON_CNTL0r_CTRL_I_VAVSMONf_SET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_VAVSMONf_SET 18187 #define PVTMON_CNTL0r_CTRL_I_PWRDNf_GET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PWRDNf_GET 18188 #define PVTMON_CNTL0r_CTRL_I_PWRDNf_SET BCMI_HURACAN_PVTMON_CNTL0r_CTRL_I_PWRDNf_SET 18189 #define READ_PVTMON_CNTL0r BCMI_HURACAN_READ_PVTMON_CNTL0r 18190 #define WRITE_PVTMON_CNTL0r BCMI_HURACAN_WRITE_PVTMON_CNTL0r 18191 #define MODIFY_PVTMON_CNTL0r BCMI_HURACAN_MODIFY_PVTMON_CNTL0r 18192 18193 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18194 /******************************************************************************* 18195 * End of 'BCMI_HURACAN_PVTMON_CNTL0r' 18196 */ 18197 18198 18199 18200 18201 /******************************************************************************* 18202 * CHIP: BCMI_HURACAN 18203 * REGISTER: PVTMON_CNTL1 18204 * BLOCKS: HARD_IP_QUAD_D 18205 * REGADDR: 0xb021 18206 * DEVAD: 1 18207 * DESC: process voltage temperature sensor controls 18208 * RESETVAL: 0x0 (0) 18209 * ACCESS: R/W 18210 * FIELDS: 18211 * CTRL_16_16_CON_PAD 18212 * CTRL_17_17_BURNIN_EN 18213 * CTRL_27_27_DAC_RESET 18214 * CTRL_28_28_DAC_SET 18215 * CTRL_23_20_VAVSMON_REFADJ_MIN0 18216 * CTRL_26_24_VAVSMON_REFADJ_MIN1 18217 * CTRL_18_RSVD 18218 * CTRL_31_29_VAVSMON_REFADJ_MAX 18219 * CTRL_19_RSVD 18220 */ 18221 #define BCMI_HURACAN_PVTMON_CNTL1r (0x0001b021 | PHYMOD_REG_ACC_RAW) 18222 18223 #define BCMI_HURACAN_PVTMON_CNTL1r_SIZE 4 18224 18225 /* 18226 * This structure should be used to declare and program PVTMON_CNTL1. 18227 */ 18228 typedef union BCMI_HURACAN_PVTMON_CNTL1r_s { 18229 uint32_t v[1]; 18230 uint32_t pvtmon_cntl1[1]; 18231 uint32_t _pvtmon_cntl1; 18232 } BCMI_HURACAN_PVTMON_CNTL1r_t; 18233 18234 #define BCMI_HURACAN_PVTMON_CNTL1r_CLR(r) (r).pvtmon_cntl1[0] = 0 18235 #define BCMI_HURACAN_PVTMON_CNTL1r_SET(r,d) (r).pvtmon_cntl1[0] = d 18236 #define BCMI_HURACAN_PVTMON_CNTL1r_GET(r) (r).pvtmon_cntl1[0] 18237 18238 /* 18239 * These macros can be used to access individual fields. 18240 */ 18241 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_19_RSVDf_GET(r) ((((r).pvtmon_cntl1[0]) >> 15) & 0x1) 18242 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_19_RSVDf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x1 << 15)) | ((((uint32_t)f) & 0x1) << 15)) | (1 << (16 + 15)) 18243 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_31_29_VAVSMON_REFADJ_MAXf_GET(r) ((((r).pvtmon_cntl1[0]) >> 12) & 0x7) 18244 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_31_29_VAVSMON_REFADJ_MAXf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 18245 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_18_RSVDf_GET(r) ((((r).pvtmon_cntl1[0]) >> 11) & 0x1) 18246 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_18_RSVDf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) | (1 << (16 + 11)) 18247 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_26_24_VAVSMON_REFADJ_MIN1f_GET(r) ((((r).pvtmon_cntl1[0]) >> 8) & 0x7) 18248 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_26_24_VAVSMON_REFADJ_MIN1f_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 18249 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_23_20_VAVSMON_REFADJ_MIN0f_GET(r) ((((r).pvtmon_cntl1[0]) >> 4) & 0xf) 18250 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_23_20_VAVSMON_REFADJ_MIN0f_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 18251 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_28_28_DAC_SETf_GET(r) ((((r).pvtmon_cntl1[0]) >> 3) & 0x1) 18252 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_28_28_DAC_SETf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 18253 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_27_27_DAC_RESETf_GET(r) ((((r).pvtmon_cntl1[0]) >> 2) & 0x1) 18254 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_27_27_DAC_RESETf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 18255 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_17_17_BURNIN_ENf_GET(r) ((((r).pvtmon_cntl1[0]) >> 1) & 0x1) 18256 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_17_17_BURNIN_ENf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 18257 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_16_16_CON_PADf_GET(r) (((r).pvtmon_cntl1[0]) & 0x1) 18258 #define BCMI_HURACAN_PVTMON_CNTL1r_CTRL_16_16_CON_PADf_SET(r,f) (r).pvtmon_cntl1[0]=(((r).pvtmon_cntl1[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 18259 18260 /* 18261 * These macros can be used to access PVTMON_CNTL1. 18262 */ 18263 #define BCMI_HURACAN_READ_PVTMON_CNTL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_CNTL1r,_r._pvtmon_cntl1) 18264 #define BCMI_HURACAN_WRITE_PVTMON_CNTL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_CNTL1r,_r._pvtmon_cntl1) 18265 18266 /* 18267 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18268 * will be redefined without the chip prefix for easier programming. 18269 * If multiple chips will be programmed in the same source file, then you should 18270 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18271 * and refer to the fully qualified versions. 18272 */ 18273 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18274 18275 #define PVTMON_CNTL1r BCMI_HURACAN_PVTMON_CNTL1r 18276 #define PVTMON_CNTL1r_SIZE BCMI_HURACAN_PVTMON_CNTL1r_SIZE 18277 typedef BCMI_HURACAN_PVTMON_CNTL1r_t PVTMON_CNTL1r_t; 18278 #define PVTMON_CNTL1r_CLR BCMI_HURACAN_PVTMON_CNTL1r_CLR 18279 #define PVTMON_CNTL1r_SET BCMI_HURACAN_PVTMON_CNTL1r_SET 18280 #define PVTMON_CNTL1r_GET BCMI_HURACAN_PVTMON_CNTL1r_GET 18281 #define PVTMON_CNTL1r_CTRL_19_RSVDf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_19_RSVDf_GET 18282 #define PVTMON_CNTL1r_CTRL_19_RSVDf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_19_RSVDf_SET 18283 #define PVTMON_CNTL1r_CTRL_31_29_VAVSMON_REFADJ_MAXf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_31_29_VAVSMON_REFADJ_MAXf_GET 18284 #define PVTMON_CNTL1r_CTRL_31_29_VAVSMON_REFADJ_MAXf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_31_29_VAVSMON_REFADJ_MAXf_SET 18285 #define PVTMON_CNTL1r_CTRL_18_RSVDf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_18_RSVDf_GET 18286 #define PVTMON_CNTL1r_CTRL_18_RSVDf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_18_RSVDf_SET 18287 #define PVTMON_CNTL1r_CTRL_26_24_VAVSMON_REFADJ_MIN1f_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_26_24_VAVSMON_REFADJ_MIN1f_GET 18288 #define PVTMON_CNTL1r_CTRL_26_24_VAVSMON_REFADJ_MIN1f_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_26_24_VAVSMON_REFADJ_MIN1f_SET 18289 #define PVTMON_CNTL1r_CTRL_23_20_VAVSMON_REFADJ_MIN0f_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_23_20_VAVSMON_REFADJ_MIN0f_GET 18290 #define PVTMON_CNTL1r_CTRL_23_20_VAVSMON_REFADJ_MIN0f_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_23_20_VAVSMON_REFADJ_MIN0f_SET 18291 #define PVTMON_CNTL1r_CTRL_28_28_DAC_SETf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_28_28_DAC_SETf_GET 18292 #define PVTMON_CNTL1r_CTRL_28_28_DAC_SETf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_28_28_DAC_SETf_SET 18293 #define PVTMON_CNTL1r_CTRL_27_27_DAC_RESETf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_27_27_DAC_RESETf_GET 18294 #define PVTMON_CNTL1r_CTRL_27_27_DAC_RESETf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_27_27_DAC_RESETf_SET 18295 #define PVTMON_CNTL1r_CTRL_17_17_BURNIN_ENf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_17_17_BURNIN_ENf_GET 18296 #define PVTMON_CNTL1r_CTRL_17_17_BURNIN_ENf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_17_17_BURNIN_ENf_SET 18297 #define PVTMON_CNTL1r_CTRL_16_16_CON_PADf_GET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_16_16_CON_PADf_GET 18298 #define PVTMON_CNTL1r_CTRL_16_16_CON_PADf_SET BCMI_HURACAN_PVTMON_CNTL1r_CTRL_16_16_CON_PADf_SET 18299 #define READ_PVTMON_CNTL1r BCMI_HURACAN_READ_PVTMON_CNTL1r 18300 #define WRITE_PVTMON_CNTL1r BCMI_HURACAN_WRITE_PVTMON_CNTL1r 18301 #define MODIFY_PVTMON_CNTL1r BCMI_HURACAN_MODIFY_PVTMON_CNTL1r 18302 18303 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18304 /******************************************************************************* 18305 * End of 'BCMI_HURACAN_PVTMON_CNTL1r' 18306 */ 18307 18308 18309 18310 18311 /******************************************************************************* 18312 * CHIP: BCMI_HURACAN 18313 * REGISTER: PVTMON_CNTL2 18314 * BLOCKS: HARD_IP_QUAD_D 18315 * REGADDR: 0xb022 18316 * DEVAD: 1 18317 * DESC: process voltage temperature sensor controls 18318 * RESETVAL: 0x0 (0) 18319 * ACCESS: R/W 18320 * FIELDS: 18321 * CTRL_14_13_ADC_INSEL_14_13 18322 * CTRL_15_15_DAC_EN 18323 */ 18324 #define BCMI_HURACAN_PVTMON_CNTL2r (0x0001b022 | PHYMOD_REG_ACC_RAW) 18325 18326 #define BCMI_HURACAN_PVTMON_CNTL2r_SIZE 4 18327 18328 /* 18329 * This structure should be used to declare and program PVTMON_CNTL2. 18330 */ 18331 typedef union BCMI_HURACAN_PVTMON_CNTL2r_s { 18332 uint32_t v[1]; 18333 uint32_t pvtmon_cntl2[1]; 18334 uint32_t _pvtmon_cntl2; 18335 } BCMI_HURACAN_PVTMON_CNTL2r_t; 18336 18337 #define BCMI_HURACAN_PVTMON_CNTL2r_CLR(r) (r).pvtmon_cntl2[0] = 0 18338 #define BCMI_HURACAN_PVTMON_CNTL2r_SET(r,d) (r).pvtmon_cntl2[0] = d 18339 #define BCMI_HURACAN_PVTMON_CNTL2r_GET(r) (r).pvtmon_cntl2[0] 18340 18341 /* 18342 * These macros can be used to access individual fields. 18343 */ 18344 #define BCMI_HURACAN_PVTMON_CNTL2r_CTRL_15_15_DAC_ENf_GET(r) ((((r).pvtmon_cntl2[0]) >> 2) & 0x1) 18345 #define BCMI_HURACAN_PVTMON_CNTL2r_CTRL_15_15_DAC_ENf_SET(r,f) (r).pvtmon_cntl2[0]=(((r).pvtmon_cntl2[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 18346 #define BCMI_HURACAN_PVTMON_CNTL2r_CTRL_14_13_ADC_INSEL_14_13f_GET(r) (((r).pvtmon_cntl2[0]) & 0x3) 18347 #define BCMI_HURACAN_PVTMON_CNTL2r_CTRL_14_13_ADC_INSEL_14_13f_SET(r,f) (r).pvtmon_cntl2[0]=(((r).pvtmon_cntl2[0] & ~((uint32_t)0x3)) | (((uint32_t)f) & 0x3)) | (0x3 << 16) 18348 18349 /* 18350 * These macros can be used to access PVTMON_CNTL2. 18351 */ 18352 #define BCMI_HURACAN_READ_PVTMON_CNTL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_CNTL2r,_r._pvtmon_cntl2) 18353 #define BCMI_HURACAN_WRITE_PVTMON_CNTL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_CNTL2r,_r._pvtmon_cntl2) 18354 18355 /* 18356 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18357 * will be redefined without the chip prefix for easier programming. 18358 * If multiple chips will be programmed in the same source file, then you should 18359 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18360 * and refer to the fully qualified versions. 18361 */ 18362 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18363 18364 #define PVTMON_CNTL2r BCMI_HURACAN_PVTMON_CNTL2r 18365 #define PVTMON_CNTL2r_SIZE BCMI_HURACAN_PVTMON_CNTL2r_SIZE 18366 typedef BCMI_HURACAN_PVTMON_CNTL2r_t PVTMON_CNTL2r_t; 18367 #define PVTMON_CNTL2r_CLR BCMI_HURACAN_PVTMON_CNTL2r_CLR 18368 #define PVTMON_CNTL2r_SET BCMI_HURACAN_PVTMON_CNTL2r_SET 18369 #define PVTMON_CNTL2r_GET BCMI_HURACAN_PVTMON_CNTL2r_GET 18370 #define PVTMON_CNTL2r_CTRL_15_15_DAC_ENf_GET BCMI_HURACAN_PVTMON_CNTL2r_CTRL_15_15_DAC_ENf_GET 18371 #define PVTMON_CNTL2r_CTRL_15_15_DAC_ENf_SET BCMI_HURACAN_PVTMON_CNTL2r_CTRL_15_15_DAC_ENf_SET 18372 #define PVTMON_CNTL2r_CTRL_14_13_ADC_INSEL_14_13f_GET BCMI_HURACAN_PVTMON_CNTL2r_CTRL_14_13_ADC_INSEL_14_13f_GET 18373 #define PVTMON_CNTL2r_CTRL_14_13_ADC_INSEL_14_13f_SET BCMI_HURACAN_PVTMON_CNTL2r_CTRL_14_13_ADC_INSEL_14_13f_SET 18374 #define READ_PVTMON_CNTL2r BCMI_HURACAN_READ_PVTMON_CNTL2r 18375 #define WRITE_PVTMON_CNTL2r BCMI_HURACAN_WRITE_PVTMON_CNTL2r 18376 #define MODIFY_PVTMON_CNTL2r BCMI_HURACAN_MODIFY_PVTMON_CNTL2r 18377 18378 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18379 /******************************************************************************* 18380 * End of 'BCMI_HURACAN_PVTMON_CNTL2r' 18381 */ 18382 18383 18384 18385 18386 /******************************************************************************* 18387 * CHIP: BCMI_HURACAN 18388 * REGISTER: PVTMON_CNTL3 18389 * BLOCKS: HARD_IP_QUAD_D 18390 * REGADDR: 0xb023 18391 * DEVAD: 1 18392 * DESC: process voltage temperature sensor controls 18393 * RESETVAL: 0x0 (0) 18394 * ACCESS: R/W 18395 * FIELDS: 18396 * CTRL_2_0_BG_ADJ 18397 * CTRL_6_3_VTEST_SEL 18398 * CTRL_9_7_RMON_SEL 18399 * CTRL_12_10_MODE 18400 */ 18401 #define BCMI_HURACAN_PVTMON_CNTL3r (0x0001b023 | PHYMOD_REG_ACC_RAW) 18402 18403 #define BCMI_HURACAN_PVTMON_CNTL3r_SIZE 4 18404 18405 /* 18406 * This structure should be used to declare and program PVTMON_CNTL3. 18407 */ 18408 typedef union BCMI_HURACAN_PVTMON_CNTL3r_s { 18409 uint32_t v[1]; 18410 uint32_t pvtmon_cntl3[1]; 18411 uint32_t _pvtmon_cntl3; 18412 } BCMI_HURACAN_PVTMON_CNTL3r_t; 18413 18414 #define BCMI_HURACAN_PVTMON_CNTL3r_CLR(r) (r).pvtmon_cntl3[0] = 0 18415 #define BCMI_HURACAN_PVTMON_CNTL3r_SET(r,d) (r).pvtmon_cntl3[0] = d 18416 #define BCMI_HURACAN_PVTMON_CNTL3r_GET(r) (r).pvtmon_cntl3[0] 18417 18418 /* 18419 * These macros can be used to access individual fields. 18420 */ 18421 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_12_10_MODEf_GET(r) ((((r).pvtmon_cntl3[0]) >> 12) & 0x7) 18422 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_12_10_MODEf_SET(r,f) (r).pvtmon_cntl3[0]=(((r).pvtmon_cntl3[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 18423 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_9_7_RMON_SELf_GET(r) ((((r).pvtmon_cntl3[0]) >> 8) & 0x7) 18424 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_9_7_RMON_SELf_SET(r,f) (r).pvtmon_cntl3[0]=(((r).pvtmon_cntl3[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 18425 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_6_3_VTEST_SELf_GET(r) ((((r).pvtmon_cntl3[0]) >> 4) & 0xf) 18426 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_6_3_VTEST_SELf_SET(r,f) (r).pvtmon_cntl3[0]=(((r).pvtmon_cntl3[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 18427 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_2_0_BG_ADJf_GET(r) (((r).pvtmon_cntl3[0]) & 0x7) 18428 #define BCMI_HURACAN_PVTMON_CNTL3r_CTRL_2_0_BG_ADJf_SET(r,f) (r).pvtmon_cntl3[0]=(((r).pvtmon_cntl3[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 18429 18430 /* 18431 * These macros can be used to access PVTMON_CNTL3. 18432 */ 18433 #define BCMI_HURACAN_READ_PVTMON_CNTL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_CNTL3r,_r._pvtmon_cntl3) 18434 #define BCMI_HURACAN_WRITE_PVTMON_CNTL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_CNTL3r,_r._pvtmon_cntl3) 18435 18436 /* 18437 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18438 * will be redefined without the chip prefix for easier programming. 18439 * If multiple chips will be programmed in the same source file, then you should 18440 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18441 * and refer to the fully qualified versions. 18442 */ 18443 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18444 18445 #define PVTMON_CNTL3r BCMI_HURACAN_PVTMON_CNTL3r 18446 #define PVTMON_CNTL3r_SIZE BCMI_HURACAN_PVTMON_CNTL3r_SIZE 18447 typedef BCMI_HURACAN_PVTMON_CNTL3r_t PVTMON_CNTL3r_t; 18448 #define PVTMON_CNTL3r_CLR BCMI_HURACAN_PVTMON_CNTL3r_CLR 18449 #define PVTMON_CNTL3r_SET BCMI_HURACAN_PVTMON_CNTL3r_SET 18450 #define PVTMON_CNTL3r_GET BCMI_HURACAN_PVTMON_CNTL3r_GET 18451 #define PVTMON_CNTL3r_CTRL_12_10_MODEf_GET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_12_10_MODEf_GET 18452 #define PVTMON_CNTL3r_CTRL_12_10_MODEf_SET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_12_10_MODEf_SET 18453 #define PVTMON_CNTL3r_CTRL_9_7_RMON_SELf_GET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_9_7_RMON_SELf_GET 18454 #define PVTMON_CNTL3r_CTRL_9_7_RMON_SELf_SET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_9_7_RMON_SELf_SET 18455 #define PVTMON_CNTL3r_CTRL_6_3_VTEST_SELf_GET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_6_3_VTEST_SELf_GET 18456 #define PVTMON_CNTL3r_CTRL_6_3_VTEST_SELf_SET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_6_3_VTEST_SELf_SET 18457 #define PVTMON_CNTL3r_CTRL_2_0_BG_ADJf_GET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_2_0_BG_ADJf_GET 18458 #define PVTMON_CNTL3r_CTRL_2_0_BG_ADJf_SET BCMI_HURACAN_PVTMON_CNTL3r_CTRL_2_0_BG_ADJf_SET 18459 #define READ_PVTMON_CNTL3r BCMI_HURACAN_READ_PVTMON_CNTL3r 18460 #define WRITE_PVTMON_CNTL3r BCMI_HURACAN_WRITE_PVTMON_CNTL3r 18461 #define MODIFY_PVTMON_CNTL3r BCMI_HURACAN_MODIFY_PVTMON_CNTL3r 18462 18463 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18464 /******************************************************************************* 18465 * End of 'BCMI_HURACAN_PVTMON_CNTL3r' 18466 */ 18467 18468 18469 18470 18471 /******************************************************************************* 18472 * CHIP: BCMI_HURACAN 18473 * REGISTER: PVTMON_CNTL4 18474 * BLOCKS: HARD_IP_QUAD_D 18475 * REGADDR: 0xb024 18476 * DEVAD: 1 18477 * DESC: process voltage temperature sensor controls 18478 * RESETVAL: 0x0 (0) 18479 * ACCESS: R/W 18480 * FIELDS: 18481 * CTRL_DAC_DATA 18482 */ 18483 #define BCMI_HURACAN_PVTMON_CNTL4r (0x0001b024 | PHYMOD_REG_ACC_RAW) 18484 18485 #define BCMI_HURACAN_PVTMON_CNTL4r_SIZE 4 18486 18487 /* 18488 * This structure should be used to declare and program PVTMON_CNTL4. 18489 */ 18490 typedef union BCMI_HURACAN_PVTMON_CNTL4r_s { 18491 uint32_t v[1]; 18492 uint32_t pvtmon_cntl4[1]; 18493 uint32_t _pvtmon_cntl4; 18494 } BCMI_HURACAN_PVTMON_CNTL4r_t; 18495 18496 #define BCMI_HURACAN_PVTMON_CNTL4r_CLR(r) (r).pvtmon_cntl4[0] = 0 18497 #define BCMI_HURACAN_PVTMON_CNTL4r_SET(r,d) (r).pvtmon_cntl4[0] = d 18498 #define BCMI_HURACAN_PVTMON_CNTL4r_GET(r) (r).pvtmon_cntl4[0] 18499 18500 /* 18501 * These macros can be used to access individual fields. 18502 */ 18503 #define BCMI_HURACAN_PVTMON_CNTL4r_CTRL_DAC_DATAf_GET(r) (((r).pvtmon_cntl4[0]) & 0x3ff) 18504 #define BCMI_HURACAN_PVTMON_CNTL4r_CTRL_DAC_DATAf_SET(r,f) (r).pvtmon_cntl4[0]=(((r).pvtmon_cntl4[0] & ~((uint32_t)0x3ff)) | (((uint32_t)f) & 0x3ff)) | (0x3ff << 16) 18505 18506 /* 18507 * These macros can be used to access PVTMON_CNTL4. 18508 */ 18509 #define BCMI_HURACAN_READ_PVTMON_CNTL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_CNTL4r,_r._pvtmon_cntl4) 18510 #define BCMI_HURACAN_WRITE_PVTMON_CNTL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_CNTL4r,_r._pvtmon_cntl4) 18511 18512 /* 18513 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18514 * will be redefined without the chip prefix for easier programming. 18515 * If multiple chips will be programmed in the same source file, then you should 18516 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18517 * and refer to the fully qualified versions. 18518 */ 18519 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18520 18521 #define PVTMON_CNTL4r BCMI_HURACAN_PVTMON_CNTL4r 18522 #define PVTMON_CNTL4r_SIZE BCMI_HURACAN_PVTMON_CNTL4r_SIZE 18523 typedef BCMI_HURACAN_PVTMON_CNTL4r_t PVTMON_CNTL4r_t; 18524 #define PVTMON_CNTL4r_CLR BCMI_HURACAN_PVTMON_CNTL4r_CLR 18525 #define PVTMON_CNTL4r_SET BCMI_HURACAN_PVTMON_CNTL4r_SET 18526 #define PVTMON_CNTL4r_GET BCMI_HURACAN_PVTMON_CNTL4r_GET 18527 #define PVTMON_CNTL4r_CTRL_DAC_DATAf_GET BCMI_HURACAN_PVTMON_CNTL4r_CTRL_DAC_DATAf_GET 18528 #define PVTMON_CNTL4r_CTRL_DAC_DATAf_SET BCMI_HURACAN_PVTMON_CNTL4r_CTRL_DAC_DATAf_SET 18529 #define READ_PVTMON_CNTL4r BCMI_HURACAN_READ_PVTMON_CNTL4r 18530 #define WRITE_PVTMON_CNTL4r BCMI_HURACAN_WRITE_PVTMON_CNTL4r 18531 #define MODIFY_PVTMON_CNTL4r BCMI_HURACAN_MODIFY_PVTMON_CNTL4r 18532 18533 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18534 /******************************************************************************* 18535 * End of 'BCMI_HURACAN_PVTMON_CNTL4r' 18536 */ 18537 18538 18539 18540 18541 /******************************************************************************* 18542 * CHIP: BCMI_HURACAN 18543 * REGISTER: PVTMON_STATUS0 18544 * BLOCKS: HARD_IP_QUAD_D 18545 * REGADDR: 0xb025 18546 * DEVAD: 1 18547 * DESC: process voltage temperature sensor controls 18548 * RESETVAL: 0x0 (0) 18549 * ACCESS: R/W 18550 * FIELDS: 18551 * STS_O_VAVS_MINB0 18552 * STS_O_VAVS_WARNINGB0 18553 * STS_O_VAVS_MINB1 18554 * STS_O_VAVS_WARNINGB1 18555 * STS_O_VAVS_MAXB0 18556 * STS_O_VAVS_MAXB1 18557 */ 18558 #define BCMI_HURACAN_PVTMON_STATUS0r (0x0001b025 | PHYMOD_REG_ACC_RAW) 18559 18560 #define BCMI_HURACAN_PVTMON_STATUS0r_SIZE 4 18561 18562 /* 18563 * This structure should be used to declare and program PVTMON_STATUS0. 18564 */ 18565 typedef union BCMI_HURACAN_PVTMON_STATUS0r_s { 18566 uint32_t v[1]; 18567 uint32_t pvtmon_status0[1]; 18568 uint32_t _pvtmon_status0; 18569 } BCMI_HURACAN_PVTMON_STATUS0r_t; 18570 18571 #define BCMI_HURACAN_PVTMON_STATUS0r_CLR(r) (r).pvtmon_status0[0] = 0 18572 #define BCMI_HURACAN_PVTMON_STATUS0r_SET(r,d) (r).pvtmon_status0[0] = d 18573 #define BCMI_HURACAN_PVTMON_STATUS0r_GET(r) (r).pvtmon_status0[0] 18574 18575 /* 18576 * These macros can be used to access individual fields. 18577 */ 18578 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB1f_GET(r) ((((r).pvtmon_status0[0]) >> 5) & 0x1) 18579 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB1f_SET(r,f) (r).pvtmon_status0[0]=(((r).pvtmon_status0[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) | (1 << (16 + 5)) 18580 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB0f_GET(r) ((((r).pvtmon_status0[0]) >> 4) & 0x1) 18581 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB0f_SET(r,f) (r).pvtmon_status0[0]=(((r).pvtmon_status0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 18582 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB1f_GET(r) ((((r).pvtmon_status0[0]) >> 3) & 0x1) 18583 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB1f_SET(r,f) (r).pvtmon_status0[0]=(((r).pvtmon_status0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 18584 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB1f_GET(r) ((((r).pvtmon_status0[0]) >> 2) & 0x1) 18585 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB1f_SET(r,f) (r).pvtmon_status0[0]=(((r).pvtmon_status0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 18586 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB0f_GET(r) ((((r).pvtmon_status0[0]) >> 1) & 0x1) 18587 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB0f_SET(r,f) (r).pvtmon_status0[0]=(((r).pvtmon_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 18588 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB0f_GET(r) (((r).pvtmon_status0[0]) & 0x1) 18589 #define BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB0f_SET(r,f) (r).pvtmon_status0[0]=(((r).pvtmon_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 18590 18591 /* 18592 * These macros can be used to access PVTMON_STATUS0. 18593 */ 18594 #define BCMI_HURACAN_READ_PVTMON_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_STATUS0r,_r._pvtmon_status0) 18595 #define BCMI_HURACAN_WRITE_PVTMON_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_STATUS0r,_r._pvtmon_status0) 18596 18597 /* 18598 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18599 * will be redefined without the chip prefix for easier programming. 18600 * If multiple chips will be programmed in the same source file, then you should 18601 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18602 * and refer to the fully qualified versions. 18603 */ 18604 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18605 18606 #define PVTMON_STATUS0r BCMI_HURACAN_PVTMON_STATUS0r 18607 #define PVTMON_STATUS0r_SIZE BCMI_HURACAN_PVTMON_STATUS0r_SIZE 18608 typedef BCMI_HURACAN_PVTMON_STATUS0r_t PVTMON_STATUS0r_t; 18609 #define PVTMON_STATUS0r_CLR BCMI_HURACAN_PVTMON_STATUS0r_CLR 18610 #define PVTMON_STATUS0r_SET BCMI_HURACAN_PVTMON_STATUS0r_SET 18611 #define PVTMON_STATUS0r_GET BCMI_HURACAN_PVTMON_STATUS0r_GET 18612 #define PVTMON_STATUS0r_STS_O_VAVS_MAXB1f_GET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB1f_GET 18613 #define PVTMON_STATUS0r_STS_O_VAVS_MAXB1f_SET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB1f_SET 18614 #define PVTMON_STATUS0r_STS_O_VAVS_MAXB0f_GET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB0f_GET 18615 #define PVTMON_STATUS0r_STS_O_VAVS_MAXB0f_SET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MAXB0f_SET 18616 #define PVTMON_STATUS0r_STS_O_VAVS_WARNINGB1f_GET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB1f_GET 18617 #define PVTMON_STATUS0r_STS_O_VAVS_WARNINGB1f_SET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB1f_SET 18618 #define PVTMON_STATUS0r_STS_O_VAVS_MINB1f_GET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB1f_GET 18619 #define PVTMON_STATUS0r_STS_O_VAVS_MINB1f_SET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB1f_SET 18620 #define PVTMON_STATUS0r_STS_O_VAVS_WARNINGB0f_GET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB0f_GET 18621 #define PVTMON_STATUS0r_STS_O_VAVS_WARNINGB0f_SET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_WARNINGB0f_SET 18622 #define PVTMON_STATUS0r_STS_O_VAVS_MINB0f_GET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB0f_GET 18623 #define PVTMON_STATUS0r_STS_O_VAVS_MINB0f_SET BCMI_HURACAN_PVTMON_STATUS0r_STS_O_VAVS_MINB0f_SET 18624 #define READ_PVTMON_STATUS0r BCMI_HURACAN_READ_PVTMON_STATUS0r 18625 #define WRITE_PVTMON_STATUS0r BCMI_HURACAN_WRITE_PVTMON_STATUS0r 18626 #define MODIFY_PVTMON_STATUS0r BCMI_HURACAN_MODIFY_PVTMON_STATUS0r 18627 18628 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18629 /******************************************************************************* 18630 * End of 'BCMI_HURACAN_PVTMON_STATUS0r' 18631 */ 18632 18633 18634 18635 18636 /******************************************************************************* 18637 * CHIP: BCMI_HURACAN 18638 * REGISTER: PVTMON_STATUS1 18639 * BLOCKS: HARD_IP_QUAD_D 18640 * REGADDR: 0xb026 18641 * DEVAD: 1 18642 * DESC: process voltage temperature sensor controls 18643 * RESETVAL: 0x0 (0) 18644 * ACCESS: R/W 18645 * FIELDS: 18646 * STS_O_ADC_DATA 18647 * STS_O_ADC_STROBE 18648 */ 18649 #define BCMI_HURACAN_PVTMON_STATUS1r (0x0001b026 | PHYMOD_REG_ACC_RAW) 18650 18651 #define BCMI_HURACAN_PVTMON_STATUS1r_SIZE 4 18652 18653 /* 18654 * This structure should be used to declare and program PVTMON_STATUS1. 18655 */ 18656 typedef union BCMI_HURACAN_PVTMON_STATUS1r_s { 18657 uint32_t v[1]; 18658 uint32_t pvtmon_status1[1]; 18659 uint32_t _pvtmon_status1; 18660 } BCMI_HURACAN_PVTMON_STATUS1r_t; 18661 18662 #define BCMI_HURACAN_PVTMON_STATUS1r_CLR(r) (r).pvtmon_status1[0] = 0 18663 #define BCMI_HURACAN_PVTMON_STATUS1r_SET(r,d) (r).pvtmon_status1[0] = d 18664 #define BCMI_HURACAN_PVTMON_STATUS1r_GET(r) (r).pvtmon_status1[0] 18665 18666 /* 18667 * These macros can be used to access individual fields. 18668 */ 18669 #define BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_STROBEf_GET(r) ((((r).pvtmon_status1[0]) >> 12) & 0x1) 18670 #define BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_STROBEf_SET(r,f) (r).pvtmon_status1[0]=(((r).pvtmon_status1[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 18671 #define BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_DATAf_GET(r) (((r).pvtmon_status1[0]) & 0x3ff) 18672 #define BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_DATAf_SET(r,f) (r).pvtmon_status1[0]=(((r).pvtmon_status1[0] & ~((uint32_t)0x3ff)) | (((uint32_t)f) & 0x3ff)) | (0x3ff << 16) 18673 18674 /* 18675 * These macros can be used to access PVTMON_STATUS1. 18676 */ 18677 #define BCMI_HURACAN_READ_PVTMON_STATUS1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_PVTMON_STATUS1r,_r._pvtmon_status1) 18678 #define BCMI_HURACAN_WRITE_PVTMON_STATUS1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_PVTMON_STATUS1r,_r._pvtmon_status1) 18679 18680 /* 18681 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18682 * will be redefined without the chip prefix for easier programming. 18683 * If multiple chips will be programmed in the same source file, then you should 18684 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18685 * and refer to the fully qualified versions. 18686 */ 18687 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18688 18689 #define PVTMON_STATUS1r BCMI_HURACAN_PVTMON_STATUS1r 18690 #define PVTMON_STATUS1r_SIZE BCMI_HURACAN_PVTMON_STATUS1r_SIZE 18691 typedef BCMI_HURACAN_PVTMON_STATUS1r_t PVTMON_STATUS1r_t; 18692 #define PVTMON_STATUS1r_CLR BCMI_HURACAN_PVTMON_STATUS1r_CLR 18693 #define PVTMON_STATUS1r_SET BCMI_HURACAN_PVTMON_STATUS1r_SET 18694 #define PVTMON_STATUS1r_GET BCMI_HURACAN_PVTMON_STATUS1r_GET 18695 #define PVTMON_STATUS1r_STS_O_ADC_STROBEf_GET BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_STROBEf_GET 18696 #define PVTMON_STATUS1r_STS_O_ADC_STROBEf_SET BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_STROBEf_SET 18697 #define PVTMON_STATUS1r_STS_O_ADC_DATAf_GET BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_DATAf_GET 18698 #define PVTMON_STATUS1r_STS_O_ADC_DATAf_SET BCMI_HURACAN_PVTMON_STATUS1r_STS_O_ADC_DATAf_SET 18699 #define READ_PVTMON_STATUS1r BCMI_HURACAN_READ_PVTMON_STATUS1r 18700 #define WRITE_PVTMON_STATUS1r BCMI_HURACAN_WRITE_PVTMON_STATUS1r 18701 #define MODIFY_PVTMON_STATUS1r BCMI_HURACAN_MODIFY_PVTMON_STATUS1r 18702 18703 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18704 /******************************************************************************* 18705 * End of 'BCMI_HURACAN_PVTMON_STATUS1r' 18706 */ 18707 18708 18709 18710 18711 /******************************************************************************* 18712 * CHIP: BCMI_HURACAN 18713 * REGISTER: I_VR_CNTL_0_TO_15 18714 * BLOCKS: HARD_IP_QUAD_D 18715 * REGADDR: 0xb030 18716 * DEVAD: 1 18717 * DESC: i_vr_cntl_0_to_15 voltage regulator control bits 18718 * RESETVAL: 0x0 (0) 18719 * ACCESS: R/W 18720 * FIELDS: 18721 * I_VR_CNTL0 18722 */ 18723 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r (0x0001b030 | PHYMOD_REG_ACC_RAW) 18724 18725 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r_SIZE 4 18726 18727 /* 18728 * This structure should be used to declare and program I_VR_CNTL_0_TO_15. 18729 */ 18730 typedef union BCMI_HURACAN_I_VR_CNTL_0_TO_15r_s { 18731 uint32_t v[1]; 18732 uint32_t i_vr_cntl_0_to_15[1]; 18733 uint32_t _i_vr_cntl_0_to_15; 18734 } BCMI_HURACAN_I_VR_CNTL_0_TO_15r_t; 18735 18736 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r_CLR(r) (r).i_vr_cntl_0_to_15[0] = 0 18737 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r_SET(r,d) (r).i_vr_cntl_0_to_15[0] = d 18738 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r_GET(r) (r).i_vr_cntl_0_to_15[0] 18739 18740 /* 18741 * These macros can be used to access individual fields. 18742 */ 18743 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r_I_VR_CNTL0f_GET(r) (((r).i_vr_cntl_0_to_15[0]) & 0xffff) 18744 #define BCMI_HURACAN_I_VR_CNTL_0_TO_15r_I_VR_CNTL0f_SET(r,f) (r).i_vr_cntl_0_to_15[0]=(((r).i_vr_cntl_0_to_15[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 18745 18746 /* 18747 * These macros can be used to access I_VR_CNTL_0_TO_15. 18748 */ 18749 #define BCMI_HURACAN_READ_I_VR_CNTL_0_TO_15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_I_VR_CNTL_0_TO_15r,_r._i_vr_cntl_0_to_15) 18750 #define BCMI_HURACAN_WRITE_I_VR_CNTL_0_TO_15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_I_VR_CNTL_0_TO_15r,_r._i_vr_cntl_0_to_15) 18751 18752 /* 18753 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18754 * will be redefined without the chip prefix for easier programming. 18755 * If multiple chips will be programmed in the same source file, then you should 18756 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18757 * and refer to the fully qualified versions. 18758 */ 18759 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18760 18761 #define I_VR_CNTL_0_TO_15r BCMI_HURACAN_I_VR_CNTL_0_TO_15r 18762 #define I_VR_CNTL_0_TO_15r_SIZE BCMI_HURACAN_I_VR_CNTL_0_TO_15r_SIZE 18763 typedef BCMI_HURACAN_I_VR_CNTL_0_TO_15r_t I_VR_CNTL_0_TO_15r_t; 18764 #define I_VR_CNTL_0_TO_15r_CLR BCMI_HURACAN_I_VR_CNTL_0_TO_15r_CLR 18765 #define I_VR_CNTL_0_TO_15r_SET BCMI_HURACAN_I_VR_CNTL_0_TO_15r_SET 18766 #define I_VR_CNTL_0_TO_15r_GET BCMI_HURACAN_I_VR_CNTL_0_TO_15r_GET 18767 #define I_VR_CNTL_0_TO_15r_I_VR_CNTL0f_GET BCMI_HURACAN_I_VR_CNTL_0_TO_15r_I_VR_CNTL0f_GET 18768 #define I_VR_CNTL_0_TO_15r_I_VR_CNTL0f_SET BCMI_HURACAN_I_VR_CNTL_0_TO_15r_I_VR_CNTL0f_SET 18769 #define READ_I_VR_CNTL_0_TO_15r BCMI_HURACAN_READ_I_VR_CNTL_0_TO_15r 18770 #define WRITE_I_VR_CNTL_0_TO_15r BCMI_HURACAN_WRITE_I_VR_CNTL_0_TO_15r 18771 #define MODIFY_I_VR_CNTL_0_TO_15r BCMI_HURACAN_MODIFY_I_VR_CNTL_0_TO_15r 18772 18773 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18774 /******************************************************************************* 18775 * End of 'BCMI_HURACAN_I_VR_CNTL_0_TO_15r' 18776 */ 18777 18778 18779 18780 18781 /******************************************************************************* 18782 * CHIP: BCMI_HURACAN 18783 * REGISTER: I_VR_CNTL_16_TO_18 18784 * BLOCKS: HARD_IP_QUAD_D 18785 * REGADDR: 0xb031 18786 * DEVAD: 1 18787 * DESC: i_vr_cntl_16_to_18 voltage regulator control bits 18788 * RESETVAL: 0x0 (0) 18789 * ACCESS: R/W 18790 * FIELDS: 18791 * I_VR_CNTL1 18792 */ 18793 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r (0x0001b031 | PHYMOD_REG_ACC_RAW) 18794 18795 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r_SIZE 4 18796 18797 /* 18798 * This structure should be used to declare and program I_VR_CNTL_16_TO_18. 18799 */ 18800 typedef union BCMI_HURACAN_I_VR_CNTL_16_TO_18r_s { 18801 uint32_t v[1]; 18802 uint32_t i_vr_cntl_16_to_18[1]; 18803 uint32_t _i_vr_cntl_16_to_18; 18804 } BCMI_HURACAN_I_VR_CNTL_16_TO_18r_t; 18805 18806 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r_CLR(r) (r).i_vr_cntl_16_to_18[0] = 0 18807 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r_SET(r,d) (r).i_vr_cntl_16_to_18[0] = d 18808 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r_GET(r) (r).i_vr_cntl_16_to_18[0] 18809 18810 /* 18811 * These macros can be used to access individual fields. 18812 */ 18813 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r_I_VR_CNTL1f_GET(r) (((r).i_vr_cntl_16_to_18[0]) & 0x7) 18814 #define BCMI_HURACAN_I_VR_CNTL_16_TO_18r_I_VR_CNTL1f_SET(r,f) (r).i_vr_cntl_16_to_18[0]=(((r).i_vr_cntl_16_to_18[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 18815 18816 /* 18817 * These macros can be used to access I_VR_CNTL_16_TO_18. 18818 */ 18819 #define BCMI_HURACAN_READ_I_VR_CNTL_16_TO_18r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_I_VR_CNTL_16_TO_18r,_r._i_vr_cntl_16_to_18) 18820 #define BCMI_HURACAN_WRITE_I_VR_CNTL_16_TO_18r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_I_VR_CNTL_16_TO_18r,_r._i_vr_cntl_16_to_18) 18821 18822 /* 18823 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18824 * will be redefined without the chip prefix for easier programming. 18825 * If multiple chips will be programmed in the same source file, then you should 18826 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18827 * and refer to the fully qualified versions. 18828 */ 18829 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18830 18831 #define I_VR_CNTL_16_TO_18r BCMI_HURACAN_I_VR_CNTL_16_TO_18r 18832 #define I_VR_CNTL_16_TO_18r_SIZE BCMI_HURACAN_I_VR_CNTL_16_TO_18r_SIZE 18833 typedef BCMI_HURACAN_I_VR_CNTL_16_TO_18r_t I_VR_CNTL_16_TO_18r_t; 18834 #define I_VR_CNTL_16_TO_18r_CLR BCMI_HURACAN_I_VR_CNTL_16_TO_18r_CLR 18835 #define I_VR_CNTL_16_TO_18r_SET BCMI_HURACAN_I_VR_CNTL_16_TO_18r_SET 18836 #define I_VR_CNTL_16_TO_18r_GET BCMI_HURACAN_I_VR_CNTL_16_TO_18r_GET 18837 #define I_VR_CNTL_16_TO_18r_I_VR_CNTL1f_GET BCMI_HURACAN_I_VR_CNTL_16_TO_18r_I_VR_CNTL1f_GET 18838 #define I_VR_CNTL_16_TO_18r_I_VR_CNTL1f_SET BCMI_HURACAN_I_VR_CNTL_16_TO_18r_I_VR_CNTL1f_SET 18839 #define READ_I_VR_CNTL_16_TO_18r BCMI_HURACAN_READ_I_VR_CNTL_16_TO_18r 18840 #define WRITE_I_VR_CNTL_16_TO_18r BCMI_HURACAN_WRITE_I_VR_CNTL_16_TO_18r 18841 #define MODIFY_I_VR_CNTL_16_TO_18r BCMI_HURACAN_MODIFY_I_VR_CNTL_16_TO_18r 18842 18843 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18844 /******************************************************************************* 18845 * End of 'BCMI_HURACAN_I_VR_CNTL_16_TO_18r' 18846 */ 18847 18848 18849 18850 18851 /******************************************************************************* 18852 * CHIP: BCMI_HURACAN 18853 * REGISTER: I_VR_PWRDN_CNTL 18854 * BLOCKS: HARD_IP_QUAD_D 18855 * REGADDR: 0xb032 18856 * DEVAD: 1 18857 * DESC: i_vr_pwrdn_cntl voltage regulator control bits 18858 * RESETVAL: 0x0 (0) 18859 * ACCESS: R/W 18860 * FIELDS: 18861 * I_VR_PWRDN 18862 */ 18863 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr (0x0001b032 | PHYMOD_REG_ACC_RAW) 18864 18865 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr_SIZE 4 18866 18867 /* 18868 * This structure should be used to declare and program I_VR_PWRDN_CNTL. 18869 */ 18870 typedef union BCMI_HURACAN_I_VR_PWRDN_CNTLr_s { 18871 uint32_t v[1]; 18872 uint32_t i_vr_pwrdn_cntl[1]; 18873 uint32_t _i_vr_pwrdn_cntl; 18874 } BCMI_HURACAN_I_VR_PWRDN_CNTLr_t; 18875 18876 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr_CLR(r) (r).i_vr_pwrdn_cntl[0] = 0 18877 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr_SET(r,d) (r).i_vr_pwrdn_cntl[0] = d 18878 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr_GET(r) (r).i_vr_pwrdn_cntl[0] 18879 18880 /* 18881 * These macros can be used to access individual fields. 18882 */ 18883 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr_I_VR_PWRDNf_GET(r) (((r).i_vr_pwrdn_cntl[0]) & 0x1) 18884 #define BCMI_HURACAN_I_VR_PWRDN_CNTLr_I_VR_PWRDNf_SET(r,f) (r).i_vr_pwrdn_cntl[0]=(((r).i_vr_pwrdn_cntl[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 18885 18886 /* 18887 * These macros can be used to access I_VR_PWRDN_CNTL. 18888 */ 18889 #define BCMI_HURACAN_READ_I_VR_PWRDN_CNTLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_I_VR_PWRDN_CNTLr,_r._i_vr_pwrdn_cntl) 18890 #define BCMI_HURACAN_WRITE_I_VR_PWRDN_CNTLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_I_VR_PWRDN_CNTLr,_r._i_vr_pwrdn_cntl) 18891 18892 /* 18893 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18894 * will be redefined without the chip prefix for easier programming. 18895 * If multiple chips will be programmed in the same source file, then you should 18896 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18897 * and refer to the fully qualified versions. 18898 */ 18899 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18900 18901 #define I_VR_PWRDN_CNTLr BCMI_HURACAN_I_VR_PWRDN_CNTLr 18902 #define I_VR_PWRDN_CNTLr_SIZE BCMI_HURACAN_I_VR_PWRDN_CNTLr_SIZE 18903 typedef BCMI_HURACAN_I_VR_PWRDN_CNTLr_t I_VR_PWRDN_CNTLr_t; 18904 #define I_VR_PWRDN_CNTLr_CLR BCMI_HURACAN_I_VR_PWRDN_CNTLr_CLR 18905 #define I_VR_PWRDN_CNTLr_SET BCMI_HURACAN_I_VR_PWRDN_CNTLr_SET 18906 #define I_VR_PWRDN_CNTLr_GET BCMI_HURACAN_I_VR_PWRDN_CNTLr_GET 18907 #define I_VR_PWRDN_CNTLr_I_VR_PWRDNf_GET BCMI_HURACAN_I_VR_PWRDN_CNTLr_I_VR_PWRDNf_GET 18908 #define I_VR_PWRDN_CNTLr_I_VR_PWRDNf_SET BCMI_HURACAN_I_VR_PWRDN_CNTLr_I_VR_PWRDNf_SET 18909 #define READ_I_VR_PWRDN_CNTLr BCMI_HURACAN_READ_I_VR_PWRDN_CNTLr 18910 #define WRITE_I_VR_PWRDN_CNTLr BCMI_HURACAN_WRITE_I_VR_PWRDN_CNTLr 18911 #define MODIFY_I_VR_PWRDN_CNTLr BCMI_HURACAN_MODIFY_I_VR_PWRDN_CNTLr 18912 18913 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18914 /******************************************************************************* 18915 * End of 'BCMI_HURACAN_I_VR_PWRDN_CNTLr' 18916 */ 18917 18918 18919 18920 18921 /******************************************************************************* 18922 * CHIP: BCMI_HURACAN 18923 * REGISTER: I_VR_CNTL_ENABLE 18924 * BLOCKS: HARD_IP_QUAD_D 18925 * REGADDR: 0xb033 18926 * DEVAD: 1 18927 * DESC: i_vr_cntl_enable enable the voltage regulator 18928 * RESETVAL: 0x0 (0) 18929 * ACCESS: R/W 18930 * FIELDS: 18931 * I_VR_CNTL_EN 18932 */ 18933 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr (0x0001b033 | PHYMOD_REG_ACC_RAW) 18934 18935 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr_SIZE 4 18936 18937 /* 18938 * This structure should be used to declare and program I_VR_CNTL_ENABLE. 18939 */ 18940 typedef union BCMI_HURACAN_I_VR_CNTL_ENABLEr_s { 18941 uint32_t v[1]; 18942 uint32_t i_vr_cntl_enable[1]; 18943 uint32_t _i_vr_cntl_enable; 18944 } BCMI_HURACAN_I_VR_CNTL_ENABLEr_t; 18945 18946 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr_CLR(r) (r).i_vr_cntl_enable[0] = 0 18947 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr_SET(r,d) (r).i_vr_cntl_enable[0] = d 18948 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr_GET(r) (r).i_vr_cntl_enable[0] 18949 18950 /* 18951 * These macros can be used to access individual fields. 18952 */ 18953 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr_I_VR_CNTL_ENf_GET(r) (((r).i_vr_cntl_enable[0]) & 0x1) 18954 #define BCMI_HURACAN_I_VR_CNTL_ENABLEr_I_VR_CNTL_ENf_SET(r,f) (r).i_vr_cntl_enable[0]=(((r).i_vr_cntl_enable[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 18955 18956 /* 18957 * These macros can be used to access I_VR_CNTL_ENABLE. 18958 */ 18959 #define BCMI_HURACAN_READ_I_VR_CNTL_ENABLEr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_I_VR_CNTL_ENABLEr,_r._i_vr_cntl_enable) 18960 #define BCMI_HURACAN_WRITE_I_VR_CNTL_ENABLEr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_I_VR_CNTL_ENABLEr,_r._i_vr_cntl_enable) 18961 18962 /* 18963 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 18964 * will be redefined without the chip prefix for easier programming. 18965 * If multiple chips will be programmed in the same source file, then you should 18966 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 18967 * and refer to the fully qualified versions. 18968 */ 18969 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 18970 18971 #define I_VR_CNTL_ENABLEr BCMI_HURACAN_I_VR_CNTL_ENABLEr 18972 #define I_VR_CNTL_ENABLEr_SIZE BCMI_HURACAN_I_VR_CNTL_ENABLEr_SIZE 18973 typedef BCMI_HURACAN_I_VR_CNTL_ENABLEr_t I_VR_CNTL_ENABLEr_t; 18974 #define I_VR_CNTL_ENABLEr_CLR BCMI_HURACAN_I_VR_CNTL_ENABLEr_CLR 18975 #define I_VR_CNTL_ENABLEr_SET BCMI_HURACAN_I_VR_CNTL_ENABLEr_SET 18976 #define I_VR_CNTL_ENABLEr_GET BCMI_HURACAN_I_VR_CNTL_ENABLEr_GET 18977 #define I_VR_CNTL_ENABLEr_I_VR_CNTL_ENf_GET BCMI_HURACAN_I_VR_CNTL_ENABLEr_I_VR_CNTL_ENf_GET 18978 #define I_VR_CNTL_ENABLEr_I_VR_CNTL_ENf_SET BCMI_HURACAN_I_VR_CNTL_ENABLEr_I_VR_CNTL_ENf_SET 18979 #define READ_I_VR_CNTL_ENABLEr BCMI_HURACAN_READ_I_VR_CNTL_ENABLEr 18980 #define WRITE_I_VR_CNTL_ENABLEr BCMI_HURACAN_WRITE_I_VR_CNTL_ENABLEr 18981 #define MODIFY_I_VR_CNTL_ENABLEr BCMI_HURACAN_MODIFY_I_VR_CNTL_ENABLEr 18982 18983 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 18984 /******************************************************************************* 18985 * End of 'BCMI_HURACAN_I_VR_CNTL_ENABLEr' 18986 */ 18987 18988 18989 18990 18991 /******************************************************************************* 18992 * CHIP: BCMI_HURACAN 18993 * REGISTER: RESCAL_STS1 18994 * BLOCKS: HARD_IP_QUAD_D 18995 * REGADDR: 0xb040 18996 * DEVAD: 1 18997 * DESC: status register-1 holds various debug signals 18998 * RESETVAL: 0x0 (0) 18999 * ACCESS: R/W 19000 * FIELDS: 19001 * O_RESCAL_CTRL_DFS 19002 * O_VALID 19003 */ 19004 #define BCMI_HURACAN_RESCAL_STS1r (0x0001b040 | PHYMOD_REG_ACC_RAW) 19005 19006 #define BCMI_HURACAN_RESCAL_STS1r_SIZE 4 19007 19008 /* 19009 * This structure should be used to declare and program RESCAL_STS1. 19010 */ 19011 typedef union BCMI_HURACAN_RESCAL_STS1r_s { 19012 uint32_t v[1]; 19013 uint32_t rescal_sts1[1]; 19014 uint32_t _rescal_sts1; 19015 } BCMI_HURACAN_RESCAL_STS1r_t; 19016 19017 #define BCMI_HURACAN_RESCAL_STS1r_CLR(r) (r).rescal_sts1[0] = 0 19018 #define BCMI_HURACAN_RESCAL_STS1r_SET(r,d) (r).rescal_sts1[0] = d 19019 #define BCMI_HURACAN_RESCAL_STS1r_GET(r) (r).rescal_sts1[0] 19020 19021 /* 19022 * These macros can be used to access individual fields. 19023 */ 19024 #define BCMI_HURACAN_RESCAL_STS1r_O_VALIDf_GET(r) ((((r).rescal_sts1[0]) >> 13) & 0x1) 19025 #define BCMI_HURACAN_RESCAL_STS1r_O_VALIDf_SET(r,f) (r).rescal_sts1[0]=(((r).rescal_sts1[0] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) | (1 << (16 + 13)) 19026 #define BCMI_HURACAN_RESCAL_STS1r_O_RESCAL_CTRL_DFSf_GET(r) (((r).rescal_sts1[0]) & 0x1fff) 19027 #define BCMI_HURACAN_RESCAL_STS1r_O_RESCAL_CTRL_DFSf_SET(r,f) (r).rescal_sts1[0]=(((r).rescal_sts1[0] & ~((uint32_t)0x1fff)) | (((uint32_t)f) & 0x1fff)) | (0x1fff << 16) 19028 19029 /* 19030 * These macros can be used to access RESCAL_STS1. 19031 */ 19032 #define BCMI_HURACAN_READ_RESCAL_STS1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_RESCAL_STS1r,_r._rescal_sts1) 19033 #define BCMI_HURACAN_WRITE_RESCAL_STS1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_RESCAL_STS1r,_r._rescal_sts1) 19034 19035 /* 19036 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19037 * will be redefined without the chip prefix for easier programming. 19038 * If multiple chips will be programmed in the same source file, then you should 19039 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19040 * and refer to the fully qualified versions. 19041 */ 19042 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19043 19044 #define RESCAL_STS1r BCMI_HURACAN_RESCAL_STS1r 19045 #define RESCAL_STS1r_SIZE BCMI_HURACAN_RESCAL_STS1r_SIZE 19046 typedef BCMI_HURACAN_RESCAL_STS1r_t RESCAL_STS1r_t; 19047 #define RESCAL_STS1r_CLR BCMI_HURACAN_RESCAL_STS1r_CLR 19048 #define RESCAL_STS1r_SET BCMI_HURACAN_RESCAL_STS1r_SET 19049 #define RESCAL_STS1r_GET BCMI_HURACAN_RESCAL_STS1r_GET 19050 #define RESCAL_STS1r_O_VALIDf_GET BCMI_HURACAN_RESCAL_STS1r_O_VALIDf_GET 19051 #define RESCAL_STS1r_O_VALIDf_SET BCMI_HURACAN_RESCAL_STS1r_O_VALIDf_SET 19052 #define RESCAL_STS1r_O_RESCAL_CTRL_DFSf_GET BCMI_HURACAN_RESCAL_STS1r_O_RESCAL_CTRL_DFSf_GET 19053 #define RESCAL_STS1r_O_RESCAL_CTRL_DFSf_SET BCMI_HURACAN_RESCAL_STS1r_O_RESCAL_CTRL_DFSf_SET 19054 #define READ_RESCAL_STS1r BCMI_HURACAN_READ_RESCAL_STS1r 19055 #define WRITE_RESCAL_STS1r BCMI_HURACAN_WRITE_RESCAL_STS1r 19056 #define MODIFY_RESCAL_STS1r BCMI_HURACAN_MODIFY_RESCAL_STS1r 19057 19058 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19059 /******************************************************************************* 19060 * End of 'BCMI_HURACAN_RESCAL_STS1r' 19061 */ 19062 19063 19064 19065 19066 /******************************************************************************* 19067 * CHIP: BCMI_HURACAN 19068 * REGISTER: RESCAL_STS2 19069 * BLOCKS: HARD_IP_QUAD_D 19070 * REGADDR: 0xb041 19071 * DEVAD: 1 19072 * DESC: status register-2 holds various debug signals 19073 * RESETVAL: 0x0 (0) 19074 * ACCESS: R/W 19075 * FIELDS: 19076 * O_RESCAL_STATE 19077 * O_RESCALCOMP 19078 * O_PREV_COMP_CNT 19079 * O_CURR_COMP_CNT 19080 */ 19081 #define BCMI_HURACAN_RESCAL_STS2r (0x0001b041 | PHYMOD_REG_ACC_RAW) 19082 19083 #define BCMI_HURACAN_RESCAL_STS2r_SIZE 4 19084 19085 /* 19086 * This structure should be used to declare and program RESCAL_STS2. 19087 */ 19088 typedef union BCMI_HURACAN_RESCAL_STS2r_s { 19089 uint32_t v[1]; 19090 uint32_t rescal_sts2[1]; 19091 uint32_t _rescal_sts2; 19092 } BCMI_HURACAN_RESCAL_STS2r_t; 19093 19094 #define BCMI_HURACAN_RESCAL_STS2r_CLR(r) (r).rescal_sts2[0] = 0 19095 #define BCMI_HURACAN_RESCAL_STS2r_SET(r,d) (r).rescal_sts2[0] = d 19096 #define BCMI_HURACAN_RESCAL_STS2r_GET(r) (r).rescal_sts2[0] 19097 19098 /* 19099 * These macros can be used to access individual fields. 19100 */ 19101 #define BCMI_HURACAN_RESCAL_STS2r_O_CURR_COMP_CNTf_GET(r) ((((r).rescal_sts2[0]) >> 8) & 0x3f) 19102 #define BCMI_HURACAN_RESCAL_STS2r_O_CURR_COMP_CNTf_SET(r,f) (r).rescal_sts2[0]=(((r).rescal_sts2[0] & ~((uint32_t)0x3f << 8)) | ((((uint32_t)f) & 0x3f) << 8)) | (63 << (16 + 8)) 19103 #define BCMI_HURACAN_RESCAL_STS2r_O_PREV_COMP_CNTf_GET(r) ((((r).rescal_sts2[0]) >> 4) & 0xf) 19104 #define BCMI_HURACAN_RESCAL_STS2r_O_PREV_COMP_CNTf_SET(r,f) (r).rescal_sts2[0]=(((r).rescal_sts2[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 19105 #define BCMI_HURACAN_RESCAL_STS2r_O_RESCALCOMPf_GET(r) ((((r).rescal_sts2[0]) >> 3) & 0x1) 19106 #define BCMI_HURACAN_RESCAL_STS2r_O_RESCALCOMPf_SET(r,f) (r).rescal_sts2[0]=(((r).rescal_sts2[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 19107 #define BCMI_HURACAN_RESCAL_STS2r_O_RESCAL_STATEf_GET(r) (((r).rescal_sts2[0]) & 0x7) 19108 #define BCMI_HURACAN_RESCAL_STS2r_O_RESCAL_STATEf_SET(r,f) (r).rescal_sts2[0]=(((r).rescal_sts2[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 19109 19110 /* 19111 * These macros can be used to access RESCAL_STS2. 19112 */ 19113 #define BCMI_HURACAN_READ_RESCAL_STS2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_RESCAL_STS2r,_r._rescal_sts2) 19114 #define BCMI_HURACAN_WRITE_RESCAL_STS2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_RESCAL_STS2r,_r._rescal_sts2) 19115 19116 /* 19117 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19118 * will be redefined without the chip prefix for easier programming. 19119 * If multiple chips will be programmed in the same source file, then you should 19120 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19121 * and refer to the fully qualified versions. 19122 */ 19123 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19124 19125 #define RESCAL_STS2r BCMI_HURACAN_RESCAL_STS2r 19126 #define RESCAL_STS2r_SIZE BCMI_HURACAN_RESCAL_STS2r_SIZE 19127 typedef BCMI_HURACAN_RESCAL_STS2r_t RESCAL_STS2r_t; 19128 #define RESCAL_STS2r_CLR BCMI_HURACAN_RESCAL_STS2r_CLR 19129 #define RESCAL_STS2r_SET BCMI_HURACAN_RESCAL_STS2r_SET 19130 #define RESCAL_STS2r_GET BCMI_HURACAN_RESCAL_STS2r_GET 19131 #define RESCAL_STS2r_O_CURR_COMP_CNTf_GET BCMI_HURACAN_RESCAL_STS2r_O_CURR_COMP_CNTf_GET 19132 #define RESCAL_STS2r_O_CURR_COMP_CNTf_SET BCMI_HURACAN_RESCAL_STS2r_O_CURR_COMP_CNTf_SET 19133 #define RESCAL_STS2r_O_PREV_COMP_CNTf_GET BCMI_HURACAN_RESCAL_STS2r_O_PREV_COMP_CNTf_GET 19134 #define RESCAL_STS2r_O_PREV_COMP_CNTf_SET BCMI_HURACAN_RESCAL_STS2r_O_PREV_COMP_CNTf_SET 19135 #define RESCAL_STS2r_O_RESCALCOMPf_GET BCMI_HURACAN_RESCAL_STS2r_O_RESCALCOMPf_GET 19136 #define RESCAL_STS2r_O_RESCALCOMPf_SET BCMI_HURACAN_RESCAL_STS2r_O_RESCALCOMPf_SET 19137 #define RESCAL_STS2r_O_RESCAL_STATEf_GET BCMI_HURACAN_RESCAL_STS2r_O_RESCAL_STATEf_GET 19138 #define RESCAL_STS2r_O_RESCAL_STATEf_SET BCMI_HURACAN_RESCAL_STS2r_O_RESCAL_STATEf_SET 19139 #define READ_RESCAL_STS2r BCMI_HURACAN_READ_RESCAL_STS2r 19140 #define WRITE_RESCAL_STS2r BCMI_HURACAN_WRITE_RESCAL_STS2r 19141 #define MODIFY_RESCAL_STS2r BCMI_HURACAN_MODIFY_RESCAL_STS2r 19142 19143 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19144 /******************************************************************************* 19145 * End of 'BCMI_HURACAN_RESCAL_STS2r' 19146 */ 19147 19148 19149 19150 19151 /******************************************************************************* 19152 * CHIP: BCMI_HURACAN 19153 * REGISTER: RESCAL_STS3 19154 * BLOCKS: HARD_IP_QUAD_D 19155 * REGADDR: 0xb042 19156 * DEVAD: 1 19157 * DESC: status register-3 holds result of rescal computation 19158 * RESETVAL: 0x0 (0) 19159 * ACCESS: R/W 19160 * FIELDS: 19161 * O_PON 19162 * O_DONE 19163 */ 19164 #define BCMI_HURACAN_RESCAL_STS3r (0x0001b042 | PHYMOD_REG_ACC_RAW) 19165 19166 #define BCMI_HURACAN_RESCAL_STS3r_SIZE 4 19167 19168 /* 19169 * This structure should be used to declare and program RESCAL_STS3. 19170 */ 19171 typedef union BCMI_HURACAN_RESCAL_STS3r_s { 19172 uint32_t v[1]; 19173 uint32_t rescal_sts3[1]; 19174 uint32_t _rescal_sts3; 19175 } BCMI_HURACAN_RESCAL_STS3r_t; 19176 19177 #define BCMI_HURACAN_RESCAL_STS3r_CLR(r) (r).rescal_sts3[0] = 0 19178 #define BCMI_HURACAN_RESCAL_STS3r_SET(r,d) (r).rescal_sts3[0] = d 19179 #define BCMI_HURACAN_RESCAL_STS3r_GET(r) (r).rescal_sts3[0] 19180 19181 /* 19182 * These macros can be used to access individual fields. 19183 */ 19184 #define BCMI_HURACAN_RESCAL_STS3r_O_DONEf_GET(r) ((((r).rescal_sts3[0]) >> 4) & 0x1) 19185 #define BCMI_HURACAN_RESCAL_STS3r_O_DONEf_SET(r,f) (r).rescal_sts3[0]=(((r).rescal_sts3[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 19186 #define BCMI_HURACAN_RESCAL_STS3r_O_PONf_GET(r) (((r).rescal_sts3[0]) & 0xf) 19187 #define BCMI_HURACAN_RESCAL_STS3r_O_PONf_SET(r,f) (r).rescal_sts3[0]=(((r).rescal_sts3[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 19188 19189 /* 19190 * These macros can be used to access RESCAL_STS3. 19191 */ 19192 #define BCMI_HURACAN_READ_RESCAL_STS3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_RESCAL_STS3r,_r._rescal_sts3) 19193 #define BCMI_HURACAN_WRITE_RESCAL_STS3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_RESCAL_STS3r,_r._rescal_sts3) 19194 19195 /* 19196 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19197 * will be redefined without the chip prefix for easier programming. 19198 * If multiple chips will be programmed in the same source file, then you should 19199 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19200 * and refer to the fully qualified versions. 19201 */ 19202 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19203 19204 #define RESCAL_STS3r BCMI_HURACAN_RESCAL_STS3r 19205 #define RESCAL_STS3r_SIZE BCMI_HURACAN_RESCAL_STS3r_SIZE 19206 typedef BCMI_HURACAN_RESCAL_STS3r_t RESCAL_STS3r_t; 19207 #define RESCAL_STS3r_CLR BCMI_HURACAN_RESCAL_STS3r_CLR 19208 #define RESCAL_STS3r_SET BCMI_HURACAN_RESCAL_STS3r_SET 19209 #define RESCAL_STS3r_GET BCMI_HURACAN_RESCAL_STS3r_GET 19210 #define RESCAL_STS3r_O_DONEf_GET BCMI_HURACAN_RESCAL_STS3r_O_DONEf_GET 19211 #define RESCAL_STS3r_O_DONEf_SET BCMI_HURACAN_RESCAL_STS3r_O_DONEf_SET 19212 #define RESCAL_STS3r_O_PONf_GET BCMI_HURACAN_RESCAL_STS3r_O_PONf_GET 19213 #define RESCAL_STS3r_O_PONf_SET BCMI_HURACAN_RESCAL_STS3r_O_PONf_SET 19214 #define READ_RESCAL_STS3r BCMI_HURACAN_READ_RESCAL_STS3r 19215 #define WRITE_RESCAL_STS3r BCMI_HURACAN_WRITE_RESCAL_STS3r 19216 #define MODIFY_RESCAL_STS3r BCMI_HURACAN_MODIFY_RESCAL_STS3r 19217 19218 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19219 /******************************************************************************* 19220 * End of 'BCMI_HURACAN_RESCAL_STS3r' 19221 */ 19222 19223 19224 19225 19226 /******************************************************************************* 19227 * CHIP: BCMI_HURACAN 19228 * REGISTER: RESCAL_CTRL0 19229 * BLOCKS: HARD_IP_QUAD_D 19230 * REGADDR: 0xb043 19231 * DEVAD: 1 19232 * DESC: control register for the rescal block 19233 * RESETVAL: 0x0 (0) 19234 * ACCESS: R/W 19235 * FIELDS: 19236 * I_RESCAL_CTRL 19237 */ 19238 #define BCMI_HURACAN_RESCAL_CTRL0r (0x0001b043 | PHYMOD_REG_ACC_RAW) 19239 19240 #define BCMI_HURACAN_RESCAL_CTRL0r_SIZE 4 19241 19242 /* 19243 * This structure should be used to declare and program RESCAL_CTRL0. 19244 */ 19245 typedef union BCMI_HURACAN_RESCAL_CTRL0r_s { 19246 uint32_t v[1]; 19247 uint32_t rescal_ctrl0[1]; 19248 uint32_t _rescal_ctrl0; 19249 } BCMI_HURACAN_RESCAL_CTRL0r_t; 19250 19251 #define BCMI_HURACAN_RESCAL_CTRL0r_CLR(r) (r).rescal_ctrl0[0] = 0 19252 #define BCMI_HURACAN_RESCAL_CTRL0r_SET(r,d) (r).rescal_ctrl0[0] = d 19253 #define BCMI_HURACAN_RESCAL_CTRL0r_GET(r) (r).rescal_ctrl0[0] 19254 19255 /* 19256 * These macros can be used to access individual fields. 19257 */ 19258 #define BCMI_HURACAN_RESCAL_CTRL0r_I_RESCAL_CTRLf_GET(r) (((r).rescal_ctrl0[0]) & 0x1fff) 19259 #define BCMI_HURACAN_RESCAL_CTRL0r_I_RESCAL_CTRLf_SET(r,f) (r).rescal_ctrl0[0]=(((r).rescal_ctrl0[0] & ~((uint32_t)0x1fff)) | (((uint32_t)f) & 0x1fff)) | (0x1fff << 16) 19260 19261 /* 19262 * These macros can be used to access RESCAL_CTRL0. 19263 */ 19264 #define BCMI_HURACAN_READ_RESCAL_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_RESCAL_CTRL0r,_r._rescal_ctrl0) 19265 #define BCMI_HURACAN_WRITE_RESCAL_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_RESCAL_CTRL0r,_r._rescal_ctrl0) 19266 19267 /* 19268 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19269 * will be redefined without the chip prefix for easier programming. 19270 * If multiple chips will be programmed in the same source file, then you should 19271 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19272 * and refer to the fully qualified versions. 19273 */ 19274 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19275 19276 #define RESCAL_CTRL0r BCMI_HURACAN_RESCAL_CTRL0r 19277 #define RESCAL_CTRL0r_SIZE BCMI_HURACAN_RESCAL_CTRL0r_SIZE 19278 typedef BCMI_HURACAN_RESCAL_CTRL0r_t RESCAL_CTRL0r_t; 19279 #define RESCAL_CTRL0r_CLR BCMI_HURACAN_RESCAL_CTRL0r_CLR 19280 #define RESCAL_CTRL0r_SET BCMI_HURACAN_RESCAL_CTRL0r_SET 19281 #define RESCAL_CTRL0r_GET BCMI_HURACAN_RESCAL_CTRL0r_GET 19282 #define RESCAL_CTRL0r_I_RESCAL_CTRLf_GET BCMI_HURACAN_RESCAL_CTRL0r_I_RESCAL_CTRLf_GET 19283 #define RESCAL_CTRL0r_I_RESCAL_CTRLf_SET BCMI_HURACAN_RESCAL_CTRL0r_I_RESCAL_CTRLf_SET 19284 #define READ_RESCAL_CTRL0r BCMI_HURACAN_READ_RESCAL_CTRL0r 19285 #define WRITE_RESCAL_CTRL0r BCMI_HURACAN_WRITE_RESCAL_CTRL0r 19286 #define MODIFY_RESCAL_CTRL0r BCMI_HURACAN_MODIFY_RESCAL_CTRL0r 19287 19288 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19289 /******************************************************************************* 19290 * End of 'BCMI_HURACAN_RESCAL_CTRL0r' 19291 */ 19292 19293 19294 19295 19296 /******************************************************************************* 19297 * CHIP: BCMI_HURACAN 19298 * REGISTER: RESCAL_CTRL1 19299 * BLOCKS: HARD_IP_QUAD_D 19300 * REGADDR: 0xb044 19301 * DEVAD: 1 19302 * DESC: control register for the rescal block 19303 * RESETVAL: 0x0 (0) 19304 * ACCESS: R/W 19305 * FIELDS: 19306 * I_PWRDN 19307 * I_DIAG_ON 19308 */ 19309 #define BCMI_HURACAN_RESCAL_CTRL1r (0x0001b044 | PHYMOD_REG_ACC_RAW) 19310 19311 #define BCMI_HURACAN_RESCAL_CTRL1r_SIZE 4 19312 19313 /* 19314 * This structure should be used to declare and program RESCAL_CTRL1. 19315 */ 19316 typedef union BCMI_HURACAN_RESCAL_CTRL1r_s { 19317 uint32_t v[1]; 19318 uint32_t rescal_ctrl1[1]; 19319 uint32_t _rescal_ctrl1; 19320 } BCMI_HURACAN_RESCAL_CTRL1r_t; 19321 19322 #define BCMI_HURACAN_RESCAL_CTRL1r_CLR(r) (r).rescal_ctrl1[0] = 0 19323 #define BCMI_HURACAN_RESCAL_CTRL1r_SET(r,d) (r).rescal_ctrl1[0] = d 19324 #define BCMI_HURACAN_RESCAL_CTRL1r_GET(r) (r).rescal_ctrl1[0] 19325 19326 /* 19327 * These macros can be used to access individual fields. 19328 */ 19329 #define BCMI_HURACAN_RESCAL_CTRL1r_I_DIAG_ONf_GET(r) ((((r).rescal_ctrl1[0]) >> 1) & 0x1) 19330 #define BCMI_HURACAN_RESCAL_CTRL1r_I_DIAG_ONf_SET(r,f) (r).rescal_ctrl1[0]=(((r).rescal_ctrl1[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 19331 #define BCMI_HURACAN_RESCAL_CTRL1r_I_PWRDNf_GET(r) (((r).rescal_ctrl1[0]) & 0x1) 19332 #define BCMI_HURACAN_RESCAL_CTRL1r_I_PWRDNf_SET(r,f) (r).rescal_ctrl1[0]=(((r).rescal_ctrl1[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 19333 19334 /* 19335 * These macros can be used to access RESCAL_CTRL1. 19336 */ 19337 #define BCMI_HURACAN_READ_RESCAL_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_RESCAL_CTRL1r,_r._rescal_ctrl1) 19338 #define BCMI_HURACAN_WRITE_RESCAL_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_RESCAL_CTRL1r,_r._rescal_ctrl1) 19339 19340 /* 19341 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19342 * will be redefined without the chip prefix for easier programming. 19343 * If multiple chips will be programmed in the same source file, then you should 19344 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19345 * and refer to the fully qualified versions. 19346 */ 19347 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19348 19349 #define RESCAL_CTRL1r BCMI_HURACAN_RESCAL_CTRL1r 19350 #define RESCAL_CTRL1r_SIZE BCMI_HURACAN_RESCAL_CTRL1r_SIZE 19351 typedef BCMI_HURACAN_RESCAL_CTRL1r_t RESCAL_CTRL1r_t; 19352 #define RESCAL_CTRL1r_CLR BCMI_HURACAN_RESCAL_CTRL1r_CLR 19353 #define RESCAL_CTRL1r_SET BCMI_HURACAN_RESCAL_CTRL1r_SET 19354 #define RESCAL_CTRL1r_GET BCMI_HURACAN_RESCAL_CTRL1r_GET 19355 #define RESCAL_CTRL1r_I_DIAG_ONf_GET BCMI_HURACAN_RESCAL_CTRL1r_I_DIAG_ONf_GET 19356 #define RESCAL_CTRL1r_I_DIAG_ONf_SET BCMI_HURACAN_RESCAL_CTRL1r_I_DIAG_ONf_SET 19357 #define RESCAL_CTRL1r_I_PWRDNf_GET BCMI_HURACAN_RESCAL_CTRL1r_I_PWRDNf_GET 19358 #define RESCAL_CTRL1r_I_PWRDNf_SET BCMI_HURACAN_RESCAL_CTRL1r_I_PWRDNf_SET 19359 #define READ_RESCAL_CTRL1r BCMI_HURACAN_READ_RESCAL_CTRL1r 19360 #define WRITE_RESCAL_CTRL1r BCMI_HURACAN_WRITE_RESCAL_CTRL1r 19361 #define MODIFY_RESCAL_CTRL1r BCMI_HURACAN_MODIFY_RESCAL_CTRL1r 19362 19363 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19364 /******************************************************************************* 19365 * End of 'BCMI_HURACAN_RESCAL_CTRL1r' 19366 */ 19367 19368 19369 19370 19371 /******************************************************************************* 19372 * CHIP: BCMI_HURACAN 19373 * REGISTER: LIB_ROSC_EN_CTRL 19374 * BLOCKS: HARD_IP_QUAD_D 19375 * REGADDR: 0xb050 19376 * DEVAD: 1 19377 * DESC: ring oscillaor enable controls 19378 * RESETVAL: 0x0 (0) 19379 * ACCESS: R/W 19380 * FIELDS: 19381 * ROSC_EN 19382 */ 19383 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr (0x0001b050 | PHYMOD_REG_ACC_RAW) 19384 19385 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr_SIZE 4 19386 19387 /* 19388 * This structure should be used to declare and program LIB_ROSC_EN_CTRL. 19389 */ 19390 typedef union BCMI_HURACAN_LIB_ROSC_EN_CTRLr_s { 19391 uint32_t v[1]; 19392 uint32_t lib_rosc_en_ctrl[1]; 19393 uint32_t _lib_rosc_en_ctrl; 19394 } BCMI_HURACAN_LIB_ROSC_EN_CTRLr_t; 19395 19396 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr_CLR(r) (r).lib_rosc_en_ctrl[0] = 0 19397 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr_SET(r,d) (r).lib_rosc_en_ctrl[0] = d 19398 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr_GET(r) (r).lib_rosc_en_ctrl[0] 19399 19400 /* 19401 * These macros can be used to access individual fields. 19402 */ 19403 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr_ROSC_ENf_GET(r) (((r).lib_rosc_en_ctrl[0]) & 0xfff) 19404 #define BCMI_HURACAN_LIB_ROSC_EN_CTRLr_ROSC_ENf_SET(r,f) (r).lib_rosc_en_ctrl[0]=(((r).lib_rosc_en_ctrl[0] & ~((uint32_t)0xfff)) | (((uint32_t)f) & 0xfff)) | (0xfff << 16) 19405 19406 /* 19407 * These macros can be used to access LIB_ROSC_EN_CTRL. 19408 */ 19409 #define BCMI_HURACAN_READ_LIB_ROSC_EN_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_LIB_ROSC_EN_CTRLr,_r._lib_rosc_en_ctrl) 19410 #define BCMI_HURACAN_WRITE_LIB_ROSC_EN_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_LIB_ROSC_EN_CTRLr,_r._lib_rosc_en_ctrl) 19411 19412 /* 19413 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19414 * will be redefined without the chip prefix for easier programming. 19415 * If multiple chips will be programmed in the same source file, then you should 19416 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19417 * and refer to the fully qualified versions. 19418 */ 19419 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19420 19421 #define LIB_ROSC_EN_CTRLr BCMI_HURACAN_LIB_ROSC_EN_CTRLr 19422 #define LIB_ROSC_EN_CTRLr_SIZE BCMI_HURACAN_LIB_ROSC_EN_CTRLr_SIZE 19423 typedef BCMI_HURACAN_LIB_ROSC_EN_CTRLr_t LIB_ROSC_EN_CTRLr_t; 19424 #define LIB_ROSC_EN_CTRLr_CLR BCMI_HURACAN_LIB_ROSC_EN_CTRLr_CLR 19425 #define LIB_ROSC_EN_CTRLr_SET BCMI_HURACAN_LIB_ROSC_EN_CTRLr_SET 19426 #define LIB_ROSC_EN_CTRLr_GET BCMI_HURACAN_LIB_ROSC_EN_CTRLr_GET 19427 #define LIB_ROSC_EN_CTRLr_ROSC_ENf_GET BCMI_HURACAN_LIB_ROSC_EN_CTRLr_ROSC_ENf_GET 19428 #define LIB_ROSC_EN_CTRLr_ROSC_ENf_SET BCMI_HURACAN_LIB_ROSC_EN_CTRLr_ROSC_ENf_SET 19429 #define READ_LIB_ROSC_EN_CTRLr BCMI_HURACAN_READ_LIB_ROSC_EN_CTRLr 19430 #define WRITE_LIB_ROSC_EN_CTRLr BCMI_HURACAN_WRITE_LIB_ROSC_EN_CTRLr 19431 #define MODIFY_LIB_ROSC_EN_CTRLr BCMI_HURACAN_MODIFY_LIB_ROSC_EN_CTRLr 19432 19433 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19434 /******************************************************************************* 19435 * End of 'BCMI_HURACAN_LIB_ROSC_EN_CTRLr' 19436 */ 19437 19438 19439 19440 19441 /******************************************************************************* 19442 * CHIP: BCMI_HURACAN 19443 * REGISTER: LIB_ROSC_SEL_CTRL 19444 * BLOCKS: HARD_IP_QUAD_D 19445 * REGADDR: 0xb051 19446 * DEVAD: 1 19447 * DESC: ring oscillaor sel controls 19448 * RESETVAL: 0x0 (0) 19449 * ACCESS: R/W 19450 * FIELDS: 19451 * ROSC_SEL 19452 */ 19453 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr (0x0001b051 | PHYMOD_REG_ACC_RAW) 19454 19455 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_SIZE 4 19456 19457 /* 19458 * This structure should be used to declare and program LIB_ROSC_SEL_CTRL. 19459 */ 19460 typedef union BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_s { 19461 uint32_t v[1]; 19462 uint32_t lib_rosc_sel_ctrl[1]; 19463 uint32_t _lib_rosc_sel_ctrl; 19464 } BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_t; 19465 19466 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_CLR(r) (r).lib_rosc_sel_ctrl[0] = 0 19467 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_SET(r,d) (r).lib_rosc_sel_ctrl[0] = d 19468 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_GET(r) (r).lib_rosc_sel_ctrl[0] 19469 19470 /* 19471 * These macros can be used to access individual fields. 19472 */ 19473 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_ROSC_SELf_GET(r) (((r).lib_rosc_sel_ctrl[0]) & 0xfff) 19474 #define BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_ROSC_SELf_SET(r,f) (r).lib_rosc_sel_ctrl[0]=(((r).lib_rosc_sel_ctrl[0] & ~((uint32_t)0xfff)) | (((uint32_t)f) & 0xfff)) | (0xfff << 16) 19475 19476 /* 19477 * These macros can be used to access LIB_ROSC_SEL_CTRL. 19478 */ 19479 #define BCMI_HURACAN_READ_LIB_ROSC_SEL_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_LIB_ROSC_SEL_CTRLr,_r._lib_rosc_sel_ctrl) 19480 #define BCMI_HURACAN_WRITE_LIB_ROSC_SEL_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_LIB_ROSC_SEL_CTRLr,_r._lib_rosc_sel_ctrl) 19481 19482 /* 19483 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19484 * will be redefined without the chip prefix for easier programming. 19485 * If multiple chips will be programmed in the same source file, then you should 19486 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19487 * and refer to the fully qualified versions. 19488 */ 19489 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19490 19491 #define LIB_ROSC_SEL_CTRLr BCMI_HURACAN_LIB_ROSC_SEL_CTRLr 19492 #define LIB_ROSC_SEL_CTRLr_SIZE BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_SIZE 19493 typedef BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_t LIB_ROSC_SEL_CTRLr_t; 19494 #define LIB_ROSC_SEL_CTRLr_CLR BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_CLR 19495 #define LIB_ROSC_SEL_CTRLr_SET BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_SET 19496 #define LIB_ROSC_SEL_CTRLr_GET BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_GET 19497 #define LIB_ROSC_SEL_CTRLr_ROSC_SELf_GET BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_ROSC_SELf_GET 19498 #define LIB_ROSC_SEL_CTRLr_ROSC_SELf_SET BCMI_HURACAN_LIB_ROSC_SEL_CTRLr_ROSC_SELf_SET 19499 #define READ_LIB_ROSC_SEL_CTRLr BCMI_HURACAN_READ_LIB_ROSC_SEL_CTRLr 19500 #define WRITE_LIB_ROSC_SEL_CTRLr BCMI_HURACAN_WRITE_LIB_ROSC_SEL_CTRLr 19501 #define MODIFY_LIB_ROSC_SEL_CTRLr BCMI_HURACAN_MODIFY_LIB_ROSC_SEL_CTRLr 19502 19503 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19504 /******************************************************************************* 19505 * End of 'BCMI_HURACAN_LIB_ROSC_SEL_CTRLr' 19506 */ 19507 19508 19509 19510 19511 /******************************************************************************* 19512 * CHIP: BCMI_HURACAN 19513 * REGISTER: BONDSEL_0_CONTROL 19514 * BLOCKS: PAD_CTRL_QUAD_D 19515 * REGADDR: 0xb060 19516 * DEVAD: 1 19517 * DESC: PAD bondsel_0 control register 19518 * RESETVAL: 0x0 (0) 19519 * ACCESS: R/W 19520 * FIELDS: 19521 * BONDSEL_0_IBYP 19522 * BONDSEL_0_INVERT_EN 19523 * BONDSEL_0_DGLH_CNT 19524 */ 19525 #define BCMI_HURACAN_BONDSEL_0_CONTROLr (0x0001b060 | PHYMOD_REG_ACC_RAW) 19526 19527 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_SIZE 4 19528 19529 /* 19530 * This structure should be used to declare and program BONDSEL_0_CONTROL. 19531 */ 19532 typedef union BCMI_HURACAN_BONDSEL_0_CONTROLr_s { 19533 uint32_t v[1]; 19534 uint32_t bondsel_0_control[1]; 19535 uint32_t _bondsel_0_control; 19536 } BCMI_HURACAN_BONDSEL_0_CONTROLr_t; 19537 19538 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_CLR(r) (r).bondsel_0_control[0] = 0 19539 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_SET(r,d) (r).bondsel_0_control[0] = d 19540 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_GET(r) (r).bondsel_0_control[0] 19541 19542 /* 19543 * These macros can be used to access individual fields. 19544 */ 19545 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_DGLH_CNTf_GET(r) ((((r).bondsel_0_control[0]) >> 12) & 0xf) 19546 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_DGLH_CNTf_SET(r,f) (r).bondsel_0_control[0]=(((r).bondsel_0_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 19547 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_INVERT_ENf_GET(r) ((((r).bondsel_0_control[0]) >> 10) & 0x1) 19548 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_INVERT_ENf_SET(r,f) (r).bondsel_0_control[0]=(((r).bondsel_0_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 19549 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_IBYPf_GET(r) ((((r).bondsel_0_control[0]) >> 9) & 0x1) 19550 #define BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_IBYPf_SET(r,f) (r).bondsel_0_control[0]=(((r).bondsel_0_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 19551 19552 /* 19553 * These macros can be used to access BONDSEL_0_CONTROL. 19554 */ 19555 #define BCMI_HURACAN_READ_BONDSEL_0_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BONDSEL_0_CONTROLr,_r._bondsel_0_control) 19556 #define BCMI_HURACAN_WRITE_BONDSEL_0_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BONDSEL_0_CONTROLr,_r._bondsel_0_control) 19557 19558 /* 19559 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19560 * will be redefined without the chip prefix for easier programming. 19561 * If multiple chips will be programmed in the same source file, then you should 19562 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19563 * and refer to the fully qualified versions. 19564 */ 19565 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19566 19567 #define BONDSEL_0_CONTROLr BCMI_HURACAN_BONDSEL_0_CONTROLr 19568 #define BONDSEL_0_CONTROLr_SIZE BCMI_HURACAN_BONDSEL_0_CONTROLr_SIZE 19569 typedef BCMI_HURACAN_BONDSEL_0_CONTROLr_t BONDSEL_0_CONTROLr_t; 19570 #define BONDSEL_0_CONTROLr_CLR BCMI_HURACAN_BONDSEL_0_CONTROLr_CLR 19571 #define BONDSEL_0_CONTROLr_SET BCMI_HURACAN_BONDSEL_0_CONTROLr_SET 19572 #define BONDSEL_0_CONTROLr_GET BCMI_HURACAN_BONDSEL_0_CONTROLr_GET 19573 #define BONDSEL_0_CONTROLr_BONDSEL_0_DGLH_CNTf_GET BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_DGLH_CNTf_GET 19574 #define BONDSEL_0_CONTROLr_BONDSEL_0_DGLH_CNTf_SET BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_DGLH_CNTf_SET 19575 #define BONDSEL_0_CONTROLr_BONDSEL_0_INVERT_ENf_GET BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_INVERT_ENf_GET 19576 #define BONDSEL_0_CONTROLr_BONDSEL_0_INVERT_ENf_SET BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_INVERT_ENf_SET 19577 #define BONDSEL_0_CONTROLr_BONDSEL_0_IBYPf_GET BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_IBYPf_GET 19578 #define BONDSEL_0_CONTROLr_BONDSEL_0_IBYPf_SET BCMI_HURACAN_BONDSEL_0_CONTROLr_BONDSEL_0_IBYPf_SET 19579 #define READ_BONDSEL_0_CONTROLr BCMI_HURACAN_READ_BONDSEL_0_CONTROLr 19580 #define WRITE_BONDSEL_0_CONTROLr BCMI_HURACAN_WRITE_BONDSEL_0_CONTROLr 19581 #define MODIFY_BONDSEL_0_CONTROLr BCMI_HURACAN_MODIFY_BONDSEL_0_CONTROLr 19582 19583 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19584 /******************************************************************************* 19585 * End of 'BCMI_HURACAN_BONDSEL_0_CONTROLr' 19586 */ 19587 19588 19589 19590 19591 /******************************************************************************* 19592 * CHIP: BCMI_HURACAN 19593 * REGISTER: BONDSEL_0_STATUS 19594 * BLOCKS: PAD_CTRL_QUAD_D 19595 * REGADDR: 0xb061 19596 * DEVAD: 1 19597 * DESC: PAD bondsel_0 status register 19598 * RESETVAL: 0x0 (0) 19599 * ACCESS: R/W 19600 * FIELDS: 19601 * BONDSEL_0_DIN_LH 19602 * BONDSEL_0_DIN_LL 19603 * BONDSEL_0_DIN 19604 */ 19605 #define BCMI_HURACAN_BONDSEL_0_STATUSr (0x0001b061 | PHYMOD_REG_ACC_RAW) 19606 19607 #define BCMI_HURACAN_BONDSEL_0_STATUSr_SIZE 4 19608 19609 /* 19610 * This structure should be used to declare and program BONDSEL_0_STATUS. 19611 */ 19612 typedef union BCMI_HURACAN_BONDSEL_0_STATUSr_s { 19613 uint32_t v[1]; 19614 uint32_t bondsel_0_status[1]; 19615 uint32_t _bondsel_0_status; 19616 } BCMI_HURACAN_BONDSEL_0_STATUSr_t; 19617 19618 #define BCMI_HURACAN_BONDSEL_0_STATUSr_CLR(r) (r).bondsel_0_status[0] = 0 19619 #define BCMI_HURACAN_BONDSEL_0_STATUSr_SET(r,d) (r).bondsel_0_status[0] = d 19620 #define BCMI_HURACAN_BONDSEL_0_STATUSr_GET(r) (r).bondsel_0_status[0] 19621 19622 /* 19623 * These macros can be used to access individual fields. 19624 */ 19625 #define BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DINf_GET(r) ((((r).bondsel_0_status[0]) >> 2) & 0x1) 19626 #define BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DINf_SET(r,f) (r).bondsel_0_status[0]=(((r).bondsel_0_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 19627 #define BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LLf_GET(r) ((((r).bondsel_0_status[0]) >> 1) & 0x1) 19628 #define BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LLf_SET(r,f) (r).bondsel_0_status[0]=(((r).bondsel_0_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 19629 #define BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LHf_GET(r) (((r).bondsel_0_status[0]) & 0x1) 19630 #define BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LHf_SET(r,f) (r).bondsel_0_status[0]=(((r).bondsel_0_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 19631 19632 /* 19633 * These macros can be used to access BONDSEL_0_STATUS. 19634 */ 19635 #define BCMI_HURACAN_READ_BONDSEL_0_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BONDSEL_0_STATUSr,_r._bondsel_0_status) 19636 #define BCMI_HURACAN_WRITE_BONDSEL_0_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BONDSEL_0_STATUSr,_r._bondsel_0_status) 19637 19638 /* 19639 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19640 * will be redefined without the chip prefix for easier programming. 19641 * If multiple chips will be programmed in the same source file, then you should 19642 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19643 * and refer to the fully qualified versions. 19644 */ 19645 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19646 19647 #define BONDSEL_0_STATUSr BCMI_HURACAN_BONDSEL_0_STATUSr 19648 #define BONDSEL_0_STATUSr_SIZE BCMI_HURACAN_BONDSEL_0_STATUSr_SIZE 19649 typedef BCMI_HURACAN_BONDSEL_0_STATUSr_t BONDSEL_0_STATUSr_t; 19650 #define BONDSEL_0_STATUSr_CLR BCMI_HURACAN_BONDSEL_0_STATUSr_CLR 19651 #define BONDSEL_0_STATUSr_SET BCMI_HURACAN_BONDSEL_0_STATUSr_SET 19652 #define BONDSEL_0_STATUSr_GET BCMI_HURACAN_BONDSEL_0_STATUSr_GET 19653 #define BONDSEL_0_STATUSr_BONDSEL_0_DINf_GET BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DINf_GET 19654 #define BONDSEL_0_STATUSr_BONDSEL_0_DINf_SET BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DINf_SET 19655 #define BONDSEL_0_STATUSr_BONDSEL_0_DIN_LLf_GET BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LLf_GET 19656 #define BONDSEL_0_STATUSr_BONDSEL_0_DIN_LLf_SET BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LLf_SET 19657 #define BONDSEL_0_STATUSr_BONDSEL_0_DIN_LHf_GET BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LHf_GET 19658 #define BONDSEL_0_STATUSr_BONDSEL_0_DIN_LHf_SET BCMI_HURACAN_BONDSEL_0_STATUSr_BONDSEL_0_DIN_LHf_SET 19659 #define READ_BONDSEL_0_STATUSr BCMI_HURACAN_READ_BONDSEL_0_STATUSr 19660 #define WRITE_BONDSEL_0_STATUSr BCMI_HURACAN_WRITE_BONDSEL_0_STATUSr 19661 #define MODIFY_BONDSEL_0_STATUSr BCMI_HURACAN_MODIFY_BONDSEL_0_STATUSr 19662 19663 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19664 /******************************************************************************* 19665 * End of 'BCMI_HURACAN_BONDSEL_0_STATUSr' 19666 */ 19667 19668 19669 19670 19671 /******************************************************************************* 19672 * CHIP: BCMI_HURACAN 19673 * REGISTER: BONDSEL_1_CONTROL 19674 * BLOCKS: PAD_CTRL_QUAD_D 19675 * REGADDR: 0xb062 19676 * DEVAD: 1 19677 * DESC: PAD bondsel_1 control register 19678 * RESETVAL: 0x0 (0) 19679 * ACCESS: R/W 19680 * FIELDS: 19681 * BONDSEL_1_IBYP 19682 * BONDSEL_1_INVERT_EN 19683 * BONDSEL_1_DGLH_CNT 19684 */ 19685 #define BCMI_HURACAN_BONDSEL_1_CONTROLr (0x0001b062 | PHYMOD_REG_ACC_RAW) 19686 19687 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_SIZE 4 19688 19689 /* 19690 * This structure should be used to declare and program BONDSEL_1_CONTROL. 19691 */ 19692 typedef union BCMI_HURACAN_BONDSEL_1_CONTROLr_s { 19693 uint32_t v[1]; 19694 uint32_t bondsel_1_control[1]; 19695 uint32_t _bondsel_1_control; 19696 } BCMI_HURACAN_BONDSEL_1_CONTROLr_t; 19697 19698 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_CLR(r) (r).bondsel_1_control[0] = 0 19699 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_SET(r,d) (r).bondsel_1_control[0] = d 19700 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_GET(r) (r).bondsel_1_control[0] 19701 19702 /* 19703 * These macros can be used to access individual fields. 19704 */ 19705 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_DGLH_CNTf_GET(r) ((((r).bondsel_1_control[0]) >> 12) & 0xf) 19706 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_DGLH_CNTf_SET(r,f) (r).bondsel_1_control[0]=(((r).bondsel_1_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 19707 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_INVERT_ENf_GET(r) ((((r).bondsel_1_control[0]) >> 10) & 0x1) 19708 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_INVERT_ENf_SET(r,f) (r).bondsel_1_control[0]=(((r).bondsel_1_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 19709 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_IBYPf_GET(r) ((((r).bondsel_1_control[0]) >> 9) & 0x1) 19710 #define BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_IBYPf_SET(r,f) (r).bondsel_1_control[0]=(((r).bondsel_1_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 19711 19712 /* 19713 * These macros can be used to access BONDSEL_1_CONTROL. 19714 */ 19715 #define BCMI_HURACAN_READ_BONDSEL_1_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BONDSEL_1_CONTROLr,_r._bondsel_1_control) 19716 #define BCMI_HURACAN_WRITE_BONDSEL_1_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BONDSEL_1_CONTROLr,_r._bondsel_1_control) 19717 19718 /* 19719 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19720 * will be redefined without the chip prefix for easier programming. 19721 * If multiple chips will be programmed in the same source file, then you should 19722 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19723 * and refer to the fully qualified versions. 19724 */ 19725 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19726 19727 #define BONDSEL_1_CONTROLr BCMI_HURACAN_BONDSEL_1_CONTROLr 19728 #define BONDSEL_1_CONTROLr_SIZE BCMI_HURACAN_BONDSEL_1_CONTROLr_SIZE 19729 typedef BCMI_HURACAN_BONDSEL_1_CONTROLr_t BONDSEL_1_CONTROLr_t; 19730 #define BONDSEL_1_CONTROLr_CLR BCMI_HURACAN_BONDSEL_1_CONTROLr_CLR 19731 #define BONDSEL_1_CONTROLr_SET BCMI_HURACAN_BONDSEL_1_CONTROLr_SET 19732 #define BONDSEL_1_CONTROLr_GET BCMI_HURACAN_BONDSEL_1_CONTROLr_GET 19733 #define BONDSEL_1_CONTROLr_BONDSEL_1_DGLH_CNTf_GET BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_DGLH_CNTf_GET 19734 #define BONDSEL_1_CONTROLr_BONDSEL_1_DGLH_CNTf_SET BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_DGLH_CNTf_SET 19735 #define BONDSEL_1_CONTROLr_BONDSEL_1_INVERT_ENf_GET BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_INVERT_ENf_GET 19736 #define BONDSEL_1_CONTROLr_BONDSEL_1_INVERT_ENf_SET BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_INVERT_ENf_SET 19737 #define BONDSEL_1_CONTROLr_BONDSEL_1_IBYPf_GET BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_IBYPf_GET 19738 #define BONDSEL_1_CONTROLr_BONDSEL_1_IBYPf_SET BCMI_HURACAN_BONDSEL_1_CONTROLr_BONDSEL_1_IBYPf_SET 19739 #define READ_BONDSEL_1_CONTROLr BCMI_HURACAN_READ_BONDSEL_1_CONTROLr 19740 #define WRITE_BONDSEL_1_CONTROLr BCMI_HURACAN_WRITE_BONDSEL_1_CONTROLr 19741 #define MODIFY_BONDSEL_1_CONTROLr BCMI_HURACAN_MODIFY_BONDSEL_1_CONTROLr 19742 19743 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19744 /******************************************************************************* 19745 * End of 'BCMI_HURACAN_BONDSEL_1_CONTROLr' 19746 */ 19747 19748 19749 19750 19751 /******************************************************************************* 19752 * CHIP: BCMI_HURACAN 19753 * REGISTER: BONDSEL_1_STATUS 19754 * BLOCKS: PAD_CTRL_QUAD_D 19755 * REGADDR: 0xb063 19756 * DEVAD: 1 19757 * DESC: PAD bondsel_1 status register 19758 * RESETVAL: 0x0 (0) 19759 * ACCESS: R/W 19760 * FIELDS: 19761 * BONDSEL_1_DIN_LH 19762 * BONDSEL_1_DIN_LL 19763 * BONDSEL_1_DIN 19764 */ 19765 #define BCMI_HURACAN_BONDSEL_1_STATUSr (0x0001b063 | PHYMOD_REG_ACC_RAW) 19766 19767 #define BCMI_HURACAN_BONDSEL_1_STATUSr_SIZE 4 19768 19769 /* 19770 * This structure should be used to declare and program BONDSEL_1_STATUS. 19771 */ 19772 typedef union BCMI_HURACAN_BONDSEL_1_STATUSr_s { 19773 uint32_t v[1]; 19774 uint32_t bondsel_1_status[1]; 19775 uint32_t _bondsel_1_status; 19776 } BCMI_HURACAN_BONDSEL_1_STATUSr_t; 19777 19778 #define BCMI_HURACAN_BONDSEL_1_STATUSr_CLR(r) (r).bondsel_1_status[0] = 0 19779 #define BCMI_HURACAN_BONDSEL_1_STATUSr_SET(r,d) (r).bondsel_1_status[0] = d 19780 #define BCMI_HURACAN_BONDSEL_1_STATUSr_GET(r) (r).bondsel_1_status[0] 19781 19782 /* 19783 * These macros can be used to access individual fields. 19784 */ 19785 #define BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DINf_GET(r) ((((r).bondsel_1_status[0]) >> 2) & 0x1) 19786 #define BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DINf_SET(r,f) (r).bondsel_1_status[0]=(((r).bondsel_1_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 19787 #define BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LLf_GET(r) ((((r).bondsel_1_status[0]) >> 1) & 0x1) 19788 #define BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LLf_SET(r,f) (r).bondsel_1_status[0]=(((r).bondsel_1_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 19789 #define BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LHf_GET(r) (((r).bondsel_1_status[0]) & 0x1) 19790 #define BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LHf_SET(r,f) (r).bondsel_1_status[0]=(((r).bondsel_1_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 19791 19792 /* 19793 * These macros can be used to access BONDSEL_1_STATUS. 19794 */ 19795 #define BCMI_HURACAN_READ_BONDSEL_1_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BONDSEL_1_STATUSr,_r._bondsel_1_status) 19796 #define BCMI_HURACAN_WRITE_BONDSEL_1_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BONDSEL_1_STATUSr,_r._bondsel_1_status) 19797 19798 /* 19799 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19800 * will be redefined without the chip prefix for easier programming. 19801 * If multiple chips will be programmed in the same source file, then you should 19802 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19803 * and refer to the fully qualified versions. 19804 */ 19805 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19806 19807 #define BONDSEL_1_STATUSr BCMI_HURACAN_BONDSEL_1_STATUSr 19808 #define BONDSEL_1_STATUSr_SIZE BCMI_HURACAN_BONDSEL_1_STATUSr_SIZE 19809 typedef BCMI_HURACAN_BONDSEL_1_STATUSr_t BONDSEL_1_STATUSr_t; 19810 #define BONDSEL_1_STATUSr_CLR BCMI_HURACAN_BONDSEL_1_STATUSr_CLR 19811 #define BONDSEL_1_STATUSr_SET BCMI_HURACAN_BONDSEL_1_STATUSr_SET 19812 #define BONDSEL_1_STATUSr_GET BCMI_HURACAN_BONDSEL_1_STATUSr_GET 19813 #define BONDSEL_1_STATUSr_BONDSEL_1_DINf_GET BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DINf_GET 19814 #define BONDSEL_1_STATUSr_BONDSEL_1_DINf_SET BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DINf_SET 19815 #define BONDSEL_1_STATUSr_BONDSEL_1_DIN_LLf_GET BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LLf_GET 19816 #define BONDSEL_1_STATUSr_BONDSEL_1_DIN_LLf_SET BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LLf_SET 19817 #define BONDSEL_1_STATUSr_BONDSEL_1_DIN_LHf_GET BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LHf_GET 19818 #define BONDSEL_1_STATUSr_BONDSEL_1_DIN_LHf_SET BCMI_HURACAN_BONDSEL_1_STATUSr_BONDSEL_1_DIN_LHf_SET 19819 #define READ_BONDSEL_1_STATUSr BCMI_HURACAN_READ_BONDSEL_1_STATUSr 19820 #define WRITE_BONDSEL_1_STATUSr BCMI_HURACAN_WRITE_BONDSEL_1_STATUSr 19821 #define MODIFY_BONDSEL_1_STATUSr BCMI_HURACAN_MODIFY_BONDSEL_1_STATUSr 19822 19823 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19824 /******************************************************************************* 19825 * End of 'BCMI_HURACAN_BONDSEL_1_STATUSr' 19826 */ 19827 19828 19829 19830 19831 /******************************************************************************* 19832 * CHIP: BCMI_HURACAN 19833 * REGISTER: BONDSEL_2_CONTROL 19834 * BLOCKS: PAD_CTRL_QUAD_D 19835 * REGADDR: 0xb064 19836 * DEVAD: 1 19837 * DESC: PAD bondsel_2 control register 19838 * RESETVAL: 0x0 (0) 19839 * ACCESS: R/W 19840 * FIELDS: 19841 * BONDSEL_2_IBYP 19842 * BONDSEL_2_INVERT_EN 19843 * BONDSEL_2_DGLH_CNT 19844 */ 19845 #define BCMI_HURACAN_BONDSEL_2_CONTROLr (0x0001b064 | PHYMOD_REG_ACC_RAW) 19846 19847 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_SIZE 4 19848 19849 /* 19850 * This structure should be used to declare and program BONDSEL_2_CONTROL. 19851 */ 19852 typedef union BCMI_HURACAN_BONDSEL_2_CONTROLr_s { 19853 uint32_t v[1]; 19854 uint32_t bondsel_2_control[1]; 19855 uint32_t _bondsel_2_control; 19856 } BCMI_HURACAN_BONDSEL_2_CONTROLr_t; 19857 19858 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_CLR(r) (r).bondsel_2_control[0] = 0 19859 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_SET(r,d) (r).bondsel_2_control[0] = d 19860 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_GET(r) (r).bondsel_2_control[0] 19861 19862 /* 19863 * These macros can be used to access individual fields. 19864 */ 19865 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_DGLH_CNTf_GET(r) ((((r).bondsel_2_control[0]) >> 12) & 0xf) 19866 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_DGLH_CNTf_SET(r,f) (r).bondsel_2_control[0]=(((r).bondsel_2_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 19867 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_INVERT_ENf_GET(r) ((((r).bondsel_2_control[0]) >> 10) & 0x1) 19868 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_INVERT_ENf_SET(r,f) (r).bondsel_2_control[0]=(((r).bondsel_2_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 19869 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_IBYPf_GET(r) ((((r).bondsel_2_control[0]) >> 9) & 0x1) 19870 #define BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_IBYPf_SET(r,f) (r).bondsel_2_control[0]=(((r).bondsel_2_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 19871 19872 /* 19873 * These macros can be used to access BONDSEL_2_CONTROL. 19874 */ 19875 #define BCMI_HURACAN_READ_BONDSEL_2_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BONDSEL_2_CONTROLr,_r._bondsel_2_control) 19876 #define BCMI_HURACAN_WRITE_BONDSEL_2_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BONDSEL_2_CONTROLr,_r._bondsel_2_control) 19877 19878 /* 19879 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19880 * will be redefined without the chip prefix for easier programming. 19881 * If multiple chips will be programmed in the same source file, then you should 19882 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19883 * and refer to the fully qualified versions. 19884 */ 19885 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19886 19887 #define BONDSEL_2_CONTROLr BCMI_HURACAN_BONDSEL_2_CONTROLr 19888 #define BONDSEL_2_CONTROLr_SIZE BCMI_HURACAN_BONDSEL_2_CONTROLr_SIZE 19889 typedef BCMI_HURACAN_BONDSEL_2_CONTROLr_t BONDSEL_2_CONTROLr_t; 19890 #define BONDSEL_2_CONTROLr_CLR BCMI_HURACAN_BONDSEL_2_CONTROLr_CLR 19891 #define BONDSEL_2_CONTROLr_SET BCMI_HURACAN_BONDSEL_2_CONTROLr_SET 19892 #define BONDSEL_2_CONTROLr_GET BCMI_HURACAN_BONDSEL_2_CONTROLr_GET 19893 #define BONDSEL_2_CONTROLr_BONDSEL_2_DGLH_CNTf_GET BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_DGLH_CNTf_GET 19894 #define BONDSEL_2_CONTROLr_BONDSEL_2_DGLH_CNTf_SET BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_DGLH_CNTf_SET 19895 #define BONDSEL_2_CONTROLr_BONDSEL_2_INVERT_ENf_GET BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_INVERT_ENf_GET 19896 #define BONDSEL_2_CONTROLr_BONDSEL_2_INVERT_ENf_SET BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_INVERT_ENf_SET 19897 #define BONDSEL_2_CONTROLr_BONDSEL_2_IBYPf_GET BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_IBYPf_GET 19898 #define BONDSEL_2_CONTROLr_BONDSEL_2_IBYPf_SET BCMI_HURACAN_BONDSEL_2_CONTROLr_BONDSEL_2_IBYPf_SET 19899 #define READ_BONDSEL_2_CONTROLr BCMI_HURACAN_READ_BONDSEL_2_CONTROLr 19900 #define WRITE_BONDSEL_2_CONTROLr BCMI_HURACAN_WRITE_BONDSEL_2_CONTROLr 19901 #define MODIFY_BONDSEL_2_CONTROLr BCMI_HURACAN_MODIFY_BONDSEL_2_CONTROLr 19902 19903 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19904 /******************************************************************************* 19905 * End of 'BCMI_HURACAN_BONDSEL_2_CONTROLr' 19906 */ 19907 19908 19909 19910 19911 /******************************************************************************* 19912 * CHIP: BCMI_HURACAN 19913 * REGISTER: BONDSEL_2_STATUS 19914 * BLOCKS: PAD_CTRL_QUAD_D 19915 * REGADDR: 0xb065 19916 * DEVAD: 1 19917 * DESC: PAD bondsel_2 status register 19918 * RESETVAL: 0x0 (0) 19919 * ACCESS: R/W 19920 * FIELDS: 19921 * BONDSEL_2_DIN_LH 19922 * BONDSEL_2_DIN_LL 19923 * BONDSEL_2_DIN 19924 */ 19925 #define BCMI_HURACAN_BONDSEL_2_STATUSr (0x0001b065 | PHYMOD_REG_ACC_RAW) 19926 19927 #define BCMI_HURACAN_BONDSEL_2_STATUSr_SIZE 4 19928 19929 /* 19930 * This structure should be used to declare and program BONDSEL_2_STATUS. 19931 */ 19932 typedef union BCMI_HURACAN_BONDSEL_2_STATUSr_s { 19933 uint32_t v[1]; 19934 uint32_t bondsel_2_status[1]; 19935 uint32_t _bondsel_2_status; 19936 } BCMI_HURACAN_BONDSEL_2_STATUSr_t; 19937 19938 #define BCMI_HURACAN_BONDSEL_2_STATUSr_CLR(r) (r).bondsel_2_status[0] = 0 19939 #define BCMI_HURACAN_BONDSEL_2_STATUSr_SET(r,d) (r).bondsel_2_status[0] = d 19940 #define BCMI_HURACAN_BONDSEL_2_STATUSr_GET(r) (r).bondsel_2_status[0] 19941 19942 /* 19943 * These macros can be used to access individual fields. 19944 */ 19945 #define BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DINf_GET(r) ((((r).bondsel_2_status[0]) >> 2) & 0x1) 19946 #define BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DINf_SET(r,f) (r).bondsel_2_status[0]=(((r).bondsel_2_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 19947 #define BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LLf_GET(r) ((((r).bondsel_2_status[0]) >> 1) & 0x1) 19948 #define BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LLf_SET(r,f) (r).bondsel_2_status[0]=(((r).bondsel_2_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 19949 #define BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LHf_GET(r) (((r).bondsel_2_status[0]) & 0x1) 19950 #define BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LHf_SET(r,f) (r).bondsel_2_status[0]=(((r).bondsel_2_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 19951 19952 /* 19953 * These macros can be used to access BONDSEL_2_STATUS. 19954 */ 19955 #define BCMI_HURACAN_READ_BONDSEL_2_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BONDSEL_2_STATUSr,_r._bondsel_2_status) 19956 #define BCMI_HURACAN_WRITE_BONDSEL_2_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BONDSEL_2_STATUSr,_r._bondsel_2_status) 19957 19958 /* 19959 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 19960 * will be redefined without the chip prefix for easier programming. 19961 * If multiple chips will be programmed in the same source file, then you should 19962 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 19963 * and refer to the fully qualified versions. 19964 */ 19965 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 19966 19967 #define BONDSEL_2_STATUSr BCMI_HURACAN_BONDSEL_2_STATUSr 19968 #define BONDSEL_2_STATUSr_SIZE BCMI_HURACAN_BONDSEL_2_STATUSr_SIZE 19969 typedef BCMI_HURACAN_BONDSEL_2_STATUSr_t BONDSEL_2_STATUSr_t; 19970 #define BONDSEL_2_STATUSr_CLR BCMI_HURACAN_BONDSEL_2_STATUSr_CLR 19971 #define BONDSEL_2_STATUSr_SET BCMI_HURACAN_BONDSEL_2_STATUSr_SET 19972 #define BONDSEL_2_STATUSr_GET BCMI_HURACAN_BONDSEL_2_STATUSr_GET 19973 #define BONDSEL_2_STATUSr_BONDSEL_2_DINf_GET BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DINf_GET 19974 #define BONDSEL_2_STATUSr_BONDSEL_2_DINf_SET BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DINf_SET 19975 #define BONDSEL_2_STATUSr_BONDSEL_2_DIN_LLf_GET BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LLf_GET 19976 #define BONDSEL_2_STATUSr_BONDSEL_2_DIN_LLf_SET BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LLf_SET 19977 #define BONDSEL_2_STATUSr_BONDSEL_2_DIN_LHf_GET BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LHf_GET 19978 #define BONDSEL_2_STATUSr_BONDSEL_2_DIN_LHf_SET BCMI_HURACAN_BONDSEL_2_STATUSr_BONDSEL_2_DIN_LHf_SET 19979 #define READ_BONDSEL_2_STATUSr BCMI_HURACAN_READ_BONDSEL_2_STATUSr 19980 #define WRITE_BONDSEL_2_STATUSr BCMI_HURACAN_WRITE_BONDSEL_2_STATUSr 19981 #define MODIFY_BONDSEL_2_STATUSr BCMI_HURACAN_MODIFY_BONDSEL_2_STATUSr 19982 19983 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 19984 /******************************************************************************* 19985 * End of 'BCMI_HURACAN_BONDSEL_2_STATUSr' 19986 */ 19987 19988 19989 19990 19991 /******************************************************************************* 19992 * CHIP: BCMI_HURACAN 19993 * REGISTER: INT_CLK_SEL_CONTROL 19994 * BLOCKS: PAD_CTRL_QUAD_D 19995 * REGADDR: 0xb066 19996 * DEVAD: 1 19997 * DESC: PAD int_clk_sel control register 19998 * RESETVAL: 0x0 (0) 19999 * ACCESS: R/W 20000 * FIELDS: 20001 * INT_CLK_SEL_IBYP 20002 * INT_CLK_SEL_INVERT_EN 20003 * INT_CLK_SEL_DGLH_CNT 20004 */ 20005 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr (0x0001b066 | PHYMOD_REG_ACC_RAW) 20006 20007 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_SIZE 4 20008 20009 /* 20010 * This structure should be used to declare and program INT_CLK_SEL_CONTROL. 20011 */ 20012 typedef union BCMI_HURACAN_INT_CLK_SEL_CONTROLr_s { 20013 uint32_t v[1]; 20014 uint32_t int_clk_sel_control[1]; 20015 uint32_t _int_clk_sel_control; 20016 } BCMI_HURACAN_INT_CLK_SEL_CONTROLr_t; 20017 20018 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_CLR(r) (r).int_clk_sel_control[0] = 0 20019 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_SET(r,d) (r).int_clk_sel_control[0] = d 20020 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_GET(r) (r).int_clk_sel_control[0] 20021 20022 /* 20023 * These macros can be used to access individual fields. 20024 */ 20025 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_DGLH_CNTf_GET(r) ((((r).int_clk_sel_control[0]) >> 12) & 0xf) 20026 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_DGLH_CNTf_SET(r,f) (r).int_clk_sel_control[0]=(((r).int_clk_sel_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 20027 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_INVERT_ENf_GET(r) ((((r).int_clk_sel_control[0]) >> 10) & 0x1) 20028 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_INVERT_ENf_SET(r,f) (r).int_clk_sel_control[0]=(((r).int_clk_sel_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 20029 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_IBYPf_GET(r) ((((r).int_clk_sel_control[0]) >> 9) & 0x1) 20030 #define BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_IBYPf_SET(r,f) (r).int_clk_sel_control[0]=(((r).int_clk_sel_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 20031 20032 /* 20033 * These macros can be used to access INT_CLK_SEL_CONTROL. 20034 */ 20035 #define BCMI_HURACAN_READ_INT_CLK_SEL_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_INT_CLK_SEL_CONTROLr,_r._int_clk_sel_control) 20036 #define BCMI_HURACAN_WRITE_INT_CLK_SEL_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_INT_CLK_SEL_CONTROLr,_r._int_clk_sel_control) 20037 20038 /* 20039 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20040 * will be redefined without the chip prefix for easier programming. 20041 * If multiple chips will be programmed in the same source file, then you should 20042 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20043 * and refer to the fully qualified versions. 20044 */ 20045 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20046 20047 #define INT_CLK_SEL_CONTROLr BCMI_HURACAN_INT_CLK_SEL_CONTROLr 20048 #define INT_CLK_SEL_CONTROLr_SIZE BCMI_HURACAN_INT_CLK_SEL_CONTROLr_SIZE 20049 typedef BCMI_HURACAN_INT_CLK_SEL_CONTROLr_t INT_CLK_SEL_CONTROLr_t; 20050 #define INT_CLK_SEL_CONTROLr_CLR BCMI_HURACAN_INT_CLK_SEL_CONTROLr_CLR 20051 #define INT_CLK_SEL_CONTROLr_SET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_SET 20052 #define INT_CLK_SEL_CONTROLr_GET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_GET 20053 #define INT_CLK_SEL_CONTROLr_INT_CLK_SEL_DGLH_CNTf_GET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_DGLH_CNTf_GET 20054 #define INT_CLK_SEL_CONTROLr_INT_CLK_SEL_DGLH_CNTf_SET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_DGLH_CNTf_SET 20055 #define INT_CLK_SEL_CONTROLr_INT_CLK_SEL_INVERT_ENf_GET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_INVERT_ENf_GET 20056 #define INT_CLK_SEL_CONTROLr_INT_CLK_SEL_INVERT_ENf_SET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_INVERT_ENf_SET 20057 #define INT_CLK_SEL_CONTROLr_INT_CLK_SEL_IBYPf_GET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_IBYPf_GET 20058 #define INT_CLK_SEL_CONTROLr_INT_CLK_SEL_IBYPf_SET BCMI_HURACAN_INT_CLK_SEL_CONTROLr_INT_CLK_SEL_IBYPf_SET 20059 #define READ_INT_CLK_SEL_CONTROLr BCMI_HURACAN_READ_INT_CLK_SEL_CONTROLr 20060 #define WRITE_INT_CLK_SEL_CONTROLr BCMI_HURACAN_WRITE_INT_CLK_SEL_CONTROLr 20061 #define MODIFY_INT_CLK_SEL_CONTROLr BCMI_HURACAN_MODIFY_INT_CLK_SEL_CONTROLr 20062 20063 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20064 /******************************************************************************* 20065 * End of 'BCMI_HURACAN_INT_CLK_SEL_CONTROLr' 20066 */ 20067 20068 20069 20070 20071 /******************************************************************************* 20072 * CHIP: BCMI_HURACAN 20073 * REGISTER: INT_CLK_SEL_STATUS 20074 * BLOCKS: PAD_CTRL_QUAD_D 20075 * REGADDR: 0xb067 20076 * DEVAD: 1 20077 * DESC: PAD int_clk_sel status register 20078 * RESETVAL: 0x0 (0) 20079 * ACCESS: R/W 20080 * FIELDS: 20081 * INT_CLK_SEL_DIN_LH 20082 * INT_CLK_SEL_DIN_LL 20083 * INT_CLK_SEL_DIN 20084 */ 20085 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr (0x0001b067 | PHYMOD_REG_ACC_RAW) 20086 20087 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_SIZE 4 20088 20089 /* 20090 * This structure should be used to declare and program INT_CLK_SEL_STATUS. 20091 */ 20092 typedef union BCMI_HURACAN_INT_CLK_SEL_STATUSr_s { 20093 uint32_t v[1]; 20094 uint32_t int_clk_sel_status[1]; 20095 uint32_t _int_clk_sel_status; 20096 } BCMI_HURACAN_INT_CLK_SEL_STATUSr_t; 20097 20098 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_CLR(r) (r).int_clk_sel_status[0] = 0 20099 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_SET(r,d) (r).int_clk_sel_status[0] = d 20100 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_GET(r) (r).int_clk_sel_status[0] 20101 20102 /* 20103 * These macros can be used to access individual fields. 20104 */ 20105 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DINf_GET(r) ((((r).int_clk_sel_status[0]) >> 2) & 0x1) 20106 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DINf_SET(r,f) (r).int_clk_sel_status[0]=(((r).int_clk_sel_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20107 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LLf_GET(r) ((((r).int_clk_sel_status[0]) >> 1) & 0x1) 20108 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LLf_SET(r,f) (r).int_clk_sel_status[0]=(((r).int_clk_sel_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20109 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LHf_GET(r) (((r).int_clk_sel_status[0]) & 0x1) 20110 #define BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LHf_SET(r,f) (r).int_clk_sel_status[0]=(((r).int_clk_sel_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 20111 20112 /* 20113 * These macros can be used to access INT_CLK_SEL_STATUS. 20114 */ 20115 #define BCMI_HURACAN_READ_INT_CLK_SEL_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_INT_CLK_SEL_STATUSr,_r._int_clk_sel_status) 20116 #define BCMI_HURACAN_WRITE_INT_CLK_SEL_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_INT_CLK_SEL_STATUSr,_r._int_clk_sel_status) 20117 20118 /* 20119 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20120 * will be redefined without the chip prefix for easier programming. 20121 * If multiple chips will be programmed in the same source file, then you should 20122 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20123 * and refer to the fully qualified versions. 20124 */ 20125 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20126 20127 #define INT_CLK_SEL_STATUSr BCMI_HURACAN_INT_CLK_SEL_STATUSr 20128 #define INT_CLK_SEL_STATUSr_SIZE BCMI_HURACAN_INT_CLK_SEL_STATUSr_SIZE 20129 typedef BCMI_HURACAN_INT_CLK_SEL_STATUSr_t INT_CLK_SEL_STATUSr_t; 20130 #define INT_CLK_SEL_STATUSr_CLR BCMI_HURACAN_INT_CLK_SEL_STATUSr_CLR 20131 #define INT_CLK_SEL_STATUSr_SET BCMI_HURACAN_INT_CLK_SEL_STATUSr_SET 20132 #define INT_CLK_SEL_STATUSr_GET BCMI_HURACAN_INT_CLK_SEL_STATUSr_GET 20133 #define INT_CLK_SEL_STATUSr_INT_CLK_SEL_DINf_GET BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DINf_GET 20134 #define INT_CLK_SEL_STATUSr_INT_CLK_SEL_DINf_SET BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DINf_SET 20135 #define INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LLf_GET BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LLf_GET 20136 #define INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LLf_SET BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LLf_SET 20137 #define INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LHf_GET BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LHf_GET 20138 #define INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LHf_SET BCMI_HURACAN_INT_CLK_SEL_STATUSr_INT_CLK_SEL_DIN_LHf_SET 20139 #define READ_INT_CLK_SEL_STATUSr BCMI_HURACAN_READ_INT_CLK_SEL_STATUSr 20140 #define WRITE_INT_CLK_SEL_STATUSr BCMI_HURACAN_WRITE_INT_CLK_SEL_STATUSr 20141 #define MODIFY_INT_CLK_SEL_STATUSr BCMI_HURACAN_MODIFY_INT_CLK_SEL_STATUSr 20142 20143 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20144 /******************************************************************************* 20145 * End of 'BCMI_HURACAN_INT_CLK_SEL_STATUSr' 20146 */ 20147 20148 20149 20150 20151 /******************************************************************************* 20152 * CHIP: BCMI_HURACAN 20153 * REGISTER: MDC_CONTROL 20154 * BLOCKS: PAD_CTRL_QUAD_D 20155 * REGADDR: 0xb068 20156 * DEVAD: 1 20157 * DESC: PAD mdc control register 20158 * RESETVAL: 0x0 (0) 20159 * ACCESS: R/W 20160 * FIELDS: 20161 * MDC_IBYP 20162 * MDC_INVERT_EN 20163 * MDC_DGLH_CNT 20164 */ 20165 #define BCMI_HURACAN_MDC_CONTROLr (0x0001b068 | PHYMOD_REG_ACC_RAW) 20166 20167 #define BCMI_HURACAN_MDC_CONTROLr_SIZE 4 20168 20169 /* 20170 * This structure should be used to declare and program MDC_CONTROL. 20171 */ 20172 typedef union BCMI_HURACAN_MDC_CONTROLr_s { 20173 uint32_t v[1]; 20174 uint32_t mdc_control[1]; 20175 uint32_t _mdc_control; 20176 } BCMI_HURACAN_MDC_CONTROLr_t; 20177 20178 #define BCMI_HURACAN_MDC_CONTROLr_CLR(r) (r).mdc_control[0] = 0 20179 #define BCMI_HURACAN_MDC_CONTROLr_SET(r,d) (r).mdc_control[0] = d 20180 #define BCMI_HURACAN_MDC_CONTROLr_GET(r) (r).mdc_control[0] 20181 20182 /* 20183 * These macros can be used to access individual fields. 20184 */ 20185 #define BCMI_HURACAN_MDC_CONTROLr_MDC_DGLH_CNTf_GET(r) ((((r).mdc_control[0]) >> 12) & 0xf) 20186 #define BCMI_HURACAN_MDC_CONTROLr_MDC_DGLH_CNTf_SET(r,f) (r).mdc_control[0]=(((r).mdc_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 20187 #define BCMI_HURACAN_MDC_CONTROLr_MDC_INVERT_ENf_GET(r) ((((r).mdc_control[0]) >> 10) & 0x1) 20188 #define BCMI_HURACAN_MDC_CONTROLr_MDC_INVERT_ENf_SET(r,f) (r).mdc_control[0]=(((r).mdc_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 20189 #define BCMI_HURACAN_MDC_CONTROLr_MDC_IBYPf_GET(r) ((((r).mdc_control[0]) >> 9) & 0x1) 20190 #define BCMI_HURACAN_MDC_CONTROLr_MDC_IBYPf_SET(r,f) (r).mdc_control[0]=(((r).mdc_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 20191 20192 /* 20193 * These macros can be used to access MDC_CONTROL. 20194 */ 20195 #define BCMI_HURACAN_READ_MDC_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDC_CONTROLr,_r._mdc_control) 20196 #define BCMI_HURACAN_WRITE_MDC_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDC_CONTROLr,_r._mdc_control) 20197 20198 /* 20199 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20200 * will be redefined without the chip prefix for easier programming. 20201 * If multiple chips will be programmed in the same source file, then you should 20202 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20203 * and refer to the fully qualified versions. 20204 */ 20205 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20206 20207 #define MDC_CONTROLr BCMI_HURACAN_MDC_CONTROLr 20208 #define MDC_CONTROLr_SIZE BCMI_HURACAN_MDC_CONTROLr_SIZE 20209 typedef BCMI_HURACAN_MDC_CONTROLr_t MDC_CONTROLr_t; 20210 #define MDC_CONTROLr_CLR BCMI_HURACAN_MDC_CONTROLr_CLR 20211 #define MDC_CONTROLr_SET BCMI_HURACAN_MDC_CONTROLr_SET 20212 #define MDC_CONTROLr_GET BCMI_HURACAN_MDC_CONTROLr_GET 20213 #define MDC_CONTROLr_MDC_DGLH_CNTf_GET BCMI_HURACAN_MDC_CONTROLr_MDC_DGLH_CNTf_GET 20214 #define MDC_CONTROLr_MDC_DGLH_CNTf_SET BCMI_HURACAN_MDC_CONTROLr_MDC_DGLH_CNTf_SET 20215 #define MDC_CONTROLr_MDC_INVERT_ENf_GET BCMI_HURACAN_MDC_CONTROLr_MDC_INVERT_ENf_GET 20216 #define MDC_CONTROLr_MDC_INVERT_ENf_SET BCMI_HURACAN_MDC_CONTROLr_MDC_INVERT_ENf_SET 20217 #define MDC_CONTROLr_MDC_IBYPf_GET BCMI_HURACAN_MDC_CONTROLr_MDC_IBYPf_GET 20218 #define MDC_CONTROLr_MDC_IBYPf_SET BCMI_HURACAN_MDC_CONTROLr_MDC_IBYPf_SET 20219 #define READ_MDC_CONTROLr BCMI_HURACAN_READ_MDC_CONTROLr 20220 #define WRITE_MDC_CONTROLr BCMI_HURACAN_WRITE_MDC_CONTROLr 20221 #define MODIFY_MDC_CONTROLr BCMI_HURACAN_MODIFY_MDC_CONTROLr 20222 20223 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20224 /******************************************************************************* 20225 * End of 'BCMI_HURACAN_MDC_CONTROLr' 20226 */ 20227 20228 20229 20230 20231 /******************************************************************************* 20232 * CHIP: BCMI_HURACAN 20233 * REGISTER: MDC_STATUS 20234 * BLOCKS: PAD_CTRL_QUAD_D 20235 * REGADDR: 0xb069 20236 * DEVAD: 1 20237 * DESC: PAD mdc status register 20238 * RESETVAL: 0x0 (0) 20239 * ACCESS: R/W 20240 * FIELDS: 20241 * MDC_DIN_LH 20242 * MDC_DIN_LL 20243 * MDC_DIN 20244 */ 20245 #define BCMI_HURACAN_MDC_STATUSr (0x0001b069 | PHYMOD_REG_ACC_RAW) 20246 20247 #define BCMI_HURACAN_MDC_STATUSr_SIZE 4 20248 20249 /* 20250 * This structure should be used to declare and program MDC_STATUS. 20251 */ 20252 typedef union BCMI_HURACAN_MDC_STATUSr_s { 20253 uint32_t v[1]; 20254 uint32_t mdc_status[1]; 20255 uint32_t _mdc_status; 20256 } BCMI_HURACAN_MDC_STATUSr_t; 20257 20258 #define BCMI_HURACAN_MDC_STATUSr_CLR(r) (r).mdc_status[0] = 0 20259 #define BCMI_HURACAN_MDC_STATUSr_SET(r,d) (r).mdc_status[0] = d 20260 #define BCMI_HURACAN_MDC_STATUSr_GET(r) (r).mdc_status[0] 20261 20262 /* 20263 * These macros can be used to access individual fields. 20264 */ 20265 #define BCMI_HURACAN_MDC_STATUSr_MDC_DINf_GET(r) ((((r).mdc_status[0]) >> 2) & 0x1) 20266 #define BCMI_HURACAN_MDC_STATUSr_MDC_DINf_SET(r,f) (r).mdc_status[0]=(((r).mdc_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20267 #define BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LLf_GET(r) ((((r).mdc_status[0]) >> 1) & 0x1) 20268 #define BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LLf_SET(r,f) (r).mdc_status[0]=(((r).mdc_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20269 #define BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LHf_GET(r) (((r).mdc_status[0]) & 0x1) 20270 #define BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LHf_SET(r,f) (r).mdc_status[0]=(((r).mdc_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 20271 20272 /* 20273 * These macros can be used to access MDC_STATUS. 20274 */ 20275 #define BCMI_HURACAN_READ_MDC_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDC_STATUSr,_r._mdc_status) 20276 #define BCMI_HURACAN_WRITE_MDC_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDC_STATUSr,_r._mdc_status) 20277 20278 /* 20279 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20280 * will be redefined without the chip prefix for easier programming. 20281 * If multiple chips will be programmed in the same source file, then you should 20282 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20283 * and refer to the fully qualified versions. 20284 */ 20285 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20286 20287 #define MDC_STATUSr BCMI_HURACAN_MDC_STATUSr 20288 #define MDC_STATUSr_SIZE BCMI_HURACAN_MDC_STATUSr_SIZE 20289 typedef BCMI_HURACAN_MDC_STATUSr_t MDC_STATUSr_t; 20290 #define MDC_STATUSr_CLR BCMI_HURACAN_MDC_STATUSr_CLR 20291 #define MDC_STATUSr_SET BCMI_HURACAN_MDC_STATUSr_SET 20292 #define MDC_STATUSr_GET BCMI_HURACAN_MDC_STATUSr_GET 20293 #define MDC_STATUSr_MDC_DINf_GET BCMI_HURACAN_MDC_STATUSr_MDC_DINf_GET 20294 #define MDC_STATUSr_MDC_DINf_SET BCMI_HURACAN_MDC_STATUSr_MDC_DINf_SET 20295 #define MDC_STATUSr_MDC_DIN_LLf_GET BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LLf_GET 20296 #define MDC_STATUSr_MDC_DIN_LLf_SET BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LLf_SET 20297 #define MDC_STATUSr_MDC_DIN_LHf_GET BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LHf_GET 20298 #define MDC_STATUSr_MDC_DIN_LHf_SET BCMI_HURACAN_MDC_STATUSr_MDC_DIN_LHf_SET 20299 #define READ_MDC_STATUSr BCMI_HURACAN_READ_MDC_STATUSr 20300 #define WRITE_MDC_STATUSr BCMI_HURACAN_WRITE_MDC_STATUSr 20301 #define MODIFY_MDC_STATUSr BCMI_HURACAN_MODIFY_MDC_STATUSr 20302 20303 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20304 /******************************************************************************* 20305 * End of 'BCMI_HURACAN_MDC_STATUSr' 20306 */ 20307 20308 20309 20310 20311 /******************************************************************************* 20312 * CHIP: BCMI_HURACAN 20313 * REGISTER: MDIO_CONTROL 20314 * BLOCKS: PAD_CTRL_QUAD_D 20315 * REGADDR: 0xb06a 20316 * DEVAD: 1 20317 * DESC: PAD mdio control register 20318 * RESETVAL: 0x0 (0) 20319 * ACCESS: R/W 20320 * FIELDS: 20321 * MDIO_SEL0 20322 * MDIO_SEL1 20323 * MDIO_SEL2 20324 * MDIO_IBOF 20325 * MDIO_INVERT_EN 20326 * MDIO_OUT_FRCVAL 20327 * MDIO_DGLH_CNT 20328 */ 20329 #define BCMI_HURACAN_MDIO_CONTROLr (0x0001b06a | PHYMOD_REG_ACC_RAW) 20330 20331 #define BCMI_HURACAN_MDIO_CONTROLr_SIZE 4 20332 20333 /* 20334 * This structure should be used to declare and program MDIO_CONTROL. 20335 */ 20336 typedef union BCMI_HURACAN_MDIO_CONTROLr_s { 20337 uint32_t v[1]; 20338 uint32_t mdio_control[1]; 20339 uint32_t _mdio_control; 20340 } BCMI_HURACAN_MDIO_CONTROLr_t; 20341 20342 #define BCMI_HURACAN_MDIO_CONTROLr_CLR(r) (r).mdio_control[0] = 0 20343 #define BCMI_HURACAN_MDIO_CONTROLr_SET(r,d) (r).mdio_control[0] = d 20344 #define BCMI_HURACAN_MDIO_CONTROLr_GET(r) (r).mdio_control[0] 20345 20346 /* 20347 * These macros can be used to access individual fields. 20348 */ 20349 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_DGLH_CNTf_GET(r) ((((r).mdio_control[0]) >> 12) & 0xf) 20350 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_DGLH_CNTf_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 20351 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_OUT_FRCVALf_GET(r) ((((r).mdio_control[0]) >> 11) & 0x1) 20352 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_OUT_FRCVALf_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) | (1 << (16 + 11)) 20353 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_INVERT_ENf_GET(r) ((((r).mdio_control[0]) >> 10) & 0x1) 20354 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_INVERT_ENf_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 20355 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_IBOFf_GET(r) ((((r).mdio_control[0]) >> 9) & 0x1) 20356 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_IBOFf_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 20357 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL2f_GET(r) ((((r).mdio_control[0]) >> 7) & 0x1) 20358 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL2f_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) | (1 << (16 + 7)) 20359 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL1f_GET(r) ((((r).mdio_control[0]) >> 6) & 0x1) 20360 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL1f_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) | (1 << (16 + 6)) 20361 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL0f_GET(r) ((((r).mdio_control[0]) >> 5) & 0x1) 20362 #define BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL0f_SET(r,f) (r).mdio_control[0]=(((r).mdio_control[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) | (1 << (16 + 5)) 20363 20364 /* 20365 * These macros can be used to access MDIO_CONTROL. 20366 */ 20367 #define BCMI_HURACAN_READ_MDIO_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDIO_CONTROLr,_r._mdio_control) 20368 #define BCMI_HURACAN_WRITE_MDIO_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDIO_CONTROLr,_r._mdio_control) 20369 20370 /* 20371 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20372 * will be redefined without the chip prefix for easier programming. 20373 * If multiple chips will be programmed in the same source file, then you should 20374 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20375 * and refer to the fully qualified versions. 20376 */ 20377 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20378 20379 #define MDIO_CONTROLr BCMI_HURACAN_MDIO_CONTROLr 20380 #define MDIO_CONTROLr_SIZE BCMI_HURACAN_MDIO_CONTROLr_SIZE 20381 typedef BCMI_HURACAN_MDIO_CONTROLr_t MDIO_CONTROLr_t; 20382 #define MDIO_CONTROLr_CLR BCMI_HURACAN_MDIO_CONTROLr_CLR 20383 #define MDIO_CONTROLr_SET BCMI_HURACAN_MDIO_CONTROLr_SET 20384 #define MDIO_CONTROLr_GET BCMI_HURACAN_MDIO_CONTROLr_GET 20385 #define MDIO_CONTROLr_MDIO_DGLH_CNTf_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_DGLH_CNTf_GET 20386 #define MDIO_CONTROLr_MDIO_DGLH_CNTf_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_DGLH_CNTf_SET 20387 #define MDIO_CONTROLr_MDIO_OUT_FRCVALf_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_OUT_FRCVALf_GET 20388 #define MDIO_CONTROLr_MDIO_OUT_FRCVALf_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_OUT_FRCVALf_SET 20389 #define MDIO_CONTROLr_MDIO_INVERT_ENf_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_INVERT_ENf_GET 20390 #define MDIO_CONTROLr_MDIO_INVERT_ENf_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_INVERT_ENf_SET 20391 #define MDIO_CONTROLr_MDIO_IBOFf_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_IBOFf_GET 20392 #define MDIO_CONTROLr_MDIO_IBOFf_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_IBOFf_SET 20393 #define MDIO_CONTROLr_MDIO_SEL2f_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL2f_GET 20394 #define MDIO_CONTROLr_MDIO_SEL2f_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL2f_SET 20395 #define MDIO_CONTROLr_MDIO_SEL1f_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL1f_GET 20396 #define MDIO_CONTROLr_MDIO_SEL1f_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL1f_SET 20397 #define MDIO_CONTROLr_MDIO_SEL0f_GET BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL0f_GET 20398 #define MDIO_CONTROLr_MDIO_SEL0f_SET BCMI_HURACAN_MDIO_CONTROLr_MDIO_SEL0f_SET 20399 #define READ_MDIO_CONTROLr BCMI_HURACAN_READ_MDIO_CONTROLr 20400 #define WRITE_MDIO_CONTROLr BCMI_HURACAN_WRITE_MDIO_CONTROLr 20401 #define MODIFY_MDIO_CONTROLr BCMI_HURACAN_MODIFY_MDIO_CONTROLr 20402 20403 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20404 /******************************************************************************* 20405 * End of 'BCMI_HURACAN_MDIO_CONTROLr' 20406 */ 20407 20408 20409 20410 20411 /******************************************************************************* 20412 * CHIP: BCMI_HURACAN 20413 * REGISTER: MDIO_STATUS 20414 * BLOCKS: PAD_CTRL_QUAD_D 20415 * REGADDR: 0xb06b 20416 * DEVAD: 1 20417 * DESC: PAD mdio status register 20418 * RESETVAL: 0x0 (0) 20419 * ACCESS: R/W 20420 * FIELDS: 20421 * MDIO_DIN_LH 20422 * MDIO_DIN_LL 20423 * MDIO_DIN 20424 */ 20425 #define BCMI_HURACAN_MDIO_STATUSr (0x0001b06b | PHYMOD_REG_ACC_RAW) 20426 20427 #define BCMI_HURACAN_MDIO_STATUSr_SIZE 4 20428 20429 /* 20430 * This structure should be used to declare and program MDIO_STATUS. 20431 */ 20432 typedef union BCMI_HURACAN_MDIO_STATUSr_s { 20433 uint32_t v[1]; 20434 uint32_t mdio_status[1]; 20435 uint32_t _mdio_status; 20436 } BCMI_HURACAN_MDIO_STATUSr_t; 20437 20438 #define BCMI_HURACAN_MDIO_STATUSr_CLR(r) (r).mdio_status[0] = 0 20439 #define BCMI_HURACAN_MDIO_STATUSr_SET(r,d) (r).mdio_status[0] = d 20440 #define BCMI_HURACAN_MDIO_STATUSr_GET(r) (r).mdio_status[0] 20441 20442 /* 20443 * These macros can be used to access individual fields. 20444 */ 20445 #define BCMI_HURACAN_MDIO_STATUSr_MDIO_DINf_GET(r) ((((r).mdio_status[0]) >> 2) & 0x1) 20446 #define BCMI_HURACAN_MDIO_STATUSr_MDIO_DINf_SET(r,f) (r).mdio_status[0]=(((r).mdio_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20447 #define BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LLf_GET(r) ((((r).mdio_status[0]) >> 1) & 0x1) 20448 #define BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LLf_SET(r,f) (r).mdio_status[0]=(((r).mdio_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20449 #define BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LHf_GET(r) (((r).mdio_status[0]) & 0x1) 20450 #define BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LHf_SET(r,f) (r).mdio_status[0]=(((r).mdio_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 20451 20452 /* 20453 * These macros can be used to access MDIO_STATUS. 20454 */ 20455 #define BCMI_HURACAN_READ_MDIO_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDIO_STATUSr,_r._mdio_status) 20456 #define BCMI_HURACAN_WRITE_MDIO_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDIO_STATUSr,_r._mdio_status) 20457 20458 /* 20459 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20460 * will be redefined without the chip prefix for easier programming. 20461 * If multiple chips will be programmed in the same source file, then you should 20462 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20463 * and refer to the fully qualified versions. 20464 */ 20465 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20466 20467 #define MDIO_STATUSr BCMI_HURACAN_MDIO_STATUSr 20468 #define MDIO_STATUSr_SIZE BCMI_HURACAN_MDIO_STATUSr_SIZE 20469 typedef BCMI_HURACAN_MDIO_STATUSr_t MDIO_STATUSr_t; 20470 #define MDIO_STATUSr_CLR BCMI_HURACAN_MDIO_STATUSr_CLR 20471 #define MDIO_STATUSr_SET BCMI_HURACAN_MDIO_STATUSr_SET 20472 #define MDIO_STATUSr_GET BCMI_HURACAN_MDIO_STATUSr_GET 20473 #define MDIO_STATUSr_MDIO_DINf_GET BCMI_HURACAN_MDIO_STATUSr_MDIO_DINf_GET 20474 #define MDIO_STATUSr_MDIO_DINf_SET BCMI_HURACAN_MDIO_STATUSr_MDIO_DINf_SET 20475 #define MDIO_STATUSr_MDIO_DIN_LLf_GET BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LLf_GET 20476 #define MDIO_STATUSr_MDIO_DIN_LLf_SET BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LLf_SET 20477 #define MDIO_STATUSr_MDIO_DIN_LHf_GET BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LHf_GET 20478 #define MDIO_STATUSr_MDIO_DIN_LHf_SET BCMI_HURACAN_MDIO_STATUSr_MDIO_DIN_LHf_SET 20479 #define READ_MDIO_STATUSr BCMI_HURACAN_READ_MDIO_STATUSr 20480 #define WRITE_MDIO_STATUSr BCMI_HURACAN_WRITE_MDIO_STATUSr 20481 #define MODIFY_MDIO_STATUSr BCMI_HURACAN_MODIFY_MDIO_STATUSr 20482 20483 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20484 /******************************************************************************* 20485 * End of 'BCMI_HURACAN_MDIO_STATUSr' 20486 */ 20487 20488 20489 20490 20491 /******************************************************************************* 20492 * CHIP: BCMI_HURACAN 20493 * REGISTER: ADR0_CONTROL 20494 * BLOCKS: PAD_CTRL_QUAD_D 20495 * REGADDR: 0xb06c 20496 * DEVAD: 1 20497 * DESC: PAD adr0 control register 20498 * RESETVAL: 0x0 (0) 20499 * ACCESS: R/W 20500 * FIELDS: 20501 * ADR0_PUP 20502 * ADR0_PDN 20503 * ADR0_IBYP 20504 * ADR0_INVERT_EN 20505 * ADR0_DGLH_CNT 20506 */ 20507 #define BCMI_HURACAN_ADR0_CONTROLr (0x0001b06c | PHYMOD_REG_ACC_RAW) 20508 20509 #define BCMI_HURACAN_ADR0_CONTROLr_SIZE 4 20510 20511 /* 20512 * This structure should be used to declare and program ADR0_CONTROL. 20513 */ 20514 typedef union BCMI_HURACAN_ADR0_CONTROLr_s { 20515 uint32_t v[1]; 20516 uint32_t adr0_control[1]; 20517 uint32_t _adr0_control; 20518 } BCMI_HURACAN_ADR0_CONTROLr_t; 20519 20520 #define BCMI_HURACAN_ADR0_CONTROLr_CLR(r) (r).adr0_control[0] = 0 20521 #define BCMI_HURACAN_ADR0_CONTROLr_SET(r,d) (r).adr0_control[0] = d 20522 #define BCMI_HURACAN_ADR0_CONTROLr_GET(r) (r).adr0_control[0] 20523 20524 /* 20525 * These macros can be used to access individual fields. 20526 */ 20527 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_DGLH_CNTf_GET(r) ((((r).adr0_control[0]) >> 12) & 0xf) 20528 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_DGLH_CNTf_SET(r,f) (r).adr0_control[0]=(((r).adr0_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 20529 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_INVERT_ENf_GET(r) ((((r).adr0_control[0]) >> 10) & 0x1) 20530 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_INVERT_ENf_SET(r,f) (r).adr0_control[0]=(((r).adr0_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 20531 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_IBYPf_GET(r) ((((r).adr0_control[0]) >> 9) & 0x1) 20532 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_IBYPf_SET(r,f) (r).adr0_control[0]=(((r).adr0_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 20533 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_PDNf_GET(r) ((((r).adr0_control[0]) >> 2) & 0x1) 20534 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_PDNf_SET(r,f) (r).adr0_control[0]=(((r).adr0_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20535 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_PUPf_GET(r) ((((r).adr0_control[0]) >> 1) & 0x1) 20536 #define BCMI_HURACAN_ADR0_CONTROLr_ADR0_PUPf_SET(r,f) (r).adr0_control[0]=(((r).adr0_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20537 20538 /* 20539 * These macros can be used to access ADR0_CONTROL. 20540 */ 20541 #define BCMI_HURACAN_READ_ADR0_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR0_CONTROLr,_r._adr0_control) 20542 #define BCMI_HURACAN_WRITE_ADR0_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR0_CONTROLr,_r._adr0_control) 20543 20544 /* 20545 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20546 * will be redefined without the chip prefix for easier programming. 20547 * If multiple chips will be programmed in the same source file, then you should 20548 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20549 * and refer to the fully qualified versions. 20550 */ 20551 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20552 20553 #define ADR0_CONTROLr BCMI_HURACAN_ADR0_CONTROLr 20554 #define ADR0_CONTROLr_SIZE BCMI_HURACAN_ADR0_CONTROLr_SIZE 20555 typedef BCMI_HURACAN_ADR0_CONTROLr_t ADR0_CONTROLr_t; 20556 #define ADR0_CONTROLr_CLR BCMI_HURACAN_ADR0_CONTROLr_CLR 20557 #define ADR0_CONTROLr_SET BCMI_HURACAN_ADR0_CONTROLr_SET 20558 #define ADR0_CONTROLr_GET BCMI_HURACAN_ADR0_CONTROLr_GET 20559 #define ADR0_CONTROLr_ADR0_DGLH_CNTf_GET BCMI_HURACAN_ADR0_CONTROLr_ADR0_DGLH_CNTf_GET 20560 #define ADR0_CONTROLr_ADR0_DGLH_CNTf_SET BCMI_HURACAN_ADR0_CONTROLr_ADR0_DGLH_CNTf_SET 20561 #define ADR0_CONTROLr_ADR0_INVERT_ENf_GET BCMI_HURACAN_ADR0_CONTROLr_ADR0_INVERT_ENf_GET 20562 #define ADR0_CONTROLr_ADR0_INVERT_ENf_SET BCMI_HURACAN_ADR0_CONTROLr_ADR0_INVERT_ENf_SET 20563 #define ADR0_CONTROLr_ADR0_IBYPf_GET BCMI_HURACAN_ADR0_CONTROLr_ADR0_IBYPf_GET 20564 #define ADR0_CONTROLr_ADR0_IBYPf_SET BCMI_HURACAN_ADR0_CONTROLr_ADR0_IBYPf_SET 20565 #define ADR0_CONTROLr_ADR0_PDNf_GET BCMI_HURACAN_ADR0_CONTROLr_ADR0_PDNf_GET 20566 #define ADR0_CONTROLr_ADR0_PDNf_SET BCMI_HURACAN_ADR0_CONTROLr_ADR0_PDNf_SET 20567 #define ADR0_CONTROLr_ADR0_PUPf_GET BCMI_HURACAN_ADR0_CONTROLr_ADR0_PUPf_GET 20568 #define ADR0_CONTROLr_ADR0_PUPf_SET BCMI_HURACAN_ADR0_CONTROLr_ADR0_PUPf_SET 20569 #define READ_ADR0_CONTROLr BCMI_HURACAN_READ_ADR0_CONTROLr 20570 #define WRITE_ADR0_CONTROLr BCMI_HURACAN_WRITE_ADR0_CONTROLr 20571 #define MODIFY_ADR0_CONTROLr BCMI_HURACAN_MODIFY_ADR0_CONTROLr 20572 20573 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20574 /******************************************************************************* 20575 * End of 'BCMI_HURACAN_ADR0_CONTROLr' 20576 */ 20577 20578 20579 20580 20581 /******************************************************************************* 20582 * CHIP: BCMI_HURACAN 20583 * REGISTER: ADR0_STATUS 20584 * BLOCKS: PAD_CTRL_QUAD_D 20585 * REGADDR: 0xb06d 20586 * DEVAD: 1 20587 * DESC: PAD adr0 status register 20588 * RESETVAL: 0x0 (0) 20589 * ACCESS: R/W 20590 * FIELDS: 20591 * ADR0_DIN_LH 20592 * ADR0_DIN_LL 20593 * ADR0_DIN 20594 */ 20595 #define BCMI_HURACAN_ADR0_STATUSr (0x0001b06d | PHYMOD_REG_ACC_RAW) 20596 20597 #define BCMI_HURACAN_ADR0_STATUSr_SIZE 4 20598 20599 /* 20600 * This structure should be used to declare and program ADR0_STATUS. 20601 */ 20602 typedef union BCMI_HURACAN_ADR0_STATUSr_s { 20603 uint32_t v[1]; 20604 uint32_t adr0_status[1]; 20605 uint32_t _adr0_status; 20606 } BCMI_HURACAN_ADR0_STATUSr_t; 20607 20608 #define BCMI_HURACAN_ADR0_STATUSr_CLR(r) (r).adr0_status[0] = 0 20609 #define BCMI_HURACAN_ADR0_STATUSr_SET(r,d) (r).adr0_status[0] = d 20610 #define BCMI_HURACAN_ADR0_STATUSr_GET(r) (r).adr0_status[0] 20611 20612 /* 20613 * These macros can be used to access individual fields. 20614 */ 20615 #define BCMI_HURACAN_ADR0_STATUSr_ADR0_DINf_GET(r) ((((r).adr0_status[0]) >> 2) & 0x1) 20616 #define BCMI_HURACAN_ADR0_STATUSr_ADR0_DINf_SET(r,f) (r).adr0_status[0]=(((r).adr0_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20617 #define BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LLf_GET(r) ((((r).adr0_status[0]) >> 1) & 0x1) 20618 #define BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LLf_SET(r,f) (r).adr0_status[0]=(((r).adr0_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20619 #define BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LHf_GET(r) (((r).adr0_status[0]) & 0x1) 20620 #define BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LHf_SET(r,f) (r).adr0_status[0]=(((r).adr0_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 20621 20622 /* 20623 * These macros can be used to access ADR0_STATUS. 20624 */ 20625 #define BCMI_HURACAN_READ_ADR0_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR0_STATUSr,_r._adr0_status) 20626 #define BCMI_HURACAN_WRITE_ADR0_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR0_STATUSr,_r._adr0_status) 20627 20628 /* 20629 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20630 * will be redefined without the chip prefix for easier programming. 20631 * If multiple chips will be programmed in the same source file, then you should 20632 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20633 * and refer to the fully qualified versions. 20634 */ 20635 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20636 20637 #define ADR0_STATUSr BCMI_HURACAN_ADR0_STATUSr 20638 #define ADR0_STATUSr_SIZE BCMI_HURACAN_ADR0_STATUSr_SIZE 20639 typedef BCMI_HURACAN_ADR0_STATUSr_t ADR0_STATUSr_t; 20640 #define ADR0_STATUSr_CLR BCMI_HURACAN_ADR0_STATUSr_CLR 20641 #define ADR0_STATUSr_SET BCMI_HURACAN_ADR0_STATUSr_SET 20642 #define ADR0_STATUSr_GET BCMI_HURACAN_ADR0_STATUSr_GET 20643 #define ADR0_STATUSr_ADR0_DINf_GET BCMI_HURACAN_ADR0_STATUSr_ADR0_DINf_GET 20644 #define ADR0_STATUSr_ADR0_DINf_SET BCMI_HURACAN_ADR0_STATUSr_ADR0_DINf_SET 20645 #define ADR0_STATUSr_ADR0_DIN_LLf_GET BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LLf_GET 20646 #define ADR0_STATUSr_ADR0_DIN_LLf_SET BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LLf_SET 20647 #define ADR0_STATUSr_ADR0_DIN_LHf_GET BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LHf_GET 20648 #define ADR0_STATUSr_ADR0_DIN_LHf_SET BCMI_HURACAN_ADR0_STATUSr_ADR0_DIN_LHf_SET 20649 #define READ_ADR0_STATUSr BCMI_HURACAN_READ_ADR0_STATUSr 20650 #define WRITE_ADR0_STATUSr BCMI_HURACAN_WRITE_ADR0_STATUSr 20651 #define MODIFY_ADR0_STATUSr BCMI_HURACAN_MODIFY_ADR0_STATUSr 20652 20653 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20654 /******************************************************************************* 20655 * End of 'BCMI_HURACAN_ADR0_STATUSr' 20656 */ 20657 20658 20659 20660 20661 /******************************************************************************* 20662 * CHIP: BCMI_HURACAN 20663 * REGISTER: ADR1_CONTROL 20664 * BLOCKS: PAD_CTRL_QUAD_D 20665 * REGADDR: 0xb06e 20666 * DEVAD: 1 20667 * DESC: PAD adr1 control register 20668 * RESETVAL: 0x0 (0) 20669 * ACCESS: R/W 20670 * FIELDS: 20671 * ADR1_PUP 20672 * ADR1_PDN 20673 * ADR1_IBYP 20674 * ADR1_INVERT_EN 20675 * ADR1_DGLH_CNT 20676 */ 20677 #define BCMI_HURACAN_ADR1_CONTROLr (0x0001b06e | PHYMOD_REG_ACC_RAW) 20678 20679 #define BCMI_HURACAN_ADR1_CONTROLr_SIZE 4 20680 20681 /* 20682 * This structure should be used to declare and program ADR1_CONTROL. 20683 */ 20684 typedef union BCMI_HURACAN_ADR1_CONTROLr_s { 20685 uint32_t v[1]; 20686 uint32_t adr1_control[1]; 20687 uint32_t _adr1_control; 20688 } BCMI_HURACAN_ADR1_CONTROLr_t; 20689 20690 #define BCMI_HURACAN_ADR1_CONTROLr_CLR(r) (r).adr1_control[0] = 0 20691 #define BCMI_HURACAN_ADR1_CONTROLr_SET(r,d) (r).adr1_control[0] = d 20692 #define BCMI_HURACAN_ADR1_CONTROLr_GET(r) (r).adr1_control[0] 20693 20694 /* 20695 * These macros can be used to access individual fields. 20696 */ 20697 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_DGLH_CNTf_GET(r) ((((r).adr1_control[0]) >> 12) & 0xf) 20698 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_DGLH_CNTf_SET(r,f) (r).adr1_control[0]=(((r).adr1_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 20699 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_INVERT_ENf_GET(r) ((((r).adr1_control[0]) >> 10) & 0x1) 20700 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_INVERT_ENf_SET(r,f) (r).adr1_control[0]=(((r).adr1_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 20701 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_IBYPf_GET(r) ((((r).adr1_control[0]) >> 9) & 0x1) 20702 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_IBYPf_SET(r,f) (r).adr1_control[0]=(((r).adr1_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 20703 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_PDNf_GET(r) ((((r).adr1_control[0]) >> 2) & 0x1) 20704 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_PDNf_SET(r,f) (r).adr1_control[0]=(((r).adr1_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20705 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_PUPf_GET(r) ((((r).adr1_control[0]) >> 1) & 0x1) 20706 #define BCMI_HURACAN_ADR1_CONTROLr_ADR1_PUPf_SET(r,f) (r).adr1_control[0]=(((r).adr1_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20707 20708 /* 20709 * These macros can be used to access ADR1_CONTROL. 20710 */ 20711 #define BCMI_HURACAN_READ_ADR1_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR1_CONTROLr,_r._adr1_control) 20712 #define BCMI_HURACAN_WRITE_ADR1_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR1_CONTROLr,_r._adr1_control) 20713 20714 /* 20715 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20716 * will be redefined without the chip prefix for easier programming. 20717 * If multiple chips will be programmed in the same source file, then you should 20718 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20719 * and refer to the fully qualified versions. 20720 */ 20721 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20722 20723 #define ADR1_CONTROLr BCMI_HURACAN_ADR1_CONTROLr 20724 #define ADR1_CONTROLr_SIZE BCMI_HURACAN_ADR1_CONTROLr_SIZE 20725 typedef BCMI_HURACAN_ADR1_CONTROLr_t ADR1_CONTROLr_t; 20726 #define ADR1_CONTROLr_CLR BCMI_HURACAN_ADR1_CONTROLr_CLR 20727 #define ADR1_CONTROLr_SET BCMI_HURACAN_ADR1_CONTROLr_SET 20728 #define ADR1_CONTROLr_GET BCMI_HURACAN_ADR1_CONTROLr_GET 20729 #define ADR1_CONTROLr_ADR1_DGLH_CNTf_GET BCMI_HURACAN_ADR1_CONTROLr_ADR1_DGLH_CNTf_GET 20730 #define ADR1_CONTROLr_ADR1_DGLH_CNTf_SET BCMI_HURACAN_ADR1_CONTROLr_ADR1_DGLH_CNTf_SET 20731 #define ADR1_CONTROLr_ADR1_INVERT_ENf_GET BCMI_HURACAN_ADR1_CONTROLr_ADR1_INVERT_ENf_GET 20732 #define ADR1_CONTROLr_ADR1_INVERT_ENf_SET BCMI_HURACAN_ADR1_CONTROLr_ADR1_INVERT_ENf_SET 20733 #define ADR1_CONTROLr_ADR1_IBYPf_GET BCMI_HURACAN_ADR1_CONTROLr_ADR1_IBYPf_GET 20734 #define ADR1_CONTROLr_ADR1_IBYPf_SET BCMI_HURACAN_ADR1_CONTROLr_ADR1_IBYPf_SET 20735 #define ADR1_CONTROLr_ADR1_PDNf_GET BCMI_HURACAN_ADR1_CONTROLr_ADR1_PDNf_GET 20736 #define ADR1_CONTROLr_ADR1_PDNf_SET BCMI_HURACAN_ADR1_CONTROLr_ADR1_PDNf_SET 20737 #define ADR1_CONTROLr_ADR1_PUPf_GET BCMI_HURACAN_ADR1_CONTROLr_ADR1_PUPf_GET 20738 #define ADR1_CONTROLr_ADR1_PUPf_SET BCMI_HURACAN_ADR1_CONTROLr_ADR1_PUPf_SET 20739 #define READ_ADR1_CONTROLr BCMI_HURACAN_READ_ADR1_CONTROLr 20740 #define WRITE_ADR1_CONTROLr BCMI_HURACAN_WRITE_ADR1_CONTROLr 20741 #define MODIFY_ADR1_CONTROLr BCMI_HURACAN_MODIFY_ADR1_CONTROLr 20742 20743 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20744 /******************************************************************************* 20745 * End of 'BCMI_HURACAN_ADR1_CONTROLr' 20746 */ 20747 20748 20749 20750 20751 /******************************************************************************* 20752 * CHIP: BCMI_HURACAN 20753 * REGISTER: ADR1_STATUS 20754 * BLOCKS: PAD_CTRL_QUAD_D 20755 * REGADDR: 0xb06f 20756 * DEVAD: 1 20757 * DESC: PAD adr1 status register 20758 * RESETVAL: 0x0 (0) 20759 * ACCESS: R/W 20760 * FIELDS: 20761 * ADR1_DIN_LH 20762 * ADR1_DIN_LL 20763 * ADR1_DIN 20764 */ 20765 #define BCMI_HURACAN_ADR1_STATUSr (0x0001b06f | PHYMOD_REG_ACC_RAW) 20766 20767 #define BCMI_HURACAN_ADR1_STATUSr_SIZE 4 20768 20769 /* 20770 * This structure should be used to declare and program ADR1_STATUS. 20771 */ 20772 typedef union BCMI_HURACAN_ADR1_STATUSr_s { 20773 uint32_t v[1]; 20774 uint32_t adr1_status[1]; 20775 uint32_t _adr1_status; 20776 } BCMI_HURACAN_ADR1_STATUSr_t; 20777 20778 #define BCMI_HURACAN_ADR1_STATUSr_CLR(r) (r).adr1_status[0] = 0 20779 #define BCMI_HURACAN_ADR1_STATUSr_SET(r,d) (r).adr1_status[0] = d 20780 #define BCMI_HURACAN_ADR1_STATUSr_GET(r) (r).adr1_status[0] 20781 20782 /* 20783 * These macros can be used to access individual fields. 20784 */ 20785 #define BCMI_HURACAN_ADR1_STATUSr_ADR1_DINf_GET(r) ((((r).adr1_status[0]) >> 2) & 0x1) 20786 #define BCMI_HURACAN_ADR1_STATUSr_ADR1_DINf_SET(r,f) (r).adr1_status[0]=(((r).adr1_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20787 #define BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LLf_GET(r) ((((r).adr1_status[0]) >> 1) & 0x1) 20788 #define BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LLf_SET(r,f) (r).adr1_status[0]=(((r).adr1_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20789 #define BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LHf_GET(r) (((r).adr1_status[0]) & 0x1) 20790 #define BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LHf_SET(r,f) (r).adr1_status[0]=(((r).adr1_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 20791 20792 /* 20793 * These macros can be used to access ADR1_STATUS. 20794 */ 20795 #define BCMI_HURACAN_READ_ADR1_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR1_STATUSr,_r._adr1_status) 20796 #define BCMI_HURACAN_WRITE_ADR1_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR1_STATUSr,_r._adr1_status) 20797 20798 /* 20799 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20800 * will be redefined without the chip prefix for easier programming. 20801 * If multiple chips will be programmed in the same source file, then you should 20802 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20803 * and refer to the fully qualified versions. 20804 */ 20805 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20806 20807 #define ADR1_STATUSr BCMI_HURACAN_ADR1_STATUSr 20808 #define ADR1_STATUSr_SIZE BCMI_HURACAN_ADR1_STATUSr_SIZE 20809 typedef BCMI_HURACAN_ADR1_STATUSr_t ADR1_STATUSr_t; 20810 #define ADR1_STATUSr_CLR BCMI_HURACAN_ADR1_STATUSr_CLR 20811 #define ADR1_STATUSr_SET BCMI_HURACAN_ADR1_STATUSr_SET 20812 #define ADR1_STATUSr_GET BCMI_HURACAN_ADR1_STATUSr_GET 20813 #define ADR1_STATUSr_ADR1_DINf_GET BCMI_HURACAN_ADR1_STATUSr_ADR1_DINf_GET 20814 #define ADR1_STATUSr_ADR1_DINf_SET BCMI_HURACAN_ADR1_STATUSr_ADR1_DINf_SET 20815 #define ADR1_STATUSr_ADR1_DIN_LLf_GET BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LLf_GET 20816 #define ADR1_STATUSr_ADR1_DIN_LLf_SET BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LLf_SET 20817 #define ADR1_STATUSr_ADR1_DIN_LHf_GET BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LHf_GET 20818 #define ADR1_STATUSr_ADR1_DIN_LHf_SET BCMI_HURACAN_ADR1_STATUSr_ADR1_DIN_LHf_SET 20819 #define READ_ADR1_STATUSr BCMI_HURACAN_READ_ADR1_STATUSr 20820 #define WRITE_ADR1_STATUSr BCMI_HURACAN_WRITE_ADR1_STATUSr 20821 #define MODIFY_ADR1_STATUSr BCMI_HURACAN_MODIFY_ADR1_STATUSr 20822 20823 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20824 /******************************************************************************* 20825 * End of 'BCMI_HURACAN_ADR1_STATUSr' 20826 */ 20827 20828 20829 20830 20831 /******************************************************************************* 20832 * CHIP: BCMI_HURACAN 20833 * REGISTER: ADR2_CONTROL 20834 * BLOCKS: PAD_CTRL_QUAD_D 20835 * REGADDR: 0xb070 20836 * DEVAD: 1 20837 * DESC: PAD adr2 control register 20838 * RESETVAL: 0x0 (0) 20839 * ACCESS: R/W 20840 * FIELDS: 20841 * ADR2_PUP 20842 * ADR2_PDN 20843 * ADR2_IBYP 20844 * ADR2_INVERT_EN 20845 * ADR2_DGLH_CNT 20846 */ 20847 #define BCMI_HURACAN_ADR2_CONTROLr (0x0001b070 | PHYMOD_REG_ACC_RAW) 20848 20849 #define BCMI_HURACAN_ADR2_CONTROLr_SIZE 4 20850 20851 /* 20852 * This structure should be used to declare and program ADR2_CONTROL. 20853 */ 20854 typedef union BCMI_HURACAN_ADR2_CONTROLr_s { 20855 uint32_t v[1]; 20856 uint32_t adr2_control[1]; 20857 uint32_t _adr2_control; 20858 } BCMI_HURACAN_ADR2_CONTROLr_t; 20859 20860 #define BCMI_HURACAN_ADR2_CONTROLr_CLR(r) (r).adr2_control[0] = 0 20861 #define BCMI_HURACAN_ADR2_CONTROLr_SET(r,d) (r).adr2_control[0] = d 20862 #define BCMI_HURACAN_ADR2_CONTROLr_GET(r) (r).adr2_control[0] 20863 20864 /* 20865 * These macros can be used to access individual fields. 20866 */ 20867 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_DGLH_CNTf_GET(r) ((((r).adr2_control[0]) >> 12) & 0xf) 20868 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_DGLH_CNTf_SET(r,f) (r).adr2_control[0]=(((r).adr2_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 20869 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_INVERT_ENf_GET(r) ((((r).adr2_control[0]) >> 10) & 0x1) 20870 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_INVERT_ENf_SET(r,f) (r).adr2_control[0]=(((r).adr2_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 20871 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_IBYPf_GET(r) ((((r).adr2_control[0]) >> 9) & 0x1) 20872 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_IBYPf_SET(r,f) (r).adr2_control[0]=(((r).adr2_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 20873 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_PDNf_GET(r) ((((r).adr2_control[0]) >> 2) & 0x1) 20874 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_PDNf_SET(r,f) (r).adr2_control[0]=(((r).adr2_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20875 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_PUPf_GET(r) ((((r).adr2_control[0]) >> 1) & 0x1) 20876 #define BCMI_HURACAN_ADR2_CONTROLr_ADR2_PUPf_SET(r,f) (r).adr2_control[0]=(((r).adr2_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20877 20878 /* 20879 * These macros can be used to access ADR2_CONTROL. 20880 */ 20881 #define BCMI_HURACAN_READ_ADR2_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR2_CONTROLr,_r._adr2_control) 20882 #define BCMI_HURACAN_WRITE_ADR2_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR2_CONTROLr,_r._adr2_control) 20883 20884 /* 20885 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20886 * will be redefined without the chip prefix for easier programming. 20887 * If multiple chips will be programmed in the same source file, then you should 20888 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20889 * and refer to the fully qualified versions. 20890 */ 20891 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20892 20893 #define ADR2_CONTROLr BCMI_HURACAN_ADR2_CONTROLr 20894 #define ADR2_CONTROLr_SIZE BCMI_HURACAN_ADR2_CONTROLr_SIZE 20895 typedef BCMI_HURACAN_ADR2_CONTROLr_t ADR2_CONTROLr_t; 20896 #define ADR2_CONTROLr_CLR BCMI_HURACAN_ADR2_CONTROLr_CLR 20897 #define ADR2_CONTROLr_SET BCMI_HURACAN_ADR2_CONTROLr_SET 20898 #define ADR2_CONTROLr_GET BCMI_HURACAN_ADR2_CONTROLr_GET 20899 #define ADR2_CONTROLr_ADR2_DGLH_CNTf_GET BCMI_HURACAN_ADR2_CONTROLr_ADR2_DGLH_CNTf_GET 20900 #define ADR2_CONTROLr_ADR2_DGLH_CNTf_SET BCMI_HURACAN_ADR2_CONTROLr_ADR2_DGLH_CNTf_SET 20901 #define ADR2_CONTROLr_ADR2_INVERT_ENf_GET BCMI_HURACAN_ADR2_CONTROLr_ADR2_INVERT_ENf_GET 20902 #define ADR2_CONTROLr_ADR2_INVERT_ENf_SET BCMI_HURACAN_ADR2_CONTROLr_ADR2_INVERT_ENf_SET 20903 #define ADR2_CONTROLr_ADR2_IBYPf_GET BCMI_HURACAN_ADR2_CONTROLr_ADR2_IBYPf_GET 20904 #define ADR2_CONTROLr_ADR2_IBYPf_SET BCMI_HURACAN_ADR2_CONTROLr_ADR2_IBYPf_SET 20905 #define ADR2_CONTROLr_ADR2_PDNf_GET BCMI_HURACAN_ADR2_CONTROLr_ADR2_PDNf_GET 20906 #define ADR2_CONTROLr_ADR2_PDNf_SET BCMI_HURACAN_ADR2_CONTROLr_ADR2_PDNf_SET 20907 #define ADR2_CONTROLr_ADR2_PUPf_GET BCMI_HURACAN_ADR2_CONTROLr_ADR2_PUPf_GET 20908 #define ADR2_CONTROLr_ADR2_PUPf_SET BCMI_HURACAN_ADR2_CONTROLr_ADR2_PUPf_SET 20909 #define READ_ADR2_CONTROLr BCMI_HURACAN_READ_ADR2_CONTROLr 20910 #define WRITE_ADR2_CONTROLr BCMI_HURACAN_WRITE_ADR2_CONTROLr 20911 #define MODIFY_ADR2_CONTROLr BCMI_HURACAN_MODIFY_ADR2_CONTROLr 20912 20913 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20914 /******************************************************************************* 20915 * End of 'BCMI_HURACAN_ADR2_CONTROLr' 20916 */ 20917 20918 20919 20920 20921 /******************************************************************************* 20922 * CHIP: BCMI_HURACAN 20923 * REGISTER: ADR2_STATUS 20924 * BLOCKS: PAD_CTRL_QUAD_D 20925 * REGADDR: 0xb071 20926 * DEVAD: 1 20927 * DESC: PAD adr2 status register 20928 * RESETVAL: 0x0 (0) 20929 * ACCESS: R/W 20930 * FIELDS: 20931 * ADR2_DIN_LH 20932 * ADR2_DIN_LL 20933 * ADR2_DIN 20934 */ 20935 #define BCMI_HURACAN_ADR2_STATUSr (0x0001b071 | PHYMOD_REG_ACC_RAW) 20936 20937 #define BCMI_HURACAN_ADR2_STATUSr_SIZE 4 20938 20939 /* 20940 * This structure should be used to declare and program ADR2_STATUS. 20941 */ 20942 typedef union BCMI_HURACAN_ADR2_STATUSr_s { 20943 uint32_t v[1]; 20944 uint32_t adr2_status[1]; 20945 uint32_t _adr2_status; 20946 } BCMI_HURACAN_ADR2_STATUSr_t; 20947 20948 #define BCMI_HURACAN_ADR2_STATUSr_CLR(r) (r).adr2_status[0] = 0 20949 #define BCMI_HURACAN_ADR2_STATUSr_SET(r,d) (r).adr2_status[0] = d 20950 #define BCMI_HURACAN_ADR2_STATUSr_GET(r) (r).adr2_status[0] 20951 20952 /* 20953 * These macros can be used to access individual fields. 20954 */ 20955 #define BCMI_HURACAN_ADR2_STATUSr_ADR2_DINf_GET(r) ((((r).adr2_status[0]) >> 2) & 0x1) 20956 #define BCMI_HURACAN_ADR2_STATUSr_ADR2_DINf_SET(r,f) (r).adr2_status[0]=(((r).adr2_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 20957 #define BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LLf_GET(r) ((((r).adr2_status[0]) >> 1) & 0x1) 20958 #define BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LLf_SET(r,f) (r).adr2_status[0]=(((r).adr2_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 20959 #define BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LHf_GET(r) (((r).adr2_status[0]) & 0x1) 20960 #define BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LHf_SET(r,f) (r).adr2_status[0]=(((r).adr2_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 20961 20962 /* 20963 * These macros can be used to access ADR2_STATUS. 20964 */ 20965 #define BCMI_HURACAN_READ_ADR2_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR2_STATUSr,_r._adr2_status) 20966 #define BCMI_HURACAN_WRITE_ADR2_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR2_STATUSr,_r._adr2_status) 20967 20968 /* 20969 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 20970 * will be redefined without the chip prefix for easier programming. 20971 * If multiple chips will be programmed in the same source file, then you should 20972 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 20973 * and refer to the fully qualified versions. 20974 */ 20975 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 20976 20977 #define ADR2_STATUSr BCMI_HURACAN_ADR2_STATUSr 20978 #define ADR2_STATUSr_SIZE BCMI_HURACAN_ADR2_STATUSr_SIZE 20979 typedef BCMI_HURACAN_ADR2_STATUSr_t ADR2_STATUSr_t; 20980 #define ADR2_STATUSr_CLR BCMI_HURACAN_ADR2_STATUSr_CLR 20981 #define ADR2_STATUSr_SET BCMI_HURACAN_ADR2_STATUSr_SET 20982 #define ADR2_STATUSr_GET BCMI_HURACAN_ADR2_STATUSr_GET 20983 #define ADR2_STATUSr_ADR2_DINf_GET BCMI_HURACAN_ADR2_STATUSr_ADR2_DINf_GET 20984 #define ADR2_STATUSr_ADR2_DINf_SET BCMI_HURACAN_ADR2_STATUSr_ADR2_DINf_SET 20985 #define ADR2_STATUSr_ADR2_DIN_LLf_GET BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LLf_GET 20986 #define ADR2_STATUSr_ADR2_DIN_LLf_SET BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LLf_SET 20987 #define ADR2_STATUSr_ADR2_DIN_LHf_GET BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LHf_GET 20988 #define ADR2_STATUSr_ADR2_DIN_LHf_SET BCMI_HURACAN_ADR2_STATUSr_ADR2_DIN_LHf_SET 20989 #define READ_ADR2_STATUSr BCMI_HURACAN_READ_ADR2_STATUSr 20990 #define WRITE_ADR2_STATUSr BCMI_HURACAN_WRITE_ADR2_STATUSr 20991 #define MODIFY_ADR2_STATUSr BCMI_HURACAN_MODIFY_ADR2_STATUSr 20992 20993 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 20994 /******************************************************************************* 20995 * End of 'BCMI_HURACAN_ADR2_STATUSr' 20996 */ 20997 20998 20999 21000 21001 /******************************************************************************* 21002 * CHIP: BCMI_HURACAN 21003 * REGISTER: ADR3_CONTROL 21004 * BLOCKS: PAD_CTRL_QUAD_D 21005 * REGADDR: 0xb072 21006 * DEVAD: 1 21007 * DESC: PAD adr3 control register 21008 * RESETVAL: 0x0 (0) 21009 * ACCESS: R/W 21010 * FIELDS: 21011 * ADR3_PUP 21012 * ADR3_PDN 21013 * ADR3_IBYP 21014 * ADR3_INVERT_EN 21015 * ADR3_DGLH_CNT 21016 */ 21017 #define BCMI_HURACAN_ADR3_CONTROLr (0x0001b072 | PHYMOD_REG_ACC_RAW) 21018 21019 #define BCMI_HURACAN_ADR3_CONTROLr_SIZE 4 21020 21021 /* 21022 * This structure should be used to declare and program ADR3_CONTROL. 21023 */ 21024 typedef union BCMI_HURACAN_ADR3_CONTROLr_s { 21025 uint32_t v[1]; 21026 uint32_t adr3_control[1]; 21027 uint32_t _adr3_control; 21028 } BCMI_HURACAN_ADR3_CONTROLr_t; 21029 21030 #define BCMI_HURACAN_ADR3_CONTROLr_CLR(r) (r).adr3_control[0] = 0 21031 #define BCMI_HURACAN_ADR3_CONTROLr_SET(r,d) (r).adr3_control[0] = d 21032 #define BCMI_HURACAN_ADR3_CONTROLr_GET(r) (r).adr3_control[0] 21033 21034 /* 21035 * These macros can be used to access individual fields. 21036 */ 21037 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_DGLH_CNTf_GET(r) ((((r).adr3_control[0]) >> 12) & 0xf) 21038 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_DGLH_CNTf_SET(r,f) (r).adr3_control[0]=(((r).adr3_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 21039 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_INVERT_ENf_GET(r) ((((r).adr3_control[0]) >> 10) & 0x1) 21040 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_INVERT_ENf_SET(r,f) (r).adr3_control[0]=(((r).adr3_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 21041 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_IBYPf_GET(r) ((((r).adr3_control[0]) >> 9) & 0x1) 21042 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_IBYPf_SET(r,f) (r).adr3_control[0]=(((r).adr3_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 21043 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_PDNf_GET(r) ((((r).adr3_control[0]) >> 2) & 0x1) 21044 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_PDNf_SET(r,f) (r).adr3_control[0]=(((r).adr3_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21045 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_PUPf_GET(r) ((((r).adr3_control[0]) >> 1) & 0x1) 21046 #define BCMI_HURACAN_ADR3_CONTROLr_ADR3_PUPf_SET(r,f) (r).adr3_control[0]=(((r).adr3_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21047 21048 /* 21049 * These macros can be used to access ADR3_CONTROL. 21050 */ 21051 #define BCMI_HURACAN_READ_ADR3_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR3_CONTROLr,_r._adr3_control) 21052 #define BCMI_HURACAN_WRITE_ADR3_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR3_CONTROLr,_r._adr3_control) 21053 21054 /* 21055 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21056 * will be redefined without the chip prefix for easier programming. 21057 * If multiple chips will be programmed in the same source file, then you should 21058 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21059 * and refer to the fully qualified versions. 21060 */ 21061 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21062 21063 #define ADR3_CONTROLr BCMI_HURACAN_ADR3_CONTROLr 21064 #define ADR3_CONTROLr_SIZE BCMI_HURACAN_ADR3_CONTROLr_SIZE 21065 typedef BCMI_HURACAN_ADR3_CONTROLr_t ADR3_CONTROLr_t; 21066 #define ADR3_CONTROLr_CLR BCMI_HURACAN_ADR3_CONTROLr_CLR 21067 #define ADR3_CONTROLr_SET BCMI_HURACAN_ADR3_CONTROLr_SET 21068 #define ADR3_CONTROLr_GET BCMI_HURACAN_ADR3_CONTROLr_GET 21069 #define ADR3_CONTROLr_ADR3_DGLH_CNTf_GET BCMI_HURACAN_ADR3_CONTROLr_ADR3_DGLH_CNTf_GET 21070 #define ADR3_CONTROLr_ADR3_DGLH_CNTf_SET BCMI_HURACAN_ADR3_CONTROLr_ADR3_DGLH_CNTf_SET 21071 #define ADR3_CONTROLr_ADR3_INVERT_ENf_GET BCMI_HURACAN_ADR3_CONTROLr_ADR3_INVERT_ENf_GET 21072 #define ADR3_CONTROLr_ADR3_INVERT_ENf_SET BCMI_HURACAN_ADR3_CONTROLr_ADR3_INVERT_ENf_SET 21073 #define ADR3_CONTROLr_ADR3_IBYPf_GET BCMI_HURACAN_ADR3_CONTROLr_ADR3_IBYPf_GET 21074 #define ADR3_CONTROLr_ADR3_IBYPf_SET BCMI_HURACAN_ADR3_CONTROLr_ADR3_IBYPf_SET 21075 #define ADR3_CONTROLr_ADR3_PDNf_GET BCMI_HURACAN_ADR3_CONTROLr_ADR3_PDNf_GET 21076 #define ADR3_CONTROLr_ADR3_PDNf_SET BCMI_HURACAN_ADR3_CONTROLr_ADR3_PDNf_SET 21077 #define ADR3_CONTROLr_ADR3_PUPf_GET BCMI_HURACAN_ADR3_CONTROLr_ADR3_PUPf_GET 21078 #define ADR3_CONTROLr_ADR3_PUPf_SET BCMI_HURACAN_ADR3_CONTROLr_ADR3_PUPf_SET 21079 #define READ_ADR3_CONTROLr BCMI_HURACAN_READ_ADR3_CONTROLr 21080 #define WRITE_ADR3_CONTROLr BCMI_HURACAN_WRITE_ADR3_CONTROLr 21081 #define MODIFY_ADR3_CONTROLr BCMI_HURACAN_MODIFY_ADR3_CONTROLr 21082 21083 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21084 /******************************************************************************* 21085 * End of 'BCMI_HURACAN_ADR3_CONTROLr' 21086 */ 21087 21088 21089 21090 21091 /******************************************************************************* 21092 * CHIP: BCMI_HURACAN 21093 * REGISTER: ADR3_STATUS 21094 * BLOCKS: PAD_CTRL_QUAD_D 21095 * REGADDR: 0xb073 21096 * DEVAD: 1 21097 * DESC: PAD adr3 status register 21098 * RESETVAL: 0x0 (0) 21099 * ACCESS: R/W 21100 * FIELDS: 21101 * ADR3_DIN_LH 21102 * ADR3_DIN_LL 21103 * ADR3_DIN 21104 */ 21105 #define BCMI_HURACAN_ADR3_STATUSr (0x0001b073 | PHYMOD_REG_ACC_RAW) 21106 21107 #define BCMI_HURACAN_ADR3_STATUSr_SIZE 4 21108 21109 /* 21110 * This structure should be used to declare and program ADR3_STATUS. 21111 */ 21112 typedef union BCMI_HURACAN_ADR3_STATUSr_s { 21113 uint32_t v[1]; 21114 uint32_t adr3_status[1]; 21115 uint32_t _adr3_status; 21116 } BCMI_HURACAN_ADR3_STATUSr_t; 21117 21118 #define BCMI_HURACAN_ADR3_STATUSr_CLR(r) (r).adr3_status[0] = 0 21119 #define BCMI_HURACAN_ADR3_STATUSr_SET(r,d) (r).adr3_status[0] = d 21120 #define BCMI_HURACAN_ADR3_STATUSr_GET(r) (r).adr3_status[0] 21121 21122 /* 21123 * These macros can be used to access individual fields. 21124 */ 21125 #define BCMI_HURACAN_ADR3_STATUSr_ADR3_DINf_GET(r) ((((r).adr3_status[0]) >> 2) & 0x1) 21126 #define BCMI_HURACAN_ADR3_STATUSr_ADR3_DINf_SET(r,f) (r).adr3_status[0]=(((r).adr3_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21127 #define BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LLf_GET(r) ((((r).adr3_status[0]) >> 1) & 0x1) 21128 #define BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LLf_SET(r,f) (r).adr3_status[0]=(((r).adr3_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21129 #define BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LHf_GET(r) (((r).adr3_status[0]) & 0x1) 21130 #define BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LHf_SET(r,f) (r).adr3_status[0]=(((r).adr3_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21131 21132 /* 21133 * These macros can be used to access ADR3_STATUS. 21134 */ 21135 #define BCMI_HURACAN_READ_ADR3_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ADR3_STATUSr,_r._adr3_status) 21136 #define BCMI_HURACAN_WRITE_ADR3_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ADR3_STATUSr,_r._adr3_status) 21137 21138 /* 21139 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21140 * will be redefined without the chip prefix for easier programming. 21141 * If multiple chips will be programmed in the same source file, then you should 21142 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21143 * and refer to the fully qualified versions. 21144 */ 21145 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21146 21147 #define ADR3_STATUSr BCMI_HURACAN_ADR3_STATUSr 21148 #define ADR3_STATUSr_SIZE BCMI_HURACAN_ADR3_STATUSr_SIZE 21149 typedef BCMI_HURACAN_ADR3_STATUSr_t ADR3_STATUSr_t; 21150 #define ADR3_STATUSr_CLR BCMI_HURACAN_ADR3_STATUSr_CLR 21151 #define ADR3_STATUSr_SET BCMI_HURACAN_ADR3_STATUSr_SET 21152 #define ADR3_STATUSr_GET BCMI_HURACAN_ADR3_STATUSr_GET 21153 #define ADR3_STATUSr_ADR3_DINf_GET BCMI_HURACAN_ADR3_STATUSr_ADR3_DINf_GET 21154 #define ADR3_STATUSr_ADR3_DINf_SET BCMI_HURACAN_ADR3_STATUSr_ADR3_DINf_SET 21155 #define ADR3_STATUSr_ADR3_DIN_LLf_GET BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LLf_GET 21156 #define ADR3_STATUSr_ADR3_DIN_LLf_SET BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LLf_SET 21157 #define ADR3_STATUSr_ADR3_DIN_LHf_GET BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LHf_GET 21158 #define ADR3_STATUSr_ADR3_DIN_LHf_SET BCMI_HURACAN_ADR3_STATUSr_ADR3_DIN_LHf_SET 21159 #define READ_ADR3_STATUSr BCMI_HURACAN_READ_ADR3_STATUSr 21160 #define WRITE_ADR3_STATUSr BCMI_HURACAN_WRITE_ADR3_STATUSr 21161 #define MODIFY_ADR3_STATUSr BCMI_HURACAN_MODIFY_ADR3_STATUSr 21162 21163 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21164 /******************************************************************************* 21165 * End of 'BCMI_HURACAN_ADR3_STATUSr' 21166 */ 21167 21168 21169 21170 21171 /******************************************************************************* 21172 * CHIP: BCMI_HURACAN 21173 * REGISTER: MDIO_SEL_CONTROL 21174 * BLOCKS: PAD_CTRL_QUAD_D 21175 * REGADDR: 0xb074 21176 * DEVAD: 1 21177 * DESC: PAD mdio_sel control register 21178 * RESETVAL: 0x0 (0) 21179 * ACCESS: R/W 21180 * FIELDS: 21181 * MDIO_SEL_PUP 21182 * MDIO_SEL_PDN 21183 * MDIO_SEL_IBYP 21184 * MDIO_SEL_INVERT_EN 21185 * MDIO_SEL_DGLH_CNT 21186 */ 21187 #define BCMI_HURACAN_MDIO_SEL_CONTROLr (0x0001b074 | PHYMOD_REG_ACC_RAW) 21188 21189 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_SIZE 4 21190 21191 /* 21192 * This structure should be used to declare and program MDIO_SEL_CONTROL. 21193 */ 21194 typedef union BCMI_HURACAN_MDIO_SEL_CONTROLr_s { 21195 uint32_t v[1]; 21196 uint32_t mdio_sel_control[1]; 21197 uint32_t _mdio_sel_control; 21198 } BCMI_HURACAN_MDIO_SEL_CONTROLr_t; 21199 21200 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_CLR(r) (r).mdio_sel_control[0] = 0 21201 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_SET(r,d) (r).mdio_sel_control[0] = d 21202 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_GET(r) (r).mdio_sel_control[0] 21203 21204 /* 21205 * These macros can be used to access individual fields. 21206 */ 21207 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_DGLH_CNTf_GET(r) ((((r).mdio_sel_control[0]) >> 12) & 0xf) 21208 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_DGLH_CNTf_SET(r,f) (r).mdio_sel_control[0]=(((r).mdio_sel_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 21209 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_INVERT_ENf_GET(r) ((((r).mdio_sel_control[0]) >> 10) & 0x1) 21210 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_INVERT_ENf_SET(r,f) (r).mdio_sel_control[0]=(((r).mdio_sel_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 21211 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_IBYPf_GET(r) ((((r).mdio_sel_control[0]) >> 9) & 0x1) 21212 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_IBYPf_SET(r,f) (r).mdio_sel_control[0]=(((r).mdio_sel_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 21213 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PDNf_GET(r) ((((r).mdio_sel_control[0]) >> 2) & 0x1) 21214 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PDNf_SET(r,f) (r).mdio_sel_control[0]=(((r).mdio_sel_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21215 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PUPf_GET(r) ((((r).mdio_sel_control[0]) >> 1) & 0x1) 21216 #define BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PUPf_SET(r,f) (r).mdio_sel_control[0]=(((r).mdio_sel_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21217 21218 /* 21219 * These macros can be used to access MDIO_SEL_CONTROL. 21220 */ 21221 #define BCMI_HURACAN_READ_MDIO_SEL_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDIO_SEL_CONTROLr,_r._mdio_sel_control) 21222 #define BCMI_HURACAN_WRITE_MDIO_SEL_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDIO_SEL_CONTROLr,_r._mdio_sel_control) 21223 21224 /* 21225 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21226 * will be redefined without the chip prefix for easier programming. 21227 * If multiple chips will be programmed in the same source file, then you should 21228 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21229 * and refer to the fully qualified versions. 21230 */ 21231 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21232 21233 #define MDIO_SEL_CONTROLr BCMI_HURACAN_MDIO_SEL_CONTROLr 21234 #define MDIO_SEL_CONTROLr_SIZE BCMI_HURACAN_MDIO_SEL_CONTROLr_SIZE 21235 typedef BCMI_HURACAN_MDIO_SEL_CONTROLr_t MDIO_SEL_CONTROLr_t; 21236 #define MDIO_SEL_CONTROLr_CLR BCMI_HURACAN_MDIO_SEL_CONTROLr_CLR 21237 #define MDIO_SEL_CONTROLr_SET BCMI_HURACAN_MDIO_SEL_CONTROLr_SET 21238 #define MDIO_SEL_CONTROLr_GET BCMI_HURACAN_MDIO_SEL_CONTROLr_GET 21239 #define MDIO_SEL_CONTROLr_MDIO_SEL_DGLH_CNTf_GET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_DGLH_CNTf_GET 21240 #define MDIO_SEL_CONTROLr_MDIO_SEL_DGLH_CNTf_SET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_DGLH_CNTf_SET 21241 #define MDIO_SEL_CONTROLr_MDIO_SEL_INVERT_ENf_GET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_INVERT_ENf_GET 21242 #define MDIO_SEL_CONTROLr_MDIO_SEL_INVERT_ENf_SET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_INVERT_ENf_SET 21243 #define MDIO_SEL_CONTROLr_MDIO_SEL_IBYPf_GET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_IBYPf_GET 21244 #define MDIO_SEL_CONTROLr_MDIO_SEL_IBYPf_SET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_IBYPf_SET 21245 #define MDIO_SEL_CONTROLr_MDIO_SEL_PDNf_GET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PDNf_GET 21246 #define MDIO_SEL_CONTROLr_MDIO_SEL_PDNf_SET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PDNf_SET 21247 #define MDIO_SEL_CONTROLr_MDIO_SEL_PUPf_GET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PUPf_GET 21248 #define MDIO_SEL_CONTROLr_MDIO_SEL_PUPf_SET BCMI_HURACAN_MDIO_SEL_CONTROLr_MDIO_SEL_PUPf_SET 21249 #define READ_MDIO_SEL_CONTROLr BCMI_HURACAN_READ_MDIO_SEL_CONTROLr 21250 #define WRITE_MDIO_SEL_CONTROLr BCMI_HURACAN_WRITE_MDIO_SEL_CONTROLr 21251 #define MODIFY_MDIO_SEL_CONTROLr BCMI_HURACAN_MODIFY_MDIO_SEL_CONTROLr 21252 21253 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21254 /******************************************************************************* 21255 * End of 'BCMI_HURACAN_MDIO_SEL_CONTROLr' 21256 */ 21257 21258 21259 21260 21261 /******************************************************************************* 21262 * CHIP: BCMI_HURACAN 21263 * REGISTER: MDIO_SEL_STATUS 21264 * BLOCKS: PAD_CTRL_QUAD_D 21265 * REGADDR: 0xb075 21266 * DEVAD: 1 21267 * DESC: PAD mdio_sel status register 21268 * RESETVAL: 0x0 (0) 21269 * ACCESS: R/W 21270 * FIELDS: 21271 * MDIO_SEL_DIN_LH 21272 * MDIO_SEL_DIN_LL 21273 * MDIO_SEL_DIN 21274 */ 21275 #define BCMI_HURACAN_MDIO_SEL_STATUSr (0x0001b075 | PHYMOD_REG_ACC_RAW) 21276 21277 #define BCMI_HURACAN_MDIO_SEL_STATUSr_SIZE 4 21278 21279 /* 21280 * This structure should be used to declare and program MDIO_SEL_STATUS. 21281 */ 21282 typedef union BCMI_HURACAN_MDIO_SEL_STATUSr_s { 21283 uint32_t v[1]; 21284 uint32_t mdio_sel_status[1]; 21285 uint32_t _mdio_sel_status; 21286 } BCMI_HURACAN_MDIO_SEL_STATUSr_t; 21287 21288 #define BCMI_HURACAN_MDIO_SEL_STATUSr_CLR(r) (r).mdio_sel_status[0] = 0 21289 #define BCMI_HURACAN_MDIO_SEL_STATUSr_SET(r,d) (r).mdio_sel_status[0] = d 21290 #define BCMI_HURACAN_MDIO_SEL_STATUSr_GET(r) (r).mdio_sel_status[0] 21291 21292 /* 21293 * These macros can be used to access individual fields. 21294 */ 21295 #define BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DINf_GET(r) ((((r).mdio_sel_status[0]) >> 2) & 0x1) 21296 #define BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DINf_SET(r,f) (r).mdio_sel_status[0]=(((r).mdio_sel_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21297 #define BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LLf_GET(r) ((((r).mdio_sel_status[0]) >> 1) & 0x1) 21298 #define BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LLf_SET(r,f) (r).mdio_sel_status[0]=(((r).mdio_sel_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21299 #define BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LHf_GET(r) (((r).mdio_sel_status[0]) & 0x1) 21300 #define BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LHf_SET(r,f) (r).mdio_sel_status[0]=(((r).mdio_sel_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21301 21302 /* 21303 * These macros can be used to access MDIO_SEL_STATUS. 21304 */ 21305 #define BCMI_HURACAN_READ_MDIO_SEL_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_MDIO_SEL_STATUSr,_r._mdio_sel_status) 21306 #define BCMI_HURACAN_WRITE_MDIO_SEL_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_MDIO_SEL_STATUSr,_r._mdio_sel_status) 21307 21308 /* 21309 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21310 * will be redefined without the chip prefix for easier programming. 21311 * If multiple chips will be programmed in the same source file, then you should 21312 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21313 * and refer to the fully qualified versions. 21314 */ 21315 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21316 21317 #define MDIO_SEL_STATUSr BCMI_HURACAN_MDIO_SEL_STATUSr 21318 #define MDIO_SEL_STATUSr_SIZE BCMI_HURACAN_MDIO_SEL_STATUSr_SIZE 21319 typedef BCMI_HURACAN_MDIO_SEL_STATUSr_t MDIO_SEL_STATUSr_t; 21320 #define MDIO_SEL_STATUSr_CLR BCMI_HURACAN_MDIO_SEL_STATUSr_CLR 21321 #define MDIO_SEL_STATUSr_SET BCMI_HURACAN_MDIO_SEL_STATUSr_SET 21322 #define MDIO_SEL_STATUSr_GET BCMI_HURACAN_MDIO_SEL_STATUSr_GET 21323 #define MDIO_SEL_STATUSr_MDIO_SEL_DINf_GET BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DINf_GET 21324 #define MDIO_SEL_STATUSr_MDIO_SEL_DINf_SET BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DINf_SET 21325 #define MDIO_SEL_STATUSr_MDIO_SEL_DIN_LLf_GET BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LLf_GET 21326 #define MDIO_SEL_STATUSr_MDIO_SEL_DIN_LLf_SET BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LLf_SET 21327 #define MDIO_SEL_STATUSr_MDIO_SEL_DIN_LHf_GET BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LHf_GET 21328 #define MDIO_SEL_STATUSr_MDIO_SEL_DIN_LHf_SET BCMI_HURACAN_MDIO_SEL_STATUSr_MDIO_SEL_DIN_LHf_SET 21329 #define READ_MDIO_SEL_STATUSr BCMI_HURACAN_READ_MDIO_SEL_STATUSr 21330 #define WRITE_MDIO_SEL_STATUSr BCMI_HURACAN_WRITE_MDIO_SEL_STATUSr 21331 #define MODIFY_MDIO_SEL_STATUSr BCMI_HURACAN_MODIFY_MDIO_SEL_STATUSr 21332 21333 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21334 /******************************************************************************* 21335 * End of 'BCMI_HURACAN_MDIO_SEL_STATUSr' 21336 */ 21337 21338 21339 21340 21341 /******************************************************************************* 21342 * CHIP: BCMI_HURACAN 21343 * REGISTER: EXT_INTRB_CONTROL 21344 * BLOCKS: PAD_CTRL_QUAD_D 21345 * REGADDR: 0xb076 21346 * DEVAD: 1 21347 * DESC: PAD ext_intrb control register 21348 * RESETVAL: 0x0 (0) 21349 * ACCESS: R/W 21350 * FIELDS: 21351 * EXT_INTRB_OEB 21352 * EXT_INTRB_SEL0 21353 * EXT_INTRB_SEL1 21354 * EXT_INTRB_SEL2 21355 * EXT_INTRB_IBOF 21356 * EXT_INTRB_INVERT_EN 21357 * EXT_INTRB_OUT_FRCVAL 21358 * EXT_INTRB_DGLH_CNT 21359 */ 21360 #define BCMI_HURACAN_EXT_INTRB_CONTROLr (0x0001b076 | PHYMOD_REG_ACC_RAW) 21361 21362 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_SIZE 4 21363 21364 /* 21365 * This structure should be used to declare and program EXT_INTRB_CONTROL. 21366 */ 21367 typedef union BCMI_HURACAN_EXT_INTRB_CONTROLr_s { 21368 uint32_t v[1]; 21369 uint32_t ext_intrb_control[1]; 21370 uint32_t _ext_intrb_control; 21371 } BCMI_HURACAN_EXT_INTRB_CONTROLr_t; 21372 21373 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_CLR(r) (r).ext_intrb_control[0] = 0 21374 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_SET(r,d) (r).ext_intrb_control[0] = d 21375 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_GET(r) (r).ext_intrb_control[0] 21376 21377 /* 21378 * These macros can be used to access individual fields. 21379 */ 21380 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_DGLH_CNTf_GET(r) ((((r).ext_intrb_control[0]) >> 12) & 0xf) 21381 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_DGLH_CNTf_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 21382 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OUT_FRCVALf_GET(r) ((((r).ext_intrb_control[0]) >> 11) & 0x1) 21383 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OUT_FRCVALf_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) | (1 << (16 + 11)) 21384 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_INVERT_ENf_GET(r) ((((r).ext_intrb_control[0]) >> 10) & 0x1) 21385 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_INVERT_ENf_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 21386 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_IBOFf_GET(r) ((((r).ext_intrb_control[0]) >> 9) & 0x1) 21387 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_IBOFf_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 21388 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL2f_GET(r) ((((r).ext_intrb_control[0]) >> 7) & 0x1) 21389 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL2f_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) | (1 << (16 + 7)) 21390 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL1f_GET(r) ((((r).ext_intrb_control[0]) >> 6) & 0x1) 21391 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL1f_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) | (1 << (16 + 6)) 21392 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL0f_GET(r) ((((r).ext_intrb_control[0]) >> 5) & 0x1) 21393 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL0f_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) | (1 << (16 + 5)) 21394 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OEBf_GET(r) (((r).ext_intrb_control[0]) & 0x1) 21395 #define BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OEBf_SET(r,f) (r).ext_intrb_control[0]=(((r).ext_intrb_control[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21396 21397 /* 21398 * These macros can be used to access EXT_INTRB_CONTROL. 21399 */ 21400 #define BCMI_HURACAN_READ_EXT_INTRB_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_EXT_INTRB_CONTROLr,_r._ext_intrb_control) 21401 #define BCMI_HURACAN_WRITE_EXT_INTRB_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_EXT_INTRB_CONTROLr,_r._ext_intrb_control) 21402 21403 /* 21404 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21405 * will be redefined without the chip prefix for easier programming. 21406 * If multiple chips will be programmed in the same source file, then you should 21407 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21408 * and refer to the fully qualified versions. 21409 */ 21410 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21411 21412 #define EXT_INTRB_CONTROLr BCMI_HURACAN_EXT_INTRB_CONTROLr 21413 #define EXT_INTRB_CONTROLr_SIZE BCMI_HURACAN_EXT_INTRB_CONTROLr_SIZE 21414 typedef BCMI_HURACAN_EXT_INTRB_CONTROLr_t EXT_INTRB_CONTROLr_t; 21415 #define EXT_INTRB_CONTROLr_CLR BCMI_HURACAN_EXT_INTRB_CONTROLr_CLR 21416 #define EXT_INTRB_CONTROLr_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_SET 21417 #define EXT_INTRB_CONTROLr_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_GET 21418 #define EXT_INTRB_CONTROLr_EXT_INTRB_DGLH_CNTf_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_DGLH_CNTf_GET 21419 #define EXT_INTRB_CONTROLr_EXT_INTRB_DGLH_CNTf_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_DGLH_CNTf_SET 21420 #define EXT_INTRB_CONTROLr_EXT_INTRB_OUT_FRCVALf_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OUT_FRCVALf_GET 21421 #define EXT_INTRB_CONTROLr_EXT_INTRB_OUT_FRCVALf_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OUT_FRCVALf_SET 21422 #define EXT_INTRB_CONTROLr_EXT_INTRB_INVERT_ENf_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_INVERT_ENf_GET 21423 #define EXT_INTRB_CONTROLr_EXT_INTRB_INVERT_ENf_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_INVERT_ENf_SET 21424 #define EXT_INTRB_CONTROLr_EXT_INTRB_IBOFf_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_IBOFf_GET 21425 #define EXT_INTRB_CONTROLr_EXT_INTRB_IBOFf_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_IBOFf_SET 21426 #define EXT_INTRB_CONTROLr_EXT_INTRB_SEL2f_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL2f_GET 21427 #define EXT_INTRB_CONTROLr_EXT_INTRB_SEL2f_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL2f_SET 21428 #define EXT_INTRB_CONTROLr_EXT_INTRB_SEL1f_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL1f_GET 21429 #define EXT_INTRB_CONTROLr_EXT_INTRB_SEL1f_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL1f_SET 21430 #define EXT_INTRB_CONTROLr_EXT_INTRB_SEL0f_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL0f_GET 21431 #define EXT_INTRB_CONTROLr_EXT_INTRB_SEL0f_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_SEL0f_SET 21432 #define EXT_INTRB_CONTROLr_EXT_INTRB_OEBf_GET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OEBf_GET 21433 #define EXT_INTRB_CONTROLr_EXT_INTRB_OEBf_SET BCMI_HURACAN_EXT_INTRB_CONTROLr_EXT_INTRB_OEBf_SET 21434 #define READ_EXT_INTRB_CONTROLr BCMI_HURACAN_READ_EXT_INTRB_CONTROLr 21435 #define WRITE_EXT_INTRB_CONTROLr BCMI_HURACAN_WRITE_EXT_INTRB_CONTROLr 21436 #define MODIFY_EXT_INTRB_CONTROLr BCMI_HURACAN_MODIFY_EXT_INTRB_CONTROLr 21437 21438 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21439 /******************************************************************************* 21440 * End of 'BCMI_HURACAN_EXT_INTRB_CONTROLr' 21441 */ 21442 21443 21444 21445 21446 /******************************************************************************* 21447 * CHIP: BCMI_HURACAN 21448 * REGISTER: EXT_INTRB_STATUS 21449 * BLOCKS: PAD_CTRL_QUAD_D 21450 * REGADDR: 0xb077 21451 * DEVAD: 1 21452 * DESC: PAD ext_intrb status register 21453 * RESETVAL: 0x0 (0) 21454 * ACCESS: R/W 21455 * FIELDS: 21456 * EXT_INTRB_DIN_LH 21457 * EXT_INTRB_DIN_LL 21458 * EXT_INTRB_DIN 21459 */ 21460 #define BCMI_HURACAN_EXT_INTRB_STATUSr (0x0001b077 | PHYMOD_REG_ACC_RAW) 21461 21462 #define BCMI_HURACAN_EXT_INTRB_STATUSr_SIZE 4 21463 21464 /* 21465 * This structure should be used to declare and program EXT_INTRB_STATUS. 21466 */ 21467 typedef union BCMI_HURACAN_EXT_INTRB_STATUSr_s { 21468 uint32_t v[1]; 21469 uint32_t ext_intrb_status[1]; 21470 uint32_t _ext_intrb_status; 21471 } BCMI_HURACAN_EXT_INTRB_STATUSr_t; 21472 21473 #define BCMI_HURACAN_EXT_INTRB_STATUSr_CLR(r) (r).ext_intrb_status[0] = 0 21474 #define BCMI_HURACAN_EXT_INTRB_STATUSr_SET(r,d) (r).ext_intrb_status[0] = d 21475 #define BCMI_HURACAN_EXT_INTRB_STATUSr_GET(r) (r).ext_intrb_status[0] 21476 21477 /* 21478 * These macros can be used to access individual fields. 21479 */ 21480 #define BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DINf_GET(r) ((((r).ext_intrb_status[0]) >> 2) & 0x1) 21481 #define BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DINf_SET(r,f) (r).ext_intrb_status[0]=(((r).ext_intrb_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21482 #define BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LLf_GET(r) ((((r).ext_intrb_status[0]) >> 1) & 0x1) 21483 #define BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LLf_SET(r,f) (r).ext_intrb_status[0]=(((r).ext_intrb_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21484 #define BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LHf_GET(r) (((r).ext_intrb_status[0]) & 0x1) 21485 #define BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LHf_SET(r,f) (r).ext_intrb_status[0]=(((r).ext_intrb_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21486 21487 /* 21488 * These macros can be used to access EXT_INTRB_STATUS. 21489 */ 21490 #define BCMI_HURACAN_READ_EXT_INTRB_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_EXT_INTRB_STATUSr,_r._ext_intrb_status) 21491 #define BCMI_HURACAN_WRITE_EXT_INTRB_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_EXT_INTRB_STATUSr,_r._ext_intrb_status) 21492 21493 /* 21494 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21495 * will be redefined without the chip prefix for easier programming. 21496 * If multiple chips will be programmed in the same source file, then you should 21497 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21498 * and refer to the fully qualified versions. 21499 */ 21500 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21501 21502 #define EXT_INTRB_STATUSr BCMI_HURACAN_EXT_INTRB_STATUSr 21503 #define EXT_INTRB_STATUSr_SIZE BCMI_HURACAN_EXT_INTRB_STATUSr_SIZE 21504 typedef BCMI_HURACAN_EXT_INTRB_STATUSr_t EXT_INTRB_STATUSr_t; 21505 #define EXT_INTRB_STATUSr_CLR BCMI_HURACAN_EXT_INTRB_STATUSr_CLR 21506 #define EXT_INTRB_STATUSr_SET BCMI_HURACAN_EXT_INTRB_STATUSr_SET 21507 #define EXT_INTRB_STATUSr_GET BCMI_HURACAN_EXT_INTRB_STATUSr_GET 21508 #define EXT_INTRB_STATUSr_EXT_INTRB_DINf_GET BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DINf_GET 21509 #define EXT_INTRB_STATUSr_EXT_INTRB_DINf_SET BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DINf_SET 21510 #define EXT_INTRB_STATUSr_EXT_INTRB_DIN_LLf_GET BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LLf_GET 21511 #define EXT_INTRB_STATUSr_EXT_INTRB_DIN_LLf_SET BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LLf_SET 21512 #define EXT_INTRB_STATUSr_EXT_INTRB_DIN_LHf_GET BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LHf_GET 21513 #define EXT_INTRB_STATUSr_EXT_INTRB_DIN_LHf_SET BCMI_HURACAN_EXT_INTRB_STATUSr_EXT_INTRB_DIN_LHf_SET 21514 #define READ_EXT_INTRB_STATUSr BCMI_HURACAN_READ_EXT_INTRB_STATUSr 21515 #define WRITE_EXT_INTRB_STATUSr BCMI_HURACAN_WRITE_EXT_INTRB_STATUSr 21516 #define MODIFY_EXT_INTRB_STATUSr BCMI_HURACAN_MODIFY_EXT_INTRB_STATUSr 21517 21518 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21519 /******************************************************************************* 21520 * End of 'BCMI_HURACAN_EXT_INTRB_STATUSr' 21521 */ 21522 21523 21524 21525 21526 /******************************************************************************* 21527 * CHIP: BCMI_HURACAN 21528 * REGISTER: GPIO_0_CONTROL 21529 * BLOCKS: PAD_CTRL_QUAD_D 21530 * REGADDR: 0xb078 21531 * DEVAD: 1 21532 * DESC: PAD gpio_0 control register 21533 * RESETVAL: 0x0 (0) 21534 * ACCESS: R/W 21535 * FIELDS: 21536 * GPIO_0_OEB 21537 * GPIO_0_PUP 21538 * GPIO_0_PDN 21539 * GPIO_0_IND 21540 * GPIO_0_SEL0 21541 * GPIO_0_SEL1 21542 * GPIO_0_SEL2 21543 * GPIO_0_IBOF 21544 * GPIO_0_INVERT_EN 21545 * GPIO_0_OUT_FRCVAL 21546 * GPIO_0_DGLH_CNT 21547 */ 21548 #define BCMI_HURACAN_GPIO_0_CONTROLr (0x0001b078 | PHYMOD_REG_ACC_RAW) 21549 21550 #define BCMI_HURACAN_GPIO_0_CONTROLr_SIZE 4 21551 21552 /* 21553 * This structure should be used to declare and program GPIO_0_CONTROL. 21554 */ 21555 typedef union BCMI_HURACAN_GPIO_0_CONTROLr_s { 21556 uint32_t v[1]; 21557 uint32_t gpio_0_control[1]; 21558 uint32_t _gpio_0_control; 21559 } BCMI_HURACAN_GPIO_0_CONTROLr_t; 21560 21561 #define BCMI_HURACAN_GPIO_0_CONTROLr_CLR(r) (r).gpio_0_control[0] = 0 21562 #define BCMI_HURACAN_GPIO_0_CONTROLr_SET(r,d) (r).gpio_0_control[0] = d 21563 #define BCMI_HURACAN_GPIO_0_CONTROLr_GET(r) (r).gpio_0_control[0] 21564 21565 /* 21566 * These macros can be used to access individual fields. 21567 */ 21568 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_DGLH_CNTf_GET(r) ((((r).gpio_0_control[0]) >> 12) & 0xf) 21569 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_DGLH_CNTf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 21570 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OUT_FRCVALf_GET(r) ((((r).gpio_0_control[0]) >> 11) & 0x1) 21571 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OUT_FRCVALf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) | (1 << (16 + 11)) 21572 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INVERT_ENf_GET(r) ((((r).gpio_0_control[0]) >> 10) & 0x1) 21573 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INVERT_ENf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 21574 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_IBOFf_GET(r) ((((r).gpio_0_control[0]) >> 9) & 0x1) 21575 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_IBOFf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 21576 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL2f_GET(r) ((((r).gpio_0_control[0]) >> 7) & 0x1) 21577 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL2f_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) | (1 << (16 + 7)) 21578 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL1f_GET(r) ((((r).gpio_0_control[0]) >> 6) & 0x1) 21579 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL1f_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) | (1 << (16 + 6)) 21580 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL0f_GET(r) ((((r).gpio_0_control[0]) >> 5) & 0x1) 21581 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL0f_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) | (1 << (16 + 5)) 21582 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INDf_GET(r) ((((r).gpio_0_control[0]) >> 4) & 0x1) 21583 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INDf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 21584 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PDNf_GET(r) ((((r).gpio_0_control[0]) >> 2) & 0x1) 21585 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PDNf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21586 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PUPf_GET(r) ((((r).gpio_0_control[0]) >> 1) & 0x1) 21587 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PUPf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21588 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OEBf_GET(r) (((r).gpio_0_control[0]) & 0x1) 21589 #define BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OEBf_SET(r,f) (r).gpio_0_control[0]=(((r).gpio_0_control[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21590 21591 /* 21592 * These macros can be used to access GPIO_0_CONTROL. 21593 */ 21594 #define BCMI_HURACAN_READ_GPIO_0_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_GPIO_0_CONTROLr,_r._gpio_0_control) 21595 #define BCMI_HURACAN_WRITE_GPIO_0_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_GPIO_0_CONTROLr,_r._gpio_0_control) 21596 21597 /* 21598 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21599 * will be redefined without the chip prefix for easier programming. 21600 * If multiple chips will be programmed in the same source file, then you should 21601 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21602 * and refer to the fully qualified versions. 21603 */ 21604 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21605 21606 #define GPIO_0_CONTROLr BCMI_HURACAN_GPIO_0_CONTROLr 21607 #define GPIO_0_CONTROLr_SIZE BCMI_HURACAN_GPIO_0_CONTROLr_SIZE 21608 typedef BCMI_HURACAN_GPIO_0_CONTROLr_t GPIO_0_CONTROLr_t; 21609 #define GPIO_0_CONTROLr_CLR BCMI_HURACAN_GPIO_0_CONTROLr_CLR 21610 #define GPIO_0_CONTROLr_SET BCMI_HURACAN_GPIO_0_CONTROLr_SET 21611 #define GPIO_0_CONTROLr_GET BCMI_HURACAN_GPIO_0_CONTROLr_GET 21612 #define GPIO_0_CONTROLr_GPIO_0_DGLH_CNTf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_DGLH_CNTf_GET 21613 #define GPIO_0_CONTROLr_GPIO_0_DGLH_CNTf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_DGLH_CNTf_SET 21614 #define GPIO_0_CONTROLr_GPIO_0_OUT_FRCVALf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OUT_FRCVALf_GET 21615 #define GPIO_0_CONTROLr_GPIO_0_OUT_FRCVALf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OUT_FRCVALf_SET 21616 #define GPIO_0_CONTROLr_GPIO_0_INVERT_ENf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INVERT_ENf_GET 21617 #define GPIO_0_CONTROLr_GPIO_0_INVERT_ENf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INVERT_ENf_SET 21618 #define GPIO_0_CONTROLr_GPIO_0_IBOFf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_IBOFf_GET 21619 #define GPIO_0_CONTROLr_GPIO_0_IBOFf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_IBOFf_SET 21620 #define GPIO_0_CONTROLr_GPIO_0_SEL2f_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL2f_GET 21621 #define GPIO_0_CONTROLr_GPIO_0_SEL2f_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL2f_SET 21622 #define GPIO_0_CONTROLr_GPIO_0_SEL1f_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL1f_GET 21623 #define GPIO_0_CONTROLr_GPIO_0_SEL1f_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL1f_SET 21624 #define GPIO_0_CONTROLr_GPIO_0_SEL0f_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL0f_GET 21625 #define GPIO_0_CONTROLr_GPIO_0_SEL0f_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_SEL0f_SET 21626 #define GPIO_0_CONTROLr_GPIO_0_INDf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INDf_GET 21627 #define GPIO_0_CONTROLr_GPIO_0_INDf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_INDf_SET 21628 #define GPIO_0_CONTROLr_GPIO_0_PDNf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PDNf_GET 21629 #define GPIO_0_CONTROLr_GPIO_0_PDNf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PDNf_SET 21630 #define GPIO_0_CONTROLr_GPIO_0_PUPf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PUPf_GET 21631 #define GPIO_0_CONTROLr_GPIO_0_PUPf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_PUPf_SET 21632 #define GPIO_0_CONTROLr_GPIO_0_OEBf_GET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OEBf_GET 21633 #define GPIO_0_CONTROLr_GPIO_0_OEBf_SET BCMI_HURACAN_GPIO_0_CONTROLr_GPIO_0_OEBf_SET 21634 #define READ_GPIO_0_CONTROLr BCMI_HURACAN_READ_GPIO_0_CONTROLr 21635 #define WRITE_GPIO_0_CONTROLr BCMI_HURACAN_WRITE_GPIO_0_CONTROLr 21636 #define MODIFY_GPIO_0_CONTROLr BCMI_HURACAN_MODIFY_GPIO_0_CONTROLr 21637 21638 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21639 /******************************************************************************* 21640 * End of 'BCMI_HURACAN_GPIO_0_CONTROLr' 21641 */ 21642 21643 21644 21645 21646 /******************************************************************************* 21647 * CHIP: BCMI_HURACAN 21648 * REGISTER: GPIO_0_STATUS 21649 * BLOCKS: PAD_CTRL_QUAD_D 21650 * REGADDR: 0xb079 21651 * DEVAD: 1 21652 * DESC: PAD gpio_0 status register 21653 * RESETVAL: 0x0 (0) 21654 * ACCESS: R/W 21655 * FIELDS: 21656 * GPIO_0_DIN_LH 21657 * GPIO_0_DIN_LL 21658 * GPIO_0_DIN 21659 */ 21660 #define BCMI_HURACAN_GPIO_0_STATUSr (0x0001b079 | PHYMOD_REG_ACC_RAW) 21661 21662 #define BCMI_HURACAN_GPIO_0_STATUSr_SIZE 4 21663 21664 /* 21665 * This structure should be used to declare and program GPIO_0_STATUS. 21666 */ 21667 typedef union BCMI_HURACAN_GPIO_0_STATUSr_s { 21668 uint32_t v[1]; 21669 uint32_t gpio_0_status[1]; 21670 uint32_t _gpio_0_status; 21671 } BCMI_HURACAN_GPIO_0_STATUSr_t; 21672 21673 #define BCMI_HURACAN_GPIO_0_STATUSr_CLR(r) (r).gpio_0_status[0] = 0 21674 #define BCMI_HURACAN_GPIO_0_STATUSr_SET(r,d) (r).gpio_0_status[0] = d 21675 #define BCMI_HURACAN_GPIO_0_STATUSr_GET(r) (r).gpio_0_status[0] 21676 21677 /* 21678 * These macros can be used to access individual fields. 21679 */ 21680 #define BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DINf_GET(r) ((((r).gpio_0_status[0]) >> 2) & 0x1) 21681 #define BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DINf_SET(r,f) (r).gpio_0_status[0]=(((r).gpio_0_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21682 #define BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LLf_GET(r) ((((r).gpio_0_status[0]) >> 1) & 0x1) 21683 #define BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LLf_SET(r,f) (r).gpio_0_status[0]=(((r).gpio_0_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21684 #define BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LHf_GET(r) (((r).gpio_0_status[0]) & 0x1) 21685 #define BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LHf_SET(r,f) (r).gpio_0_status[0]=(((r).gpio_0_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21686 21687 /* 21688 * These macros can be used to access GPIO_0_STATUS. 21689 */ 21690 #define BCMI_HURACAN_READ_GPIO_0_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_GPIO_0_STATUSr,_r._gpio_0_status) 21691 #define BCMI_HURACAN_WRITE_GPIO_0_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_GPIO_0_STATUSr,_r._gpio_0_status) 21692 21693 /* 21694 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21695 * will be redefined without the chip prefix for easier programming. 21696 * If multiple chips will be programmed in the same source file, then you should 21697 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21698 * and refer to the fully qualified versions. 21699 */ 21700 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21701 21702 #define GPIO_0_STATUSr BCMI_HURACAN_GPIO_0_STATUSr 21703 #define GPIO_0_STATUSr_SIZE BCMI_HURACAN_GPIO_0_STATUSr_SIZE 21704 typedef BCMI_HURACAN_GPIO_0_STATUSr_t GPIO_0_STATUSr_t; 21705 #define GPIO_0_STATUSr_CLR BCMI_HURACAN_GPIO_0_STATUSr_CLR 21706 #define GPIO_0_STATUSr_SET BCMI_HURACAN_GPIO_0_STATUSr_SET 21707 #define GPIO_0_STATUSr_GET BCMI_HURACAN_GPIO_0_STATUSr_GET 21708 #define GPIO_0_STATUSr_GPIO_0_DINf_GET BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DINf_GET 21709 #define GPIO_0_STATUSr_GPIO_0_DINf_SET BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DINf_SET 21710 #define GPIO_0_STATUSr_GPIO_0_DIN_LLf_GET BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LLf_GET 21711 #define GPIO_0_STATUSr_GPIO_0_DIN_LLf_SET BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LLf_SET 21712 #define GPIO_0_STATUSr_GPIO_0_DIN_LHf_GET BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LHf_GET 21713 #define GPIO_0_STATUSr_GPIO_0_DIN_LHf_SET BCMI_HURACAN_GPIO_0_STATUSr_GPIO_0_DIN_LHf_SET 21714 #define READ_GPIO_0_STATUSr BCMI_HURACAN_READ_GPIO_0_STATUSr 21715 #define WRITE_GPIO_0_STATUSr BCMI_HURACAN_WRITE_GPIO_0_STATUSr 21716 #define MODIFY_GPIO_0_STATUSr BCMI_HURACAN_MODIFY_GPIO_0_STATUSr 21717 21718 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21719 /******************************************************************************* 21720 * End of 'BCMI_HURACAN_GPIO_0_STATUSr' 21721 */ 21722 21723 21724 21725 21726 /******************************************************************************* 21727 * CHIP: BCMI_HURACAN 21728 * REGISTER: GPIO_1_CONTROL 21729 * BLOCKS: PAD_CTRL_QUAD_D 21730 * REGADDR: 0xb07a 21731 * DEVAD: 1 21732 * DESC: PAD gpio_1 control register 21733 * RESETVAL: 0x0 (0) 21734 * ACCESS: R/W 21735 * FIELDS: 21736 * GPIO_1_OEB 21737 * GPIO_1_PUP 21738 * GPIO_1_PDN 21739 * GPIO_1_IND 21740 * GPIO_1_SEL0 21741 * GPIO_1_SEL1 21742 * GPIO_1_SEL2 21743 * GPIO_1_IBOF 21744 * GPIO_1_INVERT_EN 21745 * GPIO_1_OUT_FRCVAL 21746 * GPIO_1_DGLH_CNT 21747 */ 21748 #define BCMI_HURACAN_GPIO_1_CONTROLr (0x0001b07a | PHYMOD_REG_ACC_RAW) 21749 21750 #define BCMI_HURACAN_GPIO_1_CONTROLr_SIZE 4 21751 21752 /* 21753 * This structure should be used to declare and program GPIO_1_CONTROL. 21754 */ 21755 typedef union BCMI_HURACAN_GPIO_1_CONTROLr_s { 21756 uint32_t v[1]; 21757 uint32_t gpio_1_control[1]; 21758 uint32_t _gpio_1_control; 21759 } BCMI_HURACAN_GPIO_1_CONTROLr_t; 21760 21761 #define BCMI_HURACAN_GPIO_1_CONTROLr_CLR(r) (r).gpio_1_control[0] = 0 21762 #define BCMI_HURACAN_GPIO_1_CONTROLr_SET(r,d) (r).gpio_1_control[0] = d 21763 #define BCMI_HURACAN_GPIO_1_CONTROLr_GET(r) (r).gpio_1_control[0] 21764 21765 /* 21766 * These macros can be used to access individual fields. 21767 */ 21768 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_DGLH_CNTf_GET(r) ((((r).gpio_1_control[0]) >> 12) & 0xf) 21769 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_DGLH_CNTf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 21770 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OUT_FRCVALf_GET(r) ((((r).gpio_1_control[0]) >> 11) & 0x1) 21771 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OUT_FRCVALf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 11)) | ((((uint32_t)f) & 0x1) << 11)) | (1 << (16 + 11)) 21772 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INVERT_ENf_GET(r) ((((r).gpio_1_control[0]) >> 10) & 0x1) 21773 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INVERT_ENf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 10)) | ((((uint32_t)f) & 0x1) << 10)) | (1 << (16 + 10)) 21774 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_IBOFf_GET(r) ((((r).gpio_1_control[0]) >> 9) & 0x1) 21775 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_IBOFf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 21776 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL2f_GET(r) ((((r).gpio_1_control[0]) >> 7) & 0x1) 21777 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL2f_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 7)) | ((((uint32_t)f) & 0x1) << 7)) | (1 << (16 + 7)) 21778 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL1f_GET(r) ((((r).gpio_1_control[0]) >> 6) & 0x1) 21779 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL1f_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 6)) | ((((uint32_t)f) & 0x1) << 6)) | (1 << (16 + 6)) 21780 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL0f_GET(r) ((((r).gpio_1_control[0]) >> 5) & 0x1) 21781 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL0f_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 5)) | ((((uint32_t)f) & 0x1) << 5)) | (1 << (16 + 5)) 21782 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INDf_GET(r) ((((r).gpio_1_control[0]) >> 4) & 0x1) 21783 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INDf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 21784 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PDNf_GET(r) ((((r).gpio_1_control[0]) >> 2) & 0x1) 21785 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PDNf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21786 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PUPf_GET(r) ((((r).gpio_1_control[0]) >> 1) & 0x1) 21787 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PUPf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21788 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OEBf_GET(r) (((r).gpio_1_control[0]) & 0x1) 21789 #define BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OEBf_SET(r,f) (r).gpio_1_control[0]=(((r).gpio_1_control[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21790 21791 /* 21792 * These macros can be used to access GPIO_1_CONTROL. 21793 */ 21794 #define BCMI_HURACAN_READ_GPIO_1_CONTROLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_GPIO_1_CONTROLr,_r._gpio_1_control) 21795 #define BCMI_HURACAN_WRITE_GPIO_1_CONTROLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_GPIO_1_CONTROLr,_r._gpio_1_control) 21796 21797 /* 21798 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21799 * will be redefined without the chip prefix for easier programming. 21800 * If multiple chips will be programmed in the same source file, then you should 21801 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21802 * and refer to the fully qualified versions. 21803 */ 21804 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21805 21806 #define GPIO_1_CONTROLr BCMI_HURACAN_GPIO_1_CONTROLr 21807 #define GPIO_1_CONTROLr_SIZE BCMI_HURACAN_GPIO_1_CONTROLr_SIZE 21808 typedef BCMI_HURACAN_GPIO_1_CONTROLr_t GPIO_1_CONTROLr_t; 21809 #define GPIO_1_CONTROLr_CLR BCMI_HURACAN_GPIO_1_CONTROLr_CLR 21810 #define GPIO_1_CONTROLr_SET BCMI_HURACAN_GPIO_1_CONTROLr_SET 21811 #define GPIO_1_CONTROLr_GET BCMI_HURACAN_GPIO_1_CONTROLr_GET 21812 #define GPIO_1_CONTROLr_GPIO_1_DGLH_CNTf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_DGLH_CNTf_GET 21813 #define GPIO_1_CONTROLr_GPIO_1_DGLH_CNTf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_DGLH_CNTf_SET 21814 #define GPIO_1_CONTROLr_GPIO_1_OUT_FRCVALf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OUT_FRCVALf_GET 21815 #define GPIO_1_CONTROLr_GPIO_1_OUT_FRCVALf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OUT_FRCVALf_SET 21816 #define GPIO_1_CONTROLr_GPIO_1_INVERT_ENf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INVERT_ENf_GET 21817 #define GPIO_1_CONTROLr_GPIO_1_INVERT_ENf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INVERT_ENf_SET 21818 #define GPIO_1_CONTROLr_GPIO_1_IBOFf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_IBOFf_GET 21819 #define GPIO_1_CONTROLr_GPIO_1_IBOFf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_IBOFf_SET 21820 #define GPIO_1_CONTROLr_GPIO_1_SEL2f_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL2f_GET 21821 #define GPIO_1_CONTROLr_GPIO_1_SEL2f_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL2f_SET 21822 #define GPIO_1_CONTROLr_GPIO_1_SEL1f_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL1f_GET 21823 #define GPIO_1_CONTROLr_GPIO_1_SEL1f_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL1f_SET 21824 #define GPIO_1_CONTROLr_GPIO_1_SEL0f_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL0f_GET 21825 #define GPIO_1_CONTROLr_GPIO_1_SEL0f_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_SEL0f_SET 21826 #define GPIO_1_CONTROLr_GPIO_1_INDf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INDf_GET 21827 #define GPIO_1_CONTROLr_GPIO_1_INDf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_INDf_SET 21828 #define GPIO_1_CONTROLr_GPIO_1_PDNf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PDNf_GET 21829 #define GPIO_1_CONTROLr_GPIO_1_PDNf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PDNf_SET 21830 #define GPIO_1_CONTROLr_GPIO_1_PUPf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PUPf_GET 21831 #define GPIO_1_CONTROLr_GPIO_1_PUPf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_PUPf_SET 21832 #define GPIO_1_CONTROLr_GPIO_1_OEBf_GET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OEBf_GET 21833 #define GPIO_1_CONTROLr_GPIO_1_OEBf_SET BCMI_HURACAN_GPIO_1_CONTROLr_GPIO_1_OEBf_SET 21834 #define READ_GPIO_1_CONTROLr BCMI_HURACAN_READ_GPIO_1_CONTROLr 21835 #define WRITE_GPIO_1_CONTROLr BCMI_HURACAN_WRITE_GPIO_1_CONTROLr 21836 #define MODIFY_GPIO_1_CONTROLr BCMI_HURACAN_MODIFY_GPIO_1_CONTROLr 21837 21838 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21839 /******************************************************************************* 21840 * End of 'BCMI_HURACAN_GPIO_1_CONTROLr' 21841 */ 21842 21843 21844 21845 21846 /******************************************************************************* 21847 * CHIP: BCMI_HURACAN 21848 * REGISTER: GPIO_1_STATUS 21849 * BLOCKS: PAD_CTRL_QUAD_D 21850 * REGADDR: 0xb07b 21851 * DEVAD: 1 21852 * DESC: PAD gpio_1 status register 21853 * RESETVAL: 0x0 (0) 21854 * ACCESS: R/W 21855 * FIELDS: 21856 * GPIO_1_DIN_LH 21857 * GPIO_1_DIN_LL 21858 * GPIO_1_DIN 21859 */ 21860 #define BCMI_HURACAN_GPIO_1_STATUSr (0x0001b07b | PHYMOD_REG_ACC_RAW) 21861 21862 #define BCMI_HURACAN_GPIO_1_STATUSr_SIZE 4 21863 21864 /* 21865 * This structure should be used to declare and program GPIO_1_STATUS. 21866 */ 21867 typedef union BCMI_HURACAN_GPIO_1_STATUSr_s { 21868 uint32_t v[1]; 21869 uint32_t gpio_1_status[1]; 21870 uint32_t _gpio_1_status; 21871 } BCMI_HURACAN_GPIO_1_STATUSr_t; 21872 21873 #define BCMI_HURACAN_GPIO_1_STATUSr_CLR(r) (r).gpio_1_status[0] = 0 21874 #define BCMI_HURACAN_GPIO_1_STATUSr_SET(r,d) (r).gpio_1_status[0] = d 21875 #define BCMI_HURACAN_GPIO_1_STATUSr_GET(r) (r).gpio_1_status[0] 21876 21877 /* 21878 * These macros can be used to access individual fields. 21879 */ 21880 #define BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DINf_GET(r) ((((r).gpio_1_status[0]) >> 2) & 0x1) 21881 #define BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DINf_SET(r,f) (r).gpio_1_status[0]=(((r).gpio_1_status[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 21882 #define BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LLf_GET(r) ((((r).gpio_1_status[0]) >> 1) & 0x1) 21883 #define BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LLf_SET(r,f) (r).gpio_1_status[0]=(((r).gpio_1_status[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 21884 #define BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LHf_GET(r) (((r).gpio_1_status[0]) & 0x1) 21885 #define BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LHf_SET(r,f) (r).gpio_1_status[0]=(((r).gpio_1_status[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 21886 21887 /* 21888 * These macros can be used to access GPIO_1_STATUS. 21889 */ 21890 #define BCMI_HURACAN_READ_GPIO_1_STATUSr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_GPIO_1_STATUSr,_r._gpio_1_status) 21891 #define BCMI_HURACAN_WRITE_GPIO_1_STATUSr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_GPIO_1_STATUSr,_r._gpio_1_status) 21892 21893 /* 21894 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21895 * will be redefined without the chip prefix for easier programming. 21896 * If multiple chips will be programmed in the same source file, then you should 21897 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21898 * and refer to the fully qualified versions. 21899 */ 21900 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21901 21902 #define GPIO_1_STATUSr BCMI_HURACAN_GPIO_1_STATUSr 21903 #define GPIO_1_STATUSr_SIZE BCMI_HURACAN_GPIO_1_STATUSr_SIZE 21904 typedef BCMI_HURACAN_GPIO_1_STATUSr_t GPIO_1_STATUSr_t; 21905 #define GPIO_1_STATUSr_CLR BCMI_HURACAN_GPIO_1_STATUSr_CLR 21906 #define GPIO_1_STATUSr_SET BCMI_HURACAN_GPIO_1_STATUSr_SET 21907 #define GPIO_1_STATUSr_GET BCMI_HURACAN_GPIO_1_STATUSr_GET 21908 #define GPIO_1_STATUSr_GPIO_1_DINf_GET BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DINf_GET 21909 #define GPIO_1_STATUSr_GPIO_1_DINf_SET BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DINf_SET 21910 #define GPIO_1_STATUSr_GPIO_1_DIN_LLf_GET BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LLf_GET 21911 #define GPIO_1_STATUSr_GPIO_1_DIN_LLf_SET BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LLf_SET 21912 #define GPIO_1_STATUSr_GPIO_1_DIN_LHf_GET BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LHf_GET 21913 #define GPIO_1_STATUSr_GPIO_1_DIN_LHf_SET BCMI_HURACAN_GPIO_1_STATUSr_GPIO_1_DIN_LHf_SET 21914 #define READ_GPIO_1_STATUSr BCMI_HURACAN_READ_GPIO_1_STATUSr 21915 #define WRITE_GPIO_1_STATUSr BCMI_HURACAN_WRITE_GPIO_1_STATUSr 21916 #define MODIFY_GPIO_1_STATUSr BCMI_HURACAN_MODIFY_GPIO_1_STATUSr 21917 21918 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 21919 /******************************************************************************* 21920 * End of 'BCMI_HURACAN_GPIO_1_STATUSr' 21921 */ 21922 21923 21924 21925 21926 /******************************************************************************* 21927 * CHIP: BCMI_HURACAN 21928 * REGISTER: BG_MAP0TO3_CTRL 21929 * BLOCKS: CTRL_QUAD_D 21930 * REGADDR: 0xb080 21931 * DEVAD: 1 21932 * DESC: Rescal to BG control map, value 0 to 3 21933 * RESETVAL: 0x0 (0) 21934 * ACCESS: R/W 21935 * FIELDS: 21936 * RES2BG0 21937 * RES2BG1 21938 * RES2BG2 21939 * RES2BG3 21940 */ 21941 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr (0x0001b080 | PHYMOD_REG_ACC_RAW) 21942 21943 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_SIZE 4 21944 21945 /* 21946 * This structure should be used to declare and program BG_MAP0TO3_CTRL. 21947 */ 21948 typedef union BCMI_HURACAN_BG_MAP0TO3_CTRLr_s { 21949 uint32_t v[1]; 21950 uint32_t bg_map0to3_ctrl[1]; 21951 uint32_t _bg_map0to3_ctrl; 21952 } BCMI_HURACAN_BG_MAP0TO3_CTRLr_t; 21953 21954 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_CLR(r) (r).bg_map0to3_ctrl[0] = 0 21955 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_SET(r,d) (r).bg_map0to3_ctrl[0] = d 21956 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_GET(r) (r).bg_map0to3_ctrl[0] 21957 21958 /* 21959 * These macros can be used to access individual fields. 21960 */ 21961 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG3f_GET(r) ((((r).bg_map0to3_ctrl[0]) >> 12) & 0xf) 21962 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG3f_SET(r,f) (r).bg_map0to3_ctrl[0]=(((r).bg_map0to3_ctrl[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 21963 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG2f_GET(r) ((((r).bg_map0to3_ctrl[0]) >> 8) & 0xf) 21964 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG2f_SET(r,f) (r).bg_map0to3_ctrl[0]=(((r).bg_map0to3_ctrl[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 21965 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG1f_GET(r) ((((r).bg_map0to3_ctrl[0]) >> 4) & 0xf) 21966 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG1f_SET(r,f) (r).bg_map0to3_ctrl[0]=(((r).bg_map0to3_ctrl[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 21967 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG0f_GET(r) (((r).bg_map0to3_ctrl[0]) & 0xf) 21968 #define BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG0f_SET(r,f) (r).bg_map0to3_ctrl[0]=(((r).bg_map0to3_ctrl[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 21969 21970 /* 21971 * These macros can be used to access BG_MAP0TO3_CTRL. 21972 */ 21973 #define BCMI_HURACAN_READ_BG_MAP0TO3_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_MAP0TO3_CTRLr,_r._bg_map0to3_ctrl) 21974 #define BCMI_HURACAN_WRITE_BG_MAP0TO3_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_MAP0TO3_CTRLr,_r._bg_map0to3_ctrl) 21975 21976 /* 21977 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 21978 * will be redefined without the chip prefix for easier programming. 21979 * If multiple chips will be programmed in the same source file, then you should 21980 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 21981 * and refer to the fully qualified versions. 21982 */ 21983 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 21984 21985 #define BG_MAP0TO3_CTRLr BCMI_HURACAN_BG_MAP0TO3_CTRLr 21986 #define BG_MAP0TO3_CTRLr_SIZE BCMI_HURACAN_BG_MAP0TO3_CTRLr_SIZE 21987 typedef BCMI_HURACAN_BG_MAP0TO3_CTRLr_t BG_MAP0TO3_CTRLr_t; 21988 #define BG_MAP0TO3_CTRLr_CLR BCMI_HURACAN_BG_MAP0TO3_CTRLr_CLR 21989 #define BG_MAP0TO3_CTRLr_SET BCMI_HURACAN_BG_MAP0TO3_CTRLr_SET 21990 #define BG_MAP0TO3_CTRLr_GET BCMI_HURACAN_BG_MAP0TO3_CTRLr_GET 21991 #define BG_MAP0TO3_CTRLr_RES2BG3f_GET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG3f_GET 21992 #define BG_MAP0TO3_CTRLr_RES2BG3f_SET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG3f_SET 21993 #define BG_MAP0TO3_CTRLr_RES2BG2f_GET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG2f_GET 21994 #define BG_MAP0TO3_CTRLr_RES2BG2f_SET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG2f_SET 21995 #define BG_MAP0TO3_CTRLr_RES2BG1f_GET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG1f_GET 21996 #define BG_MAP0TO3_CTRLr_RES2BG1f_SET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG1f_SET 21997 #define BG_MAP0TO3_CTRLr_RES2BG0f_GET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG0f_GET 21998 #define BG_MAP0TO3_CTRLr_RES2BG0f_SET BCMI_HURACAN_BG_MAP0TO3_CTRLr_RES2BG0f_SET 21999 #define READ_BG_MAP0TO3_CTRLr BCMI_HURACAN_READ_BG_MAP0TO3_CTRLr 22000 #define WRITE_BG_MAP0TO3_CTRLr BCMI_HURACAN_WRITE_BG_MAP0TO3_CTRLr 22001 #define MODIFY_BG_MAP0TO3_CTRLr BCMI_HURACAN_MODIFY_BG_MAP0TO3_CTRLr 22002 22003 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22004 /******************************************************************************* 22005 * End of 'BCMI_HURACAN_BG_MAP0TO3_CTRLr' 22006 */ 22007 22008 22009 22010 22011 /******************************************************************************* 22012 * CHIP: BCMI_HURACAN 22013 * REGISTER: BG_MAP4TO7_CTRL 22014 * BLOCKS: CTRL_QUAD_D 22015 * REGADDR: 0xb081 22016 * DEVAD: 1 22017 * DESC: Rescal to BG control map, value 4 to 7 22018 * RESETVAL: 0x0 (0) 22019 * ACCESS: R/W 22020 * FIELDS: 22021 * RES2BG4 22022 * RES2BG5 22023 * RES2BG6 22024 * RES2BG7 22025 */ 22026 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr (0x0001b081 | PHYMOD_REG_ACC_RAW) 22027 22028 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_SIZE 4 22029 22030 /* 22031 * This structure should be used to declare and program BG_MAP4TO7_CTRL. 22032 */ 22033 typedef union BCMI_HURACAN_BG_MAP4TO7_CTRLr_s { 22034 uint32_t v[1]; 22035 uint32_t bg_map4to7_ctrl[1]; 22036 uint32_t _bg_map4to7_ctrl; 22037 } BCMI_HURACAN_BG_MAP4TO7_CTRLr_t; 22038 22039 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_CLR(r) (r).bg_map4to7_ctrl[0] = 0 22040 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_SET(r,d) (r).bg_map4to7_ctrl[0] = d 22041 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_GET(r) (r).bg_map4to7_ctrl[0] 22042 22043 /* 22044 * These macros can be used to access individual fields. 22045 */ 22046 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG7f_GET(r) ((((r).bg_map4to7_ctrl[0]) >> 12) & 0xf) 22047 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG7f_SET(r,f) (r).bg_map4to7_ctrl[0]=(((r).bg_map4to7_ctrl[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 22048 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG6f_GET(r) ((((r).bg_map4to7_ctrl[0]) >> 8) & 0xf) 22049 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG6f_SET(r,f) (r).bg_map4to7_ctrl[0]=(((r).bg_map4to7_ctrl[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 22050 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG5f_GET(r) ((((r).bg_map4to7_ctrl[0]) >> 4) & 0xf) 22051 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG5f_SET(r,f) (r).bg_map4to7_ctrl[0]=(((r).bg_map4to7_ctrl[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22052 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG4f_GET(r) (((r).bg_map4to7_ctrl[0]) & 0xf) 22053 #define BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG4f_SET(r,f) (r).bg_map4to7_ctrl[0]=(((r).bg_map4to7_ctrl[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22054 22055 /* 22056 * These macros can be used to access BG_MAP4TO7_CTRL. 22057 */ 22058 #define BCMI_HURACAN_READ_BG_MAP4TO7_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_MAP4TO7_CTRLr,_r._bg_map4to7_ctrl) 22059 #define BCMI_HURACAN_WRITE_BG_MAP4TO7_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_MAP4TO7_CTRLr,_r._bg_map4to7_ctrl) 22060 22061 /* 22062 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22063 * will be redefined without the chip prefix for easier programming. 22064 * If multiple chips will be programmed in the same source file, then you should 22065 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22066 * and refer to the fully qualified versions. 22067 */ 22068 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22069 22070 #define BG_MAP4TO7_CTRLr BCMI_HURACAN_BG_MAP4TO7_CTRLr 22071 #define BG_MAP4TO7_CTRLr_SIZE BCMI_HURACAN_BG_MAP4TO7_CTRLr_SIZE 22072 typedef BCMI_HURACAN_BG_MAP4TO7_CTRLr_t BG_MAP4TO7_CTRLr_t; 22073 #define BG_MAP4TO7_CTRLr_CLR BCMI_HURACAN_BG_MAP4TO7_CTRLr_CLR 22074 #define BG_MAP4TO7_CTRLr_SET BCMI_HURACAN_BG_MAP4TO7_CTRLr_SET 22075 #define BG_MAP4TO7_CTRLr_GET BCMI_HURACAN_BG_MAP4TO7_CTRLr_GET 22076 #define BG_MAP4TO7_CTRLr_RES2BG7f_GET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG7f_GET 22077 #define BG_MAP4TO7_CTRLr_RES2BG7f_SET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG7f_SET 22078 #define BG_MAP4TO7_CTRLr_RES2BG6f_GET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG6f_GET 22079 #define BG_MAP4TO7_CTRLr_RES2BG6f_SET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG6f_SET 22080 #define BG_MAP4TO7_CTRLr_RES2BG5f_GET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG5f_GET 22081 #define BG_MAP4TO7_CTRLr_RES2BG5f_SET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG5f_SET 22082 #define BG_MAP4TO7_CTRLr_RES2BG4f_GET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG4f_GET 22083 #define BG_MAP4TO7_CTRLr_RES2BG4f_SET BCMI_HURACAN_BG_MAP4TO7_CTRLr_RES2BG4f_SET 22084 #define READ_BG_MAP4TO7_CTRLr BCMI_HURACAN_READ_BG_MAP4TO7_CTRLr 22085 #define WRITE_BG_MAP4TO7_CTRLr BCMI_HURACAN_WRITE_BG_MAP4TO7_CTRLr 22086 #define MODIFY_BG_MAP4TO7_CTRLr BCMI_HURACAN_MODIFY_BG_MAP4TO7_CTRLr 22087 22088 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22089 /******************************************************************************* 22090 * End of 'BCMI_HURACAN_BG_MAP4TO7_CTRLr' 22091 */ 22092 22093 22094 22095 22096 /******************************************************************************* 22097 * CHIP: BCMI_HURACAN 22098 * REGISTER: BG_MAP8TOB_CTRL 22099 * BLOCKS: CTRL_QUAD_D 22100 * REGADDR: 0xb082 22101 * DEVAD: 1 22102 * DESC: Rescal to BG control map, value 8 to B 22103 * RESETVAL: 0x0 (0) 22104 * ACCESS: R/W 22105 * FIELDS: 22106 * RES2BG8 22107 * RES2BG9 22108 * RES2BGA 22109 * RES2BGB 22110 */ 22111 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr (0x0001b082 | PHYMOD_REG_ACC_RAW) 22112 22113 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_SIZE 4 22114 22115 /* 22116 * This structure should be used to declare and program BG_MAP8TOB_CTRL. 22117 */ 22118 typedef union BCMI_HURACAN_BG_MAP8TOB_CTRLr_s { 22119 uint32_t v[1]; 22120 uint32_t bg_map8tob_ctrl[1]; 22121 uint32_t _bg_map8tob_ctrl; 22122 } BCMI_HURACAN_BG_MAP8TOB_CTRLr_t; 22123 22124 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_CLR(r) (r).bg_map8tob_ctrl[0] = 0 22125 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_SET(r,d) (r).bg_map8tob_ctrl[0] = d 22126 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_GET(r) (r).bg_map8tob_ctrl[0] 22127 22128 /* 22129 * These macros can be used to access individual fields. 22130 */ 22131 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGBf_GET(r) ((((r).bg_map8tob_ctrl[0]) >> 12) & 0xf) 22132 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGBf_SET(r,f) (r).bg_map8tob_ctrl[0]=(((r).bg_map8tob_ctrl[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 22133 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGAf_GET(r) ((((r).bg_map8tob_ctrl[0]) >> 8) & 0xf) 22134 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGAf_SET(r,f) (r).bg_map8tob_ctrl[0]=(((r).bg_map8tob_ctrl[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 22135 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG9f_GET(r) ((((r).bg_map8tob_ctrl[0]) >> 4) & 0xf) 22136 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG9f_SET(r,f) (r).bg_map8tob_ctrl[0]=(((r).bg_map8tob_ctrl[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22137 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG8f_GET(r) (((r).bg_map8tob_ctrl[0]) & 0xf) 22138 #define BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG8f_SET(r,f) (r).bg_map8tob_ctrl[0]=(((r).bg_map8tob_ctrl[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22139 22140 /* 22141 * These macros can be used to access BG_MAP8TOB_CTRL. 22142 */ 22143 #define BCMI_HURACAN_READ_BG_MAP8TOB_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_MAP8TOB_CTRLr,_r._bg_map8tob_ctrl) 22144 #define BCMI_HURACAN_WRITE_BG_MAP8TOB_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_MAP8TOB_CTRLr,_r._bg_map8tob_ctrl) 22145 22146 /* 22147 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22148 * will be redefined without the chip prefix for easier programming. 22149 * If multiple chips will be programmed in the same source file, then you should 22150 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22151 * and refer to the fully qualified versions. 22152 */ 22153 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22154 22155 #define BG_MAP8TOB_CTRLr BCMI_HURACAN_BG_MAP8TOB_CTRLr 22156 #define BG_MAP8TOB_CTRLr_SIZE BCMI_HURACAN_BG_MAP8TOB_CTRLr_SIZE 22157 typedef BCMI_HURACAN_BG_MAP8TOB_CTRLr_t BG_MAP8TOB_CTRLr_t; 22158 #define BG_MAP8TOB_CTRLr_CLR BCMI_HURACAN_BG_MAP8TOB_CTRLr_CLR 22159 #define BG_MAP8TOB_CTRLr_SET BCMI_HURACAN_BG_MAP8TOB_CTRLr_SET 22160 #define BG_MAP8TOB_CTRLr_GET BCMI_HURACAN_BG_MAP8TOB_CTRLr_GET 22161 #define BG_MAP8TOB_CTRLr_RES2BGBf_GET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGBf_GET 22162 #define BG_MAP8TOB_CTRLr_RES2BGBf_SET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGBf_SET 22163 #define BG_MAP8TOB_CTRLr_RES2BGAf_GET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGAf_GET 22164 #define BG_MAP8TOB_CTRLr_RES2BGAf_SET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BGAf_SET 22165 #define BG_MAP8TOB_CTRLr_RES2BG9f_GET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG9f_GET 22166 #define BG_MAP8TOB_CTRLr_RES2BG9f_SET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG9f_SET 22167 #define BG_MAP8TOB_CTRLr_RES2BG8f_GET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG8f_GET 22168 #define BG_MAP8TOB_CTRLr_RES2BG8f_SET BCMI_HURACAN_BG_MAP8TOB_CTRLr_RES2BG8f_SET 22169 #define READ_BG_MAP8TOB_CTRLr BCMI_HURACAN_READ_BG_MAP8TOB_CTRLr 22170 #define WRITE_BG_MAP8TOB_CTRLr BCMI_HURACAN_WRITE_BG_MAP8TOB_CTRLr 22171 #define MODIFY_BG_MAP8TOB_CTRLr BCMI_HURACAN_MODIFY_BG_MAP8TOB_CTRLr 22172 22173 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22174 /******************************************************************************* 22175 * End of 'BCMI_HURACAN_BG_MAP8TOB_CTRLr' 22176 */ 22177 22178 22179 22180 22181 /******************************************************************************* 22182 * CHIP: BCMI_HURACAN 22183 * REGISTER: BG_MAPCTOF_CTRL 22184 * BLOCKS: CTRL_QUAD_D 22185 * REGADDR: 0xb083 22186 * DEVAD: 1 22187 * DESC: Rescal to BG control map, value C to F 22188 * RESETVAL: 0x0 (0) 22189 * ACCESS: R/W 22190 * FIELDS: 22191 * RES2BGC 22192 * RES2BGD 22193 * RES2BGE 22194 * RES2BGF 22195 */ 22196 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr (0x0001b083 | PHYMOD_REG_ACC_RAW) 22197 22198 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_SIZE 4 22199 22200 /* 22201 * This structure should be used to declare and program BG_MAPCTOF_CTRL. 22202 */ 22203 typedef union BCMI_HURACAN_BG_MAPCTOF_CTRLr_s { 22204 uint32_t v[1]; 22205 uint32_t bg_mapctof_ctrl[1]; 22206 uint32_t _bg_mapctof_ctrl; 22207 } BCMI_HURACAN_BG_MAPCTOF_CTRLr_t; 22208 22209 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_CLR(r) (r).bg_mapctof_ctrl[0] = 0 22210 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_SET(r,d) (r).bg_mapctof_ctrl[0] = d 22211 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_GET(r) (r).bg_mapctof_ctrl[0] 22212 22213 /* 22214 * These macros can be used to access individual fields. 22215 */ 22216 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGFf_GET(r) ((((r).bg_mapctof_ctrl[0]) >> 12) & 0xf) 22217 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGFf_SET(r,f) (r).bg_mapctof_ctrl[0]=(((r).bg_mapctof_ctrl[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 22218 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGEf_GET(r) ((((r).bg_mapctof_ctrl[0]) >> 8) & 0xf) 22219 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGEf_SET(r,f) (r).bg_mapctof_ctrl[0]=(((r).bg_mapctof_ctrl[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 22220 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGDf_GET(r) ((((r).bg_mapctof_ctrl[0]) >> 4) & 0xf) 22221 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGDf_SET(r,f) (r).bg_mapctof_ctrl[0]=(((r).bg_mapctof_ctrl[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22222 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGCf_GET(r) (((r).bg_mapctof_ctrl[0]) & 0xf) 22223 #define BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGCf_SET(r,f) (r).bg_mapctof_ctrl[0]=(((r).bg_mapctof_ctrl[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22224 22225 /* 22226 * These macros can be used to access BG_MAPCTOF_CTRL. 22227 */ 22228 #define BCMI_HURACAN_READ_BG_MAPCTOF_CTRLr(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_MAPCTOF_CTRLr,_r._bg_mapctof_ctrl) 22229 #define BCMI_HURACAN_WRITE_BG_MAPCTOF_CTRLr(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_MAPCTOF_CTRLr,_r._bg_mapctof_ctrl) 22230 22231 /* 22232 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22233 * will be redefined without the chip prefix for easier programming. 22234 * If multiple chips will be programmed in the same source file, then you should 22235 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22236 * and refer to the fully qualified versions. 22237 */ 22238 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22239 22240 #define BG_MAPCTOF_CTRLr BCMI_HURACAN_BG_MAPCTOF_CTRLr 22241 #define BG_MAPCTOF_CTRLr_SIZE BCMI_HURACAN_BG_MAPCTOF_CTRLr_SIZE 22242 typedef BCMI_HURACAN_BG_MAPCTOF_CTRLr_t BG_MAPCTOF_CTRLr_t; 22243 #define BG_MAPCTOF_CTRLr_CLR BCMI_HURACAN_BG_MAPCTOF_CTRLr_CLR 22244 #define BG_MAPCTOF_CTRLr_SET BCMI_HURACAN_BG_MAPCTOF_CTRLr_SET 22245 #define BG_MAPCTOF_CTRLr_GET BCMI_HURACAN_BG_MAPCTOF_CTRLr_GET 22246 #define BG_MAPCTOF_CTRLr_RES2BGFf_GET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGFf_GET 22247 #define BG_MAPCTOF_CTRLr_RES2BGFf_SET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGFf_SET 22248 #define BG_MAPCTOF_CTRLr_RES2BGEf_GET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGEf_GET 22249 #define BG_MAPCTOF_CTRLr_RES2BGEf_SET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGEf_SET 22250 #define BG_MAPCTOF_CTRLr_RES2BGDf_GET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGDf_GET 22251 #define BG_MAPCTOF_CTRLr_RES2BGDf_SET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGDf_SET 22252 #define BG_MAPCTOF_CTRLr_RES2BGCf_GET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGCf_GET 22253 #define BG_MAPCTOF_CTRLr_RES2BGCf_SET BCMI_HURACAN_BG_MAPCTOF_CTRLr_RES2BGCf_SET 22254 #define READ_BG_MAPCTOF_CTRLr BCMI_HURACAN_READ_BG_MAPCTOF_CTRLr 22255 #define WRITE_BG_MAPCTOF_CTRLr BCMI_HURACAN_WRITE_BG_MAPCTOF_CTRLr 22256 #define MODIFY_BG_MAPCTOF_CTRLr BCMI_HURACAN_MODIFY_BG_MAPCTOF_CTRLr 22257 22258 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22259 /******************************************************************************* 22260 * End of 'BCMI_HURACAN_BG_MAPCTOF_CTRLr' 22261 */ 22262 22263 22264 22265 22266 /******************************************************************************* 22267 * CHIP: BCMI_HURACAN 22268 * REGISTER: BG_CTRL15 22269 * BLOCKS: CTRL_QUAD_D 22270 * REGADDR: 0xb084 22271 * DEVAD: 1 22272 * DESC: control registers for AMS BG control bus 22273 * RESETVAL: 0x0 (0) 22274 * ACCESS: R/W 22275 * FIELDS: 22276 * BG_RESERVED_FOR_255_TO_240 22277 */ 22278 #define BCMI_HURACAN_BG_CTRL15r (0x0001b084 | PHYMOD_REG_ACC_RAW) 22279 22280 #define BCMI_HURACAN_BG_CTRL15r_SIZE 4 22281 22282 /* 22283 * This structure should be used to declare and program BG_CTRL15. 22284 */ 22285 typedef union BCMI_HURACAN_BG_CTRL15r_s { 22286 uint32_t v[1]; 22287 uint32_t bg_ctrl15[1]; 22288 uint32_t _bg_ctrl15; 22289 } BCMI_HURACAN_BG_CTRL15r_t; 22290 22291 #define BCMI_HURACAN_BG_CTRL15r_CLR(r) (r).bg_ctrl15[0] = 0 22292 #define BCMI_HURACAN_BG_CTRL15r_SET(r,d) (r).bg_ctrl15[0] = d 22293 #define BCMI_HURACAN_BG_CTRL15r_GET(r) (r).bg_ctrl15[0] 22294 22295 /* 22296 * These macros can be used to access individual fields. 22297 */ 22298 #define BCMI_HURACAN_BG_CTRL15r_BG_RESERVED_FOR_255_TO_240f_GET(r) (((r).bg_ctrl15[0]) & 0xffff) 22299 #define BCMI_HURACAN_BG_CTRL15r_BG_RESERVED_FOR_255_TO_240f_SET(r,f) (r).bg_ctrl15[0]=(((r).bg_ctrl15[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 22300 22301 /* 22302 * These macros can be used to access BG_CTRL15. 22303 */ 22304 #define BCMI_HURACAN_READ_BG_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL15r,_r._bg_ctrl15) 22305 #define BCMI_HURACAN_WRITE_BG_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL15r,_r._bg_ctrl15) 22306 22307 /* 22308 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22309 * will be redefined without the chip prefix for easier programming. 22310 * If multiple chips will be programmed in the same source file, then you should 22311 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22312 * and refer to the fully qualified versions. 22313 */ 22314 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22315 22316 #define BG_CTRL15r BCMI_HURACAN_BG_CTRL15r 22317 #define BG_CTRL15r_SIZE BCMI_HURACAN_BG_CTRL15r_SIZE 22318 typedef BCMI_HURACAN_BG_CTRL15r_t BG_CTRL15r_t; 22319 #define BG_CTRL15r_CLR BCMI_HURACAN_BG_CTRL15r_CLR 22320 #define BG_CTRL15r_SET BCMI_HURACAN_BG_CTRL15r_SET 22321 #define BG_CTRL15r_GET BCMI_HURACAN_BG_CTRL15r_GET 22322 #define BG_CTRL15r_BG_RESERVED_FOR_255_TO_240f_GET BCMI_HURACAN_BG_CTRL15r_BG_RESERVED_FOR_255_TO_240f_GET 22323 #define BG_CTRL15r_BG_RESERVED_FOR_255_TO_240f_SET BCMI_HURACAN_BG_CTRL15r_BG_RESERVED_FOR_255_TO_240f_SET 22324 #define READ_BG_CTRL15r BCMI_HURACAN_READ_BG_CTRL15r 22325 #define WRITE_BG_CTRL15r BCMI_HURACAN_WRITE_BG_CTRL15r 22326 #define MODIFY_BG_CTRL15r BCMI_HURACAN_MODIFY_BG_CTRL15r 22327 22328 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22329 /******************************************************************************* 22330 * End of 'BCMI_HURACAN_BG_CTRL15r' 22331 */ 22332 22333 22334 22335 22336 /******************************************************************************* 22337 * CHIP: BCMI_HURACAN 22338 * REGISTER: BG_CTRL16 22339 * BLOCKS: CTRL_QUAD_D 22340 * REGADDR: 0xb085 22341 * DEVAD: 1 22342 * DESC: control registers for AMS BG control bus 22343 * RESETVAL: 0x0 (0) 22344 * ACCESS: R/W 22345 * FIELDS: 22346 * PMIR_TEST 22347 * VBGP_IV 22348 * BSX2_EN 22349 * TEN 22350 */ 22351 #define BCMI_HURACAN_BG_CTRL16r (0x0001b085 | PHYMOD_REG_ACC_RAW) 22352 22353 #define BCMI_HURACAN_BG_CTRL16r_SIZE 4 22354 22355 /* 22356 * This structure should be used to declare and program BG_CTRL16. 22357 */ 22358 typedef union BCMI_HURACAN_BG_CTRL16r_s { 22359 uint32_t v[1]; 22360 uint32_t bg_ctrl16[1]; 22361 uint32_t _bg_ctrl16; 22362 } BCMI_HURACAN_BG_CTRL16r_t; 22363 22364 #define BCMI_HURACAN_BG_CTRL16r_CLR(r) (r).bg_ctrl16[0] = 0 22365 #define BCMI_HURACAN_BG_CTRL16r_SET(r,d) (r).bg_ctrl16[0] = d 22366 #define BCMI_HURACAN_BG_CTRL16r_GET(r) (r).bg_ctrl16[0] 22367 22368 /* 22369 * These macros can be used to access individual fields. 22370 */ 22371 #define BCMI_HURACAN_BG_CTRL16r_TENf_GET(r) ((((r).bg_ctrl16[0]) >> 8) & 0x3) 22372 #define BCMI_HURACAN_BG_CTRL16r_TENf_SET(r,f) (r).bg_ctrl16[0]=(((r).bg_ctrl16[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 22373 #define BCMI_HURACAN_BG_CTRL16r_BSX2_ENf_GET(r) ((((r).bg_ctrl16[0]) >> 4) & 0x3) 22374 #define BCMI_HURACAN_BG_CTRL16r_BSX2_ENf_SET(r,f) (r).bg_ctrl16[0]=(((r).bg_ctrl16[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 22375 #define BCMI_HURACAN_BG_CTRL16r_VBGP_IVf_GET(r) ((((r).bg_ctrl16[0]) >> 1) & 0x1) 22376 #define BCMI_HURACAN_BG_CTRL16r_VBGP_IVf_SET(r,f) (r).bg_ctrl16[0]=(((r).bg_ctrl16[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 22377 #define BCMI_HURACAN_BG_CTRL16r_PMIR_TESTf_GET(r) (((r).bg_ctrl16[0]) & 0x1) 22378 #define BCMI_HURACAN_BG_CTRL16r_PMIR_TESTf_SET(r,f) (r).bg_ctrl16[0]=(((r).bg_ctrl16[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 22379 22380 /* 22381 * These macros can be used to access BG_CTRL16. 22382 */ 22383 #define BCMI_HURACAN_READ_BG_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL16r,_r._bg_ctrl16) 22384 #define BCMI_HURACAN_WRITE_BG_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL16r,_r._bg_ctrl16) 22385 22386 /* 22387 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22388 * will be redefined without the chip prefix for easier programming. 22389 * If multiple chips will be programmed in the same source file, then you should 22390 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22391 * and refer to the fully qualified versions. 22392 */ 22393 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22394 22395 #define BG_CTRL16r BCMI_HURACAN_BG_CTRL16r 22396 #define BG_CTRL16r_SIZE BCMI_HURACAN_BG_CTRL16r_SIZE 22397 typedef BCMI_HURACAN_BG_CTRL16r_t BG_CTRL16r_t; 22398 #define BG_CTRL16r_CLR BCMI_HURACAN_BG_CTRL16r_CLR 22399 #define BG_CTRL16r_SET BCMI_HURACAN_BG_CTRL16r_SET 22400 #define BG_CTRL16r_GET BCMI_HURACAN_BG_CTRL16r_GET 22401 #define BG_CTRL16r_TENf_GET BCMI_HURACAN_BG_CTRL16r_TENf_GET 22402 #define BG_CTRL16r_TENf_SET BCMI_HURACAN_BG_CTRL16r_TENf_SET 22403 #define BG_CTRL16r_BSX2_ENf_GET BCMI_HURACAN_BG_CTRL16r_BSX2_ENf_GET 22404 #define BG_CTRL16r_BSX2_ENf_SET BCMI_HURACAN_BG_CTRL16r_BSX2_ENf_SET 22405 #define BG_CTRL16r_VBGP_IVf_GET BCMI_HURACAN_BG_CTRL16r_VBGP_IVf_GET 22406 #define BG_CTRL16r_VBGP_IVf_SET BCMI_HURACAN_BG_CTRL16r_VBGP_IVf_SET 22407 #define BG_CTRL16r_PMIR_TESTf_GET BCMI_HURACAN_BG_CTRL16r_PMIR_TESTf_GET 22408 #define BG_CTRL16r_PMIR_TESTf_SET BCMI_HURACAN_BG_CTRL16r_PMIR_TESTf_SET 22409 #define READ_BG_CTRL16r BCMI_HURACAN_READ_BG_CTRL16r 22410 #define WRITE_BG_CTRL16r BCMI_HURACAN_WRITE_BG_CTRL16r 22411 #define MODIFY_BG_CTRL16r BCMI_HURACAN_MODIFY_BG_CTRL16r 22412 22413 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22414 /******************************************************************************* 22415 * End of 'BCMI_HURACAN_BG_CTRL16r' 22416 */ 22417 22418 22419 22420 22421 /******************************************************************************* 22422 * CHIP: BCMI_HURACAN 22423 * REGISTER: BG_CTRL17 22424 * BLOCKS: CTRL_QUAD_D 22425 * REGADDR: 0xb086 22426 * DEVAD: 1 22427 * DESC: control registers for AMS BG control bus 22428 * RESETVAL: 0x0 (0) 22429 * ACCESS: R/W 22430 * FIELDS: 22431 * PTATADJ_BG_R 22432 * CTATADJ_BG_R 22433 */ 22434 #define BCMI_HURACAN_BG_CTRL17r (0x0001b086 | PHYMOD_REG_ACC_RAW) 22435 22436 #define BCMI_HURACAN_BG_CTRL17r_SIZE 4 22437 22438 /* 22439 * This structure should be used to declare and program BG_CTRL17. 22440 */ 22441 typedef union BCMI_HURACAN_BG_CTRL17r_s { 22442 uint32_t v[1]; 22443 uint32_t bg_ctrl17[1]; 22444 uint32_t _bg_ctrl17; 22445 } BCMI_HURACAN_BG_CTRL17r_t; 22446 22447 #define BCMI_HURACAN_BG_CTRL17r_CLR(r) (r).bg_ctrl17[0] = 0 22448 #define BCMI_HURACAN_BG_CTRL17r_SET(r,d) (r).bg_ctrl17[0] = d 22449 #define BCMI_HURACAN_BG_CTRL17r_GET(r) (r).bg_ctrl17[0] 22450 22451 /* 22452 * These macros can be used to access individual fields. 22453 */ 22454 #define BCMI_HURACAN_BG_CTRL17r_CTATADJ_BG_Rf_GET(r) ((((r).bg_ctrl17[0]) >> 4) & 0xf) 22455 #define BCMI_HURACAN_BG_CTRL17r_CTATADJ_BG_Rf_SET(r,f) (r).bg_ctrl17[0]=(((r).bg_ctrl17[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22456 #define BCMI_HURACAN_BG_CTRL17r_PTATADJ_BG_Rf_GET(r) (((r).bg_ctrl17[0]) & 0xf) 22457 #define BCMI_HURACAN_BG_CTRL17r_PTATADJ_BG_Rf_SET(r,f) (r).bg_ctrl17[0]=(((r).bg_ctrl17[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22458 22459 /* 22460 * These macros can be used to access BG_CTRL17. 22461 */ 22462 #define BCMI_HURACAN_READ_BG_CTRL17r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL17r,_r._bg_ctrl17) 22463 #define BCMI_HURACAN_WRITE_BG_CTRL17r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL17r,_r._bg_ctrl17) 22464 22465 /* 22466 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22467 * will be redefined without the chip prefix for easier programming. 22468 * If multiple chips will be programmed in the same source file, then you should 22469 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22470 * and refer to the fully qualified versions. 22471 */ 22472 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22473 22474 #define BG_CTRL17r BCMI_HURACAN_BG_CTRL17r 22475 #define BG_CTRL17r_SIZE BCMI_HURACAN_BG_CTRL17r_SIZE 22476 typedef BCMI_HURACAN_BG_CTRL17r_t BG_CTRL17r_t; 22477 #define BG_CTRL17r_CLR BCMI_HURACAN_BG_CTRL17r_CLR 22478 #define BG_CTRL17r_SET BCMI_HURACAN_BG_CTRL17r_SET 22479 #define BG_CTRL17r_GET BCMI_HURACAN_BG_CTRL17r_GET 22480 #define BG_CTRL17r_CTATADJ_BG_Rf_GET BCMI_HURACAN_BG_CTRL17r_CTATADJ_BG_Rf_GET 22481 #define BG_CTRL17r_CTATADJ_BG_Rf_SET BCMI_HURACAN_BG_CTRL17r_CTATADJ_BG_Rf_SET 22482 #define BG_CTRL17r_PTATADJ_BG_Rf_GET BCMI_HURACAN_BG_CTRL17r_PTATADJ_BG_Rf_GET 22483 #define BG_CTRL17r_PTATADJ_BG_Rf_SET BCMI_HURACAN_BG_CTRL17r_PTATADJ_BG_Rf_SET 22484 #define READ_BG_CTRL17r BCMI_HURACAN_READ_BG_CTRL17r 22485 #define WRITE_BG_CTRL17r BCMI_HURACAN_WRITE_BG_CTRL17r 22486 #define MODIFY_BG_CTRL17r BCMI_HURACAN_MODIFY_BG_CTRL17r 22487 22488 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22489 /******************************************************************************* 22490 * End of 'BCMI_HURACAN_BG_CTRL17r' 22491 */ 22492 22493 22494 22495 22496 /******************************************************************************* 22497 * CHIP: BCMI_HURACAN 22498 * REGISTER: BG_CTRL18 22499 * BLOCKS: CTRL_QUAD_D 22500 * REGADDR: 0xb087 22501 * DEVAD: 1 22502 * DESC: control registers for AMS BG control bus 22503 * RESETVAL: 0x0 (0) 22504 * ACCESS: R/W 22505 * FIELDS: 22506 * PTATADJ_PTAT_RCAL 22507 * CTATADJ_PTAT_RCAL 22508 */ 22509 #define BCMI_HURACAN_BG_CTRL18r (0x0001b087 | PHYMOD_REG_ACC_RAW) 22510 22511 #define BCMI_HURACAN_BG_CTRL18r_SIZE 4 22512 22513 /* 22514 * This structure should be used to declare and program BG_CTRL18. 22515 */ 22516 typedef union BCMI_HURACAN_BG_CTRL18r_s { 22517 uint32_t v[1]; 22518 uint32_t bg_ctrl18[1]; 22519 uint32_t _bg_ctrl18; 22520 } BCMI_HURACAN_BG_CTRL18r_t; 22521 22522 #define BCMI_HURACAN_BG_CTRL18r_CLR(r) (r).bg_ctrl18[0] = 0 22523 #define BCMI_HURACAN_BG_CTRL18r_SET(r,d) (r).bg_ctrl18[0] = d 22524 #define BCMI_HURACAN_BG_CTRL18r_GET(r) (r).bg_ctrl18[0] 22525 22526 /* 22527 * These macros can be used to access individual fields. 22528 */ 22529 #define BCMI_HURACAN_BG_CTRL18r_CTATADJ_PTAT_RCALf_GET(r) ((((r).bg_ctrl18[0]) >> 8) & 0x1f) 22530 #define BCMI_HURACAN_BG_CTRL18r_CTATADJ_PTAT_RCALf_SET(r,f) (r).bg_ctrl18[0]=(((r).bg_ctrl18[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 22531 #define BCMI_HURACAN_BG_CTRL18r_PTATADJ_PTAT_RCALf_GET(r) (((r).bg_ctrl18[0]) & 0x1f) 22532 #define BCMI_HURACAN_BG_CTRL18r_PTATADJ_PTAT_RCALf_SET(r,f) (r).bg_ctrl18[0]=(((r).bg_ctrl18[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 22533 22534 /* 22535 * These macros can be used to access BG_CTRL18. 22536 */ 22537 #define BCMI_HURACAN_READ_BG_CTRL18r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL18r,_r._bg_ctrl18) 22538 #define BCMI_HURACAN_WRITE_BG_CTRL18r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL18r,_r._bg_ctrl18) 22539 22540 /* 22541 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22542 * will be redefined without the chip prefix for easier programming. 22543 * If multiple chips will be programmed in the same source file, then you should 22544 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22545 * and refer to the fully qualified versions. 22546 */ 22547 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22548 22549 #define BG_CTRL18r BCMI_HURACAN_BG_CTRL18r 22550 #define BG_CTRL18r_SIZE BCMI_HURACAN_BG_CTRL18r_SIZE 22551 typedef BCMI_HURACAN_BG_CTRL18r_t BG_CTRL18r_t; 22552 #define BG_CTRL18r_CLR BCMI_HURACAN_BG_CTRL18r_CLR 22553 #define BG_CTRL18r_SET BCMI_HURACAN_BG_CTRL18r_SET 22554 #define BG_CTRL18r_GET BCMI_HURACAN_BG_CTRL18r_GET 22555 #define BG_CTRL18r_CTATADJ_PTAT_RCALf_GET BCMI_HURACAN_BG_CTRL18r_CTATADJ_PTAT_RCALf_GET 22556 #define BG_CTRL18r_CTATADJ_PTAT_RCALf_SET BCMI_HURACAN_BG_CTRL18r_CTATADJ_PTAT_RCALf_SET 22557 #define BG_CTRL18r_PTATADJ_PTAT_RCALf_GET BCMI_HURACAN_BG_CTRL18r_PTATADJ_PTAT_RCALf_GET 22558 #define BG_CTRL18r_PTATADJ_PTAT_RCALf_SET BCMI_HURACAN_BG_CTRL18r_PTATADJ_PTAT_RCALf_SET 22559 #define READ_BG_CTRL18r BCMI_HURACAN_READ_BG_CTRL18r 22560 #define WRITE_BG_CTRL18r BCMI_HURACAN_WRITE_BG_CTRL18r 22561 #define MODIFY_BG_CTRL18r BCMI_HURACAN_MODIFY_BG_CTRL18r 22562 22563 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22564 /******************************************************************************* 22565 * End of 'BCMI_HURACAN_BG_CTRL18r' 22566 */ 22567 22568 22569 22570 22571 /******************************************************************************* 22572 * CHIP: BCMI_HURACAN 22573 * REGISTER: BG_CTRL19 22574 * BLOCKS: CTRL_QUAD_D 22575 * REGADDR: 0xb088 22576 * DEVAD: 1 22577 * DESC: control registers for AMS BG control bus 22578 * RESETVAL: 0x0 (0) 22579 * ACCESS: R/W 22580 * FIELDS: 22581 * PTATADJ_BG_RCAL 22582 * CTATADJ_BG_RCAL 22583 */ 22584 #define BCMI_HURACAN_BG_CTRL19r (0x0001b088 | PHYMOD_REG_ACC_RAW) 22585 22586 #define BCMI_HURACAN_BG_CTRL19r_SIZE 4 22587 22588 /* 22589 * This structure should be used to declare and program BG_CTRL19. 22590 */ 22591 typedef union BCMI_HURACAN_BG_CTRL19r_s { 22592 uint32_t v[1]; 22593 uint32_t bg_ctrl19[1]; 22594 uint32_t _bg_ctrl19; 22595 } BCMI_HURACAN_BG_CTRL19r_t; 22596 22597 #define BCMI_HURACAN_BG_CTRL19r_CLR(r) (r).bg_ctrl19[0] = 0 22598 #define BCMI_HURACAN_BG_CTRL19r_SET(r,d) (r).bg_ctrl19[0] = d 22599 #define BCMI_HURACAN_BG_CTRL19r_GET(r) (r).bg_ctrl19[0] 22600 22601 /* 22602 * These macros can be used to access individual fields. 22603 */ 22604 #define BCMI_HURACAN_BG_CTRL19r_CTATADJ_BG_RCALf_GET(r) ((((r).bg_ctrl19[0]) >> 8) & 0x1f) 22605 #define BCMI_HURACAN_BG_CTRL19r_CTATADJ_BG_RCALf_SET(r,f) (r).bg_ctrl19[0]=(((r).bg_ctrl19[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 22606 #define BCMI_HURACAN_BG_CTRL19r_PTATADJ_BG_RCALf_GET(r) (((r).bg_ctrl19[0]) & 0x1f) 22607 #define BCMI_HURACAN_BG_CTRL19r_PTATADJ_BG_RCALf_SET(r,f) (r).bg_ctrl19[0]=(((r).bg_ctrl19[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 22608 22609 /* 22610 * These macros can be used to access BG_CTRL19. 22611 */ 22612 #define BCMI_HURACAN_READ_BG_CTRL19r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL19r,_r._bg_ctrl19) 22613 #define BCMI_HURACAN_WRITE_BG_CTRL19r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL19r,_r._bg_ctrl19) 22614 22615 /* 22616 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22617 * will be redefined without the chip prefix for easier programming. 22618 * If multiple chips will be programmed in the same source file, then you should 22619 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22620 * and refer to the fully qualified versions. 22621 */ 22622 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22623 22624 #define BG_CTRL19r BCMI_HURACAN_BG_CTRL19r 22625 #define BG_CTRL19r_SIZE BCMI_HURACAN_BG_CTRL19r_SIZE 22626 typedef BCMI_HURACAN_BG_CTRL19r_t BG_CTRL19r_t; 22627 #define BG_CTRL19r_CLR BCMI_HURACAN_BG_CTRL19r_CLR 22628 #define BG_CTRL19r_SET BCMI_HURACAN_BG_CTRL19r_SET 22629 #define BG_CTRL19r_GET BCMI_HURACAN_BG_CTRL19r_GET 22630 #define BG_CTRL19r_CTATADJ_BG_RCALf_GET BCMI_HURACAN_BG_CTRL19r_CTATADJ_BG_RCALf_GET 22631 #define BG_CTRL19r_CTATADJ_BG_RCALf_SET BCMI_HURACAN_BG_CTRL19r_CTATADJ_BG_RCALf_SET 22632 #define BG_CTRL19r_PTATADJ_BG_RCALf_GET BCMI_HURACAN_BG_CTRL19r_PTATADJ_BG_RCALf_GET 22633 #define BG_CTRL19r_PTATADJ_BG_RCALf_SET BCMI_HURACAN_BG_CTRL19r_PTATADJ_BG_RCALf_SET 22634 #define READ_BG_CTRL19r BCMI_HURACAN_READ_BG_CTRL19r 22635 #define WRITE_BG_CTRL19r BCMI_HURACAN_WRITE_BG_CTRL19r 22636 #define MODIFY_BG_CTRL19r BCMI_HURACAN_MODIFY_BG_CTRL19r 22637 22638 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22639 /******************************************************************************* 22640 * End of 'BCMI_HURACAN_BG_CTRL19r' 22641 */ 22642 22643 22644 22645 22646 /******************************************************************************* 22647 * CHIP: BCMI_HURACAN 22648 * REGISTER: BG_CTRL20 22649 * BLOCKS: CTRL_QUAD_D 22650 * REGADDR: 0xb089 22651 * DEVAD: 1 22652 * DESC: control registers for AMS BG control bus 22653 * RESETVAL: 0x0 (0) 22654 * ACCESS: R/W 22655 * FIELDS: 22656 * BG_RESERVED_FOR_199_TO_184 22657 */ 22658 #define BCMI_HURACAN_BG_CTRL20r (0x0001b089 | PHYMOD_REG_ACC_RAW) 22659 22660 #define BCMI_HURACAN_BG_CTRL20r_SIZE 4 22661 22662 /* 22663 * This structure should be used to declare and program BG_CTRL20. 22664 */ 22665 typedef union BCMI_HURACAN_BG_CTRL20r_s { 22666 uint32_t v[1]; 22667 uint32_t bg_ctrl20[1]; 22668 uint32_t _bg_ctrl20; 22669 } BCMI_HURACAN_BG_CTRL20r_t; 22670 22671 #define BCMI_HURACAN_BG_CTRL20r_CLR(r) (r).bg_ctrl20[0] = 0 22672 #define BCMI_HURACAN_BG_CTRL20r_SET(r,d) (r).bg_ctrl20[0] = d 22673 #define BCMI_HURACAN_BG_CTRL20r_GET(r) (r).bg_ctrl20[0] 22674 22675 /* 22676 * These macros can be used to access individual fields. 22677 */ 22678 #define BCMI_HURACAN_BG_CTRL20r_BG_RESERVED_FOR_199_TO_184f_GET(r) (((r).bg_ctrl20[0]) & 0xffff) 22679 #define BCMI_HURACAN_BG_CTRL20r_BG_RESERVED_FOR_199_TO_184f_SET(r,f) (r).bg_ctrl20[0]=(((r).bg_ctrl20[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 22680 22681 /* 22682 * These macros can be used to access BG_CTRL20. 22683 */ 22684 #define BCMI_HURACAN_READ_BG_CTRL20r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL20r,_r._bg_ctrl20) 22685 #define BCMI_HURACAN_WRITE_BG_CTRL20r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL20r,_r._bg_ctrl20) 22686 22687 /* 22688 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22689 * will be redefined without the chip prefix for easier programming. 22690 * If multiple chips will be programmed in the same source file, then you should 22691 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22692 * and refer to the fully qualified versions. 22693 */ 22694 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22695 22696 #define BG_CTRL20r BCMI_HURACAN_BG_CTRL20r 22697 #define BG_CTRL20r_SIZE BCMI_HURACAN_BG_CTRL20r_SIZE 22698 typedef BCMI_HURACAN_BG_CTRL20r_t BG_CTRL20r_t; 22699 #define BG_CTRL20r_CLR BCMI_HURACAN_BG_CTRL20r_CLR 22700 #define BG_CTRL20r_SET BCMI_HURACAN_BG_CTRL20r_SET 22701 #define BG_CTRL20r_GET BCMI_HURACAN_BG_CTRL20r_GET 22702 #define BG_CTRL20r_BG_RESERVED_FOR_199_TO_184f_GET BCMI_HURACAN_BG_CTRL20r_BG_RESERVED_FOR_199_TO_184f_GET 22703 #define BG_CTRL20r_BG_RESERVED_FOR_199_TO_184f_SET BCMI_HURACAN_BG_CTRL20r_BG_RESERVED_FOR_199_TO_184f_SET 22704 #define READ_BG_CTRL20r BCMI_HURACAN_READ_BG_CTRL20r 22705 #define WRITE_BG_CTRL20r BCMI_HURACAN_WRITE_BG_CTRL20r 22706 #define MODIFY_BG_CTRL20r BCMI_HURACAN_MODIFY_BG_CTRL20r 22707 22708 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22709 /******************************************************************************* 22710 * End of 'BCMI_HURACAN_BG_CTRL20r' 22711 */ 22712 22713 22714 22715 22716 /******************************************************************************* 22717 * CHIP: BCMI_HURACAN 22718 * REGISTER: BG_CTRL21 22719 * BLOCKS: CTRL_QUAD_D 22720 * REGADDR: 0xb08a 22721 * DEVAD: 1 22722 * DESC: control registers for AMS BG control bus 22723 * RESETVAL: 0x0 (0) 22724 * ACCESS: R/W 22725 * FIELDS: 22726 * BG_CALR_LA2_0 22727 * BG_CALR_LA2_1 22728 * BG_CALR_LA2_2 22729 * BG_CALR_LA2_3 22730 */ 22731 #define BCMI_HURACAN_BG_CTRL21r (0x0001b08a | PHYMOD_REG_ACC_RAW) 22732 22733 #define BCMI_HURACAN_BG_CTRL21r_SIZE 4 22734 22735 /* 22736 * This structure should be used to declare and program BG_CTRL21. 22737 */ 22738 typedef union BCMI_HURACAN_BG_CTRL21r_s { 22739 uint32_t v[1]; 22740 uint32_t bg_ctrl21[1]; 22741 uint32_t _bg_ctrl21; 22742 } BCMI_HURACAN_BG_CTRL21r_t; 22743 22744 #define BCMI_HURACAN_BG_CTRL21r_CLR(r) (r).bg_ctrl21[0] = 0 22745 #define BCMI_HURACAN_BG_CTRL21r_SET(r,d) (r).bg_ctrl21[0] = d 22746 #define BCMI_HURACAN_BG_CTRL21r_GET(r) (r).bg_ctrl21[0] 22747 22748 /* 22749 * These macros can be used to access individual fields. 22750 */ 22751 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_3f_GET(r) ((((r).bg_ctrl21[0]) >> 12) & 0xf) 22752 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_3f_SET(r,f) (r).bg_ctrl21[0]=(((r).bg_ctrl21[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 22753 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_2f_GET(r) ((((r).bg_ctrl21[0]) >> 8) & 0xf) 22754 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_2f_SET(r,f) (r).bg_ctrl21[0]=(((r).bg_ctrl21[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 22755 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_1f_GET(r) ((((r).bg_ctrl21[0]) >> 4) & 0xf) 22756 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_1f_SET(r,f) (r).bg_ctrl21[0]=(((r).bg_ctrl21[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22757 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_0f_GET(r) (((r).bg_ctrl21[0]) & 0xf) 22758 #define BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_0f_SET(r,f) (r).bg_ctrl21[0]=(((r).bg_ctrl21[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22759 22760 /* 22761 * These macros can be used to access BG_CTRL21. 22762 */ 22763 #define BCMI_HURACAN_READ_BG_CTRL21r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL21r,_r._bg_ctrl21) 22764 #define BCMI_HURACAN_WRITE_BG_CTRL21r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL21r,_r._bg_ctrl21) 22765 22766 /* 22767 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22768 * will be redefined without the chip prefix for easier programming. 22769 * If multiple chips will be programmed in the same source file, then you should 22770 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22771 * and refer to the fully qualified versions. 22772 */ 22773 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22774 22775 #define BG_CTRL21r BCMI_HURACAN_BG_CTRL21r 22776 #define BG_CTRL21r_SIZE BCMI_HURACAN_BG_CTRL21r_SIZE 22777 typedef BCMI_HURACAN_BG_CTRL21r_t BG_CTRL21r_t; 22778 #define BG_CTRL21r_CLR BCMI_HURACAN_BG_CTRL21r_CLR 22779 #define BG_CTRL21r_SET BCMI_HURACAN_BG_CTRL21r_SET 22780 #define BG_CTRL21r_GET BCMI_HURACAN_BG_CTRL21r_GET 22781 #define BG_CTRL21r_BG_CALR_LA2_3f_GET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_3f_GET 22782 #define BG_CTRL21r_BG_CALR_LA2_3f_SET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_3f_SET 22783 #define BG_CTRL21r_BG_CALR_LA2_2f_GET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_2f_GET 22784 #define BG_CTRL21r_BG_CALR_LA2_2f_SET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_2f_SET 22785 #define BG_CTRL21r_BG_CALR_LA2_1f_GET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_1f_GET 22786 #define BG_CTRL21r_BG_CALR_LA2_1f_SET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_1f_SET 22787 #define BG_CTRL21r_BG_CALR_LA2_0f_GET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_0f_GET 22788 #define BG_CTRL21r_BG_CALR_LA2_0f_SET BCMI_HURACAN_BG_CTRL21r_BG_CALR_LA2_0f_SET 22789 #define READ_BG_CTRL21r BCMI_HURACAN_READ_BG_CTRL21r 22790 #define WRITE_BG_CTRL21r BCMI_HURACAN_WRITE_BG_CTRL21r 22791 #define MODIFY_BG_CTRL21r BCMI_HURACAN_MODIFY_BG_CTRL21r 22792 22793 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22794 /******************************************************************************* 22795 * End of 'BCMI_HURACAN_BG_CTRL21r' 22796 */ 22797 22798 22799 22800 22801 /******************************************************************************* 22802 * CHIP: BCMI_HURACAN 22803 * REGISTER: BG_CTRL22 22804 * BLOCKS: CTRL_QUAD_D 22805 * REGADDR: 0xb08b 22806 * DEVAD: 1 22807 * DESC: control registers for AMS BG control bus 22808 * RESETVAL: 0x0 (0) 22809 * ACCESS: R/W 22810 * FIELDS: 22811 * BG_CALR_LA1_0 22812 * BG_CALR_LA1_1 22813 * BG_CALR_LA1_2 22814 * BG_CALR_LA1_3 22815 */ 22816 #define BCMI_HURACAN_BG_CTRL22r (0x0001b08b | PHYMOD_REG_ACC_RAW) 22817 22818 #define BCMI_HURACAN_BG_CTRL22r_SIZE 4 22819 22820 /* 22821 * This structure should be used to declare and program BG_CTRL22. 22822 */ 22823 typedef union BCMI_HURACAN_BG_CTRL22r_s { 22824 uint32_t v[1]; 22825 uint32_t bg_ctrl22[1]; 22826 uint32_t _bg_ctrl22; 22827 } BCMI_HURACAN_BG_CTRL22r_t; 22828 22829 #define BCMI_HURACAN_BG_CTRL22r_CLR(r) (r).bg_ctrl22[0] = 0 22830 #define BCMI_HURACAN_BG_CTRL22r_SET(r,d) (r).bg_ctrl22[0] = d 22831 #define BCMI_HURACAN_BG_CTRL22r_GET(r) (r).bg_ctrl22[0] 22832 22833 /* 22834 * These macros can be used to access individual fields. 22835 */ 22836 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_3f_GET(r) ((((r).bg_ctrl22[0]) >> 12) & 0xf) 22837 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_3f_SET(r,f) (r).bg_ctrl22[0]=(((r).bg_ctrl22[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 22838 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_2f_GET(r) ((((r).bg_ctrl22[0]) >> 8) & 0xf) 22839 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_2f_SET(r,f) (r).bg_ctrl22[0]=(((r).bg_ctrl22[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 22840 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_1f_GET(r) ((((r).bg_ctrl22[0]) >> 4) & 0xf) 22841 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_1f_SET(r,f) (r).bg_ctrl22[0]=(((r).bg_ctrl22[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22842 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_0f_GET(r) (((r).bg_ctrl22[0]) & 0xf) 22843 #define BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_0f_SET(r,f) (r).bg_ctrl22[0]=(((r).bg_ctrl22[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22844 22845 /* 22846 * These macros can be used to access BG_CTRL22. 22847 */ 22848 #define BCMI_HURACAN_READ_BG_CTRL22r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL22r,_r._bg_ctrl22) 22849 #define BCMI_HURACAN_WRITE_BG_CTRL22r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL22r,_r._bg_ctrl22) 22850 22851 /* 22852 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22853 * will be redefined without the chip prefix for easier programming. 22854 * If multiple chips will be programmed in the same source file, then you should 22855 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22856 * and refer to the fully qualified versions. 22857 */ 22858 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22859 22860 #define BG_CTRL22r BCMI_HURACAN_BG_CTRL22r 22861 #define BG_CTRL22r_SIZE BCMI_HURACAN_BG_CTRL22r_SIZE 22862 typedef BCMI_HURACAN_BG_CTRL22r_t BG_CTRL22r_t; 22863 #define BG_CTRL22r_CLR BCMI_HURACAN_BG_CTRL22r_CLR 22864 #define BG_CTRL22r_SET BCMI_HURACAN_BG_CTRL22r_SET 22865 #define BG_CTRL22r_GET BCMI_HURACAN_BG_CTRL22r_GET 22866 #define BG_CTRL22r_BG_CALR_LA1_3f_GET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_3f_GET 22867 #define BG_CTRL22r_BG_CALR_LA1_3f_SET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_3f_SET 22868 #define BG_CTRL22r_BG_CALR_LA1_2f_GET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_2f_GET 22869 #define BG_CTRL22r_BG_CALR_LA1_2f_SET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_2f_SET 22870 #define BG_CTRL22r_BG_CALR_LA1_1f_GET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_1f_GET 22871 #define BG_CTRL22r_BG_CALR_LA1_1f_SET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_1f_SET 22872 #define BG_CTRL22r_BG_CALR_LA1_0f_GET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_0f_GET 22873 #define BG_CTRL22r_BG_CALR_LA1_0f_SET BCMI_HURACAN_BG_CTRL22r_BG_CALR_LA1_0f_SET 22874 #define READ_BG_CTRL22r BCMI_HURACAN_READ_BG_CTRL22r 22875 #define WRITE_BG_CTRL22r BCMI_HURACAN_WRITE_BG_CTRL22r 22876 #define MODIFY_BG_CTRL22r BCMI_HURACAN_MODIFY_BG_CTRL22r 22877 22878 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22879 /******************************************************************************* 22880 * End of 'BCMI_HURACAN_BG_CTRL22r' 22881 */ 22882 22883 22884 22885 22886 /******************************************************************************* 22887 * CHIP: BCMI_HURACAN 22888 * REGISTER: BG_CTRL23 22889 * BLOCKS: CTRL_QUAD_D 22890 * REGADDR: 0xb08c 22891 * DEVAD: 1 22892 * DESC: control registers for AMS BG control bus 22893 * RESETVAL: 0x0 (0) 22894 * ACCESS: R/W 22895 * FIELDS: 22896 * BG_CALR_DRV2_0 22897 * BG_CALR_DRV2_1 22898 * BG_CALR_DRV2_2 22899 * BG_CALR_DRV2_3 22900 */ 22901 #define BCMI_HURACAN_BG_CTRL23r (0x0001b08c | PHYMOD_REG_ACC_RAW) 22902 22903 #define BCMI_HURACAN_BG_CTRL23r_SIZE 4 22904 22905 /* 22906 * This structure should be used to declare and program BG_CTRL23. 22907 */ 22908 typedef union BCMI_HURACAN_BG_CTRL23r_s { 22909 uint32_t v[1]; 22910 uint32_t bg_ctrl23[1]; 22911 uint32_t _bg_ctrl23; 22912 } BCMI_HURACAN_BG_CTRL23r_t; 22913 22914 #define BCMI_HURACAN_BG_CTRL23r_CLR(r) (r).bg_ctrl23[0] = 0 22915 #define BCMI_HURACAN_BG_CTRL23r_SET(r,d) (r).bg_ctrl23[0] = d 22916 #define BCMI_HURACAN_BG_CTRL23r_GET(r) (r).bg_ctrl23[0] 22917 22918 /* 22919 * These macros can be used to access individual fields. 22920 */ 22921 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_3f_GET(r) ((((r).bg_ctrl23[0]) >> 12) & 0xf) 22922 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_3f_SET(r,f) (r).bg_ctrl23[0]=(((r).bg_ctrl23[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 22923 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_2f_GET(r) ((((r).bg_ctrl23[0]) >> 8) & 0xf) 22924 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_2f_SET(r,f) (r).bg_ctrl23[0]=(((r).bg_ctrl23[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 22925 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_1f_GET(r) ((((r).bg_ctrl23[0]) >> 4) & 0xf) 22926 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_1f_SET(r,f) (r).bg_ctrl23[0]=(((r).bg_ctrl23[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 22927 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_0f_GET(r) (((r).bg_ctrl23[0]) & 0xf) 22928 #define BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_0f_SET(r,f) (r).bg_ctrl23[0]=(((r).bg_ctrl23[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 22929 22930 /* 22931 * These macros can be used to access BG_CTRL23. 22932 */ 22933 #define BCMI_HURACAN_READ_BG_CTRL23r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL23r,_r._bg_ctrl23) 22934 #define BCMI_HURACAN_WRITE_BG_CTRL23r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL23r,_r._bg_ctrl23) 22935 22936 /* 22937 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 22938 * will be redefined without the chip prefix for easier programming. 22939 * If multiple chips will be programmed in the same source file, then you should 22940 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 22941 * and refer to the fully qualified versions. 22942 */ 22943 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 22944 22945 #define BG_CTRL23r BCMI_HURACAN_BG_CTRL23r 22946 #define BG_CTRL23r_SIZE BCMI_HURACAN_BG_CTRL23r_SIZE 22947 typedef BCMI_HURACAN_BG_CTRL23r_t BG_CTRL23r_t; 22948 #define BG_CTRL23r_CLR BCMI_HURACAN_BG_CTRL23r_CLR 22949 #define BG_CTRL23r_SET BCMI_HURACAN_BG_CTRL23r_SET 22950 #define BG_CTRL23r_GET BCMI_HURACAN_BG_CTRL23r_GET 22951 #define BG_CTRL23r_BG_CALR_DRV2_3f_GET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_3f_GET 22952 #define BG_CTRL23r_BG_CALR_DRV2_3f_SET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_3f_SET 22953 #define BG_CTRL23r_BG_CALR_DRV2_2f_GET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_2f_GET 22954 #define BG_CTRL23r_BG_CALR_DRV2_2f_SET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_2f_SET 22955 #define BG_CTRL23r_BG_CALR_DRV2_1f_GET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_1f_GET 22956 #define BG_CTRL23r_BG_CALR_DRV2_1f_SET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_1f_SET 22957 #define BG_CTRL23r_BG_CALR_DRV2_0f_GET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_0f_GET 22958 #define BG_CTRL23r_BG_CALR_DRV2_0f_SET BCMI_HURACAN_BG_CTRL23r_BG_CALR_DRV2_0f_SET 22959 #define READ_BG_CTRL23r BCMI_HURACAN_READ_BG_CTRL23r 22960 #define WRITE_BG_CTRL23r BCMI_HURACAN_WRITE_BG_CTRL23r 22961 #define MODIFY_BG_CTRL23r BCMI_HURACAN_MODIFY_BG_CTRL23r 22962 22963 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 22964 /******************************************************************************* 22965 * End of 'BCMI_HURACAN_BG_CTRL23r' 22966 */ 22967 22968 22969 22970 22971 /******************************************************************************* 22972 * CHIP: BCMI_HURACAN 22973 * REGISTER: BG_CTRL24 22974 * BLOCKS: CTRL_QUAD_D 22975 * REGADDR: 0xb08d 22976 * DEVAD: 1 22977 * DESC: control registers for AMS BG control bus 22978 * RESETVAL: 0x0 (0) 22979 * ACCESS: R/W 22980 * FIELDS: 22981 * BG_CALR_DRV1_0 22982 * BG_CALR_DRV1_1 22983 * BG_CALR_DRV1_2 22984 * BG_CALR_DRV1_3 22985 */ 22986 #define BCMI_HURACAN_BG_CTRL24r (0x0001b08d | PHYMOD_REG_ACC_RAW) 22987 22988 #define BCMI_HURACAN_BG_CTRL24r_SIZE 4 22989 22990 /* 22991 * This structure should be used to declare and program BG_CTRL24. 22992 */ 22993 typedef union BCMI_HURACAN_BG_CTRL24r_s { 22994 uint32_t v[1]; 22995 uint32_t bg_ctrl24[1]; 22996 uint32_t _bg_ctrl24; 22997 } BCMI_HURACAN_BG_CTRL24r_t; 22998 22999 #define BCMI_HURACAN_BG_CTRL24r_CLR(r) (r).bg_ctrl24[0] = 0 23000 #define BCMI_HURACAN_BG_CTRL24r_SET(r,d) (r).bg_ctrl24[0] = d 23001 #define BCMI_HURACAN_BG_CTRL24r_GET(r) (r).bg_ctrl24[0] 23002 23003 /* 23004 * These macros can be used to access individual fields. 23005 */ 23006 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_3f_GET(r) ((((r).bg_ctrl24[0]) >> 12) & 0xf) 23007 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_3f_SET(r,f) (r).bg_ctrl24[0]=(((r).bg_ctrl24[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 23008 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_2f_GET(r) ((((r).bg_ctrl24[0]) >> 8) & 0xf) 23009 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_2f_SET(r,f) (r).bg_ctrl24[0]=(((r).bg_ctrl24[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 23010 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_1f_GET(r) ((((r).bg_ctrl24[0]) >> 4) & 0xf) 23011 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_1f_SET(r,f) (r).bg_ctrl24[0]=(((r).bg_ctrl24[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23012 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_0f_GET(r) (((r).bg_ctrl24[0]) & 0xf) 23013 #define BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_0f_SET(r,f) (r).bg_ctrl24[0]=(((r).bg_ctrl24[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 23014 23015 /* 23016 * These macros can be used to access BG_CTRL24. 23017 */ 23018 #define BCMI_HURACAN_READ_BG_CTRL24r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL24r,_r._bg_ctrl24) 23019 #define BCMI_HURACAN_WRITE_BG_CTRL24r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL24r,_r._bg_ctrl24) 23020 23021 /* 23022 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23023 * will be redefined without the chip prefix for easier programming. 23024 * If multiple chips will be programmed in the same source file, then you should 23025 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23026 * and refer to the fully qualified versions. 23027 */ 23028 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23029 23030 #define BG_CTRL24r BCMI_HURACAN_BG_CTRL24r 23031 #define BG_CTRL24r_SIZE BCMI_HURACAN_BG_CTRL24r_SIZE 23032 typedef BCMI_HURACAN_BG_CTRL24r_t BG_CTRL24r_t; 23033 #define BG_CTRL24r_CLR BCMI_HURACAN_BG_CTRL24r_CLR 23034 #define BG_CTRL24r_SET BCMI_HURACAN_BG_CTRL24r_SET 23035 #define BG_CTRL24r_GET BCMI_HURACAN_BG_CTRL24r_GET 23036 #define BG_CTRL24r_BG_CALR_DRV1_3f_GET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_3f_GET 23037 #define BG_CTRL24r_BG_CALR_DRV1_3f_SET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_3f_SET 23038 #define BG_CTRL24r_BG_CALR_DRV1_2f_GET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_2f_GET 23039 #define BG_CTRL24r_BG_CALR_DRV1_2f_SET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_2f_SET 23040 #define BG_CTRL24r_BG_CALR_DRV1_1f_GET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_1f_GET 23041 #define BG_CTRL24r_BG_CALR_DRV1_1f_SET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_1f_SET 23042 #define BG_CTRL24r_BG_CALR_DRV1_0f_GET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_0f_GET 23043 #define BG_CTRL24r_BG_CALR_DRV1_0f_SET BCMI_HURACAN_BG_CTRL24r_BG_CALR_DRV1_0f_SET 23044 #define READ_BG_CTRL24r BCMI_HURACAN_READ_BG_CTRL24r 23045 #define WRITE_BG_CTRL24r BCMI_HURACAN_WRITE_BG_CTRL24r 23046 #define MODIFY_BG_CTRL24r BCMI_HURACAN_MODIFY_BG_CTRL24r 23047 23048 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23049 /******************************************************************************* 23050 * End of 'BCMI_HURACAN_BG_CTRL24r' 23051 */ 23052 23053 23054 23055 23056 /******************************************************************************* 23057 * CHIP: BCMI_HURACAN 23058 * REGISTER: BG_CTRL25 23059 * BLOCKS: CTRL_QUAD_D 23060 * REGADDR: 0xb08e 23061 * DEVAD: 1 23062 * DESC: control registers for AMS BG control bus 23063 * RESETVAL: 0x0 (0) 23064 * ACCESS: R/W 23065 * FIELDS: 23066 * BG_RESERVED_FOR_119_TO_104 23067 */ 23068 #define BCMI_HURACAN_BG_CTRL25r (0x0001b08e | PHYMOD_REG_ACC_RAW) 23069 23070 #define BCMI_HURACAN_BG_CTRL25r_SIZE 4 23071 23072 /* 23073 * This structure should be used to declare and program BG_CTRL25. 23074 */ 23075 typedef union BCMI_HURACAN_BG_CTRL25r_s { 23076 uint32_t v[1]; 23077 uint32_t bg_ctrl25[1]; 23078 uint32_t _bg_ctrl25; 23079 } BCMI_HURACAN_BG_CTRL25r_t; 23080 23081 #define BCMI_HURACAN_BG_CTRL25r_CLR(r) (r).bg_ctrl25[0] = 0 23082 #define BCMI_HURACAN_BG_CTRL25r_SET(r,d) (r).bg_ctrl25[0] = d 23083 #define BCMI_HURACAN_BG_CTRL25r_GET(r) (r).bg_ctrl25[0] 23084 23085 /* 23086 * These macros can be used to access individual fields. 23087 */ 23088 #define BCMI_HURACAN_BG_CTRL25r_BG_RESERVED_FOR_119_TO_104f_GET(r) (((r).bg_ctrl25[0]) & 0xffff) 23089 #define BCMI_HURACAN_BG_CTRL25r_BG_RESERVED_FOR_119_TO_104f_SET(r,f) (r).bg_ctrl25[0]=(((r).bg_ctrl25[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 23090 23091 /* 23092 * These macros can be used to access BG_CTRL25. 23093 */ 23094 #define BCMI_HURACAN_READ_BG_CTRL25r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL25r,_r._bg_ctrl25) 23095 #define BCMI_HURACAN_WRITE_BG_CTRL25r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL25r,_r._bg_ctrl25) 23096 23097 /* 23098 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23099 * will be redefined without the chip prefix for easier programming. 23100 * If multiple chips will be programmed in the same source file, then you should 23101 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23102 * and refer to the fully qualified versions. 23103 */ 23104 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23105 23106 #define BG_CTRL25r BCMI_HURACAN_BG_CTRL25r 23107 #define BG_CTRL25r_SIZE BCMI_HURACAN_BG_CTRL25r_SIZE 23108 typedef BCMI_HURACAN_BG_CTRL25r_t BG_CTRL25r_t; 23109 #define BG_CTRL25r_CLR BCMI_HURACAN_BG_CTRL25r_CLR 23110 #define BG_CTRL25r_SET BCMI_HURACAN_BG_CTRL25r_SET 23111 #define BG_CTRL25r_GET BCMI_HURACAN_BG_CTRL25r_GET 23112 #define BG_CTRL25r_BG_RESERVED_FOR_119_TO_104f_GET BCMI_HURACAN_BG_CTRL25r_BG_RESERVED_FOR_119_TO_104f_GET 23113 #define BG_CTRL25r_BG_RESERVED_FOR_119_TO_104f_SET BCMI_HURACAN_BG_CTRL25r_BG_RESERVED_FOR_119_TO_104f_SET 23114 #define READ_BG_CTRL25r BCMI_HURACAN_READ_BG_CTRL25r 23115 #define WRITE_BG_CTRL25r BCMI_HURACAN_WRITE_BG_CTRL25r 23116 #define MODIFY_BG_CTRL25r BCMI_HURACAN_MODIFY_BG_CTRL25r 23117 23118 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23119 /******************************************************************************* 23120 * End of 'BCMI_HURACAN_BG_CTRL25r' 23121 */ 23122 23123 23124 23125 23126 /******************************************************************************* 23127 * CHIP: BCMI_HURACAN 23128 * REGISTER: BG_CTRL26 23129 * BLOCKS: CTRL_QUAD_D 23130 * REGADDR: 0xb08f 23131 * DEVAD: 1 23132 * DESC: control registers for AMS BG control bus 23133 * RESETVAL: 0x0 (0) 23134 * ACCESS: R/W 23135 * FIELDS: 23136 * PTAT_CALR_LA0 23137 * PTAT_CALR_LA1 23138 * PTAT_CALR_LA2 23139 * PTAT_CALR_LA3 23140 */ 23141 #define BCMI_HURACAN_BG_CTRL26r (0x0001b08f | PHYMOD_REG_ACC_RAW) 23142 23143 #define BCMI_HURACAN_BG_CTRL26r_SIZE 4 23144 23145 /* 23146 * This structure should be used to declare and program BG_CTRL26. 23147 */ 23148 typedef union BCMI_HURACAN_BG_CTRL26r_s { 23149 uint32_t v[1]; 23150 uint32_t bg_ctrl26[1]; 23151 uint32_t _bg_ctrl26; 23152 } BCMI_HURACAN_BG_CTRL26r_t; 23153 23154 #define BCMI_HURACAN_BG_CTRL26r_CLR(r) (r).bg_ctrl26[0] = 0 23155 #define BCMI_HURACAN_BG_CTRL26r_SET(r,d) (r).bg_ctrl26[0] = d 23156 #define BCMI_HURACAN_BG_CTRL26r_GET(r) (r).bg_ctrl26[0] 23157 23158 /* 23159 * These macros can be used to access individual fields. 23160 */ 23161 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA3f_GET(r) ((((r).bg_ctrl26[0]) >> 12) & 0xf) 23162 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA3f_SET(r,f) (r).bg_ctrl26[0]=(((r).bg_ctrl26[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 23163 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA2f_GET(r) ((((r).bg_ctrl26[0]) >> 8) & 0xf) 23164 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA2f_SET(r,f) (r).bg_ctrl26[0]=(((r).bg_ctrl26[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 23165 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA1f_GET(r) ((((r).bg_ctrl26[0]) >> 4) & 0xf) 23166 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA1f_SET(r,f) (r).bg_ctrl26[0]=(((r).bg_ctrl26[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23167 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA0f_GET(r) (((r).bg_ctrl26[0]) & 0xf) 23168 #define BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA0f_SET(r,f) (r).bg_ctrl26[0]=(((r).bg_ctrl26[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 23169 23170 /* 23171 * These macros can be used to access BG_CTRL26. 23172 */ 23173 #define BCMI_HURACAN_READ_BG_CTRL26r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL26r,_r._bg_ctrl26) 23174 #define BCMI_HURACAN_WRITE_BG_CTRL26r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL26r,_r._bg_ctrl26) 23175 23176 /* 23177 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23178 * will be redefined without the chip prefix for easier programming. 23179 * If multiple chips will be programmed in the same source file, then you should 23180 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23181 * and refer to the fully qualified versions. 23182 */ 23183 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23184 23185 #define BG_CTRL26r BCMI_HURACAN_BG_CTRL26r 23186 #define BG_CTRL26r_SIZE BCMI_HURACAN_BG_CTRL26r_SIZE 23187 typedef BCMI_HURACAN_BG_CTRL26r_t BG_CTRL26r_t; 23188 #define BG_CTRL26r_CLR BCMI_HURACAN_BG_CTRL26r_CLR 23189 #define BG_CTRL26r_SET BCMI_HURACAN_BG_CTRL26r_SET 23190 #define BG_CTRL26r_GET BCMI_HURACAN_BG_CTRL26r_GET 23191 #define BG_CTRL26r_PTAT_CALR_LA3f_GET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA3f_GET 23192 #define BG_CTRL26r_PTAT_CALR_LA3f_SET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA3f_SET 23193 #define BG_CTRL26r_PTAT_CALR_LA2f_GET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA2f_GET 23194 #define BG_CTRL26r_PTAT_CALR_LA2f_SET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA2f_SET 23195 #define BG_CTRL26r_PTAT_CALR_LA1f_GET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA1f_GET 23196 #define BG_CTRL26r_PTAT_CALR_LA1f_SET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA1f_SET 23197 #define BG_CTRL26r_PTAT_CALR_LA0f_GET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA0f_GET 23198 #define BG_CTRL26r_PTAT_CALR_LA0f_SET BCMI_HURACAN_BG_CTRL26r_PTAT_CALR_LA0f_SET 23199 #define READ_BG_CTRL26r BCMI_HURACAN_READ_BG_CTRL26r 23200 #define WRITE_BG_CTRL26r BCMI_HURACAN_WRITE_BG_CTRL26r 23201 #define MODIFY_BG_CTRL26r BCMI_HURACAN_MODIFY_BG_CTRL26r 23202 23203 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23204 /******************************************************************************* 23205 * End of 'BCMI_HURACAN_BG_CTRL26r' 23206 */ 23207 23208 23209 23210 23211 /******************************************************************************* 23212 * CHIP: BCMI_HURACAN 23213 * REGISTER: BG_CTRL27 23214 * BLOCKS: CTRL_QUAD_D 23215 * REGADDR: 0xb090 23216 * DEVAD: 1 23217 * DESC: control registers for AMS BG control bus 23218 * RESETVAL: 0x0 (0) 23219 * ACCESS: R/W 23220 * FIELDS: 23221 * PTAT_CALR_CTLE0 23222 * PTAT_CALR_CTLE1 23223 * PTAT_CALR_CTLE2 23224 * PTAT_CALR_CTLE3 23225 */ 23226 #define BCMI_HURACAN_BG_CTRL27r (0x0001b090 | PHYMOD_REG_ACC_RAW) 23227 23228 #define BCMI_HURACAN_BG_CTRL27r_SIZE 4 23229 23230 /* 23231 * This structure should be used to declare and program BG_CTRL27. 23232 */ 23233 typedef union BCMI_HURACAN_BG_CTRL27r_s { 23234 uint32_t v[1]; 23235 uint32_t bg_ctrl27[1]; 23236 uint32_t _bg_ctrl27; 23237 } BCMI_HURACAN_BG_CTRL27r_t; 23238 23239 #define BCMI_HURACAN_BG_CTRL27r_CLR(r) (r).bg_ctrl27[0] = 0 23240 #define BCMI_HURACAN_BG_CTRL27r_SET(r,d) (r).bg_ctrl27[0] = d 23241 #define BCMI_HURACAN_BG_CTRL27r_GET(r) (r).bg_ctrl27[0] 23242 23243 /* 23244 * These macros can be used to access individual fields. 23245 */ 23246 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE3f_GET(r) ((((r).bg_ctrl27[0]) >> 12) & 0xf) 23247 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE3f_SET(r,f) (r).bg_ctrl27[0]=(((r).bg_ctrl27[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 23248 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE2f_GET(r) ((((r).bg_ctrl27[0]) >> 8) & 0xf) 23249 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE2f_SET(r,f) (r).bg_ctrl27[0]=(((r).bg_ctrl27[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 23250 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE1f_GET(r) ((((r).bg_ctrl27[0]) >> 4) & 0xf) 23251 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE1f_SET(r,f) (r).bg_ctrl27[0]=(((r).bg_ctrl27[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23252 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE0f_GET(r) (((r).bg_ctrl27[0]) & 0xf) 23253 #define BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE0f_SET(r,f) (r).bg_ctrl27[0]=(((r).bg_ctrl27[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 23254 23255 /* 23256 * These macros can be used to access BG_CTRL27. 23257 */ 23258 #define BCMI_HURACAN_READ_BG_CTRL27r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL27r,_r._bg_ctrl27) 23259 #define BCMI_HURACAN_WRITE_BG_CTRL27r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL27r,_r._bg_ctrl27) 23260 23261 /* 23262 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23263 * will be redefined without the chip prefix for easier programming. 23264 * If multiple chips will be programmed in the same source file, then you should 23265 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23266 * and refer to the fully qualified versions. 23267 */ 23268 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23269 23270 #define BG_CTRL27r BCMI_HURACAN_BG_CTRL27r 23271 #define BG_CTRL27r_SIZE BCMI_HURACAN_BG_CTRL27r_SIZE 23272 typedef BCMI_HURACAN_BG_CTRL27r_t BG_CTRL27r_t; 23273 #define BG_CTRL27r_CLR BCMI_HURACAN_BG_CTRL27r_CLR 23274 #define BG_CTRL27r_SET BCMI_HURACAN_BG_CTRL27r_SET 23275 #define BG_CTRL27r_GET BCMI_HURACAN_BG_CTRL27r_GET 23276 #define BG_CTRL27r_PTAT_CALR_CTLE3f_GET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE3f_GET 23277 #define BG_CTRL27r_PTAT_CALR_CTLE3f_SET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE3f_SET 23278 #define BG_CTRL27r_PTAT_CALR_CTLE2f_GET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE2f_GET 23279 #define BG_CTRL27r_PTAT_CALR_CTLE2f_SET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE2f_SET 23280 #define BG_CTRL27r_PTAT_CALR_CTLE1f_GET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE1f_GET 23281 #define BG_CTRL27r_PTAT_CALR_CTLE1f_SET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE1f_SET 23282 #define BG_CTRL27r_PTAT_CALR_CTLE0f_GET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE0f_GET 23283 #define BG_CTRL27r_PTAT_CALR_CTLE0f_SET BCMI_HURACAN_BG_CTRL27r_PTAT_CALR_CTLE0f_SET 23284 #define READ_BG_CTRL27r BCMI_HURACAN_READ_BG_CTRL27r 23285 #define WRITE_BG_CTRL27r BCMI_HURACAN_WRITE_BG_CTRL27r 23286 #define MODIFY_BG_CTRL27r BCMI_HURACAN_MODIFY_BG_CTRL27r 23287 23288 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23289 /******************************************************************************* 23290 * End of 'BCMI_HURACAN_BG_CTRL27r' 23291 */ 23292 23293 23294 23295 23296 /******************************************************************************* 23297 * CHIP: BCMI_HURACAN 23298 * REGISTER: BG_CTRL28 23299 * BLOCKS: CTRL_QUAD_D 23300 * REGADDR: 0xb091 23301 * DEVAD: 1 23302 * DESC: control registers for AMS BG control bus 23303 * RESETVAL: 0x0 (0) 23304 * ACCESS: R/W 23305 * FIELDS: 23306 * BG_RESERVED_FOR_71_TO_56 23307 */ 23308 #define BCMI_HURACAN_BG_CTRL28r (0x0001b091 | PHYMOD_REG_ACC_RAW) 23309 23310 #define BCMI_HURACAN_BG_CTRL28r_SIZE 4 23311 23312 /* 23313 * This structure should be used to declare and program BG_CTRL28. 23314 */ 23315 typedef union BCMI_HURACAN_BG_CTRL28r_s { 23316 uint32_t v[1]; 23317 uint32_t bg_ctrl28[1]; 23318 uint32_t _bg_ctrl28; 23319 } BCMI_HURACAN_BG_CTRL28r_t; 23320 23321 #define BCMI_HURACAN_BG_CTRL28r_CLR(r) (r).bg_ctrl28[0] = 0 23322 #define BCMI_HURACAN_BG_CTRL28r_SET(r,d) (r).bg_ctrl28[0] = d 23323 #define BCMI_HURACAN_BG_CTRL28r_GET(r) (r).bg_ctrl28[0] 23324 23325 /* 23326 * These macros can be used to access individual fields. 23327 */ 23328 #define BCMI_HURACAN_BG_CTRL28r_BG_RESERVED_FOR_71_TO_56f_GET(r) (((r).bg_ctrl28[0]) & 0xffff) 23329 #define BCMI_HURACAN_BG_CTRL28r_BG_RESERVED_FOR_71_TO_56f_SET(r,f) (r).bg_ctrl28[0]=(((r).bg_ctrl28[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 23330 23331 /* 23332 * These macros can be used to access BG_CTRL28. 23333 */ 23334 #define BCMI_HURACAN_READ_BG_CTRL28r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL28r,_r._bg_ctrl28) 23335 #define BCMI_HURACAN_WRITE_BG_CTRL28r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL28r,_r._bg_ctrl28) 23336 23337 /* 23338 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23339 * will be redefined without the chip prefix for easier programming. 23340 * If multiple chips will be programmed in the same source file, then you should 23341 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23342 * and refer to the fully qualified versions. 23343 */ 23344 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23345 23346 #define BG_CTRL28r BCMI_HURACAN_BG_CTRL28r 23347 #define BG_CTRL28r_SIZE BCMI_HURACAN_BG_CTRL28r_SIZE 23348 typedef BCMI_HURACAN_BG_CTRL28r_t BG_CTRL28r_t; 23349 #define BG_CTRL28r_CLR BCMI_HURACAN_BG_CTRL28r_CLR 23350 #define BG_CTRL28r_SET BCMI_HURACAN_BG_CTRL28r_SET 23351 #define BG_CTRL28r_GET BCMI_HURACAN_BG_CTRL28r_GET 23352 #define BG_CTRL28r_BG_RESERVED_FOR_71_TO_56f_GET BCMI_HURACAN_BG_CTRL28r_BG_RESERVED_FOR_71_TO_56f_GET 23353 #define BG_CTRL28r_BG_RESERVED_FOR_71_TO_56f_SET BCMI_HURACAN_BG_CTRL28r_BG_RESERVED_FOR_71_TO_56f_SET 23354 #define READ_BG_CTRL28r BCMI_HURACAN_READ_BG_CTRL28r 23355 #define WRITE_BG_CTRL28r BCMI_HURACAN_WRITE_BG_CTRL28r 23356 #define MODIFY_BG_CTRL28r BCMI_HURACAN_MODIFY_BG_CTRL28r 23357 23358 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23359 /******************************************************************************* 23360 * End of 'BCMI_HURACAN_BG_CTRL28r' 23361 */ 23362 23363 23364 23365 23366 /******************************************************************************* 23367 * CHIP: BCMI_HURACAN 23368 * REGISTER: BG_CTRL29 23369 * BLOCKS: CTRL_QUAD_D 23370 * REGADDR: 0xb092 23371 * DEVAD: 1 23372 * DESC: control registers for AMS BG control bus 23373 * RESETVAL: 0x0 (0) 23374 * ACCESS: R/W 23375 * FIELDS: 23376 * BG_R_SIGDET0_CNTRL 23377 * BG_R_SIGDET1_CNTRL 23378 * BG_R_SIGDET2_CNTRL 23379 * BG_R_SIGDET3_CNTRL 23380 */ 23381 #define BCMI_HURACAN_BG_CTRL29r (0x0001b092 | PHYMOD_REG_ACC_RAW) 23382 23383 #define BCMI_HURACAN_BG_CTRL29r_SIZE 4 23384 23385 /* 23386 * This structure should be used to declare and program BG_CTRL29. 23387 */ 23388 typedef union BCMI_HURACAN_BG_CTRL29r_s { 23389 uint32_t v[1]; 23390 uint32_t bg_ctrl29[1]; 23391 uint32_t _bg_ctrl29; 23392 } BCMI_HURACAN_BG_CTRL29r_t; 23393 23394 #define BCMI_HURACAN_BG_CTRL29r_CLR(r) (r).bg_ctrl29[0] = 0 23395 #define BCMI_HURACAN_BG_CTRL29r_SET(r,d) (r).bg_ctrl29[0] = d 23396 #define BCMI_HURACAN_BG_CTRL29r_GET(r) (r).bg_ctrl29[0] 23397 23398 /* 23399 * These macros can be used to access individual fields. 23400 */ 23401 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET3_CNTRLf_GET(r) ((((r).bg_ctrl29[0]) >> 12) & 0xf) 23402 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET3_CNTRLf_SET(r,f) (r).bg_ctrl29[0]=(((r).bg_ctrl29[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 23403 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET2_CNTRLf_GET(r) ((((r).bg_ctrl29[0]) >> 8) & 0xf) 23404 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET2_CNTRLf_SET(r,f) (r).bg_ctrl29[0]=(((r).bg_ctrl29[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 23405 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET1_CNTRLf_GET(r) ((((r).bg_ctrl29[0]) >> 4) & 0xf) 23406 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET1_CNTRLf_SET(r,f) (r).bg_ctrl29[0]=(((r).bg_ctrl29[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23407 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET0_CNTRLf_GET(r) (((r).bg_ctrl29[0]) & 0xf) 23408 #define BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET0_CNTRLf_SET(r,f) (r).bg_ctrl29[0]=(((r).bg_ctrl29[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 23409 23410 /* 23411 * These macros can be used to access BG_CTRL29. 23412 */ 23413 #define BCMI_HURACAN_READ_BG_CTRL29r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL29r,_r._bg_ctrl29) 23414 #define BCMI_HURACAN_WRITE_BG_CTRL29r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL29r,_r._bg_ctrl29) 23415 23416 /* 23417 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23418 * will be redefined without the chip prefix for easier programming. 23419 * If multiple chips will be programmed in the same source file, then you should 23420 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23421 * and refer to the fully qualified versions. 23422 */ 23423 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23424 23425 #define BG_CTRL29r BCMI_HURACAN_BG_CTRL29r 23426 #define BG_CTRL29r_SIZE BCMI_HURACAN_BG_CTRL29r_SIZE 23427 typedef BCMI_HURACAN_BG_CTRL29r_t BG_CTRL29r_t; 23428 #define BG_CTRL29r_CLR BCMI_HURACAN_BG_CTRL29r_CLR 23429 #define BG_CTRL29r_SET BCMI_HURACAN_BG_CTRL29r_SET 23430 #define BG_CTRL29r_GET BCMI_HURACAN_BG_CTRL29r_GET 23431 #define BG_CTRL29r_BG_R_SIGDET3_CNTRLf_GET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET3_CNTRLf_GET 23432 #define BG_CTRL29r_BG_R_SIGDET3_CNTRLf_SET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET3_CNTRLf_SET 23433 #define BG_CTRL29r_BG_R_SIGDET2_CNTRLf_GET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET2_CNTRLf_GET 23434 #define BG_CTRL29r_BG_R_SIGDET2_CNTRLf_SET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET2_CNTRLf_SET 23435 #define BG_CTRL29r_BG_R_SIGDET1_CNTRLf_GET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET1_CNTRLf_GET 23436 #define BG_CTRL29r_BG_R_SIGDET1_CNTRLf_SET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET1_CNTRLf_SET 23437 #define BG_CTRL29r_BG_R_SIGDET0_CNTRLf_GET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET0_CNTRLf_GET 23438 #define BG_CTRL29r_BG_R_SIGDET0_CNTRLf_SET BCMI_HURACAN_BG_CTRL29r_BG_R_SIGDET0_CNTRLf_SET 23439 #define READ_BG_CTRL29r BCMI_HURACAN_READ_BG_CTRL29r 23440 #define WRITE_BG_CTRL29r BCMI_HURACAN_WRITE_BG_CTRL29r 23441 #define MODIFY_BG_CTRL29r BCMI_HURACAN_MODIFY_BG_CTRL29r 23442 23443 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23444 /******************************************************************************* 23445 * End of 'BCMI_HURACAN_BG_CTRL29r' 23446 */ 23447 23448 23449 23450 23451 /******************************************************************************* 23452 * CHIP: BCMI_HURACAN 23453 * REGISTER: BG_CTRL30 23454 * BLOCKS: CTRL_QUAD_D 23455 * REGADDR: 0xb093 23456 * DEVAD: 1 23457 * DESC: control registers for AMS BG control bus 23458 * RESETVAL: 0x0 (0) 23459 * ACCESS: R/W 23460 * FIELDS: 23461 * BG_R_OSCOR0_CNTRL 23462 * BG_R_OSCOR1_CNTRL 23463 * BG_R_OSCOR2_CNTRL 23464 * BG_R_OSCOR3_CNTRL 23465 */ 23466 #define BCMI_HURACAN_BG_CTRL30r (0x0001b093 | PHYMOD_REG_ACC_RAW) 23467 23468 #define BCMI_HURACAN_BG_CTRL30r_SIZE 4 23469 23470 /* 23471 * This structure should be used to declare and program BG_CTRL30. 23472 */ 23473 typedef union BCMI_HURACAN_BG_CTRL30r_s { 23474 uint32_t v[1]; 23475 uint32_t bg_ctrl30[1]; 23476 uint32_t _bg_ctrl30; 23477 } BCMI_HURACAN_BG_CTRL30r_t; 23478 23479 #define BCMI_HURACAN_BG_CTRL30r_CLR(r) (r).bg_ctrl30[0] = 0 23480 #define BCMI_HURACAN_BG_CTRL30r_SET(r,d) (r).bg_ctrl30[0] = d 23481 #define BCMI_HURACAN_BG_CTRL30r_GET(r) (r).bg_ctrl30[0] 23482 23483 /* 23484 * These macros can be used to access individual fields. 23485 */ 23486 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR3_CNTRLf_GET(r) ((((r).bg_ctrl30[0]) >> 12) & 0xf) 23487 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR3_CNTRLf_SET(r,f) (r).bg_ctrl30[0]=(((r).bg_ctrl30[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 23488 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR2_CNTRLf_GET(r) ((((r).bg_ctrl30[0]) >> 8) & 0xf) 23489 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR2_CNTRLf_SET(r,f) (r).bg_ctrl30[0]=(((r).bg_ctrl30[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 23490 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR1_CNTRLf_GET(r) ((((r).bg_ctrl30[0]) >> 4) & 0xf) 23491 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR1_CNTRLf_SET(r,f) (r).bg_ctrl30[0]=(((r).bg_ctrl30[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23492 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR0_CNTRLf_GET(r) (((r).bg_ctrl30[0]) & 0xf) 23493 #define BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR0_CNTRLf_SET(r,f) (r).bg_ctrl30[0]=(((r).bg_ctrl30[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 23494 23495 /* 23496 * These macros can be used to access BG_CTRL30. 23497 */ 23498 #define BCMI_HURACAN_READ_BG_CTRL30r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL30r,_r._bg_ctrl30) 23499 #define BCMI_HURACAN_WRITE_BG_CTRL30r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL30r,_r._bg_ctrl30) 23500 23501 /* 23502 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23503 * will be redefined without the chip prefix for easier programming. 23504 * If multiple chips will be programmed in the same source file, then you should 23505 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23506 * and refer to the fully qualified versions. 23507 */ 23508 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23509 23510 #define BG_CTRL30r BCMI_HURACAN_BG_CTRL30r 23511 #define BG_CTRL30r_SIZE BCMI_HURACAN_BG_CTRL30r_SIZE 23512 typedef BCMI_HURACAN_BG_CTRL30r_t BG_CTRL30r_t; 23513 #define BG_CTRL30r_CLR BCMI_HURACAN_BG_CTRL30r_CLR 23514 #define BG_CTRL30r_SET BCMI_HURACAN_BG_CTRL30r_SET 23515 #define BG_CTRL30r_GET BCMI_HURACAN_BG_CTRL30r_GET 23516 #define BG_CTRL30r_BG_R_OSCOR3_CNTRLf_GET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR3_CNTRLf_GET 23517 #define BG_CTRL30r_BG_R_OSCOR3_CNTRLf_SET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR3_CNTRLf_SET 23518 #define BG_CTRL30r_BG_R_OSCOR2_CNTRLf_GET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR2_CNTRLf_GET 23519 #define BG_CTRL30r_BG_R_OSCOR2_CNTRLf_SET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR2_CNTRLf_SET 23520 #define BG_CTRL30r_BG_R_OSCOR1_CNTRLf_GET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR1_CNTRLf_GET 23521 #define BG_CTRL30r_BG_R_OSCOR1_CNTRLf_SET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR1_CNTRLf_SET 23522 #define BG_CTRL30r_BG_R_OSCOR0_CNTRLf_GET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR0_CNTRLf_GET 23523 #define BG_CTRL30r_BG_R_OSCOR0_CNTRLf_SET BCMI_HURACAN_BG_CTRL30r_BG_R_OSCOR0_CNTRLf_SET 23524 #define READ_BG_CTRL30r BCMI_HURACAN_READ_BG_CTRL30r 23525 #define WRITE_BG_CTRL30r BCMI_HURACAN_WRITE_BG_CTRL30r 23526 #define MODIFY_BG_CTRL30r BCMI_HURACAN_MODIFY_BG_CTRL30r 23527 23528 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23529 /******************************************************************************* 23530 * End of 'BCMI_HURACAN_BG_CTRL30r' 23531 */ 23532 23533 23534 23535 23536 /******************************************************************************* 23537 * CHIP: BCMI_HURACAN 23538 * REGISTER: BG_CTRL31 23539 * BLOCKS: CTRL_QUAD_D 23540 * REGADDR: 0xb094 23541 * DEVAD: 1 23542 * DESC: control registers for AMS BG control bus 23543 * RESETVAL: 0x0 (0) 23544 * ACCESS: R/W 23545 * FIELDS: 23546 * BG_R_CMGEN0_CNTRL 23547 * BG_R_CMGEN1_CNTRL 23548 * BG_R_CMGEN2_CNTRL 23549 * BG_R_CMGEN3_CNTRL 23550 */ 23551 #define BCMI_HURACAN_BG_CTRL31r (0x0001b094 | PHYMOD_REG_ACC_RAW) 23552 23553 #define BCMI_HURACAN_BG_CTRL31r_SIZE 4 23554 23555 /* 23556 * This structure should be used to declare and program BG_CTRL31. 23557 */ 23558 typedef union BCMI_HURACAN_BG_CTRL31r_s { 23559 uint32_t v[1]; 23560 uint32_t bg_ctrl31[1]; 23561 uint32_t _bg_ctrl31; 23562 } BCMI_HURACAN_BG_CTRL31r_t; 23563 23564 #define BCMI_HURACAN_BG_CTRL31r_CLR(r) (r).bg_ctrl31[0] = 0 23565 #define BCMI_HURACAN_BG_CTRL31r_SET(r,d) (r).bg_ctrl31[0] = d 23566 #define BCMI_HURACAN_BG_CTRL31r_GET(r) (r).bg_ctrl31[0] 23567 23568 /* 23569 * These macros can be used to access individual fields. 23570 */ 23571 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN3_CNTRLf_GET(r) ((((r).bg_ctrl31[0]) >> 12) & 0xf) 23572 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN3_CNTRLf_SET(r,f) (r).bg_ctrl31[0]=(((r).bg_ctrl31[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 23573 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN2_CNTRLf_GET(r) ((((r).bg_ctrl31[0]) >> 8) & 0xf) 23574 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN2_CNTRLf_SET(r,f) (r).bg_ctrl31[0]=(((r).bg_ctrl31[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 23575 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN1_CNTRLf_GET(r) ((((r).bg_ctrl31[0]) >> 4) & 0xf) 23576 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN1_CNTRLf_SET(r,f) (r).bg_ctrl31[0]=(((r).bg_ctrl31[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23577 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN0_CNTRLf_GET(r) (((r).bg_ctrl31[0]) & 0xf) 23578 #define BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN0_CNTRLf_SET(r,f) (r).bg_ctrl31[0]=(((r).bg_ctrl31[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 23579 23580 /* 23581 * These macros can be used to access BG_CTRL31. 23582 */ 23583 #define BCMI_HURACAN_READ_BG_CTRL31r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL31r,_r._bg_ctrl31) 23584 #define BCMI_HURACAN_WRITE_BG_CTRL31r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL31r,_r._bg_ctrl31) 23585 23586 /* 23587 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23588 * will be redefined without the chip prefix for easier programming. 23589 * If multiple chips will be programmed in the same source file, then you should 23590 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23591 * and refer to the fully qualified versions. 23592 */ 23593 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23594 23595 #define BG_CTRL31r BCMI_HURACAN_BG_CTRL31r 23596 #define BG_CTRL31r_SIZE BCMI_HURACAN_BG_CTRL31r_SIZE 23597 typedef BCMI_HURACAN_BG_CTRL31r_t BG_CTRL31r_t; 23598 #define BG_CTRL31r_CLR BCMI_HURACAN_BG_CTRL31r_CLR 23599 #define BG_CTRL31r_SET BCMI_HURACAN_BG_CTRL31r_SET 23600 #define BG_CTRL31r_GET BCMI_HURACAN_BG_CTRL31r_GET 23601 #define BG_CTRL31r_BG_R_CMGEN3_CNTRLf_GET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN3_CNTRLf_GET 23602 #define BG_CTRL31r_BG_R_CMGEN3_CNTRLf_SET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN3_CNTRLf_SET 23603 #define BG_CTRL31r_BG_R_CMGEN2_CNTRLf_GET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN2_CNTRLf_GET 23604 #define BG_CTRL31r_BG_R_CMGEN2_CNTRLf_SET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN2_CNTRLf_SET 23605 #define BG_CTRL31r_BG_R_CMGEN1_CNTRLf_GET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN1_CNTRLf_GET 23606 #define BG_CTRL31r_BG_R_CMGEN1_CNTRLf_SET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN1_CNTRLf_SET 23607 #define BG_CTRL31r_BG_R_CMGEN0_CNTRLf_GET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN0_CNTRLf_GET 23608 #define BG_CTRL31r_BG_R_CMGEN0_CNTRLf_SET BCMI_HURACAN_BG_CTRL31r_BG_R_CMGEN0_CNTRLf_SET 23609 #define READ_BG_CTRL31r BCMI_HURACAN_READ_BG_CTRL31r 23610 #define WRITE_BG_CTRL31r BCMI_HURACAN_WRITE_BG_CTRL31r 23611 #define MODIFY_BG_CTRL31r BCMI_HURACAN_MODIFY_BG_CTRL31r 23612 23613 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23614 /******************************************************************************* 23615 * End of 'BCMI_HURACAN_BG_CTRL31r' 23616 */ 23617 23618 23619 23620 23621 /******************************************************************************* 23622 * CHIP: BCMI_HURACAN 23623 * REGISTER: BG_CTRL32 23624 * BLOCKS: CTRL_QUAD_D 23625 * REGADDR: 0xb095 23626 * DEVAD: 1 23627 * DESC: control registers for AMS BG control bus 23628 * RESETVAL: 0x0 (0) 23629 * ACCESS: R/W 23630 * FIELDS: 23631 * PWRDN_BG 23632 * PWRDN_BG_R_MIRROR 23633 * PWRDN_PTAT_CALR_MIRROR 23634 * PWRDN_BG_CALR_MIRROR 23635 * BG_PON_FRC_VAL 23636 * BG_PON_FRC 23637 */ 23638 #define BCMI_HURACAN_BG_CTRL32r (0x0001b095 | PHYMOD_REG_ACC_RAW) 23639 23640 #define BCMI_HURACAN_BG_CTRL32r_SIZE 4 23641 23642 /* 23643 * This structure should be used to declare and program BG_CTRL32. 23644 */ 23645 typedef union BCMI_HURACAN_BG_CTRL32r_s { 23646 uint32_t v[1]; 23647 uint32_t bg_ctrl32[1]; 23648 uint32_t _bg_ctrl32; 23649 } BCMI_HURACAN_BG_CTRL32r_t; 23650 23651 #define BCMI_HURACAN_BG_CTRL32r_CLR(r) (r).bg_ctrl32[0] = 0 23652 #define BCMI_HURACAN_BG_CTRL32r_SET(r,d) (r).bg_ctrl32[0] = d 23653 #define BCMI_HURACAN_BG_CTRL32r_GET(r) (r).bg_ctrl32[0] 23654 23655 /* 23656 * These macros can be used to access individual fields. 23657 */ 23658 #define BCMI_HURACAN_BG_CTRL32r_BG_PON_FRCf_GET(r) ((((r).bg_ctrl32[0]) >> 8) & 0x1) 23659 #define BCMI_HURACAN_BG_CTRL32r_BG_PON_FRCf_SET(r,f) (r).bg_ctrl32[0]=(((r).bg_ctrl32[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 23660 #define BCMI_HURACAN_BG_CTRL32r_BG_PON_FRC_VALf_GET(r) ((((r).bg_ctrl32[0]) >> 4) & 0xf) 23661 #define BCMI_HURACAN_BG_CTRL32r_BG_PON_FRC_VALf_SET(r,f) (r).bg_ctrl32[0]=(((r).bg_ctrl32[0] & ~((uint32_t)0xf << 4)) | ((((uint32_t)f) & 0xf) << 4)) | (15 << (16 + 4)) 23662 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_CALR_MIRRORf_GET(r) ((((r).bg_ctrl32[0]) >> 3) & 0x1) 23663 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_CALR_MIRRORf_SET(r,f) (r).bg_ctrl32[0]=(((r).bg_ctrl32[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 23664 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_PTAT_CALR_MIRRORf_GET(r) ((((r).bg_ctrl32[0]) >> 2) & 0x1) 23665 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_PTAT_CALR_MIRRORf_SET(r,f) (r).bg_ctrl32[0]=(((r).bg_ctrl32[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 23666 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_R_MIRRORf_GET(r) ((((r).bg_ctrl32[0]) >> 1) & 0x1) 23667 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_R_MIRRORf_SET(r,f) (r).bg_ctrl32[0]=(((r).bg_ctrl32[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 23668 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_BGf_GET(r) (((r).bg_ctrl32[0]) & 0x1) 23669 #define BCMI_HURACAN_BG_CTRL32r_PWRDN_BGf_SET(r,f) (r).bg_ctrl32[0]=(((r).bg_ctrl32[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 23670 23671 /* 23672 * These macros can be used to access BG_CTRL32. 23673 */ 23674 #define BCMI_HURACAN_READ_BG_CTRL32r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL32r,_r._bg_ctrl32) 23675 #define BCMI_HURACAN_WRITE_BG_CTRL32r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL32r,_r._bg_ctrl32) 23676 23677 /* 23678 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23679 * will be redefined without the chip prefix for easier programming. 23680 * If multiple chips will be programmed in the same source file, then you should 23681 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23682 * and refer to the fully qualified versions. 23683 */ 23684 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23685 23686 #define BG_CTRL32r BCMI_HURACAN_BG_CTRL32r 23687 #define BG_CTRL32r_SIZE BCMI_HURACAN_BG_CTRL32r_SIZE 23688 typedef BCMI_HURACAN_BG_CTRL32r_t BG_CTRL32r_t; 23689 #define BG_CTRL32r_CLR BCMI_HURACAN_BG_CTRL32r_CLR 23690 #define BG_CTRL32r_SET BCMI_HURACAN_BG_CTRL32r_SET 23691 #define BG_CTRL32r_GET BCMI_HURACAN_BG_CTRL32r_GET 23692 #define BG_CTRL32r_BG_PON_FRCf_GET BCMI_HURACAN_BG_CTRL32r_BG_PON_FRCf_GET 23693 #define BG_CTRL32r_BG_PON_FRCf_SET BCMI_HURACAN_BG_CTRL32r_BG_PON_FRCf_SET 23694 #define BG_CTRL32r_BG_PON_FRC_VALf_GET BCMI_HURACAN_BG_CTRL32r_BG_PON_FRC_VALf_GET 23695 #define BG_CTRL32r_BG_PON_FRC_VALf_SET BCMI_HURACAN_BG_CTRL32r_BG_PON_FRC_VALf_SET 23696 #define BG_CTRL32r_PWRDN_BG_CALR_MIRRORf_GET BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_CALR_MIRRORf_GET 23697 #define BG_CTRL32r_PWRDN_BG_CALR_MIRRORf_SET BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_CALR_MIRRORf_SET 23698 #define BG_CTRL32r_PWRDN_PTAT_CALR_MIRRORf_GET BCMI_HURACAN_BG_CTRL32r_PWRDN_PTAT_CALR_MIRRORf_GET 23699 #define BG_CTRL32r_PWRDN_PTAT_CALR_MIRRORf_SET BCMI_HURACAN_BG_CTRL32r_PWRDN_PTAT_CALR_MIRRORf_SET 23700 #define BG_CTRL32r_PWRDN_BG_R_MIRRORf_GET BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_R_MIRRORf_GET 23701 #define BG_CTRL32r_PWRDN_BG_R_MIRRORf_SET BCMI_HURACAN_BG_CTRL32r_PWRDN_BG_R_MIRRORf_SET 23702 #define BG_CTRL32r_PWRDN_BGf_GET BCMI_HURACAN_BG_CTRL32r_PWRDN_BGf_GET 23703 #define BG_CTRL32r_PWRDN_BGf_SET BCMI_HURACAN_BG_CTRL32r_PWRDN_BGf_SET 23704 #define READ_BG_CTRL32r BCMI_HURACAN_READ_BG_CTRL32r 23705 #define WRITE_BG_CTRL32r BCMI_HURACAN_WRITE_BG_CTRL32r 23706 #define MODIFY_BG_CTRL32r BCMI_HURACAN_MODIFY_BG_CTRL32r 23707 23708 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23709 /******************************************************************************* 23710 * End of 'BCMI_HURACAN_BG_CTRL32r' 23711 */ 23712 23713 23714 23715 23716 /******************************************************************************* 23717 * CHIP: BCMI_HURACAN 23718 * REGISTER: REF_CTRL33 23719 * BLOCKS: CTRL_QUAD_D 23720 * REGADDR: 0xb096 23721 * DEVAD: 1 23722 * DESC: control registers for AMS REF clock control bus 23723 * RESETVAL: 0x0 (0) 23724 * ACCESS: R/W 23725 * FIELDS: 23726 * REFC_RESERVED_FOR_47_TO_32 23727 */ 23728 #define BCMI_HURACAN_REF_CTRL33r (0x0001b096 | PHYMOD_REG_ACC_RAW) 23729 23730 #define BCMI_HURACAN_REF_CTRL33r_SIZE 4 23731 23732 /* 23733 * This structure should be used to declare and program REF_CTRL33. 23734 */ 23735 typedef union BCMI_HURACAN_REF_CTRL33r_s { 23736 uint32_t v[1]; 23737 uint32_t ref_ctrl33[1]; 23738 uint32_t _ref_ctrl33; 23739 } BCMI_HURACAN_REF_CTRL33r_t; 23740 23741 #define BCMI_HURACAN_REF_CTRL33r_CLR(r) (r).ref_ctrl33[0] = 0 23742 #define BCMI_HURACAN_REF_CTRL33r_SET(r,d) (r).ref_ctrl33[0] = d 23743 #define BCMI_HURACAN_REF_CTRL33r_GET(r) (r).ref_ctrl33[0] 23744 23745 /* 23746 * These macros can be used to access individual fields. 23747 */ 23748 #define BCMI_HURACAN_REF_CTRL33r_REFC_RESERVED_FOR_47_TO_32f_GET(r) (((r).ref_ctrl33[0]) & 0xffff) 23749 #define BCMI_HURACAN_REF_CTRL33r_REFC_RESERVED_FOR_47_TO_32f_SET(r,f) (r).ref_ctrl33[0]=(((r).ref_ctrl33[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 23750 23751 /* 23752 * These macros can be used to access REF_CTRL33. 23753 */ 23754 #define BCMI_HURACAN_READ_REF_CTRL33r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_REF_CTRL33r,_r._ref_ctrl33) 23755 #define BCMI_HURACAN_WRITE_REF_CTRL33r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_REF_CTRL33r,_r._ref_ctrl33) 23756 23757 /* 23758 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23759 * will be redefined without the chip prefix for easier programming. 23760 * If multiple chips will be programmed in the same source file, then you should 23761 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23762 * and refer to the fully qualified versions. 23763 */ 23764 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23765 23766 #define REF_CTRL33r BCMI_HURACAN_REF_CTRL33r 23767 #define REF_CTRL33r_SIZE BCMI_HURACAN_REF_CTRL33r_SIZE 23768 typedef BCMI_HURACAN_REF_CTRL33r_t REF_CTRL33r_t; 23769 #define REF_CTRL33r_CLR BCMI_HURACAN_REF_CTRL33r_CLR 23770 #define REF_CTRL33r_SET BCMI_HURACAN_REF_CTRL33r_SET 23771 #define REF_CTRL33r_GET BCMI_HURACAN_REF_CTRL33r_GET 23772 #define REF_CTRL33r_REFC_RESERVED_FOR_47_TO_32f_GET BCMI_HURACAN_REF_CTRL33r_REFC_RESERVED_FOR_47_TO_32f_GET 23773 #define REF_CTRL33r_REFC_RESERVED_FOR_47_TO_32f_SET BCMI_HURACAN_REF_CTRL33r_REFC_RESERVED_FOR_47_TO_32f_SET 23774 #define READ_REF_CTRL33r BCMI_HURACAN_READ_REF_CTRL33r 23775 #define WRITE_REF_CTRL33r BCMI_HURACAN_WRITE_REF_CTRL33r 23776 #define MODIFY_REF_CTRL33r BCMI_HURACAN_MODIFY_REF_CTRL33r 23777 23778 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23779 /******************************************************************************* 23780 * End of 'BCMI_HURACAN_REF_CTRL33r' 23781 */ 23782 23783 23784 23785 23786 /******************************************************************************* 23787 * CHIP: BCMI_HURACAN 23788 * REGISTER: REF_CTRL34 23789 * BLOCKS: CTRL_QUAD_D 23790 * REGADDR: 0xb097 23791 * DEVAD: 1 23792 * DESC: control registers for AMS REF clock control bus 23793 * RESETVAL: 0x0 (0) 23794 * ACCESS: R/W 23795 * FIELDS: 23796 * I_OSC_CNTRL_1_TO_0 23797 * I_OSC_CNTRL_3_TO_2 23798 * REFC_RESERVED_FOR_31_TO_20 23799 */ 23800 #define BCMI_HURACAN_REF_CTRL34r (0x0001b097 | PHYMOD_REG_ACC_RAW) 23801 23802 #define BCMI_HURACAN_REF_CTRL34r_SIZE 4 23803 23804 /* 23805 * This structure should be used to declare and program REF_CTRL34. 23806 */ 23807 typedef union BCMI_HURACAN_REF_CTRL34r_s { 23808 uint32_t v[1]; 23809 uint32_t ref_ctrl34[1]; 23810 uint32_t _ref_ctrl34; 23811 } BCMI_HURACAN_REF_CTRL34r_t; 23812 23813 #define BCMI_HURACAN_REF_CTRL34r_CLR(r) (r).ref_ctrl34[0] = 0 23814 #define BCMI_HURACAN_REF_CTRL34r_SET(r,d) (r).ref_ctrl34[0] = d 23815 #define BCMI_HURACAN_REF_CTRL34r_GET(r) (r).ref_ctrl34[0] 23816 23817 /* 23818 * These macros can be used to access individual fields. 23819 */ 23820 #define BCMI_HURACAN_REF_CTRL34r_REFC_RESERVED_FOR_31_TO_20f_GET(r) ((((r).ref_ctrl34[0]) >> 4) & 0xfff) 23821 #define BCMI_HURACAN_REF_CTRL34r_REFC_RESERVED_FOR_31_TO_20f_SET(r,f) (r).ref_ctrl34[0]=(((r).ref_ctrl34[0] & ~((uint32_t)0xfff << 4)) | ((((uint32_t)f) & 0xfff) << 4)) | (4095 << (16 + 4)) 23822 #define BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_3_TO_2f_GET(r) ((((r).ref_ctrl34[0]) >> 2) & 0x3) 23823 #define BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_3_TO_2f_SET(r,f) (r).ref_ctrl34[0]=(((r).ref_ctrl34[0] & ~((uint32_t)0x3 << 2)) | ((((uint32_t)f) & 0x3) << 2)) | (3 << (16 + 2)) 23824 #define BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_1_TO_0f_GET(r) (((r).ref_ctrl34[0]) & 0x3) 23825 #define BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_1_TO_0f_SET(r,f) (r).ref_ctrl34[0]=(((r).ref_ctrl34[0] & ~((uint32_t)0x3)) | (((uint32_t)f) & 0x3)) | (0x3 << 16) 23826 23827 /* 23828 * These macros can be used to access REF_CTRL34. 23829 */ 23830 #define BCMI_HURACAN_READ_REF_CTRL34r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_REF_CTRL34r,_r._ref_ctrl34) 23831 #define BCMI_HURACAN_WRITE_REF_CTRL34r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_REF_CTRL34r,_r._ref_ctrl34) 23832 23833 /* 23834 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23835 * will be redefined without the chip prefix for easier programming. 23836 * If multiple chips will be programmed in the same source file, then you should 23837 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23838 * and refer to the fully qualified versions. 23839 */ 23840 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23841 23842 #define REF_CTRL34r BCMI_HURACAN_REF_CTRL34r 23843 #define REF_CTRL34r_SIZE BCMI_HURACAN_REF_CTRL34r_SIZE 23844 typedef BCMI_HURACAN_REF_CTRL34r_t REF_CTRL34r_t; 23845 #define REF_CTRL34r_CLR BCMI_HURACAN_REF_CTRL34r_CLR 23846 #define REF_CTRL34r_SET BCMI_HURACAN_REF_CTRL34r_SET 23847 #define REF_CTRL34r_GET BCMI_HURACAN_REF_CTRL34r_GET 23848 #define REF_CTRL34r_REFC_RESERVED_FOR_31_TO_20f_GET BCMI_HURACAN_REF_CTRL34r_REFC_RESERVED_FOR_31_TO_20f_GET 23849 #define REF_CTRL34r_REFC_RESERVED_FOR_31_TO_20f_SET BCMI_HURACAN_REF_CTRL34r_REFC_RESERVED_FOR_31_TO_20f_SET 23850 #define REF_CTRL34r_I_OSC_CNTRL_3_TO_2f_GET BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_3_TO_2f_GET 23851 #define REF_CTRL34r_I_OSC_CNTRL_3_TO_2f_SET BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_3_TO_2f_SET 23852 #define REF_CTRL34r_I_OSC_CNTRL_1_TO_0f_GET BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_1_TO_0f_GET 23853 #define REF_CTRL34r_I_OSC_CNTRL_1_TO_0f_SET BCMI_HURACAN_REF_CTRL34r_I_OSC_CNTRL_1_TO_0f_SET 23854 #define READ_REF_CTRL34r BCMI_HURACAN_READ_REF_CTRL34r 23855 #define WRITE_REF_CTRL34r BCMI_HURACAN_WRITE_REF_CTRL34r 23856 #define MODIFY_REF_CTRL34r BCMI_HURACAN_MODIFY_REF_CTRL34r 23857 23858 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23859 /******************************************************************************* 23860 * End of 'BCMI_HURACAN_REF_CTRL34r' 23861 */ 23862 23863 23864 23865 23866 /******************************************************************************* 23867 * CHIP: BCMI_HURACAN 23868 * REGISTER: REF_CTRL35 23869 * BLOCKS: CTRL_QUAD_D 23870 * REGADDR: 0xb098 23871 * DEVAD: 1 23872 * DESC: control registers for AMS REF clock control bus 23873 * RESETVAL: 0x0 (0) 23874 * ACCESS: R/W 23875 * FIELDS: 23876 * REFC_RESERVED_FOR_15_TO_10 23877 */ 23878 #define BCMI_HURACAN_REF_CTRL35r (0x0001b098 | PHYMOD_REG_ACC_RAW) 23879 23880 #define BCMI_HURACAN_REF_CTRL35r_SIZE 4 23881 23882 /* 23883 * This structure should be used to declare and program REF_CTRL35. 23884 */ 23885 typedef union BCMI_HURACAN_REF_CTRL35r_s { 23886 uint32_t v[1]; 23887 uint32_t ref_ctrl35[1]; 23888 uint32_t _ref_ctrl35; 23889 } BCMI_HURACAN_REF_CTRL35r_t; 23890 23891 #define BCMI_HURACAN_REF_CTRL35r_CLR(r) (r).ref_ctrl35[0] = 0 23892 #define BCMI_HURACAN_REF_CTRL35r_SET(r,d) (r).ref_ctrl35[0] = d 23893 #define BCMI_HURACAN_REF_CTRL35r_GET(r) (r).ref_ctrl35[0] 23894 23895 /* 23896 * These macros can be used to access individual fields. 23897 */ 23898 #define BCMI_HURACAN_REF_CTRL35r_REFC_RESERVED_FOR_15_TO_10f_GET(r) (((r).ref_ctrl35[0]) & 0x3f) 23899 #define BCMI_HURACAN_REF_CTRL35r_REFC_RESERVED_FOR_15_TO_10f_SET(r,f) (r).ref_ctrl35[0]=(((r).ref_ctrl35[0] & ~((uint32_t)0x3f)) | (((uint32_t)f) & 0x3f)) | (0x3f << 16) 23900 23901 /* 23902 * These macros can be used to access REF_CTRL35. 23903 */ 23904 #define BCMI_HURACAN_READ_REF_CTRL35r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_REF_CTRL35r,_r._ref_ctrl35) 23905 #define BCMI_HURACAN_WRITE_REF_CTRL35r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_REF_CTRL35r,_r._ref_ctrl35) 23906 23907 /* 23908 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23909 * will be redefined without the chip prefix for easier programming. 23910 * If multiple chips will be programmed in the same source file, then you should 23911 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23912 * and refer to the fully qualified versions. 23913 */ 23914 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23915 23916 #define REF_CTRL35r BCMI_HURACAN_REF_CTRL35r 23917 #define REF_CTRL35r_SIZE BCMI_HURACAN_REF_CTRL35r_SIZE 23918 typedef BCMI_HURACAN_REF_CTRL35r_t REF_CTRL35r_t; 23919 #define REF_CTRL35r_CLR BCMI_HURACAN_REF_CTRL35r_CLR 23920 #define REF_CTRL35r_SET BCMI_HURACAN_REF_CTRL35r_SET 23921 #define REF_CTRL35r_GET BCMI_HURACAN_REF_CTRL35r_GET 23922 #define REF_CTRL35r_REFC_RESERVED_FOR_15_TO_10f_GET BCMI_HURACAN_REF_CTRL35r_REFC_RESERVED_FOR_15_TO_10f_GET 23923 #define REF_CTRL35r_REFC_RESERVED_FOR_15_TO_10f_SET BCMI_HURACAN_REF_CTRL35r_REFC_RESERVED_FOR_15_TO_10f_SET 23924 #define READ_REF_CTRL35r BCMI_HURACAN_READ_REF_CTRL35r 23925 #define WRITE_REF_CTRL35r BCMI_HURACAN_WRITE_REF_CTRL35r 23926 #define MODIFY_REF_CTRL35r BCMI_HURACAN_MODIFY_REF_CTRL35r 23927 23928 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 23929 /******************************************************************************* 23930 * End of 'BCMI_HURACAN_REF_CTRL35r' 23931 */ 23932 23933 23934 23935 23936 /******************************************************************************* 23937 * CHIP: BCMI_HURACAN 23938 * REGISTER: REF_CTRL36 23939 * BLOCKS: CTRL_QUAD_D 23940 * REGADDR: 0xb099 23941 * DEVAD: 1 23942 * DESC: control registers for AMS REF clock control bus 23943 * RESETVAL: 0x0 (0) 23944 * ACCESS: R/W 23945 * FIELDS: 23946 * REFCLK_IN_BIAS 23947 * TEST_SEL 23948 * TEST_AMP 23949 * I_PD_INTERNAL_OSC 23950 * I_PD_EXTERNAL_REFCLK 23951 */ 23952 #define BCMI_HURACAN_REF_CTRL36r (0x0001b099 | PHYMOD_REG_ACC_RAW) 23953 23954 #define BCMI_HURACAN_REF_CTRL36r_SIZE 4 23955 23956 /* 23957 * This structure should be used to declare and program REF_CTRL36. 23958 */ 23959 typedef union BCMI_HURACAN_REF_CTRL36r_s { 23960 uint32_t v[1]; 23961 uint32_t ref_ctrl36[1]; 23962 uint32_t _ref_ctrl36; 23963 } BCMI_HURACAN_REF_CTRL36r_t; 23964 23965 #define BCMI_HURACAN_REF_CTRL36r_CLR(r) (r).ref_ctrl36[0] = 0 23966 #define BCMI_HURACAN_REF_CTRL36r_SET(r,d) (r).ref_ctrl36[0] = d 23967 #define BCMI_HURACAN_REF_CTRL36r_GET(r) (r).ref_ctrl36[0] 23968 23969 /* 23970 * These macros can be used to access individual fields. 23971 */ 23972 #define BCMI_HURACAN_REF_CTRL36r_I_PD_EXTERNAL_REFCLKf_GET(r) ((((r).ref_ctrl36[0]) >> 14) & 0x1) 23973 #define BCMI_HURACAN_REF_CTRL36r_I_PD_EXTERNAL_REFCLKf_SET(r,f) (r).ref_ctrl36[0]=(((r).ref_ctrl36[0] & ~((uint32_t)0x1 << 14)) | ((((uint32_t)f) & 0x1) << 14)) | (1 << (16 + 14)) 23974 #define BCMI_HURACAN_REF_CTRL36r_I_PD_INTERNAL_OSCf_GET(r) ((((r).ref_ctrl36[0]) >> 13) & 0x1) 23975 #define BCMI_HURACAN_REF_CTRL36r_I_PD_INTERNAL_OSCf_SET(r,f) (r).ref_ctrl36[0]=(((r).ref_ctrl36[0] & ~((uint32_t)0x1 << 13)) | ((((uint32_t)f) & 0x1) << 13)) | (1 << (16 + 13)) 23976 #define BCMI_HURACAN_REF_CTRL36r_TEST_AMPf_GET(r) ((((r).ref_ctrl36[0]) >> 12) & 0x1) 23977 #define BCMI_HURACAN_REF_CTRL36r_TEST_AMPf_SET(r,f) (r).ref_ctrl36[0]=(((r).ref_ctrl36[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 23978 #define BCMI_HURACAN_REF_CTRL36r_TEST_SELf_GET(r) ((((r).ref_ctrl36[0]) >> 8) & 0x7) 23979 #define BCMI_HURACAN_REF_CTRL36r_TEST_SELf_SET(r,f) (r).ref_ctrl36[0]=(((r).ref_ctrl36[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 23980 #define BCMI_HURACAN_REF_CTRL36r_REFCLK_IN_BIASf_GET(r) (((r).ref_ctrl36[0]) & 0x3f) 23981 #define BCMI_HURACAN_REF_CTRL36r_REFCLK_IN_BIASf_SET(r,f) (r).ref_ctrl36[0]=(((r).ref_ctrl36[0] & ~((uint32_t)0x3f)) | (((uint32_t)f) & 0x3f)) | (0x3f << 16) 23982 23983 /* 23984 * These macros can be used to access REF_CTRL36. 23985 */ 23986 #define BCMI_HURACAN_READ_REF_CTRL36r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_REF_CTRL36r,_r._ref_ctrl36) 23987 #define BCMI_HURACAN_WRITE_REF_CTRL36r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_REF_CTRL36r,_r._ref_ctrl36) 23988 23989 /* 23990 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 23991 * will be redefined without the chip prefix for easier programming. 23992 * If multiple chips will be programmed in the same source file, then you should 23993 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 23994 * and refer to the fully qualified versions. 23995 */ 23996 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 23997 23998 #define REF_CTRL36r BCMI_HURACAN_REF_CTRL36r 23999 #define REF_CTRL36r_SIZE BCMI_HURACAN_REF_CTRL36r_SIZE 24000 typedef BCMI_HURACAN_REF_CTRL36r_t REF_CTRL36r_t; 24001 #define REF_CTRL36r_CLR BCMI_HURACAN_REF_CTRL36r_CLR 24002 #define REF_CTRL36r_SET BCMI_HURACAN_REF_CTRL36r_SET 24003 #define REF_CTRL36r_GET BCMI_HURACAN_REF_CTRL36r_GET 24004 #define REF_CTRL36r_I_PD_EXTERNAL_REFCLKf_GET BCMI_HURACAN_REF_CTRL36r_I_PD_EXTERNAL_REFCLKf_GET 24005 #define REF_CTRL36r_I_PD_EXTERNAL_REFCLKf_SET BCMI_HURACAN_REF_CTRL36r_I_PD_EXTERNAL_REFCLKf_SET 24006 #define REF_CTRL36r_I_PD_INTERNAL_OSCf_GET BCMI_HURACAN_REF_CTRL36r_I_PD_INTERNAL_OSCf_GET 24007 #define REF_CTRL36r_I_PD_INTERNAL_OSCf_SET BCMI_HURACAN_REF_CTRL36r_I_PD_INTERNAL_OSCf_SET 24008 #define REF_CTRL36r_TEST_AMPf_GET BCMI_HURACAN_REF_CTRL36r_TEST_AMPf_GET 24009 #define REF_CTRL36r_TEST_AMPf_SET BCMI_HURACAN_REF_CTRL36r_TEST_AMPf_SET 24010 #define REF_CTRL36r_TEST_SELf_GET BCMI_HURACAN_REF_CTRL36r_TEST_SELf_GET 24011 #define REF_CTRL36r_TEST_SELf_SET BCMI_HURACAN_REF_CTRL36r_TEST_SELf_SET 24012 #define REF_CTRL36r_REFCLK_IN_BIASf_GET BCMI_HURACAN_REF_CTRL36r_REFCLK_IN_BIASf_GET 24013 #define REF_CTRL36r_REFCLK_IN_BIASf_SET BCMI_HURACAN_REF_CTRL36r_REFCLK_IN_BIASf_SET 24014 #define READ_REF_CTRL36r BCMI_HURACAN_READ_REF_CTRL36r 24015 #define WRITE_REF_CTRL36r BCMI_HURACAN_WRITE_REF_CTRL36r 24016 #define MODIFY_REF_CTRL36r BCMI_HURACAN_MODIFY_REF_CTRL36r 24017 24018 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24019 /******************************************************************************* 24020 * End of 'BCMI_HURACAN_REF_CTRL36r' 24021 */ 24022 24023 24024 24025 24026 /******************************************************************************* 24027 * CHIP: BCMI_HURACAN 24028 * REGISTER: BG_CTRL37 24029 * BLOCKS: CTRL_QUAD_D 24030 * REGADDR: 0xb09a 24031 * DEVAD: 1 24032 * DESC: control registers for AMS BG control bus 24033 * RESETVAL: 0x0 (0) 24034 * ACCESS: R/W 24035 * FIELDS: 24036 * BG_RESERVED_FOR_239_TO_234 24037 */ 24038 #define BCMI_HURACAN_BG_CTRL37r (0x0001b09a | PHYMOD_REG_ACC_RAW) 24039 24040 #define BCMI_HURACAN_BG_CTRL37r_SIZE 4 24041 24042 /* 24043 * This structure should be used to declare and program BG_CTRL37. 24044 */ 24045 typedef union BCMI_HURACAN_BG_CTRL37r_s { 24046 uint32_t v[1]; 24047 uint32_t bg_ctrl37[1]; 24048 uint32_t _bg_ctrl37; 24049 } BCMI_HURACAN_BG_CTRL37r_t; 24050 24051 #define BCMI_HURACAN_BG_CTRL37r_CLR(r) (r).bg_ctrl37[0] = 0 24052 #define BCMI_HURACAN_BG_CTRL37r_SET(r,d) (r).bg_ctrl37[0] = d 24053 #define BCMI_HURACAN_BG_CTRL37r_GET(r) (r).bg_ctrl37[0] 24054 24055 /* 24056 * These macros can be used to access individual fields. 24057 */ 24058 #define BCMI_HURACAN_BG_CTRL37r_BG_RESERVED_FOR_239_TO_234f_GET(r) (((r).bg_ctrl37[0]) & 0x3f) 24059 #define BCMI_HURACAN_BG_CTRL37r_BG_RESERVED_FOR_239_TO_234f_SET(r,f) (r).bg_ctrl37[0]=(((r).bg_ctrl37[0] & ~((uint32_t)0x3f)) | (((uint32_t)f) & 0x3f)) | (0x3f << 16) 24060 24061 /* 24062 * These macros can be used to access BG_CTRL37. 24063 */ 24064 #define BCMI_HURACAN_READ_BG_CTRL37r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_BG_CTRL37r,_r._bg_ctrl37) 24065 #define BCMI_HURACAN_WRITE_BG_CTRL37r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_BG_CTRL37r,_r._bg_ctrl37) 24066 24067 /* 24068 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24069 * will be redefined without the chip prefix for easier programming. 24070 * If multiple chips will be programmed in the same source file, then you should 24071 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24072 * and refer to the fully qualified versions. 24073 */ 24074 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24075 24076 #define BG_CTRL37r BCMI_HURACAN_BG_CTRL37r 24077 #define BG_CTRL37r_SIZE BCMI_HURACAN_BG_CTRL37r_SIZE 24078 typedef BCMI_HURACAN_BG_CTRL37r_t BG_CTRL37r_t; 24079 #define BG_CTRL37r_CLR BCMI_HURACAN_BG_CTRL37r_CLR 24080 #define BG_CTRL37r_SET BCMI_HURACAN_BG_CTRL37r_SET 24081 #define BG_CTRL37r_GET BCMI_HURACAN_BG_CTRL37r_GET 24082 #define BG_CTRL37r_BG_RESERVED_FOR_239_TO_234f_GET BCMI_HURACAN_BG_CTRL37r_BG_RESERVED_FOR_239_TO_234f_GET 24083 #define BG_CTRL37r_BG_RESERVED_FOR_239_TO_234f_SET BCMI_HURACAN_BG_CTRL37r_BG_RESERVED_FOR_239_TO_234f_SET 24084 #define READ_BG_CTRL37r BCMI_HURACAN_READ_BG_CTRL37r 24085 #define WRITE_BG_CTRL37r BCMI_HURACAN_WRITE_BG_CTRL37r 24086 #define MODIFY_BG_CTRL37r BCMI_HURACAN_MODIFY_BG_CTRL37r 24087 24088 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24089 /******************************************************************************* 24090 * End of 'BCMI_HURACAN_BG_CTRL37r' 24091 */ 24092 24093 24094 24095 24096 /******************************************************************************* 24097 * CHIP: BCMI_HURACAN 24098 * REGISTER: ANA_LANE_0_QUAD_D_CTRL0 24099 * BLOCKS: ANA_LANE_0_QUAD_D 24100 * REGADDR: 0xb100 24101 * DEVAD: 1 24102 * DESC: control registers 0 24103 * RESETVAL: 0x0 (0) 24104 * ACCESS: R/W 24105 * FIELDS: 24106 * RXTX_PWRDN 24107 * RX_SIGDET_BYPASS 24108 * RX_SIGDET_PWRDN 24109 * RX_SIGDECT_12GMODE 24110 * DC_COUPLE 24111 */ 24112 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r (0x0001b100 | PHYMOD_REG_ACC_RAW) 24113 24114 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_SIZE 4 24115 24116 /* 24117 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL0. 24118 */ 24119 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_s { 24120 uint32_t v[1]; 24121 uint32_t ana_lane_0_quad_d_ctrl0[1]; 24122 uint32_t _ana_lane_0_quad_d_ctrl0; 24123 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_t; 24124 24125 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_CLR(r) (r).ana_lane_0_quad_d_ctrl0[0] = 0 24126 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_SET(r,d) (r).ana_lane_0_quad_d_ctrl0[0] = d 24127 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_GET(r) (r).ana_lane_0_quad_d_ctrl0[0] 24128 24129 /* 24130 * These macros can be used to access individual fields. 24131 */ 24132 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_0_quad_d_ctrl0[0]) >> 4) & 0x1) 24133 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_0_quad_d_ctrl0[0]=(((r).ana_lane_0_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 24134 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_0_quad_d_ctrl0[0]) >> 3) & 0x1) 24135 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_0_quad_d_ctrl0[0]=(((r).ana_lane_0_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 24136 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_0_quad_d_ctrl0[0]) >> 2) & 0x1) 24137 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_0_quad_d_ctrl0[0]=(((r).ana_lane_0_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 24138 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_0_quad_d_ctrl0[0]) >> 1) & 0x1) 24139 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_0_quad_d_ctrl0[0]=(((r).ana_lane_0_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 24140 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_0_quad_d_ctrl0[0]) & 0x1) 24141 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_0_quad_d_ctrl0[0]=(((r).ana_lane_0_quad_d_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 24142 24143 /* 24144 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL0. 24145 */ 24146 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r,_r._ana_lane_0_quad_d_ctrl0) 24147 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r,_r._ana_lane_0_quad_d_ctrl0) 24148 24149 /* 24150 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24151 * will be redefined without the chip prefix for easier programming. 24152 * If multiple chips will be programmed in the same source file, then you should 24153 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24154 * and refer to the fully qualified versions. 24155 */ 24156 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24157 24158 #define ANA_LANE_0_QUAD_D_CTRL0r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r 24159 #define ANA_LANE_0_QUAD_D_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_SIZE 24160 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_t ANA_LANE_0_QUAD_D_CTRL0r_t; 24161 #define ANA_LANE_0_QUAD_D_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_CLR 24162 #define ANA_LANE_0_QUAD_D_CTRL0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_SET 24163 #define ANA_LANE_0_QUAD_D_CTRL0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_GET 24164 #define ANA_LANE_0_QUAD_D_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_DC_COUPLEf_GET 24165 #define ANA_LANE_0_QUAD_D_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_DC_COUPLEf_SET 24166 #define ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET 24167 #define ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET 24168 #define ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET 24169 #define ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET 24170 #define ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET 24171 #define ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET 24172 #define ANA_LANE_0_QUAD_D_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RXTX_PWRDNf_GET 24173 #define ANA_LANE_0_QUAD_D_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r_RXTX_PWRDNf_SET 24174 #define READ_ANA_LANE_0_QUAD_D_CTRL0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL0r 24175 #define WRITE_ANA_LANE_0_QUAD_D_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL0r 24176 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL0r 24177 24178 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24179 /******************************************************************************* 24180 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL0r' 24181 */ 24182 24183 24184 24185 24186 /******************************************************************************* 24187 * CHIP: BCMI_HURACAN 24188 * REGISTER: ANA_LANE_0_QUAD_D_CTRL1 24189 * BLOCKS: ANA_LANE_0_QUAD_D 24190 * REGADDR: 0xb101 24191 * DEVAD: 1 24192 * DESC: control registers 0 24193 * RESETVAL: 0x0 (0) 24194 * ACCESS: R/W 24195 * FIELDS: 24196 * RX_SIGDET_THRESHOLD 24197 * REF_OCL 24198 * OCL_PWRDN 24199 * OCL_DISABLE_LOOP 24200 * RXTX_RESERVED_FOR_15_12 24201 */ 24202 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r (0x0001b101 | PHYMOD_REG_ACC_RAW) 24203 24204 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_SIZE 4 24205 24206 /* 24207 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL1. 24208 */ 24209 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_s { 24210 uint32_t v[1]; 24211 uint32_t ana_lane_0_quad_d_ctrl1[1]; 24212 uint32_t _ana_lane_0_quad_d_ctrl1; 24213 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_t; 24214 24215 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_CLR(r) (r).ana_lane_0_quad_d_ctrl1[0] = 0 24216 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_SET(r,d) (r).ana_lane_0_quad_d_ctrl1[0] = d 24217 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_GET(r) (r).ana_lane_0_quad_d_ctrl1[0] 24218 24219 /* 24220 * These macros can be used to access individual fields. 24221 */ 24222 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_0_quad_d_ctrl1[0]) >> 12) & 0xf) 24223 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_0_quad_d_ctrl1[0]=(((r).ana_lane_0_quad_d_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 24224 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_0_quad_d_ctrl1[0]) >> 9) & 0x1) 24225 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_0_quad_d_ctrl1[0]=(((r).ana_lane_0_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 24226 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_0_quad_d_ctrl1[0]) >> 8) & 0x1) 24227 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_0_quad_d_ctrl1[0]=(((r).ana_lane_0_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 24228 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_0_quad_d_ctrl1[0]) >> 4) & 0x3) 24229 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_0_quad_d_ctrl1[0]=(((r).ana_lane_0_quad_d_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 24230 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_0_quad_d_ctrl1[0]) & 0x7) 24231 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_0_quad_d_ctrl1[0]=(((r).ana_lane_0_quad_d_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 24232 24233 /* 24234 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL1. 24235 */ 24236 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r,_r._ana_lane_0_quad_d_ctrl1) 24237 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r,_r._ana_lane_0_quad_d_ctrl1) 24238 24239 /* 24240 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24241 * will be redefined without the chip prefix for easier programming. 24242 * If multiple chips will be programmed in the same source file, then you should 24243 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24244 * and refer to the fully qualified versions. 24245 */ 24246 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24247 24248 #define ANA_LANE_0_QUAD_D_CTRL1r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r 24249 #define ANA_LANE_0_QUAD_D_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_SIZE 24250 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_t ANA_LANE_0_QUAD_D_CTRL1r_t; 24251 #define ANA_LANE_0_QUAD_D_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_CLR 24252 #define ANA_LANE_0_QUAD_D_CTRL1r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_SET 24253 #define ANA_LANE_0_QUAD_D_CTRL1r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_GET 24254 #define ANA_LANE_0_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 24255 #define ANA_LANE_0_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 24256 #define ANA_LANE_0_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET 24257 #define ANA_LANE_0_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET 24258 #define ANA_LANE_0_QUAD_D_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_PWRDNf_GET 24259 #define ANA_LANE_0_QUAD_D_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_OCL_PWRDNf_SET 24260 #define ANA_LANE_0_QUAD_D_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_REF_OCLf_GET 24261 #define ANA_LANE_0_QUAD_D_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_REF_OCLf_SET 24262 #define ANA_LANE_0_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET 24263 #define ANA_LANE_0_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET 24264 #define READ_ANA_LANE_0_QUAD_D_CTRL1r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL1r 24265 #define WRITE_ANA_LANE_0_QUAD_D_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL1r 24266 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL1r 24267 24268 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24269 /******************************************************************************* 24270 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL1r' 24271 */ 24272 24273 24274 24275 24276 /******************************************************************************* 24277 * CHIP: BCMI_HURACAN 24278 * REGISTER: ANA_LANE_0_QUAD_D_CTRL2 24279 * BLOCKS: ANA_LANE_0_QUAD_D 24280 * REGADDR: 0xb102 24281 * DEVAD: 1 24282 * DESC: control registers 0 24283 * RESETVAL: 0x0 (0) 24284 * ACCESS: R/W 24285 * FIELDS: 24286 * CTLE_ENB_NEGIMP 24287 * CTLE_ENB_NEGCAP 24288 */ 24289 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r (0x0001b102 | PHYMOD_REG_ACC_RAW) 24290 24291 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_SIZE 4 24292 24293 /* 24294 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL2. 24295 */ 24296 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_s { 24297 uint32_t v[1]; 24298 uint32_t ana_lane_0_quad_d_ctrl2[1]; 24299 uint32_t _ana_lane_0_quad_d_ctrl2; 24300 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_t; 24301 24302 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CLR(r) (r).ana_lane_0_quad_d_ctrl2[0] = 0 24303 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_SET(r,d) (r).ana_lane_0_quad_d_ctrl2[0] = d 24304 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_GET(r) (r).ana_lane_0_quad_d_ctrl2[0] 24305 24306 /* 24307 * These macros can be used to access individual fields. 24308 */ 24309 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_0_quad_d_ctrl2[0]) >> 8) & 0x7f) 24310 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_0_quad_d_ctrl2[0]=(((r).ana_lane_0_quad_d_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 24311 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_0_quad_d_ctrl2[0]) & 0x7f) 24312 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_0_quad_d_ctrl2[0]=(((r).ana_lane_0_quad_d_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 24313 24314 /* 24315 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL2. 24316 */ 24317 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r,_r._ana_lane_0_quad_d_ctrl2) 24318 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r,_r._ana_lane_0_quad_d_ctrl2) 24319 24320 /* 24321 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24322 * will be redefined without the chip prefix for easier programming. 24323 * If multiple chips will be programmed in the same source file, then you should 24324 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24325 * and refer to the fully qualified versions. 24326 */ 24327 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24328 24329 #define ANA_LANE_0_QUAD_D_CTRL2r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r 24330 #define ANA_LANE_0_QUAD_D_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_SIZE 24331 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_t ANA_LANE_0_QUAD_D_CTRL2r_t; 24332 #define ANA_LANE_0_QUAD_D_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CLR 24333 #define ANA_LANE_0_QUAD_D_CTRL2r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_SET 24334 #define ANA_LANE_0_QUAD_D_CTRL2r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_GET 24335 #define ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET 24336 #define ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET 24337 #define ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET 24338 #define ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET 24339 #define READ_ANA_LANE_0_QUAD_D_CTRL2r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL2r 24340 #define WRITE_ANA_LANE_0_QUAD_D_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL2r 24341 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL2r 24342 24343 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24344 /******************************************************************************* 24345 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL2r' 24346 */ 24347 24348 24349 24350 24351 /******************************************************************************* 24352 * CHIP: BCMI_HURACAN 24353 * REGISTER: ANA_LANE_0_QUAD_D_CTRL3 24354 * BLOCKS: ANA_LANE_0_QUAD_D 24355 * REGADDR: 0xb103 24356 * DEVAD: 1 24357 * DESC: control registers 0 24358 * RESETVAL: 0x0 (0) 24359 * ACCESS: R/W 24360 * FIELDS: 24361 * CTLE_EN_NEGRES 24362 * CTLE_EQSEL 24363 */ 24364 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r (0x0001b103 | PHYMOD_REG_ACC_RAW) 24365 24366 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_SIZE 4 24367 24368 /* 24369 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL3. 24370 */ 24371 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_s { 24372 uint32_t v[1]; 24373 uint32_t ana_lane_0_quad_d_ctrl3[1]; 24374 uint32_t _ana_lane_0_quad_d_ctrl3; 24375 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_t; 24376 24377 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CLR(r) (r).ana_lane_0_quad_d_ctrl3[0] = 0 24378 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_SET(r,d) (r).ana_lane_0_quad_d_ctrl3[0] = d 24379 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_GET(r) (r).ana_lane_0_quad_d_ctrl3[0] 24380 24381 /* 24382 * These macros can be used to access individual fields. 24383 */ 24384 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_0_quad_d_ctrl3[0]) >> 8) & 0xff) 24385 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_0_quad_d_ctrl3[0]=(((r).ana_lane_0_quad_d_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 24386 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_0_quad_d_ctrl3[0]) & 0x7f) 24387 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_0_quad_d_ctrl3[0]=(((r).ana_lane_0_quad_d_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 24388 24389 /* 24390 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL3. 24391 */ 24392 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r,_r._ana_lane_0_quad_d_ctrl3) 24393 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r,_r._ana_lane_0_quad_d_ctrl3) 24394 24395 /* 24396 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24397 * will be redefined without the chip prefix for easier programming. 24398 * If multiple chips will be programmed in the same source file, then you should 24399 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24400 * and refer to the fully qualified versions. 24401 */ 24402 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24403 24404 #define ANA_LANE_0_QUAD_D_CTRL3r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r 24405 #define ANA_LANE_0_QUAD_D_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_SIZE 24406 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_t ANA_LANE_0_QUAD_D_CTRL3r_t; 24407 #define ANA_LANE_0_QUAD_D_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CLR 24408 #define ANA_LANE_0_QUAD_D_CTRL3r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_SET 24409 #define ANA_LANE_0_QUAD_D_CTRL3r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_GET 24410 #define ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EQSELf_GET 24411 #define ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EQSELf_SET 24412 #define ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET 24413 #define ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET 24414 #define READ_ANA_LANE_0_QUAD_D_CTRL3r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL3r 24415 #define WRITE_ANA_LANE_0_QUAD_D_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL3r 24416 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL3r 24417 24418 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24419 /******************************************************************************* 24420 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL3r' 24421 */ 24422 24423 24424 24425 24426 /******************************************************************************* 24427 * CHIP: BCMI_HURACAN 24428 * REGISTER: ANA_LANE_0_QUAD_D_CTRL4 24429 * BLOCKS: ANA_LANE_0_QUAD_D 24430 * REGADDR: 0xb104 24431 * DEVAD: 1 24432 * DESC: control registers 0 24433 * RESETVAL: 0x0 (0) 24434 * ACCESS: R/W 24435 * FIELDS: 24436 * CTLE_LZEN 24437 * RXTX_RESERVED_FOR_59_52 24438 */ 24439 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r (0x0001b104 | PHYMOD_REG_ACC_RAW) 24440 24441 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_SIZE 4 24442 24443 /* 24444 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL4. 24445 */ 24446 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_s { 24447 uint32_t v[1]; 24448 uint32_t ana_lane_0_quad_d_ctrl4[1]; 24449 uint32_t _ana_lane_0_quad_d_ctrl4; 24450 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_t; 24451 24452 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_CLR(r) (r).ana_lane_0_quad_d_ctrl4[0] = 0 24453 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_SET(r,d) (r).ana_lane_0_quad_d_ctrl4[0] = d 24454 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_GET(r) (r).ana_lane_0_quad_d_ctrl4[0] 24455 24456 /* 24457 * These macros can be used to access individual fields. 24458 */ 24459 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_0_quad_d_ctrl4[0]) >> 4) & 0xff) 24460 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_0_quad_d_ctrl4[0]=(((r).ana_lane_0_quad_d_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 24461 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_0_quad_d_ctrl4[0]) & 0x1) 24462 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_0_quad_d_ctrl4[0]=(((r).ana_lane_0_quad_d_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 24463 24464 /* 24465 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL4. 24466 */ 24467 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r,_r._ana_lane_0_quad_d_ctrl4) 24468 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r,_r._ana_lane_0_quad_d_ctrl4) 24469 24470 /* 24471 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24472 * will be redefined without the chip prefix for easier programming. 24473 * If multiple chips will be programmed in the same source file, then you should 24474 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24475 * and refer to the fully qualified versions. 24476 */ 24477 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24478 24479 #define ANA_LANE_0_QUAD_D_CTRL4r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r 24480 #define ANA_LANE_0_QUAD_D_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_SIZE 24481 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_t ANA_LANE_0_QUAD_D_CTRL4r_t; 24482 #define ANA_LANE_0_QUAD_D_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_CLR 24483 #define ANA_LANE_0_QUAD_D_CTRL4r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_SET 24484 #define ANA_LANE_0_QUAD_D_CTRL4r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_GET 24485 #define ANA_LANE_0_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 24486 #define ANA_LANE_0_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 24487 #define ANA_LANE_0_QUAD_D_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_CTLE_LZENf_GET 24488 #define ANA_LANE_0_QUAD_D_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r_CTLE_LZENf_SET 24489 #define READ_ANA_LANE_0_QUAD_D_CTRL4r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL4r 24490 #define WRITE_ANA_LANE_0_QUAD_D_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL4r 24491 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL4r 24492 24493 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24494 /******************************************************************************* 24495 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL4r' 24496 */ 24497 24498 24499 24500 24501 /******************************************************************************* 24502 * CHIP: BCMI_HURACAN 24503 * REGISTER: ANA_LANE_0_QUAD_D_CTRL5 24504 * BLOCKS: ANA_LANE_0_QUAD_D 24505 * REGADDR: 0xb105 24506 * DEVAD: 1 24507 * DESC: control registers 0 24508 * RESETVAL: 0x0 (0) 24509 * ACCESS: R/W 24510 * FIELDS: 24511 * CTLE_LOPEAKING 24512 * CTLE_PD 24513 * LA_GCTRL 24514 */ 24515 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r (0x0001b105 | PHYMOD_REG_ACC_RAW) 24516 24517 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_SIZE 4 24518 24519 /* 24520 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL5. 24521 */ 24522 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_s { 24523 uint32_t v[1]; 24524 uint32_t ana_lane_0_quad_d_ctrl5[1]; 24525 uint32_t _ana_lane_0_quad_d_ctrl5; 24526 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_t; 24527 24528 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CLR(r) (r).ana_lane_0_quad_d_ctrl5[0] = 0 24529 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_SET(r,d) (r).ana_lane_0_quad_d_ctrl5[0] = d 24530 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_GET(r) (r).ana_lane_0_quad_d_ctrl5[0] 24531 24532 /* 24533 * These macros can be used to access individual fields. 24534 */ 24535 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_0_quad_d_ctrl5[0]) >> 4) & 0x3ff) 24536 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_0_quad_d_ctrl5[0]=(((r).ana_lane_0_quad_d_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 24537 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_0_quad_d_ctrl5[0]) >> 1) & 0x1) 24538 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_0_quad_d_ctrl5[0]=(((r).ana_lane_0_quad_d_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 24539 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_0_quad_d_ctrl5[0]) & 0x1) 24540 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_0_quad_d_ctrl5[0]=(((r).ana_lane_0_quad_d_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 24541 24542 /* 24543 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL5. 24544 */ 24545 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r,_r._ana_lane_0_quad_d_ctrl5) 24546 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r,_r._ana_lane_0_quad_d_ctrl5) 24547 24548 /* 24549 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24550 * will be redefined without the chip prefix for easier programming. 24551 * If multiple chips will be programmed in the same source file, then you should 24552 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24553 * and refer to the fully qualified versions. 24554 */ 24555 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24556 24557 #define ANA_LANE_0_QUAD_D_CTRL5r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r 24558 #define ANA_LANE_0_QUAD_D_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_SIZE 24559 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_t ANA_LANE_0_QUAD_D_CTRL5r_t; 24560 #define ANA_LANE_0_QUAD_D_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CLR 24561 #define ANA_LANE_0_QUAD_D_CTRL5r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_SET 24562 #define ANA_LANE_0_QUAD_D_CTRL5r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_GET 24563 #define ANA_LANE_0_QUAD_D_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_LA_GCTRLf_GET 24564 #define ANA_LANE_0_QUAD_D_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_LA_GCTRLf_SET 24565 #define ANA_LANE_0_QUAD_D_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_PDf_GET 24566 #define ANA_LANE_0_QUAD_D_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_PDf_SET 24567 #define ANA_LANE_0_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET 24568 #define ANA_LANE_0_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET 24569 #define READ_ANA_LANE_0_QUAD_D_CTRL5r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL5r 24570 #define WRITE_ANA_LANE_0_QUAD_D_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL5r 24571 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL5r 24572 24573 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24574 /******************************************************************************* 24575 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL5r' 24576 */ 24577 24578 24579 24580 24581 /******************************************************************************* 24582 * CHIP: BCMI_HURACAN 24583 * REGISTER: ANA_LANE_0_QUAD_D_CTRL6 24584 * BLOCKS: ANA_LANE_0_QUAD_D 24585 * REGADDR: 0xb106 24586 * DEVAD: 1 24587 * DESC: control registers 0 24588 * RESETVAL: 0x0 (0) 24589 * ACCESS: R/W 24590 * FIELDS: 24591 * LA_DEGAIN 24592 * LA_DETUNE 24593 */ 24594 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r (0x0001b106 | PHYMOD_REG_ACC_RAW) 24595 24596 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_SIZE 4 24597 24598 /* 24599 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL6. 24600 */ 24601 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_s { 24602 uint32_t v[1]; 24603 uint32_t ana_lane_0_quad_d_ctrl6[1]; 24604 uint32_t _ana_lane_0_quad_d_ctrl6; 24605 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_t; 24606 24607 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_CLR(r) (r).ana_lane_0_quad_d_ctrl6[0] = 0 24608 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_SET(r,d) (r).ana_lane_0_quad_d_ctrl6[0] = d 24609 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_GET(r) (r).ana_lane_0_quad_d_ctrl6[0] 24610 24611 /* 24612 * These macros can be used to access individual fields. 24613 */ 24614 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_0_quad_d_ctrl6[0]) >> 8) & 0xff) 24615 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_0_quad_d_ctrl6[0]=(((r).ana_lane_0_quad_d_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 24616 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_0_quad_d_ctrl6[0]) & 0x1f) 24617 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_0_quad_d_ctrl6[0]=(((r).ana_lane_0_quad_d_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 24618 24619 /* 24620 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL6. 24621 */ 24622 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r,_r._ana_lane_0_quad_d_ctrl6) 24623 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r,_r._ana_lane_0_quad_d_ctrl6) 24624 24625 /* 24626 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24627 * will be redefined without the chip prefix for easier programming. 24628 * If multiple chips will be programmed in the same source file, then you should 24629 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24630 * and refer to the fully qualified versions. 24631 */ 24632 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24633 24634 #define ANA_LANE_0_QUAD_D_CTRL6r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r 24635 #define ANA_LANE_0_QUAD_D_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_SIZE 24636 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_t ANA_LANE_0_QUAD_D_CTRL6r_t; 24637 #define ANA_LANE_0_QUAD_D_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_CLR 24638 #define ANA_LANE_0_QUAD_D_CTRL6r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_SET 24639 #define ANA_LANE_0_QUAD_D_CTRL6r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_GET 24640 #define ANA_LANE_0_QUAD_D_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DETUNEf_GET 24641 #define ANA_LANE_0_QUAD_D_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DETUNEf_SET 24642 #define ANA_LANE_0_QUAD_D_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DEGAINf_GET 24643 #define ANA_LANE_0_QUAD_D_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r_LA_DEGAINf_SET 24644 #define READ_ANA_LANE_0_QUAD_D_CTRL6r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL6r 24645 #define WRITE_ANA_LANE_0_QUAD_D_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL6r 24646 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL6r 24647 24648 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24649 /******************************************************************************* 24650 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL6r' 24651 */ 24652 24653 24654 24655 24656 /******************************************************************************* 24657 * CHIP: BCMI_HURACAN 24658 * REGISTER: ANA_LANE_0_QUAD_D_CTRL7 24659 * BLOCKS: ANA_LANE_0_QUAD_D 24660 * REGADDR: 0xb107 24661 * DEVAD: 1 24662 * DESC: control registers 0 24663 * RESETVAL: 0x0 (0) 24664 * ACCESS: R/W 24665 * FIELDS: 24666 * LA_LIN_MODE 24667 * RX_BIAS_FB_PDN 24668 */ 24669 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r (0x0001b107 | PHYMOD_REG_ACC_RAW) 24670 24671 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_SIZE 4 24672 24673 /* 24674 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL7. 24675 */ 24676 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_s { 24677 uint32_t v[1]; 24678 uint32_t ana_lane_0_quad_d_ctrl7[1]; 24679 uint32_t _ana_lane_0_quad_d_ctrl7; 24680 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_t; 24681 24682 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_CLR(r) (r).ana_lane_0_quad_d_ctrl7[0] = 0 24683 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_SET(r,d) (r).ana_lane_0_quad_d_ctrl7[0] = d 24684 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_GET(r) (r).ana_lane_0_quad_d_ctrl7[0] 24685 24686 /* 24687 * These macros can be used to access individual fields. 24688 */ 24689 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_0_quad_d_ctrl7[0]) >> 8) & 0x1) 24690 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_0_quad_d_ctrl7[0]=(((r).ana_lane_0_quad_d_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 24691 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_0_quad_d_ctrl7[0]) & 0x1f) 24692 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_0_quad_d_ctrl7[0]=(((r).ana_lane_0_quad_d_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 24693 24694 /* 24695 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL7. 24696 */ 24697 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r,_r._ana_lane_0_quad_d_ctrl7) 24698 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r,_r._ana_lane_0_quad_d_ctrl7) 24699 24700 /* 24701 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24702 * will be redefined without the chip prefix for easier programming. 24703 * If multiple chips will be programmed in the same source file, then you should 24704 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24705 * and refer to the fully qualified versions. 24706 */ 24707 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24708 24709 #define ANA_LANE_0_QUAD_D_CTRL7r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r 24710 #define ANA_LANE_0_QUAD_D_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_SIZE 24711 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_t ANA_LANE_0_QUAD_D_CTRL7r_t; 24712 #define ANA_LANE_0_QUAD_D_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_CLR 24713 #define ANA_LANE_0_QUAD_D_CTRL7r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_SET 24714 #define ANA_LANE_0_QUAD_D_CTRL7r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_GET 24715 #define ANA_LANE_0_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET 24716 #define ANA_LANE_0_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET 24717 #define ANA_LANE_0_QUAD_D_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_LA_LIN_MODEf_GET 24718 #define ANA_LANE_0_QUAD_D_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r_LA_LIN_MODEf_SET 24719 #define READ_ANA_LANE_0_QUAD_D_CTRL7r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL7r 24720 #define WRITE_ANA_LANE_0_QUAD_D_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL7r 24721 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL7r 24722 24723 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24724 /******************************************************************************* 24725 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL7r' 24726 */ 24727 24728 24729 24730 24731 /******************************************************************************* 24732 * CHIP: BCMI_HURACAN 24733 * REGISTER: ANA_LANE_0_QUAD_D_CTRL8 24734 * BLOCKS: ANA_LANE_0_QUAD_D 24735 * REGADDR: 0xb108 24736 * DEVAD: 1 24737 * DESC: control registers 0 24738 * RESETVAL: 0x0 (0) 24739 * ACCESS: R/W 24740 * FIELDS: 24741 * LA_PD 24742 * LA_PD_IDLE 24743 * RXTX_RESERVED_FOR_99_95 24744 */ 24745 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r (0x0001b108 | PHYMOD_REG_ACC_RAW) 24746 24747 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_SIZE 4 24748 24749 /* 24750 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL8. 24751 */ 24752 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_s { 24753 uint32_t v[1]; 24754 uint32_t ana_lane_0_quad_d_ctrl8[1]; 24755 uint32_t _ana_lane_0_quad_d_ctrl8; 24756 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_t; 24757 24758 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_CLR(r) (r).ana_lane_0_quad_d_ctrl8[0] = 0 24759 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_SET(r,d) (r).ana_lane_0_quad_d_ctrl8[0] = d 24760 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_GET(r) (r).ana_lane_0_quad_d_ctrl8[0] 24761 24762 /* 24763 * These macros can be used to access individual fields. 24764 */ 24765 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_0_quad_d_ctrl8[0]) >> 4) & 0x1f) 24766 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_0_quad_d_ctrl8[0]=(((r).ana_lane_0_quad_d_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 24767 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_0_quad_d_ctrl8[0]) >> 1) & 0x1) 24768 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_0_quad_d_ctrl8[0]=(((r).ana_lane_0_quad_d_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 24769 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_0_quad_d_ctrl8[0]) & 0x1) 24770 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_0_quad_d_ctrl8[0]=(((r).ana_lane_0_quad_d_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 24771 24772 /* 24773 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL8. 24774 */ 24775 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r,_r._ana_lane_0_quad_d_ctrl8) 24776 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r,_r._ana_lane_0_quad_d_ctrl8) 24777 24778 /* 24779 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24780 * will be redefined without the chip prefix for easier programming. 24781 * If multiple chips will be programmed in the same source file, then you should 24782 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24783 * and refer to the fully qualified versions. 24784 */ 24785 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24786 24787 #define ANA_LANE_0_QUAD_D_CTRL8r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r 24788 #define ANA_LANE_0_QUAD_D_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_SIZE 24789 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_t ANA_LANE_0_QUAD_D_CTRL8r_t; 24790 #define ANA_LANE_0_QUAD_D_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_CLR 24791 #define ANA_LANE_0_QUAD_D_CTRL8r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_SET 24792 #define ANA_LANE_0_QUAD_D_CTRL8r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_GET 24793 #define ANA_LANE_0_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 24794 #define ANA_LANE_0_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 24795 #define ANA_LANE_0_QUAD_D_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PD_IDLEf_GET 24796 #define ANA_LANE_0_QUAD_D_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PD_IDLEf_SET 24797 #define ANA_LANE_0_QUAD_D_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PDf_GET 24798 #define ANA_LANE_0_QUAD_D_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r_LA_PDf_SET 24799 #define READ_ANA_LANE_0_QUAD_D_CTRL8r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL8r 24800 #define WRITE_ANA_LANE_0_QUAD_D_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL8r 24801 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL8r 24802 24803 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24804 /******************************************************************************* 24805 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL8r' 24806 */ 24807 24808 24809 24810 24811 /******************************************************************************* 24812 * CHIP: BCMI_HURACAN 24813 * REGISTER: ANA_LANE_0_QUAD_D_CTRL9 24814 * BLOCKS: ANA_LANE_0_QUAD_D 24815 * REGADDR: 0xb109 24816 * DEVAD: 1 24817 * DESC: control registers 0 24818 * RESETVAL: 0x0 (0) 24819 * ACCESS: R/W 24820 * FIELDS: 24821 * DRV_POST1 24822 * DLINE_SWING_1 24823 * DLINE_SWING_2 24824 * DLINE_DELAY_CTRL 24825 */ 24826 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r (0x0001b109 | PHYMOD_REG_ACC_RAW) 24827 24828 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_SIZE 4 24829 24830 /* 24831 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL9. 24832 */ 24833 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_s { 24834 uint32_t v[1]; 24835 uint32_t ana_lane_0_quad_d_ctrl9[1]; 24836 uint32_t _ana_lane_0_quad_d_ctrl9; 24837 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_t; 24838 24839 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_CLR(r) (r).ana_lane_0_quad_d_ctrl9[0] = 0 24840 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_SET(r,d) (r).ana_lane_0_quad_d_ctrl9[0] = d 24841 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_GET(r) (r).ana_lane_0_quad_d_ctrl9[0] 24842 24843 /* 24844 * These macros can be used to access individual fields. 24845 */ 24846 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_0_quad_d_ctrl9[0]) >> 12) & 0x7) 24847 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_0_quad_d_ctrl9[0]=(((r).ana_lane_0_quad_d_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 24848 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_0_quad_d_ctrl9[0]) >> 8) & 0x3) 24849 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_0_quad_d_ctrl9[0]=(((r).ana_lane_0_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 24850 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_0_quad_d_ctrl9[0]) >> 4) & 0x3) 24851 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_0_quad_d_ctrl9[0]=(((r).ana_lane_0_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 24852 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_0_quad_d_ctrl9[0]) & 0xf) 24853 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_0_quad_d_ctrl9[0]=(((r).ana_lane_0_quad_d_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 24854 24855 /* 24856 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL9. 24857 */ 24858 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r,_r._ana_lane_0_quad_d_ctrl9) 24859 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r,_r._ana_lane_0_quad_d_ctrl9) 24860 24861 /* 24862 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24863 * will be redefined without the chip prefix for easier programming. 24864 * If multiple chips will be programmed in the same source file, then you should 24865 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24866 * and refer to the fully qualified versions. 24867 */ 24868 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24869 24870 #define ANA_LANE_0_QUAD_D_CTRL9r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r 24871 #define ANA_LANE_0_QUAD_D_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_SIZE 24872 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_t ANA_LANE_0_QUAD_D_CTRL9r_t; 24873 #define ANA_LANE_0_QUAD_D_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_CLR 24874 #define ANA_LANE_0_QUAD_D_CTRL9r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_SET 24875 #define ANA_LANE_0_QUAD_D_CTRL9r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_GET 24876 #define ANA_LANE_0_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET 24877 #define ANA_LANE_0_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET 24878 #define ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_2f_GET 24879 #define ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_2f_SET 24880 #define ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_1f_GET 24881 #define ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DLINE_SWING_1f_SET 24882 #define ANA_LANE_0_QUAD_D_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DRV_POST1f_GET 24883 #define ANA_LANE_0_QUAD_D_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r_DRV_POST1f_SET 24884 #define READ_ANA_LANE_0_QUAD_D_CTRL9r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL9r 24885 #define WRITE_ANA_LANE_0_QUAD_D_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL9r 24886 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL9r 24887 24888 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24889 /******************************************************************************* 24890 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL9r' 24891 */ 24892 24893 24894 24895 24896 /******************************************************************************* 24897 * CHIP: BCMI_HURACAN 24898 * REGISTER: ANA_LANE_0_QUAD_D_CTRL10 24899 * BLOCKS: ANA_LANE_0_QUAD_D 24900 * REGADDR: 0xb10a 24901 * DEVAD: 1 24902 * DESC: control registers 0 24903 * RESETVAL: 0x0 (0) 24904 * ACCESS: R/W 24905 * FIELDS: 24906 * DRV_PWD 24907 * DLINE_PWD 24908 * DRV_VBSEL 24909 * DRV_MAIN 24910 * DRV_MAIN_PU 24911 */ 24912 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r (0x0001b10a | PHYMOD_REG_ACC_RAW) 24913 24914 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_SIZE 4 24915 24916 /* 24917 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL10. 24918 */ 24919 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_s { 24920 uint32_t v[1]; 24921 uint32_t ana_lane_0_quad_d_ctrl10[1]; 24922 uint32_t _ana_lane_0_quad_d_ctrl10; 24923 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_t; 24924 24925 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_CLR(r) (r).ana_lane_0_quad_d_ctrl10[0] = 0 24926 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_SET(r,d) (r).ana_lane_0_quad_d_ctrl10[0] = d 24927 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_GET(r) (r).ana_lane_0_quad_d_ctrl10[0] 24928 24929 /* 24930 * These macros can be used to access individual fields. 24931 */ 24932 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_0_quad_d_ctrl10[0]) >> 12) & 0xf) 24933 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_0_quad_d_ctrl10[0]=(((r).ana_lane_0_quad_d_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 24934 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_0_quad_d_ctrl10[0]) >> 4) & 0x3f) 24935 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_0_quad_d_ctrl10[0]=(((r).ana_lane_0_quad_d_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 24936 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_0_quad_d_ctrl10[0]) >> 2) & 0x1) 24937 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_0_quad_d_ctrl10[0]=(((r).ana_lane_0_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 24938 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_0_quad_d_ctrl10[0]) >> 1) & 0x1) 24939 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_0_quad_d_ctrl10[0]=(((r).ana_lane_0_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 24940 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_0_quad_d_ctrl10[0]) & 0x1) 24941 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_0_quad_d_ctrl10[0]=(((r).ana_lane_0_quad_d_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 24942 24943 /* 24944 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL10. 24945 */ 24946 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r,_r._ana_lane_0_quad_d_ctrl10) 24947 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r,_r._ana_lane_0_quad_d_ctrl10) 24948 24949 /* 24950 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 24951 * will be redefined without the chip prefix for easier programming. 24952 * If multiple chips will be programmed in the same source file, then you should 24953 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 24954 * and refer to the fully qualified versions. 24955 */ 24956 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 24957 24958 #define ANA_LANE_0_QUAD_D_CTRL10r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r 24959 #define ANA_LANE_0_QUAD_D_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_SIZE 24960 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_t ANA_LANE_0_QUAD_D_CTRL10r_t; 24961 #define ANA_LANE_0_QUAD_D_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_CLR 24962 #define ANA_LANE_0_QUAD_D_CTRL10r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_SET 24963 #define ANA_LANE_0_QUAD_D_CTRL10r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_GET 24964 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET 24965 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET 24966 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAINf_GET 24967 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_MAINf_SET 24968 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_VBSELf_GET 24969 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_VBSELf_SET 24970 #define ANA_LANE_0_QUAD_D_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DLINE_PWDf_GET 24971 #define ANA_LANE_0_QUAD_D_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DLINE_PWDf_SET 24972 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_PWDf_GET 24973 #define ANA_LANE_0_QUAD_D_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r_DRV_PWDf_SET 24974 #define READ_ANA_LANE_0_QUAD_D_CTRL10r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL10r 24975 #define WRITE_ANA_LANE_0_QUAD_D_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL10r 24976 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL10r 24977 24978 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 24979 /******************************************************************************* 24980 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL10r' 24981 */ 24982 24983 24984 24985 24986 /******************************************************************************* 24987 * CHIP: BCMI_HURACAN 24988 * REGISTER: ANA_LANE_0_QUAD_D_CTRL11 24989 * BLOCKS: ANA_LANE_0_QUAD_D 24990 * REGADDR: 0xb10b 24991 * DEVAD: 1 24992 * DESC: control registers 0 24993 * RESETVAL: 0x0 (0) 24994 * ACCESS: R/W 24995 * FIELDS: 24996 * RXTX_RESERVED_FOR_143_128 24997 */ 24998 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r (0x0001b10b | PHYMOD_REG_ACC_RAW) 24999 25000 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_SIZE 4 25001 25002 /* 25003 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL11. 25004 */ 25005 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_s { 25006 uint32_t v[1]; 25007 uint32_t ana_lane_0_quad_d_ctrl11[1]; 25008 uint32_t _ana_lane_0_quad_d_ctrl11; 25009 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_t; 25010 25011 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_CLR(r) (r).ana_lane_0_quad_d_ctrl11[0] = 0 25012 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_SET(r,d) (r).ana_lane_0_quad_d_ctrl11[0] = d 25013 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_GET(r) (r).ana_lane_0_quad_d_ctrl11[0] 25014 25015 /* 25016 * These macros can be used to access individual fields. 25017 */ 25018 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_0_quad_d_ctrl11[0]) & 0xffff) 25019 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_0_quad_d_ctrl11[0]=(((r).ana_lane_0_quad_d_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 25020 25021 /* 25022 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL11. 25023 */ 25024 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r,_r._ana_lane_0_quad_d_ctrl11) 25025 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r,_r._ana_lane_0_quad_d_ctrl11) 25026 25027 /* 25028 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25029 * will be redefined without the chip prefix for easier programming. 25030 * If multiple chips will be programmed in the same source file, then you should 25031 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25032 * and refer to the fully qualified versions. 25033 */ 25034 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25035 25036 #define ANA_LANE_0_QUAD_D_CTRL11r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r 25037 #define ANA_LANE_0_QUAD_D_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_SIZE 25038 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_t ANA_LANE_0_QUAD_D_CTRL11r_t; 25039 #define ANA_LANE_0_QUAD_D_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_CLR 25040 #define ANA_LANE_0_QUAD_D_CTRL11r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_SET 25041 #define ANA_LANE_0_QUAD_D_CTRL11r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_GET 25042 #define ANA_LANE_0_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 25043 #define ANA_LANE_0_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 25044 #define READ_ANA_LANE_0_QUAD_D_CTRL11r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL11r 25045 #define WRITE_ANA_LANE_0_QUAD_D_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL11r 25046 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL11r 25047 25048 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25049 /******************************************************************************* 25050 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL11r' 25051 */ 25052 25053 25054 25055 25056 /******************************************************************************* 25057 * CHIP: BCMI_HURACAN 25058 * REGISTER: ANA_LANE_0_QUAD_D_CTRL12 25059 * BLOCKS: ANA_LANE_0_QUAD_D 25060 * REGADDR: 0xb10c 25061 * DEVAD: 1 25062 * DESC: control registers 0 25063 * RESETVAL: 0x0 (0) 25064 * ACCESS: R/W 25065 * FIELDS: 25066 * LA_RESCAL_FRC_VAL 25067 * LA_RESCAL_FRC 25068 * DRV_RESCAL_FRC_VAL 25069 * DRV_RESCAL_FRC 25070 */ 25071 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r (0x0001b10c | PHYMOD_REG_ACC_RAW) 25072 25073 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_SIZE 4 25074 25075 /* 25076 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL12. 25077 */ 25078 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_s { 25079 uint32_t v[1]; 25080 uint32_t ana_lane_0_quad_d_ctrl12[1]; 25081 uint32_t _ana_lane_0_quad_d_ctrl12; 25082 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_t; 25083 25084 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_CLR(r) (r).ana_lane_0_quad_d_ctrl12[0] = 0 25085 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_SET(r,d) (r).ana_lane_0_quad_d_ctrl12[0] = d 25086 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_GET(r) (r).ana_lane_0_quad_d_ctrl12[0] 25087 25088 /* 25089 * These macros can be used to access individual fields. 25090 */ 25091 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_d_ctrl12[0]) >> 12) & 0x1) 25092 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_d_ctrl12[0]=(((r).ana_lane_0_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 25093 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_d_ctrl12[0]) >> 8) & 0xf) 25094 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_d_ctrl12[0]=(((r).ana_lane_0_quad_d_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 25095 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_d_ctrl12[0]) >> 4) & 0x1) 25096 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_d_ctrl12[0]=(((r).ana_lane_0_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 25097 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_d_ctrl12[0]) & 0xf) 25098 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_d_ctrl12[0]=(((r).ana_lane_0_quad_d_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 25099 25100 /* 25101 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL12. 25102 */ 25103 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r,_r._ana_lane_0_quad_d_ctrl12) 25104 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r,_r._ana_lane_0_quad_d_ctrl12) 25105 25106 /* 25107 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25108 * will be redefined without the chip prefix for easier programming. 25109 * If multiple chips will be programmed in the same source file, then you should 25110 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25111 * and refer to the fully qualified versions. 25112 */ 25113 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25114 25115 #define ANA_LANE_0_QUAD_D_CTRL12r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r 25116 #define ANA_LANE_0_QUAD_D_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_SIZE 25117 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_t ANA_LANE_0_QUAD_D_CTRL12r_t; 25118 #define ANA_LANE_0_QUAD_D_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_CLR 25119 #define ANA_LANE_0_QUAD_D_CTRL12r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_SET 25120 #define ANA_LANE_0_QUAD_D_CTRL12r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_GET 25121 #define ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET 25122 #define ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET 25123 #define ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET 25124 #define ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET 25125 #define ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET 25126 #define ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET 25127 #define ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET 25128 #define ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET 25129 #define READ_ANA_LANE_0_QUAD_D_CTRL12r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL12r 25130 #define WRITE_ANA_LANE_0_QUAD_D_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL12r 25131 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL12r 25132 25133 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25134 /******************************************************************************* 25135 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL12r' 25136 */ 25137 25138 25139 25140 25141 /******************************************************************************* 25142 * CHIP: BCMI_HURACAN 25143 * REGISTER: ANA_LANE_0_QUAD_D_CTRL13 25144 * BLOCKS: ANA_LANE_0_QUAD_D 25145 * REGADDR: 0xb10d 25146 * DEVAD: 1 25147 * DESC: control registers 0 25148 * RESETVAL: 0x0 (0) 25149 * ACCESS: R/W 25150 * FIELDS: 25151 * CTLE_RESCAL_FRC_VAL 25152 * CTLE_RESCAL_FRC 25153 */ 25154 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r (0x0001b10d | PHYMOD_REG_ACC_RAW) 25155 25156 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_SIZE 4 25157 25158 /* 25159 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL13. 25160 */ 25161 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_s { 25162 uint32_t v[1]; 25163 uint32_t ana_lane_0_quad_d_ctrl13[1]; 25164 uint32_t _ana_lane_0_quad_d_ctrl13; 25165 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_t; 25166 25167 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CLR(r) (r).ana_lane_0_quad_d_ctrl13[0] = 0 25168 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_SET(r,d) (r).ana_lane_0_quad_d_ctrl13[0] = d 25169 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_GET(r) (r).ana_lane_0_quad_d_ctrl13[0] 25170 25171 /* 25172 * These macros can be used to access individual fields. 25173 */ 25174 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_0_quad_d_ctrl13[0]) >> 4) & 0x1) 25175 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_0_quad_d_ctrl13[0]=(((r).ana_lane_0_quad_d_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 25176 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_0_quad_d_ctrl13[0]) & 0xf) 25177 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_d_ctrl13[0]=(((r).ana_lane_0_quad_d_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 25178 25179 /* 25180 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL13. 25181 */ 25182 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r,_r._ana_lane_0_quad_d_ctrl13) 25183 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r,_r._ana_lane_0_quad_d_ctrl13) 25184 25185 /* 25186 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25187 * will be redefined without the chip prefix for easier programming. 25188 * If multiple chips will be programmed in the same source file, then you should 25189 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25190 * and refer to the fully qualified versions. 25191 */ 25192 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25193 25194 #define ANA_LANE_0_QUAD_D_CTRL13r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r 25195 #define ANA_LANE_0_QUAD_D_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_SIZE 25196 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_t ANA_LANE_0_QUAD_D_CTRL13r_t; 25197 #define ANA_LANE_0_QUAD_D_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CLR 25198 #define ANA_LANE_0_QUAD_D_CTRL13r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_SET 25199 #define ANA_LANE_0_QUAD_D_CTRL13r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_GET 25200 #define ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET 25201 #define ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET 25202 #define ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 25203 #define ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 25204 #define READ_ANA_LANE_0_QUAD_D_CTRL13r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL13r 25205 #define WRITE_ANA_LANE_0_QUAD_D_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL13r 25206 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL13r 25207 25208 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25209 /******************************************************************************* 25210 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL13r' 25211 */ 25212 25213 25214 25215 25216 /******************************************************************************* 25217 * CHIP: BCMI_HURACAN 25218 * REGISTER: ANA_LANE_0_QUAD_D_CTRL14 25219 * BLOCKS: ANA_LANE_0_QUAD_D 25220 * REGADDR: 0xb10e 25221 * DEVAD: 1 25222 * DESC: control registers 0 25223 * RESETVAL: 0x0 (0) 25224 * ACCESS: R/W 25225 * FIELDS: 25226 * TX_IDLE_FRC_VAL 25227 * TX_IDLE_FRC 25228 * RXSD_IDLE_OVRD 25229 */ 25230 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r (0x0001b10e | PHYMOD_REG_ACC_RAW) 25231 25232 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_SIZE 4 25233 25234 /* 25235 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL14. 25236 */ 25237 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_s { 25238 uint32_t v[1]; 25239 uint32_t ana_lane_0_quad_d_ctrl14[1]; 25240 uint32_t _ana_lane_0_quad_d_ctrl14; 25241 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_t; 25242 25243 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_CLR(r) (r).ana_lane_0_quad_d_ctrl14[0] = 0 25244 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_SET(r,d) (r).ana_lane_0_quad_d_ctrl14[0] = d 25245 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_GET(r) (r).ana_lane_0_quad_d_ctrl14[0] 25246 25247 /* 25248 * These macros can be used to access individual fields. 25249 */ 25250 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_0_quad_d_ctrl14[0]) >> 4) & 0x1) 25251 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_0_quad_d_ctrl14[0]=(((r).ana_lane_0_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 25252 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_0_quad_d_ctrl14[0]) >> 1) & 0x1) 25253 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_0_quad_d_ctrl14[0]=(((r).ana_lane_0_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 25254 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_0_quad_d_ctrl14[0]) & 0x1) 25255 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_d_ctrl14[0]=(((r).ana_lane_0_quad_d_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 25256 25257 /* 25258 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL14. 25259 */ 25260 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r,_r._ana_lane_0_quad_d_ctrl14) 25261 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r,_r._ana_lane_0_quad_d_ctrl14) 25262 25263 /* 25264 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25265 * will be redefined without the chip prefix for easier programming. 25266 * If multiple chips will be programmed in the same source file, then you should 25267 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25268 * and refer to the fully qualified versions. 25269 */ 25270 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25271 25272 #define ANA_LANE_0_QUAD_D_CTRL14r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r 25273 #define ANA_LANE_0_QUAD_D_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_SIZE 25274 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_t ANA_LANE_0_QUAD_D_CTRL14r_t; 25275 #define ANA_LANE_0_QUAD_D_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_CLR 25276 #define ANA_LANE_0_QUAD_D_CTRL14r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_SET 25277 #define ANA_LANE_0_QUAD_D_CTRL14r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_GET 25278 #define ANA_LANE_0_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET 25279 #define ANA_LANE_0_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET 25280 #define ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET 25281 #define ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET 25282 #define ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET 25283 #define ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET 25284 #define READ_ANA_LANE_0_QUAD_D_CTRL14r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL14r 25285 #define WRITE_ANA_LANE_0_QUAD_D_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL14r 25286 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL14r 25287 25288 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25289 /******************************************************************************* 25290 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL14r' 25291 */ 25292 25293 25294 25295 25296 /******************************************************************************* 25297 * CHIP: BCMI_HURACAN 25298 * REGISTER: ANA_LANE_0_QUAD_D_CTRL15 25299 * BLOCKS: ANA_LANE_0_QUAD_D 25300 * REGADDR: 0xb10f 25301 * DEVAD: 1 25302 * DESC: sigdet filter settings 0 25303 * RESETVAL: 0x0 (0) 25304 * ACCESS: R/W 25305 * FIELDS: 25306 * SIGDET_DIS 25307 * SIGDET_1US_EN 25308 * SIGDET_FRC_VAL 25309 * SIGDET_FRC 25310 * HOLD_LOS_COUNT 25311 * HOLD_SD_COUNT 25312 */ 25313 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r (0x0001b10f | PHYMOD_REG_ACC_RAW) 25314 25315 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIZE 4 25316 25317 /* 25318 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL15. 25319 */ 25320 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_s { 25321 uint32_t v[1]; 25322 uint32_t ana_lane_0_quad_d_ctrl15[1]; 25323 uint32_t _ana_lane_0_quad_d_ctrl15; 25324 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_t; 25325 25326 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_CLR(r) (r).ana_lane_0_quad_d_ctrl15[0] = 0 25327 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SET(r,d) (r).ana_lane_0_quad_d_ctrl15[0] = d 25328 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_GET(r) (r).ana_lane_0_quad_d_ctrl15[0] 25329 25330 /* 25331 * These macros can be used to access individual fields. 25332 */ 25333 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_d_ctrl15[0]) >> 8) & 0x7) 25334 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_d_ctrl15[0]=(((r).ana_lane_0_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 25335 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_0_quad_d_ctrl15[0]) >> 4) & 0x7) 25336 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_d_ctrl15[0]=(((r).ana_lane_0_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 25337 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_0_quad_d_ctrl15[0]) >> 3) & 0x1) 25338 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_0_quad_d_ctrl15[0]=(((r).ana_lane_0_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 25339 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_0_quad_d_ctrl15[0]) >> 2) & 0x1) 25340 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_0_quad_d_ctrl15[0]=(((r).ana_lane_0_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 25341 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_0_quad_d_ctrl15[0]) >> 1) & 0x1) 25342 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_0_quad_d_ctrl15[0]=(((r).ana_lane_0_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 25343 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_0_quad_d_ctrl15[0]) & 0x1) 25344 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_0_quad_d_ctrl15[0]=(((r).ana_lane_0_quad_d_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 25345 25346 /* 25347 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL15. 25348 */ 25349 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r,_r._ana_lane_0_quad_d_ctrl15) 25350 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r,_r._ana_lane_0_quad_d_ctrl15) 25351 25352 /* 25353 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25354 * will be redefined without the chip prefix for easier programming. 25355 * If multiple chips will be programmed in the same source file, then you should 25356 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25357 * and refer to the fully qualified versions. 25358 */ 25359 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25360 25361 #define ANA_LANE_0_QUAD_D_CTRL15r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r 25362 #define ANA_LANE_0_QUAD_D_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIZE 25363 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_t ANA_LANE_0_QUAD_D_CTRL15r_t; 25364 #define ANA_LANE_0_QUAD_D_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_CLR 25365 #define ANA_LANE_0_QUAD_D_CTRL15r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SET 25366 #define ANA_LANE_0_QUAD_D_CTRL15r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_GET 25367 #define ANA_LANE_0_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET 25368 #define ANA_LANE_0_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET 25369 #define ANA_LANE_0_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET 25370 #define ANA_LANE_0_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET 25371 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRCf_GET 25372 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRCf_SET 25373 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET 25374 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET 25375 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET 25376 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET 25377 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_DISf_GET 25378 #define ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r_SIGDET_DISf_SET 25379 #define READ_ANA_LANE_0_QUAD_D_CTRL15r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL15r 25380 #define WRITE_ANA_LANE_0_QUAD_D_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL15r 25381 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL15r 25382 25383 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25384 /******************************************************************************* 25385 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL15r' 25386 */ 25387 25388 25389 25390 25391 /******************************************************************************* 25392 * CHIP: BCMI_HURACAN 25393 * REGISTER: ANA_LANE_0_QUAD_D_CTRL16 25394 * BLOCKS: ANA_LANE_0_QUAD_D 25395 * REGADDR: 0xb110 25396 * DEVAD: 1 25397 * DESC: sigdet filter settings 1 25398 * RESETVAL: 0x0 (0) 25399 * ACCESS: R/W 25400 * FIELDS: 25401 * LOS_COUNT 25402 * SD_COUNT 25403 */ 25404 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r (0x0001b110 | PHYMOD_REG_ACC_RAW) 25405 25406 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SIZE 4 25407 25408 /* 25409 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_CTRL16. 25410 */ 25411 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_s { 25412 uint32_t v[1]; 25413 uint32_t ana_lane_0_quad_d_ctrl16[1]; 25414 uint32_t _ana_lane_0_quad_d_ctrl16; 25415 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_t; 25416 25417 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_CLR(r) (r).ana_lane_0_quad_d_ctrl16[0] = 0 25418 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SET(r,d) (r).ana_lane_0_quad_d_ctrl16[0] = d 25419 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_GET(r) (r).ana_lane_0_quad_d_ctrl16[0] 25420 25421 /* 25422 * These macros can be used to access individual fields. 25423 */ 25424 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_0_quad_d_ctrl16[0]) >> 8) & 0x1f) 25425 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_0_quad_d_ctrl16[0]=(((r).ana_lane_0_quad_d_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 25426 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_0_quad_d_ctrl16[0]) & 0x1f) 25427 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_0_quad_d_ctrl16[0]=(((r).ana_lane_0_quad_d_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 25428 25429 /* 25430 * These macros can be used to access ANA_LANE_0_QUAD_D_CTRL16. 25431 */ 25432 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r,_r._ana_lane_0_quad_d_ctrl16) 25433 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r,_r._ana_lane_0_quad_d_ctrl16) 25434 25435 /* 25436 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25437 * will be redefined without the chip prefix for easier programming. 25438 * If multiple chips will be programmed in the same source file, then you should 25439 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25440 * and refer to the fully qualified versions. 25441 */ 25442 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25443 25444 #define ANA_LANE_0_QUAD_D_CTRL16r BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r 25445 #define ANA_LANE_0_QUAD_D_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SIZE 25446 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_t ANA_LANE_0_QUAD_D_CTRL16r_t; 25447 #define ANA_LANE_0_QUAD_D_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_CLR 25448 #define ANA_LANE_0_QUAD_D_CTRL16r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SET 25449 #define ANA_LANE_0_QUAD_D_CTRL16r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_GET 25450 #define ANA_LANE_0_QUAD_D_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SD_COUNTf_GET 25451 #define ANA_LANE_0_QUAD_D_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_SD_COUNTf_SET 25452 #define ANA_LANE_0_QUAD_D_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_LOS_COUNTf_GET 25453 #define ANA_LANE_0_QUAD_D_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r_LOS_COUNTf_SET 25454 #define READ_ANA_LANE_0_QUAD_D_CTRL16r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_CTRL16r 25455 #define WRITE_ANA_LANE_0_QUAD_D_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_CTRL16r 25456 #define MODIFY_ANA_LANE_0_QUAD_D_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_CTRL16r 25457 25458 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25459 /******************************************************************************* 25460 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_CTRL16r' 25461 */ 25462 25463 25464 25465 25466 /******************************************************************************* 25467 * CHIP: BCMI_HURACAN 25468 * REGISTER: ANA_LANE_0_QUAD_D_STATUS0 25469 * BLOCKS: ANA_LANE_0_QUAD_D 25470 * REGADDR: 0xb120 25471 * DEVAD: 1 25472 * DESC: status registers 0 25473 * RESETVAL: 0x0 (0) 25474 * ACCESS: R/W 25475 * FIELDS: 25476 * O_RX_SIGDET 25477 * DG_RX_SIGDET 25478 */ 25479 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r (0x0001b120 | PHYMOD_REG_ACC_RAW) 25480 25481 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_SIZE 4 25482 25483 /* 25484 * This structure should be used to declare and program ANA_LANE_0_QUAD_D_STATUS0. 25485 */ 25486 typedef union BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_s { 25487 uint32_t v[1]; 25488 uint32_t ana_lane_0_quad_d_status0[1]; 25489 uint32_t _ana_lane_0_quad_d_status0; 25490 } BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_t; 25491 25492 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_CLR(r) (r).ana_lane_0_quad_d_status0[0] = 0 25493 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_SET(r,d) (r).ana_lane_0_quad_d_status0[0] = d 25494 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_GET(r) (r).ana_lane_0_quad_d_status0[0] 25495 25496 /* 25497 * These macros can be used to access individual fields. 25498 */ 25499 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_0_quad_d_status0[0]) >> 1) & 0x1) 25500 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_d_status0[0]=(((r).ana_lane_0_quad_d_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 25501 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_0_quad_d_status0[0]) & 0x1) 25502 #define BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_0_quad_d_status0[0]=(((r).ana_lane_0_quad_d_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 25503 25504 /* 25505 * These macros can be used to access ANA_LANE_0_QUAD_D_STATUS0. 25506 */ 25507 #define BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r,_r._ana_lane_0_quad_d_status0) 25508 #define BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r,_r._ana_lane_0_quad_d_status0) 25509 25510 /* 25511 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25512 * will be redefined without the chip prefix for easier programming. 25513 * If multiple chips will be programmed in the same source file, then you should 25514 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25515 * and refer to the fully qualified versions. 25516 */ 25517 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25518 25519 #define ANA_LANE_0_QUAD_D_STATUS0r BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r 25520 #define ANA_LANE_0_QUAD_D_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_SIZE 25521 typedef BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_t ANA_LANE_0_QUAD_D_STATUS0r_t; 25522 #define ANA_LANE_0_QUAD_D_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_CLR 25523 #define ANA_LANE_0_QUAD_D_STATUS0r_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_SET 25524 #define ANA_LANE_0_QUAD_D_STATUS0r_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_GET 25525 #define ANA_LANE_0_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET 25526 #define ANA_LANE_0_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET 25527 #define ANA_LANE_0_QUAD_D_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_O_RX_SIGDETf_GET 25528 #define ANA_LANE_0_QUAD_D_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r_O_RX_SIGDETf_SET 25529 #define READ_ANA_LANE_0_QUAD_D_STATUS0r BCMI_HURACAN_READ_ANA_LANE_0_QUAD_D_STATUS0r 25530 #define WRITE_ANA_LANE_0_QUAD_D_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_0_QUAD_D_STATUS0r 25531 #define MODIFY_ANA_LANE_0_QUAD_D_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_0_QUAD_D_STATUS0r 25532 25533 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25534 /******************************************************************************* 25535 * End of 'BCMI_HURACAN_ANA_LANE_0_QUAD_D_STATUS0r' 25536 */ 25537 25538 25539 25540 25541 /******************************************************************************* 25542 * CHIP: BCMI_HURACAN 25543 * REGISTER: ANA_LANE_1_QUAD_D_CTRL0 25544 * BLOCKS: ANA_LANE_1_QUAD_D 25545 * REGADDR: 0xb200 25546 * DEVAD: 1 25547 * DESC: control registers 0 25548 * RESETVAL: 0x0 (0) 25549 * ACCESS: R/W 25550 * FIELDS: 25551 * RXTX_PWRDN 25552 * RX_SIGDET_BYPASS 25553 * RX_SIGDET_PWRDN 25554 * RX_SIGDECT_12GMODE 25555 * DC_COUPLE 25556 */ 25557 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r (0x0001b200 | PHYMOD_REG_ACC_RAW) 25558 25559 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_SIZE 4 25560 25561 /* 25562 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL0. 25563 */ 25564 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_s { 25565 uint32_t v[1]; 25566 uint32_t ana_lane_1_quad_d_ctrl0[1]; 25567 uint32_t _ana_lane_1_quad_d_ctrl0; 25568 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_t; 25569 25570 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_CLR(r) (r).ana_lane_1_quad_d_ctrl0[0] = 0 25571 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_SET(r,d) (r).ana_lane_1_quad_d_ctrl0[0] = d 25572 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_GET(r) (r).ana_lane_1_quad_d_ctrl0[0] 25573 25574 /* 25575 * These macros can be used to access individual fields. 25576 */ 25577 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_1_quad_d_ctrl0[0]) >> 4) & 0x1) 25578 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_1_quad_d_ctrl0[0]=(((r).ana_lane_1_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 25579 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_1_quad_d_ctrl0[0]) >> 3) & 0x1) 25580 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_1_quad_d_ctrl0[0]=(((r).ana_lane_1_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 25581 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_1_quad_d_ctrl0[0]) >> 2) & 0x1) 25582 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_1_quad_d_ctrl0[0]=(((r).ana_lane_1_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 25583 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_1_quad_d_ctrl0[0]) >> 1) & 0x1) 25584 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_1_quad_d_ctrl0[0]=(((r).ana_lane_1_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 25585 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_1_quad_d_ctrl0[0]) & 0x1) 25586 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_1_quad_d_ctrl0[0]=(((r).ana_lane_1_quad_d_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 25587 25588 /* 25589 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL0. 25590 */ 25591 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r,_r._ana_lane_1_quad_d_ctrl0) 25592 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r,_r._ana_lane_1_quad_d_ctrl0) 25593 25594 /* 25595 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25596 * will be redefined without the chip prefix for easier programming. 25597 * If multiple chips will be programmed in the same source file, then you should 25598 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25599 * and refer to the fully qualified versions. 25600 */ 25601 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25602 25603 #define ANA_LANE_1_QUAD_D_CTRL0r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r 25604 #define ANA_LANE_1_QUAD_D_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_SIZE 25605 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_t ANA_LANE_1_QUAD_D_CTRL0r_t; 25606 #define ANA_LANE_1_QUAD_D_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_CLR 25607 #define ANA_LANE_1_QUAD_D_CTRL0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_SET 25608 #define ANA_LANE_1_QUAD_D_CTRL0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_GET 25609 #define ANA_LANE_1_QUAD_D_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_DC_COUPLEf_GET 25610 #define ANA_LANE_1_QUAD_D_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_DC_COUPLEf_SET 25611 #define ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET 25612 #define ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET 25613 #define ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET 25614 #define ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET 25615 #define ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET 25616 #define ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET 25617 #define ANA_LANE_1_QUAD_D_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RXTX_PWRDNf_GET 25618 #define ANA_LANE_1_QUAD_D_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r_RXTX_PWRDNf_SET 25619 #define READ_ANA_LANE_1_QUAD_D_CTRL0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL0r 25620 #define WRITE_ANA_LANE_1_QUAD_D_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL0r 25621 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL0r 25622 25623 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25624 /******************************************************************************* 25625 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL0r' 25626 */ 25627 25628 25629 25630 25631 /******************************************************************************* 25632 * CHIP: BCMI_HURACAN 25633 * REGISTER: ANA_LANE_1_QUAD_D_CTRL1 25634 * BLOCKS: ANA_LANE_1_QUAD_D 25635 * REGADDR: 0xb201 25636 * DEVAD: 1 25637 * DESC: control registers 0 25638 * RESETVAL: 0x0 (0) 25639 * ACCESS: R/W 25640 * FIELDS: 25641 * RX_SIGDET_THRESHOLD 25642 * REF_OCL 25643 * OCL_PWRDN 25644 * OCL_DISABLE_LOOP 25645 * RXTX_RESERVED_FOR_15_12 25646 */ 25647 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r (0x0001b201 | PHYMOD_REG_ACC_RAW) 25648 25649 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_SIZE 4 25650 25651 /* 25652 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL1. 25653 */ 25654 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_s { 25655 uint32_t v[1]; 25656 uint32_t ana_lane_1_quad_d_ctrl1[1]; 25657 uint32_t _ana_lane_1_quad_d_ctrl1; 25658 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_t; 25659 25660 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_CLR(r) (r).ana_lane_1_quad_d_ctrl1[0] = 0 25661 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_SET(r,d) (r).ana_lane_1_quad_d_ctrl1[0] = d 25662 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_GET(r) (r).ana_lane_1_quad_d_ctrl1[0] 25663 25664 /* 25665 * These macros can be used to access individual fields. 25666 */ 25667 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_1_quad_d_ctrl1[0]) >> 12) & 0xf) 25668 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_1_quad_d_ctrl1[0]=(((r).ana_lane_1_quad_d_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 25669 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_1_quad_d_ctrl1[0]) >> 9) & 0x1) 25670 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_1_quad_d_ctrl1[0]=(((r).ana_lane_1_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 25671 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_1_quad_d_ctrl1[0]) >> 8) & 0x1) 25672 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_1_quad_d_ctrl1[0]=(((r).ana_lane_1_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 25673 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_1_quad_d_ctrl1[0]) >> 4) & 0x3) 25674 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_1_quad_d_ctrl1[0]=(((r).ana_lane_1_quad_d_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 25675 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_1_quad_d_ctrl1[0]) & 0x7) 25676 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_1_quad_d_ctrl1[0]=(((r).ana_lane_1_quad_d_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 25677 25678 /* 25679 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL1. 25680 */ 25681 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r,_r._ana_lane_1_quad_d_ctrl1) 25682 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r,_r._ana_lane_1_quad_d_ctrl1) 25683 25684 /* 25685 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25686 * will be redefined without the chip prefix for easier programming. 25687 * If multiple chips will be programmed in the same source file, then you should 25688 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25689 * and refer to the fully qualified versions. 25690 */ 25691 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25692 25693 #define ANA_LANE_1_QUAD_D_CTRL1r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r 25694 #define ANA_LANE_1_QUAD_D_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_SIZE 25695 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_t ANA_LANE_1_QUAD_D_CTRL1r_t; 25696 #define ANA_LANE_1_QUAD_D_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_CLR 25697 #define ANA_LANE_1_QUAD_D_CTRL1r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_SET 25698 #define ANA_LANE_1_QUAD_D_CTRL1r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_GET 25699 #define ANA_LANE_1_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 25700 #define ANA_LANE_1_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 25701 #define ANA_LANE_1_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET 25702 #define ANA_LANE_1_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET 25703 #define ANA_LANE_1_QUAD_D_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_PWRDNf_GET 25704 #define ANA_LANE_1_QUAD_D_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_OCL_PWRDNf_SET 25705 #define ANA_LANE_1_QUAD_D_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_REF_OCLf_GET 25706 #define ANA_LANE_1_QUAD_D_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_REF_OCLf_SET 25707 #define ANA_LANE_1_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET 25708 #define ANA_LANE_1_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET 25709 #define READ_ANA_LANE_1_QUAD_D_CTRL1r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL1r 25710 #define WRITE_ANA_LANE_1_QUAD_D_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL1r 25711 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL1r 25712 25713 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25714 /******************************************************************************* 25715 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL1r' 25716 */ 25717 25718 25719 25720 25721 /******************************************************************************* 25722 * CHIP: BCMI_HURACAN 25723 * REGISTER: ANA_LANE_1_QUAD_D_CTRL2 25724 * BLOCKS: ANA_LANE_1_QUAD_D 25725 * REGADDR: 0xb202 25726 * DEVAD: 1 25727 * DESC: control registers 0 25728 * RESETVAL: 0x0 (0) 25729 * ACCESS: R/W 25730 * FIELDS: 25731 * CTLE_ENB_NEGIMP 25732 * CTLE_ENB_NEGCAP 25733 */ 25734 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r (0x0001b202 | PHYMOD_REG_ACC_RAW) 25735 25736 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_SIZE 4 25737 25738 /* 25739 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL2. 25740 */ 25741 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_s { 25742 uint32_t v[1]; 25743 uint32_t ana_lane_1_quad_d_ctrl2[1]; 25744 uint32_t _ana_lane_1_quad_d_ctrl2; 25745 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_t; 25746 25747 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CLR(r) (r).ana_lane_1_quad_d_ctrl2[0] = 0 25748 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_SET(r,d) (r).ana_lane_1_quad_d_ctrl2[0] = d 25749 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_GET(r) (r).ana_lane_1_quad_d_ctrl2[0] 25750 25751 /* 25752 * These macros can be used to access individual fields. 25753 */ 25754 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_1_quad_d_ctrl2[0]) >> 8) & 0x7f) 25755 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_1_quad_d_ctrl2[0]=(((r).ana_lane_1_quad_d_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 25756 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_1_quad_d_ctrl2[0]) & 0x7f) 25757 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_1_quad_d_ctrl2[0]=(((r).ana_lane_1_quad_d_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 25758 25759 /* 25760 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL2. 25761 */ 25762 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r,_r._ana_lane_1_quad_d_ctrl2) 25763 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r,_r._ana_lane_1_quad_d_ctrl2) 25764 25765 /* 25766 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25767 * will be redefined without the chip prefix for easier programming. 25768 * If multiple chips will be programmed in the same source file, then you should 25769 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25770 * and refer to the fully qualified versions. 25771 */ 25772 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25773 25774 #define ANA_LANE_1_QUAD_D_CTRL2r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r 25775 #define ANA_LANE_1_QUAD_D_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_SIZE 25776 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_t ANA_LANE_1_QUAD_D_CTRL2r_t; 25777 #define ANA_LANE_1_QUAD_D_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CLR 25778 #define ANA_LANE_1_QUAD_D_CTRL2r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_SET 25779 #define ANA_LANE_1_QUAD_D_CTRL2r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_GET 25780 #define ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET 25781 #define ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET 25782 #define ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET 25783 #define ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET 25784 #define READ_ANA_LANE_1_QUAD_D_CTRL2r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL2r 25785 #define WRITE_ANA_LANE_1_QUAD_D_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL2r 25786 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL2r 25787 25788 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25789 /******************************************************************************* 25790 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL2r' 25791 */ 25792 25793 25794 25795 25796 /******************************************************************************* 25797 * CHIP: BCMI_HURACAN 25798 * REGISTER: ANA_LANE_1_QUAD_D_CTRL3 25799 * BLOCKS: ANA_LANE_1_QUAD_D 25800 * REGADDR: 0xb203 25801 * DEVAD: 1 25802 * DESC: control registers 0 25803 * RESETVAL: 0x0 (0) 25804 * ACCESS: R/W 25805 * FIELDS: 25806 * CTLE_EN_NEGRES 25807 * CTLE_EQSEL 25808 */ 25809 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r (0x0001b203 | PHYMOD_REG_ACC_RAW) 25810 25811 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_SIZE 4 25812 25813 /* 25814 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL3. 25815 */ 25816 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_s { 25817 uint32_t v[1]; 25818 uint32_t ana_lane_1_quad_d_ctrl3[1]; 25819 uint32_t _ana_lane_1_quad_d_ctrl3; 25820 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_t; 25821 25822 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CLR(r) (r).ana_lane_1_quad_d_ctrl3[0] = 0 25823 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_SET(r,d) (r).ana_lane_1_quad_d_ctrl3[0] = d 25824 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_GET(r) (r).ana_lane_1_quad_d_ctrl3[0] 25825 25826 /* 25827 * These macros can be used to access individual fields. 25828 */ 25829 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_1_quad_d_ctrl3[0]) >> 8) & 0xff) 25830 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_1_quad_d_ctrl3[0]=(((r).ana_lane_1_quad_d_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 25831 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_1_quad_d_ctrl3[0]) & 0x7f) 25832 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_1_quad_d_ctrl3[0]=(((r).ana_lane_1_quad_d_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 25833 25834 /* 25835 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL3. 25836 */ 25837 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r,_r._ana_lane_1_quad_d_ctrl3) 25838 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r,_r._ana_lane_1_quad_d_ctrl3) 25839 25840 /* 25841 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25842 * will be redefined without the chip prefix for easier programming. 25843 * If multiple chips will be programmed in the same source file, then you should 25844 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25845 * and refer to the fully qualified versions. 25846 */ 25847 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25848 25849 #define ANA_LANE_1_QUAD_D_CTRL3r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r 25850 #define ANA_LANE_1_QUAD_D_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_SIZE 25851 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_t ANA_LANE_1_QUAD_D_CTRL3r_t; 25852 #define ANA_LANE_1_QUAD_D_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CLR 25853 #define ANA_LANE_1_QUAD_D_CTRL3r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_SET 25854 #define ANA_LANE_1_QUAD_D_CTRL3r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_GET 25855 #define ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EQSELf_GET 25856 #define ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EQSELf_SET 25857 #define ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET 25858 #define ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET 25859 #define READ_ANA_LANE_1_QUAD_D_CTRL3r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL3r 25860 #define WRITE_ANA_LANE_1_QUAD_D_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL3r 25861 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL3r 25862 25863 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25864 /******************************************************************************* 25865 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL3r' 25866 */ 25867 25868 25869 25870 25871 /******************************************************************************* 25872 * CHIP: BCMI_HURACAN 25873 * REGISTER: ANA_LANE_1_QUAD_D_CTRL4 25874 * BLOCKS: ANA_LANE_1_QUAD_D 25875 * REGADDR: 0xb204 25876 * DEVAD: 1 25877 * DESC: control registers 0 25878 * RESETVAL: 0x0 (0) 25879 * ACCESS: R/W 25880 * FIELDS: 25881 * CTLE_LZEN 25882 * RXTX_RESERVED_FOR_59_52 25883 */ 25884 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r (0x0001b204 | PHYMOD_REG_ACC_RAW) 25885 25886 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_SIZE 4 25887 25888 /* 25889 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL4. 25890 */ 25891 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_s { 25892 uint32_t v[1]; 25893 uint32_t ana_lane_1_quad_d_ctrl4[1]; 25894 uint32_t _ana_lane_1_quad_d_ctrl4; 25895 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_t; 25896 25897 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_CLR(r) (r).ana_lane_1_quad_d_ctrl4[0] = 0 25898 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_SET(r,d) (r).ana_lane_1_quad_d_ctrl4[0] = d 25899 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_GET(r) (r).ana_lane_1_quad_d_ctrl4[0] 25900 25901 /* 25902 * These macros can be used to access individual fields. 25903 */ 25904 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_1_quad_d_ctrl4[0]) >> 4) & 0xff) 25905 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_1_quad_d_ctrl4[0]=(((r).ana_lane_1_quad_d_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 25906 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_1_quad_d_ctrl4[0]) & 0x1) 25907 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_1_quad_d_ctrl4[0]=(((r).ana_lane_1_quad_d_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 25908 25909 /* 25910 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL4. 25911 */ 25912 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r,_r._ana_lane_1_quad_d_ctrl4) 25913 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r,_r._ana_lane_1_quad_d_ctrl4) 25914 25915 /* 25916 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25917 * will be redefined without the chip prefix for easier programming. 25918 * If multiple chips will be programmed in the same source file, then you should 25919 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25920 * and refer to the fully qualified versions. 25921 */ 25922 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 25923 25924 #define ANA_LANE_1_QUAD_D_CTRL4r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r 25925 #define ANA_LANE_1_QUAD_D_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_SIZE 25926 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_t ANA_LANE_1_QUAD_D_CTRL4r_t; 25927 #define ANA_LANE_1_QUAD_D_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_CLR 25928 #define ANA_LANE_1_QUAD_D_CTRL4r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_SET 25929 #define ANA_LANE_1_QUAD_D_CTRL4r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_GET 25930 #define ANA_LANE_1_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 25931 #define ANA_LANE_1_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 25932 #define ANA_LANE_1_QUAD_D_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_CTLE_LZENf_GET 25933 #define ANA_LANE_1_QUAD_D_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r_CTLE_LZENf_SET 25934 #define READ_ANA_LANE_1_QUAD_D_CTRL4r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL4r 25935 #define WRITE_ANA_LANE_1_QUAD_D_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL4r 25936 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL4r 25937 25938 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 25939 /******************************************************************************* 25940 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL4r' 25941 */ 25942 25943 25944 25945 25946 /******************************************************************************* 25947 * CHIP: BCMI_HURACAN 25948 * REGISTER: ANA_LANE_1_QUAD_D_CTRL5 25949 * BLOCKS: ANA_LANE_1_QUAD_D 25950 * REGADDR: 0xb205 25951 * DEVAD: 1 25952 * DESC: control registers 0 25953 * RESETVAL: 0x0 (0) 25954 * ACCESS: R/W 25955 * FIELDS: 25956 * CTLE_LOPEAKING 25957 * CTLE_PD 25958 * LA_GCTRL 25959 */ 25960 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r (0x0001b205 | PHYMOD_REG_ACC_RAW) 25961 25962 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_SIZE 4 25963 25964 /* 25965 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL5. 25966 */ 25967 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_s { 25968 uint32_t v[1]; 25969 uint32_t ana_lane_1_quad_d_ctrl5[1]; 25970 uint32_t _ana_lane_1_quad_d_ctrl5; 25971 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_t; 25972 25973 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CLR(r) (r).ana_lane_1_quad_d_ctrl5[0] = 0 25974 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_SET(r,d) (r).ana_lane_1_quad_d_ctrl5[0] = d 25975 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_GET(r) (r).ana_lane_1_quad_d_ctrl5[0] 25976 25977 /* 25978 * These macros can be used to access individual fields. 25979 */ 25980 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_1_quad_d_ctrl5[0]) >> 4) & 0x3ff) 25981 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_1_quad_d_ctrl5[0]=(((r).ana_lane_1_quad_d_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 25982 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_1_quad_d_ctrl5[0]) >> 1) & 0x1) 25983 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_1_quad_d_ctrl5[0]=(((r).ana_lane_1_quad_d_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 25984 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_1_quad_d_ctrl5[0]) & 0x1) 25985 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_1_quad_d_ctrl5[0]=(((r).ana_lane_1_quad_d_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 25986 25987 /* 25988 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL5. 25989 */ 25990 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r,_r._ana_lane_1_quad_d_ctrl5) 25991 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r,_r._ana_lane_1_quad_d_ctrl5) 25992 25993 /* 25994 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 25995 * will be redefined without the chip prefix for easier programming. 25996 * If multiple chips will be programmed in the same source file, then you should 25997 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 25998 * and refer to the fully qualified versions. 25999 */ 26000 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26001 26002 #define ANA_LANE_1_QUAD_D_CTRL5r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r 26003 #define ANA_LANE_1_QUAD_D_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_SIZE 26004 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_t ANA_LANE_1_QUAD_D_CTRL5r_t; 26005 #define ANA_LANE_1_QUAD_D_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CLR 26006 #define ANA_LANE_1_QUAD_D_CTRL5r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_SET 26007 #define ANA_LANE_1_QUAD_D_CTRL5r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_GET 26008 #define ANA_LANE_1_QUAD_D_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_LA_GCTRLf_GET 26009 #define ANA_LANE_1_QUAD_D_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_LA_GCTRLf_SET 26010 #define ANA_LANE_1_QUAD_D_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_PDf_GET 26011 #define ANA_LANE_1_QUAD_D_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_PDf_SET 26012 #define ANA_LANE_1_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET 26013 #define ANA_LANE_1_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET 26014 #define READ_ANA_LANE_1_QUAD_D_CTRL5r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL5r 26015 #define WRITE_ANA_LANE_1_QUAD_D_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL5r 26016 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL5r 26017 26018 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26019 /******************************************************************************* 26020 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL5r' 26021 */ 26022 26023 26024 26025 26026 /******************************************************************************* 26027 * CHIP: BCMI_HURACAN 26028 * REGISTER: ANA_LANE_1_QUAD_D_CTRL6 26029 * BLOCKS: ANA_LANE_1_QUAD_D 26030 * REGADDR: 0xb206 26031 * DEVAD: 1 26032 * DESC: control registers 0 26033 * RESETVAL: 0x0 (0) 26034 * ACCESS: R/W 26035 * FIELDS: 26036 * LA_DEGAIN 26037 * LA_DETUNE 26038 */ 26039 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r (0x0001b206 | PHYMOD_REG_ACC_RAW) 26040 26041 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_SIZE 4 26042 26043 /* 26044 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL6. 26045 */ 26046 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_s { 26047 uint32_t v[1]; 26048 uint32_t ana_lane_1_quad_d_ctrl6[1]; 26049 uint32_t _ana_lane_1_quad_d_ctrl6; 26050 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_t; 26051 26052 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_CLR(r) (r).ana_lane_1_quad_d_ctrl6[0] = 0 26053 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_SET(r,d) (r).ana_lane_1_quad_d_ctrl6[0] = d 26054 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_GET(r) (r).ana_lane_1_quad_d_ctrl6[0] 26055 26056 /* 26057 * These macros can be used to access individual fields. 26058 */ 26059 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_1_quad_d_ctrl6[0]) >> 8) & 0xff) 26060 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_1_quad_d_ctrl6[0]=(((r).ana_lane_1_quad_d_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 26061 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_1_quad_d_ctrl6[0]) & 0x1f) 26062 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_1_quad_d_ctrl6[0]=(((r).ana_lane_1_quad_d_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 26063 26064 /* 26065 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL6. 26066 */ 26067 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r,_r._ana_lane_1_quad_d_ctrl6) 26068 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r,_r._ana_lane_1_quad_d_ctrl6) 26069 26070 /* 26071 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26072 * will be redefined without the chip prefix for easier programming. 26073 * If multiple chips will be programmed in the same source file, then you should 26074 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26075 * and refer to the fully qualified versions. 26076 */ 26077 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26078 26079 #define ANA_LANE_1_QUAD_D_CTRL6r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r 26080 #define ANA_LANE_1_QUAD_D_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_SIZE 26081 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_t ANA_LANE_1_QUAD_D_CTRL6r_t; 26082 #define ANA_LANE_1_QUAD_D_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_CLR 26083 #define ANA_LANE_1_QUAD_D_CTRL6r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_SET 26084 #define ANA_LANE_1_QUAD_D_CTRL6r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_GET 26085 #define ANA_LANE_1_QUAD_D_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DETUNEf_GET 26086 #define ANA_LANE_1_QUAD_D_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DETUNEf_SET 26087 #define ANA_LANE_1_QUAD_D_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DEGAINf_GET 26088 #define ANA_LANE_1_QUAD_D_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r_LA_DEGAINf_SET 26089 #define READ_ANA_LANE_1_QUAD_D_CTRL6r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL6r 26090 #define WRITE_ANA_LANE_1_QUAD_D_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL6r 26091 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL6r 26092 26093 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26094 /******************************************************************************* 26095 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL6r' 26096 */ 26097 26098 26099 26100 26101 /******************************************************************************* 26102 * CHIP: BCMI_HURACAN 26103 * REGISTER: ANA_LANE_1_QUAD_D_CTRL7 26104 * BLOCKS: ANA_LANE_1_QUAD_D 26105 * REGADDR: 0xb207 26106 * DEVAD: 1 26107 * DESC: control registers 0 26108 * RESETVAL: 0x0 (0) 26109 * ACCESS: R/W 26110 * FIELDS: 26111 * LA_LIN_MODE 26112 * RX_BIAS_FB_PDN 26113 */ 26114 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r (0x0001b207 | PHYMOD_REG_ACC_RAW) 26115 26116 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_SIZE 4 26117 26118 /* 26119 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL7. 26120 */ 26121 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_s { 26122 uint32_t v[1]; 26123 uint32_t ana_lane_1_quad_d_ctrl7[1]; 26124 uint32_t _ana_lane_1_quad_d_ctrl7; 26125 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_t; 26126 26127 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_CLR(r) (r).ana_lane_1_quad_d_ctrl7[0] = 0 26128 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_SET(r,d) (r).ana_lane_1_quad_d_ctrl7[0] = d 26129 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_GET(r) (r).ana_lane_1_quad_d_ctrl7[0] 26130 26131 /* 26132 * These macros can be used to access individual fields. 26133 */ 26134 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_1_quad_d_ctrl7[0]) >> 8) & 0x1) 26135 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_1_quad_d_ctrl7[0]=(((r).ana_lane_1_quad_d_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 26136 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_1_quad_d_ctrl7[0]) & 0x1f) 26137 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_1_quad_d_ctrl7[0]=(((r).ana_lane_1_quad_d_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 26138 26139 /* 26140 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL7. 26141 */ 26142 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r,_r._ana_lane_1_quad_d_ctrl7) 26143 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r,_r._ana_lane_1_quad_d_ctrl7) 26144 26145 /* 26146 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26147 * will be redefined without the chip prefix for easier programming. 26148 * If multiple chips will be programmed in the same source file, then you should 26149 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26150 * and refer to the fully qualified versions. 26151 */ 26152 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26153 26154 #define ANA_LANE_1_QUAD_D_CTRL7r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r 26155 #define ANA_LANE_1_QUAD_D_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_SIZE 26156 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_t ANA_LANE_1_QUAD_D_CTRL7r_t; 26157 #define ANA_LANE_1_QUAD_D_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_CLR 26158 #define ANA_LANE_1_QUAD_D_CTRL7r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_SET 26159 #define ANA_LANE_1_QUAD_D_CTRL7r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_GET 26160 #define ANA_LANE_1_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET 26161 #define ANA_LANE_1_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET 26162 #define ANA_LANE_1_QUAD_D_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_LA_LIN_MODEf_GET 26163 #define ANA_LANE_1_QUAD_D_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r_LA_LIN_MODEf_SET 26164 #define READ_ANA_LANE_1_QUAD_D_CTRL7r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL7r 26165 #define WRITE_ANA_LANE_1_QUAD_D_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL7r 26166 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL7r 26167 26168 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26169 /******************************************************************************* 26170 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL7r' 26171 */ 26172 26173 26174 26175 26176 /******************************************************************************* 26177 * CHIP: BCMI_HURACAN 26178 * REGISTER: ANA_LANE_1_QUAD_D_CTRL8 26179 * BLOCKS: ANA_LANE_1_QUAD_D 26180 * REGADDR: 0xb208 26181 * DEVAD: 1 26182 * DESC: control registers 0 26183 * RESETVAL: 0x0 (0) 26184 * ACCESS: R/W 26185 * FIELDS: 26186 * LA_PD 26187 * LA_PD_IDLE 26188 * RXTX_RESERVED_FOR_99_95 26189 */ 26190 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r (0x0001b208 | PHYMOD_REG_ACC_RAW) 26191 26192 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_SIZE 4 26193 26194 /* 26195 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL8. 26196 */ 26197 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_s { 26198 uint32_t v[1]; 26199 uint32_t ana_lane_1_quad_d_ctrl8[1]; 26200 uint32_t _ana_lane_1_quad_d_ctrl8; 26201 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_t; 26202 26203 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_CLR(r) (r).ana_lane_1_quad_d_ctrl8[0] = 0 26204 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_SET(r,d) (r).ana_lane_1_quad_d_ctrl8[0] = d 26205 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_GET(r) (r).ana_lane_1_quad_d_ctrl8[0] 26206 26207 /* 26208 * These macros can be used to access individual fields. 26209 */ 26210 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_1_quad_d_ctrl8[0]) >> 4) & 0x1f) 26211 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_1_quad_d_ctrl8[0]=(((r).ana_lane_1_quad_d_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 26212 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_1_quad_d_ctrl8[0]) >> 1) & 0x1) 26213 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_1_quad_d_ctrl8[0]=(((r).ana_lane_1_quad_d_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 26214 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_1_quad_d_ctrl8[0]) & 0x1) 26215 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_1_quad_d_ctrl8[0]=(((r).ana_lane_1_quad_d_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 26216 26217 /* 26218 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL8. 26219 */ 26220 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r,_r._ana_lane_1_quad_d_ctrl8) 26221 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r,_r._ana_lane_1_quad_d_ctrl8) 26222 26223 /* 26224 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26225 * will be redefined without the chip prefix for easier programming. 26226 * If multiple chips will be programmed in the same source file, then you should 26227 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26228 * and refer to the fully qualified versions. 26229 */ 26230 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26231 26232 #define ANA_LANE_1_QUAD_D_CTRL8r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r 26233 #define ANA_LANE_1_QUAD_D_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_SIZE 26234 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_t ANA_LANE_1_QUAD_D_CTRL8r_t; 26235 #define ANA_LANE_1_QUAD_D_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_CLR 26236 #define ANA_LANE_1_QUAD_D_CTRL8r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_SET 26237 #define ANA_LANE_1_QUAD_D_CTRL8r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_GET 26238 #define ANA_LANE_1_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 26239 #define ANA_LANE_1_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 26240 #define ANA_LANE_1_QUAD_D_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PD_IDLEf_GET 26241 #define ANA_LANE_1_QUAD_D_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PD_IDLEf_SET 26242 #define ANA_LANE_1_QUAD_D_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PDf_GET 26243 #define ANA_LANE_1_QUAD_D_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r_LA_PDf_SET 26244 #define READ_ANA_LANE_1_QUAD_D_CTRL8r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL8r 26245 #define WRITE_ANA_LANE_1_QUAD_D_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL8r 26246 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL8r 26247 26248 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26249 /******************************************************************************* 26250 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL8r' 26251 */ 26252 26253 26254 26255 26256 /******************************************************************************* 26257 * CHIP: BCMI_HURACAN 26258 * REGISTER: ANA_LANE_1_QUAD_D_CTRL9 26259 * BLOCKS: ANA_LANE_1_QUAD_D 26260 * REGADDR: 0xb209 26261 * DEVAD: 1 26262 * DESC: control registers 0 26263 * RESETVAL: 0x0 (0) 26264 * ACCESS: R/W 26265 * FIELDS: 26266 * DRV_POST1 26267 * DLINE_SWING_1 26268 * DLINE_SWING_2 26269 * DLINE_DELAY_CTRL 26270 */ 26271 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r (0x0001b209 | PHYMOD_REG_ACC_RAW) 26272 26273 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_SIZE 4 26274 26275 /* 26276 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL9. 26277 */ 26278 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_s { 26279 uint32_t v[1]; 26280 uint32_t ana_lane_1_quad_d_ctrl9[1]; 26281 uint32_t _ana_lane_1_quad_d_ctrl9; 26282 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_t; 26283 26284 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_CLR(r) (r).ana_lane_1_quad_d_ctrl9[0] = 0 26285 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_SET(r,d) (r).ana_lane_1_quad_d_ctrl9[0] = d 26286 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_GET(r) (r).ana_lane_1_quad_d_ctrl9[0] 26287 26288 /* 26289 * These macros can be used to access individual fields. 26290 */ 26291 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_1_quad_d_ctrl9[0]) >> 12) & 0x7) 26292 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_1_quad_d_ctrl9[0]=(((r).ana_lane_1_quad_d_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 26293 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_1_quad_d_ctrl9[0]) >> 8) & 0x3) 26294 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_1_quad_d_ctrl9[0]=(((r).ana_lane_1_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 26295 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_1_quad_d_ctrl9[0]) >> 4) & 0x3) 26296 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_1_quad_d_ctrl9[0]=(((r).ana_lane_1_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 26297 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_1_quad_d_ctrl9[0]) & 0xf) 26298 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_1_quad_d_ctrl9[0]=(((r).ana_lane_1_quad_d_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 26299 26300 /* 26301 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL9. 26302 */ 26303 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r,_r._ana_lane_1_quad_d_ctrl9) 26304 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r,_r._ana_lane_1_quad_d_ctrl9) 26305 26306 /* 26307 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26308 * will be redefined without the chip prefix for easier programming. 26309 * If multiple chips will be programmed in the same source file, then you should 26310 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26311 * and refer to the fully qualified versions. 26312 */ 26313 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26314 26315 #define ANA_LANE_1_QUAD_D_CTRL9r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r 26316 #define ANA_LANE_1_QUAD_D_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_SIZE 26317 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_t ANA_LANE_1_QUAD_D_CTRL9r_t; 26318 #define ANA_LANE_1_QUAD_D_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_CLR 26319 #define ANA_LANE_1_QUAD_D_CTRL9r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_SET 26320 #define ANA_LANE_1_QUAD_D_CTRL9r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_GET 26321 #define ANA_LANE_1_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET 26322 #define ANA_LANE_1_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET 26323 #define ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_2f_GET 26324 #define ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_2f_SET 26325 #define ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_1f_GET 26326 #define ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DLINE_SWING_1f_SET 26327 #define ANA_LANE_1_QUAD_D_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DRV_POST1f_GET 26328 #define ANA_LANE_1_QUAD_D_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r_DRV_POST1f_SET 26329 #define READ_ANA_LANE_1_QUAD_D_CTRL9r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL9r 26330 #define WRITE_ANA_LANE_1_QUAD_D_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL9r 26331 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL9r 26332 26333 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26334 /******************************************************************************* 26335 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL9r' 26336 */ 26337 26338 26339 26340 26341 /******************************************************************************* 26342 * CHIP: BCMI_HURACAN 26343 * REGISTER: ANA_LANE_1_QUAD_D_CTRL10 26344 * BLOCKS: ANA_LANE_1_QUAD_D 26345 * REGADDR: 0xb20a 26346 * DEVAD: 1 26347 * DESC: control registers 0 26348 * RESETVAL: 0x0 (0) 26349 * ACCESS: R/W 26350 * FIELDS: 26351 * DRV_PWD 26352 * DLINE_PWD 26353 * DRV_VBSEL 26354 * DRV_MAIN 26355 * DRV_MAIN_PU 26356 */ 26357 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r (0x0001b20a | PHYMOD_REG_ACC_RAW) 26358 26359 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_SIZE 4 26360 26361 /* 26362 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL10. 26363 */ 26364 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_s { 26365 uint32_t v[1]; 26366 uint32_t ana_lane_1_quad_d_ctrl10[1]; 26367 uint32_t _ana_lane_1_quad_d_ctrl10; 26368 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_t; 26369 26370 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_CLR(r) (r).ana_lane_1_quad_d_ctrl10[0] = 0 26371 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_SET(r,d) (r).ana_lane_1_quad_d_ctrl10[0] = d 26372 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_GET(r) (r).ana_lane_1_quad_d_ctrl10[0] 26373 26374 /* 26375 * These macros can be used to access individual fields. 26376 */ 26377 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_1_quad_d_ctrl10[0]) >> 12) & 0xf) 26378 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_1_quad_d_ctrl10[0]=(((r).ana_lane_1_quad_d_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 26379 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_1_quad_d_ctrl10[0]) >> 4) & 0x3f) 26380 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_1_quad_d_ctrl10[0]=(((r).ana_lane_1_quad_d_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 26381 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_1_quad_d_ctrl10[0]) >> 2) & 0x1) 26382 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_1_quad_d_ctrl10[0]=(((r).ana_lane_1_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 26383 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_1_quad_d_ctrl10[0]) >> 1) & 0x1) 26384 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_1_quad_d_ctrl10[0]=(((r).ana_lane_1_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 26385 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_1_quad_d_ctrl10[0]) & 0x1) 26386 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_1_quad_d_ctrl10[0]=(((r).ana_lane_1_quad_d_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 26387 26388 /* 26389 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL10. 26390 */ 26391 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r,_r._ana_lane_1_quad_d_ctrl10) 26392 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r,_r._ana_lane_1_quad_d_ctrl10) 26393 26394 /* 26395 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26396 * will be redefined without the chip prefix for easier programming. 26397 * If multiple chips will be programmed in the same source file, then you should 26398 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26399 * and refer to the fully qualified versions. 26400 */ 26401 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26402 26403 #define ANA_LANE_1_QUAD_D_CTRL10r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r 26404 #define ANA_LANE_1_QUAD_D_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_SIZE 26405 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_t ANA_LANE_1_QUAD_D_CTRL10r_t; 26406 #define ANA_LANE_1_QUAD_D_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_CLR 26407 #define ANA_LANE_1_QUAD_D_CTRL10r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_SET 26408 #define ANA_LANE_1_QUAD_D_CTRL10r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_GET 26409 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET 26410 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET 26411 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAINf_GET 26412 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_MAINf_SET 26413 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_VBSELf_GET 26414 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_VBSELf_SET 26415 #define ANA_LANE_1_QUAD_D_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DLINE_PWDf_GET 26416 #define ANA_LANE_1_QUAD_D_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DLINE_PWDf_SET 26417 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_PWDf_GET 26418 #define ANA_LANE_1_QUAD_D_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r_DRV_PWDf_SET 26419 #define READ_ANA_LANE_1_QUAD_D_CTRL10r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL10r 26420 #define WRITE_ANA_LANE_1_QUAD_D_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL10r 26421 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL10r 26422 26423 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26424 /******************************************************************************* 26425 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL10r' 26426 */ 26427 26428 26429 26430 26431 /******************************************************************************* 26432 * CHIP: BCMI_HURACAN 26433 * REGISTER: ANA_LANE_1_QUAD_D_CTRL11 26434 * BLOCKS: ANA_LANE_1_QUAD_D 26435 * REGADDR: 0xb20b 26436 * DEVAD: 1 26437 * DESC: control registers 0 26438 * RESETVAL: 0x0 (0) 26439 * ACCESS: R/W 26440 * FIELDS: 26441 * RXTX_RESERVED_FOR_143_128 26442 */ 26443 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r (0x0001b20b | PHYMOD_REG_ACC_RAW) 26444 26445 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_SIZE 4 26446 26447 /* 26448 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL11. 26449 */ 26450 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_s { 26451 uint32_t v[1]; 26452 uint32_t ana_lane_1_quad_d_ctrl11[1]; 26453 uint32_t _ana_lane_1_quad_d_ctrl11; 26454 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_t; 26455 26456 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_CLR(r) (r).ana_lane_1_quad_d_ctrl11[0] = 0 26457 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_SET(r,d) (r).ana_lane_1_quad_d_ctrl11[0] = d 26458 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_GET(r) (r).ana_lane_1_quad_d_ctrl11[0] 26459 26460 /* 26461 * These macros can be used to access individual fields. 26462 */ 26463 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_1_quad_d_ctrl11[0]) & 0xffff) 26464 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_1_quad_d_ctrl11[0]=(((r).ana_lane_1_quad_d_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 26465 26466 /* 26467 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL11. 26468 */ 26469 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r,_r._ana_lane_1_quad_d_ctrl11) 26470 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r,_r._ana_lane_1_quad_d_ctrl11) 26471 26472 /* 26473 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26474 * will be redefined without the chip prefix for easier programming. 26475 * If multiple chips will be programmed in the same source file, then you should 26476 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26477 * and refer to the fully qualified versions. 26478 */ 26479 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26480 26481 #define ANA_LANE_1_QUAD_D_CTRL11r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r 26482 #define ANA_LANE_1_QUAD_D_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_SIZE 26483 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_t ANA_LANE_1_QUAD_D_CTRL11r_t; 26484 #define ANA_LANE_1_QUAD_D_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_CLR 26485 #define ANA_LANE_1_QUAD_D_CTRL11r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_SET 26486 #define ANA_LANE_1_QUAD_D_CTRL11r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_GET 26487 #define ANA_LANE_1_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 26488 #define ANA_LANE_1_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 26489 #define READ_ANA_LANE_1_QUAD_D_CTRL11r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL11r 26490 #define WRITE_ANA_LANE_1_QUAD_D_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL11r 26491 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL11r 26492 26493 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26494 /******************************************************************************* 26495 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL11r' 26496 */ 26497 26498 26499 26500 26501 /******************************************************************************* 26502 * CHIP: BCMI_HURACAN 26503 * REGISTER: ANA_LANE_1_QUAD_D_CTRL12 26504 * BLOCKS: ANA_LANE_1_QUAD_D 26505 * REGADDR: 0xb20c 26506 * DEVAD: 1 26507 * DESC: control registers 0 26508 * RESETVAL: 0x0 (0) 26509 * ACCESS: R/W 26510 * FIELDS: 26511 * LA_RESCAL_FRC_VAL 26512 * LA_RESCAL_FRC 26513 * DRV_RESCAL_FRC_VAL 26514 * DRV_RESCAL_FRC 26515 */ 26516 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r (0x0001b20c | PHYMOD_REG_ACC_RAW) 26517 26518 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_SIZE 4 26519 26520 /* 26521 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL12. 26522 */ 26523 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_s { 26524 uint32_t v[1]; 26525 uint32_t ana_lane_1_quad_d_ctrl12[1]; 26526 uint32_t _ana_lane_1_quad_d_ctrl12; 26527 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_t; 26528 26529 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_CLR(r) (r).ana_lane_1_quad_d_ctrl12[0] = 0 26530 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_SET(r,d) (r).ana_lane_1_quad_d_ctrl12[0] = d 26531 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_GET(r) (r).ana_lane_1_quad_d_ctrl12[0] 26532 26533 /* 26534 * These macros can be used to access individual fields. 26535 */ 26536 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_d_ctrl12[0]) >> 12) & 0x1) 26537 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_d_ctrl12[0]=(((r).ana_lane_1_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 26538 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_d_ctrl12[0]) >> 8) & 0xf) 26539 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_d_ctrl12[0]=(((r).ana_lane_1_quad_d_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 26540 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_d_ctrl12[0]) >> 4) & 0x1) 26541 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_d_ctrl12[0]=(((r).ana_lane_1_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 26542 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_d_ctrl12[0]) & 0xf) 26543 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_d_ctrl12[0]=(((r).ana_lane_1_quad_d_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 26544 26545 /* 26546 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL12. 26547 */ 26548 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r,_r._ana_lane_1_quad_d_ctrl12) 26549 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r,_r._ana_lane_1_quad_d_ctrl12) 26550 26551 /* 26552 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26553 * will be redefined without the chip prefix for easier programming. 26554 * If multiple chips will be programmed in the same source file, then you should 26555 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26556 * and refer to the fully qualified versions. 26557 */ 26558 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26559 26560 #define ANA_LANE_1_QUAD_D_CTRL12r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r 26561 #define ANA_LANE_1_QUAD_D_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_SIZE 26562 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_t ANA_LANE_1_QUAD_D_CTRL12r_t; 26563 #define ANA_LANE_1_QUAD_D_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_CLR 26564 #define ANA_LANE_1_QUAD_D_CTRL12r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_SET 26565 #define ANA_LANE_1_QUAD_D_CTRL12r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_GET 26566 #define ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET 26567 #define ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET 26568 #define ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET 26569 #define ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET 26570 #define ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET 26571 #define ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET 26572 #define ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET 26573 #define ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET 26574 #define READ_ANA_LANE_1_QUAD_D_CTRL12r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL12r 26575 #define WRITE_ANA_LANE_1_QUAD_D_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL12r 26576 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL12r 26577 26578 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26579 /******************************************************************************* 26580 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL12r' 26581 */ 26582 26583 26584 26585 26586 /******************************************************************************* 26587 * CHIP: BCMI_HURACAN 26588 * REGISTER: ANA_LANE_1_QUAD_D_CTRL13 26589 * BLOCKS: ANA_LANE_1_QUAD_D 26590 * REGADDR: 0xb20d 26591 * DEVAD: 1 26592 * DESC: control registers 0 26593 * RESETVAL: 0x0 (0) 26594 * ACCESS: R/W 26595 * FIELDS: 26596 * CTLE_RESCAL_FRC_VAL 26597 * CTLE_RESCAL_FRC 26598 */ 26599 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r (0x0001b20d | PHYMOD_REG_ACC_RAW) 26600 26601 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_SIZE 4 26602 26603 /* 26604 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL13. 26605 */ 26606 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_s { 26607 uint32_t v[1]; 26608 uint32_t ana_lane_1_quad_d_ctrl13[1]; 26609 uint32_t _ana_lane_1_quad_d_ctrl13; 26610 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_t; 26611 26612 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CLR(r) (r).ana_lane_1_quad_d_ctrl13[0] = 0 26613 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_SET(r,d) (r).ana_lane_1_quad_d_ctrl13[0] = d 26614 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_GET(r) (r).ana_lane_1_quad_d_ctrl13[0] 26615 26616 /* 26617 * These macros can be used to access individual fields. 26618 */ 26619 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_1_quad_d_ctrl13[0]) >> 4) & 0x1) 26620 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_1_quad_d_ctrl13[0]=(((r).ana_lane_1_quad_d_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 26621 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_1_quad_d_ctrl13[0]) & 0xf) 26622 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_d_ctrl13[0]=(((r).ana_lane_1_quad_d_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 26623 26624 /* 26625 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL13. 26626 */ 26627 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r,_r._ana_lane_1_quad_d_ctrl13) 26628 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r,_r._ana_lane_1_quad_d_ctrl13) 26629 26630 /* 26631 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26632 * will be redefined without the chip prefix for easier programming. 26633 * If multiple chips will be programmed in the same source file, then you should 26634 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26635 * and refer to the fully qualified versions. 26636 */ 26637 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26638 26639 #define ANA_LANE_1_QUAD_D_CTRL13r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r 26640 #define ANA_LANE_1_QUAD_D_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_SIZE 26641 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_t ANA_LANE_1_QUAD_D_CTRL13r_t; 26642 #define ANA_LANE_1_QUAD_D_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CLR 26643 #define ANA_LANE_1_QUAD_D_CTRL13r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_SET 26644 #define ANA_LANE_1_QUAD_D_CTRL13r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_GET 26645 #define ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET 26646 #define ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET 26647 #define ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 26648 #define ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 26649 #define READ_ANA_LANE_1_QUAD_D_CTRL13r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL13r 26650 #define WRITE_ANA_LANE_1_QUAD_D_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL13r 26651 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL13r 26652 26653 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26654 /******************************************************************************* 26655 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL13r' 26656 */ 26657 26658 26659 26660 26661 /******************************************************************************* 26662 * CHIP: BCMI_HURACAN 26663 * REGISTER: ANA_LANE_1_QUAD_D_CTRL14 26664 * BLOCKS: ANA_LANE_1_QUAD_D 26665 * REGADDR: 0xb20e 26666 * DEVAD: 1 26667 * DESC: control registers 0 26668 * RESETVAL: 0x0 (0) 26669 * ACCESS: R/W 26670 * FIELDS: 26671 * TX_IDLE_FRC_VAL 26672 * TX_IDLE_FRC 26673 * RXSD_IDLE_OVRD 26674 */ 26675 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r (0x0001b20e | PHYMOD_REG_ACC_RAW) 26676 26677 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_SIZE 4 26678 26679 /* 26680 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL14. 26681 */ 26682 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_s { 26683 uint32_t v[1]; 26684 uint32_t ana_lane_1_quad_d_ctrl14[1]; 26685 uint32_t _ana_lane_1_quad_d_ctrl14; 26686 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_t; 26687 26688 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_CLR(r) (r).ana_lane_1_quad_d_ctrl14[0] = 0 26689 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_SET(r,d) (r).ana_lane_1_quad_d_ctrl14[0] = d 26690 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_GET(r) (r).ana_lane_1_quad_d_ctrl14[0] 26691 26692 /* 26693 * These macros can be used to access individual fields. 26694 */ 26695 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_1_quad_d_ctrl14[0]) >> 4) & 0x1) 26696 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_1_quad_d_ctrl14[0]=(((r).ana_lane_1_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 26697 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_1_quad_d_ctrl14[0]) >> 1) & 0x1) 26698 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_1_quad_d_ctrl14[0]=(((r).ana_lane_1_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 26699 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_1_quad_d_ctrl14[0]) & 0x1) 26700 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_d_ctrl14[0]=(((r).ana_lane_1_quad_d_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 26701 26702 /* 26703 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL14. 26704 */ 26705 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r,_r._ana_lane_1_quad_d_ctrl14) 26706 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r,_r._ana_lane_1_quad_d_ctrl14) 26707 26708 /* 26709 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26710 * will be redefined without the chip prefix for easier programming. 26711 * If multiple chips will be programmed in the same source file, then you should 26712 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26713 * and refer to the fully qualified versions. 26714 */ 26715 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26716 26717 #define ANA_LANE_1_QUAD_D_CTRL14r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r 26718 #define ANA_LANE_1_QUAD_D_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_SIZE 26719 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_t ANA_LANE_1_QUAD_D_CTRL14r_t; 26720 #define ANA_LANE_1_QUAD_D_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_CLR 26721 #define ANA_LANE_1_QUAD_D_CTRL14r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_SET 26722 #define ANA_LANE_1_QUAD_D_CTRL14r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_GET 26723 #define ANA_LANE_1_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET 26724 #define ANA_LANE_1_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET 26725 #define ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET 26726 #define ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET 26727 #define ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET 26728 #define ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET 26729 #define READ_ANA_LANE_1_QUAD_D_CTRL14r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL14r 26730 #define WRITE_ANA_LANE_1_QUAD_D_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL14r 26731 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL14r 26732 26733 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26734 /******************************************************************************* 26735 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL14r' 26736 */ 26737 26738 26739 26740 26741 /******************************************************************************* 26742 * CHIP: BCMI_HURACAN 26743 * REGISTER: ANA_LANE_1_QUAD_D_CTRL15 26744 * BLOCKS: ANA_LANE_1_QUAD_D 26745 * REGADDR: 0xb20f 26746 * DEVAD: 1 26747 * DESC: sigdet filter settings 0 26748 * RESETVAL: 0x0 (0) 26749 * ACCESS: R/W 26750 * FIELDS: 26751 * SIGDET_DIS 26752 * SIGDET_1US_EN 26753 * SIGDET_FRC_VAL 26754 * SIGDET_FRC 26755 * HOLD_LOS_COUNT 26756 * HOLD_SD_COUNT 26757 */ 26758 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r (0x0001b20f | PHYMOD_REG_ACC_RAW) 26759 26760 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIZE 4 26761 26762 /* 26763 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL15. 26764 */ 26765 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_s { 26766 uint32_t v[1]; 26767 uint32_t ana_lane_1_quad_d_ctrl15[1]; 26768 uint32_t _ana_lane_1_quad_d_ctrl15; 26769 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_t; 26770 26771 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_CLR(r) (r).ana_lane_1_quad_d_ctrl15[0] = 0 26772 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SET(r,d) (r).ana_lane_1_quad_d_ctrl15[0] = d 26773 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_GET(r) (r).ana_lane_1_quad_d_ctrl15[0] 26774 26775 /* 26776 * These macros can be used to access individual fields. 26777 */ 26778 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_d_ctrl15[0]) >> 8) & 0x7) 26779 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_d_ctrl15[0]=(((r).ana_lane_1_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 26780 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_1_quad_d_ctrl15[0]) >> 4) & 0x7) 26781 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_d_ctrl15[0]=(((r).ana_lane_1_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 26782 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_1_quad_d_ctrl15[0]) >> 3) & 0x1) 26783 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_1_quad_d_ctrl15[0]=(((r).ana_lane_1_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 26784 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_1_quad_d_ctrl15[0]) >> 2) & 0x1) 26785 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_1_quad_d_ctrl15[0]=(((r).ana_lane_1_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 26786 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_1_quad_d_ctrl15[0]) >> 1) & 0x1) 26787 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_1_quad_d_ctrl15[0]=(((r).ana_lane_1_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 26788 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_1_quad_d_ctrl15[0]) & 0x1) 26789 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_1_quad_d_ctrl15[0]=(((r).ana_lane_1_quad_d_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 26790 26791 /* 26792 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL15. 26793 */ 26794 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r,_r._ana_lane_1_quad_d_ctrl15) 26795 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r,_r._ana_lane_1_quad_d_ctrl15) 26796 26797 /* 26798 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26799 * will be redefined without the chip prefix for easier programming. 26800 * If multiple chips will be programmed in the same source file, then you should 26801 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26802 * and refer to the fully qualified versions. 26803 */ 26804 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26805 26806 #define ANA_LANE_1_QUAD_D_CTRL15r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r 26807 #define ANA_LANE_1_QUAD_D_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIZE 26808 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_t ANA_LANE_1_QUAD_D_CTRL15r_t; 26809 #define ANA_LANE_1_QUAD_D_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_CLR 26810 #define ANA_LANE_1_QUAD_D_CTRL15r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SET 26811 #define ANA_LANE_1_QUAD_D_CTRL15r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_GET 26812 #define ANA_LANE_1_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET 26813 #define ANA_LANE_1_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET 26814 #define ANA_LANE_1_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET 26815 #define ANA_LANE_1_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET 26816 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRCf_GET 26817 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRCf_SET 26818 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET 26819 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET 26820 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET 26821 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET 26822 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_DISf_GET 26823 #define ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r_SIGDET_DISf_SET 26824 #define READ_ANA_LANE_1_QUAD_D_CTRL15r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL15r 26825 #define WRITE_ANA_LANE_1_QUAD_D_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL15r 26826 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL15r 26827 26828 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26829 /******************************************************************************* 26830 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL15r' 26831 */ 26832 26833 26834 26835 26836 /******************************************************************************* 26837 * CHIP: BCMI_HURACAN 26838 * REGISTER: ANA_LANE_1_QUAD_D_CTRL16 26839 * BLOCKS: ANA_LANE_1_QUAD_D 26840 * REGADDR: 0xb210 26841 * DEVAD: 1 26842 * DESC: sigdet filter settings 1 26843 * RESETVAL: 0x0 (0) 26844 * ACCESS: R/W 26845 * FIELDS: 26846 * LOS_COUNT 26847 * SD_COUNT 26848 */ 26849 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r (0x0001b210 | PHYMOD_REG_ACC_RAW) 26850 26851 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SIZE 4 26852 26853 /* 26854 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_CTRL16. 26855 */ 26856 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_s { 26857 uint32_t v[1]; 26858 uint32_t ana_lane_1_quad_d_ctrl16[1]; 26859 uint32_t _ana_lane_1_quad_d_ctrl16; 26860 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_t; 26861 26862 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_CLR(r) (r).ana_lane_1_quad_d_ctrl16[0] = 0 26863 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SET(r,d) (r).ana_lane_1_quad_d_ctrl16[0] = d 26864 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_GET(r) (r).ana_lane_1_quad_d_ctrl16[0] 26865 26866 /* 26867 * These macros can be used to access individual fields. 26868 */ 26869 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_1_quad_d_ctrl16[0]) >> 8) & 0x1f) 26870 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_1_quad_d_ctrl16[0]=(((r).ana_lane_1_quad_d_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 26871 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_1_quad_d_ctrl16[0]) & 0x1f) 26872 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_1_quad_d_ctrl16[0]=(((r).ana_lane_1_quad_d_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 26873 26874 /* 26875 * These macros can be used to access ANA_LANE_1_QUAD_D_CTRL16. 26876 */ 26877 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r,_r._ana_lane_1_quad_d_ctrl16) 26878 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r,_r._ana_lane_1_quad_d_ctrl16) 26879 26880 /* 26881 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26882 * will be redefined without the chip prefix for easier programming. 26883 * If multiple chips will be programmed in the same source file, then you should 26884 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26885 * and refer to the fully qualified versions. 26886 */ 26887 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26888 26889 #define ANA_LANE_1_QUAD_D_CTRL16r BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r 26890 #define ANA_LANE_1_QUAD_D_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SIZE 26891 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_t ANA_LANE_1_QUAD_D_CTRL16r_t; 26892 #define ANA_LANE_1_QUAD_D_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_CLR 26893 #define ANA_LANE_1_QUAD_D_CTRL16r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SET 26894 #define ANA_LANE_1_QUAD_D_CTRL16r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_GET 26895 #define ANA_LANE_1_QUAD_D_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SD_COUNTf_GET 26896 #define ANA_LANE_1_QUAD_D_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_SD_COUNTf_SET 26897 #define ANA_LANE_1_QUAD_D_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_LOS_COUNTf_GET 26898 #define ANA_LANE_1_QUAD_D_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r_LOS_COUNTf_SET 26899 #define READ_ANA_LANE_1_QUAD_D_CTRL16r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_CTRL16r 26900 #define WRITE_ANA_LANE_1_QUAD_D_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_CTRL16r 26901 #define MODIFY_ANA_LANE_1_QUAD_D_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_CTRL16r 26902 26903 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26904 /******************************************************************************* 26905 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_CTRL16r' 26906 */ 26907 26908 26909 26910 26911 /******************************************************************************* 26912 * CHIP: BCMI_HURACAN 26913 * REGISTER: ANA_LANE_1_QUAD_D_STATUS0 26914 * BLOCKS: ANA_LANE_1_QUAD_D 26915 * REGADDR: 0xb220 26916 * DEVAD: 1 26917 * DESC: status registers 0 26918 * RESETVAL: 0x0 (0) 26919 * ACCESS: R/W 26920 * FIELDS: 26921 * O_RX_SIGDET 26922 * DG_RX_SIGDET 26923 */ 26924 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r (0x0001b220 | PHYMOD_REG_ACC_RAW) 26925 26926 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_SIZE 4 26927 26928 /* 26929 * This structure should be used to declare and program ANA_LANE_1_QUAD_D_STATUS0. 26930 */ 26931 typedef union BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_s { 26932 uint32_t v[1]; 26933 uint32_t ana_lane_1_quad_d_status0[1]; 26934 uint32_t _ana_lane_1_quad_d_status0; 26935 } BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_t; 26936 26937 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_CLR(r) (r).ana_lane_1_quad_d_status0[0] = 0 26938 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_SET(r,d) (r).ana_lane_1_quad_d_status0[0] = d 26939 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_GET(r) (r).ana_lane_1_quad_d_status0[0] 26940 26941 /* 26942 * These macros can be used to access individual fields. 26943 */ 26944 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_1_quad_d_status0[0]) >> 1) & 0x1) 26945 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_d_status0[0]=(((r).ana_lane_1_quad_d_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 26946 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_1_quad_d_status0[0]) & 0x1) 26947 #define BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_1_quad_d_status0[0]=(((r).ana_lane_1_quad_d_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 26948 26949 /* 26950 * These macros can be used to access ANA_LANE_1_QUAD_D_STATUS0. 26951 */ 26952 #define BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r,_r._ana_lane_1_quad_d_status0) 26953 #define BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r,_r._ana_lane_1_quad_d_status0) 26954 26955 /* 26956 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 26957 * will be redefined without the chip prefix for easier programming. 26958 * If multiple chips will be programmed in the same source file, then you should 26959 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 26960 * and refer to the fully qualified versions. 26961 */ 26962 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 26963 26964 #define ANA_LANE_1_QUAD_D_STATUS0r BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r 26965 #define ANA_LANE_1_QUAD_D_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_SIZE 26966 typedef BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_t ANA_LANE_1_QUAD_D_STATUS0r_t; 26967 #define ANA_LANE_1_QUAD_D_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_CLR 26968 #define ANA_LANE_1_QUAD_D_STATUS0r_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_SET 26969 #define ANA_LANE_1_QUAD_D_STATUS0r_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_GET 26970 #define ANA_LANE_1_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET 26971 #define ANA_LANE_1_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET 26972 #define ANA_LANE_1_QUAD_D_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_O_RX_SIGDETf_GET 26973 #define ANA_LANE_1_QUAD_D_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r_O_RX_SIGDETf_SET 26974 #define READ_ANA_LANE_1_QUAD_D_STATUS0r BCMI_HURACAN_READ_ANA_LANE_1_QUAD_D_STATUS0r 26975 #define WRITE_ANA_LANE_1_QUAD_D_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_1_QUAD_D_STATUS0r 26976 #define MODIFY_ANA_LANE_1_QUAD_D_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_1_QUAD_D_STATUS0r 26977 26978 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 26979 /******************************************************************************* 26980 * End of 'BCMI_HURACAN_ANA_LANE_1_QUAD_D_STATUS0r' 26981 */ 26982 26983 26984 26985 26986 /******************************************************************************* 26987 * CHIP: BCMI_HURACAN 26988 * REGISTER: ANA_LANE_2_QUAD_D_CTRL0 26989 * BLOCKS: ANA_LANE_2_QUAD_D 26990 * REGADDR: 0xb400 26991 * DEVAD: 1 26992 * DESC: control registers 0 26993 * RESETVAL: 0x0 (0) 26994 * ACCESS: R/W 26995 * FIELDS: 26996 * RXTX_PWRDN 26997 * RX_SIGDET_BYPASS 26998 * RX_SIGDET_PWRDN 26999 * RX_SIGDECT_12GMODE 27000 * DC_COUPLE 27001 */ 27002 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r (0x0001b400 | PHYMOD_REG_ACC_RAW) 27003 27004 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_SIZE 4 27005 27006 /* 27007 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL0. 27008 */ 27009 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_s { 27010 uint32_t v[1]; 27011 uint32_t ana_lane_2_quad_d_ctrl0[1]; 27012 uint32_t _ana_lane_2_quad_d_ctrl0; 27013 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_t; 27014 27015 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_CLR(r) (r).ana_lane_2_quad_d_ctrl0[0] = 0 27016 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_SET(r,d) (r).ana_lane_2_quad_d_ctrl0[0] = d 27017 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_GET(r) (r).ana_lane_2_quad_d_ctrl0[0] 27018 27019 /* 27020 * These macros can be used to access individual fields. 27021 */ 27022 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_2_quad_d_ctrl0[0]) >> 4) & 0x1) 27023 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_2_quad_d_ctrl0[0]=(((r).ana_lane_2_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 27024 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_2_quad_d_ctrl0[0]) >> 3) & 0x1) 27025 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_2_quad_d_ctrl0[0]=(((r).ana_lane_2_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 27026 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_2_quad_d_ctrl0[0]) >> 2) & 0x1) 27027 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_2_quad_d_ctrl0[0]=(((r).ana_lane_2_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 27028 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_2_quad_d_ctrl0[0]) >> 1) & 0x1) 27029 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_2_quad_d_ctrl0[0]=(((r).ana_lane_2_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 27030 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_2_quad_d_ctrl0[0]) & 0x1) 27031 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_2_quad_d_ctrl0[0]=(((r).ana_lane_2_quad_d_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 27032 27033 /* 27034 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL0. 27035 */ 27036 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r,_r._ana_lane_2_quad_d_ctrl0) 27037 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r,_r._ana_lane_2_quad_d_ctrl0) 27038 27039 /* 27040 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27041 * will be redefined without the chip prefix for easier programming. 27042 * If multiple chips will be programmed in the same source file, then you should 27043 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27044 * and refer to the fully qualified versions. 27045 */ 27046 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27047 27048 #define ANA_LANE_2_QUAD_D_CTRL0r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r 27049 #define ANA_LANE_2_QUAD_D_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_SIZE 27050 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_t ANA_LANE_2_QUAD_D_CTRL0r_t; 27051 #define ANA_LANE_2_QUAD_D_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_CLR 27052 #define ANA_LANE_2_QUAD_D_CTRL0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_SET 27053 #define ANA_LANE_2_QUAD_D_CTRL0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_GET 27054 #define ANA_LANE_2_QUAD_D_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_DC_COUPLEf_GET 27055 #define ANA_LANE_2_QUAD_D_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_DC_COUPLEf_SET 27056 #define ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET 27057 #define ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET 27058 #define ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET 27059 #define ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET 27060 #define ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET 27061 #define ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET 27062 #define ANA_LANE_2_QUAD_D_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RXTX_PWRDNf_GET 27063 #define ANA_LANE_2_QUAD_D_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r_RXTX_PWRDNf_SET 27064 #define READ_ANA_LANE_2_QUAD_D_CTRL0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL0r 27065 #define WRITE_ANA_LANE_2_QUAD_D_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL0r 27066 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL0r 27067 27068 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27069 /******************************************************************************* 27070 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL0r' 27071 */ 27072 27073 27074 27075 27076 /******************************************************************************* 27077 * CHIP: BCMI_HURACAN 27078 * REGISTER: ANA_LANE_2_QUAD_D_CTRL1 27079 * BLOCKS: ANA_LANE_2_QUAD_D 27080 * REGADDR: 0xb401 27081 * DEVAD: 1 27082 * DESC: control registers 0 27083 * RESETVAL: 0x0 (0) 27084 * ACCESS: R/W 27085 * FIELDS: 27086 * RX_SIGDET_THRESHOLD 27087 * REF_OCL 27088 * OCL_PWRDN 27089 * OCL_DISABLE_LOOP 27090 * RXTX_RESERVED_FOR_15_12 27091 */ 27092 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r (0x0001b401 | PHYMOD_REG_ACC_RAW) 27093 27094 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_SIZE 4 27095 27096 /* 27097 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL1. 27098 */ 27099 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_s { 27100 uint32_t v[1]; 27101 uint32_t ana_lane_2_quad_d_ctrl1[1]; 27102 uint32_t _ana_lane_2_quad_d_ctrl1; 27103 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_t; 27104 27105 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_CLR(r) (r).ana_lane_2_quad_d_ctrl1[0] = 0 27106 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_SET(r,d) (r).ana_lane_2_quad_d_ctrl1[0] = d 27107 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_GET(r) (r).ana_lane_2_quad_d_ctrl1[0] 27108 27109 /* 27110 * These macros can be used to access individual fields. 27111 */ 27112 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_2_quad_d_ctrl1[0]) >> 12) & 0xf) 27113 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_2_quad_d_ctrl1[0]=(((r).ana_lane_2_quad_d_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 27114 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_2_quad_d_ctrl1[0]) >> 9) & 0x1) 27115 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_2_quad_d_ctrl1[0]=(((r).ana_lane_2_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 27116 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_2_quad_d_ctrl1[0]) >> 8) & 0x1) 27117 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_2_quad_d_ctrl1[0]=(((r).ana_lane_2_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 27118 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_2_quad_d_ctrl1[0]) >> 4) & 0x3) 27119 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_2_quad_d_ctrl1[0]=(((r).ana_lane_2_quad_d_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 27120 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_2_quad_d_ctrl1[0]) & 0x7) 27121 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_2_quad_d_ctrl1[0]=(((r).ana_lane_2_quad_d_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 27122 27123 /* 27124 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL1. 27125 */ 27126 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r,_r._ana_lane_2_quad_d_ctrl1) 27127 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r,_r._ana_lane_2_quad_d_ctrl1) 27128 27129 /* 27130 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27131 * will be redefined without the chip prefix for easier programming. 27132 * If multiple chips will be programmed in the same source file, then you should 27133 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27134 * and refer to the fully qualified versions. 27135 */ 27136 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27137 27138 #define ANA_LANE_2_QUAD_D_CTRL1r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r 27139 #define ANA_LANE_2_QUAD_D_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_SIZE 27140 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_t ANA_LANE_2_QUAD_D_CTRL1r_t; 27141 #define ANA_LANE_2_QUAD_D_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_CLR 27142 #define ANA_LANE_2_QUAD_D_CTRL1r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_SET 27143 #define ANA_LANE_2_QUAD_D_CTRL1r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_GET 27144 #define ANA_LANE_2_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 27145 #define ANA_LANE_2_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 27146 #define ANA_LANE_2_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET 27147 #define ANA_LANE_2_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET 27148 #define ANA_LANE_2_QUAD_D_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_PWRDNf_GET 27149 #define ANA_LANE_2_QUAD_D_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_OCL_PWRDNf_SET 27150 #define ANA_LANE_2_QUAD_D_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_REF_OCLf_GET 27151 #define ANA_LANE_2_QUAD_D_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_REF_OCLf_SET 27152 #define ANA_LANE_2_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET 27153 #define ANA_LANE_2_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET 27154 #define READ_ANA_LANE_2_QUAD_D_CTRL1r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL1r 27155 #define WRITE_ANA_LANE_2_QUAD_D_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL1r 27156 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL1r 27157 27158 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27159 /******************************************************************************* 27160 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL1r' 27161 */ 27162 27163 27164 27165 27166 /******************************************************************************* 27167 * CHIP: BCMI_HURACAN 27168 * REGISTER: ANA_LANE_2_QUAD_D_CTRL2 27169 * BLOCKS: ANA_LANE_2_QUAD_D 27170 * REGADDR: 0xb402 27171 * DEVAD: 1 27172 * DESC: control registers 0 27173 * RESETVAL: 0x0 (0) 27174 * ACCESS: R/W 27175 * FIELDS: 27176 * CTLE_ENB_NEGIMP 27177 * CTLE_ENB_NEGCAP 27178 */ 27179 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r (0x0001b402 | PHYMOD_REG_ACC_RAW) 27180 27181 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_SIZE 4 27182 27183 /* 27184 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL2. 27185 */ 27186 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_s { 27187 uint32_t v[1]; 27188 uint32_t ana_lane_2_quad_d_ctrl2[1]; 27189 uint32_t _ana_lane_2_quad_d_ctrl2; 27190 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_t; 27191 27192 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CLR(r) (r).ana_lane_2_quad_d_ctrl2[0] = 0 27193 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_SET(r,d) (r).ana_lane_2_quad_d_ctrl2[0] = d 27194 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_GET(r) (r).ana_lane_2_quad_d_ctrl2[0] 27195 27196 /* 27197 * These macros can be used to access individual fields. 27198 */ 27199 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_2_quad_d_ctrl2[0]) >> 8) & 0x7f) 27200 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_2_quad_d_ctrl2[0]=(((r).ana_lane_2_quad_d_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 27201 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_2_quad_d_ctrl2[0]) & 0x7f) 27202 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_2_quad_d_ctrl2[0]=(((r).ana_lane_2_quad_d_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 27203 27204 /* 27205 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL2. 27206 */ 27207 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r,_r._ana_lane_2_quad_d_ctrl2) 27208 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r,_r._ana_lane_2_quad_d_ctrl2) 27209 27210 /* 27211 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27212 * will be redefined without the chip prefix for easier programming. 27213 * If multiple chips will be programmed in the same source file, then you should 27214 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27215 * and refer to the fully qualified versions. 27216 */ 27217 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27218 27219 #define ANA_LANE_2_QUAD_D_CTRL2r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r 27220 #define ANA_LANE_2_QUAD_D_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_SIZE 27221 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_t ANA_LANE_2_QUAD_D_CTRL2r_t; 27222 #define ANA_LANE_2_QUAD_D_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CLR 27223 #define ANA_LANE_2_QUAD_D_CTRL2r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_SET 27224 #define ANA_LANE_2_QUAD_D_CTRL2r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_GET 27225 #define ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET 27226 #define ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET 27227 #define ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET 27228 #define ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET 27229 #define READ_ANA_LANE_2_QUAD_D_CTRL2r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL2r 27230 #define WRITE_ANA_LANE_2_QUAD_D_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL2r 27231 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL2r 27232 27233 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27234 /******************************************************************************* 27235 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL2r' 27236 */ 27237 27238 27239 27240 27241 /******************************************************************************* 27242 * CHIP: BCMI_HURACAN 27243 * REGISTER: ANA_LANE_2_QUAD_D_CTRL3 27244 * BLOCKS: ANA_LANE_2_QUAD_D 27245 * REGADDR: 0xb403 27246 * DEVAD: 1 27247 * DESC: control registers 0 27248 * RESETVAL: 0x0 (0) 27249 * ACCESS: R/W 27250 * FIELDS: 27251 * CTLE_EN_NEGRES 27252 * CTLE_EQSEL 27253 */ 27254 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r (0x0001b403 | PHYMOD_REG_ACC_RAW) 27255 27256 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_SIZE 4 27257 27258 /* 27259 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL3. 27260 */ 27261 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_s { 27262 uint32_t v[1]; 27263 uint32_t ana_lane_2_quad_d_ctrl3[1]; 27264 uint32_t _ana_lane_2_quad_d_ctrl3; 27265 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_t; 27266 27267 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CLR(r) (r).ana_lane_2_quad_d_ctrl3[0] = 0 27268 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_SET(r,d) (r).ana_lane_2_quad_d_ctrl3[0] = d 27269 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_GET(r) (r).ana_lane_2_quad_d_ctrl3[0] 27270 27271 /* 27272 * These macros can be used to access individual fields. 27273 */ 27274 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_2_quad_d_ctrl3[0]) >> 8) & 0xff) 27275 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_2_quad_d_ctrl3[0]=(((r).ana_lane_2_quad_d_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 27276 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_2_quad_d_ctrl3[0]) & 0x7f) 27277 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_2_quad_d_ctrl3[0]=(((r).ana_lane_2_quad_d_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 27278 27279 /* 27280 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL3. 27281 */ 27282 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r,_r._ana_lane_2_quad_d_ctrl3) 27283 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r,_r._ana_lane_2_quad_d_ctrl3) 27284 27285 /* 27286 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27287 * will be redefined without the chip prefix for easier programming. 27288 * If multiple chips will be programmed in the same source file, then you should 27289 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27290 * and refer to the fully qualified versions. 27291 */ 27292 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27293 27294 #define ANA_LANE_2_QUAD_D_CTRL3r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r 27295 #define ANA_LANE_2_QUAD_D_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_SIZE 27296 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_t ANA_LANE_2_QUAD_D_CTRL3r_t; 27297 #define ANA_LANE_2_QUAD_D_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CLR 27298 #define ANA_LANE_2_QUAD_D_CTRL3r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_SET 27299 #define ANA_LANE_2_QUAD_D_CTRL3r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_GET 27300 #define ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EQSELf_GET 27301 #define ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EQSELf_SET 27302 #define ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET 27303 #define ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET 27304 #define READ_ANA_LANE_2_QUAD_D_CTRL3r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL3r 27305 #define WRITE_ANA_LANE_2_QUAD_D_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL3r 27306 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL3r 27307 27308 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27309 /******************************************************************************* 27310 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL3r' 27311 */ 27312 27313 27314 27315 27316 /******************************************************************************* 27317 * CHIP: BCMI_HURACAN 27318 * REGISTER: ANA_LANE_2_QUAD_D_CTRL4 27319 * BLOCKS: ANA_LANE_2_QUAD_D 27320 * REGADDR: 0xb404 27321 * DEVAD: 1 27322 * DESC: control registers 0 27323 * RESETVAL: 0x0 (0) 27324 * ACCESS: R/W 27325 * FIELDS: 27326 * CTLE_LZEN 27327 * RXTX_RESERVED_FOR_59_52 27328 */ 27329 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r (0x0001b404 | PHYMOD_REG_ACC_RAW) 27330 27331 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_SIZE 4 27332 27333 /* 27334 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL4. 27335 */ 27336 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_s { 27337 uint32_t v[1]; 27338 uint32_t ana_lane_2_quad_d_ctrl4[1]; 27339 uint32_t _ana_lane_2_quad_d_ctrl4; 27340 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_t; 27341 27342 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_CLR(r) (r).ana_lane_2_quad_d_ctrl4[0] = 0 27343 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_SET(r,d) (r).ana_lane_2_quad_d_ctrl4[0] = d 27344 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_GET(r) (r).ana_lane_2_quad_d_ctrl4[0] 27345 27346 /* 27347 * These macros can be used to access individual fields. 27348 */ 27349 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_2_quad_d_ctrl4[0]) >> 4) & 0xff) 27350 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_2_quad_d_ctrl4[0]=(((r).ana_lane_2_quad_d_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 27351 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_2_quad_d_ctrl4[0]) & 0x1) 27352 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_2_quad_d_ctrl4[0]=(((r).ana_lane_2_quad_d_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 27353 27354 /* 27355 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL4. 27356 */ 27357 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r,_r._ana_lane_2_quad_d_ctrl4) 27358 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r,_r._ana_lane_2_quad_d_ctrl4) 27359 27360 /* 27361 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27362 * will be redefined without the chip prefix for easier programming. 27363 * If multiple chips will be programmed in the same source file, then you should 27364 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27365 * and refer to the fully qualified versions. 27366 */ 27367 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27368 27369 #define ANA_LANE_2_QUAD_D_CTRL4r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r 27370 #define ANA_LANE_2_QUAD_D_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_SIZE 27371 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_t ANA_LANE_2_QUAD_D_CTRL4r_t; 27372 #define ANA_LANE_2_QUAD_D_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_CLR 27373 #define ANA_LANE_2_QUAD_D_CTRL4r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_SET 27374 #define ANA_LANE_2_QUAD_D_CTRL4r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_GET 27375 #define ANA_LANE_2_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 27376 #define ANA_LANE_2_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 27377 #define ANA_LANE_2_QUAD_D_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_CTLE_LZENf_GET 27378 #define ANA_LANE_2_QUAD_D_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r_CTLE_LZENf_SET 27379 #define READ_ANA_LANE_2_QUAD_D_CTRL4r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL4r 27380 #define WRITE_ANA_LANE_2_QUAD_D_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL4r 27381 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL4r 27382 27383 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27384 /******************************************************************************* 27385 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL4r' 27386 */ 27387 27388 27389 27390 27391 /******************************************************************************* 27392 * CHIP: BCMI_HURACAN 27393 * REGISTER: ANA_LANE_2_QUAD_D_CTRL5 27394 * BLOCKS: ANA_LANE_2_QUAD_D 27395 * REGADDR: 0xb405 27396 * DEVAD: 1 27397 * DESC: control registers 0 27398 * RESETVAL: 0x0 (0) 27399 * ACCESS: R/W 27400 * FIELDS: 27401 * CTLE_LOPEAKING 27402 * CTLE_PD 27403 * LA_GCTRL 27404 */ 27405 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r (0x0001b405 | PHYMOD_REG_ACC_RAW) 27406 27407 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_SIZE 4 27408 27409 /* 27410 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL5. 27411 */ 27412 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_s { 27413 uint32_t v[1]; 27414 uint32_t ana_lane_2_quad_d_ctrl5[1]; 27415 uint32_t _ana_lane_2_quad_d_ctrl5; 27416 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_t; 27417 27418 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CLR(r) (r).ana_lane_2_quad_d_ctrl5[0] = 0 27419 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_SET(r,d) (r).ana_lane_2_quad_d_ctrl5[0] = d 27420 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_GET(r) (r).ana_lane_2_quad_d_ctrl5[0] 27421 27422 /* 27423 * These macros can be used to access individual fields. 27424 */ 27425 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_2_quad_d_ctrl5[0]) >> 4) & 0x3ff) 27426 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_2_quad_d_ctrl5[0]=(((r).ana_lane_2_quad_d_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 27427 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_2_quad_d_ctrl5[0]) >> 1) & 0x1) 27428 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_2_quad_d_ctrl5[0]=(((r).ana_lane_2_quad_d_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 27429 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_2_quad_d_ctrl5[0]) & 0x1) 27430 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_2_quad_d_ctrl5[0]=(((r).ana_lane_2_quad_d_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 27431 27432 /* 27433 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL5. 27434 */ 27435 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r,_r._ana_lane_2_quad_d_ctrl5) 27436 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r,_r._ana_lane_2_quad_d_ctrl5) 27437 27438 /* 27439 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27440 * will be redefined without the chip prefix for easier programming. 27441 * If multiple chips will be programmed in the same source file, then you should 27442 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27443 * and refer to the fully qualified versions. 27444 */ 27445 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27446 27447 #define ANA_LANE_2_QUAD_D_CTRL5r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r 27448 #define ANA_LANE_2_QUAD_D_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_SIZE 27449 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_t ANA_LANE_2_QUAD_D_CTRL5r_t; 27450 #define ANA_LANE_2_QUAD_D_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CLR 27451 #define ANA_LANE_2_QUAD_D_CTRL5r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_SET 27452 #define ANA_LANE_2_QUAD_D_CTRL5r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_GET 27453 #define ANA_LANE_2_QUAD_D_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_LA_GCTRLf_GET 27454 #define ANA_LANE_2_QUAD_D_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_LA_GCTRLf_SET 27455 #define ANA_LANE_2_QUAD_D_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_PDf_GET 27456 #define ANA_LANE_2_QUAD_D_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_PDf_SET 27457 #define ANA_LANE_2_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET 27458 #define ANA_LANE_2_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET 27459 #define READ_ANA_LANE_2_QUAD_D_CTRL5r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL5r 27460 #define WRITE_ANA_LANE_2_QUAD_D_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL5r 27461 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL5r 27462 27463 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27464 /******************************************************************************* 27465 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL5r' 27466 */ 27467 27468 27469 27470 27471 /******************************************************************************* 27472 * CHIP: BCMI_HURACAN 27473 * REGISTER: ANA_LANE_2_QUAD_D_CTRL6 27474 * BLOCKS: ANA_LANE_2_QUAD_D 27475 * REGADDR: 0xb406 27476 * DEVAD: 1 27477 * DESC: control registers 0 27478 * RESETVAL: 0x0 (0) 27479 * ACCESS: R/W 27480 * FIELDS: 27481 * LA_DEGAIN 27482 * LA_DETUNE 27483 */ 27484 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r (0x0001b406 | PHYMOD_REG_ACC_RAW) 27485 27486 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_SIZE 4 27487 27488 /* 27489 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL6. 27490 */ 27491 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_s { 27492 uint32_t v[1]; 27493 uint32_t ana_lane_2_quad_d_ctrl6[1]; 27494 uint32_t _ana_lane_2_quad_d_ctrl6; 27495 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_t; 27496 27497 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_CLR(r) (r).ana_lane_2_quad_d_ctrl6[0] = 0 27498 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_SET(r,d) (r).ana_lane_2_quad_d_ctrl6[0] = d 27499 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_GET(r) (r).ana_lane_2_quad_d_ctrl6[0] 27500 27501 /* 27502 * These macros can be used to access individual fields. 27503 */ 27504 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_2_quad_d_ctrl6[0]) >> 8) & 0xff) 27505 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_2_quad_d_ctrl6[0]=(((r).ana_lane_2_quad_d_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 27506 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_2_quad_d_ctrl6[0]) & 0x1f) 27507 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_2_quad_d_ctrl6[0]=(((r).ana_lane_2_quad_d_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 27508 27509 /* 27510 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL6. 27511 */ 27512 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r,_r._ana_lane_2_quad_d_ctrl6) 27513 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r,_r._ana_lane_2_quad_d_ctrl6) 27514 27515 /* 27516 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27517 * will be redefined without the chip prefix for easier programming. 27518 * If multiple chips will be programmed in the same source file, then you should 27519 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27520 * and refer to the fully qualified versions. 27521 */ 27522 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27523 27524 #define ANA_LANE_2_QUAD_D_CTRL6r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r 27525 #define ANA_LANE_2_QUAD_D_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_SIZE 27526 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_t ANA_LANE_2_QUAD_D_CTRL6r_t; 27527 #define ANA_LANE_2_QUAD_D_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_CLR 27528 #define ANA_LANE_2_QUAD_D_CTRL6r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_SET 27529 #define ANA_LANE_2_QUAD_D_CTRL6r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_GET 27530 #define ANA_LANE_2_QUAD_D_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DETUNEf_GET 27531 #define ANA_LANE_2_QUAD_D_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DETUNEf_SET 27532 #define ANA_LANE_2_QUAD_D_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DEGAINf_GET 27533 #define ANA_LANE_2_QUAD_D_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r_LA_DEGAINf_SET 27534 #define READ_ANA_LANE_2_QUAD_D_CTRL6r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL6r 27535 #define WRITE_ANA_LANE_2_QUAD_D_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL6r 27536 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL6r 27537 27538 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27539 /******************************************************************************* 27540 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL6r' 27541 */ 27542 27543 27544 27545 27546 /******************************************************************************* 27547 * CHIP: BCMI_HURACAN 27548 * REGISTER: ANA_LANE_2_QUAD_D_CTRL7 27549 * BLOCKS: ANA_LANE_2_QUAD_D 27550 * REGADDR: 0xb407 27551 * DEVAD: 1 27552 * DESC: control registers 0 27553 * RESETVAL: 0x0 (0) 27554 * ACCESS: R/W 27555 * FIELDS: 27556 * LA_LIN_MODE 27557 * RX_BIAS_FB_PDN 27558 */ 27559 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r (0x0001b407 | PHYMOD_REG_ACC_RAW) 27560 27561 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_SIZE 4 27562 27563 /* 27564 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL7. 27565 */ 27566 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_s { 27567 uint32_t v[1]; 27568 uint32_t ana_lane_2_quad_d_ctrl7[1]; 27569 uint32_t _ana_lane_2_quad_d_ctrl7; 27570 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_t; 27571 27572 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_CLR(r) (r).ana_lane_2_quad_d_ctrl7[0] = 0 27573 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_SET(r,d) (r).ana_lane_2_quad_d_ctrl7[0] = d 27574 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_GET(r) (r).ana_lane_2_quad_d_ctrl7[0] 27575 27576 /* 27577 * These macros can be used to access individual fields. 27578 */ 27579 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_2_quad_d_ctrl7[0]) >> 8) & 0x1) 27580 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_2_quad_d_ctrl7[0]=(((r).ana_lane_2_quad_d_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 27581 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_2_quad_d_ctrl7[0]) & 0x1f) 27582 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_2_quad_d_ctrl7[0]=(((r).ana_lane_2_quad_d_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 27583 27584 /* 27585 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL7. 27586 */ 27587 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r,_r._ana_lane_2_quad_d_ctrl7) 27588 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r,_r._ana_lane_2_quad_d_ctrl7) 27589 27590 /* 27591 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27592 * will be redefined without the chip prefix for easier programming. 27593 * If multiple chips will be programmed in the same source file, then you should 27594 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27595 * and refer to the fully qualified versions. 27596 */ 27597 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27598 27599 #define ANA_LANE_2_QUAD_D_CTRL7r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r 27600 #define ANA_LANE_2_QUAD_D_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_SIZE 27601 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_t ANA_LANE_2_QUAD_D_CTRL7r_t; 27602 #define ANA_LANE_2_QUAD_D_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_CLR 27603 #define ANA_LANE_2_QUAD_D_CTRL7r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_SET 27604 #define ANA_LANE_2_QUAD_D_CTRL7r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_GET 27605 #define ANA_LANE_2_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET 27606 #define ANA_LANE_2_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET 27607 #define ANA_LANE_2_QUAD_D_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_LA_LIN_MODEf_GET 27608 #define ANA_LANE_2_QUAD_D_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r_LA_LIN_MODEf_SET 27609 #define READ_ANA_LANE_2_QUAD_D_CTRL7r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL7r 27610 #define WRITE_ANA_LANE_2_QUAD_D_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL7r 27611 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL7r 27612 27613 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27614 /******************************************************************************* 27615 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL7r' 27616 */ 27617 27618 27619 27620 27621 /******************************************************************************* 27622 * CHIP: BCMI_HURACAN 27623 * REGISTER: ANA_LANE_2_QUAD_D_CTRL8 27624 * BLOCKS: ANA_LANE_2_QUAD_D 27625 * REGADDR: 0xb408 27626 * DEVAD: 1 27627 * DESC: control registers 0 27628 * RESETVAL: 0x0 (0) 27629 * ACCESS: R/W 27630 * FIELDS: 27631 * LA_PD 27632 * LA_PD_IDLE 27633 * RXTX_RESERVED_FOR_99_95 27634 */ 27635 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r (0x0001b408 | PHYMOD_REG_ACC_RAW) 27636 27637 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_SIZE 4 27638 27639 /* 27640 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL8. 27641 */ 27642 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_s { 27643 uint32_t v[1]; 27644 uint32_t ana_lane_2_quad_d_ctrl8[1]; 27645 uint32_t _ana_lane_2_quad_d_ctrl8; 27646 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_t; 27647 27648 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_CLR(r) (r).ana_lane_2_quad_d_ctrl8[0] = 0 27649 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_SET(r,d) (r).ana_lane_2_quad_d_ctrl8[0] = d 27650 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_GET(r) (r).ana_lane_2_quad_d_ctrl8[0] 27651 27652 /* 27653 * These macros can be used to access individual fields. 27654 */ 27655 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_2_quad_d_ctrl8[0]) >> 4) & 0x1f) 27656 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_2_quad_d_ctrl8[0]=(((r).ana_lane_2_quad_d_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 27657 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_2_quad_d_ctrl8[0]) >> 1) & 0x1) 27658 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_2_quad_d_ctrl8[0]=(((r).ana_lane_2_quad_d_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 27659 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_2_quad_d_ctrl8[0]) & 0x1) 27660 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_2_quad_d_ctrl8[0]=(((r).ana_lane_2_quad_d_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 27661 27662 /* 27663 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL8. 27664 */ 27665 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r,_r._ana_lane_2_quad_d_ctrl8) 27666 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r,_r._ana_lane_2_quad_d_ctrl8) 27667 27668 /* 27669 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27670 * will be redefined without the chip prefix for easier programming. 27671 * If multiple chips will be programmed in the same source file, then you should 27672 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27673 * and refer to the fully qualified versions. 27674 */ 27675 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27676 27677 #define ANA_LANE_2_QUAD_D_CTRL8r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r 27678 #define ANA_LANE_2_QUAD_D_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_SIZE 27679 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_t ANA_LANE_2_QUAD_D_CTRL8r_t; 27680 #define ANA_LANE_2_QUAD_D_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_CLR 27681 #define ANA_LANE_2_QUAD_D_CTRL8r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_SET 27682 #define ANA_LANE_2_QUAD_D_CTRL8r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_GET 27683 #define ANA_LANE_2_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 27684 #define ANA_LANE_2_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 27685 #define ANA_LANE_2_QUAD_D_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PD_IDLEf_GET 27686 #define ANA_LANE_2_QUAD_D_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PD_IDLEf_SET 27687 #define ANA_LANE_2_QUAD_D_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PDf_GET 27688 #define ANA_LANE_2_QUAD_D_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r_LA_PDf_SET 27689 #define READ_ANA_LANE_2_QUAD_D_CTRL8r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL8r 27690 #define WRITE_ANA_LANE_2_QUAD_D_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL8r 27691 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL8r 27692 27693 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27694 /******************************************************************************* 27695 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL8r' 27696 */ 27697 27698 27699 27700 27701 /******************************************************************************* 27702 * CHIP: BCMI_HURACAN 27703 * REGISTER: ANA_LANE_2_QUAD_D_CTRL9 27704 * BLOCKS: ANA_LANE_2_QUAD_D 27705 * REGADDR: 0xb409 27706 * DEVAD: 1 27707 * DESC: control registers 0 27708 * RESETVAL: 0x0 (0) 27709 * ACCESS: R/W 27710 * FIELDS: 27711 * DRV_POST1 27712 * DLINE_SWING_1 27713 * DLINE_SWING_2 27714 * DLINE_DELAY_CTRL 27715 */ 27716 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r (0x0001b409 | PHYMOD_REG_ACC_RAW) 27717 27718 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_SIZE 4 27719 27720 /* 27721 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL9. 27722 */ 27723 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_s { 27724 uint32_t v[1]; 27725 uint32_t ana_lane_2_quad_d_ctrl9[1]; 27726 uint32_t _ana_lane_2_quad_d_ctrl9; 27727 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_t; 27728 27729 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_CLR(r) (r).ana_lane_2_quad_d_ctrl9[0] = 0 27730 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_SET(r,d) (r).ana_lane_2_quad_d_ctrl9[0] = d 27731 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_GET(r) (r).ana_lane_2_quad_d_ctrl9[0] 27732 27733 /* 27734 * These macros can be used to access individual fields. 27735 */ 27736 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_2_quad_d_ctrl9[0]) >> 12) & 0x7) 27737 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_2_quad_d_ctrl9[0]=(((r).ana_lane_2_quad_d_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 27738 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_2_quad_d_ctrl9[0]) >> 8) & 0x3) 27739 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_2_quad_d_ctrl9[0]=(((r).ana_lane_2_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 27740 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_2_quad_d_ctrl9[0]) >> 4) & 0x3) 27741 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_2_quad_d_ctrl9[0]=(((r).ana_lane_2_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 27742 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_2_quad_d_ctrl9[0]) & 0xf) 27743 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_2_quad_d_ctrl9[0]=(((r).ana_lane_2_quad_d_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 27744 27745 /* 27746 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL9. 27747 */ 27748 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r,_r._ana_lane_2_quad_d_ctrl9) 27749 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r,_r._ana_lane_2_quad_d_ctrl9) 27750 27751 /* 27752 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27753 * will be redefined without the chip prefix for easier programming. 27754 * If multiple chips will be programmed in the same source file, then you should 27755 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27756 * and refer to the fully qualified versions. 27757 */ 27758 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27759 27760 #define ANA_LANE_2_QUAD_D_CTRL9r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r 27761 #define ANA_LANE_2_QUAD_D_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_SIZE 27762 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_t ANA_LANE_2_QUAD_D_CTRL9r_t; 27763 #define ANA_LANE_2_QUAD_D_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_CLR 27764 #define ANA_LANE_2_QUAD_D_CTRL9r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_SET 27765 #define ANA_LANE_2_QUAD_D_CTRL9r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_GET 27766 #define ANA_LANE_2_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET 27767 #define ANA_LANE_2_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET 27768 #define ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_2f_GET 27769 #define ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_2f_SET 27770 #define ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_1f_GET 27771 #define ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DLINE_SWING_1f_SET 27772 #define ANA_LANE_2_QUAD_D_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DRV_POST1f_GET 27773 #define ANA_LANE_2_QUAD_D_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r_DRV_POST1f_SET 27774 #define READ_ANA_LANE_2_QUAD_D_CTRL9r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL9r 27775 #define WRITE_ANA_LANE_2_QUAD_D_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL9r 27776 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL9r 27777 27778 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27779 /******************************************************************************* 27780 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL9r' 27781 */ 27782 27783 27784 27785 27786 /******************************************************************************* 27787 * CHIP: BCMI_HURACAN 27788 * REGISTER: ANA_LANE_2_QUAD_D_CTRL10 27789 * BLOCKS: ANA_LANE_2_QUAD_D 27790 * REGADDR: 0xb40a 27791 * DEVAD: 1 27792 * DESC: control registers 0 27793 * RESETVAL: 0x0 (0) 27794 * ACCESS: R/W 27795 * FIELDS: 27796 * DRV_PWD 27797 * DLINE_PWD 27798 * DRV_VBSEL 27799 * DRV_MAIN 27800 * DRV_MAIN_PU 27801 */ 27802 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r (0x0001b40a | PHYMOD_REG_ACC_RAW) 27803 27804 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_SIZE 4 27805 27806 /* 27807 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL10. 27808 */ 27809 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_s { 27810 uint32_t v[1]; 27811 uint32_t ana_lane_2_quad_d_ctrl10[1]; 27812 uint32_t _ana_lane_2_quad_d_ctrl10; 27813 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_t; 27814 27815 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_CLR(r) (r).ana_lane_2_quad_d_ctrl10[0] = 0 27816 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_SET(r,d) (r).ana_lane_2_quad_d_ctrl10[0] = d 27817 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_GET(r) (r).ana_lane_2_quad_d_ctrl10[0] 27818 27819 /* 27820 * These macros can be used to access individual fields. 27821 */ 27822 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_2_quad_d_ctrl10[0]) >> 12) & 0xf) 27823 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_2_quad_d_ctrl10[0]=(((r).ana_lane_2_quad_d_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 27824 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_2_quad_d_ctrl10[0]) >> 4) & 0x3f) 27825 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_2_quad_d_ctrl10[0]=(((r).ana_lane_2_quad_d_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 27826 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_2_quad_d_ctrl10[0]) >> 2) & 0x1) 27827 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_2_quad_d_ctrl10[0]=(((r).ana_lane_2_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 27828 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_2_quad_d_ctrl10[0]) >> 1) & 0x1) 27829 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_2_quad_d_ctrl10[0]=(((r).ana_lane_2_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 27830 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_2_quad_d_ctrl10[0]) & 0x1) 27831 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_2_quad_d_ctrl10[0]=(((r).ana_lane_2_quad_d_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 27832 27833 /* 27834 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL10. 27835 */ 27836 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r,_r._ana_lane_2_quad_d_ctrl10) 27837 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r,_r._ana_lane_2_quad_d_ctrl10) 27838 27839 /* 27840 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27841 * will be redefined without the chip prefix for easier programming. 27842 * If multiple chips will be programmed in the same source file, then you should 27843 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27844 * and refer to the fully qualified versions. 27845 */ 27846 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27847 27848 #define ANA_LANE_2_QUAD_D_CTRL10r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r 27849 #define ANA_LANE_2_QUAD_D_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_SIZE 27850 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_t ANA_LANE_2_QUAD_D_CTRL10r_t; 27851 #define ANA_LANE_2_QUAD_D_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_CLR 27852 #define ANA_LANE_2_QUAD_D_CTRL10r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_SET 27853 #define ANA_LANE_2_QUAD_D_CTRL10r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_GET 27854 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET 27855 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET 27856 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAINf_GET 27857 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_MAINf_SET 27858 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_VBSELf_GET 27859 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_VBSELf_SET 27860 #define ANA_LANE_2_QUAD_D_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DLINE_PWDf_GET 27861 #define ANA_LANE_2_QUAD_D_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DLINE_PWDf_SET 27862 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_PWDf_GET 27863 #define ANA_LANE_2_QUAD_D_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r_DRV_PWDf_SET 27864 #define READ_ANA_LANE_2_QUAD_D_CTRL10r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL10r 27865 #define WRITE_ANA_LANE_2_QUAD_D_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL10r 27866 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL10r 27867 27868 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27869 /******************************************************************************* 27870 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL10r' 27871 */ 27872 27873 27874 27875 27876 /******************************************************************************* 27877 * CHIP: BCMI_HURACAN 27878 * REGISTER: ANA_LANE_2_QUAD_D_CTRL11 27879 * BLOCKS: ANA_LANE_2_QUAD_D 27880 * REGADDR: 0xb40b 27881 * DEVAD: 1 27882 * DESC: control registers 0 27883 * RESETVAL: 0x0 (0) 27884 * ACCESS: R/W 27885 * FIELDS: 27886 * RXTX_RESERVED_FOR_143_128 27887 */ 27888 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r (0x0001b40b | PHYMOD_REG_ACC_RAW) 27889 27890 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_SIZE 4 27891 27892 /* 27893 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL11. 27894 */ 27895 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_s { 27896 uint32_t v[1]; 27897 uint32_t ana_lane_2_quad_d_ctrl11[1]; 27898 uint32_t _ana_lane_2_quad_d_ctrl11; 27899 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_t; 27900 27901 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_CLR(r) (r).ana_lane_2_quad_d_ctrl11[0] = 0 27902 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_SET(r,d) (r).ana_lane_2_quad_d_ctrl11[0] = d 27903 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_GET(r) (r).ana_lane_2_quad_d_ctrl11[0] 27904 27905 /* 27906 * These macros can be used to access individual fields. 27907 */ 27908 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_2_quad_d_ctrl11[0]) & 0xffff) 27909 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_2_quad_d_ctrl11[0]=(((r).ana_lane_2_quad_d_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 27910 27911 /* 27912 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL11. 27913 */ 27914 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r,_r._ana_lane_2_quad_d_ctrl11) 27915 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r,_r._ana_lane_2_quad_d_ctrl11) 27916 27917 /* 27918 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27919 * will be redefined without the chip prefix for easier programming. 27920 * If multiple chips will be programmed in the same source file, then you should 27921 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 27922 * and refer to the fully qualified versions. 27923 */ 27924 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 27925 27926 #define ANA_LANE_2_QUAD_D_CTRL11r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r 27927 #define ANA_LANE_2_QUAD_D_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_SIZE 27928 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_t ANA_LANE_2_QUAD_D_CTRL11r_t; 27929 #define ANA_LANE_2_QUAD_D_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_CLR 27930 #define ANA_LANE_2_QUAD_D_CTRL11r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_SET 27931 #define ANA_LANE_2_QUAD_D_CTRL11r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_GET 27932 #define ANA_LANE_2_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 27933 #define ANA_LANE_2_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 27934 #define READ_ANA_LANE_2_QUAD_D_CTRL11r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL11r 27935 #define WRITE_ANA_LANE_2_QUAD_D_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL11r 27936 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL11r 27937 27938 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 27939 /******************************************************************************* 27940 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL11r' 27941 */ 27942 27943 27944 27945 27946 /******************************************************************************* 27947 * CHIP: BCMI_HURACAN 27948 * REGISTER: ANA_LANE_2_QUAD_D_CTRL12 27949 * BLOCKS: ANA_LANE_2_QUAD_D 27950 * REGADDR: 0xb40c 27951 * DEVAD: 1 27952 * DESC: control registers 0 27953 * RESETVAL: 0x0 (0) 27954 * ACCESS: R/W 27955 * FIELDS: 27956 * LA_RESCAL_FRC_VAL 27957 * LA_RESCAL_FRC 27958 * DRV_RESCAL_FRC_VAL 27959 * DRV_RESCAL_FRC 27960 */ 27961 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r (0x0001b40c | PHYMOD_REG_ACC_RAW) 27962 27963 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_SIZE 4 27964 27965 /* 27966 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL12. 27967 */ 27968 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_s { 27969 uint32_t v[1]; 27970 uint32_t ana_lane_2_quad_d_ctrl12[1]; 27971 uint32_t _ana_lane_2_quad_d_ctrl12; 27972 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_t; 27973 27974 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_CLR(r) (r).ana_lane_2_quad_d_ctrl12[0] = 0 27975 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_SET(r,d) (r).ana_lane_2_quad_d_ctrl12[0] = d 27976 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_GET(r) (r).ana_lane_2_quad_d_ctrl12[0] 27977 27978 /* 27979 * These macros can be used to access individual fields. 27980 */ 27981 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_d_ctrl12[0]) >> 12) & 0x1) 27982 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_d_ctrl12[0]=(((r).ana_lane_2_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 27983 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_d_ctrl12[0]) >> 8) & 0xf) 27984 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_d_ctrl12[0]=(((r).ana_lane_2_quad_d_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 27985 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_d_ctrl12[0]) >> 4) & 0x1) 27986 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_d_ctrl12[0]=(((r).ana_lane_2_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 27987 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_d_ctrl12[0]) & 0xf) 27988 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_d_ctrl12[0]=(((r).ana_lane_2_quad_d_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 27989 27990 /* 27991 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL12. 27992 */ 27993 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r,_r._ana_lane_2_quad_d_ctrl12) 27994 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r,_r._ana_lane_2_quad_d_ctrl12) 27995 27996 /* 27997 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 27998 * will be redefined without the chip prefix for easier programming. 27999 * If multiple chips will be programmed in the same source file, then you should 28000 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28001 * and refer to the fully qualified versions. 28002 */ 28003 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28004 28005 #define ANA_LANE_2_QUAD_D_CTRL12r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r 28006 #define ANA_LANE_2_QUAD_D_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_SIZE 28007 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_t ANA_LANE_2_QUAD_D_CTRL12r_t; 28008 #define ANA_LANE_2_QUAD_D_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_CLR 28009 #define ANA_LANE_2_QUAD_D_CTRL12r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_SET 28010 #define ANA_LANE_2_QUAD_D_CTRL12r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_GET 28011 #define ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET 28012 #define ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET 28013 #define ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET 28014 #define ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET 28015 #define ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET 28016 #define ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET 28017 #define ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET 28018 #define ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET 28019 #define READ_ANA_LANE_2_QUAD_D_CTRL12r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL12r 28020 #define WRITE_ANA_LANE_2_QUAD_D_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL12r 28021 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL12r 28022 28023 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28024 /******************************************************************************* 28025 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL12r' 28026 */ 28027 28028 28029 28030 28031 /******************************************************************************* 28032 * CHIP: BCMI_HURACAN 28033 * REGISTER: ANA_LANE_2_QUAD_D_CTRL13 28034 * BLOCKS: ANA_LANE_2_QUAD_D 28035 * REGADDR: 0xb40d 28036 * DEVAD: 1 28037 * DESC: control registers 0 28038 * RESETVAL: 0x0 (0) 28039 * ACCESS: R/W 28040 * FIELDS: 28041 * CTLE_RESCAL_FRC_VAL 28042 * CTLE_RESCAL_FRC 28043 */ 28044 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r (0x0001b40d | PHYMOD_REG_ACC_RAW) 28045 28046 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_SIZE 4 28047 28048 /* 28049 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL13. 28050 */ 28051 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_s { 28052 uint32_t v[1]; 28053 uint32_t ana_lane_2_quad_d_ctrl13[1]; 28054 uint32_t _ana_lane_2_quad_d_ctrl13; 28055 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_t; 28056 28057 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CLR(r) (r).ana_lane_2_quad_d_ctrl13[0] = 0 28058 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_SET(r,d) (r).ana_lane_2_quad_d_ctrl13[0] = d 28059 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_GET(r) (r).ana_lane_2_quad_d_ctrl13[0] 28060 28061 /* 28062 * These macros can be used to access individual fields. 28063 */ 28064 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_2_quad_d_ctrl13[0]) >> 4) & 0x1) 28065 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_2_quad_d_ctrl13[0]=(((r).ana_lane_2_quad_d_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 28066 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_2_quad_d_ctrl13[0]) & 0xf) 28067 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_d_ctrl13[0]=(((r).ana_lane_2_quad_d_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 28068 28069 /* 28070 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL13. 28071 */ 28072 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r,_r._ana_lane_2_quad_d_ctrl13) 28073 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r,_r._ana_lane_2_quad_d_ctrl13) 28074 28075 /* 28076 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28077 * will be redefined without the chip prefix for easier programming. 28078 * If multiple chips will be programmed in the same source file, then you should 28079 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28080 * and refer to the fully qualified versions. 28081 */ 28082 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28083 28084 #define ANA_LANE_2_QUAD_D_CTRL13r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r 28085 #define ANA_LANE_2_QUAD_D_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_SIZE 28086 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_t ANA_LANE_2_QUAD_D_CTRL13r_t; 28087 #define ANA_LANE_2_QUAD_D_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CLR 28088 #define ANA_LANE_2_QUAD_D_CTRL13r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_SET 28089 #define ANA_LANE_2_QUAD_D_CTRL13r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_GET 28090 #define ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET 28091 #define ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET 28092 #define ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 28093 #define ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 28094 #define READ_ANA_LANE_2_QUAD_D_CTRL13r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL13r 28095 #define WRITE_ANA_LANE_2_QUAD_D_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL13r 28096 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL13r 28097 28098 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28099 /******************************************************************************* 28100 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL13r' 28101 */ 28102 28103 28104 28105 28106 /******************************************************************************* 28107 * CHIP: BCMI_HURACAN 28108 * REGISTER: ANA_LANE_2_QUAD_D_CTRL14 28109 * BLOCKS: ANA_LANE_2_QUAD_D 28110 * REGADDR: 0xb40e 28111 * DEVAD: 1 28112 * DESC: control registers 0 28113 * RESETVAL: 0x0 (0) 28114 * ACCESS: R/W 28115 * FIELDS: 28116 * TX_IDLE_FRC_VAL 28117 * TX_IDLE_FRC 28118 * RXSD_IDLE_OVRD 28119 */ 28120 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r (0x0001b40e | PHYMOD_REG_ACC_RAW) 28121 28122 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_SIZE 4 28123 28124 /* 28125 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL14. 28126 */ 28127 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_s { 28128 uint32_t v[1]; 28129 uint32_t ana_lane_2_quad_d_ctrl14[1]; 28130 uint32_t _ana_lane_2_quad_d_ctrl14; 28131 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_t; 28132 28133 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_CLR(r) (r).ana_lane_2_quad_d_ctrl14[0] = 0 28134 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_SET(r,d) (r).ana_lane_2_quad_d_ctrl14[0] = d 28135 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_GET(r) (r).ana_lane_2_quad_d_ctrl14[0] 28136 28137 /* 28138 * These macros can be used to access individual fields. 28139 */ 28140 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_2_quad_d_ctrl14[0]) >> 4) & 0x1) 28141 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_2_quad_d_ctrl14[0]=(((r).ana_lane_2_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 28142 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_2_quad_d_ctrl14[0]) >> 1) & 0x1) 28143 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_2_quad_d_ctrl14[0]=(((r).ana_lane_2_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 28144 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_2_quad_d_ctrl14[0]) & 0x1) 28145 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_d_ctrl14[0]=(((r).ana_lane_2_quad_d_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 28146 28147 /* 28148 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL14. 28149 */ 28150 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r,_r._ana_lane_2_quad_d_ctrl14) 28151 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r,_r._ana_lane_2_quad_d_ctrl14) 28152 28153 /* 28154 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28155 * will be redefined without the chip prefix for easier programming. 28156 * If multiple chips will be programmed in the same source file, then you should 28157 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28158 * and refer to the fully qualified versions. 28159 */ 28160 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28161 28162 #define ANA_LANE_2_QUAD_D_CTRL14r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r 28163 #define ANA_LANE_2_QUAD_D_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_SIZE 28164 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_t ANA_LANE_2_QUAD_D_CTRL14r_t; 28165 #define ANA_LANE_2_QUAD_D_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_CLR 28166 #define ANA_LANE_2_QUAD_D_CTRL14r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_SET 28167 #define ANA_LANE_2_QUAD_D_CTRL14r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_GET 28168 #define ANA_LANE_2_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET 28169 #define ANA_LANE_2_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET 28170 #define ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET 28171 #define ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET 28172 #define ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET 28173 #define ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET 28174 #define READ_ANA_LANE_2_QUAD_D_CTRL14r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL14r 28175 #define WRITE_ANA_LANE_2_QUAD_D_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL14r 28176 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL14r 28177 28178 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28179 /******************************************************************************* 28180 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL14r' 28181 */ 28182 28183 28184 28185 28186 /******************************************************************************* 28187 * CHIP: BCMI_HURACAN 28188 * REGISTER: ANA_LANE_2_QUAD_D_CTRL15 28189 * BLOCKS: ANA_LANE_2_QUAD_D 28190 * REGADDR: 0xb40f 28191 * DEVAD: 1 28192 * DESC: sigdet filter settings 0 28193 * RESETVAL: 0x0 (0) 28194 * ACCESS: R/W 28195 * FIELDS: 28196 * SIGDET_DIS 28197 * SIGDET_1US_EN 28198 * SIGDET_FRC_VAL 28199 * SIGDET_FRC 28200 * HOLD_LOS_COUNT 28201 * HOLD_SD_COUNT 28202 */ 28203 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r (0x0001b40f | PHYMOD_REG_ACC_RAW) 28204 28205 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIZE 4 28206 28207 /* 28208 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL15. 28209 */ 28210 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_s { 28211 uint32_t v[1]; 28212 uint32_t ana_lane_2_quad_d_ctrl15[1]; 28213 uint32_t _ana_lane_2_quad_d_ctrl15; 28214 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_t; 28215 28216 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_CLR(r) (r).ana_lane_2_quad_d_ctrl15[0] = 0 28217 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SET(r,d) (r).ana_lane_2_quad_d_ctrl15[0] = d 28218 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_GET(r) (r).ana_lane_2_quad_d_ctrl15[0] 28219 28220 /* 28221 * These macros can be used to access individual fields. 28222 */ 28223 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_d_ctrl15[0]) >> 8) & 0x7) 28224 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_d_ctrl15[0]=(((r).ana_lane_2_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 28225 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_2_quad_d_ctrl15[0]) >> 4) & 0x7) 28226 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_d_ctrl15[0]=(((r).ana_lane_2_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 28227 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_2_quad_d_ctrl15[0]) >> 3) & 0x1) 28228 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_2_quad_d_ctrl15[0]=(((r).ana_lane_2_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 28229 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_2_quad_d_ctrl15[0]) >> 2) & 0x1) 28230 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_2_quad_d_ctrl15[0]=(((r).ana_lane_2_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 28231 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_2_quad_d_ctrl15[0]) >> 1) & 0x1) 28232 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_2_quad_d_ctrl15[0]=(((r).ana_lane_2_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 28233 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_2_quad_d_ctrl15[0]) & 0x1) 28234 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_2_quad_d_ctrl15[0]=(((r).ana_lane_2_quad_d_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 28235 28236 /* 28237 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL15. 28238 */ 28239 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r,_r._ana_lane_2_quad_d_ctrl15) 28240 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r,_r._ana_lane_2_quad_d_ctrl15) 28241 28242 /* 28243 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28244 * will be redefined without the chip prefix for easier programming. 28245 * If multiple chips will be programmed in the same source file, then you should 28246 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28247 * and refer to the fully qualified versions. 28248 */ 28249 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28250 28251 #define ANA_LANE_2_QUAD_D_CTRL15r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r 28252 #define ANA_LANE_2_QUAD_D_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIZE 28253 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_t ANA_LANE_2_QUAD_D_CTRL15r_t; 28254 #define ANA_LANE_2_QUAD_D_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_CLR 28255 #define ANA_LANE_2_QUAD_D_CTRL15r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SET 28256 #define ANA_LANE_2_QUAD_D_CTRL15r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_GET 28257 #define ANA_LANE_2_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET 28258 #define ANA_LANE_2_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET 28259 #define ANA_LANE_2_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET 28260 #define ANA_LANE_2_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET 28261 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRCf_GET 28262 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRCf_SET 28263 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET 28264 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET 28265 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET 28266 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET 28267 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_DISf_GET 28268 #define ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r_SIGDET_DISf_SET 28269 #define READ_ANA_LANE_2_QUAD_D_CTRL15r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL15r 28270 #define WRITE_ANA_LANE_2_QUAD_D_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL15r 28271 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL15r 28272 28273 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28274 /******************************************************************************* 28275 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL15r' 28276 */ 28277 28278 28279 28280 28281 /******************************************************************************* 28282 * CHIP: BCMI_HURACAN 28283 * REGISTER: ANA_LANE_2_QUAD_D_CTRL16 28284 * BLOCKS: ANA_LANE_2_QUAD_D 28285 * REGADDR: 0xb410 28286 * DEVAD: 1 28287 * DESC: sigdet filter settings 1 28288 * RESETVAL: 0x0 (0) 28289 * ACCESS: R/W 28290 * FIELDS: 28291 * LOS_COUNT 28292 * SD_COUNT 28293 */ 28294 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r (0x0001b410 | PHYMOD_REG_ACC_RAW) 28295 28296 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SIZE 4 28297 28298 /* 28299 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_CTRL16. 28300 */ 28301 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_s { 28302 uint32_t v[1]; 28303 uint32_t ana_lane_2_quad_d_ctrl16[1]; 28304 uint32_t _ana_lane_2_quad_d_ctrl16; 28305 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_t; 28306 28307 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_CLR(r) (r).ana_lane_2_quad_d_ctrl16[0] = 0 28308 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SET(r,d) (r).ana_lane_2_quad_d_ctrl16[0] = d 28309 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_GET(r) (r).ana_lane_2_quad_d_ctrl16[0] 28310 28311 /* 28312 * These macros can be used to access individual fields. 28313 */ 28314 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_2_quad_d_ctrl16[0]) >> 8) & 0x1f) 28315 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_2_quad_d_ctrl16[0]=(((r).ana_lane_2_quad_d_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 28316 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_2_quad_d_ctrl16[0]) & 0x1f) 28317 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_2_quad_d_ctrl16[0]=(((r).ana_lane_2_quad_d_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 28318 28319 /* 28320 * These macros can be used to access ANA_LANE_2_QUAD_D_CTRL16. 28321 */ 28322 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r,_r._ana_lane_2_quad_d_ctrl16) 28323 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r,_r._ana_lane_2_quad_d_ctrl16) 28324 28325 /* 28326 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28327 * will be redefined without the chip prefix for easier programming. 28328 * If multiple chips will be programmed in the same source file, then you should 28329 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28330 * and refer to the fully qualified versions. 28331 */ 28332 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28333 28334 #define ANA_LANE_2_QUAD_D_CTRL16r BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r 28335 #define ANA_LANE_2_QUAD_D_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SIZE 28336 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_t ANA_LANE_2_QUAD_D_CTRL16r_t; 28337 #define ANA_LANE_2_QUAD_D_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_CLR 28338 #define ANA_LANE_2_QUAD_D_CTRL16r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SET 28339 #define ANA_LANE_2_QUAD_D_CTRL16r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_GET 28340 #define ANA_LANE_2_QUAD_D_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SD_COUNTf_GET 28341 #define ANA_LANE_2_QUAD_D_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_SD_COUNTf_SET 28342 #define ANA_LANE_2_QUAD_D_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_LOS_COUNTf_GET 28343 #define ANA_LANE_2_QUAD_D_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r_LOS_COUNTf_SET 28344 #define READ_ANA_LANE_2_QUAD_D_CTRL16r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_CTRL16r 28345 #define WRITE_ANA_LANE_2_QUAD_D_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_CTRL16r 28346 #define MODIFY_ANA_LANE_2_QUAD_D_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_CTRL16r 28347 28348 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28349 /******************************************************************************* 28350 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_CTRL16r' 28351 */ 28352 28353 28354 28355 28356 /******************************************************************************* 28357 * CHIP: BCMI_HURACAN 28358 * REGISTER: ANA_LANE_2_QUAD_D_STATUS0 28359 * BLOCKS: ANA_LANE_2_QUAD_D 28360 * REGADDR: 0xb420 28361 * DEVAD: 1 28362 * DESC: status registers 0 28363 * RESETVAL: 0x0 (0) 28364 * ACCESS: R/W 28365 * FIELDS: 28366 * O_RX_SIGDET 28367 * DG_RX_SIGDET 28368 */ 28369 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r (0x0001b420 | PHYMOD_REG_ACC_RAW) 28370 28371 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_SIZE 4 28372 28373 /* 28374 * This structure should be used to declare and program ANA_LANE_2_QUAD_D_STATUS0. 28375 */ 28376 typedef union BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_s { 28377 uint32_t v[1]; 28378 uint32_t ana_lane_2_quad_d_status0[1]; 28379 uint32_t _ana_lane_2_quad_d_status0; 28380 } BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_t; 28381 28382 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_CLR(r) (r).ana_lane_2_quad_d_status0[0] = 0 28383 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_SET(r,d) (r).ana_lane_2_quad_d_status0[0] = d 28384 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_GET(r) (r).ana_lane_2_quad_d_status0[0] 28385 28386 /* 28387 * These macros can be used to access individual fields. 28388 */ 28389 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_2_quad_d_status0[0]) >> 1) & 0x1) 28390 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_d_status0[0]=(((r).ana_lane_2_quad_d_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 28391 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_2_quad_d_status0[0]) & 0x1) 28392 #define BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_2_quad_d_status0[0]=(((r).ana_lane_2_quad_d_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 28393 28394 /* 28395 * These macros can be used to access ANA_LANE_2_QUAD_D_STATUS0. 28396 */ 28397 #define BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r,_r._ana_lane_2_quad_d_status0) 28398 #define BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r,_r._ana_lane_2_quad_d_status0) 28399 28400 /* 28401 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28402 * will be redefined without the chip prefix for easier programming. 28403 * If multiple chips will be programmed in the same source file, then you should 28404 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28405 * and refer to the fully qualified versions. 28406 */ 28407 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28408 28409 #define ANA_LANE_2_QUAD_D_STATUS0r BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r 28410 #define ANA_LANE_2_QUAD_D_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_SIZE 28411 typedef BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_t ANA_LANE_2_QUAD_D_STATUS0r_t; 28412 #define ANA_LANE_2_QUAD_D_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_CLR 28413 #define ANA_LANE_2_QUAD_D_STATUS0r_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_SET 28414 #define ANA_LANE_2_QUAD_D_STATUS0r_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_GET 28415 #define ANA_LANE_2_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET 28416 #define ANA_LANE_2_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET 28417 #define ANA_LANE_2_QUAD_D_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_O_RX_SIGDETf_GET 28418 #define ANA_LANE_2_QUAD_D_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r_O_RX_SIGDETf_SET 28419 #define READ_ANA_LANE_2_QUAD_D_STATUS0r BCMI_HURACAN_READ_ANA_LANE_2_QUAD_D_STATUS0r 28420 #define WRITE_ANA_LANE_2_QUAD_D_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_2_QUAD_D_STATUS0r 28421 #define MODIFY_ANA_LANE_2_QUAD_D_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_2_QUAD_D_STATUS0r 28422 28423 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28424 /******************************************************************************* 28425 * End of 'BCMI_HURACAN_ANA_LANE_2_QUAD_D_STATUS0r' 28426 */ 28427 28428 28429 28430 28431 /******************************************************************************* 28432 * CHIP: BCMI_HURACAN 28433 * REGISTER: ANA_LANE_3_QUAD_D_CTRL0 28434 * BLOCKS: ANA_LANE_3_QUAD_D 28435 * REGADDR: 0xb800 28436 * DEVAD: 1 28437 * DESC: control registers 0 28438 * RESETVAL: 0x0 (0) 28439 * ACCESS: R/W 28440 * FIELDS: 28441 * RXTX_PWRDN 28442 * RX_SIGDET_BYPASS 28443 * RX_SIGDET_PWRDN 28444 * RX_SIGDECT_12GMODE 28445 * DC_COUPLE 28446 */ 28447 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r (0x0001b800 | PHYMOD_REG_ACC_RAW) 28448 28449 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_SIZE 4 28450 28451 /* 28452 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL0. 28453 */ 28454 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_s { 28455 uint32_t v[1]; 28456 uint32_t ana_lane_3_quad_d_ctrl0[1]; 28457 uint32_t _ana_lane_3_quad_d_ctrl0; 28458 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_t; 28459 28460 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_CLR(r) (r).ana_lane_3_quad_d_ctrl0[0] = 0 28461 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_SET(r,d) (r).ana_lane_3_quad_d_ctrl0[0] = d 28462 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_GET(r) (r).ana_lane_3_quad_d_ctrl0[0] 28463 28464 /* 28465 * These macros can be used to access individual fields. 28466 */ 28467 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_DC_COUPLEf_GET(r) ((((r).ana_lane_3_quad_d_ctrl0[0]) >> 4) & 0x1) 28468 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_DC_COUPLEf_SET(r,f) (r).ana_lane_3_quad_d_ctrl0[0]=(((r).ana_lane_3_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 28469 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET(r) ((((r).ana_lane_3_quad_d_ctrl0[0]) >> 3) & 0x1) 28470 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET(r,f) (r).ana_lane_3_quad_d_ctrl0[0]=(((r).ana_lane_3_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 28471 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET(r) ((((r).ana_lane_3_quad_d_ctrl0[0]) >> 2) & 0x1) 28472 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET(r,f) (r).ana_lane_3_quad_d_ctrl0[0]=(((r).ana_lane_3_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 28473 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET(r) ((((r).ana_lane_3_quad_d_ctrl0[0]) >> 1) & 0x1) 28474 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET(r,f) (r).ana_lane_3_quad_d_ctrl0[0]=(((r).ana_lane_3_quad_d_ctrl0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 28475 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RXTX_PWRDNf_GET(r) (((r).ana_lane_3_quad_d_ctrl0[0]) & 0x1) 28476 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RXTX_PWRDNf_SET(r,f) (r).ana_lane_3_quad_d_ctrl0[0]=(((r).ana_lane_3_quad_d_ctrl0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 28477 28478 /* 28479 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL0. 28480 */ 28481 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r,_r._ana_lane_3_quad_d_ctrl0) 28482 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r,_r._ana_lane_3_quad_d_ctrl0) 28483 28484 /* 28485 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28486 * will be redefined without the chip prefix for easier programming. 28487 * If multiple chips will be programmed in the same source file, then you should 28488 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28489 * and refer to the fully qualified versions. 28490 */ 28491 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28492 28493 #define ANA_LANE_3_QUAD_D_CTRL0r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r 28494 #define ANA_LANE_3_QUAD_D_CTRL0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_SIZE 28495 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_t ANA_LANE_3_QUAD_D_CTRL0r_t; 28496 #define ANA_LANE_3_QUAD_D_CTRL0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_CLR 28497 #define ANA_LANE_3_QUAD_D_CTRL0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_SET 28498 #define ANA_LANE_3_QUAD_D_CTRL0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_GET 28499 #define ANA_LANE_3_QUAD_D_CTRL0r_DC_COUPLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_DC_COUPLEf_GET 28500 #define ANA_LANE_3_QUAD_D_CTRL0r_DC_COUPLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_DC_COUPLEf_SET 28501 #define ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_GET 28502 #define ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDECT_12GMODEf_SET 28503 #define ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_GET 28504 #define ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_PWRDNf_SET 28505 #define ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_GET 28506 #define ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RX_SIGDET_BYPASSf_SET 28507 #define ANA_LANE_3_QUAD_D_CTRL0r_RXTX_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RXTX_PWRDNf_GET 28508 #define ANA_LANE_3_QUAD_D_CTRL0r_RXTX_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r_RXTX_PWRDNf_SET 28509 #define READ_ANA_LANE_3_QUAD_D_CTRL0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL0r 28510 #define WRITE_ANA_LANE_3_QUAD_D_CTRL0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL0r 28511 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL0r 28512 28513 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28514 /******************************************************************************* 28515 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL0r' 28516 */ 28517 28518 28519 28520 28521 /******************************************************************************* 28522 * CHIP: BCMI_HURACAN 28523 * REGISTER: ANA_LANE_3_QUAD_D_CTRL1 28524 * BLOCKS: ANA_LANE_3_QUAD_D 28525 * REGADDR: 0xb801 28526 * DEVAD: 1 28527 * DESC: control registers 0 28528 * RESETVAL: 0x0 (0) 28529 * ACCESS: R/W 28530 * FIELDS: 28531 * RX_SIGDET_THRESHOLD 28532 * REF_OCL 28533 * OCL_PWRDN 28534 * OCL_DISABLE_LOOP 28535 * RXTX_RESERVED_FOR_15_12 28536 */ 28537 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r (0x0001b801 | PHYMOD_REG_ACC_RAW) 28538 28539 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_SIZE 4 28540 28541 /* 28542 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL1. 28543 */ 28544 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_s { 28545 uint32_t v[1]; 28546 uint32_t ana_lane_3_quad_d_ctrl1[1]; 28547 uint32_t _ana_lane_3_quad_d_ctrl1; 28548 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_t; 28549 28550 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_CLR(r) (r).ana_lane_3_quad_d_ctrl1[0] = 0 28551 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_SET(r,d) (r).ana_lane_3_quad_d_ctrl1[0] = d 28552 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_GET(r) (r).ana_lane_3_quad_d_ctrl1[0] 28553 28554 /* 28555 * These macros can be used to access individual fields. 28556 */ 28557 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET(r) ((((r).ana_lane_3_quad_d_ctrl1[0]) >> 12) & 0xf) 28558 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET(r,f) (r).ana_lane_3_quad_d_ctrl1[0]=(((r).ana_lane_3_quad_d_ctrl1[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 28559 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET(r) ((((r).ana_lane_3_quad_d_ctrl1[0]) >> 9) & 0x1) 28560 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET(r,f) (r).ana_lane_3_quad_d_ctrl1[0]=(((r).ana_lane_3_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 9)) | ((((uint32_t)f) & 0x1) << 9)) | (1 << (16 + 9)) 28561 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_PWRDNf_GET(r) ((((r).ana_lane_3_quad_d_ctrl1[0]) >> 8) & 0x1) 28562 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_PWRDNf_SET(r,f) (r).ana_lane_3_quad_d_ctrl1[0]=(((r).ana_lane_3_quad_d_ctrl1[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 28563 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_REF_OCLf_GET(r) ((((r).ana_lane_3_quad_d_ctrl1[0]) >> 4) & 0x3) 28564 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_REF_OCLf_SET(r,f) (r).ana_lane_3_quad_d_ctrl1[0]=(((r).ana_lane_3_quad_d_ctrl1[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 28565 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET(r) (((r).ana_lane_3_quad_d_ctrl1[0]) & 0x7) 28566 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET(r,f) (r).ana_lane_3_quad_d_ctrl1[0]=(((r).ana_lane_3_quad_d_ctrl1[0] & ~((uint32_t)0x7)) | (((uint32_t)f) & 0x7)) | (0x7 << 16) 28567 28568 /* 28569 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL1. 28570 */ 28571 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r,_r._ana_lane_3_quad_d_ctrl1) 28572 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL1r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r,_r._ana_lane_3_quad_d_ctrl1) 28573 28574 /* 28575 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28576 * will be redefined without the chip prefix for easier programming. 28577 * If multiple chips will be programmed in the same source file, then you should 28578 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28579 * and refer to the fully qualified versions. 28580 */ 28581 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28582 28583 #define ANA_LANE_3_QUAD_D_CTRL1r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r 28584 #define ANA_LANE_3_QUAD_D_CTRL1r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_SIZE 28585 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_t ANA_LANE_3_QUAD_D_CTRL1r_t; 28586 #define ANA_LANE_3_QUAD_D_CTRL1r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_CLR 28587 #define ANA_LANE_3_QUAD_D_CTRL1r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_SET 28588 #define ANA_LANE_3_QUAD_D_CTRL1r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_GET 28589 #define ANA_LANE_3_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_GET 28590 #define ANA_LANE_3_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RXTX_RESERVED_FOR_15_12f_SET 28591 #define ANA_LANE_3_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_GET 28592 #define ANA_LANE_3_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_DISABLE_LOOPf_SET 28593 #define ANA_LANE_3_QUAD_D_CTRL1r_OCL_PWRDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_PWRDNf_GET 28594 #define ANA_LANE_3_QUAD_D_CTRL1r_OCL_PWRDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_OCL_PWRDNf_SET 28595 #define ANA_LANE_3_QUAD_D_CTRL1r_REF_OCLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_REF_OCLf_GET 28596 #define ANA_LANE_3_QUAD_D_CTRL1r_REF_OCLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_REF_OCLf_SET 28597 #define ANA_LANE_3_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_GET 28598 #define ANA_LANE_3_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r_RX_SIGDET_THRESHOLDf_SET 28599 #define READ_ANA_LANE_3_QUAD_D_CTRL1r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL1r 28600 #define WRITE_ANA_LANE_3_QUAD_D_CTRL1r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL1r 28601 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL1r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL1r 28602 28603 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28604 /******************************************************************************* 28605 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL1r' 28606 */ 28607 28608 28609 28610 28611 /******************************************************************************* 28612 * CHIP: BCMI_HURACAN 28613 * REGISTER: ANA_LANE_3_QUAD_D_CTRL2 28614 * BLOCKS: ANA_LANE_3_QUAD_D 28615 * REGADDR: 0xb802 28616 * DEVAD: 1 28617 * DESC: control registers 0 28618 * RESETVAL: 0x0 (0) 28619 * ACCESS: R/W 28620 * FIELDS: 28621 * CTLE_ENB_NEGIMP 28622 * CTLE_ENB_NEGCAP 28623 */ 28624 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r (0x0001b802 | PHYMOD_REG_ACC_RAW) 28625 28626 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_SIZE 4 28627 28628 /* 28629 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL2. 28630 */ 28631 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_s { 28632 uint32_t v[1]; 28633 uint32_t ana_lane_3_quad_d_ctrl2[1]; 28634 uint32_t _ana_lane_3_quad_d_ctrl2; 28635 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_t; 28636 28637 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CLR(r) (r).ana_lane_3_quad_d_ctrl2[0] = 0 28638 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_SET(r,d) (r).ana_lane_3_quad_d_ctrl2[0] = d 28639 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_GET(r) (r).ana_lane_3_quad_d_ctrl2[0] 28640 28641 /* 28642 * These macros can be used to access individual fields. 28643 */ 28644 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET(r) ((((r).ana_lane_3_quad_d_ctrl2[0]) >> 8) & 0x7f) 28645 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET(r,f) (r).ana_lane_3_quad_d_ctrl2[0]=(((r).ana_lane_3_quad_d_ctrl2[0] & ~((uint32_t)0x7f << 8)) | ((((uint32_t)f) & 0x7f) << 8)) | (127 << (16 + 8)) 28646 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET(r) (((r).ana_lane_3_quad_d_ctrl2[0]) & 0x7f) 28647 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET(r,f) (r).ana_lane_3_quad_d_ctrl2[0]=(((r).ana_lane_3_quad_d_ctrl2[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 28648 28649 /* 28650 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL2. 28651 */ 28652 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r,_r._ana_lane_3_quad_d_ctrl2) 28653 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL2r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r,_r._ana_lane_3_quad_d_ctrl2) 28654 28655 /* 28656 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28657 * will be redefined without the chip prefix for easier programming. 28658 * If multiple chips will be programmed in the same source file, then you should 28659 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28660 * and refer to the fully qualified versions. 28661 */ 28662 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28663 28664 #define ANA_LANE_3_QUAD_D_CTRL2r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r 28665 #define ANA_LANE_3_QUAD_D_CTRL2r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_SIZE 28666 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_t ANA_LANE_3_QUAD_D_CTRL2r_t; 28667 #define ANA_LANE_3_QUAD_D_CTRL2r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CLR 28668 #define ANA_LANE_3_QUAD_D_CTRL2r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_SET 28669 #define ANA_LANE_3_QUAD_D_CTRL2r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_GET 28670 #define ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_GET 28671 #define ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGCAPf_SET 28672 #define ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_GET 28673 #define ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r_CTLE_ENB_NEGIMPf_SET 28674 #define READ_ANA_LANE_3_QUAD_D_CTRL2r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL2r 28675 #define WRITE_ANA_LANE_3_QUAD_D_CTRL2r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL2r 28676 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL2r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL2r 28677 28678 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28679 /******************************************************************************* 28680 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL2r' 28681 */ 28682 28683 28684 28685 28686 /******************************************************************************* 28687 * CHIP: BCMI_HURACAN 28688 * REGISTER: ANA_LANE_3_QUAD_D_CTRL3 28689 * BLOCKS: ANA_LANE_3_QUAD_D 28690 * REGADDR: 0xb803 28691 * DEVAD: 1 28692 * DESC: control registers 0 28693 * RESETVAL: 0x0 (0) 28694 * ACCESS: R/W 28695 * FIELDS: 28696 * CTLE_EN_NEGRES 28697 * CTLE_EQSEL 28698 */ 28699 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r (0x0001b803 | PHYMOD_REG_ACC_RAW) 28700 28701 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_SIZE 4 28702 28703 /* 28704 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL3. 28705 */ 28706 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_s { 28707 uint32_t v[1]; 28708 uint32_t ana_lane_3_quad_d_ctrl3[1]; 28709 uint32_t _ana_lane_3_quad_d_ctrl3; 28710 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_t; 28711 28712 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CLR(r) (r).ana_lane_3_quad_d_ctrl3[0] = 0 28713 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_SET(r,d) (r).ana_lane_3_quad_d_ctrl3[0] = d 28714 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_GET(r) (r).ana_lane_3_quad_d_ctrl3[0] 28715 28716 /* 28717 * These macros can be used to access individual fields. 28718 */ 28719 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EQSELf_GET(r) ((((r).ana_lane_3_quad_d_ctrl3[0]) >> 8) & 0xff) 28720 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EQSELf_SET(r,f) (r).ana_lane_3_quad_d_ctrl3[0]=(((r).ana_lane_3_quad_d_ctrl3[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 28721 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET(r) (((r).ana_lane_3_quad_d_ctrl3[0]) & 0x7f) 28722 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET(r,f) (r).ana_lane_3_quad_d_ctrl3[0]=(((r).ana_lane_3_quad_d_ctrl3[0] & ~((uint32_t)0x7f)) | (((uint32_t)f) & 0x7f)) | (0x7f << 16) 28723 28724 /* 28725 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL3. 28726 */ 28727 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r,_r._ana_lane_3_quad_d_ctrl3) 28728 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL3r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r,_r._ana_lane_3_quad_d_ctrl3) 28729 28730 /* 28731 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28732 * will be redefined without the chip prefix for easier programming. 28733 * If multiple chips will be programmed in the same source file, then you should 28734 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28735 * and refer to the fully qualified versions. 28736 */ 28737 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28738 28739 #define ANA_LANE_3_QUAD_D_CTRL3r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r 28740 #define ANA_LANE_3_QUAD_D_CTRL3r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_SIZE 28741 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_t ANA_LANE_3_QUAD_D_CTRL3r_t; 28742 #define ANA_LANE_3_QUAD_D_CTRL3r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CLR 28743 #define ANA_LANE_3_QUAD_D_CTRL3r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_SET 28744 #define ANA_LANE_3_QUAD_D_CTRL3r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_GET 28745 #define ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EQSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EQSELf_GET 28746 #define ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EQSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EQSELf_SET 28747 #define ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_GET 28748 #define ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r_CTLE_EN_NEGRESf_SET 28749 #define READ_ANA_LANE_3_QUAD_D_CTRL3r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL3r 28750 #define WRITE_ANA_LANE_3_QUAD_D_CTRL3r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL3r 28751 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL3r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL3r 28752 28753 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28754 /******************************************************************************* 28755 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL3r' 28756 */ 28757 28758 28759 28760 28761 /******************************************************************************* 28762 * CHIP: BCMI_HURACAN 28763 * REGISTER: ANA_LANE_3_QUAD_D_CTRL4 28764 * BLOCKS: ANA_LANE_3_QUAD_D 28765 * REGADDR: 0xb804 28766 * DEVAD: 1 28767 * DESC: control registers 0 28768 * RESETVAL: 0x0 (0) 28769 * ACCESS: R/W 28770 * FIELDS: 28771 * CTLE_LZEN 28772 * RXTX_RESERVED_FOR_59_52 28773 */ 28774 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r (0x0001b804 | PHYMOD_REG_ACC_RAW) 28775 28776 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_SIZE 4 28777 28778 /* 28779 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL4. 28780 */ 28781 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_s { 28782 uint32_t v[1]; 28783 uint32_t ana_lane_3_quad_d_ctrl4[1]; 28784 uint32_t _ana_lane_3_quad_d_ctrl4; 28785 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_t; 28786 28787 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_CLR(r) (r).ana_lane_3_quad_d_ctrl4[0] = 0 28788 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_SET(r,d) (r).ana_lane_3_quad_d_ctrl4[0] = d 28789 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_GET(r) (r).ana_lane_3_quad_d_ctrl4[0] 28790 28791 /* 28792 * These macros can be used to access individual fields. 28793 */ 28794 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET(r) ((((r).ana_lane_3_quad_d_ctrl4[0]) >> 4) & 0xff) 28795 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET(r,f) (r).ana_lane_3_quad_d_ctrl4[0]=(((r).ana_lane_3_quad_d_ctrl4[0] & ~((uint32_t)0xff << 4)) | ((((uint32_t)f) & 0xff) << 4)) | (255 << (16 + 4)) 28796 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_CTLE_LZENf_GET(r) (((r).ana_lane_3_quad_d_ctrl4[0]) & 0x1) 28797 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_CTLE_LZENf_SET(r,f) (r).ana_lane_3_quad_d_ctrl4[0]=(((r).ana_lane_3_quad_d_ctrl4[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 28798 28799 /* 28800 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL4. 28801 */ 28802 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r,_r._ana_lane_3_quad_d_ctrl4) 28803 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL4r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r,_r._ana_lane_3_quad_d_ctrl4) 28804 28805 /* 28806 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28807 * will be redefined without the chip prefix for easier programming. 28808 * If multiple chips will be programmed in the same source file, then you should 28809 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28810 * and refer to the fully qualified versions. 28811 */ 28812 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28813 28814 #define ANA_LANE_3_QUAD_D_CTRL4r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r 28815 #define ANA_LANE_3_QUAD_D_CTRL4r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_SIZE 28816 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_t ANA_LANE_3_QUAD_D_CTRL4r_t; 28817 #define ANA_LANE_3_QUAD_D_CTRL4r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_CLR 28818 #define ANA_LANE_3_QUAD_D_CTRL4r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_SET 28819 #define ANA_LANE_3_QUAD_D_CTRL4r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_GET 28820 #define ANA_LANE_3_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_GET 28821 #define ANA_LANE_3_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_RXTX_RESERVED_FOR_59_52f_SET 28822 #define ANA_LANE_3_QUAD_D_CTRL4r_CTLE_LZENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_CTLE_LZENf_GET 28823 #define ANA_LANE_3_QUAD_D_CTRL4r_CTLE_LZENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r_CTLE_LZENf_SET 28824 #define READ_ANA_LANE_3_QUAD_D_CTRL4r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL4r 28825 #define WRITE_ANA_LANE_3_QUAD_D_CTRL4r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL4r 28826 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL4r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL4r 28827 28828 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28829 /******************************************************************************* 28830 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL4r' 28831 */ 28832 28833 28834 28835 28836 /******************************************************************************* 28837 * CHIP: BCMI_HURACAN 28838 * REGISTER: ANA_LANE_3_QUAD_D_CTRL5 28839 * BLOCKS: ANA_LANE_3_QUAD_D 28840 * REGADDR: 0xb805 28841 * DEVAD: 1 28842 * DESC: control registers 0 28843 * RESETVAL: 0x0 (0) 28844 * ACCESS: R/W 28845 * FIELDS: 28846 * CTLE_LOPEAKING 28847 * CTLE_PD 28848 * LA_GCTRL 28849 */ 28850 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r (0x0001b805 | PHYMOD_REG_ACC_RAW) 28851 28852 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_SIZE 4 28853 28854 /* 28855 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL5. 28856 */ 28857 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_s { 28858 uint32_t v[1]; 28859 uint32_t ana_lane_3_quad_d_ctrl5[1]; 28860 uint32_t _ana_lane_3_quad_d_ctrl5; 28861 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_t; 28862 28863 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CLR(r) (r).ana_lane_3_quad_d_ctrl5[0] = 0 28864 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_SET(r,d) (r).ana_lane_3_quad_d_ctrl5[0] = d 28865 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_GET(r) (r).ana_lane_3_quad_d_ctrl5[0] 28866 28867 /* 28868 * These macros can be used to access individual fields. 28869 */ 28870 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_LA_GCTRLf_GET(r) ((((r).ana_lane_3_quad_d_ctrl5[0]) >> 4) & 0x3ff) 28871 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_LA_GCTRLf_SET(r,f) (r).ana_lane_3_quad_d_ctrl5[0]=(((r).ana_lane_3_quad_d_ctrl5[0] & ~((uint32_t)0x3ff << 4)) | ((((uint32_t)f) & 0x3ff) << 4)) | (1023 << (16 + 4)) 28872 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_PDf_GET(r) ((((r).ana_lane_3_quad_d_ctrl5[0]) >> 1) & 0x1) 28873 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_PDf_SET(r,f) (r).ana_lane_3_quad_d_ctrl5[0]=(((r).ana_lane_3_quad_d_ctrl5[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 28874 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET(r) (((r).ana_lane_3_quad_d_ctrl5[0]) & 0x1) 28875 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET(r,f) (r).ana_lane_3_quad_d_ctrl5[0]=(((r).ana_lane_3_quad_d_ctrl5[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 28876 28877 /* 28878 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL5. 28879 */ 28880 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r,_r._ana_lane_3_quad_d_ctrl5) 28881 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL5r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r,_r._ana_lane_3_quad_d_ctrl5) 28882 28883 /* 28884 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28885 * will be redefined without the chip prefix for easier programming. 28886 * If multiple chips will be programmed in the same source file, then you should 28887 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28888 * and refer to the fully qualified versions. 28889 */ 28890 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28891 28892 #define ANA_LANE_3_QUAD_D_CTRL5r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r 28893 #define ANA_LANE_3_QUAD_D_CTRL5r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_SIZE 28894 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_t ANA_LANE_3_QUAD_D_CTRL5r_t; 28895 #define ANA_LANE_3_QUAD_D_CTRL5r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CLR 28896 #define ANA_LANE_3_QUAD_D_CTRL5r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_SET 28897 #define ANA_LANE_3_QUAD_D_CTRL5r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_GET 28898 #define ANA_LANE_3_QUAD_D_CTRL5r_LA_GCTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_LA_GCTRLf_GET 28899 #define ANA_LANE_3_QUAD_D_CTRL5r_LA_GCTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_LA_GCTRLf_SET 28900 #define ANA_LANE_3_QUAD_D_CTRL5r_CTLE_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_PDf_GET 28901 #define ANA_LANE_3_QUAD_D_CTRL5r_CTLE_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_PDf_SET 28902 #define ANA_LANE_3_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_GET 28903 #define ANA_LANE_3_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r_CTLE_LOPEAKINGf_SET 28904 #define READ_ANA_LANE_3_QUAD_D_CTRL5r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL5r 28905 #define WRITE_ANA_LANE_3_QUAD_D_CTRL5r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL5r 28906 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL5r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL5r 28907 28908 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28909 /******************************************************************************* 28910 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL5r' 28911 */ 28912 28913 28914 28915 28916 /******************************************************************************* 28917 * CHIP: BCMI_HURACAN 28918 * REGISTER: ANA_LANE_3_QUAD_D_CTRL6 28919 * BLOCKS: ANA_LANE_3_QUAD_D 28920 * REGADDR: 0xb806 28921 * DEVAD: 1 28922 * DESC: control registers 0 28923 * RESETVAL: 0x0 (0) 28924 * ACCESS: R/W 28925 * FIELDS: 28926 * LA_DEGAIN 28927 * LA_DETUNE 28928 */ 28929 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r (0x0001b806 | PHYMOD_REG_ACC_RAW) 28930 28931 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_SIZE 4 28932 28933 /* 28934 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL6. 28935 */ 28936 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_s { 28937 uint32_t v[1]; 28938 uint32_t ana_lane_3_quad_d_ctrl6[1]; 28939 uint32_t _ana_lane_3_quad_d_ctrl6; 28940 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_t; 28941 28942 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_CLR(r) (r).ana_lane_3_quad_d_ctrl6[0] = 0 28943 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_SET(r,d) (r).ana_lane_3_quad_d_ctrl6[0] = d 28944 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_GET(r) (r).ana_lane_3_quad_d_ctrl6[0] 28945 28946 /* 28947 * These macros can be used to access individual fields. 28948 */ 28949 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DETUNEf_GET(r) ((((r).ana_lane_3_quad_d_ctrl6[0]) >> 8) & 0xff) 28950 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DETUNEf_SET(r,f) (r).ana_lane_3_quad_d_ctrl6[0]=(((r).ana_lane_3_quad_d_ctrl6[0] & ~((uint32_t)0xff << 8)) | ((((uint32_t)f) & 0xff) << 8)) | (255 << (16 + 8)) 28951 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DEGAINf_GET(r) (((r).ana_lane_3_quad_d_ctrl6[0]) & 0x1f) 28952 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DEGAINf_SET(r,f) (r).ana_lane_3_quad_d_ctrl6[0]=(((r).ana_lane_3_quad_d_ctrl6[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 28953 28954 /* 28955 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL6. 28956 */ 28957 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r,_r._ana_lane_3_quad_d_ctrl6) 28958 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL6r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r,_r._ana_lane_3_quad_d_ctrl6) 28959 28960 /* 28961 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 28962 * will be redefined without the chip prefix for easier programming. 28963 * If multiple chips will be programmed in the same source file, then you should 28964 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 28965 * and refer to the fully qualified versions. 28966 */ 28967 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 28968 28969 #define ANA_LANE_3_QUAD_D_CTRL6r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r 28970 #define ANA_LANE_3_QUAD_D_CTRL6r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_SIZE 28971 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_t ANA_LANE_3_QUAD_D_CTRL6r_t; 28972 #define ANA_LANE_3_QUAD_D_CTRL6r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_CLR 28973 #define ANA_LANE_3_QUAD_D_CTRL6r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_SET 28974 #define ANA_LANE_3_QUAD_D_CTRL6r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_GET 28975 #define ANA_LANE_3_QUAD_D_CTRL6r_LA_DETUNEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DETUNEf_GET 28976 #define ANA_LANE_3_QUAD_D_CTRL6r_LA_DETUNEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DETUNEf_SET 28977 #define ANA_LANE_3_QUAD_D_CTRL6r_LA_DEGAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DEGAINf_GET 28978 #define ANA_LANE_3_QUAD_D_CTRL6r_LA_DEGAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r_LA_DEGAINf_SET 28979 #define READ_ANA_LANE_3_QUAD_D_CTRL6r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL6r 28980 #define WRITE_ANA_LANE_3_QUAD_D_CTRL6r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL6r 28981 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL6r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL6r 28982 28983 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 28984 /******************************************************************************* 28985 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL6r' 28986 */ 28987 28988 28989 28990 28991 /******************************************************************************* 28992 * CHIP: BCMI_HURACAN 28993 * REGISTER: ANA_LANE_3_QUAD_D_CTRL7 28994 * BLOCKS: ANA_LANE_3_QUAD_D 28995 * REGADDR: 0xb807 28996 * DEVAD: 1 28997 * DESC: control registers 0 28998 * RESETVAL: 0x0 (0) 28999 * ACCESS: R/W 29000 * FIELDS: 29001 * LA_LIN_MODE 29002 * RX_BIAS_FB_PDN 29003 */ 29004 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r (0x0001b807 | PHYMOD_REG_ACC_RAW) 29005 29006 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_SIZE 4 29007 29008 /* 29009 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL7. 29010 */ 29011 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_s { 29012 uint32_t v[1]; 29013 uint32_t ana_lane_3_quad_d_ctrl7[1]; 29014 uint32_t _ana_lane_3_quad_d_ctrl7; 29015 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_t; 29016 29017 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_CLR(r) (r).ana_lane_3_quad_d_ctrl7[0] = 0 29018 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_SET(r,d) (r).ana_lane_3_quad_d_ctrl7[0] = d 29019 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_GET(r) (r).ana_lane_3_quad_d_ctrl7[0] 29020 29021 /* 29022 * These macros can be used to access individual fields. 29023 */ 29024 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET(r) ((((r).ana_lane_3_quad_d_ctrl7[0]) >> 8) & 0x1) 29025 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET(r,f) (r).ana_lane_3_quad_d_ctrl7[0]=(((r).ana_lane_3_quad_d_ctrl7[0] & ~((uint32_t)0x1 << 8)) | ((((uint32_t)f) & 0x1) << 8)) | (1 << (16 + 8)) 29026 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_LA_LIN_MODEf_GET(r) (((r).ana_lane_3_quad_d_ctrl7[0]) & 0x1f) 29027 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_LA_LIN_MODEf_SET(r,f) (r).ana_lane_3_quad_d_ctrl7[0]=(((r).ana_lane_3_quad_d_ctrl7[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 29028 29029 /* 29030 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL7. 29031 */ 29032 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r,_r._ana_lane_3_quad_d_ctrl7) 29033 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL7r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r,_r._ana_lane_3_quad_d_ctrl7) 29034 29035 /* 29036 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29037 * will be redefined without the chip prefix for easier programming. 29038 * If multiple chips will be programmed in the same source file, then you should 29039 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29040 * and refer to the fully qualified versions. 29041 */ 29042 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29043 29044 #define ANA_LANE_3_QUAD_D_CTRL7r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r 29045 #define ANA_LANE_3_QUAD_D_CTRL7r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_SIZE 29046 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_t ANA_LANE_3_QUAD_D_CTRL7r_t; 29047 #define ANA_LANE_3_QUAD_D_CTRL7r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_CLR 29048 #define ANA_LANE_3_QUAD_D_CTRL7r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_SET 29049 #define ANA_LANE_3_QUAD_D_CTRL7r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_GET 29050 #define ANA_LANE_3_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_GET 29051 #define ANA_LANE_3_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_RX_BIAS_FB_PDNf_SET 29052 #define ANA_LANE_3_QUAD_D_CTRL7r_LA_LIN_MODEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_LA_LIN_MODEf_GET 29053 #define ANA_LANE_3_QUAD_D_CTRL7r_LA_LIN_MODEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r_LA_LIN_MODEf_SET 29054 #define READ_ANA_LANE_3_QUAD_D_CTRL7r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL7r 29055 #define WRITE_ANA_LANE_3_QUAD_D_CTRL7r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL7r 29056 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL7r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL7r 29057 29058 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29059 /******************************************************************************* 29060 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL7r' 29061 */ 29062 29063 29064 29065 29066 /******************************************************************************* 29067 * CHIP: BCMI_HURACAN 29068 * REGISTER: ANA_LANE_3_QUAD_D_CTRL8 29069 * BLOCKS: ANA_LANE_3_QUAD_D 29070 * REGADDR: 0xb808 29071 * DEVAD: 1 29072 * DESC: control registers 0 29073 * RESETVAL: 0x0 (0) 29074 * ACCESS: R/W 29075 * FIELDS: 29076 * LA_PD 29077 * LA_PD_IDLE 29078 * RXTX_RESERVED_FOR_99_95 29079 */ 29080 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r (0x0001b808 | PHYMOD_REG_ACC_RAW) 29081 29082 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_SIZE 4 29083 29084 /* 29085 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL8. 29086 */ 29087 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_s { 29088 uint32_t v[1]; 29089 uint32_t ana_lane_3_quad_d_ctrl8[1]; 29090 uint32_t _ana_lane_3_quad_d_ctrl8; 29091 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_t; 29092 29093 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_CLR(r) (r).ana_lane_3_quad_d_ctrl8[0] = 0 29094 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_SET(r,d) (r).ana_lane_3_quad_d_ctrl8[0] = d 29095 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_GET(r) (r).ana_lane_3_quad_d_ctrl8[0] 29096 29097 /* 29098 * These macros can be used to access individual fields. 29099 */ 29100 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET(r) ((((r).ana_lane_3_quad_d_ctrl8[0]) >> 4) & 0x1f) 29101 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET(r,f) (r).ana_lane_3_quad_d_ctrl8[0]=(((r).ana_lane_3_quad_d_ctrl8[0] & ~((uint32_t)0x1f << 4)) | ((((uint32_t)f) & 0x1f) << 4)) | (31 << (16 + 4)) 29102 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PD_IDLEf_GET(r) ((((r).ana_lane_3_quad_d_ctrl8[0]) >> 1) & 0x1) 29103 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PD_IDLEf_SET(r,f) (r).ana_lane_3_quad_d_ctrl8[0]=(((r).ana_lane_3_quad_d_ctrl8[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 29104 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PDf_GET(r) (((r).ana_lane_3_quad_d_ctrl8[0]) & 0x1) 29105 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PDf_SET(r,f) (r).ana_lane_3_quad_d_ctrl8[0]=(((r).ana_lane_3_quad_d_ctrl8[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 29106 29107 /* 29108 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL8. 29109 */ 29110 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r,_r._ana_lane_3_quad_d_ctrl8) 29111 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL8r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r,_r._ana_lane_3_quad_d_ctrl8) 29112 29113 /* 29114 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29115 * will be redefined without the chip prefix for easier programming. 29116 * If multiple chips will be programmed in the same source file, then you should 29117 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29118 * and refer to the fully qualified versions. 29119 */ 29120 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29121 29122 #define ANA_LANE_3_QUAD_D_CTRL8r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r 29123 #define ANA_LANE_3_QUAD_D_CTRL8r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_SIZE 29124 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_t ANA_LANE_3_QUAD_D_CTRL8r_t; 29125 #define ANA_LANE_3_QUAD_D_CTRL8r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_CLR 29126 #define ANA_LANE_3_QUAD_D_CTRL8r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_SET 29127 #define ANA_LANE_3_QUAD_D_CTRL8r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_GET 29128 #define ANA_LANE_3_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_GET 29129 #define ANA_LANE_3_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_RXTX_RESERVED_FOR_99_95f_SET 29130 #define ANA_LANE_3_QUAD_D_CTRL8r_LA_PD_IDLEf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PD_IDLEf_GET 29131 #define ANA_LANE_3_QUAD_D_CTRL8r_LA_PD_IDLEf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PD_IDLEf_SET 29132 #define ANA_LANE_3_QUAD_D_CTRL8r_LA_PDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PDf_GET 29133 #define ANA_LANE_3_QUAD_D_CTRL8r_LA_PDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r_LA_PDf_SET 29134 #define READ_ANA_LANE_3_QUAD_D_CTRL8r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL8r 29135 #define WRITE_ANA_LANE_3_QUAD_D_CTRL8r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL8r 29136 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL8r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL8r 29137 29138 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29139 /******************************************************************************* 29140 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL8r' 29141 */ 29142 29143 29144 29145 29146 /******************************************************************************* 29147 * CHIP: BCMI_HURACAN 29148 * REGISTER: ANA_LANE_3_QUAD_D_CTRL9 29149 * BLOCKS: ANA_LANE_3_QUAD_D 29150 * REGADDR: 0xb809 29151 * DEVAD: 1 29152 * DESC: control registers 0 29153 * RESETVAL: 0x0 (0) 29154 * ACCESS: R/W 29155 * FIELDS: 29156 * DRV_POST1 29157 * DLINE_SWING_1 29158 * DLINE_SWING_2 29159 * DLINE_DELAY_CTRL 29160 */ 29161 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r (0x0001b809 | PHYMOD_REG_ACC_RAW) 29162 29163 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_SIZE 4 29164 29165 /* 29166 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL9. 29167 */ 29168 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_s { 29169 uint32_t v[1]; 29170 uint32_t ana_lane_3_quad_d_ctrl9[1]; 29171 uint32_t _ana_lane_3_quad_d_ctrl9; 29172 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_t; 29173 29174 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_CLR(r) (r).ana_lane_3_quad_d_ctrl9[0] = 0 29175 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_SET(r,d) (r).ana_lane_3_quad_d_ctrl9[0] = d 29176 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_GET(r) (r).ana_lane_3_quad_d_ctrl9[0] 29177 29178 /* 29179 * These macros can be used to access individual fields. 29180 */ 29181 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET(r) ((((r).ana_lane_3_quad_d_ctrl9[0]) >> 12) & 0x7) 29182 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET(r,f) (r).ana_lane_3_quad_d_ctrl9[0]=(((r).ana_lane_3_quad_d_ctrl9[0] & ~((uint32_t)0x7 << 12)) | ((((uint32_t)f) & 0x7) << 12)) | (7 << (16 + 12)) 29183 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_2f_GET(r) ((((r).ana_lane_3_quad_d_ctrl9[0]) >> 8) & 0x3) 29184 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_2f_SET(r,f) (r).ana_lane_3_quad_d_ctrl9[0]=(((r).ana_lane_3_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 8)) | ((((uint32_t)f) & 0x3) << 8)) | (3 << (16 + 8)) 29185 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_1f_GET(r) ((((r).ana_lane_3_quad_d_ctrl9[0]) >> 4) & 0x3) 29186 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_1f_SET(r,f) (r).ana_lane_3_quad_d_ctrl9[0]=(((r).ana_lane_3_quad_d_ctrl9[0] & ~((uint32_t)0x3 << 4)) | ((((uint32_t)f) & 0x3) << 4)) | (3 << (16 + 4)) 29187 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DRV_POST1f_GET(r) (((r).ana_lane_3_quad_d_ctrl9[0]) & 0xf) 29188 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DRV_POST1f_SET(r,f) (r).ana_lane_3_quad_d_ctrl9[0]=(((r).ana_lane_3_quad_d_ctrl9[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 29189 29190 /* 29191 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL9. 29192 */ 29193 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r,_r._ana_lane_3_quad_d_ctrl9) 29194 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL9r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r,_r._ana_lane_3_quad_d_ctrl9) 29195 29196 /* 29197 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29198 * will be redefined without the chip prefix for easier programming. 29199 * If multiple chips will be programmed in the same source file, then you should 29200 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29201 * and refer to the fully qualified versions. 29202 */ 29203 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29204 29205 #define ANA_LANE_3_QUAD_D_CTRL9r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r 29206 #define ANA_LANE_3_QUAD_D_CTRL9r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_SIZE 29207 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_t ANA_LANE_3_QUAD_D_CTRL9r_t; 29208 #define ANA_LANE_3_QUAD_D_CTRL9r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_CLR 29209 #define ANA_LANE_3_QUAD_D_CTRL9r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_SET 29210 #define ANA_LANE_3_QUAD_D_CTRL9r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_GET 29211 #define ANA_LANE_3_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_GET 29212 #define ANA_LANE_3_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_DELAY_CTRLf_SET 29213 #define ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_2f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_2f_GET 29214 #define ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_2f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_2f_SET 29215 #define ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_1f_GET 29216 #define ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DLINE_SWING_1f_SET 29217 #define ANA_LANE_3_QUAD_D_CTRL9r_DRV_POST1f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DRV_POST1f_GET 29218 #define ANA_LANE_3_QUAD_D_CTRL9r_DRV_POST1f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r_DRV_POST1f_SET 29219 #define READ_ANA_LANE_3_QUAD_D_CTRL9r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL9r 29220 #define WRITE_ANA_LANE_3_QUAD_D_CTRL9r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL9r 29221 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL9r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL9r 29222 29223 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29224 /******************************************************************************* 29225 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL9r' 29226 */ 29227 29228 29229 29230 29231 /******************************************************************************* 29232 * CHIP: BCMI_HURACAN 29233 * REGISTER: ANA_LANE_3_QUAD_D_CTRL10 29234 * BLOCKS: ANA_LANE_3_QUAD_D 29235 * REGADDR: 0xb80a 29236 * DEVAD: 1 29237 * DESC: control registers 0 29238 * RESETVAL: 0x0 (0) 29239 * ACCESS: R/W 29240 * FIELDS: 29241 * DRV_PWD 29242 * DLINE_PWD 29243 * DRV_VBSEL 29244 * DRV_MAIN 29245 * DRV_MAIN_PU 29246 */ 29247 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r (0x0001b80a | PHYMOD_REG_ACC_RAW) 29248 29249 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_SIZE 4 29250 29251 /* 29252 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL10. 29253 */ 29254 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_s { 29255 uint32_t v[1]; 29256 uint32_t ana_lane_3_quad_d_ctrl10[1]; 29257 uint32_t _ana_lane_3_quad_d_ctrl10; 29258 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_t; 29259 29260 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_CLR(r) (r).ana_lane_3_quad_d_ctrl10[0] = 0 29261 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_SET(r,d) (r).ana_lane_3_quad_d_ctrl10[0] = d 29262 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_GET(r) (r).ana_lane_3_quad_d_ctrl10[0] 29263 29264 /* 29265 * These macros can be used to access individual fields. 29266 */ 29267 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET(r) ((((r).ana_lane_3_quad_d_ctrl10[0]) >> 12) & 0xf) 29268 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET(r,f) (r).ana_lane_3_quad_d_ctrl10[0]=(((r).ana_lane_3_quad_d_ctrl10[0] & ~((uint32_t)0xf << 12)) | ((((uint32_t)f) & 0xf) << 12)) | (15 << (16 + 12)) 29269 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAINf_GET(r) ((((r).ana_lane_3_quad_d_ctrl10[0]) >> 4) & 0x3f) 29270 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAINf_SET(r,f) (r).ana_lane_3_quad_d_ctrl10[0]=(((r).ana_lane_3_quad_d_ctrl10[0] & ~((uint32_t)0x3f << 4)) | ((((uint32_t)f) & 0x3f) << 4)) | (63 << (16 + 4)) 29271 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_VBSELf_GET(r) ((((r).ana_lane_3_quad_d_ctrl10[0]) >> 2) & 0x1) 29272 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_VBSELf_SET(r,f) (r).ana_lane_3_quad_d_ctrl10[0]=(((r).ana_lane_3_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 29273 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DLINE_PWDf_GET(r) ((((r).ana_lane_3_quad_d_ctrl10[0]) >> 1) & 0x1) 29274 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DLINE_PWDf_SET(r,f) (r).ana_lane_3_quad_d_ctrl10[0]=(((r).ana_lane_3_quad_d_ctrl10[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 29275 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_PWDf_GET(r) (((r).ana_lane_3_quad_d_ctrl10[0]) & 0x1) 29276 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_PWDf_SET(r,f) (r).ana_lane_3_quad_d_ctrl10[0]=(((r).ana_lane_3_quad_d_ctrl10[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 29277 29278 /* 29279 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL10. 29280 */ 29281 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r,_r._ana_lane_3_quad_d_ctrl10) 29282 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL10r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r,_r._ana_lane_3_quad_d_ctrl10) 29283 29284 /* 29285 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29286 * will be redefined without the chip prefix for easier programming. 29287 * If multiple chips will be programmed in the same source file, then you should 29288 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29289 * and refer to the fully qualified versions. 29290 */ 29291 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29292 29293 #define ANA_LANE_3_QUAD_D_CTRL10r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r 29294 #define ANA_LANE_3_QUAD_D_CTRL10r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_SIZE 29295 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_t ANA_LANE_3_QUAD_D_CTRL10r_t; 29296 #define ANA_LANE_3_QUAD_D_CTRL10r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_CLR 29297 #define ANA_LANE_3_QUAD_D_CTRL10r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_SET 29298 #define ANA_LANE_3_QUAD_D_CTRL10r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_GET 29299 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAIN_PUf_GET 29300 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAIN_PUf_SET 29301 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAINf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAINf_GET 29302 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAINf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_MAINf_SET 29303 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_VBSELf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_VBSELf_GET 29304 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_VBSELf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_VBSELf_SET 29305 #define ANA_LANE_3_QUAD_D_CTRL10r_DLINE_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DLINE_PWDf_GET 29306 #define ANA_LANE_3_QUAD_D_CTRL10r_DLINE_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DLINE_PWDf_SET 29307 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_PWDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_PWDf_GET 29308 #define ANA_LANE_3_QUAD_D_CTRL10r_DRV_PWDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r_DRV_PWDf_SET 29309 #define READ_ANA_LANE_3_QUAD_D_CTRL10r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL10r 29310 #define WRITE_ANA_LANE_3_QUAD_D_CTRL10r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL10r 29311 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL10r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL10r 29312 29313 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29314 /******************************************************************************* 29315 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL10r' 29316 */ 29317 29318 29319 29320 29321 /******************************************************************************* 29322 * CHIP: BCMI_HURACAN 29323 * REGISTER: ANA_LANE_3_QUAD_D_CTRL11 29324 * BLOCKS: ANA_LANE_3_QUAD_D 29325 * REGADDR: 0xb80b 29326 * DEVAD: 1 29327 * DESC: control registers 0 29328 * RESETVAL: 0x0 (0) 29329 * ACCESS: R/W 29330 * FIELDS: 29331 * RXTX_RESERVED_FOR_143_128 29332 */ 29333 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r (0x0001b80b | PHYMOD_REG_ACC_RAW) 29334 29335 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_SIZE 4 29336 29337 /* 29338 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL11. 29339 */ 29340 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_s { 29341 uint32_t v[1]; 29342 uint32_t ana_lane_3_quad_d_ctrl11[1]; 29343 uint32_t _ana_lane_3_quad_d_ctrl11; 29344 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_t; 29345 29346 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_CLR(r) (r).ana_lane_3_quad_d_ctrl11[0] = 0 29347 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_SET(r,d) (r).ana_lane_3_quad_d_ctrl11[0] = d 29348 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_GET(r) (r).ana_lane_3_quad_d_ctrl11[0] 29349 29350 /* 29351 * These macros can be used to access individual fields. 29352 */ 29353 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET(r) (((r).ana_lane_3_quad_d_ctrl11[0]) & 0xffff) 29354 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET(r,f) (r).ana_lane_3_quad_d_ctrl11[0]=(((r).ana_lane_3_quad_d_ctrl11[0] & ~((uint32_t)0xffff)) | (((uint32_t)f) & 0xffff)) | (0xffff << 16) 29355 29356 /* 29357 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL11. 29358 */ 29359 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r,_r._ana_lane_3_quad_d_ctrl11) 29360 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL11r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r,_r._ana_lane_3_quad_d_ctrl11) 29361 29362 /* 29363 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29364 * will be redefined without the chip prefix for easier programming. 29365 * If multiple chips will be programmed in the same source file, then you should 29366 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29367 * and refer to the fully qualified versions. 29368 */ 29369 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29370 29371 #define ANA_LANE_3_QUAD_D_CTRL11r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r 29372 #define ANA_LANE_3_QUAD_D_CTRL11r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_SIZE 29373 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_t ANA_LANE_3_QUAD_D_CTRL11r_t; 29374 #define ANA_LANE_3_QUAD_D_CTRL11r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_CLR 29375 #define ANA_LANE_3_QUAD_D_CTRL11r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_SET 29376 #define ANA_LANE_3_QUAD_D_CTRL11r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_GET 29377 #define ANA_LANE_3_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_GET 29378 #define ANA_LANE_3_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r_RXTX_RESERVED_FOR_143_128f_SET 29379 #define READ_ANA_LANE_3_QUAD_D_CTRL11r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL11r 29380 #define WRITE_ANA_LANE_3_QUAD_D_CTRL11r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL11r 29381 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL11r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL11r 29382 29383 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29384 /******************************************************************************* 29385 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL11r' 29386 */ 29387 29388 29389 29390 29391 /******************************************************************************* 29392 * CHIP: BCMI_HURACAN 29393 * REGISTER: ANA_LANE_3_QUAD_D_CTRL12 29394 * BLOCKS: ANA_LANE_3_QUAD_D 29395 * REGADDR: 0xb80c 29396 * DEVAD: 1 29397 * DESC: control registers 0 29398 * RESETVAL: 0x0 (0) 29399 * ACCESS: R/W 29400 * FIELDS: 29401 * LA_RESCAL_FRC_VAL 29402 * LA_RESCAL_FRC 29403 * DRV_RESCAL_FRC_VAL 29404 * DRV_RESCAL_FRC 29405 */ 29406 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r (0x0001b80c | PHYMOD_REG_ACC_RAW) 29407 29408 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_SIZE 4 29409 29410 /* 29411 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL12. 29412 */ 29413 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_s { 29414 uint32_t v[1]; 29415 uint32_t ana_lane_3_quad_d_ctrl12[1]; 29416 uint32_t _ana_lane_3_quad_d_ctrl12; 29417 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_t; 29418 29419 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_CLR(r) (r).ana_lane_3_quad_d_ctrl12[0] = 0 29420 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_SET(r,d) (r).ana_lane_3_quad_d_ctrl12[0] = d 29421 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_GET(r) (r).ana_lane_3_quad_d_ctrl12[0] 29422 29423 /* 29424 * These macros can be used to access individual fields. 29425 */ 29426 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_d_ctrl12[0]) >> 12) & 0x1) 29427 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_d_ctrl12[0]=(((r).ana_lane_3_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 12)) | ((((uint32_t)f) & 0x1) << 12)) | (1 << (16 + 12)) 29428 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_d_ctrl12[0]) >> 8) & 0xf) 29429 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_d_ctrl12[0]=(((r).ana_lane_3_quad_d_ctrl12[0] & ~((uint32_t)0xf << 8)) | ((((uint32_t)f) & 0xf) << 8)) | (15 << (16 + 8)) 29430 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_d_ctrl12[0]) >> 4) & 0x1) 29431 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_d_ctrl12[0]=(((r).ana_lane_3_quad_d_ctrl12[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 29432 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_d_ctrl12[0]) & 0xf) 29433 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_d_ctrl12[0]=(((r).ana_lane_3_quad_d_ctrl12[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 29434 29435 /* 29436 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL12. 29437 */ 29438 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r,_r._ana_lane_3_quad_d_ctrl12) 29439 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL12r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r,_r._ana_lane_3_quad_d_ctrl12) 29440 29441 /* 29442 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29443 * will be redefined without the chip prefix for easier programming. 29444 * If multiple chips will be programmed in the same source file, then you should 29445 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29446 * and refer to the fully qualified versions. 29447 */ 29448 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29449 29450 #define ANA_LANE_3_QUAD_D_CTRL12r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r 29451 #define ANA_LANE_3_QUAD_D_CTRL12r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_SIZE 29452 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_t ANA_LANE_3_QUAD_D_CTRL12r_t; 29453 #define ANA_LANE_3_QUAD_D_CTRL12r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_CLR 29454 #define ANA_LANE_3_QUAD_D_CTRL12r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_SET 29455 #define ANA_LANE_3_QUAD_D_CTRL12r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_GET 29456 #define ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_GET 29457 #define ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRCf_SET 29458 #define ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_GET 29459 #define ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_DRV_RESCAL_FRC_VALf_SET 29460 #define ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRCf_GET 29461 #define ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRCf_SET 29462 #define ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_GET 29463 #define ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r_LA_RESCAL_FRC_VALf_SET 29464 #define READ_ANA_LANE_3_QUAD_D_CTRL12r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL12r 29465 #define WRITE_ANA_LANE_3_QUAD_D_CTRL12r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL12r 29466 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL12r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL12r 29467 29468 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29469 /******************************************************************************* 29470 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL12r' 29471 */ 29472 29473 29474 29475 29476 /******************************************************************************* 29477 * CHIP: BCMI_HURACAN 29478 * REGISTER: ANA_LANE_3_QUAD_D_CTRL13 29479 * BLOCKS: ANA_LANE_3_QUAD_D 29480 * REGADDR: 0xb80d 29481 * DEVAD: 1 29482 * DESC: control registers 0 29483 * RESETVAL: 0x0 (0) 29484 * ACCESS: R/W 29485 * FIELDS: 29486 * CTLE_RESCAL_FRC_VAL 29487 * CTLE_RESCAL_FRC 29488 */ 29489 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r (0x0001b80d | PHYMOD_REG_ACC_RAW) 29490 29491 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_SIZE 4 29492 29493 /* 29494 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL13. 29495 */ 29496 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_s { 29497 uint32_t v[1]; 29498 uint32_t ana_lane_3_quad_d_ctrl13[1]; 29499 uint32_t _ana_lane_3_quad_d_ctrl13; 29500 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_t; 29501 29502 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CLR(r) (r).ana_lane_3_quad_d_ctrl13[0] = 0 29503 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_SET(r,d) (r).ana_lane_3_quad_d_ctrl13[0] = d 29504 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_GET(r) (r).ana_lane_3_quad_d_ctrl13[0] 29505 29506 /* 29507 * These macros can be used to access individual fields. 29508 */ 29509 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET(r) ((((r).ana_lane_3_quad_d_ctrl13[0]) >> 4) & 0x1) 29510 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET(r,f) (r).ana_lane_3_quad_d_ctrl13[0]=(((r).ana_lane_3_quad_d_ctrl13[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 29511 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET(r) (((r).ana_lane_3_quad_d_ctrl13[0]) & 0xf) 29512 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_d_ctrl13[0]=(((r).ana_lane_3_quad_d_ctrl13[0] & ~((uint32_t)0xf)) | (((uint32_t)f) & 0xf)) | (0xf << 16) 29513 29514 /* 29515 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL13. 29516 */ 29517 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r,_r._ana_lane_3_quad_d_ctrl13) 29518 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL13r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r,_r._ana_lane_3_quad_d_ctrl13) 29519 29520 /* 29521 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29522 * will be redefined without the chip prefix for easier programming. 29523 * If multiple chips will be programmed in the same source file, then you should 29524 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29525 * and refer to the fully qualified versions. 29526 */ 29527 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29528 29529 #define ANA_LANE_3_QUAD_D_CTRL13r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r 29530 #define ANA_LANE_3_QUAD_D_CTRL13r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_SIZE 29531 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_t ANA_LANE_3_QUAD_D_CTRL13r_t; 29532 #define ANA_LANE_3_QUAD_D_CTRL13r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CLR 29533 #define ANA_LANE_3_QUAD_D_CTRL13r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_SET 29534 #define ANA_LANE_3_QUAD_D_CTRL13r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_GET 29535 #define ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_GET 29536 #define ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRCf_SET 29537 #define ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_GET 29538 #define ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r_CTLE_RESCAL_FRC_VALf_SET 29539 #define READ_ANA_LANE_3_QUAD_D_CTRL13r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL13r 29540 #define WRITE_ANA_LANE_3_QUAD_D_CTRL13r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL13r 29541 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL13r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL13r 29542 29543 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29544 /******************************************************************************* 29545 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL13r' 29546 */ 29547 29548 29549 29550 29551 /******************************************************************************* 29552 * CHIP: BCMI_HURACAN 29553 * REGISTER: ANA_LANE_3_QUAD_D_CTRL14 29554 * BLOCKS: ANA_LANE_3_QUAD_D 29555 * REGADDR: 0xb80e 29556 * DEVAD: 1 29557 * DESC: control registers 0 29558 * RESETVAL: 0x0 (0) 29559 * ACCESS: R/W 29560 * FIELDS: 29561 * TX_IDLE_FRC_VAL 29562 * TX_IDLE_FRC 29563 * RXSD_IDLE_OVRD 29564 */ 29565 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r (0x0001b80e | PHYMOD_REG_ACC_RAW) 29566 29567 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_SIZE 4 29568 29569 /* 29570 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL14. 29571 */ 29572 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_s { 29573 uint32_t v[1]; 29574 uint32_t ana_lane_3_quad_d_ctrl14[1]; 29575 uint32_t _ana_lane_3_quad_d_ctrl14; 29576 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_t; 29577 29578 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_CLR(r) (r).ana_lane_3_quad_d_ctrl14[0] = 0 29579 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_SET(r,d) (r).ana_lane_3_quad_d_ctrl14[0] = d 29580 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_GET(r) (r).ana_lane_3_quad_d_ctrl14[0] 29581 29582 /* 29583 * These macros can be used to access individual fields. 29584 */ 29585 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET(r) ((((r).ana_lane_3_quad_d_ctrl14[0]) >> 4) & 0x1) 29586 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET(r,f) (r).ana_lane_3_quad_d_ctrl14[0]=(((r).ana_lane_3_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 4)) | ((((uint32_t)f) & 0x1) << 4)) | (1 << (16 + 4)) 29587 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET(r) ((((r).ana_lane_3_quad_d_ctrl14[0]) >> 1) & 0x1) 29588 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET(r,f) (r).ana_lane_3_quad_d_ctrl14[0]=(((r).ana_lane_3_quad_d_ctrl14[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 29589 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET(r) (((r).ana_lane_3_quad_d_ctrl14[0]) & 0x1) 29590 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_d_ctrl14[0]=(((r).ana_lane_3_quad_d_ctrl14[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 29591 29592 /* 29593 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL14. 29594 */ 29595 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r,_r._ana_lane_3_quad_d_ctrl14) 29596 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL14r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r,_r._ana_lane_3_quad_d_ctrl14) 29597 29598 /* 29599 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29600 * will be redefined without the chip prefix for easier programming. 29601 * If multiple chips will be programmed in the same source file, then you should 29602 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29603 * and refer to the fully qualified versions. 29604 */ 29605 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29606 29607 #define ANA_LANE_3_QUAD_D_CTRL14r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r 29608 #define ANA_LANE_3_QUAD_D_CTRL14r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_SIZE 29609 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_t ANA_LANE_3_QUAD_D_CTRL14r_t; 29610 #define ANA_LANE_3_QUAD_D_CTRL14r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_CLR 29611 #define ANA_LANE_3_QUAD_D_CTRL14r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_SET 29612 #define ANA_LANE_3_QUAD_D_CTRL14r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_GET 29613 #define ANA_LANE_3_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_GET 29614 #define ANA_LANE_3_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_RXSD_IDLE_OVRDf_SET 29615 #define ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRCf_GET 29616 #define ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRCf_SET 29617 #define ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_GET 29618 #define ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r_TX_IDLE_FRC_VALf_SET 29619 #define READ_ANA_LANE_3_QUAD_D_CTRL14r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL14r 29620 #define WRITE_ANA_LANE_3_QUAD_D_CTRL14r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL14r 29621 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL14r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL14r 29622 29623 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29624 /******************************************************************************* 29625 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL14r' 29626 */ 29627 29628 29629 29630 29631 /******************************************************************************* 29632 * CHIP: BCMI_HURACAN 29633 * REGISTER: ANA_LANE_3_QUAD_D_CTRL15 29634 * BLOCKS: ANA_LANE_3_QUAD_D 29635 * REGADDR: 0xb80f 29636 * DEVAD: 1 29637 * DESC: sigdet filter settings 0 29638 * RESETVAL: 0x0 (0) 29639 * ACCESS: R/W 29640 * FIELDS: 29641 * SIGDET_DIS 29642 * SIGDET_1US_EN 29643 * SIGDET_FRC_VAL 29644 * SIGDET_FRC 29645 * HOLD_LOS_COUNT 29646 * HOLD_SD_COUNT 29647 */ 29648 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r (0x0001b80f | PHYMOD_REG_ACC_RAW) 29649 29650 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIZE 4 29651 29652 /* 29653 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL15. 29654 */ 29655 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_s { 29656 uint32_t v[1]; 29657 uint32_t ana_lane_3_quad_d_ctrl15[1]; 29658 uint32_t _ana_lane_3_quad_d_ctrl15; 29659 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_t; 29660 29661 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_CLR(r) (r).ana_lane_3_quad_d_ctrl15[0] = 0 29662 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SET(r,d) (r).ana_lane_3_quad_d_ctrl15[0] = d 29663 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_GET(r) (r).ana_lane_3_quad_d_ctrl15[0] 29664 29665 /* 29666 * These macros can be used to access individual fields. 29667 */ 29668 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_d_ctrl15[0]) >> 8) & 0x7) 29669 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_d_ctrl15[0]=(((r).ana_lane_3_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 8)) | ((((uint32_t)f) & 0x7) << 8)) | (7 << (16 + 8)) 29670 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET(r) ((((r).ana_lane_3_quad_d_ctrl15[0]) >> 4) & 0x7) 29671 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_d_ctrl15[0]=(((r).ana_lane_3_quad_d_ctrl15[0] & ~((uint32_t)0x7 << 4)) | ((((uint32_t)f) & 0x7) << 4)) | (7 << (16 + 4)) 29672 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRCf_GET(r) ((((r).ana_lane_3_quad_d_ctrl15[0]) >> 3) & 0x1) 29673 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRCf_SET(r,f) (r).ana_lane_3_quad_d_ctrl15[0]=(((r).ana_lane_3_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 3)) | ((((uint32_t)f) & 0x1) << 3)) | (1 << (16 + 3)) 29674 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET(r) ((((r).ana_lane_3_quad_d_ctrl15[0]) >> 2) & 0x1) 29675 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET(r,f) (r).ana_lane_3_quad_d_ctrl15[0]=(((r).ana_lane_3_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 2)) | ((((uint32_t)f) & 0x1) << 2)) | (1 << (16 + 2)) 29676 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET(r) ((((r).ana_lane_3_quad_d_ctrl15[0]) >> 1) & 0x1) 29677 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET(r,f) (r).ana_lane_3_quad_d_ctrl15[0]=(((r).ana_lane_3_quad_d_ctrl15[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 29678 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_DISf_GET(r) (((r).ana_lane_3_quad_d_ctrl15[0]) & 0x1) 29679 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_DISf_SET(r,f) (r).ana_lane_3_quad_d_ctrl15[0]=(((r).ana_lane_3_quad_d_ctrl15[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 29680 29681 /* 29682 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL15. 29683 */ 29684 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r,_r._ana_lane_3_quad_d_ctrl15) 29685 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL15r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r,_r._ana_lane_3_quad_d_ctrl15) 29686 29687 /* 29688 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29689 * will be redefined without the chip prefix for easier programming. 29690 * If multiple chips will be programmed in the same source file, then you should 29691 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29692 * and refer to the fully qualified versions. 29693 */ 29694 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29695 29696 #define ANA_LANE_3_QUAD_D_CTRL15r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r 29697 #define ANA_LANE_3_QUAD_D_CTRL15r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIZE 29698 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_t ANA_LANE_3_QUAD_D_CTRL15r_t; 29699 #define ANA_LANE_3_QUAD_D_CTRL15r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_CLR 29700 #define ANA_LANE_3_QUAD_D_CTRL15r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SET 29701 #define ANA_LANE_3_QUAD_D_CTRL15r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_GET 29702 #define ANA_LANE_3_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_SD_COUNTf_GET 29703 #define ANA_LANE_3_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_SD_COUNTf_SET 29704 #define ANA_LANE_3_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_GET 29705 #define ANA_LANE_3_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_HOLD_LOS_COUNTf_SET 29706 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRCf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRCf_GET 29707 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRCf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRCf_SET 29708 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRC_VALf_GET 29709 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_FRC_VALf_SET 29710 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_1US_ENf_GET 29711 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_1US_ENf_SET 29712 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_DISf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_DISf_GET 29713 #define ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_DISf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r_SIGDET_DISf_SET 29714 #define READ_ANA_LANE_3_QUAD_D_CTRL15r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL15r 29715 #define WRITE_ANA_LANE_3_QUAD_D_CTRL15r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL15r 29716 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL15r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL15r 29717 29718 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29719 /******************************************************************************* 29720 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL15r' 29721 */ 29722 29723 29724 29725 29726 /******************************************************************************* 29727 * CHIP: BCMI_HURACAN 29728 * REGISTER: ANA_LANE_3_QUAD_D_CTRL16 29729 * BLOCKS: ANA_LANE_3_QUAD_D 29730 * REGADDR: 0xb810 29731 * DEVAD: 1 29732 * DESC: sigdet filter settings 1 29733 * RESETVAL: 0x0 (0) 29734 * ACCESS: R/W 29735 * FIELDS: 29736 * LOS_COUNT 29737 * SD_COUNT 29738 */ 29739 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r (0x0001b810 | PHYMOD_REG_ACC_RAW) 29740 29741 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SIZE 4 29742 29743 /* 29744 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_CTRL16. 29745 */ 29746 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_s { 29747 uint32_t v[1]; 29748 uint32_t ana_lane_3_quad_d_ctrl16[1]; 29749 uint32_t _ana_lane_3_quad_d_ctrl16; 29750 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_t; 29751 29752 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_CLR(r) (r).ana_lane_3_quad_d_ctrl16[0] = 0 29753 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SET(r,d) (r).ana_lane_3_quad_d_ctrl16[0] = d 29754 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_GET(r) (r).ana_lane_3_quad_d_ctrl16[0] 29755 29756 /* 29757 * These macros can be used to access individual fields. 29758 */ 29759 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SD_COUNTf_GET(r) ((((r).ana_lane_3_quad_d_ctrl16[0]) >> 8) & 0x1f) 29760 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SD_COUNTf_SET(r,f) (r).ana_lane_3_quad_d_ctrl16[0]=(((r).ana_lane_3_quad_d_ctrl16[0] & ~((uint32_t)0x1f << 8)) | ((((uint32_t)f) & 0x1f) << 8)) | (31 << (16 + 8)) 29761 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_LOS_COUNTf_GET(r) (((r).ana_lane_3_quad_d_ctrl16[0]) & 0x1f) 29762 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_LOS_COUNTf_SET(r,f) (r).ana_lane_3_quad_d_ctrl16[0]=(((r).ana_lane_3_quad_d_ctrl16[0] & ~((uint32_t)0x1f)) | (((uint32_t)f) & 0x1f)) | (0x1f << 16) 29763 29764 /* 29765 * These macros can be used to access ANA_LANE_3_QUAD_D_CTRL16. 29766 */ 29767 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r,_r._ana_lane_3_quad_d_ctrl16) 29768 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL16r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r,_r._ana_lane_3_quad_d_ctrl16) 29769 29770 /* 29771 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29772 * will be redefined without the chip prefix for easier programming. 29773 * If multiple chips will be programmed in the same source file, then you should 29774 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29775 * and refer to the fully qualified versions. 29776 */ 29777 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29778 29779 #define ANA_LANE_3_QUAD_D_CTRL16r BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r 29780 #define ANA_LANE_3_QUAD_D_CTRL16r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SIZE 29781 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_t ANA_LANE_3_QUAD_D_CTRL16r_t; 29782 #define ANA_LANE_3_QUAD_D_CTRL16r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_CLR 29783 #define ANA_LANE_3_QUAD_D_CTRL16r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SET 29784 #define ANA_LANE_3_QUAD_D_CTRL16r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_GET 29785 #define ANA_LANE_3_QUAD_D_CTRL16r_SD_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SD_COUNTf_GET 29786 #define ANA_LANE_3_QUAD_D_CTRL16r_SD_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_SD_COUNTf_SET 29787 #define ANA_LANE_3_QUAD_D_CTRL16r_LOS_COUNTf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_LOS_COUNTf_GET 29788 #define ANA_LANE_3_QUAD_D_CTRL16r_LOS_COUNTf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r_LOS_COUNTf_SET 29789 #define READ_ANA_LANE_3_QUAD_D_CTRL16r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_CTRL16r 29790 #define WRITE_ANA_LANE_3_QUAD_D_CTRL16r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_CTRL16r 29791 #define MODIFY_ANA_LANE_3_QUAD_D_CTRL16r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_CTRL16r 29792 29793 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29794 /******************************************************************************* 29795 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_CTRL16r' 29796 */ 29797 29798 29799 29800 29801 /******************************************************************************* 29802 * CHIP: BCMI_HURACAN 29803 * REGISTER: ANA_LANE_3_QUAD_D_STATUS0 29804 * BLOCKS: ANA_LANE_3_QUAD_D 29805 * REGADDR: 0xb820 29806 * DEVAD: 1 29807 * DESC: status registers 0 29808 * RESETVAL: 0x0 (0) 29809 * ACCESS: R/W 29810 * FIELDS: 29811 * O_RX_SIGDET 29812 * DG_RX_SIGDET 29813 */ 29814 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r (0x0001b820 | PHYMOD_REG_ACC_RAW) 29815 29816 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_SIZE 4 29817 29818 /* 29819 * This structure should be used to declare and program ANA_LANE_3_QUAD_D_STATUS0. 29820 */ 29821 typedef union BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_s { 29822 uint32_t v[1]; 29823 uint32_t ana_lane_3_quad_d_status0[1]; 29824 uint32_t _ana_lane_3_quad_d_status0; 29825 } BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_t; 29826 29827 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_CLR(r) (r).ana_lane_3_quad_d_status0[0] = 0 29828 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_SET(r,d) (r).ana_lane_3_quad_d_status0[0] = d 29829 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_GET(r) (r).ana_lane_3_quad_d_status0[0] 29830 29831 /* 29832 * These macros can be used to access individual fields. 29833 */ 29834 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET(r) ((((r).ana_lane_3_quad_d_status0[0]) >> 1) & 0x1) 29835 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_d_status0[0]=(((r).ana_lane_3_quad_d_status0[0] & ~((uint32_t)0x1 << 1)) | ((((uint32_t)f) & 0x1) << 1)) | (1 << (16 + 1)) 29836 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_O_RX_SIGDETf_GET(r) (((r).ana_lane_3_quad_d_status0[0]) & 0x1) 29837 #define BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_O_RX_SIGDETf_SET(r,f) (r).ana_lane_3_quad_d_status0[0]=(((r).ana_lane_3_quad_d_status0[0] & ~((uint32_t)0x1)) | (((uint32_t)f) & 0x1)) | (0x1 << 16) 29838 29839 /* 29840 * These macros can be used to access ANA_LANE_3_QUAD_D_STATUS0. 29841 */ 29842 #define BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_READ(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r,_r._ana_lane_3_quad_d_status0) 29843 #define BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_STATUS0r(_pc,_r) PHYMOD_BUS_WRITE(_pc,BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r,_r._ana_lane_3_quad_d_status0) 29844 29845 /* 29846 * Unless PHYMOD_EXCLUDE_CHIPLESS_TYPES is defined, all of the above types 29847 * will be redefined without the chip prefix for easier programming. 29848 * If multiple chips will be programmed in the same source file, then you should 29849 * define PHYMOD_EXCLUDE_CHIPLESS_TYPES before including all chip header files 29850 * and refer to the fully qualified versions. 29851 */ 29852 #ifndef PHYMOD_EXCLUDE_CHIPLESS_TYPES 29853 29854 #define ANA_LANE_3_QUAD_D_STATUS0r BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r 29855 #define ANA_LANE_3_QUAD_D_STATUS0r_SIZE BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_SIZE 29856 typedef BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_t ANA_LANE_3_QUAD_D_STATUS0r_t; 29857 #define ANA_LANE_3_QUAD_D_STATUS0r_CLR BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_CLR 29858 #define ANA_LANE_3_QUAD_D_STATUS0r_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_SET 29859 #define ANA_LANE_3_QUAD_D_STATUS0r_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_GET 29860 #define ANA_LANE_3_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_DG_RX_SIGDETf_GET 29861 #define ANA_LANE_3_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_DG_RX_SIGDETf_SET 29862 #define ANA_LANE_3_QUAD_D_STATUS0r_O_RX_SIGDETf_GET BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_O_RX_SIGDETf_GET 29863 #define ANA_LANE_3_QUAD_D_STATUS0r_O_RX_SIGDETf_SET BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r_O_RX_SIGDETf_SET 29864 #define READ_ANA_LANE_3_QUAD_D_STATUS0r BCMI_HURACAN_READ_ANA_LANE_3_QUAD_D_STATUS0r 29865 #define WRITE_ANA_LANE_3_QUAD_D_STATUS0r BCMI_HURACAN_WRITE_ANA_LANE_3_QUAD_D_STATUS0r 29866 #define MODIFY_ANA_LANE_3_QUAD_D_STATUS0r BCMI_HURACAN_MODIFY_ANA_LANE_3_QUAD_D_STATUS0r 29867 29868 #endif /* PHYMOD_EXCLUDE_CHIPLESS_TYPES */ 29869 /******************************************************************************* 29870 * End of 'BCMI_HURACAN_ANA_LANE_3_QUAD_D_STATUS0r' 29871 */ 29872 29873 29874 29875 29876 #endif /* __BCMI_HURACAN_DEFS_H__ */