furia_regs_structs.h (669052B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 /*================================================================*/ 10 /* Automatically Generated by rdbHC.sh */ 11 /* - Do Not Edit - */ 12 /*================================================================*/ 13 #ifndef chip_reg_structs__H 14 #define chip_reg_structs__H 15 16 #ifdef BE_HOST 17 #define IS_BIG_ENDIAN (1) 18 #define IS_LITTLE_ENDIAN (0) 19 #else 20 #define IS_BIG_ENDIAN (0) 21 #define IS_LITTLE_ENDIAN (1) 22 #endif 23 24 /*-----------------------------------------------*/ 25 /* Structs for IEEE_PMA_PMD_BLK0 Bank */ 26 /*-----------------------------------------------*/ 27 typedef union { 28 uint32_t data; 29 struct { 30 #if IS_BIG_ENDIAN 31 uint32_t reserved : 16; 32 uint32_t reset : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[15] - SC */ 33 uint32_t reserved_14 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[14] - RSVD */ 34 uint32_t speed_selectionlsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[13] - WO */ 35 uint32_t reserved_12 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[12] - RSVD */ 36 uint32_t power_down : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[11] - WO */ 37 uint32_t reserved_07 : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[10:07] - RSVD */ 38 uint32_t speed_selectionmsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[06] - WO */ 39 uint32_t speed_selection : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[05:02] - WO */ 40 uint32_t pma_remote_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[01] - WO */ 41 uint32_t pma_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[00] - WO */ 42 #endif /* IS_BIG_ENDIAN */ 43 #if IS_LITTLE_ENDIAN 44 uint32_t pma_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[00] - WO */ 45 uint32_t pma_remote_loopback : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[01] - WO */ 46 uint32_t speed_selection : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[05:02] - WO */ 47 uint32_t speed_selectionmsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[06] - WO */ 48 uint32_t reserved_07 : 4; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[10:07] - RSVD */ 49 uint32_t power_down : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[11] - WO */ 50 uint32_t reserved_12 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[12] - RSVD */ 51 uint32_t speed_selectionlsb : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[13] - WO */ 52 uint32_t reserved_14 : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[14] - RSVD */ 53 uint32_t reset : 1; /* IEEE_PMA_PMD_BLK0_pmd_control_register_t[15] - SC */ 54 uint32_t reserved : 16; 55 #endif /* IS_LITTLE_ENDIAN */ 56 } fields; 57 } IEEE_PMA_PMD_BLK0_pmd_control_register_t; 58 59 typedef IEEE_PMA_PMD_BLK0_pmd_control_register_t IEEE_PMA_PMD_BLK0_PMD_CONTROL_REGISTER_t; 60 61 typedef union { 62 uint32_t data; 63 struct { 64 #if IS_BIG_ENDIAN 65 uint32_t reserved : 16; 66 uint32_t reserved_08 : 8; /* IEEE_PMA_PMD_BLK0_status_register_t[15:08] - RSVD */ 67 uint32_t fault : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[07] - RO */ 68 uint32_t reserved_03 : 4; /* IEEE_PMA_PMD_BLK0_status_register_t[06:03] - RSVD */ 69 uint32_t receive_link_status : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[02] - LL */ 70 uint32_t low_power_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[01] - RO */ 71 uint32_t reserved_00 : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[00] - RSVD */ 72 #endif /* IS_BIG_ENDIAN */ 73 #if IS_LITTLE_ENDIAN 74 uint32_t reserved_00 : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[00] - RSVD */ 75 uint32_t low_power_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[01] - RO */ 76 uint32_t receive_link_status : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[02] - LL */ 77 uint32_t reserved_03 : 4; /* IEEE_PMA_PMD_BLK0_status_register_t[06:03] - RSVD */ 78 uint32_t fault : 1; /* IEEE_PMA_PMD_BLK0_status_register_t[07] - RO */ 79 uint32_t reserved_08 : 8; /* IEEE_PMA_PMD_BLK0_status_register_t[15:08] - RSVD */ 80 uint32_t reserved : 16; 81 #endif /* IS_LITTLE_ENDIAN */ 82 } fields; 83 } IEEE_PMA_PMD_BLK0_status_register_t; 84 85 typedef IEEE_PMA_PMD_BLK0_status_register_t IEEE_PMA_PMD_BLK0_STATUS_REGISTER_t; 86 87 typedef union { 88 uint32_t data; 89 struct { 90 #if IS_BIG_ENDIAN 91 uint32_t reserved : 16; 92 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_t[15:00] - RO */ 93 #endif /* IS_BIG_ENDIAN */ 94 #if IS_LITTLE_ENDIAN 95 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_t[15:00] - RO */ 96 uint32_t reserved : 16; 97 #endif /* IS_LITTLE_ENDIAN */ 98 } fields; 99 } IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_t; 100 101 typedef IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_t IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_0_t; 102 103 typedef union { 104 uint32_t data; 105 struct { 106 #if IS_BIG_ENDIAN 107 uint32_t reserved : 16; 108 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_t[15:00] - RO */ 109 #endif /* IS_BIG_ENDIAN */ 110 #if IS_LITTLE_ENDIAN 111 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_t[15:00] - RO */ 112 uint32_t reserved : 16; 113 #endif /* IS_LITTLE_ENDIAN */ 114 } fields; 115 } IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_t; 116 117 typedef IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_t IEEE_PMA_PMD_BLK0_PMD_IDENTIFIER_REGISTER_1_t; 118 119 typedef union { 120 uint32_t data; 121 struct { 122 #if IS_BIG_ENDIAN 123 uint32_t reserved : 16; 124 uint32_t reserved_10 : 6; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[15:10] - RSVD */ 125 uint32_t one_hundredg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[09] - RO */ 126 uint32_t fortyg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[08] - RO */ 127 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[07:05] - RSVD */ 128 uint32_t oneg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[04] - RO */ 129 uint32_t reserved_01 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[03:01] - RSVD */ 130 uint32_t teng_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[00] - RO */ 131 #endif /* IS_BIG_ENDIAN */ 132 #if IS_LITTLE_ENDIAN 133 uint32_t teng_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[00] - RO */ 134 uint32_t reserved_01 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[03:01] - RSVD */ 135 uint32_t oneg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[04] - RO */ 136 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[07:05] - RSVD */ 137 uint32_t fortyg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[08] - RO */ 138 uint32_t one_hundredg_capable : 1; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[09] - RO */ 139 uint32_t reserved_10 : 6; /* IEEE_PMA_PMD_BLK0_pmd_speed_ability_t[15:10] - RSVD */ 140 uint32_t reserved : 16; 141 #endif /* IS_LITTLE_ENDIAN */ 142 } fields; 143 } IEEE_PMA_PMD_BLK0_pmd_speed_ability_t; 144 145 typedef IEEE_PMA_PMD_BLK0_pmd_speed_ability_t IEEE_PMA_PMD_BLK0_PMD_SPEED_ABILITY_t; 146 147 typedef union { 148 uint32_t data; 149 struct { 150 #if IS_BIG_ENDIAN 151 uint32_t reserved : 16; 152 uint32_t reserved_12 : 4; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[15:12] - RSVD */ 153 uint32_t seperate_pma_4_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[11] - RO */ 154 uint32_t seperate_pma_3_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[10] - RO */ 155 uint32_t seperate_pma_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[09] - RO */ 156 uint32_t seperate_pma_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[08] - RO */ 157 uint32_t an_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[07] - RO */ 158 uint32_t tc_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[06] - RO */ 159 uint32_t dte_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[05] - RO */ 160 uint32_t phy_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[04] - RO */ 161 uint32_t pcs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[03] - RO */ 162 uint32_t wis_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[02] - RO */ 163 uint32_t pmd_pma_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[01] - RO */ 164 uint32_t clause_22registers_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[00] - RO */ 165 #endif /* IS_BIG_ENDIAN */ 166 #if IS_LITTLE_ENDIAN 167 uint32_t clause_22registers_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[00] - RO */ 168 uint32_t pmd_pma_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[01] - RO */ 169 uint32_t wis_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[02] - RO */ 170 uint32_t pcs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[03] - RO */ 171 uint32_t phy_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[04] - RO */ 172 uint32_t dte_xs_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[05] - RO */ 173 uint32_t tc_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[06] - RO */ 174 uint32_t an_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[07] - RO */ 175 uint32_t seperate_pma_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[08] - RO */ 176 uint32_t seperate_pma_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[09] - RO */ 177 uint32_t seperate_pma_3_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[10] - RO */ 178 uint32_t seperate_pma_4_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[11] - RO */ 179 uint32_t reserved_12 : 4; /* IEEE_PMA_PMD_BLK0_devices_in_package_1_t[15:12] - RSVD */ 180 uint32_t reserved : 16; 181 #endif /* IS_LITTLE_ENDIAN */ 182 } fields; 183 } IEEE_PMA_PMD_BLK0_devices_in_package_1_t; 184 185 typedef IEEE_PMA_PMD_BLK0_devices_in_package_1_t IEEE_PMA_PMD_BLK0_DEVICES_IN_PACKAGE_1_t; 186 187 typedef union { 188 uint32_t data; 189 struct { 190 #if IS_BIG_ENDIAN 191 uint32_t reserved : 16; 192 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[15] - RO */ 193 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[14] - RO */ 194 uint32_t clause_22extension_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[13] - RO */ 195 uint32_t reserved_00 : 13; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[12:00] - RSVD */ 196 #endif /* IS_BIG_ENDIAN */ 197 #if IS_LITTLE_ENDIAN 198 uint32_t reserved_00 : 13; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[12:00] - RSVD */ 199 uint32_t clause_22extension_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[13] - RO */ 200 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[14] - RO */ 201 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_PMA_PMD_BLK0_devices_in_package_2_t[15] - RO */ 202 uint32_t reserved : 16; 203 #endif /* IS_LITTLE_ENDIAN */ 204 } fields; 205 } IEEE_PMA_PMD_BLK0_devices_in_package_2_t; 206 207 typedef IEEE_PMA_PMD_BLK0_devices_in_package_2_t IEEE_PMA_PMD_BLK0_DEVICES_IN_PACKAGE_2_t; 208 209 typedef union { 210 uint32_t data; 211 struct { 212 #if IS_BIG_ENDIAN 213 uint32_t reserved : 16; 214 uint32_t reserved_06 : 10; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_t[15:06] - RSVD */ 215 uint32_t pma_typeselection : 6; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_t[05:00] - WO */ 216 #endif /* IS_BIG_ENDIAN */ 217 #if IS_LITTLE_ENDIAN 218 uint32_t pma_typeselection : 6; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_t[05:00] - WO */ 219 uint32_t reserved_06 : 10; /* IEEE_PMA_PMD_BLK0_pmd_control_2_register_t[15:06] - RSVD */ 220 uint32_t reserved : 16; 221 #endif /* IS_LITTLE_ENDIAN */ 222 } fields; 223 } IEEE_PMA_PMD_BLK0_pmd_control_2_register_t; 224 225 typedef IEEE_PMA_PMD_BLK0_pmd_control_2_register_t IEEE_PMA_PMD_BLK0_PMD_CONTROL_2_REGISTER_t; 226 227 typedef union { 228 uint32_t data; 229 struct { 230 #if IS_BIG_ENDIAN 231 uint32_t reserved : 16; 232 uint32_t device_present : 2; /* IEEE_PMA_PMD_BLK0_status_register_2_t[15:14] - RO */ 233 uint32_t transmit_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[13] - RO */ 234 uint32_t receive_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[12] - RO */ 235 uint32_t transmit_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[11] - LH */ 236 uint32_t receive_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[10] - LH */ 237 uint32_t extended_abilities : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[09] - RO */ 238 uint32_t pmd_transmitdisable_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[08] - RO */ 239 uint32_t tengbase_sr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[07] - RO */ 240 uint32_t tengbase_lr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[06] - RO */ 241 uint32_t tengbase_er_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[05] - RO */ 242 uint32_t tengbase_lx4_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[04] - RO */ 243 uint32_t tengbase_sw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[03] - RO */ 244 uint32_t tengbase_lw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[02] - RO */ 245 uint32_t tengbase_ew_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[01] - RO */ 246 uint32_t pma_local_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[00] - RO */ 247 #endif /* IS_BIG_ENDIAN */ 248 #if IS_LITTLE_ENDIAN 249 uint32_t pma_local_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[00] - RO */ 250 uint32_t tengbase_ew_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[01] - RO */ 251 uint32_t tengbase_lw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[02] - RO */ 252 uint32_t tengbase_sw_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[03] - RO */ 253 uint32_t tengbase_lx4_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[04] - RO */ 254 uint32_t tengbase_er_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[05] - RO */ 255 uint32_t tengbase_lr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[06] - RO */ 256 uint32_t tengbase_sr_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[07] - RO */ 257 uint32_t pmd_transmitdisable_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[08] - RO */ 258 uint32_t extended_abilities : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[09] - RO */ 259 uint32_t receive_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[10] - LH */ 260 uint32_t transmit_localfault : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[11] - LH */ 261 uint32_t receive_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[12] - RO */ 262 uint32_t transmit_localfault_ability : 1; /* IEEE_PMA_PMD_BLK0_status_register_2_t[13] - RO */ 263 uint32_t device_present : 2; /* IEEE_PMA_PMD_BLK0_status_register_2_t[15:14] - RO */ 264 uint32_t reserved : 16; 265 #endif /* IS_LITTLE_ENDIAN */ 266 } fields; 267 } IEEE_PMA_PMD_BLK0_status_register_2_t; 268 269 typedef IEEE_PMA_PMD_BLK0_status_register_2_t IEEE_PMA_PMD_BLK0_STATUS_REGISTER_2_t; 270 271 typedef union { 272 uint32_t data; 273 struct { 274 #if IS_BIG_ENDIAN 275 uint32_t reserved : 16; 276 uint32_t reserved_05 : 11; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[15:05] - RSVD */ 277 uint32_t pmd_transmitdisable_0 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[04] - WO */ 278 uint32_t pmd_transmitdisable_1 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[03] - WO */ 279 uint32_t pmd_transmitdisable_2 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[02] - WO */ 280 uint32_t pmd_transmitdisable_3 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[01] - WO */ 281 uint32_t global_pmdtransmit_disable : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[00] - WO */ 282 #endif /* IS_BIG_ENDIAN */ 283 #if IS_LITTLE_ENDIAN 284 uint32_t global_pmdtransmit_disable : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[00] - WO */ 285 uint32_t pmd_transmitdisable_3 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[01] - WO */ 286 uint32_t pmd_transmitdisable_2 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[02] - WO */ 287 uint32_t pmd_transmitdisable_1 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[03] - WO */ 288 uint32_t pmd_transmitdisable_0 : 1; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[04] - WO */ 289 uint32_t reserved_05 : 11; /* IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t[15:05] - RSVD */ 290 uint32_t reserved : 16; 291 #endif /* IS_LITTLE_ENDIAN */ 292 } fields; 293 } IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t; 294 295 typedef IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_t IEEE_PMA_PMD_BLK0_PMD_TRANSMIT_DISABLE_REGISTER_t; 296 297 typedef union { 298 uint32_t data; 299 struct { 300 #if IS_BIG_ENDIAN 301 uint32_t reserved : 16; 302 uint32_t reserved_05 : 11; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[15:05] - RSVD */ 303 uint32_t pmd_receivesignal_detect_0 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[04] - RO */ 304 uint32_t pmd_receivesignal_detect_1 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[03] - RO */ 305 uint32_t pmd_receivesignal_detect_2 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[02] - RO */ 306 uint32_t pmd_receivesignal_detect_3 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[01] - RO */ 307 uint32_t global_pmdreceive_signal_ok : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[00] - RO */ 308 #endif /* IS_BIG_ENDIAN */ 309 #if IS_LITTLE_ENDIAN 310 uint32_t global_pmdreceive_signal_ok : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[00] - RO */ 311 uint32_t pmd_receivesignal_detect_3 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[01] - RO */ 312 uint32_t pmd_receivesignal_detect_2 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[02] - RO */ 313 uint32_t pmd_receivesignal_detect_1 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[03] - RO */ 314 uint32_t pmd_receivesignal_detect_0 : 1; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[04] - RO */ 315 uint32_t reserved_05 : 11; /* IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t[15:05] - RSVD */ 316 uint32_t reserved : 16; 317 #endif /* IS_LITTLE_ENDIAN */ 318 } fields; 319 } IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t; 320 321 typedef IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_t IEEE_PMA_PMD_BLK0_PMD_RECEIVE_SIGNAL_DETECT_REGISTER_t; 322 323 typedef union { 324 uint32_t data; 325 struct { 326 #if IS_BIG_ENDIAN 327 uint32_t reserved : 16; 328 uint32_t reserved_11 : 5; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[15:11] - RSVD */ 329 uint32_t fortygbase_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[10] - RO */ 330 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[09] - RSVD */ 331 uint32_t tenbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[08] - RO */ 332 uint32_t hundredbase_tx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[07] - RO */ 333 uint32_t gigbase_kx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[06] - RO */ 334 uint32_t gigbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[05] - RO */ 335 uint32_t tengbase_kr_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[04] - RO */ 336 uint32_t tengbase_kx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[03] - RO */ 337 uint32_t tengbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[02] - RO */ 338 uint32_t tengbase_lrm_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[01] - RO */ 339 uint32_t tengbase_cx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[00] - RO */ 340 #endif /* IS_BIG_ENDIAN */ 341 #if IS_LITTLE_ENDIAN 342 uint32_t tengbase_cx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[00] - RO */ 343 uint32_t tengbase_lrm_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[01] - RO */ 344 uint32_t tengbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[02] - RO */ 345 uint32_t tengbase_kx4_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[03] - RO */ 346 uint32_t tengbase_kr_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[04] - RO */ 347 uint32_t gigbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[05] - RO */ 348 uint32_t gigbase_kx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[06] - RO */ 349 uint32_t hundredbase_tx_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[07] - RO */ 350 uint32_t tenbase_t_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[08] - RO */ 351 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[09] - RSVD */ 352 uint32_t fortygbase_ability : 1; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[10] - RO */ 353 uint32_t reserved_11 : 5; /* IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t[15:11] - RSVD */ 354 uint32_t reserved : 16; 355 #endif /* IS_LITTLE_ENDIAN */ 356 } fields; 357 } IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t; 358 359 typedef IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_t IEEE_PMA_PMD_BLK0_PMD_EXTENDED_ABILITY_REGISTER_t; 360 361 /*-----------------------------------------------*/ 362 /* Structs for FUR_M0ACCESS_ADDR Bank master: */ 363 /*-----------------------------------------------*/ 364 365 typedef union { 366 uint32_t data; 367 struct { 368 #if IS_BIG_ENDIAN 369 uint32_t reserved : 16; 370 uint32_t reserved_13 : 3; /* FUR_M0ACCESS_ADDR_master_dram_mem_add_TYPE[15:13] - RSVD */ 371 uint32_t mst_dram_mem_add : 13; /* FUR_M0ACCESS_ADDR_master_dram_mem_add_TYPE[12:00] - WO */ 372 #endif /* IS_BIG_ENDIAN */ 373 #if IS_LITTLE_ENDIAN 374 uint32_t mst_dram_mem_add : 13; /* FUR_M0ACCESS_ADDR_master_dram_mem_add_TYPE[12:00] - WO */ 375 uint32_t reserved_13 : 3; /* FUR_M0ACCESS_ADDR_master_dram_mem_add_TYPE[15:13] - RSVD */ 376 uint32_t reserved : 16; 377 #endif /* IS_LITTLE_ENDIAN */ 378 } fields; 379 } FUR_M0ACCESS_ADDR_master_dram_mem_add_TYPE; 380 381 typedef FUR_M0ACCESS_ADDR_master_dram_mem_add_TYPE FUR_M0ACCESS_ADDR_MASTER_DRAM_MEM_ADD_TYPE_T; 382 /* FUR_M0ACCSS_DATA register */ 383 typedef union { 384 uint32_t data; 385 struct { 386 #if IS_BIG_ENDIAN 387 uint32_t reserved : 16; 388 uint32_t mst_dram_rdata : 16; /* FUR_M0ACCESS_DATA_master_dram_rdata_TYPE[15:00] - RO */ 389 #endif /* IS_BIG_ENDIAN */ 390 #if IS_LITTLE_ENDIAN 391 uint32_t mst_dram_rdata : 16; /* FUR_M0ACCESS_DATA_master_dram_rdata_TYPE[15:00] - RO */ 392 uint32_t reserved : 16; 393 #endif /* IS_LITTLE_ENDIAN */ 394 } fields; 395 } FUR_M0ACCESS_DATA_master_dram_rdata_TYPE; 396 397 typedef FUR_M0ACCESS_DATA_master_dram_rdata_TYPE FUR_M0ACCESS_DATA_MASTER_DRAM_RDATA_TYPE_T; 398 399 400 /*-----------------------------------------------*/ 401 /* Structs for FUR_M0ACCESS_DATA Bank Master */ 402 /*-----------------------------------------------*/ 403 404 typedef union { 405 uint32_t data; 406 struct { 407 #if IS_BIG_ENDIAN 408 uint32_t reserved : 16; 409 uint32_t mst_dram_wdata : 16; /* FUR_M0ACCESS_DATA_master_dram_wdata_TYPE[15:00] - WO */ 410 #endif /* IS_BIG_ENDIAN */ 411 #if IS_LITTLE_ENDIAN 412 uint32_t mst_dram_wdata : 16; /* FUR_M0ACCESS_DATA_master_dram_wdata_TYPE[15:00] - WO */ 413 uint32_t reserved : 16; 414 #endif /* IS_LITTLE_ENDIAN */ 415 } fields; 416 } FUR_M0ACCESS_DATA_master_dram_wdata_TYPE; 417 418 typedef FUR_M0ACCESS_DATA_master_dram_wdata_TYPE FUR_M0ACCESS_DATA_MASTER_DRAM_WDATA_TYPE_T; 419 /*-----------------------------------------------*/ 420 /* Structs for FUR_M0ACCESS_ADDR Bank SLAVE: */ 421 /*-----------------------------------------------*/ 422 423 typedef union { 424 uint32_t data; 425 struct { 426 #if IS_BIG_ENDIAN 427 uint32_t reserved : 16; 428 uint32_t reserved_13 : 3; /* FUR_M0ACCESS_ADDR_slave_dram_mem_add_TYPE[15:13] - RSVD */ 429 uint32_t slv_dram_mem_add : 13; /* FUR_M0ACCESS_ADDR_slave_dram_mem_add_TYPE[12:00] - WO */ 430 #endif /* IS_BIG_ENDIAN */ 431 #if IS_LITTLE_ENDIAN 432 uint32_t slv_dram_mem_add : 13; /* FUR_M0ACCESS_ADDR_slave_dram_mem_add_TYPE[12:00] - WO */ 433 uint32_t reserved_13 : 3; /* FUR_M0ACCESS_ADDR_slave_dram_mem_add_TYPE[15:13] - RSVD */ 434 uint32_t reserved : 16; 435 #endif /* IS_LITTLE_ENDIAN */ 436 } fields; 437 } FUR_M0ACCESS_ADDR_slave_dram_mem_add_TYPE; 438 439 typedef FUR_M0ACCESS_ADDR_slave_dram_mem_add_TYPE FUR_M0ACCESS_ADDR_SLAVE_DRAM_MEM_ADD_TYPE_T; 440 /* FUR_M0ACCSS_DATA register SLAVE */ 441 typedef union { 442 uint32_t data; 443 struct { 444 #if IS_BIG_ENDIAN 445 uint32_t reserved : 16; 446 uint32_t slv_dram_rdata : 16; /* FUR_M0ACCESS_DATA_slave_dram_rdata_TYPE[15:00] - RO */ 447 #endif /* IS_BIG_ENDIAN */ 448 #if IS_LITTLE_ENDIAN 449 uint32_t slv_dram_rdata : 16; /* FUR_M0ACCESS_DATA_slave_dram_rdata_TYPE[15:00] - RO */ 450 uint32_t reserved : 16; 451 #endif /* IS_LITTLE_ENDIAN */ 452 } fields; 453 } FUR_M0ACCESS_DATA_slave_dram_rdata_TYPE; 454 455 typedef FUR_M0ACCESS_DATA_slave_dram_rdata_TYPE FUR_M0ACCESS_DATA_SLAVE_DRAM_RDATA_TYPE_T; 456 457 458 /*-----------------------------------------------*/ 459 /* Structs for FUR_M0ACCESS_DATA Bank slave */ 460 /*-----------------------------------------------*/ 461 462 typedef union { 463 uint32_t data; 464 struct { 465 #if IS_BIG_ENDIAN 466 uint32_t reserved : 16; 467 uint32_t slv_dram_wdata : 16; /* FUR_M0ACCESS_DATA_slave_dram_wdata_TYPE[15:00] - WO */ 468 #endif /* IS_BIG_ENDIAN */ 469 #if IS_LITTLE_ENDIAN 470 uint32_t slv_dram_wdata : 16; /* FUR_M0ACCESS_DATA_slave_dram_wdata_TYPE[15:00] - WO */ 471 uint32_t reserved : 16; 472 #endif /* IS_LITTLE_ENDIAN */ 473 } fields; 474 } FUR_M0ACCESS_DATA_slave_dram_wdata_TYPE; 475 476 typedef FUR_M0ACCESS_DATA_slave_dram_wdata_TYPE FUR_M0ACCESS_DATA_SLAVE_DRAM_WDATA_TYPE_T; 477 478 typedef union { 479 uint32_t data; 480 struct { 481 #if IS_BIG_ENDIAN 482 uint32_t reserved : 16; 483 uint32_t pma_remote_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[15] - RO */ 484 uint32_t one_hundredgbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[14] - RO */ 485 uint32_t one_hundredgbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[13] - RO */ 486 uint32_t one_hundredgbase_kp4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[12] - RO */ 487 uint32_t one_hundredgbase_er4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[11] - RO */ 488 uint32_t one_hundredgbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[10] - RO */ 489 uint32_t one_hundredgbase_sr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[09] - RO */ 490 uint32_t one_hundredgbase_cr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[08] - RO */ 491 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[07:05] - RSVD */ 492 uint32_t fortygbase_fr_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[04] - RO */ 493 uint32_t fortygbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[03] - RO */ 494 uint32_t fortygbase_sr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[02] - RO */ 495 uint32_t fortygbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[01] - RO */ 496 uint32_t fortygbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[00] - RO */ 497 #endif /* IS_BIG_ENDIAN */ 498 #if IS_LITTLE_ENDIAN 499 uint32_t fortygbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[00] - RO */ 500 uint32_t fortygbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[01] - RO */ 501 uint32_t fortygbase_sr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[02] - RO */ 502 uint32_t fortygbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[03] - RO */ 503 uint32_t fortygbase_fr_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[04] - RO */ 504 uint32_t reserved_05 : 3; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[07:05] - RSVD */ 505 uint32_t one_hundredgbase_cr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[08] - RO */ 506 uint32_t one_hundredgbase_sr10_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[09] - RO */ 507 uint32_t one_hundredgbase_lr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[10] - RO */ 508 uint32_t one_hundredgbase_er4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[11] - RO */ 509 uint32_t one_hundredgbase_kp4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[12] - RO */ 510 uint32_t one_hundredgbase_kr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[13] - RO */ 511 uint32_t one_hundredgbase_cr4_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[14] - RO */ 512 uint32_t pma_remote_loopback_ability : 1; /* IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t[15] - RO */ 513 uint32_t reserved : 16; 514 #endif /* IS_LITTLE_ENDIAN */ 515 } fields; 516 } IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t; 517 518 typedef IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_t IEEE_PMA_PMD_BLK0_FORTYG_PMD_EXTENDED_ABILITY_REGISTER_t; 519 520 typedef union { 521 uint32_t data; 522 struct { 523 #if IS_BIG_ENDIAN 524 uint32_t reserved : 16; 525 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_t[15:00] - RO */ 526 #endif /* IS_BIG_ENDIAN */ 527 #if IS_LITTLE_ENDIAN 528 uint32_t device_id_0 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_t[15:00] - RO */ 529 uint32_t reserved : 16; 530 #endif /* IS_LITTLE_ENDIAN */ 531 } fields; 532 } IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_t; 533 534 typedef IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_t IEEE_PMA_PMD_BLK0_PMD_OUI_ID0_REGISTER_t; 535 536 typedef union { 537 uint32_t data; 538 struct { 539 #if IS_BIG_ENDIAN 540 uint32_t reserved : 16; 541 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_t[15:00] - RO */ 542 #endif /* IS_BIG_ENDIAN */ 543 #if IS_LITTLE_ENDIAN 544 uint32_t device_id_1 : 16; /* IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_t[15:00] - RO */ 545 uint32_t reserved : 16; 546 #endif /* IS_LITTLE_ENDIAN */ 547 } fields; 548 } IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_t; 549 550 typedef IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_t IEEE_PMA_PMD_BLK0_PMD_OUI_ID1_REG_t; 551 552 553 /*-----------------------------------------------*/ 554 /* Structs for CL93n72_IEEE_TX Bank */ 555 /*-----------------------------------------------*/ 556 typedef union { 557 uint32_t data; 558 struct { 559 #if IS_BIG_ENDIAN 560 uint32_t reserved : 16; 561 uint32_t reserved_02 : 14; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t[15:02] - RSVD */ 562 uint32_t cl93n72_ieee_training_enable : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t[01] - RW */ 563 uint32_t cl93n72_ieee_restart_training : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t[00] - SC */ 564 #endif /* IS_BIG_ENDIAN */ 565 #if IS_LITTLE_ENDIAN 566 uint32_t cl93n72_ieee_restart_training : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t[00] - SC */ 567 uint32_t cl93n72_ieee_training_enable : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t[01] - RW */ 568 uint32_t reserved_02 : 14; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t[15:02] - RSVD */ 569 uint32_t reserved : 16; 570 #endif /* IS_LITTLE_ENDIAN */ 571 } fields; 572 } CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t; 573 574 typedef CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150_t; 575 576 typedef union { 577 uint32_t data; 578 struct { 579 #if IS_BIG_ENDIAN 580 uint32_t reserved : 16; 581 uint32_t reserved_04 : 12; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[15:04] - RSVD */ 582 uint32_t cl93n72_ieee_training_failure : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[03] - RO */ 583 uint32_t cl93n72_ieee_training_status : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[02] - RO */ 584 uint32_t cl93n72_ieee_frame_lock : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[01] - RO */ 585 uint32_t cl93n72_ieee_receiver_status : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[00] - RO */ 586 #endif /* IS_BIG_ENDIAN */ 587 #if IS_LITTLE_ENDIAN 588 uint32_t cl93n72_ieee_receiver_status : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[00] - RO */ 589 uint32_t cl93n72_ieee_frame_lock : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[01] - RO */ 590 uint32_t cl93n72_ieee_training_status : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[02] - RO */ 591 uint32_t cl93n72_ieee_training_failure : 1; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[03] - RO */ 592 uint32_t reserved_04 : 12; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t[15:04] - RSVD */ 593 uint32_t reserved : 16; 594 #endif /* IS_LITTLE_ENDIAN */ 595 } fields; 596 } CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t; 597 598 typedef CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151_t; 599 600 typedef union { 601 uint32_t data; 602 struct { 603 #if IS_BIG_ENDIAN 604 uint32_t reserved : 16; 605 uint32_t cl93n72_ieee_ld_coeff_update : 16; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_t[15:00] - RO */ 606 #endif /* IS_BIG_ENDIAN */ 607 #if IS_LITTLE_ENDIAN 608 uint32_t cl93n72_ieee_ld_coeff_update : 16; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_t[15:00] - RO */ 609 uint32_t reserved : 16; 610 #endif /* IS_LITTLE_ENDIAN */ 611 } fields; 612 } CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_t; 613 614 typedef CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154_t; 615 616 typedef union { 617 uint32_t data; 618 struct { 619 #if IS_BIG_ENDIAN 620 uint32_t reserved : 16; 621 uint32_t cl93n72_ieee_ld_status_report : 16; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_t[15:00] - RO */ 622 #endif /* IS_BIG_ENDIAN */ 623 #if IS_LITTLE_ENDIAN 624 uint32_t cl93n72_ieee_ld_status_report : 16; /* CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_t[15:00] - RO */ 625 uint32_t reserved : 16; 626 #endif /* IS_LITTLE_ENDIAN */ 627 } fields; 628 } CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_t; 629 630 typedef CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_t CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155_t; 631 632 633 /*-----------------------------------------------*/ 634 /* Structs for CL93n72_IEEE_RX Bank */ 635 /*-----------------------------------------------*/ 636 typedef union { 637 uint32_t data; 638 struct { 639 #if IS_BIG_ENDIAN 640 uint32_t reserved : 16; 641 uint32_t cl93n72_ieee_lp_coeff_update : 16; /* CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_t[15:00] - RO */ 642 #endif /* IS_BIG_ENDIAN */ 643 #if IS_LITTLE_ENDIAN 644 uint32_t cl93n72_ieee_lp_coeff_update : 16; /* CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_t[15:00] - RO */ 645 uint32_t reserved : 16; 646 #endif /* IS_LITTLE_ENDIAN */ 647 } fields; 648 } CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_t; 649 650 typedef CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_t CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152_t; 651 652 typedef union { 653 uint32_t data; 654 struct { 655 #if IS_BIG_ENDIAN 656 uint32_t reserved : 16; 657 uint32_t cl93n72_ieee_lp_status_report : 16; /* CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_t[15:00] - RO */ 658 #endif /* IS_BIG_ENDIAN */ 659 #if IS_LITTLE_ENDIAN 660 uint32_t cl93n72_ieee_lp_status_report : 16; /* CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_t[15:00] - RO */ 661 uint32_t reserved : 16; 662 #endif /* IS_LITTLE_ENDIAN */ 663 } fields; 664 } CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_t; 665 666 typedef CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_t CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153_t; 667 668 669 /*-----------------------------------------------*/ 670 /* Structs for IEEE_PMA_PMD_BLK10 Bank */ 671 /*-----------------------------------------------*/ 672 typedef union { 673 uint32_t data; 674 struct { 675 #if IS_BIG_ENDIAN 676 uint32_t reserved : 16; 677 uint32_t reserved_01 : 15; /* IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_t[15:01] - RSVD */ 678 uint32_t pmd_transmit_disable : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_t[00] - WO */ 679 #endif /* IS_BIG_ENDIAN */ 680 #if IS_LITTLE_ENDIAN 681 uint32_t pmd_transmit_disable : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_t[00] - WO */ 682 uint32_t reserved_01 : 15; /* IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_t[15:01] - RSVD */ 683 uint32_t reserved : 16; 684 #endif /* IS_LITTLE_ENDIAN */ 685 } fields; 686 } IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_t; 687 688 typedef IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_t IEEE_PMA_PMD_BLK10_TENGBASE_KX_CONTROL_REGISTER_t; 689 690 typedef union { 691 uint32_t data; 692 struct { 693 #if IS_BIG_ENDIAN 694 uint32_t reserved : 16; 695 uint32_t reserved_14 : 2; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[15:14] - RSVD */ 696 uint32_t transmit_faultability : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[13] - RO */ 697 uint32_t receive_faultability : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[12] - RO */ 698 uint32_t transmit_fault : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[11] - LH */ 699 uint32_t receive_fault : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[10] - LH */ 700 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[09] - RSVD */ 701 uint32_t pmd_transmitdisable_ability : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[08] - RO */ 702 uint32_t reserved_01 : 7; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[07:01] - RSVD */ 703 uint32_t signal_detectfrom_pmd : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[00] - RO */ 704 #endif /* IS_BIG_ENDIAN */ 705 #if IS_LITTLE_ENDIAN 706 uint32_t signal_detectfrom_pmd : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[00] - RO */ 707 uint32_t reserved_01 : 7; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[07:01] - RSVD */ 708 uint32_t pmd_transmitdisable_ability : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[08] - RO */ 709 uint32_t reserved_09 : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[09] - RSVD */ 710 uint32_t receive_fault : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[10] - LH */ 711 uint32_t transmit_fault : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[11] - LH */ 712 uint32_t receive_faultability : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[12] - RO */ 713 uint32_t transmit_faultability : 1; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[13] - RO */ 714 uint32_t reserved_14 : 2; /* IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t[15:14] - RSVD */ 715 uint32_t reserved : 16; 716 #endif /* IS_LITTLE_ENDIAN */ 717 } fields; 718 } IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t; 719 720 typedef IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_t IEEE_PMA_PMD_BLK10_TENGBASE_KX_STATUS_REGISTER_t; 721 722 723 /*-----------------------------------------------*/ 724 /* Structs for IEEE_CL91_RX Bank */ 725 /*-----------------------------------------------*/ 726 typedef union { 727 uint32_t data; 728 struct { 729 #if IS_BIG_ENDIAN 730 uint32_t reserved : 16; 731 uint32_t reserved_02 : 14; /* IEEE_CL91_RX_fec_control_t[15:02] - RSVD */ 732 uint32_t fec_byp_ind_en : 1; /* IEEE_CL91_RX_fec_control_t[01] - WO */ 733 uint32_t fec_byp_corr_en : 1; /* IEEE_CL91_RX_fec_control_t[00] - WO */ 734 #endif /* IS_BIG_ENDIAN */ 735 #if IS_LITTLE_ENDIAN 736 uint32_t fec_byp_corr_en : 1; /* IEEE_CL91_RX_fec_control_t[00] - WO */ 737 uint32_t fec_byp_ind_en : 1; /* IEEE_CL91_RX_fec_control_t[01] - WO */ 738 uint32_t reserved_02 : 14; /* IEEE_CL91_RX_fec_control_t[15:02] - RSVD */ 739 uint32_t reserved : 16; 740 #endif /* IS_LITTLE_ENDIAN */ 741 } fields; 742 } IEEE_CL91_RX_fec_control_t; 743 744 typedef IEEE_CL91_RX_fec_control_t IEEE_CL91_RX_FEC_CONTROL_t; 745 746 typedef union { 747 uint32_t data; 748 struct { 749 #if IS_BIG_ENDIAN 750 uint32_t reserved : 16; 751 uint32_t pcs_align_status : 1; /* IEEE_CL91_RX_fec_status_t[15] - RO */ 752 uint32_t fec_align_status : 1; /* IEEE_CL91_RX_fec_status_t[14] - RO */ 753 uint32_t reserved_03 : 11; /* IEEE_CL91_RX_fec_status_t[13:03] - RSVD */ 754 uint32_t high_ser : 1; /* IEEE_CL91_RX_fec_status_t[02] - RO */ 755 uint32_t fec_byp_ind_ability : 1; /* IEEE_CL91_RX_fec_status_t[01] - RO */ 756 uint32_t fec_byp_corr_ability : 1; /* IEEE_CL91_RX_fec_status_t[00] - RO */ 757 #endif /* IS_BIG_ENDIAN */ 758 #if IS_LITTLE_ENDIAN 759 uint32_t fec_byp_corr_ability : 1; /* IEEE_CL91_RX_fec_status_t[00] - RO */ 760 uint32_t fec_byp_ind_ability : 1; /* IEEE_CL91_RX_fec_status_t[01] - RO */ 761 uint32_t high_ser : 1; /* IEEE_CL91_RX_fec_status_t[02] - RO */ 762 uint32_t reserved_03 : 11; /* IEEE_CL91_RX_fec_status_t[13:03] - RSVD */ 763 uint32_t fec_align_status : 1; /* IEEE_CL91_RX_fec_status_t[14] - RO */ 764 uint32_t pcs_align_status : 1; /* IEEE_CL91_RX_fec_status_t[15] - RO */ 765 uint32_t reserved : 16; 766 #endif /* IS_LITTLE_ENDIAN */ 767 } fields; 768 } IEEE_CL91_RX_fec_status_t; 769 770 typedef IEEE_CL91_RX_fec_status_t IEEE_CL91_RX_FEC_STATUS_t; 771 772 typedef union { 773 uint32_t data; 774 struct { 775 #if IS_BIG_ENDIAN 776 uint32_t reserved : 16; 777 uint32_t fec_corr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_t[15:00] - RO */ 778 #endif /* IS_BIG_ENDIAN */ 779 #if IS_LITTLE_ENDIAN 780 uint32_t fec_corr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_t[15:00] - RO */ 781 uint32_t reserved : 16; 782 #endif /* IS_LITTLE_ENDIAN */ 783 } fields; 784 } IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_t; 785 786 typedef IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_t IEEE_CL91_RX_FEC_CORR_CW_CNT_LOWER_REG_t; 787 788 typedef union { 789 uint32_t data; 790 struct { 791 #if IS_BIG_ENDIAN 792 uint32_t reserved : 16; 793 uint32_t fec_corr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_t[15:00] - RO */ 794 #endif /* IS_BIG_ENDIAN */ 795 #if IS_LITTLE_ENDIAN 796 uint32_t fec_corr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_t[15:00] - RO */ 797 uint32_t reserved : 16; 798 #endif /* IS_LITTLE_ENDIAN */ 799 } fields; 800 } IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_t; 801 802 typedef IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_t IEEE_CL91_RX_FEC_CORR_CW_CNT_UPPER_REG_t; 803 804 typedef union { 805 uint32_t data; 806 struct { 807 #if IS_BIG_ENDIAN 808 uint32_t reserved : 16; 809 uint32_t fec_uncorr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_t[15:00] - RO */ 810 #endif /* IS_BIG_ENDIAN */ 811 #if IS_LITTLE_ENDIAN 812 uint32_t fec_uncorr_cw_cnt_lower : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_t[15:00] - RO */ 813 uint32_t reserved : 16; 814 #endif /* IS_LITTLE_ENDIAN */ 815 } fields; 816 } IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_t; 817 818 typedef IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_t IEEE_CL91_RX_FEC_UNCORR_CW_CNT_LOWER_REG_t; 819 820 typedef union { 821 uint32_t data; 822 struct { 823 #if IS_BIG_ENDIAN 824 uint32_t reserved : 16; 825 uint32_t fec_uncorr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_t[15:00] - RO */ 826 #endif /* IS_BIG_ENDIAN */ 827 #if IS_LITTLE_ENDIAN 828 uint32_t fec_uncorr_cw_cnt_upper : 16; /* IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_t[15:00] - RO */ 829 uint32_t reserved : 16; 830 #endif /* IS_LITTLE_ENDIAN */ 831 } fields; 832 } IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_t; 833 834 typedef IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_t IEEE_CL91_RX_FEC_UNCORR_CW_CNT_UPPER_REG_t; 835 836 typedef union { 837 uint32_t data; 838 struct { 839 #if IS_BIG_ENDIAN 840 uint32_t reserved : 16; 841 uint32_t reserved_08 : 8; /* IEEE_CL91_RX_fec_lane_mapping_t[15:08] - RSVD */ 842 uint32_t fec_lane_0_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[07:06] - RO */ 843 uint32_t fec_lane_1_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[05:04] - RO */ 844 uint32_t fec_lane_2_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[03:02] - RO */ 845 uint32_t fec_lane_3_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[01:00] - RO */ 846 #endif /* IS_BIG_ENDIAN */ 847 #if IS_LITTLE_ENDIAN 848 uint32_t fec_lane_3_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[01:00] - RO */ 849 uint32_t fec_lane_2_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[03:02] - RO */ 850 uint32_t fec_lane_1_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[05:04] - RO */ 851 uint32_t fec_lane_0_mapping : 2; /* IEEE_CL91_RX_fec_lane_mapping_t[07:06] - RO */ 852 uint32_t reserved_08 : 8; /* IEEE_CL91_RX_fec_lane_mapping_t[15:08] - RSVD */ 853 uint32_t reserved : 16; 854 #endif /* IS_LITTLE_ENDIAN */ 855 } fields; 856 } IEEE_CL91_RX_fec_lane_mapping_t; 857 858 typedef IEEE_CL91_RX_fec_lane_mapping_t IEEE_CL91_RX_FEC_LANE_MAPPING_t; 859 860 typedef union { 861 uint32_t data; 862 struct { 863 #if IS_BIG_ENDIAN 864 uint32_t reserved : 16; 865 uint32_t fec_sym_err_cnt_ln_3_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_t[15:00] - RO */ 866 #endif /* IS_BIG_ENDIAN */ 867 #if IS_LITTLE_ENDIAN 868 uint32_t fec_sym_err_cnt_ln_3_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_t[15:00] - RO */ 869 uint32_t reserved : 16; 870 #endif /* IS_LITTLE_ENDIAN */ 871 } fields; 872 } IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_t; 873 874 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_3_LOWER_REG_t; 875 876 typedef union { 877 uint32_t data; 878 struct { 879 #if IS_BIG_ENDIAN 880 uint32_t reserved : 16; 881 uint32_t fec_sym_err_cnt_ln_3_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_t[15:00] - RO */ 882 #endif /* IS_BIG_ENDIAN */ 883 #if IS_LITTLE_ENDIAN 884 uint32_t fec_sym_err_cnt_ln_3_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_t[15:00] - RO */ 885 uint32_t reserved : 16; 886 #endif /* IS_LITTLE_ENDIAN */ 887 } fields; 888 } IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_t; 889 890 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_3_UPPER_REG_t; 891 892 typedef union { 893 uint32_t data; 894 struct { 895 #if IS_BIG_ENDIAN 896 uint32_t reserved : 16; 897 uint32_t fec_sym_err_cnt_ln_2_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_t[15:00] - RO */ 898 #endif /* IS_BIG_ENDIAN */ 899 #if IS_LITTLE_ENDIAN 900 uint32_t fec_sym_err_cnt_ln_2_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_t[15:00] - RO */ 901 uint32_t reserved : 16; 902 #endif /* IS_LITTLE_ENDIAN */ 903 } fields; 904 } IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_t; 905 906 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_2_LOWER_REG_t; 907 908 typedef union { 909 uint32_t data; 910 struct { 911 #if IS_BIG_ENDIAN 912 uint32_t reserved : 16; 913 uint32_t fec_sym_err_cnt_ln_2_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_t[15:00] - RO */ 914 #endif /* IS_BIG_ENDIAN */ 915 #if IS_LITTLE_ENDIAN 916 uint32_t fec_sym_err_cnt_ln_2_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_t[15:00] - RO */ 917 uint32_t reserved : 16; 918 #endif /* IS_LITTLE_ENDIAN */ 919 } fields; 920 } IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_t; 921 922 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_2_UPPER_REG_t; 923 924 typedef union { 925 uint32_t data; 926 struct { 927 #if IS_BIG_ENDIAN 928 uint32_t reserved : 16; 929 uint32_t fec_sym_err_cnt_ln_1_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_t[15:00] - RO */ 930 #endif /* IS_BIG_ENDIAN */ 931 #if IS_LITTLE_ENDIAN 932 uint32_t fec_sym_err_cnt_ln_1_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_t[15:00] - RO */ 933 uint32_t reserved : 16; 934 #endif /* IS_LITTLE_ENDIAN */ 935 } fields; 936 } IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_t; 937 938 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_1_LOWER_REG_t; 939 940 typedef union { 941 uint32_t data; 942 struct { 943 #if IS_BIG_ENDIAN 944 uint32_t reserved : 16; 945 uint32_t fec_sym_err_cnt_ln_1_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_t[15:00] - RO */ 946 #endif /* IS_BIG_ENDIAN */ 947 #if IS_LITTLE_ENDIAN 948 uint32_t fec_sym_err_cnt_ln_1_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_t[15:00] - RO */ 949 uint32_t reserved : 16; 950 #endif /* IS_LITTLE_ENDIAN */ 951 } fields; 952 } IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_t; 953 954 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_1_UPPER_REG_t; 955 956 typedef union { 957 uint32_t data; 958 struct { 959 #if IS_BIG_ENDIAN 960 uint32_t reserved : 16; 961 uint32_t fec_sym_err_cnt_ln_0_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_t[15:00] - RO */ 962 #endif /* IS_BIG_ENDIAN */ 963 #if IS_LITTLE_ENDIAN 964 uint32_t fec_sym_err_cnt_ln_0_lower : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_t[15:00] - RO */ 965 uint32_t reserved : 16; 966 #endif /* IS_LITTLE_ENDIAN */ 967 } fields; 968 } IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_t; 969 970 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_0_LOWER_REG_t; 971 972 typedef union { 973 uint32_t data; 974 struct { 975 #if IS_BIG_ENDIAN 976 uint32_t reserved : 16; 977 uint32_t fec_sym_err_cnt_ln_0_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_t[15:00] - RO */ 978 #endif /* IS_BIG_ENDIAN */ 979 #if IS_LITTLE_ENDIAN 980 uint32_t fec_sym_err_cnt_ln_0_upper : 16; /* IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_t[15:00] - RO */ 981 uint32_t reserved : 16; 982 #endif /* IS_LITTLE_ENDIAN */ 983 } fields; 984 } IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_t; 985 986 typedef IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_t IEEE_CL91_RX_FEC_SYM_ERR_CNT_LN_0_UPPER_REG_t; 987 988 989 /*-----------------------------------------------*/ 990 /* Structs for IEEE_CL91_TX Bank */ 991 /*-----------------------------------------------*/ 992 typedef union { 993 uint32_t data; 994 struct { 995 #if IS_BIG_ENDIAN 996 uint32_t reserved : 16; 997 uint32_t bip_err_cnt_ln_0 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_0_reg_t[15:00] - RO */ 998 #endif /* IS_BIG_ENDIAN */ 999 #if IS_LITTLE_ENDIAN 1000 uint32_t bip_err_cnt_ln_0 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_0_reg_t[15:00] - RO */ 1001 uint32_t reserved : 16; 1002 #endif /* IS_LITTLE_ENDIAN */ 1003 } fields; 1004 } IEEE_CL91_TX_bip_err_cnt_ln_0_reg_t; 1005 1006 typedef IEEE_CL91_TX_bip_err_cnt_ln_0_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_0_REG_t; 1007 1008 typedef union { 1009 uint32_t data; 1010 struct { 1011 #if IS_BIG_ENDIAN 1012 uint32_t reserved : 16; 1013 uint32_t bip_err_cnt_ln_1 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_1_reg_t[15:00] - RO */ 1014 #endif /* IS_BIG_ENDIAN */ 1015 #if IS_LITTLE_ENDIAN 1016 uint32_t bip_err_cnt_ln_1 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_1_reg_t[15:00] - RO */ 1017 uint32_t reserved : 16; 1018 #endif /* IS_LITTLE_ENDIAN */ 1019 } fields; 1020 } IEEE_CL91_TX_bip_err_cnt_ln_1_reg_t; 1021 1022 typedef IEEE_CL91_TX_bip_err_cnt_ln_1_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_1_REG_t; 1023 1024 typedef union { 1025 uint32_t data; 1026 struct { 1027 #if IS_BIG_ENDIAN 1028 uint32_t reserved : 16; 1029 uint32_t bip_err_cnt_ln_2 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_2_reg_t[15:00] - RO */ 1030 #endif /* IS_BIG_ENDIAN */ 1031 #if IS_LITTLE_ENDIAN 1032 uint32_t bip_err_cnt_ln_2 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_2_reg_t[15:00] - RO */ 1033 uint32_t reserved : 16; 1034 #endif /* IS_LITTLE_ENDIAN */ 1035 } fields; 1036 } IEEE_CL91_TX_bip_err_cnt_ln_2_reg_t; 1037 1038 typedef IEEE_CL91_TX_bip_err_cnt_ln_2_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_2_REG_t; 1039 1040 typedef union { 1041 uint32_t data; 1042 struct { 1043 #if IS_BIG_ENDIAN 1044 uint32_t reserved : 16; 1045 uint32_t bip_err_cnt_ln_3 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_3_reg_t[15:00] - RO */ 1046 #endif /* IS_BIG_ENDIAN */ 1047 #if IS_LITTLE_ENDIAN 1048 uint32_t bip_err_cnt_ln_3 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_3_reg_t[15:00] - RO */ 1049 uint32_t reserved : 16; 1050 #endif /* IS_LITTLE_ENDIAN */ 1051 } fields; 1052 } IEEE_CL91_TX_bip_err_cnt_ln_3_reg_t; 1053 1054 typedef IEEE_CL91_TX_bip_err_cnt_ln_3_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_3_REG_t; 1055 1056 typedef union { 1057 uint32_t data; 1058 struct { 1059 #if IS_BIG_ENDIAN 1060 uint32_t reserved : 16; 1061 uint32_t bip_err_cnt_ln_4 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_4_reg_t[15:00] - RO */ 1062 #endif /* IS_BIG_ENDIAN */ 1063 #if IS_LITTLE_ENDIAN 1064 uint32_t bip_err_cnt_ln_4 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_4_reg_t[15:00] - RO */ 1065 uint32_t reserved : 16; 1066 #endif /* IS_LITTLE_ENDIAN */ 1067 } fields; 1068 } IEEE_CL91_TX_bip_err_cnt_ln_4_reg_t; 1069 1070 typedef IEEE_CL91_TX_bip_err_cnt_ln_4_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_4_REG_t; 1071 1072 typedef union { 1073 uint32_t data; 1074 struct { 1075 #if IS_BIG_ENDIAN 1076 uint32_t reserved : 16; 1077 uint32_t bip_err_cnt_ln_5 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_5_reg_t[15:00] - RO */ 1078 #endif /* IS_BIG_ENDIAN */ 1079 #if IS_LITTLE_ENDIAN 1080 uint32_t bip_err_cnt_ln_5 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_5_reg_t[15:00] - RO */ 1081 uint32_t reserved : 16; 1082 #endif /* IS_LITTLE_ENDIAN */ 1083 } fields; 1084 } IEEE_CL91_TX_bip_err_cnt_ln_5_reg_t; 1085 1086 typedef IEEE_CL91_TX_bip_err_cnt_ln_5_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_5_REG_t; 1087 1088 typedef union { 1089 uint32_t data; 1090 struct { 1091 #if IS_BIG_ENDIAN 1092 uint32_t reserved : 16; 1093 uint32_t bip_err_cnt_ln_6 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_6_reg_t[15:00] - RO */ 1094 #endif /* IS_BIG_ENDIAN */ 1095 #if IS_LITTLE_ENDIAN 1096 uint32_t bip_err_cnt_ln_6 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_6_reg_t[15:00] - RO */ 1097 uint32_t reserved : 16; 1098 #endif /* IS_LITTLE_ENDIAN */ 1099 } fields; 1100 } IEEE_CL91_TX_bip_err_cnt_ln_6_reg_t; 1101 1102 typedef IEEE_CL91_TX_bip_err_cnt_ln_6_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_6_REG_t; 1103 1104 typedef union { 1105 uint32_t data; 1106 struct { 1107 #if IS_BIG_ENDIAN 1108 uint32_t reserved : 16; 1109 uint32_t bip_err_cnt_ln_7 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_7_reg_t[15:00] - RO */ 1110 #endif /* IS_BIG_ENDIAN */ 1111 #if IS_LITTLE_ENDIAN 1112 uint32_t bip_err_cnt_ln_7 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_7_reg_t[15:00] - RO */ 1113 uint32_t reserved : 16; 1114 #endif /* IS_LITTLE_ENDIAN */ 1115 } fields; 1116 } IEEE_CL91_TX_bip_err_cnt_ln_7_reg_t; 1117 1118 typedef IEEE_CL91_TX_bip_err_cnt_ln_7_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_7_REG_t; 1119 1120 typedef union { 1121 uint32_t data; 1122 struct { 1123 #if IS_BIG_ENDIAN 1124 uint32_t reserved : 16; 1125 uint32_t bip_err_cnt_ln_8 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_8_reg_t[15:00] - RO */ 1126 #endif /* IS_BIG_ENDIAN */ 1127 #if IS_LITTLE_ENDIAN 1128 uint32_t bip_err_cnt_ln_8 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_8_reg_t[15:00] - RO */ 1129 uint32_t reserved : 16; 1130 #endif /* IS_LITTLE_ENDIAN */ 1131 } fields; 1132 } IEEE_CL91_TX_bip_err_cnt_ln_8_reg_t; 1133 1134 typedef IEEE_CL91_TX_bip_err_cnt_ln_8_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_8_REG_t; 1135 1136 typedef union { 1137 uint32_t data; 1138 struct { 1139 #if IS_BIG_ENDIAN 1140 uint32_t reserved : 16; 1141 uint32_t bip_err_cnt_ln_9 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_9_reg_t[15:00] - RO */ 1142 #endif /* IS_BIG_ENDIAN */ 1143 #if IS_LITTLE_ENDIAN 1144 uint32_t bip_err_cnt_ln_9 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_9_reg_t[15:00] - RO */ 1145 uint32_t reserved : 16; 1146 #endif /* IS_LITTLE_ENDIAN */ 1147 } fields; 1148 } IEEE_CL91_TX_bip_err_cnt_ln_9_reg_t; 1149 1150 typedef IEEE_CL91_TX_bip_err_cnt_ln_9_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_9_REG_t; 1151 1152 typedef union { 1153 uint32_t data; 1154 struct { 1155 #if IS_BIG_ENDIAN 1156 uint32_t reserved : 16; 1157 uint32_t bip_err_cnt_ln_10 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_10_reg_t[15:00] - RO */ 1158 #endif /* IS_BIG_ENDIAN */ 1159 #if IS_LITTLE_ENDIAN 1160 uint32_t bip_err_cnt_ln_10 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_10_reg_t[15:00] - RO */ 1161 uint32_t reserved : 16; 1162 #endif /* IS_LITTLE_ENDIAN */ 1163 } fields; 1164 } IEEE_CL91_TX_bip_err_cnt_ln_10_reg_t; 1165 1166 typedef IEEE_CL91_TX_bip_err_cnt_ln_10_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_10_REG_t; 1167 1168 typedef union { 1169 uint32_t data; 1170 struct { 1171 #if IS_BIG_ENDIAN 1172 uint32_t reserved : 16; 1173 uint32_t bip_err_cnt_ln_11 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_11_reg_t[15:00] - RO */ 1174 #endif /* IS_BIG_ENDIAN */ 1175 #if IS_LITTLE_ENDIAN 1176 uint32_t bip_err_cnt_ln_11 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_11_reg_t[15:00] - RO */ 1177 uint32_t reserved : 16; 1178 #endif /* IS_LITTLE_ENDIAN */ 1179 } fields; 1180 } IEEE_CL91_TX_bip_err_cnt_ln_11_reg_t; 1181 1182 typedef IEEE_CL91_TX_bip_err_cnt_ln_11_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_11_REG_t; 1183 1184 typedef union { 1185 uint32_t data; 1186 struct { 1187 #if IS_BIG_ENDIAN 1188 uint32_t reserved : 16; 1189 uint32_t bip_err_cnt_ln_12 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_12_reg_t[15:00] - RO */ 1190 #endif /* IS_BIG_ENDIAN */ 1191 #if IS_LITTLE_ENDIAN 1192 uint32_t bip_err_cnt_ln_12 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_12_reg_t[15:00] - RO */ 1193 uint32_t reserved : 16; 1194 #endif /* IS_LITTLE_ENDIAN */ 1195 } fields; 1196 } IEEE_CL91_TX_bip_err_cnt_ln_12_reg_t; 1197 1198 typedef IEEE_CL91_TX_bip_err_cnt_ln_12_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_12_REG_t; 1199 1200 typedef union { 1201 uint32_t data; 1202 struct { 1203 #if IS_BIG_ENDIAN 1204 uint32_t reserved : 16; 1205 uint32_t bip_err_cnt_ln_13 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_13_reg_t[15:00] - RO */ 1206 #endif /* IS_BIG_ENDIAN */ 1207 #if IS_LITTLE_ENDIAN 1208 uint32_t bip_err_cnt_ln_13 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_13_reg_t[15:00] - RO */ 1209 uint32_t reserved : 16; 1210 #endif /* IS_LITTLE_ENDIAN */ 1211 } fields; 1212 } IEEE_CL91_TX_bip_err_cnt_ln_13_reg_t; 1213 1214 typedef IEEE_CL91_TX_bip_err_cnt_ln_13_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_13_REG_t; 1215 1216 typedef union { 1217 uint32_t data; 1218 struct { 1219 #if IS_BIG_ENDIAN 1220 uint32_t reserved : 16; 1221 uint32_t bip_err_cnt_ln_14 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_14_reg_t[15:00] - RO */ 1222 #endif /* IS_BIG_ENDIAN */ 1223 #if IS_LITTLE_ENDIAN 1224 uint32_t bip_err_cnt_ln_14 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_14_reg_t[15:00] - RO */ 1225 uint32_t reserved : 16; 1226 #endif /* IS_LITTLE_ENDIAN */ 1227 } fields; 1228 } IEEE_CL91_TX_bip_err_cnt_ln_14_reg_t; 1229 1230 typedef IEEE_CL91_TX_bip_err_cnt_ln_14_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_14_REG_t; 1231 1232 typedef union { 1233 uint32_t data; 1234 struct { 1235 #if IS_BIG_ENDIAN 1236 uint32_t reserved : 16; 1237 uint32_t bip_err_cnt_ln_15 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_15_reg_t[15:00] - RO */ 1238 #endif /* IS_BIG_ENDIAN */ 1239 #if IS_LITTLE_ENDIAN 1240 uint32_t bip_err_cnt_ln_15 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_15_reg_t[15:00] - RO */ 1241 uint32_t reserved : 16; 1242 #endif /* IS_LITTLE_ENDIAN */ 1243 } fields; 1244 } IEEE_CL91_TX_bip_err_cnt_ln_15_reg_t; 1245 1246 typedef IEEE_CL91_TX_bip_err_cnt_ln_15_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_15_REG_t; 1247 1248 typedef union { 1249 uint32_t data; 1250 struct { 1251 #if IS_BIG_ENDIAN 1252 uint32_t reserved : 16; 1253 uint32_t bip_err_cnt_ln_16 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_16_reg_t[15:00] - RO */ 1254 #endif /* IS_BIG_ENDIAN */ 1255 #if IS_LITTLE_ENDIAN 1256 uint32_t bip_err_cnt_ln_16 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_16_reg_t[15:00] - RO */ 1257 uint32_t reserved : 16; 1258 #endif /* IS_LITTLE_ENDIAN */ 1259 } fields; 1260 } IEEE_CL91_TX_bip_err_cnt_ln_16_reg_t; 1261 1262 typedef IEEE_CL91_TX_bip_err_cnt_ln_16_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_16_REG_t; 1263 1264 typedef union { 1265 uint32_t data; 1266 struct { 1267 #if IS_BIG_ENDIAN 1268 uint32_t reserved : 16; 1269 uint32_t bip_err_cnt_ln_17 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_17_reg_t[15:00] - RO */ 1270 #endif /* IS_BIG_ENDIAN */ 1271 #if IS_LITTLE_ENDIAN 1272 uint32_t bip_err_cnt_ln_17 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_17_reg_t[15:00] - RO */ 1273 uint32_t reserved : 16; 1274 #endif /* IS_LITTLE_ENDIAN */ 1275 } fields; 1276 } IEEE_CL91_TX_bip_err_cnt_ln_17_reg_t; 1277 1278 typedef IEEE_CL91_TX_bip_err_cnt_ln_17_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_17_REG_t; 1279 1280 typedef union { 1281 uint32_t data; 1282 struct { 1283 #if IS_BIG_ENDIAN 1284 uint32_t reserved : 16; 1285 uint32_t bip_err_cnt_ln_18 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_18_reg_t[15:00] - RO */ 1286 #endif /* IS_BIG_ENDIAN */ 1287 #if IS_LITTLE_ENDIAN 1288 uint32_t bip_err_cnt_ln_18 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_18_reg_t[15:00] - RO */ 1289 uint32_t reserved : 16; 1290 #endif /* IS_LITTLE_ENDIAN */ 1291 } fields; 1292 } IEEE_CL91_TX_bip_err_cnt_ln_18_reg_t; 1293 1294 typedef IEEE_CL91_TX_bip_err_cnt_ln_18_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_18_REG_t; 1295 1296 typedef union { 1297 uint32_t data; 1298 struct { 1299 #if IS_BIG_ENDIAN 1300 uint32_t reserved : 16; 1301 uint32_t bip_err_cnt_ln_19 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_19_reg_t[15:00] - RO */ 1302 #endif /* IS_BIG_ENDIAN */ 1303 #if IS_LITTLE_ENDIAN 1304 uint32_t bip_err_cnt_ln_19 : 16; /* IEEE_CL91_TX_bip_err_cnt_ln_19_reg_t[15:00] - RO */ 1305 uint32_t reserved : 16; 1306 #endif /* IS_LITTLE_ENDIAN */ 1307 } fields; 1308 } IEEE_CL91_TX_bip_err_cnt_ln_19_reg_t; 1309 1310 typedef IEEE_CL91_TX_bip_err_cnt_ln_19_reg_t IEEE_CL91_TX_BIP_ERR_CNT_LN_19_REG_t; 1311 1312 typedef union { 1313 uint32_t data; 1314 struct { 1315 #if IS_BIG_ENDIAN 1316 uint32_t reserved : 16; 1317 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_t[15:05] - RSVD */ 1318 uint32_t pcs_ln_0_mapping : 5; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_t[04:00] - RO */ 1319 #endif /* IS_BIG_ENDIAN */ 1320 #if IS_LITTLE_ENDIAN 1321 uint32_t pcs_ln_0_mapping : 5; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_t[04:00] - RO */ 1322 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_0_mapping_reg_t[15:05] - RSVD */ 1323 uint32_t reserved : 16; 1324 #endif /* IS_LITTLE_ENDIAN */ 1325 } fields; 1326 } IEEE_CL91_TX_pcs_ln_0_mapping_reg_t; 1327 1328 typedef IEEE_CL91_TX_pcs_ln_0_mapping_reg_t IEEE_CL91_TX_PCS_LN_0_MAPPING_REG_t; 1329 1330 typedef union { 1331 uint32_t data; 1332 struct { 1333 #if IS_BIG_ENDIAN 1334 uint32_t reserved : 16; 1335 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_t[15:05] - RSVD */ 1336 uint32_t pcs_ln_1_mapping : 5; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_t[04:00] - RO */ 1337 #endif /* IS_BIG_ENDIAN */ 1338 #if IS_LITTLE_ENDIAN 1339 uint32_t pcs_ln_1_mapping : 5; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_t[04:00] - RO */ 1340 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_1_mapping_reg_t[15:05] - RSVD */ 1341 uint32_t reserved : 16; 1342 #endif /* IS_LITTLE_ENDIAN */ 1343 } fields; 1344 } IEEE_CL91_TX_pcs_ln_1_mapping_reg_t; 1345 1346 typedef IEEE_CL91_TX_pcs_ln_1_mapping_reg_t IEEE_CL91_TX_PCS_LN_1_MAPPING_REG_t; 1347 1348 typedef union { 1349 uint32_t data; 1350 struct { 1351 #if IS_BIG_ENDIAN 1352 uint32_t reserved : 16; 1353 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_t[15:05] - RSVD */ 1354 uint32_t pcs_ln_2_mapping : 5; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_t[04:00] - RO */ 1355 #endif /* IS_BIG_ENDIAN */ 1356 #if IS_LITTLE_ENDIAN 1357 uint32_t pcs_ln_2_mapping : 5; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_t[04:00] - RO */ 1358 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_2_mapping_reg_t[15:05] - RSVD */ 1359 uint32_t reserved : 16; 1360 #endif /* IS_LITTLE_ENDIAN */ 1361 } fields; 1362 } IEEE_CL91_TX_pcs_ln_2_mapping_reg_t; 1363 1364 typedef IEEE_CL91_TX_pcs_ln_2_mapping_reg_t IEEE_CL91_TX_PCS_LN_2_MAPPING_REG_t; 1365 1366 typedef union { 1367 uint32_t data; 1368 struct { 1369 #if IS_BIG_ENDIAN 1370 uint32_t reserved : 16; 1371 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_t[15:05] - RSVD */ 1372 uint32_t pcs_ln_3_mapping : 5; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_t[04:00] - RO */ 1373 #endif /* IS_BIG_ENDIAN */ 1374 #if IS_LITTLE_ENDIAN 1375 uint32_t pcs_ln_3_mapping : 5; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_t[04:00] - RO */ 1376 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_3_mapping_reg_t[15:05] - RSVD */ 1377 uint32_t reserved : 16; 1378 #endif /* IS_LITTLE_ENDIAN */ 1379 } fields; 1380 } IEEE_CL91_TX_pcs_ln_3_mapping_reg_t; 1381 1382 typedef IEEE_CL91_TX_pcs_ln_3_mapping_reg_t IEEE_CL91_TX_PCS_LN_3_MAPPING_REG_t; 1383 1384 typedef union { 1385 uint32_t data; 1386 struct { 1387 #if IS_BIG_ENDIAN 1388 uint32_t reserved : 16; 1389 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_t[15:05] - RSVD */ 1390 uint32_t pcs_ln_4_mapping : 5; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_t[04:00] - RO */ 1391 #endif /* IS_BIG_ENDIAN */ 1392 #if IS_LITTLE_ENDIAN 1393 uint32_t pcs_ln_4_mapping : 5; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_t[04:00] - RO */ 1394 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_4_mapping_reg_t[15:05] - RSVD */ 1395 uint32_t reserved : 16; 1396 #endif /* IS_LITTLE_ENDIAN */ 1397 } fields; 1398 } IEEE_CL91_TX_pcs_ln_4_mapping_reg_t; 1399 1400 typedef IEEE_CL91_TX_pcs_ln_4_mapping_reg_t IEEE_CL91_TX_PCS_LN_4_MAPPING_REG_t; 1401 1402 typedef union { 1403 uint32_t data; 1404 struct { 1405 #if IS_BIG_ENDIAN 1406 uint32_t reserved : 16; 1407 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_t[15:05] - RSVD */ 1408 uint32_t pcs_ln_5_mapping : 5; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_t[04:00] - RO */ 1409 #endif /* IS_BIG_ENDIAN */ 1410 #if IS_LITTLE_ENDIAN 1411 uint32_t pcs_ln_5_mapping : 5; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_t[04:00] - RO */ 1412 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_5_mapping_reg_t[15:05] - RSVD */ 1413 uint32_t reserved : 16; 1414 #endif /* IS_LITTLE_ENDIAN */ 1415 } fields; 1416 } IEEE_CL91_TX_pcs_ln_5_mapping_reg_t; 1417 1418 typedef IEEE_CL91_TX_pcs_ln_5_mapping_reg_t IEEE_CL91_TX_PCS_LN_5_MAPPING_REG_t; 1419 1420 typedef union { 1421 uint32_t data; 1422 struct { 1423 #if IS_BIG_ENDIAN 1424 uint32_t reserved : 16; 1425 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_t[15:05] - RSVD */ 1426 uint32_t pcs_ln_6_mapping : 5; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_t[04:00] - RO */ 1427 #endif /* IS_BIG_ENDIAN */ 1428 #if IS_LITTLE_ENDIAN 1429 uint32_t pcs_ln_6_mapping : 5; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_t[04:00] - RO */ 1430 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_6_mapping_reg_t[15:05] - RSVD */ 1431 uint32_t reserved : 16; 1432 #endif /* IS_LITTLE_ENDIAN */ 1433 } fields; 1434 } IEEE_CL91_TX_pcs_ln_6_mapping_reg_t; 1435 1436 typedef IEEE_CL91_TX_pcs_ln_6_mapping_reg_t IEEE_CL91_TX_PCS_LN_6_MAPPING_REG_t; 1437 1438 typedef union { 1439 uint32_t data; 1440 struct { 1441 #if IS_BIG_ENDIAN 1442 uint32_t reserved : 16; 1443 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_t[15:05] - RSVD */ 1444 uint32_t pcs_ln_7_mapping : 5; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_t[04:00] - RO */ 1445 #endif /* IS_BIG_ENDIAN */ 1446 #if IS_LITTLE_ENDIAN 1447 uint32_t pcs_ln_7_mapping : 5; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_t[04:00] - RO */ 1448 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_7_mapping_reg_t[15:05] - RSVD */ 1449 uint32_t reserved : 16; 1450 #endif /* IS_LITTLE_ENDIAN */ 1451 } fields; 1452 } IEEE_CL91_TX_pcs_ln_7_mapping_reg_t; 1453 1454 typedef IEEE_CL91_TX_pcs_ln_7_mapping_reg_t IEEE_CL91_TX_PCS_LN_7_MAPPING_REG_t; 1455 1456 typedef union { 1457 uint32_t data; 1458 struct { 1459 #if IS_BIG_ENDIAN 1460 uint32_t reserved : 16; 1461 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_t[15:05] - RSVD */ 1462 uint32_t pcs_ln_8_mapping : 5; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_t[04:00] - RO */ 1463 #endif /* IS_BIG_ENDIAN */ 1464 #if IS_LITTLE_ENDIAN 1465 uint32_t pcs_ln_8_mapping : 5; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_t[04:00] - RO */ 1466 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_8_mapping_reg_t[15:05] - RSVD */ 1467 uint32_t reserved : 16; 1468 #endif /* IS_LITTLE_ENDIAN */ 1469 } fields; 1470 } IEEE_CL91_TX_pcs_ln_8_mapping_reg_t; 1471 1472 typedef IEEE_CL91_TX_pcs_ln_8_mapping_reg_t IEEE_CL91_TX_PCS_LN_8_MAPPING_REG_t; 1473 1474 typedef union { 1475 uint32_t data; 1476 struct { 1477 #if IS_BIG_ENDIAN 1478 uint32_t reserved : 16; 1479 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_t[15:05] - RSVD */ 1480 uint32_t pcs_ln_9_mapping : 5; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_t[04:00] - RO */ 1481 #endif /* IS_BIG_ENDIAN */ 1482 #if IS_LITTLE_ENDIAN 1483 uint32_t pcs_ln_9_mapping : 5; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_t[04:00] - RO */ 1484 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_9_mapping_reg_t[15:05] - RSVD */ 1485 uint32_t reserved : 16; 1486 #endif /* IS_LITTLE_ENDIAN */ 1487 } fields; 1488 } IEEE_CL91_TX_pcs_ln_9_mapping_reg_t; 1489 1490 typedef IEEE_CL91_TX_pcs_ln_9_mapping_reg_t IEEE_CL91_TX_PCS_LN_9_MAPPING_REG_t; 1491 1492 typedef union { 1493 uint32_t data; 1494 struct { 1495 #if IS_BIG_ENDIAN 1496 uint32_t reserved : 16; 1497 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_t[15:05] - RSVD */ 1498 uint32_t pcs_ln_10_mapping : 5; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_t[04:00] - RO */ 1499 #endif /* IS_BIG_ENDIAN */ 1500 #if IS_LITTLE_ENDIAN 1501 uint32_t pcs_ln_10_mapping : 5; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_t[04:00] - RO */ 1502 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_10_mapping_reg_t[15:05] - RSVD */ 1503 uint32_t reserved : 16; 1504 #endif /* IS_LITTLE_ENDIAN */ 1505 } fields; 1506 } IEEE_CL91_TX_pcs_ln_10_mapping_reg_t; 1507 1508 typedef IEEE_CL91_TX_pcs_ln_10_mapping_reg_t IEEE_CL91_TX_PCS_LN_10_MAPPING_REG_t; 1509 1510 typedef union { 1511 uint32_t data; 1512 struct { 1513 #if IS_BIG_ENDIAN 1514 uint32_t reserved : 16; 1515 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_t[15:05] - RSVD */ 1516 uint32_t pcs_ln_11_mapping : 5; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_t[04:00] - RO */ 1517 #endif /* IS_BIG_ENDIAN */ 1518 #if IS_LITTLE_ENDIAN 1519 uint32_t pcs_ln_11_mapping : 5; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_t[04:00] - RO */ 1520 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_11_mapping_reg_t[15:05] - RSVD */ 1521 uint32_t reserved : 16; 1522 #endif /* IS_LITTLE_ENDIAN */ 1523 } fields; 1524 } IEEE_CL91_TX_pcs_ln_11_mapping_reg_t; 1525 1526 typedef IEEE_CL91_TX_pcs_ln_11_mapping_reg_t IEEE_CL91_TX_PCS_LN_11_MAPPING_REG_t; 1527 1528 typedef union { 1529 uint32_t data; 1530 struct { 1531 #if IS_BIG_ENDIAN 1532 uint32_t reserved : 16; 1533 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_t[15:05] - RSVD */ 1534 uint32_t pcs_ln_12_mapping : 5; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_t[04:00] - RO */ 1535 #endif /* IS_BIG_ENDIAN */ 1536 #if IS_LITTLE_ENDIAN 1537 uint32_t pcs_ln_12_mapping : 5; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_t[04:00] - RO */ 1538 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_12_mapping_reg_t[15:05] - RSVD */ 1539 uint32_t reserved : 16; 1540 #endif /* IS_LITTLE_ENDIAN */ 1541 } fields; 1542 } IEEE_CL91_TX_pcs_ln_12_mapping_reg_t; 1543 1544 typedef IEEE_CL91_TX_pcs_ln_12_mapping_reg_t IEEE_CL91_TX_PCS_LN_12_MAPPING_REG_t; 1545 1546 typedef union { 1547 uint32_t data; 1548 struct { 1549 #if IS_BIG_ENDIAN 1550 uint32_t reserved : 16; 1551 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_t[15:05] - RSVD */ 1552 uint32_t pcs_ln_13_mapping : 5; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_t[04:00] - RO */ 1553 #endif /* IS_BIG_ENDIAN */ 1554 #if IS_LITTLE_ENDIAN 1555 uint32_t pcs_ln_13_mapping : 5; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_t[04:00] - RO */ 1556 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_13_mapping_reg_t[15:05] - RSVD */ 1557 uint32_t reserved : 16; 1558 #endif /* IS_LITTLE_ENDIAN */ 1559 } fields; 1560 } IEEE_CL91_TX_pcs_ln_13_mapping_reg_t; 1561 1562 typedef IEEE_CL91_TX_pcs_ln_13_mapping_reg_t IEEE_CL91_TX_PCS_LN_13_MAPPING_REG_t; 1563 1564 typedef union { 1565 uint32_t data; 1566 struct { 1567 #if IS_BIG_ENDIAN 1568 uint32_t reserved : 16; 1569 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_t[15:05] - RSVD */ 1570 uint32_t pcs_ln_14_mapping : 5; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_t[04:00] - RO */ 1571 #endif /* IS_BIG_ENDIAN */ 1572 #if IS_LITTLE_ENDIAN 1573 uint32_t pcs_ln_14_mapping : 5; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_t[04:00] - RO */ 1574 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_14_mapping_reg_t[15:05] - RSVD */ 1575 uint32_t reserved : 16; 1576 #endif /* IS_LITTLE_ENDIAN */ 1577 } fields; 1578 } IEEE_CL91_TX_pcs_ln_14_mapping_reg_t; 1579 1580 typedef IEEE_CL91_TX_pcs_ln_14_mapping_reg_t IEEE_CL91_TX_PCS_LN_14_MAPPING_REG_t; 1581 1582 typedef union { 1583 uint32_t data; 1584 struct { 1585 #if IS_BIG_ENDIAN 1586 uint32_t reserved : 16; 1587 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_t[15:05] - RSVD */ 1588 uint32_t pcs_ln_15_mapping : 5; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_t[04:00] - RO */ 1589 #endif /* IS_BIG_ENDIAN */ 1590 #if IS_LITTLE_ENDIAN 1591 uint32_t pcs_ln_15_mapping : 5; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_t[04:00] - RO */ 1592 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_15_mapping_reg_t[15:05] - RSVD */ 1593 uint32_t reserved : 16; 1594 #endif /* IS_LITTLE_ENDIAN */ 1595 } fields; 1596 } IEEE_CL91_TX_pcs_ln_15_mapping_reg_t; 1597 1598 typedef IEEE_CL91_TX_pcs_ln_15_mapping_reg_t IEEE_CL91_TX_PCS_LN_15_MAPPING_REG_t; 1599 1600 typedef union { 1601 uint32_t data; 1602 struct { 1603 #if IS_BIG_ENDIAN 1604 uint32_t reserved : 16; 1605 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_t[15:05] - RSVD */ 1606 uint32_t pcs_ln_16_mapping : 5; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_t[04:00] - RO */ 1607 #endif /* IS_BIG_ENDIAN */ 1608 #if IS_LITTLE_ENDIAN 1609 uint32_t pcs_ln_16_mapping : 5; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_t[04:00] - RO */ 1610 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_16_mapping_reg_t[15:05] - RSVD */ 1611 uint32_t reserved : 16; 1612 #endif /* IS_LITTLE_ENDIAN */ 1613 } fields; 1614 } IEEE_CL91_TX_pcs_ln_16_mapping_reg_t; 1615 1616 typedef IEEE_CL91_TX_pcs_ln_16_mapping_reg_t IEEE_CL91_TX_PCS_LN_16_MAPPING_REG_t; 1617 1618 typedef union { 1619 uint32_t data; 1620 struct { 1621 #if IS_BIG_ENDIAN 1622 uint32_t reserved : 16; 1623 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_t[15:05] - RSVD */ 1624 uint32_t pcs_ln_17_mapping : 5; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_t[04:00] - RO */ 1625 #endif /* IS_BIG_ENDIAN */ 1626 #if IS_LITTLE_ENDIAN 1627 uint32_t pcs_ln_17_mapping : 5; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_t[04:00] - RO */ 1628 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_17_mapping_reg_t[15:05] - RSVD */ 1629 uint32_t reserved : 16; 1630 #endif /* IS_LITTLE_ENDIAN */ 1631 } fields; 1632 } IEEE_CL91_TX_pcs_ln_17_mapping_reg_t; 1633 1634 typedef IEEE_CL91_TX_pcs_ln_17_mapping_reg_t IEEE_CL91_TX_PCS_LN_17_MAPPING_REG_t; 1635 1636 typedef union { 1637 uint32_t data; 1638 struct { 1639 #if IS_BIG_ENDIAN 1640 uint32_t reserved : 16; 1641 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_t[15:05] - RSVD */ 1642 uint32_t pcs_ln_18_mapping : 5; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_t[04:00] - RO */ 1643 #endif /* IS_BIG_ENDIAN */ 1644 #if IS_LITTLE_ENDIAN 1645 uint32_t pcs_ln_18_mapping : 5; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_t[04:00] - RO */ 1646 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_18_mapping_reg_t[15:05] - RSVD */ 1647 uint32_t reserved : 16; 1648 #endif /* IS_LITTLE_ENDIAN */ 1649 } fields; 1650 } IEEE_CL91_TX_pcs_ln_18_mapping_reg_t; 1651 1652 typedef IEEE_CL91_TX_pcs_ln_18_mapping_reg_t IEEE_CL91_TX_PCS_LN_18_MAPPING_REG_t; 1653 1654 typedef union { 1655 uint32_t data; 1656 struct { 1657 #if IS_BIG_ENDIAN 1658 uint32_t reserved : 16; 1659 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_t[15:05] - RSVD */ 1660 uint32_t pcs_ln_19_mapping : 5; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_t[04:00] - RO */ 1661 #endif /* IS_BIG_ENDIAN */ 1662 #if IS_LITTLE_ENDIAN 1663 uint32_t pcs_ln_19_mapping : 5; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_t[04:00] - RO */ 1664 uint32_t reserved_05 : 11; /* IEEE_CL91_TX_pcs_ln_19_mapping_reg_t[15:05] - RSVD */ 1665 uint32_t reserved : 16; 1666 #endif /* IS_LITTLE_ENDIAN */ 1667 } fields; 1668 } IEEE_CL91_TX_pcs_ln_19_mapping_reg_t; 1669 1670 typedef IEEE_CL91_TX_pcs_ln_19_mapping_reg_t IEEE_CL91_TX_PCS_LN_19_MAPPING_REG_t; 1671 1672 typedef union { 1673 uint32_t data; 1674 struct { 1675 #if IS_BIG_ENDIAN 1676 uint32_t reserved : 16; 1677 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_t[15:08] - RSVD */ 1678 uint32_t pcs_blk_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_t[07:00] - RO */ 1679 #endif /* IS_BIG_ENDIAN */ 1680 #if IS_LITTLE_ENDIAN 1681 uint32_t pcs_blk_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_t[07:00] - RO */ 1682 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status1_reg_t[15:08] - RSVD */ 1683 uint32_t reserved : 16; 1684 #endif /* IS_LITTLE_ENDIAN */ 1685 } fields; 1686 } IEEE_CL91_TX_pcs_align_status1_reg_t; 1687 1688 typedef IEEE_CL91_TX_pcs_align_status1_reg_t IEEE_CL91_TX_PCS_ALIGN_STATUS1_REG_t; 1689 1690 typedef union { 1691 uint32_t data; 1692 struct { 1693 #if IS_BIG_ENDIAN 1694 uint32_t reserved : 16; 1695 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status2_reg_t[15:12] - RSVD */ 1696 uint32_t pcs_blk_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status2_reg_t[11:00] - RO */ 1697 #endif /* IS_BIG_ENDIAN */ 1698 #if IS_LITTLE_ENDIAN 1699 uint32_t pcs_blk_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status2_reg_t[11:00] - RO */ 1700 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status2_reg_t[15:12] - RSVD */ 1701 uint32_t reserved : 16; 1702 #endif /* IS_LITTLE_ENDIAN */ 1703 } fields; 1704 } IEEE_CL91_TX_pcs_align_status2_reg_t; 1705 1706 typedef IEEE_CL91_TX_pcs_align_status2_reg_t IEEE_CL91_TX_PCS_ALIGN_STATUS2_REG_t; 1707 1708 typedef union { 1709 uint32_t data; 1710 struct { 1711 #if IS_BIG_ENDIAN 1712 uint32_t reserved : 16; 1713 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_t[15:08] - RSVD */ 1714 uint32_t pcs_am_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_t[07:00] - RO */ 1715 #endif /* IS_BIG_ENDIAN */ 1716 #if IS_LITTLE_ENDIAN 1717 uint32_t pcs_am_lock_status_7_0 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_t[07:00] - RO */ 1718 uint32_t reserved_08 : 8; /* IEEE_CL91_TX_pcs_align_status3_reg_t[15:08] - RSVD */ 1719 uint32_t reserved : 16; 1720 #endif /* IS_LITTLE_ENDIAN */ 1721 } fields; 1722 } IEEE_CL91_TX_pcs_align_status3_reg_t; 1723 1724 typedef IEEE_CL91_TX_pcs_align_status3_reg_t IEEE_CL91_TX_PCS_ALIGN_STATUS3_REG_t; 1725 1726 typedef union { 1727 uint32_t data; 1728 struct { 1729 #if IS_BIG_ENDIAN 1730 uint32_t reserved : 16; 1731 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status4_reg_t[15:12] - RSVD */ 1732 uint32_t pcs_am_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status4_reg_t[11:00] - RO */ 1733 #endif /* IS_BIG_ENDIAN */ 1734 #if IS_LITTLE_ENDIAN 1735 uint32_t pcs_am_lock_status_19_8 : 12; /* IEEE_CL91_TX_pcs_align_status4_reg_t[11:00] - RO */ 1736 uint32_t reserved_12 : 4; /* IEEE_CL91_TX_pcs_align_status4_reg_t[15:12] - RSVD */ 1737 uint32_t reserved : 16; 1738 #endif /* IS_LITTLE_ENDIAN */ 1739 } fields; 1740 } IEEE_CL91_TX_pcs_align_status4_reg_t; 1741 1742 typedef IEEE_CL91_TX_pcs_align_status4_reg_t IEEE_CL91_TX_PCS_ALIGN_STATUS4_REG_t; 1743 1744 1745 /*-----------------------------------------------*/ 1746 /* Structs for DEV1_SLICE Bank */ 1747 /*-----------------------------------------------*/ 1748 typedef union { 1749 uint32_t data; 1750 struct { 1751 #if IS_BIG_ENDIAN 1752 uint32_t reserved : 16; 1753 uint32_t devid : 5; /* DEV1_SLICE_slice_t[15:11] - WO */ 1754 uint32_t reserved_10 : 1; /* DEV1_SLICE_slice_t[10] - RSVD */ 1755 uint32_t rd_lane : 2; /* DEV1_SLICE_slice_t[09:08] - WO */ 1756 uint32_t wr_lane : 4; /* DEV1_SLICE_slice_t[07:04] - WO */ 1757 uint32_t reserved_01 : 3; /* DEV1_SLICE_slice_t[03:01] - RSVD */ 1758 uint32_t sysen : 1; /* DEV1_SLICE_slice_t[00] - WO */ 1759 #endif /* IS_BIG_ENDIAN */ 1760 #if IS_LITTLE_ENDIAN 1761 uint32_t sysen : 1; /* DEV1_SLICE_slice_t[00] - WO */ 1762 uint32_t reserved_01 : 3; /* DEV1_SLICE_slice_t[03:01] - RSVD */ 1763 uint32_t wr_lane : 4; /* DEV1_SLICE_slice_t[07:04] - WO */ 1764 uint32_t rd_lane : 2; /* DEV1_SLICE_slice_t[09:08] - WO */ 1765 uint32_t reserved_10 : 1; /* DEV1_SLICE_slice_t[10] - RSVD */ 1766 uint32_t devid : 5; /* DEV1_SLICE_slice_t[15:11] - WO */ 1767 uint32_t reserved : 16; 1768 #endif /* IS_LITTLE_ENDIAN */ 1769 } fields; 1770 } DEV1_SLICE_slice_t; 1771 1772 typedef DEV1_SLICE_slice_t DEV1_SLICE_SLICE_t; 1773 1774 1775 /*-----------------------------------------------*/ 1776 /* Structs for FUR_MDICS_PMI_ARB_MASK Bank */ 1777 /*-----------------------------------------------*/ 1778 typedef union { 1779 uint32_t data; 1780 struct { 1781 #if IS_BIG_ENDIAN 1782 uint32_t reserved : 16; 1783 uint32_t data : 16; /* FUR_MDICS_PMI_ARB_MASK_mdics_pmi_arb_mask_t[15:00] - SC */ 1784 #endif /* IS_BIG_ENDIAN */ 1785 #if IS_LITTLE_ENDIAN 1786 uint32_t data : 16; /* FUR_MDICS_PMI_ARB_MASK_mdics_pmi_arb_mask_t[15:00] - SC */ 1787 uint32_t reserved : 16; 1788 #endif /* IS_LITTLE_ENDIAN */ 1789 } fields; 1790 } FUR_MDICS_PMI_ARB_MASK_mdics_pmi_arb_mask_t; 1791 1792 typedef FUR_MDICS_PMI_ARB_MASK_mdics_pmi_arb_mask_t FUR_MDICS_PMI_ARB_MASK_MDICS_PMI_ARB_MASK_t; 1793 1794 1795 /*-----------------------------------------------*/ 1796 /* Structs for FUR_GEN_CNTRLS Bank */ 1797 /*-----------------------------------------------*/ 1798 typedef union { 1799 uint32_t data; 1800 struct { 1801 #if IS_BIG_ENDIAN 1802 uint32_t reserved : 16; 1803 uint32_t reserved_07 : 9; /* FUR_GEN_CNTRLS_gen_control1_t[15:07] - RSVD */ 1804 uint32_t reserved_06 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[06] - RSVD */ 1805 uint32_t reserved_05 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[05] - RSVD */ 1806 uint32_t reserved_04 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[04] - RSVD */ 1807 uint32_t reserved_03 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[03] - RSVD */ 1808 uint32_t reserved_02 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[02] - RSVD */ 1809 uint32_t reg_rstb : 1; /* FUR_GEN_CNTRLS_gen_control1_t[01] - WO */ 1810 uint32_t resetb : 1; /* FUR_GEN_CNTRLS_gen_control1_t[00] - WO */ 1811 #endif /* IS_BIG_ENDIAN */ 1812 #if IS_LITTLE_ENDIAN 1813 uint32_t resetb : 1; /* FUR_GEN_CNTRLS_gen_control1_t[00] - WO */ 1814 uint32_t reg_rstb : 1; /* FUR_GEN_CNTRLS_gen_control1_t[01] - WO */ 1815 uint32_t reserved_02 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[02] - RSVD */ 1816 uint32_t reserved_03 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[03] - RSVD */ 1817 uint32_t reserved_04 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[04] - RSVD */ 1818 uint32_t reserved_05 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[05] - RSVD */ 1819 uint32_t reserved_06 : 1; /* FUR_GEN_CNTRLS_gen_control1_t[06] - RSVD */ 1820 uint32_t reserved_07 : 9; /* FUR_GEN_CNTRLS_gen_control1_t[15:07] - RSVD */ 1821 uint32_t reserved : 16; 1822 #endif /* IS_LITTLE_ENDIAN */ 1823 } fields; 1824 } FUR_GEN_CNTRLS_gen_control1_t; 1825 1826 typedef FUR_GEN_CNTRLS_gen_control1_t FUR_GEN_CNTRLS_GEN_CONTROL1_t; 1827 1828 typedef union { 1829 uint32_t data; 1830 struct { 1831 #if IS_BIG_ENDIAN 1832 uint32_t reserved : 16; 1833 uint32_t reserved_06 : 10; /* FUR_GEN_CNTRLS_gen_control2_t[15:06] - RSVD */ 1834 uint32_t spi_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[05] - RSVD */ 1835 uint32_t spi2x_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[04] - RSVD */ 1836 uint32_t m0_slv_ucp_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[03] - WO */ 1837 uint32_t m0_slv_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[02] - WO */ 1838 uint32_t m0_mstr_ucp_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[01] - WO */ 1839 uint32_t m0_mstr_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[00] - WO */ 1840 #endif /* IS_BIG_ENDIAN */ 1841 #if IS_LITTLE_ENDIAN 1842 uint32_t m0_mstr_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[00] - WO */ 1843 uint32_t m0_mstr_ucp_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[01] - WO */ 1844 uint32_t m0_slv_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[02] - WO */ 1845 uint32_t m0_slv_ucp_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[03] - WO */ 1846 uint32_t spi2x_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[04] - RSVD */ 1847 uint32_t spi_rstb : 1; /* FUR_GEN_CNTRLS_gen_control2_t[05] - RSVD */ 1848 uint32_t reserved_06 : 10; /* FUR_GEN_CNTRLS_gen_control2_t[15:06] - RSVD */ 1849 uint32_t reserved : 16; 1850 #endif /* IS_LITTLE_ENDIAN */ 1851 } fields; 1852 } FUR_GEN_CNTRLS_gen_control2_t; 1853 1854 typedef FUR_GEN_CNTRLS_gen_control2_t FUR_GEN_CNTRLS_GEN_CONTROL2_t; 1855 1856 typedef union { 1857 uint32_t data; 1858 struct { 1859 #if IS_BIG_ENDIAN 1860 uint32_t reserved : 16; 1861 uint32_t reserved_13 : 3; /* FUR_GEN_CNTRLS_gen_control3_t[15:13] - RSVD */ 1862 uint32_t clock_sclr_lock : 1; /* FUR_GEN_CNTRLS_gen_control3_t[12] - WO */ 1863 uint32_t reserved_11 : 1; /* FUR_GEN_CNTRLS_gen_control3_t[11] - RSVD */ 1864 uint32_t reserved_10 : 1; /* FUR_GEN_CNTRLS_gen_control3_t[10] - RSVD */ 1865 uint32_t ucspi_slow : 1; /* FUR_GEN_CNTRLS_gen_control3_t[09] - RSVD */ 1866 uint32_t clock_scaler_frc : 1; /* FUR_GEN_CNTRLS_gen_control3_t[08] - WO */ 1867 uint32_t clock_scaler_frcval : 4; /* FUR_GEN_CNTRLS_gen_control3_t[07:04] - WO */ 1868 uint32_t reserved_03 : 1; /* FUR_GEN_CNTRLS_gen_control3_t[03] - RSVD */ 1869 uint32_t clock_scaler_code : 3; /* FUR_GEN_CNTRLS_gen_control3_t[02:00] - WO */ 1870 #endif /* IS_BIG_ENDIAN */ 1871 #if IS_LITTLE_ENDIAN 1872 uint32_t clock_scaler_code : 3; /* FUR_GEN_CNTRLS_gen_control3_t[02:00] - WO */ 1873 uint32_t reserved_03 : 1; /* FUR_GEN_CNTRLS_gen_control3_t[03] - RSVD */ 1874 uint32_t clock_scaler_frcval : 4; /* FUR_GEN_CNTRLS_gen_control3_t[07:04] - WO */ 1875 uint32_t clock_scaler_frc : 1; /* FUR_GEN_CNTRLS_gen_control3_t[08] - WO */ 1876 uint32_t ucspi_slow : 1; /* FUR_GEN_CNTRLS_gen_control3_t[09] - RSVD */ 1877 uint32_t reserved_10 : 1; /* FUR_GEN_CNTRLS_gen_control3_t[10] - RSVD */ 1878 uint32_t reserved_11 : 1; /* FUR_GEN_CNTRLS_gen_control3_t[11] - RSVD */ 1879 uint32_t clock_sclr_lock : 1; /* FUR_GEN_CNTRLS_gen_control3_t[12] - WO */ 1880 uint32_t reserved_13 : 3; /* FUR_GEN_CNTRLS_gen_control3_t[15:13] - RSVD */ 1881 uint32_t reserved : 16; 1882 #endif /* IS_LITTLE_ENDIAN */ 1883 } fields; 1884 } FUR_GEN_CNTRLS_gen_control3_t; 1885 1886 typedef FUR_GEN_CNTRLS_gen_control3_t FUR_GEN_CNTRLS_GEN_CONTROL3_t; 1887 1888 typedef union { 1889 uint32_t data; 1890 struct { 1891 #if IS_BIG_ENDIAN 1892 uint32_t reserved : 16; 1893 uint32_t reserved_05 : 11; /* FUR_GEN_CNTRLS_gen_control4_t[15:05] - RSVD */ 1894 uint32_t datapath_rstb : 1; /* FUR_GEN_CNTRLS_gen_control4_t[04] - WO */ 1895 uint32_t datapath_lane_rstb : 4; /* FUR_GEN_CNTRLS_gen_control4_t[03:00] - WO */ 1896 #endif /* IS_BIG_ENDIAN */ 1897 #if IS_LITTLE_ENDIAN 1898 uint32_t datapath_lane_rstb : 4; /* FUR_GEN_CNTRLS_gen_control4_t[03:00] - WO */ 1899 uint32_t datapath_rstb : 1; /* FUR_GEN_CNTRLS_gen_control4_t[04] - WO */ 1900 uint32_t reserved_05 : 11; /* FUR_GEN_CNTRLS_gen_control4_t[15:05] - RSVD */ 1901 uint32_t reserved : 16; 1902 #endif /* IS_LITTLE_ENDIAN */ 1903 } fields; 1904 } FUR_GEN_CNTRLS_gen_control4_t; 1905 1906 typedef FUR_GEN_CNTRLS_gen_control4_t FUR_GEN_CNTRLS_GEN_CONTROL4_t; 1907 1908 typedef union { 1909 uint32_t data; 1910 struct { 1911 #if IS_BIG_ENDIAN 1912 uint32_t reserved : 16; 1913 uint32_t master_code_start_ptr : 16; /* FUR_GEN_CNTRLS_spi_mst_code_start_ptr_t[15:00] - WO */ 1914 #endif /* IS_BIG_ENDIAN */ 1915 #if IS_LITTLE_ENDIAN 1916 uint32_t master_code_start_ptr : 16; /* FUR_GEN_CNTRLS_spi_mst_code_start_ptr_t[15:00] - WO */ 1917 uint32_t reserved : 16; 1918 #endif /* IS_LITTLE_ENDIAN */ 1919 } fields; 1920 } FUR_GEN_CNTRLS_spi_mst_code_start_ptr_t; 1921 1922 typedef FUR_GEN_CNTRLS_spi_mst_code_start_ptr_t FUR_GEN_CNTRLS_SPI_MST_CODE_START_PTR_t; 1923 1924 typedef union { 1925 uint32_t data; 1926 struct { 1927 #if IS_BIG_ENDIAN 1928 uint32_t reserved : 16; 1929 uint32_t slave_code_start_ptr : 16; /* FUR_GEN_CNTRLS_spi_slv_code_start_ptr_t[15:00] - WO */ 1930 #endif /* IS_BIG_ENDIAN */ 1931 #if IS_LITTLE_ENDIAN 1932 uint32_t slave_code_start_ptr : 16; /* FUR_GEN_CNTRLS_spi_slv_code_start_ptr_t[15:00] - WO */ 1933 uint32_t reserved : 16; 1934 #endif /* IS_LITTLE_ENDIAN */ 1935 } fields; 1936 } FUR_GEN_CNTRLS_spi_slv_code_start_ptr_t; 1937 1938 typedef FUR_GEN_CNTRLS_spi_slv_code_start_ptr_t FUR_GEN_CNTRLS_SPI_SLV_CODE_START_PTR_t; 1939 1940 typedef union { 1941 uint32_t data; 1942 struct { 1943 #if IS_BIG_ENDIAN 1944 uint32_t reserved : 16; 1945 uint32_t reserved_03 : 13; /* FUR_GEN_CNTRLS_spi_code_load_en_t[15:03] - RSVD */ 1946 uint32_t code_broadcast_en : 1; /* FUR_GEN_CNTRLS_spi_code_load_en_t[02] - WO */ 1947 uint32_t slave_code_download_en : 1; /* FUR_GEN_CNTRLS_spi_code_load_en_t[01] - WO */ 1948 uint32_t master_code_download_en : 1; /* FUR_GEN_CNTRLS_spi_code_load_en_t[00] - WO */ 1949 #endif /* IS_BIG_ENDIAN */ 1950 #if IS_LITTLE_ENDIAN 1951 uint32_t master_code_download_en : 1; /* FUR_GEN_CNTRLS_spi_code_load_en_t[00] - WO */ 1952 uint32_t slave_code_download_en : 1; /* FUR_GEN_CNTRLS_spi_code_load_en_t[01] - WO */ 1953 uint32_t code_broadcast_en : 1; /* FUR_GEN_CNTRLS_spi_code_load_en_t[02] - WO */ 1954 uint32_t reserved_03 : 13; /* FUR_GEN_CNTRLS_spi_code_load_en_t[15:03] - RSVD */ 1955 uint32_t reserved : 16; 1956 #endif /* IS_LITTLE_ENDIAN */ 1957 } fields; 1958 } FUR_GEN_CNTRLS_spi_code_load_en_t; 1959 1960 typedef FUR_GEN_CNTRLS_spi_code_load_en_t FUR_GEN_CNTRLS_SPI_CODE_LOAD_EN_t; 1961 1962 typedef union { 1963 uint32_t data; 1964 struct { 1965 #if IS_BIG_ENDIAN 1966 uint32_t reserved : 16; 1967 uint32_t slv_eeprom_offset : 4; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[15:12] - WO */ 1968 uint32_t reserved_11 : 1; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[11] - RSVD */ 1969 uint32_t slv_eeprom_count : 3; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[10:08] - WO */ 1970 uint32_t mst_eeprom_offset : 4; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[07:04] - WO */ 1971 uint32_t spi_master_oeb : 1; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[03] - WO */ 1972 uint32_t mst_eeprom_count : 3; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[02:00] - WO */ 1973 #endif /* IS_BIG_ENDIAN */ 1974 #if IS_LITTLE_ENDIAN 1975 uint32_t mst_eeprom_count : 3; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[02:00] - WO */ 1976 uint32_t spi_master_oeb : 1; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[03] - WO */ 1977 uint32_t mst_eeprom_offset : 4; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[07:04] - WO */ 1978 uint32_t slv_eeprom_count : 3; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[10:08] - WO */ 1979 uint32_t reserved_11 : 1; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[11] - RSVD */ 1980 uint32_t slv_eeprom_offset : 4; /* FUR_GEN_CNTRLS_spi_eeprom_control_t[15:12] - WO */ 1981 uint32_t reserved : 16; 1982 #endif /* IS_LITTLE_ENDIAN */ 1983 } fields; 1984 } FUR_GEN_CNTRLS_spi_eeprom_control_t; 1985 1986 typedef FUR_GEN_CNTRLS_spi_eeprom_control_t FUR_GEN_CNTRLS_SPI_EEPROM_CONTROL_t; 1987 1988 typedef union { 1989 uint32_t data; 1990 struct { 1991 #if IS_BIG_ENDIAN 1992 uint32_t reserved : 16; 1993 uint32_t global_intr_mask : 1; /* FUR_GEN_CNTRLS_mscr_t[15] - WO */ 1994 uint32_t reserved_03 : 12; /* FUR_GEN_CNTRLS_mscr_t[14:03] - RSVD */ 1995 uint32_t hresp_mask : 1; /* FUR_GEN_CNTRLS_mscr_t[02] - WO */ 1996 uint32_t reserved_00 : 2; /* FUR_GEN_CNTRLS_mscr_t[01:00] - RSVD */ 1997 #endif /* IS_BIG_ENDIAN */ 1998 #if IS_LITTLE_ENDIAN 1999 uint32_t reserved_00 : 2; /* FUR_GEN_CNTRLS_mscr_t[01:00] - RSVD */ 2000 uint32_t hresp_mask : 1; /* FUR_GEN_CNTRLS_mscr_t[02] - WO */ 2001 uint32_t reserved_03 : 12; /* FUR_GEN_CNTRLS_mscr_t[14:03] - RSVD */ 2002 uint32_t global_intr_mask : 1; /* FUR_GEN_CNTRLS_mscr_t[15] - WO */ 2003 uint32_t reserved : 16; 2004 #endif /* IS_LITTLE_ENDIAN */ 2005 } fields; 2006 } FUR_GEN_CNTRLS_mscr_t; 2007 2008 typedef FUR_GEN_CNTRLS_mscr_t FUR_GEN_CNTRLS_MSCR_t; 2009 2010 typedef union { 2011 uint32_t data; 2012 struct { 2013 #if IS_BIG_ENDIAN 2014 uint32_t reserved : 16; 2015 uint32_t msgout_val : 16; /* FUR_GEN_CNTRLS_msgout_t[15:00] - SC */ 2016 #endif /* IS_BIG_ENDIAN */ 2017 #if IS_LITTLE_ENDIAN 2018 uint32_t msgout_val : 16; /* FUR_GEN_CNTRLS_msgout_t[15:00] - SC */ 2019 uint32_t reserved : 16; 2020 #endif /* IS_LITTLE_ENDIAN */ 2021 } fields; 2022 } FUR_GEN_CNTRLS_msgout_t; 2023 2024 typedef FUR_GEN_CNTRLS_msgout_t FUR_GEN_CNTRLS_MSGOUT_t; 2025 2026 typedef union { 2027 uint32_t data; 2028 struct { 2029 #if IS_BIG_ENDIAN 2030 uint32_t reserved : 16; 2031 uint32_t msgin_val : 16; /* FUR_GEN_CNTRLS_msgin_t[15:00] - WO */ 2032 #endif /* IS_BIG_ENDIAN */ 2033 #if IS_LITTLE_ENDIAN 2034 uint32_t msgin_val : 16; /* FUR_GEN_CNTRLS_msgin_t[15:00] - WO */ 2035 uint32_t reserved : 16; 2036 #endif /* IS_LITTLE_ENDIAN */ 2037 } fields; 2038 } FUR_GEN_CNTRLS_msgin_t; 2039 2040 typedef FUR_GEN_CNTRLS_msgin_t FUR_GEN_CNTRLS_MSGIN_t; 2041 2042 typedef union { 2043 uint32_t data; 2044 struct { 2045 #if IS_BIG_ENDIAN 2046 uint32_t reserved : 16; 2047 uint32_t reserved_03 : 13; /* FUR_GEN_CNTRLS_boot_t[15:03] - RSVD */ 2048 uint32_t serboot_done_once : 1; /* FUR_GEN_CNTRLS_boot_t[02] - RO */ 2049 uint32_t serboot_busy : 1; /* FUR_GEN_CNTRLS_boot_t[01] - RO */ 2050 uint32_t reserved_00 : 1; /* FUR_GEN_CNTRLS_boot_t[00] - RSVD */ 2051 #endif /* IS_BIG_ENDIAN */ 2052 #if IS_LITTLE_ENDIAN 2053 uint32_t reserved_00 : 1; /* FUR_GEN_CNTRLS_boot_t[00] - RSVD */ 2054 uint32_t serboot_busy : 1; /* FUR_GEN_CNTRLS_boot_t[01] - RO */ 2055 uint32_t serboot_done_once : 1; /* FUR_GEN_CNTRLS_boot_t[02] - RO */ 2056 uint32_t reserved_03 : 13; /* FUR_GEN_CNTRLS_boot_t[15:03] - RSVD */ 2057 uint32_t reserved : 16; 2058 #endif /* IS_LITTLE_ENDIAN */ 2059 } fields; 2060 } FUR_GEN_CNTRLS_boot_t; 2061 2062 typedef FUR_GEN_CNTRLS_boot_t FUR_GEN_CNTRLS_BOOT_t; 2063 2064 typedef union { 2065 uint32_t data; 2066 struct { 2067 #if IS_BIG_ENDIAN 2068 uint32_t reserved : 16; 2069 uint32_t slv_msgout_val : 16; /* FUR_GEN_CNTRLS_slv_msgout_t[15:00] - SC */ 2070 #endif /* IS_BIG_ENDIAN */ 2071 #if IS_LITTLE_ENDIAN 2072 uint32_t slv_msgout_val : 16; /* FUR_GEN_CNTRLS_slv_msgout_t[15:00] - SC */ 2073 uint32_t reserved : 16; 2074 #endif /* IS_LITTLE_ENDIAN */ 2075 } fields; 2076 } FUR_GEN_CNTRLS_slv_msgout_t; 2077 2078 typedef FUR_GEN_CNTRLS_slv_msgout_t FUR_GEN_CNTRLS_SLV_MSGOUT_t; 2079 2080 typedef union { 2081 uint32_t data; 2082 struct { 2083 #if IS_BIG_ENDIAN 2084 uint32_t reserved : 16; 2085 uint32_t slv_msgin_val : 16; /* FUR_GEN_CNTRLS_slv_msgin_t[15:00] - WO */ 2086 #endif /* IS_BIG_ENDIAN */ 2087 #if IS_LITTLE_ENDIAN 2088 uint32_t slv_msgin_val : 16; /* FUR_GEN_CNTRLS_slv_msgin_t[15:00] - WO */ 2089 uint32_t reserved : 16; 2090 #endif /* IS_LITTLE_ENDIAN */ 2091 } fields; 2092 } FUR_GEN_CNTRLS_slv_msgin_t; 2093 2094 typedef FUR_GEN_CNTRLS_slv_msgin_t FUR_GEN_CNTRLS_SLV_MSGIN_t; 2095 2096 typedef union { 2097 uint32_t data; 2098 struct { 2099 #if IS_BIG_ENDIAN 2100 uint32_t reserved : 16; 2101 uint32_t mst_misc_intr_val : 16; /* FUR_GEN_CNTRLS_mst_misc_intr_t[15:00] - SC */ 2102 #endif /* IS_BIG_ENDIAN */ 2103 #if IS_LITTLE_ENDIAN 2104 uint32_t mst_misc_intr_val : 16; /* FUR_GEN_CNTRLS_mst_misc_intr_t[15:00] - SC */ 2105 uint32_t reserved : 16; 2106 #endif /* IS_LITTLE_ENDIAN */ 2107 } fields; 2108 } FUR_GEN_CNTRLS_mst_misc_intr_t; 2109 2110 typedef FUR_GEN_CNTRLS_mst_misc_intr_t FUR_GEN_CNTRLS_MST_MISC_INTR_t; 2111 2112 typedef union { 2113 uint32_t data; 2114 struct { 2115 #if IS_BIG_ENDIAN 2116 uint32_t reserved : 16; 2117 uint32_t slv_misc_intr_val : 16; /* FUR_GEN_CNTRLS_slv_misc_intr_t[15:00] - SC */ 2118 #endif /* IS_BIG_ENDIAN */ 2119 #if IS_LITTLE_ENDIAN 2120 uint32_t slv_misc_intr_val : 16; /* FUR_GEN_CNTRLS_slv_misc_intr_t[15:00] - SC */ 2121 uint32_t reserved : 16; 2122 #endif /* IS_LITTLE_ENDIAN */ 2123 } fields; 2124 } FUR_GEN_CNTRLS_slv_misc_intr_t; 2125 2126 typedef FUR_GEN_CNTRLS_slv_misc_intr_t FUR_GEN_CNTRLS_SLV_MISC_INTR_t; 2127 typedef union { 2128 uint32_t data; 2129 struct { 2130 #if IS_BIG_ENDIAN 2131 uint32_t reserved : 16; 2132 uint32_t reserved1 : 4; /* FUR_GEN_CNTRLS_gpreg10_TYPE[15:12] - WO */ 2133 uint32_t en_api_set_ln_cfg : 1; /* FUR_GEN_CNTRLS_gpreg10_TYPE[11:11] - WO */ 2134 uint32_t reserved2 : 3; /* FUR_GEN_CNTRLS_gpreg10_TYPE[10:08] - WO */ 2135 uint32_t reserved3 : 4; /* FUR_GEN_CNTRLS_gpreg10_TYPE[07:04] - WO */ 2136 uint32_t reserved4 : 4; /* FUR_GEN_CNTRLS_gpreg10_TYPE[03:00] - WO */ 2137 #endif /* IS_BIG_ENDIAN */ 2138 #if IS_LITTLE_ENDIAN 2139 uint32_t reserved4 : 4; /* FUR_GEN_CNTRLS_gpreg10_TYPE[03:00] - WO */ 2140 uint32_t reserved3 : 4; /* FUR_GEN_CNTRLS_gpreg10_TYPE[07:04] - WO */ 2141 uint32_t reserved2 : 3; /* FUR_GEN_CNTRLS_gpreg10_TYPE[10:08] - WO */ 2142 uint32_t en_api_set_ln_cfg : 1; /* FUR_GEN_CNTRLS_gpreg10_TYPE[11:11] - WO */ 2143 uint32_t reserved1 : 4; /* FUR_GEN_CNTRLS_gpreg10_TYPE[15:12] - WO */ 2144 uint32_t reserved : 16; 2145 #endif /* IS_LITTLE_ENDIAN */ 2146 } fields; 2147 } FUR_GEN_CNTRLS_gpreg10_t; 2148 2149 typedef union { 2150 uint32_t data; 2151 struct { 2152 #if IS_BIG_ENDIAN 2153 uint32_t reserved : 16; 2154 uint32_t en_tx_squelch_sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[15:12] - WO */ 2155 uint32_t en_frc_tx_trng_sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[11:08] - WO */ 2156 uint32_t en_ull_dp_line2sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[07:04] - WO */ 2157 uint32_t en_tx_rptr_mode_line2sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[03:00] - WO */ 2158 #endif /* IS_BIG_ENDIAN */ 2159 #if IS_LITTLE_ENDIAN 2160 uint32_t en_tx_rptr_mode_line2sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[03:00] - WO */ 2161 uint32_t en_ull_dp_line2sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[07:04] - WO */ 2162 uint32_t en_frc_tx_trng_sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[11:08] - WO */ 2163 uint32_t en_tx_squelch_sys : 4; /* FUR_GEN_CNTRLS_gpreg11_TYPE[15:12] - WO */ 2164 uint32_t reserved : 16; 2165 #endif /* IS_LITTLE_ENDIAN */ 2166 } fields; 2167 } FUR_GEN_CNTRLS_gpreg11_t; 2168 2169 typedef FUR_GEN_CNTRLS_gpreg11_t FUR_GEN_CNTRLS_GPREG11_t; 2170 2171 typedef union { 2172 uint32_t data; 2173 struct { 2174 #if IS_BIG_ENDIAN 2175 uint32_t reserved : 16; 2176 uint32_t en_tx_squelch_line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[15:12] - WO */ 2177 uint32_t en_frc_tx_trng_line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[11:08] - WO */ 2178 uint32_t en_ull_dp_sys2line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[07:04] - WO */ 2179 uint32_t en_tx_rptr_mode_sys2line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[03:00] - WO */ 2180 #endif /* IS_BIG_ENDIAN */ 2181 #if IS_LITTLE_ENDIAN 2182 uint32_t en_tx_rptr_mode_sys2line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[03:00] - WO */ 2183 uint32_t en_ull_dp_sys2line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[07:04] - WO */ 2184 uint32_t en_frc_tx_trng_line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[11:08] - WO */ 2185 uint32_t en_tx_squelch_line : 4; /* FUR_GEN_CNTRLS_gpreg12_TYPE[15:12] - WO */ 2186 uint32_t reserved : 16; 2187 #endif /* IS_LITTLE_ENDIAN */ 2188 } fields; 2189 } FUR_GEN_CNTRLS_gpreg12_t; 2190 2191 typedef FUR_GEN_CNTRLS_gpreg12_t FUR_GEN_CNTRLS_GPREG12_t; 2192 2193 typedef union { 2194 uint32_t data; 2195 struct { 2196 #if IS_BIG_ENDIAN 2197 uint32_t reserved : 16; 2198 uint32_t phy_type_sys : 3; /* FUR_GEN_CNTRLS_gpreg13_TYPE[15:13] - WO */ 2199 uint32_t en_auto_module_det : 1; /* FUR_GEN_CNTRLS_gpreg13_TYPE[12] - WO */ 2200 uint32_t rsrvd1 : 1; /* FUR_GEN_CNTRLS_gpreg13_TYPE[11] - WO */ 2201 uint32_t lane_cfg_override_en : 1; /* FUR_GEN_CNTRLS_gpreg13_TYPE[10] - WO */ 2202 uint32_t rsrvd : 10; /* FUR_GEN_CNTRLS_gpreg13_TYPE[09:00] - WO */ 2203 #endif /* IS_BIG_ENDIAN */ 2204 #if IS_LITTLE_ENDIAN 2205 uint32_t rsrvd : 10; /* FUR_GEN_CNTRLS_gpreg13_TYPE[09:00] - WO */ 2206 uint32_t lane_cfg_override_en : 1; /* FUR_GEN_CNTRLS_gpreg13_TYPE[10] - WO */ 2207 uint32_t rsrvd1 : 1; /* FUR_GEN_CNTRLS_gpreg13_TYPE[11] - WO */ 2208 uint32_t en_auto_module_det : 1; /* FUR_GEN_CNTRLS_gpreg13_TYPE[12] - WO */ 2209 uint32_t phy_type_sys : 3; /* FUR_GEN_CNTRLS_gpreg13_TYPE[15:13] - WO */ 2210 uint32_t reserved : 16; 2211 #endif /* IS_LITTLE_ENDIAN */ 2212 } fields; 2213 } FUR_GEN_CNTRLS_gpreg13_t; 2214 2215 typedef FUR_GEN_CNTRLS_gpreg13_t FUR_GEN_CNTRLS_GPREG13_t; 2216 2217 typedef union { 2218 uint32_t data; 2219 struct { 2220 #if IS_BIG_ENDIAN 2221 uint32_t reserved : 16; 2222 uint32_t gpreg14_data : 16; /* FUR_GEN_CNTRLS_gpreg14_t[15:00] - WO */ 2223 #endif /* IS_BIG_ENDIAN */ 2224 #if IS_LITTLE_ENDIAN 2225 uint32_t gpreg14_data : 16; /* FUR_GEN_CNTRLS_gpreg14_t[15:00] - WO */ 2226 uint32_t reserved : 16; 2227 #endif /* IS_LITTLE_ENDIAN */ 2228 } fields; 2229 } FUR_GEN_CNTRLS_gpreg14_t; 2230 2231 typedef FUR_GEN_CNTRLS_gpreg14_t FUR_GEN_CNTRLS_GPREG14_t; 2232 2233 typedef union { 2234 uint32_t data; 2235 struct { 2236 #if IS_BIG_ENDIAN 2237 uint32_t reserved : 16; 2238 uint32_t gpreg15_data : 16; /* FUR_GEN_CNTRLS_gpreg15_t[15:00] - WO */ 2239 #endif /* IS_BIG_ENDIAN */ 2240 #if IS_LITTLE_ENDIAN 2241 uint32_t gpreg15_data : 16; /* FUR_GEN_CNTRLS_gpreg15_t[15:00] - WO */ 2242 uint32_t reserved : 16; 2243 #endif /* IS_LITTLE_ENDIAN */ 2244 } fields; 2245 } FUR_GEN_CNTRLS_gpreg15_t; 2246 2247 typedef FUR_GEN_CNTRLS_gpreg15_t FUR_GEN_CNTRLS_GPREG15_t; 2248 2249 typedef union { 2250 uint32_t data; 2251 struct { 2252 #if IS_BIG_ENDIAN 2253 uint32_t reserved : 16; 2254 uint32_t mst_running_chksum_val : 16; /* FUR_GEN_CNTRLS_mst_running_chksum_t[15:00] - WO */ 2255 #endif /* IS_BIG_ENDIAN */ 2256 #if IS_LITTLE_ENDIAN 2257 uint32_t mst_running_chksum_val : 16; /* FUR_GEN_CNTRLS_mst_running_chksum_t[15:00] - WO */ 2258 uint32_t reserved : 16; 2259 #endif /* IS_LITTLE_ENDIAN */ 2260 } fields; 2261 } FUR_GEN_CNTRLS_mst_running_chksum_t; 2262 2263 typedef FUR_GEN_CNTRLS_mst_running_chksum_t FUR_GEN_CNTRLS_MST_RUNNING_CHKSUM_t; 2264 2265 typedef union { 2266 uint32_t data; 2267 struct { 2268 #if IS_BIG_ENDIAN 2269 uint32_t reserved : 16; 2270 uint32_t slv_running_chksum_val : 16; /* FUR_GEN_CNTRLS_slv_running_chksum_t[15:00] - WO */ 2271 #endif /* IS_BIG_ENDIAN */ 2272 #if IS_LITTLE_ENDIAN 2273 uint32_t slv_running_chksum_val : 16; /* FUR_GEN_CNTRLS_slv_running_chksum_t[15:00] - WO */ 2274 uint32_t reserved : 16; 2275 #endif /* IS_LITTLE_ENDIAN */ 2276 } fields; 2277 } FUR_GEN_CNTRLS_slv_running_chksum_t; 2278 2279 typedef FUR_GEN_CNTRLS_slv_running_chksum_t FUR_GEN_CNTRLS_SLV_RUNNING_CHKSUM_t; 2280 2281 typedef union { 2282 uint32_t data; 2283 struct { 2284 #if IS_BIG_ENDIAN 2285 uint32_t reserved : 16; 2286 uint32_t mst_running_byte_cnt_val : 16; /* FUR_GEN_CNTRLS_mst_running_byte_cnt_t[15:00] - WO */ 2287 #endif /* IS_BIG_ENDIAN */ 2288 #if IS_LITTLE_ENDIAN 2289 uint32_t mst_running_byte_cnt_val : 16; /* FUR_GEN_CNTRLS_mst_running_byte_cnt_t[15:00] - WO */ 2290 uint32_t reserved : 16; 2291 #endif /* IS_LITTLE_ENDIAN */ 2292 } fields; 2293 } FUR_GEN_CNTRLS_mst_running_byte_cnt_t; 2294 2295 typedef FUR_GEN_CNTRLS_mst_running_byte_cnt_t FUR_GEN_CNTRLS_MST_RUNNING_BYTE_CNT_t; 2296 2297 typedef union { 2298 uint32_t data; 2299 struct { 2300 #if IS_BIG_ENDIAN 2301 uint32_t reserved : 16; 2302 uint32_t slv_running_byte_cnt_val : 16; /* FUR_GEN_CNTRLS_slv_running_byte_cnt_t[15:00] - WO */ 2303 #endif /* IS_BIG_ENDIAN */ 2304 #if IS_LITTLE_ENDIAN 2305 uint32_t slv_running_byte_cnt_val : 16; /* FUR_GEN_CNTRLS_slv_running_byte_cnt_t[15:00] - WO */ 2306 uint32_t reserved : 16; 2307 #endif /* IS_LITTLE_ENDIAN */ 2308 } fields; 2309 } FUR_GEN_CNTRLS_slv_running_byte_cnt_t; 2310 2311 typedef FUR_GEN_CNTRLS_slv_running_byte_cnt_t FUR_GEN_CNTRLS_SLV_RUNNING_BYTE_CNT_t; 2312 2313 typedef union { 2314 uint32_t data; 2315 struct { 2316 #if IS_BIG_ENDIAN 2317 uint32_t reserved : 16; 2318 uint32_t firmware_version_val : 16; /* FUR_GEN_CNTRLS_firmware_version_t[15:00] - WO */ 2319 #endif /* IS_BIG_ENDIAN */ 2320 #if IS_LITTLE_ENDIAN 2321 uint32_t firmware_version_val : 16; /* FUR_GEN_CNTRLS_firmware_version_t[15:00] - WO */ 2322 uint32_t reserved : 16; 2323 #endif /* IS_LITTLE_ENDIAN */ 2324 } fields; 2325 } FUR_GEN_CNTRLS_firmware_version_t; 2326 2327 typedef FUR_GEN_CNTRLS_firmware_version_t FUR_GEN_CNTRLS_FIRMWARE_VERSION_t; 2328 2329 typedef union { 2330 uint32_t data; 2331 struct { 2332 #if IS_BIG_ENDIAN 2333 uint32_t reserved : 16; 2334 uint32_t reserved_01 : 15; /* FUR_GEN_CNTRLS_firmware_enable_t[15:01] - RSVD */ 2335 uint32_t fw_enable_val : 1; /* FUR_GEN_CNTRLS_firmware_enable_t[00] - WO */ 2336 #endif /* IS_BIG_ENDIAN */ 2337 #if IS_LITTLE_ENDIAN 2338 uint32_t fw_enable_val : 1; /* FUR_GEN_CNTRLS_firmware_enable_t[00] - WO */ 2339 uint32_t reserved_01 : 15; /* FUR_GEN_CNTRLS_firmware_enable_t[15:01] - RSVD */ 2340 uint32_t reserved : 16; 2341 #endif /* IS_LITTLE_ENDIAN */ 2342 } fields; 2343 } FUR_GEN_CNTRLS_firmware_enable_t; 2344 2345 typedef FUR_GEN_CNTRLS_firmware_enable_t FUR_GEN_CNTRLS_FIRMWARE_ENABLE_t; 2346 2347 2348 /*-----------------------------------------------*/ 2349 /* Structs for FUR_MICRO_BOOT Bank */ 2350 /*-----------------------------------------------*/ 2351 typedef union { 2352 uint32_t data; 2353 struct { 2354 #if IS_BIG_ENDIAN 2355 uint32_t reserved : 16; 2356 uint32_t spi_port_used : 1; /* FUR_MICRO_BOOT_boot_por_t[15] - WO */ 2357 uint32_t serboot : 1; /* FUR_MICRO_BOOT_boot_por_t[14] - WO */ 2358 uint32_t mst_dwld_done : 1; /* FUR_MICRO_BOOT_boot_por_t[13] - WO */ 2359 uint32_t slv_dwld_done : 1; /* FUR_MICRO_BOOT_boot_por_t[12] - WO */ 2360 uint32_t reserved_11 : 1; /* FUR_MICRO_BOOT_boot_por_t[11] - RSVD */ 2361 uint32_t reserved_08 : 3; /* FUR_MICRO_BOOT_boot_por_t[10:08] - RSVD */ 2362 uint32_t reserved_00 : 8; /* FUR_MICRO_BOOT_boot_por_t[07:00] - RSVD */ 2363 #endif /* IS_BIG_ENDIAN */ 2364 #if IS_LITTLE_ENDIAN 2365 uint32_t reserved_00 : 8; /* FUR_MICRO_BOOT_boot_por_t[07:00] - RSVD */ 2366 uint32_t reserved_08 : 3; /* FUR_MICRO_BOOT_boot_por_t[10:08] - RSVD */ 2367 uint32_t reserved_11 : 1; /* FUR_MICRO_BOOT_boot_por_t[11] - RSVD */ 2368 uint32_t slv_dwld_done : 1; /* FUR_MICRO_BOOT_boot_por_t[12] - WO */ 2369 uint32_t mst_dwld_done : 1; /* FUR_MICRO_BOOT_boot_por_t[13] - WO */ 2370 uint32_t serboot : 1; /* FUR_MICRO_BOOT_boot_por_t[14] - WO */ 2371 uint32_t spi_port_used : 1; /* FUR_MICRO_BOOT_boot_por_t[15] - WO */ 2372 uint32_t reserved : 16; 2373 #endif /* IS_LITTLE_ENDIAN */ 2374 } fields; 2375 } FUR_MICRO_BOOT_boot_por_t; 2376 2377 typedef FUR_MICRO_BOOT_boot_por_t FUR_MICRO_BOOT_BOOT_POR_t; 2378 2379 2380 /*-----------------------------------------------*/ 2381 /* Structs for FUR_MODULE_CNTRL Bank */ 2382 /*-----------------------------------------------*/ 2383 typedef union { 2384 uint32_t data; 2385 struct { 2386 #if IS_BIG_ENDIAN 2387 uint32_t reserved : 16; 2388 uint32_t i2c_en : 1; /* FUR_MODULE_CNTRL_CONTROL_t[15] - WO */ 2389 uint32_t i2cflush : 1; /* FUR_MODULE_CNTRL_CONTROL_t[14] - WO */ 2390 uint32_t sl_add_cnt : 1; /* FUR_MODULE_CNTRL_CONTROL_t[13] - WO */ 2391 uint32_t sl_dat_cnt : 1; /* FUR_MODULE_CNTRL_CONTROL_t[12] - WO */ 2392 uint32_t reserved_06 : 6; /* FUR_MODULE_CNTRL_CONTROL_t[11:06] - RSVD */ 2393 uint32_t slave_cmd : 1; /* FUR_MODULE_CNTRL_CONTROL_t[05] - WO */ 2394 uint32_t reserved_02 : 3; /* FUR_MODULE_CNTRL_CONTROL_t[04:02] - RSVD */ 2395 uint32_t extend_cmd : 2; /* FUR_MODULE_CNTRL_CONTROL_t[01:00] - WO */ 2396 #endif /* IS_BIG_ENDIAN */ 2397 #if IS_LITTLE_ENDIAN 2398 uint32_t extend_cmd : 2; /* FUR_MODULE_CNTRL_CONTROL_t[01:00] - WO */ 2399 uint32_t reserved_02 : 3; /* FUR_MODULE_CNTRL_CONTROL_t[04:02] - RSVD */ 2400 uint32_t slave_cmd : 1; /* FUR_MODULE_CNTRL_CONTROL_t[05] - WO */ 2401 uint32_t reserved_06 : 6; /* FUR_MODULE_CNTRL_CONTROL_t[11:06] - RSVD */ 2402 uint32_t sl_dat_cnt : 1; /* FUR_MODULE_CNTRL_CONTROL_t[12] - WO */ 2403 uint32_t sl_add_cnt : 1; /* FUR_MODULE_CNTRL_CONTROL_t[13] - WO */ 2404 uint32_t i2cflush : 1; /* FUR_MODULE_CNTRL_CONTROL_t[14] - WO */ 2405 uint32_t i2c_en : 1; /* FUR_MODULE_CNTRL_CONTROL_t[15] - WO */ 2406 uint32_t reserved : 16; 2407 #endif /* IS_LITTLE_ENDIAN */ 2408 } fields; 2409 } FUR_MODULE_CNTRL_CONTROL_t; 2410 2411 2412 typedef union { 2413 uint32_t data; 2414 struct { 2415 #if IS_BIG_ENDIAN 2416 uint32_t reserved : 16; 2417 uint32_t reserved_03 : 13; /* FUR_MODULE_CNTRL_STATUS_t[15:03] - RSVD */ 2418 uint32_t i2cm_stat : 2; /* FUR_MODULE_CNTRL_STATUS_t[02:01] - RO */ 2419 uint32_t xaction_done : 1; /* FUR_MODULE_CNTRL_STATUS_t[00] - RO */ 2420 #endif /* IS_BIG_ENDIAN */ 2421 #if IS_LITTLE_ENDIAN 2422 uint32_t xaction_done : 1; /* FUR_MODULE_CNTRL_STATUS_t[00] - RO */ 2423 uint32_t i2cm_stat : 2; /* FUR_MODULE_CNTRL_STATUS_t[02:01] - RO */ 2424 uint32_t reserved_03 : 13; /* FUR_MODULE_CNTRL_STATUS_t[15:03] - RSVD */ 2425 uint32_t reserved : 16; 2426 #endif /* IS_LITTLE_ENDIAN */ 2427 } fields; 2428 } FUR_MODULE_CNTRL_STATUS_t; 2429 2430 2431 typedef union { 2432 uint32_t data; 2433 struct { 2434 #if IS_BIG_ENDIAN 2435 uint32_t reserved : 16; 2436 uint32_t reserved_13 : 3; /* FUR_MODULE_CNTRL_XFER_COUNT_t[15:13] - RSVD */ 2437 uint32_t chk_live_status : 1; /* FUR_MODULE_CNTRL_XFER_COUNT_t[12] - WO */ 2438 uint32_t page_2ld : 4; /* FUR_MODULE_CNTRL_XFER_COUNT_t[11:08] - WO */ 2439 uint32_t xfer_cnt : 8; /* FUR_MODULE_CNTRL_XFER_COUNT_t[07:00] - WO */ 2440 #endif /* IS_BIG_ENDIAN */ 2441 #if IS_LITTLE_ENDIAN 2442 uint32_t xfer_cnt : 8; /* FUR_MODULE_CNTRL_XFER_COUNT_t[07:00] - WO */ 2443 uint32_t page_2ld : 4; /* FUR_MODULE_CNTRL_XFER_COUNT_t[11:08] - WO */ 2444 uint32_t chk_live_status : 1; /* FUR_MODULE_CNTRL_XFER_COUNT_t[12] - WO */ 2445 uint32_t reserved_13 : 3; /* FUR_MODULE_CNTRL_XFER_COUNT_t[15:13] - RSVD */ 2446 uint32_t reserved : 16; 2447 #endif /* IS_LITTLE_ENDIAN */ 2448 } fields; 2449 } FUR_MODULE_CNTRL_XFER_COUNT_t; 2450 2451 2452 typedef union { 2453 uint32_t data; 2454 struct { 2455 #if IS_BIG_ENDIAN 2456 uint32_t reserved : 16; 2457 uint32_t slave_addr : 16; /* FUR_MODULE_CNTRL_ADDRESS_t[15:00] - WO */ 2458 #endif /* IS_BIG_ENDIAN */ 2459 #if IS_LITTLE_ENDIAN 2460 uint32_t slave_addr : 16; /* FUR_MODULE_CNTRL_ADDRESS_t[15:00] - WO */ 2461 uint32_t reserved : 16; 2462 #endif /* IS_LITTLE_ENDIAN */ 2463 } fields; 2464 } FUR_MODULE_CNTRL_ADDRESS_t; 2465 2466 2467 typedef union { 2468 uint32_t data; 2469 struct { 2470 #if IS_BIG_ENDIAN 2471 uint32_t reserved : 16; 2472 uint32_t xfer_addr : 16; /* FUR_MODULE_CNTRL_XFER_ADDR_t[15:00] - WO */ 2473 #endif /* IS_BIG_ENDIAN */ 2474 #if IS_LITTLE_ENDIAN 2475 uint32_t xfer_addr : 16; /* FUR_MODULE_CNTRL_XFER_ADDR_t[15:00] - WO */ 2476 uint32_t reserved : 16; 2477 #endif /* IS_LITTLE_ENDIAN */ 2478 } fields; 2479 } FUR_MODULE_CNTRL_XFER_ADDR_t; 2480 2481 2482 typedef union { 2483 uint32_t data; 2484 struct { 2485 #if IS_BIG_ENDIAN 2486 uint32_t reserved : 16; 2487 uint32_t sl_dev_add : 7; /* FUR_MODULE_CNTRL_DEV_ID_t[15:09] - WO */ 2488 uint32_t i2c_speed : 1; /* FUR_MODULE_CNTRL_DEV_ID_t[08] - WO */ 2489 uint32_t slave_addr_msb : 8; /* FUR_MODULE_CNTRL_DEV_ID_t[07:00] - WO */ 2490 #endif /* IS_BIG_ENDIAN */ 2491 #if IS_LITTLE_ENDIAN 2492 uint32_t slave_addr_msb : 8; /* FUR_MODULE_CNTRL_DEV_ID_t[07:00] - WO */ 2493 uint32_t i2c_speed : 1; /* FUR_MODULE_CNTRL_DEV_ID_t[08] - WO */ 2494 uint32_t sl_dev_add : 7; /* FUR_MODULE_CNTRL_DEV_ID_t[15:09] - WO */ 2495 uint32_t reserved : 16; 2496 #endif /* IS_LITTLE_ENDIAN */ 2497 } fields; 2498 } FUR_MODULE_CNTRL_DEV_ID_t; 2499 2500 2501 2502 /*-----------------------------------------------*/ 2503 /* Structs for FUR_MODULE_CNTRL_RAM Bank */ 2504 /*-----------------------------------------------*/ 2505 typedef union { 2506 uint32_t data; 2507 struct { 2508 #if IS_BIG_ENDIAN 2509 uint32_t reserved : 16; 2510 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR0_t[15:08] - RSVD */ 2511 uint32_t nvr0 : 8; /* FUR_MODULE_CNTRL_RAM_NVR0_t[07:00] - WO */ 2512 #endif /* IS_BIG_ENDIAN */ 2513 #if IS_LITTLE_ENDIAN 2514 uint32_t nvr0 : 8; /* FUR_MODULE_CNTRL_RAM_NVR0_t[07:00] - WO */ 2515 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR0_t[15:08] - RSVD */ 2516 uint32_t reserved : 16; 2517 #endif /* IS_LITTLE_ENDIAN */ 2518 } fields; 2519 } FUR_MODULE_CNTRL_RAM_NVR0_t; 2520 2521 2522 typedef union { 2523 uint32_t data; 2524 struct { 2525 #if IS_BIG_ENDIAN 2526 uint32_t reserved : 16; 2527 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR1_t[15:08] - RSVD */ 2528 uint32_t nvr1 : 8; /* FUR_MODULE_CNTRL_RAM_NVR1_t[07:00] - WO */ 2529 #endif /* IS_BIG_ENDIAN */ 2530 #if IS_LITTLE_ENDIAN 2531 uint32_t nvr1 : 8; /* FUR_MODULE_CNTRL_RAM_NVR1_t[07:00] - WO */ 2532 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR1_t[15:08] - RSVD */ 2533 uint32_t reserved : 16; 2534 #endif /* IS_LITTLE_ENDIAN */ 2535 } fields; 2536 } FUR_MODULE_CNTRL_RAM_NVR1_t; 2537 2538 2539 typedef union { 2540 uint32_t data; 2541 struct { 2542 #if IS_BIG_ENDIAN 2543 uint32_t reserved : 16; 2544 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR2_t[15:08] - RSVD */ 2545 uint32_t nvr2 : 8; /* FUR_MODULE_CNTRL_RAM_NVR2_t[07:00] - WO */ 2546 #endif /* IS_BIG_ENDIAN */ 2547 #if IS_LITTLE_ENDIAN 2548 uint32_t nvr2 : 8; /* FUR_MODULE_CNTRL_RAM_NVR2_t[07:00] - WO */ 2549 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR2_t[15:08] - RSVD */ 2550 uint32_t reserved : 16; 2551 #endif /* IS_LITTLE_ENDIAN */ 2552 } fields; 2553 } FUR_MODULE_CNTRL_RAM_NVR2_t; 2554 2555 2556 typedef union { 2557 uint32_t data; 2558 struct { 2559 #if IS_BIG_ENDIAN 2560 uint32_t reserved : 16; 2561 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR3_t[15:08] - RSVD */ 2562 uint32_t nvr3 : 8; /* FUR_MODULE_CNTRL_RAM_NVR3_t[07:00] - WO */ 2563 #endif /* IS_BIG_ENDIAN */ 2564 #if IS_LITTLE_ENDIAN 2565 uint32_t nvr3 : 8; /* FUR_MODULE_CNTRL_RAM_NVR3_t[07:00] - WO */ 2566 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR3_t[15:08] - RSVD */ 2567 uint32_t reserved : 16; 2568 #endif /* IS_LITTLE_ENDIAN */ 2569 } fields; 2570 } FUR_MODULE_CNTRL_RAM_NVR3_t; 2571 2572 2573 typedef union { 2574 uint32_t data; 2575 struct { 2576 #if IS_BIG_ENDIAN 2577 uint32_t reserved : 16; 2578 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR4_t[15:08] - RSVD */ 2579 uint32_t nvr4 : 8; /* FUR_MODULE_CNTRL_RAM_NVR4_t[07:00] - WO */ 2580 #endif /* IS_BIG_ENDIAN */ 2581 #if IS_LITTLE_ENDIAN 2582 uint32_t nvr4 : 8; /* FUR_MODULE_CNTRL_RAM_NVR4_t[07:00] - WO */ 2583 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR4_t[15:08] - RSVD */ 2584 uint32_t reserved : 16; 2585 #endif /* IS_LITTLE_ENDIAN */ 2586 } fields; 2587 } FUR_MODULE_CNTRL_RAM_NVR4_t; 2588 2589 2590 typedef union { 2591 uint32_t data; 2592 struct { 2593 #if IS_BIG_ENDIAN 2594 uint32_t reserved : 16; 2595 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR5_t[15:08] - RSVD */ 2596 uint32_t nvr5 : 8; /* FUR_MODULE_CNTRL_RAM_NVR5_t[07:00] - WO */ 2597 #endif /* IS_BIG_ENDIAN */ 2598 #if IS_LITTLE_ENDIAN 2599 uint32_t nvr5 : 8; /* FUR_MODULE_CNTRL_RAM_NVR5_t[07:00] - WO */ 2600 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR5_t[15:08] - RSVD */ 2601 uint32_t reserved : 16; 2602 #endif /* IS_LITTLE_ENDIAN */ 2603 } fields; 2604 } FUR_MODULE_CNTRL_RAM_NVR5_t; 2605 2606 2607 typedef union { 2608 uint32_t data; 2609 struct { 2610 #if IS_BIG_ENDIAN 2611 uint32_t reserved : 16; 2612 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR6_t[15:08] - RSVD */ 2613 uint32_t nvr6 : 8; /* FUR_MODULE_CNTRL_RAM_NVR6_t[07:00] - WO */ 2614 #endif /* IS_BIG_ENDIAN */ 2615 #if IS_LITTLE_ENDIAN 2616 uint32_t nvr6 : 8; /* FUR_MODULE_CNTRL_RAM_NVR6_t[07:00] - WO */ 2617 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR6_t[15:08] - RSVD */ 2618 uint32_t reserved : 16; 2619 #endif /* IS_LITTLE_ENDIAN */ 2620 } fields; 2621 } FUR_MODULE_CNTRL_RAM_NVR6_t; 2622 2623 2624 typedef union { 2625 uint32_t data; 2626 struct { 2627 #if IS_BIG_ENDIAN 2628 uint32_t reserved : 16; 2629 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR7_t[15:08] - RSVD */ 2630 uint32_t nvr7 : 8; /* FUR_MODULE_CNTRL_RAM_NVR7_t[07:00] - WO */ 2631 #endif /* IS_BIG_ENDIAN */ 2632 #if IS_LITTLE_ENDIAN 2633 uint32_t nvr7 : 8; /* FUR_MODULE_CNTRL_RAM_NVR7_t[07:00] - WO */ 2634 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR7_t[15:08] - RSVD */ 2635 uint32_t reserved : 16; 2636 #endif /* IS_LITTLE_ENDIAN */ 2637 } fields; 2638 } FUR_MODULE_CNTRL_RAM_NVR7_t; 2639 2640 2641 typedef union { 2642 uint32_t data; 2643 struct { 2644 #if IS_BIG_ENDIAN 2645 uint32_t reserved : 16; 2646 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR8_t[15:08] - RSVD */ 2647 uint32_t nvr8 : 8; /* FUR_MODULE_CNTRL_RAM_NVR8_t[07:00] - WO */ 2648 #endif /* IS_BIG_ENDIAN */ 2649 #if IS_LITTLE_ENDIAN 2650 uint32_t nvr8 : 8; /* FUR_MODULE_CNTRL_RAM_NVR8_t[07:00] - WO */ 2651 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR8_t[15:08] - RSVD */ 2652 uint32_t reserved : 16; 2653 #endif /* IS_LITTLE_ENDIAN */ 2654 } fields; 2655 } FUR_MODULE_CNTRL_RAM_NVR8_t; 2656 2657 2658 typedef union { 2659 uint32_t data; 2660 struct { 2661 #if IS_BIG_ENDIAN 2662 uint32_t reserved : 16; 2663 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR9_t[15:08] - RSVD */ 2664 uint32_t nvr9 : 8; /* FUR_MODULE_CNTRL_RAM_NVR9_t[07:00] - WO */ 2665 #endif /* IS_BIG_ENDIAN */ 2666 #if IS_LITTLE_ENDIAN 2667 uint32_t nvr9 : 8; /* FUR_MODULE_CNTRL_RAM_NVR9_t[07:00] - WO */ 2668 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR9_t[15:08] - RSVD */ 2669 uint32_t reserved : 16; 2670 #endif /* IS_LITTLE_ENDIAN */ 2671 } fields; 2672 } FUR_MODULE_CNTRL_RAM_NVR9_t; 2673 2674 2675 typedef union { 2676 uint32_t data; 2677 struct { 2678 #if IS_BIG_ENDIAN 2679 uint32_t reserved : 16; 2680 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR10_t[15:08] - RSVD */ 2681 uint32_t nvr10 : 8; /* FUR_MODULE_CNTRL_RAM_NVR10_t[07:00] - WO */ 2682 #endif /* IS_BIG_ENDIAN */ 2683 #if IS_LITTLE_ENDIAN 2684 uint32_t nvr10 : 8; /* FUR_MODULE_CNTRL_RAM_NVR10_t[07:00] - WO */ 2685 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR10_t[15:08] - RSVD */ 2686 uint32_t reserved : 16; 2687 #endif /* IS_LITTLE_ENDIAN */ 2688 } fields; 2689 } FUR_MODULE_CNTRL_RAM_NVR10_t; 2690 2691 2692 typedef union { 2693 uint32_t data; 2694 struct { 2695 #if IS_BIG_ENDIAN 2696 uint32_t reserved : 16; 2697 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR11_t[15:08] - RSVD */ 2698 uint32_t nvr11 : 8; /* FUR_MODULE_CNTRL_RAM_NVR11_t[07:00] - WO */ 2699 #endif /* IS_BIG_ENDIAN */ 2700 #if IS_LITTLE_ENDIAN 2701 uint32_t nvr11 : 8; /* FUR_MODULE_CNTRL_RAM_NVR11_t[07:00] - WO */ 2702 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR11_t[15:08] - RSVD */ 2703 uint32_t reserved : 16; 2704 #endif /* IS_LITTLE_ENDIAN */ 2705 } fields; 2706 } FUR_MODULE_CNTRL_RAM_NVR11_t; 2707 2708 2709 typedef union { 2710 uint32_t data; 2711 struct { 2712 #if IS_BIG_ENDIAN 2713 uint32_t reserved : 16; 2714 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR12_t[15:08] - RSVD */ 2715 uint32_t nvr12 : 8; /* FUR_MODULE_CNTRL_RAM_NVR12_t[07:00] - WO */ 2716 #endif /* IS_BIG_ENDIAN */ 2717 #if IS_LITTLE_ENDIAN 2718 uint32_t nvr12 : 8; /* FUR_MODULE_CNTRL_RAM_NVR12_t[07:00] - WO */ 2719 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR12_t[15:08] - RSVD */ 2720 uint32_t reserved : 16; 2721 #endif /* IS_LITTLE_ENDIAN */ 2722 } fields; 2723 } FUR_MODULE_CNTRL_RAM_NVR12_t; 2724 2725 2726 typedef union { 2727 uint32_t data; 2728 struct { 2729 #if IS_BIG_ENDIAN 2730 uint32_t reserved : 16; 2731 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR13_t[15:08] - RSVD */ 2732 uint32_t nvr13 : 8; /* FUR_MODULE_CNTRL_RAM_NVR13_t[07:00] - WO */ 2733 #endif /* IS_BIG_ENDIAN */ 2734 #if IS_LITTLE_ENDIAN 2735 uint32_t nvr13 : 8; /* FUR_MODULE_CNTRL_RAM_NVR13_t[07:00] - WO */ 2736 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR13_t[15:08] - RSVD */ 2737 uint32_t reserved : 16; 2738 #endif /* IS_LITTLE_ENDIAN */ 2739 } fields; 2740 } FUR_MODULE_CNTRL_RAM_NVR13_t; 2741 2742 2743 typedef union { 2744 uint32_t data; 2745 struct { 2746 #if IS_BIG_ENDIAN 2747 uint32_t reserved : 16; 2748 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR14_t[15:08] - RSVD */ 2749 uint32_t nvr14 : 8; /* FUR_MODULE_CNTRL_RAM_NVR14_t[07:00] - WO */ 2750 #endif /* IS_BIG_ENDIAN */ 2751 #if IS_LITTLE_ENDIAN 2752 uint32_t nvr14 : 8; /* FUR_MODULE_CNTRL_RAM_NVR14_t[07:00] - WO */ 2753 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR14_t[15:08] - RSVD */ 2754 uint32_t reserved : 16; 2755 #endif /* IS_LITTLE_ENDIAN */ 2756 } fields; 2757 } FUR_MODULE_CNTRL_RAM_NVR14_t; 2758 2759 2760 typedef union { 2761 uint32_t data; 2762 struct { 2763 #if IS_BIG_ENDIAN 2764 uint32_t reserved : 16; 2765 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR15_t[15:08] - RSVD */ 2766 uint32_t nvr15 : 8; /* FUR_MODULE_CNTRL_RAM_NVR15_t[07:00] - WO */ 2767 #endif /* IS_BIG_ENDIAN */ 2768 #if IS_LITTLE_ENDIAN 2769 uint32_t nvr15 : 8; /* FUR_MODULE_CNTRL_RAM_NVR15_t[07:00] - WO */ 2770 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR15_t[15:08] - RSVD */ 2771 uint32_t reserved : 16; 2772 #endif /* IS_LITTLE_ENDIAN */ 2773 } fields; 2774 } FUR_MODULE_CNTRL_RAM_NVR15_t; 2775 2776 2777 typedef union { 2778 uint32_t data; 2779 struct { 2780 #if IS_BIG_ENDIAN 2781 uint32_t reserved : 16; 2782 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR16_t[15:08] - RSVD */ 2783 uint32_t nvr16 : 8; /* FUR_MODULE_CNTRL_RAM_NVR16_t[07:00] - WO */ 2784 #endif /* IS_BIG_ENDIAN */ 2785 #if IS_LITTLE_ENDIAN 2786 uint32_t nvr16 : 8; /* FUR_MODULE_CNTRL_RAM_NVR16_t[07:00] - WO */ 2787 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR16_t[15:08] - RSVD */ 2788 uint32_t reserved : 16; 2789 #endif /* IS_LITTLE_ENDIAN */ 2790 } fields; 2791 } FUR_MODULE_CNTRL_RAM_NVR16_t; 2792 2793 2794 typedef union { 2795 uint32_t data; 2796 struct { 2797 #if IS_BIG_ENDIAN 2798 uint32_t reserved : 16; 2799 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR17_t[15:08] - RSVD */ 2800 uint32_t nvr17 : 8; /* FUR_MODULE_CNTRL_RAM_NVR17_t[07:00] - WO */ 2801 #endif /* IS_BIG_ENDIAN */ 2802 #if IS_LITTLE_ENDIAN 2803 uint32_t nvr17 : 8; /* FUR_MODULE_CNTRL_RAM_NVR17_t[07:00] - WO */ 2804 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR17_t[15:08] - RSVD */ 2805 uint32_t reserved : 16; 2806 #endif /* IS_LITTLE_ENDIAN */ 2807 } fields; 2808 } FUR_MODULE_CNTRL_RAM_NVR17_t; 2809 2810 2811 typedef union { 2812 uint32_t data; 2813 struct { 2814 #if IS_BIG_ENDIAN 2815 uint32_t reserved : 16; 2816 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR18_t[15:08] - RSVD */ 2817 uint32_t nvr18 : 8; /* FUR_MODULE_CNTRL_RAM_NVR18_t[07:00] - WO */ 2818 #endif /* IS_BIG_ENDIAN */ 2819 #if IS_LITTLE_ENDIAN 2820 uint32_t nvr18 : 8; /* FUR_MODULE_CNTRL_RAM_NVR18_t[07:00] - WO */ 2821 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR18_t[15:08] - RSVD */ 2822 uint32_t reserved : 16; 2823 #endif /* IS_LITTLE_ENDIAN */ 2824 } fields; 2825 } FUR_MODULE_CNTRL_RAM_NVR18_t; 2826 2827 2828 typedef union { 2829 uint32_t data; 2830 struct { 2831 #if IS_BIG_ENDIAN 2832 uint32_t reserved : 16; 2833 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR19_t[15:08] - RSVD */ 2834 uint32_t nvr19 : 8; /* FUR_MODULE_CNTRL_RAM_NVR19_t[07:00] - WO */ 2835 #endif /* IS_BIG_ENDIAN */ 2836 #if IS_LITTLE_ENDIAN 2837 uint32_t nvr19 : 8; /* FUR_MODULE_CNTRL_RAM_NVR19_t[07:00] - WO */ 2838 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR19_t[15:08] - RSVD */ 2839 uint32_t reserved : 16; 2840 #endif /* IS_LITTLE_ENDIAN */ 2841 } fields; 2842 } FUR_MODULE_CNTRL_RAM_NVR19_t; 2843 2844 2845 typedef union { 2846 uint32_t data; 2847 struct { 2848 #if IS_BIG_ENDIAN 2849 uint32_t reserved : 16; 2850 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR20_t[15:08] - RSVD */ 2851 uint32_t nvr20 : 8; /* FUR_MODULE_CNTRL_RAM_NVR20_t[07:00] - WO */ 2852 #endif /* IS_BIG_ENDIAN */ 2853 #if IS_LITTLE_ENDIAN 2854 uint32_t nvr20 : 8; /* FUR_MODULE_CNTRL_RAM_NVR20_t[07:00] - WO */ 2855 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR20_t[15:08] - RSVD */ 2856 uint32_t reserved : 16; 2857 #endif /* IS_LITTLE_ENDIAN */ 2858 } fields; 2859 } FUR_MODULE_CNTRL_RAM_NVR20_t; 2860 2861 2862 typedef union { 2863 uint32_t data; 2864 struct { 2865 #if IS_BIG_ENDIAN 2866 uint32_t reserved : 16; 2867 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR21_t[15:08] - RSVD */ 2868 uint32_t nvr21 : 8; /* FUR_MODULE_CNTRL_RAM_NVR21_t[07:00] - WO */ 2869 #endif /* IS_BIG_ENDIAN */ 2870 #if IS_LITTLE_ENDIAN 2871 uint32_t nvr21 : 8; /* FUR_MODULE_CNTRL_RAM_NVR21_t[07:00] - WO */ 2872 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR21_t[15:08] - RSVD */ 2873 uint32_t reserved : 16; 2874 #endif /* IS_LITTLE_ENDIAN */ 2875 } fields; 2876 } FUR_MODULE_CNTRL_RAM_NVR21_t; 2877 2878 2879 typedef union { 2880 uint32_t data; 2881 struct { 2882 #if IS_BIG_ENDIAN 2883 uint32_t reserved : 16; 2884 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR22_t[15:08] - RSVD */ 2885 uint32_t nvr22 : 8; /* FUR_MODULE_CNTRL_RAM_NVR22_t[07:00] - WO */ 2886 #endif /* IS_BIG_ENDIAN */ 2887 #if IS_LITTLE_ENDIAN 2888 uint32_t nvr22 : 8; /* FUR_MODULE_CNTRL_RAM_NVR22_t[07:00] - WO */ 2889 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR22_t[15:08] - RSVD */ 2890 uint32_t reserved : 16; 2891 #endif /* IS_LITTLE_ENDIAN */ 2892 } fields; 2893 } FUR_MODULE_CNTRL_RAM_NVR22_t; 2894 2895 2896 typedef union { 2897 uint32_t data; 2898 struct { 2899 #if IS_BIG_ENDIAN 2900 uint32_t reserved : 16; 2901 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR23_t[15:08] - RSVD */ 2902 uint32_t nvr23 : 8; /* FUR_MODULE_CNTRL_RAM_NVR23_t[07:00] - WO */ 2903 #endif /* IS_BIG_ENDIAN */ 2904 #if IS_LITTLE_ENDIAN 2905 uint32_t nvr23 : 8; /* FUR_MODULE_CNTRL_RAM_NVR23_t[07:00] - WO */ 2906 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR23_t[15:08] - RSVD */ 2907 uint32_t reserved : 16; 2908 #endif /* IS_LITTLE_ENDIAN */ 2909 } fields; 2910 } FUR_MODULE_CNTRL_RAM_NVR23_t; 2911 2912 2913 typedef union { 2914 uint32_t data; 2915 struct { 2916 #if IS_BIG_ENDIAN 2917 uint32_t reserved : 16; 2918 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR24_t[15:08] - RSVD */ 2919 uint32_t nvr24 : 8; /* FUR_MODULE_CNTRL_RAM_NVR24_t[07:00] - WO */ 2920 #endif /* IS_BIG_ENDIAN */ 2921 #if IS_LITTLE_ENDIAN 2922 uint32_t nvr24 : 8; /* FUR_MODULE_CNTRL_RAM_NVR24_t[07:00] - WO */ 2923 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR24_t[15:08] - RSVD */ 2924 uint32_t reserved : 16; 2925 #endif /* IS_LITTLE_ENDIAN */ 2926 } fields; 2927 } FUR_MODULE_CNTRL_RAM_NVR24_t; 2928 2929 2930 typedef union { 2931 uint32_t data; 2932 struct { 2933 #if IS_BIG_ENDIAN 2934 uint32_t reserved : 16; 2935 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR25_t[15:08] - RSVD */ 2936 uint32_t nvr25 : 8; /* FUR_MODULE_CNTRL_RAM_NVR25_t[07:00] - WO */ 2937 #endif /* IS_BIG_ENDIAN */ 2938 #if IS_LITTLE_ENDIAN 2939 uint32_t nvr25 : 8; /* FUR_MODULE_CNTRL_RAM_NVR25_t[07:00] - WO */ 2940 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR25_t[15:08] - RSVD */ 2941 uint32_t reserved : 16; 2942 #endif /* IS_LITTLE_ENDIAN */ 2943 } fields; 2944 } FUR_MODULE_CNTRL_RAM_NVR25_t; 2945 2946 2947 typedef union { 2948 uint32_t data; 2949 struct { 2950 #if IS_BIG_ENDIAN 2951 uint32_t reserved : 16; 2952 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR26_t[15:08] - RSVD */ 2953 uint32_t nvr26 : 8; /* FUR_MODULE_CNTRL_RAM_NVR26_t[07:00] - WO */ 2954 #endif /* IS_BIG_ENDIAN */ 2955 #if IS_LITTLE_ENDIAN 2956 uint32_t nvr26 : 8; /* FUR_MODULE_CNTRL_RAM_NVR26_t[07:00] - WO */ 2957 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR26_t[15:08] - RSVD */ 2958 uint32_t reserved : 16; 2959 #endif /* IS_LITTLE_ENDIAN */ 2960 } fields; 2961 } FUR_MODULE_CNTRL_RAM_NVR26_t; 2962 2963 2964 typedef union { 2965 uint32_t data; 2966 struct { 2967 #if IS_BIG_ENDIAN 2968 uint32_t reserved : 16; 2969 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR27_t[15:08] - RSVD */ 2970 uint32_t nvr27 : 8; /* FUR_MODULE_CNTRL_RAM_NVR27_t[07:00] - WO */ 2971 #endif /* IS_BIG_ENDIAN */ 2972 #if IS_LITTLE_ENDIAN 2973 uint32_t nvr27 : 8; /* FUR_MODULE_CNTRL_RAM_NVR27_t[07:00] - WO */ 2974 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR27_t[15:08] - RSVD */ 2975 uint32_t reserved : 16; 2976 #endif /* IS_LITTLE_ENDIAN */ 2977 } fields; 2978 } FUR_MODULE_CNTRL_RAM_NVR27_t; 2979 2980 2981 typedef union { 2982 uint32_t data; 2983 struct { 2984 #if IS_BIG_ENDIAN 2985 uint32_t reserved : 16; 2986 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR28_t[15:08] - RSVD */ 2987 uint32_t nvr28 : 8; /* FUR_MODULE_CNTRL_RAM_NVR28_t[07:00] - WO */ 2988 #endif /* IS_BIG_ENDIAN */ 2989 #if IS_LITTLE_ENDIAN 2990 uint32_t nvr28 : 8; /* FUR_MODULE_CNTRL_RAM_NVR28_t[07:00] - WO */ 2991 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR28_t[15:08] - RSVD */ 2992 uint32_t reserved : 16; 2993 #endif /* IS_LITTLE_ENDIAN */ 2994 } fields; 2995 } FUR_MODULE_CNTRL_RAM_NVR28_t; 2996 2997 2998 typedef union { 2999 uint32_t data; 3000 struct { 3001 #if IS_BIG_ENDIAN 3002 uint32_t reserved : 16; 3003 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR29_t[15:08] - RSVD */ 3004 uint32_t nvr29 : 8; /* FUR_MODULE_CNTRL_RAM_NVR29_t[07:00] - WO */ 3005 #endif /* IS_BIG_ENDIAN */ 3006 #if IS_LITTLE_ENDIAN 3007 uint32_t nvr29 : 8; /* FUR_MODULE_CNTRL_RAM_NVR29_t[07:00] - WO */ 3008 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR29_t[15:08] - RSVD */ 3009 uint32_t reserved : 16; 3010 #endif /* IS_LITTLE_ENDIAN */ 3011 } fields; 3012 } FUR_MODULE_CNTRL_RAM_NVR29_t; 3013 3014 3015 typedef union { 3016 uint32_t data; 3017 struct { 3018 #if IS_BIG_ENDIAN 3019 uint32_t reserved : 16; 3020 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR30_t[15:08] - RSVD */ 3021 uint32_t nvr30 : 8; /* FUR_MODULE_CNTRL_RAM_NVR30_t[07:00] - WO */ 3022 #endif /* IS_BIG_ENDIAN */ 3023 #if IS_LITTLE_ENDIAN 3024 uint32_t nvr30 : 8; /* FUR_MODULE_CNTRL_RAM_NVR30_t[07:00] - WO */ 3025 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR30_t[15:08] - RSVD */ 3026 uint32_t reserved : 16; 3027 #endif /* IS_LITTLE_ENDIAN */ 3028 } fields; 3029 } FUR_MODULE_CNTRL_RAM_NVR30_t; 3030 3031 3032 typedef union { 3033 uint32_t data; 3034 struct { 3035 #if IS_BIG_ENDIAN 3036 uint32_t reserved : 16; 3037 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR31_t[15:08] - RSVD */ 3038 uint32_t nvr31 : 8; /* FUR_MODULE_CNTRL_RAM_NVR31_t[07:00] - WO */ 3039 #endif /* IS_BIG_ENDIAN */ 3040 #if IS_LITTLE_ENDIAN 3041 uint32_t nvr31 : 8; /* FUR_MODULE_CNTRL_RAM_NVR31_t[07:00] - WO */ 3042 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR31_t[15:08] - RSVD */ 3043 uint32_t reserved : 16; 3044 #endif /* IS_LITTLE_ENDIAN */ 3045 } fields; 3046 } FUR_MODULE_CNTRL_RAM_NVR31_t; 3047 3048 3049 typedef union { 3050 uint32_t data; 3051 struct { 3052 #if IS_BIG_ENDIAN 3053 uint32_t reserved : 16; 3054 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR32_t[15:08] - RSVD */ 3055 uint32_t nvr32 : 8; /* FUR_MODULE_CNTRL_RAM_NVR32_t[07:00] - WO */ 3056 #endif /* IS_BIG_ENDIAN */ 3057 #if IS_LITTLE_ENDIAN 3058 uint32_t nvr32 : 8; /* FUR_MODULE_CNTRL_RAM_NVR32_t[07:00] - WO */ 3059 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR32_t[15:08] - RSVD */ 3060 uint32_t reserved : 16; 3061 #endif /* IS_LITTLE_ENDIAN */ 3062 } fields; 3063 } FUR_MODULE_CNTRL_RAM_NVR32_t; 3064 3065 3066 typedef union { 3067 uint32_t data; 3068 struct { 3069 #if IS_BIG_ENDIAN 3070 uint32_t reserved : 16; 3071 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR33_t[15:08] - RSVD */ 3072 uint32_t nvr33 : 8; /* FUR_MODULE_CNTRL_RAM_NVR33_t[07:00] - WO */ 3073 #endif /* IS_BIG_ENDIAN */ 3074 #if IS_LITTLE_ENDIAN 3075 uint32_t nvr33 : 8; /* FUR_MODULE_CNTRL_RAM_NVR33_t[07:00] - WO */ 3076 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR33_t[15:08] - RSVD */ 3077 uint32_t reserved : 16; 3078 #endif /* IS_LITTLE_ENDIAN */ 3079 } fields; 3080 } FUR_MODULE_CNTRL_RAM_NVR33_t; 3081 3082 3083 typedef union { 3084 uint32_t data; 3085 struct { 3086 #if IS_BIG_ENDIAN 3087 uint32_t reserved : 16; 3088 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR34_t[15:08] - RSVD */ 3089 uint32_t nvr34 : 8; /* FUR_MODULE_CNTRL_RAM_NVR34_t[07:00] - WO */ 3090 #endif /* IS_BIG_ENDIAN */ 3091 #if IS_LITTLE_ENDIAN 3092 uint32_t nvr34 : 8; /* FUR_MODULE_CNTRL_RAM_NVR34_t[07:00] - WO */ 3093 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR34_t[15:08] - RSVD */ 3094 uint32_t reserved : 16; 3095 #endif /* IS_LITTLE_ENDIAN */ 3096 } fields; 3097 } FUR_MODULE_CNTRL_RAM_NVR34_t; 3098 3099 3100 typedef union { 3101 uint32_t data; 3102 struct { 3103 #if IS_BIG_ENDIAN 3104 uint32_t reserved : 16; 3105 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR35_t[15:08] - RSVD */ 3106 uint32_t nvr35 : 8; /* FUR_MODULE_CNTRL_RAM_NVR35_t[07:00] - WO */ 3107 #endif /* IS_BIG_ENDIAN */ 3108 #if IS_LITTLE_ENDIAN 3109 uint32_t nvr35 : 8; /* FUR_MODULE_CNTRL_RAM_NVR35_t[07:00] - WO */ 3110 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR35_t[15:08] - RSVD */ 3111 uint32_t reserved : 16; 3112 #endif /* IS_LITTLE_ENDIAN */ 3113 } fields; 3114 } FUR_MODULE_CNTRL_RAM_NVR35_t; 3115 3116 3117 typedef union { 3118 uint32_t data; 3119 struct { 3120 #if IS_BIG_ENDIAN 3121 uint32_t reserved : 16; 3122 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR36_t[15:08] - RSVD */ 3123 uint32_t nvr36 : 8; /* FUR_MODULE_CNTRL_RAM_NVR36_t[07:00] - WO */ 3124 #endif /* IS_BIG_ENDIAN */ 3125 #if IS_LITTLE_ENDIAN 3126 uint32_t nvr36 : 8; /* FUR_MODULE_CNTRL_RAM_NVR36_t[07:00] - WO */ 3127 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR36_t[15:08] - RSVD */ 3128 uint32_t reserved : 16; 3129 #endif /* IS_LITTLE_ENDIAN */ 3130 } fields; 3131 } FUR_MODULE_CNTRL_RAM_NVR36_t; 3132 3133 3134 typedef union { 3135 uint32_t data; 3136 struct { 3137 #if IS_BIG_ENDIAN 3138 uint32_t reserved : 16; 3139 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR37_t[15:08] - RSVD */ 3140 uint32_t nvr37 : 8; /* FUR_MODULE_CNTRL_RAM_NVR37_t[07:00] - WO */ 3141 #endif /* IS_BIG_ENDIAN */ 3142 #if IS_LITTLE_ENDIAN 3143 uint32_t nvr37 : 8; /* FUR_MODULE_CNTRL_RAM_NVR37_t[07:00] - WO */ 3144 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR37_t[15:08] - RSVD */ 3145 uint32_t reserved : 16; 3146 #endif /* IS_LITTLE_ENDIAN */ 3147 } fields; 3148 } FUR_MODULE_CNTRL_RAM_NVR37_t; 3149 3150 3151 typedef union { 3152 uint32_t data; 3153 struct { 3154 #if IS_BIG_ENDIAN 3155 uint32_t reserved : 16; 3156 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR38_t[15:08] - RSVD */ 3157 uint32_t nvr38 : 8; /* FUR_MODULE_CNTRL_RAM_NVR38_t[07:00] - WO */ 3158 #endif /* IS_BIG_ENDIAN */ 3159 #if IS_LITTLE_ENDIAN 3160 uint32_t nvr38 : 8; /* FUR_MODULE_CNTRL_RAM_NVR38_t[07:00] - WO */ 3161 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR38_t[15:08] - RSVD */ 3162 uint32_t reserved : 16; 3163 #endif /* IS_LITTLE_ENDIAN */ 3164 } fields; 3165 } FUR_MODULE_CNTRL_RAM_NVR38_t; 3166 3167 3168 typedef union { 3169 uint32_t data; 3170 struct { 3171 #if IS_BIG_ENDIAN 3172 uint32_t reserved : 16; 3173 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR39_t[15:08] - RSVD */ 3174 uint32_t nvr39 : 8; /* FUR_MODULE_CNTRL_RAM_NVR39_t[07:00] - WO */ 3175 #endif /* IS_BIG_ENDIAN */ 3176 #if IS_LITTLE_ENDIAN 3177 uint32_t nvr39 : 8; /* FUR_MODULE_CNTRL_RAM_NVR39_t[07:00] - WO */ 3178 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR39_t[15:08] - RSVD */ 3179 uint32_t reserved : 16; 3180 #endif /* IS_LITTLE_ENDIAN */ 3181 } fields; 3182 } FUR_MODULE_CNTRL_RAM_NVR39_t; 3183 3184 3185 typedef union { 3186 uint32_t data; 3187 struct { 3188 #if IS_BIG_ENDIAN 3189 uint32_t reserved : 16; 3190 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR40_t[15:08] - RSVD */ 3191 uint32_t nvr40 : 8; /* FUR_MODULE_CNTRL_RAM_NVR40_t[07:00] - WO */ 3192 #endif /* IS_BIG_ENDIAN */ 3193 #if IS_LITTLE_ENDIAN 3194 uint32_t nvr40 : 8; /* FUR_MODULE_CNTRL_RAM_NVR40_t[07:00] - WO */ 3195 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR40_t[15:08] - RSVD */ 3196 uint32_t reserved : 16; 3197 #endif /* IS_LITTLE_ENDIAN */ 3198 } fields; 3199 } FUR_MODULE_CNTRL_RAM_NVR40_t; 3200 3201 3202 typedef union { 3203 uint32_t data; 3204 struct { 3205 #if IS_BIG_ENDIAN 3206 uint32_t reserved : 16; 3207 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR41_t[15:08] - RSVD */ 3208 uint32_t nvr41 : 8; /* FUR_MODULE_CNTRL_RAM_NVR41_t[07:00] - WO */ 3209 #endif /* IS_BIG_ENDIAN */ 3210 #if IS_LITTLE_ENDIAN 3211 uint32_t nvr41 : 8; /* FUR_MODULE_CNTRL_RAM_NVR41_t[07:00] - WO */ 3212 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR41_t[15:08] - RSVD */ 3213 uint32_t reserved : 16; 3214 #endif /* IS_LITTLE_ENDIAN */ 3215 } fields; 3216 } FUR_MODULE_CNTRL_RAM_NVR41_t; 3217 3218 3219 typedef union { 3220 uint32_t data; 3221 struct { 3222 #if IS_BIG_ENDIAN 3223 uint32_t reserved : 16; 3224 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR42_t[15:08] - RSVD */ 3225 uint32_t nvr42 : 8; /* FUR_MODULE_CNTRL_RAM_NVR42_t[07:00] - WO */ 3226 #endif /* IS_BIG_ENDIAN */ 3227 #if IS_LITTLE_ENDIAN 3228 uint32_t nvr42 : 8; /* FUR_MODULE_CNTRL_RAM_NVR42_t[07:00] - WO */ 3229 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR42_t[15:08] - RSVD */ 3230 uint32_t reserved : 16; 3231 #endif /* IS_LITTLE_ENDIAN */ 3232 } fields; 3233 } FUR_MODULE_CNTRL_RAM_NVR42_t; 3234 3235 3236 typedef union { 3237 uint32_t data; 3238 struct { 3239 #if IS_BIG_ENDIAN 3240 uint32_t reserved : 16; 3241 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR43_t[15:08] - RSVD */ 3242 uint32_t nvr43 : 8; /* FUR_MODULE_CNTRL_RAM_NVR43_t[07:00] - WO */ 3243 #endif /* IS_BIG_ENDIAN */ 3244 #if IS_LITTLE_ENDIAN 3245 uint32_t nvr43 : 8; /* FUR_MODULE_CNTRL_RAM_NVR43_t[07:00] - WO */ 3246 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR43_t[15:08] - RSVD */ 3247 uint32_t reserved : 16; 3248 #endif /* IS_LITTLE_ENDIAN */ 3249 } fields; 3250 } FUR_MODULE_CNTRL_RAM_NVR43_t; 3251 3252 3253 typedef union { 3254 uint32_t data; 3255 struct { 3256 #if IS_BIG_ENDIAN 3257 uint32_t reserved : 16; 3258 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR44_t[15:08] - RSVD */ 3259 uint32_t nvr44 : 8; /* FUR_MODULE_CNTRL_RAM_NVR44_t[07:00] - WO */ 3260 #endif /* IS_BIG_ENDIAN */ 3261 #if IS_LITTLE_ENDIAN 3262 uint32_t nvr44 : 8; /* FUR_MODULE_CNTRL_RAM_NVR44_t[07:00] - WO */ 3263 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR44_t[15:08] - RSVD */ 3264 uint32_t reserved : 16; 3265 #endif /* IS_LITTLE_ENDIAN */ 3266 } fields; 3267 } FUR_MODULE_CNTRL_RAM_NVR44_t; 3268 3269 3270 typedef union { 3271 uint32_t data; 3272 struct { 3273 #if IS_BIG_ENDIAN 3274 uint32_t reserved : 16; 3275 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR45_t[15:08] - RSVD */ 3276 uint32_t nvr45 : 8; /* FUR_MODULE_CNTRL_RAM_NVR45_t[07:00] - WO */ 3277 #endif /* IS_BIG_ENDIAN */ 3278 #if IS_LITTLE_ENDIAN 3279 uint32_t nvr45 : 8; /* FUR_MODULE_CNTRL_RAM_NVR45_t[07:00] - WO */ 3280 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR45_t[15:08] - RSVD */ 3281 uint32_t reserved : 16; 3282 #endif /* IS_LITTLE_ENDIAN */ 3283 } fields; 3284 } FUR_MODULE_CNTRL_RAM_NVR45_t; 3285 3286 3287 typedef union { 3288 uint32_t data; 3289 struct { 3290 #if IS_BIG_ENDIAN 3291 uint32_t reserved : 16; 3292 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR46_t[15:08] - RSVD */ 3293 uint32_t nvr46 : 8; /* FUR_MODULE_CNTRL_RAM_NVR46_t[07:00] - WO */ 3294 #endif /* IS_BIG_ENDIAN */ 3295 #if IS_LITTLE_ENDIAN 3296 uint32_t nvr46 : 8; /* FUR_MODULE_CNTRL_RAM_NVR46_t[07:00] - WO */ 3297 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR46_t[15:08] - RSVD */ 3298 uint32_t reserved : 16; 3299 #endif /* IS_LITTLE_ENDIAN */ 3300 } fields; 3301 } FUR_MODULE_CNTRL_RAM_NVR46_t; 3302 3303 3304 typedef union { 3305 uint32_t data; 3306 struct { 3307 #if IS_BIG_ENDIAN 3308 uint32_t reserved : 16; 3309 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR47_t[15:08] - RSVD */ 3310 uint32_t nvr47 : 8; /* FUR_MODULE_CNTRL_RAM_NVR47_t[07:00] - WO */ 3311 #endif /* IS_BIG_ENDIAN */ 3312 #if IS_LITTLE_ENDIAN 3313 uint32_t nvr47 : 8; /* FUR_MODULE_CNTRL_RAM_NVR47_t[07:00] - WO */ 3314 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR47_t[15:08] - RSVD */ 3315 uint32_t reserved : 16; 3316 #endif /* IS_LITTLE_ENDIAN */ 3317 } fields; 3318 } FUR_MODULE_CNTRL_RAM_NVR47_t; 3319 3320 3321 typedef union { 3322 uint32_t data; 3323 struct { 3324 #if IS_BIG_ENDIAN 3325 uint32_t reserved : 16; 3326 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR48_t[15:08] - RSVD */ 3327 uint32_t nvr48 : 8; /* FUR_MODULE_CNTRL_RAM_NVR48_t[07:00] - WO */ 3328 #endif /* IS_BIG_ENDIAN */ 3329 #if IS_LITTLE_ENDIAN 3330 uint32_t nvr48 : 8; /* FUR_MODULE_CNTRL_RAM_NVR48_t[07:00] - WO */ 3331 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR48_t[15:08] - RSVD */ 3332 uint32_t reserved : 16; 3333 #endif /* IS_LITTLE_ENDIAN */ 3334 } fields; 3335 } FUR_MODULE_CNTRL_RAM_NVR48_t; 3336 3337 3338 typedef union { 3339 uint32_t data; 3340 struct { 3341 #if IS_BIG_ENDIAN 3342 uint32_t reserved : 16; 3343 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR49_t[15:08] - RSVD */ 3344 uint32_t nvr49 : 8; /* FUR_MODULE_CNTRL_RAM_NVR49_t[07:00] - WO */ 3345 #endif /* IS_BIG_ENDIAN */ 3346 #if IS_LITTLE_ENDIAN 3347 uint32_t nvr49 : 8; /* FUR_MODULE_CNTRL_RAM_NVR49_t[07:00] - WO */ 3348 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR49_t[15:08] - RSVD */ 3349 uint32_t reserved : 16; 3350 #endif /* IS_LITTLE_ENDIAN */ 3351 } fields; 3352 } FUR_MODULE_CNTRL_RAM_NVR49_t; 3353 3354 3355 typedef union { 3356 uint32_t data; 3357 struct { 3358 #if IS_BIG_ENDIAN 3359 uint32_t reserved : 16; 3360 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR50_t[15:08] - RSVD */ 3361 uint32_t nvr50 : 8; /* FUR_MODULE_CNTRL_RAM_NVR50_t[07:00] - WO */ 3362 #endif /* IS_BIG_ENDIAN */ 3363 #if IS_LITTLE_ENDIAN 3364 uint32_t nvr50 : 8; /* FUR_MODULE_CNTRL_RAM_NVR50_t[07:00] - WO */ 3365 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR50_t[15:08] - RSVD */ 3366 uint32_t reserved : 16; 3367 #endif /* IS_LITTLE_ENDIAN */ 3368 } fields; 3369 } FUR_MODULE_CNTRL_RAM_NVR50_t; 3370 3371 3372 typedef union { 3373 uint32_t data; 3374 struct { 3375 #if IS_BIG_ENDIAN 3376 uint32_t reserved : 16; 3377 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR51_t[15:08] - RSVD */ 3378 uint32_t nvr51 : 8; /* FUR_MODULE_CNTRL_RAM_NVR51_t[07:00] - WO */ 3379 #endif /* IS_BIG_ENDIAN */ 3380 #if IS_LITTLE_ENDIAN 3381 uint32_t nvr51 : 8; /* FUR_MODULE_CNTRL_RAM_NVR51_t[07:00] - WO */ 3382 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR51_t[15:08] - RSVD */ 3383 uint32_t reserved : 16; 3384 #endif /* IS_LITTLE_ENDIAN */ 3385 } fields; 3386 } FUR_MODULE_CNTRL_RAM_NVR51_t; 3387 3388 3389 typedef union { 3390 uint32_t data; 3391 struct { 3392 #if IS_BIG_ENDIAN 3393 uint32_t reserved : 16; 3394 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR52_t[15:08] - RSVD */ 3395 uint32_t nvr52 : 8; /* FUR_MODULE_CNTRL_RAM_NVR52_t[07:00] - WO */ 3396 #endif /* IS_BIG_ENDIAN */ 3397 #if IS_LITTLE_ENDIAN 3398 uint32_t nvr52 : 8; /* FUR_MODULE_CNTRL_RAM_NVR52_t[07:00] - WO */ 3399 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR52_t[15:08] - RSVD */ 3400 uint32_t reserved : 16; 3401 #endif /* IS_LITTLE_ENDIAN */ 3402 } fields; 3403 } FUR_MODULE_CNTRL_RAM_NVR52_t; 3404 3405 3406 typedef union { 3407 uint32_t data; 3408 struct { 3409 #if IS_BIG_ENDIAN 3410 uint32_t reserved : 16; 3411 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR53_t[15:08] - RSVD */ 3412 uint32_t nvr53 : 8; /* FUR_MODULE_CNTRL_RAM_NVR53_t[07:00] - WO */ 3413 #endif /* IS_BIG_ENDIAN */ 3414 #if IS_LITTLE_ENDIAN 3415 uint32_t nvr53 : 8; /* FUR_MODULE_CNTRL_RAM_NVR53_t[07:00] - WO */ 3416 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR53_t[15:08] - RSVD */ 3417 uint32_t reserved : 16; 3418 #endif /* IS_LITTLE_ENDIAN */ 3419 } fields; 3420 } FUR_MODULE_CNTRL_RAM_NVR53_t; 3421 3422 3423 typedef union { 3424 uint32_t data; 3425 struct { 3426 #if IS_BIG_ENDIAN 3427 uint32_t reserved : 16; 3428 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR54_t[15:08] - RSVD */ 3429 uint32_t nvr54 : 8; /* FUR_MODULE_CNTRL_RAM_NVR54_t[07:00] - WO */ 3430 #endif /* IS_BIG_ENDIAN */ 3431 #if IS_LITTLE_ENDIAN 3432 uint32_t nvr54 : 8; /* FUR_MODULE_CNTRL_RAM_NVR54_t[07:00] - WO */ 3433 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR54_t[15:08] - RSVD */ 3434 uint32_t reserved : 16; 3435 #endif /* IS_LITTLE_ENDIAN */ 3436 } fields; 3437 } FUR_MODULE_CNTRL_RAM_NVR54_t; 3438 3439 3440 typedef union { 3441 uint32_t data; 3442 struct { 3443 #if IS_BIG_ENDIAN 3444 uint32_t reserved : 16; 3445 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR55_t[15:08] - RSVD */ 3446 uint32_t nvr55 : 8; /* FUR_MODULE_CNTRL_RAM_NVR55_t[07:00] - WO */ 3447 #endif /* IS_BIG_ENDIAN */ 3448 #if IS_LITTLE_ENDIAN 3449 uint32_t nvr55 : 8; /* FUR_MODULE_CNTRL_RAM_NVR55_t[07:00] - WO */ 3450 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR55_t[15:08] - RSVD */ 3451 uint32_t reserved : 16; 3452 #endif /* IS_LITTLE_ENDIAN */ 3453 } fields; 3454 } FUR_MODULE_CNTRL_RAM_NVR55_t; 3455 3456 3457 typedef union { 3458 uint32_t data; 3459 struct { 3460 #if IS_BIG_ENDIAN 3461 uint32_t reserved : 16; 3462 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR56_t[15:08] - RSVD */ 3463 uint32_t nvr56 : 8; /* FUR_MODULE_CNTRL_RAM_NVR56_t[07:00] - WO */ 3464 #endif /* IS_BIG_ENDIAN */ 3465 #if IS_LITTLE_ENDIAN 3466 uint32_t nvr56 : 8; /* FUR_MODULE_CNTRL_RAM_NVR56_t[07:00] - WO */ 3467 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR56_t[15:08] - RSVD */ 3468 uint32_t reserved : 16; 3469 #endif /* IS_LITTLE_ENDIAN */ 3470 } fields; 3471 } FUR_MODULE_CNTRL_RAM_NVR56_t; 3472 3473 3474 typedef union { 3475 uint32_t data; 3476 struct { 3477 #if IS_BIG_ENDIAN 3478 uint32_t reserved : 16; 3479 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR57_t[15:08] - RSVD */ 3480 uint32_t nvr57 : 8; /* FUR_MODULE_CNTRL_RAM_NVR57_t[07:00] - WO */ 3481 #endif /* IS_BIG_ENDIAN */ 3482 #if IS_LITTLE_ENDIAN 3483 uint32_t nvr57 : 8; /* FUR_MODULE_CNTRL_RAM_NVR57_t[07:00] - WO */ 3484 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR57_t[15:08] - RSVD */ 3485 uint32_t reserved : 16; 3486 #endif /* IS_LITTLE_ENDIAN */ 3487 } fields; 3488 } FUR_MODULE_CNTRL_RAM_NVR57_t; 3489 3490 3491 typedef union { 3492 uint32_t data; 3493 struct { 3494 #if IS_BIG_ENDIAN 3495 uint32_t reserved : 16; 3496 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR58_t[15:08] - RSVD */ 3497 uint32_t nvr58 : 8; /* FUR_MODULE_CNTRL_RAM_NVR58_t[07:00] - WO */ 3498 #endif /* IS_BIG_ENDIAN */ 3499 #if IS_LITTLE_ENDIAN 3500 uint32_t nvr58 : 8; /* FUR_MODULE_CNTRL_RAM_NVR58_t[07:00] - WO */ 3501 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR58_t[15:08] - RSVD */ 3502 uint32_t reserved : 16; 3503 #endif /* IS_LITTLE_ENDIAN */ 3504 } fields; 3505 } FUR_MODULE_CNTRL_RAM_NVR58_t; 3506 3507 3508 typedef union { 3509 uint32_t data; 3510 struct { 3511 #if IS_BIG_ENDIAN 3512 uint32_t reserved : 16; 3513 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR59_t[15:08] - RSVD */ 3514 uint32_t nvr59 : 8; /* FUR_MODULE_CNTRL_RAM_NVR59_t[07:00] - WO */ 3515 #endif /* IS_BIG_ENDIAN */ 3516 #if IS_LITTLE_ENDIAN 3517 uint32_t nvr59 : 8; /* FUR_MODULE_CNTRL_RAM_NVR59_t[07:00] - WO */ 3518 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR59_t[15:08] - RSVD */ 3519 uint32_t reserved : 16; 3520 #endif /* IS_LITTLE_ENDIAN */ 3521 } fields; 3522 } FUR_MODULE_CNTRL_RAM_NVR59_t; 3523 3524 3525 typedef union { 3526 uint32_t data; 3527 struct { 3528 #if IS_BIG_ENDIAN 3529 uint32_t reserved : 16; 3530 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR60_t[15:08] - RSVD */ 3531 uint32_t nvr60 : 8; /* FUR_MODULE_CNTRL_RAM_NVR60_t[07:00] - WO */ 3532 #endif /* IS_BIG_ENDIAN */ 3533 #if IS_LITTLE_ENDIAN 3534 uint32_t nvr60 : 8; /* FUR_MODULE_CNTRL_RAM_NVR60_t[07:00] - WO */ 3535 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR60_t[15:08] - RSVD */ 3536 uint32_t reserved : 16; 3537 #endif /* IS_LITTLE_ENDIAN */ 3538 } fields; 3539 } FUR_MODULE_CNTRL_RAM_NVR60_t; 3540 3541 3542 typedef union { 3543 uint32_t data; 3544 struct { 3545 #if IS_BIG_ENDIAN 3546 uint32_t reserved : 16; 3547 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR61_t[15:08] - RSVD */ 3548 uint32_t nvr61 : 8; /* FUR_MODULE_CNTRL_RAM_NVR61_t[07:00] - WO */ 3549 #endif /* IS_BIG_ENDIAN */ 3550 #if IS_LITTLE_ENDIAN 3551 uint32_t nvr61 : 8; /* FUR_MODULE_CNTRL_RAM_NVR61_t[07:00] - WO */ 3552 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR61_t[15:08] - RSVD */ 3553 uint32_t reserved : 16; 3554 #endif /* IS_LITTLE_ENDIAN */ 3555 } fields; 3556 } FUR_MODULE_CNTRL_RAM_NVR61_t; 3557 3558 3559 typedef union { 3560 uint32_t data; 3561 struct { 3562 #if IS_BIG_ENDIAN 3563 uint32_t reserved : 16; 3564 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR62_t[15:08] - RSVD */ 3565 uint32_t nvr62 : 8; /* FUR_MODULE_CNTRL_RAM_NVR62_t[07:00] - WO */ 3566 #endif /* IS_BIG_ENDIAN */ 3567 #if IS_LITTLE_ENDIAN 3568 uint32_t nvr62 : 8; /* FUR_MODULE_CNTRL_RAM_NVR62_t[07:00] - WO */ 3569 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR62_t[15:08] - RSVD */ 3570 uint32_t reserved : 16; 3571 #endif /* IS_LITTLE_ENDIAN */ 3572 } fields; 3573 } FUR_MODULE_CNTRL_RAM_NVR62_t; 3574 3575 3576 typedef union { 3577 uint32_t data; 3578 struct { 3579 #if IS_BIG_ENDIAN 3580 uint32_t reserved : 16; 3581 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR63_t[15:08] - RSVD */ 3582 uint32_t nvr63 : 8; /* FUR_MODULE_CNTRL_RAM_NVR63_t[07:00] - WO */ 3583 #endif /* IS_BIG_ENDIAN */ 3584 #if IS_LITTLE_ENDIAN 3585 uint32_t nvr63 : 8; /* FUR_MODULE_CNTRL_RAM_NVR63_t[07:00] - WO */ 3586 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR63_t[15:08] - RSVD */ 3587 uint32_t reserved : 16; 3588 #endif /* IS_LITTLE_ENDIAN */ 3589 } fields; 3590 } FUR_MODULE_CNTRL_RAM_NVR63_t; 3591 3592 3593 typedef union { 3594 uint32_t data; 3595 struct { 3596 #if IS_BIG_ENDIAN 3597 uint32_t reserved : 16; 3598 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR64_t[15:08] - RSVD */ 3599 uint32_t nvr64 : 8; /* FUR_MODULE_CNTRL_RAM_NVR64_t[07:00] - WO */ 3600 #endif /* IS_BIG_ENDIAN */ 3601 #if IS_LITTLE_ENDIAN 3602 uint32_t nvr64 : 8; /* FUR_MODULE_CNTRL_RAM_NVR64_t[07:00] - WO */ 3603 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR64_t[15:08] - RSVD */ 3604 uint32_t reserved : 16; 3605 #endif /* IS_LITTLE_ENDIAN */ 3606 } fields; 3607 } FUR_MODULE_CNTRL_RAM_NVR64_t; 3608 3609 3610 typedef union { 3611 uint32_t data; 3612 struct { 3613 #if IS_BIG_ENDIAN 3614 uint32_t reserved : 16; 3615 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR65_t[15:08] - RSVD */ 3616 uint32_t nvr65 : 8; /* FUR_MODULE_CNTRL_RAM_NVR65_t[07:00] - WO */ 3617 #endif /* IS_BIG_ENDIAN */ 3618 #if IS_LITTLE_ENDIAN 3619 uint32_t nvr65 : 8; /* FUR_MODULE_CNTRL_RAM_NVR65_t[07:00] - WO */ 3620 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR65_t[15:08] - RSVD */ 3621 uint32_t reserved : 16; 3622 #endif /* IS_LITTLE_ENDIAN */ 3623 } fields; 3624 } FUR_MODULE_CNTRL_RAM_NVR65_t; 3625 3626 3627 typedef union { 3628 uint32_t data; 3629 struct { 3630 #if IS_BIG_ENDIAN 3631 uint32_t reserved : 16; 3632 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR66_t[15:08] - RSVD */ 3633 uint32_t nvr66 : 8; /* FUR_MODULE_CNTRL_RAM_NVR66_t[07:00] - WO */ 3634 #endif /* IS_BIG_ENDIAN */ 3635 #if IS_LITTLE_ENDIAN 3636 uint32_t nvr66 : 8; /* FUR_MODULE_CNTRL_RAM_NVR66_t[07:00] - WO */ 3637 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR66_t[15:08] - RSVD */ 3638 uint32_t reserved : 16; 3639 #endif /* IS_LITTLE_ENDIAN */ 3640 } fields; 3641 } FUR_MODULE_CNTRL_RAM_NVR66_t; 3642 3643 3644 typedef union { 3645 uint32_t data; 3646 struct { 3647 #if IS_BIG_ENDIAN 3648 uint32_t reserved : 16; 3649 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR67_t[15:08] - RSVD */ 3650 uint32_t nvr67 : 8; /* FUR_MODULE_CNTRL_RAM_NVR67_t[07:00] - WO */ 3651 #endif /* IS_BIG_ENDIAN */ 3652 #if IS_LITTLE_ENDIAN 3653 uint32_t nvr67 : 8; /* FUR_MODULE_CNTRL_RAM_NVR67_t[07:00] - WO */ 3654 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR67_t[15:08] - RSVD */ 3655 uint32_t reserved : 16; 3656 #endif /* IS_LITTLE_ENDIAN */ 3657 } fields; 3658 } FUR_MODULE_CNTRL_RAM_NVR67_t; 3659 3660 3661 typedef union { 3662 uint32_t data; 3663 struct { 3664 #if IS_BIG_ENDIAN 3665 uint32_t reserved : 16; 3666 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR68_t[15:08] - RSVD */ 3667 uint32_t nvr68 : 8; /* FUR_MODULE_CNTRL_RAM_NVR68_t[07:00] - WO */ 3668 #endif /* IS_BIG_ENDIAN */ 3669 #if IS_LITTLE_ENDIAN 3670 uint32_t nvr68 : 8; /* FUR_MODULE_CNTRL_RAM_NVR68_t[07:00] - WO */ 3671 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR68_t[15:08] - RSVD */ 3672 uint32_t reserved : 16; 3673 #endif /* IS_LITTLE_ENDIAN */ 3674 } fields; 3675 } FUR_MODULE_CNTRL_RAM_NVR68_t; 3676 3677 3678 typedef union { 3679 uint32_t data; 3680 struct { 3681 #if IS_BIG_ENDIAN 3682 uint32_t reserved : 16; 3683 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR69_t[15:08] - RSVD */ 3684 uint32_t nvr69 : 8; /* FUR_MODULE_CNTRL_RAM_NVR69_t[07:00] - WO */ 3685 #endif /* IS_BIG_ENDIAN */ 3686 #if IS_LITTLE_ENDIAN 3687 uint32_t nvr69 : 8; /* FUR_MODULE_CNTRL_RAM_NVR69_t[07:00] - WO */ 3688 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR69_t[15:08] - RSVD */ 3689 uint32_t reserved : 16; 3690 #endif /* IS_LITTLE_ENDIAN */ 3691 } fields; 3692 } FUR_MODULE_CNTRL_RAM_NVR69_t; 3693 3694 3695 typedef union { 3696 uint32_t data; 3697 struct { 3698 #if IS_BIG_ENDIAN 3699 uint32_t reserved : 16; 3700 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR70_t[15:08] - RSVD */ 3701 uint32_t nvr70 : 8; /* FUR_MODULE_CNTRL_RAM_NVR70_t[07:00] - WO */ 3702 #endif /* IS_BIG_ENDIAN */ 3703 #if IS_LITTLE_ENDIAN 3704 uint32_t nvr70 : 8; /* FUR_MODULE_CNTRL_RAM_NVR70_t[07:00] - WO */ 3705 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR70_t[15:08] - RSVD */ 3706 uint32_t reserved : 16; 3707 #endif /* IS_LITTLE_ENDIAN */ 3708 } fields; 3709 } FUR_MODULE_CNTRL_RAM_NVR70_t; 3710 3711 3712 typedef union { 3713 uint32_t data; 3714 struct { 3715 #if IS_BIG_ENDIAN 3716 uint32_t reserved : 16; 3717 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR71_t[15:08] - RSVD */ 3718 uint32_t nvr71 : 8; /* FUR_MODULE_CNTRL_RAM_NVR71_t[07:00] - WO */ 3719 #endif /* IS_BIG_ENDIAN */ 3720 #if IS_LITTLE_ENDIAN 3721 uint32_t nvr71 : 8; /* FUR_MODULE_CNTRL_RAM_NVR71_t[07:00] - WO */ 3722 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR71_t[15:08] - RSVD */ 3723 uint32_t reserved : 16; 3724 #endif /* IS_LITTLE_ENDIAN */ 3725 } fields; 3726 } FUR_MODULE_CNTRL_RAM_NVR71_t; 3727 3728 3729 typedef union { 3730 uint32_t data; 3731 struct { 3732 #if IS_BIG_ENDIAN 3733 uint32_t reserved : 16; 3734 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR72_t[15:08] - RSVD */ 3735 uint32_t nvr72 : 8; /* FUR_MODULE_CNTRL_RAM_NVR72_t[07:00] - WO */ 3736 #endif /* IS_BIG_ENDIAN */ 3737 #if IS_LITTLE_ENDIAN 3738 uint32_t nvr72 : 8; /* FUR_MODULE_CNTRL_RAM_NVR72_t[07:00] - WO */ 3739 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR72_t[15:08] - RSVD */ 3740 uint32_t reserved : 16; 3741 #endif /* IS_LITTLE_ENDIAN */ 3742 } fields; 3743 } FUR_MODULE_CNTRL_RAM_NVR72_t; 3744 3745 3746 typedef union { 3747 uint32_t data; 3748 struct { 3749 #if IS_BIG_ENDIAN 3750 uint32_t reserved : 16; 3751 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR73_t[15:08] - RSVD */ 3752 uint32_t nvr73 : 8; /* FUR_MODULE_CNTRL_RAM_NVR73_t[07:00] - WO */ 3753 #endif /* IS_BIG_ENDIAN */ 3754 #if IS_LITTLE_ENDIAN 3755 uint32_t nvr73 : 8; /* FUR_MODULE_CNTRL_RAM_NVR73_t[07:00] - WO */ 3756 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR73_t[15:08] - RSVD */ 3757 uint32_t reserved : 16; 3758 #endif /* IS_LITTLE_ENDIAN */ 3759 } fields; 3760 } FUR_MODULE_CNTRL_RAM_NVR73_t; 3761 3762 3763 typedef union { 3764 uint32_t data; 3765 struct { 3766 #if IS_BIG_ENDIAN 3767 uint32_t reserved : 16; 3768 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR74_t[15:08] - RSVD */ 3769 uint32_t nvr74 : 8; /* FUR_MODULE_CNTRL_RAM_NVR74_t[07:00] - WO */ 3770 #endif /* IS_BIG_ENDIAN */ 3771 #if IS_LITTLE_ENDIAN 3772 uint32_t nvr74 : 8; /* FUR_MODULE_CNTRL_RAM_NVR74_t[07:00] - WO */ 3773 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR74_t[15:08] - RSVD */ 3774 uint32_t reserved : 16; 3775 #endif /* IS_LITTLE_ENDIAN */ 3776 } fields; 3777 } FUR_MODULE_CNTRL_RAM_NVR74_t; 3778 3779 3780 typedef union { 3781 uint32_t data; 3782 struct { 3783 #if IS_BIG_ENDIAN 3784 uint32_t reserved : 16; 3785 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR75_t[15:08] - RSVD */ 3786 uint32_t nvr75 : 8; /* FUR_MODULE_CNTRL_RAM_NVR75_t[07:00] - WO */ 3787 #endif /* IS_BIG_ENDIAN */ 3788 #if IS_LITTLE_ENDIAN 3789 uint32_t nvr75 : 8; /* FUR_MODULE_CNTRL_RAM_NVR75_t[07:00] - WO */ 3790 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR75_t[15:08] - RSVD */ 3791 uint32_t reserved : 16; 3792 #endif /* IS_LITTLE_ENDIAN */ 3793 } fields; 3794 } FUR_MODULE_CNTRL_RAM_NVR75_t; 3795 3796 3797 typedef union { 3798 uint32_t data; 3799 struct { 3800 #if IS_BIG_ENDIAN 3801 uint32_t reserved : 16; 3802 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR76_t[15:08] - RSVD */ 3803 uint32_t nvr76 : 8; /* FUR_MODULE_CNTRL_RAM_NVR76_t[07:00] - WO */ 3804 #endif /* IS_BIG_ENDIAN */ 3805 #if IS_LITTLE_ENDIAN 3806 uint32_t nvr76 : 8; /* FUR_MODULE_CNTRL_RAM_NVR76_t[07:00] - WO */ 3807 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR76_t[15:08] - RSVD */ 3808 uint32_t reserved : 16; 3809 #endif /* IS_LITTLE_ENDIAN */ 3810 } fields; 3811 } FUR_MODULE_CNTRL_RAM_NVR76_t; 3812 3813 3814 typedef union { 3815 uint32_t data; 3816 struct { 3817 #if IS_BIG_ENDIAN 3818 uint32_t reserved : 16; 3819 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR77_t[15:08] - RSVD */ 3820 uint32_t nvr77 : 8; /* FUR_MODULE_CNTRL_RAM_NVR77_t[07:00] - WO */ 3821 #endif /* IS_BIG_ENDIAN */ 3822 #if IS_LITTLE_ENDIAN 3823 uint32_t nvr77 : 8; /* FUR_MODULE_CNTRL_RAM_NVR77_t[07:00] - WO */ 3824 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR77_t[15:08] - RSVD */ 3825 uint32_t reserved : 16; 3826 #endif /* IS_LITTLE_ENDIAN */ 3827 } fields; 3828 } FUR_MODULE_CNTRL_RAM_NVR77_t; 3829 3830 3831 typedef union { 3832 uint32_t data; 3833 struct { 3834 #if IS_BIG_ENDIAN 3835 uint32_t reserved : 16; 3836 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR78_t[15:08] - RSVD */ 3837 uint32_t nvr78 : 8; /* FUR_MODULE_CNTRL_RAM_NVR78_t[07:00] - WO */ 3838 #endif /* IS_BIG_ENDIAN */ 3839 #if IS_LITTLE_ENDIAN 3840 uint32_t nvr78 : 8; /* FUR_MODULE_CNTRL_RAM_NVR78_t[07:00] - WO */ 3841 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR78_t[15:08] - RSVD */ 3842 uint32_t reserved : 16; 3843 #endif /* IS_LITTLE_ENDIAN */ 3844 } fields; 3845 } FUR_MODULE_CNTRL_RAM_NVR78_t; 3846 3847 3848 typedef union { 3849 uint32_t data; 3850 struct { 3851 #if IS_BIG_ENDIAN 3852 uint32_t reserved : 16; 3853 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR79_t[15:08] - RSVD */ 3854 uint32_t nvr79 : 8; /* FUR_MODULE_CNTRL_RAM_NVR79_t[07:00] - WO */ 3855 #endif /* IS_BIG_ENDIAN */ 3856 #if IS_LITTLE_ENDIAN 3857 uint32_t nvr79 : 8; /* FUR_MODULE_CNTRL_RAM_NVR79_t[07:00] - WO */ 3858 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR79_t[15:08] - RSVD */ 3859 uint32_t reserved : 16; 3860 #endif /* IS_LITTLE_ENDIAN */ 3861 } fields; 3862 } FUR_MODULE_CNTRL_RAM_NVR79_t; 3863 3864 3865 typedef union { 3866 uint32_t data; 3867 struct { 3868 #if IS_BIG_ENDIAN 3869 uint32_t reserved : 16; 3870 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR80_t[15:08] - RSVD */ 3871 uint32_t nvr80 : 8; /* FUR_MODULE_CNTRL_RAM_NVR80_t[07:00] - WO */ 3872 #endif /* IS_BIG_ENDIAN */ 3873 #if IS_LITTLE_ENDIAN 3874 uint32_t nvr80 : 8; /* FUR_MODULE_CNTRL_RAM_NVR80_t[07:00] - WO */ 3875 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR80_t[15:08] - RSVD */ 3876 uint32_t reserved : 16; 3877 #endif /* IS_LITTLE_ENDIAN */ 3878 } fields; 3879 } FUR_MODULE_CNTRL_RAM_NVR80_t; 3880 3881 3882 typedef union { 3883 uint32_t data; 3884 struct { 3885 #if IS_BIG_ENDIAN 3886 uint32_t reserved : 16; 3887 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR81_t[15:08] - RSVD */ 3888 uint32_t nvr81 : 8; /* FUR_MODULE_CNTRL_RAM_NVR81_t[07:00] - WO */ 3889 #endif /* IS_BIG_ENDIAN */ 3890 #if IS_LITTLE_ENDIAN 3891 uint32_t nvr81 : 8; /* FUR_MODULE_CNTRL_RAM_NVR81_t[07:00] - WO */ 3892 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR81_t[15:08] - RSVD */ 3893 uint32_t reserved : 16; 3894 #endif /* IS_LITTLE_ENDIAN */ 3895 } fields; 3896 } FUR_MODULE_CNTRL_RAM_NVR81_t; 3897 3898 3899 typedef union { 3900 uint32_t data; 3901 struct { 3902 #if IS_BIG_ENDIAN 3903 uint32_t reserved : 16; 3904 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR82_t[15:08] - RSVD */ 3905 uint32_t nvr82 : 8; /* FUR_MODULE_CNTRL_RAM_NVR82_t[07:00] - WO */ 3906 #endif /* IS_BIG_ENDIAN */ 3907 #if IS_LITTLE_ENDIAN 3908 uint32_t nvr82 : 8; /* FUR_MODULE_CNTRL_RAM_NVR82_t[07:00] - WO */ 3909 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR82_t[15:08] - RSVD */ 3910 uint32_t reserved : 16; 3911 #endif /* IS_LITTLE_ENDIAN */ 3912 } fields; 3913 } FUR_MODULE_CNTRL_RAM_NVR82_t; 3914 3915 3916 typedef union { 3917 uint32_t data; 3918 struct { 3919 #if IS_BIG_ENDIAN 3920 uint32_t reserved : 16; 3921 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR83_t[15:08] - RSVD */ 3922 uint32_t nvr83 : 8; /* FUR_MODULE_CNTRL_RAM_NVR83_t[07:00] - WO */ 3923 #endif /* IS_BIG_ENDIAN */ 3924 #if IS_LITTLE_ENDIAN 3925 uint32_t nvr83 : 8; /* FUR_MODULE_CNTRL_RAM_NVR83_t[07:00] - WO */ 3926 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR83_t[15:08] - RSVD */ 3927 uint32_t reserved : 16; 3928 #endif /* IS_LITTLE_ENDIAN */ 3929 } fields; 3930 } FUR_MODULE_CNTRL_RAM_NVR83_t; 3931 3932 3933 typedef union { 3934 uint32_t data; 3935 struct { 3936 #if IS_BIG_ENDIAN 3937 uint32_t reserved : 16; 3938 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR84_t[15:08] - RSVD */ 3939 uint32_t nvr84 : 8; /* FUR_MODULE_CNTRL_RAM_NVR84_t[07:00] - WO */ 3940 #endif /* IS_BIG_ENDIAN */ 3941 #if IS_LITTLE_ENDIAN 3942 uint32_t nvr84 : 8; /* FUR_MODULE_CNTRL_RAM_NVR84_t[07:00] - WO */ 3943 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR84_t[15:08] - RSVD */ 3944 uint32_t reserved : 16; 3945 #endif /* IS_LITTLE_ENDIAN */ 3946 } fields; 3947 } FUR_MODULE_CNTRL_RAM_NVR84_t; 3948 3949 3950 typedef union { 3951 uint32_t data; 3952 struct { 3953 #if IS_BIG_ENDIAN 3954 uint32_t reserved : 16; 3955 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR85_t[15:08] - RSVD */ 3956 uint32_t nvr85 : 8; /* FUR_MODULE_CNTRL_RAM_NVR85_t[07:00] - WO */ 3957 #endif /* IS_BIG_ENDIAN */ 3958 #if IS_LITTLE_ENDIAN 3959 uint32_t nvr85 : 8; /* FUR_MODULE_CNTRL_RAM_NVR85_t[07:00] - WO */ 3960 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR85_t[15:08] - RSVD */ 3961 uint32_t reserved : 16; 3962 #endif /* IS_LITTLE_ENDIAN */ 3963 } fields; 3964 } FUR_MODULE_CNTRL_RAM_NVR85_t; 3965 3966 3967 typedef union { 3968 uint32_t data; 3969 struct { 3970 #if IS_BIG_ENDIAN 3971 uint32_t reserved : 16; 3972 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR86_t[15:08] - RSVD */ 3973 uint32_t nvr86 : 8; /* FUR_MODULE_CNTRL_RAM_NVR86_t[07:00] - WO */ 3974 #endif /* IS_BIG_ENDIAN */ 3975 #if IS_LITTLE_ENDIAN 3976 uint32_t nvr86 : 8; /* FUR_MODULE_CNTRL_RAM_NVR86_t[07:00] - WO */ 3977 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR86_t[15:08] - RSVD */ 3978 uint32_t reserved : 16; 3979 #endif /* IS_LITTLE_ENDIAN */ 3980 } fields; 3981 } FUR_MODULE_CNTRL_RAM_NVR86_t; 3982 3983 3984 typedef union { 3985 uint32_t data; 3986 struct { 3987 #if IS_BIG_ENDIAN 3988 uint32_t reserved : 16; 3989 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR87_t[15:08] - RSVD */ 3990 uint32_t nvr87 : 8; /* FUR_MODULE_CNTRL_RAM_NVR87_t[07:00] - WO */ 3991 #endif /* IS_BIG_ENDIAN */ 3992 #if IS_LITTLE_ENDIAN 3993 uint32_t nvr87 : 8; /* FUR_MODULE_CNTRL_RAM_NVR87_t[07:00] - WO */ 3994 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR87_t[15:08] - RSVD */ 3995 uint32_t reserved : 16; 3996 #endif /* IS_LITTLE_ENDIAN */ 3997 } fields; 3998 } FUR_MODULE_CNTRL_RAM_NVR87_t; 3999 4000 4001 typedef union { 4002 uint32_t data; 4003 struct { 4004 #if IS_BIG_ENDIAN 4005 uint32_t reserved : 16; 4006 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR88_t[15:08] - RSVD */ 4007 uint32_t nvr88 : 8; /* FUR_MODULE_CNTRL_RAM_NVR88_t[07:00] - WO */ 4008 #endif /* IS_BIG_ENDIAN */ 4009 #if IS_LITTLE_ENDIAN 4010 uint32_t nvr88 : 8; /* FUR_MODULE_CNTRL_RAM_NVR88_t[07:00] - WO */ 4011 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR88_t[15:08] - RSVD */ 4012 uint32_t reserved : 16; 4013 #endif /* IS_LITTLE_ENDIAN */ 4014 } fields; 4015 } FUR_MODULE_CNTRL_RAM_NVR88_t; 4016 4017 4018 typedef union { 4019 uint32_t data; 4020 struct { 4021 #if IS_BIG_ENDIAN 4022 uint32_t reserved : 16; 4023 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR89_t[15:08] - RSVD */ 4024 uint32_t nvr89 : 8; /* FUR_MODULE_CNTRL_RAM_NVR89_t[07:00] - WO */ 4025 #endif /* IS_BIG_ENDIAN */ 4026 #if IS_LITTLE_ENDIAN 4027 uint32_t nvr89 : 8; /* FUR_MODULE_CNTRL_RAM_NVR89_t[07:00] - WO */ 4028 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR89_t[15:08] - RSVD */ 4029 uint32_t reserved : 16; 4030 #endif /* IS_LITTLE_ENDIAN */ 4031 } fields; 4032 } FUR_MODULE_CNTRL_RAM_NVR89_t; 4033 4034 4035 typedef union { 4036 uint32_t data; 4037 struct { 4038 #if IS_BIG_ENDIAN 4039 uint32_t reserved : 16; 4040 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR90_t[15:08] - RSVD */ 4041 uint32_t nvr90 : 8; /* FUR_MODULE_CNTRL_RAM_NVR90_t[07:00] - WO */ 4042 #endif /* IS_BIG_ENDIAN */ 4043 #if IS_LITTLE_ENDIAN 4044 uint32_t nvr90 : 8; /* FUR_MODULE_CNTRL_RAM_NVR90_t[07:00] - WO */ 4045 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR90_t[15:08] - RSVD */ 4046 uint32_t reserved : 16; 4047 #endif /* IS_LITTLE_ENDIAN */ 4048 } fields; 4049 } FUR_MODULE_CNTRL_RAM_NVR90_t; 4050 4051 4052 typedef union { 4053 uint32_t data; 4054 struct { 4055 #if IS_BIG_ENDIAN 4056 uint32_t reserved : 16; 4057 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR91_t[15:08] - RSVD */ 4058 uint32_t nvr91 : 8; /* FUR_MODULE_CNTRL_RAM_NVR91_t[07:00] - WO */ 4059 #endif /* IS_BIG_ENDIAN */ 4060 #if IS_LITTLE_ENDIAN 4061 uint32_t nvr91 : 8; /* FUR_MODULE_CNTRL_RAM_NVR91_t[07:00] - WO */ 4062 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR91_t[15:08] - RSVD */ 4063 uint32_t reserved : 16; 4064 #endif /* IS_LITTLE_ENDIAN */ 4065 } fields; 4066 } FUR_MODULE_CNTRL_RAM_NVR91_t; 4067 4068 4069 typedef union { 4070 uint32_t data; 4071 struct { 4072 #if IS_BIG_ENDIAN 4073 uint32_t reserved : 16; 4074 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR92_t[15:08] - RSVD */ 4075 uint32_t nvr92 : 8; /* FUR_MODULE_CNTRL_RAM_NVR92_t[07:00] - WO */ 4076 #endif /* IS_BIG_ENDIAN */ 4077 #if IS_LITTLE_ENDIAN 4078 uint32_t nvr92 : 8; /* FUR_MODULE_CNTRL_RAM_NVR92_t[07:00] - WO */ 4079 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR92_t[15:08] - RSVD */ 4080 uint32_t reserved : 16; 4081 #endif /* IS_LITTLE_ENDIAN */ 4082 } fields; 4083 } FUR_MODULE_CNTRL_RAM_NVR92_t; 4084 4085 4086 typedef union { 4087 uint32_t data; 4088 struct { 4089 #if IS_BIG_ENDIAN 4090 uint32_t reserved : 16; 4091 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR93_t[15:08] - RSVD */ 4092 uint32_t nvr93 : 8; /* FUR_MODULE_CNTRL_RAM_NVR93_t[07:00] - WO */ 4093 #endif /* IS_BIG_ENDIAN */ 4094 #if IS_LITTLE_ENDIAN 4095 uint32_t nvr93 : 8; /* FUR_MODULE_CNTRL_RAM_NVR93_t[07:00] - WO */ 4096 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR93_t[15:08] - RSVD */ 4097 uint32_t reserved : 16; 4098 #endif /* IS_LITTLE_ENDIAN */ 4099 } fields; 4100 } FUR_MODULE_CNTRL_RAM_NVR93_t; 4101 4102 4103 typedef union { 4104 uint32_t data; 4105 struct { 4106 #if IS_BIG_ENDIAN 4107 uint32_t reserved : 16; 4108 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR94_t[15:08] - RSVD */ 4109 uint32_t nvr94 : 8; /* FUR_MODULE_CNTRL_RAM_NVR94_t[07:00] - WO */ 4110 #endif /* IS_BIG_ENDIAN */ 4111 #if IS_LITTLE_ENDIAN 4112 uint32_t nvr94 : 8; /* FUR_MODULE_CNTRL_RAM_NVR94_t[07:00] - WO */ 4113 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR94_t[15:08] - RSVD */ 4114 uint32_t reserved : 16; 4115 #endif /* IS_LITTLE_ENDIAN */ 4116 } fields; 4117 } FUR_MODULE_CNTRL_RAM_NVR94_t; 4118 4119 4120 typedef union { 4121 uint32_t data; 4122 struct { 4123 #if IS_BIG_ENDIAN 4124 uint32_t reserved : 16; 4125 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR95_t[15:08] - RSVD */ 4126 uint32_t nvr95 : 8; /* FUR_MODULE_CNTRL_RAM_NVR95_t[07:00] - WO */ 4127 #endif /* IS_BIG_ENDIAN */ 4128 #if IS_LITTLE_ENDIAN 4129 uint32_t nvr95 : 8; /* FUR_MODULE_CNTRL_RAM_NVR95_t[07:00] - WO */ 4130 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR95_t[15:08] - RSVD */ 4131 uint32_t reserved : 16; 4132 #endif /* IS_LITTLE_ENDIAN */ 4133 } fields; 4134 } FUR_MODULE_CNTRL_RAM_NVR95_t; 4135 4136 4137 typedef union { 4138 uint32_t data; 4139 struct { 4140 #if IS_BIG_ENDIAN 4141 uint32_t reserved : 16; 4142 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR96_t[15:08] - RSVD */ 4143 uint32_t nvr96 : 8; /* FUR_MODULE_CNTRL_RAM_NVR96_t[07:00] - WO */ 4144 #endif /* IS_BIG_ENDIAN */ 4145 #if IS_LITTLE_ENDIAN 4146 uint32_t nvr96 : 8; /* FUR_MODULE_CNTRL_RAM_NVR96_t[07:00] - WO */ 4147 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR96_t[15:08] - RSVD */ 4148 uint32_t reserved : 16; 4149 #endif /* IS_LITTLE_ENDIAN */ 4150 } fields; 4151 } FUR_MODULE_CNTRL_RAM_NVR96_t; 4152 4153 4154 typedef union { 4155 uint32_t data; 4156 struct { 4157 #if IS_BIG_ENDIAN 4158 uint32_t reserved : 16; 4159 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR97_t[15:08] - RSVD */ 4160 uint32_t nvr97 : 8; /* FUR_MODULE_CNTRL_RAM_NVR97_t[07:00] - WO */ 4161 #endif /* IS_BIG_ENDIAN */ 4162 #if IS_LITTLE_ENDIAN 4163 uint32_t nvr97 : 8; /* FUR_MODULE_CNTRL_RAM_NVR97_t[07:00] - WO */ 4164 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR97_t[15:08] - RSVD */ 4165 uint32_t reserved : 16; 4166 #endif /* IS_LITTLE_ENDIAN */ 4167 } fields; 4168 } FUR_MODULE_CNTRL_RAM_NVR97_t; 4169 4170 4171 typedef union { 4172 uint32_t data; 4173 struct { 4174 #if IS_BIG_ENDIAN 4175 uint32_t reserved : 16; 4176 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR98_t[15:08] - RSVD */ 4177 uint32_t nvr98 : 8; /* FUR_MODULE_CNTRL_RAM_NVR98_t[07:00] - WO */ 4178 #endif /* IS_BIG_ENDIAN */ 4179 #if IS_LITTLE_ENDIAN 4180 uint32_t nvr98 : 8; /* FUR_MODULE_CNTRL_RAM_NVR98_t[07:00] - WO */ 4181 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR98_t[15:08] - RSVD */ 4182 uint32_t reserved : 16; 4183 #endif /* IS_LITTLE_ENDIAN */ 4184 } fields; 4185 } FUR_MODULE_CNTRL_RAM_NVR98_t; 4186 4187 4188 typedef union { 4189 uint32_t data; 4190 struct { 4191 #if IS_BIG_ENDIAN 4192 uint32_t reserved : 16; 4193 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR99_t[15:08] - RSVD */ 4194 uint32_t nvr99 : 8; /* FUR_MODULE_CNTRL_RAM_NVR99_t[07:00] - WO */ 4195 #endif /* IS_BIG_ENDIAN */ 4196 #if IS_LITTLE_ENDIAN 4197 uint32_t nvr99 : 8; /* FUR_MODULE_CNTRL_RAM_NVR99_t[07:00] - WO */ 4198 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR99_t[15:08] - RSVD */ 4199 uint32_t reserved : 16; 4200 #endif /* IS_LITTLE_ENDIAN */ 4201 } fields; 4202 } FUR_MODULE_CNTRL_RAM_NVR99_t; 4203 4204 4205 typedef union { 4206 uint32_t data; 4207 struct { 4208 #if IS_BIG_ENDIAN 4209 uint32_t reserved : 16; 4210 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR100_t[15:08] - RSVD */ 4211 uint32_t nvr100 : 8; /* FUR_MODULE_CNTRL_RAM_NVR100_t[07:00] - WO */ 4212 #endif /* IS_BIG_ENDIAN */ 4213 #if IS_LITTLE_ENDIAN 4214 uint32_t nvr100 : 8; /* FUR_MODULE_CNTRL_RAM_NVR100_t[07:00] - WO */ 4215 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR100_t[15:08] - RSVD */ 4216 uint32_t reserved : 16; 4217 #endif /* IS_LITTLE_ENDIAN */ 4218 } fields; 4219 } FUR_MODULE_CNTRL_RAM_NVR100_t; 4220 4221 4222 typedef union { 4223 uint32_t data; 4224 struct { 4225 #if IS_BIG_ENDIAN 4226 uint32_t reserved : 16; 4227 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR101_t[15:08] - RSVD */ 4228 uint32_t nvr101 : 8; /* FUR_MODULE_CNTRL_RAM_NVR101_t[07:00] - WO */ 4229 #endif /* IS_BIG_ENDIAN */ 4230 #if IS_LITTLE_ENDIAN 4231 uint32_t nvr101 : 8; /* FUR_MODULE_CNTRL_RAM_NVR101_t[07:00] - WO */ 4232 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR101_t[15:08] - RSVD */ 4233 uint32_t reserved : 16; 4234 #endif /* IS_LITTLE_ENDIAN */ 4235 } fields; 4236 } FUR_MODULE_CNTRL_RAM_NVR101_t; 4237 4238 4239 typedef union { 4240 uint32_t data; 4241 struct { 4242 #if IS_BIG_ENDIAN 4243 uint32_t reserved : 16; 4244 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR102_t[15:08] - RSVD */ 4245 uint32_t nvr102 : 8; /* FUR_MODULE_CNTRL_RAM_NVR102_t[07:00] - WO */ 4246 #endif /* IS_BIG_ENDIAN */ 4247 #if IS_LITTLE_ENDIAN 4248 uint32_t nvr102 : 8; /* FUR_MODULE_CNTRL_RAM_NVR102_t[07:00] - WO */ 4249 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR102_t[15:08] - RSVD */ 4250 uint32_t reserved : 16; 4251 #endif /* IS_LITTLE_ENDIAN */ 4252 } fields; 4253 } FUR_MODULE_CNTRL_RAM_NVR102_t; 4254 4255 4256 typedef union { 4257 uint32_t data; 4258 struct { 4259 #if IS_BIG_ENDIAN 4260 uint32_t reserved : 16; 4261 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR103_t[15:08] - RSVD */ 4262 uint32_t nvr103 : 8; /* FUR_MODULE_CNTRL_RAM_NVR103_t[07:00] - WO */ 4263 #endif /* IS_BIG_ENDIAN */ 4264 #if IS_LITTLE_ENDIAN 4265 uint32_t nvr103 : 8; /* FUR_MODULE_CNTRL_RAM_NVR103_t[07:00] - WO */ 4266 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR103_t[15:08] - RSVD */ 4267 uint32_t reserved : 16; 4268 #endif /* IS_LITTLE_ENDIAN */ 4269 } fields; 4270 } FUR_MODULE_CNTRL_RAM_NVR103_t; 4271 4272 4273 typedef union { 4274 uint32_t data; 4275 struct { 4276 #if IS_BIG_ENDIAN 4277 uint32_t reserved : 16; 4278 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR104_t[15:08] - RSVD */ 4279 uint32_t nvr104 : 8; /* FUR_MODULE_CNTRL_RAM_NVR104_t[07:00] - WO */ 4280 #endif /* IS_BIG_ENDIAN */ 4281 #if IS_LITTLE_ENDIAN 4282 uint32_t nvr104 : 8; /* FUR_MODULE_CNTRL_RAM_NVR104_t[07:00] - WO */ 4283 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR104_t[15:08] - RSVD */ 4284 uint32_t reserved : 16; 4285 #endif /* IS_LITTLE_ENDIAN */ 4286 } fields; 4287 } FUR_MODULE_CNTRL_RAM_NVR104_t; 4288 4289 4290 typedef union { 4291 uint32_t data; 4292 struct { 4293 #if IS_BIG_ENDIAN 4294 uint32_t reserved : 16; 4295 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR105_t[15:08] - RSVD */ 4296 uint32_t nvr105 : 8; /* FUR_MODULE_CNTRL_RAM_NVR105_t[07:00] - WO */ 4297 #endif /* IS_BIG_ENDIAN */ 4298 #if IS_LITTLE_ENDIAN 4299 uint32_t nvr105 : 8; /* FUR_MODULE_CNTRL_RAM_NVR105_t[07:00] - WO */ 4300 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR105_t[15:08] - RSVD */ 4301 uint32_t reserved : 16; 4302 #endif /* IS_LITTLE_ENDIAN */ 4303 } fields; 4304 } FUR_MODULE_CNTRL_RAM_NVR105_t; 4305 4306 4307 typedef union { 4308 uint32_t data; 4309 struct { 4310 #if IS_BIG_ENDIAN 4311 uint32_t reserved : 16; 4312 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR106_t[15:08] - RSVD */ 4313 uint32_t nvr106 : 8; /* FUR_MODULE_CNTRL_RAM_NVR106_t[07:00] - WO */ 4314 #endif /* IS_BIG_ENDIAN */ 4315 #if IS_LITTLE_ENDIAN 4316 uint32_t nvr106 : 8; /* FUR_MODULE_CNTRL_RAM_NVR106_t[07:00] - WO */ 4317 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR106_t[15:08] - RSVD */ 4318 uint32_t reserved : 16; 4319 #endif /* IS_LITTLE_ENDIAN */ 4320 } fields; 4321 } FUR_MODULE_CNTRL_RAM_NVR106_t; 4322 4323 4324 typedef union { 4325 uint32_t data; 4326 struct { 4327 #if IS_BIG_ENDIAN 4328 uint32_t reserved : 16; 4329 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR107_t[15:08] - RSVD */ 4330 uint32_t nvr107 : 8; /* FUR_MODULE_CNTRL_RAM_NVR107_t[07:00] - WO */ 4331 #endif /* IS_BIG_ENDIAN */ 4332 #if IS_LITTLE_ENDIAN 4333 uint32_t nvr107 : 8; /* FUR_MODULE_CNTRL_RAM_NVR107_t[07:00] - WO */ 4334 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR107_t[15:08] - RSVD */ 4335 uint32_t reserved : 16; 4336 #endif /* IS_LITTLE_ENDIAN */ 4337 } fields; 4338 } FUR_MODULE_CNTRL_RAM_NVR107_t; 4339 4340 4341 typedef union { 4342 uint32_t data; 4343 struct { 4344 #if IS_BIG_ENDIAN 4345 uint32_t reserved : 16; 4346 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR108_t[15:08] - RSVD */ 4347 uint32_t nvr108 : 8; /* FUR_MODULE_CNTRL_RAM_NVR108_t[07:00] - WO */ 4348 #endif /* IS_BIG_ENDIAN */ 4349 #if IS_LITTLE_ENDIAN 4350 uint32_t nvr108 : 8; /* FUR_MODULE_CNTRL_RAM_NVR108_t[07:00] - WO */ 4351 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR108_t[15:08] - RSVD */ 4352 uint32_t reserved : 16; 4353 #endif /* IS_LITTLE_ENDIAN */ 4354 } fields; 4355 } FUR_MODULE_CNTRL_RAM_NVR108_t; 4356 4357 4358 typedef union { 4359 uint32_t data; 4360 struct { 4361 #if IS_BIG_ENDIAN 4362 uint32_t reserved : 16; 4363 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR109_t[15:08] - RSVD */ 4364 uint32_t nvr109 : 8; /* FUR_MODULE_CNTRL_RAM_NVR109_t[07:00] - WO */ 4365 #endif /* IS_BIG_ENDIAN */ 4366 #if IS_LITTLE_ENDIAN 4367 uint32_t nvr109 : 8; /* FUR_MODULE_CNTRL_RAM_NVR109_t[07:00] - WO */ 4368 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR109_t[15:08] - RSVD */ 4369 uint32_t reserved : 16; 4370 #endif /* IS_LITTLE_ENDIAN */ 4371 } fields; 4372 } FUR_MODULE_CNTRL_RAM_NVR109_t; 4373 4374 4375 typedef union { 4376 uint32_t data; 4377 struct { 4378 #if IS_BIG_ENDIAN 4379 uint32_t reserved : 16; 4380 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR110_t[15:08] - RSVD */ 4381 uint32_t nvr110 : 8; /* FUR_MODULE_CNTRL_RAM_NVR110_t[07:00] - WO */ 4382 #endif /* IS_BIG_ENDIAN */ 4383 #if IS_LITTLE_ENDIAN 4384 uint32_t nvr110 : 8; /* FUR_MODULE_CNTRL_RAM_NVR110_t[07:00] - WO */ 4385 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR110_t[15:08] - RSVD */ 4386 uint32_t reserved : 16; 4387 #endif /* IS_LITTLE_ENDIAN */ 4388 } fields; 4389 } FUR_MODULE_CNTRL_RAM_NVR110_t; 4390 4391 4392 typedef union { 4393 uint32_t data; 4394 struct { 4395 #if IS_BIG_ENDIAN 4396 uint32_t reserved : 16; 4397 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR111_t[15:08] - RSVD */ 4398 uint32_t nvr111 : 8; /* FUR_MODULE_CNTRL_RAM_NVR111_t[07:00] - WO */ 4399 #endif /* IS_BIG_ENDIAN */ 4400 #if IS_LITTLE_ENDIAN 4401 uint32_t nvr111 : 8; /* FUR_MODULE_CNTRL_RAM_NVR111_t[07:00] - WO */ 4402 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR111_t[15:08] - RSVD */ 4403 uint32_t reserved : 16; 4404 #endif /* IS_LITTLE_ENDIAN */ 4405 } fields; 4406 } FUR_MODULE_CNTRL_RAM_NVR111_t; 4407 4408 4409 typedef union { 4410 uint32_t data; 4411 struct { 4412 #if IS_BIG_ENDIAN 4413 uint32_t reserved : 16; 4414 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR112_t[15:08] - RSVD */ 4415 uint32_t nvr112 : 8; /* FUR_MODULE_CNTRL_RAM_NVR112_t[07:00] - WO */ 4416 #endif /* IS_BIG_ENDIAN */ 4417 #if IS_LITTLE_ENDIAN 4418 uint32_t nvr112 : 8; /* FUR_MODULE_CNTRL_RAM_NVR112_t[07:00] - WO */ 4419 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR112_t[15:08] - RSVD */ 4420 uint32_t reserved : 16; 4421 #endif /* IS_LITTLE_ENDIAN */ 4422 } fields; 4423 } FUR_MODULE_CNTRL_RAM_NVR112_t; 4424 4425 4426 typedef union { 4427 uint32_t data; 4428 struct { 4429 #if IS_BIG_ENDIAN 4430 uint32_t reserved : 16; 4431 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR113_t[15:08] - RSVD */ 4432 uint32_t nvr113 : 8; /* FUR_MODULE_CNTRL_RAM_NVR113_t[07:00] - WO */ 4433 #endif /* IS_BIG_ENDIAN */ 4434 #if IS_LITTLE_ENDIAN 4435 uint32_t nvr113 : 8; /* FUR_MODULE_CNTRL_RAM_NVR113_t[07:00] - WO */ 4436 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR113_t[15:08] - RSVD */ 4437 uint32_t reserved : 16; 4438 #endif /* IS_LITTLE_ENDIAN */ 4439 } fields; 4440 } FUR_MODULE_CNTRL_RAM_NVR113_t; 4441 4442 4443 typedef union { 4444 uint32_t data; 4445 struct { 4446 #if IS_BIG_ENDIAN 4447 uint32_t reserved : 16; 4448 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR114_t[15:08] - RSVD */ 4449 uint32_t nvr114 : 8; /* FUR_MODULE_CNTRL_RAM_NVR114_t[07:00] - WO */ 4450 #endif /* IS_BIG_ENDIAN */ 4451 #if IS_LITTLE_ENDIAN 4452 uint32_t nvr114 : 8; /* FUR_MODULE_CNTRL_RAM_NVR114_t[07:00] - WO */ 4453 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR114_t[15:08] - RSVD */ 4454 uint32_t reserved : 16; 4455 #endif /* IS_LITTLE_ENDIAN */ 4456 } fields; 4457 } FUR_MODULE_CNTRL_RAM_NVR114_t; 4458 4459 4460 typedef union { 4461 uint32_t data; 4462 struct { 4463 #if IS_BIG_ENDIAN 4464 uint32_t reserved : 16; 4465 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR115_t[15:08] - RSVD */ 4466 uint32_t nvr115 : 8; /* FUR_MODULE_CNTRL_RAM_NVR115_t[07:00] - WO */ 4467 #endif /* IS_BIG_ENDIAN */ 4468 #if IS_LITTLE_ENDIAN 4469 uint32_t nvr115 : 8; /* FUR_MODULE_CNTRL_RAM_NVR115_t[07:00] - WO */ 4470 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR115_t[15:08] - RSVD */ 4471 uint32_t reserved : 16; 4472 #endif /* IS_LITTLE_ENDIAN */ 4473 } fields; 4474 } FUR_MODULE_CNTRL_RAM_NVR115_t; 4475 4476 4477 typedef union { 4478 uint32_t data; 4479 struct { 4480 #if IS_BIG_ENDIAN 4481 uint32_t reserved : 16; 4482 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR116_t[15:08] - RSVD */ 4483 uint32_t nvr116 : 8; /* FUR_MODULE_CNTRL_RAM_NVR116_t[07:00] - WO */ 4484 #endif /* IS_BIG_ENDIAN */ 4485 #if IS_LITTLE_ENDIAN 4486 uint32_t nvr116 : 8; /* FUR_MODULE_CNTRL_RAM_NVR116_t[07:00] - WO */ 4487 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR116_t[15:08] - RSVD */ 4488 uint32_t reserved : 16; 4489 #endif /* IS_LITTLE_ENDIAN */ 4490 } fields; 4491 } FUR_MODULE_CNTRL_RAM_NVR116_t; 4492 4493 4494 typedef union { 4495 uint32_t data; 4496 struct { 4497 #if IS_BIG_ENDIAN 4498 uint32_t reserved : 16; 4499 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR117_t[15:08] - RSVD */ 4500 uint32_t nvr117 : 8; /* FUR_MODULE_CNTRL_RAM_NVR117_t[07:00] - WO */ 4501 #endif /* IS_BIG_ENDIAN */ 4502 #if IS_LITTLE_ENDIAN 4503 uint32_t nvr117 : 8; /* FUR_MODULE_CNTRL_RAM_NVR117_t[07:00] - WO */ 4504 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR117_t[15:08] - RSVD */ 4505 uint32_t reserved : 16; 4506 #endif /* IS_LITTLE_ENDIAN */ 4507 } fields; 4508 } FUR_MODULE_CNTRL_RAM_NVR117_t; 4509 4510 4511 typedef union { 4512 uint32_t data; 4513 struct { 4514 #if IS_BIG_ENDIAN 4515 uint32_t reserved : 16; 4516 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR118_t[15:08] - RSVD */ 4517 uint32_t nvr118 : 8; /* FUR_MODULE_CNTRL_RAM_NVR118_t[07:00] - WO */ 4518 #endif /* IS_BIG_ENDIAN */ 4519 #if IS_LITTLE_ENDIAN 4520 uint32_t nvr118 : 8; /* FUR_MODULE_CNTRL_RAM_NVR118_t[07:00] - WO */ 4521 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR118_t[15:08] - RSVD */ 4522 uint32_t reserved : 16; 4523 #endif /* IS_LITTLE_ENDIAN */ 4524 } fields; 4525 } FUR_MODULE_CNTRL_RAM_NVR118_t; 4526 4527 4528 typedef union { 4529 uint32_t data; 4530 struct { 4531 #if IS_BIG_ENDIAN 4532 uint32_t reserved : 16; 4533 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR119_t[15:08] - RSVD */ 4534 uint32_t nvr119 : 8; /* FUR_MODULE_CNTRL_RAM_NVR119_t[07:00] - WO */ 4535 #endif /* IS_BIG_ENDIAN */ 4536 #if IS_LITTLE_ENDIAN 4537 uint32_t nvr119 : 8; /* FUR_MODULE_CNTRL_RAM_NVR119_t[07:00] - WO */ 4538 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR119_t[15:08] - RSVD */ 4539 uint32_t reserved : 16; 4540 #endif /* IS_LITTLE_ENDIAN */ 4541 } fields; 4542 } FUR_MODULE_CNTRL_RAM_NVR119_t; 4543 4544 4545 typedef union { 4546 uint32_t data; 4547 struct { 4548 #if IS_BIG_ENDIAN 4549 uint32_t reserved : 16; 4550 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR120_t[15:08] - RSVD */ 4551 uint32_t nvr120 : 8; /* FUR_MODULE_CNTRL_RAM_NVR120_t[07:00] - WO */ 4552 #endif /* IS_BIG_ENDIAN */ 4553 #if IS_LITTLE_ENDIAN 4554 uint32_t nvr120 : 8; /* FUR_MODULE_CNTRL_RAM_NVR120_t[07:00] - WO */ 4555 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR120_t[15:08] - RSVD */ 4556 uint32_t reserved : 16; 4557 #endif /* IS_LITTLE_ENDIAN */ 4558 } fields; 4559 } FUR_MODULE_CNTRL_RAM_NVR120_t; 4560 4561 4562 typedef union { 4563 uint32_t data; 4564 struct { 4565 #if IS_BIG_ENDIAN 4566 uint32_t reserved : 16; 4567 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR121_t[15:08] - RSVD */ 4568 uint32_t nvr121 : 8; /* FUR_MODULE_CNTRL_RAM_NVR121_t[07:00] - WO */ 4569 #endif /* IS_BIG_ENDIAN */ 4570 #if IS_LITTLE_ENDIAN 4571 uint32_t nvr121 : 8; /* FUR_MODULE_CNTRL_RAM_NVR121_t[07:00] - WO */ 4572 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR121_t[15:08] - RSVD */ 4573 uint32_t reserved : 16; 4574 #endif /* IS_LITTLE_ENDIAN */ 4575 } fields; 4576 } FUR_MODULE_CNTRL_RAM_NVR121_t; 4577 4578 4579 typedef union { 4580 uint32_t data; 4581 struct { 4582 #if IS_BIG_ENDIAN 4583 uint32_t reserved : 16; 4584 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR122_t[15:08] - RSVD */ 4585 uint32_t nvr122 : 8; /* FUR_MODULE_CNTRL_RAM_NVR122_t[07:00] - WO */ 4586 #endif /* IS_BIG_ENDIAN */ 4587 #if IS_LITTLE_ENDIAN 4588 uint32_t nvr122 : 8; /* FUR_MODULE_CNTRL_RAM_NVR122_t[07:00] - WO */ 4589 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR122_t[15:08] - RSVD */ 4590 uint32_t reserved : 16; 4591 #endif /* IS_LITTLE_ENDIAN */ 4592 } fields; 4593 } FUR_MODULE_CNTRL_RAM_NVR122_t; 4594 4595 4596 typedef union { 4597 uint32_t data; 4598 struct { 4599 #if IS_BIG_ENDIAN 4600 uint32_t reserved : 16; 4601 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR123_t[15:08] - RSVD */ 4602 uint32_t nvr123 : 8; /* FUR_MODULE_CNTRL_RAM_NVR123_t[07:00] - WO */ 4603 #endif /* IS_BIG_ENDIAN */ 4604 #if IS_LITTLE_ENDIAN 4605 uint32_t nvr123 : 8; /* FUR_MODULE_CNTRL_RAM_NVR123_t[07:00] - WO */ 4606 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR123_t[15:08] - RSVD */ 4607 uint32_t reserved : 16; 4608 #endif /* IS_LITTLE_ENDIAN */ 4609 } fields; 4610 } FUR_MODULE_CNTRL_RAM_NVR123_t; 4611 4612 4613 typedef union { 4614 uint32_t data; 4615 struct { 4616 #if IS_BIG_ENDIAN 4617 uint32_t reserved : 16; 4618 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR124_t[15:08] - RSVD */ 4619 uint32_t nvr124 : 8; /* FUR_MODULE_CNTRL_RAM_NVR124_t[07:00] - WO */ 4620 #endif /* IS_BIG_ENDIAN */ 4621 #if IS_LITTLE_ENDIAN 4622 uint32_t nvr124 : 8; /* FUR_MODULE_CNTRL_RAM_NVR124_t[07:00] - WO */ 4623 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR124_t[15:08] - RSVD */ 4624 uint32_t reserved : 16; 4625 #endif /* IS_LITTLE_ENDIAN */ 4626 } fields; 4627 } FUR_MODULE_CNTRL_RAM_NVR124_t; 4628 4629 4630 typedef union { 4631 uint32_t data; 4632 struct { 4633 #if IS_BIG_ENDIAN 4634 uint32_t reserved : 16; 4635 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR125_t[15:08] - RSVD */ 4636 uint32_t nvr125 : 8; /* FUR_MODULE_CNTRL_RAM_NVR125_t[07:00] - WO */ 4637 #endif /* IS_BIG_ENDIAN */ 4638 #if IS_LITTLE_ENDIAN 4639 uint32_t nvr125 : 8; /* FUR_MODULE_CNTRL_RAM_NVR125_t[07:00] - WO */ 4640 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR125_t[15:08] - RSVD */ 4641 uint32_t reserved : 16; 4642 #endif /* IS_LITTLE_ENDIAN */ 4643 } fields; 4644 } FUR_MODULE_CNTRL_RAM_NVR125_t; 4645 4646 4647 typedef union { 4648 uint32_t data; 4649 struct { 4650 #if IS_BIG_ENDIAN 4651 uint32_t reserved : 16; 4652 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR126_t[15:08] - RSVD */ 4653 uint32_t nvr126 : 8; /* FUR_MODULE_CNTRL_RAM_NVR126_t[07:00] - WO */ 4654 #endif /* IS_BIG_ENDIAN */ 4655 #if IS_LITTLE_ENDIAN 4656 uint32_t nvr126 : 8; /* FUR_MODULE_CNTRL_RAM_NVR126_t[07:00] - WO */ 4657 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR126_t[15:08] - RSVD */ 4658 uint32_t reserved : 16; 4659 #endif /* IS_LITTLE_ENDIAN */ 4660 } fields; 4661 } FUR_MODULE_CNTRL_RAM_NVR126_t; 4662 4663 4664 typedef union { 4665 uint32_t data; 4666 struct { 4667 #if IS_BIG_ENDIAN 4668 uint32_t reserved : 16; 4669 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR127_t[15:08] - RSVD */ 4670 uint32_t nvr127 : 8; /* FUR_MODULE_CNTRL_RAM_NVR127_t[07:00] - WO */ 4671 #endif /* IS_BIG_ENDIAN */ 4672 #if IS_LITTLE_ENDIAN 4673 uint32_t nvr127 : 8; /* FUR_MODULE_CNTRL_RAM_NVR127_t[07:00] - WO */ 4674 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR127_t[15:08] - RSVD */ 4675 uint32_t reserved : 16; 4676 #endif /* IS_LITTLE_ENDIAN */ 4677 } fields; 4678 } FUR_MODULE_CNTRL_RAM_NVR127_t; 4679 4680 4681 typedef union { 4682 uint32_t data; 4683 struct { 4684 #if IS_BIG_ENDIAN 4685 uint32_t reserved : 16; 4686 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR128_t[15:08] - RSVD */ 4687 uint32_t nvr128 : 8; /* FUR_MODULE_CNTRL_RAM_NVR128_t[07:00] - WO */ 4688 #endif /* IS_BIG_ENDIAN */ 4689 #if IS_LITTLE_ENDIAN 4690 uint32_t nvr128 : 8; /* FUR_MODULE_CNTRL_RAM_NVR128_t[07:00] - WO */ 4691 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR128_t[15:08] - RSVD */ 4692 uint32_t reserved : 16; 4693 #endif /* IS_LITTLE_ENDIAN */ 4694 } fields; 4695 } FUR_MODULE_CNTRL_RAM_NVR128_t; 4696 4697 4698 typedef union { 4699 uint32_t data; 4700 struct { 4701 #if IS_BIG_ENDIAN 4702 uint32_t reserved : 16; 4703 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR129_t[15:08] - RSVD */ 4704 uint32_t nvr129 : 8; /* FUR_MODULE_CNTRL_RAM_NVR129_t[07:00] - WO */ 4705 #endif /* IS_BIG_ENDIAN */ 4706 #if IS_LITTLE_ENDIAN 4707 uint32_t nvr129 : 8; /* FUR_MODULE_CNTRL_RAM_NVR129_t[07:00] - WO */ 4708 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR129_t[15:08] - RSVD */ 4709 uint32_t reserved : 16; 4710 #endif /* IS_LITTLE_ENDIAN */ 4711 } fields; 4712 } FUR_MODULE_CNTRL_RAM_NVR129_t; 4713 4714 4715 typedef union { 4716 uint32_t data; 4717 struct { 4718 #if IS_BIG_ENDIAN 4719 uint32_t reserved : 16; 4720 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR130_t[15:08] - RSVD */ 4721 uint32_t nvr130 : 8; /* FUR_MODULE_CNTRL_RAM_NVR130_t[07:00] - WO */ 4722 #endif /* IS_BIG_ENDIAN */ 4723 #if IS_LITTLE_ENDIAN 4724 uint32_t nvr130 : 8; /* FUR_MODULE_CNTRL_RAM_NVR130_t[07:00] - WO */ 4725 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR130_t[15:08] - RSVD */ 4726 uint32_t reserved : 16; 4727 #endif /* IS_LITTLE_ENDIAN */ 4728 } fields; 4729 } FUR_MODULE_CNTRL_RAM_NVR130_t; 4730 4731 4732 typedef union { 4733 uint32_t data; 4734 struct { 4735 #if IS_BIG_ENDIAN 4736 uint32_t reserved : 16; 4737 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR131_t[15:08] - RSVD */ 4738 uint32_t nvr131 : 8; /* FUR_MODULE_CNTRL_RAM_NVR131_t[07:00] - WO */ 4739 #endif /* IS_BIG_ENDIAN */ 4740 #if IS_LITTLE_ENDIAN 4741 uint32_t nvr131 : 8; /* FUR_MODULE_CNTRL_RAM_NVR131_t[07:00] - WO */ 4742 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR131_t[15:08] - RSVD */ 4743 uint32_t reserved : 16; 4744 #endif /* IS_LITTLE_ENDIAN */ 4745 } fields; 4746 } FUR_MODULE_CNTRL_RAM_NVR131_t; 4747 4748 4749 typedef union { 4750 uint32_t data; 4751 struct { 4752 #if IS_BIG_ENDIAN 4753 uint32_t reserved : 16; 4754 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR132_t[15:08] - RSVD */ 4755 uint32_t nvr132 : 8; /* FUR_MODULE_CNTRL_RAM_NVR132_t[07:00] - WO */ 4756 #endif /* IS_BIG_ENDIAN */ 4757 #if IS_LITTLE_ENDIAN 4758 uint32_t nvr132 : 8; /* FUR_MODULE_CNTRL_RAM_NVR132_t[07:00] - WO */ 4759 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR132_t[15:08] - RSVD */ 4760 uint32_t reserved : 16; 4761 #endif /* IS_LITTLE_ENDIAN */ 4762 } fields; 4763 } FUR_MODULE_CNTRL_RAM_NVR132_t; 4764 4765 4766 typedef union { 4767 uint32_t data; 4768 struct { 4769 #if IS_BIG_ENDIAN 4770 uint32_t reserved : 16; 4771 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR133_t[15:08] - RSVD */ 4772 uint32_t nvr133 : 8; /* FUR_MODULE_CNTRL_RAM_NVR133_t[07:00] - WO */ 4773 #endif /* IS_BIG_ENDIAN */ 4774 #if IS_LITTLE_ENDIAN 4775 uint32_t nvr133 : 8; /* FUR_MODULE_CNTRL_RAM_NVR133_t[07:00] - WO */ 4776 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR133_t[15:08] - RSVD */ 4777 uint32_t reserved : 16; 4778 #endif /* IS_LITTLE_ENDIAN */ 4779 } fields; 4780 } FUR_MODULE_CNTRL_RAM_NVR133_t; 4781 4782 4783 typedef union { 4784 uint32_t data; 4785 struct { 4786 #if IS_BIG_ENDIAN 4787 uint32_t reserved : 16; 4788 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR134_t[15:08] - RSVD */ 4789 uint32_t nvr134 : 8; /* FUR_MODULE_CNTRL_RAM_NVR134_t[07:00] - WO */ 4790 #endif /* IS_BIG_ENDIAN */ 4791 #if IS_LITTLE_ENDIAN 4792 uint32_t nvr134 : 8; /* FUR_MODULE_CNTRL_RAM_NVR134_t[07:00] - WO */ 4793 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR134_t[15:08] - RSVD */ 4794 uint32_t reserved : 16; 4795 #endif /* IS_LITTLE_ENDIAN */ 4796 } fields; 4797 } FUR_MODULE_CNTRL_RAM_NVR134_t; 4798 4799 4800 typedef union { 4801 uint32_t data; 4802 struct { 4803 #if IS_BIG_ENDIAN 4804 uint32_t reserved : 16; 4805 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR135_t[15:08] - RSVD */ 4806 uint32_t nvr135 : 8; /* FUR_MODULE_CNTRL_RAM_NVR135_t[07:00] - WO */ 4807 #endif /* IS_BIG_ENDIAN */ 4808 #if IS_LITTLE_ENDIAN 4809 uint32_t nvr135 : 8; /* FUR_MODULE_CNTRL_RAM_NVR135_t[07:00] - WO */ 4810 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR135_t[15:08] - RSVD */ 4811 uint32_t reserved : 16; 4812 #endif /* IS_LITTLE_ENDIAN */ 4813 } fields; 4814 } FUR_MODULE_CNTRL_RAM_NVR135_t; 4815 4816 4817 typedef union { 4818 uint32_t data; 4819 struct { 4820 #if IS_BIG_ENDIAN 4821 uint32_t reserved : 16; 4822 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR136_t[15:08] - RSVD */ 4823 uint32_t nvr136 : 8; /* FUR_MODULE_CNTRL_RAM_NVR136_t[07:00] - WO */ 4824 #endif /* IS_BIG_ENDIAN */ 4825 #if IS_LITTLE_ENDIAN 4826 uint32_t nvr136 : 8; /* FUR_MODULE_CNTRL_RAM_NVR136_t[07:00] - WO */ 4827 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR136_t[15:08] - RSVD */ 4828 uint32_t reserved : 16; 4829 #endif /* IS_LITTLE_ENDIAN */ 4830 } fields; 4831 } FUR_MODULE_CNTRL_RAM_NVR136_t; 4832 4833 4834 typedef union { 4835 uint32_t data; 4836 struct { 4837 #if IS_BIG_ENDIAN 4838 uint32_t reserved : 16; 4839 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR137_t[15:08] - RSVD */ 4840 uint32_t nvr137 : 8; /* FUR_MODULE_CNTRL_RAM_NVR137_t[07:00] - WO */ 4841 #endif /* IS_BIG_ENDIAN */ 4842 #if IS_LITTLE_ENDIAN 4843 uint32_t nvr137 : 8; /* FUR_MODULE_CNTRL_RAM_NVR137_t[07:00] - WO */ 4844 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR137_t[15:08] - RSVD */ 4845 uint32_t reserved : 16; 4846 #endif /* IS_LITTLE_ENDIAN */ 4847 } fields; 4848 } FUR_MODULE_CNTRL_RAM_NVR137_t; 4849 4850 4851 typedef union { 4852 uint32_t data; 4853 struct { 4854 #if IS_BIG_ENDIAN 4855 uint32_t reserved : 16; 4856 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR138_t[15:08] - RSVD */ 4857 uint32_t nvr138 : 8; /* FUR_MODULE_CNTRL_RAM_NVR138_t[07:00] - WO */ 4858 #endif /* IS_BIG_ENDIAN */ 4859 #if IS_LITTLE_ENDIAN 4860 uint32_t nvr138 : 8; /* FUR_MODULE_CNTRL_RAM_NVR138_t[07:00] - WO */ 4861 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR138_t[15:08] - RSVD */ 4862 uint32_t reserved : 16; 4863 #endif /* IS_LITTLE_ENDIAN */ 4864 } fields; 4865 } FUR_MODULE_CNTRL_RAM_NVR138_t; 4866 4867 4868 typedef union { 4869 uint32_t data; 4870 struct { 4871 #if IS_BIG_ENDIAN 4872 uint32_t reserved : 16; 4873 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR139_t[15:08] - RSVD */ 4874 uint32_t nvr139 : 8; /* FUR_MODULE_CNTRL_RAM_NVR139_t[07:00] - WO */ 4875 #endif /* IS_BIG_ENDIAN */ 4876 #if IS_LITTLE_ENDIAN 4877 uint32_t nvr139 : 8; /* FUR_MODULE_CNTRL_RAM_NVR139_t[07:00] - WO */ 4878 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR139_t[15:08] - RSVD */ 4879 uint32_t reserved : 16; 4880 #endif /* IS_LITTLE_ENDIAN */ 4881 } fields; 4882 } FUR_MODULE_CNTRL_RAM_NVR139_t; 4883 4884 4885 typedef union { 4886 uint32_t data; 4887 struct { 4888 #if IS_BIG_ENDIAN 4889 uint32_t reserved : 16; 4890 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR140_t[15:08] - RSVD */ 4891 uint32_t nvr140 : 8; /* FUR_MODULE_CNTRL_RAM_NVR140_t[07:00] - WO */ 4892 #endif /* IS_BIG_ENDIAN */ 4893 #if IS_LITTLE_ENDIAN 4894 uint32_t nvr140 : 8; /* FUR_MODULE_CNTRL_RAM_NVR140_t[07:00] - WO */ 4895 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR140_t[15:08] - RSVD */ 4896 uint32_t reserved : 16; 4897 #endif /* IS_LITTLE_ENDIAN */ 4898 } fields; 4899 } FUR_MODULE_CNTRL_RAM_NVR140_t; 4900 4901 4902 typedef union { 4903 uint32_t data; 4904 struct { 4905 #if IS_BIG_ENDIAN 4906 uint32_t reserved : 16; 4907 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR141_t[15:08] - RSVD */ 4908 uint32_t nvr141 : 8; /* FUR_MODULE_CNTRL_RAM_NVR141_t[07:00] - WO */ 4909 #endif /* IS_BIG_ENDIAN */ 4910 #if IS_LITTLE_ENDIAN 4911 uint32_t nvr141 : 8; /* FUR_MODULE_CNTRL_RAM_NVR141_t[07:00] - WO */ 4912 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR141_t[15:08] - RSVD */ 4913 uint32_t reserved : 16; 4914 #endif /* IS_LITTLE_ENDIAN */ 4915 } fields; 4916 } FUR_MODULE_CNTRL_RAM_NVR141_t; 4917 4918 4919 typedef union { 4920 uint32_t data; 4921 struct { 4922 #if IS_BIG_ENDIAN 4923 uint32_t reserved : 16; 4924 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR142_t[15:08] - RSVD */ 4925 uint32_t nvr142 : 8; /* FUR_MODULE_CNTRL_RAM_NVR142_t[07:00] - WO */ 4926 #endif /* IS_BIG_ENDIAN */ 4927 #if IS_LITTLE_ENDIAN 4928 uint32_t nvr142 : 8; /* FUR_MODULE_CNTRL_RAM_NVR142_t[07:00] - WO */ 4929 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR142_t[15:08] - RSVD */ 4930 uint32_t reserved : 16; 4931 #endif /* IS_LITTLE_ENDIAN */ 4932 } fields; 4933 } FUR_MODULE_CNTRL_RAM_NVR142_t; 4934 4935 4936 typedef union { 4937 uint32_t data; 4938 struct { 4939 #if IS_BIG_ENDIAN 4940 uint32_t reserved : 16; 4941 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR143_t[15:08] - RSVD */ 4942 uint32_t nvr143 : 8; /* FUR_MODULE_CNTRL_RAM_NVR143_t[07:00] - WO */ 4943 #endif /* IS_BIG_ENDIAN */ 4944 #if IS_LITTLE_ENDIAN 4945 uint32_t nvr143 : 8; /* FUR_MODULE_CNTRL_RAM_NVR143_t[07:00] - WO */ 4946 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR143_t[15:08] - RSVD */ 4947 uint32_t reserved : 16; 4948 #endif /* IS_LITTLE_ENDIAN */ 4949 } fields; 4950 } FUR_MODULE_CNTRL_RAM_NVR143_t; 4951 4952 4953 typedef union { 4954 uint32_t data; 4955 struct { 4956 #if IS_BIG_ENDIAN 4957 uint32_t reserved : 16; 4958 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR144_t[15:08] - RSVD */ 4959 uint32_t nvr144 : 8; /* FUR_MODULE_CNTRL_RAM_NVR144_t[07:00] - WO */ 4960 #endif /* IS_BIG_ENDIAN */ 4961 #if IS_LITTLE_ENDIAN 4962 uint32_t nvr144 : 8; /* FUR_MODULE_CNTRL_RAM_NVR144_t[07:00] - WO */ 4963 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR144_t[15:08] - RSVD */ 4964 uint32_t reserved : 16; 4965 #endif /* IS_LITTLE_ENDIAN */ 4966 } fields; 4967 } FUR_MODULE_CNTRL_RAM_NVR144_t; 4968 4969 4970 typedef union { 4971 uint32_t data; 4972 struct { 4973 #if IS_BIG_ENDIAN 4974 uint32_t reserved : 16; 4975 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR145_t[15:08] - RSVD */ 4976 uint32_t nvr145 : 8; /* FUR_MODULE_CNTRL_RAM_NVR145_t[07:00] - WO */ 4977 #endif /* IS_BIG_ENDIAN */ 4978 #if IS_LITTLE_ENDIAN 4979 uint32_t nvr145 : 8; /* FUR_MODULE_CNTRL_RAM_NVR145_t[07:00] - WO */ 4980 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR145_t[15:08] - RSVD */ 4981 uint32_t reserved : 16; 4982 #endif /* IS_LITTLE_ENDIAN */ 4983 } fields; 4984 } FUR_MODULE_CNTRL_RAM_NVR145_t; 4985 4986 4987 typedef union { 4988 uint32_t data; 4989 struct { 4990 #if IS_BIG_ENDIAN 4991 uint32_t reserved : 16; 4992 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR146_t[15:08] - RSVD */ 4993 uint32_t nvr146 : 8; /* FUR_MODULE_CNTRL_RAM_NVR146_t[07:00] - WO */ 4994 #endif /* IS_BIG_ENDIAN */ 4995 #if IS_LITTLE_ENDIAN 4996 uint32_t nvr146 : 8; /* FUR_MODULE_CNTRL_RAM_NVR146_t[07:00] - WO */ 4997 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR146_t[15:08] - RSVD */ 4998 uint32_t reserved : 16; 4999 #endif /* IS_LITTLE_ENDIAN */ 5000 } fields; 5001 } FUR_MODULE_CNTRL_RAM_NVR146_t; 5002 5003 5004 typedef union { 5005 uint32_t data; 5006 struct { 5007 #if IS_BIG_ENDIAN 5008 uint32_t reserved : 16; 5009 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR147_t[15:08] - RSVD */ 5010 uint32_t nvr147 : 8; /* FUR_MODULE_CNTRL_RAM_NVR147_t[07:00] - WO */ 5011 #endif /* IS_BIG_ENDIAN */ 5012 #if IS_LITTLE_ENDIAN 5013 uint32_t nvr147 : 8; /* FUR_MODULE_CNTRL_RAM_NVR147_t[07:00] - WO */ 5014 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR147_t[15:08] - RSVD */ 5015 uint32_t reserved : 16; 5016 #endif /* IS_LITTLE_ENDIAN */ 5017 } fields; 5018 } FUR_MODULE_CNTRL_RAM_NVR147_t; 5019 5020 5021 typedef union { 5022 uint32_t data; 5023 struct { 5024 #if IS_BIG_ENDIAN 5025 uint32_t reserved : 16; 5026 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR148_t[15:08] - RSVD */ 5027 uint32_t nvr148 : 8; /* FUR_MODULE_CNTRL_RAM_NVR148_t[07:00] - WO */ 5028 #endif /* IS_BIG_ENDIAN */ 5029 #if IS_LITTLE_ENDIAN 5030 uint32_t nvr148 : 8; /* FUR_MODULE_CNTRL_RAM_NVR148_t[07:00] - WO */ 5031 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR148_t[15:08] - RSVD */ 5032 uint32_t reserved : 16; 5033 #endif /* IS_LITTLE_ENDIAN */ 5034 } fields; 5035 } FUR_MODULE_CNTRL_RAM_NVR148_t; 5036 5037 5038 typedef union { 5039 uint32_t data; 5040 struct { 5041 #if IS_BIG_ENDIAN 5042 uint32_t reserved : 16; 5043 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR149_t[15:08] - RSVD */ 5044 uint32_t nvr149 : 8; /* FUR_MODULE_CNTRL_RAM_NVR149_t[07:00] - WO */ 5045 #endif /* IS_BIG_ENDIAN */ 5046 #if IS_LITTLE_ENDIAN 5047 uint32_t nvr149 : 8; /* FUR_MODULE_CNTRL_RAM_NVR149_t[07:00] - WO */ 5048 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR149_t[15:08] - RSVD */ 5049 uint32_t reserved : 16; 5050 #endif /* IS_LITTLE_ENDIAN */ 5051 } fields; 5052 } FUR_MODULE_CNTRL_RAM_NVR149_t; 5053 5054 5055 typedef union { 5056 uint32_t data; 5057 struct { 5058 #if IS_BIG_ENDIAN 5059 uint32_t reserved : 16; 5060 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR150_t[15:08] - RSVD */ 5061 uint32_t nvr150 : 8; /* FUR_MODULE_CNTRL_RAM_NVR150_t[07:00] - WO */ 5062 #endif /* IS_BIG_ENDIAN */ 5063 #if IS_LITTLE_ENDIAN 5064 uint32_t nvr150 : 8; /* FUR_MODULE_CNTRL_RAM_NVR150_t[07:00] - WO */ 5065 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR150_t[15:08] - RSVD */ 5066 uint32_t reserved : 16; 5067 #endif /* IS_LITTLE_ENDIAN */ 5068 } fields; 5069 } FUR_MODULE_CNTRL_RAM_NVR150_t; 5070 5071 5072 typedef union { 5073 uint32_t data; 5074 struct { 5075 #if IS_BIG_ENDIAN 5076 uint32_t reserved : 16; 5077 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR151_t[15:08] - RSVD */ 5078 uint32_t nvr151 : 8; /* FUR_MODULE_CNTRL_RAM_NVR151_t[07:00] - WO */ 5079 #endif /* IS_BIG_ENDIAN */ 5080 #if IS_LITTLE_ENDIAN 5081 uint32_t nvr151 : 8; /* FUR_MODULE_CNTRL_RAM_NVR151_t[07:00] - WO */ 5082 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR151_t[15:08] - RSVD */ 5083 uint32_t reserved : 16; 5084 #endif /* IS_LITTLE_ENDIAN */ 5085 } fields; 5086 } FUR_MODULE_CNTRL_RAM_NVR151_t; 5087 5088 5089 typedef union { 5090 uint32_t data; 5091 struct { 5092 #if IS_BIG_ENDIAN 5093 uint32_t reserved : 16; 5094 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR152_t[15:08] - RSVD */ 5095 uint32_t nvr152 : 8; /* FUR_MODULE_CNTRL_RAM_NVR152_t[07:00] - WO */ 5096 #endif /* IS_BIG_ENDIAN */ 5097 #if IS_LITTLE_ENDIAN 5098 uint32_t nvr152 : 8; /* FUR_MODULE_CNTRL_RAM_NVR152_t[07:00] - WO */ 5099 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR152_t[15:08] - RSVD */ 5100 uint32_t reserved : 16; 5101 #endif /* IS_LITTLE_ENDIAN */ 5102 } fields; 5103 } FUR_MODULE_CNTRL_RAM_NVR152_t; 5104 5105 5106 typedef union { 5107 uint32_t data; 5108 struct { 5109 #if IS_BIG_ENDIAN 5110 uint32_t reserved : 16; 5111 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR153_t[15:08] - RSVD */ 5112 uint32_t nvr153 : 8; /* FUR_MODULE_CNTRL_RAM_NVR153_t[07:00] - WO */ 5113 #endif /* IS_BIG_ENDIAN */ 5114 #if IS_LITTLE_ENDIAN 5115 uint32_t nvr153 : 8; /* FUR_MODULE_CNTRL_RAM_NVR153_t[07:00] - WO */ 5116 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR153_t[15:08] - RSVD */ 5117 uint32_t reserved : 16; 5118 #endif /* IS_LITTLE_ENDIAN */ 5119 } fields; 5120 } FUR_MODULE_CNTRL_RAM_NVR153_t; 5121 5122 5123 typedef union { 5124 uint32_t data; 5125 struct { 5126 #if IS_BIG_ENDIAN 5127 uint32_t reserved : 16; 5128 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR154_t[15:08] - RSVD */ 5129 uint32_t nvr154 : 8; /* FUR_MODULE_CNTRL_RAM_NVR154_t[07:00] - WO */ 5130 #endif /* IS_BIG_ENDIAN */ 5131 #if IS_LITTLE_ENDIAN 5132 uint32_t nvr154 : 8; /* FUR_MODULE_CNTRL_RAM_NVR154_t[07:00] - WO */ 5133 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR154_t[15:08] - RSVD */ 5134 uint32_t reserved : 16; 5135 #endif /* IS_LITTLE_ENDIAN */ 5136 } fields; 5137 } FUR_MODULE_CNTRL_RAM_NVR154_t; 5138 5139 5140 typedef union { 5141 uint32_t data; 5142 struct { 5143 #if IS_BIG_ENDIAN 5144 uint32_t reserved : 16; 5145 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR155_t[15:08] - RSVD */ 5146 uint32_t nvr155 : 8; /* FUR_MODULE_CNTRL_RAM_NVR155_t[07:00] - WO */ 5147 #endif /* IS_BIG_ENDIAN */ 5148 #if IS_LITTLE_ENDIAN 5149 uint32_t nvr155 : 8; /* FUR_MODULE_CNTRL_RAM_NVR155_t[07:00] - WO */ 5150 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR155_t[15:08] - RSVD */ 5151 uint32_t reserved : 16; 5152 #endif /* IS_LITTLE_ENDIAN */ 5153 } fields; 5154 } FUR_MODULE_CNTRL_RAM_NVR155_t; 5155 5156 5157 typedef union { 5158 uint32_t data; 5159 struct { 5160 #if IS_BIG_ENDIAN 5161 uint32_t reserved : 16; 5162 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR156_t[15:08] - RSVD */ 5163 uint32_t nvr156 : 8; /* FUR_MODULE_CNTRL_RAM_NVR156_t[07:00] - WO */ 5164 #endif /* IS_BIG_ENDIAN */ 5165 #if IS_LITTLE_ENDIAN 5166 uint32_t nvr156 : 8; /* FUR_MODULE_CNTRL_RAM_NVR156_t[07:00] - WO */ 5167 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR156_t[15:08] - RSVD */ 5168 uint32_t reserved : 16; 5169 #endif /* IS_LITTLE_ENDIAN */ 5170 } fields; 5171 } FUR_MODULE_CNTRL_RAM_NVR156_t; 5172 5173 5174 typedef union { 5175 uint32_t data; 5176 struct { 5177 #if IS_BIG_ENDIAN 5178 uint32_t reserved : 16; 5179 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR157_t[15:08] - RSVD */ 5180 uint32_t nvr157 : 8; /* FUR_MODULE_CNTRL_RAM_NVR157_t[07:00] - WO */ 5181 #endif /* IS_BIG_ENDIAN */ 5182 #if IS_LITTLE_ENDIAN 5183 uint32_t nvr157 : 8; /* FUR_MODULE_CNTRL_RAM_NVR157_t[07:00] - WO */ 5184 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR157_t[15:08] - RSVD */ 5185 uint32_t reserved : 16; 5186 #endif /* IS_LITTLE_ENDIAN */ 5187 } fields; 5188 } FUR_MODULE_CNTRL_RAM_NVR157_t; 5189 5190 5191 typedef union { 5192 uint32_t data; 5193 struct { 5194 #if IS_BIG_ENDIAN 5195 uint32_t reserved : 16; 5196 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR158_t[15:08] - RSVD */ 5197 uint32_t nvr158 : 8; /* FUR_MODULE_CNTRL_RAM_NVR158_t[07:00] - WO */ 5198 #endif /* IS_BIG_ENDIAN */ 5199 #if IS_LITTLE_ENDIAN 5200 uint32_t nvr158 : 8; /* FUR_MODULE_CNTRL_RAM_NVR158_t[07:00] - WO */ 5201 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR158_t[15:08] - RSVD */ 5202 uint32_t reserved : 16; 5203 #endif /* IS_LITTLE_ENDIAN */ 5204 } fields; 5205 } FUR_MODULE_CNTRL_RAM_NVR158_t; 5206 5207 5208 typedef union { 5209 uint32_t data; 5210 struct { 5211 #if IS_BIG_ENDIAN 5212 uint32_t reserved : 16; 5213 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR159_t[15:08] - RSVD */ 5214 uint32_t nvr159 : 8; /* FUR_MODULE_CNTRL_RAM_NVR159_t[07:00] - WO */ 5215 #endif /* IS_BIG_ENDIAN */ 5216 #if IS_LITTLE_ENDIAN 5217 uint32_t nvr159 : 8; /* FUR_MODULE_CNTRL_RAM_NVR159_t[07:00] - WO */ 5218 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR159_t[15:08] - RSVD */ 5219 uint32_t reserved : 16; 5220 #endif /* IS_LITTLE_ENDIAN */ 5221 } fields; 5222 } FUR_MODULE_CNTRL_RAM_NVR159_t; 5223 5224 5225 typedef union { 5226 uint32_t data; 5227 struct { 5228 #if IS_BIG_ENDIAN 5229 uint32_t reserved : 16; 5230 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR160_t[15:08] - RSVD */ 5231 uint32_t nvr160 : 8; /* FUR_MODULE_CNTRL_RAM_NVR160_t[07:00] - WO */ 5232 #endif /* IS_BIG_ENDIAN */ 5233 #if IS_LITTLE_ENDIAN 5234 uint32_t nvr160 : 8; /* FUR_MODULE_CNTRL_RAM_NVR160_t[07:00] - WO */ 5235 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR160_t[15:08] - RSVD */ 5236 uint32_t reserved : 16; 5237 #endif /* IS_LITTLE_ENDIAN */ 5238 } fields; 5239 } FUR_MODULE_CNTRL_RAM_NVR160_t; 5240 5241 5242 typedef union { 5243 uint32_t data; 5244 struct { 5245 #if IS_BIG_ENDIAN 5246 uint32_t reserved : 16; 5247 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR161_t[15:08] - RSVD */ 5248 uint32_t nvr161 : 8; /* FUR_MODULE_CNTRL_RAM_NVR161_t[07:00] - WO */ 5249 #endif /* IS_BIG_ENDIAN */ 5250 #if IS_LITTLE_ENDIAN 5251 uint32_t nvr161 : 8; /* FUR_MODULE_CNTRL_RAM_NVR161_t[07:00] - WO */ 5252 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR161_t[15:08] - RSVD */ 5253 uint32_t reserved : 16; 5254 #endif /* IS_LITTLE_ENDIAN */ 5255 } fields; 5256 } FUR_MODULE_CNTRL_RAM_NVR161_t; 5257 5258 5259 typedef union { 5260 uint32_t data; 5261 struct { 5262 #if IS_BIG_ENDIAN 5263 uint32_t reserved : 16; 5264 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR162_t[15:08] - RSVD */ 5265 uint32_t nvr162 : 8; /* FUR_MODULE_CNTRL_RAM_NVR162_t[07:00] - WO */ 5266 #endif /* IS_BIG_ENDIAN */ 5267 #if IS_LITTLE_ENDIAN 5268 uint32_t nvr162 : 8; /* FUR_MODULE_CNTRL_RAM_NVR162_t[07:00] - WO */ 5269 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR162_t[15:08] - RSVD */ 5270 uint32_t reserved : 16; 5271 #endif /* IS_LITTLE_ENDIAN */ 5272 } fields; 5273 } FUR_MODULE_CNTRL_RAM_NVR162_t; 5274 5275 5276 typedef union { 5277 uint32_t data; 5278 struct { 5279 #if IS_BIG_ENDIAN 5280 uint32_t reserved : 16; 5281 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR163_t[15:08] - RSVD */ 5282 uint32_t nvr163 : 8; /* FUR_MODULE_CNTRL_RAM_NVR163_t[07:00] - WO */ 5283 #endif /* IS_BIG_ENDIAN */ 5284 #if IS_LITTLE_ENDIAN 5285 uint32_t nvr163 : 8; /* FUR_MODULE_CNTRL_RAM_NVR163_t[07:00] - WO */ 5286 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR163_t[15:08] - RSVD */ 5287 uint32_t reserved : 16; 5288 #endif /* IS_LITTLE_ENDIAN */ 5289 } fields; 5290 } FUR_MODULE_CNTRL_RAM_NVR163_t; 5291 5292 5293 typedef union { 5294 uint32_t data; 5295 struct { 5296 #if IS_BIG_ENDIAN 5297 uint32_t reserved : 16; 5298 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR164_t[15:08] - RSVD */ 5299 uint32_t nvr164 : 8; /* FUR_MODULE_CNTRL_RAM_NVR164_t[07:00] - WO */ 5300 #endif /* IS_BIG_ENDIAN */ 5301 #if IS_LITTLE_ENDIAN 5302 uint32_t nvr164 : 8; /* FUR_MODULE_CNTRL_RAM_NVR164_t[07:00] - WO */ 5303 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR164_t[15:08] - RSVD */ 5304 uint32_t reserved : 16; 5305 #endif /* IS_LITTLE_ENDIAN */ 5306 } fields; 5307 } FUR_MODULE_CNTRL_RAM_NVR164_t; 5308 5309 5310 typedef union { 5311 uint32_t data; 5312 struct { 5313 #if IS_BIG_ENDIAN 5314 uint32_t reserved : 16; 5315 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR165_t[15:08] - RSVD */ 5316 uint32_t nvr165 : 8; /* FUR_MODULE_CNTRL_RAM_NVR165_t[07:00] - WO */ 5317 #endif /* IS_BIG_ENDIAN */ 5318 #if IS_LITTLE_ENDIAN 5319 uint32_t nvr165 : 8; /* FUR_MODULE_CNTRL_RAM_NVR165_t[07:00] - WO */ 5320 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR165_t[15:08] - RSVD */ 5321 uint32_t reserved : 16; 5322 #endif /* IS_LITTLE_ENDIAN */ 5323 } fields; 5324 } FUR_MODULE_CNTRL_RAM_NVR165_t; 5325 5326 5327 typedef union { 5328 uint32_t data; 5329 struct { 5330 #if IS_BIG_ENDIAN 5331 uint32_t reserved : 16; 5332 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR166_t[15:08] - RSVD */ 5333 uint32_t nvr166 : 8; /* FUR_MODULE_CNTRL_RAM_NVR166_t[07:00] - WO */ 5334 #endif /* IS_BIG_ENDIAN */ 5335 #if IS_LITTLE_ENDIAN 5336 uint32_t nvr166 : 8; /* FUR_MODULE_CNTRL_RAM_NVR166_t[07:00] - WO */ 5337 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR166_t[15:08] - RSVD */ 5338 uint32_t reserved : 16; 5339 #endif /* IS_LITTLE_ENDIAN */ 5340 } fields; 5341 } FUR_MODULE_CNTRL_RAM_NVR166_t; 5342 5343 5344 typedef union { 5345 uint32_t data; 5346 struct { 5347 #if IS_BIG_ENDIAN 5348 uint32_t reserved : 16; 5349 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR167_t[15:08] - RSVD */ 5350 uint32_t nvr167 : 8; /* FUR_MODULE_CNTRL_RAM_NVR167_t[07:00] - WO */ 5351 #endif /* IS_BIG_ENDIAN */ 5352 #if IS_LITTLE_ENDIAN 5353 uint32_t nvr167 : 8; /* FUR_MODULE_CNTRL_RAM_NVR167_t[07:00] - WO */ 5354 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR167_t[15:08] - RSVD */ 5355 uint32_t reserved : 16; 5356 #endif /* IS_LITTLE_ENDIAN */ 5357 } fields; 5358 } FUR_MODULE_CNTRL_RAM_NVR167_t; 5359 5360 5361 typedef union { 5362 uint32_t data; 5363 struct { 5364 #if IS_BIG_ENDIAN 5365 uint32_t reserved : 16; 5366 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR168_t[15:08] - RSVD */ 5367 uint32_t nvr168 : 8; /* FUR_MODULE_CNTRL_RAM_NVR168_t[07:00] - WO */ 5368 #endif /* IS_BIG_ENDIAN */ 5369 #if IS_LITTLE_ENDIAN 5370 uint32_t nvr168 : 8; /* FUR_MODULE_CNTRL_RAM_NVR168_t[07:00] - WO */ 5371 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR168_t[15:08] - RSVD */ 5372 uint32_t reserved : 16; 5373 #endif /* IS_LITTLE_ENDIAN */ 5374 } fields; 5375 } FUR_MODULE_CNTRL_RAM_NVR168_t; 5376 5377 5378 typedef union { 5379 uint32_t data; 5380 struct { 5381 #if IS_BIG_ENDIAN 5382 uint32_t reserved : 16; 5383 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR169_t[15:08] - RSVD */ 5384 uint32_t nvr169 : 8; /* FUR_MODULE_CNTRL_RAM_NVR169_t[07:00] - WO */ 5385 #endif /* IS_BIG_ENDIAN */ 5386 #if IS_LITTLE_ENDIAN 5387 uint32_t nvr169 : 8; /* FUR_MODULE_CNTRL_RAM_NVR169_t[07:00] - WO */ 5388 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR169_t[15:08] - RSVD */ 5389 uint32_t reserved : 16; 5390 #endif /* IS_LITTLE_ENDIAN */ 5391 } fields; 5392 } FUR_MODULE_CNTRL_RAM_NVR169_t; 5393 5394 5395 typedef union { 5396 uint32_t data; 5397 struct { 5398 #if IS_BIG_ENDIAN 5399 uint32_t reserved : 16; 5400 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR170_t[15:08] - RSVD */ 5401 uint32_t nvr170 : 8; /* FUR_MODULE_CNTRL_RAM_NVR170_t[07:00] - WO */ 5402 #endif /* IS_BIG_ENDIAN */ 5403 #if IS_LITTLE_ENDIAN 5404 uint32_t nvr170 : 8; /* FUR_MODULE_CNTRL_RAM_NVR170_t[07:00] - WO */ 5405 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR170_t[15:08] - RSVD */ 5406 uint32_t reserved : 16; 5407 #endif /* IS_LITTLE_ENDIAN */ 5408 } fields; 5409 } FUR_MODULE_CNTRL_RAM_NVR170_t; 5410 5411 5412 typedef union { 5413 uint32_t data; 5414 struct { 5415 #if IS_BIG_ENDIAN 5416 uint32_t reserved : 16; 5417 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR171_t[15:08] - RSVD */ 5418 uint32_t nvr171 : 8; /* FUR_MODULE_CNTRL_RAM_NVR171_t[07:00] - WO */ 5419 #endif /* IS_BIG_ENDIAN */ 5420 #if IS_LITTLE_ENDIAN 5421 uint32_t nvr171 : 8; /* FUR_MODULE_CNTRL_RAM_NVR171_t[07:00] - WO */ 5422 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR171_t[15:08] - RSVD */ 5423 uint32_t reserved : 16; 5424 #endif /* IS_LITTLE_ENDIAN */ 5425 } fields; 5426 } FUR_MODULE_CNTRL_RAM_NVR171_t; 5427 5428 5429 typedef union { 5430 uint32_t data; 5431 struct { 5432 #if IS_BIG_ENDIAN 5433 uint32_t reserved : 16; 5434 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR172_t[15:08] - RSVD */ 5435 uint32_t nvr172 : 8; /* FUR_MODULE_CNTRL_RAM_NVR172_t[07:00] - WO */ 5436 #endif /* IS_BIG_ENDIAN */ 5437 #if IS_LITTLE_ENDIAN 5438 uint32_t nvr172 : 8; /* FUR_MODULE_CNTRL_RAM_NVR172_t[07:00] - WO */ 5439 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR172_t[15:08] - RSVD */ 5440 uint32_t reserved : 16; 5441 #endif /* IS_LITTLE_ENDIAN */ 5442 } fields; 5443 } FUR_MODULE_CNTRL_RAM_NVR172_t; 5444 5445 5446 typedef union { 5447 uint32_t data; 5448 struct { 5449 #if IS_BIG_ENDIAN 5450 uint32_t reserved : 16; 5451 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR173_t[15:08] - RSVD */ 5452 uint32_t nvr173 : 8; /* FUR_MODULE_CNTRL_RAM_NVR173_t[07:00] - WO */ 5453 #endif /* IS_BIG_ENDIAN */ 5454 #if IS_LITTLE_ENDIAN 5455 uint32_t nvr173 : 8; /* FUR_MODULE_CNTRL_RAM_NVR173_t[07:00] - WO */ 5456 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR173_t[15:08] - RSVD */ 5457 uint32_t reserved : 16; 5458 #endif /* IS_LITTLE_ENDIAN */ 5459 } fields; 5460 } FUR_MODULE_CNTRL_RAM_NVR173_t; 5461 5462 5463 typedef union { 5464 uint32_t data; 5465 struct { 5466 #if IS_BIG_ENDIAN 5467 uint32_t reserved : 16; 5468 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR174_t[15:08] - RSVD */ 5469 uint32_t nvr174 : 8; /* FUR_MODULE_CNTRL_RAM_NVR174_t[07:00] - WO */ 5470 #endif /* IS_BIG_ENDIAN */ 5471 #if IS_LITTLE_ENDIAN 5472 uint32_t nvr174 : 8; /* FUR_MODULE_CNTRL_RAM_NVR174_t[07:00] - WO */ 5473 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR174_t[15:08] - RSVD */ 5474 uint32_t reserved : 16; 5475 #endif /* IS_LITTLE_ENDIAN */ 5476 } fields; 5477 } FUR_MODULE_CNTRL_RAM_NVR174_t; 5478 5479 5480 typedef union { 5481 uint32_t data; 5482 struct { 5483 #if IS_BIG_ENDIAN 5484 uint32_t reserved : 16; 5485 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR175_t[15:08] - RSVD */ 5486 uint32_t nvr175 : 8; /* FUR_MODULE_CNTRL_RAM_NVR175_t[07:00] - WO */ 5487 #endif /* IS_BIG_ENDIAN */ 5488 #if IS_LITTLE_ENDIAN 5489 uint32_t nvr175 : 8; /* FUR_MODULE_CNTRL_RAM_NVR175_t[07:00] - WO */ 5490 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR175_t[15:08] - RSVD */ 5491 uint32_t reserved : 16; 5492 #endif /* IS_LITTLE_ENDIAN */ 5493 } fields; 5494 } FUR_MODULE_CNTRL_RAM_NVR175_t; 5495 5496 5497 typedef union { 5498 uint32_t data; 5499 struct { 5500 #if IS_BIG_ENDIAN 5501 uint32_t reserved : 16; 5502 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR176_t[15:08] - RSVD */ 5503 uint32_t nvr176 : 8; /* FUR_MODULE_CNTRL_RAM_NVR176_t[07:00] - WO */ 5504 #endif /* IS_BIG_ENDIAN */ 5505 #if IS_LITTLE_ENDIAN 5506 uint32_t nvr176 : 8; /* FUR_MODULE_CNTRL_RAM_NVR176_t[07:00] - WO */ 5507 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR176_t[15:08] - RSVD */ 5508 uint32_t reserved : 16; 5509 #endif /* IS_LITTLE_ENDIAN */ 5510 } fields; 5511 } FUR_MODULE_CNTRL_RAM_NVR176_t; 5512 5513 5514 typedef union { 5515 uint32_t data; 5516 struct { 5517 #if IS_BIG_ENDIAN 5518 uint32_t reserved : 16; 5519 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR177_t[15:08] - RSVD */ 5520 uint32_t nvr177 : 8; /* FUR_MODULE_CNTRL_RAM_NVR177_t[07:00] - WO */ 5521 #endif /* IS_BIG_ENDIAN */ 5522 #if IS_LITTLE_ENDIAN 5523 uint32_t nvr177 : 8; /* FUR_MODULE_CNTRL_RAM_NVR177_t[07:00] - WO */ 5524 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR177_t[15:08] - RSVD */ 5525 uint32_t reserved : 16; 5526 #endif /* IS_LITTLE_ENDIAN */ 5527 } fields; 5528 } FUR_MODULE_CNTRL_RAM_NVR177_t; 5529 5530 5531 typedef union { 5532 uint32_t data; 5533 struct { 5534 #if IS_BIG_ENDIAN 5535 uint32_t reserved : 16; 5536 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR178_t[15:08] - RSVD */ 5537 uint32_t nvr178 : 8; /* FUR_MODULE_CNTRL_RAM_NVR178_t[07:00] - WO */ 5538 #endif /* IS_BIG_ENDIAN */ 5539 #if IS_LITTLE_ENDIAN 5540 uint32_t nvr178 : 8; /* FUR_MODULE_CNTRL_RAM_NVR178_t[07:00] - WO */ 5541 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR178_t[15:08] - RSVD */ 5542 uint32_t reserved : 16; 5543 #endif /* IS_LITTLE_ENDIAN */ 5544 } fields; 5545 } FUR_MODULE_CNTRL_RAM_NVR178_t; 5546 5547 5548 typedef union { 5549 uint32_t data; 5550 struct { 5551 #if IS_BIG_ENDIAN 5552 uint32_t reserved : 16; 5553 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR179_t[15:08] - RSVD */ 5554 uint32_t nvr179 : 8; /* FUR_MODULE_CNTRL_RAM_NVR179_t[07:00] - WO */ 5555 #endif /* IS_BIG_ENDIAN */ 5556 #if IS_LITTLE_ENDIAN 5557 uint32_t nvr179 : 8; /* FUR_MODULE_CNTRL_RAM_NVR179_t[07:00] - WO */ 5558 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR179_t[15:08] - RSVD */ 5559 uint32_t reserved : 16; 5560 #endif /* IS_LITTLE_ENDIAN */ 5561 } fields; 5562 } FUR_MODULE_CNTRL_RAM_NVR179_t; 5563 5564 5565 typedef union { 5566 uint32_t data; 5567 struct { 5568 #if IS_BIG_ENDIAN 5569 uint32_t reserved : 16; 5570 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR180_t[15:08] - RSVD */ 5571 uint32_t nvr180 : 8; /* FUR_MODULE_CNTRL_RAM_NVR180_t[07:00] - WO */ 5572 #endif /* IS_BIG_ENDIAN */ 5573 #if IS_LITTLE_ENDIAN 5574 uint32_t nvr180 : 8; /* FUR_MODULE_CNTRL_RAM_NVR180_t[07:00] - WO */ 5575 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR180_t[15:08] - RSVD */ 5576 uint32_t reserved : 16; 5577 #endif /* IS_LITTLE_ENDIAN */ 5578 } fields; 5579 } FUR_MODULE_CNTRL_RAM_NVR180_t; 5580 5581 5582 typedef union { 5583 uint32_t data; 5584 struct { 5585 #if IS_BIG_ENDIAN 5586 uint32_t reserved : 16; 5587 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR181_t[15:08] - RSVD */ 5588 uint32_t nvr181 : 8; /* FUR_MODULE_CNTRL_RAM_NVR181_t[07:00] - WO */ 5589 #endif /* IS_BIG_ENDIAN */ 5590 #if IS_LITTLE_ENDIAN 5591 uint32_t nvr181 : 8; /* FUR_MODULE_CNTRL_RAM_NVR181_t[07:00] - WO */ 5592 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR181_t[15:08] - RSVD */ 5593 uint32_t reserved : 16; 5594 #endif /* IS_LITTLE_ENDIAN */ 5595 } fields; 5596 } FUR_MODULE_CNTRL_RAM_NVR181_t; 5597 5598 5599 typedef union { 5600 uint32_t data; 5601 struct { 5602 #if IS_BIG_ENDIAN 5603 uint32_t reserved : 16; 5604 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR182_t[15:08] - RSVD */ 5605 uint32_t nvr182 : 8; /* FUR_MODULE_CNTRL_RAM_NVR182_t[07:00] - WO */ 5606 #endif /* IS_BIG_ENDIAN */ 5607 #if IS_LITTLE_ENDIAN 5608 uint32_t nvr182 : 8; /* FUR_MODULE_CNTRL_RAM_NVR182_t[07:00] - WO */ 5609 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR182_t[15:08] - RSVD */ 5610 uint32_t reserved : 16; 5611 #endif /* IS_LITTLE_ENDIAN */ 5612 } fields; 5613 } FUR_MODULE_CNTRL_RAM_NVR182_t; 5614 5615 5616 typedef union { 5617 uint32_t data; 5618 struct { 5619 #if IS_BIG_ENDIAN 5620 uint32_t reserved : 16; 5621 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR183_t[15:08] - RSVD */ 5622 uint32_t nvr183 : 8; /* FUR_MODULE_CNTRL_RAM_NVR183_t[07:00] - WO */ 5623 #endif /* IS_BIG_ENDIAN */ 5624 #if IS_LITTLE_ENDIAN 5625 uint32_t nvr183 : 8; /* FUR_MODULE_CNTRL_RAM_NVR183_t[07:00] - WO */ 5626 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR183_t[15:08] - RSVD */ 5627 uint32_t reserved : 16; 5628 #endif /* IS_LITTLE_ENDIAN */ 5629 } fields; 5630 } FUR_MODULE_CNTRL_RAM_NVR183_t; 5631 5632 5633 typedef union { 5634 uint32_t data; 5635 struct { 5636 #if IS_BIG_ENDIAN 5637 uint32_t reserved : 16; 5638 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR184_t[15:08] - RSVD */ 5639 uint32_t nvr184 : 8; /* FUR_MODULE_CNTRL_RAM_NVR184_t[07:00] - WO */ 5640 #endif /* IS_BIG_ENDIAN */ 5641 #if IS_LITTLE_ENDIAN 5642 uint32_t nvr184 : 8; /* FUR_MODULE_CNTRL_RAM_NVR184_t[07:00] - WO */ 5643 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR184_t[15:08] - RSVD */ 5644 uint32_t reserved : 16; 5645 #endif /* IS_LITTLE_ENDIAN */ 5646 } fields; 5647 } FUR_MODULE_CNTRL_RAM_NVR184_t; 5648 5649 5650 typedef union { 5651 uint32_t data; 5652 struct { 5653 #if IS_BIG_ENDIAN 5654 uint32_t reserved : 16; 5655 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR185_t[15:08] - RSVD */ 5656 uint32_t nvr185 : 8; /* FUR_MODULE_CNTRL_RAM_NVR185_t[07:00] - WO */ 5657 #endif /* IS_BIG_ENDIAN */ 5658 #if IS_LITTLE_ENDIAN 5659 uint32_t nvr185 : 8; /* FUR_MODULE_CNTRL_RAM_NVR185_t[07:00] - WO */ 5660 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR185_t[15:08] - RSVD */ 5661 uint32_t reserved : 16; 5662 #endif /* IS_LITTLE_ENDIAN */ 5663 } fields; 5664 } FUR_MODULE_CNTRL_RAM_NVR185_t; 5665 5666 5667 typedef union { 5668 uint32_t data; 5669 struct { 5670 #if IS_BIG_ENDIAN 5671 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR186_t[15:08] - RSVD */ 5672 uint32_t nvr186 : 8; /* FUR_MODULE_CNTRL_RAM_NVR186_t[07:00] - WO */ 5673 #endif /* IS_BIG_ENDIAN */ 5674 #if IS_LITTLE_ENDIAN 5675 uint32_t nvr186 : 8; /* FUR_MODULE_CNTRL_RAM_NVR186_t[07:00] - WO */ 5676 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR186_t[15:08] - RSVD */ 5677 uint32_t reserved : 16; 5678 #endif /* IS_LITTLE_ENDIAN */ 5679 } fields; 5680 } FUR_MODULE_CNTRL_RAM_NVR186_t; 5681 5682 5683 typedef union { 5684 uint32_t data; 5685 struct { 5686 #if IS_BIG_ENDIAN 5687 uint32_t reserved : 16; 5688 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR187_t[15:08] - RSVD */ 5689 uint32_t nvr187 : 8; /* FUR_MODULE_CNTRL_RAM_NVR187_t[07:00] - WO */ 5690 #endif /* IS_BIG_ENDIAN */ 5691 #if IS_LITTLE_ENDIAN 5692 uint32_t nvr187 : 8; /* FUR_MODULE_CNTRL_RAM_NVR187_t[07:00] - WO */ 5693 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR187_t[15:08] - RSVD */ 5694 uint32_t reserved : 16; 5695 #endif /* IS_LITTLE_ENDIAN */ 5696 } fields; 5697 } FUR_MODULE_CNTRL_RAM_NVR187_t; 5698 5699 5700 typedef union { 5701 uint32_t data; 5702 struct { 5703 #if IS_BIG_ENDIAN 5704 uint32_t reserved : 16; 5705 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR188_t[15:08] - RSVD */ 5706 uint32_t nvr188 : 8; /* FUR_MODULE_CNTRL_RAM_NVR188_t[07:00] - WO */ 5707 #endif /* IS_BIG_ENDIAN */ 5708 #if IS_LITTLE_ENDIAN 5709 uint32_t nvr188 : 8; /* FUR_MODULE_CNTRL_RAM_NVR188_t[07:00] - WO */ 5710 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR188_t[15:08] - RSVD */ 5711 uint32_t reserved : 16; 5712 #endif /* IS_LITTLE_ENDIAN */ 5713 } fields; 5714 } FUR_MODULE_CNTRL_RAM_NVR188_t; 5715 5716 5717 typedef union { 5718 uint32_t data; 5719 struct { 5720 #if IS_BIG_ENDIAN 5721 uint32_t reserved : 16; 5722 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR189_t[15:08] - RSVD */ 5723 uint32_t nvr189 : 8; /* FUR_MODULE_CNTRL_RAM_NVR189_t[07:00] - WO */ 5724 #endif /* IS_BIG_ENDIAN */ 5725 #if IS_LITTLE_ENDIAN 5726 uint32_t nvr189 : 8; /* FUR_MODULE_CNTRL_RAM_NVR189_t[07:00] - WO */ 5727 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR189_t[15:08] - RSVD */ 5728 uint32_t reserved : 16; 5729 #endif /* IS_LITTLE_ENDIAN */ 5730 } fields; 5731 } FUR_MODULE_CNTRL_RAM_NVR189_t; 5732 5733 5734 typedef union { 5735 uint32_t data; 5736 struct { 5737 #if IS_BIG_ENDIAN 5738 uint32_t reserved : 16; 5739 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR190_t[15:08] - RSVD */ 5740 uint32_t nvr190 : 8; /* FUR_MODULE_CNTRL_RAM_NVR190_t[07:00] - WO */ 5741 #endif /* IS_BIG_ENDIAN */ 5742 #if IS_LITTLE_ENDIAN 5743 uint32_t nvr190 : 8; /* FUR_MODULE_CNTRL_RAM_NVR190_t[07:00] - WO */ 5744 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR190_t[15:08] - RSVD */ 5745 uint32_t reserved : 16; 5746 #endif /* IS_LITTLE_ENDIAN */ 5747 } fields; 5748 } FUR_MODULE_CNTRL_RAM_NVR190_t; 5749 5750 5751 typedef union { 5752 uint32_t data; 5753 struct { 5754 #if IS_BIG_ENDIAN 5755 uint32_t reserved : 16; 5756 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR191_t[15:08] - RSVD */ 5757 uint32_t nvr191 : 8; /* FUR_MODULE_CNTRL_RAM_NVR191_t[07:00] - WO */ 5758 #endif /* IS_BIG_ENDIAN */ 5759 #if IS_LITTLE_ENDIAN 5760 uint32_t nvr191 : 8; /* FUR_MODULE_CNTRL_RAM_NVR191_t[07:00] - WO */ 5761 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR191_t[15:08] - RSVD */ 5762 uint32_t reserved : 16; 5763 #endif /* IS_LITTLE_ENDIAN */ 5764 } fields; 5765 } FUR_MODULE_CNTRL_RAM_NVR191_t; 5766 5767 5768 typedef union { 5769 uint32_t data; 5770 struct { 5771 #if IS_BIG_ENDIAN 5772 uint32_t reserved : 16; 5773 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR192_t[15:08] - RSVD */ 5774 uint32_t nvr192 : 8; /* FUR_MODULE_CNTRL_RAM_NVR192_t[07:00] - WO */ 5775 #endif /* IS_BIG_ENDIAN */ 5776 #if IS_LITTLE_ENDIAN 5777 uint32_t nvr192 : 8; /* FUR_MODULE_CNTRL_RAM_NVR192_t[07:00] - WO */ 5778 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR192_t[15:08] - RSVD */ 5779 uint32_t reserved : 16; 5780 #endif /* IS_LITTLE_ENDIAN */ 5781 } fields; 5782 } FUR_MODULE_CNTRL_RAM_NVR192_t; 5783 5784 5785 typedef union { 5786 uint32_t data; 5787 struct { 5788 #if IS_BIG_ENDIAN 5789 uint32_t reserved : 16; 5790 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR193_t[15:08] - RSVD */ 5791 uint32_t nvr193 : 8; /* FUR_MODULE_CNTRL_RAM_NVR193_t[07:00] - WO */ 5792 #endif /* IS_BIG_ENDIAN */ 5793 #if IS_LITTLE_ENDIAN 5794 uint32_t nvr193 : 8; /* FUR_MODULE_CNTRL_RAM_NVR193_t[07:00] - WO */ 5795 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR193_t[15:08] - RSVD */ 5796 uint32_t reserved : 16; 5797 #endif /* IS_LITTLE_ENDIAN */ 5798 } fields; 5799 } FUR_MODULE_CNTRL_RAM_NVR193_t; 5800 5801 5802 typedef union { 5803 uint32_t data; 5804 struct { 5805 #if IS_BIG_ENDIAN 5806 uint32_t reserved : 16; 5807 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR194_t[15:08] - RSVD */ 5808 uint32_t nvr194 : 8; /* FUR_MODULE_CNTRL_RAM_NVR194_t[07:00] - WO */ 5809 #endif /* IS_BIG_ENDIAN */ 5810 #if IS_LITTLE_ENDIAN 5811 uint32_t nvr194 : 8; /* FUR_MODULE_CNTRL_RAM_NVR194_t[07:00] - WO */ 5812 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR194_t[15:08] - RSVD */ 5813 uint32_t reserved : 16; 5814 #endif /* IS_LITTLE_ENDIAN */ 5815 } fields; 5816 } FUR_MODULE_CNTRL_RAM_NVR194_t; 5817 5818 5819 typedef union { 5820 uint32_t data; 5821 struct { 5822 #if IS_BIG_ENDIAN 5823 uint32_t reserved : 16; 5824 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR195_t[15:08] - RSVD */ 5825 uint32_t nvr195 : 8; /* FUR_MODULE_CNTRL_RAM_NVR195_t[07:00] - WO */ 5826 #endif /* IS_BIG_ENDIAN */ 5827 #if IS_LITTLE_ENDIAN 5828 uint32_t nvr195 : 8; /* FUR_MODULE_CNTRL_RAM_NVR195_t[07:00] - WO */ 5829 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR195_t[15:08] - RSVD */ 5830 uint32_t reserved : 16; 5831 #endif /* IS_LITTLE_ENDIAN */ 5832 } fields; 5833 } FUR_MODULE_CNTRL_RAM_NVR195_t; 5834 5835 5836 typedef union { 5837 uint32_t data; 5838 struct { 5839 #if IS_BIG_ENDIAN 5840 uint32_t reserved : 16; 5841 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR196_t[15:08] - RSVD */ 5842 uint32_t nvr196 : 8; /* FUR_MODULE_CNTRL_RAM_NVR196_t[07:00] - WO */ 5843 #endif /* IS_BIG_ENDIAN */ 5844 #if IS_LITTLE_ENDIAN 5845 uint32_t nvr196 : 8; /* FUR_MODULE_CNTRL_RAM_NVR196_t[07:00] - WO */ 5846 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR196_t[15:08] - RSVD */ 5847 uint32_t reserved : 16; 5848 #endif /* IS_LITTLE_ENDIAN */ 5849 } fields; 5850 } FUR_MODULE_CNTRL_RAM_NVR196_t; 5851 5852 5853 typedef union { 5854 uint32_t data; 5855 struct { 5856 #if IS_BIG_ENDIAN 5857 uint32_t reserved : 16; 5858 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR197_t[15:08] - RSVD */ 5859 uint32_t nvr197 : 8; /* FUR_MODULE_CNTRL_RAM_NVR197_t[07:00] - WO */ 5860 #endif /* IS_BIG_ENDIAN */ 5861 #if IS_LITTLE_ENDIAN 5862 uint32_t nvr197 : 8; /* FUR_MODULE_CNTRL_RAM_NVR197_t[07:00] - WO */ 5863 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR197_t[15:08] - RSVD */ 5864 uint32_t reserved : 16; 5865 #endif /* IS_LITTLE_ENDIAN */ 5866 } fields; 5867 } FUR_MODULE_CNTRL_RAM_NVR197_t; 5868 5869 5870 typedef union { 5871 uint32_t data; 5872 struct { 5873 #if IS_BIG_ENDIAN 5874 uint32_t reserved : 16; 5875 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR198_t[15:08] - RSVD */ 5876 uint32_t nvr198 : 8; /* FUR_MODULE_CNTRL_RAM_NVR198_t[07:00] - WO */ 5877 #endif /* IS_BIG_ENDIAN */ 5878 #if IS_LITTLE_ENDIAN 5879 uint32_t nvr198 : 8; /* FUR_MODULE_CNTRL_RAM_NVR198_t[07:00] - WO */ 5880 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR198_t[15:08] - RSVD */ 5881 uint32_t reserved : 16; 5882 #endif /* IS_LITTLE_ENDIAN */ 5883 } fields; 5884 } FUR_MODULE_CNTRL_RAM_NVR198_t; 5885 5886 5887 typedef union { 5888 uint32_t data; 5889 struct { 5890 #if IS_BIG_ENDIAN 5891 uint32_t reserved : 16; 5892 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR199_t[15:08] - RSVD */ 5893 uint32_t nvr199 : 8; /* FUR_MODULE_CNTRL_RAM_NVR199_t[07:00] - WO */ 5894 #endif /* IS_BIG_ENDIAN */ 5895 #if IS_LITTLE_ENDIAN 5896 uint32_t nvr199 : 8; /* FUR_MODULE_CNTRL_RAM_NVR199_t[07:00] - WO */ 5897 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR199_t[15:08] - RSVD */ 5898 uint32_t reserved : 16; 5899 #endif /* IS_LITTLE_ENDIAN */ 5900 } fields; 5901 } FUR_MODULE_CNTRL_RAM_NVR199_t; 5902 5903 5904 typedef union { 5905 uint32_t data; 5906 struct { 5907 #if IS_BIG_ENDIAN 5908 uint32_t reserved : 16; 5909 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR200_t[15:08] - RSVD */ 5910 uint32_t nvr200 : 8; /* FUR_MODULE_CNTRL_RAM_NVR200_t[07:00] - WO */ 5911 #endif /* IS_BIG_ENDIAN */ 5912 #if IS_LITTLE_ENDIAN 5913 uint32_t nvr200 : 8; /* FUR_MODULE_CNTRL_RAM_NVR200_t[07:00] - WO */ 5914 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR200_t[15:08] - RSVD */ 5915 uint32_t reserved : 16; 5916 #endif /* IS_LITTLE_ENDIAN */ 5917 } fields; 5918 } FUR_MODULE_CNTRL_RAM_NVR200_t; 5919 5920 5921 typedef union { 5922 uint32_t data; 5923 struct { 5924 #if IS_BIG_ENDIAN 5925 uint32_t reserved : 16; 5926 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR201_t[15:08] - RSVD */ 5927 uint32_t nvr201 : 8; /* FUR_MODULE_CNTRL_RAM_NVR201_t[07:00] - WO */ 5928 #endif /* IS_BIG_ENDIAN */ 5929 #if IS_LITTLE_ENDIAN 5930 uint32_t nvr201 : 8; /* FUR_MODULE_CNTRL_RAM_NVR201_t[07:00] - WO */ 5931 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR201_t[15:08] - RSVD */ 5932 uint32_t reserved : 16; 5933 #endif /* IS_LITTLE_ENDIAN */ 5934 } fields; 5935 } FUR_MODULE_CNTRL_RAM_NVR201_t; 5936 5937 5938 typedef union { 5939 uint32_t data; 5940 struct { 5941 #if IS_BIG_ENDIAN 5942 uint32_t reserved : 16; 5943 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR202_t[15:08] - RSVD */ 5944 uint32_t nvr202 : 8; /* FUR_MODULE_CNTRL_RAM_NVR202_t[07:00] - WO */ 5945 #endif /* IS_BIG_ENDIAN */ 5946 #if IS_LITTLE_ENDIAN 5947 uint32_t nvr202 : 8; /* FUR_MODULE_CNTRL_RAM_NVR202_t[07:00] - WO */ 5948 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR202_t[15:08] - RSVD */ 5949 uint32_t reserved : 16; 5950 #endif /* IS_LITTLE_ENDIAN */ 5951 } fields; 5952 } FUR_MODULE_CNTRL_RAM_NVR202_t; 5953 5954 5955 typedef union { 5956 uint32_t data; 5957 struct { 5958 #if IS_BIG_ENDIAN 5959 uint32_t reserved : 16; 5960 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR203_t[15:08] - RSVD */ 5961 uint32_t nvr203 : 8; /* FUR_MODULE_CNTRL_RAM_NVR203_t[07:00] - WO */ 5962 #endif /* IS_BIG_ENDIAN */ 5963 #if IS_LITTLE_ENDIAN 5964 uint32_t nvr203 : 8; /* FUR_MODULE_CNTRL_RAM_NVR203_t[07:00] - WO */ 5965 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR203_t[15:08] - RSVD */ 5966 uint32_t reserved : 16; 5967 #endif /* IS_LITTLE_ENDIAN */ 5968 } fields; 5969 } FUR_MODULE_CNTRL_RAM_NVR203_t; 5970 5971 5972 typedef union { 5973 uint32_t data; 5974 struct { 5975 #if IS_BIG_ENDIAN 5976 uint32_t reserved : 16; 5977 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR204_t[15:08] - RSVD */ 5978 uint32_t nvr204 : 8; /* FUR_MODULE_CNTRL_RAM_NVR204_t[07:00] - WO */ 5979 #endif /* IS_BIG_ENDIAN */ 5980 #if IS_LITTLE_ENDIAN 5981 uint32_t nvr204 : 8; /* FUR_MODULE_CNTRL_RAM_NVR204_t[07:00] - WO */ 5982 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR204_t[15:08] - RSVD */ 5983 uint32_t reserved : 16; 5984 #endif /* IS_LITTLE_ENDIAN */ 5985 } fields; 5986 } FUR_MODULE_CNTRL_RAM_NVR204_t; 5987 5988 5989 typedef union { 5990 uint32_t data; 5991 struct { 5992 #if IS_BIG_ENDIAN 5993 uint32_t reserved : 16; 5994 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR205_t[15:08] - RSVD */ 5995 uint32_t nvr205 : 8; /* FUR_MODULE_CNTRL_RAM_NVR205_t[07:00] - WO */ 5996 #endif /* IS_BIG_ENDIAN */ 5997 #if IS_LITTLE_ENDIAN 5998 uint32_t nvr205 : 8; /* FUR_MODULE_CNTRL_RAM_NVR205_t[07:00] - WO */ 5999 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR205_t[15:08] - RSVD */ 6000 uint32_t reserved : 16; 6001 #endif /* IS_LITTLE_ENDIAN */ 6002 } fields; 6003 } FUR_MODULE_CNTRL_RAM_NVR205_t; 6004 6005 6006 typedef union { 6007 uint32_t data; 6008 struct { 6009 #if IS_BIG_ENDIAN 6010 uint32_t reserved : 16; 6011 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR206_t[15:08] - RSVD */ 6012 uint32_t nvr206 : 8; /* FUR_MODULE_CNTRL_RAM_NVR206_t[07:00] - WO */ 6013 #endif /* IS_BIG_ENDIAN */ 6014 #if IS_LITTLE_ENDIAN 6015 uint32_t nvr206 : 8; /* FUR_MODULE_CNTRL_RAM_NVR206_t[07:00] - WO */ 6016 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR206_t[15:08] - RSVD */ 6017 uint32_t reserved : 16; 6018 #endif /* IS_LITTLE_ENDIAN */ 6019 } fields; 6020 } FUR_MODULE_CNTRL_RAM_NVR206_t; 6021 6022 6023 typedef union { 6024 uint32_t data; 6025 struct { 6026 #if IS_BIG_ENDIAN 6027 uint32_t reserved : 16; 6028 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR207_t[15:08] - RSVD */ 6029 uint32_t nvr207 : 8; /* FUR_MODULE_CNTRL_RAM_NVR207_t[07:00] - WO */ 6030 #endif /* IS_BIG_ENDIAN */ 6031 #if IS_LITTLE_ENDIAN 6032 uint32_t nvr207 : 8; /* FUR_MODULE_CNTRL_RAM_NVR207_t[07:00] - WO */ 6033 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR207_t[15:08] - RSVD */ 6034 uint32_t reserved : 16; 6035 #endif /* IS_LITTLE_ENDIAN */ 6036 } fields; 6037 } FUR_MODULE_CNTRL_RAM_NVR207_t; 6038 6039 6040 typedef union { 6041 uint32_t data; 6042 struct { 6043 #if IS_BIG_ENDIAN 6044 uint32_t reserved : 16; 6045 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR208_t[15:08] - RSVD */ 6046 uint32_t nvr208 : 8; /* FUR_MODULE_CNTRL_RAM_NVR208_t[07:00] - WO */ 6047 #endif /* IS_BIG_ENDIAN */ 6048 #if IS_LITTLE_ENDIAN 6049 uint32_t nvr208 : 8; /* FUR_MODULE_CNTRL_RAM_NVR208_t[07:00] - WO */ 6050 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR208_t[15:08] - RSVD */ 6051 uint32_t reserved : 16; 6052 #endif /* IS_LITTLE_ENDIAN */ 6053 } fields; 6054 } FUR_MODULE_CNTRL_RAM_NVR208_t; 6055 6056 6057 typedef union { 6058 uint32_t data; 6059 struct { 6060 #if IS_BIG_ENDIAN 6061 uint32_t reserved : 16; 6062 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR209_t[15:08] - RSVD */ 6063 uint32_t nvr209 : 8; /* FUR_MODULE_CNTRL_RAM_NVR209_t[07:00] - WO */ 6064 #endif /* IS_BIG_ENDIAN */ 6065 #if IS_LITTLE_ENDIAN 6066 uint32_t nvr209 : 8; /* FUR_MODULE_CNTRL_RAM_NVR209_t[07:00] - WO */ 6067 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR209_t[15:08] - RSVD */ 6068 uint32_t reserved : 16; 6069 #endif /* IS_LITTLE_ENDIAN */ 6070 } fields; 6071 } FUR_MODULE_CNTRL_RAM_NVR209_t; 6072 6073 6074 typedef union { 6075 uint32_t data; 6076 struct { 6077 #if IS_BIG_ENDIAN 6078 uint32_t reserved : 16; 6079 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR210_t[15:08] - RSVD */ 6080 uint32_t nvr210 : 8; /* FUR_MODULE_CNTRL_RAM_NVR210_t[07:00] - WO */ 6081 #endif /* IS_BIG_ENDIAN */ 6082 #if IS_LITTLE_ENDIAN 6083 uint32_t nvr210 : 8; /* FUR_MODULE_CNTRL_RAM_NVR210_t[07:00] - WO */ 6084 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR210_t[15:08] - RSVD */ 6085 uint32_t reserved : 16; 6086 #endif /* IS_LITTLE_ENDIAN */ 6087 } fields; 6088 } FUR_MODULE_CNTRL_RAM_NVR210_t; 6089 6090 6091 typedef union { 6092 uint32_t data; 6093 struct { 6094 #if IS_BIG_ENDIAN 6095 uint32_t reserved : 16; 6096 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR211_t[15:08] - RSVD */ 6097 uint32_t nvr211 : 8; /* FUR_MODULE_CNTRL_RAM_NVR211_t[07:00] - WO */ 6098 #endif /* IS_BIG_ENDIAN */ 6099 #if IS_LITTLE_ENDIAN 6100 uint32_t nvr211 : 8; /* FUR_MODULE_CNTRL_RAM_NVR211_t[07:00] - WO */ 6101 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR211_t[15:08] - RSVD */ 6102 uint32_t reserved : 16; 6103 #endif /* IS_LITTLE_ENDIAN */ 6104 } fields; 6105 } FUR_MODULE_CNTRL_RAM_NVR211_t; 6106 6107 6108 typedef union { 6109 uint32_t data; 6110 struct { 6111 #if IS_BIG_ENDIAN 6112 uint32_t reserved : 16; 6113 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR212_t[15:08] - RSVD */ 6114 uint32_t nvr212 : 8; /* FUR_MODULE_CNTRL_RAM_NVR212_t[07:00] - WO */ 6115 #endif /* IS_BIG_ENDIAN */ 6116 #if IS_LITTLE_ENDIAN 6117 uint32_t nvr212 : 8; /* FUR_MODULE_CNTRL_RAM_NVR212_t[07:00] - WO */ 6118 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR212_t[15:08] - RSVD */ 6119 uint32_t reserved : 16; 6120 #endif /* IS_LITTLE_ENDIAN */ 6121 } fields; 6122 } FUR_MODULE_CNTRL_RAM_NVR212_t; 6123 6124 6125 typedef union { 6126 uint32_t data; 6127 struct { 6128 #if IS_BIG_ENDIAN 6129 uint32_t reserved : 16; 6130 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR213_t[15:08] - RSVD */ 6131 uint32_t nvr213 : 8; /* FUR_MODULE_CNTRL_RAM_NVR213_t[07:00] - WO */ 6132 #endif /* IS_BIG_ENDIAN */ 6133 #if IS_LITTLE_ENDIAN 6134 uint32_t nvr213 : 8; /* FUR_MODULE_CNTRL_RAM_NVR213_t[07:00] - WO */ 6135 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR213_t[15:08] - RSVD */ 6136 uint32_t reserved : 16; 6137 #endif /* IS_LITTLE_ENDIAN */ 6138 } fields; 6139 } FUR_MODULE_CNTRL_RAM_NVR213_t; 6140 6141 6142 typedef union { 6143 uint32_t data; 6144 struct { 6145 #if IS_BIG_ENDIAN 6146 uint32_t reserved : 16; 6147 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR214_t[15:08] - RSVD */ 6148 uint32_t nvr214 : 8; /* FUR_MODULE_CNTRL_RAM_NVR214_t[07:00] - WO */ 6149 #endif /* IS_BIG_ENDIAN */ 6150 #if IS_LITTLE_ENDIAN 6151 uint32_t nvr214 : 8; /* FUR_MODULE_CNTRL_RAM_NVR214_t[07:00] - WO */ 6152 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR214_t[15:08] - RSVD */ 6153 uint32_t reserved : 16; 6154 #endif /* IS_LITTLE_ENDIAN */ 6155 } fields; 6156 } FUR_MODULE_CNTRL_RAM_NVR214_t; 6157 6158 6159 typedef union { 6160 uint32_t data; 6161 struct { 6162 #if IS_BIG_ENDIAN 6163 uint32_t reserved : 16; 6164 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR215_t[15:08] - RSVD */ 6165 uint32_t nvr215 : 8; /* FUR_MODULE_CNTRL_RAM_NVR215_t[07:00] - WO */ 6166 #endif /* IS_BIG_ENDIAN */ 6167 #if IS_LITTLE_ENDIAN 6168 uint32_t nvr215 : 8; /* FUR_MODULE_CNTRL_RAM_NVR215_t[07:00] - WO */ 6169 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR215_t[15:08] - RSVD */ 6170 uint32_t reserved : 16; 6171 #endif /* IS_LITTLE_ENDIAN */ 6172 } fields; 6173 } FUR_MODULE_CNTRL_RAM_NVR215_t; 6174 6175 6176 typedef union { 6177 uint32_t data; 6178 struct { 6179 #if IS_BIG_ENDIAN 6180 uint32_t reserved : 16; 6181 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR216_t[15:08] - RSVD */ 6182 uint32_t nvr216 : 8; /* FUR_MODULE_CNTRL_RAM_NVR216_t[07:00] - WO */ 6183 #endif /* IS_BIG_ENDIAN */ 6184 #if IS_LITTLE_ENDIAN 6185 uint32_t nvr216 : 8; /* FUR_MODULE_CNTRL_RAM_NVR216_t[07:00] - WO */ 6186 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR216_t[15:08] - RSVD */ 6187 uint32_t reserved : 16; 6188 #endif /* IS_LITTLE_ENDIAN */ 6189 } fields; 6190 } FUR_MODULE_CNTRL_RAM_NVR216_t; 6191 6192 6193 typedef union { 6194 uint32_t data; 6195 struct { 6196 #if IS_BIG_ENDIAN 6197 uint32_t reserved : 16; 6198 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR217_t[15:08] - RSVD */ 6199 uint32_t nvr217 : 8; /* FUR_MODULE_CNTRL_RAM_NVR217_t[07:00] - WO */ 6200 #endif /* IS_BIG_ENDIAN */ 6201 #if IS_LITTLE_ENDIAN 6202 uint32_t nvr217 : 8; /* FUR_MODULE_CNTRL_RAM_NVR217_t[07:00] - WO */ 6203 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR217_t[15:08] - RSVD */ 6204 uint32_t reserved : 16; 6205 #endif /* IS_LITTLE_ENDIAN */ 6206 } fields; 6207 } FUR_MODULE_CNTRL_RAM_NVR217_t; 6208 6209 6210 typedef union { 6211 uint32_t data; 6212 struct { 6213 #if IS_BIG_ENDIAN 6214 uint32_t reserved : 16; 6215 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR218_t[15:08] - RSVD */ 6216 uint32_t nvr218 : 8; /* FUR_MODULE_CNTRL_RAM_NVR218_t[07:00] - WO */ 6217 #endif /* IS_BIG_ENDIAN */ 6218 #if IS_LITTLE_ENDIAN 6219 uint32_t nvr218 : 8; /* FUR_MODULE_CNTRL_RAM_NVR218_t[07:00] - WO */ 6220 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR218_t[15:08] - RSVD */ 6221 uint32_t reserved : 16; 6222 #endif /* IS_LITTLE_ENDIAN */ 6223 } fields; 6224 } FUR_MODULE_CNTRL_RAM_NVR218_t; 6225 6226 6227 typedef union { 6228 uint32_t data; 6229 struct { 6230 #if IS_BIG_ENDIAN 6231 uint32_t reserved : 16; 6232 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR219_t[15:08] - RSVD */ 6233 uint32_t nvr219 : 8; /* FUR_MODULE_CNTRL_RAM_NVR219_t[07:00] - WO */ 6234 #endif /* IS_BIG_ENDIAN */ 6235 #if IS_LITTLE_ENDIAN 6236 uint32_t nvr219 : 8; /* FUR_MODULE_CNTRL_RAM_NVR219_t[07:00] - WO */ 6237 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR219_t[15:08] - RSVD */ 6238 uint32_t reserved : 16; 6239 #endif /* IS_LITTLE_ENDIAN */ 6240 } fields; 6241 } FUR_MODULE_CNTRL_RAM_NVR219_t; 6242 6243 6244 typedef union { 6245 uint32_t data; 6246 struct { 6247 #if IS_BIG_ENDIAN 6248 uint32_t reserved : 16; 6249 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR220_t[15:08] - RSVD */ 6250 uint32_t nvr220 : 8; /* FUR_MODULE_CNTRL_RAM_NVR220_t[07:00] - WO */ 6251 #endif /* IS_BIG_ENDIAN */ 6252 #if IS_LITTLE_ENDIAN 6253 uint32_t nvr220 : 8; /* FUR_MODULE_CNTRL_RAM_NVR220_t[07:00] - WO */ 6254 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR220_t[15:08] - RSVD */ 6255 uint32_t reserved : 16; 6256 #endif /* IS_LITTLE_ENDIAN */ 6257 } fields; 6258 } FUR_MODULE_CNTRL_RAM_NVR220_t; 6259 6260 6261 typedef union { 6262 uint32_t data; 6263 struct { 6264 #if IS_BIG_ENDIAN 6265 uint32_t reserved : 16; 6266 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR221_t[15:08] - RSVD */ 6267 uint32_t nvr221 : 8; /* FUR_MODULE_CNTRL_RAM_NVR221_t[07:00] - WO */ 6268 #endif /* IS_BIG_ENDIAN */ 6269 #if IS_LITTLE_ENDIAN 6270 uint32_t nvr221 : 8; /* FUR_MODULE_CNTRL_RAM_NVR221_t[07:00] - WO */ 6271 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR221_t[15:08] - RSVD */ 6272 uint32_t reserved : 16; 6273 #endif /* IS_LITTLE_ENDIAN */ 6274 } fields; 6275 } FUR_MODULE_CNTRL_RAM_NVR221_t; 6276 6277 6278 typedef union { 6279 uint32_t data; 6280 struct { 6281 #if IS_BIG_ENDIAN 6282 uint32_t reserved : 16; 6283 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR222_t[15:08] - RSVD */ 6284 uint32_t nvr222 : 8; /* FUR_MODULE_CNTRL_RAM_NVR222_t[07:00] - WO */ 6285 #endif /* IS_BIG_ENDIAN */ 6286 #if IS_LITTLE_ENDIAN 6287 uint32_t nvr222 : 8; /* FUR_MODULE_CNTRL_RAM_NVR222_t[07:00] - WO */ 6288 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR222_t[15:08] - RSVD */ 6289 uint32_t reserved : 16; 6290 #endif /* IS_LITTLE_ENDIAN */ 6291 } fields; 6292 } FUR_MODULE_CNTRL_RAM_NVR222_t; 6293 6294 6295 typedef union { 6296 uint32_t data; 6297 struct { 6298 #if IS_BIG_ENDIAN 6299 uint32_t reserved : 16; 6300 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR223_t[15:08] - RSVD */ 6301 uint32_t nvr223 : 8; /* FUR_MODULE_CNTRL_RAM_NVR223_t[07:00] - WO */ 6302 #endif /* IS_BIG_ENDIAN */ 6303 #if IS_LITTLE_ENDIAN 6304 uint32_t nvr223 : 8; /* FUR_MODULE_CNTRL_RAM_NVR223_t[07:00] - WO */ 6305 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR223_t[15:08] - RSVD */ 6306 uint32_t reserved : 16; 6307 #endif /* IS_LITTLE_ENDIAN */ 6308 } fields; 6309 } FUR_MODULE_CNTRL_RAM_NVR223_t; 6310 6311 6312 typedef union { 6313 uint32_t data; 6314 struct { 6315 #if IS_BIG_ENDIAN 6316 uint32_t reserved : 16; 6317 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR224_t[15:08] - RSVD */ 6318 uint32_t nvr224 : 8; /* FUR_MODULE_CNTRL_RAM_NVR224_t[07:00] - WO */ 6319 #endif /* IS_BIG_ENDIAN */ 6320 #if IS_LITTLE_ENDIAN 6321 uint32_t nvr224 : 8; /* FUR_MODULE_CNTRL_RAM_NVR224_t[07:00] - WO */ 6322 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR224_t[15:08] - RSVD */ 6323 uint32_t reserved : 16; 6324 #endif /* IS_LITTLE_ENDIAN */ 6325 } fields; 6326 } FUR_MODULE_CNTRL_RAM_NVR224_t; 6327 6328 6329 typedef union { 6330 uint32_t data; 6331 struct { 6332 #if IS_BIG_ENDIAN 6333 uint32_t reserved : 16; 6334 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR225_t[15:08] - RSVD */ 6335 uint32_t nvr225 : 8; /* FUR_MODULE_CNTRL_RAM_NVR225_t[07:00] - WO */ 6336 #endif /* IS_BIG_ENDIAN */ 6337 #if IS_LITTLE_ENDIAN 6338 uint32_t nvr225 : 8; /* FUR_MODULE_CNTRL_RAM_NVR225_t[07:00] - WO */ 6339 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR225_t[15:08] - RSVD */ 6340 uint32_t reserved : 16; 6341 #endif /* IS_LITTLE_ENDIAN */ 6342 } fields; 6343 } FUR_MODULE_CNTRL_RAM_NVR225_t; 6344 6345 6346 typedef union { 6347 uint32_t data; 6348 struct { 6349 #if IS_BIG_ENDIAN 6350 uint32_t reserved : 16; 6351 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR226_t[15:08] - RSVD */ 6352 uint32_t nvr226 : 8; /* FUR_MODULE_CNTRL_RAM_NVR226_t[07:00] - WO */ 6353 #endif /* IS_BIG_ENDIAN */ 6354 #if IS_LITTLE_ENDIAN 6355 uint32_t nvr226 : 8; /* FUR_MODULE_CNTRL_RAM_NVR226_t[07:00] - WO */ 6356 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR226_t[15:08] - RSVD */ 6357 uint32_t reserved : 16; 6358 #endif /* IS_LITTLE_ENDIAN */ 6359 } fields; 6360 } FUR_MODULE_CNTRL_RAM_NVR226_t; 6361 6362 6363 typedef union { 6364 uint32_t data; 6365 struct { 6366 #if IS_BIG_ENDIAN 6367 uint32_t reserved : 16; 6368 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR227_t[15:08] - RSVD */ 6369 uint32_t nvr227 : 8; /* FUR_MODULE_CNTRL_RAM_NVR227_t[07:00] - WO */ 6370 #endif /* IS_BIG_ENDIAN */ 6371 #if IS_LITTLE_ENDIAN 6372 uint32_t nvr227 : 8; /* FUR_MODULE_CNTRL_RAM_NVR227_t[07:00] - WO */ 6373 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR227_t[15:08] - RSVD */ 6374 uint32_t reserved : 16; 6375 #endif /* IS_LITTLE_ENDIAN */ 6376 } fields; 6377 } FUR_MODULE_CNTRL_RAM_NVR227_t; 6378 6379 6380 typedef union { 6381 uint32_t data; 6382 struct { 6383 #if IS_BIG_ENDIAN 6384 uint32_t reserved : 16; 6385 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR228_t[15:08] - RSVD */ 6386 uint32_t nvr228 : 8; /* FUR_MODULE_CNTRL_RAM_NVR228_t[07:00] - WO */ 6387 #endif /* IS_BIG_ENDIAN */ 6388 #if IS_LITTLE_ENDIAN 6389 uint32_t nvr228 : 8; /* FUR_MODULE_CNTRL_RAM_NVR228_t[07:00] - WO */ 6390 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR228_t[15:08] - RSVD */ 6391 uint32_t reserved : 16; 6392 #endif /* IS_LITTLE_ENDIAN */ 6393 } fields; 6394 } FUR_MODULE_CNTRL_RAM_NVR228_t; 6395 6396 6397 typedef union { 6398 uint32_t data; 6399 struct { 6400 #if IS_BIG_ENDIAN 6401 uint32_t reserved : 16; 6402 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR229_t[15:08] - RSVD */ 6403 uint32_t nvr229 : 8; /* FUR_MODULE_CNTRL_RAM_NVR229_t[07:00] - WO */ 6404 #endif /* IS_BIG_ENDIAN */ 6405 #if IS_LITTLE_ENDIAN 6406 uint32_t nvr229 : 8; /* FUR_MODULE_CNTRL_RAM_NVR229_t[07:00] - WO */ 6407 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR229_t[15:08] - RSVD */ 6408 uint32_t reserved : 16; 6409 #endif /* IS_LITTLE_ENDIAN */ 6410 } fields; 6411 } FUR_MODULE_CNTRL_RAM_NVR229_t; 6412 6413 6414 typedef union { 6415 uint32_t data; 6416 struct { 6417 #if IS_BIG_ENDIAN 6418 uint32_t reserved : 16; 6419 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR230_t[15:08] - RSVD */ 6420 uint32_t nvr230 : 8; /* FUR_MODULE_CNTRL_RAM_NVR230_t[07:00] - WO */ 6421 #endif /* IS_BIG_ENDIAN */ 6422 #if IS_LITTLE_ENDIAN 6423 uint32_t nvr230 : 8; /* FUR_MODULE_CNTRL_RAM_NVR230_t[07:00] - WO */ 6424 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR230_t[15:08] - RSVD */ 6425 uint32_t reserved : 16; 6426 #endif /* IS_LITTLE_ENDIAN */ 6427 } fields; 6428 } FUR_MODULE_CNTRL_RAM_NVR230_t; 6429 6430 6431 typedef union { 6432 uint32_t data; 6433 struct { 6434 #if IS_BIG_ENDIAN 6435 uint32_t reserved : 16; 6436 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR231_t[15:08] - RSVD */ 6437 uint32_t nvr231 : 8; /* FUR_MODULE_CNTRL_RAM_NVR231_t[07:00] - WO */ 6438 #endif /* IS_BIG_ENDIAN */ 6439 #if IS_LITTLE_ENDIAN 6440 uint32_t nvr231 : 8; /* FUR_MODULE_CNTRL_RAM_NVR231_t[07:00] - WO */ 6441 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR231_t[15:08] - RSVD */ 6442 uint32_t reserved : 16; 6443 #endif /* IS_LITTLE_ENDIAN */ 6444 } fields; 6445 } FUR_MODULE_CNTRL_RAM_NVR231_t; 6446 6447 6448 typedef union { 6449 uint32_t data; 6450 struct { 6451 #if IS_BIG_ENDIAN 6452 uint32_t reserved : 16; 6453 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR232_t[15:08] - RSVD */ 6454 uint32_t nvr232 : 8; /* FUR_MODULE_CNTRL_RAM_NVR232_t[07:00] - WO */ 6455 #endif /* IS_BIG_ENDIAN */ 6456 #if IS_LITTLE_ENDIAN 6457 uint32_t nvr232 : 8; /* FUR_MODULE_CNTRL_RAM_NVR232_t[07:00] - WO */ 6458 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR232_t[15:08] - RSVD */ 6459 uint32_t reserved : 16; 6460 #endif /* IS_LITTLE_ENDIAN */ 6461 } fields; 6462 } FUR_MODULE_CNTRL_RAM_NVR232_t; 6463 6464 6465 typedef union { 6466 uint32_t data; 6467 struct { 6468 #if IS_BIG_ENDIAN 6469 uint32_t reserved : 16; 6470 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR233_t[15:08] - RSVD */ 6471 uint32_t nvr233 : 8; /* FUR_MODULE_CNTRL_RAM_NVR233_t[07:00] - WO */ 6472 #endif /* IS_BIG_ENDIAN */ 6473 #if IS_LITTLE_ENDIAN 6474 uint32_t nvr233 : 8; /* FUR_MODULE_CNTRL_RAM_NVR233_t[07:00] - WO */ 6475 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR233_t[15:08] - RSVD */ 6476 uint32_t reserved : 16; 6477 #endif /* IS_LITTLE_ENDIAN */ 6478 } fields; 6479 } FUR_MODULE_CNTRL_RAM_NVR233_t; 6480 6481 6482 typedef union { 6483 uint32_t data; 6484 struct { 6485 #if IS_BIG_ENDIAN 6486 uint32_t reserved : 16; 6487 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR234_t[15:08] - RSVD */ 6488 uint32_t nvr234 : 8; /* FUR_MODULE_CNTRL_RAM_NVR234_t[07:00] - WO */ 6489 #endif /* IS_BIG_ENDIAN */ 6490 #if IS_LITTLE_ENDIAN 6491 uint32_t nvr234 : 8; /* FUR_MODULE_CNTRL_RAM_NVR234_t[07:00] - WO */ 6492 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR234_t[15:08] - RSVD */ 6493 uint32_t reserved : 16; 6494 #endif /* IS_LITTLE_ENDIAN */ 6495 } fields; 6496 } FUR_MODULE_CNTRL_RAM_NVR234_t; 6497 6498 6499 typedef union { 6500 uint32_t data; 6501 struct { 6502 #if IS_BIG_ENDIAN 6503 uint32_t reserved : 16; 6504 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR235_t[15:08] - RSVD */ 6505 uint32_t nvr235 : 8; /* FUR_MODULE_CNTRL_RAM_NVR235_t[07:00] - WO */ 6506 #endif /* IS_BIG_ENDIAN */ 6507 #if IS_LITTLE_ENDIAN 6508 uint32_t nvr235 : 8; /* FUR_MODULE_CNTRL_RAM_NVR235_t[07:00] - WO */ 6509 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR235_t[15:08] - RSVD */ 6510 uint32_t reserved : 16; 6511 #endif /* IS_LITTLE_ENDIAN */ 6512 } fields; 6513 } FUR_MODULE_CNTRL_RAM_NVR235_t; 6514 6515 6516 typedef union { 6517 uint32_t data; 6518 struct { 6519 #if IS_BIG_ENDIAN 6520 uint32_t reserved : 16; 6521 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR236_t[15:08] - RSVD */ 6522 uint32_t nvr236 : 8; /* FUR_MODULE_CNTRL_RAM_NVR236_t[07:00] - WO */ 6523 #endif /* IS_BIG_ENDIAN */ 6524 #if IS_LITTLE_ENDIAN 6525 uint32_t nvr236 : 8; /* FUR_MODULE_CNTRL_RAM_NVR236_t[07:00] - WO */ 6526 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR236_t[15:08] - RSVD */ 6527 uint32_t reserved : 16; 6528 #endif /* IS_LITTLE_ENDIAN */ 6529 } fields; 6530 } FUR_MODULE_CNTRL_RAM_NVR236_t; 6531 6532 6533 typedef union { 6534 uint32_t data; 6535 struct { 6536 #if IS_BIG_ENDIAN 6537 uint32_t reserved : 16; 6538 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR237_t[15:08] - RSVD */ 6539 uint32_t nvr237 : 8; /* FUR_MODULE_CNTRL_RAM_NVR237_t[07:00] - WO */ 6540 #endif /* IS_BIG_ENDIAN */ 6541 #if IS_LITTLE_ENDIAN 6542 uint32_t nvr237 : 8; /* FUR_MODULE_CNTRL_RAM_NVR237_t[07:00] - WO */ 6543 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR237_t[15:08] - RSVD */ 6544 uint32_t reserved : 16; 6545 #endif /* IS_LITTLE_ENDIAN */ 6546 } fields; 6547 } FUR_MODULE_CNTRL_RAM_NVR237_t; 6548 6549 6550 typedef union { 6551 uint32_t data; 6552 struct { 6553 #if IS_BIG_ENDIAN 6554 uint32_t reserved : 16; 6555 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR238_t[15:08] - RSVD */ 6556 uint32_t nvr238 : 8; /* FUR_MODULE_CNTRL_RAM_NVR238_t[07:00] - WO */ 6557 #endif /* IS_BIG_ENDIAN */ 6558 #if IS_LITTLE_ENDIAN 6559 uint32_t nvr238 : 8; /* FUR_MODULE_CNTRL_RAM_NVR238_t[07:00] - WO */ 6560 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR238_t[15:08] - RSVD */ 6561 uint32_t reserved : 16; 6562 #endif /* IS_LITTLE_ENDIAN */ 6563 } fields; 6564 } FUR_MODULE_CNTRL_RAM_NVR238_t; 6565 6566 6567 typedef union { 6568 uint32_t data; 6569 struct { 6570 #if IS_BIG_ENDIAN 6571 uint32_t reserved : 16; 6572 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR239_t[15:08] - RSVD */ 6573 uint32_t nvr239 : 8; /* FUR_MODULE_CNTRL_RAM_NVR239_t[07:00] - WO */ 6574 #endif /* IS_BIG_ENDIAN */ 6575 #if IS_LITTLE_ENDIAN 6576 uint32_t nvr239 : 8; /* FUR_MODULE_CNTRL_RAM_NVR239_t[07:00] - WO */ 6577 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR239_t[15:08] - RSVD */ 6578 uint32_t reserved : 16; 6579 #endif /* IS_LITTLE_ENDIAN */ 6580 } fields; 6581 } FUR_MODULE_CNTRL_RAM_NVR239_t; 6582 6583 6584 typedef union { 6585 uint32_t data; 6586 struct { 6587 #if IS_BIG_ENDIAN 6588 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR240_t[15:08] - RSVD */ 6589 uint32_t nvr240 : 8; /* FUR_MODULE_CNTRL_RAM_NVR240_t[07:00] - WO */ 6590 #endif /* IS_BIG_ENDIAN */ 6591 #if IS_LITTLE_ENDIAN 6592 uint32_t nvr240 : 8; /* FUR_MODULE_CNTRL_RAM_NVR240_t[07:00] - WO */ 6593 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR240_t[15:08] - RSVD */ 6594 uint32_t reserved : 16; 6595 #endif /* IS_LITTLE_ENDIAN */ 6596 } fields; 6597 } FUR_MODULE_CNTRL_RAM_NVR240_t; 6598 6599 6600 typedef union { 6601 uint32_t data; 6602 struct { 6603 #if IS_BIG_ENDIAN 6604 uint32_t reserved : 16; 6605 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR241_t[15:08] - RSVD */ 6606 uint32_t nvr241 : 8; /* FUR_MODULE_CNTRL_RAM_NVR241_t[07:00] - WO */ 6607 #endif /* IS_BIG_ENDIAN */ 6608 #if IS_LITTLE_ENDIAN 6609 uint32_t nvr241 : 8; /* FUR_MODULE_CNTRL_RAM_NVR241_t[07:00] - WO */ 6610 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR241_t[15:08] - RSVD */ 6611 uint32_t reserved : 16; 6612 #endif /* IS_LITTLE_ENDIAN */ 6613 } fields; 6614 } FUR_MODULE_CNTRL_RAM_NVR241_t; 6615 6616 6617 typedef union { 6618 uint32_t data; 6619 struct { 6620 #if IS_BIG_ENDIAN 6621 uint32_t reserved : 16; 6622 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR242_t[15:08] - RSVD */ 6623 uint32_t nvr242 : 8; /* FUR_MODULE_CNTRL_RAM_NVR242_t[07:00] - WO */ 6624 #endif /* IS_BIG_ENDIAN */ 6625 #if IS_LITTLE_ENDIAN 6626 uint32_t nvr242 : 8; /* FUR_MODULE_CNTRL_RAM_NVR242_t[07:00] - WO */ 6627 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR242_t[15:08] - RSVD */ 6628 uint32_t reserved : 16; 6629 #endif /* IS_LITTLE_ENDIAN */ 6630 } fields; 6631 } FUR_MODULE_CNTRL_RAM_NVR242_t; 6632 6633 6634 typedef union { 6635 uint32_t data; 6636 struct { 6637 #if IS_BIG_ENDIAN 6638 uint32_t reserved : 16; 6639 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR243_t[15:08] - RSVD */ 6640 uint32_t nvr243 : 8; /* FUR_MODULE_CNTRL_RAM_NVR243_t[07:00] - WO */ 6641 #endif /* IS_BIG_ENDIAN */ 6642 #if IS_LITTLE_ENDIAN 6643 uint32_t nvr243 : 8; /* FUR_MODULE_CNTRL_RAM_NVR243_t[07:00] - WO */ 6644 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR243_t[15:08] - RSVD */ 6645 uint32_t reserved : 16; 6646 #endif /* IS_LITTLE_ENDIAN */ 6647 } fields; 6648 } FUR_MODULE_CNTRL_RAM_NVR243_t; 6649 6650 6651 typedef union { 6652 uint32_t data; 6653 struct { 6654 #if IS_BIG_ENDIAN 6655 uint32_t reserved : 16; 6656 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR244_t[15:08] - RSVD */ 6657 uint32_t nvr244 : 8; /* FUR_MODULE_CNTRL_RAM_NVR244_t[07:00] - WO */ 6658 #endif /* IS_BIG_ENDIAN */ 6659 #if IS_LITTLE_ENDIAN 6660 uint32_t nvr244 : 8; /* FUR_MODULE_CNTRL_RAM_NVR244_t[07:00] - WO */ 6661 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR244_t[15:08] - RSVD */ 6662 uint32_t reserved : 16; 6663 #endif /* IS_LITTLE_ENDIAN */ 6664 } fields; 6665 } FUR_MODULE_CNTRL_RAM_NVR244_t; 6666 6667 6668 typedef union { 6669 uint32_t data; 6670 struct { 6671 #if IS_BIG_ENDIAN 6672 uint32_t reserved : 16; 6673 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR245_t[15:08] - RSVD */ 6674 uint32_t nvr245 : 8; /* FUR_MODULE_CNTRL_RAM_NVR245_t[07:00] - WO */ 6675 #endif /* IS_BIG_ENDIAN */ 6676 #if IS_LITTLE_ENDIAN 6677 uint32_t nvr245 : 8; /* FUR_MODULE_CNTRL_RAM_NVR245_t[07:00] - WO */ 6678 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR245_t[15:08] - RSVD */ 6679 uint32_t reserved : 16; 6680 #endif /* IS_LITTLE_ENDIAN */ 6681 } fields; 6682 } FUR_MODULE_CNTRL_RAM_NVR245_t; 6683 6684 6685 typedef union { 6686 uint32_t data; 6687 struct { 6688 #if IS_BIG_ENDIAN 6689 uint32_t reserved : 16; 6690 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR246_t[15:08] - RSVD */ 6691 uint32_t nvr246 : 8; /* FUR_MODULE_CNTRL_RAM_NVR246_t[07:00] - WO */ 6692 #endif /* IS_BIG_ENDIAN */ 6693 #if IS_LITTLE_ENDIAN 6694 uint32_t nvr246 : 8; /* FUR_MODULE_CNTRL_RAM_NVR246_t[07:00] - WO */ 6695 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR246_t[15:08] - RSVD */ 6696 uint32_t reserved : 16; 6697 #endif /* IS_LITTLE_ENDIAN */ 6698 } fields; 6699 } FUR_MODULE_CNTRL_RAM_NVR246_t; 6700 6701 6702 typedef union { 6703 uint32_t data; 6704 struct { 6705 #if IS_BIG_ENDIAN 6706 uint32_t reserved : 16; 6707 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR247_t[15:08] - RSVD */ 6708 uint32_t nvr247 : 8; /* FUR_MODULE_CNTRL_RAM_NVR247_t[07:00] - WO */ 6709 #endif /* IS_BIG_ENDIAN */ 6710 #if IS_LITTLE_ENDIAN 6711 uint32_t nvr247 : 8; /* FUR_MODULE_CNTRL_RAM_NVR247_t[07:00] - WO */ 6712 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR247_t[15:08] - RSVD */ 6713 uint32_t reserved : 16; 6714 #endif /* IS_LITTLE_ENDIAN */ 6715 } fields; 6716 } FUR_MODULE_CNTRL_RAM_NVR247_t; 6717 6718 6719 typedef union { 6720 uint32_t data; 6721 struct { 6722 #if IS_BIG_ENDIAN 6723 uint32_t reserved : 16; 6724 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR248_t[15:08] - RSVD */ 6725 uint32_t nvr248 : 8; /* FUR_MODULE_CNTRL_RAM_NVR248_t[07:00] - WO */ 6726 #endif /* IS_BIG_ENDIAN */ 6727 #if IS_LITTLE_ENDIAN 6728 uint32_t nvr248 : 8; /* FUR_MODULE_CNTRL_RAM_NVR248_t[07:00] - WO */ 6729 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR248_t[15:08] - RSVD */ 6730 uint32_t reserved : 16; 6731 #endif /* IS_LITTLE_ENDIAN */ 6732 } fields; 6733 } FUR_MODULE_CNTRL_RAM_NVR248_t; 6734 6735 6736 typedef union { 6737 uint32_t data; 6738 struct { 6739 #if IS_BIG_ENDIAN 6740 uint32_t reserved : 16; 6741 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR249_t[15:08] - RSVD */ 6742 uint32_t nvr249 : 8; /* FUR_MODULE_CNTRL_RAM_NVR249_t[07:00] - WO */ 6743 #endif /* IS_BIG_ENDIAN */ 6744 #if IS_LITTLE_ENDIAN 6745 uint32_t nvr249 : 8; /* FUR_MODULE_CNTRL_RAM_NVR249_t[07:00] - WO */ 6746 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR249_t[15:08] - RSVD */ 6747 uint32_t reserved : 16; 6748 #endif /* IS_LITTLE_ENDIAN */ 6749 } fields; 6750 } FUR_MODULE_CNTRL_RAM_NVR249_t; 6751 6752 6753 typedef union { 6754 uint32_t data; 6755 struct { 6756 #if IS_BIG_ENDIAN 6757 uint32_t reserved : 16; 6758 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR250_t[15:08] - RSVD */ 6759 uint32_t nvr250 : 8; /* FUR_MODULE_CNTRL_RAM_NVR250_t[07:00] - WO */ 6760 #endif /* IS_BIG_ENDIAN */ 6761 #if IS_LITTLE_ENDIAN 6762 uint32_t nvr250 : 8; /* FUR_MODULE_CNTRL_RAM_NVR250_t[07:00] - WO */ 6763 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR250_t[15:08] - RSVD */ 6764 uint32_t reserved : 16; 6765 #endif /* IS_LITTLE_ENDIAN */ 6766 } fields; 6767 } FUR_MODULE_CNTRL_RAM_NVR250_t; 6768 6769 6770 typedef union { 6771 uint32_t data; 6772 struct { 6773 #if IS_BIG_ENDIAN 6774 uint32_t reserved : 16; 6775 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR251_t[15:08] - RSVD */ 6776 uint32_t nvr251 : 8; /* FUR_MODULE_CNTRL_RAM_NVR251_t[07:00] - WO */ 6777 #endif /* IS_BIG_ENDIAN */ 6778 #if IS_LITTLE_ENDIAN 6779 uint32_t nvr251 : 8; /* FUR_MODULE_CNTRL_RAM_NVR251_t[07:00] - WO */ 6780 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR251_t[15:08] - RSVD */ 6781 uint32_t reserved : 16; 6782 #endif /* IS_LITTLE_ENDIAN */ 6783 } fields; 6784 } FUR_MODULE_CNTRL_RAM_NVR251_t; 6785 6786 6787 typedef union { 6788 uint32_t data; 6789 struct { 6790 #if IS_BIG_ENDIAN 6791 uint32_t reserved : 16; 6792 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR252_t[15:08] - RSVD */ 6793 uint32_t nvr252 : 8; /* FUR_MODULE_CNTRL_RAM_NVR252_t[07:00] - WO */ 6794 #endif /* IS_BIG_ENDIAN */ 6795 #if IS_LITTLE_ENDIAN 6796 uint32_t nvr252 : 8; /* FUR_MODULE_CNTRL_RAM_NVR252_t[07:00] - WO */ 6797 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR252_t[15:08] - RSVD */ 6798 uint32_t reserved : 16; 6799 #endif /* IS_LITTLE_ENDIAN */ 6800 } fields; 6801 } FUR_MODULE_CNTRL_RAM_NVR252_t; 6802 6803 6804 typedef union { 6805 uint32_t data; 6806 struct { 6807 #if IS_BIG_ENDIAN 6808 uint32_t reserved : 16; 6809 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR253_t[15:08] - RSVD */ 6810 uint32_t nvr253 : 8; /* FUR_MODULE_CNTRL_RAM_NVR253_t[07:00] - WO */ 6811 #endif /* IS_BIG_ENDIAN */ 6812 #if IS_LITTLE_ENDIAN 6813 uint32_t nvr253 : 8; /* FUR_MODULE_CNTRL_RAM_NVR253_t[07:00] - WO */ 6814 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR253_t[15:08] - RSVD */ 6815 uint32_t reserved : 16; 6816 #endif /* IS_LITTLE_ENDIAN */ 6817 } fields; 6818 } FUR_MODULE_CNTRL_RAM_NVR253_t; 6819 6820 6821 typedef union { 6822 uint32_t data; 6823 struct { 6824 #if IS_BIG_ENDIAN 6825 uint32_t reserved : 16; 6826 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR254_t[15:08] - RSVD */ 6827 uint32_t nvr254 : 8; /* FUR_MODULE_CNTRL_RAM_NVR254_t[07:00] - WO */ 6828 #endif /* IS_BIG_ENDIAN */ 6829 #if IS_LITTLE_ENDIAN 6830 uint32_t nvr254 : 8; /* FUR_MODULE_CNTRL_RAM_NVR254_t[07:00] - WO */ 6831 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR254_t[15:08] - RSVD */ 6832 uint32_t reserved : 16; 6833 #endif /* IS_LITTLE_ENDIAN */ 6834 } fields; 6835 } FUR_MODULE_CNTRL_RAM_NVR254_t; 6836 6837 6838 typedef union { 6839 uint32_t data; 6840 struct { 6841 #if IS_BIG_ENDIAN 6842 uint32_t reserved : 16; 6843 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR255_t[15:08] - RSVD */ 6844 uint32_t nvr255 : 8; /* FUR_MODULE_CNTRL_RAM_NVR255_t[07:00] - WO */ 6845 #endif /* IS_BIG_ENDIAN */ 6846 #if IS_LITTLE_ENDIAN 6847 uint32_t nvr255 : 8; /* FUR_MODULE_CNTRL_RAM_NVR255_t[07:00] - WO */ 6848 uint32_t reserved_08 : 8; /* FUR_MODULE_CNTRL_RAM_NVR255_t[15:08] - RSVD */ 6849 uint32_t reserved : 16; 6850 #endif /* IS_LITTLE_ENDIAN */ 6851 } fields; 6852 } FUR_MODULE_CNTRL_RAM_NVR255_t; 6853 6854 6855 6856 /*-----------------------------------------------*/ 6857 /* Structs for FUR_MISC_CTRL Bank */ 6858 /*-----------------------------------------------*/ 6859 typedef union { 6860 uint32_t data; 6861 struct { 6862 #if IS_BIG_ENDIAN 6863 uint32_t reserved : 16; 6864 uint32_t chip_id_15_0 : 16; /* FUR_MISC_CTRL_chip_id_t[15:00] - RO */ 6865 #endif /* IS_BIG_ENDIAN */ 6866 #if IS_LITTLE_ENDIAN 6867 uint32_t chip_id_15_0 : 16; /* FUR_MISC_CTRL_chip_id_t[15:00] - RO */ 6868 uint32_t reserved : 16; 6869 #endif /* IS_LITTLE_ENDIAN */ 6870 } fields; 6871 } FUR_MISC_CTRL_chip_id_t; 6872 6873 typedef FUR_MISC_CTRL_chip_id_t FUR_MISC_CTRL_CHIP_ID_t; 6874 6875 typedef union { 6876 uint32_t data; 6877 struct { 6878 #if IS_BIG_ENDIAN 6879 uint32_t reserved : 16; 6880 uint32_t chip_id_19_16 : 4; /* FUR_MISC_CTRL_chip_revision_t[15:12] - RO */ 6881 uint32_t reserved_for_eco_08 : 4; /* FUR_MISC_CTRL_chip_revision_t[11:08] - RSVD */ 6882 uint32_t chip_rev : 8; /* FUR_MISC_CTRL_chip_revision_t[07:00] - RO */ 6883 #endif /* IS_BIG_ENDIAN */ 6884 #if IS_LITTLE_ENDIAN 6885 uint32_t chip_rev : 8; /* FUR_MISC_CTRL_chip_revision_t[07:00] - RO */ 6886 uint32_t reserved_for_eco_08 : 4; /* FUR_MISC_CTRL_chip_revision_t[11:08] - RSVD */ 6887 uint32_t chip_id_19_16 : 4; /* FUR_MISC_CTRL_chip_revision_t[15:12] - RO */ 6888 uint32_t reserved : 16; 6889 #endif /* IS_LITTLE_ENDIAN */ 6890 } fields; 6891 } FUR_MISC_CTRL_chip_revision_t; 6892 6893 typedef FUR_MISC_CTRL_chip_revision_t FUR_MISC_CTRL_CHIP_REVISION_t; 6894 6895 typedef union { 6896 uint32_t data; 6897 struct { 6898 #if IS_BIG_ENDIAN 6899 uint32_t reserved : 16; 6900 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_mode_dec_frc_t[15:08] - RSVD */ 6901 uint32_t rg_1gtx_mode_16p5_frc : 4; /* FUR_MISC_CTRL_mode_dec_frc_t[07:04] - WO */ 6902 uint32_t rg_cl91_enabled_frc : 1; /* FUR_MISC_CTRL_mode_dec_frc_t[03] - WO */ 6903 uint32_t reserved_01 : 2; /* FUR_MISC_CTRL_mode_dec_frc_t[02:01] - RSVD */ 6904 uint32_t rg_single_pmd_frc : 1; /* FUR_MISC_CTRL_mode_dec_frc_t[00] - WO */ 6905 #endif /* IS_BIG_ENDIAN */ 6906 #if IS_LITTLE_ENDIAN 6907 uint32_t rg_single_pmd_frc : 1; /* FUR_MISC_CTRL_mode_dec_frc_t[00] - WO */ 6908 uint32_t reserved_01 : 2; /* FUR_MISC_CTRL_mode_dec_frc_t[02:01] - RSVD */ 6909 uint32_t rg_cl91_enabled_frc : 1; /* FUR_MISC_CTRL_mode_dec_frc_t[03] - WO */ 6910 uint32_t rg_1gtx_mode_16p5_frc : 4; /* FUR_MISC_CTRL_mode_dec_frc_t[07:04] - WO */ 6911 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_mode_dec_frc_t[15:08] - RSVD */ 6912 uint32_t reserved : 16; 6913 #endif /* IS_LITTLE_ENDIAN */ 6914 } fields; 6915 } FUR_MISC_CTRL_mode_dec_frc_t; 6916 6917 typedef FUR_MISC_CTRL_mode_dec_frc_t FUR_MISC_CTRL_MODE_DEC_FRC_t; 6918 6919 typedef union { 6920 uint32_t data; 6921 struct { 6922 #if IS_BIG_ENDIAN 6923 uint32_t reserved : 16; 6924 uint32_t udms_en : 1; /* FUR_MISC_CTRL_udms_phy_t[15] - WO */ 6925 uint32_t reserved_03 : 12; /* FUR_MISC_CTRL_udms_phy_t[14:03] - RSVD */ 6926 uint32_t udms_phy_type : 3; /* FUR_MISC_CTRL_udms_phy_t[02:00] - WO */ 6927 #endif /* IS_BIG_ENDIAN */ 6928 #if IS_LITTLE_ENDIAN 6929 uint32_t udms_phy_type : 3; /* FUR_MISC_CTRL_udms_phy_t[02:00] - WO */ 6930 uint32_t reserved_03 : 12; /* FUR_MISC_CTRL_udms_phy_t[14:03] - RSVD */ 6931 uint32_t udms_en : 1; /* FUR_MISC_CTRL_udms_phy_t[15] - WO */ 6932 uint32_t reserved : 16; 6933 #endif /* IS_LITTLE_ENDIAN */ 6934 } fields; 6935 } FUR_MISC_CTRL_udms_phy_t; 6936 6937 typedef FUR_MISC_CTRL_udms_phy_t FUR_MISC_CTRL_UDMS_PHY_t; 6938 6939 typedef union { 6940 uint32_t data; 6941 struct { 6942 #if IS_BIG_ENDIAN 6943 uint32_t reserved : 16; 6944 uint32_t udms_ln3_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[15:12] - WO */ 6945 uint32_t udms_ln2_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[11:08] - WO */ 6946 uint32_t udms_ln1_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[07:04] - WO */ 6947 uint32_t udms_ln0_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[03:00] - WO */ 6948 #endif /* IS_BIG_ENDIAN */ 6949 #if IS_LITTLE_ENDIAN 6950 uint32_t udms_ln0_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[03:00] - WO */ 6951 uint32_t udms_ln1_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[07:04] - WO */ 6952 uint32_t udms_ln2_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[11:08] - WO */ 6953 uint32_t udms_ln3_lnk_type : 4; /* FUR_MISC_CTRL_udms_link_t[15:12] - WO */ 6954 uint32_t reserved : 16; 6955 #endif /* IS_LITTLE_ENDIAN */ 6956 } fields; 6957 } FUR_MISC_CTRL_udms_link_t; 6958 6959 typedef FUR_MISC_CTRL_udms_link_t FUR_MISC_CTRL_UDMS_LINK_t; 6960 6961 typedef union { 6962 uint32_t data; 6963 struct { 6964 #if IS_BIG_ENDIAN 6965 uint32_t reserved : 16; 6966 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_mode_dec_frc_val_t[15:08] - RSVD */ 6967 uint32_t rg_1gtx_mode_16p5_frc_val : 4; /* FUR_MISC_CTRL_mode_dec_frc_val_t[07:04] - WO */ 6968 uint32_t rg_cl91_enabled_frc_val : 1; /* FUR_MISC_CTRL_mode_dec_frc_val_t[03] - WO */ 6969 uint32_t reserved_01 : 2; /* FUR_MISC_CTRL_mode_dec_frc_val_t[02:01] - RSVD */ 6970 uint32_t rg_single_pmd_frc_val : 1; /* FUR_MISC_CTRL_mode_dec_frc_val_t[00] - WO */ 6971 #endif /* IS_BIG_ENDIAN */ 6972 #if IS_LITTLE_ENDIAN 6973 uint32_t rg_single_pmd_frc_val : 1; /* FUR_MISC_CTRL_mode_dec_frc_val_t[00] - WO */ 6974 uint32_t reserved_01 : 2; /* FUR_MISC_CTRL_mode_dec_frc_val_t[02:01] - RSVD */ 6975 uint32_t rg_cl91_enabled_frc_val : 1; /* FUR_MISC_CTRL_mode_dec_frc_val_t[03] - WO */ 6976 uint32_t rg_1gtx_mode_16p5_frc_val : 4; /* FUR_MISC_CTRL_mode_dec_frc_val_t[07:04] - WO */ 6977 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_mode_dec_frc_val_t[15:08] - RSVD */ 6978 uint32_t reserved : 16; 6979 #endif /* IS_LITTLE_ENDIAN */ 6980 } fields; 6981 } FUR_MISC_CTRL_mode_dec_frc_val_t; 6982 6983 typedef FUR_MISC_CTRL_mode_dec_frc_val_t FUR_MISC_CTRL_MODE_DEC_FRC_VAL_t; 6984 6985 typedef union { 6986 uint32_t data; 6987 struct { 6988 #if IS_BIG_ENDIAN 6989 uint32_t reserved : 16; 6990 uint32_t reserved_15 : 1; /* FUR_MISC_CTRL_phy_type_status_t[15] - RSVD */ 6991 uint32_t ln0_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[14:12] - RO */ 6992 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_phy_type_status_t[11] - RSVD */ 6993 uint32_t ln1_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[10:08] - RO */ 6994 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_phy_type_status_t[07] - RSVD */ 6995 uint32_t ln2_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[06:04] - RO */ 6996 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_phy_type_status_t[03] - RSVD */ 6997 uint32_t ln3_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[02:00] - RO */ 6998 #endif /* IS_BIG_ENDIAN */ 6999 #if IS_LITTLE_ENDIAN 7000 uint32_t ln3_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[02:00] - RO */ 7001 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_phy_type_status_t[03] - RSVD */ 7002 uint32_t ln2_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[06:04] - RO */ 7003 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_phy_type_status_t[07] - RSVD */ 7004 uint32_t ln1_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[10:08] - RO */ 7005 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_phy_type_status_t[11] - RSVD */ 7006 uint32_t ln0_phy_status : 3; /* FUR_MISC_CTRL_phy_type_status_t[14:12] - RO */ 7007 uint32_t reserved_15 : 1; /* FUR_MISC_CTRL_phy_type_status_t[15] - RSVD */ 7008 uint32_t reserved : 16; 7009 #endif /* IS_LITTLE_ENDIAN */ 7010 } fields; 7011 } FUR_MISC_CTRL_phy_type_status_t; 7012 7013 typedef FUR_MISC_CTRL_phy_type_status_t FUR_MISC_CTRL_PHY_TYPE_STATUS_t; 7014 7015 typedef union { 7016 uint32_t data; 7017 struct { 7018 #if IS_BIG_ENDIAN 7019 uint32_t reserved : 16; 7020 uint32_t ln3_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[15:12] - RO */ 7021 uint32_t ln2_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[11:08] - RO */ 7022 uint32_t ln1_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[07:04] - RO */ 7023 uint32_t ln0_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[03:00] - RO */ 7024 #endif /* IS_BIG_ENDIAN */ 7025 #if IS_LITTLE_ENDIAN 7026 uint32_t ln0_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[03:00] - RO */ 7027 uint32_t ln1_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[07:04] - RO */ 7028 uint32_t ln2_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[11:08] - RO */ 7029 uint32_t ln3_lnk_status : 4; /* FUR_MISC_CTRL_link_type_status_t[15:12] - RO */ 7030 uint32_t reserved : 16; 7031 #endif /* IS_LITTLE_ENDIAN */ 7032 } fields; 7033 } FUR_MISC_CTRL_link_type_status_t; 7034 7035 typedef FUR_MISC_CTRL_link_type_status_t FUR_MISC_CTRL_LINK_TYPE_STATUS_t; 7036 7037 typedef union { 7038 uint32_t data; 7039 struct { 7040 #if IS_BIG_ENDIAN 7041 uint32_t reserved : 16; 7042 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[15:10] - RSVD */ 7043 uint32_t twolane_pmd_prt1_ln0_on_pl : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[09:08] - WO */ 7044 uint32_t reserved_06 : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[07:06] - RSVD */ 7045 uint32_t twolane_pmd_prt2_ln0_on_pl : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[05:04] - WO */ 7046 uint32_t reserved_02 : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[03:02] - RSVD */ 7047 uint32_t single_pmd_prt1_ln0_on_pl : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[01:00] - WO */ 7048 #endif /* IS_BIG_ENDIAN */ 7049 #if IS_LITTLE_ENDIAN 7050 uint32_t single_pmd_prt1_ln0_on_pl : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[01:00] - WO */ 7051 uint32_t reserved_02 : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[03:02] - RSVD */ 7052 uint32_t twolane_pmd_prt2_ln0_on_pl : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[05:04] - WO */ 7053 uint32_t reserved_06 : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[07:06] - RSVD */ 7054 uint32_t twolane_pmd_prt1_ln0_on_pl : 2; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[09:08] - WO */ 7055 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_logic_to_phy_ln0_map_t[15:10] - RSVD */ 7056 uint32_t reserved : 16; 7057 #endif /* IS_LITTLE_ENDIAN */ 7058 } fields; 7059 } FUR_MISC_CTRL_logic_to_phy_ln0_map_t; 7060 7061 typedef FUR_MISC_CTRL_logic_to_phy_ln0_map_t FUR_MISC_CTRL_LOGIC_TO_PHY_LN0_MAP_t; 7062 7063 typedef union { 7064 uint32_t data; 7065 struct { 7066 #if IS_BIG_ENDIAN 7067 uint32_t reserved : 16; 7068 uint32_t reserved_12 : 4; /* FUR_MISC_CTRL_m0_eisr_t[15:12] - RSVD */ 7069 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_m0_eisr_t[11] - RSVD */ 7070 uint32_t reserved_10 : 1; /* FUR_MISC_CTRL_m0_eisr_t[10] - RSVD */ 7071 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_m0_eisr_t[09] - RSVD */ 7072 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_m0_eisr_t[08] - RSVD */ 7073 uint32_t m0_mst_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eisr_t[07] - WO */ 7074 uint32_t m0_slv_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eisr_t[06] - WO */ 7075 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_m0_eisr_t[05] - RSVD */ 7076 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_m0_eisr_t[04] - RSVD */ 7077 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_m0_eisr_t[03] - RSVD */ 7078 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_m0_eisr_t[02] - RSVD */ 7079 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_m0_eisr_t[01] - RSVD */ 7080 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_m0_eisr_t[00] - RSVD */ 7081 #endif /* IS_BIG_ENDIAN */ 7082 #if IS_LITTLE_ENDIAN 7083 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_m0_eisr_t[00] - RSVD */ 7084 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_m0_eisr_t[01] - RSVD */ 7085 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_m0_eisr_t[02] - RSVD */ 7086 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_m0_eisr_t[03] - RSVD */ 7087 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_m0_eisr_t[04] - RSVD */ 7088 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_m0_eisr_t[05] - RSVD */ 7089 uint32_t m0_slv_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eisr_t[06] - WO */ 7090 uint32_t m0_mst_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eisr_t[07] - WO */ 7091 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_m0_eisr_t[08] - RSVD */ 7092 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_m0_eisr_t[09] - RSVD */ 7093 uint32_t reserved_10 : 1; /* FUR_MISC_CTRL_m0_eisr_t[10] - RSVD */ 7094 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_m0_eisr_t[11] - RSVD */ 7095 uint32_t reserved_12 : 4; /* FUR_MISC_CTRL_m0_eisr_t[15:12] - RSVD */ 7096 uint32_t reserved : 16; 7097 #endif /* IS_LITTLE_ENDIAN */ 7098 } fields; 7099 } FUR_MISC_CTRL_m0_eisr_t; 7100 7101 typedef FUR_MISC_CTRL_m0_eisr_t FUR_MISC_CTRL_M0_EISR_t; 7102 7103 typedef union { 7104 uint32_t data; 7105 struct { 7106 #if IS_BIG_ENDIAN 7107 uint32_t reserved : 16; 7108 uint32_t reserved_12 : 4; /* FUR_MISC_CTRL_m0_eipr_t[15:12] - RSVD */ 7109 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_m0_eipr_t[11] - RSVD */ 7110 uint32_t reserved_10 : 1; /* FUR_MISC_CTRL_m0_eipr_t[10] - RSVD */ 7111 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_m0_eipr_t[09] - RSVD */ 7112 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_m0_eipr_t[08] - RSVD */ 7113 uint32_t p_m0_mst_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eipr_t[07] - RO */ 7114 uint32_t p_m0_slv_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eipr_t[06] - RO */ 7115 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_m0_eipr_t[05] - RSVD */ 7116 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_m0_eipr_t[04] - RSVD */ 7117 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_m0_eipr_t[03] - RSVD */ 7118 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_m0_eipr_t[02] - RSVD */ 7119 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_m0_eipr_t[01] - RSVD */ 7120 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_m0_eipr_t[00] - RSVD */ 7121 #endif /* IS_BIG_ENDIAN */ 7122 #if IS_LITTLE_ENDIAN 7123 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_m0_eipr_t[00] - RSVD */ 7124 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_m0_eipr_t[01] - RSVD */ 7125 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_m0_eipr_t[02] - RSVD */ 7126 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_m0_eipr_t[03] - RSVD */ 7127 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_m0_eipr_t[04] - RSVD */ 7128 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_m0_eipr_t[05] - RSVD */ 7129 uint32_t p_m0_slv_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eipr_t[06] - RO */ 7130 uint32_t p_m0_mst_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eipr_t[07] - RO */ 7131 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_m0_eipr_t[08] - RSVD */ 7132 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_m0_eipr_t[09] - RSVD */ 7133 uint32_t reserved_10 : 1; /* FUR_MISC_CTRL_m0_eipr_t[10] - RSVD */ 7134 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_m0_eipr_t[11] - RSVD */ 7135 uint32_t reserved_12 : 4; /* FUR_MISC_CTRL_m0_eipr_t[15:12] - RSVD */ 7136 uint32_t reserved : 16; 7137 #endif /* IS_LITTLE_ENDIAN */ 7138 } fields; 7139 } FUR_MISC_CTRL_m0_eipr_t; 7140 7141 typedef FUR_MISC_CTRL_m0_eipr_t FUR_MISC_CTRL_M0_EIPR_t; 7142 7143 typedef union { 7144 uint32_t data; 7145 struct { 7146 #if IS_BIG_ENDIAN 7147 uint32_t reserved : 16; 7148 uint32_t reserved_12 : 4; /* FUR_MISC_CTRL_m0_eimr_t[15:12] - RSVD */ 7149 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_m0_eimr_t[11] - RSVD */ 7150 uint32_t reserved_10 : 1; /* FUR_MISC_CTRL_m0_eimr_t[10] - RSVD */ 7151 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_m0_eimr_t[09] - RSVD */ 7152 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_m0_eimr_t[08] - RSVD */ 7153 uint32_t mask_m0_mst_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eimr_t[07] - WO */ 7154 uint32_t mask_m0_slv_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eimr_t[06] - WO */ 7155 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_m0_eimr_t[05] - RSVD */ 7156 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_m0_eimr_t[04] - RSVD */ 7157 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_m0_eimr_t[03] - RSVD */ 7158 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_m0_eimr_t[02] - RSVD */ 7159 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_m0_eimr_t[01] - RSVD */ 7160 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_m0_eimr_t[00] - RSVD */ 7161 #endif /* IS_BIG_ENDIAN */ 7162 #if IS_LITTLE_ENDIAN 7163 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_m0_eimr_t[00] - RSVD */ 7164 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_m0_eimr_t[01] - RSVD */ 7165 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_m0_eimr_t[02] - RSVD */ 7166 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_m0_eimr_t[03] - RSVD */ 7167 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_m0_eimr_t[04] - RSVD */ 7168 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_m0_eimr_t[05] - RSVD */ 7169 uint32_t mask_m0_slv_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eimr_t[06] - WO */ 7170 uint32_t mask_m0_mst_msgout_intr : 1; /* FUR_MISC_CTRL_m0_eimr_t[07] - WO */ 7171 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_m0_eimr_t[08] - RSVD */ 7172 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_m0_eimr_t[09] - RSVD */ 7173 uint32_t reserved_10 : 1; /* FUR_MISC_CTRL_m0_eimr_t[10] - RSVD */ 7174 uint32_t reserved_11 : 1; /* FUR_MISC_CTRL_m0_eimr_t[11] - RSVD */ 7175 uint32_t reserved_12 : 4; /* FUR_MISC_CTRL_m0_eimr_t[15:12] - RSVD */ 7176 uint32_t reserved : 16; 7177 #endif /* IS_LITTLE_ENDIAN */ 7178 } fields; 7179 } FUR_MISC_CTRL_m0_eimr_t; 7180 7181 typedef FUR_MISC_CTRL_m0_eimr_t FUR_MISC_CTRL_M0_EIMR_t; 7182 7183 typedef union { 7184 uint32_t data; 7185 struct { 7186 #if IS_BIG_ENDIAN 7187 uint32_t reserved : 16; 7188 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_sf_eisr_t[15:10] - RSVD */ 7189 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_sf_eisr_t[09] - RSVD */ 7190 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_sf_eisr_t[08] - RSVD */ 7191 uint32_t sys_pll_lock_found : 1; /* FUR_MISC_CTRL_sf_eisr_t[07] - WO */ 7192 uint32_t sys_pll_lock_lost : 1; /* FUR_MISC_CTRL_sf_eisr_t[06] - WO */ 7193 uint32_t sys_rx_sigdet_found : 1; /* FUR_MISC_CTRL_sf_eisr_t[05] - WO */ 7194 uint32_t sys_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_sf_eisr_t[04] - WO */ 7195 uint32_t sys_pmd_lock_found : 1; /* FUR_MISC_CTRL_sf_eisr_t[03] - WO */ 7196 uint32_t sys_pmd_lock_lost : 1; /* FUR_MISC_CTRL_sf_eisr_t[02] - WO */ 7197 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_sf_eisr_t[01] - RSVD */ 7198 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_sf_eisr_t[00] - RSVD */ 7199 #endif /* IS_BIG_ENDIAN */ 7200 #if IS_LITTLE_ENDIAN 7201 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_sf_eisr_t[00] - RSVD */ 7202 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_sf_eisr_t[01] - RSVD */ 7203 uint32_t sys_pmd_lock_lost : 1; /* FUR_MISC_CTRL_sf_eisr_t[02] - WO */ 7204 uint32_t sys_pmd_lock_found : 1; /* FUR_MISC_CTRL_sf_eisr_t[03] - WO */ 7205 uint32_t sys_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_sf_eisr_t[04] - WO */ 7206 uint32_t sys_rx_sigdet_found : 1; /* FUR_MISC_CTRL_sf_eisr_t[05] - WO */ 7207 uint32_t sys_pll_lock_lost : 1; /* FUR_MISC_CTRL_sf_eisr_t[06] - WO */ 7208 uint32_t sys_pll_lock_found : 1; /* FUR_MISC_CTRL_sf_eisr_t[07] - WO */ 7209 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_sf_eisr_t[08] - RSVD */ 7210 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_sf_eisr_t[09] - RSVD */ 7211 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_sf_eisr_t[15:10] - RSVD */ 7212 uint32_t reserved : 16; 7213 #endif /* IS_LITTLE_ENDIAN */ 7214 } fields; 7215 } FUR_MISC_CTRL_sf_eisr_t; 7216 7217 typedef FUR_MISC_CTRL_sf_eisr_t FUR_MISC_CTRL_SF_EISR_t; 7218 7219 typedef union { 7220 uint32_t data; 7221 struct { 7222 #if IS_BIG_ENDIAN 7223 uint32_t reserved : 16; 7224 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_sf_eipr_t[15:10] - RSVD */ 7225 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_sf_eipr_t[09] - RSVD */ 7226 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_sf_eipr_t[08] - RSVD */ 7227 uint32_t p_sys_pll_lock_found : 1; /* FUR_MISC_CTRL_sf_eipr_t[07] - RO */ 7228 uint32_t p_sys_pll_lock_lost : 1; /* FUR_MISC_CTRL_sf_eipr_t[06] - RO */ 7229 uint32_t p_sys_rx_sigdet_found : 1; /* FUR_MISC_CTRL_sf_eipr_t[05] - RO */ 7230 uint32_t p_sys_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_sf_eipr_t[04] - RO */ 7231 uint32_t p_sys_pmd_lock_found : 1; /* FUR_MISC_CTRL_sf_eipr_t[03] - RO */ 7232 uint32_t p_sys_pmd_lock_lost : 1; /* FUR_MISC_CTRL_sf_eipr_t[02] - RO */ 7233 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_sf_eipr_t[01] - RSVD */ 7234 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_sf_eipr_t[00] - RSVD */ 7235 #endif /* IS_BIG_ENDIAN */ 7236 #if IS_LITTLE_ENDIAN 7237 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_sf_eipr_t[00] - RSVD */ 7238 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_sf_eipr_t[01] - RSVD */ 7239 uint32_t p_sys_pmd_lock_lost : 1; /* FUR_MISC_CTRL_sf_eipr_t[02] - RO */ 7240 uint32_t p_sys_pmd_lock_found : 1; /* FUR_MISC_CTRL_sf_eipr_t[03] - RO */ 7241 uint32_t p_sys_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_sf_eipr_t[04] - RO */ 7242 uint32_t p_sys_rx_sigdet_found : 1; /* FUR_MISC_CTRL_sf_eipr_t[05] - RO */ 7243 uint32_t p_sys_pll_lock_lost : 1; /* FUR_MISC_CTRL_sf_eipr_t[06] - RO */ 7244 uint32_t p_sys_pll_lock_found : 1; /* FUR_MISC_CTRL_sf_eipr_t[07] - RO */ 7245 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_sf_eipr_t[08] - RSVD */ 7246 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_sf_eipr_t[09] - RSVD */ 7247 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_sf_eipr_t[15:10] - RSVD */ 7248 uint32_t reserved : 16; 7249 #endif /* IS_LITTLE_ENDIAN */ 7250 } fields; 7251 } FUR_MISC_CTRL_sf_eipr_t; 7252 7253 typedef FUR_MISC_CTRL_sf_eipr_t FUR_MISC_CTRL_SF_EIPR_t; 7254 7255 typedef union { 7256 uint32_t data; 7257 struct { 7258 #if IS_BIG_ENDIAN 7259 uint32_t reserved : 16; 7260 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_sf_eimr_t[15:10] - RSVD */ 7261 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_sf_eimr_t[09] - RSVD */ 7262 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_sf_eimr_t[08] - RSVD */ 7263 uint32_t mask_sys_pll_lock_found : 1; /* FUR_MISC_CTRL_sf_eimr_t[07] - WO */ 7264 uint32_t mask_sys_pll_lock_lost : 1; /* FUR_MISC_CTRL_sf_eimr_t[06] - WO */ 7265 uint32_t mask_sys_rx_sigdet_found : 1; /* FUR_MISC_CTRL_sf_eimr_t[05] - WO */ 7266 uint32_t mask_sys_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_sf_eimr_t[04] - WO */ 7267 uint32_t mask_sys_pmd_lock_found : 1; /* FUR_MISC_CTRL_sf_eimr_t[03] - WO */ 7268 uint32_t mask_sys_pmd_lock_lost : 1; /* FUR_MISC_CTRL_sf_eimr_t[02] - WO */ 7269 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_sf_eimr_t[01] - RSVD */ 7270 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_sf_eimr_t[00] - RSVD */ 7271 #endif /* IS_BIG_ENDIAN */ 7272 #if IS_LITTLE_ENDIAN 7273 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_sf_eimr_t[00] - RSVD */ 7274 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_sf_eimr_t[01] - RSVD */ 7275 uint32_t mask_sys_pmd_lock_lost : 1; /* FUR_MISC_CTRL_sf_eimr_t[02] - WO */ 7276 uint32_t mask_sys_pmd_lock_found : 1; /* FUR_MISC_CTRL_sf_eimr_t[03] - WO */ 7277 uint32_t mask_sys_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_sf_eimr_t[04] - WO */ 7278 uint32_t mask_sys_rx_sigdet_found : 1; /* FUR_MISC_CTRL_sf_eimr_t[05] - WO */ 7279 uint32_t mask_sys_pll_lock_lost : 1; /* FUR_MISC_CTRL_sf_eimr_t[06] - WO */ 7280 uint32_t mask_sys_pll_lock_found : 1; /* FUR_MISC_CTRL_sf_eimr_t[07] - WO */ 7281 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_sf_eimr_t[08] - RSVD */ 7282 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_sf_eimr_t[09] - RSVD */ 7283 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_sf_eimr_t[15:10] - RSVD */ 7284 uint32_t reserved : 16; 7285 #endif /* IS_LITTLE_ENDIAN */ 7286 } fields; 7287 } FUR_MISC_CTRL_sf_eimr_t; 7288 7289 typedef FUR_MISC_CTRL_sf_eimr_t FUR_MISC_CTRL_SF_EIMR_t; 7290 7291 typedef union { 7292 uint32_t data; 7293 struct { 7294 #if IS_BIG_ENDIAN 7295 uint32_t reserved : 16; 7296 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_lf_eisr_t[15:10] - RSVD */ 7297 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_lf_eisr_t[09] - RSVD */ 7298 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_lf_eisr_t[08] - RSVD */ 7299 uint32_t line_pll_lock_found : 1; /* FUR_MISC_CTRL_lf_eisr_t[07] - WO */ 7300 uint32_t line_pll_lock_lost : 1; /* FUR_MISC_CTRL_lf_eisr_t[06] - WO */ 7301 uint32_t line_rx_sigdet_found : 1; /* FUR_MISC_CTRL_lf_eisr_t[05] - WO */ 7302 uint32_t line_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_lf_eisr_t[04] - WO */ 7303 uint32_t line_pmd_lock_found : 1; /* FUR_MISC_CTRL_lf_eisr_t[03] - WO */ 7304 uint32_t line_pmd_lock_lost : 1; /* FUR_MISC_CTRL_lf_eisr_t[02] - WO */ 7305 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_lf_eisr_t[01] - RSVD */ 7306 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_lf_eisr_t[00] - RSVD */ 7307 #endif /* IS_BIG_ENDIAN */ 7308 #if IS_LITTLE_ENDIAN 7309 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_lf_eisr_t[00] - RSVD */ 7310 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_lf_eisr_t[01] - RSVD */ 7311 uint32_t line_pmd_lock_lost : 1; /* FUR_MISC_CTRL_lf_eisr_t[02] - WO */ 7312 uint32_t line_pmd_lock_found : 1; /* FUR_MISC_CTRL_lf_eisr_t[03] - WO */ 7313 uint32_t line_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_lf_eisr_t[04] - WO */ 7314 uint32_t line_rx_sigdet_found : 1; /* FUR_MISC_CTRL_lf_eisr_t[05] - WO */ 7315 uint32_t line_pll_lock_lost : 1; /* FUR_MISC_CTRL_lf_eisr_t[06] - WO */ 7316 uint32_t line_pll_lock_found : 1; /* FUR_MISC_CTRL_lf_eisr_t[07] - WO */ 7317 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_lf_eisr_t[08] - RSVD */ 7318 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_lf_eisr_t[09] - RSVD */ 7319 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_lf_eisr_t[15:10] - RSVD */ 7320 uint32_t reserved : 16; 7321 #endif /* IS_LITTLE_ENDIAN */ 7322 } fields; 7323 } FUR_MISC_CTRL_lf_eisr_t; 7324 7325 typedef FUR_MISC_CTRL_lf_eisr_t FUR_MISC_CTRL_LF_EISR_t; 7326 7327 typedef union { 7328 uint32_t data; 7329 struct { 7330 #if IS_BIG_ENDIAN 7331 uint32_t reserved : 16; 7332 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_lf_eipr_t[15:10] - RSVD */ 7333 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_lf_eipr_t[09] - RSVD */ 7334 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_lf_eipr_t[08] - RSVD */ 7335 uint32_t p_line_pll_lock_found : 1; /* FUR_MISC_CTRL_lf_eipr_t[07] - RO */ 7336 uint32_t p_line_pll_lock_lost : 1; /* FUR_MISC_CTRL_lf_eipr_t[06] - RO */ 7337 uint32_t p_line_rx_sigdet_found : 1; /* FUR_MISC_CTRL_lf_eipr_t[05] - RO */ 7338 uint32_t p_line_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_lf_eipr_t[04] - RO */ 7339 uint32_t p_line_pmd_lock_found : 1; /* FUR_MISC_CTRL_lf_eipr_t[03] - RO */ 7340 uint32_t p_line_pmd_lock_lost : 1; /* FUR_MISC_CTRL_lf_eipr_t[02] - RO */ 7341 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_lf_eipr_t[01] - RSVD */ 7342 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_lf_eipr_t[00] - RSVD */ 7343 #endif /* IS_BIG_ENDIAN */ 7344 #if IS_LITTLE_ENDIAN 7345 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_lf_eipr_t[00] - RSVD */ 7346 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_lf_eipr_t[01] - RSVD */ 7347 uint32_t p_line_pmd_lock_lost : 1; /* FUR_MISC_CTRL_lf_eipr_t[02] - RO */ 7348 uint32_t p_line_pmd_lock_found : 1; /* FUR_MISC_CTRL_lf_eipr_t[03] - RO */ 7349 uint32_t p_line_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_lf_eipr_t[04] - RO */ 7350 uint32_t p_line_rx_sigdet_found : 1; /* FUR_MISC_CTRL_lf_eipr_t[05] - RO */ 7351 uint32_t p_line_pll_lock_lost : 1; /* FUR_MISC_CTRL_lf_eipr_t[06] - RO */ 7352 uint32_t p_line_pll_lock_found : 1; /* FUR_MISC_CTRL_lf_eipr_t[07] - RO */ 7353 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_lf_eipr_t[08] - RSVD */ 7354 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_lf_eipr_t[09] - RSVD */ 7355 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_lf_eipr_t[15:10] - RSVD */ 7356 uint32_t reserved : 16; 7357 #endif /* IS_LITTLE_ENDIAN */ 7358 } fields; 7359 } FUR_MISC_CTRL_lf_eipr_t; 7360 7361 typedef FUR_MISC_CTRL_lf_eipr_t FUR_MISC_CTRL_LF_EIPR_t; 7362 7363 typedef union { 7364 uint32_t data; 7365 struct { 7366 #if IS_BIG_ENDIAN 7367 uint32_t reserved : 16; 7368 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_lf_eimr_t[15:10] - RSVD */ 7369 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_lf_eimr_t[09] - RSVD */ 7370 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_lf_eimr_t[08] - RSVD */ 7371 uint32_t mask_line_pll_lock_found : 1; /* FUR_MISC_CTRL_lf_eimr_t[07] - WO */ 7372 uint32_t mask_line_pll_lock_lost : 1; /* FUR_MISC_CTRL_lf_eimr_t[06] - WO */ 7373 uint32_t mask_line_rx_sigdet_found : 1; /* FUR_MISC_CTRL_lf_eimr_t[05] - WO */ 7374 uint32_t mask_line_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_lf_eimr_t[04] - WO */ 7375 uint32_t mask_line_pmd_lock_found : 1; /* FUR_MISC_CTRL_lf_eimr_t[03] - WO */ 7376 uint32_t mask_line_pmd_lock_lost : 1; /* FUR_MISC_CTRL_lf_eimr_t[02] - WO */ 7377 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_lf_eimr_t[01] - RSVD */ 7378 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_lf_eimr_t[00] - RSVD */ 7379 #endif /* IS_BIG_ENDIAN */ 7380 #if IS_LITTLE_ENDIAN 7381 uint32_t reserved_00 : 1; /* FUR_MISC_CTRL_lf_eimr_t[00] - RSVD */ 7382 uint32_t reserved_01 : 1; /* FUR_MISC_CTRL_lf_eimr_t[01] - RSVD */ 7383 uint32_t mask_line_pmd_lock_lost : 1; /* FUR_MISC_CTRL_lf_eimr_t[02] - WO */ 7384 uint32_t mask_line_pmd_lock_found : 1; /* FUR_MISC_CTRL_lf_eimr_t[03] - WO */ 7385 uint32_t mask_line_rx_sigdet_lost : 1; /* FUR_MISC_CTRL_lf_eimr_t[04] - WO */ 7386 uint32_t mask_line_rx_sigdet_found : 1; /* FUR_MISC_CTRL_lf_eimr_t[05] - WO */ 7387 uint32_t mask_line_pll_lock_lost : 1; /* FUR_MISC_CTRL_lf_eimr_t[06] - WO */ 7388 uint32_t mask_line_pll_lock_found : 1; /* FUR_MISC_CTRL_lf_eimr_t[07] - WO */ 7389 uint32_t reserved_08 : 1; /* FUR_MISC_CTRL_lf_eimr_t[08] - RSVD */ 7390 uint32_t reserved_09 : 1; /* FUR_MISC_CTRL_lf_eimr_t[09] - RSVD */ 7391 uint32_t reserved_10 : 6; /* FUR_MISC_CTRL_lf_eimr_t[15:10] - RSVD */ 7392 uint32_t reserved : 16; 7393 #endif /* IS_LITTLE_ENDIAN */ 7394 } fields; 7395 } FUR_MISC_CTRL_lf_eimr_t; 7396 7397 typedef FUR_MISC_CTRL_lf_eimr_t FUR_MISC_CTRL_LF_EIMR_t; 7398 7399 typedef union { 7400 uint32_t data; 7401 struct { 7402 #if IS_BIG_ENDIAN 7403 uint32_t reserved : 16; 7404 uint32_t cl73_an_complete_ln : 4; /* FUR_MISC_CTRL_rx_eisr_t[15:12] - WO */ 7405 uint32_t reserved_08 : 4; /* FUR_MISC_CTRL_rx_eisr_t[11:08] - RSVD */ 7406 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_rx_eisr_t[07] - RSVD */ 7407 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_rx_eisr_t[06] - RSVD */ 7408 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_rx_eisr_t[05] - RSVD */ 7409 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_rx_eisr_t[04] - RSVD */ 7410 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_rx_eisr_t[03] - RSVD */ 7411 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_rx_eisr_t[02] - RSVD */ 7412 uint32_t cl91_rx_align_found : 1; /* FUR_MISC_CTRL_rx_eisr_t[01] - WO */ 7413 uint32_t cl91_rx_align_lost : 1; /* FUR_MISC_CTRL_rx_eisr_t[00] - WO */ 7414 #endif /* IS_BIG_ENDIAN */ 7415 #if IS_LITTLE_ENDIAN 7416 uint32_t cl91_rx_align_lost : 1; /* FUR_MISC_CTRL_rx_eisr_t[00] - WO */ 7417 uint32_t cl91_rx_align_found : 1; /* FUR_MISC_CTRL_rx_eisr_t[01] - WO */ 7418 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_rx_eisr_t[02] - RSVD */ 7419 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_rx_eisr_t[03] - RSVD */ 7420 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_rx_eisr_t[04] - RSVD */ 7421 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_rx_eisr_t[05] - RSVD */ 7422 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_rx_eisr_t[06] - RSVD */ 7423 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_rx_eisr_t[07] - RSVD */ 7424 uint32_t reserved_08 : 4; /* FUR_MISC_CTRL_rx_eisr_t[11:08] - RSVD */ 7425 uint32_t cl73_an_complete_ln : 4; /* FUR_MISC_CTRL_rx_eisr_t[15:12] - WO */ 7426 uint32_t reserved : 16; 7427 #endif /* IS_LITTLE_ENDIAN */ 7428 } fields; 7429 } FUR_MISC_CTRL_rx_eisr_t; 7430 7431 typedef FUR_MISC_CTRL_rx_eisr_t FUR_MISC_CTRL_RX_EISR_t; 7432 7433 typedef union { 7434 uint32_t data; 7435 struct { 7436 #if IS_BIG_ENDIAN 7437 uint32_t p_cl73_an_complete_ln : 4; /* FUR_MISC_CTRL_rx_eipr_t[15:12] - RO */ 7438 uint32_t reserved_08 : 4; /* FUR_MISC_CTRL_rx_eipr_t[11:08] - RSVD */ 7439 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_rx_eipr_t[07] - RSVD */ 7440 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_rx_eipr_t[06] - RSVD */ 7441 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_rx_eipr_t[05] - RSVD */ 7442 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_rx_eipr_t[04] - RSVD */ 7443 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_rx_eipr_t[03] - RSVD */ 7444 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_rx_eipr_t[02] - RSVD */ 7445 uint32_t p_cl91_rx_align_found : 1; /* FUR_MISC_CTRL_rx_eipr_t[01] - RO */ 7446 uint32_t p_cl91_rx_align_lost : 1; /* FUR_MISC_CTRL_rx_eipr_t[00] - RO */ 7447 #endif /* IS_BIG_ENDIAN */ 7448 #if IS_LITTLE_ENDIAN 7449 uint32_t p_cl91_rx_align_lost : 1; /* FUR_MISC_CTRL_rx_eipr_t[00] - RO */ 7450 uint32_t p_cl91_rx_align_found : 1; /* FUR_MISC_CTRL_rx_eipr_t[01] - RO */ 7451 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_rx_eipr_t[02] - RSVD */ 7452 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_rx_eipr_t[03] - RSVD */ 7453 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_rx_eipr_t[04] - RSVD */ 7454 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_rx_eipr_t[05] - RSVD */ 7455 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_rx_eipr_t[06] - RSVD */ 7456 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_rx_eipr_t[07] - RSVD */ 7457 uint32_t reserved_08 : 4; /* FUR_MISC_CTRL_rx_eipr_t[11:08] - RSVD */ 7458 uint32_t p_cl73_an_complete_ln : 4; /* FUR_MISC_CTRL_rx_eipr_t[15:12] - RO */ 7459 uint32_t reserved : 16; 7460 #endif /* IS_LITTLE_ENDIAN */ 7461 } fields; 7462 } FUR_MISC_CTRL_rx_eipr_t; 7463 7464 typedef FUR_MISC_CTRL_rx_eipr_t FUR_MISC_CTRL_RX_EIPR_t; 7465 7466 typedef union { 7467 uint32_t data; 7468 struct { 7469 #if IS_BIG_ENDIAN 7470 uint32_t reserved : 16; 7471 uint32_t mask_cl73_an_complete_ln : 4; /* FUR_MISC_CTRL_rx_eimr_t[15:12] - WO */ 7472 uint32_t reserved_08 : 4; /* FUR_MISC_CTRL_rx_eimr_t[11:08] - RSVD */ 7473 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_rx_eimr_t[07] - RSVD */ 7474 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_rx_eimr_t[06] - RSVD */ 7475 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_rx_eimr_t[05] - RSVD */ 7476 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_rx_eimr_t[04] - RSVD */ 7477 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_rx_eimr_t[03] - RSVD */ 7478 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_rx_eimr_t[02] - RSVD */ 7479 uint32_t mask_cl91_rx_align_found : 1; /* FUR_MISC_CTRL_rx_eimr_t[01] - WO */ 7480 uint32_t mask_cl91_rx_align_lost : 1; /* FUR_MISC_CTRL_rx_eimr_t[00] - WO */ 7481 #endif /* IS_BIG_ENDIAN */ 7482 #if IS_LITTLE_ENDIAN 7483 uint32_t mask_cl91_rx_align_lost : 1; /* FUR_MISC_CTRL_rx_eimr_t[00] - WO */ 7484 uint32_t mask_cl91_rx_align_found : 1; /* FUR_MISC_CTRL_rx_eimr_t[01] - WO */ 7485 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_rx_eimr_t[02] - RSVD */ 7486 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_rx_eimr_t[03] - RSVD */ 7487 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_rx_eimr_t[04] - RSVD */ 7488 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_rx_eimr_t[05] - RSVD */ 7489 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_rx_eimr_t[06] - RSVD */ 7490 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_rx_eimr_t[07] - RSVD */ 7491 uint32_t reserved_08 : 4; /* FUR_MISC_CTRL_rx_eimr_t[11:08] - RSVD */ 7492 uint32_t mask_cl73_an_complete_ln : 4; /* FUR_MISC_CTRL_rx_eimr_t[15:12] - WO */ 7493 uint32_t reserved : 16; 7494 #endif /* IS_LITTLE_ENDIAN */ 7495 } fields; 7496 } FUR_MISC_CTRL_rx_eimr_t; 7497 7498 typedef FUR_MISC_CTRL_rx_eimr_t FUR_MISC_CTRL_RX_EIMR_t; 7499 7500 typedef union { 7501 uint32_t data; 7502 struct { 7503 #if IS_BIG_ENDIAN 7504 uint32_t reserved : 16; 7505 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_tx_eisr_t[15:08] - RSVD */ 7506 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_tx_eisr_t[07] - RSVD */ 7507 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_tx_eisr_t[06] - RSVD */ 7508 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_tx_eisr_t[05] - RSVD */ 7509 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_tx_eisr_t[04] - RSVD */ 7510 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_tx_eisr_t[03] - RSVD */ 7511 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_tx_eisr_t[02] - RSVD */ 7512 uint32_t cl91_tx_align_found : 1; /* FUR_MISC_CTRL_tx_eisr_t[01] - WO */ 7513 uint32_t cl91_tx_align_lost : 1; /* FUR_MISC_CTRL_tx_eisr_t[00] - WO */ 7514 #endif /* IS_BIG_ENDIAN */ 7515 #if IS_LITTLE_ENDIAN 7516 uint32_t cl91_tx_align_lost : 1; /* FUR_MISC_CTRL_tx_eisr_t[00] - WO */ 7517 uint32_t cl91_tx_align_found : 1; /* FUR_MISC_CTRL_tx_eisr_t[01] - WO */ 7518 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_tx_eisr_t[02] - RSVD */ 7519 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_tx_eisr_t[03] - RSVD */ 7520 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_tx_eisr_t[04] - RSVD */ 7521 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_tx_eisr_t[05] - RSVD */ 7522 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_tx_eisr_t[06] - RSVD */ 7523 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_tx_eisr_t[07] - RSVD */ 7524 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_tx_eisr_t[15:08] - RSVD */ 7525 uint32_t reserved : 16; 7526 #endif /* IS_LITTLE_ENDIAN */ 7527 } fields; 7528 } FUR_MISC_CTRL_tx_eisr_t; 7529 7530 typedef FUR_MISC_CTRL_tx_eisr_t FUR_MISC_CTRL_TX_EISR_t; 7531 7532 typedef union { 7533 uint32_t data; 7534 struct { 7535 #if IS_BIG_ENDIAN 7536 uint32_t reserved : 16; 7537 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_tx_eipr_t[15:08] - RSVD */ 7538 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_tx_eipr_t[07] - RSVD */ 7539 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_tx_eipr_t[06] - RSVD */ 7540 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_tx_eipr_t[05] - RSVD */ 7541 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_tx_eipr_t[04] - RSVD */ 7542 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_tx_eipr_t[03] - RSVD */ 7543 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_tx_eipr_t[02] - RSVD */ 7544 uint32_t p_cl91_tx_align_found : 1; /* FUR_MISC_CTRL_tx_eipr_t[01] - RO */ 7545 uint32_t p_cl91_tx_align_lost : 1; /* FUR_MISC_CTRL_tx_eipr_t[00] - RO */ 7546 #endif /* IS_BIG_ENDIAN */ 7547 #if IS_LITTLE_ENDIAN 7548 uint32_t p_cl91_tx_align_lost : 1; /* FUR_MISC_CTRL_tx_eipr_t[00] - RO */ 7549 uint32_t p_cl91_tx_align_found : 1; /* FUR_MISC_CTRL_tx_eipr_t[01] - RO */ 7550 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_tx_eipr_t[02] - RSVD */ 7551 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_tx_eipr_t[03] - RSVD */ 7552 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_tx_eipr_t[04] - RSVD */ 7553 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_tx_eipr_t[05] - RSVD */ 7554 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_tx_eipr_t[06] - RSVD */ 7555 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_tx_eipr_t[07] - RSVD */ 7556 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_tx_eipr_t[15:08] - RSVD */ 7557 uint32_t reserved : 16; 7558 #endif /* IS_LITTLE_ENDIAN */ 7559 } fields; 7560 } FUR_MISC_CTRL_tx_eipr_t; 7561 7562 typedef FUR_MISC_CTRL_tx_eipr_t FUR_MISC_CTRL_TX_EIPR_t; 7563 7564 typedef union { 7565 uint32_t data; 7566 struct { 7567 #if IS_BIG_ENDIAN 7568 uint32_t reserved : 16; 7569 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_tx_eimr_t[15:08] - RSVD */ 7570 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_tx_eimr_t[07] - RSVD */ 7571 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_tx_eimr_t[06] - RSVD */ 7572 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_tx_eimr_t[05] - RSVD */ 7573 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_tx_eimr_t[04] - RSVD */ 7574 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_tx_eimr_t[03] - RSVD */ 7575 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_tx_eimr_t[02] - RSVD */ 7576 uint32_t mask_cl91_tx_align_found : 1; /* FUR_MISC_CTRL_tx_eimr_t[01] - WO */ 7577 uint32_t mask_cl91_tx_align_lost : 1; /* FUR_MISC_CTRL_tx_eimr_t[00] - WO */ 7578 #endif /* IS_BIG_ENDIAN */ 7579 #if IS_LITTLE_ENDIAN 7580 uint32_t mask_cl91_tx_align_lost : 1; /* FUR_MISC_CTRL_tx_eimr_t[00] - WO */ 7581 uint32_t mask_cl91_tx_align_found : 1; /* FUR_MISC_CTRL_tx_eimr_t[01] - WO */ 7582 uint32_t reserved_02 : 1; /* FUR_MISC_CTRL_tx_eimr_t[02] - RSVD */ 7583 uint32_t reserved_03 : 1; /* FUR_MISC_CTRL_tx_eimr_t[03] - RSVD */ 7584 uint32_t reserved_04 : 1; /* FUR_MISC_CTRL_tx_eimr_t[04] - RSVD */ 7585 uint32_t reserved_05 : 1; /* FUR_MISC_CTRL_tx_eimr_t[05] - RSVD */ 7586 uint32_t reserved_06 : 1; /* FUR_MISC_CTRL_tx_eimr_t[06] - RSVD */ 7587 uint32_t reserved_07 : 1; /* FUR_MISC_CTRL_tx_eimr_t[07] - RSVD */ 7588 uint32_t reserved_08 : 8; /* FUR_MISC_CTRL_tx_eimr_t[15:08] - RSVD */ 7589 uint32_t reserved : 16; 7590 #endif /* IS_LITTLE_ENDIAN */ 7591 } fields; 7592 } FUR_MISC_CTRL_tx_eimr_t; 7593 7594 typedef FUR_MISC_CTRL_tx_eimr_t FUR_MISC_CTRL_TX_EIMR_t; 7595 7596 7597 /*-----------------------------------------------*/ 7598 /* Structs for CL91_USER_RX Bank */ 7599 /*-----------------------------------------------*/ 7600 typedef union { 7601 uint32_t data; 7602 struct { 7603 #if IS_BIG_ENDIAN 7604 uint32_t reserved : 16; 7605 uint32_t reserved_05 : 11; /* CL91_USER_RX_status_t[15:05] - RSVD */ 7606 uint32_t align_status : 1; /* CL91_USER_RX_status_t[04] - RO */ 7607 uint32_t amp_lock_ln : 4; /* CL91_USER_RX_status_t[03:00] - RO */ 7608 #endif /* IS_BIG_ENDIAN */ 7609 #if IS_LITTLE_ENDIAN 7610 uint32_t amp_lock_ln : 4; /* CL91_USER_RX_status_t[03:00] - RO */ 7611 uint32_t align_status : 1; /* CL91_USER_RX_status_t[04] - RO */ 7612 uint32_t reserved_05 : 11; /* CL91_USER_RX_status_t[15:05] - RSVD */ 7613 uint32_t reserved : 16; 7614 #endif /* IS_LITTLE_ENDIAN */ 7615 } fields; 7616 } CL91_USER_RX_status_t; 7617 7618 typedef CL91_USER_RX_status_t CL91_USER_RX_STATUS_t; 7619 7620 typedef union { 7621 uint32_t data; 7622 struct { 7623 #if IS_BIG_ENDIAN 7624 uint32_t reserved : 16; 7625 uint32_t reserved_10 : 6; /* CL91_USER_RX_latched_status_t[15:10] - RSVD */ 7626 uint32_t align_status_ll : 1; /* CL91_USER_RX_latched_status_t[09] - RO */ 7627 uint32_t align_status_lh : 1; /* CL91_USER_RX_latched_status_t[08] - RO */ 7628 uint32_t amp_lock_ln0_ll : 1; /* CL91_USER_RX_latched_status_t[07] - RO */ 7629 uint32_t amp_lock_ln0_lh : 1; /* CL91_USER_RX_latched_status_t[06] - RO */ 7630 uint32_t amp_lock_ln1_ll : 1; /* CL91_USER_RX_latched_status_t[05] - RO */ 7631 uint32_t amp_lock_ln1_lh : 1; /* CL91_USER_RX_latched_status_t[04] - RO */ 7632 uint32_t amp_lock_ln2_ll : 1; /* CL91_USER_RX_latched_status_t[03] - RO */ 7633 uint32_t amp_lock_ln2_lh : 1; /* CL91_USER_RX_latched_status_t[02] - RO */ 7634 uint32_t amp_lock_ln3_ll : 1; /* CL91_USER_RX_latched_status_t[01] - RO */ 7635 uint32_t amp_lock_ln3_lh : 1; /* CL91_USER_RX_latched_status_t[00] - RO */ 7636 #endif /* IS_BIG_ENDIAN */ 7637 #if IS_LITTLE_ENDIAN 7638 uint32_t amp_lock_ln3_lh : 1; /* CL91_USER_RX_latched_status_t[00] - RO */ 7639 uint32_t amp_lock_ln3_ll : 1; /* CL91_USER_RX_latched_status_t[01] - RO */ 7640 uint32_t amp_lock_ln2_lh : 1; /* CL91_USER_RX_latched_status_t[02] - RO */ 7641 uint32_t amp_lock_ln2_ll : 1; /* CL91_USER_RX_latched_status_t[03] - RO */ 7642 uint32_t amp_lock_ln1_lh : 1; /* CL91_USER_RX_latched_status_t[04] - RO */ 7643 uint32_t amp_lock_ln1_ll : 1; /* CL91_USER_RX_latched_status_t[05] - RO */ 7644 uint32_t amp_lock_ln0_lh : 1; /* CL91_USER_RX_latched_status_t[06] - RO */ 7645 uint32_t amp_lock_ln0_ll : 1; /* CL91_USER_RX_latched_status_t[07] - RO */ 7646 uint32_t align_status_lh : 1; /* CL91_USER_RX_latched_status_t[08] - RO */ 7647 uint32_t align_status_ll : 1; /* CL91_USER_RX_latched_status_t[09] - RO */ 7648 uint32_t reserved_10 : 6; /* CL91_USER_RX_latched_status_t[15:10] - RSVD */ 7649 uint32_t reserved : 16; 7650 #endif /* IS_LITTLE_ENDIAN */ 7651 } fields; 7652 } CL91_USER_RX_latched_status_t; 7653 7654 typedef CL91_USER_RX_latched_status_t CL91_USER_RX_LATCHED_STATUS_t; 7655 7656 typedef union { 7657 uint32_t data; 7658 struct { 7659 #if IS_BIG_ENDIAN 7660 uint32_t reserved : 16; 7661 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln3_t[15:14] - RSVD */ 7662 uint32_t bit_offset_ln3 : 6; /* CL91_USER_RX_skew_ln3_t[13:08] - RO */ 7663 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln3_t[07] - RSVD */ 7664 uint32_t fec_skew_ln3 : 7; /* CL91_USER_RX_skew_ln3_t[06:00] - RO */ 7665 #endif /* IS_BIG_ENDIAN */ 7666 #if IS_LITTLE_ENDIAN 7667 uint32_t fec_skew_ln3 : 7; /* CL91_USER_RX_skew_ln3_t[06:00] - RO */ 7668 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln3_t[07] - RSVD */ 7669 uint32_t bit_offset_ln3 : 6; /* CL91_USER_RX_skew_ln3_t[13:08] - RO */ 7670 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln3_t[15:14] - RSVD */ 7671 uint32_t reserved : 16; 7672 #endif /* IS_LITTLE_ENDIAN */ 7673 } fields; 7674 } CL91_USER_RX_skew_ln3_t; 7675 7676 typedef CL91_USER_RX_skew_ln3_t CL91_USER_RX_SKEW_LN3_t; 7677 7678 typedef union { 7679 uint32_t data; 7680 struct { 7681 #if IS_BIG_ENDIAN 7682 uint32_t reserved : 16; 7683 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln2_t[15:14] - RSVD */ 7684 uint32_t bit_offset_ln2 : 6; /* CL91_USER_RX_skew_ln2_t[13:08] - RO */ 7685 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln2_t[07] - RSVD */ 7686 uint32_t fec_skew_ln2 : 7; /* CL91_USER_RX_skew_ln2_t[06:00] - RO */ 7687 #endif /* IS_BIG_ENDIAN */ 7688 #if IS_LITTLE_ENDIAN 7689 uint32_t fec_skew_ln2 : 7; /* CL91_USER_RX_skew_ln2_t[06:00] - RO */ 7690 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln2_t[07] - RSVD */ 7691 uint32_t bit_offset_ln2 : 6; /* CL91_USER_RX_skew_ln2_t[13:08] - RO */ 7692 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln2_t[15:14] - RSVD */ 7693 uint32_t reserved : 16; 7694 #endif /* IS_LITTLE_ENDIAN */ 7695 } fields; 7696 } CL91_USER_RX_skew_ln2_t; 7697 7698 typedef CL91_USER_RX_skew_ln2_t CL91_USER_RX_SKEW_LN2_t; 7699 7700 typedef union { 7701 uint32_t data; 7702 struct { 7703 #if IS_BIG_ENDIAN 7704 uint32_t reserved : 16; 7705 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln1_t[15:14] - RSVD */ 7706 uint32_t bit_offset_ln1 : 6; /* CL91_USER_RX_skew_ln1_t[13:08] - RO */ 7707 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln1_t[07] - RSVD */ 7708 uint32_t fec_skew_ln1 : 7; /* CL91_USER_RX_skew_ln1_t[06:00] - RO */ 7709 #endif /* IS_BIG_ENDIAN */ 7710 #if IS_LITTLE_ENDIAN 7711 uint32_t fec_skew_ln1 : 7; /* CL91_USER_RX_skew_ln1_t[06:00] - RO */ 7712 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln1_t[07] - RSVD */ 7713 uint32_t bit_offset_ln1 : 6; /* CL91_USER_RX_skew_ln1_t[13:08] - RO */ 7714 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln1_t[15:14] - RSVD */ 7715 uint32_t reserved : 16; 7716 #endif /* IS_LITTLE_ENDIAN */ 7717 } fields; 7718 } CL91_USER_RX_skew_ln1_t; 7719 7720 typedef CL91_USER_RX_skew_ln1_t CL91_USER_RX_SKEW_LN1_t; 7721 7722 typedef union { 7723 uint32_t data; 7724 struct { 7725 #if IS_BIG_ENDIAN 7726 uint32_t reserved : 16; 7727 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln0_t[15:14] - RSVD */ 7728 uint32_t bit_offset_ln0 : 6; /* CL91_USER_RX_skew_ln0_t[13:08] - RO */ 7729 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln0_t[07] - RSVD */ 7730 uint32_t fec_skew_ln0 : 7; /* CL91_USER_RX_skew_ln0_t[06:00] - RO */ 7731 #endif /* IS_BIG_ENDIAN */ 7732 #if IS_LITTLE_ENDIAN 7733 uint32_t fec_skew_ln0 : 7; /* CL91_USER_RX_skew_ln0_t[06:00] - RO */ 7734 uint32_t reserved_07 : 1; /* CL91_USER_RX_skew_ln0_t[07] - RSVD */ 7735 uint32_t bit_offset_ln0 : 6; /* CL91_USER_RX_skew_ln0_t[13:08] - RO */ 7736 uint32_t reserved_14 : 2; /* CL91_USER_RX_skew_ln0_t[15:14] - RSVD */ 7737 uint32_t reserved : 16; 7738 #endif /* IS_LITTLE_ENDIAN */ 7739 } fields; 7740 } CL91_USER_RX_skew_ln0_t; 7741 7742 typedef CL91_USER_RX_skew_ln0_t CL91_USER_RX_SKEW_LN0_t; 7743 7744 typedef union { 7745 uint32_t data; 7746 struct { 7747 #if IS_BIG_ENDIAN 7748 uint32_t reserved : 16; 7749 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[15:13] - RSVD */ 7750 uint32_t phy_ln3_log_ln2 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[12:08] - WO */ 7751 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[07:05] - RSVD */ 7752 uint32_t phy_ln3_log_ln3 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[04:00] - WO */ 7753 #endif /* IS_BIG_ENDIAN */ 7754 #if IS_LITTLE_ENDIAN 7755 uint32_t phy_ln3_log_ln3 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[04:00] - WO */ 7756 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[07:05] - RSVD */ 7757 uint32_t phy_ln3_log_ln2 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[12:08] - WO */ 7758 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl1_t[15:13] - RSVD */ 7759 uint32_t reserved : 16; 7760 #endif /* IS_LITTLE_ENDIAN */ 7761 } fields; 7762 } CL91_USER_RX_phy_ln3_mapping_ctrl1_t; 7763 7764 typedef CL91_USER_RX_phy_ln3_mapping_ctrl1_t CL91_USER_RX_PHY_LN3_MAPPING_CTRL1_t; 7765 7766 typedef union { 7767 uint32_t data; 7768 struct { 7769 #if IS_BIG_ENDIAN 7770 uint32_t reserved : 16; 7771 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[15:13] - RSVD */ 7772 uint32_t phy_ln3_log_ln0 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[12:08] - WO */ 7773 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[07:05] - RSVD */ 7774 uint32_t phy_ln3_log_ln1 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[04:00] - WO */ 7775 #endif /* IS_BIG_ENDIAN */ 7776 #if IS_LITTLE_ENDIAN 7777 uint32_t phy_ln3_log_ln1 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[04:00] - WO */ 7778 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[07:05] - RSVD */ 7779 uint32_t phy_ln3_log_ln0 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[12:08] - WO */ 7780 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln3_mapping_ctrl2_t[15:13] - RSVD */ 7781 uint32_t reserved : 16; 7782 #endif /* IS_LITTLE_ENDIAN */ 7783 } fields; 7784 } CL91_USER_RX_phy_ln3_mapping_ctrl2_t; 7785 7786 typedef CL91_USER_RX_phy_ln3_mapping_ctrl2_t CL91_USER_RX_PHY_LN3_MAPPING_CTRL2_t; 7787 7788 typedef union { 7789 uint32_t data; 7790 struct { 7791 #if IS_BIG_ENDIAN 7792 uint32_t reserved : 16; 7793 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_t[15:05] - RSVD */ 7794 uint32_t phy_ln3_log_ln4 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_t[04:00] - WO */ 7795 #endif /* IS_BIG_ENDIAN */ 7796 #if IS_LITTLE_ENDIAN 7797 uint32_t phy_ln3_log_ln4 : 5; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_t[04:00] - WO */ 7798 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln3_mapping_ctrl3_t[15:05] - RSVD */ 7799 uint32_t reserved : 16; 7800 #endif /* IS_LITTLE_ENDIAN */ 7801 } fields; 7802 } CL91_USER_RX_phy_ln3_mapping_ctrl3_t; 7803 7804 typedef CL91_USER_RX_phy_ln3_mapping_ctrl3_t CL91_USER_RX_PHY_LN3_MAPPING_CTRL3_t; 7805 7806 typedef union { 7807 uint32_t data; 7808 struct { 7809 #if IS_BIG_ENDIAN 7810 uint32_t reserved : 16; 7811 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[15:13] - RSVD */ 7812 uint32_t phy_ln2_log_ln2 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[12:08] - WO */ 7813 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[07:05] - RSVD */ 7814 uint32_t phy_ln2_log_ln3 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[04:00] - WO */ 7815 #endif /* IS_BIG_ENDIAN */ 7816 #if IS_LITTLE_ENDIAN 7817 uint32_t phy_ln2_log_ln3 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[04:00] - WO */ 7818 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[07:05] - RSVD */ 7819 uint32_t phy_ln2_log_ln2 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[12:08] - WO */ 7820 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl1_t[15:13] - RSVD */ 7821 uint32_t reserved : 16; 7822 #endif /* IS_LITTLE_ENDIAN */ 7823 } fields; 7824 } CL91_USER_RX_phy_ln2_mapping_ctrl1_t; 7825 7826 typedef CL91_USER_RX_phy_ln2_mapping_ctrl1_t CL91_USER_RX_PHY_LN2_MAPPING_CTRL1_t; 7827 7828 typedef union { 7829 uint32_t data; 7830 struct { 7831 #if IS_BIG_ENDIAN 7832 uint32_t reserved : 16; 7833 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[15:13] - RSVD */ 7834 uint32_t phy_ln2_log_ln0 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[12:08] - WO */ 7835 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[07:05] - RSVD */ 7836 uint32_t phy_ln2_log_ln1 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[04:00] - WO */ 7837 #endif /* IS_BIG_ENDIAN */ 7838 #if IS_LITTLE_ENDIAN 7839 uint32_t phy_ln2_log_ln1 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[04:00] - WO */ 7840 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[07:05] - RSVD */ 7841 uint32_t phy_ln2_log_ln0 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[12:08] - WO */ 7842 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln2_mapping_ctrl2_t[15:13] - RSVD */ 7843 uint32_t reserved : 16; 7844 #endif /* IS_LITTLE_ENDIAN */ 7845 } fields; 7846 } CL91_USER_RX_phy_ln2_mapping_ctrl2_t; 7847 7848 typedef CL91_USER_RX_phy_ln2_mapping_ctrl2_t CL91_USER_RX_PHY_LN2_MAPPING_CTRL2_t; 7849 7850 typedef union { 7851 uint32_t data; 7852 struct { 7853 #if IS_BIG_ENDIAN 7854 uint32_t reserved : 16; 7855 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_t[15:05] - RSVD */ 7856 uint32_t phy_ln2_log_ln4 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_t[04:00] - WO */ 7857 #endif /* IS_BIG_ENDIAN */ 7858 #if IS_LITTLE_ENDIAN 7859 uint32_t phy_ln2_log_ln4 : 5; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_t[04:00] - WO */ 7860 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln2_mapping_ctrl3_t[15:05] - RSVD */ 7861 uint32_t reserved : 16; 7862 #endif /* IS_LITTLE_ENDIAN */ 7863 } fields; 7864 } CL91_USER_RX_phy_ln2_mapping_ctrl3_t; 7865 7866 typedef CL91_USER_RX_phy_ln2_mapping_ctrl3_t CL91_USER_RX_PHY_LN2_MAPPING_CTRL3_t; 7867 7868 typedef union { 7869 uint32_t data; 7870 struct { 7871 #if IS_BIG_ENDIAN 7872 uint32_t reserved : 16; 7873 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[15:13] - RSVD */ 7874 uint32_t phy_ln1_log_ln2 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[12:08] - WO */ 7875 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[07:05] - RSVD */ 7876 uint32_t phy_ln1_log_ln3 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[04:00] - WO */ 7877 #endif /* IS_BIG_ENDIAN */ 7878 #if IS_LITTLE_ENDIAN 7879 uint32_t phy_ln1_log_ln3 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[04:00] - WO */ 7880 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[07:05] - RSVD */ 7881 uint32_t phy_ln1_log_ln2 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[12:08] - WO */ 7882 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl1_t[15:13] - RSVD */ 7883 uint32_t reserved : 16; 7884 #endif /* IS_LITTLE_ENDIAN */ 7885 } fields; 7886 } CL91_USER_RX_phy_ln1_mapping_ctrl1_t; 7887 7888 typedef CL91_USER_RX_phy_ln1_mapping_ctrl1_t CL91_USER_RX_PHY_LN1_MAPPING_CTRL1_t; 7889 7890 typedef union { 7891 uint32_t data; 7892 struct { 7893 #if IS_BIG_ENDIAN 7894 uint32_t reserved : 16; 7895 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[15:13] - RSVD */ 7896 uint32_t phy_ln1_log_ln0 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[12:08] - WO */ 7897 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[07:05] - RSVD */ 7898 uint32_t phy_ln1_log_ln1 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[04:00] - WO */ 7899 #endif /* IS_BIG_ENDIAN */ 7900 #if IS_LITTLE_ENDIAN 7901 uint32_t phy_ln1_log_ln1 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[04:00] - WO */ 7902 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[07:05] - RSVD */ 7903 uint32_t phy_ln1_log_ln0 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[12:08] - WO */ 7904 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln1_mapping_ctrl2_t[15:13] - RSVD */ 7905 uint32_t reserved : 16; 7906 #endif /* IS_LITTLE_ENDIAN */ 7907 } fields; 7908 } CL91_USER_RX_phy_ln1_mapping_ctrl2_t; 7909 7910 typedef CL91_USER_RX_phy_ln1_mapping_ctrl2_t CL91_USER_RX_PHY_LN1_MAPPING_CTRL2_t; 7911 7912 typedef union { 7913 uint32_t data; 7914 struct { 7915 #if IS_BIG_ENDIAN 7916 uint32_t reserved : 16; 7917 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_t[15:05] - RSVD */ 7918 uint32_t phy_ln1_log_ln4 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_t[04:00] - WO */ 7919 #endif /* IS_BIG_ENDIAN */ 7920 #if IS_LITTLE_ENDIAN 7921 uint32_t phy_ln1_log_ln4 : 5; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_t[04:00] - WO */ 7922 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln1_mapping_ctrl3_t[15:05] - RSVD */ 7923 uint32_t reserved : 16; 7924 #endif /* IS_LITTLE_ENDIAN */ 7925 } fields; 7926 } CL91_USER_RX_phy_ln1_mapping_ctrl3_t; 7927 7928 typedef CL91_USER_RX_phy_ln1_mapping_ctrl3_t CL91_USER_RX_PHY_LN1_MAPPING_CTRL3_t; 7929 7930 typedef union { 7931 uint32_t data; 7932 struct { 7933 #if IS_BIG_ENDIAN 7934 uint32_t reserved : 16; 7935 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[15:13] - RSVD */ 7936 uint32_t phy_ln0_log_ln2 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[12:08] - WO */ 7937 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[07:05] - RSVD */ 7938 uint32_t phy_ln0_log_ln3 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[04:00] - WO */ 7939 #endif /* IS_BIG_ENDIAN */ 7940 #if IS_LITTLE_ENDIAN 7941 uint32_t phy_ln0_log_ln3 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[04:00] - WO */ 7942 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[07:05] - RSVD */ 7943 uint32_t phy_ln0_log_ln2 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[12:08] - WO */ 7944 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl1_t[15:13] - RSVD */ 7945 uint32_t reserved : 16; 7946 #endif /* IS_LITTLE_ENDIAN */ 7947 } fields; 7948 } CL91_USER_RX_phy_ln0_mapping_ctrl1_t; 7949 7950 typedef CL91_USER_RX_phy_ln0_mapping_ctrl1_t CL91_USER_RX_PHY_LN0_MAPPING_CTRL1_t; 7951 7952 typedef union { 7953 uint32_t data; 7954 struct { 7955 #if IS_BIG_ENDIAN 7956 uint32_t reserved : 16; 7957 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[15:13] - RSVD */ 7958 uint32_t phy_ln0_log_ln0 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[12:08] - WO */ 7959 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[07:05] - RSVD */ 7960 uint32_t phy_ln0_log_ln1 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[04:00] - WO */ 7961 #endif /* IS_BIG_ENDIAN */ 7962 #if IS_LITTLE_ENDIAN 7963 uint32_t phy_ln0_log_ln1 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[04:00] - WO */ 7964 uint32_t reserved_05 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[07:05] - RSVD */ 7965 uint32_t phy_ln0_log_ln0 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[12:08] - WO */ 7966 uint32_t reserved_13 : 3; /* CL91_USER_RX_phy_ln0_mapping_ctrl2_t[15:13] - RSVD */ 7967 uint32_t reserved : 16; 7968 #endif /* IS_LITTLE_ENDIAN */ 7969 } fields; 7970 } CL91_USER_RX_phy_ln0_mapping_ctrl2_t; 7971 7972 typedef CL91_USER_RX_phy_ln0_mapping_ctrl2_t CL91_USER_RX_PHY_LN0_MAPPING_CTRL2_t; 7973 7974 typedef union { 7975 uint32_t data; 7976 struct { 7977 #if IS_BIG_ENDIAN 7978 uint32_t reserved : 16; 7979 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_t[15:05] - RSVD */ 7980 uint32_t phy_ln0_log_ln4 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_t[04:00] - WO */ 7981 #endif /* IS_BIG_ENDIAN */ 7982 #if IS_LITTLE_ENDIAN 7983 uint32_t phy_ln0_log_ln4 : 5; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_t[04:00] - WO */ 7984 uint32_t reserved_05 : 11; /* CL91_USER_RX_phy_ln0_mapping_ctrl3_t[15:05] - RSVD */ 7985 uint32_t reserved : 16; 7986 #endif /* IS_LITTLE_ENDIAN */ 7987 } fields; 7988 } CL91_USER_RX_phy_ln0_mapping_ctrl3_t; 7989 7990 typedef CL91_USER_RX_phy_ln0_mapping_ctrl3_t CL91_USER_RX_PHY_LN0_MAPPING_CTRL3_t; 7991 7992 typedef union { 7993 uint32_t data; 7994 struct { 7995 #if IS_BIG_ENDIAN 7996 uint32_t reserved : 16; 7997 uint32_t rx_dp_rstb : 1; /* CL91_USER_RX_debug_ctrl_t[15] - WO */ 7998 uint32_t frc_rx_dp_rstb : 1; /* CL91_USER_RX_debug_ctrl_t[14] - WO */ 7999 uint32_t reserved_10 : 4; /* CL91_USER_RX_debug_ctrl_t[13:10] - RSVD */ 8000 uint32_t debug_out_ctrl : 2; /* CL91_USER_RX_debug_ctrl_t[09:08] - WO */ 8001 uint32_t reserved_05 : 3; /* CL91_USER_RX_debug_ctrl_t[07:05] - RSVD */ 8002 uint32_t byp_dec_ooa : 1; /* CL91_USER_RX_debug_ctrl_t[04] - WO */ 8003 uint32_t crpt_xcw_on_loa : 1; /* CL91_USER_RX_debug_ctrl_t[03] - WO */ 8004 uint32_t frc_am_relock : 1; /* CL91_USER_RX_debug_ctrl_t[02] - WO */ 8005 uint32_t frc_re_align : 1; /* CL91_USER_RX_debug_ctrl_t[01] - WO */ 8006 uint32_t rst_dsc_fifo : 1; /* CL91_USER_RX_debug_ctrl_t[00] - WO */ 8007 #endif /* IS_BIG_ENDIAN */ 8008 #if IS_LITTLE_ENDIAN 8009 uint32_t rst_dsc_fifo : 1; /* CL91_USER_RX_debug_ctrl_t[00] - WO */ 8010 uint32_t frc_re_align : 1; /* CL91_USER_RX_debug_ctrl_t[01] - WO */ 8011 uint32_t frc_am_relock : 1; /* CL91_USER_RX_debug_ctrl_t[02] - WO */ 8012 uint32_t crpt_xcw_on_loa : 1; /* CL91_USER_RX_debug_ctrl_t[03] - WO */ 8013 uint32_t byp_dec_ooa : 1; /* CL91_USER_RX_debug_ctrl_t[04] - WO */ 8014 uint32_t reserved_05 : 3; /* CL91_USER_RX_debug_ctrl_t[07:05] - RSVD */ 8015 uint32_t debug_out_ctrl : 2; /* CL91_USER_RX_debug_ctrl_t[09:08] - WO */ 8016 uint32_t reserved_10 : 4; /* CL91_USER_RX_debug_ctrl_t[13:10] - RSVD */ 8017 uint32_t frc_rx_dp_rstb : 1; /* CL91_USER_RX_debug_ctrl_t[14] - WO */ 8018 uint32_t rx_dp_rstb : 1; /* CL91_USER_RX_debug_ctrl_t[15] - WO */ 8019 uint32_t reserved : 16; 8020 #endif /* IS_LITTLE_ENDIAN */ 8021 } fields; 8022 } CL91_USER_RX_debug_ctrl_t; 8023 8024 typedef CL91_USER_RX_debug_ctrl_t CL91_USER_RX_DEBUG_CTRL_t; 8025 8026 typedef union { 8027 uint32_t data; 8028 struct { 8029 #if IS_BIG_ENDIAN 8030 uint32_t reserved : 16; 8031 uint32_t reserved_11 : 5; /* CL91_USER_RX_debug_status1_t[15:11] - RSVD */ 8032 uint32_t deskew_fail_lh : 1; /* CL91_USER_RX_debug_status1_t[10] - RO */ 8033 uint32_t three_bad_cw_lh : 1; /* CL91_USER_RX_debug_status1_t[09] - RO */ 8034 uint32_t non_unique_am_lh : 1; /* CL91_USER_RX_debug_status1_t[08] - RO */ 8035 uint32_t bad_cw_lh : 1; /* CL91_USER_RX_debug_status1_t[07] - RO */ 8036 uint32_t dsc_fifo_colsn_ln0_lh : 1; /* CL91_USER_RX_debug_status1_t[06] - RO */ 8037 uint32_t dsc_fifo_colsn_ln1_lh : 1; /* CL91_USER_RX_debug_status1_t[05] - RO */ 8038 uint32_t dsc_fifo_colsn_ln2_lh : 1; /* CL91_USER_RX_debug_status1_t[04] - RO */ 8039 uint32_t dsc_fifo_colsn_ln3_lh : 1; /* CL91_USER_RX_debug_status1_t[03] - RO */ 8040 uint32_t dsc_err_lh : 1; /* CL91_USER_RX_debug_status1_t[02] - RO */ 8041 uint32_t rx_xc_sh_err_lh : 1; /* CL91_USER_RX_debug_status1_t[01] - RO */ 8042 uint32_t rx_xc_blk_err_lh : 1; /* CL91_USER_RX_debug_status1_t[00] - RO */ 8043 #endif /* IS_BIG_ENDIAN */ 8044 #if IS_LITTLE_ENDIAN 8045 uint32_t rx_xc_blk_err_lh : 1; /* CL91_USER_RX_debug_status1_t[00] - RO */ 8046 uint32_t rx_xc_sh_err_lh : 1; /* CL91_USER_RX_debug_status1_t[01] - RO */ 8047 uint32_t dsc_err_lh : 1; /* CL91_USER_RX_debug_status1_t[02] - RO */ 8048 uint32_t dsc_fifo_colsn_ln3_lh : 1; /* CL91_USER_RX_debug_status1_t[03] - RO */ 8049 uint32_t dsc_fifo_colsn_ln2_lh : 1; /* CL91_USER_RX_debug_status1_t[04] - RO */ 8050 uint32_t dsc_fifo_colsn_ln1_lh : 1; /* CL91_USER_RX_debug_status1_t[05] - RO */ 8051 uint32_t dsc_fifo_colsn_ln0_lh : 1; /* CL91_USER_RX_debug_status1_t[06] - RO */ 8052 uint32_t bad_cw_lh : 1; /* CL91_USER_RX_debug_status1_t[07] - RO */ 8053 uint32_t non_unique_am_lh : 1; /* CL91_USER_RX_debug_status1_t[08] - RO */ 8054 uint32_t three_bad_cw_lh : 1; /* CL91_USER_RX_debug_status1_t[09] - RO */ 8055 uint32_t deskew_fail_lh : 1; /* CL91_USER_RX_debug_status1_t[10] - RO */ 8056 uint32_t reserved_11 : 5; /* CL91_USER_RX_debug_status1_t[15:11] - RSVD */ 8057 uint32_t reserved : 16; 8058 #endif /* IS_LITTLE_ENDIAN */ 8059 } fields; 8060 } CL91_USER_RX_debug_status1_t; 8061 8062 typedef CL91_USER_RX_debug_status1_t CL91_USER_RX_DEBUG_STATUS1_t; 8063 8064 typedef union { 8065 uint32_t data; 8066 struct { 8067 #if IS_BIG_ENDIAN 8068 uint32_t reserved : 16; 8069 uint32_t reserved_11 : 5; /* CL91_USER_RX_debug_status2_t[15:11] - RSVD */ 8070 uint32_t fec_algn_sm_state : 3; /* CL91_USER_RX_debug_status2_t[10:08] - RO */ 8071 uint32_t am_lk_sm_state_ln3 : 2; /* CL91_USER_RX_debug_status2_t[07:06] - RO */ 8072 uint32_t am_lk_sm_state_ln2 : 2; /* CL91_USER_RX_debug_status2_t[05:04] - RO */ 8073 uint32_t am_lk_sm_state_ln1 : 2; /* CL91_USER_RX_debug_status2_t[03:02] - RO */ 8074 uint32_t am_lk_sm_state_ln0 : 2; /* CL91_USER_RX_debug_status2_t[01:00] - RO */ 8075 #endif /* IS_BIG_ENDIAN */ 8076 #if IS_LITTLE_ENDIAN 8077 uint32_t am_lk_sm_state_ln0 : 2; /* CL91_USER_RX_debug_status2_t[01:00] - RO */ 8078 uint32_t am_lk_sm_state_ln1 : 2; /* CL91_USER_RX_debug_status2_t[03:02] - RO */ 8079 uint32_t am_lk_sm_state_ln2 : 2; /* CL91_USER_RX_debug_status2_t[05:04] - RO */ 8080 uint32_t am_lk_sm_state_ln3 : 2; /* CL91_USER_RX_debug_status2_t[07:06] - RO */ 8081 uint32_t fec_algn_sm_state : 3; /* CL91_USER_RX_debug_status2_t[10:08] - RO */ 8082 uint32_t reserved_11 : 5; /* CL91_USER_RX_debug_status2_t[15:11] - RSVD */ 8083 uint32_t reserved : 16; 8084 #endif /* IS_LITTLE_ENDIAN */ 8085 } fields; 8086 } CL91_USER_RX_debug_status2_t; 8087 8088 typedef CL91_USER_RX_debug_status2_t CL91_USER_RX_DEBUG_STATUS2_t; 8089 8090 8091 /*-----------------------------------------------*/ 8092 /* Structs for CL91_USER_TX Bank */ 8093 /*-----------------------------------------------*/ 8094 typedef union { 8095 uint32_t data; 8096 struct { 8097 #if IS_BIG_ENDIAN 8098 uint32_t reserved : 16; 8099 uint32_t tx_dp_rstb : 1; /* CL91_USER_TX_control_t[15] - WO */ 8100 uint32_t frc_tx_dp_rstb : 1; /* CL91_USER_TX_control_t[14] - WO */ 8101 uint32_t reserved_for_eco_04 : 10; /* CL91_USER_TX_control_t[13:04] - RSVD */ 8102 uint32_t use_mlg_10g_am : 1; /* CL91_USER_TX_control_t[03] - WO */ 8103 uint32_t use_mlg_40g_am : 1; /* CL91_USER_TX_control_t[02] - WO */ 8104 uint32_t dis_som_on_loa : 1; /* CL91_USER_TX_control_t[01] - WO */ 8105 uint32_t crpt_xcw_on_loa : 1; /* CL91_USER_TX_control_t[00] - WO */ 8106 #endif /* IS_BIG_ENDIAN */ 8107 #if IS_LITTLE_ENDIAN 8108 uint32_t crpt_xcw_on_loa : 1; /* CL91_USER_TX_control_t[00] - WO */ 8109 uint32_t dis_som_on_loa : 1; /* CL91_USER_TX_control_t[01] - WO */ 8110 uint32_t use_mlg_40g_am : 1; /* CL91_USER_TX_control_t[02] - WO */ 8111 uint32_t use_mlg_10g_am : 1; /* CL91_USER_TX_control_t[03] - WO */ 8112 uint32_t reserved_for_eco_04 : 10; /* CL91_USER_TX_control_t[13:04] - RSVD */ 8113 uint32_t frc_tx_dp_rstb : 1; /* CL91_USER_TX_control_t[14] - WO */ 8114 uint32_t tx_dp_rstb : 1; /* CL91_USER_TX_control_t[15] - WO */ 8115 uint32_t reserved : 16; 8116 #endif /* IS_LITTLE_ENDIAN */ 8117 } fields; 8118 } CL91_USER_TX_control_t; 8119 8120 typedef CL91_USER_TX_control_t CL91_USER_TX_CONTROL_t; 8121 8122 typedef union { 8123 uint32_t data; 8124 struct { 8125 #if IS_BIG_ENDIAN 8126 uint32_t reserved : 16; 8127 uint32_t reserved_for_eco_05 : 11; /* CL91_USER_TX_status1_t[15:05] - RSVD */ 8128 uint32_t tx_xc_sh_err_lh : 1; /* CL91_USER_TX_status1_t[04] - RO */ 8129 uint32_t all_aligned_lh : 1; /* CL91_USER_TX_status1_t[03] - RO */ 8130 uint32_t all_aligned_ll : 1; /* CL91_USER_TX_status1_t[02] - RO */ 8131 uint32_t all_aligned : 1; /* CL91_USER_TX_status1_t[01] - RO */ 8132 uint32_t nonuniq_pcsl_found_lh : 1; /* CL91_USER_TX_status1_t[00] - RO */ 8133 #endif /* IS_BIG_ENDIAN */ 8134 #if IS_LITTLE_ENDIAN 8135 uint32_t nonuniq_pcsl_found_lh : 1; /* CL91_USER_TX_status1_t[00] - RO */ 8136 uint32_t all_aligned : 1; /* CL91_USER_TX_status1_t[01] - RO */ 8137 uint32_t all_aligned_ll : 1; /* CL91_USER_TX_status1_t[02] - RO */ 8138 uint32_t all_aligned_lh : 1; /* CL91_USER_TX_status1_t[03] - RO */ 8139 uint32_t tx_xc_sh_err_lh : 1; /* CL91_USER_TX_status1_t[04] - RO */ 8140 uint32_t reserved_for_eco_05 : 11; /* CL91_USER_TX_status1_t[15:05] - RSVD */ 8141 uint32_t reserved : 16; 8142 #endif /* IS_LITTLE_ENDIAN */ 8143 } fields; 8144 } CL91_USER_TX_status1_t; 8145 8146 typedef CL91_USER_TX_status1_t CL91_USER_TX_STATUS1_t; 8147 8148 typedef union { 8149 uint32_t data; 8150 struct { 8151 #if IS_BIG_ENDIAN 8152 uint32_t reserved : 16; 8153 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status2_t[15:10] - RSVD */ 8154 uint32_t block_lock_9_0 : 10; /* CL91_USER_TX_status2_t[09:00] - RO */ 8155 #endif /* IS_BIG_ENDIAN */ 8156 #if IS_LITTLE_ENDIAN 8157 uint32_t block_lock_9_0 : 10; /* CL91_USER_TX_status2_t[09:00] - RO */ 8158 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status2_t[15:10] - RSVD */ 8159 uint32_t reserved : 16; 8160 #endif /* IS_LITTLE_ENDIAN */ 8161 } fields; 8162 } CL91_USER_TX_status2_t; 8163 8164 typedef CL91_USER_TX_status2_t CL91_USER_TX_STATUS2_t; 8165 8166 typedef union { 8167 uint32_t data; 8168 struct { 8169 #if IS_BIG_ENDIAN 8170 uint32_t reserved : 16; 8171 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status3_t[15:10] - RSVD */ 8172 uint32_t block_lock_19_10 : 10; /* CL91_USER_TX_status3_t[09:00] - RO */ 8173 #endif /* IS_BIG_ENDIAN */ 8174 #if IS_LITTLE_ENDIAN 8175 uint32_t block_lock_19_10 : 10; /* CL91_USER_TX_status3_t[09:00] - RO */ 8176 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status3_t[15:10] - RSVD */ 8177 uint32_t reserved : 16; 8178 #endif /* IS_LITTLE_ENDIAN */ 8179 } fields; 8180 } CL91_USER_TX_status3_t; 8181 8182 typedef CL91_USER_TX_status3_t CL91_USER_TX_STATUS3_t; 8183 8184 typedef union { 8185 uint32_t data; 8186 struct { 8187 #if IS_BIG_ENDIAN 8188 uint32_t reserved : 16; 8189 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status4_t[15:10] - RSVD */ 8190 uint32_t am_lock_9_0 : 10; /* CL91_USER_TX_status4_t[09:00] - RO */ 8191 #endif /* IS_BIG_ENDIAN */ 8192 #if IS_LITTLE_ENDIAN 8193 uint32_t am_lock_9_0 : 10; /* CL91_USER_TX_status4_t[09:00] - RO */ 8194 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status4_t[15:10] - RSVD */ 8195 uint32_t reserved : 16; 8196 #endif /* IS_LITTLE_ENDIAN */ 8197 } fields; 8198 } CL91_USER_TX_status4_t; 8199 8200 typedef CL91_USER_TX_status4_t CL91_USER_TX_STATUS4_t; 8201 8202 typedef union { 8203 uint32_t data; 8204 struct { 8205 #if IS_BIG_ENDIAN 8206 uint32_t reserved : 16; 8207 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status5_t[15:10] - RSVD */ 8208 uint32_t am_lock_19_10 : 10; /* CL91_USER_TX_status5_t[09:00] - RO */ 8209 #endif /* IS_BIG_ENDIAN */ 8210 #if IS_LITTLE_ENDIAN 8211 uint32_t am_lock_19_10 : 10; /* CL91_USER_TX_status5_t[09:00] - RO */ 8212 uint32_t reserved_for_eco_10 : 6; /* CL91_USER_TX_status5_t[15:10] - RSVD */ 8213 uint32_t reserved : 16; 8214 #endif /* IS_LITTLE_ENDIAN */ 8215 } fields; 8216 } CL91_USER_TX_status5_t; 8217 8218 typedef CL91_USER_TX_status5_t CL91_USER_TX_STATUS5_t; 8219 8220 typedef union { 8221 uint32_t data; 8222 struct { 8223 #if IS_BIG_ENDIAN 8224 uint32_t reserved : 16; 8225 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln0_status_t[15:14] - RSVD */ 8226 uint32_t ln0_block_lock : 1; /* CL91_USER_TX_ln0_status_t[13] - RO */ 8227 uint32_t ln0_block_lock_lh : 1; /* CL91_USER_TX_ln0_status_t[12] - RO */ 8228 uint32_t ln0_block_lock_ll : 1; /* CL91_USER_TX_ln0_status_t[11] - RO */ 8229 uint32_t ln0_am_lock : 1; /* CL91_USER_TX_ln0_status_t[10] - RO */ 8230 uint32_t ln0_am_lock_lh : 1; /* CL91_USER_TX_ln0_status_t[09] - RO */ 8231 uint32_t ln0_am_lock_ll : 1; /* CL91_USER_TX_ln0_status_t[08] - RO */ 8232 uint32_t reserved_05 : 3; /* CL91_USER_TX_ln0_status_t[07:05] - RSVD */ 8233 uint32_t ln0_pcsl_lane_number : 5; /* CL91_USER_TX_ln0_status_t[04:00] - RO */ 8234 #endif /* IS_BIG_ENDIAN */ 8235 #if IS_LITTLE_ENDIAN 8236 uint32_t ln0_pcsl_lane_number : 5; /* CL91_USER_TX_ln0_status_t[04:00] - RO */ 8237 uint32_t reserved_05 : 3; /* CL91_USER_TX_ln0_status_t[07:05] - RSVD */ 8238 uint32_t ln0_am_lock_ll : 1; /* CL91_USER_TX_ln0_status_t[08] - RO */ 8239 uint32_t ln0_am_lock_lh : 1; /* CL91_USER_TX_ln0_status_t[09] - RO */ 8240 uint32_t ln0_am_lock : 1; /* CL91_USER_TX_ln0_status_t[10] - RO */ 8241 uint32_t ln0_block_lock_ll : 1; /* CL91_USER_TX_ln0_status_t[11] - RO */ 8242 uint32_t ln0_block_lock_lh : 1; /* CL91_USER_TX_ln0_status_t[12] - RO */ 8243 uint32_t ln0_block_lock : 1; /* CL91_USER_TX_ln0_status_t[13] - RO */ 8244 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln0_status_t[15:14] - RSVD */ 8245 uint32_t reserved : 16; 8246 #endif /* IS_LITTLE_ENDIAN */ 8247 } fields; 8248 } CL91_USER_TX_ln0_status_t; 8249 8250 typedef CL91_USER_TX_ln0_status_t CL91_USER_TX_LN0_STATUS_t; 8251 8252 typedef union { 8253 uint32_t data; 8254 struct { 8255 #if IS_BIG_ENDIAN 8256 uint32_t reserved : 16; 8257 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln1_status_t[15:14] - RSVD */ 8258 uint32_t ln1_block_lock : 1; /* CL91_USER_TX_ln1_status_t[13] - RO */ 8259 uint32_t ln1_block_lock_lh : 1; /* CL91_USER_TX_ln1_status_t[12] - RO */ 8260 uint32_t ln1_block_lock_ll : 1; /* CL91_USER_TX_ln1_status_t[11] - RO */ 8261 uint32_t ln1_am_lock : 1; /* CL91_USER_TX_ln1_status_t[10] - RO */ 8262 uint32_t ln1_am_lock_lh : 1; /* CL91_USER_TX_ln1_status_t[09] - RO */ 8263 uint32_t ln1_am_lock_ll : 1; /* CL91_USER_TX_ln1_status_t[08] - RO */ 8264 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln1_status_t[07:05] - RSVD */ 8265 uint32_t ln1_pcsl_lane_number : 5; /* CL91_USER_TX_ln1_status_t[04:00] - RO */ 8266 #endif /* IS_BIG_ENDIAN */ 8267 #if IS_LITTLE_ENDIAN 8268 uint32_t ln1_pcsl_lane_number : 5; /* CL91_USER_TX_ln1_status_t[04:00] - RO */ 8269 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln1_status_t[07:05] - RSVD */ 8270 uint32_t ln1_am_lock_ll : 1; /* CL91_USER_TX_ln1_status_t[08] - RO */ 8271 uint32_t ln1_am_lock_lh : 1; /* CL91_USER_TX_ln1_status_t[09] - RO */ 8272 uint32_t ln1_am_lock : 1; /* CL91_USER_TX_ln1_status_t[10] - RO */ 8273 uint32_t ln1_block_lock_ll : 1; /* CL91_USER_TX_ln1_status_t[11] - RO */ 8274 uint32_t ln1_block_lock_lh : 1; /* CL91_USER_TX_ln1_status_t[12] - RO */ 8275 uint32_t ln1_block_lock : 1; /* CL91_USER_TX_ln1_status_t[13] - RO */ 8276 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln1_status_t[15:14] - RSVD */ 8277 uint32_t reserved : 16; 8278 #endif /* IS_LITTLE_ENDIAN */ 8279 } fields; 8280 } CL91_USER_TX_ln1_status_t; 8281 8282 typedef CL91_USER_TX_ln1_status_t CL91_USER_TX_LN1_STATUS_t; 8283 8284 typedef union { 8285 uint32_t data; 8286 struct { 8287 #if IS_BIG_ENDIAN 8288 uint32_t reserved : 16; 8289 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln2_status_t[15:14] - RSVD */ 8290 uint32_t ln2_block_lock : 1; /* CL91_USER_TX_ln2_status_t[13] - RO */ 8291 uint32_t ln2_block_lock_lh : 1; /* CL91_USER_TX_ln2_status_t[12] - RO */ 8292 uint32_t ln2_block_lock_ll : 1; /* CL91_USER_TX_ln2_status_t[11] - RO */ 8293 uint32_t ln2_am_lock : 1; /* CL91_USER_TX_ln2_status_t[10] - RO */ 8294 uint32_t ln2_am_lock_lh : 1; /* CL91_USER_TX_ln2_status_t[09] - RO */ 8295 uint32_t ln2_am_lock_ll : 1; /* CL91_USER_TX_ln2_status_t[08] - RO */ 8296 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln2_status_t[07:05] - RSVD */ 8297 uint32_t ln2_pcsl_lane_number : 5; /* CL91_USER_TX_ln2_status_t[04:00] - RO */ 8298 #endif /* IS_BIG_ENDIAN */ 8299 #if IS_LITTLE_ENDIAN 8300 uint32_t ln2_pcsl_lane_number : 5; /* CL91_USER_TX_ln2_status_t[04:00] - RO */ 8301 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln2_status_t[07:05] - RSVD */ 8302 uint32_t ln2_am_lock_ll : 1; /* CL91_USER_TX_ln2_status_t[08] - RO */ 8303 uint32_t ln2_am_lock_lh : 1; /* CL91_USER_TX_ln2_status_t[09] - RO */ 8304 uint32_t ln2_am_lock : 1; /* CL91_USER_TX_ln2_status_t[10] - RO */ 8305 uint32_t ln2_block_lock_ll : 1; /* CL91_USER_TX_ln2_status_t[11] - RO */ 8306 uint32_t ln2_block_lock_lh : 1; /* CL91_USER_TX_ln2_status_t[12] - RO */ 8307 uint32_t ln2_block_lock : 1; /* CL91_USER_TX_ln2_status_t[13] - RO */ 8308 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln2_status_t[15:14] - RSVD */ 8309 uint32_t reserved : 16; 8310 #endif /* IS_LITTLE_ENDIAN */ 8311 } fields; 8312 } CL91_USER_TX_ln2_status_t; 8313 8314 typedef CL91_USER_TX_ln2_status_t CL91_USER_TX_LN2_STATUS_t; 8315 8316 typedef union { 8317 uint32_t data; 8318 struct { 8319 #if IS_BIG_ENDIAN 8320 uint32_t reserved : 16; 8321 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln3_status_t[15:14] - RSVD */ 8322 uint32_t ln3_block_lock : 1; /* CL91_USER_TX_ln3_status_t[13] - RO */ 8323 uint32_t ln3_block_lock_lh : 1; /* CL91_USER_TX_ln3_status_t[12] - RO */ 8324 uint32_t ln3_block_lock_ll : 1; /* CL91_USER_TX_ln3_status_t[11] - RO */ 8325 uint32_t ln3_am_lock : 1; /* CL91_USER_TX_ln3_status_t[10] - RO */ 8326 uint32_t ln3_am_lock_lh : 1; /* CL91_USER_TX_ln3_status_t[09] - RO */ 8327 uint32_t ln3_am_lock_ll : 1; /* CL91_USER_TX_ln3_status_t[08] - RO */ 8328 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln3_status_t[07:05] - RSVD */ 8329 uint32_t ln3_pcsl_lane_number : 5; /* CL91_USER_TX_ln3_status_t[04:00] - RO */ 8330 #endif /* IS_BIG_ENDIAN */ 8331 #if IS_LITTLE_ENDIAN 8332 uint32_t ln3_pcsl_lane_number : 5; /* CL91_USER_TX_ln3_status_t[04:00] - RO */ 8333 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln3_status_t[07:05] - RSVD */ 8334 uint32_t ln3_am_lock_ll : 1; /* CL91_USER_TX_ln3_status_t[08] - RO */ 8335 uint32_t ln3_am_lock_lh : 1; /* CL91_USER_TX_ln3_status_t[09] - RO */ 8336 uint32_t ln3_am_lock : 1; /* CL91_USER_TX_ln3_status_t[10] - RO */ 8337 uint32_t ln3_block_lock_ll : 1; /* CL91_USER_TX_ln3_status_t[11] - RO */ 8338 uint32_t ln3_block_lock_lh : 1; /* CL91_USER_TX_ln3_status_t[12] - RO */ 8339 uint32_t ln3_block_lock : 1; /* CL91_USER_TX_ln3_status_t[13] - RO */ 8340 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln3_status_t[15:14] - RSVD */ 8341 uint32_t reserved : 16; 8342 #endif /* IS_LITTLE_ENDIAN */ 8343 } fields; 8344 } CL91_USER_TX_ln3_status_t; 8345 8346 typedef CL91_USER_TX_ln3_status_t CL91_USER_TX_LN3_STATUS_t; 8347 8348 typedef union { 8349 uint32_t data; 8350 struct { 8351 #if IS_BIG_ENDIAN 8352 uint32_t reserved : 16; 8353 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln4_status_t[15:14] - RSVD */ 8354 uint32_t ln4_block_lock : 1; /* CL91_USER_TX_ln4_status_t[13] - RO */ 8355 uint32_t ln4_block_lock_lh : 1; /* CL91_USER_TX_ln4_status_t[12] - RO */ 8356 uint32_t ln4_block_lock_ll : 1; /* CL91_USER_TX_ln4_status_t[11] - RO */ 8357 uint32_t ln4_am_lock : 1; /* CL91_USER_TX_ln4_status_t[10] - RO */ 8358 uint32_t ln4_am_lock_lh : 1; /* CL91_USER_TX_ln4_status_t[09] - RO */ 8359 uint32_t ln4_am_lock_ll : 1; /* CL91_USER_TX_ln4_status_t[08] - RO */ 8360 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln4_status_t[07:05] - RSVD */ 8361 uint32_t ln4_pcsl_lane_number : 5; /* CL91_USER_TX_ln4_status_t[04:00] - RO */ 8362 #endif /* IS_BIG_ENDIAN */ 8363 #if IS_LITTLE_ENDIAN 8364 uint32_t ln4_pcsl_lane_number : 5; /* CL91_USER_TX_ln4_status_t[04:00] - RO */ 8365 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln4_status_t[07:05] - RSVD */ 8366 uint32_t ln4_am_lock_ll : 1; /* CL91_USER_TX_ln4_status_t[08] - RO */ 8367 uint32_t ln4_am_lock_lh : 1; /* CL91_USER_TX_ln4_status_t[09] - RO */ 8368 uint32_t ln4_am_lock : 1; /* CL91_USER_TX_ln4_status_t[10] - RO */ 8369 uint32_t ln4_block_lock_ll : 1; /* CL91_USER_TX_ln4_status_t[11] - RO */ 8370 uint32_t ln4_block_lock_lh : 1; /* CL91_USER_TX_ln4_status_t[12] - RO */ 8371 uint32_t ln4_block_lock : 1; /* CL91_USER_TX_ln4_status_t[13] - RO */ 8372 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln4_status_t[15:14] - RSVD */ 8373 uint32_t reserved : 16; 8374 #endif /* IS_LITTLE_ENDIAN */ 8375 } fields; 8376 } CL91_USER_TX_ln4_status_t; 8377 8378 typedef CL91_USER_TX_ln4_status_t CL91_USER_TX_LN4_STATUS_t; 8379 8380 typedef union { 8381 uint32_t data; 8382 struct { 8383 #if IS_BIG_ENDIAN 8384 uint32_t reserved : 16; 8385 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln5_status_t[15:14] - RSVD */ 8386 uint32_t ln5_block_lock : 1; /* CL91_USER_TX_ln5_status_t[13] - RO */ 8387 uint32_t ln5_block_lock_lh : 1; /* CL91_USER_TX_ln5_status_t[12] - RO */ 8388 uint32_t ln5_block_lock_ll : 1; /* CL91_USER_TX_ln5_status_t[11] - RO */ 8389 uint32_t ln5_am_lock : 1; /* CL91_USER_TX_ln5_status_t[10] - RO */ 8390 uint32_t ln5_am_lock_lh : 1; /* CL91_USER_TX_ln5_status_t[09] - RO */ 8391 uint32_t ln5_am_lock_ll : 1; /* CL91_USER_TX_ln5_status_t[08] - RO */ 8392 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln5_status_t[07:05] - RSVD */ 8393 uint32_t ln5_pcsl_lane_number : 5; /* CL91_USER_TX_ln5_status_t[04:00] - RO */ 8394 #endif /* IS_BIG_ENDIAN */ 8395 #if IS_LITTLE_ENDIAN 8396 uint32_t ln5_pcsl_lane_number : 5; /* CL91_USER_TX_ln5_status_t[04:00] - RO */ 8397 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln5_status_t[07:05] - RSVD */ 8398 uint32_t ln5_am_lock_ll : 1; /* CL91_USER_TX_ln5_status_t[08] - RO */ 8399 uint32_t ln5_am_lock_lh : 1; /* CL91_USER_TX_ln5_status_t[09] - RO */ 8400 uint32_t ln5_am_lock : 1; /* CL91_USER_TX_ln5_status_t[10] - RO */ 8401 uint32_t ln5_block_lock_ll : 1; /* CL91_USER_TX_ln5_status_t[11] - RO */ 8402 uint32_t ln5_block_lock_lh : 1; /* CL91_USER_TX_ln5_status_t[12] - RO */ 8403 uint32_t ln5_block_lock : 1; /* CL91_USER_TX_ln5_status_t[13] - RO */ 8404 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln5_status_t[15:14] - RSVD */ 8405 uint32_t reserved : 16; 8406 #endif /* IS_LITTLE_ENDIAN */ 8407 } fields; 8408 } CL91_USER_TX_ln5_status_t; 8409 8410 typedef CL91_USER_TX_ln5_status_t CL91_USER_TX_LN5_STATUS_t; 8411 8412 typedef union { 8413 uint32_t data; 8414 struct { 8415 #if IS_BIG_ENDIAN 8416 uint32_t reserved : 16; 8417 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln6_status_t[15:14] - RSVD */ 8418 uint32_t ln6_block_lock : 1; /* CL91_USER_TX_ln6_status_t[13] - RO */ 8419 uint32_t ln6_block_lock_lh : 1; /* CL91_USER_TX_ln6_status_t[12] - RO */ 8420 uint32_t ln6_block_lock_ll : 1; /* CL91_USER_TX_ln6_status_t[11] - RO */ 8421 uint32_t ln6_am_lock : 1; /* CL91_USER_TX_ln6_status_t[10] - RO */ 8422 uint32_t ln6_am_lock_lh : 1; /* CL91_USER_TX_ln6_status_t[09] - RO */ 8423 uint32_t ln6_am_lock_ll : 1; /* CL91_USER_TX_ln6_status_t[08] - RO */ 8424 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln6_status_t[07:05] - RSVD */ 8425 uint32_t ln6_pcsl_lane_number : 5; /* CL91_USER_TX_ln6_status_t[04:00] - RO */ 8426 #endif /* IS_BIG_ENDIAN */ 8427 #if IS_LITTLE_ENDIAN 8428 uint32_t ln6_pcsl_lane_number : 5; /* CL91_USER_TX_ln6_status_t[04:00] - RO */ 8429 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln6_status_t[07:05] - RSVD */ 8430 uint32_t ln6_am_lock_ll : 1; /* CL91_USER_TX_ln6_status_t[08] - RO */ 8431 uint32_t ln6_am_lock_lh : 1; /* CL91_USER_TX_ln6_status_t[09] - RO */ 8432 uint32_t ln6_am_lock : 1; /* CL91_USER_TX_ln6_status_t[10] - RO */ 8433 uint32_t ln6_block_lock_ll : 1; /* CL91_USER_TX_ln6_status_t[11] - RO */ 8434 uint32_t ln6_block_lock_lh : 1; /* CL91_USER_TX_ln6_status_t[12] - RO */ 8435 uint32_t ln6_block_lock : 1; /* CL91_USER_TX_ln6_status_t[13] - RO */ 8436 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln6_status_t[15:14] - RSVD */ 8437 uint32_t reserved : 16; 8438 #endif /* IS_LITTLE_ENDIAN */ 8439 } fields; 8440 } CL91_USER_TX_ln6_status_t; 8441 8442 typedef CL91_USER_TX_ln6_status_t CL91_USER_TX_LN6_STATUS_t; 8443 8444 typedef union { 8445 uint32_t data; 8446 struct { 8447 #if IS_BIG_ENDIAN 8448 uint32_t reserved : 16; 8449 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln7_status_t[15:14] - RSVD */ 8450 uint32_t ln7_block_lock : 1; /* CL91_USER_TX_ln7_status_t[13] - RO */ 8451 uint32_t ln7_block_lock_lh : 1; /* CL91_USER_TX_ln7_status_t[12] - RO */ 8452 uint32_t ln7_block_lock_ll : 1; /* CL91_USER_TX_ln7_status_t[11] - RO */ 8453 uint32_t ln7_am_lock : 1; /* CL91_USER_TX_ln7_status_t[10] - RO */ 8454 uint32_t ln7_am_lock_lh : 1; /* CL91_USER_TX_ln7_status_t[09] - RO */ 8455 uint32_t ln7_am_lock_ll : 1; /* CL91_USER_TX_ln7_status_t[08] - RO */ 8456 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln7_status_t[07:05] - RSVD */ 8457 uint32_t ln7_pcsl_lane_number : 5; /* CL91_USER_TX_ln7_status_t[04:00] - RO */ 8458 #endif /* IS_BIG_ENDIAN */ 8459 #if IS_LITTLE_ENDIAN 8460 uint32_t ln7_pcsl_lane_number : 5; /* CL91_USER_TX_ln7_status_t[04:00] - RO */ 8461 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln7_status_t[07:05] - RSVD */ 8462 uint32_t ln7_am_lock_ll : 1; /* CL91_USER_TX_ln7_status_t[08] - RO */ 8463 uint32_t ln7_am_lock_lh : 1; /* CL91_USER_TX_ln7_status_t[09] - RO */ 8464 uint32_t ln7_am_lock : 1; /* CL91_USER_TX_ln7_status_t[10] - RO */ 8465 uint32_t ln7_block_lock_ll : 1; /* CL91_USER_TX_ln7_status_t[11] - RO */ 8466 uint32_t ln7_block_lock_lh : 1; /* CL91_USER_TX_ln7_status_t[12] - RO */ 8467 uint32_t ln7_block_lock : 1; /* CL91_USER_TX_ln7_status_t[13] - RO */ 8468 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln7_status_t[15:14] - RSVD */ 8469 uint32_t reserved : 16; 8470 #endif /* IS_LITTLE_ENDIAN */ 8471 } fields; 8472 } CL91_USER_TX_ln7_status_t; 8473 8474 typedef CL91_USER_TX_ln7_status_t CL91_USER_TX_LN7_STATUS_t; 8475 8476 typedef union { 8477 uint32_t data; 8478 struct { 8479 #if IS_BIG_ENDIAN 8480 uint32_t reserved : 16; 8481 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln8_status_t[15:14] - RSVD */ 8482 uint32_t ln8_block_lock : 1; /* CL91_USER_TX_ln8_status_t[13] - RO */ 8483 uint32_t ln8_block_lock_lh : 1; /* CL91_USER_TX_ln8_status_t[12] - RO */ 8484 uint32_t ln8_block_lock_ll : 1; /* CL91_USER_TX_ln8_status_t[11] - RO */ 8485 uint32_t ln8_am_lock : 1; /* CL91_USER_TX_ln8_status_t[10] - RO */ 8486 uint32_t ln8_am_lock_lh : 1; /* CL91_USER_TX_ln8_status_t[09] - RO */ 8487 uint32_t ln8_am_lock_ll : 1; /* CL91_USER_TX_ln8_status_t[08] - RO */ 8488 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln8_status_t[07:05] - RSVD */ 8489 uint32_t ln8_pcsl_lane_number : 5; /* CL91_USER_TX_ln8_status_t[04:00] - RO */ 8490 #endif /* IS_BIG_ENDIAN */ 8491 #if IS_LITTLE_ENDIAN 8492 uint32_t ln8_pcsl_lane_number : 5; /* CL91_USER_TX_ln8_status_t[04:00] - RO */ 8493 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln8_status_t[07:05] - RSVD */ 8494 uint32_t ln8_am_lock_ll : 1; /* CL91_USER_TX_ln8_status_t[08] - RO */ 8495 uint32_t ln8_am_lock_lh : 1; /* CL91_USER_TX_ln8_status_t[09] - RO */ 8496 uint32_t ln8_am_lock : 1; /* CL91_USER_TX_ln8_status_t[10] - RO */ 8497 uint32_t ln8_block_lock_ll : 1; /* CL91_USER_TX_ln8_status_t[11] - RO */ 8498 uint32_t ln8_block_lock_lh : 1; /* CL91_USER_TX_ln8_status_t[12] - RO */ 8499 uint32_t ln8_block_lock : 1; /* CL91_USER_TX_ln8_status_t[13] - RO */ 8500 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln8_status_t[15:14] - RSVD */ 8501 uint32_t reserved : 16; 8502 #endif /* IS_LITTLE_ENDIAN */ 8503 } fields; 8504 } CL91_USER_TX_ln8_status_t; 8505 8506 typedef CL91_USER_TX_ln8_status_t CL91_USER_TX_LN8_STATUS_t; 8507 8508 typedef union { 8509 uint32_t data; 8510 struct { 8511 #if IS_BIG_ENDIAN 8512 uint32_t reserved : 16; 8513 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln9_status_t[15:14] - RSVD */ 8514 uint32_t ln9_block_lock : 1; /* CL91_USER_TX_ln9_status_t[13] - RO */ 8515 uint32_t ln9_block_lock_lh : 1; /* CL91_USER_TX_ln9_status_t[12] - RO */ 8516 uint32_t ln9_block_lock_ll : 1; /* CL91_USER_TX_ln9_status_t[11] - RO */ 8517 uint32_t ln9_am_lock : 1; /* CL91_USER_TX_ln9_status_t[10] - RO */ 8518 uint32_t ln9_am_lock_lh : 1; /* CL91_USER_TX_ln9_status_t[09] - RO */ 8519 uint32_t ln9_am_lock_ll : 1; /* CL91_USER_TX_ln9_status_t[08] - RO */ 8520 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln9_status_t[07:05] - RSVD */ 8521 uint32_t ln9_pcsl_lane_number : 5; /* CL91_USER_TX_ln9_status_t[04:00] - RO */ 8522 #endif /* IS_BIG_ENDIAN */ 8523 #if IS_LITTLE_ENDIAN 8524 uint32_t ln9_pcsl_lane_number : 5; /* CL91_USER_TX_ln9_status_t[04:00] - RO */ 8525 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln9_status_t[07:05] - RSVD */ 8526 uint32_t ln9_am_lock_ll : 1; /* CL91_USER_TX_ln9_status_t[08] - RO */ 8527 uint32_t ln9_am_lock_lh : 1; /* CL91_USER_TX_ln9_status_t[09] - RO */ 8528 uint32_t ln9_am_lock : 1; /* CL91_USER_TX_ln9_status_t[10] - RO */ 8529 uint32_t ln9_block_lock_ll : 1; /* CL91_USER_TX_ln9_status_t[11] - RO */ 8530 uint32_t ln9_block_lock_lh : 1; /* CL91_USER_TX_ln9_status_t[12] - RO */ 8531 uint32_t ln9_block_lock : 1; /* CL91_USER_TX_ln9_status_t[13] - RO */ 8532 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln9_status_t[15:14] - RSVD */ 8533 uint32_t reserved : 16; 8534 #endif /* IS_LITTLE_ENDIAN */ 8535 } fields; 8536 } CL91_USER_TX_ln9_status_t; 8537 8538 typedef CL91_USER_TX_ln9_status_t CL91_USER_TX_LN9_STATUS_t; 8539 8540 typedef union { 8541 uint32_t data; 8542 struct { 8543 #if IS_BIG_ENDIAN 8544 uint32_t reserved : 16; 8545 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln10_status_t[15:14] - RSVD */ 8546 uint32_t ln10_block_lock : 1; /* CL91_USER_TX_ln10_status_t[13] - RO */ 8547 uint32_t ln10_block_lock_lh : 1; /* CL91_USER_TX_ln10_status_t[12] - RO */ 8548 uint32_t ln10_block_lock_ll : 1; /* CL91_USER_TX_ln10_status_t[11] - RO */ 8549 uint32_t ln10_am_lock : 1; /* CL91_USER_TX_ln10_status_t[10] - RO */ 8550 uint32_t ln10_am_lock_lh : 1; /* CL91_USER_TX_ln10_status_t[09] - RO */ 8551 uint32_t ln10_am_lock_ll : 1; /* CL91_USER_TX_ln10_status_t[08] - RO */ 8552 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln10_status_t[07:05] - RSVD */ 8553 uint32_t ln10_pcsl_lane_number : 5; /* CL91_USER_TX_ln10_status_t[04:00] - RO */ 8554 #endif /* IS_BIG_ENDIAN */ 8555 #if IS_LITTLE_ENDIAN 8556 uint32_t ln10_pcsl_lane_number : 5; /* CL91_USER_TX_ln10_status_t[04:00] - RO */ 8557 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln10_status_t[07:05] - RSVD */ 8558 uint32_t ln10_am_lock_ll : 1; /* CL91_USER_TX_ln10_status_t[08] - RO */ 8559 uint32_t ln10_am_lock_lh : 1; /* CL91_USER_TX_ln10_status_t[09] - RO */ 8560 uint32_t ln10_am_lock : 1; /* CL91_USER_TX_ln10_status_t[10] - RO */ 8561 uint32_t ln10_block_lock_ll : 1; /* CL91_USER_TX_ln10_status_t[11] - RO */ 8562 uint32_t ln10_block_lock_lh : 1; /* CL91_USER_TX_ln10_status_t[12] - RO */ 8563 uint32_t ln10_block_lock : 1; /* CL91_USER_TX_ln10_status_t[13] - RO */ 8564 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln10_status_t[15:14] - RSVD */ 8565 uint32_t reserved : 16; 8566 #endif /* IS_LITTLE_ENDIAN */ 8567 } fields; 8568 } CL91_USER_TX_ln10_status_t; 8569 8570 typedef CL91_USER_TX_ln10_status_t CL91_USER_TX_LN10_STATUS_t; 8571 8572 typedef union { 8573 uint32_t data; 8574 struct { 8575 #if IS_BIG_ENDIAN 8576 uint32_t reserved : 16; 8577 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln11_status_t[15:14] - RSVD */ 8578 uint32_t ln11_block_lock : 1; /* CL91_USER_TX_ln11_status_t[13] - RO */ 8579 uint32_t ln11_block_lock_lh : 1; /* CL91_USER_TX_ln11_status_t[12] - RO */ 8580 uint32_t ln11_block_lock_ll : 1; /* CL91_USER_TX_ln11_status_t[11] - RO */ 8581 uint32_t ln11_am_lock : 1; /* CL91_USER_TX_ln11_status_t[10] - RO */ 8582 uint32_t ln11_am_lock_lh : 1; /* CL91_USER_TX_ln11_status_t[09] - RO */ 8583 uint32_t ln11_am_lock_ll : 1; /* CL91_USER_TX_ln11_status_t[08] - RO */ 8584 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln11_status_t[07:05] - RSVD */ 8585 uint32_t ln11_pcsl_lane_number : 5; /* CL91_USER_TX_ln11_status_t[04:00] - RO */ 8586 #endif /* IS_BIG_ENDIAN */ 8587 #if IS_LITTLE_ENDIAN 8588 uint32_t ln11_pcsl_lane_number : 5; /* CL91_USER_TX_ln11_status_t[04:00] - RO */ 8589 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln11_status_t[07:05] - RSVD */ 8590 uint32_t ln11_am_lock_ll : 1; /* CL91_USER_TX_ln11_status_t[08] - RO */ 8591 uint32_t ln11_am_lock_lh : 1; /* CL91_USER_TX_ln11_status_t[09] - RO */ 8592 uint32_t ln11_am_lock : 1; /* CL91_USER_TX_ln11_status_t[10] - RO */ 8593 uint32_t ln11_block_lock_ll : 1; /* CL91_USER_TX_ln11_status_t[11] - RO */ 8594 uint32_t ln11_block_lock_lh : 1; /* CL91_USER_TX_ln11_status_t[12] - RO */ 8595 uint32_t ln11_block_lock : 1; /* CL91_USER_TX_ln11_status_t[13] - RO */ 8596 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln11_status_t[15:14] - RSVD */ 8597 uint32_t reserved : 16; 8598 #endif /* IS_LITTLE_ENDIAN */ 8599 } fields; 8600 } CL91_USER_TX_ln11_status_t; 8601 8602 typedef CL91_USER_TX_ln11_status_t CL91_USER_TX_LN11_STATUS_t; 8603 8604 typedef union { 8605 uint32_t data; 8606 struct { 8607 #if IS_BIG_ENDIAN 8608 uint32_t reserved : 16; 8609 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln12_status_t[15:14] - RSVD */ 8610 uint32_t ln12_block_lock : 1; /* CL91_USER_TX_ln12_status_t[13] - RO */ 8611 uint32_t ln12_block_lock_lh : 1; /* CL91_USER_TX_ln12_status_t[12] - RO */ 8612 uint32_t ln12_block_lock_ll : 1; /* CL91_USER_TX_ln12_status_t[11] - RO */ 8613 uint32_t ln12_am_lock : 1; /* CL91_USER_TX_ln12_status_t[10] - RO */ 8614 uint32_t ln12_am_lock_lh : 1; /* CL91_USER_TX_ln12_status_t[09] - RO */ 8615 uint32_t ln12_am_lock_ll : 1; /* CL91_USER_TX_ln12_status_t[08] - RO */ 8616 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln12_status_t[07:05] - RSVD */ 8617 uint32_t ln12_pcsl_lane_number : 5; /* CL91_USER_TX_ln12_status_t[04:00] - RO */ 8618 #endif /* IS_BIG_ENDIAN */ 8619 #if IS_LITTLE_ENDIAN 8620 uint32_t ln12_pcsl_lane_number : 5; /* CL91_USER_TX_ln12_status_t[04:00] - RO */ 8621 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln12_status_t[07:05] - RSVD */ 8622 uint32_t ln12_am_lock_ll : 1; /* CL91_USER_TX_ln12_status_t[08] - RO */ 8623 uint32_t ln12_am_lock_lh : 1; /* CL91_USER_TX_ln12_status_t[09] - RO */ 8624 uint32_t ln12_am_lock : 1; /* CL91_USER_TX_ln12_status_t[10] - RO */ 8625 uint32_t ln12_block_lock_ll : 1; /* CL91_USER_TX_ln12_status_t[11] - RO */ 8626 uint32_t ln12_block_lock_lh : 1; /* CL91_USER_TX_ln12_status_t[12] - RO */ 8627 uint32_t ln12_block_lock : 1; /* CL91_USER_TX_ln12_status_t[13] - RO */ 8628 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln12_status_t[15:14] - RSVD */ 8629 uint32_t reserved : 16; 8630 #endif /* IS_LITTLE_ENDIAN */ 8631 } fields; 8632 } CL91_USER_TX_ln12_status_t; 8633 8634 typedef CL91_USER_TX_ln12_status_t CL91_USER_TX_LN12_STATUS_t; 8635 8636 typedef union { 8637 uint32_t data; 8638 struct { 8639 #if IS_BIG_ENDIAN 8640 uint32_t reserved : 16; 8641 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln13_status_t[15:14] - RSVD */ 8642 uint32_t ln13_block_lock : 1; /* CL91_USER_TX_ln13_status_t[13] - RO */ 8643 uint32_t ln13_block_lock_lh : 1; /* CL91_USER_TX_ln13_status_t[12] - RO */ 8644 uint32_t ln13_block_lock_ll : 1; /* CL91_USER_TX_ln13_status_t[11] - RO */ 8645 uint32_t ln13_am_lock : 1; /* CL91_USER_TX_ln13_status_t[10] - RO */ 8646 uint32_t ln13_am_lock_lh : 1; /* CL91_USER_TX_ln13_status_t[09] - RO */ 8647 uint32_t ln13_am_lock_ll : 1; /* CL91_USER_TX_ln13_status_t[08] - RO */ 8648 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln13_status_t[07:05] - RSVD */ 8649 uint32_t ln13_pcsl_lane_number : 5; /* CL91_USER_TX_ln13_status_t[04:00] - RO */ 8650 #endif /* IS_BIG_ENDIAN */ 8651 #if IS_LITTLE_ENDIAN 8652 uint32_t ln13_pcsl_lane_number : 5; /* CL91_USER_TX_ln13_status_t[04:00] - RO */ 8653 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln13_status_t[07:05] - RSVD */ 8654 uint32_t ln13_am_lock_ll : 1; /* CL91_USER_TX_ln13_status_t[08] - RO */ 8655 uint32_t ln13_am_lock_lh : 1; /* CL91_USER_TX_ln13_status_t[09] - RO */ 8656 uint32_t ln13_am_lock : 1; /* CL91_USER_TX_ln13_status_t[10] - RO */ 8657 uint32_t ln13_block_lock_ll : 1; /* CL91_USER_TX_ln13_status_t[11] - RO */ 8658 uint32_t ln13_block_lock_lh : 1; /* CL91_USER_TX_ln13_status_t[12] - RO */ 8659 uint32_t ln13_block_lock : 1; /* CL91_USER_TX_ln13_status_t[13] - RO */ 8660 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln13_status_t[15:14] - RSVD */ 8661 uint32_t reserved : 16; 8662 #endif /* IS_LITTLE_ENDIAN */ 8663 } fields; 8664 } CL91_USER_TX_ln13_status_t; 8665 8666 typedef CL91_USER_TX_ln13_status_t CL91_USER_TX_LN13_STATUS_t; 8667 8668 typedef union { 8669 uint32_t data; 8670 struct { 8671 #if IS_BIG_ENDIAN 8672 uint32_t reserved : 16; 8673 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln14_status_t[15:14] - RSVD */ 8674 uint32_t ln14_block_lock : 1; /* CL91_USER_TX_ln14_status_t[13] - RO */ 8675 uint32_t ln14_block_lock_lh : 1; /* CL91_USER_TX_ln14_status_t[12] - RO */ 8676 uint32_t ln14_block_lock_ll : 1; /* CL91_USER_TX_ln14_status_t[11] - RO */ 8677 uint32_t ln14_am_lock : 1; /* CL91_USER_TX_ln14_status_t[10] - RO */ 8678 uint32_t ln14_am_lock_lh : 1; /* CL91_USER_TX_ln14_status_t[09] - RO */ 8679 uint32_t ln14_am_lock_ll : 1; /* CL91_USER_TX_ln14_status_t[08] - RO */ 8680 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln14_status_t[07:05] - RSVD */ 8681 uint32_t ln14_pcsl_lane_number : 5; /* CL91_USER_TX_ln14_status_t[04:00] - RO */ 8682 #endif /* IS_BIG_ENDIAN */ 8683 #if IS_LITTLE_ENDIAN 8684 uint32_t ln14_pcsl_lane_number : 5; /* CL91_USER_TX_ln14_status_t[04:00] - RO */ 8685 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln14_status_t[07:05] - RSVD */ 8686 uint32_t ln14_am_lock_ll : 1; /* CL91_USER_TX_ln14_status_t[08] - RO */ 8687 uint32_t ln14_am_lock_lh : 1; /* CL91_USER_TX_ln14_status_t[09] - RO */ 8688 uint32_t ln14_am_lock : 1; /* CL91_USER_TX_ln14_status_t[10] - RO */ 8689 uint32_t ln14_block_lock_ll : 1; /* CL91_USER_TX_ln14_status_t[11] - RO */ 8690 uint32_t ln14_block_lock_lh : 1; /* CL91_USER_TX_ln14_status_t[12] - RO */ 8691 uint32_t ln14_block_lock : 1; /* CL91_USER_TX_ln14_status_t[13] - RO */ 8692 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln14_status_t[15:14] - RSVD */ 8693 uint32_t reserved : 16; 8694 #endif /* IS_LITTLE_ENDIAN */ 8695 } fields; 8696 } CL91_USER_TX_ln14_status_t; 8697 8698 typedef CL91_USER_TX_ln14_status_t CL91_USER_TX_LN14_STATUS_t; 8699 8700 typedef union { 8701 uint32_t data; 8702 struct { 8703 #if IS_BIG_ENDIAN 8704 uint32_t reserved : 16; 8705 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln15_status_t[15:14] - RSVD */ 8706 uint32_t ln15_block_lock : 1; /* CL91_USER_TX_ln15_status_t[13] - RO */ 8707 uint32_t ln15_block_lock_lh : 1; /* CL91_USER_TX_ln15_status_t[12] - RO */ 8708 uint32_t ln15_block_lock_ll : 1; /* CL91_USER_TX_ln15_status_t[11] - RO */ 8709 uint32_t ln15_am_lock : 1; /* CL91_USER_TX_ln15_status_t[10] - RO */ 8710 uint32_t ln15_am_lock_lh : 1; /* CL91_USER_TX_ln15_status_t[09] - RO */ 8711 uint32_t ln15_am_lock_ll : 1; /* CL91_USER_TX_ln15_status_t[08] - RO */ 8712 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln15_status_t[07:05] - RSVD */ 8713 uint32_t ln15_pcsl_lane_number : 5; /* CL91_USER_TX_ln15_status_t[04:00] - RO */ 8714 #endif /* IS_BIG_ENDIAN */ 8715 #if IS_LITTLE_ENDIAN 8716 uint32_t ln15_pcsl_lane_number : 5; /* CL91_USER_TX_ln15_status_t[04:00] - RO */ 8717 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln15_status_t[07:05] - RSVD */ 8718 uint32_t ln15_am_lock_ll : 1; /* CL91_USER_TX_ln15_status_t[08] - RO */ 8719 uint32_t ln15_am_lock_lh : 1; /* CL91_USER_TX_ln15_status_t[09] - RO */ 8720 uint32_t ln15_am_lock : 1; /* CL91_USER_TX_ln15_status_t[10] - RO */ 8721 uint32_t ln15_block_lock_ll : 1; /* CL91_USER_TX_ln15_status_t[11] - RO */ 8722 uint32_t ln15_block_lock_lh : 1; /* CL91_USER_TX_ln15_status_t[12] - RO */ 8723 uint32_t ln15_block_lock : 1; /* CL91_USER_TX_ln15_status_t[13] - RO */ 8724 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln15_status_t[15:14] - RSVD */ 8725 uint32_t reserved : 16; 8726 #endif /* IS_LITTLE_ENDIAN */ 8727 } fields; 8728 } CL91_USER_TX_ln15_status_t; 8729 8730 typedef CL91_USER_TX_ln15_status_t CL91_USER_TX_LN15_STATUS_t; 8731 8732 typedef union { 8733 uint32_t data; 8734 struct { 8735 #if IS_BIG_ENDIAN 8736 uint32_t reserved : 16; 8737 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln16_status_t[15:14] - RSVD */ 8738 uint32_t ln16_block_lock : 1; /* CL91_USER_TX_ln16_status_t[13] - RO */ 8739 uint32_t ln16_block_lock_lh : 1; /* CL91_USER_TX_ln16_status_t[12] - RO */ 8740 uint32_t ln16_block_lock_ll : 1; /* CL91_USER_TX_ln16_status_t[11] - RO */ 8741 uint32_t ln16_am_lock : 1; /* CL91_USER_TX_ln16_status_t[10] - RO */ 8742 uint32_t ln16_am_lock_lh : 1; /* CL91_USER_TX_ln16_status_t[09] - RO */ 8743 uint32_t ln16_am_lock_ll : 1; /* CL91_USER_TX_ln16_status_t[08] - RO */ 8744 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln16_status_t[07:05] - RSVD */ 8745 uint32_t ln16_pcsl_lane_number : 5; /* CL91_USER_TX_ln16_status_t[04:00] - RO */ 8746 #endif /* IS_BIG_ENDIAN */ 8747 #if IS_LITTLE_ENDIAN 8748 uint32_t ln16_pcsl_lane_number : 5; /* CL91_USER_TX_ln16_status_t[04:00] - RO */ 8749 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln16_status_t[07:05] - RSVD */ 8750 uint32_t ln16_am_lock_ll : 1; /* CL91_USER_TX_ln16_status_t[08] - RO */ 8751 uint32_t ln16_am_lock_lh : 1; /* CL91_USER_TX_ln16_status_t[09] - RO */ 8752 uint32_t ln16_am_lock : 1; /* CL91_USER_TX_ln16_status_t[10] - RO */ 8753 uint32_t ln16_block_lock_ll : 1; /* CL91_USER_TX_ln16_status_t[11] - RO */ 8754 uint32_t ln16_block_lock_lh : 1; /* CL91_USER_TX_ln16_status_t[12] - RO */ 8755 uint32_t ln16_block_lock : 1; /* CL91_USER_TX_ln16_status_t[13] - RO */ 8756 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln16_status_t[15:14] - RSVD */ 8757 uint32_t reserved : 16; 8758 #endif /* IS_LITTLE_ENDIAN */ 8759 } fields; 8760 } CL91_USER_TX_ln16_status_t; 8761 8762 typedef CL91_USER_TX_ln16_status_t CL91_USER_TX_LN16_STATUS_t; 8763 8764 typedef union { 8765 uint32_t data; 8766 struct { 8767 #if IS_BIG_ENDIAN 8768 uint32_t reserved : 16; 8769 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln17_status_t[15:14] - RSVD */ 8770 uint32_t ln17_block_lock : 1; /* CL91_USER_TX_ln17_status_t[13] - RO */ 8771 uint32_t ln17_block_lock_lh : 1; /* CL91_USER_TX_ln17_status_t[12] - RO */ 8772 uint32_t ln17_block_lock_ll : 1; /* CL91_USER_TX_ln17_status_t[11] - RO */ 8773 uint32_t ln17_am_lock : 1; /* CL91_USER_TX_ln17_status_t[10] - RO */ 8774 uint32_t ln17_am_lock_lh : 1; /* CL91_USER_TX_ln17_status_t[09] - RO */ 8775 uint32_t ln17_am_lock_ll : 1; /* CL91_USER_TX_ln17_status_t[08] - RO */ 8776 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln17_status_t[07:05] - RSVD */ 8777 uint32_t ln17_pcsl_lane_number : 5; /* CL91_USER_TX_ln17_status_t[04:00] - RO */ 8778 #endif /* IS_BIG_ENDIAN */ 8779 #if IS_LITTLE_ENDIAN 8780 uint32_t ln17_pcsl_lane_number : 5; /* CL91_USER_TX_ln17_status_t[04:00] - RO */ 8781 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln17_status_t[07:05] - RSVD */ 8782 uint32_t ln17_am_lock_ll : 1; /* CL91_USER_TX_ln17_status_t[08] - RO */ 8783 uint32_t ln17_am_lock_lh : 1; /* CL91_USER_TX_ln17_status_t[09] - RO */ 8784 uint32_t ln17_am_lock : 1; /* CL91_USER_TX_ln17_status_t[10] - RO */ 8785 uint32_t ln17_block_lock_ll : 1; /* CL91_USER_TX_ln17_status_t[11] - RO */ 8786 uint32_t ln17_block_lock_lh : 1; /* CL91_USER_TX_ln17_status_t[12] - RO */ 8787 uint32_t ln17_block_lock : 1; /* CL91_USER_TX_ln17_status_t[13] - RO */ 8788 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln17_status_t[15:14] - RSVD */ 8789 uint32_t reserved : 16; 8790 #endif /* IS_LITTLE_ENDIAN */ 8791 } fields; 8792 } CL91_USER_TX_ln17_status_t; 8793 8794 typedef CL91_USER_TX_ln17_status_t CL91_USER_TX_LN17_STATUS_t; 8795 8796 typedef union { 8797 uint32_t data; 8798 struct { 8799 #if IS_BIG_ENDIAN 8800 uint32_t reserved : 16; 8801 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln18_status_t[15:14] - RSVD */ 8802 uint32_t ln18_block_lock : 1; /* CL91_USER_TX_ln18_status_t[13] - RO */ 8803 uint32_t ln18_block_lock_lh : 1; /* CL91_USER_TX_ln18_status_t[12] - RO */ 8804 uint32_t ln18_block_lock_ll : 1; /* CL91_USER_TX_ln18_status_t[11] - RO */ 8805 uint32_t ln18_am_lock : 1; /* CL91_USER_TX_ln18_status_t[10] - RO */ 8806 uint32_t ln18_am_lock_lh : 1; /* CL91_USER_TX_ln18_status_t[09] - RO */ 8807 uint32_t ln18_am_lock_ll : 1; /* CL91_USER_TX_ln18_status_t[08] - RO */ 8808 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln18_status_t[07:05] - RSVD */ 8809 uint32_t ln18_pcsl_lane_number : 5; /* CL91_USER_TX_ln18_status_t[04:00] - RO */ 8810 #endif /* IS_BIG_ENDIAN */ 8811 #if IS_LITTLE_ENDIAN 8812 uint32_t ln18_pcsl_lane_number : 5; /* CL91_USER_TX_ln18_status_t[04:00] - RO */ 8813 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln18_status_t[07:05] - RSVD */ 8814 uint32_t ln18_am_lock_ll : 1; /* CL91_USER_TX_ln18_status_t[08] - RO */ 8815 uint32_t ln18_am_lock_lh : 1; /* CL91_USER_TX_ln18_status_t[09] - RO */ 8816 uint32_t ln18_am_lock : 1; /* CL91_USER_TX_ln18_status_t[10] - RO */ 8817 uint32_t ln18_block_lock_ll : 1; /* CL91_USER_TX_ln18_status_t[11] - RO */ 8818 uint32_t ln18_block_lock_lh : 1; /* CL91_USER_TX_ln18_status_t[12] - RO */ 8819 uint32_t ln18_block_lock : 1; /* CL91_USER_TX_ln18_status_t[13] - RO */ 8820 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln18_status_t[15:14] - RSVD */ 8821 uint32_t reserved : 16; 8822 #endif /* IS_LITTLE_ENDIAN */ 8823 } fields; 8824 } CL91_USER_TX_ln18_status_t; 8825 8826 typedef CL91_USER_TX_ln18_status_t CL91_USER_TX_LN18_STATUS_t; 8827 8828 typedef union { 8829 uint32_t data; 8830 struct { 8831 #if IS_BIG_ENDIAN 8832 uint32_t reserved : 16; 8833 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln19_status_t[15:14] - RSVD */ 8834 uint32_t ln19_block_lock : 1; /* CL91_USER_TX_ln19_status_t[13] - RO */ 8835 uint32_t ln19_block_lock_lh : 1; /* CL91_USER_TX_ln19_status_t[12] - RO */ 8836 uint32_t ln19_block_lock_ll : 1; /* CL91_USER_TX_ln19_status_t[11] - RO */ 8837 uint32_t ln19_am_lock : 1; /* CL91_USER_TX_ln19_status_t[10] - RO */ 8838 uint32_t ln19_am_lock_lh : 1; /* CL91_USER_TX_ln19_status_t[09] - RO */ 8839 uint32_t ln19_am_lock_ll : 1; /* CL91_USER_TX_ln19_status_t[08] - RO */ 8840 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln19_status_t[07:05] - RSVD */ 8841 uint32_t ln19_pcsl_lane_number : 5; /* CL91_USER_TX_ln19_status_t[04:00] - RO */ 8842 #endif /* IS_BIG_ENDIAN */ 8843 #if IS_LITTLE_ENDIAN 8844 uint32_t ln19_pcsl_lane_number : 5; /* CL91_USER_TX_ln19_status_t[04:00] - RO */ 8845 uint32_t reserved_for_eco_05 : 3; /* CL91_USER_TX_ln19_status_t[07:05] - RSVD */ 8846 uint32_t ln19_am_lock_ll : 1; /* CL91_USER_TX_ln19_status_t[08] - RO */ 8847 uint32_t ln19_am_lock_lh : 1; /* CL91_USER_TX_ln19_status_t[09] - RO */ 8848 uint32_t ln19_am_lock : 1; /* CL91_USER_TX_ln19_status_t[10] - RO */ 8849 uint32_t ln19_block_lock_ll : 1; /* CL91_USER_TX_ln19_status_t[11] - RO */ 8850 uint32_t ln19_block_lock_lh : 1; /* CL91_USER_TX_ln19_status_t[12] - RO */ 8851 uint32_t ln19_block_lock : 1; /* CL91_USER_TX_ln19_status_t[13] - RO */ 8852 uint32_t reserved_for_eco_14 : 2; /* CL91_USER_TX_ln19_status_t[15:14] - RSVD */ 8853 uint32_t reserved : 16; 8854 #endif /* IS_LITTLE_ENDIAN */ 8855 } fields; 8856 } CL91_USER_TX_ln19_status_t; 8857 8858 typedef CL91_USER_TX_ln19_status_t CL91_USER_TX_LN19_STATUS_t; 8859 8860 8861 /*-----------------------------------------------*/ 8862 /* Structs for XGXS_BLK0 Bank */ 8863 /*-----------------------------------------------*/ 8864 typedef union { 8865 uint32_t data; 8866 struct { 8867 #if IS_BIG_ENDIAN 8868 uint32_t reserved : 16; 8869 uint32_t reserved_14 : 2; /* XGXS_BLK0_xgxsControl_t[15:14] - RSVD */ 8870 uint32_t start_sequencer : 1; /* XGXS_BLK0_xgxsControl_t[13] - WO */ 8871 uint32_t reserved_12 : 1; /* XGXS_BLK0_xgxsControl_t[12] - RSVD */ 8872 uint32_t reserved_08 : 4; /* XGXS_BLK0_xgxsControl_t[11:08] - RSVD */ 8873 uint32_t reserved_00 : 8; /* XGXS_BLK0_xgxsControl_t[07:00] - RSVD */ 8874 #endif /* IS_BIG_ENDIAN */ 8875 #if IS_LITTLE_ENDIAN 8876 uint32_t reserved_00 : 8; /* XGXS_BLK0_xgxsControl_t[07:00] - RSVD */ 8877 uint32_t reserved_08 : 4; /* XGXS_BLK0_xgxsControl_t[11:08] - RSVD */ 8878 uint32_t reserved_12 : 1; /* XGXS_BLK0_xgxsControl_t[12] - RSVD */ 8879 uint32_t start_sequencer : 1; /* XGXS_BLK0_xgxsControl_t[13] - WO */ 8880 uint32_t reserved_14 : 2; /* XGXS_BLK0_xgxsControl_t[15:14] - RSVD */ 8881 uint32_t reserved : 16; 8882 #endif /* IS_LITTLE_ENDIAN */ 8883 } fields; 8884 } XGXS_BLK0_xgxsControl_t; 8885 8886 typedef XGXS_BLK0_xgxsControl_t XGXS_BLK0_XGXSCONTROL_t; 8887 8888 typedef union { 8889 uint32_t data; 8890 struct { 8891 #if IS_BIG_ENDIAN 8892 uint32_t reserved : 16; 8893 uint32_t reserved_15 : 1; /* XGXS_BLK0_xgxsStatus_t[15] - RSVD */ 8894 uint32_t reserved_12 : 3; /* XGXS_BLK0_xgxsStatus_t[14:12] - RSVD */ 8895 uint32_t txpll_lock : 1; /* XGXS_BLK0_xgxsStatus_t[11] - RO */ 8896 uint32_t reserved_00 : 11; /* XGXS_BLK0_xgxsStatus_t[10:00] - RSVD */ 8897 #endif /* IS_BIG_ENDIAN */ 8898 #if IS_LITTLE_ENDIAN 8899 uint32_t reserved_00 : 11; /* XGXS_BLK0_xgxsStatus_t[10:00] - RSVD */ 8900 uint32_t txpll_lock : 1; /* XGXS_BLK0_xgxsStatus_t[11] - RO */ 8901 uint32_t reserved_12 : 3; /* XGXS_BLK0_xgxsStatus_t[14:12] - RSVD */ 8902 uint32_t reserved_15 : 1; /* XGXS_BLK0_xgxsStatus_t[15] - RSVD */ 8903 uint32_t reserved : 16; 8904 #endif /* IS_LITTLE_ENDIAN */ 8905 } fields; 8906 } XGXS_BLK0_xgxsStatus_t; 8907 8908 typedef XGXS_BLK0_xgxsStatus_t XGXS_BLK0_XGXSSTATUS_t; 8909 8910 typedef union { 8911 uint32_t data; 8912 struct { 8913 #if IS_BIG_ENDIAN 8914 uint32_t reserved : 16; 8915 uint32_t pmd_lane0_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[15] - WO */ 8916 uint32_t pmd_lane1_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[14] - WO */ 8917 uint32_t pmd_lane2_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[13] - WO */ 8918 uint32_t pmd_lane3_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[12] - WO */ 8919 uint32_t global_pmd_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[11] - WO */ 8920 uint32_t reserved_08 : 3; /* XGXS_BLK0_miscControl1_t[10:08] - RSVD */ 8921 uint32_t reserved_05 : 3; /* XGXS_BLK0_miscControl1_t[07:05] - RSVD */ 8922 uint32_t reserved_04 : 1; /* XGXS_BLK0_miscControl1_t[04] - RSVD */ 8923 uint32_t reserved_02 : 2; /* XGXS_BLK0_miscControl1_t[03:02] - RSVD */ 8924 uint32_t reserved_01 : 1; /* XGXS_BLK0_miscControl1_t[01] - RSVD */ 8925 uint32_t reserved_00 : 1; /* XGXS_BLK0_miscControl1_t[00] - RSVD */ 8926 #endif /* IS_BIG_ENDIAN */ 8927 #if IS_LITTLE_ENDIAN 8928 uint32_t reserved_00 : 1; /* XGXS_BLK0_miscControl1_t[00] - RSVD */ 8929 uint32_t reserved_01 : 1; /* XGXS_BLK0_miscControl1_t[01] - RSVD */ 8930 uint32_t reserved_02 : 2; /* XGXS_BLK0_miscControl1_t[03:02] - RSVD */ 8931 uint32_t reserved_04 : 1; /* XGXS_BLK0_miscControl1_t[04] - RSVD */ 8932 uint32_t reserved_05 : 3; /* XGXS_BLK0_miscControl1_t[07:05] - RSVD */ 8933 uint32_t reserved_08 : 3; /* XGXS_BLK0_miscControl1_t[10:08] - RSVD */ 8934 uint32_t global_pmd_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[11] - WO */ 8935 uint32_t pmd_lane3_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[12] - WO */ 8936 uint32_t pmd_lane2_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[13] - WO */ 8937 uint32_t pmd_lane1_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[14] - WO */ 8938 uint32_t pmd_lane0_tx_disable : 1; /* XGXS_BLK0_miscControl1_t[15] - WO */ 8939 uint32_t reserved : 16; 8940 #endif /* IS_LITTLE_ENDIAN */ 8941 } fields; 8942 } XGXS_BLK0_miscControl1_t; 8943 8944 typedef XGXS_BLK0_miscControl1_t XGXS_BLK0_MISCCONTROL1_t; 8945 8946 8947 /*-----------------------------------------------*/ 8948 /* Structs for TX_ANA_REGS Bank */ 8949 /*-----------------------------------------------*/ 8950 typedef union { 8951 uint32_t data; 8952 struct { 8953 #if IS_BIG_ENDIAN 8954 uint32_t reserved : 16; 8955 uint32_t reserved_08 : 8; /* TX_ANA_REGS_anaTxAStatus_t[15:08] - RSVD */ 8956 uint32_t reserved_05 : 3; /* TX_ANA_REGS_anaTxAStatus_t[07:05] - RSVD */ 8957 uint32_t reserved_04 : 1; /* TX_ANA_REGS_anaTxAStatus_t[04] - RSVD */ 8958 uint32_t pmd_ln_dp_tx_rst : 1; /* TX_ANA_REGS_anaTxAStatus_t[03] - RO */ 8959 uint32_t reserved_02 : 1; /* TX_ANA_REGS_anaTxAStatus_t[02] - RSVD */ 8960 uint32_t reserved_01 : 1; /* TX_ANA_REGS_anaTxAStatus_t[01] - RSVD */ 8961 uint32_t reserved_00 : 1; /* TX_ANA_REGS_anaTxAStatus_t[00] - RSVD */ 8962 #endif /* IS_BIG_ENDIAN */ 8963 #if IS_LITTLE_ENDIAN 8964 uint32_t reserved_00 : 1; /* TX_ANA_REGS_anaTxAStatus_t[00] - RSVD */ 8965 uint32_t reserved_01 : 1; /* TX_ANA_REGS_anaTxAStatus_t[01] - RSVD */ 8966 uint32_t reserved_02 : 1; /* TX_ANA_REGS_anaTxAStatus_t[02] - RSVD */ 8967 uint32_t pmd_ln_dp_tx_rst : 1; /* TX_ANA_REGS_anaTxAStatus_t[03] - RO */ 8968 uint32_t reserved_04 : 1; /* TX_ANA_REGS_anaTxAStatus_t[04] - RSVD */ 8969 uint32_t reserved_05 : 3; /* TX_ANA_REGS_anaTxAStatus_t[07:05] - RSVD */ 8970 uint32_t reserved_08 : 8; /* TX_ANA_REGS_anaTxAStatus_t[15:08] - RSVD */ 8971 uint32_t reserved : 16; 8972 #endif /* IS_LITTLE_ENDIAN */ 8973 } fields; 8974 } TX_ANA_REGS_anaTxAStatus_t; 8975 8976 typedef TX_ANA_REGS_anaTxAStatus_t TX_ANA_REGS_ANATXASTATUS_t; 8977 8978 typedef union { 8979 uint32_t data; 8980 struct { 8981 #if IS_BIG_ENDIAN 8982 uint32_t reserved : 16; 8983 uint32_t reserved_14 : 2; /* TX_ANA_REGS_anaTxAControl0_t[15:14] - RSVD */ 8984 uint32_t reserved_13 : 1; /* TX_ANA_REGS_anaTxAControl0_t[13] - RSVD */ 8985 uint32_t reserved_12 : 1; /* TX_ANA_REGS_anaTxAControl0_t[12] - RSVD */ 8986 uint32_t reserved_11 : 1; /* TX_ANA_REGS_anaTxAControl0_t[11] - RSVD */ 8987 uint32_t txck_dme_en_sm : 1; /* TX_ANA_REGS_anaTxAControl0_t[10] - WO */ 8988 uint32_t reserved_08 : 2; /* TX_ANA_REGS_anaTxAControl0_t[09:08] - RSVD */ 8989 uint32_t reserved_07 : 1; /* TX_ANA_REGS_anaTxAControl0_t[07] - RSVD */ 8990 uint32_t reserved_04 : 3; /* TX_ANA_REGS_anaTxAControl0_t[06:04] - RSVD */ 8991 uint32_t reserved_00 : 4; /* TX_ANA_REGS_anaTxAControl0_t[03:00] - RSVD */ 8992 #endif /* IS_BIG_ENDIAN */ 8993 #if IS_LITTLE_ENDIAN 8994 uint32_t reserved_00 : 4; /* TX_ANA_REGS_anaTxAControl0_t[03:00] - RSVD */ 8995 uint32_t reserved_04 : 3; /* TX_ANA_REGS_anaTxAControl0_t[06:04] - RSVD */ 8996 uint32_t reserved_07 : 1; /* TX_ANA_REGS_anaTxAControl0_t[07] - RSVD */ 8997 uint32_t reserved_08 : 2; /* TX_ANA_REGS_anaTxAControl0_t[09:08] - RSVD */ 8998 uint32_t txck_dme_en_sm : 1; /* TX_ANA_REGS_anaTxAControl0_t[10] - WO */ 8999 uint32_t reserved_11 : 1; /* TX_ANA_REGS_anaTxAControl0_t[11] - RSVD */ 9000 uint32_t reserved_12 : 1; /* TX_ANA_REGS_anaTxAControl0_t[12] - RSVD */ 9001 uint32_t reserved_13 : 1; /* TX_ANA_REGS_anaTxAControl0_t[13] - RSVD */ 9002 uint32_t reserved_14 : 2; /* TX_ANA_REGS_anaTxAControl0_t[15:14] - RSVD */ 9003 uint32_t reserved : 16; 9004 #endif /* IS_LITTLE_ENDIAN */ 9005 } fields; 9006 } TX_ANA_REGS_anaTxAControl0_t; 9007 9008 typedef TX_ANA_REGS_anaTxAControl0_t TX_ANA_REGS_ANATXACONTROL0_t; 9009 9010 typedef union { 9011 uint32_t data; 9012 struct { 9013 #if IS_BIG_ENDIAN 9014 uint32_t reserved : 16; 9015 uint32_t reserved_12 : 4; /* TX_ANA_REGS_anaTxAControl7_t[15:12] - RSVD */ 9016 uint32_t reserved_11 : 1; /* TX_ANA_REGS_anaTxAControl7_t[11] - RSVD */ 9017 uint32_t pmd_ln_dp_tx_rst_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[10] - WO */ 9018 uint32_t pmd_ln_tx_h_pwrdn_val_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[09] - WO */ 9019 uint32_t pmd_ln_tx_h_pwrdn_enb_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[08] - WO */ 9020 uint32_t reserved_06 : 2; /* TX_ANA_REGS_anaTxAControl7_t[07:06] - RSVD */ 9021 uint32_t use_mgt_pmd_lock_4_tx_squelch_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[05] - WO */ 9022 uint32_t tx_disable_an_good_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[04] - WO */ 9023 uint32_t tx_disable_force_en_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[03] - WO */ 9024 uint32_t tx_disable_force_val_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[02] - WO */ 9025 uint32_t tx_squelch_force_en_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[01] - WO */ 9026 uint32_t tx_squelch_force_val_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[00] - WO */ 9027 #endif /* IS_BIG_ENDIAN */ 9028 #if IS_LITTLE_ENDIAN 9029 uint32_t tx_squelch_force_val_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[00] - WO */ 9030 uint32_t tx_squelch_force_en_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[01] - WO */ 9031 uint32_t tx_disable_force_val_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[02] - WO */ 9032 uint32_t tx_disable_force_en_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[03] - WO */ 9033 uint32_t tx_disable_an_good_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[04] - WO */ 9034 uint32_t use_mgt_pmd_lock_4_tx_squelch_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[05] - WO */ 9035 uint32_t reserved_06 : 2; /* TX_ANA_REGS_anaTxAControl7_t[07:06] - RSVD */ 9036 uint32_t pmd_ln_tx_h_pwrdn_enb_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[08] - WO */ 9037 uint32_t pmd_ln_tx_h_pwrdn_val_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[09] - WO */ 9038 uint32_t pmd_ln_dp_tx_rst_sm : 1; /* TX_ANA_REGS_anaTxAControl7_t[10] - WO */ 9039 uint32_t reserved_11 : 1; /* TX_ANA_REGS_anaTxAControl7_t[11] - RSVD */ 9040 uint32_t reserved_12 : 4; /* TX_ANA_REGS_anaTxAControl7_t[15:12] - RSVD */ 9041 uint32_t reserved : 16; 9042 #endif /* IS_LITTLE_ENDIAN */ 9043 } fields; 9044 } TX_ANA_REGS_anaTxAControl7_t; 9045 9046 typedef TX_ANA_REGS_anaTxAControl7_t TX_ANA_REGS_ANATXACONTROL7_t; 9047 9048 9049 /*-----------------------------------------------*/ 9050 /* Structs for RX_ANA_REGS Bank */ 9051 /*-----------------------------------------------*/ 9052 typedef union { 9053 uint32_t data; 9054 struct { 9055 #if IS_BIG_ENDIAN 9056 uint32_t reserved : 16; 9057 uint32_t rxstatus : 16; /* RX_ANA_REGS_anaRxStatus_t[15:00] - RO */ 9058 #endif /* IS_BIG_ENDIAN */ 9059 #if IS_LITTLE_ENDIAN 9060 uint32_t rxstatus : 16; /* RX_ANA_REGS_anaRxStatus_t[15:00] - RO */ 9061 uint32_t reserved : 16; 9062 #endif /* IS_LITTLE_ENDIAN */ 9063 } fields; 9064 } RX_ANA_REGS_anaRxStatus_t; 9065 9066 typedef RX_ANA_REGS_anaRxStatus_t RX_ANA_REGS_ANARXSTATUS_t; 9067 9068 typedef union { 9069 uint32_t data; 9070 struct { 9071 #if IS_BIG_ENDIAN 9072 uint32_t reserved : 16; 9073 uint32_t reserved_10 : 6; /* RX_ANA_REGS_anaRxControl_t[15:10] - RSVD */ 9074 uint32_t force_pmd_lock_sm : 1; /* RX_ANA_REGS_anaRxControl_t[09] - WO */ 9075 uint32_t force_pmd_lock_val_sm : 1; /* RX_ANA_REGS_anaRxControl_t[08] - WO */ 9076 uint32_t use_cl73_an_good_kr4_sm : 1; /* RX_ANA_REGS_anaRxControl_t[07] - WO */ 9077 uint32_t use_cl73_an_good_sm : 1; /* RX_ANA_REGS_anaRxControl_t[06] - WO */ 9078 uint32_t forcerxseqdone_en_sm : 1; /* RX_ANA_REGS_anaRxControl_t[05] - WO */ 9079 uint32_t forcerxseqdone_val_sm : 1; /* RX_ANA_REGS_anaRxControl_t[04] - WO */ 9080 uint32_t reserved_03 : 1; /* RX_ANA_REGS_anaRxControl_t[03] - RSVD */ 9081 uint32_t status_sel : 3; /* RX_ANA_REGS_anaRxControl_t[02:00] - WO */ 9082 #endif /* IS_BIG_ENDIAN */ 9083 #if IS_LITTLE_ENDIAN 9084 uint32_t status_sel : 3; /* RX_ANA_REGS_anaRxControl_t[02:00] - WO */ 9085 uint32_t reserved_03 : 1; /* RX_ANA_REGS_anaRxControl_t[03] - RSVD */ 9086 uint32_t forcerxseqdone_val_sm : 1; /* RX_ANA_REGS_anaRxControl_t[04] - WO */ 9087 uint32_t forcerxseqdone_en_sm : 1; /* RX_ANA_REGS_anaRxControl_t[05] - WO */ 9088 uint32_t use_cl73_an_good_sm : 1; /* RX_ANA_REGS_anaRxControl_t[06] - WO */ 9089 uint32_t use_cl73_an_good_kr4_sm : 1; /* RX_ANA_REGS_anaRxControl_t[07] - WO */ 9090 uint32_t force_pmd_lock_val_sm : 1; /* RX_ANA_REGS_anaRxControl_t[08] - WO */ 9091 uint32_t force_pmd_lock_sm : 1; /* RX_ANA_REGS_anaRxControl_t[09] - WO */ 9092 uint32_t reserved_10 : 6; /* RX_ANA_REGS_anaRxControl_t[15:10] - RSVD */ 9093 uint32_t reserved : 16; 9094 #endif /* IS_LITTLE_ENDIAN */ 9095 } fields; 9096 } RX_ANA_REGS_anaRxControl_t; 9097 9098 typedef RX_ANA_REGS_anaRxControl_t RX_ANA_REGS_ANARXCONTROL_t; 9099 9100 typedef union { 9101 uint32_t data; 9102 struct { 9103 #if IS_BIG_ENDIAN 9104 uint32_t reserved : 16; 9105 uint32_t reserved_05 : 11; /* RX_ANA_REGS_anaRxSigdet_t[15:05] - RSVD */ 9106 uint32_t rx_sigdet_r : 1; /* RX_ANA_REGS_anaRxSigdet_t[04] - WO */ 9107 uint32_t rx_sigdet_force_r : 1; /* RX_ANA_REGS_anaRxSigdet_t[03] - WO */ 9108 uint32_t reserved_00 : 3; /* RX_ANA_REGS_anaRxSigdet_t[02:00] - RSVD */ 9109 #endif /* IS_BIG_ENDIAN */ 9110 #if IS_LITTLE_ENDIAN 9111 uint32_t reserved_00 : 3; /* RX_ANA_REGS_anaRxSigdet_t[02:00] - RSVD */ 9112 uint32_t rx_sigdet_force_r : 1; /* RX_ANA_REGS_anaRxSigdet_t[03] - WO */ 9113 uint32_t rx_sigdet_r : 1; /* RX_ANA_REGS_anaRxSigdet_t[04] - WO */ 9114 uint32_t reserved_05 : 11; /* RX_ANA_REGS_anaRxSigdet_t[15:05] - RSVD */ 9115 uint32_t reserved : 16; 9116 #endif /* IS_LITTLE_ENDIAN */ 9117 } fields; 9118 } RX_ANA_REGS_anaRxSigdet_t; 9119 9120 typedef RX_ANA_REGS_anaRxSigdet_t RX_ANA_REGS_ANARXSIGDET_t; 9121 9122 typedef union { 9123 uint32_t data; 9124 struct { 9125 #if IS_BIG_ENDIAN 9126 uint32_t reserved : 16; 9127 uint32_t reserved_12 : 4; /* RX_ANA_REGS_anaRxControl2_t[15:12] - RSVD */ 9128 uint32_t reserved_11 : 1; /* RX_ANA_REGS_anaRxControl2_t[11] - RSVD */ 9129 uint32_t reserved_10 : 1; /* RX_ANA_REGS_anaRxControl2_t[10] - RSVD */ 9130 uint32_t pmd_ln_rx_h_pwrdn_val_sm : 1; /* RX_ANA_REGS_anaRxControl2_t[09] - WO */ 9131 uint32_t pmd_ln_dp_rx_rst_sm : 1; /* RX_ANA_REGS_anaRxControl2_t[08] - WO */ 9132 uint32_t reserved_02 : 6; /* RX_ANA_REGS_anaRxControl2_t[07:02] - RSVD */ 9133 uint32_t rxtm_tstsel_sm : 2; /* RX_ANA_REGS_anaRxControl2_t[01:00] - WO */ 9134 #endif /* IS_BIG_ENDIAN */ 9135 #if IS_LITTLE_ENDIAN 9136 uint32_t rxtm_tstsel_sm : 2; /* RX_ANA_REGS_anaRxControl2_t[01:00] - WO */ 9137 uint32_t reserved_02 : 6; /* RX_ANA_REGS_anaRxControl2_t[07:02] - RSVD */ 9138 uint32_t pmd_ln_dp_rx_rst_sm : 1; /* RX_ANA_REGS_anaRxControl2_t[08] - WO */ 9139 uint32_t pmd_ln_rx_h_pwrdn_val_sm : 1; /* RX_ANA_REGS_anaRxControl2_t[09] - WO */ 9140 uint32_t reserved_10 : 1; /* RX_ANA_REGS_anaRxControl2_t[10] - RSVD */ 9141 uint32_t reserved_11 : 1; /* RX_ANA_REGS_anaRxControl2_t[11] - RSVD */ 9142 uint32_t reserved_12 : 4; /* RX_ANA_REGS_anaRxControl2_t[15:12] - RSVD */ 9143 uint32_t reserved : 16; 9144 #endif /* IS_LITTLE_ENDIAN */ 9145 } fields; 9146 } RX_ANA_REGS_anaRxControl2_t; 9147 9148 typedef RX_ANA_REGS_anaRxControl2_t RX_ANA_REGS_ANARXCONTROL2_t; 9149 9150 typedef union { 9151 uint32_t data; 9152 struct { 9153 #if IS_BIG_ENDIAN 9154 uint32_t reserved : 16; 9155 uint32_t rxck_dme_en_force : 1; /* RX_ANA_REGS_anaRxControl3_t[15] - WO */ 9156 uint32_t rxck_dme_en_r : 1; /* RX_ANA_REGS_anaRxControl3_t[14] - WO */ 9157 uint32_t rst_dme_en_force : 1; /* RX_ANA_REGS_anaRxControl3_t[13] - WO */ 9158 uint32_t rst_dme_en_r : 1; /* RX_ANA_REGS_anaRxControl3_t[12] - WO */ 9159 uint32_t cl73_clk25_rst_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[11] - WO */ 9160 uint32_t cl73_clk25_en_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[10] - WO */ 9161 uint32_t reserved_09 : 1; /* RX_ANA_REGS_anaRxControl3_t[09] - RSVD */ 9162 uint32_t reserved_08 : 1; /* RX_ANA_REGS_anaRxControl3_t[08] - RSVD */ 9163 uint32_t use_kr_block_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[07] - WO */ 9164 uint32_t use_kr4_block_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[06] - WO */ 9165 uint32_t link_en_force_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[05] - WO */ 9166 uint32_t link_en_r : 1; /* RX_ANA_REGS_anaRxControl3_t[04] - WO */ 9167 uint32_t use_kr4_pmd_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[03] - WO */ 9168 uint32_t reserved_02 : 1; /* RX_ANA_REGS_anaRxControl3_t[02] - RSVD */ 9169 uint32_t reserved_01 : 1; /* RX_ANA_REGS_anaRxControl3_t[01] - RSVD */ 9170 uint32_t reserved_00 : 1; /* RX_ANA_REGS_anaRxControl3_t[00] - RSVD */ 9171 #endif /* IS_BIG_ENDIAN */ 9172 #if IS_LITTLE_ENDIAN 9173 uint32_t reserved_00 : 1; /* RX_ANA_REGS_anaRxControl3_t[00] - RSVD */ 9174 uint32_t reserved_01 : 1; /* RX_ANA_REGS_anaRxControl3_t[01] - RSVD */ 9175 uint32_t reserved_02 : 1; /* RX_ANA_REGS_anaRxControl3_t[02] - RSVD */ 9176 uint32_t use_kr4_pmd_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[03] - WO */ 9177 uint32_t link_en_r : 1; /* RX_ANA_REGS_anaRxControl3_t[04] - WO */ 9178 uint32_t link_en_force_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[05] - WO */ 9179 uint32_t use_kr4_block_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[06] - WO */ 9180 uint32_t use_kr_block_lock_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[07] - WO */ 9181 uint32_t reserved_08 : 1; /* RX_ANA_REGS_anaRxControl3_t[08] - RSVD */ 9182 uint32_t reserved_09 : 1; /* RX_ANA_REGS_anaRxControl3_t[09] - RSVD */ 9183 uint32_t cl73_clk25_en_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[10] - WO */ 9184 uint32_t cl73_clk25_rst_sm : 1; /* RX_ANA_REGS_anaRxControl3_t[11] - WO */ 9185 uint32_t rst_dme_en_r : 1; /* RX_ANA_REGS_anaRxControl3_t[12] - WO */ 9186 uint32_t rst_dme_en_force : 1; /* RX_ANA_REGS_anaRxControl3_t[13] - WO */ 9187 uint32_t rxck_dme_en_r : 1; /* RX_ANA_REGS_anaRxControl3_t[14] - WO */ 9188 uint32_t rxck_dme_en_force : 1; /* RX_ANA_REGS_anaRxControl3_t[15] - WO */ 9189 uint32_t reserved : 16; 9190 #endif /* IS_LITTLE_ENDIAN */ 9191 } fields; 9192 } RX_ANA_REGS_anaRxControl3_t; 9193 9194 typedef RX_ANA_REGS_anaRxControl3_t RX_ANA_REGS_ANARXCONTROL3_t; 9195 9196 9197 /*-----------------------------------------------*/ 9198 /* Structs for XGXS_BLK2 Bank */ 9199 /*-----------------------------------------------*/ 9200 typedef union { 9201 uint32_t data; 9202 struct { 9203 #if IS_BIG_ENDIAN 9204 uint32_t reserved : 16; 9205 uint32_t reset_mdio : 1; /* XGXS_BLK2_laneReset_t[15] - SC */ 9206 uint32_t reserved_09 : 6; /* XGXS_BLK2_laneReset_t[14:09] - RSVD */ 9207 uint32_t reset_pll : 1; /* XGXS_BLK2_laneReset_t[08] - WO */ 9208 uint32_t reserved_04 : 4; /* XGXS_BLK2_laneReset_t[07:04] - RSVD */ 9209 uint32_t lane_reset : 4; /* XGXS_BLK2_laneReset_t[03:00] - WO */ 9210 #endif /* IS_BIG_ENDIAN */ 9211 #if IS_LITTLE_ENDIAN 9212 uint32_t lane_reset : 4; /* XGXS_BLK2_laneReset_t[03:00] - WO */ 9213 uint32_t reserved_04 : 4; /* XGXS_BLK2_laneReset_t[07:04] - RSVD */ 9214 uint32_t reset_pll : 1; /* XGXS_BLK2_laneReset_t[08] - WO */ 9215 uint32_t reserved_09 : 6; /* XGXS_BLK2_laneReset_t[14:09] - RSVD */ 9216 uint32_t reset_mdio : 1; /* XGXS_BLK2_laneReset_t[15] - SC */ 9217 uint32_t reserved : 16; 9218 #endif /* IS_LITTLE_ENDIAN */ 9219 } fields; 9220 } XGXS_BLK2_laneReset_t; 9221 9222 typedef XGXS_BLK2_laneReset_t XGXS_BLK2_LANERESET_t; 9223 9224 9225 /*-----------------------------------------------*/ 9226 /* Structs for XGXS_BLK8 Bank */ 9227 /*-----------------------------------------------*/ 9228 typedef union { 9229 uint32_t data; 9230 struct { 9231 #if IS_BIG_ENDIAN 9232 uint32_t reserved : 16; 9233 uint32_t reserved_14 : 2; /* XGXS_BLK8_cl73Control9_t[15:14] - RSVD */ 9234 uint32_t cl73_link_fail_inhibit_timer_kr_val : 14; /* XGXS_BLK8_cl73Control9_t[13:00] - WO */ 9235 #endif /* IS_BIG_ENDIAN */ 9236 #if IS_LITTLE_ENDIAN 9237 uint32_t cl73_link_fail_inhibit_timer_kr_val : 14; /* XGXS_BLK8_cl73Control9_t[13:00] - WO */ 9238 uint32_t reserved_14 : 2; /* XGXS_BLK8_cl73Control9_t[15:14] - RSVD */ 9239 uint32_t reserved : 16; 9240 #endif /* IS_LITTLE_ENDIAN */ 9241 } fields; 9242 } XGXS_BLK8_cl73Control9_t; 9243 9244 typedef XGXS_BLK8_cl73Control9_t XGXS_BLK8_CL73CONTROL9_t; 9245 9246 9247 /*-----------------------------------------------*/ 9248 /* Structs for PMA_PMD_GNRTL_STATUS Bank */ 9249 /*-----------------------------------------------*/ 9250 typedef union { 9251 uint32_t data; 9252 struct { 9253 #if IS_BIG_ENDIAN 9254 uint32_t reserved : 16; 9255 uint32_t pmd_pll_mode : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[15:12] - RO */ 9256 uint32_t pmd_rx_sigdet : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[11:08] - RO */ 9257 uint32_t pmd_tx_clk_vld : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[07:04] - RO */ 9258 uint32_t pmd_rx_pmd_lock : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[03:00] - RO */ 9259 #endif /* IS_BIG_ENDIAN */ 9260 #if IS_LITTLE_ENDIAN 9261 uint32_t pmd_rx_pmd_lock : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[03:00] - RO */ 9262 uint32_t pmd_tx_clk_vld : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[07:04] - RO */ 9263 uint32_t pmd_rx_sigdet : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[11:08] - RO */ 9264 uint32_t pmd_pll_mode : 4; /* PMA_PMD_GNRTL_STATUS_GP2_0_t[15:12] - RO */ 9265 uint32_t reserved : 16; 9266 #endif /* IS_LITTLE_ENDIAN */ 9267 } fields; 9268 } PMA_PMD_GNRTL_STATUS_GP2_0_t; 9269 9270 9271 typedef union { 9272 uint32_t data; 9273 struct { 9274 #if IS_BIG_ENDIAN 9275 uint32_t reserved : 16; 9276 uint32_t pmd_osr_mode_ln0 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[15:12] - RO */ 9277 uint32_t pmd_osr_mode_ln1 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[11:08] - RO */ 9278 uint32_t pmd_osr_mode_ln2 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[07:04] - RO */ 9279 uint32_t pmd_osr_mode_ln3 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[03:00] - RO */ 9280 #endif /* IS_BIG_ENDIAN */ 9281 #if IS_LITTLE_ENDIAN 9282 uint32_t pmd_osr_mode_ln3 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[03:00] - RO */ 9283 uint32_t pmd_osr_mode_ln2 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[07:04] - RO */ 9284 uint32_t pmd_osr_mode_ln1 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[11:08] - RO */ 9285 uint32_t pmd_osr_mode_ln0 : 4; /* PMA_PMD_GNRTL_STATUS_GP2_1_t[15:12] - RO */ 9286 uint32_t reserved : 16; 9287 #endif /* IS_LITTLE_ENDIAN */ 9288 } fields; 9289 } PMA_PMD_GNRTL_STATUS_GP2_1_t; 9290 9291 9292 typedef union { 9293 uint32_t data; 9294 struct { 9295 #if IS_BIG_ENDIAN 9296 uint32_t reserved : 16; 9297 uint32_t actual_speed_ln2 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_2_t[15:08] - RO */ 9298 uint32_t actual_speed_ln3 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_2_t[07:00] - RO */ 9299 #endif /* IS_BIG_ENDIAN */ 9300 #if IS_LITTLE_ENDIAN 9301 uint32_t actual_speed_ln3 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_2_t[07:00] - RO */ 9302 uint32_t actual_speed_ln2 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_2_t[15:08] - RO */ 9303 uint32_t reserved : 16; 9304 #endif /* IS_LITTLE_ENDIAN */ 9305 } fields; 9306 } PMA_PMD_GNRTL_STATUS_GP2_2_t; 9307 9308 9309 typedef union { 9310 uint32_t data; 9311 struct { 9312 #if IS_BIG_ENDIAN 9313 uint32_t reserved : 16; 9314 uint32_t actual_speed_ln0 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_3_t[15:08] - RO */ 9315 uint32_t actual_speed_ln1 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_3_t[07:00] - RO */ 9316 #endif /* IS_BIG_ENDIAN */ 9317 #if IS_LITTLE_ENDIAN 9318 uint32_t actual_speed_ln1 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_3_t[07:00] - RO */ 9319 uint32_t actual_speed_ln0 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_3_t[15:08] - RO */ 9320 uint32_t reserved : 16; 9321 #endif /* IS_LITTLE_ENDIAN */ 9322 } fields; 9323 } PMA_PMD_GNRTL_STATUS_GP2_3_t; 9324 9325 9326 typedef union { 9327 uint32_t data; 9328 struct { 9329 #if IS_BIG_ENDIAN 9330 uint32_t reserved : 16; 9331 uint32_t cl73_autoneg_complete : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[15:12] - RO */ 9332 uint32_t pmd_rx_dme_en : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[11:08] - RO */ 9333 uint32_t cl73_mr_lp_autoneg_able : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[07:04] - RO */ 9334 uint32_t cl73_mr_autoneg_able : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[03:00] - RO */ 9335 #endif /* IS_BIG_ENDIAN */ 9336 #if IS_LITTLE_ENDIAN 9337 uint32_t cl73_mr_autoneg_able : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[03:00] - RO */ 9338 uint32_t cl73_mr_lp_autoneg_able : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[07:04] - RO */ 9339 uint32_t pmd_rx_dme_en : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[11:08] - RO */ 9340 uint32_t cl73_autoneg_complete : 4; /* PMA_PMD_GNRTL_STATUS_GP2_4_t[15:12] - RO */ 9341 uint32_t reserved : 16; 9342 #endif /* IS_LITTLE_ENDIAN */ 9343 } fields; 9344 } PMA_PMD_GNRTL_STATUS_GP2_4_t; 9345 9346 9347 typedef union { 9348 uint32_t data; 9349 struct { 9350 #if IS_BIG_ENDIAN 9351 uint32_t reserved : 16; 9352 uint32_t cl73_bamstat123_ln3 : 16; /* PMA_PMD_GNRTL_STATUS_GP2_5_t[15:00] - RO */ 9353 #endif /* IS_BIG_ENDIAN */ 9354 #if IS_LITTLE_ENDIAN 9355 uint32_t cl73_bamstat123_ln3 : 16; /* PMA_PMD_GNRTL_STATUS_GP2_5_t[15:00] - RO */ 9356 uint32_t reserved : 16; 9357 #endif /* IS_LITTLE_ENDIAN */ 9358 } fields; 9359 } PMA_PMD_GNRTL_STATUS_GP2_5_t; 9360 9361 9362 typedef union { 9363 uint32_t data; 9364 struct { 9365 #if IS_BIG_ENDIAN 9366 uint32_t reserved : 16; 9367 uint32_t cl73_bamstat123_ln3 : 16; /* PMA_PMD_GNRTL_STATUS_GP2_6_t[15:00] - RO */ 9368 #endif /* IS_BIG_ENDIAN */ 9369 #if IS_LITTLE_ENDIAN 9370 uint32_t cl73_bamstat123_ln3 : 16; /* PMA_PMD_GNRTL_STATUS_GP2_6_t[15:00] - RO */ 9371 uint32_t reserved : 16; 9372 #endif /* IS_LITTLE_ENDIAN */ 9373 } fields; 9374 } PMA_PMD_GNRTL_STATUS_GP2_6_t; 9375 9376 9377 typedef union { 9378 uint32_t data; 9379 struct { 9380 #if IS_BIG_ENDIAN 9381 uint32_t reserved : 16; 9382 uint32_t cl73_bamstat123_ln3 : 16; /* PMA_PMD_GNRTL_STATUS_GP2_7_t[15:00] - RO */ 9383 #endif /* IS_BIG_ENDIAN */ 9384 #if IS_LITTLE_ENDIAN 9385 uint32_t cl73_bamstat123_ln3 : 16; /* PMA_PMD_GNRTL_STATUS_GP2_7_t[15:00] - RO */ 9386 uint32_t reserved : 16; 9387 #endif /* IS_LITTLE_ENDIAN */ 9388 } fields; 9389 } PMA_PMD_GNRTL_STATUS_GP2_7_t; 9390 9391 9392 typedef union { 9393 uint32_t data; 9394 struct { 9395 #if IS_BIG_ENDIAN 9396 uint32_t reserved : 16; 9397 uint32_t an_speed_ln2 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_8_t[15:08] - RO */ 9398 uint32_t an_speed_ln3 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_8_t[07:00] - RO */ 9399 #endif /* IS_BIG_ENDIAN */ 9400 #if IS_LITTLE_ENDIAN 9401 uint32_t an_speed_ln3 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_8_t[07:00] - RO */ 9402 uint32_t an_speed_ln2 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_8_t[15:08] - RO */ 9403 uint32_t reserved : 16; 9404 #endif /* IS_LITTLE_ENDIAN */ 9405 } fields; 9406 } PMA_PMD_GNRTL_STATUS_GP2_8_t; 9407 9408 9409 typedef union { 9410 uint32_t data; 9411 struct { 9412 #if IS_BIG_ENDIAN 9413 uint32_t reserved : 16; 9414 uint32_t an_speed_ln0 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_9_t[15:08] - RO */ 9415 uint32_t an_speed_ln1 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_9_t[07:00] - RO */ 9416 #endif /* IS_BIG_ENDIAN */ 9417 #if IS_LITTLE_ENDIAN 9418 uint32_t an_speed_ln1 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_9_t[07:00] - RO */ 9419 uint32_t an_speed_ln0 : 8; /* PMA_PMD_GNRTL_STATUS_GP2_9_t[15:08] - RO */ 9420 uint32_t reserved : 16; 9421 #endif /* IS_LITTLE_ENDIAN */ 9422 } fields; 9423 } PMA_PMD_GNRTL_STATUS_GP2_9_t; 9424 9425 9426 9427 /*-----------------------------------------------*/ 9428 /* Structs for LINE_RX_PMA_DP Bank */ 9429 /*-----------------------------------------------*/ 9430 typedef union { 9431 uint32_t data; 9432 struct { 9433 #if IS_BIG_ENDIAN 9434 uint32_t reserved : 16; 9435 uint32_t reserved_06 : 10; /* LINE_RX_PMA_DP_main_ctrl_t[15:06] - RSVD */ 9436 uint32_t reserved_04 : 2; /* LINE_RX_PMA_DP_main_ctrl_t[05:04] - RSVD */ 9437 uint32_t reserved_03 : 1; /* LINE_RX_PMA_DP_main_ctrl_t[03] - RSVD */ 9438 uint32_t reserved_02 : 1; /* LINE_RX_PMA_DP_main_ctrl_t[02] - RSVD */ 9439 uint32_t rstb_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_t[01] - WO */ 9440 uint32_t rstb : 1; /* LINE_RX_PMA_DP_main_ctrl_t[00] - WO */ 9441 #endif /* IS_BIG_ENDIAN */ 9442 #if IS_LITTLE_ENDIAN 9443 uint32_t rstb : 1; /* LINE_RX_PMA_DP_main_ctrl_t[00] - WO */ 9444 uint32_t rstb_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_t[01] - WO */ 9445 uint32_t reserved_02 : 1; /* LINE_RX_PMA_DP_main_ctrl_t[02] - RSVD */ 9446 uint32_t reserved_03 : 1; /* LINE_RX_PMA_DP_main_ctrl_t[03] - RSVD */ 9447 uint32_t reserved_04 : 2; /* LINE_RX_PMA_DP_main_ctrl_t[05:04] - RSVD */ 9448 uint32_t reserved_06 : 10; /* LINE_RX_PMA_DP_main_ctrl_t[15:06] - RSVD */ 9449 uint32_t reserved : 16; 9450 #endif /* IS_LITTLE_ENDIAN */ 9451 } fields; 9452 } LINE_RX_PMA_DP_main_ctrl_t; 9453 9454 typedef LINE_RX_PMA_DP_main_ctrl_t LINE_RX_PMA_DP_MAIN_CTRL_t; 9455 9456 typedef union { 9457 uint32_t data; 9458 struct { 9459 #if IS_BIG_ENDIAN 9460 uint32_t reserved : 16; 9461 uint32_t reserved_15 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[15] - RSVD */ 9462 uint32_t reserved_14 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[14] - RSVD */ 9463 uint32_t reserved_13 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[13] - RSVD */ 9464 uint32_t pf_rstb : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[12] - WO */ 9465 uint32_t reserved_11 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[11] - RSVD */ 9466 uint32_t auto_reset_dis : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[10] - WO */ 9467 uint32_t out_sel : 2; /* LINE_RX_PMA_DP_dp_ctrl_t[09:08] - RSVD */ 9468 uint32_t reserved_04 : 4; /* LINE_RX_PMA_DP_dp_ctrl_t[07:04] - RSVD */ 9469 uint32_t ptr_sync : 4; /* LINE_RX_PMA_DP_dp_ctrl_t[03:00] - RSVD */ 9470 #endif /* IS_BIG_ENDIAN */ 9471 #if IS_LITTLE_ENDIAN 9472 uint32_t ptr_sync : 4; /* LINE_RX_PMA_DP_dp_ctrl_t[03:00] - RSVD */ 9473 uint32_t reserved_04 : 4; /* LINE_RX_PMA_DP_dp_ctrl_t[07:04] - RSVD */ 9474 uint32_t out_sel : 2; /* LINE_RX_PMA_DP_dp_ctrl_t[09:08] - RSVD */ 9475 uint32_t auto_reset_dis : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[10] - WO */ 9476 uint32_t reserved_11 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[11] - RSVD */ 9477 uint32_t pf_rstb : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[12] - WO */ 9478 uint32_t reserved_13 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[13] - RSVD */ 9479 uint32_t reserved_14 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[14] - RSVD */ 9480 uint32_t reserved_15 : 1; /* LINE_RX_PMA_DP_dp_ctrl_t[15] - RSVD */ 9481 uint32_t reserved : 16; 9482 #endif /* IS_LITTLE_ENDIAN */ 9483 } fields; 9484 } LINE_RX_PMA_DP_dp_ctrl_t; 9485 9486 typedef LINE_RX_PMA_DP_dp_ctrl_t LINE_RX_PMA_DP_DP_CTRL_t; 9487 9488 typedef union { 9489 uint32_t data; 9490 struct { 9491 #if IS_BIG_ENDIAN 9492 uint32_t reserved : 16; 9493 uint32_t reserved_01 : 15; /* LINE_RX_PMA_DP_latched_status_t[15:01] - RSVD */ 9494 uint32_t pf_col_lh : 1; /* LINE_RX_PMA_DP_latched_status_t[00] - RO */ 9495 #endif /* IS_BIG_ENDIAN */ 9496 #if IS_LITTLE_ENDIAN 9497 uint32_t pf_col_lh : 1; /* LINE_RX_PMA_DP_latched_status_t[00] - RO */ 9498 uint32_t reserved_01 : 15; /* LINE_RX_PMA_DP_latched_status_t[15:01] - RSVD */ 9499 uint32_t reserved : 16; 9500 #endif /* IS_LITTLE_ENDIAN */ 9501 } fields; 9502 } LINE_RX_PMA_DP_latched_status_t; 9503 9504 typedef LINE_RX_PMA_DP_latched_status_t LINE_RX_PMA_DP_LATCHED_STATUS_t; 9505 9506 typedef union { 9507 uint32_t data; 9508 struct { 9509 #if IS_BIG_ENDIAN 9510 uint32_t reserved : 16; 9511 uint32_t reserved_08 : 8; /* LINE_RX_PMA_DP_live_status_t[15:08] - RSVD */ 9512 uint32_t reserved_01 : 7; /* LINE_RX_PMA_DP_live_status_t[07:01] - RSVD */ 9513 uint32_t pf_col : 1; /* LINE_RX_PMA_DP_live_status_t[00] - RO */ 9514 #endif /* IS_BIG_ENDIAN */ 9515 #if IS_LITTLE_ENDIAN 9516 uint32_t pf_col : 1; /* LINE_RX_PMA_DP_live_status_t[00] - RO */ 9517 uint32_t reserved_01 : 7; /* LINE_RX_PMA_DP_live_status_t[07:01] - RSVD */ 9518 uint32_t reserved_08 : 8; /* LINE_RX_PMA_DP_live_status_t[15:08] - RSVD */ 9519 uint32_t reserved : 16; 9520 #endif /* IS_LITTLE_ENDIAN */ 9521 } fields; 9522 } LINE_RX_PMA_DP_live_status_t; 9523 9524 typedef LINE_RX_PMA_DP_live_status_t LINE_RX_PMA_DP_LIVE_STATUS_t; 9525 9526 9527 /*-----------------------------------------------*/ 9528 /* Structs for LINE_TX_PMA_DP Bank */ 9529 /*-----------------------------------------------*/ 9530 typedef union { 9531 uint32_t data; 9532 struct { 9533 #if IS_BIG_ENDIAN 9534 uint32_t reserved : 16; 9535 uint32_t reserved_02 : 14; /* LINE_TX_PMA_DP_soft_rst_t[15:02] - RSVD */ 9536 uint32_t rstb_frc : 1; /* LINE_TX_PMA_DP_soft_rst_t[01] - WO */ 9537 uint32_t rstb : 1; /* LINE_TX_PMA_DP_soft_rst_t[00] - WO */ 9538 #endif /* IS_BIG_ENDIAN */ 9539 #if IS_LITTLE_ENDIAN 9540 uint32_t rstb : 1; /* LINE_TX_PMA_DP_soft_rst_t[00] - WO */ 9541 uint32_t rstb_frc : 1; /* LINE_TX_PMA_DP_soft_rst_t[01] - WO */ 9542 uint32_t reserved_02 : 14; /* LINE_TX_PMA_DP_soft_rst_t[15:02] - RSVD */ 9543 uint32_t reserved : 16; 9544 #endif /* IS_LITTLE_ENDIAN */ 9545 } fields; 9546 } LINE_TX_PMA_DP_soft_rst_t; 9547 9548 typedef LINE_TX_PMA_DP_soft_rst_t LINE_TX_PMA_DP_SOFT_RST_t; 9549 9550 typedef union { 9551 uint32_t data; 9552 struct { 9553 #if IS_BIG_ENDIAN 9554 uint32_t reserved : 16; 9555 uint32_t reserved_15 : 1; /* LINE_TX_PMA_DP_ctrl_t[15] - RSVD */ 9556 uint32_t reserved_14 : 1; /* LINE_TX_PMA_DP_ctrl_t[14] - RSVD */ 9557 uint32_t reserved_12 : 2; /* LINE_TX_PMA_DP_ctrl_t[13:12] - RSVD */ 9558 uint32_t reserved_11 : 1; /* LINE_TX_PMA_DP_ctrl_t[11] - RSVD */ 9559 uint32_t pf_rstb : 1; /* LINE_TX_PMA_DP_ctrl_t[10] - WO */ 9560 uint32_t reserved_09 : 1; /* LINE_TX_PMA_DP_ctrl_t[09] - RSVD */ 9561 uint32_t auto_reset_dis : 1; /* LINE_TX_PMA_DP_ctrl_t[08] - WO */ 9562 uint32_t reserved_04 : 4; /* LINE_TX_PMA_DP_ctrl_t[07:04] - RSVD */ 9563 uint32_t ptr_sync : 4; /* LINE_TX_PMA_DP_ctrl_t[03:00] - RSVD */ 9564 #endif /* IS_BIG_ENDIAN */ 9565 #if IS_LITTLE_ENDIAN 9566 uint32_t ptr_sync : 4; /* LINE_TX_PMA_DP_ctrl_t[03:00] - RSVD */ 9567 uint32_t reserved_04 : 4; /* LINE_TX_PMA_DP_ctrl_t[07:04] - RSVD */ 9568 uint32_t auto_reset_dis : 1; /* LINE_TX_PMA_DP_ctrl_t[08] - WO */ 9569 uint32_t reserved_09 : 1; /* LINE_TX_PMA_DP_ctrl_t[09] - RSVD */ 9570 uint32_t pf_rstb : 1; /* LINE_TX_PMA_DP_ctrl_t[10] - WO */ 9571 uint32_t reserved_11 : 1; /* LINE_TX_PMA_DP_ctrl_t[11] - RSVD */ 9572 uint32_t reserved_12 : 2; /* LINE_TX_PMA_DP_ctrl_t[13:12] - RSVD */ 9573 uint32_t reserved_14 : 1; /* LINE_TX_PMA_DP_ctrl_t[14] - RSVD */ 9574 uint32_t reserved_15 : 1; /* LINE_TX_PMA_DP_ctrl_t[15] - RSVD */ 9575 uint32_t reserved : 16; 9576 #endif /* IS_LITTLE_ENDIAN */ 9577 } fields; 9578 } LINE_TX_PMA_DP_ctrl_t; 9579 9580 typedef LINE_TX_PMA_DP_ctrl_t LINE_TX_PMA_DP_CTRL_t; 9581 9582 typedef union { 9583 uint32_t data; 9584 struct { 9585 #if IS_BIG_ENDIAN 9586 uint32_t reserved : 16; 9587 uint32_t reserved_02 : 14; /* LINE_TX_PMA_DP_pf_status_t[15:02] - RSVD */ 9588 uint32_t pf_col : 1; /* LINE_TX_PMA_DP_pf_status_t[01] - RO */ 9589 uint32_t pf_col_lh : 1; /* LINE_TX_PMA_DP_pf_status_t[00] - RO */ 9590 #endif /* IS_BIG_ENDIAN */ 9591 #if IS_LITTLE_ENDIAN 9592 uint32_t pf_col_lh : 1; /* LINE_TX_PMA_DP_pf_status_t[00] - RO */ 9593 uint32_t pf_col : 1; /* LINE_TX_PMA_DP_pf_status_t[01] - RO */ 9594 uint32_t reserved_02 : 14; /* LINE_TX_PMA_DP_pf_status_t[15:02] - RSVD */ 9595 uint32_t reserved : 16; 9596 #endif /* IS_LITTLE_ENDIAN */ 9597 } fields; 9598 } LINE_TX_PMA_DP_pf_status_t; 9599 9600 typedef LINE_TX_PMA_DP_pf_status_t LINE_TX_PMA_DP_PF_STATUS_t; 9601 9602 9603 /*-----------------------------------------------*/ 9604 /* Structs for SYS_RX_PMA_DP Bank */ 9605 /*-----------------------------------------------*/ 9606 typedef union { 9607 uint32_t data; 9608 struct { 9609 #if IS_BIG_ENDIAN 9610 uint32_t reserved : 16; 9611 uint32_t reserved_06 : 10; /* SYS_RX_PMA_DP_main_ctrl_t[15:06] - RSVD */ 9612 uint32_t reserved_04 : 2; /* SYS_RX_PMA_DP_main_ctrl_t[05:04] - RSVD */ 9613 uint32_t reserved_03 : 1; /* SYS_RX_PMA_DP_main_ctrl_t[03] - RSVD */ 9614 uint32_t reserved_02 : 1; /* SYS_RX_PMA_DP_main_ctrl_t[02] - RSVD */ 9615 uint32_t rstb_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_t[01] - WO */ 9616 uint32_t rstb : 1; /* SYS_RX_PMA_DP_main_ctrl_t[00] - WO */ 9617 #endif /* IS_BIG_ENDIAN */ 9618 #if IS_LITTLE_ENDIAN 9619 uint32_t rstb : 1; /* SYS_RX_PMA_DP_main_ctrl_t[00] - WO */ 9620 uint32_t rstb_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_t[01] - WO */ 9621 uint32_t reserved_02 : 1; /* SYS_RX_PMA_DP_main_ctrl_t[02] - RSVD */ 9622 uint32_t reserved_03 : 1; /* SYS_RX_PMA_DP_main_ctrl_t[03] - RSVD */ 9623 uint32_t reserved_04 : 2; /* SYS_RX_PMA_DP_main_ctrl_t[05:04] - RSVD */ 9624 uint32_t reserved_06 : 10; /* SYS_RX_PMA_DP_main_ctrl_t[15:06] - RSVD */ 9625 uint32_t reserved : 16; 9626 #endif /* IS_LITTLE_ENDIAN */ 9627 } fields; 9628 } SYS_RX_PMA_DP_main_ctrl_t; 9629 9630 typedef SYS_RX_PMA_DP_main_ctrl_t SYS_RX_PMA_DP_MAIN_CTRL_t; 9631 9632 typedef union { 9633 uint32_t data; 9634 struct { 9635 #if IS_BIG_ENDIAN 9636 uint32_t reserved : 16; 9637 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[15] - RSVD */ 9638 uint32_t reserved_14 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[14] - RSVD */ 9639 uint32_t reserved_13 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[13] - RSVD */ 9640 uint32_t pf_rstb : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[12] - WO */ 9641 uint32_t reserved_11 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[11] - RSVD */ 9642 uint32_t auto_reset_dis : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[10] - WO */ 9643 uint32_t out_sel: 2; /* SYS_RX_PMA_DP_dp_ctrl_t[09:08] - RSVD */ 9644 uint32_t reserved_04 : 4; /* SYS_RX_PMA_DP_dp_ctrl_t[07:04] - RSVD */ 9645 uint32_t ptr_sync : 4; /* SYS_RX_PMA_DP_dp_ctrl_t[03:00] - RSVD */ 9646 #endif /* IS_BIG_ENDIAN */ 9647 #if IS_LITTLE_ENDIAN 9648 uint32_t ptr_sync : 4; /* SYS_RX_PMA_DP_dp_ctrl_t[03:00] - RSVD */ 9649 uint32_t reserved_04 : 4; /* SYS_RX_PMA_DP_dp_ctrl_t[07:04] - RSVD */ 9650 uint32_t out_sel: 2; /* SYS_RX_PMA_DP_dp_ctrl_t[09:08] - RSVD */ 9651 uint32_t auto_reset_dis : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[10] - WO */ 9652 uint32_t reserved_11 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[11] - RSVD */ 9653 uint32_t pf_rstb : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[12] - WO */ 9654 uint32_t reserved_13 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[13] - RSVD */ 9655 uint32_t reserved_14 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[14] - RSVD */ 9656 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_dp_ctrl_t[15] - RSVD */ 9657 uint32_t reserved : 16; 9658 #endif /* IS_LITTLE_ENDIAN */ 9659 } fields; 9660 } SYS_RX_PMA_DP_dp_ctrl_t; 9661 9662 typedef SYS_RX_PMA_DP_dp_ctrl_t SYS_RX_PMA_DP_DP_CTRL_t; 9663 9664 typedef union { 9665 uint32_t data; 9666 struct { 9667 #if IS_BIG_ENDIAN 9668 uint32_t reserved : 16; 9669 uint32_t reserved_01 : 15; /* SYS_RX_PMA_DP_latched_status_t[15:01] - RSVD */ 9670 uint32_t pf_col_lh : 1; /* SYS_RX_PMA_DP_latched_status_t[00] - RO */ 9671 #endif /* IS_BIG_ENDIAN */ 9672 #if IS_LITTLE_ENDIAN 9673 uint32_t pf_col_lh : 1; /* SYS_RX_PMA_DP_latched_status_t[00] - RO */ 9674 uint32_t reserved_01 : 15; /* SYS_RX_PMA_DP_latched_status_t[15:01] - RSVD */ 9675 uint32_t reserved : 16; 9676 #endif /* IS_LITTLE_ENDIAN */ 9677 } fields; 9678 } SYS_RX_PMA_DP_latched_status_t; 9679 9680 typedef SYS_RX_PMA_DP_latched_status_t SYS_RX_PMA_DP_LATCHED_STATUS_t; 9681 9682 typedef union { 9683 uint32_t data; 9684 struct { 9685 #if IS_BIG_ENDIAN 9686 uint32_t reserved : 16; 9687 uint32_t reserved_08 : 8; /* SYS_RX_PMA_DP_live_status_t[15:08] - RSVD */ 9688 uint32_t reserved_01 : 7; /* SYS_RX_PMA_DP_live_status_t[07:01] - RSVD */ 9689 uint32_t pf_col : 1; /* SYS_RX_PMA_DP_live_status_t[00] - RO */ 9690 #endif /* IS_BIG_ENDIAN */ 9691 #if IS_LITTLE_ENDIAN 9692 uint32_t pf_col : 1; /* SYS_RX_PMA_DP_live_status_t[00] - RO */ 9693 uint32_t reserved_01 : 7; /* SYS_RX_PMA_DP_live_status_t[07:01] - RSVD */ 9694 uint32_t reserved_08 : 8; /* SYS_RX_PMA_DP_live_status_t[15:08] - RSVD */ 9695 uint32_t reserved : 16; 9696 #endif /* IS_LITTLE_ENDIAN */ 9697 } fields; 9698 } SYS_RX_PMA_DP_live_status_t; 9699 9700 typedef SYS_RX_PMA_DP_live_status_t SYS_RX_PMA_DP_LIVE_STATUS_t; 9701 9702 9703 /*-----------------------------------------------*/ 9704 /* Structs for SYS_TX_PMA_DP Bank */ 9705 /*-----------------------------------------------*/ 9706 typedef union { 9707 uint32_t data; 9708 struct { 9709 #if IS_BIG_ENDIAN 9710 uint32_t reserved : 16; 9711 uint32_t reserved_02 : 14; /* SYS_TX_PMA_DP_soft_rst_t[15:02] - RSVD */ 9712 uint32_t rstb_frc : 1; /* SYS_TX_PMA_DP_soft_rst_t[01] - WO */ 9713 uint32_t rstb : 1; /* SYS_TX_PMA_DP_soft_rst_t[00] - WO */ 9714 #endif /* IS_BIG_ENDIAN */ 9715 #if IS_LITTLE_ENDIAN 9716 uint32_t rstb : 1; /* SYS_TX_PMA_DP_soft_rst_t[00] - WO */ 9717 uint32_t rstb_frc : 1; /* SYS_TX_PMA_DP_soft_rst_t[01] - WO */ 9718 uint32_t reserved_02 : 14; /* SYS_TX_PMA_DP_soft_rst_t[15:02] - RSVD */ 9719 uint32_t reserved : 16; 9720 #endif /* IS_LITTLE_ENDIAN */ 9721 } fields; 9722 } SYS_TX_PMA_DP_soft_rst_t; 9723 9724 typedef SYS_TX_PMA_DP_soft_rst_t SYS_TX_PMA_DP_SOFT_RST_t; 9725 9726 typedef union { 9727 uint32_t data; 9728 struct { 9729 #if IS_BIG_ENDIAN 9730 uint32_t reserved : 16; 9731 uint32_t reserved_15 : 1; /* SYS_TX_PMA_DP_ctrl_t[15] - RSVD */ 9732 uint32_t reserved_14 : 1; /* SYS_TX_PMA_DP_ctrl_t[14] - RSVD */ 9733 uint32_t reserved_12 : 2; /* SYS_TX_PMA_DP_ctrl_t[13:12] - RSVD */ 9734 uint32_t reserved_11 : 1; /* SYS_TX_PMA_DP_ctrl_t[11] - RSVD */ 9735 uint32_t pf_rstb : 1; /* SYS_TX_PMA_DP_ctrl_t[10] - WO */ 9736 uint32_t reserved_09 : 1; /* SYS_TX_PMA_DP_ctrl_t[09] - RSVD */ 9737 uint32_t auto_reset_dis : 1; /* SYS_TX_PMA_DP_ctrl_t[08] - WO */ 9738 uint32_t reserved_04 : 4; /* SYS_TX_PMA_DP_ctrl_t[07:04] - RSVD */ 9739 uint32_t ptr_sync : 4; /* SYS_TX_PMA_DP_ctrl_t[03:00] - RSVD */ 9740 #endif /* IS_BIG_ENDIAN */ 9741 #if IS_LITTLE_ENDIAN 9742 uint32_t ptr_sync : 4; /* SYS_TX_PMA_DP_ctrl_t[03:00] - RSVD */ 9743 uint32_t reserved_04 : 4; /* SYS_TX_PMA_DP_ctrl_t[07:04] - RSVD */ 9744 uint32_t auto_reset_dis : 1; /* SYS_TX_PMA_DP_ctrl_t[08] - WO */ 9745 uint32_t reserved_09 : 1; /* SYS_TX_PMA_DP_ctrl_t[09] - RSVD */ 9746 uint32_t pf_rstb : 1; /* SYS_TX_PMA_DP_ctrl_t[10] - WO */ 9747 uint32_t reserved_11 : 1; /* SYS_TX_PMA_DP_ctrl_t[11] - RSVD */ 9748 uint32_t reserved_12 : 2; /* SYS_TX_PMA_DP_ctrl_t[13:12] - RSVD */ 9749 uint32_t reserved_14 : 1; /* SYS_TX_PMA_DP_ctrl_t[14] - RSVD */ 9750 uint32_t reserved_15 : 1; /* SYS_TX_PMA_DP_ctrl_t[15] - RSVD */ 9751 uint32_t reserved : 16; 9752 #endif /* IS_LITTLE_ENDIAN */ 9753 } fields; 9754 } SYS_TX_PMA_DP_ctrl_t; 9755 9756 typedef SYS_TX_PMA_DP_ctrl_t SYS_TX_PMA_DP_CTRL_t; 9757 9758 typedef union { 9759 uint32_t data; 9760 struct { 9761 #if IS_BIG_ENDIAN 9762 uint32_t reserved : 16; 9763 uint32_t reserved_02 : 14; /* SYS_TX_PMA_DP_pf_status_t[15:02] - RSVD */ 9764 uint32_t pf_col : 1; /* SYS_TX_PMA_DP_pf_status_t[01] - RO */ 9765 uint32_t pf_col_lh : 1; /* SYS_TX_PMA_DP_pf_status_t[00] - RO */ 9766 #endif /* IS_BIG_ENDIAN */ 9767 #if IS_LITTLE_ENDIAN 9768 uint32_t pf_col_lh : 1; /* SYS_TX_PMA_DP_pf_status_t[00] - RO */ 9769 uint32_t pf_col : 1; /* SYS_TX_PMA_DP_pf_status_t[01] - RO */ 9770 uint32_t reserved_02 : 14; /* SYS_TX_PMA_DP_pf_status_t[15:02] - RSVD */ 9771 uint32_t reserved : 16; 9772 #endif /* IS_LITTLE_ENDIAN */ 9773 } fields; 9774 } SYS_TX_PMA_DP_pf_status_t; 9775 9776 typedef SYS_TX_PMA_DP_pf_status_t SYS_TX_PMA_DP_PF_STATUS_t; 9777 9778 9779 /*-----------------------------------------------*/ 9780 /* Structs for DSC_C Bank */ 9781 /*-----------------------------------------------*/ 9782 typedef union { 9783 uint32_t data; 9784 struct { 9785 #if IS_BIG_ENDIAN 9786 uint32_t reserved : 16; 9787 uint32_t reserved_10 : 6; /* DSC_C_cdr_control_2_t[15:10] - RSVD */ 9788 uint32_t cdr_1g_manual_strobe : 1; /* DSC_C_cdr_control_2_t[09] - SC */ 9789 uint32_t cdr_1g_manual_mode : 1; /* DSC_C_cdr_control_2_t[08] - RW */ 9790 uint32_t phs_sum_ignore_dsc_lock : 1; /* DSC_C_cdr_control_2_t[07] - RW */ 9791 uint32_t tx_pi_loop_timing_src_sel : 1; /* DSC_C_cdr_control_2_t[06] - RW */ 9792 uint32_t cdr_1g_force_en : 1; /* DSC_C_cdr_control_2_t[05] - RW */ 9793 uint32_t cdr_1g_swap_pz : 1; /* DSC_C_cdr_control_2_t[04] - RW */ 9794 uint32_t cdr_lm_thr_sel : 4; /* DSC_C_cdr_control_2_t[03:00] - RW */ 9795 #endif /* IS_BIG_ENDIAN */ 9796 #if IS_LITTLE_ENDIAN 9797 uint32_t cdr_lm_thr_sel : 4; /* DSC_C_cdr_control_2_t[03:00] - RW */ 9798 uint32_t cdr_1g_swap_pz : 1; /* DSC_C_cdr_control_2_t[04] - RW */ 9799 uint32_t cdr_1g_force_en : 1; /* DSC_C_cdr_control_2_t[05] - RW */ 9800 uint32_t tx_pi_loop_timing_src_sel : 1; /* DSC_C_cdr_control_2_t[06] - RW */ 9801 uint32_t phs_sum_ignore_dsc_lock : 1; /* DSC_C_cdr_control_2_t[07] - RW */ 9802 uint32_t cdr_1g_manual_mode : 1; /* DSC_C_cdr_control_2_t[08] - RW */ 9803 uint32_t cdr_1g_manual_strobe : 1; /* DSC_C_cdr_control_2_t[09] - SC */ 9804 uint32_t reserved_10 : 6; /* DSC_C_cdr_control_2_t[15:10] - RSVD */ 9805 uint32_t reserved : 16; 9806 #endif /* IS_LITTLE_ENDIAN */ 9807 } fields; 9808 } DSC_C_cdr_control_2_t; 9809 9810 typedef DSC_C_cdr_control_2_t DSC_C_CDR_CONTROL_2_t; 9811 9812 typedef union { 9813 uint32_t data; 9814 struct { 9815 #if IS_BIG_ENDIAN 9816 uint32_t reserved : 16; 9817 uint32_t reserved_12 : 4; /* DSC_C_rx_pi_control_t[15:12] - RSVD */ 9818 uint32_t rx_pi_manual_strobe : 1; /* DSC_C_rx_pi_control_t[11] - SC */ 9819 uint32_t rx_pi_manual_mode : 1; /* DSC_C_rx_pi_control_t[10] - RW */ 9820 uint32_t rx_pi_phase_step_dir : 1; /* DSC_C_rx_pi_control_t[09] - RW */ 9821 uint32_t rx_pi_phase_step_cnt : 3; /* DSC_C_rx_pi_control_t[08:06] - RW */ 9822 uint32_t rx_pi_slicers_en : 6; /* DSC_C_rx_pi_control_t[05:00] - RW */ 9823 #endif /* IS_BIG_ENDIAN */ 9824 #if IS_LITTLE_ENDIAN 9825 uint32_t rx_pi_slicers_en : 6; /* DSC_C_rx_pi_control_t[05:00] - RW */ 9826 uint32_t rx_pi_phase_step_cnt : 3; /* DSC_C_rx_pi_control_t[08:06] - RW */ 9827 uint32_t rx_pi_phase_step_dir : 1; /* DSC_C_rx_pi_control_t[09] - RW */ 9828 uint32_t rx_pi_manual_mode : 1; /* DSC_C_rx_pi_control_t[10] - RW */ 9829 uint32_t rx_pi_manual_strobe : 1; /* DSC_C_rx_pi_control_t[11] - SC */ 9830 uint32_t reserved_12 : 4; /* DSC_C_rx_pi_control_t[15:12] - RSVD */ 9831 uint32_t reserved : 16; 9832 #endif /* IS_LITTLE_ENDIAN */ 9833 } fields; 9834 } DSC_C_rx_pi_control_t; 9835 9836 typedef DSC_C_rx_pi_control_t DSC_C_RX_PI_CONTROL_t; 9837 9838 9839 /*-----------------------------------------------*/ 9840 /* Structs for DSC_D Bank */ 9841 /*-----------------------------------------------*/ 9842 typedef union { 9843 uint32_t data; 9844 struct { 9845 #if IS_BIG_ENDIAN 9846 uint32_t reserved : 16; 9847 uint32_t reserved_2 : 14; /* DSC_D_dsc_sm_ctrl_9_t[15:2] - RSVD */ 9848 uint32_t rx_restart_pmd_hold : 1; /* DSC_D_dsc_sm_ctrl_9_t[01] - RW */ 9849 uint32_t rx_restart_pmd : 1; /* DSC_D_dsc_sm_ctrl_9_t[00] - RW */ 9850 #endif /* IS_BIG_ENDIAN */ 9851 #if IS_LITTLE_ENDIAN 9852 uint32_t rx_restart_pmd : 1; /* DSC_D_dsc_sm_ctrl_9_t[00] - RW */ 9853 uint32_t rx_restart_pmd_hold : 1; /* DSC_D_dsc_sm_ctrl_9_t[01] - RW */ 9854 uint32_t reserved_2 : 14; /* DSC_D_dsc_sm_ctrl_9_t[15:2] - RSVD */ 9855 uint32_t reserved : 16; 9856 #endif /* IS_LITTLE_ENDIAN */ 9857 } fields; 9858 } DSC_D_dsc_sm_ctrl_9_t; 9859 9860 typedef DSC_D_dsc_sm_ctrl_9_t DSC_D_DSC_CONTROL_9_t; 9861 9862 9863 /*-----------------------------------------------*/ 9864 /* Structs for TX_PI_RPTR Bank */ 9865 /*-----------------------------------------------*/ 9866 typedef union { 9867 uint32_t data; 9868 struct { 9869 #if IS_BIG_ENDIAN 9870 uint32_t reserved : 16; 9871 uint32_t reserved_15 : 1; /* TX_PI_RPTR_tx_pi_control_0_t[15] - RSVD */ 9872 uint32_t tx_pi_ext_phase_bwsel_integ : 3; /* TX_PI_RPTR_tx_pi_control_0_t[14:12] - RW */ 9873 uint32_t tx_pi_second_order_bwsel_integ : 2; /* TX_PI_RPTR_tx_pi_control_0_t[11:10] - RW */ 9874 uint32_t tx_pi_first_order_bwsel_integ : 2; /* TX_PI_RPTR_tx_pi_control_0_t[09:08] - RW */ 9875 uint32_t tx_pi_second_order_loop_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[07] - RW */ 9876 uint32_t tx_pi_jit_ssc_freq_mode : 1; /* TX_PI_RPTR_tx_pi_control_0_t[06] - RW */ 9877 uint32_t tx_pi_ssc_gen_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[05] - RW */ 9878 uint32_t tx_pi_sj_gen_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[04] - RW */ 9879 uint32_t tx_pi_freq_override_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[03] - RW */ 9880 uint32_t tx_pi_ext_ctrl_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[02] - RW */ 9881 uint32_t tx_pi_jitter_filter_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[01] - RW */ 9882 uint32_t tx_pi_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[00] - RW */ 9883 #endif /* IS_BIG_ENDIAN */ 9884 #if IS_LITTLE_ENDIAN 9885 uint32_t tx_pi_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[00] - RW */ 9886 uint32_t tx_pi_jitter_filter_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[01] - RW */ 9887 uint32_t tx_pi_ext_ctrl_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[02] - RW */ 9888 uint32_t tx_pi_freq_override_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[03] - RW */ 9889 uint32_t tx_pi_sj_gen_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[04] - RW */ 9890 uint32_t tx_pi_ssc_gen_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[05] - RW */ 9891 uint32_t tx_pi_jit_ssc_freq_mode : 1; /* TX_PI_RPTR_tx_pi_control_0_t[06] - RW */ 9892 uint32_t tx_pi_second_order_loop_en : 1; /* TX_PI_RPTR_tx_pi_control_0_t[07] - RW */ 9893 uint32_t tx_pi_first_order_bwsel_integ : 2; /* TX_PI_RPTR_tx_pi_control_0_t[09:08] - RW */ 9894 uint32_t tx_pi_second_order_bwsel_integ : 2; /* TX_PI_RPTR_tx_pi_control_0_t[11:10] - RW */ 9895 uint32_t tx_pi_ext_phase_bwsel_integ : 3; /* TX_PI_RPTR_tx_pi_control_0_t[14:12] - RW */ 9896 uint32_t reserved_15 : 1; /* TX_PI_RPTR_tx_pi_control_0_t[15] - RSVD */ 9897 uint32_t reserved : 16; 9898 #endif /* IS_LITTLE_ENDIAN */ 9899 } fields; 9900 } TX_PI_RPTR_tx_pi_control_0_t; 9901 9902 typedef TX_PI_RPTR_tx_pi_control_0_t TX_PI_RPTR_TX_PI_CONTROL_0_t; 9903 9904 typedef union { 9905 uint32_t data; 9906 struct { 9907 #if IS_BIG_ENDIAN 9908 uint32_t reserved : 16; 9909 uint32_t reserved_12 : 4; /* TX_PI_RPTR_tx_pi_control_5_t[15:12] - RSVD */ 9910 uint32_t tx_pi_pd_bypass_vco : 1; /* TX_PI_RPTR_tx_pi_control_5_t[11] - RW */ 9911 uint32_t tx_pi_pd_bypass_flt : 1; /* TX_PI_RPTR_tx_pi_control_5_t[10] - RW */ 9912 uint32_t afe_tx_fifo_resetb_frc : 1; /* TX_PI_RPTR_tx_pi_control_5_t[09] - RW */ 9913 uint32_t afe_tx_fifo_resetb : 1; /* TX_PI_RPTR_tx_pi_control_5_t[08] - RW */ 9914 uint32_t reserved_04 : 4; /* TX_PI_RPTR_tx_pi_control_5_t[07:04] - RSVD */ 9915 uint32_t tx_pi_ext_pd_sel : 1; /* TX_PI_RPTR_tx_pi_control_5_t[03] - RW */ 9916 uint32_t tx_pi_repeater_mode_en : 1; /* TX_PI_RPTR_tx_pi_control_5_t[02] - RW */ 9917 uint32_t tx_pi_hs_fifo_phserr_invert : 1; /* TX_PI_RPTR_tx_pi_control_5_t[01] - RW */ 9918 uint32_t reserved_00 : 1; /* TX_PI_RPTR_tx_pi_control_5_t[00] - RSVD */ 9919 #endif /* IS_BIG_ENDIAN */ 9920 #if IS_LITTLE_ENDIAN 9921 uint32_t reserved_00 : 1; /* TX_PI_RPTR_tx_pi_control_5_t[00] - RSVD */ 9922 uint32_t tx_pi_hs_fifo_phserr_invert : 1; /* TX_PI_RPTR_tx_pi_control_5_t[01] - RW */ 9923 uint32_t tx_pi_repeater_mode_en : 1; /* TX_PI_RPTR_tx_pi_control_5_t[02] - RW */ 9924 uint32_t tx_pi_ext_pd_sel : 1; /* TX_PI_RPTR_tx_pi_control_5_t[03] - RW */ 9925 uint32_t reserved_04 : 4; /* TX_PI_RPTR_tx_pi_control_5_t[07:04] - RSVD */ 9926 uint32_t afe_tx_fifo_resetb : 1; /* TX_PI_RPTR_tx_pi_control_5_t[08] - RW */ 9927 uint32_t afe_tx_fifo_resetb_frc : 1; /* TX_PI_RPTR_tx_pi_control_5_t[09] - RW */ 9928 uint32_t tx_pi_pd_bypass_flt : 1; /* TX_PI_RPTR_tx_pi_control_5_t[10] - RW */ 9929 uint32_t tx_pi_pd_bypass_vco : 1; /* TX_PI_RPTR_tx_pi_control_5_t[11] - RW */ 9930 uint32_t reserved_12 : 4; /* TX_PI_RPTR_tx_pi_control_5_t[15:12] - RSVD */ 9931 uint32_t reserved : 16; 9932 #endif /* IS_LITTLE_ENDIAN */ 9933 } fields; 9934 } TX_PI_RPTR_tx_pi_control_5_t; 9935 9936 typedef TX_PI_RPTR_tx_pi_control_5_t TX_PI_RPTR_TX_PI_CONTROL_5_t; 9937 9938 9939 /*-----------------------------------------------*/ 9940 /* Structs for CL93n72_USER_TX Bank */ 9941 /*-----------------------------------------------*/ 9942 typedef union { 9943 uint32_t data; 9944 struct { 9945 #if IS_BIG_ENDIAN 9946 uint32_t reserved : 16; 9947 uint32_t reserved_14 : 2; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[15:14] - RSVD */ 9948 uint32_t cl93n72_txfir_post : 6; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[13:08] - RW */ 9949 uint32_t reserved_05 : 3; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[07:05] - RSVD */ 9950 uint32_t cl93n72_txfir_pre : 5; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[04:00] - RW */ 9951 #endif /* IS_BIG_ENDIAN */ 9952 #if IS_LITTLE_ENDIAN 9953 uint32_t cl93n72_txfir_pre : 5; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[04:00] - RW */ 9954 uint32_t reserved_05 : 3; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[07:05] - RSVD */ 9955 uint32_t cl93n72_txfir_post : 6; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[13:08] - RW */ 9956 uint32_t reserved_14 : 2; /* CL93n72_USER_TX_cl93n72ut_control2_register_t[15:14] - RSVD */ 9957 uint32_t reserved : 16; 9958 #endif /* IS_LITTLE_ENDIAN */ 9959 } fields; 9960 } CL93n72_USER_TX_cl93n72ut_control2_register_t; 9961 9962 typedef CL93n72_USER_TX_cl93n72ut_control2_register_t CL93N72_USER_TX_CL93N72UT_CONTROL2_REGISTER_t; 9963 9964 typedef union { 9965 uint32_t data; 9966 struct { 9967 #if IS_BIG_ENDIAN 9968 uint32_t reserved : 16; 9969 uint32_t reserved_07 : 9; /* CL93n72_USER_TX_cl93n72ut_control3_register_t[15:07] - RSVD */ 9970 uint32_t cl93n72_txfir_main : 7; /* CL93n72_USER_TX_cl93n72ut_control3_register_t[06:00] - RW */ 9971 #endif /* IS_BIG_ENDIAN */ 9972 #if IS_LITTLE_ENDIAN 9973 uint32_t cl93n72_txfir_main : 7; /* CL93n72_USER_TX_cl93n72ut_control3_register_t[06:00] - RW */ 9974 uint32_t reserved_07 : 9; /* CL93n72_USER_TX_cl93n72ut_control3_register_t[15:07] - RSVD */ 9975 uint32_t reserved : 16; 9976 #endif /* IS_LITTLE_ENDIAN */ 9977 } fields; 9978 } CL93n72_USER_TX_cl93n72ut_control3_register_t; 9979 9980 typedef CL93n72_USER_TX_cl93n72ut_control3_register_t CL93N72_USER_TX_CL93N72UT_CONTROL3_REGISTER_t; 9981 9982 9983 /*-----------------------------------------------*/ 9984 /* Structs for CKRST_CTRL_RPTR Bank */ 9985 /*-----------------------------------------------*/ 9986 typedef union { 9987 uint32_t data; 9988 struct { 9989 #if IS_BIG_ENDIAN 9990 uint32_t reserved : 16; 9991 uint32_t osr_mode_frc : 1; /* CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t[15] - RW */ 9992 uint32_t reserved_04 : 11; /* CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t[14:04] - RSVD */ 9993 uint32_t osr_mode_frc_val : 4; /* CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t[03:00] - RW */ 9994 #endif /* IS_BIG_ENDIAN */ 9995 #if IS_LITTLE_ENDIAN 9996 uint32_t osr_mode_frc_val : 4; /* CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t[03:00] - RW */ 9997 uint32_t reserved_04 : 11; /* CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t[14:04] - RSVD */ 9998 uint32_t osr_mode_frc : 1; /* CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t[15] - RW */ 9999 uint32_t reserved : 16; 10000 #endif /* IS_LITTLE_ENDIAN */ 10001 } fields; 10002 } CKRST_CTRL_RPTR_OSR_MODE_CONTROL_t; 10003 10004 10005 typedef union { 10006 uint32_t data; 10007 struct { 10008 #if IS_BIG_ENDIAN 10009 uint32_t reserved : 16; 10010 uint32_t reserved_05 : 11; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[15:05] - RSVD */ 10011 uint32_t afe_sigdet_pwrdn : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[04] - RW */ 10012 uint32_t ln_tx_s_pwrdn : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[03] - RW */ 10013 uint32_t ln_rx_s_pwrdn : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[02] - RW */ 10014 uint32_t ln_dp_s_rstb : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[01] - RW */ 10015 uint32_t reserved_00 : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[00] - RSVD */ 10016 #endif /* IS_BIG_ENDIAN */ 10017 #if IS_LITTLE_ENDIAN 10018 uint32_t reserved_00 : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[00] - RSVD */ 10019 uint32_t ln_dp_s_rstb : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[01] - RW */ 10020 uint32_t ln_rx_s_pwrdn : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[02] - RW */ 10021 uint32_t ln_tx_s_pwrdn : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[03] - RW */ 10022 uint32_t afe_sigdet_pwrdn : 1; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[04] - RW */ 10023 uint32_t reserved_05 : 11; /* CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t[15:05] - RSVD */ 10024 uint32_t reserved : 16; 10025 #endif /* IS_LITTLE_ENDIAN */ 10026 } fields; 10027 } CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_t; 10028 10029 typedef union { 10030 uint32_t data; 10031 struct { 10032 #if IS_BIG_ENDIAN 10033 uint32_t reserved : 16; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10034 uint32_t reserved_10 : 6; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10035 uint32_t afe_rx_rclk20_pwrdn_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[09] - RW */ 10036 uint32_t afe_rx_rclk20_pwrdn_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[08] - RW */ 10037 uint32_t afe_tx_reset_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[07] - RW */ 10038 uint32_t afe_tx_reset_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[06] - RW */ 10039 uint32_t afe_tx_pwrdn_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[05] - RW */ 10040 uint32_t afe_tx_pwrdn_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[04] - RW */ 10041 uint32_t afe_rx_reset_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 10042 uint32_t afe_rx_reset_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 10043 uint32_t afe_rx_pwrdn_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 10044 uint32_t afe_rx_pwrdn_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 10045 #endif /* IS_BIG_ENDIAN */ 10046 #if IS_LITTLE_ENDIAN 10047 uint32_t afe_rx_pwrdn_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 10048 uint32_t afe_rx_pwrdn_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 10049 uint32_t afe_rx_reset_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 10050 uint32_t afe_rx_reset_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 10051 uint32_t afe_tx_pwrdn_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[04] - RW */ 10052 uint32_t afe_tx_pwrdn_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[05] - RW */ 10053 uint32_t afe_tx_reset_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[06] - RW */ 10054 uint32_t afe_tx_reset_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[07] - RW */ 10055 uint32_t afe_rx_rclk20_pwrdn_frc : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[08] - RW */ 10056 uint32_t afe_rx_rclk20_pwrdn_frc_val : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[09] - RW */ 10057 uint32_t reserved_10 : 6; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10058 uint32_t reserved : 16; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10059 #endif /* IS_LITTLE_ENDIAN */ 10060 } fields; 10061 } CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_t; 10062 10063 10064 typedef union { 10065 uint32_t data; 10066 struct { 10067 #if IS_BIG_ENDIAN 10068 uint32_t reserved : 16; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10069 uint32_t rsrvd : 12; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:04] - RW */ 10070 uint32_t pmd_ln_tx_h_pwrdn_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 10071 uint32_t pmd_ln_rx_h_pwrdn_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 10072 uint32_t pmd_ln_dp_h_rstb_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 10073 uint32_t pmd_ln_h_rstb_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 10074 #endif /* IS_BIG_ENDIAN */ 10075 #if IS_LITTLE_ENDIAN 10076 uint32_t pmd_ln_h_rstb_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[00] - RW */ 10077 uint32_t pmd_ln_dp_h_rstb_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[01] - RW */ 10078 uint32_t pmd_ln_rx_h_pwrdn_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[02] - RW */ 10079 uint32_t pmd_ln_tx_h_pwrdn_pkill : 1; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[03] - RW */ 10080 uint32_t rsrvd : 12; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:04] - RW */ 10081 uint32_t reserved : 16; /* CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_TYPE[15:10] - RSVD */ 10082 #endif /* IS_LITTLE_ENDIAN */ 10083 } fields; 10084 } CKRST_CTRL_RPTR_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_t; 10085 10086 10087 10088 /*-----------------------------------------------*/ 10089 /* Structs for PLL_CAL_COM Bank */ 10090 /*-----------------------------------------------*/ 10091 typedef union { 10092 uint32_t data; 10093 struct { 10094 #if IS_BIG_ENDIAN 10095 uint32_t reserved : 16; 10096 uint32_t vco_start_time : 8; /* PLL_CAL_COM_CTL_0_t[15:08] - RW */ 10097 uint32_t vco_step_time : 8; /* PLL_CAL_COM_CTL_0_t[07:00] - RW */ 10098 #endif /* IS_BIG_ENDIAN */ 10099 #if IS_LITTLE_ENDIAN 10100 uint32_t vco_step_time : 8; /* PLL_CAL_COM_CTL_0_t[07:00] - RW */ 10101 uint32_t vco_start_time : 8; /* PLL_CAL_COM_CTL_0_t[15:08] - RW */ 10102 uint32_t reserved : 16; 10103 #endif /* IS_LITTLE_ENDIAN */ 10104 } fields; 10105 } PLL_CAL_COM_CTL_0_t; 10106 10107 10108 typedef union { 10109 uint32_t data; 10110 struct { 10111 #if IS_BIG_ENDIAN 10112 uint32_t reserved : 16; 10113 uint32_t pre_freq_det_time : 8; /* PLL_CAL_COM_CTL_1_t[15:08] - RW */ 10114 uint32_t retry_time : 8; /* PLL_CAL_COM_CTL_1_t[07:00] - RW */ 10115 #endif /* IS_BIG_ENDIAN */ 10116 #if IS_LITTLE_ENDIAN 10117 uint32_t retry_time : 8; /* PLL_CAL_COM_CTL_1_t[07:00] - RW */ 10118 uint32_t pre_freq_det_time : 8; /* PLL_CAL_COM_CTL_1_t[15:08] - RW */ 10119 uint32_t reserved : 16; 10120 #endif /* IS_LITTLE_ENDIAN */ 10121 } fields; 10122 } PLL_CAL_COM_CTL_1_t; 10123 10124 10125 typedef union { 10126 uint32_t data; 10127 struct { 10128 #if IS_BIG_ENDIAN 10129 uint32_t reserved : 16; 10130 uint32_t res_cal_cntr : 8; /* PLL_CAL_COM_CTL_2_t[15:08] - RW */ 10131 uint32_t win_cal_cntr : 8; /* PLL_CAL_COM_CTL_2_t[07:00] - RW */ 10132 #endif /* IS_BIG_ENDIAN */ 10133 #if IS_LITTLE_ENDIAN 10134 uint32_t win_cal_cntr : 8; /* PLL_CAL_COM_CTL_2_t[07:00] - RW */ 10135 uint32_t res_cal_cntr : 8; /* PLL_CAL_COM_CTL_2_t[15:08] - RW */ 10136 uint32_t reserved : 16; 10137 #endif /* IS_LITTLE_ENDIAN */ 10138 } fields; 10139 } PLL_CAL_COM_CTL_2_t; 10140 10141 10142 typedef union { 10143 uint32_t data; 10144 struct { 10145 #if IS_BIG_ENDIAN 10146 uint32_t reserved : 16; 10147 uint32_t reserved_14 : 2; /* PLL_CAL_COM_CTL_5_t[15:14] - RSVD */ 10148 uint32_t refclk_divcnt : 14; /* PLL_CAL_COM_CTL_5_t[13:00] - RW */ 10149 #endif /* IS_BIG_ENDIAN */ 10150 #if IS_LITTLE_ENDIAN 10151 uint32_t refclk_divcnt : 14; /* PLL_CAL_COM_CTL_5_t[13:00] - RW */ 10152 uint32_t reserved_14 : 2; /* PLL_CAL_COM_CTL_5_t[15:14] - RSVD */ 10153 uint32_t reserved : 16; 10154 #endif /* IS_LITTLE_ENDIAN */ 10155 } fields; 10156 } PLL_CAL_COM_CTL_5_t; 10157 10158 10159 typedef union { 10160 uint32_t data; 10161 struct { 10162 #if IS_BIG_ENDIAN 10163 uint32_t reserved : 16; 10164 uint32_t vco_range_adjust : 5; /* PLL_CAL_COM_CTL_7_t[15:11] - RW */ 10165 uint32_t rescal_frc : 1; /* PLL_CAL_COM_CTL_7_t[10] - RW */ 10166 uint32_t rescal_frc_val : 4; /* PLL_CAL_COM_CTL_7_t[09:06] - RW */ 10167 uint32_t reserved_05 : 1; /* PLL_CAL_COM_CTL_7_t[05] - RSVD */ 10168 uint32_t pll_mode : 5; /* PLL_CAL_COM_CTL_7_t[04:00] - RW */ 10169 #endif /* IS_BIG_ENDIAN */ 10170 #if IS_LITTLE_ENDIAN 10171 uint32_t pll_mode : 5; /* PLL_CAL_COM_CTL_7_t[04:00] - RW */ 10172 uint32_t reserved_05 : 1; /* PLL_CAL_COM_CTL_7_t[05] - RSVD */ 10173 uint32_t rescal_frc_val : 4; /* PLL_CAL_COM_CTL_7_t[09:06] - RW */ 10174 uint32_t rescal_frc : 1; /* PLL_CAL_COM_CTL_7_t[10] - RW */ 10175 uint32_t vco_range_adjust : 5; /* PLL_CAL_COM_CTL_7_t[15:11] - RW */ 10176 uint32_t reserved : 16; 10177 #endif /* IS_LITTLE_ENDIAN */ 10178 } fields; 10179 } PLL_CAL_COM_CTL_7_t; 10180 10181 10182 typedef union { 10183 uint32_t data; 10184 struct { 10185 #if IS_BIG_ENDIAN 10186 uint32_t reserved : 16; 10187 uint32_t lost_pll_lock_sm : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[15] - RO */ 10188 uint32_t cap_done : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[14] - RO */ 10189 uint32_t cap_pass : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[13] - RO */ 10190 uint32_t freq_done_sm : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[12] - RO */ 10191 uint32_t freq_pass_sm : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[11] - RO */ 10192 uint32_t pll_seq_done : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[10] - RO */ 10193 uint32_t pll_seq_pass : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[09] - RO */ 10194 uint32_t pll_lock : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[08] - RO */ 10195 uint32_t reserved_07 : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[07] - RSVD */ 10196 uint32_t cap_done_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[06] - RO */ 10197 uint32_t cap_pass_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[05] - RO */ 10198 uint32_t freq_done_sm_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[04] - RO */ 10199 uint32_t freq_pass_sm_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[03] - RO */ 10200 uint32_t pll_seq_done_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[02] - RO */ 10201 uint32_t pll_seq_pass_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[01] - RO */ 10202 uint32_t pll_lock_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[00] - RO */ 10203 #endif /* IS_BIG_ENDIAN */ 10204 #if IS_LITTLE_ENDIAN 10205 uint32_t pll_lock_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[00] - RO */ 10206 uint32_t pll_seq_pass_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[01] - RO */ 10207 uint32_t pll_seq_done_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[02] - RO */ 10208 uint32_t freq_pass_sm_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[03] - RO */ 10209 uint32_t freq_done_sm_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[04] - RO */ 10210 uint32_t cap_pass_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[05] - RO */ 10211 uint32_t cap_done_lh_ll : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[06] - RO */ 10212 uint32_t reserved_07 : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[07] - RSVD */ 10213 uint32_t pll_lock : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[08] - RO */ 10214 uint32_t pll_seq_pass : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[09] - RO */ 10215 uint32_t pll_seq_done : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[10] - RO */ 10216 uint32_t freq_pass_sm : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[11] - RO */ 10217 uint32_t freq_done_sm : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[12] - RO */ 10218 uint32_t cap_pass : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[13] - RO */ 10219 uint32_t cap_done : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[14] - RO */ 10220 uint32_t lost_pll_lock_sm : 1; /* PLL_CAL_COM_CTL_STATUS_0_t[15] - RO */ 10221 uint32_t reserved : 16; 10222 #endif /* IS_LITTLE_ENDIAN */ 10223 } fields; 10224 } PLL_CAL_COM_CTL_STATUS_0_t; 10225 10226 10227 10228 /*-----------------------------------------------*/ 10229 /* Structs for AMS_COM Bank */ 10230 /*-----------------------------------------------*/ 10231 typedef union { 10232 uint32_t data; 10233 struct { 10234 #if IS_BIG_ENDIAN 10235 uint32_t reserved : 16; 10236 uint32_t ams_pll_enable_ftune : 1; /* AMS_COM_PLL_CONTROL_1_t[15] - RW */ 10237 uint32_t ams_pll_reset : 1; /* AMS_COM_PLL_CONTROL_1_t[14] - RW */ 10238 uint32_t ams_pll_ivco : 3; /* AMS_COM_PLL_CONTROL_1_t[13:11] - RW */ 10239 uint32_t ams_pll_vco_indicator : 1; /* AMS_COM_PLL_CONTROL_1_t[10] - RW */ 10240 uint32_t ams_pll_vcoictrl : 2; /* AMS_COM_PLL_CONTROL_1_t[09:08] - RW */ 10241 uint32_t ams_pll_vco2_15g : 1; /* AMS_COM_PLL_CONTROL_1_t[07] - RW */ 10242 uint32_t ams_pll_spare_22 : 1; /* AMS_COM_PLL_CONTROL_1_t[06] - RW */ 10243 uint32_t ams_pll_test_bg_opamp_bias : 2; /* AMS_COM_PLL_CONTROL_1_t[05:04] - RW */ 10244 uint32_t ams_pll_drv_hv_disable : 1; /* AMS_COM_PLL_CONTROL_1_t[03] - RW */ 10245 uint32_t ams_pll_imode_ickgen : 1; /* AMS_COM_PLL_CONTROL_1_t[02] - RW */ 10246 uint32_t ams_pll_imax_ickgen : 1; /* AMS_COM_PLL_CONTROL_1_t[01] - RW */ 10247 uint32_t ams_pll_imin_ickgen : 1; /* AMS_COM_PLL_CONTROL_1_t[00] - RW */ 10248 #endif /* IS_BIG_ENDIAN */ 10249 #if IS_LITTLE_ENDIAN 10250 uint32_t ams_pll_imin_ickgen : 1; /* AMS_COM_PLL_CONTROL_1_t[00] - RW */ 10251 uint32_t ams_pll_imax_ickgen : 1; /* AMS_COM_PLL_CONTROL_1_t[01] - RW */ 10252 uint32_t ams_pll_imode_ickgen : 1; /* AMS_COM_PLL_CONTROL_1_t[02] - RW */ 10253 uint32_t ams_pll_drv_hv_disable : 1; /* AMS_COM_PLL_CONTROL_1_t[03] - RW */ 10254 uint32_t ams_pll_test_bg_opamp_bias : 2; /* AMS_COM_PLL_CONTROL_1_t[05:04] - RW */ 10255 uint32_t ams_pll_spare_22 : 1; /* AMS_COM_PLL_CONTROL_1_t[06] - RW */ 10256 uint32_t ams_pll_vco2_15g : 1; /* AMS_COM_PLL_CONTROL_1_t[07] - RW */ 10257 uint32_t ams_pll_vcoictrl : 2; /* AMS_COM_PLL_CONTROL_1_t[09:08] - RW */ 10258 uint32_t ams_pll_vco_indicator : 1; /* AMS_COM_PLL_CONTROL_1_t[10] - RW */ 10259 uint32_t ams_pll_ivco : 3; /* AMS_COM_PLL_CONTROL_1_t[13:11] - RW */ 10260 uint32_t ams_pll_reset : 1; /* AMS_COM_PLL_CONTROL_1_t[14] - RW */ 10261 uint32_t ams_pll_enable_ftune : 1; /* AMS_COM_PLL_CONTROL_1_t[15] - RW */ 10262 uint32_t reserved : 16; 10263 #endif /* IS_LITTLE_ENDIAN */ 10264 } fields; 10265 } AMS_COM_PLL_CONTROL_1_t; 10266 10267 10268 typedef union { 10269 uint32_t data; 10270 struct { 10271 #if IS_BIG_ENDIAN 10272 uint32_t reserved : 16; 10273 uint32_t ams_pll_test_rx : 1; /* AMS_COM_PLL_CONTROL_3_t[15] - RW */ 10274 uint32_t ams_pll_test_pll : 1; /* AMS_COM_PLL_CONTROL_3_t[14] - RW */ 10275 uint32_t reserved_13 : 1; /* AMS_COM_PLL_CONTROL_3_t[13] - RSVD */ 10276 uint32_t reserved_12 : 1; /* AMS_COM_PLL_CONTROL_3_t[12] - RSVD */ 10277 uint32_t reserved_11 : 1; /* AMS_COM_PLL_CONTROL_3_t[11] - RSVD */ 10278 uint32_t reserved_10 : 1; /* AMS_COM_PLL_CONTROL_3_t[10] - RSVD */ 10279 uint32_t reserved_09 : 1; /* AMS_COM_PLL_CONTROL_3_t[09] - RSVD */ 10280 uint32_t reserved_08 : 1; /* AMS_COM_PLL_CONTROL_3_t[08] - RSVD */ 10281 uint32_t reserved_07 : 1; /* AMS_COM_PLL_CONTROL_3_t[07] - RSVD */ 10282 uint32_t reserved_06 : 1; /* AMS_COM_PLL_CONTROL_3_t[06] - RSVD */ 10283 uint32_t reserved_05 : 1; /* AMS_COM_PLL_CONTROL_3_t[05] - RSVD */ 10284 uint32_t reserved_04 : 1; /* AMS_COM_PLL_CONTROL_3_t[04] - RSVD */ 10285 uint32_t reserved_03 : 1; /* AMS_COM_PLL_CONTROL_3_t[03] - RSVD */ 10286 uint32_t reserved_02 : 1; /* AMS_COM_PLL_CONTROL_3_t[02] - RSVD */ 10287 uint32_t reserved_01 : 1; /* AMS_COM_PLL_CONTROL_3_t[01] - RSVD */ 10288 uint32_t reserved_00 : 1; /* AMS_COM_PLL_CONTROL_3_t[00] - RSVD */ 10289 #endif /* IS_BIG_ENDIAN */ 10290 #if IS_LITTLE_ENDIAN 10291 uint32_t reserved_00 : 1; /* AMS_COM_PLL_CONTROL_3_t[00] - RSVD */ 10292 uint32_t reserved_01 : 1; /* AMS_COM_PLL_CONTROL_3_t[01] - RSVD */ 10293 uint32_t reserved_02 : 1; /* AMS_COM_PLL_CONTROL_3_t[02] - RSVD */ 10294 uint32_t reserved_03 : 1; /* AMS_COM_PLL_CONTROL_3_t[03] - RSVD */ 10295 uint32_t reserved_04 : 1; /* AMS_COM_PLL_CONTROL_3_t[04] - RSVD */ 10296 uint32_t reserved_05 : 1; /* AMS_COM_PLL_CONTROL_3_t[05] - RSVD */ 10297 uint32_t reserved_06 : 1; /* AMS_COM_PLL_CONTROL_3_t[06] - RSVD */ 10298 uint32_t reserved_07 : 1; /* AMS_COM_PLL_CONTROL_3_t[07] - RSVD */ 10299 uint32_t reserved_08 : 1; /* AMS_COM_PLL_CONTROL_3_t[08] - RSVD */ 10300 uint32_t reserved_09 : 1; /* AMS_COM_PLL_CONTROL_3_t[09] - RSVD */ 10301 uint32_t reserved_10 : 1; /* AMS_COM_PLL_CONTROL_3_t[10] - RSVD */ 10302 uint32_t reserved_11 : 1; /* AMS_COM_PLL_CONTROL_3_t[11] - RSVD */ 10303 uint32_t reserved_12 : 1; /* AMS_COM_PLL_CONTROL_3_t[12] - RSVD */ 10304 uint32_t reserved_13 : 1; /* AMS_COM_PLL_CONTROL_3_t[13] - RSVD */ 10305 uint32_t ams_pll_test_pll : 1; /* AMS_COM_PLL_CONTROL_3_t[14] - RW */ 10306 uint32_t ams_pll_test_rx : 1; /* AMS_COM_PLL_CONTROL_3_t[15] - RW */ 10307 uint32_t reserved : 16; 10308 #endif /* IS_LITTLE_ENDIAN */ 10309 } fields; 10310 } AMS_COM_PLL_CONTROL_3_t; 10311 10312 10313 10314 /*-----------------------------------------------*/ 10315 /* Structs for PATT_GEN_COM Bank */ 10316 /*-----------------------------------------------*/ 10317 typedef union { 10318 uint32_t data; 10319 struct { 10320 #if IS_BIG_ENDIAN 10321 uint32_t reserved : 16; 10322 uint32_t patt_gen_seq_0 : 16; /* PATT_GEN_COM_patt_gen_seq_0_t[15:00] - RW */ 10323 #endif /* IS_BIG_ENDIAN */ 10324 #if IS_LITTLE_ENDIAN 10325 uint32_t patt_gen_seq_0 : 16; /* PATT_GEN_COM_patt_gen_seq_0_t[15:00] - RW */ 10326 uint32_t reserved : 16; 10327 #endif /* IS_LITTLE_ENDIAN */ 10328 } fields; 10329 } PATT_GEN_COM_patt_gen_seq_0_t; 10330 10331 typedef PATT_GEN_COM_patt_gen_seq_0_t PATT_GEN_COM_PATT_GEN_SEQ_0_t; 10332 10333 typedef union { 10334 uint32_t data; 10335 struct { 10336 #if IS_BIG_ENDIAN 10337 uint32_t reserved : 16; 10338 uint32_t patt_gen_seq_1 : 16; /* PATT_GEN_COM_patt_gen_seq_1_t[15:00] - RW */ 10339 #endif /* IS_BIG_ENDIAN */ 10340 #if IS_LITTLE_ENDIAN 10341 uint32_t patt_gen_seq_1 : 16; /* PATT_GEN_COM_patt_gen_seq_1_t[15:00] - RW */ 10342 uint32_t reserved : 16; 10343 #endif /* IS_LITTLE_ENDIAN */ 10344 } fields; 10345 } PATT_GEN_COM_patt_gen_seq_1_t; 10346 10347 typedef PATT_GEN_COM_patt_gen_seq_1_t PATT_GEN_COM_PATT_GEN_SEQ_1_t; 10348 10349 typedef union { 10350 uint32_t data; 10351 struct { 10352 #if IS_BIG_ENDIAN 10353 uint32_t reserved : 16; 10354 uint32_t patt_gen_seq_2 : 16; /* PATT_GEN_COM_patt_gen_seq_2_t[15:00] - RW */ 10355 #endif /* IS_BIG_ENDIAN */ 10356 #if IS_LITTLE_ENDIAN 10357 uint32_t patt_gen_seq_2 : 16; /* PATT_GEN_COM_patt_gen_seq_2_t[15:00] - RW */ 10358 uint32_t reserved : 16; 10359 #endif /* IS_LITTLE_ENDIAN */ 10360 } fields; 10361 } PATT_GEN_COM_patt_gen_seq_2_t; 10362 10363 typedef PATT_GEN_COM_patt_gen_seq_2_t PATT_GEN_COM_PATT_GEN_SEQ_2_t; 10364 10365 typedef union { 10366 uint32_t data; 10367 struct { 10368 #if IS_BIG_ENDIAN 10369 uint32_t reserved : 16; 10370 uint32_t patt_gen_seq_3 : 16; /* PATT_GEN_COM_patt_gen_seq_3_t[15:00] - RW */ 10371 #endif /* IS_BIG_ENDIAN */ 10372 #if IS_LITTLE_ENDIAN 10373 uint32_t patt_gen_seq_3 : 16; /* PATT_GEN_COM_patt_gen_seq_3_t[15:00] - RW */ 10374 uint32_t reserved : 16; 10375 #endif /* IS_LITTLE_ENDIAN */ 10376 } fields; 10377 } PATT_GEN_COM_patt_gen_seq_3_t; 10378 10379 typedef PATT_GEN_COM_patt_gen_seq_3_t PATT_GEN_COM_PATT_GEN_SEQ_3_t; 10380 10381 typedef union { 10382 uint32_t data; 10383 struct { 10384 #if IS_BIG_ENDIAN 10385 uint32_t reserved : 16; 10386 uint32_t patt_gen_seq_4 : 16; /* PATT_GEN_COM_patt_gen_seq_4_t[15:00] - RW */ 10387 #endif /* IS_BIG_ENDIAN */ 10388 #if IS_LITTLE_ENDIAN 10389 uint32_t patt_gen_seq_4 : 16; /* PATT_GEN_COM_patt_gen_seq_4_t[15:00] - RW */ 10390 uint32_t reserved : 16; 10391 #endif /* IS_LITTLE_ENDIAN */ 10392 } fields; 10393 } PATT_GEN_COM_patt_gen_seq_4_t; 10394 10395 typedef PATT_GEN_COM_patt_gen_seq_4_t PATT_GEN_COM_PATT_GEN_SEQ_4_t; 10396 10397 typedef union { 10398 uint32_t data; 10399 struct { 10400 #if IS_BIG_ENDIAN 10401 uint32_t reserved : 16; 10402 uint32_t patt_gen_seq_5 : 16; /* PATT_GEN_COM_patt_gen_seq_5_t[15:00] - RW */ 10403 #endif /* IS_BIG_ENDIAN */ 10404 #if IS_LITTLE_ENDIAN 10405 uint32_t patt_gen_seq_5 : 16; /* PATT_GEN_COM_patt_gen_seq_5_t[15:00] - RW */ 10406 uint32_t reserved : 16; 10407 #endif /* IS_LITTLE_ENDIAN */ 10408 } fields; 10409 } PATT_GEN_COM_patt_gen_seq_5_t; 10410 10411 typedef PATT_GEN_COM_patt_gen_seq_5_t PATT_GEN_COM_PATT_GEN_SEQ_5_t; 10412 10413 typedef union { 10414 uint32_t data; 10415 struct { 10416 #if IS_BIG_ENDIAN 10417 uint32_t reserved : 16; 10418 uint32_t patt_gen_seq_6 : 16; /* PATT_GEN_COM_patt_gen_seq_6_t[15:00] - RW */ 10419 #endif /* IS_BIG_ENDIAN */ 10420 #if IS_LITTLE_ENDIAN 10421 uint32_t patt_gen_seq_6 : 16; /* PATT_GEN_COM_patt_gen_seq_6_t[15:00] - RW */ 10422 uint32_t reserved : 16; 10423 #endif /* IS_LITTLE_ENDIAN */ 10424 } fields; 10425 } PATT_GEN_COM_patt_gen_seq_6_t; 10426 10427 typedef PATT_GEN_COM_patt_gen_seq_6_t PATT_GEN_COM_PATT_GEN_SEQ_6_t; 10428 10429 typedef union { 10430 uint32_t data; 10431 struct { 10432 #if IS_BIG_ENDIAN 10433 uint32_t reserved : 16; 10434 uint32_t patt_gen_seq_7 : 16; /* PATT_GEN_COM_patt_gen_seq_7_t[15:00] - RW */ 10435 #endif /* IS_BIG_ENDIAN */ 10436 #if IS_LITTLE_ENDIAN 10437 uint32_t patt_gen_seq_7 : 16; /* PATT_GEN_COM_patt_gen_seq_7_t[15:00] - RW */ 10438 uint32_t reserved : 16; 10439 #endif /* IS_LITTLE_ENDIAN */ 10440 } fields; 10441 } PATT_GEN_COM_patt_gen_seq_7_t; 10442 10443 typedef PATT_GEN_COM_patt_gen_seq_7_t PATT_GEN_COM_PATT_GEN_SEQ_7_t; 10444 10445 typedef union { 10446 uint32_t data; 10447 struct { 10448 #if IS_BIG_ENDIAN 10449 uint32_t reserved : 16; 10450 uint32_t patt_gen_seq_8 : 16; /* PATT_GEN_COM_patt_gen_seq_8_t[15:00] - RW */ 10451 #endif /* IS_BIG_ENDIAN */ 10452 #if IS_LITTLE_ENDIAN 10453 uint32_t patt_gen_seq_8 : 16; /* PATT_GEN_COM_patt_gen_seq_8_t[15:00] - RW */ 10454 uint32_t reserved : 16; 10455 #endif /* IS_LITTLE_ENDIAN */ 10456 } fields; 10457 } PATT_GEN_COM_patt_gen_seq_8_t; 10458 10459 typedef PATT_GEN_COM_patt_gen_seq_8_t PATT_GEN_COM_PATT_GEN_SEQ_8_t; 10460 10461 typedef union { 10462 uint32_t data; 10463 struct { 10464 #if IS_BIG_ENDIAN 10465 uint32_t reserved : 16; 10466 uint32_t patt_gen_seq_9 : 16; /* PATT_GEN_COM_patt_gen_seq_9_t[15:00] - RW */ 10467 #endif /* IS_BIG_ENDIAN */ 10468 #if IS_LITTLE_ENDIAN 10469 uint32_t patt_gen_seq_9 : 16; /* PATT_GEN_COM_patt_gen_seq_9_t[15:00] - RW */ 10470 uint32_t reserved : 16; 10471 #endif /* IS_LITTLE_ENDIAN */ 10472 } fields; 10473 } PATT_GEN_COM_patt_gen_seq_9_t; 10474 10475 typedef PATT_GEN_COM_patt_gen_seq_9_t PATT_GEN_COM_PATT_GEN_SEQ_9_t; 10476 10477 typedef union { 10478 uint32_t data; 10479 struct { 10480 #if IS_BIG_ENDIAN 10481 uint32_t reserved : 16; 10482 uint32_t patt_gen_seq_10 : 16; /* PATT_GEN_COM_patt_gen_seq_10_t[15:00] - RW */ 10483 #endif /* IS_BIG_ENDIAN */ 10484 #if IS_LITTLE_ENDIAN 10485 uint32_t patt_gen_seq_10 : 16; /* PATT_GEN_COM_patt_gen_seq_10_t[15:00] - RW */ 10486 uint32_t reserved : 16; 10487 #endif /* IS_LITTLE_ENDIAN */ 10488 } fields; 10489 } PATT_GEN_COM_patt_gen_seq_10_t; 10490 10491 typedef PATT_GEN_COM_patt_gen_seq_10_t PATT_GEN_COM_PATT_GEN_SEQ_10_t; 10492 10493 typedef union { 10494 uint32_t data; 10495 struct { 10496 #if IS_BIG_ENDIAN 10497 uint32_t reserved : 16; 10498 uint32_t patt_gen_seq_11 : 16; /* PATT_GEN_COM_patt_gen_seq_11_t[15:00] - RW */ 10499 #endif /* IS_BIG_ENDIAN */ 10500 #if IS_LITTLE_ENDIAN 10501 uint32_t patt_gen_seq_11 : 16; /* PATT_GEN_COM_patt_gen_seq_11_t[15:00] - RW */ 10502 uint32_t reserved : 16; 10503 #endif /* IS_LITTLE_ENDIAN */ 10504 } fields; 10505 } PATT_GEN_COM_patt_gen_seq_11_t; 10506 10507 typedef PATT_GEN_COM_patt_gen_seq_11_t PATT_GEN_COM_PATT_GEN_SEQ_11_t; 10508 10509 typedef union { 10510 uint32_t data; 10511 struct { 10512 #if IS_BIG_ENDIAN 10513 uint32_t reserved : 16; 10514 uint32_t patt_gen_seq_12 : 16; /* PATT_GEN_COM_patt_gen_seq_12_t[15:00] - RW */ 10515 #endif /* IS_BIG_ENDIAN */ 10516 #if IS_LITTLE_ENDIAN 10517 uint32_t patt_gen_seq_12 : 16; /* PATT_GEN_COM_patt_gen_seq_12_t[15:00] - RW */ 10518 uint32_t reserved : 16; 10519 #endif /* IS_LITTLE_ENDIAN */ 10520 } fields; 10521 } PATT_GEN_COM_patt_gen_seq_12_t; 10522 10523 typedef PATT_GEN_COM_patt_gen_seq_12_t PATT_GEN_COM_PATT_GEN_SEQ_12_t; 10524 10525 typedef union { 10526 uint32_t data; 10527 struct { 10528 #if IS_BIG_ENDIAN 10529 uint32_t reserved : 16; 10530 uint32_t patt_gen_seq_13 : 16; /* PATT_GEN_COM_patt_gen_seq_13_t[15:00] - RW */ 10531 #endif /* IS_BIG_ENDIAN */ 10532 #if IS_LITTLE_ENDIAN 10533 uint32_t patt_gen_seq_13 : 16; /* PATT_GEN_COM_patt_gen_seq_13_t[15:00] - RW */ 10534 uint32_t reserved : 16; 10535 #endif /* IS_LITTLE_ENDIAN */ 10536 } fields; 10537 } PATT_GEN_COM_patt_gen_seq_13_t; 10538 10539 typedef PATT_GEN_COM_patt_gen_seq_13_t PATT_GEN_COM_PATT_GEN_SEQ_13_t; 10540 10541 typedef union { 10542 uint32_t data; 10543 struct { 10544 #if IS_BIG_ENDIAN 10545 uint32_t reserved : 16; 10546 uint32_t patt_gen_seq_14 : 16; /* PATT_GEN_COM_patt_gen_seq_14_t[15:00] - RW */ 10547 #endif /* IS_BIG_ENDIAN */ 10548 #if IS_LITTLE_ENDIAN 10549 uint32_t patt_gen_seq_14 : 16; /* PATT_GEN_COM_patt_gen_seq_14_t[15:00] - RW */ 10550 uint32_t reserved : 16; 10551 #endif /* IS_LITTLE_ENDIAN */ 10552 } fields; 10553 } PATT_GEN_COM_patt_gen_seq_14_t; 10554 10555 typedef PATT_GEN_COM_patt_gen_seq_14_t PATT_GEN_COM_PATT_GEN_SEQ_14_t; 10556 10557 10558 /*-----------------------------------------------*/ 10559 /* Structs for TX_FED Bank */ 10560 /*-----------------------------------------------*/ 10561 typedef union { 10562 uint32_t data; 10563 struct { 10564 #if IS_BIG_ENDIAN 10565 uint32_t reserved : 16; 10566 uint32_t reserved_12 : 4; /* TX_FED_txfir_control1_t[15:12] - RSVD */ 10567 uint32_t reserved_08 : 4; /* TX_FED_txfir_control1_t[11:08] - RSVD */ 10568 uint32_t reserved_05 : 3; /* TX_FED_txfir_control1_t[07:05] - RSVD */ 10569 int32_t txfir_post2 : 5; /* TX_FED_txfir_control1_t[04:00] - RW */ 10570 #endif /* IS_BIG_ENDIAN */ 10571 #if IS_LITTLE_ENDIAN 10572 int32_t txfir_post2 : 5; /* TX_FED_txfir_control1_t[04:00] - RW */ 10573 uint32_t reserved_05 : 3; /* TX_FED_txfir_control1_t[07:05] - RSVD */ 10574 uint32_t reserved_08 : 4; /* TX_FED_txfir_control1_t[11:08] - RSVD */ 10575 uint32_t reserved_12 : 4; /* TX_FED_txfir_control1_t[15:12] - RSVD */ 10576 uint32_t reserved : 16; 10577 #endif /* IS_LITTLE_ENDIAN */ 10578 } fields; 10579 } TX_FED_txfir_control1_t; 10580 10581 typedef TX_FED_txfir_control1_t TX_FED_TXFIR_CONTROL1_t; 10582 10583 typedef union { 10584 uint32_t data; 10585 struct { 10586 #if IS_BIG_ENDIAN 10587 uint32_t reserved : 16; 10588 uint32_t reserved_12 : 4; /* TX_FED_txfir_control2_t[15:12] - RSVD */ 10589 uint32_t reserved_08 : 4; /* TX_FED_txfir_control2_t[11:08] - RSVD */ 10590 uint32_t reserved_04 : 4; /* TX_FED_txfir_control2_t[07:04] - RSVD */ 10591 int32_t txfir_post3 : 4; /* TX_FED_txfir_control2_t[03:00] - RW */ 10592 #endif /* IS_BIG_ENDIAN */ 10593 #if IS_LITTLE_ENDIAN 10594 int32_t txfir_post3 : 4; /* TX_FED_txfir_control2_t[03:00] - RW */ 10595 uint32_t reserved_04 : 4; /* TX_FED_txfir_control2_t[07:04] - RSVD */ 10596 uint32_t reserved_08 : 4; /* TX_FED_txfir_control2_t[11:08] - RSVD */ 10597 uint32_t reserved_12 : 4; /* TX_FED_txfir_control2_t[15:12] - RSVD */ 10598 uint32_t reserved : 16; 10599 #endif /* IS_LITTLE_ENDIAN */ 10600 } fields; 10601 } TX_FED_txfir_control2_t; 10602 10603 typedef TX_FED_txfir_control2_t TX_FED_TXFIR_CONTROL2_t; 10604 10605 typedef union { 10606 uint32_t data; 10607 struct { 10608 #if IS_BIG_ENDIAN 10609 uint32_t reserved_13 : 3; /* TX_FED_txfir_misc_control1_t[15:13] - RSVD */ 10610 uint32_t dp_reset_tx_disable_dis : 1; /* TX_FED_txfir_misc_control1_t[12] - RW */ 10611 uint32_t tx_disable_output_sel : 2; /* TX_FED_txfir_misc_control1_t[11:10] - RW */ 10612 uint32_t tx_eee_alert_en : 1; /* TX_FED_txfir_misc_control1_t[09] - RW */ 10613 uint32_t tx_eee_quiet_en : 1; /* TX_FED_txfir_misc_control1_t[08] - RW */ 10614 uint32_t tx_disable_timer_ctrl : 6; /* TX_FED_txfir_misc_control1_t[07:02] - RW */ 10615 uint32_t pmd_tx_disable_pin_dis : 1; /* TX_FED_txfir_misc_control1_t[01] - RW */ 10616 uint32_t sdk_tx_disable : 1; /* TX_FED_txfir_misc_control1_t[00] - RW */ 10617 #endif /* IS_BIG_ENDIAN */ 10618 #if IS_LITTLE_ENDIAN 10619 uint32_t sdk_tx_disable : 1; /* TX_FED_txfir_misc_control1_t[00] - RW */ 10620 uint32_t pmd_tx_disable_pin_dis : 1; /* TX_FED_txfir_misc_control1_t[01] - RW */ 10621 uint32_t tx_disable_timer_ctrl : 6; /* TX_FED_txfir_misc_control1_t[07:02] - RW */ 10622 uint32_t tx_eee_quiet_en : 1; /* TX_FED_txfir_misc_control1_t[08] - RW */ 10623 uint32_t tx_eee_alert_en : 1; /* TX_FED_txfir_misc_control1_t[09] - RW */ 10624 uint32_t tx_disable_output_sel : 2; /* TX_FED_txfir_misc_control1_t[11:10] - RW */ 10625 uint32_t dp_reset_tx_disable_dis : 1; /* TX_FED_txfir_misc_control1_t[12] - RW */ 10626 uint32_t reserved_13 : 3; /* TX_FED_txfir_misc_control1_t[15:13] - RSVD */ 10627 uint32_t reserved : 16; 10628 #endif /* IS_LITTLE_ENDIAN */ 10629 } fields; 10630 } TX_FED_txfir_misc_control1_t; 10631 10632 typedef TX_FED_txfir_misc_control1_t TX_FED_TXFIR_MISC_CONTROL1_t; 10633 10634 10635 /*-----------------------------------------------*/ 10636 /* Structs for TLB_RX Bank */ 10637 /*-----------------------------------------------*/ 10638 typedef union { 10639 uint32_t data; 10640 struct { 10641 #if IS_BIG_ENDIAN 10642 uint32_t reserved : 16; 10643 uint32_t reserved_13 : 3; /* TLB_RX_prbs_chk_cnt_config_t[15:13] - RSVD */ 10644 uint32_t prbs_chk_ool_cnt : 5; /* TLB_RX_prbs_chk_cnt_config_t[12:08] - RW */ 10645 uint32_t reserved_05 : 3; /* TLB_RX_prbs_chk_cnt_config_t[07:05] - RSVD */ 10646 uint32_t prbs_chk_lock_cnt : 5; /* TLB_RX_prbs_chk_cnt_config_t[04:00] - RW */ 10647 #endif /* IS_BIG_ENDIAN */ 10648 #if IS_LITTLE_ENDIAN 10649 uint32_t prbs_chk_lock_cnt : 5; /* TLB_RX_prbs_chk_cnt_config_t[04:00] - RW */ 10650 uint32_t reserved_05 : 3; /* TLB_RX_prbs_chk_cnt_config_t[07:05] - RSVD */ 10651 uint32_t prbs_chk_ool_cnt : 5; /* TLB_RX_prbs_chk_cnt_config_t[12:08] - RW */ 10652 uint32_t reserved_13 : 3; /* TLB_RX_prbs_chk_cnt_config_t[15:13] - RSVD */ 10653 uint32_t reserved : 16; 10654 #endif /* IS_LITTLE_ENDIAN */ 10655 } fields; 10656 } TLB_RX_prbs_chk_cnt_config_t; 10657 10658 typedef TLB_RX_prbs_chk_cnt_config_t TLB_RX_PRBS_CHK_CNT_CONFIG_t; 10659 10660 typedef union { 10661 uint32_t data; 10662 struct { 10663 #if IS_BIG_ENDIAN 10664 uint32_t reserved : 16; 10665 uint32_t reserved_12 : 4; /* TLB_RX_prbs_chk_config_t[15:12] - RSVD */ 10666 uint32_t prbs_chk_clk_en_frc_on : 1; /* TLB_RX_prbs_chk_config_t[11] - RW */ 10667 uint32_t reserved_10 : 1; /* TLB_RX_prbs_chk_config_t[10] - RSVD */ 10668 uint32_t reserved_09 : 1; /* TLB_RX_prbs_chk_config_t[09] - RSVD */ 10669 uint32_t reserved_08 : 1; /* TLB_RX_prbs_chk_config_t[08] - RSVD */ 10670 uint32_t prbs_chk_en_auto_mode : 1; /* TLB_RX_prbs_chk_config_t[07] - RW */ 10671 uint32_t prbs_chk_mode : 2; /* TLB_RX_prbs_chk_config_t[06:05] - RW */ 10672 uint32_t prbs_chk_inv : 1; /* TLB_RX_prbs_chk_config_t[04] - RW */ 10673 uint32_t prbs_chk_mode_sel : 3; /* TLB_RX_prbs_chk_config_t[03:01] - RW */ 10674 uint32_t prbs_chk_en : 1; /* TLB_RX_prbs_chk_config_t[00] - RW */ 10675 #endif /* IS_BIG_ENDIAN */ 10676 #if IS_LITTLE_ENDIAN 10677 uint32_t prbs_chk_en : 1; /* TLB_RX_prbs_chk_config_t[00] - RW */ 10678 uint32_t prbs_chk_mode_sel : 3; /* TLB_RX_prbs_chk_config_t[03:01] - RW */ 10679 uint32_t prbs_chk_inv : 1; /* TLB_RX_prbs_chk_config_t[04] - RW */ 10680 uint32_t prbs_chk_mode : 2; /* TLB_RX_prbs_chk_config_t[06:05] - RW */ 10681 uint32_t prbs_chk_en_auto_mode : 1; /* TLB_RX_prbs_chk_config_t[07] - RW */ 10682 uint32_t reserved_08 : 1; /* TLB_RX_prbs_chk_config_t[08] - RSVD */ 10683 uint32_t reserved_09 : 1; /* TLB_RX_prbs_chk_config_t[09] - RSVD */ 10684 uint32_t reserved_10 : 1; /* TLB_RX_prbs_chk_config_t[10] - RSVD */ 10685 uint32_t prbs_chk_clk_en_frc_on : 1; /* TLB_RX_prbs_chk_config_t[11] - RW */ 10686 uint32_t reserved_12 : 4; /* TLB_RX_prbs_chk_config_t[15:12] - RSVD */ 10687 uint32_t reserved : 16; 10688 #endif /* IS_LITTLE_ENDIAN */ 10689 } fields; 10690 } TLB_RX_prbs_chk_config_t; 10691 10692 typedef TLB_RX_prbs_chk_config_t TLB_RX_PRBS_CHK_CONFIG_t; 10693 10694 typedef union { 10695 uint32_t data; 10696 struct { 10697 #if IS_BIG_ENDIAN 10698 uint32_t reserved : 16; 10699 uint32_t reserved_04 : 12; /* TLB_RX_dig_lpbk_config_t[15:04] - RSVD */ 10700 uint32_t reserved_03 : 1; /* TLB_RX_dig_lpbk_config_t[03] - RSVD */ 10701 uint32_t reserved_02 : 1; /* TLB_RX_dig_lpbk_config_t[02] - RSVD */ 10702 uint32_t reserved_01 : 1; /* TLB_RX_dig_lpbk_config_t[01] - RSVD */ 10703 uint32_t dig_lpbk_en : 1; /* TLB_RX_dig_lpbk_config_t[00] - RW */ 10704 #endif /* IS_BIG_ENDIAN */ 10705 #if IS_LITTLE_ENDIAN 10706 uint32_t dig_lpbk_en : 1; /* TLB_RX_dig_lpbk_config_t[00] - RW */ 10707 uint32_t reserved_01 : 1; /* TLB_RX_dig_lpbk_config_t[01] - RSVD */ 10708 uint32_t reserved_02 : 1; /* TLB_RX_dig_lpbk_config_t[02] - RSVD */ 10709 uint32_t reserved_03 : 1; /* TLB_RX_dig_lpbk_config_t[03] - RSVD */ 10710 uint32_t reserved_04 : 12; /* TLB_RX_dig_lpbk_config_t[15:04] - RSVD */ 10711 uint32_t reserved : 16; 10712 #endif /* IS_LITTLE_ENDIAN */ 10713 } fields; 10714 } TLB_RX_dig_lpbk_config_t; 10715 10716 typedef TLB_RX_dig_lpbk_config_t TLB_RX_DIG_LPBK_CONFIG_t; 10717 10718 typedef union { 10719 uint32_t data; 10720 struct { 10721 #if IS_BIG_ENDIAN 10722 uint32_t reserved : 16; 10723 uint32_t reserved_04 : 12; /* TLB_RX_tlb_rx_misc_config_t[15:04] - RSVD */ 10724 uint32_t reserved_03 : 1; /* TLB_RX_tlb_rx_misc_config_t[03] - RSVD */ 10725 uint32_t reserved_02 : 1; /* TLB_RX_tlb_rx_misc_config_t[02] - RSVD */ 10726 uint32_t reserved_01 : 1; /* TLB_RX_tlb_rx_misc_config_t[01] - RSVD */ 10727 uint32_t rx_pmd_dp_invert : 1; /* TLB_RX_tlb_rx_misc_config_t[00] - RW */ 10728 #endif /* IS_BIG_ENDIAN */ 10729 #if IS_LITTLE_ENDIAN 10730 uint32_t rx_pmd_dp_invert : 1; /* TLB_RX_tlb_rx_misc_config_t[00] - RW */ 10731 uint32_t reserved_01 : 1; /* TLB_RX_tlb_rx_misc_config_t[01] - RSVD */ 10732 uint32_t reserved_02 : 1; /* TLB_RX_tlb_rx_misc_config_t[02] - RSVD */ 10733 uint32_t reserved_03 : 1; /* TLB_RX_tlb_rx_misc_config_t[03] - RSVD */ 10734 uint32_t reserved_04 : 12; /* TLB_RX_tlb_rx_misc_config_t[15:04] - RSVD */ 10735 uint32_t reserved : 16; 10736 #endif /* IS_LITTLE_ENDIAN */ 10737 } fields; 10738 } TLB_RX_tlb_rx_misc_config_t; 10739 10740 typedef TLB_RX_tlb_rx_misc_config_t TLB_RX_TLB_RX_MISC_CONFIG_t; 10741 10742 typedef union { 10743 uint32_t data; 10744 struct { 10745 #if IS_BIG_ENDIAN 10746 uint32_t reserved : 16; 10747 uint32_t reserved_01 : 15; /* TLB_RX_prbs_chk_lock_status_t[15:01] - RSVD */ 10748 uint32_t prbs_chk_lock : 1; /* TLB_RX_prbs_chk_lock_status_t[00] - RO */ 10749 #endif /* IS_BIG_ENDIAN */ 10750 #if IS_LITTLE_ENDIAN 10751 uint32_t prbs_chk_lock : 1; /* TLB_RX_prbs_chk_lock_status_t[00] - RO */ 10752 uint32_t reserved_01 : 15; /* TLB_RX_prbs_chk_lock_status_t[15:01] - RSVD */ 10753 uint32_t reserved : 16; 10754 #endif /* IS_LITTLE_ENDIAN */ 10755 } fields; 10756 } TLB_RX_prbs_chk_lock_status_t; 10757 10758 typedef TLB_RX_prbs_chk_lock_status_t TLB_RX_PRBS_CHK_LOCK_STATUS_t; 10759 10760 typedef union { 10761 uint32_t data; 10762 struct { 10763 #if IS_BIG_ENDIAN 10764 uint32_t reserved : 16; 10765 uint32_t prbs_chk_lock_lost_lh : 1; /* TLB_RX_prbs_chk_err_cnt_msb_status_t[15] - RO */ 10766 uint32_t prbs_chk_err_cnt_msb : 15; /* TLB_RX_prbs_chk_err_cnt_msb_status_t[14:00] - RO */ 10767 #endif /* IS_BIG_ENDIAN */ 10768 #if IS_LITTLE_ENDIAN 10769 uint32_t prbs_chk_err_cnt_msb : 15; /* TLB_RX_prbs_chk_err_cnt_msb_status_t[14:00] - RO */ 10770 uint32_t prbs_chk_lock_lost_lh : 1; /* TLB_RX_prbs_chk_err_cnt_msb_status_t[15] - RO */ 10771 uint32_t reserved : 16; 10772 #endif /* IS_LITTLE_ENDIAN */ 10773 } fields; 10774 } TLB_RX_prbs_chk_err_cnt_msb_status_t; 10775 10776 typedef TLB_RX_prbs_chk_err_cnt_msb_status_t TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS_t; 10777 10778 typedef union { 10779 uint32_t data; 10780 struct { 10781 #if IS_BIG_ENDIAN 10782 uint32_t reserved : 16; 10783 uint32_t prbs_chk_err_cnt_lsb : 16; /* TLB_RX_prbs_chk_err_cnt_lsb_status_t[15:00] - RO */ 10784 #endif /* IS_BIG_ENDIAN */ 10785 #if IS_LITTLE_ENDIAN 10786 uint32_t prbs_chk_err_cnt_lsb : 16; /* TLB_RX_prbs_chk_err_cnt_lsb_status_t[15:00] - RO */ 10787 uint32_t reserved : 16; 10788 #endif /* IS_LITTLE_ENDIAN */ 10789 } fields; 10790 } TLB_RX_prbs_chk_err_cnt_lsb_status_t; 10791 10792 typedef TLB_RX_prbs_chk_err_cnt_lsb_status_t TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS_t; 10793 10794 typedef union { 10795 uint32_t data; 10796 struct { 10797 #if IS_BIG_ENDIAN 10798 uint32_t reserved : 16; 10799 uint32_t reserved_02 : 14; /* TLB_RX_pmd_rx_lock_status_t[15:02] - RSVD */ 10800 uint32_t pmd_rx_lock_change : 1; /* TLB_RX_pmd_rx_lock_status_t[01] - RO */ 10801 uint32_t pmd_rx_lock : 1; /* TLB_RX_pmd_rx_lock_status_t[00] - RO */ 10802 #endif /* IS_BIG_ENDIAN */ 10803 #if IS_LITTLE_ENDIAN 10804 uint32_t pmd_rx_lock : 1; /* TLB_RX_pmd_rx_lock_status_t[00] - RO */ 10805 uint32_t pmd_rx_lock_change : 1; /* TLB_RX_pmd_rx_lock_status_t[01] - RO */ 10806 uint32_t reserved_02 : 14; /* TLB_RX_pmd_rx_lock_status_t[15:02] - RSVD */ 10807 uint32_t reserved : 16; 10808 #endif /* IS_LITTLE_ENDIAN */ 10809 } fields; 10810 } TLB_RX_pmd_rx_lock_status_t; 10811 10812 typedef TLB_RX_pmd_rx_lock_status_t TLB_RX_PMD_RX_LOCK_STATUS_t; 10813 10814 10815 /*-----------------------------------------------*/ 10816 /* Structs for TLB_TX Bank */ 10817 /*-----------------------------------------------*/ 10818 typedef union { 10819 uint32_t data; 10820 struct { 10821 #if IS_BIG_ENDIAN 10822 uint32_t reserved : 16; 10823 uint32_t patt_gen_start_pos : 4; /* TLB_TX_patt_gen_config_t[15:12] - RW */ 10824 uint32_t patt_gen_stop_pos : 4; /* TLB_TX_patt_gen_config_t[11:08] - RW */ 10825 uint32_t reserved_01 : 7; /* TLB_TX_patt_gen_config_t[07:01] - RSVD */ 10826 uint32_t patt_gen_en : 1; /* TLB_TX_patt_gen_config_t[00] - RW */ 10827 #endif /* IS_BIG_ENDIAN */ 10828 #if IS_LITTLE_ENDIAN 10829 uint32_t patt_gen_en : 1; /* TLB_TX_patt_gen_config_t[00] - RW */ 10830 uint32_t reserved_01 : 7; /* TLB_TX_patt_gen_config_t[07:01] - RSVD */ 10831 uint32_t patt_gen_stop_pos : 4; /* TLB_TX_patt_gen_config_t[11:08] - RW */ 10832 uint32_t patt_gen_start_pos : 4; /* TLB_TX_patt_gen_config_t[15:12] - RW */ 10833 uint32_t reserved : 16; 10834 #endif /* IS_LITTLE_ENDIAN */ 10835 } fields; 10836 } TLB_TX_patt_gen_config_t; 10837 10838 typedef TLB_TX_patt_gen_config_t TLB_TX_PATT_GEN_CONFIG_t; 10839 10840 typedef union { 10841 uint32_t data; 10842 struct { 10843 #if IS_BIG_ENDIAN 10844 uint32_t reserved : 16; 10845 uint32_t reserved_06 : 10; /* TLB_TX_prbs_gen_config_t[15:06] - RSVD */ 10846 uint32_t prbs_gen_err_ins : 1; /* TLB_TX_prbs_gen_config_t[05] - RW */ 10847 uint32_t prbs_gen_inv : 1; /* TLB_TX_prbs_gen_config_t[04] - RW */ 10848 uint32_t prbs_gen_mode_sel : 3; /* TLB_TX_prbs_gen_config_t[03:01] - RW */ 10849 uint32_t prbs_gen_en : 1; /* TLB_TX_prbs_gen_config_t[00] - RW */ 10850 #endif /* IS_BIG_ENDIAN */ 10851 #if IS_LITTLE_ENDIAN 10852 uint32_t prbs_gen_en : 1; /* TLB_TX_prbs_gen_config_t[00] - RW */ 10853 uint32_t prbs_gen_mode_sel : 3; /* TLB_TX_prbs_gen_config_t[03:01] - RW */ 10854 uint32_t prbs_gen_inv : 1; /* TLB_TX_prbs_gen_config_t[04] - RW */ 10855 uint32_t prbs_gen_err_ins : 1; /* TLB_TX_prbs_gen_config_t[05] - RW */ 10856 uint32_t reserved_06 : 10; /* TLB_TX_prbs_gen_config_t[15:06] - RSVD */ 10857 uint32_t reserved : 16; 10858 #endif /* IS_LITTLE_ENDIAN */ 10859 } fields; 10860 } TLB_TX_prbs_gen_config_t; 10861 10862 typedef TLB_TX_prbs_gen_config_t TLB_TX_PRBS_GEN_CONFIG_t; 10863 10864 typedef union { 10865 uint32_t data; 10866 struct { 10867 #if IS_BIG_ENDIAN 10868 uint32_t reserved : 16; 10869 uint32_t reserved_03 : 13; /* TLB_TX_rmt_lpbk_config_t[15:03] - RSVD */ 10870 uint32_t reserved_02 : 1; /* TLB_TX_rmt_lpbk_config_t[02] - RSVD */ 10871 uint32_t reserved_01 : 1; /* TLB_TX_rmt_lpbk_config_t[01] - RSVD */ 10872 uint32_t rmt_lpbk_en : 1; /* TLB_TX_rmt_lpbk_config_t[00] - RW */ 10873 #endif /* IS_BIG_ENDIAN */ 10874 #if IS_LITTLE_ENDIAN 10875 uint32_t rmt_lpbk_en : 1; /* TLB_TX_rmt_lpbk_config_t[00] - RW */ 10876 uint32_t reserved_01 : 1; /* TLB_TX_rmt_lpbk_config_t[01] - RSVD */ 10877 uint32_t reserved_02 : 1; /* TLB_TX_rmt_lpbk_config_t[02] - RSVD */ 10878 uint32_t reserved_03 : 13; /* TLB_TX_rmt_lpbk_config_t[15:03] - RSVD */ 10879 uint32_t reserved : 16; 10880 #endif /* IS_LITTLE_ENDIAN */ 10881 } fields; 10882 } TLB_TX_rmt_lpbk_config_t; 10883 10884 typedef TLB_TX_rmt_lpbk_config_t TLB_TX_RMT_LPBK_CONFIG_t; 10885 10886 typedef union { 10887 uint32_t data; 10888 struct { 10889 #if IS_BIG_ENDIAN 10890 uint32_t reserved : 16; 10891 uint32_t reserved_04 : 12; /* TLB_TX_tlb_tx_misc_config_t[15:04] - RSVD */ 10892 uint32_t reserved_03 : 1; /* TLB_TX_tlb_tx_misc_config_t[03] - RSVD */ 10893 uint32_t reserved_02 : 1; /* TLB_TX_tlb_tx_misc_config_t[02] - RSVD */ 10894 uint32_t reserved_01 : 1; /* TLB_TX_tlb_tx_misc_config_t[01] - RSVD */ 10895 uint32_t tx_pmd_dp_invert : 1; /* TLB_TX_tlb_tx_misc_config_t[00] - RW */ 10896 #endif /* IS_BIG_ENDIAN */ 10897 #if IS_LITTLE_ENDIAN 10898 uint32_t tx_pmd_dp_invert : 1; /* TLB_TX_tlb_tx_misc_config_t[00] - RW */ 10899 uint32_t reserved_01 : 1; /* TLB_TX_tlb_tx_misc_config_t[01] - RSVD */ 10900 uint32_t reserved_02 : 1; /* TLB_TX_tlb_tx_misc_config_t[02] - RSVD */ 10901 uint32_t reserved_03 : 1; /* TLB_TX_tlb_tx_misc_config_t[03] - RSVD */ 10902 uint32_t reserved_04 : 12; /* TLB_TX_tlb_tx_misc_config_t[15:04] - RSVD */ 10903 uint32_t reserved : 16; 10904 #endif /* IS_LITTLE_ENDIAN */ 10905 } fields; 10906 } TLB_TX_tlb_tx_misc_config_t; 10907 10908 typedef TLB_TX_tlb_tx_misc_config_t TLB_TX_TLB_TX_MISC_CONFIG_t; 10909 10910 10911 /*-----------------------------------------------*/ 10912 /* Structs for IEEE_AN_BLK0 Bank */ 10913 /*-----------------------------------------------*/ 10914 typedef union { 10915 uint32_t data; 10916 struct { 10917 #if IS_BIG_ENDIAN 10918 uint32_t reserved : 16; 10919 uint32_t an_reset : 1; /* IEEE_AN_BLK0_an_control_register_t[15] - SC */ 10920 uint32_t reserved_13 : 2; /* IEEE_AN_BLK0_an_control_register_t[14:13] - RSVD */ 10921 uint32_t auto_negotiationenable : 1; /* IEEE_AN_BLK0_an_control_register_t[12] - WO */ 10922 uint32_t reserved_10 : 2; /* IEEE_AN_BLK0_an_control_register_t[11:10] - RSVD */ 10923 uint32_t restart_auto_negotiation : 1; /* IEEE_AN_BLK0_an_control_register_t[09] - SC */ 10924 uint32_t reserved_00 : 9; /* IEEE_AN_BLK0_an_control_register_t[08:00] - RSVD */ 10925 #endif /* IS_BIG_ENDIAN */ 10926 #if IS_LITTLE_ENDIAN 10927 uint32_t reserved_00 : 9; /* IEEE_AN_BLK0_an_control_register_t[08:00] - RSVD */ 10928 uint32_t restart_auto_negotiation : 1; /* IEEE_AN_BLK0_an_control_register_t[09] - SC */ 10929 uint32_t reserved_10 : 2; /* IEEE_AN_BLK0_an_control_register_t[11:10] - RSVD */ 10930 uint32_t auto_negotiationenable : 1; /* IEEE_AN_BLK0_an_control_register_t[12] - WO */ 10931 uint32_t reserved_13 : 2; /* IEEE_AN_BLK0_an_control_register_t[14:13] - RSVD */ 10932 uint32_t an_reset : 1; /* IEEE_AN_BLK0_an_control_register_t[15] - SC */ 10933 uint32_t reserved : 16; 10934 #endif /* IS_LITTLE_ENDIAN */ 10935 } fields; 10936 } IEEE_AN_BLK0_an_control_register_t; 10937 10938 typedef IEEE_AN_BLK0_an_control_register_t IEEE_AN_BLK0_AN_CONTROL_REGISTER_t; 10939 10940 typedef union { 10941 uint32_t data; 10942 struct { 10943 #if IS_BIG_ENDIAN 10944 uint32_t reserved : 16; 10945 uint32_t reserved_10 : 6; /* IEEE_AN_BLK0_an_status_register_t[15:10] - RSVD */ 10946 uint32_t parallel_detection_fault : 1; /* IEEE_AN_BLK0_an_status_register_t[09] - LH */ 10947 uint32_t reserved_08 : 1; /* IEEE_AN_BLK0_an_status_register_t[08] - RSVD */ 10948 uint32_t extended_next_pagestatus : 1; /* IEEE_AN_BLK0_an_status_register_t[07] - RO */ 10949 uint32_t page_received : 1; /* IEEE_AN_BLK0_an_status_register_t[06] - LH */ 10950 uint32_t auto_negotiationcomplete : 1; /* IEEE_AN_BLK0_an_status_register_t[05] - RO */ 10951 uint32_t remote_fault : 1; /* IEEE_AN_BLK0_an_status_register_t[04] - LH */ 10952 uint32_t auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_t[03] - RO */ 10953 uint32_t link_status : 1; /* IEEE_AN_BLK0_an_status_register_t[02] - LL */ 10954 uint32_t reserved_01 : 1; /* IEEE_AN_BLK0_an_status_register_t[01] - RSVD */ 10955 uint32_t link_partner_auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_t[00] - RO */ 10956 #endif /* IS_BIG_ENDIAN */ 10957 #if IS_LITTLE_ENDIAN 10958 uint32_t link_partner_auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_t[00] - RO */ 10959 uint32_t reserved_01 : 1; /* IEEE_AN_BLK0_an_status_register_t[01] - RSVD */ 10960 uint32_t link_status : 1; /* IEEE_AN_BLK0_an_status_register_t[02] - LL */ 10961 uint32_t auto_negotiationability : 1; /* IEEE_AN_BLK0_an_status_register_t[03] - RO */ 10962 uint32_t remote_fault : 1; /* IEEE_AN_BLK0_an_status_register_t[04] - LH */ 10963 uint32_t auto_negotiationcomplete : 1; /* IEEE_AN_BLK0_an_status_register_t[05] - RO */ 10964 uint32_t page_received : 1; /* IEEE_AN_BLK0_an_status_register_t[06] - LH */ 10965 uint32_t extended_next_pagestatus : 1; /* IEEE_AN_BLK0_an_status_register_t[07] - RO */ 10966 uint32_t reserved_08 : 1; /* IEEE_AN_BLK0_an_status_register_t[08] - RSVD */ 10967 uint32_t parallel_detection_fault : 1; /* IEEE_AN_BLK0_an_status_register_t[09] - LH */ 10968 uint32_t reserved_10 : 6; /* IEEE_AN_BLK0_an_status_register_t[15:10] - RSVD */ 10969 uint32_t reserved : 16; 10970 #endif /* IS_LITTLE_ENDIAN */ 10971 } fields; 10972 } IEEE_AN_BLK0_an_status_register_t; 10973 10974 typedef IEEE_AN_BLK0_an_status_register_t IEEE_AN_BLK0_AN_STATUS_REGISTER_t; 10975 10976 typedef union { 10977 uint32_t data; 10978 struct { 10979 #if IS_BIG_ENDIAN 10980 uint32_t reserved : 16; 10981 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_identifier_register_0_t[15:00] - RO */ 10982 #endif /* IS_BIG_ENDIAN */ 10983 #if IS_LITTLE_ENDIAN 10984 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_identifier_register_0_t[15:00] - RO */ 10985 uint32_t reserved : 16; 10986 #endif /* IS_LITTLE_ENDIAN */ 10987 } fields; 10988 } IEEE_AN_BLK0_an_identifier_register_0_t; 10989 10990 typedef IEEE_AN_BLK0_an_identifier_register_0_t IEEE_AN_BLK0_AN_IDENTIFIER_REGISTER_0_t; 10991 10992 typedef union { 10993 uint32_t data; 10994 struct { 10995 #if IS_BIG_ENDIAN 10996 uint32_t reserved : 16; 10997 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_identifier_register_1_t[15:00] - RO */ 10998 #endif /* IS_BIG_ENDIAN */ 10999 #if IS_LITTLE_ENDIAN 11000 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_identifier_register_1_t[15:00] - RO */ 11001 uint32_t reserved : 16; 11002 #endif /* IS_LITTLE_ENDIAN */ 11003 } fields; 11004 } IEEE_AN_BLK0_an_identifier_register_1_t; 11005 11006 typedef IEEE_AN_BLK0_an_identifier_register_1_t IEEE_AN_BLK0_AN_IDENTIFIER_REGISTER_1_t; 11007 11008 typedef union { 11009 uint32_t data; 11010 struct { 11011 #if IS_BIG_ENDIAN 11012 uint32_t reserved : 16; 11013 uint32_t reserved_12 : 4; /* IEEE_AN_BLK0_an_devices_in_package_1_t[15:12] - RSVD */ 11014 uint32_t seperate_pma_4_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[11] - RO */ 11015 uint32_t seperate_pma_3_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[10] - RO */ 11016 uint32_t seperate_pma_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[09] - RO */ 11017 uint32_t seperate_pma_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[08] - RO */ 11018 uint32_t an_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[07] - RO */ 11019 uint32_t tc_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[06] - RO */ 11020 uint32_t dte_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[05] - RO */ 11021 uint32_t phy_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[04] - RO */ 11022 uint32_t pcs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[03] - RO */ 11023 uint32_t wis_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[02] - RO */ 11024 uint32_t pmd_pma_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[01] - RO */ 11025 uint32_t clause_22registers_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[00] - RO */ 11026 #endif /* IS_BIG_ENDIAN */ 11027 #if IS_LITTLE_ENDIAN 11028 uint32_t clause_22registers_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[00] - RO */ 11029 uint32_t pmd_pma_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[01] - RO */ 11030 uint32_t wis_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[02] - RO */ 11031 uint32_t pcs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[03] - RO */ 11032 uint32_t phy_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[04] - RO */ 11033 uint32_t dte_xs_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[05] - RO */ 11034 uint32_t tc_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[06] - RO */ 11035 uint32_t an_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[07] - RO */ 11036 uint32_t seperate_pma_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[08] - RO */ 11037 uint32_t seperate_pma_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[09] - RO */ 11038 uint32_t seperate_pma_3_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[10] - RO */ 11039 uint32_t seperate_pma_4_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_1_t[11] - RO */ 11040 uint32_t reserved_12 : 4; /* IEEE_AN_BLK0_an_devices_in_package_1_t[15:12] - RSVD */ 11041 uint32_t reserved : 16; 11042 #endif /* IS_LITTLE_ENDIAN */ 11043 } fields; 11044 } IEEE_AN_BLK0_an_devices_in_package_1_t; 11045 11046 typedef IEEE_AN_BLK0_an_devices_in_package_1_t IEEE_AN_BLK0_AN_DEVICES_IN_PACKAGE_1_t; 11047 11048 typedef union { 11049 uint32_t data; 11050 struct { 11051 #if IS_BIG_ENDIAN 11052 uint32_t reserved : 16; 11053 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_t[15] - RO */ 11054 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_t[14] - RO */ 11055 uint32_t clause_22extension_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_t[13] - RO */ 11056 uint32_t reserved_00 : 13; /* IEEE_AN_BLK0_an_devices_in_package_2_t[12:00] - RSVD */ 11057 #endif /* IS_BIG_ENDIAN */ 11058 #if IS_LITTLE_ENDIAN 11059 uint32_t reserved_00 : 13; /* IEEE_AN_BLK0_an_devices_in_package_2_t[12:00] - RSVD */ 11060 uint32_t clause_22extension_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_t[13] - RO */ 11061 uint32_t vendor_specificdevice_1_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_t[14] - RO */ 11062 uint32_t vendor_specificdevice_2_present : 1; /* IEEE_AN_BLK0_an_devices_in_package_2_t[15] - RO */ 11063 uint32_t reserved : 16; 11064 #endif /* IS_LITTLE_ENDIAN */ 11065 } fields; 11066 } IEEE_AN_BLK0_an_devices_in_package_2_t; 11067 11068 typedef IEEE_AN_BLK0_an_devices_in_package_2_t IEEE_AN_BLK0_AN_DEVICES_IN_PACKAGE_2_t; 11069 11070 typedef union { 11071 uint32_t data; 11072 struct { 11073 #if IS_BIG_ENDIAN 11074 uint32_t reserved : 16; 11075 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_oui_id0_register_t[15:00] - RO */ 11076 #endif /* IS_BIG_ENDIAN */ 11077 #if IS_LITTLE_ENDIAN 11078 uint32_t device_id_0 : 16; /* IEEE_AN_BLK0_an_oui_id0_register_t[15:00] - RO */ 11079 uint32_t reserved : 16; 11080 #endif /* IS_LITTLE_ENDIAN */ 11081 } fields; 11082 } IEEE_AN_BLK0_an_oui_id0_register_t; 11083 11084 typedef IEEE_AN_BLK0_an_oui_id0_register_t IEEE_AN_BLK0_AN_OUI_ID0_REGISTER_t; 11085 11086 typedef union { 11087 uint32_t data; 11088 struct { 11089 #if IS_BIG_ENDIAN 11090 uint32_t reserved : 16; 11091 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_oui_id1_reg_t[15:00] - RO */ 11092 #endif /* IS_BIG_ENDIAN */ 11093 #if IS_LITTLE_ENDIAN 11094 uint32_t device_id_1 : 16; /* IEEE_AN_BLK0_an_oui_id1_reg_t[15:00] - RO */ 11095 uint32_t reserved : 16; 11096 #endif /* IS_LITTLE_ENDIAN */ 11097 } fields; 11098 } IEEE_AN_BLK0_an_oui_id1_reg_t; 11099 11100 typedef IEEE_AN_BLK0_an_oui_id1_reg_t IEEE_AN_BLK0_AN_OUI_ID1_REG_t; 11101 11102 11103 /*-----------------------------------------------*/ 11104 /* Structs for IEEE_AN_BLK1 Bank */ 11105 /*-----------------------------------------------*/ 11106 typedef union { 11107 uint32_t data; 11108 struct { 11109 #if IS_BIG_ENDIAN 11110 uint32_t reserved : 16; 11111 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_t[15] - WO */ 11112 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_t[14] - RO */ 11113 uint32_t remote_fault : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_t[13] - WO */ 11114 uint32_t pause : 3; /* IEEE_AN_BLK1_an_advertisement_1_register_t[12:10] - WO */ 11115 uint32_t echoed_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_t[09:05] - WO */ 11116 uint32_t selector_field : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_t[04:00] - WO */ 11117 #endif /* IS_BIG_ENDIAN */ 11118 #if IS_LITTLE_ENDIAN 11119 uint32_t selector_field : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_t[04:00] - WO */ 11120 uint32_t echoed_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_1_register_t[09:05] - WO */ 11121 uint32_t pause : 3; /* IEEE_AN_BLK1_an_advertisement_1_register_t[12:10] - WO */ 11122 uint32_t remote_fault : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_t[13] - WO */ 11123 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_t[14] - RO */ 11124 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_advertisement_1_register_t[15] - WO */ 11125 uint32_t reserved : 16; 11126 #endif /* IS_LITTLE_ENDIAN */ 11127 } fields; 11128 } IEEE_AN_BLK1_an_advertisement_1_register_t; 11129 11130 typedef IEEE_AN_BLK1_an_advertisement_1_register_t IEEE_AN_BLK1_AN_ADVERTISEMENT_1_REGISTER_t; 11131 11132 typedef union { 11133 uint32_t data; 11134 struct { 11135 #if IS_BIG_ENDIAN 11136 uint32_t reserved : 16; 11137 uint32_t techability : 11; /* IEEE_AN_BLK1_an_advertisement_2_register_t[15:05] - WO */ 11138 uint32_t transmitted_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_2_register_t[04:00] - WO */ 11139 #endif /* IS_BIG_ENDIAN */ 11140 #if IS_LITTLE_ENDIAN 11141 uint32_t transmitted_nonce : 5; /* IEEE_AN_BLK1_an_advertisement_2_register_t[04:00] - WO */ 11142 uint32_t techability : 11; /* IEEE_AN_BLK1_an_advertisement_2_register_t[15:05] - WO */ 11143 uint32_t reserved : 16; 11144 #endif /* IS_LITTLE_ENDIAN */ 11145 } fields; 11146 } IEEE_AN_BLK1_an_advertisement_2_register_t; 11147 11148 typedef IEEE_AN_BLK1_an_advertisement_2_register_t IEEE_AN_BLK1_AN_ADVERTISEMENT_2_REGISTER_t; 11149 11150 typedef union { 11151 uint32_t data; 11152 struct { 11153 #if IS_BIG_ENDIAN 11154 uint32_t reserved : 16; 11155 uint32_t fec_requested : 2; /* IEEE_AN_BLK1_an_advertisement_3_register_t[15:14] - WO */ 11156 uint32_t an_adv_d45_d32 : 14; /* IEEE_AN_BLK1_an_advertisement_3_register_t[13:00] - WO */ 11157 #endif /* IS_BIG_ENDIAN */ 11158 #if IS_LITTLE_ENDIAN 11159 uint32_t an_adv_d45_d32 : 14; /* IEEE_AN_BLK1_an_advertisement_3_register_t[13:00] - WO */ 11160 uint32_t fec_requested : 2; /* IEEE_AN_BLK1_an_advertisement_3_register_t[15:14] - WO */ 11161 uint32_t reserved : 16; 11162 #endif /* IS_LITTLE_ENDIAN */ 11163 } fields; 11164 } IEEE_AN_BLK1_an_advertisement_3_register_t; 11165 11166 typedef IEEE_AN_BLK1_an_advertisement_3_register_t IEEE_AN_BLK1_AN_ADVERTISEMENT_3_REGISTER_t; 11167 11168 typedef union { 11169 uint32_t data; 11170 struct { 11171 #if IS_BIG_ENDIAN 11172 uint32_t reserved : 16; 11173 uint32_t d15_d0 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_t[15:00] - RO */ 11174 #endif /* IS_BIG_ENDIAN */ 11175 #if IS_LITTLE_ENDIAN 11176 uint32_t d15_d0 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_t[15:00] - RO */ 11177 uint32_t reserved : 16; 11178 #endif /* IS_LITTLE_ENDIAN */ 11179 } fields; 11180 } IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_t; 11181 11182 typedef IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_t IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_1_REG_t; 11183 11184 typedef union { 11185 uint32_t data; 11186 struct { 11187 #if IS_BIG_ENDIAN 11188 uint32_t reserved : 16; 11189 uint32_t d31_16 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_t[15:00] - RO */ 11190 #endif /* IS_BIG_ENDIAN */ 11191 #if IS_LITTLE_ENDIAN 11192 uint32_t d31_16 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_t[15:00] - RO */ 11193 uint32_t reserved : 16; 11194 #endif /* IS_LITTLE_ENDIAN */ 11195 } fields; 11196 } IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_t; 11197 11198 typedef IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_t IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_2_REG_t; 11199 11200 typedef union { 11201 uint32_t data; 11202 struct { 11203 #if IS_BIG_ENDIAN 11204 uint32_t reserved : 16; 11205 uint32_t d47_32 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_t[15:00] - RO */ 11206 #endif /* IS_BIG_ENDIAN */ 11207 #if IS_LITTLE_ENDIAN 11208 uint32_t d47_32 : 16; /* IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_t[15:00] - RO */ 11209 uint32_t reserved : 16; 11210 #endif /* IS_LITTLE_ENDIAN */ 11211 } fields; 11212 } IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_t; 11213 11214 typedef IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_t IEEE_AN_BLK1_AN_LP_BASE_PAGE_ABILITY_3_REG_t; 11215 11216 typedef union { 11217 uint32_t data; 11218 struct { 11219 #if IS_BIG_ENDIAN 11220 uint32_t reserved : 16; 11221 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[15] - WO */ 11222 uint32_t reserved_14 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[14] - RSVD */ 11223 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[13] - WO */ 11224 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[12] - WO */ 11225 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[11] - RO */ 11226 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[10:00] - WO */ 11227 #endif /* IS_BIG_ENDIAN */ 11228 #if IS_LITTLE_ENDIAN 11229 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[10:00] - WO */ 11230 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[11] - RO */ 11231 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[12] - WO */ 11232 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[13] - WO */ 11233 uint32_t reserved_14 : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[14] - RSVD */ 11234 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_xnp_transmit_1_register_t[15] - WO */ 11235 uint32_t reserved : 16; 11236 #endif /* IS_LITTLE_ENDIAN */ 11237 } fields; 11238 } IEEE_AN_BLK1_an_xnp_transmit_1_register_t; 11239 11240 typedef IEEE_AN_BLK1_an_xnp_transmit_1_register_t IEEE_AN_BLK1_AN_XNP_TRANSMIT_1_REGISTER_t; 11241 11242 typedef union { 11243 uint32_t data; 11244 struct { 11245 #if IS_BIG_ENDIAN 11246 uint32_t reserved : 16; 11247 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_2_register_t[15:00] - WO */ 11248 #endif /* IS_BIG_ENDIAN */ 11249 #if IS_LITTLE_ENDIAN 11250 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_2_register_t[15:00] - WO */ 11251 uint32_t reserved : 16; 11252 #endif /* IS_LITTLE_ENDIAN */ 11253 } fields; 11254 } IEEE_AN_BLK1_an_xnp_transmit_2_register_t; 11255 11256 typedef IEEE_AN_BLK1_an_xnp_transmit_2_register_t IEEE_AN_BLK1_AN_XNP_TRANSMIT_2_REGISTER_t; 11257 11258 typedef union { 11259 uint32_t data; 11260 struct { 11261 #if IS_BIG_ENDIAN 11262 uint32_t reserved : 16; 11263 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_3_register_t[15:00] - WO */ 11264 #endif /* IS_BIG_ENDIAN */ 11265 #if IS_LITTLE_ENDIAN 11266 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_xnp_transmit_3_register_t[15:00] - WO */ 11267 uint32_t reserved : 16; 11268 #endif /* IS_LITTLE_ENDIAN */ 11269 } fields; 11270 } IEEE_AN_BLK1_an_xnp_transmit_3_register_t; 11271 11272 typedef IEEE_AN_BLK1_an_xnp_transmit_3_register_t IEEE_AN_BLK1_AN_XNP_TRANSMIT_3_REGISTER_t; 11273 11274 typedef union { 11275 uint32_t data; 11276 struct { 11277 #if IS_BIG_ENDIAN 11278 uint32_t reserved : 16; 11279 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[15] - RO */ 11280 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[14] - RO */ 11281 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[13] - RO */ 11282 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[12] - RO */ 11283 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[11] - RO */ 11284 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[10:00] - RO */ 11285 #endif /* IS_BIG_ENDIAN */ 11286 #if IS_LITTLE_ENDIAN 11287 uint32_t message_unformatedcode_field : 11; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[10:00] - RO */ 11288 uint32_t toggle : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[11] - RO */ 11289 uint32_t acknowledge_2 : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[12] - RO */ 11290 uint32_t message_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[13] - RO */ 11291 uint32_t acknowledge : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[14] - RO */ 11292 uint32_t next_page : 1; /* IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t[15] - RO */ 11293 uint32_t reserved : 16; 11294 #endif /* IS_LITTLE_ENDIAN */ 11295 } fields; 11296 } IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t; 11297 11298 typedef IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_t IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_1_REGISTER_t; 11299 11300 typedef union { 11301 uint32_t data; 11302 struct { 11303 #if IS_BIG_ENDIAN 11304 uint32_t reserved : 16; 11305 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_t[15:00] - RO */ 11306 #endif /* IS_BIG_ENDIAN */ 11307 #if IS_LITTLE_ENDIAN 11308 uint32_t unformated_codefield_1 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_t[15:00] - RO */ 11309 uint32_t reserved : 16; 11310 #endif /* IS_LITTLE_ENDIAN */ 11311 } fields; 11312 } IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_t; 11313 11314 typedef IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_t IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_2_REGISTER_t; 11315 11316 typedef union { 11317 uint32_t data; 11318 struct { 11319 #if IS_BIG_ENDIAN 11320 uint32_t reserved : 16; 11321 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_t[15:00] - RO */ 11322 #endif /* IS_BIG_ENDIAN */ 11323 #if IS_LITTLE_ENDIAN 11324 uint32_t unformated_codefield_3 : 16; /* IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_t[15:00] - RO */ 11325 uint32_t reserved : 16; 11326 #endif /* IS_LITTLE_ENDIAN */ 11327 } fields; 11328 } IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_t; 11329 11330 typedef IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_t IEEE_AN_BLK1_AN_LP_XNP_TRANSMIT_3_REGISTER_t; 11331 11332 11333 /*-----------------------------------------------*/ 11334 /* Structs for IEEE_AN_BLK3 Bank */ 11335 /*-----------------------------------------------*/ 11336 typedef union { 11337 uint32_t data; 11338 struct { 11339 #if IS_BIG_ENDIAN 11340 uint32_t reserved : 16; 11341 uint32_t reserved_12 : 4; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[15:12] - RSVD */ 11342 uint32_t onehundredbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[11] - RO */ 11343 uint32_t onehundredbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[10] - RO */ 11344 uint32_t onehundredbase_kp4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[09] - RO */ 11345 uint32_t onehundredbase_cr10 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[08] - RO */ 11346 uint32_t reserved_07 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[07] - RSVD */ 11347 uint32_t fortygbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[06] - RO */ 11348 uint32_t fortygbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[05] - RO */ 11349 uint32_t fec_negotiated : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[04] - RO */ 11350 uint32_t tengbase_kr : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[03] - RO */ 11351 uint32_t tengbase_kx4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[02] - RO */ 11352 uint32_t gigbase_kx : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[01] - RO */ 11353 uint32_t bp_an_ability : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[00] - RO */ 11354 #endif /* IS_BIG_ENDIAN */ 11355 #if IS_LITTLE_ENDIAN 11356 uint32_t bp_an_ability : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[00] - RO */ 11357 uint32_t gigbase_kx : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[01] - RO */ 11358 uint32_t tengbase_kx4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[02] - RO */ 11359 uint32_t tengbase_kr : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[03] - RO */ 11360 uint32_t fec_negotiated : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[04] - RO */ 11361 uint32_t fortygbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[05] - RO */ 11362 uint32_t fortygbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[06] - RO */ 11363 uint32_t reserved_07 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[07] - RSVD */ 11364 uint32_t onehundredbase_cr10 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[08] - RO */ 11365 uint32_t onehundredbase_kp4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[09] - RO */ 11366 uint32_t onehundredbase_kr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[10] - RO */ 11367 uint32_t onehundredbase_cr4 : 1; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[11] - RO */ 11368 uint32_t reserved_12 : 4; /* IEEE_AN_BLK3_backplane_ethernet_status_register_t[15:12] - RSVD */ 11369 uint32_t reserved : 16; 11370 #endif /* IS_LITTLE_ENDIAN */ 11371 } fields; 11372 } IEEE_AN_BLK3_backplane_ethernet_status_register_t; 11373 11374 typedef IEEE_AN_BLK3_backplane_ethernet_status_register_t IEEE_AN_BLK3_BACKPLANE_ETHERNET_STATUS_REGISTER_t; 11375 11376 typedef union { 11377 uint32_t data; 11378 struct { 11379 #if IS_BIG_ENDIAN 11380 uint32_t reserved : 16; 11381 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_adv_t[15:07] - RSVD */ 11382 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_adv_t[06] - WO */ 11383 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_adv_t[05] - WO */ 11384 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_adv_t[04] - WO */ 11385 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_adv_t[03:00] - RSVD */ 11386 #endif /* IS_BIG_ENDIAN */ 11387 #if IS_LITTLE_ENDIAN 11388 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_adv_t[03:00] - RSVD */ 11389 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_adv_t[04] - WO */ 11390 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_adv_t[05] - WO */ 11391 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_adv_t[06] - WO */ 11392 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_adv_t[15:07] - RSVD */ 11393 uint32_t reserved : 16; 11394 #endif /* IS_LITTLE_ENDIAN */ 11395 } fields; 11396 } IEEE_AN_BLK3_EEE_adv_t; 11397 11398 typedef IEEE_AN_BLK3_EEE_adv_t IEEE_AN_BLK3_EEE_ADV_t; 11399 11400 typedef union { 11401 uint32_t data; 11402 struct { 11403 #if IS_BIG_ENDIAN 11404 uint32_t reserved : 16; 11405 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_lp_adv_t[15:07] - RSVD */ 11406 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_lp_adv_t[06] - RO */ 11407 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_lp_adv_t[05] - RO */ 11408 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_lp_adv_t[04] - RO */ 11409 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_lp_adv_t[03:00] - RSVD */ 11410 #endif /* IS_BIG_ENDIAN */ 11411 #if IS_LITTLE_ENDIAN 11412 uint32_t reserved_00 : 4; /* IEEE_AN_BLK3_EEE_lp_adv_t[03:00] - RSVD */ 11413 uint32_t eee_1g_kx : 1; /* IEEE_AN_BLK3_EEE_lp_adv_t[04] - RO */ 11414 uint32_t eee_10g_kx4 : 1; /* IEEE_AN_BLK3_EEE_lp_adv_t[05] - RO */ 11415 uint32_t eee_10g_kr : 1; /* IEEE_AN_BLK3_EEE_lp_adv_t[06] - RO */ 11416 uint32_t reserved_07 : 9; /* IEEE_AN_BLK3_EEE_lp_adv_t[15:07] - RSVD */ 11417 uint32_t reserved : 16; 11418 #endif /* IS_LITTLE_ENDIAN */ 11419 } fields; 11420 } IEEE_AN_BLK3_EEE_lp_adv_t; 11421 11422 typedef IEEE_AN_BLK3_EEE_lp_adv_t IEEE_AN_BLK3_EEE_LP_ADV_t; 11423 11424 11425 /*-----------------------------------------------*/ 11426 /* Structs for DEV7_SLICE Bank */ 11427 /*-----------------------------------------------*/ 11428 typedef union { 11429 uint32_t data; 11430 struct { 11431 #if IS_BIG_ENDIAN 11432 uint32_t reserved : 16; 11433 uint32_t devid : 5; /* DEV7_SLICE_slice_t[15:11] - WO */ 11434 uint32_t reserved_10 : 1; /* DEV7_SLICE_slice_t[10] - RSVD */ 11435 uint32_t rd_lane : 2; /* DEV7_SLICE_slice_t[09:08] - WO */ 11436 uint32_t wr_lane : 4; /* DEV7_SLICE_slice_t[07:04] - WO */ 11437 uint32_t reserved_01 : 3; /* DEV7_SLICE_slice_t[03:01] - RSVD */ 11438 uint32_t sysen : 1; /* DEV7_SLICE_slice_t[00] - WO */ 11439 #endif /* IS_BIG_ENDIAN */ 11440 #if IS_LITTLE_ENDIAN 11441 uint32_t sysen : 1; /* DEV7_SLICE_slice_t[00] - WO */ 11442 uint32_t reserved_01 : 3; /* DEV7_SLICE_slice_t[03:01] - RSVD */ 11443 uint32_t wr_lane : 4; /* DEV7_SLICE_slice_t[07:04] - WO */ 11444 uint32_t rd_lane : 2; /* DEV7_SLICE_slice_t[09:08] - WO */ 11445 uint32_t reserved_10 : 1; /* DEV7_SLICE_slice_t[10] - RSVD */ 11446 uint32_t devid : 5; /* DEV7_SLICE_slice_t[15:11] - WO */ 11447 uint32_t reserved : 16; 11448 #endif /* IS_LITTLE_ENDIAN */ 11449 } fields; 11450 } DEV7_SLICE_slice_t; 11451 11452 typedef DEV7_SLICE_slice_t DEV7_SLICE_SLICE_t; 11453 11454 typedef union { 11455 uint32_t data; 11456 struct { 11457 #if IS_BIG_ENDIAN 11458 uint32_t reserved : 16; 11459 uint32_t mode_50g : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[15] - WO */ 11460 uint32_t mode_100g : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[14] - WO */ 11461 uint32_t pcs_mon_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[13] - WO */ 11462 uint32_t sync_sh_cnt_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[12] - WO */ 11463 uint32_t cl82_sync_sh_cnt_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[11] - WO */ 11464 uint32_t ber_cfg_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[10] - WO */ 11465 uint32_t ber_dis : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[09] - WO */ 11466 uint32_t logic_lane : 3; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[08:06] - WO */ 11467 uint32_t link_mon_mode_frcval : 2; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[05:04] - WO */ 11468 uint32_t link_mon_mode_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[03] - WO */ 11469 uint32_t link_mon_en : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[02] - WO */ 11470 uint32_t rstb_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[01] - WO */ 11471 uint32_t rstb : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[00] - WO */ 11472 #endif /* IS_BIG_ENDIAN */ 11473 #if IS_LITTLE_ENDIAN 11474 uint32_t rstb : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[00] - WO */ 11475 uint32_t rstb_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[01] - WO */ 11476 uint32_t link_mon_en : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[02] - WO */ 11477 uint32_t link_mon_mode_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[03] - WO */ 11478 uint32_t link_mon_mode_frcval : 2; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[05:04] - WO */ 11479 uint32_t logic_lane : 3; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[08:06] - WO */ 11480 uint32_t ber_dis : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[09] - WO */ 11481 uint32_t ber_cfg_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[10] - WO */ 11482 uint32_t cl82_sync_sh_cnt_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[11] - WO */ 11483 uint32_t sync_sh_cnt_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[12] - WO */ 11484 uint32_t pcs_mon_frc : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[13] - WO */ 11485 uint32_t mode_100g : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[14] - WO */ 11486 uint32_t mode_50g : 1; /* LINE_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[15] - WO */ 11487 uint32_t reserved : 16; 11488 #endif /* IS_LITTLE_ENDIAN */ 11489 } fields; 11490 } LINE_RX_PMA_DP_main_ctrl_PCS_mode_t; 11491 11492 typedef LINE_RX_PMA_DP_main_ctrl_PCS_mode_t LINE_RX_PMA_DP_MAIN_CTRL_PCS_MODE_t; 11493 typedef union { 11494 uint32_t data; 11495 struct { 11496 #if IS_BIG_ENDIAN 11497 uint32_t reserved : 16; 11498 uint32_t reserved_15 : 1; /* LINE_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[15] - RSVD */ 11499 uint32_t reserved_01 : 14; /* LINE_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[14:01] - RSVD */ 11500 uint32_t comma_fail_lh : 1; /* LINE_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[00] - RO */ 11501 #endif /* IS_BIG_ENDIAN */ 11502 #if IS_LITTLE_ENDIAN 11503 uint32_t comma_fail_lh : 1; /* LINE_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[00] - RO */ 11504 uint32_t reserved_01 : 14; /* LINE_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[14:01] - RSVD */ 11505 uint32_t reserved_15 : 1; /* LINE_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[15] - RSVD */ 11506 uint32_t reserved : 16; 11507 #endif /* IS_LITTLE_ENDIAN */ 11508 } fields; 11509 } LINE_RX_PMA_DP_cl49_latched_status_FC_mode_t; 11510 11511 typedef LINE_RX_PMA_DP_cl49_latched_status_FC_mode_t LINE_RX_PMA_DP_CL49_LATCHED_STATUS_FC_MODE_t; 11512 typedef union { 11513 uint32_t data; 11514 struct { 11515 #if IS_BIG_ENDIAN 11516 uint32_t reserved : 16; 11517 uint32_t ber_count_msb : 16; /* LINE_RX_PMA_DP_cl82_ber_count_MSB_TYPE[15:00] - RO */ 11518 #endif /* IS_BIG_ENDIAN */ 11519 #if IS_LITTLE_ENDIAN 11520 uint32_t ber_count_msb : 16; /* LINE_RX_PMA_DP_cl82_ber_count_MSB_TYPE[15:00] - RO */ 11521 uint32_t reserved : 16; 11522 #endif /* IS_LITTLE_ENDIAN */ 11523 } fields; 11524 } LINE_RX_PMA_DP_cl82_ber_count_MSB_t; 11525 11526 typedef LINE_RX_PMA_DP_cl82_ber_count_MSB_t LINE_RX_PMA_DP_CL82_BER_COUNT_MSB_t; 11527 11528 typedef union { 11529 uint32_t data; 11530 struct { 11531 #if IS_BIG_ENDIAN 11532 uint32_t reserved : 16; 11533 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[15] - RSVD */ 11534 uint32_t reserved_01 : 14; /* SYS_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[14:01] - RSVD */ 11535 uint32_t comma_fail_lh : 1; /* SYS_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[00] - RO */ 11536 #endif /* IS_BIG_ENDIAN */ 11537 #if IS_LITTLE_ENDIAN 11538 uint32_t comma_fail_lh : 1; /* SYS_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[00] - RO */ 11539 uint32_t reserved_01 : 14; /* SYS_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[14:01] - RSVD */ 11540 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_cl49_latched_status_FC_mode_TYPE[15] - RSVD */ 11541 uint32_t reserved : 16; 11542 #endif /* IS_LITTLE_ENDIAN */ 11543 } fields; 11544 } SYS_RX_PMA_DP_cl49_latched_status_FC_mode_t; 11545 11546 typedef SYS_RX_PMA_DP_cl49_latched_status_FC_mode_t SYS_RX_PMA_DP_CL49_LATCHED_STATUS_FC_MODE_t; 11547 11548 typedef union { 11549 uint32_t data; 11550 struct { 11551 #if IS_BIG_ENDIAN 11552 uint32_t reserved : 16; 11553 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[15] - RSVD */ 11554 uint32_t ber_done : 1; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[14] - RO */ 11555 uint32_t ber_fsm_lstate : 7; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[13:07] - RO */ 11556 uint32_t ber_count : 6; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[06:01] - RO */ 11557 uint32_t hi_ber_lh : 1; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[00] - RO */ 11558 #endif /* IS_BIG_ENDIAN */ 11559 #if IS_LITTLE_ENDIAN 11560 uint32_t hi_ber_lh : 1; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[00] - RO */ 11561 uint32_t ber_count : 6; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[06:01] - RO */ 11562 uint32_t ber_fsm_lstate : 7; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[13:07] - RO */ 11563 uint32_t ber_done : 1; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[14] - RO */ 11564 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[15] - RSVD */ 11565 uint32_t reserved : 16; 11566 #endif /* IS_LITTLE_ENDIAN */ 11567 } fields; 11568 } SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_t; 11569 11570 typedef SYS_RX_PMA_DP_cl49_latched_status_PCS_mode_t SYS_RX_PMA_DP_CL49_LATCHED_STATUS_PCS_MODE_t; 11571 11572 typedef union { 11573 uint32_t data; 11574 struct { 11575 #if IS_BIG_ENDIAN 11576 uint32_t reserved : 16; 11577 uint32_t ber_count_msb : 16; /* SYS_RX_PMA_DP_cl82_ber_count_MSB_TYPE[15:00] - RO */ 11578 #endif /* IS_BIG_ENDIAN */ 11579 #if IS_LITTLE_ENDIAN 11580 uint32_t ber_count_msb : 16; /* SYS_RX_PMA_DP_cl82_ber_count_MSB_TYPE[15:00] - RO */ 11581 uint32_t reserved : 16; 11582 #endif /* IS_LITTLE_ENDIAN */ 11583 } fields; 11584 } SYS_RX_PMA_DP_cl82_ber_count_MSB_t; 11585 11586 typedef SYS_RX_PMA_DP_cl82_ber_count_MSB_t SYS_RX_PMA_DP_CL82_BER_COUNT_MSB_t; 11587 typedef union { 11588 uint32_t data; 11589 struct { 11590 #if IS_BIG_ENDIAN 11591 uint32_t reserved : 16; 11592 uint32_t reserved_08 : 8; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[15:08] - RSVD */ 11593 uint32_t wsync_fsm : 3; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[07:05] - RO */ 11594 uint32_t wsyn_link_fail : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[04] - RO */ 11595 uint32_t dec_err : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[03] - RO */ 11596 uint32_t dec_rd_err : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[02] - RO */ 11597 uint32_t wsyn_loss_sync : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[01] - RO */ 11598 uint32_t pf_col : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[00] - RO */ 11599 #endif /* IS_BIG_ENDIAN */ 11600 #if IS_LITTLE_ENDIAN 11601 uint32_t pf_col : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[00] - RO */ 11602 uint32_t wsyn_loss_sync : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[01] - RO */ 11603 uint32_t dec_rd_err : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[02] - RO */ 11604 uint32_t dec_err : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[03] - RO */ 11605 uint32_t wsyn_link_fail : 1; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[04] - RO */ 11606 uint32_t wsync_fsm : 3; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[07:05] - RO */ 11607 uint32_t reserved_08 : 8; /* SYS_RX_PMA_DP_live_status_FC_mode_TYPE[15:08] - RSVD */ 11608 uint32_t reserved : 16; 11609 #endif /* IS_LITTLE_ENDIAN */ 11610 } fields; 11611 } SYS_RX_PMA_DP_live_status_FC_mode_t; 11612 11613 typedef SYS_RX_PMA_DP_live_status_FC_mode_t SYS_RX_PMA_DP_LIVE_STATUS_FC_MODE_t; 11614 11615 typedef union { 11616 uint32_t data; 11617 struct { 11618 #if IS_BIG_ENDIAN 11619 uint32_t reserved : 16; 11620 uint32_t reserved_08 : 8; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[15:08] - RSVD */ 11621 uint32_t ber_fsm : 2; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[07:06] - RO */ 11622 uint32_t lock_fsm : 2; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[05:04] - RO */ 11623 uint32_t hi_ber : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[03] - RO */ 11624 uint32_t block_lock : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[02] - RO */ 11625 uint32_t pcs_status : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[01] - RO */ 11626 uint32_t pf_col : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[00] - RO */ 11627 #endif /* IS_BIG_ENDIAN */ 11628 #if IS_LITTLE_ENDIAN 11629 uint32_t pf_col : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[00] - RO */ 11630 uint32_t pcs_status : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[01] - RO */ 11631 uint32_t block_lock : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[02] - RO */ 11632 uint32_t hi_ber : 1; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[03] - RO */ 11633 uint32_t lock_fsm : 2; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[05:04] - RO */ 11634 uint32_t ber_fsm : 2; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[07:06] - RO */ 11635 uint32_t reserved_08 : 8; /* SYS_RX_PMA_DP_live_status_PCS_mode_TYPE[15:08] - RSVD */ 11636 uint32_t reserved : 16; 11637 #endif /* IS_LITTLE_ENDIAN */ 11638 } fields; 11639 } SYS_RX_PMA_DP_live_status_PCS_mode_t; 11640 11641 typedef SYS_RX_PMA_DP_live_status_PCS_mode_t SYS_RX_PMA_DP_LIVE_STATUS_PCS_MODE_t; 11642 11643 typedef union { 11644 uint32_t data; 11645 struct { 11646 #if IS_BIG_ENDIAN 11647 uint32_t reserved : 16; 11648 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[15] - RSVD */ 11649 uint32_t word_sync_mode : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[14] - WO */ 11650 uint32_t sync_test_start : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[13] - WO */ 11651 uint32_t sync_test_window_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[12] - WO */ 11652 uint32_t link_test_window_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[11] - WO */ 11653 uint32_t comma_test_window_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[10] - WO */ 11654 uint32_t wsyn_fsm_rst : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[09] - WO */ 11655 uint32_t comma_test_window_size : 3; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[08:06] - WO */ 11656 uint32_t link_mon_mode_frcval : 2; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[05:04] - WO */ 11657 uint32_t link_mon_mode_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[03] - WO */ 11658 uint32_t link_mon_en : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[02] - WO */ 11659 uint32_t rstb_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[01] - WO */ 11660 uint32_t rstb : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[00] - WO */ 11661 #endif /* IS_BIG_ENDIAN */ 11662 #if IS_LITTLE_ENDIAN 11663 uint32_t rstb : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[00] - WO */ 11664 uint32_t rstb_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[01] - WO */ 11665 uint32_t link_mon_en : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[02] - WO */ 11666 uint32_t link_mon_mode_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[03] - WO */ 11667 uint32_t link_mon_mode_frcval : 2; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[05:04] - WO */ 11668 uint32_t comma_test_window_size : 3; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[08:06] - WO */ 11669 uint32_t wsyn_fsm_rst : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[09] - WO */ 11670 uint32_t comma_test_window_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[10] - WO */ 11671 uint32_t link_test_window_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[11] - WO */ 11672 uint32_t sync_test_window_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[12] - WO */ 11673 uint32_t sync_test_start : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[13] - WO */ 11674 uint32_t word_sync_mode : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[14] - WO */ 11675 uint32_t reserved_15 : 1; /* SYS_RX_PMA_DP_main_ctrl_FC_mode_TYPE[15] - RSVD */ 11676 uint32_t reserved : 16; 11677 #endif /* IS_LITTLE_ENDIAN */ 11678 } fields; 11679 } SYS_RX_PMA_DP_main_ctrl_FC_mode_t; 11680 11681 typedef SYS_RX_PMA_DP_main_ctrl_FC_mode_t SYS_RX_PMA_DP_MAIN_CTRL_FC_MODE_t; 11682 11683 typedef union { 11684 uint32_t data; 11685 struct { 11686 #if IS_BIG_ENDIAN 11687 uint32_t reserved : 16; 11688 uint32_t mode_50g : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[15] - WO */ 11689 uint32_t mode_100g : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[14] - WO */ 11690 uint32_t pcs_mon_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[13] - WO */ 11691 uint32_t sync_sh_cnt_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[12] - WO */ 11692 uint32_t cl82_sync_sh_cnt_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[11] - WO */ 11693 uint32_t ber_cfg_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[10] - WO */ 11694 uint32_t ber_dis : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[09] - WO */ 11695 uint32_t logic_lane : 3; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[08:06] - WO */ 11696 uint32_t link_mon_mode_frcval : 2; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[05:04] - WO */ 11697 uint32_t link_mon_mode_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[03] - WO */ 11698 uint32_t link_mon_en : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[02] - WO */ 11699 uint32_t rstb_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[01] - WO */ 11700 uint32_t rstb : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[00] - WO */ 11701 #endif /* IS_BIG_ENDIAN */ 11702 #if IS_LITTLE_ENDIAN 11703 uint32_t rstb : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[00] - WO */ 11704 uint32_t rstb_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[01] - WO */ 11705 uint32_t link_mon_en : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[02] - WO */ 11706 uint32_t link_mon_mode_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[03] - WO */ 11707 uint32_t link_mon_mode_frcval : 2; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[05:04] - WO */ 11708 uint32_t logic_lane : 3; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[08:06] - WO */ 11709 uint32_t ber_dis : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[09] - WO */ 11710 uint32_t ber_cfg_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[10] - WO */ 11711 uint32_t cl82_sync_sh_cnt_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[11] - WO */ 11712 uint32_t sync_sh_cnt_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[12] - WO */ 11713 uint32_t pcs_mon_frc : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[13] - WO */ 11714 uint32_t mode_100g : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[14] - WO */ 11715 uint32_t mode_50g : 1; /* SYS_RX_PMA_DP_main_ctrl_PCS_mode_TYPE[15] - WO */ 11716 uint32_t reserved : 16; 11717 #endif /* IS_LITTLE_ENDIAN */ 11718 } fields; 11719 } SYS_RX_PMA_DP_main_ctrl_PCS_mode_t; 11720 11721 typedef union { 11722 uint32_t data; 11723 struct { 11724 #if IS_BIG_ENDIAN 11725 uint32_t reserved : 16; 11726 uint32_t reserved_08 : 8; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[15:08] - RSVD */ 11727 uint32_t wsync_fsm : 3; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[07:05] - RO */ 11728 uint32_t wsyn_link_fail : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[04] - RO */ 11729 uint32_t dec_err : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[03] - RO */ 11730 uint32_t dec_rd_err : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[02] - RO */ 11731 uint32_t wsyn_loss_sync : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[01] - RO */ 11732 uint32_t pf_col : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[00] - RO */ 11733 #endif /* IS_BIG_ENDIAN */ 11734 #if IS_LITTLE_ENDIAN 11735 uint32_t pf_col : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[00] - RO */ 11736 uint32_t wsyn_loss_sync : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[01] - RO */ 11737 uint32_t dec_rd_err : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[02] - RO */ 11738 uint32_t dec_err : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[03] - RO */ 11739 uint32_t wsyn_link_fail : 1; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[04] - RO */ 11740 uint32_t wsync_fsm : 3; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[07:05] - RO */ 11741 uint32_t reserved_08 : 8; /* LINE_RX_PMA_DP_live_status_FC_mode_TYPE[15:08] - RSVD */ 11742 uint32_t reserved : 16; 11743 #endif /* IS_LITTLE_ENDIAN */ 11744 } fields; 11745 } LINE_RX_PMA_DP_live_status_FC_mode_t; 11746 11747 typedef LINE_RX_PMA_DP_live_status_FC_mode_t LINE_RX_PMA_DP_LIVE_STATUS_FC_MODE_t; 11748 11749 typedef union { 11750 uint32_t data; 11751 struct { 11752 #if IS_BIG_ENDIAN 11753 uint32_t reserved : 16; 11754 uint32_t reserved_08 : 8; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[15:08] - RSVD */ 11755 uint32_t ber_fsm : 2; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[07:06] - RO */ 11756 uint32_t lock_fsm : 2; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[05:04] - RO */ 11757 uint32_t hi_ber : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[03] - RO */ 11758 uint32_t block_lock : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[02] - RO */ 11759 uint32_t pcs_status : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[01] - RO */ 11760 uint32_t pf_col : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[00] - RO */ 11761 #endif /* IS_BIG_ENDIAN */ 11762 #if IS_LITTLE_ENDIAN 11763 uint32_t pf_col : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[00] - RO */ 11764 uint32_t pcs_status : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[01] - RO */ 11765 uint32_t block_lock : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[02] - RO */ 11766 uint32_t hi_ber : 1; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[03] - RO */ 11767 uint32_t lock_fsm : 2; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[05:04] - RO */ 11768 uint32_t ber_fsm : 2; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[07:06] - RO */ 11769 uint32_t reserved_08 : 8; /* LINE_RX_PMA_DP_live_status_PCS_mode_TYPE[15:08] - RSVD */ 11770 uint32_t reserved : 16; 11771 #endif /* IS_LITTLE_ENDIAN */ 11772 } fields; 11773 } LINE_RX_PMA_DP_live_status_PCS_mode_t; 11774 11775 typedef LINE_RX_PMA_DP_live_status_PCS_mode_t LINE_RX_PMA_DP_LIVE_STATUS_PCS_MODE_t; 11776 typedef union { 11777 uint32_t data; 11778 struct { 11779 #if IS_BIG_ENDIAN 11780 uint32_t reserved : 16; 11781 uint32_t wsync_fsm_lstate : 8; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[15:08] - RO */ 11782 uint32_t sync_test_end : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[07] - RO */ 11783 uint32_t sync_test_fail : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[06] - RO */ 11784 uint32_t wsyn_link_fail_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[05] - RO */ 11785 uint32_t dec_err_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[04] - RO */ 11786 uint32_t dec_rd_err_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[03] - RO */ 11787 uint32_t wsyn_sync_gain_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[02] - RO */ 11788 uint32_t wsyn_sync_lose_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[01] - RO */ 11789 uint32_t pf_col_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[00] - RO */ 11790 #endif /* IS_BIG_ENDIAN */ 11791 #if IS_LITTLE_ENDIAN 11792 uint32_t pf_col_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[00] - RO */ 11793 uint32_t wsyn_sync_lose_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[01] - RO */ 11794 uint32_t wsyn_sync_gain_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[02] - RO */ 11795 uint32_t dec_rd_err_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[03] - RO */ 11796 uint32_t dec_err_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[04] - RO */ 11797 uint32_t wsyn_link_fail_lh : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[05] - RO */ 11798 uint32_t sync_test_fail : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[06] - RO */ 11799 uint32_t sync_test_end : 1; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[07] - RO */ 11800 uint32_t wsync_fsm_lstate : 8; /* LINE_RX_PMA_DP_latched_status_FC_mode_TYPE[15:08] - RO */ 11801 uint32_t reserved : 16; 11802 #endif /* IS_LITTLE_ENDIAN */ 11803 } fields; 11804 } LINE_RX_PMA_DP_latched_status_FC_mode_t; 11805 11806 typedef LINE_RX_PMA_DP_latched_status_FC_mode_t LINE_RX_PMA_DP_LATCHED_STATUS_FC_MODE_t; 11807 11808 typedef union { 11809 uint32_t data; 11810 struct { 11811 #if IS_BIG_ENDIAN 11812 uint32_t reserved : 16; 11813 uint32_t reserved_14 : 2; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[15:14] - RSVD */ 11814 uint32_t lock_fsm_lstate : 9; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[13:05] - RO */ 11815 uint32_t receive_fault_lh : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[04] - RO */ 11816 uint32_t pcs_status_ll : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[03] - RO */ 11817 uint32_t block_lock_lh : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[02] - RO */ 11818 uint32_t block_lock_ll : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[01] - RO */ 11819 uint32_t pf_col_lh : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[00] - RO */ 11820 #endif /* IS_BIG_ENDIAN */ 11821 #if IS_LITTLE_ENDIAN 11822 uint32_t pf_col_lh : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[00] - RO */ 11823 uint32_t block_lock_ll : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[01] - RO */ 11824 uint32_t block_lock_lh : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[02] - RO */ 11825 uint32_t pcs_status_ll : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[03] - RO */ 11826 uint32_t receive_fault_lh : 1; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[04] - RO */ 11827 uint32_t lock_fsm_lstate : 9; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[13:05] - RO */ 11828 uint32_t reserved_14 : 2; /* LINE_RX_PMA_DP_latched_status_PCS_mode_TYPE[15:14] - RSVD */ 11829 uint32_t reserved : 16; 11830 #endif /* IS_LITTLE_ENDIAN */ 11831 } fields; 11832 } LINE_RX_PMA_DP_latched_status_PCS_mode_t; 11833 11834 typedef LINE_RX_PMA_DP_latched_status_PCS_mode_t LINE_RX_PMA_DP_LATCHED_STATUS_PCS_MODE_t; 11835 typedef union { 11836 uint32_t data; 11837 struct { 11838 #if IS_BIG_ENDIAN 11839 uint32_t reserved : 16; 11840 uint32_t reserved_15 : 1; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[15] - RSVD */ 11841 uint32_t ber_done : 1; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[14] - RO */ 11842 uint32_t ber_fsm_lstate : 7; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[13:07] - RO */ 11843 uint32_t ber_count : 6; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[06:01] - RO */ 11844 uint32_t hi_ber_lh : 1; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[00] - RO */ 11845 #endif /* IS_BIG_ENDIAN */ 11846 #if IS_LITTLE_ENDIAN 11847 uint32_t hi_ber_lh : 1; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[00] - RO */ 11848 uint32_t ber_count : 6; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[06:01] - RO */ 11849 uint32_t ber_fsm_lstate : 7; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[13:07] - RO */ 11850 uint32_t ber_done : 1; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[14] - RO */ 11851 uint32_t reserved_15 : 1; /* LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_TYPE[15] - RSVD */ 11852 uint32_t reserved : 16; 11853 #endif /* IS_LITTLE_ENDIAN */ 11854 } fields; 11855 } LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_t; 11856 11857 typedef LINE_RX_PMA_DP_cl49_latched_status_PCS_mode_t LINE_RX_PMA_DP_CL49_LATCHED_STATUS_PCS_MODE_t; 11858 typedef union { 11859 uint32_t data; 11860 struct { 11861 #if IS_BIG_ENDIAN 11862 uint32_t reserved : 16; 11863 uint32_t wsync_fsm_lstate : 8; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[15:08] - RO */ 11864 uint32_t sync_test_end : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[07] - RO */ 11865 uint32_t sync_test_fail : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[06] - RO */ 11866 uint32_t wsyn_link_fail_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[05] - RO */ 11867 uint32_t dec_err_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[04] - RO */ 11868 uint32_t dec_rd_err_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[03] - RO */ 11869 uint32_t wsyn_sync_gain_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[02] - RO */ 11870 uint32_t wsyn_sync_lose_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[01] - RO */ 11871 uint32_t pf_col_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[00] - RO */ 11872 #endif /* IS_BIG_ENDIAN */ 11873 #if IS_LITTLE_ENDIAN 11874 uint32_t pf_col_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[00] - RO */ 11875 uint32_t wsyn_sync_lose_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[01] - RO */ 11876 uint32_t wsyn_sync_gain_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[02] - RO */ 11877 uint32_t dec_rd_err_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[03] - RO */ 11878 uint32_t dec_err_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[04] - RO */ 11879 uint32_t wsyn_link_fail_lh : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[05] - RO */ 11880 uint32_t sync_test_fail : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[06] - RO */ 11881 uint32_t sync_test_end : 1; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[07] - RO */ 11882 uint32_t wsync_fsm_lstate : 8; /* SYS_RX_PMA_DP_latched_status_FC_mode_TYPE[15:08] - RO */ 11883 uint32_t reserved : 16; 11884 #endif /* IS_LITTLE_ENDIAN */ 11885 } fields; 11886 } SYS_RX_PMA_DP_latched_status_FC_mode_t; 11887 11888 typedef SYS_RX_PMA_DP_latched_status_FC_mode_t SYS_RX_PMA_DP_LATCHED_STATUS_FC_MODE_t; 11889 typedef union { 11890 uint32_t data; 11891 struct { 11892 #if IS_BIG_ENDIAN 11893 uint32_t reserved : 16; 11894 uint32_t reserved_14 : 2; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[15:14] - RSVD */ 11895 uint32_t lock_fsm_lstate : 9; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[13:05] - RO */ 11896 uint32_t receive_fault_lh : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[04] - RO */ 11897 uint32_t pcs_status_ll : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[03] - RO */ 11898 uint32_t block_lock_lh : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[02] - RO */ 11899 uint32_t block_lock_ll : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[01] - RO */ 11900 uint32_t pf_col_lh : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[00] - RO */ 11901 #endif /* IS_BIG_ENDIAN */ 11902 #if IS_LITTLE_ENDIAN 11903 uint32_t pf_col_lh : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[00] - RO */ 11904 uint32_t block_lock_ll : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[01] - RO */ 11905 uint32_t block_lock_lh : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[02] - RO */ 11906 uint32_t pcs_status_ll : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[03] - RO */ 11907 uint32_t receive_fault_lh : 1; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[04] - RO */ 11908 uint32_t lock_fsm_lstate : 9; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[13:05] - RO */ 11909 uint32_t reserved_14 : 2; /* SYS_RX_PMA_DP_latched_status_PCS_mode_TYPE[15:14] - RSVD */ 11910 uint32_t reserved : 16; 11911 #endif /* IS_LITTLE_ENDIAN */ 11912 } fields; 11913 } SYS_RX_PMA_DP_latched_status_PCS_mode_t; 11914 11915 typedef SYS_RX_PMA_DP_latched_status_PCS_mode_t SYS_RX_PMA_DP_LATCHED_STATUS_PCS_MODE_t; 11916 /*-----------------------------------------------*/ 11917 /* Structs for LINE_FALCON_IF Bank */ 11918 /*-----------------------------------------------*/ 11919 typedef union { 11920 uint32_t data; 11921 struct { 11922 #if IS_BIG_ENDIAN 11923 uint32_t reserved : 16; 11924 uint32_t software_mode_pmd_pll_div2and4 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[15] - WO */ 11925 uint32_t software_mode_pmd_rterm200 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[14] - WO */ 11926 uint32_t software_mode_pmd_ext_los_0 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[13] - WO */ 11927 uint32_t software_mode_pmd_ext_los_1 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[12] - WO */ 11928 uint32_t software_mode_pmd_ext_los_2 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[11] - WO */ 11929 uint32_t software_mode_pmd_ext_los_3 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[10] - WO */ 11930 uint32_t software_mode_pmd_ln_dp_h_rstb : 4; /* LINE_FALCON_IF_soft_mode0_TYPE[09:06] - WO */ 11931 uint32_t software_mode_pmd_ln_h_rstb_0 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[05] - WO */ 11932 uint32_t software_mode_pmd_ln_h_rstb_1 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[04] - WO */ 11933 uint32_t software_mode_pmd_ln_h_rstb_2 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[03] - WO */ 11934 uint32_t software_mode_pmd_ln_h_rstb_3 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[02] - WO */ 11935 uint32_t software_mode_pmd_core_dp_h_rstb : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[01] - WO */ 11936 uint32_t software_mode_pmd_por_h_rstb : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[00] - WO */ 11937 #endif /* IS_BIG_ENDIAN */ 11938 #if IS_LITTLE_ENDIAN 11939 uint32_t software_mode_pmd_por_h_rstb : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[00] - WO */ 11940 uint32_t software_mode_pmd_core_dp_h_rstb : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[01] - WO */ 11941 uint32_t software_mode_pmd_ln_h_rstb_3 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[02] - WO */ 11942 uint32_t software_mode_pmd_ln_h_rstb_2 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[03] - WO */ 11943 uint32_t software_mode_pmd_ln_h_rstb_1 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[04] - WO */ 11944 uint32_t software_mode_pmd_ln_h_rstb_0 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[05] - WO */ 11945 uint32_t software_mode_pmd_ln_dp_h_rstb : 4; /* LINE_FALCON_IF_soft_mode0_TYPE[09:06] - WO */ 11946 uint32_t software_mode_pmd_ext_los_3 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[10] - WO */ 11947 uint32_t software_mode_pmd_ext_los_2 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[11] - WO */ 11948 uint32_t software_mode_pmd_ext_los_1 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[12] - WO */ 11949 uint32_t software_mode_pmd_ext_los_0 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[13] - WO */ 11950 uint32_t software_mode_pmd_rterm200 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[14] - WO */ 11951 uint32_t software_mode_pmd_pll_div2and4 : 1; /* LINE_FALCON_IF_soft_mode0_TYPE[15] - WO */ 11952 uint32_t reserved : 16; 11953 #endif /* IS_LITTLE_ENDIAN */ 11954 } fields; 11955 } LINE_FALCON_IF_soft_mode0_t; 11956 11957 typedef LINE_FALCON_IF_soft_mode0_t LINE_FALCON_IF_SOFT_MODE0_t; 11958 11959 typedef union { 11960 uint32_t data; 11961 struct { 11962 #if IS_BIG_ENDIAN 11963 uint32_t reserved : 16; 11964 uint32_t rsvd1 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[15] - WO */ 11965 uint32_t pmd_pll_div4 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[14] - WO */ 11966 uint32_t pmd_pll_div2 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[13] - WO */ 11967 uint32_t pmd_rterm200 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[12] - WO */ 11968 uint32_t tx_drv_hv_disable : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[11] - WO */ 11969 uint32_t pmd_iddq : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[10] - WO */ 11970 uint32_t pmd_ln_dp_h_rstb : 4; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[09:06] - WO */ 11971 uint32_t pmd_ln_h_rstb : 4; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[05:02] - WO */ 11972 uint32_t pmd_core_dp_h_rstb : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[01] - WO */ 11973 uint32_t pmd_por_h_rstb : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[00] - WO */ 11974 #endif /* IS_BIG_ENDIAN */ 11975 #if IS_LITTLE_ENDIAN 11976 uint32_t pmd_por_h_rstb : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[00] - WO */ 11977 uint32_t pmd_core_dp_h_rstb : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[01] - WO */ 11978 uint32_t pmd_ln_h_rstb : 4; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[05:02] - WO */ 11979 uint32_t pmd_ln_dp_h_rstb : 4; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[09:06] - WO */ 11980 uint32_t pmd_iddq : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[10] - WO */ 11981 uint32_t tx_drv_hv_disable : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[11] - WO */ 11982 uint32_t pmd_rterm200 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[12] - WO */ 11983 uint32_t pmd_pll_div2 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[13] - WO */ 11984 uint32_t pmd_pll_div4 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[14] - WO */ 11985 uint32_t rsvd1 : 1; /* LINE_FALCON_IF_c_and_r_cntl_TYPE[15] - WO */ 11986 uint32_t reserved : 16; 11987 #endif /* IS_LITTLE_ENDIAN */ 11988 } fields; 11989 } LINE_FALCON_IF_c_and_r_cntl_t; 11990 11991 typedef LINE_FALCON_IF_c_and_r_cntl_t LINE_FALCON_IF_C_AND_R_CNTL_t; 11992 11993 /*-----------------------------------------------*/ 11994 /* Structs for SYS_FALCON_IF Bank */ 11995 /*-----------------------------------------------*/ 11996 typedef union { 11997 uint32_t data; 11998 struct { 11999 #if IS_BIG_ENDIAN 12000 uint32_t reserved : 16; 12001 uint32_t software_mode_pmd_pll_div2and4 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[15] - WO */ 12002 uint32_t software_mode_pmd_rterm200 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[14] - WO */ 12003 uint32_t software_mode_pmd_ext_los_0 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[13] - WO */ 12004 uint32_t software_mode_pmd_ext_los_1 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[12] - WO */ 12005 uint32_t software_mode_pmd_ext_los_2 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[11] - WO */ 12006 uint32_t software_mode_pmd_ext_los_3 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[10] - WO */ 12007 uint32_t software_mode_pmd_ln_dp_h_rstb : 4; /* SYS_FALCON_IF_soft_mode0_TYPE[09:06] - WO */ 12008 uint32_t software_mode_pmd_ln_h_rstb_0 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[05] - WO */ 12009 uint32_t software_mode_pmd_ln_h_rstb_1 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[04] - WO */ 12010 uint32_t software_mode_pmd_ln_h_rstb_2 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[03] - WO */ 12011 uint32_t software_mode_pmd_ln_h_rstb_3 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[02] - WO */ 12012 uint32_t software_mode_pmd_core_dp_h_rstb : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[01] - WO */ 12013 uint32_t software_mode_pmd_por_h_rstb : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[00] - WO */ 12014 #endif /* IS_BIG_ENDIAN */ 12015 #if IS_LITTLE_ENDIAN 12016 uint32_t software_mode_pmd_por_h_rstb : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[00] - WO */ 12017 uint32_t software_mode_pmd_core_dp_h_rstb : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[01] - WO */ 12018 uint32_t software_mode_pmd_ln_h_rstb_3 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[02] - WO */ 12019 uint32_t software_mode_pmd_ln_h_rstb_2 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[03] - WO */ 12020 uint32_t software_mode_pmd_ln_h_rstb_1 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[04] - WO */ 12021 uint32_t software_mode_pmd_ln_h_rstb_0 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[05] - WO */ 12022 uint32_t software_mode_pmd_ln_dp_h_rstb : 4; /* SYS_FALCON_IF_soft_mode0_TYPE[09:06] - WO */ 12023 uint32_t software_mode_pmd_ext_los_3 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[10] - WO */ 12024 uint32_t software_mode_pmd_ext_los_2 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[11] - WO */ 12025 uint32_t software_mode_pmd_ext_los_1 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[12] - WO */ 12026 uint32_t software_mode_pmd_ext_los_0 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[13] - WO */ 12027 uint32_t software_mode_pmd_rterm200 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[14] - WO */ 12028 uint32_t software_mode_pmd_pll_div2and4 : 1; /* SYS_FALCON_IF_soft_mode0_TYPE[15] - WO */ 12029 uint32_t reserved : 16; 12030 #endif /* IS_LITTLE_ENDIAN */ 12031 } fields; 12032 } SYS_FALCON_IF_soft_mode0_t; 12033 12034 typedef SYS_FALCON_IF_soft_mode0_t SYS_FALCON_IF_SOFT_MODE0_t; 12035 12036 12037 typedef union { 12038 uint32_t data; 12039 struct { 12040 #if IS_BIG_ENDIAN 12041 uint32_t reserved : 16; 12042 uint32_t rsvd1 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[15] - WO */ 12043 uint32_t pmd_pll_div4 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[14] - WO */ 12044 uint32_t pmd_pll_div2 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[13] - WO */ 12045 uint32_t pmd_rterm200 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[12] - WO */ 12046 uint32_t tx_drv_hv_disable : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[11] - WO */ 12047 uint32_t pmd_iddq : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[10] - WO */ 12048 uint32_t pmd_ln_dp_h_rstb : 4; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[09:06] - WO */ 12049 uint32_t pmd_ln_h_rstb : 4; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[05:02] - WO */ 12050 uint32_t pmd_core_dp_h_rstb : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[01] - WO */ 12051 uint32_t pmd_por_h_rstb : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[00] - WO */ 12052 #endif /* IS_BIG_ENDIAN */ 12053 #if IS_LITTLE_ENDIAN 12054 uint32_t pmd_por_h_rstb : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[00] - WO */ 12055 uint32_t pmd_core_dp_h_rstb : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[01] - WO */ 12056 uint32_t pmd_ln_h_rstb : 4; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[05:02] - WO */ 12057 uint32_t pmd_ln_dp_h_rstb : 4; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[09:06] - WO */ 12058 uint32_t pmd_iddq : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[10] - WO */ 12059 uint32_t tx_drv_hv_disable : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[11] - WO */ 12060 uint32_t pmd_rterm200 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[12] - WO */ 12061 uint32_t pmd_pll_div2 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[13] - WO */ 12062 uint32_t pmd_pll_div4 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[14] - WO */ 12063 uint32_t rsvd1 : 1; /* SYS_FALCON_IF_c_and_r_cntl_TYPE[15] - WO */ 12064 uint32_t reserved : 16; 12065 #endif /* IS_LITTLE_ENDIAN */ 12066 } fields; 12067 } SYS_FALCON_IF_c_and_r_cntl_t; 12068 12069 typedef SYS_FALCON_IF_c_and_r_cntl_t SYS_FALCON_IF_C_AND_R_CNTL_t; 12070 typedef union { 12071 uint32_t data; 12072 struct { 12073 #if IS_BIG_ENDIAN 12074 uint32_t reserved : 16; 12075 uint32_t energy_detect_mask_count : 5; /* SIGDET_SIGDET_CTRL_1_TYPE[15:11] - RW */ 12076 uint32_t reserved_09 : 2; /* SIGDET_SIGDET_CTRL_1_TYPE[10:09] - RSVD */ 12077 uint32_t signal_detect_frc_val : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[08] - RW */ 12078 uint32_t signal_detect_frc : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[07] - RW */ 12079 uint32_t energy_detect_frc_val : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[06] - RW */ 12080 uint32_t energy_detect_frc : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[05] - RW */ 12081 uint32_t signal_detect_filter_1us : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[04] - RW */ 12082 uint32_t ignore_lp_mode : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[03] - RW */ 12083 uint32_t ext_los_inv : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[02] - RW */ 12084 uint32_t ext_los_en : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[01] - RW */ 12085 uint32_t afe_signal_detect_dis : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[00] - RW */ 12086 #endif /* IS_BIG_ENDIAN */ 12087 #if IS_LITTLE_ENDIAN 12088 uint32_t afe_signal_detect_dis : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[00] - RW */ 12089 uint32_t ext_los_en : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[01] - RW */ 12090 uint32_t ext_los_inv : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[02] - RW */ 12091 uint32_t ignore_lp_mode : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[03] - RW */ 12092 uint32_t signal_detect_filter_1us : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[04] - RW */ 12093 uint32_t energy_detect_frc : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[05] - RW */ 12094 uint32_t energy_detect_frc_val : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[06] - RW */ 12095 uint32_t signal_detect_frc : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[07] - RW */ 12096 uint32_t signal_detect_frc_val : 1; /* SIGDET_SIGDET_CTRL_1_TYPE[08] - RW */ 12097 uint32_t reserved_09 : 2; /* SIGDET_SIGDET_CTRL_1_TYPE[10:09] - RSVD */ 12098 uint32_t energy_detect_mask_count : 5; /* SIGDET_SIGDET_CTRL_1_TYPE[15:11] - RW */ 12099 uint32_t reserved : 16; 12100 #endif /* IS_LITTLE_ENDIAN */ 12101 } fields; 12102 } SIGDET_SIGDET_CTRL_1_t; 12103 12104 typedef union { 12105 uint32_t data; 12106 struct { 12107 #if IS_BIG_ENDIAN 12108 uint32_t reserved : 16; 12109 uint32_t ref_clk : 7; 12110 uint32_t highgig : 1; 12111 uint32_t intf_type_ln7 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[7] - RW */ 12112 uint32_t intf_type_ln6 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[6] - RW */ 12113 uint32_t intf_type_ln5 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[5] - RW */ 12114 uint32_t intf_type_ln4 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[4] - RW */ 12115 uint32_t intf_type_ln3 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[3] - RW */ 12116 uint32_t intf_type_ln2 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[2] - RW */ 12117 uint32_t intf_type_ln1 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[1] - RW */ 12118 uint32_t intf_type_ln0 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[0] - RW */ 12119 #endif /* IS_BIG_ENDIAN */ 12120 #if IS_LITTLE_ENDIAN 12121 uint32_t intf_type_ln0 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[0] - RW */ 12122 uint32_t intf_type_ln1 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[1] - RW */ 12123 uint32_t intf_type_ln2 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[2] - RW */ 12124 uint32_t intf_type_ln3 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[3] - RW */ 12125 uint32_t intf_type_ln4 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[4] - RW */ 12126 uint32_t intf_type_ln5 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[5] - RW */ 12127 uint32_t intf_type_ln6 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[6] - RW */ 12128 uint32_t intf_type_ln7 : 1; /* FUR_GEN_CNTRLS_micro_sync_6_t[7] - RW */ 12129 uint32_t highgig : 1; 12130 uint32_t ref_clk : 7; 12131 uint32_t reserved : 16; 12132 12133 #endif /* IS_LITTLE_ENDIAN */ 12134 } fields; 12135 } FUR_GEN_CNTRLS_micro_sync_6_t; 12136 12137 typedef union { 12138 uint32_t data; 12139 struct { 12140 #if IS_BIG_ENDIAN 12141 uint32_t reserved : 16; 12142 uint32_t intf_type_ln7 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[15:14] - RW */ 12143 uint32_t intf_type_ln6 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[13:12] - RW */ 12144 uint32_t intf_type_ln5 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[11:10] - RW */ 12145 uint32_t intf_type_ln4 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[09:08] - RW */ 12146 uint32_t intf_type_ln3 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[07:06] - RW */ 12147 uint32_t intf_type_ln2 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[05:04] - RW */ 12148 uint32_t intf_type_ln1 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[03:02] - RW */ 12149 uint32_t intf_type_ln0 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[01:00] - RW */ 12150 #endif /* IS_BIG_ENDIAN */ 12151 #if IS_LITTLE_ENDIAN 12152 uint32_t intf_type_ln0 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[01:00] - RW */ 12153 uint32_t intf_type_ln1 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[03:02] - RW */ 12154 uint32_t intf_type_ln2 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[05:04] - RW */ 12155 uint32_t intf_type_ln3 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[07:06] - RW */ 12156 uint32_t intf_type_ln4 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[09:08] - RW */ 12157 uint32_t intf_type_ln5 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[11:10] - RW */ 12158 uint32_t intf_type_ln6 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[13:12] - RW */ 12159 uint32_t intf_type_ln7 : 2; /* FUR_GEN_CNTRLS_micro_sync_7_t[15:14] - RW */ 12160 uint32_t reserved : 16; 12161 #endif /* IS_LITTLE_ENDIAN */ 12162 } fields; 12163 } FUR_GEN_CNTRLS_micro_sync_7_t; 12164 typedef union { 12165 uint32_t data; 12166 struct { 12167 #if IS_BIG_ENDIAN 12168 uint32_t reserved : 16; 12169 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[15:12] - WO */ 12170 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[11] - WO */ 12171 uint32_t invert_en : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[10] - WO */ 12172 uint32_t ibof : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[09] - WO */ 12173 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[08] - RSVD */ 12174 uint32_t sel2 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[07] - WO */ 12175 uint32_t sel1 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[06] - WO */ 12176 uint32_t sel0 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[05] - WO */ 12177 uint32_t ind : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[04] - WO */ 12178 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[03] - RSVD */ 12179 uint32_t pdn : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[02] - WO */ 12180 uint32_t pup : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[01] - WO */ 12181 uint32_t oeb : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[00] - WO */ 12182 #endif /* IS_BIG_ENDIAN */ 12183 #if IS_LITTLE_ENDIAN 12184 uint32_t oeb : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[00] - WO */ 12185 uint32_t pup : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[01] - WO */ 12186 uint32_t pdn : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[02] - WO */ 12187 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[03] - RSVD */ 12188 uint32_t ind : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[04] - WO */ 12189 uint32_t sel0 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[05] - WO */ 12190 uint32_t sel1 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[06] - WO */ 12191 uint32_t sel2 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[07] - WO */ 12192 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[08] - RSVD */ 12193 uint32_t ibof : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[09] - WO */ 12194 uint32_t invert_en : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[10] - WO */ 12195 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[11] - WO */ 12196 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_ext_uc_rstb_control_TYPE[15:12] - WO */ 12197 uint32_t reserved : 16; 12198 #endif /* IS_LITTLE_ENDIAN */ 12199 } fields; 12200 } FUR_PAD_CTRL_ext_uc_rstb_control_t; 12201 12202 typedef FUR_PAD_CTRL_ext_uc_rstb_control_t FUR_PAD_CTRL_EXT_UC_RSTB_CONTROL_t; 12203 typedef union { 12204 uint32_t data; 12205 struct { 12206 #if IS_BIG_ENDIAN 12207 uint32_t reserved : 16; 12208 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_mod_absent_control_TYPE[15:12] - WO */ 12209 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[11] - WO */ 12210 uint32_t invert_en : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[10] - WO */ 12211 uint32_t ibof : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[09] - WO */ 12212 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[08] - RSVD */ 12213 uint32_t sel2 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[07] - WO */ 12214 uint32_t sel1 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[06] - WO */ 12215 uint32_t sel0 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[05] - WO */ 12216 uint32_t ind : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[04] - WO */ 12217 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[03] - RSVD */ 12218 uint32_t pdn : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[02] - WO */ 12219 uint32_t pup : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[01] - WO */ 12220 uint32_t oeb : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[00] - WO */ 12221 #endif /* IS_BIG_ENDIAN */ 12222 #if IS_LITTLE_ENDIAN 12223 uint32_t oeb : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[00] - WO */ 12224 uint32_t pup : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[01] - WO */ 12225 uint32_t pdn : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[02] - WO */ 12226 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[03] - RSVD */ 12227 uint32_t ind : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[04] - WO */ 12228 uint32_t sel0 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[05] - WO */ 12229 uint32_t sel1 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[06] - WO */ 12230 uint32_t sel2 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[07] - WO */ 12231 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[08] - RSVD */ 12232 uint32_t ibof : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[09] - WO */ 12233 uint32_t invert_en : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[10] - WO */ 12234 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_mod_absent_control_TYPE[11] - WO */ 12235 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_mod_absent_control_TYPE[15:12] - WO */ 12236 uint32_t reserved : 16; 12237 #endif /* IS_LITTLE_ENDIAN */ 12238 } fields; 12239 } FUR_PAD_CTRL_mod_absent_control_t; 12240 12241 typedef FUR_PAD_CTRL_mod_absent_control_t FUR_PAD_CTRL_MOD_ABSENT_CONTROL_t; 12242 typedef union { 12243 uint32_t data; 12244 struct { 12245 #if IS_BIG_ENDIAN 12246 uint32_t reserved : 16; 12247 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_mod_absent_status_TYPE[15:03] - RSVD */ 12248 uint32_t din : 1; /* FUR_PAD_CTRL_mod_absent_status_TYPE[02] - RO */ 12249 uint32_t din_ll : 1; /* FUR_PAD_CTRL_mod_absent_status_TYPE[01] - RO */ 12250 uint32_t din_lh : 1; /* FUR_PAD_CTRL_mod_absent_status_TYPE[00] - RO */ 12251 #endif /* IS_BIG_ENDIAN */ 12252 #if IS_LITTLE_ENDIAN 12253 uint32_t din_lh : 1; /* FUR_PAD_CTRL_mod_absent_status_TYPE[00] - RO */ 12254 uint32_t din_ll : 1; /* FUR_PAD_CTRL_mod_absent_status_TYPE[01] - RO */ 12255 uint32_t din : 1; /* FUR_PAD_CTRL_mod_absent_status_TYPE[02] - RO */ 12256 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_mod_absent_status_TYPE[15:03] - RSVD */ 12257 uint32_t reserved : 16; 12258 #endif /* IS_LITTLE_ENDIAN */ 12259 } fields; 12260 } FUR_PAD_CTRL_mod_absent_status_t; 12261 12262 typedef FUR_PAD_CTRL_mod_absent_status_t FUR_PAD_CTRL_MOD_ABSENT_STATUS_t; 12263 12264 typedef union { 12265 uint32_t data; 12266 struct { 12267 #if IS_BIG_ENDIAN 12268 uint32_t reserved : 16; 12269 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_opttxenb_control_TYPE[15:12] - WO */ 12270 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[11] - WO */ 12271 uint32_t invert_en : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[10] - WO */ 12272 uint32_t ibof : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[09] - WO */ 12273 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[08] - RSVD */ 12274 uint32_t sel2 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[07] - WO */ 12275 uint32_t sel1 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[06] - WO */ 12276 uint32_t sel0 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[05] - WO */ 12277 uint32_t ind : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[04] - WO */ 12278 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[03] - RSVD */ 12279 uint32_t pdn : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[02] - WO */ 12280 uint32_t pup : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[01] - WO */ 12281 uint32_t oeb : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[00] - WO */ 12282 #endif /* IS_BIG_ENDIAN */ 12283 #if IS_LITTLE_ENDIAN 12284 uint32_t oeb : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[00] - WO */ 12285 uint32_t pup : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[01] - WO */ 12286 uint32_t pdn : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[02] - WO */ 12287 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[03] - RSVD */ 12288 uint32_t ind : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[04] - WO */ 12289 uint32_t sel0 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[05] - WO */ 12290 uint32_t sel1 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[06] - WO */ 12291 uint32_t sel2 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[07] - WO */ 12292 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[08] - RSVD */ 12293 uint32_t ibof : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[09] - WO */ 12294 uint32_t invert_en : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[10] - WO */ 12295 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_opttxenb_control_TYPE[11] - WO */ 12296 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_opttxenb_control_TYPE[15:12] - WO */ 12297 uint32_t reserved : 16; 12298 #endif /* IS_LITTLE_ENDIAN */ 12299 } fields; 12300 } FUR_PAD_CTRL_opttxenb_control_t; 12301 12302 typedef FUR_PAD_CTRL_opttxenb_control_t FUR_PAD_CTRL_OPTTXENB_CONTROL_t; 12303 12304 12305 typedef union { 12306 uint32_t data; 12307 struct { 12308 #if IS_BIG_ENDIAN 12309 uint32_t reserved : 16; 12310 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_opttxenb_status_TYPE[15:03] - RSVD */ 12311 uint32_t din : 1; /* FUR_PAD_CTRL_opttxenb_status_TYPE[02] - RO */ 12312 uint32_t din_ll : 1; /* FUR_PAD_CTRL_opttxenb_status_TYPE[01] - RO */ 12313 uint32_t din_lh : 1; /* FUR_PAD_CTRL_opttxenb_status_TYPE[00] - RO */ 12314 #endif /* IS_BIG_ENDIAN */ 12315 #if IS_LITTLE_ENDIAN 12316 uint32_t din_lh : 1; /* FUR_PAD_CTRL_opttxenb_status_TYPE[00] - RO */ 12317 uint32_t din_ll : 1; /* FUR_PAD_CTRL_opttxenb_status_TYPE[01] - RO */ 12318 uint32_t din : 1; /* FUR_PAD_CTRL_opttxenb_status_TYPE[02] - RO */ 12319 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_opttxenb_status_TYPE[15:03] - RSVD */ 12320 uint32_t reserved : 16; 12321 #endif /* IS_LITTLE_ENDIAN */ 12322 } fields; 12323 } FUR_PAD_CTRL_opttxenb_status_t; 12324 12325 typedef FUR_PAD_CTRL_opttxenb_status_t FUR_PAD_CTRL_OPTTXENB_STATUS_t; 12326 12327 typedef union { 12328 uint32_t data; 12329 struct { 12330 #if IS_BIG_ENDIAN 12331 uint32_t reserved : 16; 12332 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[15:12] - WO */ 12333 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[11] - WO */ 12334 uint32_t invert_en : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[10] - WO */ 12335 uint32_t ibof : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[09] - WO */ 12336 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[08] - RSVD */ 12337 uint32_t sel2 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[07] - WO */ 12338 uint32_t sel1 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[06] - WO */ 12339 uint32_t sel0 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[05] - WO */ 12340 uint32_t ind : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[04] - WO */ 12341 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[03] - RSVD */ 12342 uint32_t pdn : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[02] - WO */ 12343 uint32_t pup : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[01] - WO */ 12344 uint32_t oeb : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[00] - WO */ 12345 #endif /* IS_BIG_ENDIAN */ 12346 #if IS_LITTLE_ENDIAN 12347 uint32_t oeb : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[00] - WO */ 12348 uint32_t pup : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[01] - WO */ 12349 uint32_t pdn : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[02] - WO */ 12350 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[03] - RSVD */ 12351 uint32_t ind : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[04] - WO */ 12352 uint32_t sel0 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[05] - WO */ 12353 uint32_t sel1 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[06] - WO */ 12354 uint32_t sel2 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[07] - WO */ 12355 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[08] - RSVD */ 12356 uint32_t ibof : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[09] - WO */ 12357 uint32_t invert_en : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[10] - WO */ 12358 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[11] - WO */ 12359 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_mod_rxlos_control_TYPE[15:12] - WO */ 12360 uint32_t reserved : 16; 12361 #endif /* IS_LITTLE_ENDIAN */ 12362 } fields; 12363 } FUR_PAD_CTRL_mod_rxlos_control_t; 12364 12365 typedef FUR_PAD_CTRL_mod_rxlos_control_t FUR_PAD_CTRL_MOD_RXLOS_CONTROL_t; 12366 12367 typedef union { 12368 uint32_t data; 12369 struct { 12370 #if IS_BIG_ENDIAN 12371 uint32_t reserved : 16; 12372 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[15:03] - RSVD */ 12373 uint32_t din : 1; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[02] - RO */ 12374 uint32_t din_ll : 1; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[01] - RO */ 12375 uint32_t din_lh : 1; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[00] - RO */ 12376 #endif /* IS_BIG_ENDIAN */ 12377 #if IS_LITTLE_ENDIAN 12378 uint32_t din_lh : 1; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[00] - RO */ 12379 uint32_t din_ll : 1; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[01] - RO */ 12380 uint32_t din : 1; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[02] - RO */ 12381 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_mod_rxlos_status_TYPE[15:03] - RSVD */ 12382 uint32_t reserved : 16; 12383 #endif /* IS_LITTLE_ENDIAN */ 12384 } fields; 12385 } FUR_PAD_CTRL_mod_rxlos_status_t; 12386 12387 typedef FUR_PAD_CTRL_mod_rxlos_status_t FUR_PAD_CTRL_MOD_RXLOS_STATUS_t; 12388 12389 12390 typedef union { 12391 uint32_t data; 12392 struct { 12393 #if IS_BIG_ENDIAN 12394 uint32_t reserved : 16; 12395 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_0_control_TYPE[15:12] - WO */ 12396 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[11] - WO */ 12397 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[10] - WO */ 12398 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[09] - WO */ 12399 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[08] - RSVD */ 12400 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[07] - WO */ 12401 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[06] - WO */ 12402 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[05] - WO */ 12403 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[04] - WO */ 12404 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[03] - RSVD */ 12405 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[02] - WO */ 12406 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[01] - WO */ 12407 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[00] - WO */ 12408 #endif /* IS_BIG_ENDIAN */ 12409 #if IS_LITTLE_ENDIAN 12410 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[00] - WO */ 12411 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[01] - WO */ 12412 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[02] - WO */ 12413 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[03] - RSVD */ 12414 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[04] - WO */ 12415 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[05] - WO */ 12416 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[06] - WO */ 12417 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[07] - WO */ 12418 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[08] - RSVD */ 12419 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[09] - WO */ 12420 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[10] - WO */ 12421 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_0_control_TYPE[11] - WO */ 12422 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_0_control_TYPE[15:12] - WO */ 12423 uint32_t reserved : 16; 12424 #endif /* IS_LITTLE_ENDIAN */ 12425 } fields; 12426 } FUR_PAD_CTRL_gpio_0_control_t; 12427 12428 typedef FUR_PAD_CTRL_gpio_0_control_t FUR_PAD_CTRL_GPIO_0_CONTROL_t; 12429 12430 12431 typedef union { 12432 uint32_t data; 12433 struct { 12434 #if IS_BIG_ENDIAN 12435 uint32_t reserved : 16; 12436 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_0_status_TYPE[15:03] - RSVD */ 12437 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_0_status_TYPE[02] - RO */ 12438 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_0_status_TYPE[01] - RO */ 12439 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_0_status_TYPE[00] - RO */ 12440 #endif /* IS_BIG_ENDIAN */ 12441 #if IS_LITTLE_ENDIAN 12442 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_0_status_TYPE[00] - RO */ 12443 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_0_status_TYPE[01] - RO */ 12444 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_0_status_TYPE[02] - RO */ 12445 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_0_status_TYPE[15:03] - RSVD */ 12446 uint32_t reserved : 16; 12447 #endif /* IS_LITTLE_ENDIAN */ 12448 } fields; 12449 } FUR_PAD_CTRL_gpio_0_status_t; 12450 12451 typedef FUR_PAD_CTRL_gpio_0_status_t FUR_PAD_CTRL_GPIO_0_STATUS_t; 12452 12453 12454 typedef union { 12455 uint32_t data; 12456 struct { 12457 #if IS_BIG_ENDIAN 12458 uint32_t reserved : 16; 12459 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_1_control_TYPE[15:12] - WO */ 12460 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[11] - WO */ 12461 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[10] - WO */ 12462 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[09] - WO */ 12463 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[08] - RSVD */ 12464 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[07] - WO */ 12465 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[06] - WO */ 12466 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[05] - WO */ 12467 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[04] - WO */ 12468 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[03] - RSVD */ 12469 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[02] - WO */ 12470 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[01] - WO */ 12471 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[00] - WO */ 12472 #endif /* IS_BIG_ENDIAN */ 12473 #if IS_LITTLE_ENDIAN 12474 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[00] - WO */ 12475 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[01] - WO */ 12476 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[02] - WO */ 12477 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[03] - RSVD */ 12478 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[04] - WO */ 12479 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[05] - WO */ 12480 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[06] - WO */ 12481 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[07] - WO */ 12482 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[08] - RSVD */ 12483 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[09] - WO */ 12484 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[10] - WO */ 12485 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_1_control_TYPE[11] - WO */ 12486 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_1_control_TYPE[15:12] - WO */ 12487 uint32_t reserved : 16; 12488 #endif /* IS_LITTLE_ENDIAN */ 12489 } fields; 12490 } FUR_PAD_CTRL_gpio_1_control_t; 12491 12492 typedef FUR_PAD_CTRL_gpio_1_control_t FUR_PAD_CTRL_GPIO_1_CONTROL_t; 12493 12494 12495 typedef union { 12496 uint32_t data; 12497 struct { 12498 #if IS_BIG_ENDIAN 12499 uint32_t reserved : 16; 12500 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_1_status_TYPE[15:03] - RSVD */ 12501 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_1_status_TYPE[02] - RO */ 12502 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_1_status_TYPE[01] - RO */ 12503 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_1_status_TYPE[00] - RO */ 12504 #endif /* IS_BIG_ENDIAN */ 12505 #if IS_LITTLE_ENDIAN 12506 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_1_status_TYPE[00] - RO */ 12507 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_1_status_TYPE[01] - RO */ 12508 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_1_status_TYPE[02] - RO */ 12509 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_1_status_TYPE[15:03] - RSVD */ 12510 uint32_t reserved : 16; 12511 #endif /* IS_LITTLE_ENDIAN */ 12512 } fields; 12513 } FUR_PAD_CTRL_gpio_1_status_t; 12514 12515 typedef FUR_PAD_CTRL_gpio_1_status_t FUR_PAD_CTRL_GPIO_1_STATUS_t; 12516 12517 typedef union { 12518 uint32_t data; 12519 struct { 12520 #if IS_BIG_ENDIAN 12521 uint32_t reserved : 16; 12522 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_2_control_TYPE[15:12] - WO */ 12523 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[11] - WO */ 12524 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[10] - WO */ 12525 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[09] - WO */ 12526 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[08] - RSVD */ 12527 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[07] - WO */ 12528 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[06] - WO */ 12529 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[05] - WO */ 12530 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[04] - WO */ 12531 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[03] - RSVD */ 12532 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[02] - WO */ 12533 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[01] - WO */ 12534 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[00] - WO */ 12535 #endif /* IS_BIG_ENDIAN */ 12536 #if IS_LITTLE_ENDIAN 12537 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[00] - WO */ 12538 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[01] - WO */ 12539 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[02] - WO */ 12540 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[03] - RSVD */ 12541 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[04] - WO */ 12542 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[05] - WO */ 12543 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[06] - WO */ 12544 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[07] - WO */ 12545 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[08] - RSVD */ 12546 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[09] - WO */ 12547 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[10] - WO */ 12548 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_2_control_TYPE[11] - WO */ 12549 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_2_control_TYPE[15:12] - WO */ 12550 uint32_t reserved : 16; 12551 #endif /* IS_LITTLE_ENDIAN */ 12552 } fields; 12553 } FUR_PAD_CTRL_gpio_2_control_t; 12554 12555 typedef FUR_PAD_CTRL_gpio_2_control_t FUR_PAD_CTRL_GPIO_2_CONTROL_t; 12556 12557 typedef union { 12558 uint32_t data; 12559 struct { 12560 #if IS_BIG_ENDIAN 12561 uint32_t reserved : 16; 12562 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_2_status_TYPE[15:03] - RSVD */ 12563 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_2_status_TYPE[02] - RO */ 12564 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_2_status_TYPE[01] - RO */ 12565 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_2_status_TYPE[00] - RO */ 12566 #endif /* IS_BIG_ENDIAN */ 12567 #if IS_LITTLE_ENDIAN 12568 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_2_status_TYPE[00] - RO */ 12569 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_2_status_TYPE[01] - RO */ 12570 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_2_status_TYPE[02] - RO */ 12571 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_2_status_TYPE[15:03] - RSVD */ 12572 uint32_t reserved : 16; 12573 #endif /* IS_LITTLE_ENDIAN */ 12574 } fields; 12575 } FUR_PAD_CTRL_gpio_2_status_t; 12576 12577 typedef FUR_PAD_CTRL_gpio_2_status_t FUR_PAD_CTRL_GPIO_2_STATUS_t; 12578 12579 typedef union { 12580 uint32_t data; 12581 struct { 12582 #if IS_BIG_ENDIAN 12583 uint32_t reserved : 16; 12584 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_3_control_TYPE[15:12] - WO */ 12585 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[11] - WO */ 12586 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[10] - WO */ 12587 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[09] - WO */ 12588 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[08] - RSVD */ 12589 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[07] - WO */ 12590 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[06] - WO */ 12591 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[05] - WO */ 12592 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[04] - WO */ 12593 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[03] - RSVD */ 12594 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[02] - WO */ 12595 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[01] - WO */ 12596 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[00] - WO */ 12597 #endif /* IS_BIG_ENDIAN */ 12598 #if IS_LITTLE_ENDIAN 12599 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[00] - WO */ 12600 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[01] - WO */ 12601 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[02] - WO */ 12602 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[03] - RSVD */ 12603 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[04] - WO */ 12604 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[05] - WO */ 12605 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[06] - WO */ 12606 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[07] - WO */ 12607 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[08] - RSVD */ 12608 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[09] - WO */ 12609 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[10] - WO */ 12610 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_3_control_TYPE[11] - WO */ 12611 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_3_control_TYPE[15:12] - WO */ 12612 uint32_t reserved : 16; 12613 #endif /* IS_LITTLE_ENDIAN */ 12614 } fields; 12615 } FUR_PAD_CTRL_gpio_3_control_t; 12616 12617 typedef FUR_PAD_CTRL_gpio_3_control_t FUR_PAD_CTRL_GPIO_3_CONTROL_t; 12618 12619 typedef union { 12620 uint32_t data; 12621 struct { 12622 #if IS_BIG_ENDIAN 12623 uint32_t reserved : 16; 12624 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_3_status_TYPE[15:03] - RSVD */ 12625 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_3_status_TYPE[02] - RO */ 12626 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_3_status_TYPE[01] - RO */ 12627 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_3_status_TYPE[00] - RO */ 12628 #endif /* IS_BIG_ENDIAN */ 12629 #if IS_LITTLE_ENDIAN 12630 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_3_status_TYPE[00] - RO */ 12631 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_3_status_TYPE[01] - RO */ 12632 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_3_status_TYPE[02] - RO */ 12633 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_3_status_TYPE[15:03] - RSVD */ 12634 uint32_t reserved : 16; 12635 #endif /* IS_LITTLE_ENDIAN */ 12636 } fields; 12637 } FUR_PAD_CTRL_gpio_3_status_t; 12638 12639 typedef FUR_PAD_CTRL_gpio_3_status_t FUR_PAD_CTRL_GPIO_3_STATUS_t; 12640 12641 typedef union { 12642 uint32_t data; 12643 struct { 12644 #if IS_BIG_ENDIAN 12645 uint32_t reserved : 16; 12646 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_4_control_TYPE[15:12] - WO */ 12647 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[11] - WO */ 12648 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[10] - WO */ 12649 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[09] - WO */ 12650 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[08] - RSVD */ 12651 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[07] - WO */ 12652 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[06] - WO */ 12653 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[05] - WO */ 12654 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[04] - WO */ 12655 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[03] - RSVD */ 12656 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[02] - WO */ 12657 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[01] - WO */ 12658 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[00] - WO */ 12659 #endif /* IS_BIG_ENDIAN */ 12660 #if IS_LITTLE_ENDIAN 12661 uint32_t oeb : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[00] - WO */ 12662 uint32_t pup : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[01] - WO */ 12663 uint32_t pdn : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[02] - WO */ 12664 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[03] - RSVD */ 12665 uint32_t ind : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[04] - WO */ 12666 uint32_t sel0 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[05] - WO */ 12667 uint32_t sel1 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[06] - WO */ 12668 uint32_t sel2 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[07] - WO */ 12669 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[08] - RSVD */ 12670 uint32_t ibof : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[09] - WO */ 12671 uint32_t invert_en : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[10] - WO */ 12672 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_gpio_4_control_TYPE[11] - WO */ 12673 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_gpio_4_control_TYPE[15:12] - WO */ 12674 uint32_t reserved : 16; 12675 #endif /* IS_LITTLE_ENDIAN */ 12676 } fields; 12677 } FUR_PAD_CTRL_gpio_4_control_t; 12678 12679 typedef FUR_PAD_CTRL_gpio_4_control_t FUR_PAD_CTRL_GPIO_4_CONTROL_t; 12680 12681 12682 12683 typedef union { 12684 uint32_t data; 12685 struct { 12686 #if IS_BIG_ENDIAN 12687 uint32_t reserved : 16; 12688 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_4_status_TYPE[15:03] - RSVD */ 12689 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_4_status_TYPE[02] - RO */ 12690 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_4_status_TYPE[01] - RO */ 12691 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_4_status_TYPE[00] - RO */ 12692 #endif /* IS_BIG_ENDIAN */ 12693 #if IS_LITTLE_ENDIAN 12694 uint32_t din_lh : 1; /* FUR_PAD_CTRL_gpio_4_status_TYPE[00] - RO */ 12695 uint32_t din_ll : 1; /* FUR_PAD_CTRL_gpio_4_status_TYPE[01] - RO */ 12696 uint32_t din : 1; /* FUR_PAD_CTRL_gpio_4_status_TYPE[02] - RO */ 12697 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_gpio_4_status_TYPE[15:03] - RSVD */ 12698 uint32_t reserved : 16; 12699 #endif /* IS_LITTLE_ENDIAN */ 12700 } fields; 12701 } FUR_PAD_CTRL_gpio_4_status_t; 12702 12703 typedef FUR_PAD_CTRL_gpio_4_status_t FUR_PAD_CTRL_GPIO_4_STATUS_t; 12704 12705 12706 typedef union { 12707 uint32_t data; 12708 struct { 12709 #if IS_BIG_ENDIAN 12710 uint32_t reserved : 16; 12711 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_testpad_control_TYPE[15:12] - WO */ 12712 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[11] - WO */ 12713 uint32_t invert_en : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[10] - WO */ 12714 uint32_t ibof : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[09] - WO */ 12715 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[08] - RSVD */ 12716 uint32_t sel2 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[07] - WO */ 12717 uint32_t sel1 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[06] - WO */ 12718 uint32_t sel0 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[05] - WO */ 12719 uint32_t ind : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[04] - WO */ 12720 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[03] - RSVD */ 12721 uint32_t pdn : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[02] - WO */ 12722 uint32_t pup : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[01] - WO */ 12723 uint32_t oeb : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[00] - WO */ 12724 #endif /* IS_BIG_ENDIAN */ 12725 #if IS_LITTLE_ENDIAN 12726 uint32_t oeb : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[00] - WO */ 12727 uint32_t pup : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[01] - WO */ 12728 uint32_t pdn : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[02] - WO */ 12729 uint32_t reserved_03 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[03] - RSVD */ 12730 uint32_t ind : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[04] - WO */ 12731 uint32_t sel0 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[05] - WO */ 12732 uint32_t sel1 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[06] - WO */ 12733 uint32_t sel2 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[07] - WO */ 12734 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[08] - RSVD */ 12735 uint32_t ibof : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[09] - WO */ 12736 uint32_t invert_en : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[10] - WO */ 12737 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_testpad_control_TYPE[11] - WO */ 12738 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_testpad_control_TYPE[15:12] - WO */ 12739 uint32_t reserved : 16; 12740 #endif /* IS_LITTLE_ENDIAN */ 12741 } fields; 12742 } FUR_PAD_CTRL_testpad_control_t; 12743 12744 typedef FUR_PAD_CTRL_testpad_control_t FUR_PAD_CTRL_TESTPAD_CONTROL_t; 12745 12746 typedef union { 12747 uint32_t data; 12748 struct { 12749 #if IS_BIG_ENDIAN 12750 uint32_t reserved : 16; 12751 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_testpad_status_TYPE[15:03] - RSVD */ 12752 uint32_t din : 1; /* FUR_PAD_CTRL_testpad_status_TYPE[02] - RO */ 12753 uint32_t din_ll : 1; /* FUR_PAD_CTRL_testpad_status_TYPE[01] - RO */ 12754 uint32_t din_lh : 1; /* FUR_PAD_CTRL_testpad_status_TYPE[00] - RO */ 12755 #endif /* IS_BIG_ENDIAN */ 12756 #if IS_LITTLE_ENDIAN 12757 uint32_t din_lh : 1; /* FUR_PAD_CTRL_testpad_status_TYPE[00] - RO */ 12758 uint32_t din_ll : 1; /* FUR_PAD_CTRL_testpad_status_TYPE[01] - RO */ 12759 uint32_t din : 1; /* FUR_PAD_CTRL_testpad_status_TYPE[02] - RO */ 12760 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_testpad_status_TYPE[15:03] - RSVD */ 12761 uint32_t reserved : 16; 12762 #endif /* IS_LITTLE_ENDIAN */ 12763 } fields; 12764 } FUR_PAD_CTRL_testpad_status_t; 12765 12766 typedef FUR_PAD_CTRL_testpad_status_t FUR_PAD_CTRL_TESTPAD_STATUS_t; 12767 12768 typedef union { 12769 uint32_t data; 12770 struct { 12771 #if IS_BIG_ENDIAN 12772 uint32_t reserved : 16; 12773 uint32_t reserved_09 : 7; /* FUR_MISC_CTRL_general_status_IO_TYPE[15:09] - RSVD */ 12774 uint32_t rosc_testpad_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[08] - WO */ 12775 uint32_t srx_los_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[07] - WO */ 12776 uint32_t lrx_los_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[06] - WO */ 12777 uint32_t sys_lol_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[05] - WO */ 12778 uint32_t line_lol_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[04] - WO */ 12779 uint32_t srx_fifoerrb_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[03] - WO */ 12780 uint32_t lrx_fifoerrb_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[02] - WO */ 12781 uint32_t mod_lowpwr_in_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[01] - WO */ 12782 uint32_t tx_disable_in_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[00] - WO */ 12783 #endif /* IS_BIG_ENDIAN */ 12784 #if IS_LITTLE_ENDIAN 12785 uint32_t tx_disable_in_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[00] - WO */ 12786 uint32_t mod_lowpwr_in_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[01] - WO */ 12787 uint32_t lrx_fifoerrb_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[02] - WO */ 12788 uint32_t srx_fifoerrb_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[03] - WO */ 12789 uint32_t line_lol_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[04] - WO */ 12790 uint32_t sys_lol_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[05] - WO */ 12791 uint32_t lrx_los_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[06] - WO */ 12792 uint32_t srx_los_gpio_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[07] - WO */ 12793 uint32_t rosc_testpad_en : 1; /* FUR_MISC_CTRL_general_status_IO_TYPE[08] - WO */ 12794 uint32_t reserved_09 : 7; /* FUR_MISC_CTRL_general_status_IO_TYPE[15:09] - RSVD */ 12795 uint32_t reserved : 16; 12796 #endif /* IS_LITTLE_ENDIAN */ 12797 } fields; 12798 } FUR_MISC_CTRL_general_status_IO_t; 12799 12800 typedef FUR_MISC_CTRL_general_status_IO_t FUR_MISC_CTRL_GENERAL_STATUS_IO_t; 12801 12802 typedef union { 12803 uint32_t data; 12804 struct { 12805 #if IS_BIG_ENDIAN 12806 uint32_t reserved : 16; 12807 uint32_t reserved_15 : 1; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[15] - RSVD */ 12808 uint32_t dataram_tm : 7; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[14:08] - WO */ 12809 uint32_t reserved_02 : 6; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[07:02] - RSVD */ 12810 uint32_t use_internal_xfer_done : 1; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[01] - WO */ 12811 uint32_t qsfp_mode : 1; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[00] - WO */ 12812 #endif /* IS_BIG_ENDIAN */ 12813 #if IS_LITTLE_ENDIAN 12814 uint32_t qsfp_mode : 1; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[00] - WO */ 12815 uint32_t use_internal_xfer_done : 1; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[01] - WO */ 12816 uint32_t reserved_02 : 6; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[07:02] - RSVD */ 12817 uint32_t dataram_tm : 7; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[14:08] - WO */ 12818 uint32_t reserved_15 : 1; /* FUR_MISC_CTRL_DEBUG_CTRL_TYPE[15] - RSVD */ 12819 uint32_t reserved : 16; 12820 #endif /* IS_LITTLE_ENDIAN */ 12821 } fields; 12822 } FUR_MISC_CTRL_DEBUG_CTRL_t; 12823 12824 typedef union { 12825 uint32_t data; 12826 struct { 12827 #if IS_BIG_ENDIAN 12828 uint32_t reserved : 16; 12829 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[15:12] - WO */ 12830 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[11] - WO */ 12831 uint32_t invert_en : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[10] - WO */ 12832 uint32_t ibof : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[09] - WO */ 12833 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[08] - RSVD */ 12834 uint32_t sel2 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[07] - WO */ 12835 uint32_t sel1 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[06] - WO */ 12836 uint32_t sel0 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[05] - WO */ 12837 uint32_t reserved_00 : 5; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[04:00] - RSVD */ 12838 #endif /* IS_BIG_ENDIAN */ 12839 #if IS_LITTLE_ENDIAN 12840 uint32_t reserved_00 : 5; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[04:00] - RSVD */ 12841 uint32_t sel0 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[05] - WO */ 12842 uint32_t sel1 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[06] - WO */ 12843 uint32_t sel2 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[07] - WO */ 12844 uint32_t reserved_08 : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[08] - RSVD */ 12845 uint32_t ibof : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[09] - WO */ 12846 uint32_t invert_en : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[10] - WO */ 12847 uint32_t out_frcval : 1; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[11] - WO */ 12848 uint32_t dglh_cnt : 4; /* FUR_PAD_CTRL_ext_intrb_control_TYPE[15:12] - WO */ 12849 uint32_t reserved : 16; 12850 #endif /* IS_LITTLE_ENDIAN */ 12851 } fields; 12852 } FUR_PAD_CTRL_ext_intrb_control_t; 12853 12854 12855 typedef FUR_PAD_CTRL_ext_intrb_control_t FUR_PAD_CTRL_EXT_INTRB_CONTROL_t; 12856 typedef union { 12857 uint32_t data; 12858 struct { 12859 #if IS_BIG_ENDIAN 12860 uint32_t reserved : 16; 12861 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[15:03] - RSVD */ 12862 uint32_t din : 1; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[02] - RO */ 12863 uint32_t din_ll : 1; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[01] - RO */ 12864 uint32_t din_lh : 1; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[00] - RO */ 12865 #endif /* IS_BIG_ENDIAN */ 12866 #if IS_LITTLE_ENDIAN 12867 uint32_t din_lh : 1; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[00] - RO */ 12868 uint32_t din_ll : 1; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[01] - RO */ 12869 uint32_t din : 1; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[02] - RO */ 12870 uint32_t reserved_03 : 13; /* FUR_PAD_CTRL_ext_intrb_status_TYPE[15:03] - RSVD */ 12871 uint32_t reserved : 16; 12872 #endif /* IS_LITTLE_ENDIAN */ 12873 } fields; 12874 } FUR_PAD_CTRL_ext_intrb_status_t; 12875 12876 typedef union { 12877 uint32_t data; 12878 struct { 12879 #if IS_BIG_ENDIAN 12880 uint32_t reserved : 16; 12881 uint32_t reserved_05 : 11; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[15:05] - RSVD */ 12882 uint32_t gallardoa0_dis : 1; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[04] - WO */ 12883 uint32_t reserved_01 : 3; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[03:01] - RSVD */ 12884 uint32_t ext_pcs_link_en : 1; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[00] - WO */ 12885 #endif /* IS_BIG_ENDIAN */ 12886 #if IS_LITTLE_ENDIAN 12887 uint32_t ext_pcs_link_en : 1; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[00] - WO */ 12888 uint32_t reserved_01 : 3; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[03:01] - RSVD */ 12889 uint32_t gallardoa0_dis : 1; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[04] - WO */ 12890 uint32_t reserved_05 : 11; /* FUR_MISC_CTRL_furia_qsfi_misc_TYPE[15:05] - RSVD */ 12891 uint32_t reserved : 16; 12892 #endif /* IS_LITTLE_ENDIAN */ 12893 } fields; 12894 } FUR_MISC_CTRL_furia_qsfi_misc_t; 12895 12896 typedef FUR_MISC_CTRL_furia_qsfi_misc_t FUR_MISC_CTRL_FURIA_QSFI_MISC_t; 12897 12898 #endif /* chip_reg_structs__H */