furia_reg_access.h (6729B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 #ifndef __FURIA_REG_ACCESS_H__ 10 #define __FURIA_REG_ACCESS_H__ 11 12 #include <phymod/phymod.h> 13 14 /** Read Register 15 * This function is used to read the register content of given 16 * register address 17 * 18 * @param pa Pointer to phymod access structure 19 * @param addr Register address supplied by user 20 * @param data Regiser content/value of the given register 21 * 22 * @return ioerr Error return 23 * 0 - Success 24 * any other value - Error 25 */ 26 int furia_reg_read(const phymod_access_t *pa, uint32_t addr, uint32_t *data); 27 28 /** Write Register 29 * This function is used to write the content to given register 30 * 31 * @param pa Pointer to phymod access structure 32 * @param addr Register address supplied by user 33 * @param data Regiser content/value to be written to register 34 * 35 * @return ioerr Error return 36 * 0 - Success 37 * any other value - Error 38 */ 39 int furia_reg_write(const phymod_access_t *pa, uint32_t addr, uint32_t data); 40 41 /** Modify Register 42 * This function is used to modify the content without overwriting it 43 * 44 * @param pa Pointer to phymod access structure 45 * @param addr Register address supplied by user 46 * @param reg_data Regiser data for modified portion 47 * @param reg_mask Register mask for the data bits to be modified 48 * 49 * @return ioerr Error return 50 * 0 - Success 51 * any other value - Error 52 */ 53 int furia_reg_modify(const phymod_access_t *pa, 54 uint32_t addr, 55 uint16_t reg_data, 56 uint16_t reg_mask); 57 /** Set slice register 58 * This function is used to set the slice register for indirect 59 * accessing of register 60 * 61 * @param pa Pointer to phymod access structure 62 * @param intf_side Interface side 63 * 0 - Line side 1 - System side 64 * @param wr_lane Write lane information 65 * 0xF - broadcast 66 * 0x3 - multicast01 67 * 0xC - multicast23 68 * 0x8 - ln3 69 * 0x4 - ln2 70 * 0x2 - ln1 71 * 0x1 - ln0 72 * @param rd_lane Read lane information 73 * 0x0 = ReadLane_0 74 * 0x1 = ReadLane_1 75 * 0x2 = ReadLane_2 76 * 0x3 = ReadLane_3 77 * 78 * @return ioerr Error return 79 * 0 - Success 80 * any other value - Error 81 */ 82 83 int furia_set_slice_reg(const phymod_access_t *pa, 84 uint16_t intf_side, 85 uint16_t wr_lane, 86 uint16_t rd_lane); 87 /** Set slice register 88 * This function is used to set the an slice register for indirect 89 * accessing of register 90 * 91 * @param pa Pointer to phymod access structure 92 * @param intf_side Interface side 93 * 0 - Line side 1 - System side 94 * @param wr_lane Write lane information 95 * 0xF - broadcast 96 * 0x3 - multicast01 97 * 0xC - multicast23 98 * 0x8 - ln3 99 * 0x4 - ln2 100 * 0x2 - ln1 101 * 0x1 - ln0 102 * @param rd_lane Read lane information 103 * 0x0 = ReadLane_0 104 * 0x1 = ReadLane_1 105 * 0x2 = ReadLane_2 106 * 0x3 = ReadLane_3 107 * 108 * @return ioerr Error return 109 * 0 - Success 110 * any other value - Error 111 */ 112 113 int furia_set_an_slice_reg(const phymod_access_t *pa, 114 uint16_t intf_side, 115 uint16_t wr_lane, 116 uint16_t rd_lane); 117 118 #define PHY_FURIA_C45_DEV_PMA_PMD 0x01 119 #define PHY_FURIA_C45_DEV_PCS 0x03 120 #define PHY_FURIA_C45_DEV_AN 0x07 121 122 123 #define FURIA_CLAUSE45_ADDR(_devad, _regad) \ 124 ((((_devad) & 0x3F) << 16) | \ 125 ((_regad) & 0xFFFF)) 126 127 128 /* WRITE To FURITA Slice Register */ 129 130 #define WRITE_FURIA_SLICE_REG(_pa, _intf, _wrlane, _rdlane) \ 131 furia_set_slice_reg(_pa, _intf, _wrlane, _rdlane) 132 #define WRITE_FURIA_AN_SLICE_REG(_pa, _intf, _wrlane, _rdlane) \ 133 furia_set_an_slice_reg(_pa, _intf, _wrlane, _rdlane) 134 135 136 /* PMA/PMD Device (Dev Addr 1) */ 137 #define READ_FURIA_PMA_PMD_REG(_pa, _reg, _val) \ 138 furia_reg_read(_pa,\ 139 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_PMA_PMD, (_reg)), _val) 140 #define WRITE_FURIA_PMA_PMD_REG(_pa, _reg,_val) \ 141 furia_reg_write(_pa,\ 142 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_PMA_PMD, (_reg)), _val) 143 #define MODIFY_FURIA_PMA_PMD_REG(_pa, _reg, _val, _mask) \ 144 furia_reg_modify((_pa),\ 145 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_PMA_PMD, (_reg)),\ 146 (_val),\ 147 (_mask)) 148 /* PCS Device (Dev Addr 3) */ 149 #define READ_FURIA_PCS_REG(_pa, _reg,_val) \ 150 furia_reg_read(_pa, \ 151 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_PCS, (_reg)), _val) 152 #define WRITE_FURIA_PCS_REG(_pa, _reg,_val) \ 153 furia_reg_write(_pa,\ 154 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_PCS, (_reg)), _val) 155 #define MODIFY_FURIA_PCS_REG(_pa, _reg, _val, _mask) \ 156 furia_reg_modify((_pa),\ 157 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_PCS, (_reg)),\ 158 (_val),\ 159 (_mask)) 160 161 /* AN Device (Dev Addr 7) */ 162 #define READ_FURIA_AN_REG(_pa, _reg,_val) \ 163 furia_reg_read(_pa, \ 164 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_AN, (_reg)), _val) 165 #define WRITE_FURIA_AN_REG(_pa, _reg,_val) \ 166 furia_reg_write(_pa,\ 167 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_AN, (_reg)), _val) 168 #define MODIFY_FURIA_AN_REG(_pa, _reg, _val, _mask) \ 169 furia_reg_modify((_pa),\ 170 FURIA_CLAUSE45_ADDR(PHY_FURIA_C45_DEV_AN, (_reg)),\ 171 (_val),\ 172 (_mask)) 173 174 #endif /*__FURIA_REG_ACCESS_H__*/