furia_cfg_seq.h (24653B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 #ifndef __FURIA_CFG_SEQ_H__ 10 #define __FURIA_CFG_SEQ_H__ 11 12 /* 13 * Includes 14 */ 15 #include "furia_pkg_cfg.h" 16 #include "furia_types.h" 17 18 #include "furia_micro_seq.h" 19 #include "furia_regs_structs.h" 20 #include "common/srds_api_enum.h" 21 #include <phymod/phymod.h> 22 #include <phymod/phymod_diagnostics.h> 23 /* 24 * Functions for Furia 25 */ 26 27 /* 28 * Defines 29 */ 30 31 /* 32 * Types 33 */ 34 35 /* 36 * Macros 37 */ 38 #define GET_ARRAY_SIZE(array) (sizeof(array)/sizeof(array[0])) 39 #define FURIA_IS_SIMPLEX(devid)\ 40 ((devid) == FURIA_ID_82208 ||\ 41 (devid) == FURIA_ID_82209 ||\ 42 (devid) == FURIA_ID_82212 ||\ 43 (devid) == FURIA_ID_82216 \ 44 ) 45 46 #define FURIA_IS_DUPLEX(devid)\ 47 ((devid) == FURIA_ID_82071 ||\ 48 (devid) == FURIA_ID_82070 ||\ 49 (devid) == FURIA_ID_82073 ||\ 50 (devid) == FURIA_ID_82072 ||\ 51 (devid) == FURIA_ID_82380 ||\ 52 (devid) == FURIA_ID_82381 ||\ 53 (devid) == FURIA_ID_82383 ||\ 54 (devid) == FURIA_ID_82385 ||\ 55 (devid) == FURIA_ID_82314 ||\ 56 (devid) == FURIA_ID_82315 \ 57 ) 58 59 60 #define FURIA_IS_DUAL_DIE_DUPLEX(devid)\ 61 ((devid) == FURIA_ID_82073 ||\ 62 (devid) == FURIA_ID_82072 ||\ 63 (devid) == FURIA_ID_82381 ||\ 64 (devid) == FURIA_ID_82383 ||\ 65 (devid) == FURIA_ID_82385 \ 66 ) 67 #define FURIA_GET_IF_SIDE(_FLAGS, _SIDE) \ 68 { \ 69 if(((_FLAGS >> PHYMOD_INTERFACE_SIDE_SHIFT) & 0x1) == 0x1) { \ 70 _SIDE = SIDE_B; \ 71 } else { \ 72 _SIDE = SIDE_A; \ 73 } \ 74 } 75 76 #define FURIA_IF_BCAST_SET(chip_id, lane_map) \ 77 ( ((FURIA_IS_DUPLEX(chip_id)) && (lane_map == 0xF)) \ 78 ) 79 80 81 #define FURIA_IF_TX_SIDE(chip_id, pkg_side) \ 82 ( ((FURIA_IS_SIMPLEX(chip_id)) && (pkg_side == SIDE_A)) || \ 83 (FURIA_IS_DUPLEX(chip_id)) \ 84 ) 85 86 87 #define FURIA_IF_RX_SIDE(chip_id, pkg_side) \ 88 ( (FURIA_IS_SIMPLEX(chip_id) && (pkg_side == SIDE_B)) || \ 89 (FURIA_IS_DUPLEX(chip_id)) \ 90 ) 91 92 #define FURIA_MAX_INTRS_SUPPORT 8 93 94 #define FURIA_PHYTYPE_BP 0 95 #define FURIA_PHYTYPE_FP 1 96 #define FURIA_PHYTYPE_OTN 2 97 #define FURIA_PHYTYPE_FC 3 98 #define FURIA_PHYTYPE_PROP 4 99 100 #define FURIA_LINKTYPE_1 1 101 #define FURIA_LINKTYPE_2 2 102 #define FURIA_LINKTYPE_3 3 103 #define FURIA_LINKTYPE_4 4 104 #define FURIA_LINKTYPE_5 5 105 #define FURIA_LINKTYPE_6 6 106 #define FURIA_LINKTYPE_7 7 107 #define FURIA_LINKTYPE_8 8 108 #define FURIA_LINKTYPE_9 9 109 #define FURIA_LINKTYPE_C 12 110 #define FURIA_LINKTYPE_D 13 111 #define FURIA_LINKTYPE_E 14 112 #define FURIA_LINKTYPE_F 15 113 #define FURIA_IF_LR_LR4 0 114 #define FURIA_IF_SR_SR4 1 115 #define FURIA_IF_ER_ER4 2 116 #define FURIA_IF_KR_KR4 3 117 #define FURIA_IF_CR4 3 118 #define FURIA_IF_CR2 2 119 #define FURIA_IF_CX 1 120 #define FURIA_IF_CR 2 121 #define FURIA_IF_SFI 3 122 #define FURIA_IF_CAUI 0 123 #define FURIA_IF_CC 1 124 #define FURIA_IF_CM 2 125 #define FURIA_IF_CAUI4 3 126 #define FURIA_IF_XFI 1 127 #define FURIA_IF_XLAUI 2 128 #define FURIA_IF_1E 0 129 #define FURIA_IF_2E 1 130 #define FURIA_IF_3E1 0 131 #define FURIA_IF_3E2 1 132 #define FURIA_CLK_106 0 133 #define FURIA_CLK_156 1 134 #define FURIA_CLK_157 2 135 #define FURIA_CLK_158 3 136 #define FURIA_CLK_161 4 137 #define FURIA_CLK_168 5 138 #define FURIA_CLK_174 6 139 #define FURIA_CLK_125 7 140 #define FURIA_CLK_159 8 141 #define FURIA_IF_HIGIG 1 142 143 #define FURIA_REG_SET(reg,lane,val) \ 144 if (lane == 0) { reg##0=val; } \ 145 else if (lane == 1) { reg##1=val;} \ 146 else if (lane == 2) { reg##2=val;} \ 147 else if (lane == 3) { reg##3=val;} \ 148 else if (lane == 4) { reg##4=val;} \ 149 else if (lane == 5) { reg##5=val;} \ 150 else if (lane == 6) { reg##6=val;} \ 151 else if (lane == 7) { reg##7=val;} 152 153 #define FURIA_REG_GET(reg,lane,val) \ 154 if (lane == 0) { val = reg##0; } \ 155 else if (lane == 1) { val = reg##1;} \ 156 else if (lane == 2) { val = reg##2;} \ 157 else if (lane == 3) { val = reg##3;} \ 158 else if (lane == 4) { val = reg##4;} \ 159 else if (lane == 5) { val = reg##5;} \ 160 else if (lane == 6) { val = reg##6;} \ 161 else if (lane == 7) { val = reg##7;} 162 163 #define FURIA_GET_NUM_LANES(cid, nl) \ 164 if (FURIA_IS_SIMPLEX(cid)) { \ 165 if (cid == FURIA_ID_82212) { \ 166 nl=12;} \ 167 else { \ 168 nl=8; } \ 169 } else { \ 170 nl = 4;} 171 172 #define FURIA_GET_LANE_MASK(cid, lm) \ 173 if (FURIA_IS_SIMPLEX(cid)) { \ 174 if (cid == FURIA_ID_82212) { \ 175 lm=0xFFF;} \ 176 else { \ 177 lm=0xFF; } \ 178 } else { \ 179 lm= 0xF;} 180 /* 181 * Global Variables 182 */ 183 184 /* 185 * Functions 186 */ 187 188 /* 189 * Functions for Manipulating Chip/Port Cfg Descriptors 190 */ 191 192 /* 193 * Functions 194 */ 195 196 /* 197 * Functions for Manipulating Chip/Port Cfg Descriptors 198 */ 199 200 /** Get Revision ID 201 * This function retrieves Revision ID from PHY chip 202 * 203 * @param pa Pointer to phymod access structure 204 * 205 * @return rev_id Revision ID retrieved from the chip 206 */ 207 uint16_t _furia_get_rev_id(const phymod_access_t *pa); 208 209 /** Get Chip ID 210 * This function retrieves Chip ID from PHY chip 211 * 212 * @param pa Pointer to phymod access structure 213 * 214 * @return chip_id Chip id retrieved from the chip 215 */ 216 uint32_t _furia_get_chip_id(const phymod_access_t *pa); 217 218 /** Reset Chip 219 * This function is used to reset entire chip 220 * 221 * @param pa Pointer to phymod access structure 222 * 223 * @return PHYMOD_E_NONE successful function execution 224 */ 225 int _furia_chip_reset(const phymod_access_t *pa); 226 227 /** Reset Register 228 * This function is used to perform register reset 229 * 230 * @param pa Pointer to phymod access structure 231 * 232 * @return PHYMOD_E_NONE successful function execution 233 */ 234 int _furia_register_rst(const phymod_access_t *pa); 235 236 237 /** Configure PRBS generator 238 * This function is used to configure PRBS generator with user provided 239 * polynomial and invert data information 240 * 241 * @param pa Pointer to phymod access structure 242 * @param flags Flags to prbs config 243 * @param prbs_mode User specified polynomial 244 * 0 - PRBS7 245 * 1 - PRBS9 246 * 2 - PRBS11 247 * 3 - PRBS15 248 * 4 - PRBS23 249 * 5 - PRBS31 250 * 6 - PRBS58 251 * 252 * @param prbs_inv User specified invert data config 253 * 0 - do not invert PRBS data 254 * 1 - invert PRBS data 255 * 256 * @return PHYMOD_E_NONE successful function execution 257 */ 258 int furia_prbs_config_set(const phymod_access_t *pa, 259 uint32_t flags, 260 enum srds_prbs_polynomial_enum prbs_mode, 261 uint32_t prbs_inv); 262 263 264 /** Enable PRBS generator and PRBS checker 265 * This function is used to enable or disable PRBS generator and PRBS checker 266 * as requested by the user 267 * 268 * @param pa Pointer to phymod access structure 269 * @param flags Flags to prbs config 270 * @param enable Enable or disable as specified by the user 271 * 1 - Enable 272 * 0 - Disable 273 * 274 * @return PHYMOD_E_NONE successful function execution 275 */ 276 int furia_prbs_enable_set(const phymod_access_t *pa, uint32_t flags, uint32_t enable); 277 278 /** Get Enable status of PRBS generator and PRBS checker 279 * This function is used to retrieve the enable status of PRBS generator and 280 * PRBS checker 281 * 282 * @param pa Pointer to phymod access structure 283 * @param flags Flags to prbs config 284 * @param *enable Enable or disable read from chip 285 * 1 - Enable 286 * 0 - Disable 287 * 288 * @return PHYMOD_E_NONE successful function execution 289 */ 290 int furia_prbs_enable_get(const phymod_access_t *pa, uint32_t flags, uint32_t *enable); 291 292 /** Get PRBS checker configuration 293 * This function is used to retrieve PRBS checker configuration from 294 * the chip 295 * 296 * @param pa Pointer to phymod access structure 297 * @param flags Flags to prbs config 298 * @param prbs_mode Configured Polynomial retrieved from chip 299 * @param prbs_inv Configured invert data retrieved from chip 300 * 0 - do not invert PRBS data 301 * 1 - invert PRBS data 302 * 303 * @return PHYMOD_E_NONE successful function execution 304 */ 305 int furia_prbs_config_get(const phymod_access_t *pa, 306 uint32_t flags, 307 enum srds_prbs_polynomial_enum *prbs_mode, 308 uint32_t *prbs_inv); 309 310 311 /** Get PRBS lock and error status 312 * This function is used to retrieve PRBS lock, loss of lock and error counts 313 * from the chip 314 * 315 * @param pa Pointer to phymod access structure 316 * @param lock_status PRBS lock status denotes PRBS generator and 317 * checker are locked to same polynomial data 318 * @param lock_loss Loss of lock denotes PRBS generator and checker 319 * are not in sync 320 * @param error_count PRBS error count retrieved from chip 321 * 322 * @return PHYMOD_E_NONE successful function execution 323 */ 324 int furia_prbs_status_get(const phymod_access_t *pa, 325 uint32_t *lock_status, 326 uint32_t *lock_loss, 327 uint32_t *error_count); 328 329 /** Get lane descriptor 330 * This function is used to retrieve lane descriptor from package lane 331 * 332 * @param chip_id chip id number 333 * @param pa Pointer to phymod access structure 334 * @param pkg_lane Package lane number 335 * 336 * @return pkg_ln_des Lane descriptor structure contains the info 337 * about package lane and die lane mapping 338 */ 339 const struct _FURIA_PKG_LANE_CFG_S* _furia_pkg_ln_des(uint32_t chip_id, const phymod_access_t *pa, int pkg_lane); 340 341 /** Get lane descriptor 342 * This function is used to retrieve lane descriptor from package lane 343 * 344 * @param chip_id chip id number 345 * @param pa Pointer to phymod access structure 346 * @param pkg_lane Package lane number 347 * @param tx_rx Tx or Rx 348 * 349 * @return pkg_ln_des Lane descriptor structure contains the info 350 * about package lane and die lane mapping 351 */ 352 const struct _FURIA_PKG_LANE_CFG_S* _furia_pkg_ln_des_lane_swap(uint32_t chip_id, const phymod_access_t *pa, int pkg_lane, int tx_rx); 353 354 /** Get link status of PHY 355 * This function is used to retrieve the link status of PHY chip 356 * 357 * @param pa Pointer to phymod access structure 358 * 359 * @param link_status link status of the PHY 360 * 1 - Up 361 * 0 - Down 362 * 363 * @return PHYMOD_E_NONE successful function execution 364 */ 365 int furia_chk_phy_link_mode_status(const phymod_access_t *pa, 366 uint32_t *link_status); 367 368 /** Set config mode 369 * This function is used to set the operating mode of the PHY 370 * 371 * @param pa Pointer to phymod access structure 372 * @param config Pointer to phy interface config structure 373 * 374 * @return PHYMOD_E_NONE successful function execution 375 */ 376 int furia_set_config_mode(const phymod_access_t *pa, 377 const phymod_phy_inf_config_t* config); 378 379 380 /** Get config mode 381 * This function is used to retrieve the operating mode of the PHY 382 * 383 * @param pa Pointer to phymod access structure 384 * @param intf Interface type 385 * @param speed Speed val retrieved from PHY 386 * @param ref_clk Reference clock frequency to set 387 * the PHY into specified interface 388 * and speed 389 * @param interface_modes mode which is currently unused 390 * @param config used to return the OTN type i.e OTN4.4, OTN3.4 etc 391 * @param saved_lane_map Lane map provided by user 392 * 393 * @return PHYMOD_E_NONE successful function execution 394 */ 395 int furia_get_config_mode(const phymod_access_t *pa, 396 phymod_interface_t *intf, 397 uint32_t *speed, 398 phymod_ref_clk_t *ref_clk, 399 uint32_t *interface_modes, phymod_phy_inf_config_t* config, uint16_t saved_lane_map); 400 401 /** Get phymod interface type from pma type 402 * This function is used to retrieve PHYMOD interface type from pma_type 403 * 404 * @param pma_type pma type read from mode register 405 * @param intf PHYMOD interface type 406 * @param speed Speed val 407 * 408 * @return PHYMOD_E_NONE successful function execution 409 */ 410 int _furia_get_phymod_interface_type(uint16_t pma_type, 411 phymod_interface_t *intf, 412 uint32_t *speed); 413 414 /** Get pma type from interface and speed 415 * This function is used to get the pma type from interface and speed. 416 * This pma type will be programmed to mode register for different PHY modes 417 * 418 * @param intf PHYMOD interface type 419 * @param speed Speed val 420 * 421 * @return pma_typeselection pma type calculated with interface and speed 422 */ 423 uint16_t _furia_get_pma_type_selection(phymod_interface_t intf, uint32_t speed); 424 425 426 int furia_tx_rx_polarity_set (const phymod_access_t *pa, 427 uint32_t tx_polarity, 428 uint32_t rx_polarity); 429 430 431 int furia_tx_rx_polarity_get (const phymod_access_t *pa, 432 uint32_t *tx_polarity, 433 uint32_t *rx_polarity); 434 int furia_tx_squelch(const phymod_access_t *pa, 435 uint32_t enable); 436 int furia_tx_disable(const phymod_access_t *pa, 437 uint32_t enable); 438 int furia_pmd_lock_get(const phymod_access_t *pa, 439 uint32_t *rx_seq_done); 440 int furia_enable_set(const phymod_access_t *pa, 441 uint32_t enable); 442 int furia_rev_id(const phymod_access_t *pa, 443 uint32_t *rev_id); 444 int furia_rx_power_down(const phymod_access_t *pa, 445 uint32_t enable); 446 int furia_tx_power_down(const phymod_access_t *pa, 447 uint32_t enable); 448 int furia_tx_rx_power_get(const phymod_access_t *pa, 449 uint32_t *power_tx, 450 uint32_t *power_rx); 451 int furia_link_status(const phymod_access_t *pa, 452 uint32_t *link_status); 453 int furia_tx_rx_power_set(const phymod_access_t *pa, 454 uint8_t tx_rx, 455 uint32_t enable); 456 int furia_loopback_set(const phymod_access_t *pa, 457 phymod_loopback_mode_t loopback, 458 uint32_t enable); 459 int furia_loopback_get(const phymod_access_t *pa, 460 phymod_loopback_mode_t loopback, 461 uint32_t* enable); 462 463 int furia_reset_set(const phymod_access_t *pa, 464 phymod_reset_mode_t reset_mode, 465 phymod_reset_direction_t direction); 466 467 int furia_tx_set(const phymod_access_t *pa, 468 const phymod_tx_t* tx); 469 470 int furia_tx_get(const phymod_access_t *pa, 471 phymod_tx_t* tx); 472 int furia_rx_set(const phymod_access_t *pa, 473 const phymod_rx_t* rx); 474 int furia_rx_get(const phymod_access_t *pa, 475 phymod_rx_t* rx); 476 477 int furia_tx_lane_control_set(const phymod_access_t *pa, 478 phymod_phy_tx_lane_control_t tx_control); 479 480 int furia_tx_lane_control_get(const phymod_access_t *pa, 481 phymod_phy_tx_lane_control_t* tx_control); 482 483 int furia_rx_lane_control_set(const phymod_access_t *pa, 484 phymod_phy_rx_lane_control_t rx_control); 485 486 int furia_rx_lane_control_get(const phymod_access_t *pa, 487 phymod_phy_rx_lane_control_t* rx_control); 488 int furia_lane_cross_switch_map_set(const phymod_access_t* phy, 489 const uint32_t* tx_source_array); 490 int furia_lane_cross_switch_map_get(const phymod_access_t *pa, 491 uint32_t* tx_source_array); 492 int furia_force_tx_training_set(const phymod_access_t *pa, 493 uint32_t enable); 494 int furia_force_tx_training_get(const phymod_access_t *pa, 495 uint32_t *enable); 496 int furia_force_tx_training_status_get(const phymod_access_t *pa, phymod_cl72_status_t* status); 497 498 int _furia_phy_reset_set(const phymod_access_t *pa, 499 const phymod_phy_reset_t* reset); 500 int _furia_phy_reset_get(const phymod_access_t *pa, 501 phymod_phy_reset_t* reset); 502 int furia_ber_proj (const phymod_access_t *pa, const phymod_phy_eyescan_options_t* eyescan_options); 503 int furia_rx_adaptation_resume(const phymod_access_t *pa); 504 int furia_slice_reg_set(const phymod_access_t *pa); 505 int furia_slice_reg_unset(const phymod_access_t *pa); 506 #define FURIA_BIT(x) (1<<x) 507 #define SLICE_REG_SET_BIT 31 508 #define FURIA_DEVICE_ID_MASK 0x3F 509 #define FURIA_PMD_DEVICE_ID 1 510 #define FURIA_AN_DEVICE_ID 7 511 512 typedef enum { 513 FURIA_CL73_NO_TECH = 0, 514 FURIA_CL73_1000BASE_KX = 0x1, 515 FURIA_CL73_10GBASE_KX4 = 0x2, 516 FURIA_CL73_10GBASE_KR = 0x4, 517 FURIA_CL73_40GBASE_KR4 = 0x8, 518 FURIA_CL73_40GBASE_CR4 = 0x10, 519 FURIA_CL73_100GBASE_CR10 = 0x20, 520 FURIA_CL73_100GBASE_KP4 = 0x40, 521 FURIA_CL73_100GBASE_KR4 = 0x80, 522 FURIA_CL73_100GBASE_CR4 = 0x100 523 }furia_cl73_speed_t; 524 525 typedef enum { 526 FURIA_NO_PAUSE = 0, 527 FURIA_ASYM_PAUSE, 528 FURIA_SYMM_PAUSE, 529 FURIA_ASYM_SYMM_PAUSE, 530 FURIA_AN_PAUSE_COUNT 531 }furia_an_pause_t; 532 533 typedef struct FURIA_an_adv_ability_s{ 534 furia_cl73_speed_t an_base_speed; 535 furia_an_pause_t an_pause; 536 uint16_t an_fec; 537 uint16_t an_hg2; 538 uint16_t an_cl72; 539 }furia_an_adv_ability_t; 540 541 typedef struct FURIA_an_ability_s { 542 furia_an_adv_ability_t cl73_adv; /*includes cl73 related */ 543 uint32_t an_master_lane; 544 } furia_an_ability_t; 545 546 int _furia_autoneg_set(const phymod_access_t* pa, 547 const phymod_autoneg_control_t* an); 548 int _furia_autoneg_get(const phymod_access_t* pa, 549 phymod_autoneg_control_t* an, 550 uint32_t *an_done); 551 int _furia_autoneg_ability_get (const phymod_access_t* pa, 552 furia_an_ability_t *an_ablity); 553 int _furia_autoneg_ability_set (const phymod_access_t* pa, 554 furia_an_ability_t *an_ablity); 555 int _furia_config_pll_div(const phymod_access_t *pa, uint16_t pll_mode); 556 557 int furia_display_eye_scan(const phymod_access_t *pa); 558 int furia_pll_sequencer_restart(const phymod_access_t *pa, phymod_sequencer_operation_t operation); 559 int furia_fec_enable_set(const phymod_access_t *pa, uint32_t enable); 560 int furia_fec_enable_get(const phymod_access_t *pa, uint32_t* enable); 561 int _furia_phy_status_dump(const phymod_access_t *pa); 562 int _furia_core_diagnostics_get(const phymod_access_t *pa, phymod_core_diagnostics_t* diag); 563 int _furia_phy_diagnostics_get(const phymod_access_t *pa, phymod_phy_diagnostics_t* diag); 564 int furia_pmd_info_dump(const phymod_access_t *pa, char* type); 565 int furia_pcs_info_dump(const phymod_access_t *pa, char* type); 566 int furia_ext_intr_status_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t* intr_status); 567 int furia_ext_intr_enable_set(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t enable); 568 int furia_ext_intr_enable_get(const phymod_phy_access_t *phy, uint32_t intr_type, uint32_t* enable); 569 int furia_ext_intr_status_clear(const phymod_phy_access_t *phy, uint32_t intr_type); 570 int furia_fc_pcs_chkr_enable_set(const phymod_access_t *pa, uint32_t fcpcs_chkr_mode, uint32_t enable); 571 int furia_fc_pcs_chkr_enable_get(const phymod_access_t *pa, uint32_t fcpcs_chkr_mode, uint32_t* enable); 572 int furia_fc_pcs_chkr_status_get(const phymod_access_t *pa, uint32_t* lock_status, uint32_t* lock_lost_lh, uint32_t* error_count); 573 int _furia_core_rptr_rtmr_mode_set(const phymod_access_t* pa, 574 uint32_t rptr_rtmr_mode); 575 int _furia_core_sys_interface_set(const phymod_core_access_t* core, uint32_t sys_side_intf); 576 int _furia_autoneg_remote_ability_get (const phymod_access_t* pa, phymod_autoneg_ability_t* an_ability_get); 577 578 int _furia_core_avddtxdrv_config_set(const phymod_core_access_t* core, uint32_t avdd_txdrv); 579 int furia_gpio_config_set(const phymod_access_t *pa, int pin_no, phymod_gpio_mode_t gpio_mode); 580 int furia_gpio_config_get(const phymod_access_t *pa, int pin_no, phymod_gpio_mode_t* gpio_mode); 581 int furia_gpio_pin_value_set(const phymod_access_t *pa, int pin_no, int value); 582 int furia_gpio_pin_value_get(const phymod_access_t *pa, int pin_no, int* value); 583 int furia_module_write(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, uint32_t no_of_bytes, const uint8_t *write_data); 584 int furia_module_read(const phymod_access_t *pa, uint32_t slv_addr, uint32_t start_addr, uint32_t no_of_bytes, uint8_t *read_data); 585 int _furia_cfg_fw_ull_dp(const phymod_core_access_t* core, uint32_t ull_dp_enable); 586 int _furia_cfg_an_master_lane(const phymod_core_access_t* core, uint32_t 587 an_master_lane); 588 int _furia_pcs_monitor_enable_set(const phymod_core_access_t* core, int enable); 589 int _furia_core_cfg_hcd_link_status_criteria(const phymod_access_t *pa, uint32_t hcd_link_criteria); 590 int _furia_core_cfg_pfifo_4_max_ieee_input_skew(const phymod_access_t* pa, uint32_t tx_ptr_sync, uint32_t rx_ptr_sync); 591 int _furia_core_cfg_polarity_set(const phymod_access_t *pa, uint32_t rx_polarity, uint32_t tx_polarity); 592 int _furia_core_cfg_tx_set(const phymod_access_t *pa,const phymod_tx_t* tx); 593 void _furia_get_phy_id_idx(uint32_t phy_id, uint32_t *idx, uint32_t *exist_phy); 594 int furia_firmware_core_config_set(const phymod_access_t* pa, phymod_firmware_core_config_t fw_config); 595 int furia_firmware_core_config_get(const phymod_access_t* pa, phymod_firmware_core_config_t* fw_config); 596 int furia_firmware_lane_config_set(const phymod_access_t* pa, phymod_firmware_lane_config_t fw_config); 597 int furia_firmware_lane_config_get(const phymod_access_t* pa, phymod_firmware_lane_config_t* fw_config); 598 int _furia_get_pll_for_serdes(phymod_ref_clk_t ref_clk, uint32_t speed, FALCON_PLL_MODE_E pll_mode, uint16_t *serdes_pll_mode); 599 int _furia_phy_short_channel_mode_set(const phymod_access_t *pa, uint32_t enable); 600 int _furia_phy_short_channel_mode_get(const phymod_access_t *pa, uint32_t *enable, uint32_t *status); 601 int furia_single_pmd_enable(const phymod_access_t *pa); 602 #endif