furia_address_defines.h (73913B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 #ifndef chip_address_defines__H 10 #define chip_address_defines__H 11 12 /*-----------------------------------------------*/ 13 /* Defines for IEEE_PMA_PMD_BLK0 Bank */ 14 /*-----------------------------------------------*/ 15 #define IEEE_PMA_PMD_BLK0_BaseAdr (0x0000) 16 #define IEEE_PMA_PMD_BLK0_pmd_control_register_Adr (0x0000) 17 #define IEEE_PMA_PMD_BLK0_status_register_Adr (0x0001) 18 #define IEEE_PMA_PMD_BLK0_pmd_identifier_register_0_Adr (0x0002) 19 #define IEEE_PMA_PMD_BLK0_pmd_identifier_register_1_Adr (0x0003) 20 #define IEEE_PMA_PMD_BLK0_pmd_speed_ability_Adr (0x0004) 21 #define IEEE_PMA_PMD_BLK0_devices_in_package_1_Adr (0x0005) 22 #define IEEE_PMA_PMD_BLK0_devices_in_package_2_Adr (0x0006) 23 #define IEEE_PMA_PMD_BLK0_pmd_control_2_register_Adr (0x0007) 24 #define IEEE_PMA_PMD_BLK0_status_register_2_Adr (0x0008) 25 #define IEEE_PMA_PMD_BLK0_pmd_transmit_disable_register_Adr (0x0009) 26 #define IEEE_PMA_PMD_BLK0_pmd_receive_signal_detect_register_Adr (0x000a) 27 #define IEEE_PMA_PMD_BLK0_pmd_extended_ability_register_Adr (0x000b) 28 #define IEEE_PMA_PMD_BLK0_fortyg_pmd_extended_ability_register_Adr (0x000d) 29 #define IEEE_PMA_PMD_BLK0_pmd_oui_id0_register_Adr (0x000e) 30 #define IEEE_PMA_PMD_BLK0_pmd_oui_id1_reg_Adr (0x000f) 31 32 33 /*-----------------------------------------------*/ 34 /* Defines for FUR_M0ACCESS_ADDR Bank */ 35 /*-----------------------------------------------*/ 36 #define FUR_M0ACCESS_ADDR_BASEADR (0x0000) 37 #define FUR_M0ACCESS_ADDR_MASTER_DRAM_MEM_ADD_ADR (0x8401) 38 #define FUR_M0ACCESS_ADDR_SLAVE_DRAM_MEM_ADD_ADR (0x8403) 39 /*-----------------------------------------------*/ 40 /* Defines for FUR_M0ACCESS_DATA Bank */ 41 /*-----------------------------------------------*/ 42 #define FUR_M0ACCESS_DATA_BASEADR (0x0000) 43 #define FUR_M0ACCESS_DATA_MASTER_DRAM_WDATA_ADR (0x8414) 44 #define FUR_M0ACCESS_DATA_MASTER_DRAM_RDATA_ADR (0x8415) 45 #define FUR_M0ACCESS_DATA_SLAVE_DRAM_WDATA_ADR (0x841a) 46 #define FUR_M0ACCESS_DATA_SLAVE_DRAM_RDATA_ADR (0x841b) 47 48 /*-----------------------------------------------*/ 49 /* Defines for CL93n72_IEEE_TX Bank */ 50 /*-----------------------------------------------*/ 51 #define CL93n72_IEEE_TX_BaseAdr (0x0090) 52 #define CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_control_register_150_Adr (0x0096) 53 #define CL93n72_IEEE_TX_cl93n72it_BASE_R_PMD_status_register_151_Adr (0x0097) 54 #define CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_coeff_update_register_154_Adr (0x009a) 55 #define CL93n72_IEEE_TX_cl93n72it_BASE_R_LD_status_report_register_155_Adr (0x009b) 56 57 /*-----------------------------------------------*/ 58 /* Defines for CL93n72_IEEE_RX Bank */ 59 /*-----------------------------------------------*/ 60 #define CL93n72_IEEE_RX_BaseAdr (0x0090) 61 #define CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_coeff_update_register_152_Adr (0x0098) 62 #define CL93n72_IEEE_RX_cl93n72ir_BASE_R_LP_status_report_register_153_Adr (0x0099) 63 64 /*-----------------------------------------------*/ 65 /* Defines for IEEE_PMA_PMD_BLK10 Bank */ 66 /*-----------------------------------------------*/ 67 #define IEEE_PMA_PMD_BLK10_BaseAdr (0x00a0) 68 #define IEEE_PMA_PMD_BLK10_tengbase_kx_control_register_Adr (0x00a0) 69 #define IEEE_PMA_PMD_BLK10_tengbase_kx_status_register_Adr (0x00a1) 70 71 /*-----------------------------------------------*/ 72 /* Defines for IEEE_CL91_RX Bank */ 73 /*-----------------------------------------------*/ 74 #define IEEE_CL91_RX_BaseAdr (0x0000) 75 #define IEEE_CL91_RX_fec_control_Adr (0x00c8) 76 #define IEEE_CL91_RX_fec_status_Adr (0x00c9) 77 #define IEEE_CL91_RX_fec_corr_cw_cnt_lower_reg_Adr (0x00ca) 78 #define IEEE_CL91_RX_fec_corr_cw_cnt_upper_reg_Adr (0x00cb) 79 #define IEEE_CL91_RX_fec_uncorr_cw_cnt_lower_reg_Adr (0x00cc) 80 #define IEEE_CL91_RX_fec_uncorr_cw_cnt_upper_reg_Adr (0x00cd) 81 #define IEEE_CL91_RX_fec_lane_mapping_Adr (0x00ce) 82 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_3_lower_reg_Adr (0x00d2) 83 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_3_upper_reg_Adr (0x00d3) 84 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_2_lower_reg_Adr (0x00d4) 85 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_2_upper_reg_Adr (0x00d5) 86 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_1_lower_reg_Adr (0x00d6) 87 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_1_upper_reg_Adr (0x00d7) 88 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_0_lower_reg_Adr (0x00d8) 89 #define IEEE_CL91_RX_fec_sym_err_cnt_ln_0_upper_reg_Adr (0x00d9) 90 91 /*-----------------------------------------------*/ 92 /* Defines for IEEE_CL91_TX Bank */ 93 /*-----------------------------------------------*/ 94 #define IEEE_CL91_TX_BaseAdr (0x0000) 95 #define IEEE_CL91_TX_bip_err_cnt_ln_0_reg_Adr (0x00e6) 96 #define IEEE_CL91_TX_bip_err_cnt_ln_1_reg_Adr (0x00e7) 97 #define IEEE_CL91_TX_bip_err_cnt_ln_2_reg_Adr (0x00e8) 98 #define IEEE_CL91_TX_bip_err_cnt_ln_3_reg_Adr (0x00e9) 99 #define IEEE_CL91_TX_bip_err_cnt_ln_4_reg_Adr (0x00ea) 100 #define IEEE_CL91_TX_bip_err_cnt_ln_5_reg_Adr (0x00eb) 101 #define IEEE_CL91_TX_bip_err_cnt_ln_6_reg_Adr (0x00ec) 102 #define IEEE_CL91_TX_bip_err_cnt_ln_7_reg_Adr (0x00ed) 103 #define IEEE_CL91_TX_bip_err_cnt_ln_8_reg_Adr (0x00ee) 104 #define IEEE_CL91_TX_bip_err_cnt_ln_9_reg_Adr (0x00ef) 105 #define IEEE_CL91_TX_bip_err_cnt_ln_10_reg_Adr (0x00f0) 106 #define IEEE_CL91_TX_bip_err_cnt_ln_11_reg_Adr (0x00f1) 107 #define IEEE_CL91_TX_bip_err_cnt_ln_12_reg_Adr (0x00f2) 108 #define IEEE_CL91_TX_bip_err_cnt_ln_13_reg_Adr (0x00f3) 109 #define IEEE_CL91_TX_bip_err_cnt_ln_14_reg_Adr (0x00f4) 110 #define IEEE_CL91_TX_bip_err_cnt_ln_15_reg_Adr (0x00f5) 111 #define IEEE_CL91_TX_bip_err_cnt_ln_16_reg_Adr (0x00f6) 112 #define IEEE_CL91_TX_bip_err_cnt_ln_17_reg_Adr (0x00f7) 113 #define IEEE_CL91_TX_bip_err_cnt_ln_18_reg_Adr (0x00f8) 114 #define IEEE_CL91_TX_bip_err_cnt_ln_19_reg_Adr (0x00f9) 115 #define IEEE_CL91_TX_pcs_ln_0_mapping_reg_Adr (0x00fa) 116 #define IEEE_CL91_TX_pcs_ln_1_mapping_reg_Adr (0x00fb) 117 #define IEEE_CL91_TX_pcs_ln_2_mapping_reg_Adr (0x00fc) 118 #define IEEE_CL91_TX_pcs_ln_3_mapping_reg_Adr (0x00fd) 119 #define IEEE_CL91_TX_pcs_ln_4_mapping_reg_Adr (0x00fe) 120 #define IEEE_CL91_TX_pcs_ln_5_mapping_reg_Adr (0x00ff) 121 #define IEEE_CL91_TX_pcs_ln_6_mapping_reg_Adr (0x0100) 122 #define IEEE_CL91_TX_pcs_ln_7_mapping_reg_Adr (0x0101) 123 #define IEEE_CL91_TX_pcs_ln_8_mapping_reg_Adr (0x0102) 124 #define IEEE_CL91_TX_pcs_ln_9_mapping_reg_Adr (0x0103) 125 #define IEEE_CL91_TX_pcs_ln_10_mapping_reg_Adr (0x0104) 126 #define IEEE_CL91_TX_pcs_ln_11_mapping_reg_Adr (0x0105) 127 #define IEEE_CL91_TX_pcs_ln_12_mapping_reg_Adr (0x0106) 128 #define IEEE_CL91_TX_pcs_ln_13_mapping_reg_Adr (0x0107) 129 #define IEEE_CL91_TX_pcs_ln_14_mapping_reg_Adr (0x0108) 130 #define IEEE_CL91_TX_pcs_ln_15_mapping_reg_Adr (0x0109) 131 #define IEEE_CL91_TX_pcs_ln_16_mapping_reg_Adr (0x010a) 132 #define IEEE_CL91_TX_pcs_ln_17_mapping_reg_Adr (0x010b) 133 #define IEEE_CL91_TX_pcs_ln_18_mapping_reg_Adr (0x010c) 134 #define IEEE_CL91_TX_pcs_ln_19_mapping_reg_Adr (0x010d) 135 #define IEEE_CL91_TX_pcs_align_status1_reg_Adr (0x0118) 136 #define IEEE_CL91_TX_pcs_align_status2_reg_Adr (0x0119) 137 #define IEEE_CL91_TX_pcs_align_status3_reg_Adr (0x011a) 138 #define IEEE_CL91_TX_pcs_align_status4_reg_Adr (0x011b) 139 140 /*-----------------------------------------------*/ 141 /* Defines for DEV1_SLICE Bank */ 142 /*-----------------------------------------------*/ 143 #define DEV1_SLICE_BaseAdr (0x0000) 144 #define DEV1_SLICE_slice_Adr (0x8000) 145 146 /*-----------------------------------------------*/ 147 /* Defines for FUR_MDICS_PMI_ARB_MASK Bank */ 148 /*-----------------------------------------------*/ 149 #define FUR_MDICS_PMI_ARB_MASK_BaseAdr (0x0000) 150 #define FUR_MDICS_PMI_ARB_MASK_mdics_pmi_arb_mask_Adr (0x8020) 151 152 /*-----------------------------------------------*/ 153 /* Defines for FUR_GEN_CNTRLS Bank */ 154 /*-----------------------------------------------*/ 155 #define FUR_GEN_CNTRLS_BaseAdr (0x0000) 156 #define FUR_GEN_CNTRLS_gen_control1_Adr (0x8200) 157 #define FUR_GEN_CNTRLS_gen_control2_Adr (0x8201) 158 #define FUR_GEN_CNTRLS_gen_control3_Adr (0x8202) 159 #define FUR_GEN_CNTRLS_gen_control4_Adr (0x8203) 160 #define FUR_GEN_CNTRLS_spi_mst_code_start_ptr_Adr (0x8210) 161 #define FUR_GEN_CNTRLS_spi_slv_code_start_ptr_Adr (0x8211) 162 #define FUR_GEN_CNTRLS_spi_code_load_en_Adr (0x8212) 163 #define FUR_GEN_CNTRLS_spi_eeprom_control_Adr (0x8213) 164 #define FUR_GEN_CNTRLS_mscr_Adr (0x8214) 165 #define FUR_GEN_CNTRLS_msgout_Adr (0x8215) 166 #define FUR_GEN_CNTRLS_msgin_Adr (0x8216) 167 #define FUR_GEN_CNTRLS_boot_Adr (0x8217) 168 #define FUR_GEN_CNTRLS_slv_msgout_Adr (0x8218) 169 #define FUR_GEN_CNTRLS_slv_msgin_Adr (0x8219) 170 #define FUR_GEN_CNTRLS_mst_misc_intr_Adr (0x821b) 171 #define FUR_GEN_CNTRLS_slv_misc_intr_Adr (0x821c) 172 #define FUR_GEN_CNTRLS_gpreg10_Adr (0x822a) 173 #define FUR_GEN_CNTRLS_gpreg11_Adr (0x822b) 174 #define FUR_GEN_CNTRLS_gpreg12_Adr (0x822c) 175 #define FUR_GEN_CNTRLS_gpreg13_Adr (0x822d) 176 #define FUR_GEN_CNTRLS_gpreg14_Adr (0x822e) 177 #define FUR_GEN_CNTRLS_gpreg15_Adr (0x822f) 178 #define FUR_GEN_CNTRLS_mst_running_chksum_Adr (0x8230) 179 #define FUR_GEN_CNTRLS_slv_running_chksum_Adr (0x8231) 180 #define FUR_GEN_CNTRLS_mst_running_byte_cnt_Adr (0x8232) 181 #define FUR_GEN_CNTRLS_slv_running_byte_cnt_Adr (0x8233) 182 #define FUR_GEN_CNTRLS_firmware_version_Adr (0x8234) 183 #define FUR_GEN_CNTRLS_firmware_enable_Adr (0x8235) 184 #define FUR_GEN_CNTRLS_micro_sync_7_Adr (0x8247) 185 #define FUR_GEN_CNTRLS_micro_sync_6_Adr (0x8246) 186 187 /*-----------------------------------------------*/ 188 /* Defines for FUR_MICRO_BOOT Bank */ 189 /*-----------------------------------------------*/ 190 #define FUR_MICRO_BOOT_BaseAdr (0x0000) 191 #define FUR_MICRO_BOOT_boot_por_Adr (0x82ff) 192 193 /*-----------------------------------------------*/ 194 /* Defines for FUR_MODULE_CNTRL Bank */ 195 /*-----------------------------------------------*/ 196 #define FUR_MODULE_CNTRL_BaseAdr (0x0000) 197 #define FUR_MODULE_CNTRL_CONTROL_Adr (0x8800) 198 #define FUR_MODULE_CNTRL_STATUS_Adr (0x8801) 199 #define FUR_MODULE_CNTRL_XFER_COUNT_Adr (0x8802) 200 #define FUR_MODULE_CNTRL_ADDRESS_Adr (0x8803) 201 #define FUR_MODULE_CNTRL_XFER_ADDR_Adr (0x8804) 202 #define FUR_MODULE_CNTRL_DEV_ID_Adr (0x8805) 203 204 /*-----------------------------------------------*/ 205 /* Defines for AMS_RX_CTRL Registers */ 206 /*-----------------------------------------------*/ 207 #define FUR_AMS_RX_RX_CNTRL0_Adr (0xd0c0) 208 209 /*-----------------------------------------------*/ 210 /* Defines for FUR_MODULE_CNTRL_RAM Bank */ 211 /*-----------------------------------------------*/ 212 #define FUR_MODULE_CNTRL_RAM_BaseAdr (0x0000) 213 #define FUR_MODULE_CNTRL_RAM_NVR0_Adr (0x8807) 214 #define FUR_MODULE_CNTRL_RAM_NVR1_Adr (0x8808) 215 #define FUR_MODULE_CNTRL_RAM_NVR2_Adr (0x8809) 216 #define FUR_MODULE_CNTRL_RAM_NVR3_Adr (0x880a) 217 #define FUR_MODULE_CNTRL_RAM_NVR4_Adr (0x880b) 218 #define FUR_MODULE_CNTRL_RAM_NVR5_Adr (0x880c) 219 #define FUR_MODULE_CNTRL_RAM_NVR6_Adr (0x880d) 220 #define FUR_MODULE_CNTRL_RAM_NVR7_Adr (0x880e) 221 #define FUR_MODULE_CNTRL_RAM_NVR8_Adr (0x880f) 222 #define FUR_MODULE_CNTRL_RAM_NVR9_Adr (0x8810) 223 #define FUR_MODULE_CNTRL_RAM_NVR10_Adr (0x8811) 224 #define FUR_MODULE_CNTRL_RAM_NVR11_Adr (0x8812) 225 #define FUR_MODULE_CNTRL_RAM_NVR12_Adr (0x8813) 226 #define FUR_MODULE_CNTRL_RAM_NVR13_Adr (0x8814) 227 #define FUR_MODULE_CNTRL_RAM_NVR14_Adr (0x8815) 228 #define FUR_MODULE_CNTRL_RAM_NVR15_Adr (0x8816) 229 #define FUR_MODULE_CNTRL_RAM_NVR16_Adr (0x8817) 230 #define FUR_MODULE_CNTRL_RAM_NVR17_Adr (0x8818) 231 #define FUR_MODULE_CNTRL_RAM_NVR18_Adr (0x8819) 232 #define FUR_MODULE_CNTRL_RAM_NVR19_Adr (0x881a) 233 #define FUR_MODULE_CNTRL_RAM_NVR20_Adr (0x881b) 234 #define FUR_MODULE_CNTRL_RAM_NVR21_Adr (0x881c) 235 #define FUR_MODULE_CNTRL_RAM_NVR22_Adr (0x881d) 236 #define FUR_MODULE_CNTRL_RAM_NVR23_Adr (0x881e) 237 #define FUR_MODULE_CNTRL_RAM_NVR24_Adr (0x881f) 238 #define FUR_MODULE_CNTRL_RAM_NVR25_Adr (0x8820) 239 #define FUR_MODULE_CNTRL_RAM_NVR26_Adr (0x8821) 240 #define FUR_MODULE_CNTRL_RAM_NVR27_Adr (0x8822) 241 #define FUR_MODULE_CNTRL_RAM_NVR28_Adr (0x8823) 242 #define FUR_MODULE_CNTRL_RAM_NVR29_Adr (0x8824) 243 #define FUR_MODULE_CNTRL_RAM_NVR30_Adr (0x8825) 244 #define FUR_MODULE_CNTRL_RAM_NVR31_Adr (0x8826) 245 #define FUR_MODULE_CNTRL_RAM_NVR32_Adr (0x8827) 246 #define FUR_MODULE_CNTRL_RAM_NVR33_Adr (0x8828) 247 #define FUR_MODULE_CNTRL_RAM_NVR34_Adr (0x8829) 248 #define FUR_MODULE_CNTRL_RAM_NVR35_Adr (0x882a) 249 #define FUR_MODULE_CNTRL_RAM_NVR36_Adr (0x882b) 250 #define FUR_MODULE_CNTRL_RAM_NVR37_Adr (0x882c) 251 #define FUR_MODULE_CNTRL_RAM_NVR38_Adr (0x882d) 252 #define FUR_MODULE_CNTRL_RAM_NVR39_Adr (0x882e) 253 #define FUR_MODULE_CNTRL_RAM_NVR40_Adr (0x882f) 254 #define FUR_MODULE_CNTRL_RAM_NVR41_Adr (0x8830) 255 #define FUR_MODULE_CNTRL_RAM_NVR42_Adr (0x8831) 256 #define FUR_MODULE_CNTRL_RAM_NVR43_Adr (0x8832) 257 #define FUR_MODULE_CNTRL_RAM_NVR44_Adr (0x8833) 258 #define FUR_MODULE_CNTRL_RAM_NVR45_Adr (0x8834) 259 #define FUR_MODULE_CNTRL_RAM_NVR46_Adr (0x8835) 260 #define FUR_MODULE_CNTRL_RAM_NVR47_Adr (0x8836) 261 #define FUR_MODULE_CNTRL_RAM_NVR48_Adr (0x8837) 262 #define FUR_MODULE_CNTRL_RAM_NVR49_Adr (0x8838) 263 #define FUR_MODULE_CNTRL_RAM_NVR50_Adr (0x8839) 264 #define FUR_MODULE_CNTRL_RAM_NVR51_Adr (0x883a) 265 #define FUR_MODULE_CNTRL_RAM_NVR52_Adr (0x883b) 266 #define FUR_MODULE_CNTRL_RAM_NVR53_Adr (0x883c) 267 #define FUR_MODULE_CNTRL_RAM_NVR54_Adr (0x883d) 268 #define FUR_MODULE_CNTRL_RAM_NVR55_Adr (0x883e) 269 #define FUR_MODULE_CNTRL_RAM_NVR56_Adr (0x883f) 270 #define FUR_MODULE_CNTRL_RAM_NVR57_Adr (0x8840) 271 #define FUR_MODULE_CNTRL_RAM_NVR58_Adr (0x8841) 272 #define FUR_MODULE_CNTRL_RAM_NVR59_Adr (0x8842) 273 #define FUR_MODULE_CNTRL_RAM_NVR60_Adr (0x8843) 274 #define FUR_MODULE_CNTRL_RAM_NVR61_Adr (0x8844) 275 #define FUR_MODULE_CNTRL_RAM_NVR62_Adr (0x8845) 276 #define FUR_MODULE_CNTRL_RAM_NVR63_Adr (0x8846) 277 #define FUR_MODULE_CNTRL_RAM_NVR64_Adr (0x8847) 278 #define FUR_MODULE_CNTRL_RAM_NVR65_Adr (0x8848) 279 #define FUR_MODULE_CNTRL_RAM_NVR66_Adr (0x8849) 280 #define FUR_MODULE_CNTRL_RAM_NVR67_Adr (0x884a) 281 #define FUR_MODULE_CNTRL_RAM_NVR68_Adr (0x884b) 282 #define FUR_MODULE_CNTRL_RAM_NVR69_Adr (0x884c) 283 #define FUR_MODULE_CNTRL_RAM_NVR70_Adr (0x884d) 284 #define FUR_MODULE_CNTRL_RAM_NVR71_Adr (0x884e) 285 #define FUR_MODULE_CNTRL_RAM_NVR72_Adr (0x884f) 286 #define FUR_MODULE_CNTRL_RAM_NVR73_Adr (0x8850) 287 #define FUR_MODULE_CNTRL_RAM_NVR74_Adr (0x8851) 288 #define FUR_MODULE_CNTRL_RAM_NVR75_Adr (0x8852) 289 #define FUR_MODULE_CNTRL_RAM_NVR76_Adr (0x8853) 290 #define FUR_MODULE_CNTRL_RAM_NVR77_Adr (0x8854) 291 #define FUR_MODULE_CNTRL_RAM_NVR78_Adr (0x8855) 292 #define FUR_MODULE_CNTRL_RAM_NVR79_Adr (0x8856) 293 #define FUR_MODULE_CNTRL_RAM_NVR80_Adr (0x8857) 294 #define FUR_MODULE_CNTRL_RAM_NVR81_Adr (0x8858) 295 #define FUR_MODULE_CNTRL_RAM_NVR82_Adr (0x8859) 296 #define FUR_MODULE_CNTRL_RAM_NVR83_Adr (0x885a) 297 #define FUR_MODULE_CNTRL_RAM_NVR84_Adr (0x885b) 298 #define FUR_MODULE_CNTRL_RAM_NVR85_Adr (0x885c) 299 #define FUR_MODULE_CNTRL_RAM_NVR86_Adr (0x885d) 300 #define FUR_MODULE_CNTRL_RAM_NVR87_Adr (0x885e) 301 #define FUR_MODULE_CNTRL_RAM_NVR88_Adr (0x885f) 302 #define FUR_MODULE_CNTRL_RAM_NVR89_Adr (0x8860) 303 #define FUR_MODULE_CNTRL_RAM_NVR90_Adr (0x8861) 304 #define FUR_MODULE_CNTRL_RAM_NVR91_Adr (0x8862) 305 #define FUR_MODULE_CNTRL_RAM_NVR92_Adr (0x8863) 306 #define FUR_MODULE_CNTRL_RAM_NVR93_Adr (0x8864) 307 #define FUR_MODULE_CNTRL_RAM_NVR94_Adr (0x8865) 308 #define FUR_MODULE_CNTRL_RAM_NVR95_Adr (0x8866) 309 #define FUR_MODULE_CNTRL_RAM_NVR96_Adr (0x8867) 310 #define FUR_MODULE_CNTRL_RAM_NVR97_Adr (0x8868) 311 #define FUR_MODULE_CNTRL_RAM_NVR98_Adr (0x8869) 312 #define FUR_MODULE_CNTRL_RAM_NVR99_Adr (0x886a) 313 #define FUR_MODULE_CNTRL_RAM_NVR100_Adr (0x886b) 314 #define FUR_MODULE_CNTRL_RAM_NVR101_Adr (0x886c) 315 #define FUR_MODULE_CNTRL_RAM_NVR102_Adr (0x886d) 316 #define FUR_MODULE_CNTRL_RAM_NVR103_Adr (0x886e) 317 #define FUR_MODULE_CNTRL_RAM_NVR104_Adr (0x886f) 318 #define FUR_MODULE_CNTRL_RAM_NVR105_Adr (0x8870) 319 #define FUR_MODULE_CNTRL_RAM_NVR106_Adr (0x8871) 320 #define FUR_MODULE_CNTRL_RAM_NVR107_Adr (0x8872) 321 #define FUR_MODULE_CNTRL_RAM_NVR108_Adr (0x8873) 322 #define FUR_MODULE_CNTRL_RAM_NVR109_Adr (0x8874) 323 #define FUR_MODULE_CNTRL_RAM_NVR110_Adr (0x8875) 324 #define FUR_MODULE_CNTRL_RAM_NVR111_Adr (0x8876) 325 #define FUR_MODULE_CNTRL_RAM_NVR112_Adr (0x8877) 326 #define FUR_MODULE_CNTRL_RAM_NVR113_Adr (0x8878) 327 #define FUR_MODULE_CNTRL_RAM_NVR114_Adr (0x8879) 328 #define FUR_MODULE_CNTRL_RAM_NVR115_Adr (0x887a) 329 #define FUR_MODULE_CNTRL_RAM_NVR116_Adr (0x887b) 330 #define FUR_MODULE_CNTRL_RAM_NVR117_Adr (0x887c) 331 #define FUR_MODULE_CNTRL_RAM_NVR118_Adr (0x887d) 332 #define FUR_MODULE_CNTRL_RAM_NVR119_Adr (0x887e) 333 #define FUR_MODULE_CNTRL_RAM_NVR120_Adr (0x887f) 334 #define FUR_MODULE_CNTRL_RAM_NVR121_Adr (0x8880) 335 #define FUR_MODULE_CNTRL_RAM_NVR122_Adr (0x8881) 336 #define FUR_MODULE_CNTRL_RAM_NVR123_Adr (0x8882) 337 #define FUR_MODULE_CNTRL_RAM_NVR124_Adr (0x8883) 338 #define FUR_MODULE_CNTRL_RAM_NVR125_Adr (0x8884) 339 #define FUR_MODULE_CNTRL_RAM_NVR126_Adr (0x8885) 340 #define FUR_MODULE_CNTRL_RAM_NVR127_Adr (0x8886) 341 #define FUR_MODULE_CNTRL_RAM_NVR128_Adr (0x8887) 342 #define FUR_MODULE_CNTRL_RAM_NVR129_Adr (0x8888) 343 #define FUR_MODULE_CNTRL_RAM_NVR130_Adr (0x8889) 344 #define FUR_MODULE_CNTRL_RAM_NVR131_Adr (0x888a) 345 #define FUR_MODULE_CNTRL_RAM_NVR132_Adr (0x888b) 346 #define FUR_MODULE_CNTRL_RAM_NVR133_Adr (0x888c) 347 #define FUR_MODULE_CNTRL_RAM_NVR134_Adr (0x888d) 348 #define FUR_MODULE_CNTRL_RAM_NVR135_Adr (0x888e) 349 #define FUR_MODULE_CNTRL_RAM_NVR136_Adr (0x888f) 350 #define FUR_MODULE_CNTRL_RAM_NVR137_Adr (0x8890) 351 #define FUR_MODULE_CNTRL_RAM_NVR138_Adr (0x8891) 352 #define FUR_MODULE_CNTRL_RAM_NVR139_Adr (0x8892) 353 #define FUR_MODULE_CNTRL_RAM_NVR140_Adr (0x8893) 354 #define FUR_MODULE_CNTRL_RAM_NVR141_Adr (0x8894) 355 #define FUR_MODULE_CNTRL_RAM_NVR142_Adr (0x8895) 356 #define FUR_MODULE_CNTRL_RAM_NVR143_Adr (0x8896) 357 #define FUR_MODULE_CNTRL_RAM_NVR144_Adr (0x8897) 358 #define FUR_MODULE_CNTRL_RAM_NVR145_Adr (0x8898) 359 #define FUR_MODULE_CNTRL_RAM_NVR146_Adr (0x8899) 360 #define FUR_MODULE_CNTRL_RAM_NVR147_Adr (0x889a) 361 #define FUR_MODULE_CNTRL_RAM_NVR148_Adr (0x889b) 362 #define FUR_MODULE_CNTRL_RAM_NVR149_Adr (0x889c) 363 #define FUR_MODULE_CNTRL_RAM_NVR150_Adr (0x889d) 364 #define FUR_MODULE_CNTRL_RAM_NVR151_Adr (0x889e) 365 #define FUR_MODULE_CNTRL_RAM_NVR152_Adr (0x889f) 366 #define FUR_MODULE_CNTRL_RAM_NVR153_Adr (0x88a0) 367 #define FUR_MODULE_CNTRL_RAM_NVR154_Adr (0x88a1) 368 #define FUR_MODULE_CNTRL_RAM_NVR155_Adr (0x88a2) 369 #define FUR_MODULE_CNTRL_RAM_NVR156_Adr (0x88a3) 370 #define FUR_MODULE_CNTRL_RAM_NVR157_Adr (0x88a4) 371 #define FUR_MODULE_CNTRL_RAM_NVR158_Adr (0x88a5) 372 #define FUR_MODULE_CNTRL_RAM_NVR159_Adr (0x88a6) 373 #define FUR_MODULE_CNTRL_RAM_NVR160_Adr (0x88a7) 374 #define FUR_MODULE_CNTRL_RAM_NVR161_Adr (0x88a8) 375 #define FUR_MODULE_CNTRL_RAM_NVR162_Adr (0x88a9) 376 #define FUR_MODULE_CNTRL_RAM_NVR163_Adr (0x88aa) 377 #define FUR_MODULE_CNTRL_RAM_NVR164_Adr (0x88ab) 378 #define FUR_MODULE_CNTRL_RAM_NVR165_Adr (0x88ac) 379 #define FUR_MODULE_CNTRL_RAM_NVR166_Adr (0x88ad) 380 #define FUR_MODULE_CNTRL_RAM_NVR167_Adr (0x88ae) 381 #define FUR_MODULE_CNTRL_RAM_NVR168_Adr (0x88af) 382 #define FUR_MODULE_CNTRL_RAM_NVR169_Adr (0x88b0) 383 #define FUR_MODULE_CNTRL_RAM_NVR170_Adr (0x88b1) 384 #define FUR_MODULE_CNTRL_RAM_NVR171_Adr (0x88b2) 385 #define FUR_MODULE_CNTRL_RAM_NVR172_Adr (0x88b3) 386 #define FUR_MODULE_CNTRL_RAM_NVR173_Adr (0x88b4) 387 #define FUR_MODULE_CNTRL_RAM_NVR174_Adr (0x88b5) 388 #define FUR_MODULE_CNTRL_RAM_NVR175_Adr (0x88b6) 389 #define FUR_MODULE_CNTRL_RAM_NVR176_Adr (0x88b7) 390 #define FUR_MODULE_CNTRL_RAM_NVR177_Adr (0x88b8) 391 #define FUR_MODULE_CNTRL_RAM_NVR178_Adr (0x88b9) 392 #define FUR_MODULE_CNTRL_RAM_NVR179_Adr (0x88ba) 393 #define FUR_MODULE_CNTRL_RAM_NVR180_Adr (0x88bb) 394 #define FUR_MODULE_CNTRL_RAM_NVR181_Adr (0x88bc) 395 #define FUR_MODULE_CNTRL_RAM_NVR182_Adr (0x88bd) 396 #define FUR_MODULE_CNTRL_RAM_NVR183_Adr (0x88be) 397 #define FUR_MODULE_CNTRL_RAM_NVR184_Adr (0x88bf) 398 #define FUR_MODULE_CNTRL_RAM_NVR185_Adr (0x88c0) 399 #define FUR_MODULE_CNTRL_RAM_NVR186_Adr (0x88c1) 400 #define FUR_MODULE_CNTRL_RAM_NVR187_Adr (0x88c2) 401 #define FUR_MODULE_CNTRL_RAM_NVR188_Adr (0x88c3) 402 #define FUR_MODULE_CNTRL_RAM_NVR189_Adr (0x88c4) 403 #define FUR_MODULE_CNTRL_RAM_NVR190_Adr (0x88c5) 404 #define FUR_MODULE_CNTRL_RAM_NVR191_Adr (0x88c6) 405 #define FUR_MODULE_CNTRL_RAM_NVR192_Adr (0x88c7) 406 #define FUR_MODULE_CNTRL_RAM_NVR193_Adr (0x88c8) 407 #define FUR_MODULE_CNTRL_RAM_NVR194_Adr (0x88c9) 408 #define FUR_MODULE_CNTRL_RAM_NVR195_Adr (0x88ca) 409 #define FUR_MODULE_CNTRL_RAM_NVR196_Adr (0x88cb) 410 #define FUR_MODULE_CNTRL_RAM_NVR197_Adr (0x88cc) 411 #define FUR_MODULE_CNTRL_RAM_NVR198_Adr (0x88cd) 412 #define FUR_MODULE_CNTRL_RAM_NVR199_Adr (0x88ce) 413 #define FUR_MODULE_CNTRL_RAM_NVR200_Adr (0x88cf) 414 #define FUR_MODULE_CNTRL_RAM_NVR201_Adr (0x88d0) 415 #define FUR_MODULE_CNTRL_RAM_NVR202_Adr (0x88d1) 416 #define FUR_MODULE_CNTRL_RAM_NVR203_Adr (0x88d2) 417 #define FUR_MODULE_CNTRL_RAM_NVR204_Adr (0x88d3) 418 #define FUR_MODULE_CNTRL_RAM_NVR205_Adr (0x88d4) 419 #define FUR_MODULE_CNTRL_RAM_NVR206_Adr (0x88d5) 420 #define FUR_MODULE_CNTRL_RAM_NVR207_Adr (0x88d6) 421 #define FUR_MODULE_CNTRL_RAM_NVR208_Adr (0x88d7) 422 #define FUR_MODULE_CNTRL_RAM_NVR209_Adr (0x88d8) 423 #define FUR_MODULE_CNTRL_RAM_NVR210_Adr (0x88d9) 424 #define FUR_MODULE_CNTRL_RAM_NVR211_Adr (0x88da) 425 #define FUR_MODULE_CNTRL_RAM_NVR212_Adr (0x88db) 426 #define FUR_MODULE_CNTRL_RAM_NVR213_Adr (0x88dc) 427 #define FUR_MODULE_CNTRL_RAM_NVR214_Adr (0x88dd) 428 #define FUR_MODULE_CNTRL_RAM_NVR215_Adr (0x88de) 429 #define FUR_MODULE_CNTRL_RAM_NVR216_Adr (0x88df) 430 #define FUR_MODULE_CNTRL_RAM_NVR217_Adr (0x88e0) 431 #define FUR_MODULE_CNTRL_RAM_NVR218_Adr (0x88e1) 432 #define FUR_MODULE_CNTRL_RAM_NVR219_Adr (0x88e2) 433 #define FUR_MODULE_CNTRL_RAM_NVR220_Adr (0x88e3) 434 #define FUR_MODULE_CNTRL_RAM_NVR221_Adr (0x88e4) 435 #define FUR_MODULE_CNTRL_RAM_NVR222_Adr (0x88e5) 436 #define FUR_MODULE_CNTRL_RAM_NVR223_Adr (0x88e6) 437 #define FUR_MODULE_CNTRL_RAM_NVR224_Adr (0x88e7) 438 #define FUR_MODULE_CNTRL_RAM_NVR225_Adr (0x88e8) 439 #define FUR_MODULE_CNTRL_RAM_NVR226_Adr (0x88e9) 440 #define FUR_MODULE_CNTRL_RAM_NVR227_Adr (0x88ea) 441 #define FUR_MODULE_CNTRL_RAM_NVR228_Adr (0x88eb) 442 #define FUR_MODULE_CNTRL_RAM_NVR229_Adr (0x88ec) 443 #define FUR_MODULE_CNTRL_RAM_NVR230_Adr (0x88ed) 444 #define FUR_MODULE_CNTRL_RAM_NVR231_Adr (0x88ee) 445 #define FUR_MODULE_CNTRL_RAM_NVR232_Adr (0x88ef) 446 #define FUR_MODULE_CNTRL_RAM_NVR233_Adr (0x88f0) 447 #define FUR_MODULE_CNTRL_RAM_NVR234_Adr (0x88f1) 448 #define FUR_MODULE_CNTRL_RAM_NVR235_Adr (0x88f2) 449 #define FUR_MODULE_CNTRL_RAM_NVR236_Adr (0x88f3) 450 #define FUR_MODULE_CNTRL_RAM_NVR237_Adr (0x88f4) 451 #define FUR_MODULE_CNTRL_RAM_NVR238_Adr (0x88f5) 452 #define FUR_MODULE_CNTRL_RAM_NVR239_Adr (0x88f6) 453 #define FUR_MODULE_CNTRL_RAM_NVR240_Adr (0x88f7) 454 #define FUR_MODULE_CNTRL_RAM_NVR241_Adr (0x88f8) 455 #define FUR_MODULE_CNTRL_RAM_NVR242_Adr (0x88f9) 456 #define FUR_MODULE_CNTRL_RAM_NVR243_Adr (0x88fa) 457 #define FUR_MODULE_CNTRL_RAM_NVR244_Adr (0x88fb) 458 #define FUR_MODULE_CNTRL_RAM_NVR245_Adr (0x88fc) 459 #define FUR_MODULE_CNTRL_RAM_NVR246_Adr (0x88fd) 460 #define FUR_MODULE_CNTRL_RAM_NVR247_Adr (0x88fe) 461 #define FUR_MODULE_CNTRL_RAM_NVR248_Adr (0x88ff) 462 #define FUR_MODULE_CNTRL_RAM_NVR249_Adr (0x8900) 463 #define FUR_MODULE_CNTRL_RAM_NVR250_Adr (0x8901) 464 #define FUR_MODULE_CNTRL_RAM_NVR251_Adr (0x8902) 465 #define FUR_MODULE_CNTRL_RAM_NVR252_Adr (0x8903) 466 #define FUR_MODULE_CNTRL_RAM_NVR253_Adr (0x8904) 467 #define FUR_MODULE_CNTRL_RAM_NVR254_Adr (0x8905) 468 #define FUR_MODULE_CNTRL_RAM_NVR255_Adr (0x8906) 469 470 /*-----------------------------------------------*/ 471 /* Defines for FUR_MISC_CTRL Bank */ 472 /*-----------------------------------------------*/ 473 #define FUR_MISC_CTRL_BaseAdr (0x0000) 474 #define FUR_MISC_CTRL_chip_id_Adr (0x8a00) 475 #define FUR_MISC_CTRL_chip_revision_Adr (0x8a01) 476 #define FUR_MISC_CTRL_mode_dec_frc_Adr (0x8a02) 477 #define FUR_MISC_CTRL_udms_phy_Adr (0x8a03) 478 #define FUR_MISC_CTRL_udms_link_Adr (0x8a04) 479 #define FUR_MISC_CTRL_mode_dec_frc_val_Adr (0x8a05) 480 #define FUR_MISC_CTRL_phy_type_status_Adr (0x8a06) 481 #define FUR_MISC_CTRL_link_type_status_Adr (0x8a07) 482 #define FUR_MISC_CTRL_logic_to_phy_ln0_map_Adr (0x8a08) 483 #define FUR_MISC_CTRL_m0_eisr_Adr (0x8a10) 484 #define FUR_MISC_CTRL_m0_eipr_Adr (0x8a11) 485 #define FUR_MISC_CTRL_m0_eimr_Adr (0x8a12) 486 #define FUR_MISC_CTRL_sf_eisr_Adr (0x8a13) 487 #define FUR_MISC_CTRL_sf_eipr_Adr (0x8a14) 488 #define FUR_MISC_CTRL_sf_eimr_Adr (0x8a15) 489 #define FUR_MISC_CTRL_lf_eisr_Adr (0x8a16) 490 #define FUR_MISC_CTRL_lf_eipr_Adr (0x8a17) 491 #define FUR_MISC_CTRL_lf_eimr_Adr (0x8a18) 492 #define FUR_MISC_CTRL_rx_eisr_Adr (0x8a19) 493 #define FUR_MISC_CTRL_rx_eipr_Adr (0x8a1a) 494 #define FUR_MISC_CTRL_rx_eimr_Adr (0x8a1b) 495 #define FUR_MISC_CTRL_tx_eisr_Adr (0x8a1c) 496 #define FUR_MISC_CTRL_tx_eipr_Adr (0x8a1d) 497 #define FUR_MISC_CTRL_tx_eimr_Adr (0x8a1e) 498 499 /*-----------------------------------------------*/ 500 /* Defines for CL91_USER_RX Bank */ 501 /*-----------------------------------------------*/ 502 #define CL91_USER_RX_BaseAdr (0x9400) 503 #define CL91_USER_RX_status_Adr (0x9400) 504 #define CL91_USER_RX_latched_status_Adr (0x9401) 505 #define CL91_USER_RX_skew_ln3_Adr (0x9402) 506 #define CL91_USER_RX_skew_ln2_Adr (0x9403) 507 #define CL91_USER_RX_skew_ln1_Adr (0x9404) 508 #define CL91_USER_RX_skew_ln0_Adr (0x9405) 509 #define CL91_USER_RX_phy_ln3_mapping_ctrl1_Adr (0x9406) 510 #define CL91_USER_RX_phy_ln3_mapping_ctrl2_Adr (0x9407) 511 #define CL91_USER_RX_phy_ln3_mapping_ctrl3_Adr (0x9408) 512 #define CL91_USER_RX_phy_ln2_mapping_ctrl1_Adr (0x9409) 513 #define CL91_USER_RX_phy_ln2_mapping_ctrl2_Adr (0x940a) 514 #define CL91_USER_RX_phy_ln2_mapping_ctrl3_Adr (0x940b) 515 #define CL91_USER_RX_phy_ln1_mapping_ctrl1_Adr (0x940c) 516 #define CL91_USER_RX_phy_ln1_mapping_ctrl2_Adr (0x940d) 517 #define CL91_USER_RX_phy_ln1_mapping_ctrl3_Adr (0x940e) 518 #define CL91_USER_RX_phy_ln0_mapping_ctrl1_Adr (0x940f) 519 #define CL91_USER_RX_phy_ln0_mapping_ctrl2_Adr (0x9410) 520 #define CL91_USER_RX_phy_ln0_mapping_ctrl3_Adr (0x9411) 521 #define CL91_USER_RX_debug_ctrl_Adr (0x9420) 522 #define CL91_USER_RX_debug_status1_Adr (0x9421) 523 #define CL91_USER_RX_debug_status2_Adr (0x9422) 524 525 /*-----------------------------------------------*/ 526 /* Defines for CL91_USER_TX Bank */ 527 /*-----------------------------------------------*/ 528 #define CL91_USER_TX_BaseAdr (0x9c00) 529 #define CL91_USER_TX_control_Adr (0x9c00) 530 #define CL91_USER_TX_status1_Adr (0x9c01) 531 #define CL91_USER_TX_status2_Adr (0x9c02) 532 #define CL91_USER_TX_status3_Adr (0x9c03) 533 #define CL91_USER_TX_status4_Adr (0x9c04) 534 #define CL91_USER_TX_status5_Adr (0x9c05) 535 #define CL91_USER_TX_ln0_status_Adr (0x9c06) 536 #define CL91_USER_TX_ln1_status_Adr (0x9c07) 537 #define CL91_USER_TX_ln2_status_Adr (0x9c08) 538 #define CL91_USER_TX_ln3_status_Adr (0x9c09) 539 #define CL91_USER_TX_ln4_status_Adr (0x9c0a) 540 #define CL91_USER_TX_ln5_status_Adr (0x9c0b) 541 #define CL91_USER_TX_ln6_status_Adr (0x9c0c) 542 #define CL91_USER_TX_ln7_status_Adr (0x9c0d) 543 #define CL91_USER_TX_ln8_status_Adr (0x9c0e) 544 #define CL91_USER_TX_ln9_status_Adr (0x9c0f) 545 #define CL91_USER_TX_ln10_status_Adr (0x9c10) 546 #define CL91_USER_TX_ln11_status_Adr (0x9c11) 547 #define CL91_USER_TX_ln12_status_Adr (0x9c12) 548 #define CL91_USER_TX_ln13_status_Adr (0x9c13) 549 #define CL91_USER_TX_ln14_status_Adr (0x9c14) 550 #define CL91_USER_TX_ln15_status_Adr (0x9c15) 551 #define CL91_USER_TX_ln16_status_Adr (0x9c16) 552 #define CL91_USER_TX_ln17_status_Adr (0x9c17) 553 #define CL91_USER_TX_ln18_status_Adr (0x9c18) 554 #define CL91_USER_TX_ln19_status_Adr (0x9c19) 555 556 /*-----------------------------------------------*/ 557 /* Defines for XGXS_BLK0 Bank */ 558 /*-----------------------------------------------*/ 559 #define XGXS_BLK0_BaseAdr (0xc000) 560 #define XGXS_BLK0_xgxsControl_Adr (0xc000) 561 #define XGXS_BLK0_xgxsStatus_Adr (0xc001) 562 #define XGXS_BLK0_miscControl1_Adr (0xc00e) 563 564 /*-----------------------------------------------*/ 565 /* Defines for TX_ANA_REGS Bank */ 566 /*-----------------------------------------------*/ 567 #define TX_ANA_REGS_BaseAdr (0xc080) 568 #define TX_ANA_REGS_anaTxAStatus_Adr (0xc080) 569 #define TX_ANA_REGS_anaTxAControl0_Adr (0xc081) 570 #define TX_ANA_REGS_anaTxAControl7_Adr (0xc08b) 571 572 /*-----------------------------------------------*/ 573 /* Defines for RX_ANA_REGS Bank */ 574 /*-----------------------------------------------*/ 575 #define RX_ANA_REGS_BaseAdr (0xc0b0) 576 #define RX_ANA_REGS_anaRxStatus_Adr (0xc0b0) 577 #define RX_ANA_REGS_anaRxControl_Adr (0xc0b1) 578 #define RX_ANA_REGS_anaRxSigdet_Adr (0xc0b4) 579 #define RX_ANA_REGS_anaRxControl2_Adr (0xc0b6) 580 #define RX_ANA_REGS_anaRxControl3_Adr (0xc0ba) 581 582 /*-----------------------------------------------*/ 583 /* Defines for XGXS_BLK2 Bank */ 584 /*-----------------------------------------------*/ 585 #define XGXS_BLK2_BaseAdr (0xc100) 586 #define XGXS_BLK2_laneReset_Adr (0xc10a) 587 588 /*-----------------------------------------------*/ 589 /* Defines for XGXS_BLK8 Bank */ 590 /*-----------------------------------------------*/ 591 #define XGXS_BLK8_BaseAdr (0xc160) 592 #define XGXS_BLK8_cl73Control9_Adr (0xc162) 593 594 /*-----------------------------------------------*/ 595 /* Defines for PMA_PMD_GNRTL_STATUS Bank */ 596 /*-----------------------------------------------*/ 597 #define PMA_PMD_GNRTL_STATUS_BaseAdr (0xc1d0) 598 #define PMA_PMD_GNRTL_STATUS_GP2_0_Adr (0xc1d0) 599 #define PMA_PMD_GNRTL_STATUS_GP2_1_Adr (0xc1d1) 600 #define PMA_PMD_GNRTL_STATUS_GP2_2_Adr (0xc1d2) 601 #define PMA_PMD_GNRTL_STATUS_GP2_3_Adr (0xc1d3) 602 #define PMA_PMD_GNRTL_STATUS_GP2_4_Adr (0xc1d4) 603 #define PMA_PMD_GNRTL_STATUS_GP2_5_Adr (0xc1d5) 604 #define PMA_PMD_GNRTL_STATUS_GP2_6_Adr (0xc1d6) 605 #define PMA_PMD_GNRTL_STATUS_GP2_7_Adr (0xc1d7) 606 #define PMA_PMD_GNRTL_STATUS_GP2_8_Adr (0xc1d8) 607 #define PMA_PMD_GNRTL_STATUS_GP2_9_Adr (0xc1d9) 608 609 /*-----------------------------------------------*/ 610 /* Defines for LINE_RX_PMA_DP Bank */ 611 /*-----------------------------------------------*/ 612 #define LINE_RX_PMA_DP_BaseAdr (0xa000) 613 #define LINE_RX_PMA_DP_main_ctrl_Adr (0xa000) 614 #define LINE_RX_PMA_DP_dp_ctrl_Adr (0xa001) 615 #define LINE_RX_PMA_DP_latched_status_Adr (0xa010) 616 #define LINE_RX_PMA_DP_cl49_latched_status_Adr (0xa011) 617 #define LINE_RX_PMA_DP_cl82_ber_count_MSB_Adr (0xa012) 618 #define LINE_RX_PMA_DP_live_status_Adr (0xa013) 619 620 /*-----------------------------------------------*/ 621 /* Defines for LINE_TX_PMA_DP Bank */ 622 /*-----------------------------------------------*/ 623 #define LINE_TX_PMA_DP_BaseAdr (0xac00) 624 #define LINE_TX_PMA_DP_soft_rst_Adr (0xac00) 625 #define LINE_TX_PMA_DP_ctrl_Adr (0xac01) 626 #define LINE_TX_PMA_DP_pf_status_Adr (0xac10) 627 628 /*-----------------------------------------------*/ 629 /* Defines for SYS_RX_PMA_DP Bank */ 630 /*-----------------------------------------------*/ 631 #define SYS_RX_PMA_DP_BaseAdr (0xb000) 632 #define SYS_RX_PMA_DP_main_ctrl_Adr (0xb000) 633 #define SYS_RX_PMA_DP_dp_ctrl_Adr (0xb001) 634 #define SYS_RX_PMA_DP_latched_status_Adr (0xb010) 635 #define SYS_RX_PMA_DP_cl49_latched_status_Adr (0xa011) 636 #define SYS_RX_PMA_DP_cl82_ber_count_MSB_Adr (0xb012) 637 #define SYS_RX_PMA_DP_live_status_Adr (0xb013) 638 639 /*-----------------------------------------------*/ 640 /* Defines for SYS_TX_PMA_DP Bank */ 641 /*-----------------------------------------------*/ 642 #define SYS_TX_PMA_DP_BaseAdr (0xbc00) 643 #define SYS_TX_PMA_DP_soft_rst_Adr (0xbc00) 644 #define SYS_TX_PMA_DP_ctrl_Adr (0xbc01) 645 #define SYS_TX_PMA_DP_pf_status_Adr (0xbc10) 646 647 /*-----------------------------------------------*/ 648 /* Defines for DSC_C Bank */ 649 /*-----------------------------------------------*/ 650 #define DSC_C_BaseAdr (0xd050) 651 #define DSC_C_cdr_control_2_Adr (0xd052) 652 #define DSC_C_rx_pi_control_Adr (0xd053) 653 654 /*-----------------------------------------------*/ 655 /* Defines for DSC_D Bank */ 656 /*-----------------------------------------------*/ 657 #define DSC_D_dsc_sm_ctrl_9_Adr (0xd069) 658 659 /* Defines for TX_PI_RPTR Bank */ 660 /*-----------------------------------------------*/ 661 #define TX_PI_RPTR_BaseAdr (0xd0a0) 662 #define TX_PI_RPTR_tx_pi_control_0_Adr (0xd0a0) 663 #define TX_PI_RPTR_tx_pi_control_5_Adr (0xd0a5) 664 665 /*-----------------------------------------------*/ 666 /* Defines for CL93n72_USER_TX Bank */ 667 /*-----------------------------------------------*/ 668 #define CL93n72_USER_TX_BaseAdr (0xd090) 669 #define CL93n72_USER_TX_cl93n72ut_control2_register_Adr (0xd094) 670 #define CL93n72_USER_TX_cl93n72ut_control3_register_Adr (0xd095) 671 672 /*-----------------------------------------------*/ 673 /* Defines for CKRST_CTRL_RPTR Bank */ 674 /*-----------------------------------------------*/ 675 #define CKRST_CTRL_RPTR_BaseAdr (0xd0b0) 676 #define CKRST_CTRL_RPTR_OSR_MODE_CONTROL_Adr (0xd0b0) 677 #define CKRST_CTRL_RPTR_LANE_CLK_RESET_N_POWERDOWN_CONTROL_Adr (0xd0b1) 678 #define CKRST_CTRL_RPTR_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL_Adr (0xd0b2) 679 #define CKRST_CTRL_RPTR_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL_Adr (0xd0b3) 680 681 /*-----------------------------------------------*/ 682 /* Defines for PLL_CAL_COM Bank */ 683 /*-----------------------------------------------*/ 684 #define PLL_CAL_COM_BaseAdr (0xd140) 685 #define PLL_CAL_COM_CTL_0_Adr (0xd140) 686 #define PLL_CAL_COM_CTL_1_Adr (0xd141) 687 #define PLL_CAL_COM_CTL_2_Adr (0xd142) 688 #define PLL_CAL_COM_CTL_5_Adr (0xd145) 689 #define PLL_CAL_COM_CTL_7_Adr (0xd147) 690 #define PLL_CAL_COM_CTL_STATUS_0_Adr (0xd148) 691 692 /*-----------------------------------------------*/ 693 /* Defines for AMS_COM Bank */ 694 /*-----------------------------------------------*/ 695 #define AMS_COM_BaseAdr (0xd110) 696 #define AMS_COM_PLL_CONTROL_1_Adr (0xd111) 697 #define AMS_COM_PLL_CONTROL_3_Adr (0xd113) 698 699 /*-----------------------------------------------*/ 700 /* Defines for PATT_GEN_COM Bank */ 701 /*-----------------------------------------------*/ 702 #define PATT_GEN_COM_BaseAdr (0xd120) 703 #define PATT_GEN_COM_patt_gen_seq_0_Adr (0xd120) 704 #define PATT_GEN_COM_patt_gen_seq_1_Adr (0xd121) 705 #define PATT_GEN_COM_patt_gen_seq_2_Adr (0xd122) 706 #define PATT_GEN_COM_patt_gen_seq_3_Adr (0xd123) 707 #define PATT_GEN_COM_patt_gen_seq_4_Adr (0xd124) 708 #define PATT_GEN_COM_patt_gen_seq_5_Adr (0xd125) 709 #define PATT_GEN_COM_patt_gen_seq_6_Adr (0xd126) 710 #define PATT_GEN_COM_patt_gen_seq_7_Adr (0xd127) 711 #define PATT_GEN_COM_patt_gen_seq_8_Adr (0xd128) 712 #define PATT_GEN_COM_patt_gen_seq_9_Adr (0xd129) 713 #define PATT_GEN_COM_patt_gen_seq_10_Adr (0xd12a) 714 #define PATT_GEN_COM_patt_gen_seq_11_Adr (0xd12b) 715 #define PATT_GEN_COM_patt_gen_seq_12_Adr (0xd12c) 716 #define PATT_GEN_COM_patt_gen_seq_13_Adr (0xd12d) 717 #define PATT_GEN_COM_patt_gen_seq_14_Adr (0xd12e) 718 719 /*-----------------------------------------------*/ 720 /* Defines for TX_FED Bank */ 721 /*-----------------------------------------------*/ 722 #define TX_FED_BaseAdr (0xd130) 723 #define TX_FED_txfir_control1_Adr (0xd131) 724 #define TX_FED_txfir_control2_Adr (0xd132) 725 #define TX_FED_txfir_misc_control1_Adr (0xd139) 726 727 /*-----------------------------------------------*/ 728 /* Defines for TLB_RX Bank */ 729 /*-----------------------------------------------*/ 730 #define TLB_RX_BaseAdr (0xd160) 731 #define TLB_RX_prbs_chk_cnt_config_Adr (0xd160) 732 #define TLB_RX_prbs_chk_config_Adr (0xd161) 733 #define TLB_RX_dig_lpbk_config_Adr (0xd162) 734 #define TLB_RX_tlb_rx_misc_config_Adr (0xd163) 735 #define TLB_RX_prbs_chk_lock_status_Adr (0xd169) 736 #define TLB_RX_prbs_chk_err_cnt_msb_status_Adr (0xd16a) 737 #define TLB_RX_prbs_chk_err_cnt_lsb_status_Adr (0xd16b) 738 #define TLB_RX_pmd_rx_lock_status_Adr (0xd16c) 739 740 /*-----------------------------------------------*/ 741 /* Defines for TLB_TX Bank */ 742 /*-----------------------------------------------*/ 743 #define TLB_TX_BaseAdr (0xd170) 744 #define TLB_TX_patt_gen_config_Adr (0xd170) 745 #define TLB_TX_prbs_gen_config_Adr (0xd171) 746 #define TLB_TX_rmt_lpbk_config_Adr (0xd172) 747 #define TLB_TX_tlb_tx_misc_config_Adr (0xd173) 748 749 /*-----------------------------------------------*/ 750 /* Defines for IEEE_AN_BLK0 Bank */ 751 /*-----------------------------------------------*/ 752 #define IEEE_AN_BLK0_BaseAdr (0x0000) 753 #define IEEE_AN_BLK0_an_control_register_Adr (0x0000) 754 #define IEEE_AN_BLK0_an_status_register_Adr (0x0001) 755 #define IEEE_AN_BLK0_an_identifier_register_0_Adr (0x0002) 756 #define IEEE_AN_BLK0_an_identifier_register_1_Adr (0x0003) 757 #define IEEE_AN_BLK0_an_devices_in_package_1_Adr (0x0005) 758 #define IEEE_AN_BLK0_an_devices_in_package_2_Adr (0x0006) 759 #define IEEE_AN_BLK0_an_oui_id0_register_Adr (0x000e) 760 #define IEEE_AN_BLK0_an_oui_id1_reg_Adr (0x000f) 761 762 /*-----------------------------------------------*/ 763 /* Defines for IEEE_AN_BLK1 Bank */ 764 /*-----------------------------------------------*/ 765 #define IEEE_AN_BLK1_BaseAdr (0x0010) 766 #define IEEE_AN_BLK1_an_advertisement_1_register_Adr (0x0010) 767 #define IEEE_AN_BLK1_an_advertisement_2_register_Adr (0x0011) 768 #define IEEE_AN_BLK1_an_advertisement_3_register_Adr (0x0012) 769 #define IEEE_AN_BLK1_an_lp_base_page_ability_1_reg_Adr (0x0013) 770 #define IEEE_AN_BLK1_an_lp_base_page_ability_2_reg_Adr (0x0014) 771 #define IEEE_AN_BLK1_an_lp_base_page_ability_3_reg_Adr (0x0015) 772 #define IEEE_AN_BLK1_an_xnp_transmit_1_register_Adr (0x0016) 773 #define IEEE_AN_BLK1_an_xnp_transmit_2_register_Adr (0x0017) 774 #define IEEE_AN_BLK1_an_xnp_transmit_3_register_Adr (0x0018) 775 #define IEEE_AN_BLK1_an_lp_xnp_transmit_1_register_Adr (0x0019) 776 #define IEEE_AN_BLK1_an_lp_xnp_transmit_2_register_Adr (0x001a) 777 #define IEEE_AN_BLK1_an_lp_xnp_transmit_3_register_Adr (0x001b) 778 779 /*-----------------------------------------------*/ 780 /* Defines for IEEE_AN_BLK3 Bank */ 781 /*-----------------------------------------------*/ 782 #define IEEE_AN_BLK3_BaseAdr (0x0030) 783 #define IEEE_AN_BLK3_backplane_ethernet_status_register_Adr (0x0030) 784 #define IEEE_AN_BLK3_EEE_adv_Adr (0x003c) 785 #define IEEE_AN_BLK3_EEE_lp_adv_Adr (0x003d) 786 787 /*-----------------------------------------------*/ 788 /* Defines for DEV7_SLICE Bank */ 789 /*-----------------------------------------------*/ 790 #define DEV7_SLICE_BaseAdr (0x0000) 791 #define DEV7_SLICE_slice_Adr (0x8000) 792 793 #define LINE_FALCON_IF_soft_mode0_Adr (0xa400) 794 #define LINE_FALCON_IF_c_and_r_cntl_Adr (0xa401) 795 #define LINE_FALCON_IF_soft_mode1_Adr (0xa406) 796 #define SYS_FALCON_IF_soft_mode0_Adr (0xb400) 797 #define SYS_FALCON_IF_soft_mode1_Adr (0xb406) 798 #define SYS_FALCON_IF_c_and_r_cntl_Adr (0xb401) 799 #define FUR_MISC_CTRL_furia_qsfi_misc_Adr (0x8af1) 800 #define FUR_MISC_CTRL_DEBUG_CTRL_Adr (0x8af0) 801 #define FUR_PAD_CTRL_opttxenb_control_Adr (0x8a50) 802 #define FUR_PAD_CTRL_opttxenb_status_Adr (0x8a51) 803 #define FUR_PAD_CTRL_gpio_0_control_Adr (0x8a54) 804 #define FUR_PAD_CTRL_gpio_0_status_Adr (0x8a55) 805 #define FUR_PAD_CTRL_gpio_1_control_Adr (0x8a56) 806 #define FUR_PAD_CTRL_gpio_1_status_Adr (0x8a57) 807 #define FUR_PAD_CTRL_gpio_2_control_Adr (0x8a58) 808 #define FUR_PAD_CTRL_gpio_2_status_Adr (0x8a59) 809 #define FUR_PAD_CTRL_gpio_3_control_Adr (0x8a5a) 810 #define FUR_PAD_CTRL_gpio_3_status_Adr (0x8a5b) 811 #define FUR_PAD_CTRL_gpio_4_control_Adr (0x8a5c) 812 #define FUR_PAD_CTRL_gpio_4_status_Adr (0x8a5d) 813 #define FUR_PAD_CTRL_testpad_control_Adr (0x8a5e) 814 #define FUR_PAD_CTRL_testpad_status_Adr (0x8a5f) 815 #define FUR_MISC_CTRL_general_status_IO_Adr (0x8a70) 816 #define FUR_PAD_CTRL_ext_uc_rstb_control_Adr (0x8a4a) 817 #define FUR_PAD_CTRL_mod_absent_control_Adr (0x8a4c) 818 #define FUR_PAD_CTRL_mod_absent_status_Adr (0x8a4d) 819 #define FUR_PAD_CTRL_ext_intrb_control_Adr (0x8a4e) 820 #define FUR_PAD_CTRL_ext_intrb_status_Adr (0x8a4f) 821 #define FUR_PAD_CTRL_mod_rxlos_control_Adr (0x8a52) 822 #define FUR_PAD_CTRL_mod_rxlos_status_Adr (0x8a53) 823 #define SIGDET_SIGDET_CTRL_1_Adr (0xd0e1) 824 #endif /* chip_address_defines__H */