falcon16_diagnostics.c (13374B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_diagnostics.h> 13 #include <phymod/phymod_diagnostics_dispatch.h> 14 #include <phymod/phymod_util.h> 15 #include "falcon16/tier1/src/falcon16_cfg_seq.h" 16 #include "falcon16/tier1/include/falcon16_tsc_diag.h" 17 #include "falcon16/tier1/include/falcon16_tsc_access.h" 18 #include "falcon16/tier1/include/falcon16_tsc_config.h" 19 20 21 #ifdef PHYMOD_FALCON16_SUPPORT 22 23 int falcon16_phy_rx_slicer_position_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_slicer_position_t* position) 24 { 25 26 27 /* Place your code here */ 28 29 30 return PHYMOD_E_NONE; 31 32 } 33 34 int falcon16_phy_rx_slicer_position_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_slicer_position_t* position) 35 { 36 37 38 /* Place your code here */ 39 40 41 return PHYMOD_E_NONE; 42 43 } 44 45 46 int falcon16_phy_rx_slicer_position_max_get(const phymod_phy_access_t* phy, uint32_t flags, const phymod_slicer_position_t* position_min, const phymod_slicer_position_t* position_max) 47 { 48 49 50 /* Place your code here */ 51 52 53 return PHYMOD_E_NONE; 54 55 } 56 57 58 int falcon16_phy_prbs_config_set(const phymod_phy_access_t* phy, uint32_t flags , const phymod_prbs_t* prbs) 59 { 60 61 62 /* Place your code here */ 63 64 65 return PHYMOD_E_NONE; 66 67 } 68 69 int falcon16_phy_prbs_config_get(const phymod_phy_access_t* phy, uint32_t flags , phymod_prbs_t* prbs) 70 { 71 72 73 /* Place your code here */ 74 75 76 return PHYMOD_E_NONE; 77 78 } 79 80 81 int falcon16_phy_prbs_enable_set(const phymod_phy_access_t* phy, uint32_t flags , uint32_t enable) 82 { 83 84 85 /* Place your code here */ 86 87 88 return PHYMOD_E_NONE; 89 90 } 91 92 int falcon16_phy_prbs_enable_get(const phymod_phy_access_t* phy, uint32_t flags , uint32_t* enable) 93 { 94 95 96 /* Place your code here */ 97 98 99 return PHYMOD_E_NONE; 100 101 } 102 103 104 int falcon16_phy_prbs_status_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_prbs_status_t* prbs_status) 105 { 106 107 108 /* Place your code here */ 109 110 111 return PHYMOD_E_NONE; 112 113 } 114 115 116 int falcon16_phy_pattern_config_set(const phymod_phy_access_t* phy, const phymod_pattern_t* pattern) 117 { 118 119 120 /* Place your code here */ 121 122 123 return PHYMOD_E_NONE; 124 125 } 126 127 int falcon16_phy_pattern_config_get(const phymod_phy_access_t* phy, phymod_pattern_t* pattern) 128 { 129 130 131 /* Place your code here */ 132 133 134 return PHYMOD_E_NONE; 135 136 } 137 138 139 int falcon16_phy_pattern_enable_set(const phymod_phy_access_t* phy, uint32_t enable, const phymod_pattern_t* pattern) 140 { 141 142 143 /* Place your code here */ 144 145 146 return PHYMOD_E_NONE; 147 148 } 149 150 int falcon16_phy_pattern_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 151 { 152 153 154 /* Place your code here */ 155 156 157 return PHYMOD_E_NONE; 158 159 } 160 161 162 int falcon16_core_diagnostics_get(const phymod_core_access_t* core, phymod_core_diagnostics_t* diag) 163 { 164 165 166 /* Place your code here */ 167 168 169 return PHYMOD_E_NONE; 170 171 } 172 173 174 int falcon16_phy_diagnostics_get(const phymod_phy_access_t* phy, phymod_phy_diagnostics_t* diag) 175 { 176 177 178 /* Place your code here */ 179 180 181 return PHYMOD_E_NONE; 182 183 } 184 185 186 int falcon16_phy_pmd_info_dump(const phymod_phy_access_t* phy, const char* type) 187 { 188 189 190 /* Place your code here */ 191 192 193 return PHYMOD_E_NONE; 194 195 } 196 197 198 static void _falcon16_diag_uc_reg_dump(const phymod_access_t *pa) 199 { 200 err_code_t errc; 201 202 COMPILER_REFERENCE(errc); 203 204 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 205 PHYMOD_DIAG_OUT(("| MICRO CODE USR CTRL CONFIGURATION REGISTERS |\n")); 206 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 207 PHYMOD_DIAG_OUT(("| config_word [0x00]: 0x%04X |\n", falcon16_tsc_rdwl_uc_var(pa,&errc,0x0))); 208 PHYMOD_DIAG_OUT(("| retune_after_restart [0x02]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x2))); 209 PHYMOD_DIAG_OUT(("| clk90_offset_adjust [0x03]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x3))); 210 PHYMOD_DIAG_OUT(("| clk90_offset_override [0x04]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x4))); 211 PHYMOD_DIAG_OUT(("| lane_event_log_level [0x05]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x5))); 212 PHYMOD_DIAG_OUT(("| disable_startup [0x06]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x6))); 213 PHYMOD_DIAG_OUT(("| disable_startup_dfe [0x07]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x7))); 214 PHYMOD_DIAG_OUT(("| disable_steady_state [0x08]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x8))); 215 PHYMOD_DIAG_OUT(("| disable_steady_state_dfe [0x09]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x9))); 216 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 217 PHYMOD_DIAG_OUT(("| MICRO CODE USER STATUS REGISTERS |\n")); 218 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 219 PHYMOD_DIAG_OUT(("| restart_counter [0x0A]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0xa))); 220 PHYMOD_DIAG_OUT(("| reset_counter [0x0B]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0xb))); 221 PHYMOD_DIAG_OUT(("| pmd_lock_counter [0x0C]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0xc))); 222 PHYMOD_DIAG_OUT(("| heye_left [0x0D]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0xd))); 223 PHYMOD_DIAG_OUT(("| heye_left_lsbyte [0x0E]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0xe))); 224 PHYMOD_DIAG_OUT(("| heye_right [0x0F]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0xf))); 225 PHYMOD_DIAG_OUT(("| heye_right_lsbyte [0x10]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x10))); 226 PHYMOD_DIAG_OUT(("| veye_upper [0x11]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x11))); 227 PHYMOD_DIAG_OUT(("| veye_upper_lsbyte [0x12]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x12))); 228 PHYMOD_DIAG_OUT(("| veye_lower [0x13]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x13))); 229 PHYMOD_DIAG_OUT(("| veye_lower_lsbyte [0x14]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x14))); 230 PHYMOD_DIAG_OUT(("| micro_stopped [0x15]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x15))); 231 PHYMOD_DIAG_OUT(("| link_time [0x16]: 0x%04X |\n", falcon16_tsc_rdwl_uc_var(pa,&errc,0x16))); 232 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 233 PHYMOD_DIAG_OUT(("| MICRO CODE MISC REGISTERS |\n")); 234 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 235 PHYMOD_DIAG_OUT(("| usr_diag_status [0x18]: 0x%04X |\n", falcon16_tsc_rdwl_uc_var(pa,&errc,0x18))); 236 PHYMOD_DIAG_OUT(("| usr_diag_rd_ptr [0x1A]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x1a))); 237 PHYMOD_DIAG_OUT(("| usr_diag_mode [0x1B]: 0x%04X |\n", falcon16_tsc_rdbl_uc_var(pa,&errc,0x1b))); 238 PHYMOD_DIAG_OUT(("| usr_var_msb [0x1C]: 0x%04X |\n", falcon16_tsc_rdwl_uc_var(pa,&errc,0x1c))); 239 PHYMOD_DIAG_OUT(("| usr_var_lsb [0x1E]: 0x%04X |\n", falcon16_tsc_rdwl_uc_var(pa,&errc,0x1e))); 240 PHYMOD_DIAG_OUT(("+-------------------------------------------------+\n")); 241 } 242 243 244 STATIC int falcon16_diagnostics_eyescan_run_uc(const phymod_phy_access_t* phy, uint32_t flags) 245 { 246 int ii, rc = PHYMOD_E_NONE; 247 uint32_t stripe[64]; 248 uint16_t status; 249 int j ; 250 phymod_phy_access_t phy_copy; 251 252 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 253 254 for(j=0; j< PHYMOD_CONFIG_MAX_LANES_PER_CORE; j++) { /* Loop for all lanes. */ 255 if ((phy->access.lane_mask & (1<<j))==0) continue; 256 257 phy_copy.access.lane_mask = (phy->access.lane_mask & (1<<j)); 258 259 PHYMOD_IF_ERR_RETURN 260 (falcon16_tsc_init_falcon16_tsc_info(&phy_copy.access)); 261 262 if(PHYMOD_EYESCAN_F_ENABLE_GET(flags)) { 263 PHYMOD_IF_ERR_RETURN(falcon16_tsc_meas_eye_scan_start(&(phy_copy.access), 0)); 264 265 if(!PHYMOD_EYESCAN_F_ENABLE_DONT_WAIT_GET(flags)) { 266 PHYMOD_USLEEP(100000); 267 } 268 } 269 270 if(PHYMOD_EYESCAN_F_PROCESS_GET(flags)) { 271 for (ii = 62; ii >= -62; ii=ii-2) { 272 if (ii == 62) { 273 PHYMOD_DIAG_OUT(("\n\n\n")); 274 PHYMOD_DIAG_OUT((" +--------------------------------------------------------------------+\n")); 275 PHYMOD_DIAG_OUT((" | EYESCAN Phy: 0x%03x lane_mask: 0x%02x |\n", phy_copy.access.addr, phy_copy.access.lane_mask)); 276 PHYMOD_DIAG_OUT((" +--------------------------------------------------------------------+\n")); 277 /*display eyescan header*/ 278 PHYMOD_IF_ERR_RETURN(falcon16_tsc_display_eye_scan_header(1)); 279 } 280 281 rc = falcon16_tsc_read_eye_scan_stripe(&(phy_copy.access), stripe, &status); 282 if(rc != PHYMOD_E_NONE) { 283 _falcon16_diag_uc_reg_dump(&(phy_copy.access)); 284 PHYMOD_IF_ERR_RETURN(rc); 285 } 286 PHYMOD_IF_ERR_RETURN(falcon16_tsc_display_eye_scan_stripe(&(phy_copy.access), ii, &stripe[0])); 287 288 PHYMOD_DIAG_OUT(("\n")); 289 } 290 291 if (rc == PHYMOD_E_NONE) { 292 PHYMOD_IF_ERR_RETURN(falcon16_tsc_display_eye_scan_footer(1)); 293 PHYMOD_DIAG_OUT(("\n")); 294 } 295 } 296 297 if(PHYMOD_EYESCAN_F_DONE_GET(flags)) { 298 PHYMOD_IF_ERR_RETURN(falcon16_tsc_meas_eye_scan_done(&(phy_copy.access))); 299 } 300 } 301 return PHYMOD_E_NONE; 302 } 303 304 int falcon16_diagnostics_eye_margin_proj( const phymod_phy_access_t* phy, uint32_t flags, 305 const phymod_phy_eyescan_options_t* eyescan_options) 306 { 307 #ifdef SERDES_API_FLOATING_POINT 308 int osr_mode; 309 USR_DOUBLE data_rate, data_rate_in_Mhz; 310 phymod_phy_access_t phy_copy; 311 int start_lane, num_lane, i, found=0; 312 313 struct falcon16_tsc_uc_core_config_st core_cfg; 314 if(PHYMOD_EYESCAN_F_PROCESS_GET(flags)) { 315 PHYMOD_IF_ERR_RETURN 316 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 317 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 318 for (i = 0; i < num_lane; i++) { 319 phy_copy.access.lane_mask = 1 << (start_lane + i); 320 321 if (found == 0) { 322 PHYMOD_IF_ERR_RETURN(falcon16_tsc_get_uc_core_config (&(phy_copy.access), &core_cfg)); 323 PHYMOD_IF_ERR_RETURN(falcon16_osr_mode_get(&phy_copy.access, &osr_mode)); 324 data_rate = (core_cfg.vco_rate_in_Mhz * 1000.0 * 1000.0) / (1<<osr_mode); 325 data_rate_in_Mhz = (core_cfg.vco_rate_in_Mhz) / (1<<osr_mode); 326 found = 1; 327 } 328 if(num_lane > 1) { 329 PHYMOD_DIAG_OUT((" l=%0d, data rate = %fMHz\n", i, data_rate_in_Mhz)); 330 } else { 331 PHYMOD_DIAG_OUT((" data rate = %fMHz\n", data_rate_in_Mhz)); 332 } 333 falcon16_tsc_eye_margin_proj(&phy_copy.access, data_rate, eyescan_options->ber_proj_scan_mode, 334 eyescan_options->ber_proj_timer_cnt, eyescan_options->ber_proj_err_cnt); 335 } 336 } 337 #else 338 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("BER Proj is supported with SERDES_API_FLOATING_POINT only\n"))); 339 #endif 340 return PHYMOD_E_NONE; 341 } 342 343 int falcon16_phy_eyescan_run(const phymod_phy_access_t* phy, uint32_t flags, phymod_eyescan_mode_t mode, const phymod_phy_eyescan_options_t* eyescan_options) 344 { 345 uint8_t pmd_rx_lock=0; 346 347 PHYMOD_IF_ERR_RETURN 348 (falcon16_tsc_pmd_lock_status(&phy->access, &pmd_rx_lock)); 349 350 if(pmd_rx_lock == 0) { 351 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("Can not get eyescan when pmd_rx is not locked\n"))); 352 } 353 354 /* If stage isn't set - perform all stages*/ 355 if(!PHYMOD_EYESCAN_F_ENABLE_GET(flags) 356 && !PHYMOD_EYESCAN_F_PROCESS_GET(flags) 357 && !PHYMOD_EYESCAN_F_DONE_GET(flags)) 358 { 359 PHYMOD_EYESCAN_F_ENABLE_SET(flags); 360 PHYMOD_EYESCAN_F_PROCESS_SET(flags); 361 PHYMOD_EYESCAN_F_DONE_SET(flags); 362 } 363 364 /* mode phymodEyescanModeBERProj gives BER projection */ 365 switch(mode) { 366 case phymodEyescanModeFast: 367 return falcon16_diagnostics_eyescan_run_uc(phy, flags); 368 case phymodEyescanModeBERProj: 369 return falcon16_diagnostics_eye_margin_proj(phy, flags, eyescan_options); 370 default: 371 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("unsupported eyescan mode %u"), mode)); 372 } 373 374 return PHYMOD_E_NONE; 375 376 } 377 378 379 #endif /* PHYMOD_FALCON16_SUPPORT */