openbcm

Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
git clone git://git.finwo.net/mirror/broadcom/openbcm
Log | Files | Refs | README

falcon_cfg_seq.h (8125B)


      1 /*----------------------------------------------------------------------
      2  *  
      3  *
      4  * Broadcom Corporation
      5  * Proprietary and Confidential information
      6  * All rights reserved
      7  * This source file is the property of Broadcom Corporation, and
      8  * may not be copied or distributed in any isomorphic form without the
      9  * prior written consent of Broadcom Corporation.
     10  *---------------------------------------------------------------------
     11  * File       : falcon_cfg_seq.h
     12  * Description: c functions implementing Tier1s for TEMod Serdes Driver
     13  *---------------------------------------------------------------------*/
     14 /*
     15  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
     16  * 
     17  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
     18  * 
     19 */
     20 
     21 
     22 #ifndef FALCON_CFG_SEQ_H 
     23 #define FALCON_CFG_SEQ_H
     24 
     25 #include "common/srds_api_err_code.h"
     26 #include "falcon_tsc_enum.h"
     27 
     28 typedef struct {
     29   int8_t pll_pwrdn;
     30   int8_t tx_s_pwrdn;
     31   int8_t rx_s_pwrdn;
     32 } power_status_t;
     33 
     34 typedef struct {
     35   int8_t revid_model;
     36   int8_t revid_process;
     37   int8_t revid_bonding;
     38   int8_t revid_rev_number;
     39   int8_t revid_rev_letter;
     40 } falcon_rev_id0_t;
     41 
     42 typedef struct {
     43   int8_t revid_eee;
     44   int8_t revid_llp; 
     45   int8_t revid_pir; 
     46   int8_t revid_cl72; 
     47   int8_t revid_micro; 
     48   int8_t revid_mdio; 
     49   int8_t revid_multiplicity;
     50 } falcon_rev_id1_t;
     51 
     52 typedef enum {
     53   TX = 0,
     54   Rx
     55 } tx_rx_t;
     56 
     57 typedef enum {
     58     FALCON_PRBS_POLYNOMIAL_7 = 0,
     59     FALCON_PRBS_POLYNOMIAL_9,
     60     FALCON_PRBS_POLYNOMIAL_11,
     61     FALCON_PRBS_POLYNOMIAL_15,
     62     FALCON_PRBS_POLYNOMIAL_23,
     63     FALCON_PRBS_POLYNOMIAL_31,
     64     FALCON_PRBS_POLYNOMIAL_58,
     65     FALCON_PRBS_POLYNOMIAL_TYPE_COUNT 
     66 }falcon_prbs_polynomial_type_t;
     67 
     68 #define PATTERN_MAX_SIZE 8
     69 
     70 extern err_code_t _falcon_pmd_mwr_reg_byte( const phymod_access_t *pa, uint16_t addr, uint16_t mask, uint8_t lsb, uint8_t val);
     71 extern uint8_t _falcon_pmd_rde_field_byte( const phymod_access_t *pa, uint16_t addr, uint8_t shift_left, uint8_t shift_right, err_code_t *err_code_p);
     72 extern uint16_t _falcon_pmd_rde_field( const phymod_access_t *pa, uint16_t addr, uint8_t shift_left, uint8_t shift_right, err_code_t *err_code_p);
     73 err_code_t falcon_tx_pi_control_get(const phymod_access_t *pa,  int16_t *value);
     74 
     75 err_code_t falcon_tx_rx_polarity_set(const phymod_access_t *pa, uint32_t tx_pol, uint32_t rx_pol);
     76 err_code_t falcon_tx_rx_polarity_get(const phymod_access_t *pa, uint32_t *tx_pol, uint32_t *rx_pol);
     77 err_code_t falcon_uc_active_set(const phymod_access_t *pa, uint32_t enable);
     78 err_code_t falcon_uc_active_get(const phymod_access_t *pa, uint32_t *enable);
     79 /* int falcon_uc_reset(const phymod_access_t *pa, uint32_t enable); */
     80 err_code_t falcon_prbs_tx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data);
     81 err_code_t falcon_prbs_rx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data);
     82 err_code_t falcon_prbs_tx_poly_get(const phymod_access_t *pa, falcon_prbs_polynomial_type_t *prbs_poly);
     83 err_code_t falcon_prbs_rx_poly_get(const phymod_access_t *pa, falcon_prbs_polynomial_type_t *prbs_poly);
     84 err_code_t falcon_prbs_tx_enable_get(const phymod_access_t *pa, uint32_t *enable);
     85 err_code_t falcon_prbs_rx_enable_get(const phymod_access_t *pa, uint32_t *enable);
     86 err_code_t falcon_pmd_force_signal_detect(const phymod_access_t *pa, uint32_t enable);
     87 err_code_t falcon_pll_mode_set(const phymod_access_t *pa, int pll_mode);
     88 err_code_t falcon_pll_mode_get(const phymod_access_t *pa, uint32_t *pll_mode);
     89 err_code_t falcon_afe_pll_reg_set(const phymod_access_t *pa, const phymod_afe_pll_t *afe_pll);
     90 err_code_t falcon_afe_pll_reg_get(const phymod_access_t *pa, phymod_afe_pll_t *afe_pll);
     91 err_code_t falcon_osr_mode_set(const phymod_access_t *pa, int osr_mode);
     92 err_code_t falcon_osr_mode_get(const phymod_access_t *pa, int *osr_mode);
     93 err_code_t falcon_tsc_dig_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk);
     94 err_code_t falcon_tsc_rmt_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk);
     95 err_code_t falcon_core_soft_reset(const phymod_access_t *pa);
     96 err_code_t falcon_core_soft_reset_release(const phymod_access_t *pa, uint32_t enable);
     97 err_code_t falcon_core_soft_reset_read(const phymod_access_t *pa, uint32_t *enable);
     98 err_code_t falcon_lane_soft_reset_read(const phymod_access_t *pa, uint32_t *enable);
     99 err_code_t falcon_pmd_tx_disable_pin_dis_set(const phymod_access_t *pa, uint32_t enable);
    100 err_code_t falcon_pmd_tx_disable_pin_dis_get(const phymod_access_t *pa, uint32_t *enable);
    101 err_code_t falcon_tsc_pwrdn_set(const phymod_access_t *pa, int tx_rx, int pwrdn);
    102 err_code_t falcon_tsc_pwrdn_get(const phymod_access_t *pa, power_status_t *pwrdn);
    103 err_code_t falcon_pcs_lane_swap_tx(const phymod_access_t *pa, uint32_t tx_lane_map);
    104 err_code_t falcon_pmd_lane_swap (const phymod_access_t *pa, uint32_t lane_map);
    105 err_code_t falcon_pmd_lane_swap_tx_get(const phymod_access_t *pa, uint32_t *lane_map);
    106 err_code_t falcon_pmd_loopback_get(const phymod_access_t *pa, uint32_t *enable);   
    107 err_code_t falcon_tsc_identify(const phymod_access_t *pa, falcon_rev_id0_t *rev_id0, falcon_rev_id1_t *rev_id1);
    108 err_code_t falcon_pmd_ln_h_rstb_pkill_override( const phymod_access_t *pa, uint16_t val); 
    109 err_code_t falcon_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable);   /* pmd core soft reset */
    110 err_code_t falcon_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable);
    111 err_code_t falcon_rx_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable);
    112 err_code_t falcon_rx_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable);
    113 err_code_t falcon_tx_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable);
    114 err_code_t falcon_tx_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable);
    115 err_code_t falcon_lane_hard_soft_reset_release(const phymod_access_t *pa, uint32_t enable);
    116 err_code_t falcon_clause72_control(const phymod_access_t *pc, uint32_t cl_72_en);        /* CLAUSE_72_CONTROL */
    117 err_code_t falcon_clause72_control_get(const phymod_access_t *pc, uint32_t *cl_72_en);   /* CLAUSE_72_CONTROL */
    118 err_code_t falcon_pmd_cl72_enable_get(const phymod_access_t *pa, uint32_t *enable);
    119 err_code_t falcon_pmd_cl72_receiver_status(const phymod_access_t *pa, uint32_t *status); 
    120 err_code_t falcon_tsc_ucode_init( const phymod_access_t *pa );
    121 err_code_t falcon_pram_firmware_enable(const phymod_access_t *pa, int enable, int wait);  
    122 err_code_t falcon_pmd_reset_seq(const phymod_access_t *pa, int pmd_touched);
    123 err_code_t falcon_pll_reset_enable_set(const phymod_access_t *pa, int enable);
    124 err_code_t falcon_tsc_read_pll_range(const phymod_access_t *pa, uint32_t *pll_range);
    125 err_code_t falcon_tsc_signal_detect (const phymod_access_t *pa, uint32_t *signal_detect);
    126 err_code_t falcon_rx_squelch_set(const phymod_access_t *pa, uint32_t enable);
    127 err_code_t falcon_rx_squelch_get(const phymod_access_t *pa, uint32_t *val);
    128 err_code_t falcon_force_tx_set_rst (const phymod_access_t *pa, uint32_t rst);
    129 err_code_t falcon_force_tx_get_rst (const phymod_access_t *pa, uint32_t *rst);
    130 err_code_t falcon_force_rx_set_rst (const phymod_access_t *pa, uint32_t rst);
    131 err_code_t falcon_force_rx_get_rst (const phymod_access_t *pa, uint32_t *rst);
    132 err_code_t falcon_tsc_ladder_setting_to_mV(const phymod_access_t *pa, int8_t y, int16_t* level);
    133 err_code_t falcon_electrical_idle_set(const phymod_access_t *pa, uint32_t en);
    134 err_code_t falcon_tsc_get_vco (const phymod_phy_inf_config_t* config, uint32_t *vco_rate, uint32_t *new_pll_div, int16_t *new_os_mode);
    135 err_code_t falcon_tsc_tx_shared_patt_gen_en_get( const phymod_access_t *pa, uint8_t *enable);
    136 err_code_t falcon_tsc_config_shared_tx_pattern_idx_set( const phymod_access_t *pa, const uint32_t *pattern_len);
    137 err_code_t falcon_tsc_config_shared_tx_pattern_idx_get( const phymod_access_t *pa, uint32_t *pattern_len, uint32_t *pattern);
    138 err_code_t falcon_tsc_tx_disable_get (const phymod_access_t *pa, uint8_t *enable);
    139 err_code_t falcon_refclk_set(const phymod_access_t *pa, phymod_ref_clk_t ref_clock);
    140 err_code_t falcon_tsc_rx_ppm(const phymod_access_t *pa, int16_t *rx_ppm);
    141 #endif /* PHY_TSC_IBLK_H */