falcon_cfg_seq.c (33305B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 8 /* 9 * 10 * 11 * 12 * This program is the proprietary software of Broadcom Corporation 13 * and/or its licensors, and may only be used, duplicated, modified 14 * or distributed pursuant to the terms and conditions of a separate, 15 * written license agreement executed between you and Broadcom 16 * (an "Authorized License"). Except as set forth in an Authorized 17 * License, Broadcom grants no license (express or implied), right 18 * to use, or waiver of any kind with respect to the Software, and 19 * Broadcom expressly reserves all rights in and to the Software 20 * and all intellectual property rights therein. IF YOU HAVE 21 * NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE 22 * IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE 23 * ALL USE OF THE SOFTWARE. 24 * 25 * Except as expressly set forth in the Authorized License, 26 * 27 * 1. This program, including its structure, sequence and organization, 28 * constitutes the valuable trade secrets of Broadcom, and you shall use 29 * all reasonable efforts to protect the confidentiality thereof, 30 * and to use this information only in connection with your use of 31 * Broadcom integrated circuit products. 32 * 33 * 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS 34 * PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, 35 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, 36 * OR OTHERWISE, WITH RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY 37 * DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY, 38 * NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, 39 * ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 40 * CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING 41 * OUT OF USE OR PERFORMANCE OF THE SOFTWARE. 42 * 43 * 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL 44 * BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, 45 * INCIDENTAL, SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER 46 * ARISING OUT OF OR IN ANY WAY RELATING TO YOUR USE OF OR INABILITY 47 * TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF THE 48 * POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF 49 * THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR USD 1.00, 50 * WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING 51 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$ 52 */ 53 54 55 #include <phymod/phymod.h> 56 #include "falcon_cfg_seq.h" 57 #include "falcon_tsc_fields.h" 58 #include "falcon_tsc_field_access.h" 59 #include <phymod/chip/bcmi_tscf_xgxs_defs.h> 60 #include "falcon_tsc_dependencies.h" 61 #include "falcon_tsc_interface.h" 62 63 64 err_code_t falcon_tx_rx_polarity_set(const phymod_access_t *pa, uint32_t tx_pol, uint32_t rx_pol) 65 { 66 err_code_t __err; 67 __err=ERR_CODE_NONE; 68 __err = (uint32_t) wr_tx_pmd_dp_invert(tx_pol); 69 if(__err) return(__err); 70 __err = (uint32_t) wr_rx_pmd_dp_invert(rx_pol); 71 if(__err) return(__err); 72 73 return ERR_CODE_NONE; 74 } 75 76 err_code_t falcon_tx_rx_polarity_get(const phymod_access_t *pa, uint32_t *tx_pol, uint32_t *rx_pol) 77 { 78 err_code_t __err; 79 __err=ERR_CODE_NONE; 80 *tx_pol = (uint32_t) rd_tx_pmd_dp_invert(); 81 if(__err) return(__err); 82 *rx_pol = (uint32_t) rd_rx_pmd_dp_invert(); 83 if(__err) return(__err); 84 85 return ERR_CODE_NONE; 86 } 87 88 err_code_t falcon_uc_active_set(const phymod_access_t *pa, uint32_t enable) 89 { 90 err_code_t __err; 91 __err=ERR_CODE_NONE; 92 __err=wrc_uc_active(enable); 93 if(__err) return(__err); 94 95 return ERR_CODE_NONE; 96 } 97 98 err_code_t falcon_uc_active_get(const phymod_access_t *pa, uint32_t *enable) 99 { 100 err_code_t __err; 101 __err=ERR_CODE_NONE; 102 *enable = (uint32_t) rdc_uc_active(); 103 if(__err) return(__err); 104 return ERR_CODE_NONE; 105 } 106 107 108 /* 109 err_code_t falcon_uc_reset(const phymod_access_t *pa, uint32_t enable) 110 { 111 return ERR_CODE_NONE; 112 } 113 */ 114 115 err_code_t falcon_force_tx_set_rst (const phymod_access_t *pa, uint32_t rst) 116 { 117 /* coverity[check_return] */ 118 wr_afe_tx_reset_frc_val(rst); 119 /* coverity[check_return] */ 120 wr_afe_tx_reset_frc(0x1); 121 return ERR_CODE_NONE; 122 } 123 124 err_code_t falcon_force_tx_get_rst (const phymod_access_t *pa, uint32_t *rst) 125 { 126 err_code_t __err; 127 __err=ERR_CODE_NONE; 128 *rst=(uint32_t) rd_afe_tx_reset_frc_val(); 129 return ERR_CODE_NONE; 130 } 131 132 err_code_t falcon_force_rx_set_rst (const phymod_access_t *pa, uint32_t rst) 133 { 134 /* coverity[check_return] */ 135 wr_afe_rx_reset_frc_val(rst); 136 /* coverity[check_return] */ 137 wr_afe_rx_reset_frc(0x1); 138 return ERR_CODE_NONE; 139 } 140 141 err_code_t falcon_force_rx_get_rst (const phymod_access_t *pa, uint32_t *rst) 142 { 143 err_code_t __err; 144 __err=ERR_CODE_NONE; 145 *rst=(uint32_t) rd_afe_rx_reset_frc_val(); 146 return ERR_CODE_NONE; 147 } 148 149 err_code_t falcon_prbs_tx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data) 150 { 151 err_code_t __err; 152 __err=ERR_CODE_NONE; 153 *inv_data = (uint32_t) rd_prbs_gen_inv(); 154 if(__err) return(__err); 155 156 return ERR_CODE_NONE; 157 } 158 159 err_code_t falcon_prbs_rx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data) 160 { 161 err_code_t __err; 162 __err=ERR_CODE_NONE; 163 *inv_data = (uint32_t) rd_prbs_gen_inv(); 164 if(__err) return(__err); 165 166 return ERR_CODE_NONE; 167 } 168 169 err_code_t falcon_prbs_tx_poly_get(const phymod_access_t *pa, falcon_prbs_polynomial_type_t *prbs_poly) 170 { 171 err_code_t __err; 172 __err=ERR_CODE_NONE; 173 *prbs_poly = rd_prbs_gen_mode_sel(); 174 if(__err) return(__err); 175 176 return ERR_CODE_NONE; 177 } 178 179 err_code_t falcon_prbs_rx_poly_get(const phymod_access_t *pa, falcon_prbs_polynomial_type_t *prbs_poly) 180 { 181 err_code_t __err; 182 __err=ERR_CODE_NONE; 183 *prbs_poly = rd_prbs_gen_mode_sel(); 184 if(__err) return(__err); 185 186 return ERR_CODE_NONE; 187 } 188 189 err_code_t falcon_prbs_tx_enable_get(const phymod_access_t *pa, uint32_t *enable) 190 { 191 err_code_t __err; 192 uint8_t val = 0; 193 194 __err=ERR_CODE_NONE; 195 __err = falcon_tsc_get_tx_prbs_en(pa, &val); 196 if(__err) return(__err); 197 *enable = val; 198 199 return ERR_CODE_NONE; 200 } 201 202 err_code_t falcon_prbs_rx_enable_get(const phymod_access_t *pa, uint32_t *enable) 203 { 204 err_code_t __err; 205 uint8_t val = 0; 206 207 __err=ERR_CODE_NONE; 208 __err = falcon_tsc_get_rx_prbs_en(pa, &val); 209 if(__err) return(__err); 210 *enable = val; 211 212 return ERR_CODE_NONE; 213 } 214 215 err_code_t falcon_pmd_force_signal_detect(const phymod_access_t *pa, uint32_t enable) 216 { 217 err_code_t __err; 218 __err=ERR_CODE_NONE; 219 __err = wr_signal_detect_frc(enable); if(__err) return(__err); 220 __err = wr_signal_detect_frc_val(enable); if(__err) return(__err); 221 222 return ERR_CODE_NONE; 223 } 224 225 err_code_t falcon_rx_squelch_set(const phymod_access_t *pa, uint32_t enable) 226 { 227 err_code_t __err; 228 __err=ERR_CODE_NONE; 229 if (enable) { 230 __err = wr_signal_detect_frc(1); if(__err) return(__err); 231 __err = wr_signal_detect_frc_val(0); if(__err) return(__err); 232 } else { 233 __err = wr_signal_detect_frc(0); if(__err) return(__err); 234 __err = wr_signal_detect_frc_val(0); if(__err) return(__err); 235 } 236 237 return ERR_CODE_NONE; 238 } 239 240 err_code_t falcon_rx_squelch_get(const phymod_access_t *pa, uint32_t *val) 241 { 242 err_code_t __err; 243 __err=ERR_CODE_NONE; 244 *val = rd_signal_detect_frc(); 245 if(__err) return(__err); 246 247 return ERR_CODE_NONE; 248 } 249 250 err_code_t falcon_pll_mode_set(const phymod_access_t *pa, int pll_mode) 251 { 252 err_code_t __err; 253 __err=ERR_CODE_NONE; 254 __err=wrc_pll_mode(pll_mode); 255 if(__err) return(__err); 256 257 return ERR_CODE_NONE; 258 } 259 260 err_code_t falcon_pll_mode_get(const phymod_access_t *pa, uint32_t *pll_mode) 261 { 262 err_code_t __err; 263 __err=ERR_CODE_NONE; 264 *pll_mode=rdc_pll_mode(); 265 if(__err) return(__err); 266 267 return ERR_CODE_NONE; 268 } 269 270 err_code_t falcon_afe_pll_reg_set(const phymod_access_t *pa, const phymod_afe_pll_t *afe_pll) 271 { 272 err_code_t __err; 273 __err=ERR_CODE_NONE; 274 if(afe_pll->afe_pll_change_default) { 275 __err=wrc_ams_pll_iqp(afe_pll->ams_pll_iqp); 276 if(__err) return(__err); 277 __err=wrc_ams_pll_en_hrz(afe_pll->ams_pll_en_hrz); 278 if(__err) return(__err); 279 } else { 280 __err=wrc_ams_pll_iqp(0x5); 281 if(__err) return(__err); 282 } 283 284 return ERR_CODE_NONE; 285 } 286 287 err_code_t falcon_afe_pll_reg_get(const phymod_access_t *pa, phymod_afe_pll_t *afe_pll) 288 { 289 err_code_t __err; 290 __err=ERR_CODE_NONE; 291 afe_pll->ams_pll_iqp=rdc_ams_pll_iqp(); 292 if(__err) return(__err); 293 afe_pll->ams_pll_en_hrz=rdc_ams_pll_en_hrz(); 294 if(__err) return(__err); 295 296 return ERR_CODE_NONE; 297 } 298 299 300 err_code_t falcon_osr_mode_set(const phymod_access_t *pa, int osr_mode) 301 { 302 err_code_t __err; 303 __err=ERR_CODE_NONE; 304 __err=wr_osr_mode_frc_val(osr_mode); 305 if(__err) return(__err); 306 __err=wr_osr_mode_frc(1); 307 if(__err) return(__err); 308 309 return ERR_CODE_NONE; 310 } 311 312 err_code_t falcon_osr_mode_get(const phymod_access_t *pa, int *osr_mode) 313 { 314 int osr_forced; 315 err_code_t __err; 316 __err=ERR_CODE_NONE; 317 osr_forced = rd_osr_mode_frc(); 318 if(osr_forced) { 319 *osr_mode = rd_osr_mode_frc_val(); 320 if(__err) return(__err); 321 } else { 322 *osr_mode = rd_osr_mode_pin(); 323 if(__err) return(__err); 324 } 325 326 return ERR_CODE_NONE; 327 } 328 329 err_code_t falcon_tsc_dig_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk) 330 { 331 err_code_t __err; 332 __err=ERR_CODE_NONE; 333 *lpbk=rd_dig_lpbk_en(); 334 if(__err) return(__err); 335 336 return ERR_CODE_NONE; 337 } 338 339 err_code_t falcon_tsc_rmt_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk) 340 { 341 err_code_t __err; 342 __err=ERR_CODE_NONE; 343 *lpbk=rd_rmt_lpbk_en(); 344 if(__err) return(__err); 345 346 return ERR_CODE_NONE; 347 } 348 349 err_code_t falcon_core_soft_reset(const phymod_access_t *pa) 350 { 351 err_code_t __err; 352 __err=ERR_CODE_NONE; 353 __err=wrc_core_dp_s_rstb(1); 354 if(__err) return(__err); 355 356 return ERR_CODE_NONE; 357 } 358 359 err_code_t falcon_core_soft_reset_release(const phymod_access_t *pa, uint32_t enable) 360 { 361 err_code_t __err; 362 __err=ERR_CODE_NONE; 363 __err=wrc_core_dp_s_rstb(enable); 364 if(__err) return(__err); 365 366 return ERR_CODE_NONE; 367 } 368 369 err_code_t falcon_core_soft_reset_read(const phymod_access_t *pa, uint32_t *enable) 370 { 371 err_code_t __err; 372 __err=ERR_CODE_NONE; 373 *enable = rdc_core_dp_s_rstb(); if(__err) return(__err); 374 375 return ERR_CODE_NONE; 376 } 377 378 err_code_t falcon_lane_soft_reset_read(const phymod_access_t *pa, uint32_t *enable) 379 { 380 err_code_t __err; 381 __err=ERR_CODE_NONE; 382 *enable = rd_ln_dp_s_rstb(); if(__err) return(__err); 383 384 return ERR_CODE_NONE; 385 } 386 387 err_code_t falcon_pmd_tx_disable_pin_dis_set(const phymod_access_t *pa, uint32_t enable) { 388 err_code_t __err; 389 __err=ERR_CODE_NONE; 390 __err=wr_pmd_tx_disable_pkill(enable); if(__err) return(__err); 391 392 return ERR_CODE_NONE; 393 } 394 395 err_code_t falcon_pmd_tx_disable_pin_dis_get(const phymod_access_t *pa, uint32_t *enable) { 396 err_code_t __err; 397 __err=ERR_CODE_NONE; 398 *enable = rd_pmd_tx_disable_pkill(); if(__err) return(__err); 399 400 return ERR_CODE_NONE; 401 } 402 403 /* set powerdown for tx or rx */ 404 /* tx_rx == 1 => disable (enable) power for Tx */ 405 /* tx_rx != 0 => disable (enable) power for Rx */ 406 /* pwrdn == 0 => enable power */ 407 /* pwrdn == 1 => disable power */ 408 err_code_t falcon_tsc_pwrdn_set(const phymod_access_t *pa, int tx_rx, int pwrdn) 409 { 410 err_code_t __err; 411 __err=ERR_CODE_NONE; 412 if(tx_rx) { 413 __err = (uint32_t) wr_ln_tx_s_pwrdn(pwrdn); 414 } else { 415 __err = (uint32_t) wr_ln_rx_s_pwrdn(pwrdn); 416 } 417 if(__err) return(__err); 418 419 return ERR_CODE_NONE; 420 } 421 422 err_code_t falcon_tsc_pwrdn_get(const phymod_access_t *pa, power_status_t *pwrdn) 423 { 424 err_code_t __err; 425 __err=ERR_CODE_NONE; 426 pwrdn->pll_pwrdn = 0; 427 pwrdn->tx_s_pwrdn = 0; 428 pwrdn->rx_s_pwrdn = 0; 429 pwrdn->pll_pwrdn = rdc_afe_s_pll_pwrdn(); if(__err) return(__err); 430 pwrdn->tx_s_pwrdn = rd_ln_tx_s_pwrdn(); if(__err) return(__err); 431 pwrdn->rx_s_pwrdn = rd_ln_rx_s_pwrdn(); if(__err) return(__err); 432 433 return ERR_CODE_NONE; 434 } 435 436 err_code_t falcon_pcs_lane_swap_tx(const phymod_access_t *pa, uint32_t tx_lane_map) { 437 err_code_t __err; 438 uint32_t lane_addr_0, lane_addr_1, lane_addr_2, lane_addr_3; 439 440 __err=ERR_CODE_NONE; 441 lane_addr_0 = (tx_lane_map >> 16) & 0xf; 442 lane_addr_1 = (tx_lane_map >> 20) & 0xf; 443 lane_addr_2 = (tx_lane_map >> 24) & 0xf; 444 lane_addr_3 = (tx_lane_map >> 28) & 0xf; 445 446 __err=wrc_lane_addr_0(lane_addr_0); if(__err) return(__err); 447 __err=wrc_lane_addr_1(lane_addr_1); if(__err) return(__err); 448 __err=wrc_lane_addr_2(lane_addr_2); if(__err) return(__err); 449 __err=wrc_lane_addr_3(lane_addr_3); if(__err) return(__err); 450 451 return ERR_CODE_NONE; 452 } 453 454 err_code_t falcon_pmd_loopback_get(const phymod_access_t *pa, uint32_t *enable) 455 { 456 err_code_t __err; 457 __err=ERR_CODE_NONE; 458 *enable = rd_dig_lpbk_en(); if(__err) return(__err); 459 return ERR_CODE_NONE; 460 } 461 462 err_code_t falcon_pmd_cl72_enable_get(const phymod_access_t *pa, uint32_t *enable) 463 { 464 err_code_t __err; 465 __err=ERR_CODE_NONE; 466 *enable = rd_cl93n72_ieee_training_enable(); if(__err) return(__err); 467 return ERR_CODE_NONE; 468 } 469 470 err_code_t falcon_pmd_cl72_receiver_status(const phymod_access_t *pa, uint32_t *status) 471 { 472 err_code_t __err; 473 __err=ERR_CODE_NONE; 474 *status = rd_cl93n72_ieee_receiver_status(); if(__err) return(__err); 475 return ERR_CODE_NONE; 476 } 477 478 err_code_t falcon_pram_firmware_enable(const phymod_access_t *pa, int enable, int wait) /* release the pmd core soft reset */ 479 { 480 err_code_t __err; 481 482 __err=ERR_CODE_NONE; 483 if(enable == 1) { 484 __err=wrc_micro_pramif_ahb_wraddr_msw(0); if(__err) return(__err); 485 __err=wrc_micro_pramif_ahb_wraddr_lsw(0); if(__err) return(__err); 486 487 __err=wrc_micro_pram_if_rstb(1); if(__err) return(__err); 488 __err=wrc_micro_pramif_en(1); if(__err) return(__err); 489 490 if(wait) { 491 /* coverity[check_return] */ 492 falcon_tsc_delay_us(500); 493 } 494 } else { 495 __err=wrc_micro_pramif_en(0); if(__err) return(__err); 496 __err=wrc_micro_core_clk_en(1); if(__err) return(__err); 497 498 } 499 return ERR_CODE_NONE; 500 } 501 502 503 err_code_t falcon_pmd_lane_swap (const phymod_access_t *pa, uint32_t lane_map) { 504 err_code_t __err; 505 uint32_t lane_0, lane_1, lane_2, lane_3; 506 507 __err=ERR_CODE_NONE; 508 lane_0 = ((lane_map >> 0) & 0x3); 509 lane_1 = ((lane_map >> 4) & 0x3); 510 lane_2 = ((lane_map >> 8) & 0x3); 511 lane_3 = ((lane_map >> 12) & 0x3); 512 513 __err=wrc_tx_lane_map_0(lane_0); if(__err) return(__err); 514 __err=wrc_tx_lane_map_1(lane_1); if(__err) return(__err); 515 __err=wrc_tx_lane_map_2(lane_2); if(__err) return(__err); 516 __err=wrc_tx_lane_map_3(lane_3); if(__err) return(__err); 517 518 return ERR_CODE_NONE; 519 } 520 521 err_code_t falcon_pmd_lane_swap_tx_get (const phymod_access_t *pa, uint32_t *lane_map) { 522 err_code_t __err; 523 uint32_t lane_0, lane_1, lane_2, lane_3; 524 525 __err=ERR_CODE_NONE; 526 527 lane_0=rdc_tx_lane_map_0(); if(__err) return(__err); 528 lane_1=rdc_tx_lane_map_1(); if(__err) return(__err); 529 lane_2=rdc_tx_lane_map_2(); if(__err) return(__err); 530 lane_3=rdc_tx_lane_map_3(); if(__err) return(__err); 531 532 *lane_map = ((lane_3 & 0x3) <<12)|((lane_2 & 0x3) <<8)|((lane_1 & 0x3) <<4)|((lane_0 & 0x3) <<0); 533 534 return ERR_CODE_NONE; 535 } 536 537 err_code_t falcon_tx_pi_control_get(const phymod_access_t *pa, int16_t* value) 538 { 539 err_code_t __err; 540 uint32_t enable; 541 542 __err=ERR_CODE_NONE; 543 544 enable=rdc_tx_pi_en(); if(__err) return(__err); 545 if (enable) { 546 *value=rdc_tx_pi_freq_override_val(); if(__err) return(__err); 547 } else { 548 *value=0; 549 } 550 551 return ERR_CODE_NONE; 552 } 553 554 err_code_t falcon_tsc_identify(const phymod_access_t *pa, falcon_rev_id0_t *rev_id0, falcon_rev_id1_t *rev_id1) 555 { 556 err_code_t __err; 557 558 rev_id0->revid_rev_letter =0; 559 rev_id0->revid_rev_number =0; 560 rev_id0->revid_bonding =0; 561 rev_id0->revid_process =0; 562 rev_id0->revid_model =0; 563 564 rev_id1->revid_multiplicity =0; 565 rev_id1->revid_mdio =0; 566 rev_id1->revid_micro =0; 567 rev_id1->revid_cl72 =0; 568 rev_id1->revid_pir =0; 569 rev_id1->revid_llp =0; 570 rev_id1->revid_eee =0; 571 572 __err=ERR_CODE_NONE; 573 574 rev_id0->revid_rev_letter =rdc_revid_rev_letter(); if(__err) return(__err); 575 rev_id0->revid_rev_number =rdc_revid_rev_number(); if(__err) return(__err); 576 rev_id0->revid_bonding =rdc_revid_bonding(); if(__err) return(__err); 577 rev_id0->revid_process =rdc_revid_process(); if(__err) return(__err); 578 rev_id0->revid_model =rdc_revid_model(); if(__err) return(__err); 579 580 rev_id1->revid_multiplicity =rdc_revid_multiplicity(); if(__err) return(__err); 581 rev_id1->revid_mdio =rdc_revid_mdio(); if(__err) return(__err); 582 rev_id1->revid_micro =rdc_revid_micro(); if(__err) return(__err); 583 rev_id1->revid_cl72 =rdc_revid_cl72(); if(__err) return(__err); 584 rev_id1->revid_pir =rdc_revid_pir(); if(__err) return(__err); 585 rev_id1->revid_llp =rdc_revid_llp(); if(__err) return(__err); 586 rev_id1->revid_eee =rdc_revid_eee(); if(__err) return(__err); 587 588 return ERR_CODE_NONE; 589 } 590 591 err_code_t falcon_pmd_ln_h_rstb_pkill_override( const phymod_access_t *pa, uint16_t val) 592 { 593 err_code_t __err; 594 /* 595 * Work around per Magesh/Justin 596 * override input from PCS to allow uc_dsc_ready_for_cmd 597 * reg get written by UC 598 */ 599 __err=ERR_CODE_NONE; 600 __err=wr_pmd_ln_h_rstb_pkill(val); if(__err) return(__err); 601 return ERR_CODE_NONE; 602 } 603 604 err_code_t falcon_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 605 { 606 err_code_t __err; 607 __err=ERR_CODE_NONE; 608 __err=wr_ln_dp_s_rstb(enable); if(__err) return(__err); 609 610 return ERR_CODE_NONE; 611 } 612 613 err_code_t falcon_rx_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the rx lane soft reset */ 614 { 615 err_code_t __err; 616 __err=ERR_CODE_NONE; 617 __err=wr_ln_rx_dp_s_rstb(enable); if(__err) return(__err); 618 619 return ERR_CODE_NONE; 620 } 621 622 err_code_t falcon_tx_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd tx lane reset */ 623 { 624 err_code_t __err; 625 __err=ERR_CODE_NONE; 626 __err=wr_ln_tx_dp_s_rstb(enable); if(__err) return(__err); 627 628 return ERR_CODE_NONE; 629 } 630 631 err_code_t falcon_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable) /* release the pmd core soft reset */ 632 { 633 err_code_t __err; 634 __err=ERR_CODE_NONE; 635 636 *enable=rd_ln_dp_s_rstb(); if(__err) return(__err); 637 638 return ERR_CODE_NONE; 639 } 640 641 err_code_t falcon_rx_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable) /* release the pmd rx lane soft reset */ 642 { 643 err_code_t __err; 644 __err=ERR_CODE_NONE; 645 646 *enable=rd_ln_rx_dp_s_rstb(); if(__err) return(__err); 647 648 return ERR_CODE_NONE; 649 } 650 651 err_code_t falcon_tx_lane_soft_reset_release_get(const phymod_access_t *pa, uint32_t *enable) /* release the pmd tx lane soft reset */ 652 { 653 err_code_t __err; 654 __err=ERR_CODE_NONE; 655 656 *enable=rd_ln_tx_dp_s_rstb(); if(__err) return(__err); 657 658 return ERR_CODE_NONE; 659 } 660 661 662 663 err_code_t falcon_lane_hard_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 664 { 665 err_code_t __err; 666 __err=ERR_CODE_NONE; 667 __err=wr_ln_s_rstb(enable); if(__err) return(__err); 668 669 return ERR_CODE_NONE; 670 } 671 672 err_code_t falcon_clause72_control(const phymod_access_t *pa, uint32_t cl_72_en) /* CLAUSE_72_CONTROL */ 673 { 674 err_code_t __err; 675 uint32_t enable; 676 677 __err=ERR_CODE_NONE; 678 679 if (cl_72_en) { 680 __err=wr_cl93n72_ieee_training_enable(1); if(__err) return(__err); 681 682 } else { 683 684 __err=wr_cl93n72_ieee_training_enable(0); if(__err) return(__err); 685 } 686 687 enable=rd_ln_dp_s_rstb(); if(__err) return(__err); 688 if (enable) 689 { 690 __err=wr_ln_dp_s_rstb(0); if(__err) return(__err); 691 __err=wr_ln_dp_s_rstb(1); if(__err) return(__err); 692 } 693 return ERR_CODE_NONE; 694 } 695 696 err_code_t falcon_clause72_control_get(const phymod_access_t *pa, uint32_t *cl_72_en) /* CLAUSE_72_CONTROL */ 697 { 698 err_code_t __err; 699 __err=ERR_CODE_NONE; 700 *cl_72_en = rd_cl93n72_ieee_training_enable(); if(__err) return(__err); 701 702 return ERR_CODE_NONE; 703 } 704 705 err_code_t falcon_electrical_idle_set(const phymod_access_t *pa, uint32_t en) 706 { 707 err_code_t __err; 708 __err=ERR_CODE_NONE; 709 710 __err = wr_ams_tx_elec_idle_aux(en); if(__err) return(__err); 711 712 return ERR_CODE_NONE; 713 } 714 715 716 /***********************************************/ 717 /* Microcode Init into Program RAM Functions */ 718 /***********************************************/ 719 720 /* uCode Load through Register (MDIO) Interface [Return Val = Error_Code (0 = PASS)] */ 721 err_code_t falcon_tsc_ucode_init( const phymod_access_t *pa ) { 722 723 err_code_t __err; 724 uint8_t result; 725 __err=ERR_CODE_NONE; 726 /* coverity[check_return] */ 727 wrc_micro_master_clk_en(0x1); /* Enable clock to microcontroller subsystem */ 728 /* coverity[check_return] */ 729 wrc_micro_master_rstb(0x1); /* De-assert reset to microcontroller sybsystem */ 730 /* coverity[check_return] */ 731 wrc_micro_master_rstb(0x0); /* Assert reset to microcontroller sybsystem - Toggling reset*/ 732 /* coverity[check_return] */ 733 wrc_micro_master_rstb(0x1); /* De-assert reset to microcontroller sybsystem */ 734 735 /* coverity[check_return] */ 736 wrc_micro_ra_init(0x1); /* Set initialization command to initialize code RAM */ 737 /* coverity[check_return] */ 738 falcon_tsc_delay_us(1000); 739 740 result = rdc_micro_ra_initdone(); /* Poll for micro_ra_initdone = 1 to indicate initialization done */ 741 if (!result) { /* Check if initialization done within 500us time interval */ 742 PHYMOD_DEBUG_ERROR(("ERR_CODE_MICRO_INIT_NOT_DONE\n")); 743 return (ERR_CODE_MICRO_INIT_NOT_DONE); /* Else issue error code */ 744 } 745 746 /* coverity[check_return] */ 747 wrc_micro_ra_init(0x0); 748 749 return (ERR_CODE_NONE); 750 } 751 752 /** 753 @brief Init the PMD 754 @param pmd_touched If the PMD is already initialized 755 @returns The value ERR_CODE_NONE upon successful completion 756 @details Per core PMD resets (both datapath and entire core) 757 We only intend to use this function if the PMD has never been initialized. 758 */ 759 err_code_t falcon_pmd_reset_seq(const phymod_access_t *pa, int pmd_touched) 760 { 761 if (pmd_touched == 0) { 762 /* coverity[check_return] */ 763 wrc_core_s_rstb(1); 764 /* coverity[check_return] */ 765 wrc_core_dp_s_rstb(1); 766 } 767 return (ERR_CODE_NONE); 768 } 769 770 771 /** 772 @brief Enable the pll reset bit 773 @param enable Controls whether to reset PLL 774 @returns The value ERR_CODE_NONE upon successful completion 775 @details 776 Resets the PLL 777 */ 778 err_code_t falcon_pll_reset_enable_set (const phymod_access_t *pa, int enable) 779 { 780 /* coverity[check_return] */ 781 wrc_afe_s_pll_reset_frc_val(enable); 782 /* coverity[check_return] */ 783 wrc_afe_s_pll_reset_frc(1); 784 return (ERR_CODE_NONE); 785 } 786 787 /** 788 @brief Read PLL range 789 */ 790 err_code_t falcon_tsc_read_pll_range (const phymod_access_t *pa, uint32_t *pll_range) 791 { 792 err_code_t __err; 793 __err=ERR_CODE_NONE; 794 *pll_range = rdc_ams_pll_range(); 795 return (ERR_CODE_NONE); 796 } 797 798 799 /** 800 @brief Reag signal detect 801 */ 802 err_code_t falcon_tsc_signal_detect (const phymod_access_t *pa, uint32_t *signal_detect) 803 { 804 err_code_t __err; 805 __err=ERR_CODE_NONE; 806 *signal_detect = rd_signal_detect(); 807 return (ERR_CODE_NONE); 808 } 809 810 811 err_code_t falcon_tsc_ladder_setting_to_mV(const phymod_access_t *pa, int8_t y, int16_t* level) { 812 813 /* *level = _ladder_setting_to_mV(y,0); */ 814 *level = (y*300)/127; 815 816 return(ERR_CODE_NONE); 817 } 818 819 820 err_code_t falcon_tsc_get_vco (const phymod_phy_inf_config_t* config, uint32_t *vco_rate, uint32_t *new_pll_div, int16_t *new_os_mode) { 821 *vco_rate = 0; 822 *new_pll_div=0; 823 *new_os_mode =0; 824 if(config->ref_clock == phymodRefClk156Mhz) { 825 switch (config->data_rate) { 826 case 6250 : /* speed 6.25G */ 827 *new_pll_div = 0x6; *new_os_mode = 2; *vco_rate = 25000; 828 break; 829 830 case 10312: /* speed 10.3125G */ 831 *new_pll_div = 0x4; *new_os_mode = 1; *vco_rate = 20625; 832 break; 833 834 case 10937: /* speed 10.9375G */ 835 *new_pll_div = 0x5; *new_os_mode = 1; *vco_rate = 21875; 836 break; 837 838 case 12500: /* speed 12.5G */ 839 *new_pll_div = 0x6; *new_os_mode = 1; *vco_rate = 25000; 840 break; 841 842 case 20625: /* speed 20.625G */ 843 *new_pll_div = 0x4; *new_os_mode = 0; *vco_rate = 20625; 844 break; 845 846 case 21875: /* speed 21.875G */ 847 *new_pll_div = 0x5; *new_os_mode = 0; *vco_rate = 21875; 848 break; 849 850 case 25000: /* speed 25G */ 851 *new_pll_div = 0x6; *new_os_mode = 0; *vco_rate = 25000; 852 break; 853 854 case 25781: /* speed 25.78125G */ 855 *new_pll_div = 0x7; *new_os_mode = 0; *vco_rate = 25781; 856 break; 857 858 case 27343: /* speed 27.3435G */ 859 *new_pll_div = 0xa; *new_os_mode = 0; *vco_rate = 27343; 860 break; 861 862 case 28125: /* speed 25.78125G */ 863 *new_pll_div = 0xb; *new_os_mode = 0; *vco_rate = 28125; 864 break; 865 866 default: 867 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d\n", (int)config->data_rate, config->ref_clock)); 868 return ERR_CODE_DIAG; 869 break; 870 } 871 } else if(config->ref_clock == phymodRefClk125Mhz) { 872 switch (config->data_rate) { 873 874 case 1250: /* speed 1.25G */ 875 *new_pll_div = 0x7; *new_os_mode = 8; *vco_rate = 20625; 876 break; 877 878 case 5750: /* speed 5.75G */ 879 *new_pll_div = 0xc; *new_os_mode = 2; *vco_rate = 23000; 880 break; 881 882 case 6250: /* speed 6.25G */ 883 *new_pll_div = 0xd; *new_os_mode = 2; *vco_rate = 25000; 884 break; 885 886 case 10312: /* speed 10.3125G */ 887 *new_pll_div = 0x7; *new_os_mode = 1; *vco_rate = 20625; 888 break; 889 890 case 10937: /* speed 10.937G */ 891 *new_pll_div = 0xa; *new_os_mode = 1; *vco_rate = 21875; 892 break; 893 894 case 11250: /* speed 11.25G */ 895 *new_pll_div = 0xb; *new_os_mode = 1; *vco_rate = 22500; 896 break; 897 898 case 11500: /* speed 11.5G */ 899 *new_pll_div = 0xc; *new_os_mode = 1; *vco_rate = 23000; 900 break; 901 902 case 12500: /* speed 12.5G */ 903 *new_pll_div = 0xd; *new_os_mode = 1; *vco_rate = 25000; 904 break; 905 906 case 20625: /* speed 20.625G */ 907 *new_pll_div = 0x7; *new_os_mode = 0; *vco_rate = 20625; 908 break; 909 910 case 21875: /* speed 21.875G */ 911 *new_pll_div = 0xa; *new_os_mode = 0; *vco_rate = 21875; 912 break; 913 914 case 22500: /* speed 22.5G */ 915 *new_pll_div = 0xb; *new_os_mode = 0; *vco_rate = 22500; 916 break; 917 918 case 23000: /* speed 23G */ 919 *new_pll_div = 0xc; *new_os_mode = 0; *vco_rate = 23000; 920 break; 921 922 case 25000: /* speed 25G */ 923 *new_pll_div = 0xd; *new_os_mode = 0; *vco_rate = 25000; 924 break; 925 926 case 28000: /* speed 28G */ 927 *new_pll_div = 0xe; *new_os_mode = 0; *vco_rate = 25000; 928 break; 929 930 default: 931 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d\n", (int)config->data_rate, config->ref_clock)); 932 return ERR_CODE_DIAG; 933 break; 934 } 935 } else { 936 PHYMOD_DEBUG_ERROR(("Unsupported ref clk :: %d\n", config->ref_clock)); 937 return ERR_CODE_DIAG; 938 } 939 return(ERR_CODE_NONE); 940 } 941 942 /* Get Enable/Disable Shared TX pattern generator */ 943 err_code_t falcon_tsc_tx_shared_patt_gen_en_get( const phymod_access_t *pa, uint8_t *enable) { 944 err_code_t __err; 945 __err=ERR_CODE_NONE; 946 947 *enable = rd_patt_gen_en(); if(__err) return(__err); 948 return ERR_CODE_NONE; 949 } 950 951 err_code_t falcon_tsc_config_shared_tx_pattern_idx_set( const phymod_access_t *pa, const uint32_t *pattern_len) { 952 err_code_t __err; 953 uint8_t mode_sel; 954 955 __err=ERR_CODE_NONE; 956 957 if(*pattern_len==240) { 958 mode_sel = 11; 959 } else if (*pattern_len== 220 ) { 960 mode_sel = 10; 961 } else if (*pattern_len == 200) { 962 mode_sel = 9; 963 } else if (*pattern_len == 180) { 964 mode_sel = 8; 965 } else if (*pattern_len == 160) { 966 mode_sel = 7; 967 } else if (*pattern_len == 140) { 968 mode_sel = 6; 969 } else { 970 mode_sel = 0; 971 PHYMOD_DEBUG_ERROR(("Invalid length input!\n")); 972 return ERR_CODE_DIAG; 973 } 974 975 if(mode_sel !=0){ 976 __err = wr_patt_gen_start_pos(mode_sel); 977 } 978 if(__err) return(__err); 979 980 /* 981 for (pattern_idx=0;pattern_idx<PATTERN_MAX_SIZE;pattern_idx++) { 982 983 lsb = (uint16_t)(pattern[pattern_idx] & 0xffff); 984 msb = (uint16_t) ((pattern[pattern_idx]>>16) & 0xffff); 985 986 switch (pattern_idx) { 987 case 0: 988 __err=wrc_patt_gen_seq_14(msb); if(__err) return(__err); 989 __err=wrc_patt_gen_seq_13(lsb); if(__err) return(__err); 990 break; 991 case 1: 992 __err=wrc_patt_gen_seq_12(msb); if(__err) return(__err); 993 __err=wrc_patt_gen_seq_11(lsb); if(__err) return(__err); 994 break; 995 case 2: 996 __err=wrc_patt_gen_seq_10(msb); if(__err) return(__err); 997 __err=wrc_patt_gen_seq_9(lsb); if(__err) return(__err); 998 break; 999 case 3: 1000 __err=wrc_patt_gen_seq_8(msb); if(__err) return(__err); 1001 __err=wrc_patt_gen_seq_7(lsb); if(__err) return(__err); 1002 break; 1003 case 4: 1004 __err=wrc_patt_gen_seq_6(msb); if(__err) return(__err); 1005 __err=wrc_patt_gen_seq_5(lsb); if(__err) return(__err); 1006 break; 1007 case 5: 1008 __err=wrc_patt_gen_seq_4(msb); if(__err) return(__err); 1009 __err=wrc_patt_gen_seq_3(lsb); if(__err) return(__err); 1010 break; 1011 case 6: 1012 __err=wrc_patt_gen_seq_2(msb); if(__err) return(__err); 1013 __err=wrc_patt_gen_seq_1(lsb); if(__err) return(__err); 1014 break; 1015 case 7: 1016 __err=wrc_patt_gen_seq_0(msb); if(__err) return(__err); 1017 break; 1018 */ /* Its a dead default and cause coverity defect 1019 default: 1020 PHYMOD_DEBUG_ERROR(("Wrong index value : Should be between 0 and 7\n")); 1021 return ERR_CODE_DIAG; 1022 break; 1023 */ 1024 /* } 1025 }*/ 1026 return ERR_CODE_NONE; 1027 } 1028 1029 err_code_t falcon_tsc_config_shared_tx_pattern_idx_get( const phymod_access_t *pa, uint32_t *pattern_len, uint32_t *pattern) { 1030 err_code_t __err; 1031 uint8_t mode_sel; 1032 uint32_t lsb = 0, msb = 0; 1033 int pattern_idx; 1034 1035 __err=ERR_CODE_NONE; 1036 1037 mode_sel = rd_patt_gen_start_pos(); if(__err) return(__err); 1038 1039 mode_sel = 12 - mode_sel; 1040 1041 if(mode_sel == 6) { 1042 *pattern_len = 140; 1043 } else if (mode_sel == 5) { 1044 *pattern_len = 160; 1045 } else if (mode_sel == 4) { 1046 *pattern_len = 180; 1047 } else if (mode_sel == 3) { 1048 *pattern_len = 200; 1049 } else if (mode_sel == 2) { 1050 *pattern_len = 220; 1051 } else if (mode_sel == 1) { 1052 *pattern_len = 240; 1053 } else { 1054 *pattern_len = 0; 1055 } 1056 1057 for (pattern_idx=0;pattern_idx<PATTERN_MAX_SIZE;pattern_idx++) { 1058 switch (pattern_idx) { 1059 case 0: 1060 msb=rdc_patt_gen_seq_14(); if(__err) return(__err); 1061 lsb=rdc_patt_gen_seq_13(); if(__err) return(__err); 1062 break; 1063 case 1: 1064 msb=rdc_patt_gen_seq_12(); if(__err) return(__err); 1065 lsb=rdc_patt_gen_seq_11(); if(__err) return(__err); 1066 break; 1067 case 2: 1068 msb=rdc_patt_gen_seq_10(); if(__err) return(__err); 1069 lsb=rdc_patt_gen_seq_9(); if(__err) return(__err); 1070 break; 1071 case 3: 1072 msb=rdc_patt_gen_seq_8(); if(__err) return(__err); 1073 lsb=rdc_patt_gen_seq_7(); if(__err) return(__err); 1074 break; 1075 case 4: 1076 msb=rdc_patt_gen_seq_6(); if(__err) return(__err); 1077 lsb=rdc_patt_gen_seq_5(); if(__err) return(__err); 1078 break; 1079 case 5: 1080 msb=rdc_patt_gen_seq_4(); if(__err) return(__err); 1081 lsb=rdc_patt_gen_seq_3(); if(__err) return(__err); 1082 break; 1083 case 6: 1084 msb=rdc_patt_gen_seq_2(); if(__err) return(__err); 1085 lsb=rdc_patt_gen_seq_1(); if(__err) return(__err); 1086 break; 1087 case 7: 1088 msb=rdc_patt_gen_seq_0(); if(__err) return(__err); 1089 lsb=0; 1090 break; 1091 /* Its a dead default and cause coverity defect 1092 default: 1093 PHYMOD_DEBUG_ERROR(("Wrong index value : Should be between 0 and 7\n")); 1094 return ERR_CODE_DIAG; 1095 break;*/ 1096 } 1097 1098 pattern[pattern_idx] = (msb <<16) | lsb; 1099 } 1100 1101 return ERR_CODE_NONE; 1102 } 1103 1104 /**********************************/ 1105 /* Serdes TX disable/RX Restart */ 1106 /**********************************/ 1107 1108 err_code_t falcon_tsc_tx_disable_get (const phymod_access_t *pa, uint8_t *enable){ 1109 err_code_t __err; 1110 1111 __err=ERR_CODE_NONE; 1112 *enable = (uint8_t) rd_sdk_tx_disable(); 1113 if(__err) return(__err); 1114 1115 return ERR_CODE_NONE; 1116 } 1117 1118 err_code_t falcon_refclk_set(const phymod_access_t *pa, phymod_ref_clk_t ref_clock) 1119 { 1120 err_code_t __err = ERR_CODE_NONE; 1121 1122 switch (ref_clock) { 1123 case phymodRefClk156Mhz: 1124 __err = wrc_heartbeat_count_1us(0x271); 1125 break; 1126 case phymodRefClk125Mhz: 1127 __err = wrc_heartbeat_count_1us(0x1f4); 1128 break; 1129 default: 1130 __err = wrc_heartbeat_count_1us(0x271); 1131 break; 1132 } 1133 1134 return __err; 1135 } 1136 1137 err_code_t falcon_tsc_rx_ppm(const phymod_access_t *pa, int16_t *rx_ppm) 1138 { 1139 err_code_t __err; 1140 __err=ERR_CODE_NONE; 1141 *rx_ppm = rd_cdr_integ_reg() / 84; 1142 return (ERR_CODE_NONE); 1143 } 1144