eagle_dpll.c (51785B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_dispatch.h> 13 #include <phymod/phymod_util.h> 14 #include <phymod/chip/bcmi_eagle_dpll_xgxs_defs.h> 15 16 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_enum.h" 17 #include "../../eagle_dpll/tier1/eagle2_cfg_seq.h" 18 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_common.h" 19 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_interface.h" 20 #include "../../eagle_dpll/tier1/eagle2_tsc2pll_dependencies.h" 21 #define EAGLE2PLL_ID0 0 22 #define EAGLE2PLL_ID1 0 23 #define EAGLE2PLL_MODEL 0x1a 24 #define EAGLE2PLL_REV_MASK 0x0 25 #define TSCE2PLL_PHY_ALL_LANES 0xf 26 #define TSCE2PLL_PMD_CRC_UCODE 0 27 28 #define TSCE2PLL_CORE_TO_PHY_ACCESS(_phy_access, _core_access) \ 29 do{\ 30 PHYMOD_MEMCPY(&(_phy_access)->access, &(_core_access)->access, sizeof((_phy_access)->access));\ 31 (_phy_access)->type = (_core_access)->type; \ 32 (_phy_access)->port_loc = (_core_access)->port_loc; \ 33 (_phy_access)->device_op_mode = (_core_access)->device_op_mode; \ 34 (_phy_access)->access.lane_mask = TSCE2PLL_PHY_ALL_LANES; \ 35 }while(0) 36 37 #define TSCE2PLL_NOF_DFES 9 38 #define TSCE2PLL_NOF_LANES_IN_CORE 4 39 extern unsigned char eagle2_tsc2pll_ucode[]; 40 extern unsigned short eagle2_tsc2pll_ucode_len; 41 #define EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(_phy_access) \ 42 do{\ 43 (_phy_access)->access.pll_idx = 0;\ 44 (_phy_access)->access.pll_idx = eagle2_tsc2pll_get_current_pll(&((_phy_access)->access));\ 45 }while(0) 46 47 48 49 50 int eagle_dpll_phy_firmware_core_config_set(const phymod_phy_access_t* phy, phymod_firmware_core_config_t fw_config) 51 { 52 phymod_phy_access_t phy_copy; 53 struct eagle2_tsc2pll_uc_core_config_st serdes_firmware_core_config; 54 55 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 56 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 57 PHYMOD_MEMSET(&serdes_firmware_core_config, 0, sizeof(serdes_firmware_core_config)); 58 serdes_firmware_core_config.field.core_cfg_from_pcs = fw_config.CoreConfigFromPCS; 59 serdes_firmware_core_config.field.vco_rate = fw_config.VcoRate; 60 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_set_uc_core_config(&phy_copy.access, serdes_firmware_core_config)); 61 return PHYMOD_E_NONE; 62 } 63 64 65 int eagle_dpll_phy_firmware_core_config_get(const phymod_phy_access_t* phy, phymod_firmware_core_config_t* fw_config) 66 { 67 phymod_phy_access_t phy_copy; 68 struct eagle2_tsc2pll_uc_core_config_st serdes_firmware_core_config; 69 70 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 71 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 72 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_get_uc_core_config(&phy_copy.access, &serdes_firmware_core_config)); 73 PHYMOD_MEMSET(fw_config, 0, sizeof(*fw_config)); 74 fw_config->CoreConfigFromPCS = serdes_firmware_core_config.field.core_cfg_from_pcs; 75 fw_config->VcoRate = serdes_firmware_core_config.field.vco_rate; 76 return PHYMOD_E_NONE; 77 } 78 79 80 int eagle_dpll_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_config) 81 { 82 phymod_phy_access_t phy_copy; 83 struct eagle2_tsc2pll_uc_lane_config_st serdes_firmware_config; 84 85 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 86 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 87 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_get_uc_lane_cfg(&phy_copy.access, &serdes_firmware_config)); 88 PHYMOD_MEMSET(fw_config, 0, sizeof(*fw_config)); 89 fw_config->LaneConfigFromPCS = serdes_firmware_config.field.lane_cfg_from_pcs; 90 fw_config->AnEnabled = serdes_firmware_config.field.an_enabled; 91 fw_config->DfeOn = serdes_firmware_config.field.dfe_on; 92 fw_config->ForceBrDfe = serdes_firmware_config.field.force_brdfe_on; 93 fw_config->Cl72AutoPolEn = serdes_firmware_config.field.cl72_auto_polarity_en; 94 fw_config->Cl72RestTO = serdes_firmware_config.field.cl72_restart_timeout_en; 95 fw_config->ScramblingDisable = serdes_firmware_config.field.scrambling_dis; 96 fw_config->UnreliableLos = serdes_firmware_config.field.unreliable_los; 97 fw_config->MediaType = serdes_firmware_config.field.media_type; 98 99 return PHYMOD_E_NONE; 100 } 101 102 int _eagle_dpll_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 103 { 104 phymod_phy_access_t phy_copy; 105 struct eagle2_tsc2pll_uc_lane_config_st serdes_firmware_config; 106 107 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 108 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 109 serdes_firmware_config.field.lane_cfg_from_pcs = fw_config.LaneConfigFromPCS; 110 serdes_firmware_config.field.an_enabled = fw_config.AnEnabled; 111 serdes_firmware_config.field.dfe_on = fw_config.DfeOn; 112 serdes_firmware_config.field.force_brdfe_on = fw_config.ForceBrDfe; 113 serdes_firmware_config.field.cl72_auto_polarity_en = fw_config.Cl72AutoPolEn; 114 serdes_firmware_config.field.cl72_restart_timeout_en = fw_config.Cl72RestTO; 115 serdes_firmware_config.field.scrambling_dis = fw_config.ScramblingDisable; 116 serdes_firmware_config.field.unreliable_los = fw_config.UnreliableLos; 117 serdes_firmware_config.field.media_type = fw_config.MediaType; 118 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_set_uc_lane_cfg(&phy_copy.access, serdes_firmware_config)); 119 return PHYMOD_E_NONE; 120 } 121 122 int eagle_dpll_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 123 { 124 phymod_phy_access_t phy_copy; 125 int start_lane, num_lane, i; 126 127 PHYMOD_IF_ERR_RETURN 128 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 129 130 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 131 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 132 /*Hold the per lne soft reset bit*/ 133 for (i = 0; i < num_lane; i++) { 134 phy_copy.access.lane_mask = 1 << (start_lane + i); 135 136 PHYMOD_IF_ERR_RETURN 137 (eagle2_tsc2pll_lane_soft_reset_release(&phy->access, 0)); 138 139 PHYMOD_IF_ERR_RETURN 140 (_eagle_dpll_phy_firmware_lane_config_set(phy, fw_config)); 141 142 PHYMOD_IF_ERR_RETURN 143 (eagle2_tsc2pll_lane_soft_reset_release(&phy->access, 1)); 144 } 145 146 return PHYMOD_E_NONE; 147 } 148 149 int _eagle_dpll_pll_multiplier_get(enum eagle2_tsc2pll_pll_enum pll_div, uint32_t *pll_multiplier) 150 { 151 switch (pll_div) { 152 case EAGLE2_TSC2PLL_pll_div_46x: 153 *pll_multiplier = 460; 154 break; 155 case EAGLE2_TSC2PLL_pll_div_72x: 156 *pll_multiplier = 720; 157 break; 158 case EAGLE2_TSC2PLL_pll_div_40x: 159 *pll_multiplier = 400; 160 break; 161 case EAGLE2_TSC2PLL_pll_div_42x: 162 *pll_multiplier = 420; 163 break; 164 /* 165 case 0x4: 166 *pll_multiplier = 580; 167 break; 168 */ 169 case EAGLE2_TSC2PLL_pll_div_50x: 170 *pll_multiplier = 500; 171 break; 172 case EAGLE2_TSC2PLL_pll_div_52x: 173 *pll_multiplier = 520; 174 break; 175 /* 176 case 0x7: 177 *pll_multiplier = 540; 178 break; 179 */ 180 case EAGLE2_TSC2PLL_pll_div_60x: 181 *pll_multiplier = 600; 182 break; 183 case EAGLE2_TSC2PLL_pll_div_64x: 184 *pll_multiplier = 640; 185 break; 186 case EAGLE2_TSC2PLL_pll_div_66x: 187 *pll_multiplier = 660; 188 break; 189 case EAGLE2_TSC2PLL_pll_div_68x: 190 *pll_multiplier = 680; 191 break; 192 case EAGLE2_TSC2PLL_pll_div_70x: 193 *pll_multiplier = 700; 194 break; 195 case EAGLE2_TSC2PLL_pll_div_80x: 196 *pll_multiplier = 800; 197 break; 198 case EAGLE2_TSC2PLL_pll_div_92x: 199 *pll_multiplier = 920; 200 break; 201 case EAGLE2_TSC2PLL_pll_div_100x: 202 *pll_multiplier = 1000; 203 break; 204 case EAGLE2_TSC2PLL_pll_div_82p5x: 205 *pll_multiplier = 825; 206 break; 207 case EAGLE2_TSC2PLL_pll_div_87p5x: 208 *pll_multiplier = 875; 209 break; 210 case EAGLE2_TSC2PLL_pll_div_73p6x: 211 *pll_multiplier = 736; 212 break; 213 case EAGLE2_TSC2PLL_pll_div_36p8x: 214 *pll_multiplier = 368; 215 break; 216 /* 217 case EAGLE_TSC_pll_div_199p04x: 218 *pll_multiplier = 1990.4; 219 break; 220 */ 221 default: 222 *pll_multiplier = 660; 223 break; 224 } 225 return PHYMOD_E_NONE; 226 } 227 228 int eagle_dpll_core_identify(const phymod_core_access_t* core, uint32_t core_id, uint32_t* is_identified) 229 { 230 const phymod_access_t *pm_acc = &core->access; 231 eagle_rev_id0_t rev_id0; 232 eagle_rev_id1_t rev_id1; 233 234 *is_identified = 0; 235 236 /* PHY IDs match - now check model */ 237 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_identify(pm_acc, &rev_id0, &rev_id1)); 238 if (rev_id0.revid_model == EAGLE2PLL_MODEL) { 239 *is_identified = 1; 240 } 241 242 return PHYMOD_E_NONE; 243 } 244 245 246 int eagle_dpll_core_info_get(const phymod_core_access_t* core, phymod_core_info_t* info) 247 { 248 249 250 /* Place your code here */ 251 252 253 return PHYMOD_E_NONE; 254 255 } 256 257 258 /* 259 * set lane swapping for core 260 * The tx swap is composed of PCS swap and after that the PMD swap. 261 * The rx swap is composed just by PCS swap 262 */ 263 int eagle_dpll_core_lane_map_set(const phymod_core_access_t* core, const phymod_lane_map_t* lane_map) 264 { 265 266 uint32_t lane, pmd_tx_map =0; 267 phymod_phy_access_t phy_copy; 268 269 TSCE2PLL_CORE_TO_PHY_ACCESS(&phy_copy, core); 270 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 271 272 for( lane = 0 ; lane < TSCE2PLL_NOF_LANES_IN_CORE ; lane++){ 273 pmd_tx_map |= ((lane_map->lane_map_tx[lane]) & 3) << (lane*4); 274 } 275 276 PHYMOD_IF_ERR_RETURN 277 (eagle2_tsc2pll_pmd_lane_swap(&phy_copy.access, pmd_tx_map)); 278 279 return PHYMOD_E_NONE; 280 281 } 282 283 int eagle_dpll_core_lane_map_get(const phymod_core_access_t* core, phymod_lane_map_t* lane_map) 284 { 285 286 int lane; 287 uint32_t pmd_swap = 0; 288 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_lane_swap_tx_get(&core->access, &pmd_swap)); 289 for( lane = 0 ; lane < TSCE2PLL_NOF_LANES_IN_CORE ; lane++){ 290 /*decode each lane from four bits*/ 291 /*considering the pcs lane swap: tx_map[lane] = pmd_map[pcs_map[lane]]*/ 292 /* lane_map->lane_map_tx[lane] = (pmd_swap>>(lane_map->lane_map_rx[lane]*4)) & TSCE_LANE_SWAP_LANE_MASK; */ 293 lane_map->lane_map_tx[lane] = (pmd_swap>>(lane*4)) & 0x3; 294 /*rx lane map is not supported*/ 295 lane_map->lane_map_rx[lane] = lane; 296 } 297 lane_map->num_of_lanes = TSCE2PLL_NOF_LANES_IN_CORE; 298 299 return PHYMOD_E_NONE; 300 301 } 302 303 304 int eagle_dpll_core_reset_set(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 305 { 306 307 308 /* Place your code here */ 309 310 311 return PHYMOD_E_NONE; 312 313 } 314 315 int eagle_dpll_core_reset_get(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t* direction) 316 { 317 318 319 /* Place your code here */ 320 321 322 return PHYMOD_E_NONE; 323 324 } 325 326 327 int eagle_dpll_core_firmware_info_get(const phymod_core_access_t* core, phymod_core_firmware_info_t* fw_info) 328 { 329 330 331 /* Place your code here */ 332 333 334 return PHYMOD_E_NONE; 335 336 } 337 338 339 int eagle_dpll_core_pll_sequencer_restart(const phymod_core_access_t* core, uint32_t flags, phymod_sequencer_operation_t operation) 340 { 341 342 343 /* Place your code here */ 344 345 346 return PHYMOD_E_NONE; 347 348 } 349 350 351 int eagle_dpll_core_wait_event(const phymod_core_access_t* core, phymod_core_event_t event, uint32_t timeout) 352 { 353 354 355 /* Place your code here */ 356 357 358 return PHYMOD_E_NONE; 359 360 } 361 362 363 int eagle_dpll_phy_rx_restart(const phymod_phy_access_t* phy) 364 { 365 phymod_phy_access_t phy_copy; 366 367 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 368 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 369 370 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rx_restart(&phy_copy.access, 1)); 371 372 return PHYMOD_E_NONE; 373 374 } 375 376 377 int eagle_dpll_phy_polarity_set(const phymod_phy_access_t* phy, const phymod_polarity_t* polarity) 378 { 379 phymod_phy_access_t phy_copy; 380 381 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 382 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 383 384 PHYMOD_IF_ERR_RETURN 385 (eagle2_tsc2pll_tx_rx_polarity_set(&phy_copy.access, polarity->tx_polarity, polarity->rx_polarity)); 386 387 return PHYMOD_E_NONE; 388 389 } 390 391 int eagle_dpll_phy_polarity_get(const phymod_phy_access_t* phy, phymod_polarity_t* polarity) 392 { 393 phymod_phy_access_t phy_copy; 394 395 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 396 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 397 398 PHYMOD_IF_ERR_RETURN 399 (eagle2_tsc2pll_tx_rx_polarity_get(&phy_copy.access, &polarity->tx_polarity, &polarity->rx_polarity)); 400 401 return PHYMOD_E_NONE; 402 403 } 404 405 406 int eagle_dpll_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx) 407 { 408 409 phymod_phy_access_t phy_copy; 410 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 411 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 412 413 PHYMOD_IF_ERR_RETURN 414 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_PRE, (int8_t)tx->pre)); 415 PHYMOD_IF_ERR_RETURN 416 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_MAIN, (int8_t)tx->main)); 417 PHYMOD_IF_ERR_RETURN 418 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_POST1, (int8_t)tx->post)); 419 PHYMOD_IF_ERR_RETURN 420 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_POST2, (int8_t)tx->post2)); 421 PHYMOD_IF_ERR_RETURN 422 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_POST3, (int8_t)tx->post3)); 423 PHYMOD_IF_ERR_RETURN 424 (eagle2_tsc2pll_write_tx_afe(&phy_copy.access, TX_AFE_AMP, (int8_t)tx->amp)); 425 426 427 return PHYMOD_E_NONE; 428 429 } 430 431 int eagle_dpll_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx) 432 { 433 int8_t value = 0; 434 phymod_phy_access_t phy_copy; 435 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 436 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 437 438 PHYMOD_IF_ERR_RETURN 439 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_PRE, &value)); 440 tx->pre = value; 441 PHYMOD_IF_ERR_RETURN 442 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_MAIN, &value)); 443 tx->main = value; 444 PHYMOD_IF_ERR_RETURN 445 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_POST1, &value)); 446 tx->post = value; 447 PHYMOD_IF_ERR_RETURN 448 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_POST2, &value)); 449 tx->post2 = value; 450 PHYMOD_IF_ERR_RETURN 451 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_POST3, &value)); 452 tx->post3 = value; 453 PHYMOD_IF_ERR_RETURN 454 (eagle2_tsc2pll_read_tx_afe(&phy_copy.access, TX_AFE_AMP, &value)); 455 tx->amp = value; 456 457 return PHYMOD_E_NONE; 458 459 } 460 461 462 int eagle_dpll_phy_media_type_tx_get(const phymod_phy_access_t* phy, phymod_media_typed_t media, phymod_tx_t* tx) 463 { 464 465 466 switch (media) { 467 case phymodMediaTypeChipToChip: 468 tx->pre = 0xc; 469 tx->main = 0x64; 470 tx->post = 0x0; 471 tx->post2 = 0x0; 472 tx->post3 = 0x0; 473 tx->amp = 0xc; 474 break; 475 case phymodMediaTypeShort: 476 tx->pre = 0xc; 477 tx->main = 0x64; 478 tx->post = 0x0; 479 tx->post2 = 0x0; 480 tx->post3 = 0x0; 481 tx->amp = 0xc; 482 break; 483 case phymodMediaTypeMid: 484 tx->pre = 0xc; 485 tx->main = 0x64; 486 tx->post = 0x0; 487 tx->post2 = 0x0; 488 tx->post3 = 0x0; 489 tx->amp = 0xc; 490 break; 491 case phymodMediaTypeLong: 492 tx->pre = 0xc; 493 tx->main = 0x64; 494 tx->post = 0x0; 495 tx->post2 = 0x0; 496 tx->post3 = 0x0; 497 tx->amp = 0xc; 498 break; 499 default: 500 tx->pre = 0xc; 501 tx->main = 0x64; 502 tx->post = 0x0; 503 tx->post2 = 0x0; 504 tx->post3 = 0x0; 505 tx->amp = 0xc; 506 break; 507 } 508 509 510 return PHYMOD_E_NONE; 511 512 } 513 514 515 int eagle_dpll_phy_tx_override_set(const phymod_phy_access_t* phy, const phymod_tx_override_t* tx_override) 516 { 517 518 phymod_phy_access_t phy_copy; 519 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 520 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 521 522 PHYMOD_IF_ERR_RETURN 523 (eagle2_tsc2pll_tx_pi_freq_override(&phy_copy.access, 524 tx_override->phase_interpolator.enable, 525 tx_override->phase_interpolator.value)); 526 527 return PHYMOD_E_NONE; 528 529 } 530 531 int eagle_dpll_phy_tx_override_get(const phymod_phy_access_t* phy, phymod_tx_override_t* tx_override) 532 { 533 534 535 /* Place your code here */ 536 537 538 return PHYMOD_E_NONE; 539 540 } 541 542 543 int eagle_dpll_phy_rx_set(const phymod_phy_access_t* phy, const phymod_rx_t* rx) 544 { 545 546 uint32_t i; 547 phymod_phy_access_t phy_copy; 548 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 549 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 550 551 /*params check*/ 552 if((rx->num_of_dfe_taps == 0) || (rx->num_of_dfe_taps < TSCE2PLL_NOF_DFES)){ 553 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal number of DFEs to set %u"), rx->num_of_dfe_taps)); 554 } 555 556 /*vga set*/ 557 if (rx->vga.enable) { 558 /* first stop the rx adaption */ 559 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 1)); 560 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_VGA, rx->vga.value)); 561 } else { 562 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 0)); 563 } 564 565 /*dfe set*/ 566 for (i = 0 ; i < rx->num_of_dfe_taps ; i++){ 567 if(rx->dfe[i].enable){ 568 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 1)); 569 switch (i) { 570 case 0: 571 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_DFE1, rx->dfe[i].value)); 572 break; 573 case 1: 574 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_DFE2, rx->dfe[i].value)); 575 break; 576 case 2: 577 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_DFE3, rx->dfe[i].value)); 578 break; 579 case 3: 580 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_DFE4, rx->dfe[i].value)); 581 break; 582 case 4: 583 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_DFE5, rx->dfe[i].value)); 584 break; 585 default: 586 return PHYMOD_E_PARAM; 587 } 588 } else { 589 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 0)); 590 } 591 592 593 } 594 595 /*peaking filter set*/ 596 if(rx->peaking_filter.enable){ 597 /* first stop the rx adaption */ 598 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 1)); 599 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_PF, rx->peaking_filter.value)); 600 } else { 601 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 0)); 602 } 603 604 if(rx->low_freq_peaking_filter.enable){ 605 /* first stop the rx adaption */ 606 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 1)); 607 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_write_rx_afe(&phy_copy.access, RX_AFE_PF2, rx->low_freq_peaking_filter.value)); 608 } else { 609 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_stop_rx_adaptation(&phy_copy.access, 0)); 610 } 611 612 return PHYMOD_E_NONE; 613 614 } 615 616 int eagle_dpll_phy_rx_get(const phymod_phy_access_t* phy, phymod_rx_t* rx) 617 { 618 int8_t val; 619 phymod_phy_access_t phy_copy; 620 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 621 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 622 623 PHYMOD_IF_ERR_RETURN 624 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_PF, &val)); 625 rx->peaking_filter.value = val; 626 627 PHYMOD_IF_ERR_RETURN 628 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_PF2, &val)); 629 rx->low_freq_peaking_filter.value = val; 630 631 PHYMOD_IF_ERR_RETURN 632 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_VGA, &val)); 633 rx->vga.value = val; 634 635 PHYMOD_IF_ERR_RETURN 636 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE1, &val)); 637 rx->dfe[0].value = val; 638 639 PHYMOD_IF_ERR_RETURN 640 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE2, &val)); 641 rx->dfe[1].value = val; 642 643 PHYMOD_IF_ERR_RETURN 644 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE3, &val)); 645 rx->dfe[2].value = val; 646 647 PHYMOD_IF_ERR_RETURN 648 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE4, &val)); 649 rx->dfe[3].value = val; 650 651 PHYMOD_IF_ERR_RETURN 652 (eagle2_tsc2pll_read_rx_afe(&phy_copy.access, RX_AFE_DFE5, &val)); 653 rx->dfe[4].value = val; 654 655 rx->num_of_dfe_taps = 5; 656 rx->dfe[0].enable = 1; 657 rx->dfe[1].enable = 1; 658 rx->dfe[2].enable = 1; 659 rx->dfe[3].enable = 1; 660 rx->dfe[4].enable = 1; 661 rx->vga.enable = 1; 662 rx->low_freq_peaking_filter.enable = 1; 663 rx->peaking_filter.enable = 1; 664 665 return PHYMOD_E_NONE; 666 667 } 668 669 670 int eagle_dpll_phy_reset_set(const phymod_phy_access_t* phy, const phymod_phy_reset_t* reset) 671 { 672 phymod_phy_access_t phy_copy; 673 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 674 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 675 676 switch (reset->rx) { 677 case phymodResetDirectionIn: 678 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_rx_set_rst(&phy_copy.access, 0x1)); 679 break; 680 case phymodResetDirectionOut: 681 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_rx_set_rst(&phy_copy.access, 0x0)); 682 break; 683 case phymodResetDirectionInOut: 684 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_rx_set_rst(&phy_copy.access, 0x1)); 685 PHYMOD_USLEEP(10); 686 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_rx_set_rst(&phy_copy.access, 0x0)); 687 break; 688 default: 689 break; 690 } 691 switch (reset->tx) { 692 case phymodResetDirectionIn: 693 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_tx_set_rst(&phy_copy.access, 0x1)); 694 break; 695 case phymodResetDirectionOut: 696 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_tx_set_rst(&phy_copy.access, 0x0)); 697 break; 698 case phymodResetDirectionInOut: 699 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_tx_set_rst(&phy_copy.access, 0x1)); 700 PHYMOD_USLEEP(10); 701 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_tx_set_rst(&phy_copy.access, 0x0)); 702 break; 703 default: 704 break; 705 } 706 707 return PHYMOD_E_NONE; 708 709 } 710 711 int eagle_dpll_phy_reset_get(const phymod_phy_access_t* phy, phymod_phy_reset_t* reset) 712 { 713 714 uint32_t rst; 715 phymod_phy_access_t phy_copy; 716 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 717 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 718 719 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_tx_get_rst(&phy_copy.access, &rst)); 720 if(rst == 0) { 721 reset->tx = phymodResetDirectionOut; 722 } else { 723 reset->tx = phymodResetDirectionIn; 724 } 725 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_force_rx_get_rst(&phy_copy.access, &rst)); 726 if(rst == 0) { 727 reset->rx = phymodResetDirectionOut; 728 } else { 729 reset->rx = phymodResetDirectionIn; 730 } 731 732 return PHYMOD_E_NONE; 733 734 } 735 736 737 int eagle_dpll_phy_power_set(const phymod_phy_access_t* phy, const phymod_phy_power_t* power) 738 { 739 740 enum srds_core_pwrdn_mode_enum mode; 741 phymod_phy_access_t phy_copy; 742 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 743 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 744 mode = PWRDN; 745 /* printf("MODE: %x\n", mode); */ 746 if ((power->tx == phymodPowerOff) && (power->rx == phymodPowerNoChange)) { 747 /*disable tx on the PMD side */ 748 mode = PWRDN_TX; 749 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_pwrdn(&phy_copy.access, mode)); 750 } 751 if ((power->tx == phymodPowerOn) && (power->rx == phymodPowerNoChange)) { 752 /*enable tx on the PMD side */ 753 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pwrdn_set(&phy_copy.access, 1, 0)); 754 } 755 if ((power->tx == phymodPowerNoChange) && (power->rx == phymodPowerOff)) { 756 /*disable rx on the PMD side */ 757 mode = PWRDN_RX; 758 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_pwrdn(&phy_copy.access, mode)); 759 } 760 if ((power->tx == phymodPowerNoChange) && (power->rx == phymodPowerOn)) { 761 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pwrdn_set(&phy_copy.access, 0, 0)); 762 /*enable rx on the PMD side */ 763 } 764 if ((power->tx == phymodPowerOn) && (power->rx == phymodPowerOn)) { 765 mode = PWR_ON; 766 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_pwrdn(&phy_copy.access, mode)); 767 } 768 if ((power->tx == phymodPowerOff) && (power->rx == phymodPowerOff)) { 769 /* Both Tx and Rx power down */ 770 mode = PWRDN; 771 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_pwrdn(&phy_copy.access, mode)); 772 } 773 774 return PHYMOD_E_NONE; 775 776 } 777 778 int eagle_dpll_phy_power_get(const phymod_phy_access_t* phy, phymod_phy_power_t* power) 779 { 780 781 782 power_status_t pwrdn; 783 phymod_phy_access_t phy_copy; 784 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 785 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 786 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pwrdn_get(&phy_copy.access, &pwrdn)); 787 power->rx = (pwrdn.rx_s_pwrdn == 0)? phymodPowerOn: phymodPowerOff; 788 power->tx = (pwrdn.tx_s_pwrdn == 0)? phymodPowerOn: phymodPowerOff; 789 790 return PHYMOD_E_NONE; 791 792 } 793 794 795 int eagle_dpll_phy_tx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t tx_control) 796 { 797 phymod_phy_access_t phy_copy; 798 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 799 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 800 801 switch (tx_control) 802 { 803 case phymodTxSquelchOn: 804 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_tx_lane_control_set(&phy_copy.access, 1)); 805 break; 806 case phymodTxSquelchOff: 807 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_tx_lane_control_set(&phy_copy.access, 0)); 808 break; 809 default: 810 PHYMOD_DEBUG_ERROR(("This control is NOT SUPPORTED!! (eagle_phy_tx_lane_control_set) \n")); 811 break; 812 } 813 814 return PHYMOD_E_NONE; 815 816 } 817 818 int eagle_dpll_phy_tx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t* tx_control) 819 { 820 821 uint32_t enable; 822 phymod_phy_access_t phy_copy; 823 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 824 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 825 826 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_tx_lane_control_get(&phy_copy.access, &enable)); 827 828 if(enable){ 829 *tx_control = phymodTxSquelchOn; 830 } else { 831 *tx_control = phymodTxSquelchOff; 832 } 833 834 return PHYMOD_E_NONE; 835 836 } 837 838 839 int eagle_dpll_phy_rx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t rx_control) 840 { 841 phymod_phy_access_t phy_copy; 842 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 843 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 844 845 switch (rx_control) 846 { 847 case phymodRxSquelchOn: 848 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rx_lane_control_set(&phy_copy.access, 1)); 849 break; 850 case phymodRxSquelchOff: 851 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rx_lane_control_set(&phy_copy.access, 0)); 852 break; 853 default: 854 PHYMOD_DEBUG_ERROR(("This control is NOT SUPPORTED!! (eagle_phy_rx_lane_control_set) \n")); 855 break; 856 } 857 858 return PHYMOD_E_NONE; 859 860 861 } 862 863 int eagle_dpll_phy_rx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t* rx_control) 864 { 865 866 uint32_t enable; 867 phymod_phy_access_t phy_copy; 868 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 869 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 870 871 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rx_lane_control_get(&phy_copy.access, &enable)); 872 873 if(enable){ 874 *rx_control = phymodRxSquelchOn; 875 } else { 876 *rx_control = phymodRxSquelchOff; 877 } 878 879 return PHYMOD_E_NONE; 880 881 } 882 int _eagle_dpll_phy_pll_config(const phymod_phy_access_t* phy, uint32_t new_pll_div, uint32_t vco_rate, uint8_t pll_index) 883 { 884 phymod_phy_access_t pm_phy_copy; 885 phymod_firmware_core_config_t firmware_core_config; 886 int start_lane =0, num_lane; 887 PHYMOD_MEMSET(&firmware_core_config, 0x0, sizeof(firmware_core_config)); 888 889 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 890 pm_phy_copy.access.pll_idx = pll_index; 891 892 PHYMOD_IF_ERR_RETURN 893 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 894 895 firmware_core_config.CoreConfigFromPCS = 0; 896 897 /* phymod_access_t tmp_phy_access; */ 898 PHYMOD_IF_ERR_RETURN 899 (eagle2_tsc2pll_core_soft_reset_release(&pm_phy_copy.access, 0)); 900 901 /*set the PLL divider */ 902 PHYMOD_IF_ERR_RETURN 903 (eagle2_tsc2pll_configure_pll(&pm_phy_copy.access, new_pll_div)); 904 905 firmware_core_config.VcoRate = (vco_rate - 5750) / 250 + 1; 906 907 /*update the firmware config properly*/ 908 PHYMOD_IF_ERR_RETURN 909 (eagle_dpll_phy_firmware_core_config_set(&pm_phy_copy, firmware_core_config)); 910 PHYMOD_IF_ERR_RETURN 911 (eagle2_tsc2pll_core_soft_reset_release(&pm_phy_copy.access, 1)); 912 return PHYMOD_E_NONE; 913 } 914 915 int _eagle_dpll_phy_pll_select(const phymod_phy_access_t *phy, uint8_t pll_select) 916 { 917 int i, start_lane=0, num_lane; 918 phymod_phy_access_t pm_phy_copy; 919 920 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 921 PHYMOD_IF_ERR_RETURN 922 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 923 924 for (i = 0; i < num_lane; i++) { 925 if (!PHYMOD_LANEPBMP_MEMBER(phy->access.lane_mask, start_lane + i)) { 926 continue; 927 } 928 PHYMOD_IF_ERR_RETURN 929 (eagle2_tsc2pll_select_pll(&pm_phy_copy.access, pll_select)); 930 } 931 932 return PHYMOD_E_NONE; 933 } 934 int _eagle_dpll_phy_pll_set(const phymod_phy_access_t* phy, uint32_t new_div, uint32_t vco_rate, uint8_t* pll_select) 935 { 936 uint32_t current_div0, current_div1,new_pll_multiplier, pll_multiplier_0, pll_multiplier_1; 937 int start_lane=0, num_lane; 938 phymod_phy_access_t pm_phy_copy; 939 uint8_t pll_index_temp = 0; 940 enum eagle2_tsc2pll_pll_enum pll_mode; 941 942 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 943 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 944 PHYMOD_IF_ERR_RETURN 945 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 946 PHYMOD_IF_ERR_RETURN 947 (_eagle_dpll_pll_multiplier_get(new_div, &new_pll_multiplier)); 948 949 /* get the current PLL0 and PLL1 setting */ 950 pll_index_temp = pm_phy_copy.access.pll_idx; 951 pm_phy_copy.access.lane_mask = 1 << start_lane; 952 pm_phy_copy.access.pll_idx = 0; 953 PHYMOD_IF_ERR_RETURN 954 (eagle2_tsc2pll_pll_config_get(&pm_phy_copy.access, &pll_mode)); 955 current_div0 = (uint32_t) pll_mode; 956 pm_phy_copy.access.pll_idx = 1; 957 PHYMOD_IF_ERR_RETURN 958 (eagle2_tsc2pll_pll_config_get(&pm_phy_copy.access, &pll_mode)); 959 current_div1 = (uint32_t) pll_mode; 960 pm_phy_copy.access.pll_idx = pll_index_temp; 961 962 PHYMOD_IF_ERR_RETURN 963 (_eagle_dpll_pll_multiplier_get(current_div0, &pll_multiplier_0)); 964 PHYMOD_IF_ERR_RETURN 965 (_eagle_dpll_pll_multiplier_get(current_div1, &pll_multiplier_1)); 966 /* 967 a)PLL0 is always programmed with the highest VCO frequency vs. PLL1. 968 b)PLL1 only can be configured to 6.25G 969 c) No flexing of PLL VCO frequency will be supported. If one of the 2 PLLs needs to be reconfigured, all 4 ports need to be brought down. 970 d) The lane has to be in reset before the field can be reconfigured to select a different PLL. 971 */ 972 /*Compare the new div with the current divs , if new div equal to any one of the dual pll 973 then select the pll for the lane 974 */ 975 if (new_div == current_div0 || new_div == current_div1) { 976 if((new_div == current_div0) && (pm_phy_copy.access.pll_idx != 0)){ 977 /*select pll0*/ 978 PHYMOD_IF_ERR_RETURN 979 (_eagle_dpll_phy_pll_select(phy, 0)); 980 *pll_select = 0; 981 } 982 if((new_div == current_div1) && pm_phy_copy.access.pll_idx != 1) { 983 /*select pll1*/ 984 PHYMOD_IF_ERR_RETURN 985 (_eagle_dpll_phy_pll_select(phy, 1)); 986 *pll_select = 1; 987 } 988 return PHYMOD_E_NONE; 989 } 990 /*Else need to compare the current pll with pll1*/ 991 /*PLL1 must be configured to 6.25G , and pll0 must higher than pll1. If new pll lower than pll1, it`s a illegal div*/ 992 if (new_pll_multiplier < pll_multiplier_1) { 993 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 994 (_PHYMOD_MSG("this div %d is not supported at this vco %d"), 995 new_pll_multiplier, vco_rate)); 996 /*IF the new pll higher than pll1, then select pll0 and re-configure pll0*/ 997 } else { 998 /*select pll0 then configure pll0*/ 999 PHYMOD_IF_ERR_RETURN 1000 (_eagle_dpll_phy_pll_select(phy, 0)); 1001 *pll_select = 0; 1002 /*reconfig pll0 with new_div*/ 1003 PHYMOD_IF_ERR_RETURN 1004 (_eagle_dpll_phy_pll_config(phy, new_div, vco_rate, 0)); 1005 } 1006 1007 return PHYMOD_E_NONE; 1008 } 1009 1010 1011 int eagle_dpll_phy_interface_config_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_phy_inf_config_t* config) 1012 { 1013 1014 /* phymod_tx_t tx_params; */ 1015 enum eagle2_tsc2pll_pll_enum new_pll_div=EAGLE2_TSC2PLL_pll_div_66x; 1016 uint32_t vco_rate; 1017 int16_t new_os_mode =-1; 1018 phymod_phy_access_t pm_phy_copy; 1019 int start_lane, num_lane, i; 1020 uint8_t pll_select; 1021 1022 /* sc_table_entry exp_entry; RAVI */ 1023 phymod_firmware_lane_config_t firmware_lane_config; 1024 1025 firmware_lane_config.MediaType = 0; 1026 1027 /*next program the tx fir taps and driver current based on the input*/ 1028 PHYMOD_IF_ERR_RETURN 1029 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1030 1031 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1032 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 1033 1034 /*Hold the per lne soft reset bit*/ 1035 for (i = 0; i < num_lane; i++) { 1036 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1037 PHYMOD_IF_ERR_RETURN 1038 (eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 0)); 1039 } 1040 1041 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 1042 PHYMOD_IF_ERR_RETURN 1043 (eagle_dpll_phy_firmware_lane_config_get(&pm_phy_copy, &firmware_lane_config)); 1044 1045 /*make sure that an and config from pcs is off*/ 1046 firmware_lane_config.AnEnabled = 0; 1047 firmware_lane_config.LaneConfigFromPCS = 0; 1048 firmware_lane_config.DfeOn = 0; 1049 firmware_lane_config.Cl72RestTO = 1; 1050 1051 PHYMOD_IF_ERR_RETURN 1052 (eagle2_tsc2pll_get_vco(config, &vco_rate, &new_pll_div, &new_os_mode)); 1053 1054 if(config->data_rate >= 10312) { 1055 firmware_lane_config.DfeOn = 1; 1056 } 1057 PHYMOD_IF_ERR_RETURN 1058 (_eagle_dpll_phy_pll_set(phy, new_pll_div, vco_rate, &pll_select)); 1059 pm_phy_copy.access.pll_idx = pll_select; 1060 1061 for (i = 0; i < num_lane; i++) { 1062 pm_phy_copy.access.lane_mask = 0x1 << (start_lane + i); 1063 PHYMOD_IF_ERR_RETURN 1064 (_eagle_dpll_phy_firmware_lane_config_set(&pm_phy_copy, firmware_lane_config)); 1065 } 1066 1067 /*release the per lne soft reset bit*/ 1068 for (i = 0; i < num_lane; i++) { 1069 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1070 PHYMOD_IF_ERR_RETURN 1071 (eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 1)); 1072 } 1073 1074 for (i=0; i < num_lane; i++) { 1075 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1076 PHYMOD_IF_ERR_RETURN 1077 (eagle2_tsc2pll_osr_mode_set(&pm_phy_copy.access, new_os_mode)); 1078 } 1079 1080 return PHYMOD_E_NONE; 1081 1082 } 1083 1084 int eagle_dpll_phy_interface_config_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_ref_clk_t ref_clock, phymod_phy_inf_config_t* config) 1085 { 1086 int osr_mode; 1087 /* uint32_t pll_div; */ 1088 enum eagle2_tsc2pll_pll_enum pll_div; 1089 uint32_t pll_multiplier, refclk; 1090 phymod_phy_access_t phy_copy; 1091 uint32_t actual_osr, actual_osr_rem; 1092 phymod_osr_mode_t osr_mode_enum; 1093 int start_lane, num_lane; 1094 1095 config->ref_clock = ref_clock; 1096 1097 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1098 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1099 PHYMOD_IF_ERR_RETURN 1100 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1101 phy_copy.access.lane_mask = 0x1 << start_lane; 1102 1103 PHYMOD_IF_ERR_RETURN 1104 (eagle2_tsc2pll_osr_mode_get(&phy_copy.access, &osr_mode)); 1105 /* 1106 PHYMOD_IF_ERR_RETURN 1107 (eagle_pll_mode_get(&phy_copy.access, &pll_div)); 1108 */ 1109 PHYMOD_IF_ERR_RETURN 1110 (eagle2_tsc2pll_pll_config_get(&phy_copy.access, &pll_div)); 1111 PHYMOD_IF_ERR_RETURN 1112 (_eagle_dpll_pll_multiplier_get(pll_div, &pll_multiplier)); 1113 1114 1115 if (ref_clock == phymodRefClk156Mhz) { 1116 refclk = 15625; 1117 } else if (ref_clock == phymodRefClk125Mhz) { 1118 refclk = 12500; 1119 } else { 1120 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("Unknown refclk"))); 1121 } 1122 1123 1124 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_osr_mode_to_enum(osr_mode, &osr_mode_enum)); 1125 PHYMOD_IF_ERR_RETURN(phymod_osr_mode_to_actual_os(osr_mode_enum, &actual_osr, &actual_osr_rem)); 1126 1127 /* Divide by 1000 is take care of pll_mulitple(by 10) and ref_clk (by 100) */ 1128 config->data_rate = (refclk*pll_multiplier)/(1000*actual_osr); 1129 config->interface_type = phymodInterfaceBypass; 1130 1131 if(osr_mode_enum == phymodOversampleMode2) { 1132 PHYMOD_INTF_MODES_OS2_SET(config); 1133 } 1134 return PHYMOD_E_NONE; 1135 1136 } 1137 1138 1139 int eagle_dpll_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en) 1140 { 1141 phymod_phy_access_t phy_copy; 1142 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1143 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1144 1145 PHYMOD_IF_ERR_RETURN 1146 (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 0)); 1147 PHYMOD_IF_ERR_RETURN 1148 (eagle2_tsc2pll_clause72_control(&phy_copy.access, cl72_en)); 1149 PHYMOD_IF_ERR_RETURN 1150 (eagle2_tsc2pll_lane_soft_reset_release(&phy_copy.access, 1)); 1151 1152 return PHYMOD_E_NONE; 1153 1154 } 1155 1156 int eagle_dpll_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en) 1157 { 1158 phymod_phy_access_t phy_copy; 1159 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1160 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1161 1162 PHYMOD_IF_ERR_RETURN 1163 (eagle2_tsc2pll_clause72_control_get(&phy_copy.access, cl72_en)); 1164 1165 return PHYMOD_E_NONE; 1166 1167 } 1168 1169 1170 int eagle_dpll_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status) 1171 { 1172 1173 1174 uint32_t local_status; 1175 phymod_phy_access_t phy_copy; 1176 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1177 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1178 PHYMOD_IF_ERR_RETURN 1179 (eagle2_tsc2pll_pmd_cl72_receiver_status(&phy_copy.access, &local_status)); 1180 status->locked = local_status; 1181 return PHYMOD_E_NONE; 1182 1183 } 1184 1185 1186 int eagle_dpll_phy_autoneg_ability_set(const phymod_phy_access_t* phy, const phymod_autoneg_ability_t* an_ability_set_type) 1187 { 1188 1189 1190 /* Place your code here */ 1191 1192 1193 return PHYMOD_E_NONE; 1194 1195 } 1196 1197 int eagle_dpll_phy_autoneg_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type) 1198 { 1199 1200 1201 /* Place your code here */ 1202 1203 1204 return PHYMOD_E_NONE; 1205 1206 } 1207 1208 1209 int eagle_dpll_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 1210 { 1211 1212 1213 /* Place your code here */ 1214 1215 1216 return PHYMOD_E_NONE; 1217 1218 } 1219 1220 int eagle_dpll_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an, uint32_t* an_done) 1221 { 1222 1223 1224 /* Place your code here */ 1225 1226 1227 return PHYMOD_E_NONE; 1228 1229 } 1230 1231 1232 int eagle_dpll_phy_autoneg_status_get(const phymod_phy_access_t* phy, phymod_autoneg_status_t* status) 1233 { 1234 1235 1236 /* Place your code here */ 1237 1238 1239 return PHYMOD_E_NONE; 1240 1241 } 1242 1243 /* load tsce fw. the fw_loader parameter is valid just for external fw load*/ 1244 STATIC 1245 int _eagle_dpll_core_firmware_load(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config) 1246 { 1247 /* int wait; */ 1248 1249 switch(init_config->firmware_load_method){ 1250 case phymodFirmwareLoadMethodInternal: 1251 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_ucode_mdio_load(&core->access, eagle2_tsc2pll_ucode, eagle2_tsc2pll_ucode_len)); 1252 break; 1253 case phymodFirmwareLoadMethodExternal: 1254 if(!PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 1255 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pram_flop_set(&core->access, 0x0)); 1256 1257 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_ucode_init(&core->access)); 1258 1259 /* 1260 wait = (PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) ? 0 : 1; 1261 PHYMOD_IF_ERR_RETURN(eagle_pram_firmware_enable(&core->access, 1, wait)); 1262 */ 1263 1264 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pram_firmware_enable(&core->access, 1)); 1265 1266 if(PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 1267 return PHYMOD_E_NONE; 1268 } 1269 1270 PHYMOD_NULL_CHECK(init_config->firmware_loader); 1271 1272 PHYMOD_IF_ERR_RETURN(init_config->firmware_loader(core, eagle2_tsc2pll_ucode_len, eagle2_tsc2pll_ucode)); 1273 } 1274 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pram_firmware_enable(&core->access, 0)); 1275 break; 1276 case phymodFirmwareLoadMethodNone: 1277 break; 1278 default: 1279 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal fw load method %u"), init_config->firmware_load_method)); 1280 } 1281 if(init_config->firmware_load_method != phymodFirmwareLoadMethodNone){ 1282 /*PHYMOD_IF_ERR_RETURN(tsce_core_firmware_info_get(core, &actual_fw)); 1283 if((tsce_ucode_crc != actual_fw.fw_crc) || (tsce_ucode_ver != actual_fw.fw_version)){ 1284 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("fw load validation was failed"))); 1285 } */ 1286 } 1287 return PHYMOD_E_NONE; 1288 } 1289 int eagle_dpll_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config, const phymod_core_status_t* core_status) 1290 { 1291 int rv; 1292 phymod_phy_access_t phy_access, phy_access_copy; 1293 phymod_core_access_t core_copy; 1294 phymod_firmware_core_config_t firmware_core_config_tmp; 1295 1296 TSCE2PLL_CORE_TO_PHY_ACCESS(&phy_access, core); 1297 phy_access_copy = phy_access; 1298 PHYMOD_MEMCPY(&core_copy, core, sizeof(core_copy)); 1299 core_copy.access.lane_mask = 0x1; 1300 phy_access_copy = phy_access; 1301 phy_access_copy.access = core->access; 1302 phy_access_copy.access.lane_mask = 0x1; 1303 phy_access_copy.type = core->type; 1304 1305 1306 if(!PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 1307 PHYMOD_IF_ERR_RETURN 1308 (eagle2_tsc2pll_pmd_reset_seq(&core_copy.access, core_status->pmd_active)); 1309 } 1310 rv = _eagle_dpll_core_firmware_load(&core_copy, init_config); 1311 if (rv != PHYMOD_E_NONE) { 1312 PHYMOD_DEBUG_ERROR(("devad 0x%x lane 0x%x: UC firmware-load failed\n", core->access.addr, core->access.lane_mask)); 1313 PHYMOD_IF_ERR_RETURN(rv); 1314 } 1315 1316 if(PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 1317 return PHYMOD_E_NONE; 1318 } 1319 1320 /*next we need to check if the load is correct or not */ 1321 if(init_config->firmware_load_method != phymodFirmwareLoadMethodNone) { 1322 1323 /* This moved earlier as compared to falcon, to sync up with tsce.c */ 1324 PHYMOD_IF_ERR_RETURN 1325 (eagle2_tsc2pll_pmd_ln_h_rstb_pkill_override( &phy_access_copy.access, 0x1)); 1326 1327 /*next we need to set the uc active and release uc */ 1328 PHYMOD_IF_ERR_RETURN 1329 (eagle2_tsc2pll_uc_active_set(&core_copy.access ,1)); 1330 1331 /*release the uc reset */ 1332 PHYMOD_IF_ERR_RETURN 1333 (eagle2_tsc2pll_uc_reset(&core_copy.access ,0)); 1334 1335 #ifndef TSCE_PMD_CRC_UCODE 1336 if(PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_GET(init_config)) { 1337 rv = eagle2_tsc2pll_ucode_load_verify(&core_copy.access, (uint8_t *) &eagle2_tsc2pll_ucode, eagle2_tsc2pll_ucode_len); 1338 if (rv != PHYMOD_E_NONE) { 1339 PHYMOD_DEBUG_ERROR(("devad 0x%x lane 0x%x: UC load-verify failed\n", core->access.addr, core->access.lane_mask)); 1340 PHYMOD_IF_ERR_RETURN(rv); 1341 } 1342 } 1343 #endif 1344 1345 /* we need to wait at least 10ms for the uc to settle */ 1346 PHYMOD_USLEEP(10000); 1347 1348 /* poll the ready bit in 10 ms */ 1349 #ifndef TSCE_PMD_CRC_UCODE 1350 PHYMOD_IF_ERR_RETURN 1351 (eagle2_tsc2pll_poll_uc_dsc_ready_for_cmd_equals_1(&phy_access_copy.access, 1)); 1352 #else 1353 /* 1354 PHYMOD_IF_ERR_RETURN( 1355 eagle_tsc_ucode_crc_verify( &core_copy.access, tsce_ucode_len,tsce_ucode_crc)); 1356 */ 1357 #endif 1358 1359 1360 PHYMOD_IF_ERR_RETURN 1361 (eagle2_tsc2pll_pmd_ln_h_rstb_pkill_override( &phy_access_copy.access, 0x0)); 1362 } 1363 1364 /* plldiv CONFIG */ 1365 firmware_core_config_tmp = init_config->firmware_core_config; 1366 firmware_core_config_tmp.CoreConfigFromPCS = 0; 1367 core_copy.access.pll_idx = 0x0; 1368 PHYMOD_IF_ERR_RETURN 1369 (eagle2_tsc2pll_pll_mode_set(&core_copy.access, 0xa)); 1370 /*set the PLL0 vco rate to be default at 10.3125G */ 1371 firmware_core_config_tmp.VcoRate = 0x13; 1372 PHYMOD_IF_ERR_RETURN 1373 (eagle_dpll_phy_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 1374 core_copy.access.pll_idx = 0x1; 1375 PHYMOD_IF_ERR_RETURN 1376 (eagle2_tsc2pll_pll_mode_set(&core_copy.access, 0x2)); 1377 /*set the PLL1 vco rate to be default at 6.25G */ 1378 firmware_core_config_tmp.VcoRate = 0x3; 1379 PHYMOD_IF_ERR_RETURN 1380 (eagle_dpll_phy_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 1381 1382 /*now config the lane mapping and polarity */ 1383 PHYMOD_IF_ERR_RETURN 1384 (eagle_dpll_core_lane_map_set(core, &init_config->lane_map)); 1385 /* 1386 PHYMOD_IF_ERR_RETURN 1387 (tsce_core_lane_map_set(core, &init_config->lane_map)); 1388 PHYMOD_IF_ERR_RETURN 1389 (temod_autoneg_timer_init(&core->access)); 1390 PHYMOD_IF_ERR_RETURN 1391 (temod_master_port_num_set(&core->access, 0)); 1392 */ 1393 /*don't overide the fw that set in config set if not specified*/ 1394 1395 /* release core soft reset */ 1396 PHYMOD_IF_ERR_RETURN 1397 (eagle2_tsc2pll_core_soft_reset_release(&core_copy.access, 1)); 1398 1399 1400 return PHYMOD_E_NONE; 1401 1402 } 1403 1404 1405 int eagle_dpll_phy_init(const phymod_phy_access_t* phy, const phymod_phy_init_config_t* init_config) 1406 { 1407 1408 const phymod_access_t *pm_acc = &phy->access; 1409 phymod_phy_access_t pm_phy_copy; 1410 int start_lane, num_lane, i; 1411 int lane_bkup; 1412 phymod_polarity_t tmp_pol; 1413 1414 PHYMOD_MEMSET(&tmp_pol, 0x0, sizeof(tmp_pol)); 1415 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1416 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&pm_phy_copy); 1417 1418 /*next program the tx fir taps and driver current based on the input*/ 1419 PHYMOD_IF_ERR_RETURN 1420 (phymod_util_lane_config_get(pm_acc, &start_lane, &num_lane)); 1421 /*per lane based reset release */ 1422 /* PHYMOD_IF_ERR_RETURN 1423 (temod_pmd_x4_reset(pm_acc)); */ 1424 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_hard_soft_reset_release(&pm_phy_copy.access, 0)); 1425 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_hard_soft_reset_release(&pm_phy_copy.access, 1)); 1426 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 0)); 1427 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 1)); 1428 1429 lane_bkup = pm_phy_copy.access.lane_mask; 1430 for (i = 0; i < num_lane; i++) { 1431 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1432 PHYMOD_IF_ERR_RETURN 1433 (eagle2_tsc2pll_lane_soft_reset_release(&pm_phy_copy.access, 1)); 1434 } 1435 pm_phy_copy.access.lane_mask = lane_bkup; 1436 1437 /* program the rx/tx polarity */ 1438 for (i = 0; i < num_lane; i++) { 1439 pm_phy_copy.access.lane_mask = 0x1 << (i + start_lane); 1440 tmp_pol.tx_polarity = (init_config->polarity.tx_polarity) >> i & 0x1; 1441 tmp_pol.rx_polarity = (init_config->polarity.rx_polarity) >> i & 0x1; 1442 PHYMOD_IF_ERR_RETURN 1443 (eagle_dpll_phy_polarity_set(&pm_phy_copy, &tmp_pol)); 1444 } 1445 1446 for (i = 0; i < num_lane; i++) { 1447 pm_phy_copy.access.lane_mask = 0x1 << (i + start_lane); 1448 PHYMOD_IF_ERR_RETURN 1449 (eagle_dpll_phy_tx_set(&pm_phy_copy, &init_config->tx[i])); 1450 } 1451 1452 PHYMOD_IF_ERR_RETURN 1453 (eagle_dpll_phy_cl72_set(&pm_phy_copy, init_config->cl72_en)); 1454 1455 1456 return PHYMOD_E_NONE; 1457 1458 } 1459 1460 1461 int eagle_dpll_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable) 1462 { 1463 1464 int i; 1465 int start_lane, num_lane; 1466 int rv = PHYMOD_E_NONE; 1467 phymod_phy_access_t phy_copy; 1468 1469 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1470 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1471 1472 /* next figure out the lane num and start_lane based on the input */ 1473 PHYMOD_IF_ERR_RETURN 1474 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1475 1476 switch (loopback) { 1477 case phymodLoopbackGlobal : 1478 /* PHYMOD_IF_ERR_RETURN(temod_tx_loopback_control(&phy->access, enable, start_lane, num_lane)); */ 1479 break; 1480 case phymodLoopbackGlobalPMD : 1481 for (i = 0; i < num_lane; i++) { 1482 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 1483 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_dig_lpbk(&phy_copy.access, (uint8_t) enable)); 1484 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_force_signal_detect(&phy_copy.access, (int) enable)); 1485 } 1486 break; 1487 case phymodLoopbackRemotePMD : 1488 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rmt_lpbk(&phy_copy.access, (uint8_t)enable)); 1489 break; 1490 case phymodLoopbackRemotePCS : 1491 /* PHYMOD_IF_ERR_RETURN(temod_rx_loopback_control(&phy->access, enable)); */ 1492 break; 1493 default : 1494 break; 1495 } 1496 return rv; 1497 1498 } 1499 1500 int eagle_dpll_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable) 1501 { 1502 1503 int start_lane, num_lane; 1504 phymod_phy_access_t phy_copy; 1505 1506 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1507 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1508 1509 /*next figure out the lane num and start_lane based on the input*/ 1510 PHYMOD_IF_ERR_RETURN 1511 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1512 1513 switch (loopback) { 1514 case phymodLoopbackGlobal : 1515 /* PHYMOD_IF_ERR_RETURN(temod_tx_loopback_get(&phy->access, &enable_core)); */ 1516 /* *enable = (enable_core >> start_lane) & 0x1; */ 1517 break; 1518 case phymodLoopbackGlobalPMD : 1519 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_dig_lpbk_get(&phy_copy.access, enable)); 1520 break; 1521 case phymodLoopbackRemotePMD : 1522 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_rmt_lpbk_get(&phy_copy.access, enable)); 1523 break; 1524 case phymodLoopbackRemotePCS : 1525 /* PHYMOD_IF_ERR_RETURN(temod_rx_loopback_control(&phy->access, enable, enable, enable)); */ 1526 break; 1527 default : 1528 break; 1529 } 1530 return PHYMOD_E_NONE; 1531 1532 } 1533 1534 1535 int eagle_dpll_phy_link_status_get(const phymod_phy_access_t* phy, uint32_t* link_status) 1536 { 1537 1538 unsigned char rx_lock; 1539 phymod_phy_access_t phy_copy; 1540 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1541 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1542 PHYMOD_IF_ERR_RETURN(eagle2_tsc2pll_pmd_lock_status(&phy_copy.access, &rx_lock)); 1543 *link_status = (uint32_t ) rx_lock; 1544 1545 return PHYMOD_E_NONE; 1546 1547 } 1548 1549 1550 int eagle_dpll_phy_rx_pmd_locked_get(const phymod_phy_access_t* phy, uint32_t* rx_pmd_locked) 1551 { 1552 1553 PHYMOD_IF_ERR_RETURN(eagle_dpll_phy_link_status_get(phy, rx_pmd_locked)); 1554 return PHYMOD_E_NONE; 1555 1556 } 1557 1558 1559 int eagle_dpll_phy_reg_read(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t* val) 1560 { 1561 1562 phymod_phy_access_t phy_copy; 1563 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1564 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1565 1566 PHYMOD_IF_ERR_RETURN(phymod_tsc_iblk_read(&phy_copy.access, reg_addr, val)); 1567 return PHYMOD_E_NONE; 1568 1569 } 1570 1571 1572 int eagle_dpll_phy_reg_write(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t val) 1573 { 1574 phymod_phy_access_t phy_copy; 1575 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1576 EAGLE2PLL_PHY_ACCESS_PLLIDX_SET(&phy_copy); 1577 1578 PHYMOD_IF_ERR_RETURN(phymod_tsc_iblk_write(&phy_copy.access, reg_addr, val)); 1579 return PHYMOD_E_NONE; 1580 1581 } 1582 1583 1584