eagle_diagnostics.c (26823B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_util.h> 13 #include <phymod/phymod_config.h> 14 #include <phymod/phymod_diagnostics.h> 15 #include <phymod/phymod_diagnostics_dispatch.h> 16 17 #define PATTERN_MAX_LENGTH 240 18 19 #ifdef PHYMOD_EAGLE_SUPPORT 20 21 #include <phymod/chip/eagle_common.h> 22 23 #include "../../eagle/tier1/eagle_tsc_enum.h" 24 #include "../../eagle/tier1/eagle_tsc_common.h" 25 /* #include "../../eagle/tier1/eagle_tsc_common_enum.h" */ 26 #include "../../eagle/tier1/eagle_cfg_seq.h" 27 #include "../../eagle/tier1/eagle_tsc_interface.h" 28 #include "../../eagle/tier1/eagle_tsc_dependencies.h" 29 #include "../../eagle/tier1/eagle_tsc_debug_functions.h" 30 31 #include "../../tsce/tier1/temod_enum_defines.h" 32 33 int eagle_phy_rx_slicer_position_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_slicer_position_t* position) 34 { 35 36 37 /* Place your code here */ 38 PHYMOD_DEBUG_ERROR(("eagle_phy_rx_slicer_position_set function is NOT SUPPORTED!!\n")); 39 40 41 return PHYMOD_E_NONE; 42 43 } 44 45 int eagle_phy_rx_slicer_position_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_slicer_position_t* position) 46 { 47 48 49 /* Place your code here */ 50 PHYMOD_DEBUG_ERROR(("eagle_phy_rx_slicer_position_get function is NOT SUPPORTED!!\n")); 51 52 53 return PHYMOD_E_NONE; 54 55 } 56 57 58 int eagle_phy_rx_slicer_position_max_get(const phymod_phy_access_t* phy, uint32_t flags, const phymod_slicer_position_t* position_min, const phymod_slicer_position_t* position_max) 59 { 60 61 /* Place your code here */ 62 PHYMOD_DEBUG_ERROR(("eagle_phy_rx_slicer_position_max_get function is NOT SUPPORTED!!\n")); 63 64 return PHYMOD_E_NONE; 65 66 } 67 68 69 70 71 int eagle_phy_prbs_enable_set(const phymod_phy_access_t* phy, uint32_t flags , uint32_t enable) 72 { 73 74 if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 75 PHYMOD_IF_ERR_RETURN(eagle_tsc_tx_prbs_en(&phy->access, enable)); 76 } else if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 77 PHYMOD_IF_ERR_RETURN(eagle_tsc_rx_prbs_en(&phy->access, enable)); 78 } else { 79 PHYMOD_IF_ERR_RETURN(eagle_tsc_tx_prbs_en(&phy->access, enable)); 80 PHYMOD_IF_ERR_RETURN(eagle_tsc_rx_prbs_en(&phy->access, enable)); 81 } 82 return PHYMOD_E_NONE; 83 84 } 85 86 int eagle_phy_prbs_enable_get(const phymod_phy_access_t* phy, uint32_t flags , uint32_t* enable) 87 { 88 uint32_t enable_tmp; 89 if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 90 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_enable_get(&phy->access, &enable_tmp)); 91 *enable = enable_tmp; 92 } else if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 93 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_enable_get(&phy->access, &enable_tmp)); 94 *enable = enable_tmp; 95 } else { 96 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_enable_get(&phy->access, &enable_tmp)); 97 *enable = enable_tmp; 98 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_enable_get(&phy->access, &enable_tmp)); 99 *enable &= enable_tmp; 100 } 101 102 return PHYMOD_E_NONE; 103 104 } 105 106 107 int eagle_phy_prbs_status_get(const phymod_phy_access_t* phy, uint32_t flags, phymod_prbs_status_t* prbs_status) 108 { 109 110 uint8_t status = 0; 111 uint32_t prbs_err_count = 0; 112 113 PHYMOD_IF_ERR_RETURN(eagle_tsc_prbs_chk_lock_state(&phy->access, &status)); 114 if (status) { 115 prbs_status->prbs_lock = 1; 116 /*next check the lost of lock and error count */ 117 status = 0; 118 PHYMOD_IF_ERR_RETURN 119 (eagle_tsc_prbs_err_count_state(&phy->access, &prbs_err_count, &status)); 120 if (status) { 121 /*temp lost of lock */ 122 prbs_status->prbs_lock_loss = 1; 123 } else { 124 prbs_status->prbs_lock_loss = 0; 125 prbs_status->error_count = prbs_err_count; 126 } 127 } else { 128 prbs_status->prbs_lock = 0; 129 } 130 131 return PHYMOD_E_NONE; 132 133 } 134 135 136 int eagle_phy_pattern_config_set(const phymod_phy_access_t* phy, const phymod_pattern_t* pattern) 137 { 138 int i,j = 0, bit; 139 char patt[PATTERN_MAX_LENGTH+1]; 140 141 for (i=0; i< PATTERN_MAX_SIZE; i++) 142 { 143 for (j=0;j<32 && i*32+j <= PATTERN_MAX_LENGTH; j++) 144 { 145 if (i*32+j == pattern->pattern_len) { 146 break; 147 } 148 bit = pattern->pattern[i] >> j & 00000001; 149 switch (bit) { 150 case (1): 151 patt[i*32+j] = '1'; 152 break; 153 default: 154 patt[i*32+j] = '0'; 155 break; 156 } 157 } 158 if (i*32+j == pattern->pattern_len && i*32+j <= PATTERN_MAX_LENGTH) { 159 /* coverity[overrun-local] */ 160 patt[i*32+j] = '\0'; 161 break; 162 } 163 } 164 PHYMOD_IF_ERR_RETURN 165 (eagle_tsc_config_shared_tx_pattern_idx_set(&phy->access, 166 &pattern->pattern_len )); 167 PHYMOD_IF_ERR_RETURN 168 (eagle_tsc_config_shared_tx_pattern (&phy->access, 169 (uint8_t) pattern->pattern_len, (const char *) patt)); 170 171 return PHYMOD_E_NONE; 172 } 173 174 int eagle_phy_pattern_config_get(const phymod_phy_access_t* phy, phymod_pattern_t* pattern) 175 { 176 PHYMOD_IF_ERR_RETURN 177 (eagle_tsc_config_shared_tx_pattern_idx_get(&phy->access, 178 &pattern->pattern_len, 179 pattern->pattern)); 180 return PHYMOD_E_NONE; 181 } 182 183 184 int eagle_phy_pattern_enable_set(const phymod_phy_access_t* phy, uint32_t enable, phymod_pattern_t* pattern) 185 { 186 PHYMOD_IF_ERR_RETURN 187 (eagle_tsc_tx_shared_patt_gen_en(&phy->access, (uint8_t) enable, (uint8_t)pattern->pattern_len)); 188 return PHYMOD_E_NONE; 189 } 190 191 int eagle_phy_pattern_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 192 { 193 uint8_t enable_8; 194 PHYMOD_IF_ERR_RETURN 195 (eagle_tsc_tx_shared_patt_gen_en_get(&phy->access, &enable_8)); 196 *enable = (uint32_t) enable_8; 197 return PHYMOD_E_NONE; 198 } 199 200 201 int eagle_core_diagnostics_get(const phymod_core_access_t* core, phymod_core_diagnostics_t* diag) 202 { 203 204 205 /* NOT SUPPORTED IN EAGLE YET 206 signed short temperature; 207 208 eagle_tsc_read_die_temperature(&core->access, &temperature); 209 diag->temperature = temperature; 210 */ 211 212 eagle_tsc_read_pll_range(&core->access, &diag->pll_range); 213 214 return PHYMOD_E_NONE; 215 216 } 217 218 219 int eagle_phy_diagnostics_get(const phymod_phy_access_t* phy, phymod_phy_diagnostics_t* diag) 220 { 221 222 unsigned char rx_lock; 223 int osr_mode; 224 phymod_diag_eyescan_t_init(&diag->eyescan); 225 phymod_diag_slicer_offset_t_init(&diag->slicer_offset); 226 227 PHYMOD_IF_ERR_RETURN(eagle_tsc_pmd_lock_status(&phy->access, &rx_lock)); 228 diag->rx_lock = (uint32_t ) rx_lock; 229 PHYMOD_IF_ERR_RETURN(eagle_osr_mode_get(&phy->access, &osr_mode)); 230 PHYMOD_IF_ERR_RETURN(eagle_osr_mode_to_enum(osr_mode, &diag->osr_mode)); 231 PHYMOD_IF_ERR_RETURN(eagle_tsc_signal_detect(&phy->access, &diag->signal_detect)); 232 233 return PHYMOD_E_NONE; 234 235 } 236 237 STATIC err_code_t eagle_phy_meas_lowber_eye (const phymod_access_t *pa, 238 const phymod_phy_eyescan_options_t *eyescan_options, 239 uint32_t *buffer) 240 { 241 struct eagle_tsc_eyescan_options_st e_options; 242 243 e_options.linerate_in_khz = eyescan_options->linerate_in_khz; 244 e_options.timeout_in_milliseconds = eyescan_options->timeout_in_milliseconds; 245 e_options.horz_max = eyescan_options->horz_max; 246 e_options.horz_min = eyescan_options->horz_min; 247 e_options.hstep = eyescan_options->hstep; 248 e_options.vert_max = eyescan_options->vert_max; 249 e_options.vert_min = eyescan_options->vert_min; 250 e_options.vstep = eyescan_options->vstep; 251 e_options.mode = eyescan_options->mode; 252 253 return (eagle_tsc_meas_lowber_eye(pa, e_options, buffer)); 254 } 255 256 STATIC err_code_t eagle_phy_display_lowber_eye (const phymod_access_t *pa, 257 const phymod_phy_eyescan_options_t *eyescan_options, 258 uint32_t *buffer) 259 { 260 struct eagle_tsc_eyescan_options_st e_options; 261 262 e_options.linerate_in_khz = eyescan_options->linerate_in_khz; 263 e_options.timeout_in_milliseconds = eyescan_options->timeout_in_milliseconds; 264 e_options.horz_max = eyescan_options->horz_max; 265 e_options.horz_min = eyescan_options->horz_min; 266 e_options.hstep = eyescan_options->hstep; 267 e_options.vert_max = eyescan_options->vert_max; 268 e_options.vert_min = eyescan_options->vert_min; 269 e_options.vstep = eyescan_options->vstep; 270 e_options.mode = eyescan_options->mode; 271 272 return(eagle_tsc_display_lowber_eye (pa, e_options, buffer)); 273 } 274 275 276 static void _eagle_diag_uc_reg_dump(const phymod_access_t *pa) 277 { 278 err_code_t errc = PHYMOD_E_NONE; 279 280 COMPILER_REFERENCE(errc); 281 282 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 283 PHYMOD_DEBUG_ERROR(("| MICRO CODE USR CTRL CONFIGURATION REGISTERS |\n")); 284 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 285 PHYMOD_DEBUG_ERROR(("| config_word [0x00]: 0x%04X |\n", eagle_tsc_rdwl_uc_var(pa,&errc,0x0))); 286 PHYMOD_DEBUG_ERROR(("| retune_after_restart [0x02]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x2))); 287 PHYMOD_DEBUG_ERROR(("| clk90_offset_adjust [0x03]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x3))); 288 PHYMOD_DEBUG_ERROR(("| clk90_offset_override [0x04]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x4))); 289 PHYMOD_DEBUG_ERROR(("| lane_event_log_level [0x05]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x5))); 290 PHYMOD_DEBUG_ERROR(("| disable_startup [0x06]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x6))); 291 PHYMOD_DEBUG_ERROR(("| disable_startup_dfe [0x07]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x7))); 292 PHYMOD_DEBUG_ERROR(("| disable_steady_state [0x08]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x8))); 293 PHYMOD_DEBUG_ERROR(("| disable_steady_state_dfe [0x09]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x9))); 294 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 295 PHYMOD_DEBUG_ERROR(("| MICRO CODE USER STATUS REGISTERS |\n")); 296 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 297 PHYMOD_DEBUG_ERROR(("| restart_counter [0x0A]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0xa))); 298 PHYMOD_DEBUG_ERROR(("| reset_counter [0x0B]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0xb))); 299 PHYMOD_DEBUG_ERROR(("| pmd_lock_counter [0x0C]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0xc))); 300 PHYMOD_DEBUG_ERROR(("| heye_left [0x0D]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0xd))); 301 PHYMOD_DEBUG_ERROR(("| heye_left_lsbyte [0x0E]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0xe))); 302 PHYMOD_DEBUG_ERROR(("| heye_right [0x0F]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0xf))); 303 PHYMOD_DEBUG_ERROR(("| heye_right_lsbyte [0x10]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x10))); 304 PHYMOD_DEBUG_ERROR(("| veye_upper [0x11]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x11))); 305 PHYMOD_DEBUG_ERROR(("| veye_upper_lsbyte [0x12]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x12))); 306 PHYMOD_DEBUG_ERROR(("| veye_lower [0x13]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x13))); 307 PHYMOD_DEBUG_ERROR(("| veye_lower_lsbyte [0x14]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x14))); 308 PHYMOD_DEBUG_ERROR(("| micro_stopped [0x15]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x15))); 309 PHYMOD_DEBUG_ERROR(("| link_time [0x16]: 0x%04X |\n", eagle_tsc_rdwl_uc_var(pa,&errc,0x16))); 310 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 311 PHYMOD_DEBUG_ERROR(("| MICRO CODE MISC REGISTERS |\n")); 312 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 313 PHYMOD_DEBUG_ERROR(("| usr_diag_status [0x18]: 0x%04X |\n", eagle_tsc_rdwl_uc_var(pa,&errc,0x18))); 314 PHYMOD_DEBUG_ERROR(("| usr_diag_rd_ptr [0x1A]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x1a))); 315 PHYMOD_DEBUG_ERROR(("| usr_diag_mode [0x1B]: 0x%04X |\n", eagle_tsc_rdbl_uc_var(pa,&errc,0x1b))); 316 PHYMOD_DEBUG_ERROR(("| usr_var_msb [0x1C]: 0x%04X |\n", eagle_tsc_rdwl_uc_var(pa,&errc,0x1c))); 317 PHYMOD_DEBUG_ERROR(("| usr_var_lsb [0x1E]: 0x%04X |\n", eagle_tsc_rdwl_uc_var(pa,&errc,0x1e))); 318 PHYMOD_DEBUG_ERROR(("+-------------------------------------------------+\n")); 319 320 } 321 322 STATIC int eagle_diagnostics_eyescan_run_uc(const phymod_phy_access_t* phy, uint32_t flags) 323 { 324 int j; 325 int ii, rc = PHYMOD_E_NONE; 326 uint32_t stripe[64]; 327 uint16_t status; 328 phymod_phy_access_t phy_copy; 329 330 331 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 332 333 for(j=0; j< PHYMOD_CONFIG_MAX_LANES_PER_CORE; j++) { /* Loop for all lanes. */ 334 if ((phy->access.lane_mask & (1<<j))==0) continue; 335 336 phy_copy.access.lane_mask = (phy->access.lane_mask & (1<<j)); 337 338 if(PHYMOD_EYESCAN_F_ENABLE_GET(flags)) { 339 PHYMOD_IF_ERR_RETURN(eagle_tsc_meas_eye_scan_start(&(phy_copy.access), 0)); 340 341 if(!PHYMOD_EYESCAN_F_ENABLE_DONT_WAIT_GET(flags)) { 342 PHYMOD_USLEEP(100000); 343 } 344 } 345 346 if(PHYMOD_EYESCAN_F_PROCESS_GET(flags)) { 347 348 for (ii = 31; ii >= -31; ii--) { 349 if (ii == 31) { 350 PHYMOD_DIAG_OUT(("\n\n\n")); 351 PHYMOD_DIAG_OUT((" +--------------------------------------------------------------------+\n")); 352 PHYMOD_DIAG_OUT((" | EYESCAN Phy: 0x%02x lane_mask 0x%02x |\n", phy_copy.access.addr, phy_copy.access.lane_mask)); 353 PHYMOD_DIAG_OUT((" +--------------------------------------------------------------------+\n")); 354 /*display eyescan header*/ 355 PHYMOD_IF_ERR_RETURN(eagle_tsc_display_eye_scan_header(&(phy_copy.access), 1)); 356 } 357 358 rc = eagle_tsc_read_eye_scan_stripe(&(phy_copy.access), stripe, &status); 359 if(rc != PHYMOD_E_NONE) { 360 _eagle_diag_uc_reg_dump(&(phy_copy.access)); 361 PHYMOD_IF_ERR_RETURN(rc); 362 } 363 PHYMOD_IF_ERR_RETURN(eagle_tsc_display_eye_scan_stripe(&(phy_copy.access), ii, &stripe[0])); 364 365 PHYMOD_DIAG_OUT(("\n")); 366 } 367 368 if (rc == PHYMOD_E_NONE) { 369 PHYMOD_IF_ERR_RETURN(eagle_tsc_display_eye_scan_footer(&(phy_copy.access), 1)); 370 PHYMOD_DIAG_OUT(("\n")); 371 } 372 } 373 374 if(PHYMOD_EYESCAN_F_DONE_GET(flags)) { 375 PHYMOD_IF_ERR_RETURN(eagle_tsc_meas_eye_scan_done(&(phy_copy.access))); 376 } 377 } 378 379 return PHYMOD_E_NONE; 380 } 381 382 STATIC int eagle_diagnostics_eyescan_run_lowber( 383 const phymod_phy_access_t* phy, 384 uint32_t flags, 385 const phymod_phy_eyescan_options_t* eyescan_options 386 ) 387 { 388 uint32_t *buffer; 389 int buffer_size = 64*64; 390 int rv = PHYMOD_E_NONE; 391 392 buffer = PHYMOD_MALLOC(sizeof(uint32_t) * buffer_size, "buffer"); 393 if (NULL == buffer) { 394 return PHYMOD_E_MEMORY; 395 } 396 PHYMOD_MEMSET(buffer, 0, sizeof(uint32_t) * buffer_size); 397 398 /*enable eyescan*/ 399 if(PHYMOD_EYESCAN_F_PROCESS_GET(flags)) { 400 401 rv = eagle_phy_meas_lowber_eye (&(phy->access), eyescan_options, buffer); 402 if (rv < 0) { 403 goto cleanup; 404 } 405 rv = eagle_phy_display_lowber_eye (&(phy->access), eyescan_options, buffer); 406 if (rv < 0) { 407 goto cleanup; 408 } 409 } 410 if (buffer != NULL) { 411 PHYMOD_FREE(buffer); 412 } 413 414 if(PHYMOD_EYESCAN_F_DONE_GET(flags)) { 415 PHYMOD_IF_ERR_RETURN(eagle_tsc_pmd_uc_cmd(&(phy->access), CMD_CAPTURE_BER_END, 0, 2000)); 416 } 417 418 return PHYMOD_E_NONE; 419 420 cleanup: 421 if (buffer != NULL) { 422 PHYMOD_FREE(buffer); 423 } 424 425 return rv; 426 } 427 428 int eagle_diagnostics_eye_margin_proj( const phymod_phy_access_t* phy, uint32_t flags, 429 const phymod_phy_eyescan_options_t* eyescan_options) { 430 #ifdef SERDES_API_FLOATING_POINT 431 int osr_mode; 432 USR_DOUBLE data_rate, data_rate_in_Mhz; 433 struct eagle_tsc_uc_core_config_st core_cfg; 434 phymod_phy_access_t phy_copy; 435 int start_lane, num_lane, i, found=0; 436 437 if(PHYMOD_EYESCAN_F_PROCESS_GET(flags)) { 438 PHYMOD_IF_ERR_RETURN 439 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 440 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 441 for (i = 0; i < num_lane; i++) { 442 phy_copy.access.lane_mask = 1 << (start_lane + i); 443 444 if (found == 0) { 445 PHYMOD_IF_ERR_RETURN(eagle_tsc_get_uc_core_config (&(phy_copy.access), &core_cfg)); 446 PHYMOD_IF_ERR_RETURN(eagle_osr_mode_get(&phy_copy.access, &osr_mode)); 447 data_rate = (core_cfg.vco_rate_in_Mhz * 1000.0 * 1000.0) / (1<<osr_mode); 448 data_rate_in_Mhz = (core_cfg.vco_rate_in_Mhz) / (1<<osr_mode); 449 found = 1; 450 } 451 if(num_lane > 1) { 452 PHYMOD_DIAG_OUT((" l=%0d, data rate = %fMHz\n", i, data_rate_in_Mhz)); 453 } else { 454 PHYMOD_DIAG_OUT((" data rate = %fMHz\n", data_rate_in_Mhz)); 455 } 456 eagle_tsc_eye_margin_proj(&phy_copy.access, data_rate, eyescan_options->ber_proj_scan_mode, 457 eyescan_options->ber_proj_timer_cnt, eyescan_options->ber_proj_err_cnt); 458 } 459 } 460 #else 461 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("BER Proj is supported with SERDES_API_FLOATING_POINT only\n"))); 462 #endif 463 return PHYMOD_E_NONE; 464 } 465 466 int eagle_phy_eyescan_run(const phymod_phy_access_t* phy, 467 uint32_t flags, 468 phymod_eyescan_mode_t mode, 469 const phymod_phy_eyescan_options_t* eyescan_options) 470 { 471 /* If stage isn't set - perform all stages*/ 472 if(!PHYMOD_EYESCAN_F_ENABLE_GET(flags) 473 && !PHYMOD_EYESCAN_F_PROCESS_GET(flags) 474 && !PHYMOD_EYESCAN_F_DONE_GET(flags)) 475 { 476 PHYMOD_EYESCAN_F_ENABLE_SET(flags); 477 PHYMOD_EYESCAN_F_PROCESS_SET(flags); 478 PHYMOD_EYESCAN_F_DONE_SET(flags); 479 } 480 481 482 switch(mode) { 483 case phymodEyescanModeFast: 484 return eagle_diagnostics_eyescan_run_uc(phy, flags); 485 case phymodEyescanModeLowBER: 486 return eagle_diagnostics_eyescan_run_lowber(phy, flags, eyescan_options); 487 case phymodEyescanModeBERProj: 488 return eagle_diagnostics_eye_margin_proj(phy, flags, eyescan_options); 489 default: 490 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("unsupported eyescan mode %u"), mode)); 491 } 492 } 493 494 /*phymod, internal enum mappings*/ 495 STATIC 496 int _eagle_prbs_poly_phymod_to_eagle(phymod_prbs_poly_t phymod_poly, enum srds_prbs_polynomial_enum *eagle_poly) 497 { 498 switch(phymod_poly){ 499 case phymodPrbsPoly7: 500 *eagle_poly = PRBS_7; 501 break; 502 case phymodPrbsPoly9: 503 *eagle_poly = PRBS_9; 504 break; 505 case phymodPrbsPoly11: 506 *eagle_poly = PRBS_11; 507 break; 508 case phymodPrbsPoly15: 509 *eagle_poly = PRBS_15; 510 break; 511 case phymodPrbsPoly23: 512 *eagle_poly = PRBS_23; 513 break; 514 case phymodPrbsPoly31: 515 *eagle_poly = PRBS_31; 516 break; 517 case phymodPrbsPoly58: 518 *eagle_poly = PRBS_58; 519 break; 520 default: 521 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("unsupported poly for tsce %u"), phymod_poly)); 522 } 523 return PHYMOD_E_NONE; 524 } 525 526 STATIC 527 int _eagle_prbs_poly_tsce_to_phymod(eagle_prbs_polynomial_type_t tsce_poly, phymod_prbs_poly_t *phymod_poly) 528 { 529 switch(tsce_poly){ 530 case EAGLE_PRBS_POLYNOMIAL_7: 531 *phymod_poly = phymodPrbsPoly7; 532 break; 533 case EAGLE_PRBS_POLYNOMIAL_9: 534 *phymod_poly = phymodPrbsPoly9; 535 break; 536 case EAGLE_PRBS_POLYNOMIAL_11: 537 *phymod_poly = phymodPrbsPoly11; 538 break; 539 case EAGLE_PRBS_POLYNOMIAL_15: 540 *phymod_poly = phymodPrbsPoly15; 541 break; 542 case EAGLE_PRBS_POLYNOMIAL_23: 543 *phymod_poly = phymodPrbsPoly23; 544 break; 545 case EAGLE_PRBS_POLYNOMIAL_31: 546 *phymod_poly = phymodPrbsPoly31; 547 break; 548 case EAGLE_PRBS_POLYNOMIAL_58: 549 *phymod_poly = phymodPrbsPoly58; 550 break; 551 default: 552 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("uknown poly %u"), tsce_poly)); 553 } 554 return PHYMOD_E_NONE; 555 } 556 557 int eagle_phy_pmd_info_dump(const phymod_phy_access_t* phy, const char* type) 558 { 559 int start_lane, num_lane; 560 phymod_phy_access_t phy_copy; 561 int i = 0; 562 /* 563 int j = 0; 564 struct eagle_tsc_detailed_lane_status_st lane_st[4]; 565 */ 566 uint32_t cmd_type; 567 uint8_t trace_mem[768]; 568 569 if (!type) { 570 cmd_type = (uint32_t)TEMOD_DIAG_STATE; 571 } else if (!PHYMOD_STRCMP(type, "ber")) { 572 cmd_type = (uint32_t)TEMOD_DIAG_BER; 573 } else if (!PHYMOD_STRCMP(type, "config")) { 574 cmd_type = (uint32_t)TEMOD_DIAG_CFG; 575 } else if (!PHYMOD_STRCMP(type, "CL72")) { 576 cmd_type = (uint32_t)TEMOD_DIAG_CL72; 577 } else if (!PHYMOD_STRCMP(type, "debug")) { 578 cmd_type = (uint32_t)TEMOD_DIAG_DEBUG; 579 } else if (!PHYMOD_STRCMP(type, "STD")) { 580 cmd_type = (uint32_t)TEMOD_DIAG_DSC_STD; 581 } else { 582 cmd_type = (uint32_t)TEMOD_DIAG_STATE; 583 } 584 585 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 586 587 /*next figure out the lane num and start_lane based on the input*/ 588 PHYMOD_IF_ERR_RETURN 589 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 590 for (i = 0; i < num_lane; i++) { 591 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 592 593 switch (cmd_type) { 594 case TEMOD_DIAG_CFG: 595 PHYMOD_IF_ERR_RETURN 596 (eagle_tsc_display_core_config(&phy_copy.access)); 597 PHYMOD_IF_ERR_RETURN 598 (eagle_tsc_display_lane_config(&phy_copy.access)); 599 break; 600 601 case TEMOD_DIAG_CL72: 602 PHYMOD_IF_ERR_RETURN 603 (eagle_tsc_display_cl72_status(&phy_copy.access)); 604 break; 605 606 case TEMOD_DIAG_DEBUG: 607 PHYMOD_IF_ERR_RETURN 608 (eagle_tsc_display_lane_debug_status(&phy_copy.access)); 609 break; 610 611 case TEMOD_DIAG_BER: 612 break; 613 614 case TEMOD_DIAG_STATE: 615 case TEMOD_DIAG_DSC_STD: 616 default: 617 PHYMOD_DIAG_OUT((" +--------------------------------------------------------------------+\n")); 618 PHYMOD_DIAG_OUT((" | DSC Phy: 0x%03x lane_mask: 0x%02x |\n", phy->access.addr, phy->access.lane_mask)); 619 PHYMOD_DIAG_OUT((" +--------------------------------------------------------------------+\n")); 620 PHYMOD_IF_ERR_RETURN 621 (eagle_tsc_display_core_state(&phy_copy.access)); 622 PHYMOD_IF_ERR_RETURN 623 (eagle_tsc_display_lane_state_hdr(&phy_copy.access)); 624 PHYMOD_IF_ERR_RETURN 625 (eagle_tsc_display_lane_state(&phy_copy.access)); 626 /* 627 NOT SUPPORTED YET in EAGle: eagle_tsc_log_full_pmd_state and eagle_tsc_disp_full_pmd_state 628 for (j = 0; j < 4; j++) { 629 PHYMOD_IF_ERR_RETURN 630 (eagle_tsc_log_full_pmd_state(&phy_copy.access, &lane_st[j])); 631 } 632 PHYMOD_IF_ERR_RETURN 633 (eagle_tsc_disp_full_pmd_state(&phy_copy.access, lane_st, 4)); 634 */ 635 PHYMOD_IF_ERR_RETURN 636 (eagle_tsc_read_event_log((&phy_copy.access), trace_mem, 2)); 637 break; 638 } 639 } 640 641 return PHYMOD_E_NONE; 642 } 643 644 645 int eagle_phy_prbs_config_get(const phymod_phy_access_t* phy, uint32_t flags , phymod_prbs_t* prbs) 646 { 647 648 phymod_prbs_t config_tmp; 649 eagle_prbs_polynomial_type_t tsce_poly; 650 651 if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 652 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_inv_data_get(&phy->access, &config_tmp.invert)); 653 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_poly_get(&phy->access, &tsce_poly)); 654 PHYMOD_IF_ERR_RETURN(_eagle_prbs_poly_tsce_to_phymod(tsce_poly, &config_tmp.poly)); 655 prbs->invert = config_tmp.invert; 656 prbs->poly = config_tmp.poly; 657 } else if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 658 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_inv_data_get(&phy->access, &config_tmp.invert)); 659 PHYMOD_IF_ERR_RETURN(eagle_prbs_rx_poly_get(&phy->access, &tsce_poly)); 660 PHYMOD_IF_ERR_RETURN(_eagle_prbs_poly_tsce_to_phymod(tsce_poly, &config_tmp.poly)); 661 prbs->invert = config_tmp.invert; 662 prbs->poly = config_tmp.poly; 663 } else { 664 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_inv_data_get(&phy->access, &config_tmp.invert)); 665 PHYMOD_IF_ERR_RETURN(eagle_prbs_tx_poly_get(&phy->access, &tsce_poly)); 666 PHYMOD_IF_ERR_RETURN(_eagle_prbs_poly_tsce_to_phymod(tsce_poly, &config_tmp.poly)); 667 prbs->invert = config_tmp.invert; 668 prbs->poly = config_tmp.poly; 669 } 670 return PHYMOD_E_NONE; 671 672 673 } 674 675 int eagle_phy_prbs_config_set(const phymod_phy_access_t* phy, uint32_t flags , phymod_prbs_t* prbs) 676 { 677 678 679 enum srds_prbs_polynomial_enum eagle_poly; 680 PHYMOD_IF_ERR_RETURN(_eagle_prbs_poly_phymod_to_eagle(prbs->poly, &eagle_poly)); 681 /*first check which direction */ 682 if (PHYMOD_PRBS_DIRECTION_RX_GET(flags)) { 683 PHYMOD_IF_ERR_RETURN 684 (eagle_tsc_config_rx_prbs(&phy->access, eagle_poly, PRBS_INITIAL_SEED_HYSTERESIS, prbs->invert)); 685 } else if (PHYMOD_PRBS_DIRECTION_TX_GET(flags)) { 686 PHYMOD_IF_ERR_RETURN 687 (eagle_tsc_config_tx_prbs(&phy->access, eagle_poly, prbs->invert)); 688 } else { 689 PHYMOD_IF_ERR_RETURN 690 (eagle_tsc_config_rx_prbs(&phy->access, eagle_poly, PRBS_INITIAL_SEED_HYSTERESIS, prbs->invert)); 691 PHYMOD_IF_ERR_RETURN 692 (eagle_tsc_config_tx_prbs(&phy->access, eagle_poly, prbs->invert)); 693 } 694 695 return PHYMOD_E_NONE; 696 697 } 698 699 700 701 #endif /* PHYMOD_EAGLE_SUPPORT */