eagle.c (45841B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_dispatch.h> 13 #include <phymod/phymod_util.h> 14 #include <phymod/chip/bcmi_eagle_xgxs_defs.h> 15 #include <phymod/chip/eagle_common.h> 16 17 #include "../../eagle/tier1/eagle_tsc_enum.h" 18 #include "../../eagle/tier1/eagle_cfg_seq.h" 19 #include "../../eagle/tier1/eagle_tsc_common.h" 20 #include "../../eagle/tier1/eagle_tsc_interface.h" 21 #include "../../eagle/tier1/eagle_tsc_dependencies.h" 22 /* #include "../../eagle/tier1/eagle_tsc_common_enum.h" */ 23 24 #define EAGLE_ID0 0 25 #define EAGLE_ID1 0 26 #define EAGLE_MODEL 0x1a 27 #define EAGLE_REV_MASK 0x0 28 #define TSCE_PHY_ALL_LANES 0xf 29 #define TSCE_PMD_CRC_UCODE 0 30 31 #define TSCE_CORE_TO_PHY_ACCESS(_phy_access, _core_access) \ 32 do{\ 33 PHYMOD_MEMCPY(&(_phy_access)->access, &(_core_access)->access, sizeof((_phy_access)->access));\ 34 (_phy_access)->type = (_core_access)->type; \ 35 (_phy_access)->port_loc = (_core_access)->port_loc; \ 36 (_phy_access)->device_op_mode = (_core_access)->device_op_mode; \ 37 (_phy_access)->access.lane_mask = TSCE_PHY_ALL_LANES; \ 38 }while(0) 39 40 #define TSCE_NOF_DFES 9 41 #define TSCE_NOF_LANES_IN_CORE 4 42 extern unsigned char tsce_ucode[]; 43 extern unsigned short tsce_ucode_len; 44 45 46 47 int eagle_phy_firmware_core_config_set(const phymod_phy_access_t* phy, phymod_firmware_core_config_t fw_config) 48 { 49 struct eagle_tsc_uc_core_config_st serdes_firmware_core_config; 50 PHYMOD_MEMSET(&serdes_firmware_core_config, 0, sizeof(serdes_firmware_core_config)); 51 serdes_firmware_core_config.field.core_cfg_from_pcs = fw_config.CoreConfigFromPCS; 52 serdes_firmware_core_config.field.vco_rate = fw_config.VcoRate; 53 PHYMOD_IF_ERR_RETURN(eagle_tsc_set_uc_core_config(&phy->access, serdes_firmware_core_config)); 54 return PHYMOD_E_NONE; 55 } 56 57 58 int eagle_phy_firmware_core_config_get(const phymod_phy_access_t* phy, phymod_firmware_core_config_t* fw_config) 59 { 60 struct eagle_tsc_uc_core_config_st serdes_firmware_core_config; 61 PHYMOD_IF_ERR_RETURN(eagle_tsc_get_uc_core_config(&phy->access, &serdes_firmware_core_config)); 62 PHYMOD_MEMSET(fw_config, 0, sizeof(*fw_config)); 63 fw_config->CoreConfigFromPCS = serdes_firmware_core_config.field.core_cfg_from_pcs; 64 fw_config->VcoRate = serdes_firmware_core_config.field.vco_rate; 65 return PHYMOD_E_NONE; 66 } 67 68 69 int eagle_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_config) 70 { 71 struct eagle_tsc_uc_lane_config_st serdes_firmware_config; 72 PHYMOD_IF_ERR_RETURN(eagle_tsc_get_uc_lane_cfg(&phy->access, &serdes_firmware_config)); 73 PHYMOD_MEMSET(fw_config, 0, sizeof(*fw_config)); 74 fw_config->LaneConfigFromPCS = serdes_firmware_config.field.lane_cfg_from_pcs; 75 fw_config->AnEnabled = serdes_firmware_config.field.an_enabled; 76 fw_config->DfeOn = serdes_firmware_config.field.dfe_on; 77 fw_config->ForceBrDfe = serdes_firmware_config.field.force_brdfe_on; 78 fw_config->Cl72AutoPolEn = serdes_firmware_config.field.cl72_auto_polarity_en; 79 fw_config->Cl72RestTO = serdes_firmware_config.field.cl72_restart_timeout_en; 80 fw_config->ScramblingDisable = serdes_firmware_config.field.scrambling_dis; 81 fw_config->UnreliableLos = serdes_firmware_config.field.unreliable_los; 82 fw_config->MediaType = serdes_firmware_config.field.media_type; 83 84 return PHYMOD_E_NONE; 85 } 86 87 int _eagle_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 88 { 89 struct eagle_tsc_uc_lane_config_st serdes_firmware_config; 90 serdes_firmware_config.field.lane_cfg_from_pcs = fw_config.LaneConfigFromPCS; 91 serdes_firmware_config.field.an_enabled = fw_config.AnEnabled; 92 serdes_firmware_config.field.dfe_on = fw_config.DfeOn; 93 serdes_firmware_config.field.force_brdfe_on = fw_config.ForceBrDfe; 94 serdes_firmware_config.field.cl72_auto_polarity_en = fw_config.Cl72AutoPolEn; 95 serdes_firmware_config.field.cl72_restart_timeout_en = fw_config.Cl72RestTO; 96 serdes_firmware_config.field.scrambling_dis = fw_config.ScramblingDisable; 97 serdes_firmware_config.field.unreliable_los = fw_config.UnreliableLos; 98 serdes_firmware_config.field.media_type = fw_config.MediaType; 99 PHYMOD_IF_ERR_RETURN(eagle_tsc_set_uc_lane_cfg(&phy->access, serdes_firmware_config)); 100 return PHYMOD_E_NONE; 101 } 102 103 int eagle_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 104 { 105 PHYMOD_IF_ERR_RETURN 106 (eagle_lane_soft_reset_release(&phy->access, 0)); 107 108 PHYMOD_IF_ERR_RETURN 109 (_eagle_phy_firmware_lane_config_set(phy, fw_config)); 110 111 PHYMOD_IF_ERR_RETURN 112 (eagle_lane_soft_reset_release(&phy->access, 1)); 113 return PHYMOD_E_NONE; 114 } 115 116 int _eagle_pll_multiplier_get(enum eagle_tsc_pll_enum pll_div, uint32_t *pll_multiplier) 117 { 118 switch (pll_div) { 119 case EAGLE_TSC_pll_div_46x: 120 *pll_multiplier = 460; 121 break; 122 case EAGLE_TSC_pll_div_72x: 123 *pll_multiplier = 720; 124 break; 125 case EAGLE_TSC_pll_div_40x: 126 *pll_multiplier = 400; 127 break; 128 case EAGLE_TSC_pll_div_42x: 129 *pll_multiplier = 420; 130 break; 131 /* 132 case 0x4: 133 *pll_multiplier = 580; 134 break; 135 */ 136 case EAGLE_TSC_pll_div_50x: 137 *pll_multiplier = 500; 138 break; 139 case EAGLE_TSC_pll_div_52x: 140 *pll_multiplier = 520; 141 break; 142 /* 143 case 0x7: 144 *pll_multiplier = 540; 145 break; 146 */ 147 case EAGLE_TSC_pll_div_60x: 148 *pll_multiplier = 600; 149 break; 150 case EAGLE_TSC_pll_div_64x: 151 *pll_multiplier = 640; 152 break; 153 case EAGLE_TSC_pll_div_66x: 154 *pll_multiplier = 660; 155 break; 156 case EAGLE_TSC_pll_div_68x: 157 *pll_multiplier = 680; 158 break; 159 case EAGLE_TSC_pll_div_70x: 160 *pll_multiplier = 700; 161 break; 162 case EAGLE_TSC_pll_div_80x: 163 *pll_multiplier = 800; 164 break; 165 case EAGLE_TSC_pll_div_92x: 166 *pll_multiplier = 920; 167 break; 168 case EAGLE_TSC_pll_div_100x: 169 *pll_multiplier = 1000; 170 break; 171 case EAGLE_TSC_pll_div_82p5x: 172 *pll_multiplier = 825; 173 break; 174 case EAGLE_TSC_pll_div_87p5x: 175 *pll_multiplier = 875; 176 break; 177 case EAGLE_TSC_pll_div_73p6x: 178 *pll_multiplier = 736; 179 break; 180 case EAGLE_TSC_pll_div_36p8x: 181 *pll_multiplier = 368; 182 break; 183 /* 184 case EAGLE_TSC_pll_div_199p04x: 185 *pll_multiplier = 1990.4; 186 break; 187 */ 188 default: 189 *pll_multiplier = 660; 190 break; 191 } 192 return PHYMOD_E_NONE; 193 } 194 195 int eagle_core_identify(const phymod_core_access_t* core, uint32_t core_id, uint32_t* is_identified) 196 { 197 const phymod_access_t *pm_acc = &core->access; 198 eagle_rev_id0_t rev_id0; 199 eagle_rev_id1_t rev_id1; 200 201 *is_identified = 0; 202 203 /* PHY IDs match - now check model */ 204 PHYMOD_IF_ERR_RETURN(eagle_tsc_identify(pm_acc, &rev_id0, &rev_id1)); 205 if (rev_id0.revid_model == EAGLE_MODEL) { 206 *is_identified = 1; 207 } 208 209 return PHYMOD_E_NONE; 210 } 211 212 int eagle_core_info_get(const phymod_core_access_t* core, phymod_core_info_t* info) 213 { 214 215 return (1); 216 217 } 218 219 220 /* 221 * set lane swapping for core 222 * The tx swap is composed of PCS swap and after that the PMD swap. 223 * The rx swap is composed just by PCS swap 224 */ 225 int eagle_core_lane_map_set(const phymod_core_access_t* core, const phymod_lane_map_t* lane_map) 226 { 227 228 phymod_phy_access_t phy_access; 229 uint32_t lane, pmd_tx_map =0; 230 231 for( lane = 0 ; lane < TSCE_NOF_LANES_IN_CORE ; lane++){ 232 pmd_tx_map |= ((lane_map->lane_map_tx[lane]) & 3) << (lane*4); 233 } 234 235 TSCE_CORE_TO_PHY_ACCESS(&phy_access, core); 236 PHYMOD_IF_ERR_RETURN 237 (eagle_pmd_lane_swap(&phy_access.access, pmd_tx_map)); 238 239 return PHYMOD_E_NONE; 240 241 } 242 243 int eagle_core_lane_map_get(const phymod_core_access_t* core, phymod_lane_map_t* lane_map) 244 { 245 246 int lane; 247 uint32_t pmd_swap = 0; 248 PHYMOD_IF_ERR_RETURN(eagle_pmd_lane_swap_tx_get(&core->access, &pmd_swap)); 249 for( lane = 0 ; lane < TSCE_NOF_LANES_IN_CORE ; lane++){ 250 /*decode each lane from four bits*/ 251 /*considering the pcs lane swap: tx_map[lane] = pmd_map[pcs_map[lane]]*/ 252 /* lane_map->lane_map_tx[lane] = (pmd_swap>>(lane_map->lane_map_rx[lane]*4)) & TSCE_LANE_SWAP_LANE_MASK; */ 253 lane_map->lane_map_tx[lane] = (pmd_swap>>(lane*4)) & 0x3; 254 /*rx lane map is not supported*/ 255 lane_map->lane_map_rx[lane] = lane; 256 } 257 lane_map->num_of_lanes = TSCE_NOF_LANES_IN_CORE; 258 259 return PHYMOD_E_NONE; 260 261 } 262 263 264 int eagle_core_reset_set(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 265 { 266 267 /* Not supported */ 268 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_core_reset_set)\n")); 269 270 return PHYMOD_E_NONE; 271 272 } 273 274 int eagle_core_reset_get(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t* direction) 275 { 276 277 /* Not supported */ 278 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_core_reset_get) \n")); 279 280 281 return PHYMOD_E_NONE; 282 283 } 284 285 286 int eagle_core_firmware_info_get(const phymod_core_access_t* core, phymod_core_firmware_info_t* fw_info) 287 { 288 289 /* Not supported */ 290 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_core_firmware_info_get) \n")); 291 292 return PHYMOD_E_NONE; 293 294 } 295 296 297 int eagle_phy_firmware_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_mode) 298 { 299 300 301 /* Place your code here */ 302 303 304 return PHYMOD_E_NONE; 305 306 } 307 308 int eagle_phy_firmware_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_mode) 309 { 310 311 312 /* Place your code here */ 313 314 315 return PHYMOD_E_NONE; 316 317 } 318 319 320 int eagle_core_pll_sequencer_restart(const phymod_core_access_t* core, uint32_t flags, phymod_sequencer_operation_t operation) 321 { 322 323 /* Not supported */ 324 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_core_pll_sequencer_restart)\n")); 325 326 return PHYMOD_E_NONE; 327 328 } 329 330 int eagle_core_wait_event(const phymod_core_access_t* core, phymod_core_event_t event, uint32_t timeout) 331 { 332 333 /* Not supported */ 334 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_core_wait_event) \n")); 335 336 337 return PHYMOD_E_NONE; 338 339 } 340 341 /* reset rx sequencer 342 * flags - unused parameter 343 */ 344 int eagle_phy_rx_restart(const phymod_phy_access_t* phy) 345 { 346 PHYMOD_IF_ERR_RETURN(eagle_tsc_rx_restart(&phy->access, 1)); 347 return PHYMOD_E_NONE; 348 } 349 350 int eagle_phy_polarity_set(const phymod_phy_access_t* phy, const phymod_polarity_t* polarity) 351 { 352 353 PHYMOD_IF_ERR_RETURN 354 (eagle_tx_rx_polarity_set(&phy->access, polarity->tx_polarity, polarity->rx_polarity)); 355 356 return PHYMOD_E_NONE; 357 } 358 359 int eagle_phy_polarity_get(const phymod_phy_access_t* phy, phymod_polarity_t* polarity) 360 { 361 362 PHYMOD_IF_ERR_RETURN 363 (eagle_tx_rx_polarity_get(&phy->access, &polarity->tx_polarity, &polarity->rx_polarity)); 364 365 return PHYMOD_E_NONE; 366 367 } 368 369 370 int eagle_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx) 371 { 372 373 374 PHYMOD_IF_ERR_RETURN 375 (eagle_tsc_write_tx_afe(&phy->access, TX_AFE_PRE, (int8_t)tx->pre)); 376 PHYMOD_IF_ERR_RETURN 377 (eagle_tsc_write_tx_afe(&phy->access, TX_AFE_MAIN, (int8_t)tx->main)); 378 PHYMOD_IF_ERR_RETURN 379 (eagle_tsc_write_tx_afe(&phy->access, TX_AFE_POST1, (int8_t)tx->post)); 380 PHYMOD_IF_ERR_RETURN 381 (eagle_tsc_write_tx_afe(&phy->access, TX_AFE_POST2, (int8_t)tx->post2)); 382 PHYMOD_IF_ERR_RETURN 383 (eagle_tsc_write_tx_afe(&phy->access, TX_AFE_POST3, (int8_t)tx->post3)); 384 PHYMOD_IF_ERR_RETURN 385 (eagle_tsc_write_tx_afe(&phy->access, TX_AFE_AMP, (int8_t)tx->amp)); 386 387 388 return PHYMOD_E_NONE; 389 390 } 391 392 int eagle_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx) 393 { 394 int8_t value = 0; 395 396 PHYMOD_IF_ERR_RETURN 397 (eagle_tsc_read_tx_afe(&phy->access, TX_AFE_PRE, &value)); 398 tx->pre = value; 399 PHYMOD_IF_ERR_RETURN 400 (eagle_tsc_read_tx_afe(&phy->access, TX_AFE_MAIN, &value)); 401 tx->main = value; 402 PHYMOD_IF_ERR_RETURN 403 (eagle_tsc_read_tx_afe(&phy->access, TX_AFE_POST1, &value)); 404 tx->post = value; 405 PHYMOD_IF_ERR_RETURN 406 (eagle_tsc_read_tx_afe(&phy->access, TX_AFE_POST2, &value)); 407 tx->post2 = value; 408 PHYMOD_IF_ERR_RETURN 409 (eagle_tsc_read_tx_afe(&phy->access, TX_AFE_POST3, &value)); 410 tx->post3 = value; 411 PHYMOD_IF_ERR_RETURN 412 (eagle_tsc_read_tx_afe(&phy->access, TX_AFE_AMP, &value)); 413 tx->amp = value; 414 415 return PHYMOD_E_NONE; 416 417 } 418 419 420 int eagle_phy_media_type_tx_get(const phymod_phy_access_t* phy, phymod_media_typed_t media, phymod_tx_t* tx) 421 { 422 423 424 switch (media) { 425 case phymodMediaTypeChipToChip: 426 tx->pre = 0xc; 427 tx->main = 0x64; 428 tx->post = 0x0; 429 tx->post2 = 0x0; 430 tx->post3 = 0x0; 431 tx->amp = 0xc; 432 break; 433 case phymodMediaTypeShort: 434 tx->pre = 0xc; 435 tx->main = 0x64; 436 tx->post = 0x0; 437 tx->post2 = 0x0; 438 tx->post3 = 0x0; 439 tx->amp = 0xc; 440 break; 441 case phymodMediaTypeMid: 442 tx->pre = 0xc; 443 tx->main = 0x64; 444 tx->post = 0x0; 445 tx->post2 = 0x0; 446 tx->post3 = 0x0; 447 tx->amp = 0xc; 448 break; 449 case phymodMediaTypeLong: 450 tx->pre = 0xc; 451 tx->main = 0x64; 452 tx->post = 0x0; 453 tx->post2 = 0x0; 454 tx->post3 = 0x0; 455 tx->amp = 0xc; 456 break; 457 default: 458 tx->pre = 0xc; 459 tx->main = 0x64; 460 tx->post = 0x0; 461 tx->post2 = 0x0; 462 tx->post3 = 0x0; 463 tx->amp = 0xc; 464 break; 465 } 466 467 468 return PHYMOD_E_NONE; 469 470 } 471 472 473 int eagle_phy_tx_override_set(const phymod_phy_access_t* phy, const phymod_tx_override_t* tx_override) 474 { 475 476 477 PHYMOD_IF_ERR_RETURN 478 (eagle_tsc_tx_pi_freq_override(&phy->access, 479 tx_override->phase_interpolator.enable, 480 tx_override->phase_interpolator.value)); 481 482 return PHYMOD_E_NONE; 483 484 } 485 486 int eagle_phy_tx_override_get(const phymod_phy_access_t* phy, phymod_tx_override_t* tx_override) 487 { 488 489 490 /* 491 PHYMOD_IF_ERR_RETURN 492 (temod_tx_pi_control_get(&phy->access, &tx_override->phase_interpolator.value)); 493 */ 494 495 return PHYMOD_E_NONE; 496 497 } 498 499 500 int eagle_phy_rx_set(const phymod_phy_access_t* phy, const phymod_rx_t* rx) 501 { 502 503 uint32_t i; 504 505 /*params check*/ 506 if((rx->num_of_dfe_taps == 0) || (rx->num_of_dfe_taps < TSCE_NOF_DFES)){ 507 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal number of DFEs to set %u"), rx->num_of_dfe_taps)); 508 } 509 510 /*vga set*/ 511 if (rx->vga.enable) { 512 /* first stop the rx adaption */ 513 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 1)); 514 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_VGA, rx->vga.value)); 515 } else { 516 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 0)); 517 } 518 519 /*dfe set*/ 520 for (i = 0 ; i < rx->num_of_dfe_taps ; i++){ 521 if(rx->dfe[i].enable){ 522 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 1)); 523 switch (i) { 524 case 0: 525 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_DFE1, rx->dfe[i].value)); 526 break; 527 case 1: 528 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_DFE2, rx->dfe[i].value)); 529 break; 530 case 2: 531 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_DFE3, rx->dfe[i].value)); 532 break; 533 case 3: 534 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_DFE4, rx->dfe[i].value)); 535 break; 536 case 4: 537 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_DFE5, rx->dfe[i].value)); 538 break; 539 default: 540 return PHYMOD_E_PARAM; 541 } 542 } else { 543 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 0)); 544 } 545 546 547 } 548 549 /*peaking filter set*/ 550 if(rx->peaking_filter.enable){ 551 /* first stop the rx adaption */ 552 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 1)); 553 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_PF, rx->peaking_filter.value)); 554 } else { 555 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 0)); 556 } 557 558 if(rx->low_freq_peaking_filter.enable){ 559 /* first stop the rx adaption */ 560 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 1)); 561 PHYMOD_IF_ERR_RETURN(eagle_tsc_write_rx_afe(&phy->access, RX_AFE_PF2, rx->low_freq_peaking_filter.value)); 562 } else { 563 PHYMOD_IF_ERR_RETURN(eagle_tsc_stop_rx_adaptation(&phy->access, 0)); 564 } 565 566 return PHYMOD_E_NONE; 567 568 } 569 570 int eagle_phy_rx_get(const phymod_phy_access_t* phy, phymod_rx_t* rx) 571 { 572 int8_t val; 573 574 PHYMOD_IF_ERR_RETURN 575 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_PF, &val)); 576 rx->peaking_filter.value = val; 577 578 PHYMOD_IF_ERR_RETURN 579 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_PF2, &val)); 580 rx->low_freq_peaking_filter.value = val; 581 582 PHYMOD_IF_ERR_RETURN 583 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_VGA, &val)); 584 rx->vga.value = val; 585 586 PHYMOD_IF_ERR_RETURN 587 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_DFE1, &val)); 588 rx->dfe[0].value = val; 589 590 PHYMOD_IF_ERR_RETURN 591 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_DFE2, &val)); 592 rx->dfe[1].value = val; 593 594 PHYMOD_IF_ERR_RETURN 595 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_DFE3, &val)); 596 rx->dfe[2].value = val; 597 598 PHYMOD_IF_ERR_RETURN 599 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_DFE4, &val)); 600 rx->dfe[3].value = val; 601 602 PHYMOD_IF_ERR_RETURN 603 (eagle_tsc_read_rx_afe(&phy->access, RX_AFE_DFE5, &val)); 604 rx->dfe[4].value = val; 605 606 rx->num_of_dfe_taps = 5; 607 rx->dfe[0].enable = 1; 608 rx->dfe[1].enable = 1; 609 rx->dfe[2].enable = 1; 610 rx->dfe[3].enable = 1; 611 rx->dfe[4].enable = 1; 612 rx->vga.enable = 1; 613 rx->low_freq_peaking_filter.enable = 1; 614 rx->peaking_filter.enable = 1; 615 616 return PHYMOD_E_NONE; 617 618 } 619 620 621 int eagle_phy_reset_set(const phymod_phy_access_t* phy, const phymod_phy_reset_t* reset) 622 { 623 624 switch (reset->rx) { 625 case phymodResetDirectionIn: 626 PHYMOD_IF_ERR_RETURN(eagle_force_rx_set_rst(&phy->access, 0x1)); 627 break; 628 case phymodResetDirectionOut: 629 PHYMOD_IF_ERR_RETURN(eagle_force_rx_set_rst(&phy->access, 0x0)); 630 break; 631 case phymodResetDirectionInOut: 632 PHYMOD_IF_ERR_RETURN(eagle_force_rx_set_rst(&phy->access, 0x1)); 633 PHYMOD_USLEEP(10); 634 PHYMOD_IF_ERR_RETURN(eagle_force_rx_set_rst(&phy->access, 0x0)); 635 break; 636 default: 637 break; 638 } 639 switch (reset->tx) { 640 case phymodResetDirectionIn: 641 PHYMOD_IF_ERR_RETURN(eagle_force_tx_set_rst(&phy->access, 0x1)); 642 break; 643 case phymodResetDirectionOut: 644 PHYMOD_IF_ERR_RETURN(eagle_force_tx_set_rst(&phy->access, 0x0)); 645 break; 646 case phymodResetDirectionInOut: 647 PHYMOD_IF_ERR_RETURN(eagle_force_tx_set_rst(&phy->access, 0x1)); 648 PHYMOD_USLEEP(10); 649 PHYMOD_IF_ERR_RETURN(eagle_force_tx_set_rst(&phy->access, 0x0)); 650 break; 651 default: 652 break; 653 } 654 655 return PHYMOD_E_NONE; 656 657 } 658 659 int eagle_phy_reset_get(const phymod_phy_access_t* phy, phymod_phy_reset_t* reset) 660 { 661 662 663 uint32_t rst; 664 PHYMOD_IF_ERR_RETURN(eagle_force_tx_get_rst(&phy->access, &rst)); 665 if(rst == 0) { 666 reset->tx = phymodResetDirectionOut; 667 } else { 668 reset->tx = phymodResetDirectionIn; 669 } 670 PHYMOD_IF_ERR_RETURN(eagle_force_rx_get_rst(&phy->access, &rst)); 671 if(rst == 0) { 672 reset->rx = phymodResetDirectionOut; 673 } else { 674 reset->rx = phymodResetDirectionIn; 675 } 676 677 return PHYMOD_E_NONE; 678 679 } 680 681 682 int eagle_phy_power_set(const phymod_phy_access_t* phy, const phymod_phy_power_t* power) 683 { 684 685 enum srds_core_pwrdn_mode_enum mode; 686 mode = PWRDN; 687 /* printf("MODE: %x\n", mode); */ 688 if ((power->tx == phymodPowerOff) && (power->rx == phymodPowerNoChange)) { 689 /*disable tx on the PMD side */ 690 mode = PWRDN_TX; 691 PHYMOD_IF_ERR_RETURN(eagle_tsc_lane_pwrdn(&phy->access, mode)); 692 } 693 if ((power->tx == phymodPowerOn) && (power->rx == phymodPowerNoChange)) { 694 /*enable tx on the PMD side */ 695 PHYMOD_IF_ERR_RETURN(eagle_tsc_pwrdn_set(&phy->access, 1, 0)); 696 } 697 if ((power->tx == phymodPowerNoChange) && (power->rx == phymodPowerOff)) { 698 /*disable rx on the PMD side */ 699 mode = PWRDN_RX; 700 PHYMOD_IF_ERR_RETURN(eagle_tsc_lane_pwrdn(&phy->access, mode)); 701 } 702 if ((power->tx == phymodPowerNoChange) && (power->rx == phymodPowerOn)) { 703 PHYMOD_IF_ERR_RETURN(eagle_tsc_pwrdn_set(&phy->access, 0, 0)); 704 /*enable rx on the PMD side */ 705 } 706 if ((power->tx == phymodPowerOn) && (power->rx == phymodPowerOn)) { 707 mode = PWR_ON; 708 PHYMOD_IF_ERR_RETURN(eagle_tsc_lane_pwrdn(&phy->access, mode)); 709 } 710 if ((power->tx == phymodPowerOff) && (power->rx == phymodPowerOff)) { 711 /* Both Tx and Rx power down */ 712 mode = PWRDN; 713 PHYMOD_IF_ERR_RETURN(eagle_tsc_lane_pwrdn(&phy->access, mode)); 714 } 715 716 return PHYMOD_E_NONE; 717 718 } 719 720 int eagle_phy_power_get(const phymod_phy_access_t* phy, phymod_phy_power_t* power) 721 { 722 723 power_status_t pwrdn; 724 PHYMOD_IF_ERR_RETURN(eagle_tsc_pwrdn_get(&phy->access, &pwrdn)); 725 power->rx = (pwrdn.rx_s_pwrdn == 0)? phymodPowerOn: phymodPowerOff; 726 power->tx = (pwrdn.tx_s_pwrdn == 0)? phymodPowerOn: phymodPowerOff; 727 728 return PHYMOD_E_NONE; 729 730 } 731 732 733 int eagle_phy_tx_disable_set(const phymod_phy_access_t* phy, uint32_t tx_disable) 734 { 735 736 737 /* Place your code here */ 738 739 740 return PHYMOD_E_NONE; 741 742 } 743 744 int eagle_phy_tx_disable_get(const phymod_phy_access_t* phy, uint32_t* tx_disable) 745 { 746 747 748 /* Place your code here */ 749 750 751 return PHYMOD_E_NONE; 752 753 } 754 755 int eagle_phy_tx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t tx_control) 756 { 757 758 switch (tx_control) 759 { 760 case phymodTxSquelchOn: 761 PHYMOD_IF_ERR_RETURN(eagle_tx_lane_control_set(&phy->access, 1)); 762 break; 763 case phymodTxSquelchOff: 764 PHYMOD_IF_ERR_RETURN(eagle_tx_lane_control_set(&phy->access, 0)); 765 break; 766 default: 767 PHYMOD_DEBUG_ERROR(("This control is NOT SUPPORTED!! (eagle_phy_tx_lane_control_set) \n")); 768 break; 769 } 770 771 return PHYMOD_E_NONE; 772 773 } 774 775 int eagle_phy_tx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t* tx_control) 776 { 777 778 uint32_t enable; 779 780 PHYMOD_IF_ERR_RETURN(eagle_tx_lane_control_get(&phy->access, &enable)); 781 782 if(enable){ 783 *tx_control = phymodTxSquelchOn; 784 } else { 785 *tx_control = phymodTxSquelchOff; 786 } 787 788 return PHYMOD_E_NONE; 789 790 } 791 792 /*Rx control*/ 793 int eagle_phy_rx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t rx_control) 794 { 795 796 switch (rx_control) 797 { 798 case phymodRxSquelchOn: 799 PHYMOD_IF_ERR_RETURN(eagle_rx_lane_control_set(&phy->access, 1)); 800 break; 801 case phymodRxSquelchOff: 802 PHYMOD_IF_ERR_RETURN(eagle_rx_lane_control_set(&phy->access, 0)); 803 break; 804 default: 805 PHYMOD_DEBUG_ERROR(("This control is NOT SUPPORTED!! (eagle_phy_rx_lane_control_set) \n")); 806 break; 807 } 808 809 return PHYMOD_E_NONE; 810 811 812 } 813 814 int eagle_phy_rx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t* rx_control) 815 { 816 817 uint32_t enable; 818 819 PHYMOD_IF_ERR_RETURN(eagle_rx_lane_control_get(&phy->access, &enable)); 820 821 if(enable){ 822 *rx_control = phymodRxSquelchOn; 823 } else { 824 *rx_control = phymodRxSquelchOff; 825 } 826 827 return PHYMOD_E_NONE; 828 829 } 830 831 int eagle_phy_interface_config_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_phy_inf_config_t* config) 832 { 833 834 /* phymod_tx_t tx_params; */ 835 enum eagle_tsc_pll_enum current_pll_div=EAGLE_TSC_pll_div_66x; 836 enum eagle_tsc_pll_enum new_pll_div=EAGLE_TSC_pll_div_66x; 837 uint32_t vco_rate; 838 int16_t new_os_mode =-1; 839 phymod_phy_access_t pm_phy_copy; 840 int start_lane, num_lane, i; 841 842 /* sc_table_entry exp_entry; RAVI */ 843 phymod_firmware_lane_config_t firmware_lane_config; 844 phymod_firmware_core_config_t firmware_core_config; 845 846 firmware_lane_config.MediaType = 0; 847 848 /*next program the tx fir taps and driver current based on the input*/ 849 PHYMOD_IF_ERR_RETURN 850 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 851 852 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 853 854 /*Hold the per lne soft reset bit*/ 855 for (i = 0; i < num_lane; i++) { 856 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 857 PHYMOD_IF_ERR_RETURN 858 (eagle_lane_soft_reset_release(&pm_phy_copy.access, 0)); 859 } 860 861 pm_phy_copy.access.lane_mask = 0x1 << start_lane; 862 PHYMOD_IF_ERR_RETURN 863 (eagle_phy_firmware_lane_config_get(&pm_phy_copy, &firmware_lane_config)); 864 865 /*make sure that an and config from pcs is off*/ 866 firmware_core_config.CoreConfigFromPCS = 0; 867 firmware_lane_config.AnEnabled = 0; 868 firmware_lane_config.LaneConfigFromPCS = 0; 869 firmware_lane_config.DfeOn = 0; 870 firmware_lane_config.Cl72RestTO = 1; 871 872 /* No PCS 873 PHYMOD_IF_ERR_RETURN 874 (temod_update_port_mode(&phy->access, (int *) &pll_switch)); 875 */ 876 PHYMOD_IF_ERR_RETURN 877 (eagle_tsc_get_vco(config, &vco_rate, &new_pll_div, &new_os_mode)); 878 879 if(config->data_rate >= 10312) { 880 firmware_lane_config.DfeOn = 1; 881 } 882 883 /* 884 PHYMOD_IF_ERR_RETURN 885 (eagle_pll_mode_get(&pm_phy_copy.access, ¤t_pll_div)); 886 */ 887 PHYMOD_IF_ERR_RETURN 888 (eagle_pll_config_get(&pm_phy_copy.access, ¤t_pll_div)); 889 890 /* new_pll_div already found 891 PHYMOD_IF_ERR_RETURN 892 (temod_plldiv_lkup_get(&phy->access, spd_intf, &new_pll_div)); 893 */ 894 895 /* 896 if(config->device_aux_modes !=NULL){ 897 PHYMOD_IF_ERR_RETURN 898 (_tsce_st_hto_interface_config_set(config->device_aux_modes, start_lane, new_speed_vec, &new_pll_div, &new_os_mode)) ; 899 } 900 */ 901 902 903 904 905 906 /*if pll change is enabled*/ 907 if((current_pll_div != new_pll_div) && (PHYMOD_INTF_F_DONT_TURN_OFF_PLL & flags)){ 908 if(config->interface_type != phymodInterfaceBypass) { 909 /*Terminate the execution of the function*/ 910 PHYMOD_DEBUG_WARN(("PLL has to change for speed_set from %u to %u but DONT_TURN_OFF_PLL flag is enabled \n", 911 (unsigned int)current_pll_div, (unsigned int)new_pll_div)); 912 return PHYMOD_E_NONE; 913 } 914 } 915 /*pll switch is required and expected */ 916 if((current_pll_div != new_pll_div) && !(PHYMOD_INTF_F_DONT_TURN_OFF_PLL & flags)) { 917 /* phymod_access_t tmp_phy_access; */ 918 PHYMOD_IF_ERR_RETURN 919 (eagle_core_soft_reset_release(&pm_phy_copy.access, 0)); 920 921 /*release the uc reset */ 922 #if 0 923 PHYMOD_IF_ERR_RETURN 924 (eagle_tsc_uc_reset(&pm_phy_copy.access ,0)); 925 #endif 926 /*set the PLL divider */ 927 PHYMOD_IF_ERR_RETURN 928 (eagle_tsc_configure_pll(&pm_phy_copy.access, new_pll_div)); 929 /* 930 PHYMOD_IF_ERR_RETURN 931 (eagle_pll_mode_set(&pm_phy_copy.access, new_pll_div)); 932 */ 933 934 /* firmware_core_config.VcoRate = (vco_rate * 16 + 500) / 1000 - 224; */ 935 firmware_core_config.VcoRate = (vco_rate - 5750) / 250 + 1; 936 937 /*change the master port num to the current caller port */ 938 939 /* 940 PHYMOD_IF_ERR_RETURN 941 (temod_master_port_num_set(&phy->access, start_lane)); 942 ////////////////// Do we need PLL reset /////////////// 943 */ 944 #if 0 945 PHYMOD_IF_ERR_RETURN 946 (eagle_pll_reset_enable_set(&pm_phy_copy.access, 1)); 947 #endif 948 /*update the firmware config properly*/ 949 PHYMOD_IF_ERR_RETURN 950 (eagle_phy_firmware_core_config_set(&pm_phy_copy, firmware_core_config)); 951 PHYMOD_IF_ERR_RETURN 952 (eagle_core_soft_reset_release(&pm_phy_copy.access, 1)); 953 } 954 955 /* 956 PHYMOD_IF_ERR_RETURN 957 (temod_set_spd_intf(&phy->access, spd_intf)); 958 */ 959 960 /*change TX parameters if enabled*/ 961 /* 962 if((PHYMOD_IF_F_DONT_OVERIDE_TX_PARAMS & flags) == 0) { 963 PHYMOD_IF_ERR_RETURN 964 (tsce_phy_media_type_tx_get(phy, phymodMediaTypeMid, &tx_params)); 965 } 966 */ 967 for (i = 0; i < num_lane; i++) { 968 pm_phy_copy.access.lane_mask = 0x1 << (start_lane + i); 969 PHYMOD_IF_ERR_RETURN 970 (_eagle_phy_firmware_lane_config_set(&pm_phy_copy, firmware_lane_config)); 971 } 972 973 /*release the per lne soft reset bit*/ 974 for (i = 0; i < num_lane; i++) { 975 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 976 PHYMOD_IF_ERR_RETURN 977 (eagle_lane_soft_reset_release(&pm_phy_copy.access, 1)); 978 } 979 980 PHYMOD_IF_ERR_RETURN 981 (eagle_osr_mode_set(&phy->access, new_os_mode)); 982 983 984 return PHYMOD_E_NONE; 985 986 } 987 988 /*flags- unused parameter*/ 989 int eagle_phy_interface_config_get(const phymod_phy_access_t* phy, 990 uint32_t flags, 991 phymod_ref_clk_t ref_clock, 992 phymod_phy_inf_config_t* config) 993 { 994 int osr_mode; 995 /* uint32_t pll_div; */ 996 enum eagle_tsc_pll_enum pll_div; 997 uint32_t pll_multiplier, refclk; 998 phymod_phy_access_t phy_copy; 999 uint32_t actual_osr, actual_osr_rem; 1000 phymod_osr_mode_t osr_mode_enum; 1001 int start_lane, num_lane; 1002 1003 config->ref_clock = ref_clock; 1004 1005 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1006 PHYMOD_IF_ERR_RETURN 1007 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1008 phy_copy.access.lane_mask = 0x1 << start_lane; 1009 1010 PHYMOD_IF_ERR_RETURN 1011 (eagle_osr_mode_get(&phy->access, &osr_mode)); 1012 /* 1013 PHYMOD_IF_ERR_RETURN 1014 (eagle_pll_mode_get(&phy_copy.access, &pll_div)); 1015 */ 1016 PHYMOD_IF_ERR_RETURN 1017 (eagle_pll_config_get(&phy_copy.access, &pll_div)); 1018 PHYMOD_IF_ERR_RETURN 1019 (_eagle_pll_multiplier_get(pll_div, &pll_multiplier)); 1020 1021 1022 if (ref_clock == phymodRefClk156Mhz) { 1023 refclk = 15625; 1024 } else if (ref_clock == phymodRefClk125Mhz) { 1025 refclk = 12500; 1026 } else { 1027 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INTERNAL, (_PHYMOD_MSG("Unknown refclk"))); 1028 } 1029 1030 1031 PHYMOD_IF_ERR_RETURN(eagle_osr_mode_to_enum(osr_mode, &osr_mode_enum)); 1032 PHYMOD_IF_ERR_RETURN(phymod_osr_mode_to_actual_os(osr_mode_enum, &actual_osr, &actual_osr_rem)); 1033 1034 /* Divide by 1000 is take care of pll_mulitple(by 10) and ref_clk (by 100) */ 1035 config->data_rate = (refclk*pll_multiplier)/(1000*actual_osr); 1036 config->interface_type = phymodInterfaceBypass; 1037 1038 if(osr_mode_enum == phymodOversampleMode2) { 1039 PHYMOD_INTF_MODES_OS2_SET(config); 1040 } 1041 1042 return PHYMOD_E_NONE; 1043 } 1044 1045 1046 int eagle_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en) 1047 { 1048 PHYMOD_IF_ERR_RETURN 1049 (eagle_lane_soft_reset_release(&phy->access, 0)); 1050 PHYMOD_IF_ERR_RETURN 1051 (eagle_clause72_control(&phy->access, cl72_en)); 1052 PHYMOD_IF_ERR_RETURN 1053 (eagle_lane_soft_reset_release(&phy->access, 1)); 1054 1055 return PHYMOD_E_NONE; 1056 1057 } 1058 1059 int eagle_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en) 1060 { 1061 1062 PHYMOD_IF_ERR_RETURN 1063 (eagle_clause72_control_get(&phy->access, cl72_en)); 1064 1065 return PHYMOD_E_NONE; 1066 1067 } 1068 1069 1070 int eagle_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status) 1071 { 1072 1073 1074 uint32_t local_status; 1075 PHYMOD_IF_ERR_RETURN 1076 (eagle_pmd_cl72_receiver_status(&phy->access, &local_status)); 1077 status->locked = local_status; 1078 return PHYMOD_E_NONE; 1079 1080 } 1081 1082 1083 int eagle_phy_autoneg_ability_set(const phymod_phy_access_t* phy, const phymod_autoneg_ability_t* an_ability_set_type) 1084 { 1085 1086 /* Not supported */ 1087 /* PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_phy_autoneg_ability_set) \n")); */ 1088 1089 return PHYMOD_E_NONE; 1090 1091 } 1092 1093 int eagle_phy_autoneg_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type) 1094 { 1095 1096 /* Not supported */ 1097 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_phy_autoneg_ability_get) \n")); 1098 1099 return PHYMOD_E_NONE; 1100 1101 } 1102 1103 1104 int eagle_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 1105 { 1106 1107 /* Not supported */ 1108 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_phy_autoneg_set) \n")); 1109 1110 return PHYMOD_E_NONE; 1111 1112 } 1113 1114 int eagle_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an) 1115 { 1116 1117 /* Not supported */ 1118 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_phy_autoneg_get) \n")); 1119 1120 1121 return PHYMOD_E_NONE; 1122 1123 } 1124 1125 1126 int eagle_phy_autoneg_status_get(const phymod_phy_access_t* phy, phymod_autoneg_status_t* status) 1127 { 1128 1129 /* Not supported */ 1130 PHYMOD_DEBUG_ERROR(("This function is NOT SUPPORTED!! (eagle_phy_autoneg_status_get) \n")); 1131 1132 return PHYMOD_E_NONE; 1133 1134 } 1135 1136 /* load tsce fw. the fw_loader parameter is valid just for external fw load*/ 1137 STATIC 1138 int _eagle_core_firmware_load(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config) 1139 { 1140 /* int wait; */ 1141 1142 switch(init_config->firmware_load_method){ 1143 case phymodFirmwareLoadMethodInternal: 1144 PHYMOD_IF_ERR_RETURN(eagle_tsc_ucode_mdio_load(&core->access, tsce_ucode, tsce_ucode_len)); 1145 break; 1146 case phymodFirmwareLoadMethodExternal: 1147 if(!PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 1148 PHYMOD_IF_ERR_RETURN(eagle_pram_flop_set(&core->access, 0x0)); 1149 1150 PHYMOD_IF_ERR_RETURN(eagle_tsc_ucode_init(&core->access)); 1151 1152 /* 1153 wait = (PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) ? 0 : 1; 1154 PHYMOD_IF_ERR_RETURN(eagle_pram_firmware_enable(&core->access, 1, wait)); 1155 */ 1156 1157 PHYMOD_IF_ERR_RETURN(eagle_pram_firmware_enable(&core->access, 1)); 1158 1159 if(PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 1160 return PHYMOD_E_NONE; 1161 } 1162 1163 PHYMOD_NULL_CHECK(init_config->firmware_loader); 1164 1165 PHYMOD_IF_ERR_RETURN(init_config->firmware_loader(core, tsce_ucode_len, tsce_ucode)); 1166 } 1167 PHYMOD_IF_ERR_RETURN(eagle_pram_firmware_enable(&core->access, 0)); 1168 break; 1169 case phymodFirmwareLoadMethodNone: 1170 break; 1171 default: 1172 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal fw load method %u"), init_config->firmware_load_method)); 1173 } 1174 if(init_config->firmware_load_method != phymodFirmwareLoadMethodNone){ 1175 /*PHYMOD_IF_ERR_RETURN(tsce_core_firmware_info_get(core, &actual_fw)); 1176 if((tsce_ucode_crc != actual_fw.fw_crc) || (tsce_ucode_ver != actual_fw.fw_version)){ 1177 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("fw load validation was failed"))); 1178 } */ 1179 } 1180 return PHYMOD_E_NONE; 1181 } 1182 1183 int eagle_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config, const phymod_core_status_t* core_status) 1184 { 1185 int rv; 1186 phymod_phy_access_t phy_access, phy_access_copy; 1187 phymod_core_access_t core_copy; 1188 phymod_firmware_core_config_t firmware_core_config_tmp; 1189 1190 TSCE_CORE_TO_PHY_ACCESS(&phy_access, core); 1191 phy_access_copy = phy_access; 1192 PHYMOD_MEMCPY(&core_copy, core, sizeof(core_copy)); 1193 core_copy.access.lane_mask = 0x1; 1194 phy_access_copy = phy_access; 1195 phy_access_copy.access = core->access; 1196 phy_access_copy.access.lane_mask = 0x1; 1197 phy_access_copy.type = core->type; 1198 1199 1200 if(!PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 1201 PHYMOD_IF_ERR_RETURN 1202 (eagle_pmd_reset_seq(&core_copy.access, core_status->pmd_active)); 1203 } 1204 rv = _eagle_core_firmware_load(&core_copy, init_config); 1205 if (rv != PHYMOD_E_NONE) { 1206 PHYMOD_DEBUG_ERROR(("devad 0x%x lane 0x%x: UC firmware-load failed\n", core->access.addr, core->access.lane_mask)); 1207 PHYMOD_IF_ERR_RETURN(rv); 1208 } 1209 1210 if(PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 1211 return PHYMOD_E_NONE; 1212 } 1213 1214 /*next we need to check if the load is correct or not */ 1215 if(init_config->firmware_load_method != phymodFirmwareLoadMethodNone) { 1216 1217 /* This moved earlier as compared to falcon, to sync up with tsce.c */ 1218 PHYMOD_IF_ERR_RETURN 1219 (eagle_pmd_ln_h_rstb_pkill_override( &phy_access_copy.access, 0x1)); 1220 1221 /*next we need to set the uc active and release uc */ 1222 PHYMOD_IF_ERR_RETURN 1223 (eagle_uc_active_set(&core_copy.access ,1)); 1224 1225 /*release the uc reset */ 1226 PHYMOD_IF_ERR_RETURN 1227 (eagle_tsc_uc_reset(&core_copy.access ,0)); 1228 1229 #ifndef TSCE_PMD_CRC_UCODE 1230 if(PHYMOD_CORE_INIT_F_FIRMWARE_LOAD_VERIFY_GET(init_config)) { 1231 rv = eagle_tsc_ucode_load_verify(&core_copy.access, (uint8_t *) &tsce_ucode, tsce_ucode_len); 1232 if (rv != PHYMOD_E_NONE) { 1233 PHYMOD_DEBUG_ERROR(("devad 0x%x lane 0x%x: UC load-verify failed\n", core->access.addr, core->access.lane_mask)); 1234 PHYMOD_IF_ERR_RETURN(rv); 1235 } 1236 } 1237 #endif 1238 1239 /* we need to wait at least 10ms for the uc to settle */ 1240 PHYMOD_USLEEP(10000); 1241 1242 /* poll the ready bit in 10 ms */ 1243 #ifndef TSCE_PMD_CRC_UCODE 1244 PHYMOD_IF_ERR_RETURN 1245 (eagle_tsc_poll_uc_dsc_ready_for_cmd_equals_1(&phy_access_copy.access, 1)); 1246 #else 1247 /* 1248 PHYMOD_IF_ERR_RETURN( 1249 eagle_tsc_ucode_crc_verify( &core_copy.access, tsce_ucode_len,tsce_ucode_crc)); 1250 */ 1251 #endif 1252 1253 1254 PHYMOD_IF_ERR_RETURN 1255 (eagle_pmd_ln_h_rstb_pkill_override( &phy_access_copy.access, 0x0)); 1256 } 1257 1258 /* plldiv CONFIG */ 1259 PHYMOD_IF_ERR_RETURN 1260 (eagle_pll_mode_set(&core_copy.access, 0xa)); 1261 1262 /*now config the lane mapping and polarity */ 1263 PHYMOD_IF_ERR_RETURN 1264 (eagle_core_lane_map_set(core, &init_config->lane_map)); 1265 /* 1266 PHYMOD_IF_ERR_RETURN 1267 (tsce_core_lane_map_set(core, &init_config->lane_map)); 1268 PHYMOD_IF_ERR_RETURN 1269 (temod_autoneg_timer_init(&core->access)); 1270 PHYMOD_IF_ERR_RETURN 1271 (temod_master_port_num_set(&core->access, 0)); 1272 */ 1273 /*don't overide the fw that set in config set if not specified*/ 1274 firmware_core_config_tmp = init_config->firmware_core_config; 1275 firmware_core_config_tmp.CoreConfigFromPCS = 0; 1276 /*set the vco rate to be default at 10.3125G */ 1277 firmware_core_config_tmp.VcoRate = 0x13; 1278 1279 PHYMOD_IF_ERR_RETURN 1280 (eagle_phy_firmware_core_config_set(&phy_access_copy, firmware_core_config_tmp)); 1281 1282 /* release core soft reset */ 1283 PHYMOD_IF_ERR_RETURN 1284 (eagle_core_soft_reset_release(&core_copy.access, 1)); 1285 1286 1287 return PHYMOD_E_NONE; 1288 1289 } 1290 1291 1292 int eagle_phy_init(const phymod_phy_access_t* phy, const phymod_phy_init_config_t* init_config) 1293 { 1294 1295 const phymod_access_t *pm_acc = &phy->access; 1296 phymod_phy_access_t pm_phy_copy; 1297 int start_lane, num_lane, i; 1298 int lane_bkup; 1299 phymod_polarity_t tmp_pol; 1300 1301 PHYMOD_MEMSET(&tmp_pol, 0x0, sizeof(tmp_pol)); 1302 PHYMOD_MEMCPY(&pm_phy_copy, phy, sizeof(pm_phy_copy)); 1303 1304 /*next program the tx fir taps and driver current based on the input*/ 1305 PHYMOD_IF_ERR_RETURN 1306 (phymod_util_lane_config_get(pm_acc, &start_lane, &num_lane)); 1307 /*per lane based reset release */ 1308 /* PHYMOD_IF_ERR_RETURN 1309 (temod_pmd_x4_reset(pm_acc)); */ 1310 PHYMOD_IF_ERR_RETURN(eagle_lane_hard_soft_reset_release(&pm_phy_copy.access, 0)); 1311 PHYMOD_IF_ERR_RETURN(eagle_lane_hard_soft_reset_release(&pm_phy_copy.access, 1)); 1312 PHYMOD_IF_ERR_RETURN(eagle_lane_soft_reset_release(&pm_phy_copy.access, 0)); 1313 PHYMOD_IF_ERR_RETURN(eagle_lane_soft_reset_release(&pm_phy_copy.access, 1)); 1314 1315 lane_bkup = pm_phy_copy.access.lane_mask; 1316 for (i = 0; i < num_lane; i++) { 1317 pm_phy_copy.access.lane_mask = 1 << (start_lane + i); 1318 PHYMOD_IF_ERR_RETURN 1319 (eagle_lane_soft_reset_release(&pm_phy_copy.access, 1)); 1320 } 1321 pm_phy_copy.access.lane_mask = lane_bkup; 1322 1323 /* program the rx/tx polarity */ 1324 for (i = 0; i < num_lane; i++) { 1325 pm_phy_copy.access.lane_mask = 0x1 << (i + start_lane); 1326 tmp_pol.tx_polarity = (init_config->polarity.tx_polarity) >> i & 0x1; 1327 tmp_pol.rx_polarity = (init_config->polarity.rx_polarity) >> i & 0x1; 1328 PHYMOD_IF_ERR_RETURN 1329 (eagle_phy_polarity_set(&pm_phy_copy, &tmp_pol)); 1330 } 1331 1332 for (i = 0; i < num_lane; i++) { 1333 pm_phy_copy.access.lane_mask = 0x1 << (i + start_lane); 1334 PHYMOD_IF_ERR_RETURN 1335 (eagle_phy_tx_set(&pm_phy_copy, &init_config->tx[i])); 1336 } 1337 1338 PHYMOD_IF_ERR_RETURN 1339 (eagle_phy_cl72_set(&pm_phy_copy, init_config->cl72_en)); 1340 1341 /* ONLY for PCS 1342 PHYMOD_IF_ERR_RETURN 1343 (temod_update_port_mode(pm_acc, &pll_restart)); 1344 1345 PHYMOD_IF_ERR_RETURN 1346 (temod_rx_lane_control_set(pm_acc, 1)); 1347 PHYMOD_IF_ERR_RETURN 1348 (temod_tx_lane_control_set(pm_acc, TEMOD_TX_LANE_RESET_TRAFFIC_ENABLE)); 1349 */ 1350 1351 return PHYMOD_E_NONE; 1352 1353 } 1354 1355 int eagle_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable) 1356 { 1357 1358 int i; 1359 int start_lane, num_lane; 1360 int rv = PHYMOD_E_NONE; 1361 phymod_phy_access_t phy_copy; 1362 1363 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phy_copy)); 1364 1365 /* next figure out the lane num and start_lane based on the input */ 1366 PHYMOD_IF_ERR_RETURN 1367 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1368 1369 switch (loopback) { 1370 case phymodLoopbackGlobal : 1371 /* PHYMOD_IF_ERR_RETURN(temod_tx_loopback_control(&phy->access, enable, start_lane, num_lane)); */ 1372 break; 1373 case phymodLoopbackGlobalPMD : 1374 for (i = 0; i < num_lane; i++) { 1375 phy_copy.access.lane_mask = 0x1 << (i + start_lane); 1376 PHYMOD_IF_ERR_RETURN(eagle_tsc_dig_lpbk(&phy_copy.access, (uint8_t) enable)); 1377 PHYMOD_IF_ERR_RETURN(eagle_pmd_force_signal_detect(&phy_copy.access, (int) enable)); 1378 } 1379 break; 1380 case phymodLoopbackRemotePMD : 1381 PHYMOD_IF_ERR_RETURN(eagle_tsc_rmt_lpbk(&phy->access, (uint8_t)enable)); 1382 break; 1383 case phymodLoopbackRemotePCS : 1384 /* PHYMOD_IF_ERR_RETURN(temod_rx_loopback_control(&phy->access, enable)); */ 1385 break; 1386 default : 1387 break; 1388 } 1389 return rv; 1390 1391 } 1392 1393 int eagle_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable) 1394 { 1395 1396 int start_lane, num_lane; 1397 1398 /*next figure out the lane num and start_lane based on the input*/ 1399 PHYMOD_IF_ERR_RETURN 1400 (phymod_util_lane_config_get(&phy->access, &start_lane, &num_lane)); 1401 1402 switch (loopback) { 1403 case phymodLoopbackGlobal : 1404 /* PHYMOD_IF_ERR_RETURN(temod_tx_loopback_get(&phy->access, &enable_core)); */ 1405 /* *enable = (enable_core >> start_lane) & 0x1; */ 1406 break; 1407 case phymodLoopbackGlobalPMD : 1408 PHYMOD_IF_ERR_RETURN(eagle_tsc_dig_lpbk_get(&phy->access, enable)); 1409 break; 1410 case phymodLoopbackRemotePMD : 1411 PHYMOD_IF_ERR_RETURN(eagle_tsc_rmt_lpbk_get(&phy->access, enable)); 1412 break; 1413 case phymodLoopbackRemotePCS : 1414 /* PHYMOD_IF_ERR_RETURN(temod_rx_loopback_control(&phy->access, enable, enable, enable)); */ 1415 break; 1416 default : 1417 break; 1418 } 1419 return PHYMOD_E_NONE; 1420 1421 } 1422 1423 1424 /* this function gives the PMD_RX_LOCK_STATUS */ 1425 int eagle_phy_rx_signal_detect_get(const phymod_phy_access_t* phy, uint32_t* signal_detect) 1426 { 1427 1428 PHYMOD_IF_ERR_RETURN(eagle_tsc_signal_detect(&phy->access, signal_detect)); 1429 1430 return PHYMOD_E_NONE; 1431 1432 } 1433 1434 1435 int eagle_phy_link_status_get(const phymod_phy_access_t* phy, uint32_t* link_status) 1436 { 1437 1438 unsigned char rx_lock; 1439 PHYMOD_IF_ERR_RETURN(eagle_tsc_pmd_lock_status(&phy->access, &rx_lock)); 1440 *link_status = (uint32_t ) rx_lock; 1441 1442 return PHYMOD_E_NONE; 1443 1444 } 1445 1446 1447 int eagle_phy_rx_pmd_locked_get(const phymod_phy_access_t* phy, uint32_t* pmd_lock) 1448 { 1449 1450 PHYMOD_IF_ERR_RETURN(eagle_phy_link_status_get(phy, pmd_lock)); 1451 return PHYMOD_E_NONE; 1452 1453 } 1454 1455 int eagle_phy_reg_read(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t* val) 1456 { 1457 1458 1459 PHYMOD_IF_ERR_RETURN(phymod_tsc_iblk_read(&phy->access, reg_addr, val)); 1460 return PHYMOD_E_NONE; 1461 1462 } 1463 1464 1465 int eagle_phy_reg_write(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t val) 1466 { 1467 1468 PHYMOD_IF_ERR_RETURN(phymod_tsc_iblk_write(&phy->access, reg_addr, val)); 1469 return PHYMOD_E_NONE; 1470 1471 } 1472 1473 1474