eagle_tsc_fields.h (163977B)
1 /************************************************************************************* 2 ************************************************************************************* 3 * * 4 * * 5 * Description : Register access macros for EAGLE_TSC * 6 * * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 10 * No portions of this material may be reproduced in any form without * 11 * the written permission of: * 12 * Broadcom Corporation * 13 * 5300 California Avenue * 14 * Irvine, CA 92617 * 15 * * 16 * All information contained in this document is Broadcom Corporation * 17 * company private proprietary, and trade secret. * 18 */ 19 20 /** @file eagle_tsc_fields.h 21 * Register access macros for EAGLE_TSC 22 */ 23 24 /* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */ 25 26 #ifndef EAGLE_TSC_FIELDS_H 27 #define EAGLE_TSC_FIELDS_H 28 #define __ERR &__err 29 30 #define rdc_ams_pll_cal_aux() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 0, 12, __ERR) 31 #define wrc_ams_pll_cal_aux(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0xf000, 12, wr_val) 32 #define rdc_ams_pll_cal_off() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 4, 15, __ERR) 33 #define wrc_ams_pll_cal_off(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0800, 11, wr_val) 34 #define rdc_ams_pll_imode_iclkidrv1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 5, 15, __ERR) 35 #define wrc_ams_pll_imode_iclkidrv1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0400, 10, wr_val) 36 #define rdc_ams_pll_imax_iclkidrv1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 6, 15, __ERR) 37 #define wrc_ams_pll_imax_iclkidrv1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0200, 9, wr_val) 38 #define rdc_ams_pll_imin_iclkidrv1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 7, 15, __ERR) 39 #define wrc_ams_pll_imin_iclkidrv1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0100, 8, wr_val) 40 #define rdc_ams_pll_imode_ickgen() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 8, 15, __ERR) 41 #define wrc_ams_pll_imode_ickgen(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0080, 7, wr_val) 42 #define rdc_ams_pll_imax_ickgen() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 9, 15, __ERR) 43 #define wrc_ams_pll_imax_ickgen(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0040, 6, wr_val) 44 #define rdc_ams_pll_imin_ickgen() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 10, 15, __ERR) 45 #define wrc_ams_pll_imin_ickgen(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0020, 5, wr_val) 46 #define rdc_ams_pll_imode_iclkint() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 11, 15, __ERR) 47 #define wrc_ams_pll_imode_iclkint(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0010, 4, wr_val) 48 #define rdc_ams_pll_imax_iclkint() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 12, 15, __ERR) 49 #define wrc_ams_pll_imax_iclkint(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0008, 3, wr_val) 50 #define rdc_ams_pll_imin_iclkint() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 13, 15, __ERR) 51 #define wrc_ams_pll_imin_iclkint(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0004, 2, wr_val) 52 #define rdc_ams_pll_txcg_vddr_bgb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 14, 15, __ERR) 53 #define wrc_ams_pll_txcg_vddr_bgb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0002, 1, wr_val) 54 #define rdc_ams_pll_lowpwr_6g() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b0, 15, 15, __ERR) 55 #define wrc_ams_pll_lowpwr_6g(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x0001, 0, wr_val) 56 #define rdc_ams_pll_enable_ftune() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 0, 15, __ERR) 57 #define wrc_ams_pll_enable_ftune(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x8000, 15, wr_val) 58 #define rdc_ams_pll_reset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 1, 15, __ERR) 59 #define wrc_ams_pll_reset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x4000, 14, wr_val) 60 #define rdc_ams_pll_ivco() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 2, 13, __ERR) 61 #define wrc_ams_pll_ivco(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x3800, 11, wr_val) 62 #define rdc_ams_pll_vco_imax() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 5, 15, __ERR) 63 #define wrc_ams_pll_vco_imax(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0400, 10, wr_val) 64 #define rdc_ams_pll_vcoictrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 6, 14, __ERR) 65 #define wrc_ams_pll_vcoictrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0300, 8, wr_val) 66 #define rdc_ams_pll_vco_div4() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 8, 15, __ERR) 67 #define wrc_ams_pll_vco_div4(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0080, 7, wr_val) 68 #define rdc_ams_pll_vco_div2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 9, 15, __ERR) 69 #define wrc_ams_pll_vco_div2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0040, 6, wr_val) 70 #define rdc_ams_pll_fp3_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 10, 14, __ERR) 71 #define wrc_ams_pll_fp3_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0030, 4, wr_val) 72 #define rdc_ams_pll_fp3_rh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 12, 15, __ERR) 73 #define wrc_ams_pll_fp3_rh(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0008, 3, wr_val) 74 #define rdc_ams_pll_spare_18() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 13, 15, __ERR) 75 #define wrc_ams_pll_spare_18(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0004, 2, wr_val) 76 #define rdc_ams_pll_dblr_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b1, 14, 14, __ERR) 77 #define wrc_ams_pll_dblr_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0003, 0, wr_val) 78 #define rdc_ams_pll_imax_ick() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 0, 15, __ERR) 79 #define wrc_ams_pll_imax_ick(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x8000, 15, wr_val) 80 #define rdc_ams_pll_imode_ick() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 1, 15, __ERR) 81 #define wrc_ams_pll_imode_ick(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x4000, 14, wr_val) 82 #define rdc_ams_pll_imin_ick() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 2, 15, __ERR) 83 #define wrc_ams_pll_imin_ick(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x2000, 13, wr_val) 84 #define rdc_ams_pll_imax_icp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 3, 15, __ERR) 85 #define wrc_ams_pll_imax_icp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x1000, 12, wr_val) 86 #define rdc_ams_pll_imode_icp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 4, 15, __ERR) 87 #define wrc_ams_pll_imode_icp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0800, 11, wr_val) 88 #define rdc_ams_pll_imin_icp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 5, 15, __ERR) 89 #define wrc_ams_pll_imin_icp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0400, 10, wr_val) 90 #define rdc_ams_pll_imax_ibias() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 6, 15, __ERR) 91 #define wrc_ams_pll_imax_ibias(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0200, 9, wr_val) 92 #define rdc_ams_pll_imode_ibias() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 7, 15, __ERR) 93 #define wrc_ams_pll_imode_ibias(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0100, 8, wr_val) 94 #define rdc_ams_pll_imin_ibias() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 8, 15, __ERR) 95 #define wrc_ams_pll_imin_ibias(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0080, 7, wr_val) 96 #define rdc_ams_pll_refh_pll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 9, 15, __ERR) 97 #define wrc_ams_pll_refh_pll(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0040, 6, wr_val) 98 #define rdc_ams_pll_refl_pll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 10, 15, __ERR) 99 #define wrc_ams_pll_refl_pll(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0020, 5, wr_val) 100 #define rdc_ams_pll_iqp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 11, 12, __ERR) 101 #define wrc_ams_pll_iqp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x001e, 1, wr_val) 102 #define rdc_ams_pll_en_hrz() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b2, 15, 15, __ERR) 103 #define wrc_ams_pll_en_hrz(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0001, 0, wr_val) 104 #define rdc_ams_pll_test_rx() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 0, 15, __ERR) 105 #define wrc_ams_pll_test_rx(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x8000, 15, wr_val) 106 #define rdc_ams_pll_test_pll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 1, 15, __ERR) 107 #define wrc_ams_pll_test_pll(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x4000, 14, wr_val) 108 #define rdc_ams_pll_test_vc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 2, 15, __ERR) 109 #define wrc_ams_pll_test_vc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x2000, 13, wr_val) 110 #define rdc_ams_pll_test_vref() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 3, 15, __ERR) 111 #define wrc_ams_pll_test_vref(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x1000, 12, wr_val) 112 #define rdc_ams_pll_imax_iop() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 4, 15, __ERR) 113 #define wrc_ams_pll_imax_iop(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0800, 11, wr_val) 114 #define rdc_ams_pll_imode_iop() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 5, 15, __ERR) 115 #define wrc_ams_pll_imode_iop(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0400, 10, wr_val) 116 #define rdc_ams_pll_imin_iop() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 6, 15, __ERR) 117 #define wrc_ams_pll_imin_iop(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0200, 9, wr_val) 118 #define rdc_ams_pll_imax_icomp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 7, 15, __ERR) 119 #define wrc_ams_pll_imax_icomp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0100, 8, wr_val) 120 #define rdc_ams_pll_imode_icomp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 8, 15, __ERR) 121 #define wrc_ams_pll_imode_icomp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0080, 7, wr_val) 122 #define rdc_ams_pll_imin_icomp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 9, 15, __ERR) 123 #define wrc_ams_pll_imin_icomp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0040, 6, wr_val) 124 #define rdc_ams_pll_imax_icml() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 10, 15, __ERR) 125 #define wrc_ams_pll_imax_icml(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0020, 5, wr_val) 126 #define rdc_ams_pll_imode_icml() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 11, 15, __ERR) 127 #define wrc_ams_pll_imode_icml(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0010, 4, wr_val) 128 #define rdc_ams_pll_imin_icml() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 12, 15, __ERR) 129 #define wrc_ams_pll_imin_icml(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0008, 3, wr_val) 130 #define rdc_ams_pll_imax_i10gbuf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 13, 15, __ERR) 131 #define wrc_ams_pll_imax_i10gbuf(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0004, 2, wr_val) 132 #define rdc_ams_pll_imode_i10gbuf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 14, 15, __ERR) 133 #define wrc_ams_pll_imode_i10gbuf(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0002, 1, wr_val) 134 #define rdc_ams_pll_imin_i10gbuf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b3, 15, 15, __ERR) 135 #define wrc_ams_pll_imin_i10gbuf(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0001, 0, wr_val) 136 #define rdc_ams_pll_force_rescal() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 0, 15, __ERR) 137 #define wrc_ams_pll_force_rescal(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x8000, 15, wr_val) 138 #define rdc_ams_pll_force_kvh_bw() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 1, 15, __ERR) 139 #define wrc_ams_pll_force_kvh_bw(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x4000, 14, wr_val) 140 #define rdc_ams_pll_kvh_force() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 2, 14, __ERR) 141 #define wrc_ams_pll_kvh_force(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x3000, 12, wr_val) 142 #define rdc_ams_pll_vddr_bgb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 4, 15, __ERR) 143 #define wrc_ams_pll_vddr_bgb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0800, 11, wr_val) 144 #define rdc_ams_pll_comp_vth() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 5, 15, __ERR) 145 #define wrc_ams_pll_comp_vth(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0400, 10, wr_val) 146 #define rdc_ams_pll_2rx_clkbw() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 6, 14, __ERR) 147 #define wrc_ams_pll_2rx_clkbw(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0300, 8, wr_val) 148 #define rdc_ams_pll_bgr_ctatadj() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 8, 12, __ERR) 149 #define wrc_ams_pll_bgr_ctatadj(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x00f0, 4, wr_val) 150 #define rdc_ams_pll_bgr_ptatadj() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b4, 12, 12, __ERR) 151 #define wrc_ams_pll_bgr_ptatadj(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x000f, 0, wr_val) 152 #define rdc_ams_pll_bgcalr_ptatadj() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 0, 11, __ERR) 153 #define wrc_ams_pll_bgcalr_ptatadj(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0xf800, 11, wr_val) 154 #define rdc_ams_pll_bgcalr_ctatadj() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 5, 11, __ERR) 155 #define wrc_ams_pll_bgcalr_ctatadj(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x07c0, 6, wr_val) 156 #define rdc_ams_pll_test_pnp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 10, 14, __ERR) 157 #define wrc_ams_pll_test_pnp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0030, 4, wr_val) 158 #define rdc_ams_pll_vbypass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 12, 15, __ERR) 159 #define wrc_ams_pll_vbypass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0008, 3, wr_val) 160 #define rdc_ams_pll_bgint() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 13, 15, __ERR) 161 #define wrc_ams_pll_bgint(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0004, 2, wr_val) 162 #define rdc_ams_pll_bgip() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 14, 15, __ERR) 163 #define wrc_ams_pll_bgip(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0002, 1, wr_val) 164 #define rdc_ams_pll_max_test_port_ampl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b5, 15, 15, __ERR) 165 #define wrc_ams_pll_max_test_port_ampl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0001, 0, wr_val) 166 #define rdc_ams_pll_mix2p1cr_ptatadj() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 0, 11, __ERR) 167 #define wrc_ams_pll_mix2p1cr_ptatadj(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0xf800, 11, wr_val) 168 #define rdc_ams_pll_mix2p1cr_ctatadj() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 5, 11, __ERR) 169 #define wrc_ams_pll_mix2p1cr_ctatadj(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x07c0, 6, wr_val) 170 #define rdc_ams_pll_refclk_doubler() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 10, 15, __ERR) 171 #define wrc_ams_pll_refclk_doubler(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0020, 5, wr_val) 172 #define rdc_ams_pll_spare_100() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 11, 15, __ERR) 173 #define wrc_ams_pll_spare_100(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0010, 4, wr_val) 174 #define rdc_ams_pll_pdf_ref_skew() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 12, 15, __ERR) 175 #define wrc_ams_pll_pdf_ref_skew(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0008, 3, wr_val) 176 #define rdc_ams_pll_pdf_fd_skew() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 13, 15, __ERR) 177 #define wrc_ams_pll_pdf_fd_skew(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0004, 2, wr_val) 178 #define rdc_ams_pll_pdf_skew_enlarge() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 14, 15, __ERR) 179 #define wrc_ams_pll_pdf_skew_enlarge(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0002, 1, wr_val) 180 #define rdc_ams_pll_test_fracn_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b6, 15, 15, __ERR) 181 #define wrc_ams_pll_test_fracn_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0001, 0, wr_val) 182 #define rdc_ams_pll_fracn_div_l() _eagle_tsc_pmd_rde_reg(pa, 0xd0b7, __ERR) 183 #define wrc_ams_pll_fracn_div_l(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd0b7, wr_val) 184 #define rdc_ams_pll_fracn_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b8, 0, 15, __ERR) 185 #define wrc_ams_pll_fracn_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b8, 0x8000, 15, wr_val) 186 #define rdc_ams_pll_ditheren() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b8, 1, 15, __ERR) 187 #define wrc_ams_pll_ditheren(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b8, 0x4000, 14, wr_val) 188 #define rdc_ams_pll_fracn_ndiv_int() _eagle_tsc_pmd_rde_field(pa, 0xd0b8, 2, 6, __ERR) 189 #define wrc_ams_pll_fracn_ndiv_int(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b8, 0x3ff0, 4, wr_val) 190 #define rdc_ams_pll_fracn_bypass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b8, 12, 15, __ERR) 191 #define wrc_ams_pll_fracn_bypass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b8, 0x0008, 3, wr_val) 192 #define rdc_ams_pll_fracn_divrange() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b8, 13, 15, __ERR) 193 #define wrc_ams_pll_fracn_divrange(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b8, 0x0004, 2, wr_val) 194 #define rdc_ams_pll_fracn_div_h() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b8, 14, 14, __ERR) 195 #define wrc_ams_pll_fracn_div_h(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b8, 0x0003, 0, wr_val) 196 #define rdc_ams_pll_tx_lowpwr_6g() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0b9, 15, 15, __ERR) 197 #define wrc_ams_pll_tx_lowpwr_6g(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0b9, 0x0001, 0, wr_val) 198 #define rdc_ams_pll_kvh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0ba, 0, 14, __ERR) 199 #define rdc_ams_pll_range() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0ba, 2, 8, __ERR) 200 #define rdc_ams_pll_low() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0ba, 10, 15, __ERR) 201 #define rdc_ams_pll_ndiv() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0ba, 12, 12, __ERR) 202 #define rd_ams_rx_imod_commonmode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 0, 15, __ERR) 203 #define wr_ams_rx_imod_commonmode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x8000, 15, wr_val) 204 #define rd_ams_rx_imin_commonmode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 1, 15, __ERR) 205 #define wr_ams_rx_imin_commonmode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x4000, 14, wr_val) 206 #define rd_ams_rx_en_10gmode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 2, 15, __ERR) 207 #define wr_ams_rx_en_10gmode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x2000, 13, wr_val) 208 #define rd_ams_rx_dc_couple() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 3, 15, __ERR) 209 #define wr_ams_rx_dc_couple(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x1000, 12, wr_val) 210 #define rd_ams_rx_vga_bw_extension() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 4, 15, __ERR) 211 #define wr_ams_rx_vga_bw_extension(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0800, 11, wr_val) 212 #define rd_ams_rx_sigdet_low_power() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 5, 15, __ERR) 213 #define wr_ams_rx_sigdet_low_power(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0400, 10, wr_val) 214 #define rd_ams_rx_sigdet_bypass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 6, 15, __ERR) 215 #define wr_ams_rx_sigdet_bypass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0200, 9, wr_val) 216 #define rd_ams_rx_tport_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 7, 15, __ERR) 217 #define wr_ams_rx_tport_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0100, 8, wr_val) 218 #define rd_ams_rx_vga_output_idle() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 8, 15, __ERR) 219 #define wr_ams_rx_vga_output_idle(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0080, 7, wr_val) 220 #define rd_ams_rx_sig_pwrdn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 9, 15, __ERR) 221 #define wr_ams_rx_sig_pwrdn(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0040, 6, wr_val) 222 #define rd_ams_rx_sigdet_threshold() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 10, 13, __ERR) 223 #define wr_ams_rx_sigdet_threshold(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0038, 3, wr_val) 224 #define rd_ams_rx_phase_int_ampl_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 13, 15, __ERR) 225 #define wr_ams_rx_phase_int_ampl_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0004, 2, wr_val) 226 #define rd_ams_rx_sel_dfeckdelay() _eagle_tsc_pmd_rde_field_byte(pa, 0xd090, 14, 14, __ERR) 227 #define wr_ams_rx_sel_dfeckdelay(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd090, 0x0003, 0, wr_val) 228 #define rd_ams_rx_imax_ctat() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 0, 15, __ERR) 229 #define wr_ams_rx_imax_ctat(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x8000, 15, wr_val) 230 #define rd_ams_rx_imode_ctat() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 1, 15, __ERR) 231 #define wr_ams_rx_imode_ctat(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x4000, 14, wr_val) 232 #define rd_ams_rx_imin_ctat() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 2, 15, __ERR) 233 #define wr_ams_rx_imin_ctat(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x2000, 13, wr_val) 234 #define rd_ams_rx_imax_pf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 3, 15, __ERR) 235 #define wr_ams_rx_imax_pf(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x1000, 12, wr_val) 236 #define rd_ams_rx_imode_pf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 4, 15, __ERR) 237 #define wr_ams_rx_imode_pf(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0800, 11, wr_val) 238 #define rd_ams_rx_imin_pf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 5, 15, __ERR) 239 #define wr_ams_rx_imin_pf(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0400, 10, wr_val) 240 #define rd_ams_rx_imax_dfe_summer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 6, 15, __ERR) 241 #define wr_ams_rx_imax_dfe_summer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0200, 9, wr_val) 242 #define rd_ams_rx_imode_dfe_summer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 7, 15, __ERR) 243 #define wr_ams_rx_imode_dfe_summer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0100, 8, wr_val) 244 #define rd_ams_rx_imin_dfe_summer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 8, 15, __ERR) 245 #define wr_ams_rx_imin_dfe_summer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0080, 7, wr_val) 246 #define rd_ams_rx_imax_vga() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 9, 15, __ERR) 247 #define wr_ams_rx_imax_vga(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0040, 6, wr_val) 248 #define rd_ams_rx_imode_vga() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 10, 15, __ERR) 249 #define wr_ams_rx_imode_vga(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0020, 5, wr_val) 250 #define rd_ams_rx_imin_vga() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 11, 15, __ERR) 251 #define wr_ams_rx_imin_vga(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0010, 4, wr_val) 252 #define rd_ams_rx_imax_phase_int() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 12, 15, __ERR) 253 #define wr_ams_rx_imax_phase_int(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0008, 3, wr_val) 254 #define rd_ams_rx_imode_phase_int() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 13, 15, __ERR) 255 #define wr_ams_rx_imode_phase_int(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0004, 2, wr_val) 256 #define rd_ams_rx_imin_phase_int() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 14, 15, __ERR) 257 #define wr_ams_rx_imin_phase_int(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0002, 1, wr_val) 258 #define rd_ams_rx_imax_commonmode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd091, 15, 15, __ERR) 259 #define wr_ams_rx_imax_commonmode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd091, 0x0001, 0, wr_val) 260 #define rd_ams_rx_spare_47() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 0, 15, __ERR) 261 #define wr_ams_rx_spare_47(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x8000, 15, wr_val) 262 #define rd_ams_rx_spare_46() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 1, 15, __ERR) 263 #define wr_ams_rx_spare_46(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x4000, 14, wr_val) 264 #define rd_ams_rx_en_vcctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 2, 15, __ERR) 265 #define wr_ams_rx_en_vcctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x2000, 13, wr_val) 266 #define rd_ams_rx_sel_th4dfe() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 3, 14, __ERR) 267 #define wr_ams_rx_sel_th4dfe(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x1800, 11, wr_val) 268 #define rd_ams_rx_sel_ugbw() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 5, 14, __ERR) 269 #define wr_ams_rx_sel_ugbw(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0600, 9, wr_val) 270 #define rd_ams_rx_imax_dfe_tap_weight() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 7, 15, __ERR) 271 #define wr_ams_rx_imax_dfe_tap_weight(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0100, 8, wr_val) 272 #define rd_ams_rx_imode_dfe_tap_weight() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 8, 15, __ERR) 273 #define wr_ams_rx_imode_dfe_tap_weight(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0080, 7, wr_val) 274 #define rd_ams_rx_imin_dfe_tap_weight() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 9, 15, __ERR) 275 #define wr_ams_rx_imin_dfe_tap_weight(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0040, 6, wr_val) 276 #define rd_ams_rx_imax_slicer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 10, 15, __ERR) 277 #define wr_ams_rx_imax_slicer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0020, 5, wr_val) 278 #define rd_ams_rx_imode_slicer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 11, 15, __ERR) 279 #define wr_ams_rx_imode_slicer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0010, 4, wr_val) 280 #define rd_ams_rx_imin_slicer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 12, 15, __ERR) 281 #define wr_ams_rx_imin_slicer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0008, 3, wr_val) 282 #define rd_ams_rx_spare_34() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 13, 15, __ERR) 283 #define wr_ams_rx_spare_34(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0004, 2, wr_val) 284 #define rd_ams_rx_spare_33() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 14, 15, __ERR) 285 #define wr_ams_rx_spare_33(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0002, 1, wr_val) 286 #define rd_ams_rx_spare_32() _eagle_tsc_pmd_rde_field_byte(pa, 0xd092, 15, 15, __ERR) 287 #define wr_ams_rx_spare_32(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0001, 0, wr_val) 288 #define rd_ams_rx_spare_63() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 0, 15, __ERR) 289 #define wr_ams_rx_spare_63(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x8000, 15, wr_val) 290 #define rd_ams_rx_spare_62() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 1, 15, __ERR) 291 #define wr_ams_rx_spare_62(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x4000, 14, wr_val) 292 #define rd_ams_rx_i1p25dfe() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 2, 15, __ERR) 293 #define wr_ams_rx_i1p25dfe(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x2000, 13, wr_val) 294 #define rd_ams_rx_i4deadzone() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 3, 15, __ERR) 295 #define wr_ams_rx_i4deadzone(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x1000, 12, wr_val) 296 #define rd_ams_rx_imax_signal_detect() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 4, 15, __ERR) 297 #define wr_ams_rx_imax_signal_detect(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0800, 11, wr_val) 298 #define rd_ams_rx_imode_signal_detect() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 5, 15, __ERR) 299 #define wr_ams_rx_imode_signal_detect(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0400, 10, wr_val) 300 #define rd_ams_rx_imin_signal_detect() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 6, 15, __ERR) 301 #define wr_ams_rx_imin_signal_detect(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0200, 9, wr_val) 302 #define rd_ams_rx_imax_metres_eyediag() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 7, 15, __ERR) 303 #define wr_ams_rx_imax_metres_eyediag(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0100, 8, wr_val) 304 #define rd_ams_rx_imode_metres_eyediag() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 8, 15, __ERR) 305 #define wr_ams_rx_imode_metres_eyediag(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0080, 7, wr_val) 306 #define rd_ams_rx_imin_metres_eyediag() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 9, 15, __ERR) 307 #define wr_ams_rx_imin_metres_eyediag(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0040, 6, wr_val) 308 #define rd_ams_rx_imax_phase_int_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 10, 15, __ERR) 309 #define wr_ams_rx_imax_phase_int_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0020, 5, wr_val) 310 #define rd_ams_rx_imode_phase_int_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 11, 15, __ERR) 311 #define wr_ams_rx_imode_phase_int_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0010, 4, wr_val) 312 #define rd_ams_rx_imin_phase_int_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 12, 15, __ERR) 313 #define wr_ams_rx_imin_phase_int_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0008, 3, wr_val) 314 #define rd_ams_rx_imax_dc_offset_dac() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 13, 15, __ERR) 315 #define wr_ams_rx_imax_dc_offset_dac(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0004, 2, wr_val) 316 #define rd_ams_rx_imode_dc_offset_dac() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 14, 15, __ERR) 317 #define wr_ams_rx_imode_dc_offset_dac(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0002, 1, wr_val) 318 #define rd_ams_rx_imin_dc_offset_dac() _eagle_tsc_pmd_rde_field_byte(pa, 0xd093, 15, 15, __ERR) 319 #define wr_ams_rx_imin_dc_offset_dac(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0001, 0, wr_val) 320 #define rd_ams_rx_phs_interp_rescal_mux() _eagle_tsc_pmd_rde_field_byte(pa, 0xd094, 0, 12, __ERR) 321 #define wr_ams_rx_phs_interp_rescal_mux(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0xf000, 12, wr_val) 322 #define rd_ams_rx_vga_rescal_mux() _eagle_tsc_pmd_rde_field_byte(pa, 0xd094, 4, 13, __ERR) 323 #define wr_ams_rx_vga_rescal_mux(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x0e00, 9, wr_val) 324 #define rd_ams_rx_dc_offset_range() _eagle_tsc_pmd_rde_field_byte(pa, 0xd094, 7, 15, __ERR) 325 #define wr_ams_rx_dc_offset_range(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x0100, 8, wr_val) 326 #define rd_ams_rx_force_dc_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd094, 8, 15, __ERR) 327 #define wr_ams_rx_force_dc_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x0080, 7, wr_val) 328 #define rd_ams_rx_dc_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd094, 9, 9, __ERR) 329 #define wr_ams_rx_dc_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x007f, 0, wr_val) 330 #define rd_ams_rx_dfe_os2x_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd098, 15, 15, __ERR) 331 #define wr_ams_rx_dfe_os2x_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd098, 0x0001, 0, wr_val) 332 #define rd_ams_rx_sigdet() _eagle_tsc_pmd_rde_field_byte(pa, 0xd099, 0, 15, __ERR) 333 #define rd_ams_rx_pf() _eagle_tsc_pmd_rde_field_byte(pa, 0xd099, 1, 12, __ERR) 334 #define rd_ams_rx_tap1_dfe_gray() _eagle_tsc_pmd_rde_field_byte(pa, 0xd099, 5, 10, __ERR) 335 #define rd_ams_rx_vga() _eagle_tsc_pmd_rde_field_byte(pa, 0xd099, 11, 11, __ERR) 336 #define rd_ams_tx_cal_aux() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 0, 12, __ERR) 337 #define wr_ams_tx_cal_aux(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0xf000, 12, wr_val) 338 #define rd_ams_tx_cal_off() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 4, 15, __ERR) 339 #define wr_ams_tx_cal_off(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0800, 11, wr_val) 340 #define rd_ams_tx_dcc_dis() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 5, 15, __ERR) 341 #define wr_ams_tx_dcc_dis(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0400, 10, wr_val) 342 #define rd_ams_tx_dcc_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 6, 15, __ERR) 343 #define wr_ams_tx_dcc_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0200, 9, wr_val) 344 #define rd_ams_tx_kr_test_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 7, 15, __ERR) 345 #define wr_ams_tx_kr_test_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0100, 8, wr_val) 346 #define rd_ams_tx_ticksel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 8, 14, __ERR) 347 #define wr_ams_tx_ticksel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x00c0, 6, wr_val) 348 #define rd_ams_tx_test_data() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 10, 14, __ERR) 349 #define wr_ams_tx_test_data(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0030, 4, wr_val) 350 #define rd_ams_tx_spare_3() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 12, 15, __ERR) 351 #define wr_ams_tx_spare_3(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0008, 3, wr_val) 352 #define rd_ams_tx_spare_2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 13, 15, __ERR) 353 #define wr_ams_tx_spare_2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0004, 2, wr_val) 354 #define rd_ams_tx_spare_1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 14, 15, __ERR) 355 #define wr_ams_tx_spare_1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0002, 1, wr_val) 356 #define rd_ams_tx_osr4() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a0, 15, 15, __ERR) 357 #define wr_ams_tx_osr4(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0001, 0, wr_val) 358 #define rd_ams_tx_lp_ovrd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a1, 0, 15, __ERR) 359 #define wr_ams_tx_lp_ovrd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a1, 0x8000, 15, wr_val) 360 #define rd_ams_tx_spare_30_25() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a1, 1, 10, __ERR) 361 #define wr_ams_tx_spare_30_25(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a1, 0x7e00, 9, wr_val) 362 #define rd_ams_tx_icml() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a1, 7, 13, __ERR) 363 #define wr_ams_tx_icml(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a1, 0x01c0, 6, wr_val) 364 #define rd_ams_tx_idcc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a1, 10, 13, __ERR) 365 #define wr_ams_tx_idcc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a1, 0x0038, 3, wr_val) 366 #define rd_ams_tx_ibias() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a1, 13, 13, __ERR) 367 #define wr_ams_tx_ibias(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a1, 0x0007, 0, wr_val) 368 #define rd_ams_tx_elec_idle_aux() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 0, 15, __ERR) 369 #define wr_ams_tx_elec_idle_aux(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x8000, 15, wr_val) 370 #define rd_ams_tx_drivermode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 1, 14, __ERR) 371 #define wr_ams_tx_drivermode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x6000, 13, wr_val) 372 #define rd_ams_tx_sign_post2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 3, 15, __ERR) 373 #define wr_ams_tx_sign_post2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x1000, 12, wr_val) 374 #define rd_ams_tx_post2_coef() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 4, 12, __ERR) 375 #define wr_ams_tx_post2_coef(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x0f00, 8, wr_val) 376 #define rd_ams_tx_sign_post3() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 8, 15, __ERR) 377 #define wr_ams_tx_sign_post3(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x0080, 7, wr_val) 378 #define rd_ams_tx_post3_coef() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 9, 13, __ERR) 379 #define wr_ams_tx_post3_coef(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x0070, 4, wr_val) 380 #define rd_ams_tx_amp_ctl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a2, 12, 12, __ERR) 381 #define wr_ams_tx_amp_ctl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x000f, 0, wr_val) 382 #define rd_ams_tx_sel_halfrate() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a8, 15, 15, __ERR) 383 #define wr_ams_tx_sel_halfrate(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0a8, 0x0001, 0, wr_val) 384 #define rd_ams_tx_id() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a9, 0, 14, __ERR) 385 #define rd_ams_tx_ana_rescal() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a9, 4, 12, __ERR) 386 #define rd_ams_tx_version_id() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0a9, 8, 8, __ERR) 387 #define rd_osr_mode_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd080, 0, 15, __ERR) 388 #define wr_osr_mode_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x8000, 15, wr_val) 389 #define rd_osr_mode_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd080, 12, 12, __ERR) 390 #define wr_osr_mode_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x000f, 0, wr_val) 391 #define rd_afe_sigdet_pwrdn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd081, 11, 15, __ERR) 392 #define wr_afe_sigdet_pwrdn(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0010, 4, wr_val) 393 #define rd_ln_tx_s_pwrdn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd081, 12, 15, __ERR) 394 #define wr_ln_tx_s_pwrdn(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0008, 3, wr_val) 395 #define rd_ln_rx_s_pwrdn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd081, 13, 15, __ERR) 396 #define wr_ln_rx_s_pwrdn(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0004, 2, wr_val) 397 #define rd_ln_dp_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd081, 14, 15, __ERR) 398 #define wr_ln_dp_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0002, 1, wr_val) 399 #define rd_ln_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd08e, 15, 15, __ERR) 400 #define wr_ln_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd08e, 0x0001, 0, wr_val) 401 #define rd_pmd_rx_clk_vld_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd087, 11, 15, __ERR) 402 #define wr_pmd_rx_clk_vld_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd087, 0x0010, 4, wr_val) 403 #define rd_pmd_rx_clk_vld_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd087, 12, 15, __ERR) 404 #define wr_pmd_rx_clk_vld_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd087, 0x0008, 3, wr_val) 405 #define rd_ln_rx_s_comclk_frc_on() _eagle_tsc_pmd_rde_field_byte(pa, 0xd087, 13, 15, __ERR) 406 #define wr_ln_rx_s_comclk_frc_on(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd087, 0x0004, 2, wr_val) 407 #define rd_ln_rx_s_comclk_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd087, 14, 15, __ERR) 408 #define wr_ln_rx_s_comclk_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd087, 0x0002, 1, wr_val) 409 #define rd_ln_rx_s_clkgate_frc_on() _eagle_tsc_pmd_rde_field_byte(pa, 0xd087, 15, 15, __ERR) 410 #define wr_ln_rx_s_clkgate_frc_on(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd087, 0x0001, 0, wr_val) 411 #define rd_ln_tx_dp_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd084, 6, 15, __ERR) 412 #define wr_ln_tx_dp_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0200, 9, wr_val) 413 #define rd_ln_tx_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd084, 7, 15, __ERR) 414 #define wr_ln_tx_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0100, 8, wr_val) 415 #define rd_sigdet_dp_rstb_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd084, 13, 15, __ERR) 416 #define wr_sigdet_dp_rstb_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0004, 2, wr_val) 417 #define rd_ln_rx_dp_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd084, 14, 15, __ERR) 418 #define wr_ln_rx_dp_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0002, 1, wr_val) 419 #define rd_ln_rx_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd084, 15, 15, __ERR) 420 #define wr_ln_rx_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0001, 0, wr_val) 421 #define rd_afe_tx_reset_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 8, 15, __ERR) 422 #define wr_afe_tx_reset_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0080, 7, wr_val) 423 #define rd_afe_tx_reset_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 9, 15, __ERR) 424 #define wr_afe_tx_reset_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0040, 6, wr_val) 425 #define rd_afe_tx_pwrdn_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 10, 15, __ERR) 426 #define wr_afe_tx_pwrdn_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0020, 5, wr_val) 427 #define rd_afe_tx_pwrdn_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 11, 15, __ERR) 428 #define wr_afe_tx_pwrdn_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0010, 4, wr_val) 429 #define rd_afe_rx_reset_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 12, 15, __ERR) 430 #define wr_afe_rx_reset_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0008, 3, wr_val) 431 #define rd_afe_rx_reset_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 13, 15, __ERR) 432 #define wr_afe_rx_reset_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0004, 2, wr_val) 433 #define rd_afe_rx_pwrdn_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 14, 15, __ERR) 434 #define wr_afe_rx_pwrdn_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0002, 1, wr_val) 435 #define rd_afe_rx_pwrdn_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd082, 15, 15, __ERR) 436 #define wr_afe_rx_pwrdn_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0001, 0, wr_val) 437 #define rd_pmd_ln_tx_h_pwrdn_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd083, 12, 15, __ERR) 438 #define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd083, 0x0008, 3, wr_val) 439 #define rd_pmd_ln_rx_h_pwrdn_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd083, 13, 15, __ERR) 440 #define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd083, 0x0004, 2, wr_val) 441 #define rd_pmd_ln_dp_h_rstb_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd083, 14, 15, __ERR) 442 #define wr_pmd_ln_dp_h_rstb_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd083, 0x0002, 1, wr_val) 443 #define rd_pmd_ln_h_rstb_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd083, 15, 15, __ERR) 444 #define wr_pmd_ln_h_rstb_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd083, 0x0001, 0, wr_val) 445 #define rd_pmd_lane_mode() _eagle_tsc_pmd_rde_reg(pa, 0xd088, __ERR) 446 #define rd_uc_ack_lane_dp_reset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd085, 14, 15, __ERR) 447 #define wr_uc_ack_lane_dp_reset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd085, 0x0002, 1, wr_val) 448 #define rd_uc_ack_lane_cfg_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd085, 15, 15, __ERR) 449 #define wr_uc_ack_lane_cfg_done(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd085, 0x0001, 0, wr_val) 450 #define rd_lane_dp_reset_state() _eagle_tsc_pmd_rde_field_byte(pa, 0xd089, 13, 13, __ERR) 451 #define rd_lane_reg_reset_occurred() _eagle_tsc_pmd_rde_field_byte(pa, 0xd086, 15, 15, __ERR) 452 #define wr_lane_reg_reset_occurred(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd086, 0x0001, 0, wr_val) 453 #define rd_lane_multicast_mask_control() _eagle_tsc_pmd_rde_field_byte(pa, 0xd08a, 15, 15, __ERR) 454 #define wr_lane_multicast_mask_control(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd08a, 0x0001, 0, wr_val) 455 #define rd_osr_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd08b, 12, 12, __ERR) 456 #define rd_osr_mode_pin() _eagle_tsc_pmd_rde_field_byte(pa, 0xd08c, 12, 12, __ERR) 457 #define rd_cl72_ieee_lp_status_report() _eagle_tsc_pmd_rde_reg(pa, 0x0099, __ERR) 458 #define rd_cl72_ieee_training_enable() _eagle_tsc_pmd_rde_field_byte(pa, 0x0096, 14, 15, __ERR) 459 #define wr_cl72_ieee_training_enable(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0x0096, 0x0002, 1, wr_val) 460 #define rd_cl72_ieee_restart_training() _eagle_tsc_pmd_rde_field_byte(pa, 0x0096, 15, 15, __ERR) 461 #define wr_cl72_ieee_restart_training(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0x0096, 0x0001, 0, wr_val) 462 #define rd_cl72_ieee_training_failure() _eagle_tsc_pmd_rde_field_byte(pa, 0x0097, 12, 15, __ERR) 463 #define rd_cl72_ieee_training_status() _eagle_tsc_pmd_rde_field_byte(pa, 0x0097, 13, 15, __ERR) 464 #define rd_cl72_ieee_frame_lock() _eagle_tsc_pmd_rde_field_byte(pa, 0x0097, 14, 15, __ERR) 465 #define rd_cl72_ieee_receiver_status() _eagle_tsc_pmd_rde_field_byte(pa, 0x0097, 15, 15, __ERR) 466 #define rd_cl72_ieee_lp_coeff_update() _eagle_tsc_pmd_rde_reg(pa, 0x0098, __ERR) 467 #define rd_cl72_ieee_ld_coeff_update() _eagle_tsc_pmd_rde_reg(pa, 0x009a, __ERR) 468 #define rd_cl72_ieee_ld_status_report() _eagle_tsc_pmd_rde_reg(pa, 0x009b, __ERR) 469 #define rd_cl72_rcvd_status_page() _eagle_tsc_pmd_rde_reg(pa, 0xd050, __ERR) 470 #define rd_cl72_rx_dp_ln_clk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd051, 13, 15, __ERR) 471 #define wr_cl72_rx_dp_ln_clk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd051, 0x0004, 2, wr_val) 472 #define rd_cl72_tr_coarse_lock() _eagle_tsc_pmd_rde_field_byte(pa, 0xd051, 14, 15, __ERR) 473 #define wr_cl72_tr_coarse_lock(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd051, 0x0002, 1, wr_val) 474 #define rd_cl72_ppm_offset_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 1, 15, __ERR) 475 #define wr_cl72_ppm_offset_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x4000, 14, wr_val) 476 #define rd_cl72_strict_marker_chk() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 2, 15, __ERR) 477 #define wr_cl72_strict_marker_chk(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x2000, 13, wr_val) 478 #define rd_cl72_strict_dme_chk() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 3, 15, __ERR) 479 #define wr_cl72_strict_dme_chk(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x1000, 12, wr_val) 480 #define rd_cl72_ctrl_frame_dly() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 4, 12, __ERR) 481 #define wr_cl72_ctrl_frame_dly(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0f00, 8, wr_val) 482 #define rd_cl72_dme_cell_boundary_chk() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 8, 15, __ERR) 483 #define wr_cl72_dme_cell_boundary_chk(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0080, 7, wr_val) 484 #define rd_cl72_bad_marker_cnt() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 11, 13, __ERR) 485 #define wr_cl72_bad_marker_cnt(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x001c, 2, wr_val) 486 #define rd_cl72_good_marker_cnt() _eagle_tsc_pmd_rde_field_byte(pa, 0xd052, 14, 14, __ERR) 487 #define wr_cl72_good_marker_cnt(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0003, 0, wr_val) 488 #define rd_cl72_lp_control_page() _eagle_tsc_pmd_rde_reg(pa, 0xd053, __ERR) 489 #define rd_cl72_signal_detect() _eagle_tsc_pmd_rde_field_byte(pa, 0xd054, 15, 15, __ERR) 490 #define rd_cl72_xmt_update_page() _eagle_tsc_pmd_rde_reg(pa, 0xd060, __ERR) 491 #define wr_cl72_xmt_update_page(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd060, wr_val) 492 #define rd_cl72_double_cmd_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 3, 15, __ERR) 493 #define wr_cl72_double_cmd_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x1000, 12, wr_val) 494 #define rd_cl72_dis_lp_coeff_updates_to_ld() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 4, 15, __ERR) 495 #define wr_cl72_dis_lp_coeff_updates_to_ld(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0800, 11, wr_val) 496 #define rd_cl72_ld_xmt_status_override() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 5, 15, __ERR) 497 #define wr_cl72_ld_xmt_status_override(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0400, 10, wr_val) 498 #define rd_cl72_ld_xmt_status_load() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 6, 15, __ERR) 499 #define wr_cl72_ld_xmt_status_load(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0200, 9, wr_val) 500 #define rd_cl72_v2_constraint_dis() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 7, 15, __ERR) 501 #define wr_cl72_v2_constraint_dis(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0100, 8, wr_val) 502 #define rd_cl72_tap_v2_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 8, 10, __ERR) 503 #define wr_cl72_tap_v2_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x00fc, 2, wr_val) 504 #define rd_cl72_inc_dec_val_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd068, 14, 14, __ERR) 505 #define wr_cl72_inc_dec_val_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0003, 0, wr_val) 506 #define rd_cl72_tx_dp_ln_clk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd061, 13, 15, __ERR) 507 #define wr_cl72_tx_dp_ln_clk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0004, 2, wr_val) 508 #define rd_cl72_signal_det_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd061, 14, 15, __ERR) 509 #define wr_cl72_signal_det_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0002, 1, wr_val) 510 #define rd_cl72_rx_trained() _eagle_tsc_pmd_rde_field_byte(pa, 0xd061, 15, 15, __ERR) 511 #define wr_cl72_rx_trained(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0001, 0, wr_val) 512 #define rd_cl72_frame_lock_rdy_for_cmd_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd062, 14, 15, __ERR) 513 #define wr_cl72_frame_lock_rdy_for_cmd_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd062, 0x0002, 1, wr_val) 514 #define rd_cl72_brk_ring_osc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd062, 15, 15, __ERR) 515 #define wr_cl72_brk_ring_osc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd062, 0x0001, 0, wr_val) 516 #define rd_cl72_dis_max_wait_timer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd063, 15, 15, __ERR) 517 #define wr_cl72_dis_max_wait_timer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd063, 0x0001, 0, wr_val) 518 #define rd_cl72_ld_status_page() _eagle_tsc_pmd_rde_reg(pa, 0xd064, __ERR) 519 #define rd_cl72_ready_for_cmd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd065, 15, 15, __ERR) 520 #define rd_cl72_tx_fir_tap_post_kr_init_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd066, 5, 10, __ERR) 521 #define wr_cl72_tx_fir_tap_post_kr_init_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd066, 0x07e0, 5, wr_val) 522 #define rd_cl72_tx_fir_tap_pre_kr_init_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd066, 11, 11, __ERR) 523 #define wr_cl72_tx_fir_tap_pre_kr_init_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd066, 0x001f, 0, wr_val) 524 #define rd_cl72_tx_fir_tap_main_kr_init_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd067, 9, 9, __ERR) 525 #define wr_cl72_tx_fir_tap_main_kr_init_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x007f, 0, wr_val) 526 #define rd_cl72_override_ld_status_page() _eagle_tsc_pmd_rde_reg(pa, 0xd069, __ERR) 527 #define wr_cl72_override_ld_status_page(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd069, wr_val) 528 #define rd_cl72_frame_lock_lh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd06a, 4, 15, __ERR) 529 #define rd_cl72_ld_coeff_cmd_hist() _eagle_tsc_pmd_rde_field(pa, 0xd06a, 5, 5, __ERR) 530 #define rdc_revid_rev_letter() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f0, 0, 14, __ERR) 531 #define rdc_revid_rev_number() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f0, 2, 13, __ERR) 532 #define rdc_revid_bonding() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f0, 5, 14, __ERR) 533 #define rdc_revid_process() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f0, 7, 13, __ERR) 534 #define rdc_revid_model() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f0, 10, 10, __ERR) 535 #define rdc_revid_multiplicity() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 0, 12, __ERR) 536 #define rdc_revid_mdio() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 10, 15, __ERR) 537 #define rdc_revid_micro() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 11, 15, __ERR) 538 #define rdc_revid_cl72() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 12, 15, __ERR) 539 #define rdc_revid_pir() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 13, 15, __ERR) 540 #define rdc_revid_llp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 14, 15, __ERR) 541 #define rdc_revid_eee() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fa, 15, 15, __ERR) 542 #define rdc_revid2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fe, 12, 12, __ERR) 543 #define rdc_core_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f1, 15, 15, __ERR) 544 #define wrc_core_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f1, 0x0001, 0, wr_val) 545 #define rdc_tx_pi_loop_filter_stable() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 1, 15, __ERR) 546 #define wrc_tx_pi_loop_filter_stable(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x4000, 14, wr_val) 547 #define rdc_afe_s_pll_reset_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 2, 15, __ERR) 548 #define wrc_afe_s_pll_reset_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x2000, 13, wr_val) 549 #define rdc_afe_s_pll_reset_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 3, 15, __ERR) 550 #define wrc_afe_s_pll_reset_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x1000, 12, wr_val) 551 #define rdc_tx_s_clkgate_frc_on() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 4, 15, __ERR) 552 #define wrc_tx_s_clkgate_frc_on(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0800, 11, wr_val) 553 #define rdc_tx_s_comclk_frc_on() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 5, 15, __ERR) 554 #define wrc_tx_s_comclk_frc_on(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0400, 10, wr_val) 555 #define rdc_tx_s_comclk_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 6, 15, __ERR) 556 #define wrc_tx_s_comclk_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0200, 9, wr_val) 557 #define rdc_pmd_tx_clk_vld_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 7, 15, __ERR) 558 #define wrc_pmd_tx_clk_vld_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0100, 8, wr_val) 559 #define rdc_pmd_tx_clk_vld_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 8, 15, __ERR) 560 #define wrc_pmd_tx_clk_vld_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0080, 7, wr_val) 561 #define rdc_pmd_mdio_trans_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 10, 15, __ERR) 562 #define wrc_pmd_mdio_trans_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0020, 5, wr_val) 563 #define rdc_sup_rst_seq_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 11, 15, __ERR) 564 #define wrc_sup_rst_seq_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0010, 4, wr_val) 565 #define rdc_sup_rst_seq_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 12, 15, __ERR) 566 #define wrc_sup_rst_seq_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0008, 3, wr_val) 567 #define rdc_pmd_core_dp_h_rstb_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f2, 14, 15, __ERR) 568 #define wrc_pmd_core_dp_h_rstb_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f2, 0x0002, 1, wr_val) 569 #define rdc_core_multicast_mask_control() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f3, 12, 12, __ERR) 570 #define wrc_core_multicast_mask_control(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f3, 0x000f, 0, wr_val) 571 #define rdc_uc_active() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f4, 0, 15, __ERR) 572 #define wrc_uc_active(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f4, 0x8000, 15, wr_val) 573 #define rdc_afe_s_pll_pwrdn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f4, 1, 15, __ERR) 574 #define wrc_afe_s_pll_pwrdn(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f4, 0x4000, 14, wr_val) 575 #define rdc_core_dp_s_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f4, 2, 15, __ERR) 576 #define wrc_core_dp_s_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f4, 0x2000, 13, wr_val) 577 #define rdc_heartbeat_count_1us() _eagle_tsc_pmd_rde_field(pa, 0xd0f4, 6, 6, __ERR) 578 #define wrc_heartbeat_count_1us(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd0f4, 0x03ff, 0, wr_val) 579 #define rdc_uc_ack_core_dp_reset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f5, 14, 15, __ERR) 580 #define wrc_uc_ack_core_dp_reset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f5, 0x0002, 1, wr_val) 581 #define rdc_uc_ack_core_cfg_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f5, 15, 15, __ERR) 582 #define wrc_uc_ack_core_cfg_done(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f5, 0x0001, 0, wr_val) 583 #define rdc_lane_reset_released() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f8, 1, 15, __ERR) 584 #define rdc_lane_reset_released_index() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f8, 3, 11, __ERR) 585 #define rdc_core_dp_reset_state() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f8, 13, 13, __ERR) 586 #define rdc_core_reg_reset_occurred() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f6, 15, 15, __ERR) 587 #define wrc_core_reg_reset_occurred(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f6, 0x0001, 0, wr_val) 588 #define rdc_rst_seq_dis_flt_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f7, 0, 14, __ERR) 589 #define wrc_rst_seq_dis_flt_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f7, 0xc000, 14, wr_val) 590 #define rdc_pwrdn_seq_timer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f7, 5, 13, __ERR) 591 #define wrc_pwrdn_seq_timer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f7, 0x0700, 8, wr_val) 592 #define rdc_rst_seq_timer() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0f7, 13, 13, __ERR) 593 #define wrc_rst_seq_timer(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0f7, 0x0007, 0, wr_val) 594 #define rdc_pmd_core_mode() _eagle_tsc_pmd_rde_reg(pa, 0xd0f9, __ERR) 595 #define rdc_tx_lane_map_2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fb, 1, 11, __ERR) 596 #define wrc_tx_lane_map_2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fb, 0x7c00, 10, wr_val) 597 #define rdc_tx_lane_map_1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fb, 6, 11, __ERR) 598 #define wrc_tx_lane_map_1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fb, 0x03e0, 5, wr_val) 599 #define rdc_tx_lane_map_0() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fb, 11, 11, __ERR) 600 #define wrc_tx_lane_map_0(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fb, 0x001f, 0, wr_val) 601 #define rdc_lane_addr_1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fc, 1, 11, __ERR) 602 #define wrc_lane_addr_1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fc, 0x7c00, 10, wr_val) 603 #define rdc_lane_addr_0() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fc, 6, 11, __ERR) 604 #define wrc_lane_addr_0(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fc, 0x03e0, 5, wr_val) 605 #define rdc_tx_lane_map_3() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fc, 11, 11, __ERR) 606 #define wrc_tx_lane_map_3(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fc, 0x001f, 0, wr_val) 607 #define rdc_lane_addr_3() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fd, 3, 11, __ERR) 608 #define wrc_lane_addr_3(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fd, 0x1f00, 8, wr_val) 609 #define rdc_lane_addr_2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0fd, 11, 11, __ERR) 610 #define wrc_lane_addr_2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0fd, 0x001f, 0, wr_val) 611 #define rd_cdr_integ_reg() _eagle_tsc_pmd_rde_field_signed(pa, 0xd005, 0, 0, __ERR) 612 #define rd_cdr_lm_outoflock() _eagle_tsc_pmd_rde_field_byte(pa, 0xd006, 7, 15, __ERR) 613 #define rd_cdr_phase_err() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd006, 11, 11, __ERR) 614 #define rd_cnt_bin_p1_dreg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd007, 1, 9, __ERR) 615 #define rd_cnt_bin_d_dreg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd007, 9, 9, __ERR) 616 #define rd_cnt_bin_m1_preg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd008, 1, 9, __ERR) 617 #define rd_cnt_bin_p1_preg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd008, 9, 9, __ERR) 618 #define rd_cnt_bin_d_mreg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd009, 1, 9, __ERR) 619 #define rd_cnt_bin_m1_mreg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd009, 9, 9, __ERR) 620 #define rd_cnt_d_minus_p1() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd00a, 0, 8, __ERR) 621 #define rd_cnt_d_minus_m1() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd00a, 8, 8, __ERR) 622 #define rd_cdr_lm_thr_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 5, 13, __ERR) 623 #define wr_cdr_lm_thr_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0700, 8, wr_val) 624 #define rd_cdr_freq_override_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 8, 15, __ERR) 625 #define wr_cdr_freq_override_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0080, 7, wr_val) 626 #define rd_cdr_integ_sat_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 9, 15, __ERR) 627 #define wr_cdr_integ_sat_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0040, 6, wr_val) 628 #define rd_cdr_phase_err_frz() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 10, 15, __ERR) 629 #define wr_cdr_phase_err_frz(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0020, 5, wr_val) 630 #define rd_cdr_integ_reg_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 11, 15, __ERR) 631 #define wr_cdr_integ_reg_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0010, 4, wr_val) 632 #define rd_cdr_freq_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 13, 15, __ERR) 633 #define wr_cdr_freq_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0004, 2, wr_val) 634 #define rd_br_pd_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 14, 15, __ERR) 635 #define wr_br_pd_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0002, 1, wr_val) 636 #define rd_cdr_phase_sat_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd001, 15, 15, __ERR) 637 #define wr_cdr_phase_sat_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x0001, 0, wr_val) 638 #define rd_cdr_freq_override_val() _eagle_tsc_pmd_rde_field_signed(pa, 0xd002, 0, 1, __ERR) 639 #define wr_cdr_freq_override_val(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd002, 0xfffe, 1, wr_val) 640 #define rd_dfe_vga_unfreeze() _eagle_tsc_pmd_rde_field_byte(pa, 0xd002, 15, 15, __ERR) 641 #define wr_dfe_vga_unfreeze(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd002, 0x0001, 0, wr_val) 642 #define rd_osx2p_pherr_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd003, 6, 14, __ERR) 643 #define wr_osx2p_pherr_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x0300, 8, wr_val) 644 #define rd_pattern_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd003, 8, 12, __ERR) 645 #define wr_pattern_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x00f0, 4, wr_val) 646 #define rd_phase_err_offset_mult_2() _eagle_tsc_pmd_rde_field_byte(pa, 0xd003, 14, 15, __ERR) 647 #define wr_phase_err_offset_mult_2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x0002, 1, wr_val) 648 #define rd_cdr_zero_polarity() _eagle_tsc_pmd_rde_field_byte(pa, 0xd003, 15, 15, __ERR) 649 #define wr_cdr_zero_polarity(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x0001, 0, wr_val) 650 #define rd_send_lms_to_pcs() _eagle_tsc_pmd_rde_field_byte(pa, 0xd00b, 1, 15, __ERR) 651 #define wr_send_lms_to_pcs(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd00b, 0x4000, 14, wr_val) 652 #define rd_rx_pi_manual_reset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd004, 0, 15, __ERR) 653 #define wr_rx_pi_manual_reset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x8000, 15, wr_val) 654 #define rd_rx_pi_slicers_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd004, 1, 13, __ERR) 655 #define wr_rx_pi_slicers_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x7000, 12, wr_val) 656 #define rd_rx_pi_manual_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd004, 4, 15, __ERR) 657 #define wr_rx_pi_manual_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x0800, 11, wr_val) 658 #define rd_rx_pi_phase_step_dir() _eagle_tsc_pmd_rde_field_byte(pa, 0xd004, 5, 15, __ERR) 659 #define wr_rx_pi_phase_step_dir(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x0400, 10, wr_val) 660 #define rd_rx_pi_manual_strobe() _eagle_tsc_pmd_rde_field_byte(pa, 0xd004, 6, 15, __ERR) 661 #define wr_rx_pi_manual_strobe(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x0200, 9, wr_val) 662 #define rd_rx_pi_phase_step_cnt() _eagle_tsc_pmd_rde_field_byte(pa, 0xd004, 9, 9, __ERR) 663 #define wr_rx_pi_phase_step_cnt(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x007f, 0, wr_val) 664 #define rd_uc_dsc_supp_info() _eagle_tsc_pmd_rde_field_byte(pa, 0xd00d, 0, 8, __ERR) 665 #define wr_uc_dsc_supp_info(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd00d, 0xff00, 8, wr_val) 666 #define rd_uc_dsc_ready_for_cmd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd00d, 8, 15, __ERR) 667 #define wr_uc_dsc_ready_for_cmd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd00d, 0x0080, 7, wr_val) 668 #define rd_uc_dsc_error_found() _eagle_tsc_pmd_rde_field_byte(pa, 0xd00d, 9, 15, __ERR) 669 #define wr_uc_dsc_error_found(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd00d, 0x0040, 6, wr_val) 670 #define rd_uc_dsc_gp_uc_req() _eagle_tsc_pmd_rde_field_byte(pa, 0xd00d, 10, 10, __ERR) 671 #define wr_uc_dsc_gp_uc_req(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd00d, 0x003f, 0, wr_val) 672 #define rd_uc_dsc_data() _eagle_tsc_pmd_rde_reg(pa, 0xd00e, __ERR) 673 #define wr_uc_dsc_data(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd00e, wr_val) 674 #define rd_eee_mode_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 14, 15, __ERR) 675 #define wr_eee_mode_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0002, 1, wr_val) 676 #define rd_eee_quiet_rx_afe_pwrdwn_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 13, 15, __ERR) 677 #define wr_eee_quiet_rx_afe_pwrdwn_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0004, 2, wr_val) 678 #define rd_ignore_rx_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 12, 15, __ERR) 679 #define wr_ignore_rx_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0008, 3, wr_val) 680 #define rd_cl72_timer_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 11, 15, __ERR) 681 #define wr_cl72_timer_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0010, 4, wr_val) 682 #define rd_uc_tune_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 10, 15, __ERR) 683 #define wr_uc_tune_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0020, 5, wr_val) 684 #define rd_hw_tune_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 9, 15, __ERR) 685 #define wr_hw_tune_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0040, 6, wr_val) 686 #define rd_uc_trnsum_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 8, 15, __ERR) 687 #define wr_uc_trnsum_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0080, 7, wr_val) 688 #define rd_eee_measure_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 7, 15, __ERR) 689 #define wr_eee_measure_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0100, 8, wr_val) 690 #define rd_uc_ack_dsc_eee_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 4, 15, __ERR) 691 #define wr_uc_ack_dsc_eee_done(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x0800, 11, wr_val) 692 #define rd_uc_ack_dsc_reset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 3, 15, __ERR) 693 #define wr_uc_ack_dsc_reset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x1000, 12, wr_val) 694 #define rd_uc_ack_dsc_restart() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 2, 15, __ERR) 695 #define wr_uc_ack_dsc_restart(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x2000, 13, wr_val) 696 #define rd_uc_ack_dsc_config() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 1, 15, __ERR) 697 #define wr_uc_ack_dsc_config(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x4000, 14, wr_val) 698 #define rd_set_meas_incomplete() _eagle_tsc_pmd_rde_field_byte(pa, 0xd010, 0, 15, __ERR) 699 #define wr_set_meas_incomplete(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x8000, 15, wr_val) 700 #define rd_rx_dsc_lock_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 15, 15, __ERR) 701 #define wr_rx_dsc_lock_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0001, 0, wr_val) 702 #define rd_rx_dsc_lock_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 14, 15, __ERR) 703 #define wr_rx_dsc_lock_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0002, 1, wr_val) 704 #define rd_dsc_clr_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 13, 15, __ERR) 705 #define wr_dsc_clr_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0004, 2, wr_val) 706 #define rd_dsc_clr_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 12, 15, __ERR) 707 #define wr_dsc_clr_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0008, 3, wr_val) 708 #define rd_trnsum_frz_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 11, 15, __ERR) 709 #define wr_trnsum_frz_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0010, 4, wr_val) 710 #define rd_trnsum_frz_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 10, 15, __ERR) 711 #define wr_trnsum_frz_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0020, 5, wr_val) 712 #define rd_timer_done_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 9, 15, __ERR) 713 #define wr_timer_done_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0040, 6, wr_val) 714 #define rd_timer_done_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 8, 15, __ERR) 715 #define wr_timer_done_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0080, 7, wr_val) 716 #define rd_freq_upd_en_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 7, 15, __ERR) 717 #define wr_freq_upd_en_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0100, 8, wr_val) 718 #define rd_freq_upd_en_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 6, 15, __ERR) 719 #define wr_freq_upd_en_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0200, 9, wr_val) 720 #define rd_cdr_frz_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 5, 15, __ERR) 721 #define wr_cdr_frz_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0400, 10, wr_val) 722 #define rd_cdr_frz_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 4, 15, __ERR) 723 #define wr_cdr_frz_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x0800, 11, wr_val) 724 #define rd_trnsum_clr_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 3, 15, __ERR) 725 #define wr_trnsum_clr_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x1000, 12, wr_val) 726 #define rd_trnsum_clr_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd011, 2, 15, __ERR) 727 #define wr_trnsum_clr_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x2000, 13, wr_val) 728 #define rd_eee_lfsr_cnt() _eagle_tsc_pmd_rde_field(pa, 0xd012, 3, 3, __ERR) 729 #define wr_eee_lfsr_cnt(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd012, 0x1fff, 0, wr_val) 730 #define rd_measure_lfsr_cnt() _eagle_tsc_pmd_rde_field(pa, 0xd013, 3, 3, __ERR) 731 #define wr_measure_lfsr_cnt(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd013, 0x1fff, 0, wr_val) 732 #define rd_acq_cdr_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd014, 11, 11, __ERR) 733 #define wr_acq_cdr_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x001f, 0, wr_val) 734 #define rd_cdr_settle_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd014, 6, 11, __ERR) 735 #define wr_cdr_settle_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x03e0, 5, wr_val) 736 #define rd_hw_tune_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd014, 1, 11, __ERR) 737 #define wr_hw_tune_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x7c00, 10, wr_val) 738 #define rd_measure_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd015, 11, 11, __ERR) 739 #define wr_measure_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x001f, 0, wr_val) 740 #define rd_eee_acq_cdr_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd015, 6, 11, __ERR) 741 #define wr_eee_acq_cdr_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x03e0, 5, wr_val) 742 #define rd_eee_cdr_settle_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd015, 1, 11, __ERR) 743 #define wr_eee_cdr_settle_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x7c00, 10, wr_val) 744 #define rd_eee_hw_tune_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd016, 11, 11, __ERR) 745 #define wr_eee_hw_tune_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x001f, 0, wr_val) 746 #define rd_eee_ana_pwr_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd016, 1, 11, __ERR) 747 #define wr_eee_ana_pwr_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x7c00, 10, wr_val) 748 #define rd_cdr_bwsel_integ_acqcdr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd017, 12, 12, __ERR) 749 #define wr_cdr_bwsel_integ_acqcdr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x000f, 0, wr_val) 750 #define rd_cdr_bwsel_integ_eee_acqcdr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd017, 8, 12, __ERR) 751 #define wr_cdr_bwsel_integ_eee_acqcdr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x00f0, 4, wr_val) 752 #define rd_cdr_bwsel_integ_norm() _eagle_tsc_pmd_rde_field_byte(pa, 0xd017, 4, 12, __ERR) 753 #define wr_cdr_bwsel_integ_norm(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x0f00, 8, wr_val) 754 #define rd_cdr_bwsel_prop_acqcdr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd017, 2, 14, __ERR) 755 #define wr_cdr_bwsel_prop_acqcdr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x3000, 12, wr_val) 756 #define rd_cdr_bwsel_prop_norm() _eagle_tsc_pmd_rde_field_byte(pa, 0xd017, 0, 14, __ERR) 757 #define wr_cdr_bwsel_prop_norm(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0xc000, 14, wr_val) 758 #define rd_phase_err_offset() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 12, 12, __ERR) 759 #define wr_phase_err_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x000f, 0, wr_val) 760 #define rd_eee_phase_err_offset() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 8, 12, __ERR) 761 #define wr_eee_phase_err_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x00f0, 4, wr_val) 762 #define rd_phase_err_offset_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd018, 6, 14, __ERR) 763 #define wr_phase_err_offset_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x0300, 8, wr_val) 764 #define rd_eee_phase_err_offset_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd018, 4, 14, __ERR) 765 #define wr_eee_phase_err_offset_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x0c00, 10, wr_val) 766 #define rd_cdr_bwsel_prop_eee_acqcdr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd018, 0, 14, __ERR) 767 #define wr_cdr_bwsel_prop_eee_acqcdr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0xc000, 14, wr_val) 768 #define rd_rx_restart_pmd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd019, 15, 15, __ERR) 769 #define wr_rx_restart_pmd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x0001, 0, wr_val) 770 #define rd_rx_restart_pmd_hold() _eagle_tsc_pmd_rde_field_byte(pa, 0xd019, 14, 15, __ERR) 771 #define wr_rx_restart_pmd_hold(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x0002, 1, wr_val) 772 #define rd_dsc_state_one_hot() _eagle_tsc_pmd_rde_field(pa, 0xd01b, 6, 6, __ERR) 773 #define rd_dsc_state_eee_one_hot() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01c, 9, 9, __ERR) 774 #define rd_restart_pi_ext_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01d, 15, 15, __ERR) 775 #define rd_restart_sigdet() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01d, 14, 15, __ERR) 776 #define rd_restart_pmd_restart() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01d, 13, 15, __ERR) 777 #define rd_eee_quiet_from_eee_states() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01d, 12, 15, __ERR) 778 #define rd_dsc_state() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01e, 0, 11, __ERR) 779 #define rd_dsc_sm_gp_uc_req() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01e, 5, 10, __ERR) 780 #define rd_dsc_sm_ready_for_cmd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01e, 11, 15, __ERR) 781 #define rd_dsc_sm_scratch() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01e, 12, 12, __ERR) 782 #define rd_eee_measure_cnt() _eagle_tsc_pmd_rde_field(pa, 0xd01a, 0, 7, __ERR) 783 #define rd_meas_incomplete() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01a, 14, 15, __ERR) 784 #define rd_rx_dsc_lock() _eagle_tsc_pmd_rde_field_byte(pa, 0xd01a, 15, 15, __ERR) 785 #define rd_dfe_1_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 0, 15, __ERR) 786 #define wr_dfe_1_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x8000, 15, wr_val) 787 #define rd_dfe_1_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 1, 14, __ERR) 788 #define wr_dfe_1_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x6000, 13, wr_val) 789 #define rd_dfe_1_gradient_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 3, 15, __ERR) 790 #define wr_dfe_1_gradient_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x1000, 12, wr_val) 791 #define rd_dfe_1_err_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 4, 14, __ERR) 792 #define wr_dfe_1_err_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0c00, 10, wr_val) 793 #define rd_dfe_1_inv_m1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 6, 15, __ERR) 794 #define wr_dfe_1_inv_m1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0200, 9, wr_val) 795 #define rd_dfe_1_inv_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 7, 15, __ERR) 796 #define wr_dfe_1_inv_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0100, 8, wr_val) 797 #define rd_dfe_1_cmn_only() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 14, 15, __ERR) 798 #define wr_dfe_1_cmn_only(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0002, 1, wr_val) 799 #define rd_dfe_1_acc_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd021, 15, 15, __ERR) 800 #define wr_dfe_1_acc_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0001, 0, wr_val) 801 #define rd_dfe_1_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd022, 2, 10, __ERR) 802 #define wr_dfe_1_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x3f00, 8, wr_val) 803 #define rd_dfe_1_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd022, 10, 10, __ERR) 804 #define wr_dfe_1_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x003f, 0, wr_val) 805 #define rd_dfe_2_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 0, 15, __ERR) 806 #define wr_dfe_2_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x8000, 15, wr_val) 807 #define rd_dfe_2_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 1, 14, __ERR) 808 #define wr_dfe_2_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x6000, 13, wr_val) 809 #define rd_dfe_2_gradient_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 3, 15, __ERR) 810 #define wr_dfe_2_gradient_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x1000, 12, wr_val) 811 #define rd_dfe_2_err_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 4, 14, __ERR) 812 #define wr_dfe_2_err_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0c00, 10, wr_val) 813 #define rd_dfe_2_inv_m1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 6, 15, __ERR) 814 #define wr_dfe_2_inv_m1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0200, 9, wr_val) 815 #define rd_dfe_2_inv_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 7, 15, __ERR) 816 #define wr_dfe_2_inv_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0100, 8, wr_val) 817 #define rd_dfe_2_cmn_only() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 14, 15, __ERR) 818 #define wr_dfe_2_cmn_only(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0002, 1, wr_val) 819 #define rd_dfe_2_acc_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd023, 15, 15, __ERR) 820 #define wr_dfe_2_acc_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0001, 0, wr_val) 821 #define rd_dfe_2_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd024, 2, 10, __ERR) 822 #define wr_dfe_2_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x3f00, 8, wr_val) 823 #define rd_dfe_2_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd024, 10, 10, __ERR) 824 #define wr_dfe_2_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x003f, 0, wr_val) 825 #define rd_dfe_3_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 0, 15, __ERR) 826 #define wr_dfe_3_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x8000, 15, wr_val) 827 #define rd_dfe_3_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 1, 14, __ERR) 828 #define wr_dfe_3_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x6000, 13, wr_val) 829 #define rd_dfe_3_gradient_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 3, 15, __ERR) 830 #define wr_dfe_3_gradient_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x1000, 12, wr_val) 831 #define rd_dfe_3_err_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 4, 14, __ERR) 832 #define wr_dfe_3_err_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0c00, 10, wr_val) 833 #define rd_dfe_3_inv_m1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 6, 15, __ERR) 834 #define wr_dfe_3_inv_m1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0200, 9, wr_val) 835 #define rd_dfe_3_inv_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 7, 15, __ERR) 836 #define wr_dfe_3_inv_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0100, 8, wr_val) 837 #define rd_dfe_3_acc_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd025, 15, 15, __ERR) 838 #define wr_dfe_3_acc_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0001, 0, wr_val) 839 #define rd_dfe_3_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd026, 2, 10, __ERR) 840 #define wr_dfe_3_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x3f00, 8, wr_val) 841 #define rd_dfe_3_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd026, 10, 10, __ERR) 842 #define wr_dfe_3_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x003f, 0, wr_val) 843 #define rd_dfe_4_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 0, 15, __ERR) 844 #define wr_dfe_4_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x8000, 15, wr_val) 845 #define rd_dfe_4_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 1, 14, __ERR) 846 #define wr_dfe_4_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x6000, 13, wr_val) 847 #define rd_dfe_4_gradient_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 3, 15, __ERR) 848 #define wr_dfe_4_gradient_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x1000, 12, wr_val) 849 #define rd_dfe_4_err_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 4, 14, __ERR) 850 #define wr_dfe_4_err_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0c00, 10, wr_val) 851 #define rd_dfe_4_inv_m1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 6, 15, __ERR) 852 #define wr_dfe_4_inv_m1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0200, 9, wr_val) 853 #define rd_dfe_4_inv_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 7, 15, __ERR) 854 #define wr_dfe_4_inv_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0100, 8, wr_val) 855 #define rd_dfe_4_acc_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd027, 15, 15, __ERR) 856 #define wr_dfe_4_acc_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0001, 0, wr_val) 857 #define rd_dfe_4_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd028, 2, 10, __ERR) 858 #define wr_dfe_4_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x3f00, 8, wr_val) 859 #define rd_dfe_4_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd028, 10, 10, __ERR) 860 #define wr_dfe_4_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x003f, 0, wr_val) 861 #define rd_dfe_5_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 0, 15, __ERR) 862 #define wr_dfe_5_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x8000, 15, wr_val) 863 #define rd_dfe_5_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 1, 14, __ERR) 864 #define wr_dfe_5_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x6000, 13, wr_val) 865 #define rd_dfe_5_gradient_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 3, 15, __ERR) 866 #define wr_dfe_5_gradient_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x1000, 12, wr_val) 867 #define rd_dfe_5_err_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 4, 14, __ERR) 868 #define wr_dfe_5_err_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x0c00, 10, wr_val) 869 #define rd_dfe_5_inv_m1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 6, 15, __ERR) 870 #define wr_dfe_5_inv_m1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x0200, 9, wr_val) 871 #define rd_dfe_5_inv_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 7, 15, __ERR) 872 #define wr_dfe_5_inv_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x0100, 8, wr_val) 873 #define rd_dfe_5_acc_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd029, 15, 15, __ERR) 874 #define wr_dfe_5_acc_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x0001, 0, wr_val) 875 #define rd_dfe_5_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02a, 2, 10, __ERR) 876 #define wr_dfe_5_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02a, 0x3f00, 8, wr_val) 877 #define rd_dfe_5_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02a, 10, 10, __ERR) 878 #define wr_dfe_5_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02a, 0x003f, 0, wr_val) 879 #define rd_dfe_acc_hys_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd020, 0, 15, __ERR) 880 #define wr_dfe_acc_hys_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x8000, 15, wr_val) 881 #define rd_dfe_allow_simult() _eagle_tsc_pmd_rde_field_byte(pa, 0xd020, 1, 15, __ERR) 882 #define wr_dfe_allow_simult(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x4000, 14, wr_val) 883 #define rd_dfe_update_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd020, 2, 15, __ERR) 884 #define wr_dfe_update_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x2000, 13, wr_val) 885 #define rd_dfe_vga_write_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02b, 0, 15, __ERR) 886 #define wr_dfe_vga_write_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02b, 0x8000, 15, wr_val) 887 #define rd_dfe_vga_write_tapsel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02b, 2, 11, __ERR) 888 #define wr_dfe_vga_write_tapsel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02b, 0x3e00, 9, wr_val) 889 #define rd_dfe_vga_write_val() _eagle_tsc_pmd_rde_field(pa, 0xd02b, 7, 7, __ERR) 890 #define wr_dfe_vga_write_val(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd02b, 0x01ff, 0, wr_val) 891 #define rd_vga_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 0, 15, __ERR) 892 #define wr_vga_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x8000, 15, wr_val) 893 #define rd_vga_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 1, 14, __ERR) 894 #define wr_vga_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x6000, 13, wr_val) 895 #define rd_vga_p1_gradient_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 3, 15, __ERR) 896 #define wr_vga_p1_gradient_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x1000, 12, wr_val) 897 #define rd_vga_err_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 4, 14, __ERR) 898 #define wr_vga_err_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x0c00, 10, wr_val) 899 #define rd_vga_inv_m1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 6, 15, __ERR) 900 #define wr_vga_inv_m1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x0200, 9, wr_val) 901 #define rd_vga_inv_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 7, 15, __ERR) 902 #define wr_vga_inv_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x0100, 8, wr_val) 903 #define rd_vga_update_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 8, 14, __ERR) 904 #define wr_vga_update_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x00c0, 6, wr_val) 905 #define rd_vga_tablemap_disable() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 13, 15, __ERR) 906 #define wr_vga_tablemap_disable(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x0004, 2, wr_val) 907 #define rd_vga_acc_hys_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 14, 15, __ERR) 908 #define wr_vga_acc_hys_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x0002, 1, wr_val) 909 #define rd_vga_p1_acc_clr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02c, 15, 15, __ERR) 910 #define wr_vga_p1_acc_clr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02c, 0x0001, 0, wr_val) 911 #define rd_p1_eyediag_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02d, 0, 15, __ERR) 912 #define wr_p1_eyediag_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02d, 0x8000, 15, wr_val) 913 #define rd_vga_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02d, 8, 12, __ERR) 914 #define wr_vga_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02d, 0x00f0, 4, wr_val) 915 #define rd_vga_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02d, 12, 12, __ERR) 916 #define wr_vga_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02d, 0x000f, 0, wr_val) 917 #define rd_p1_off_3levelq_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02e, 7, 15, __ERR) 918 #define wr_p1_off_3levelq_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02e, 0x0100, 8, wr_val) 919 #define rd_p1_offset_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd02e, 8, 15, __ERR) 920 #define wr_p1_offset_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02e, 0x0080, 7, wr_val) 921 #define rd_p1_offset() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd02e, 9, 9, __ERR) 922 #define wr_p1_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd02e, 0x007f, 0, wr_val) 923 #define rd_trnsum_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 0, 15, __ERR) 924 #define wr_trnsum_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x8000, 15, wr_val) 925 #define rd_trnsum_err_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 1, 13, __ERR) 926 #define wr_trnsum_err_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x7000, 12, wr_val) 927 #define rd_trnsum_random_tapsel_disable() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 4, 15, __ERR) 928 #define wr_trnsum_random_tapsel_disable(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x0800, 11, wr_val) 929 #define rd_trnsum_inv_pattern_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 5, 15, __ERR) 930 #define wr_trnsum_inv_pattern_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x0400, 10, wr_val) 931 #define rd_trnsum_pattern_full_check_off() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 6, 15, __ERR) 932 #define wr_trnsum_pattern_full_check_off(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x0200, 9, wr_val) 933 #define rd_trnsum_gain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 8, 14, __ERR) 934 #define wr_trnsum_gain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x00c0, 6, wr_val) 935 #define rd_trnsum_eye_closure_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 10, 15, __ERR) 936 #define wr_trnsum_eye_closure_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x0020, 5, wr_val) 937 #define rd_cdr_qphase_mult_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 11, 15, __ERR) 938 #define wr_cdr_qphase_mult_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x0010, 4, wr_val) 939 #define rd_trnsum_tap_range_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd030, 12, 14, __ERR) 940 #define wr_trnsum_tap_range_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd030, 0x000c, 2, wr_val) 941 #define rd_trnsum_pattern() _eagle_tsc_pmd_rde_field_byte(pa, 0xd031, 0, 8, __ERR) 942 #define wr_trnsum_pattern(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd031, 0xff00, 8, wr_val) 943 #define rd_trnsum_pattern_bit_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd031, 8, 8, __ERR) 944 #define wr_trnsum_pattern_bit_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd031, 0x00ff, 0, wr_val) 945 #define rd_trnsum_tap_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd032, 0, 8, __ERR) 946 #define wr_trnsum_tap_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd032, 0xff00, 8, wr_val) 947 #define rd_trnsum_tap_sign() _eagle_tsc_pmd_rde_field_byte(pa, 0xd032, 8, 8, __ERR) 948 #define wr_trnsum_tap_sign(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd032, 0x00ff, 0, wr_val) 949 #define rd_tdr_cycle_bin() _eagle_tsc_pmd_rde_field_byte(pa, 0xd033, 0, 12, __ERR) 950 #define wr_tdr_cycle_bin(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd033, 0xf000, 12, wr_val) 951 #define rd_tdr_cycle_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd033, 4, 12, __ERR) 952 #define wr_tdr_cycle_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd033, 0x0f00, 8, wr_val) 953 #define rd_tdr_trnsum_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd033, 8, 15, __ERR) 954 #define wr_tdr_trnsum_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd033, 0x0080, 7, wr_val) 955 #define rd_tdr_bit_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd033, 9, 11, __ERR) 956 #define wr_tdr_bit_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd033, 0x007c, 2, wr_val) 957 #define rd_trnsum_unsigned_flip() _eagle_tsc_pmd_rde_field_byte(pa, 0xd033, 14, 15, __ERR) 958 #define wr_trnsum_unsigned_flip(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd033, 0x0002, 1, wr_val) 959 #define rd_trnsum_unsigned_corr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd033, 15, 15, __ERR) 960 #define wr_trnsum_unsigned_corr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd033, 0x0001, 0, wr_val) 961 #define rd_trnsum_e_high() _eagle_tsc_pmd_rde_field_signed(pa, 0xd034, 0, 0, __ERR) 962 #define rd_trnsum_e_low() _eagle_tsc_pmd_rde_field_byte(pa, 0xd035, 8, 8, __ERR) 963 #define rd_trnsum_o_high() _eagle_tsc_pmd_rde_field_signed(pa, 0xd036, 0, 0, __ERR) 964 #define rd_trnsum_o_low() _eagle_tsc_pmd_rde_field_byte(pa, 0xd037, 8, 8, __ERR) 965 #define rd_trnsum_high() _eagle_tsc_pmd_rde_field_signed(pa, 0xd038, 0, 0, __ERR) 966 #define rd_trnsum_low() _eagle_tsc_pmd_rde_field(pa, 0xd039, 6, 6, __ERR) 967 #define rd_p1_eyediag_bin() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd03a, 2, 10, __ERR) 968 #define rd_vga_bin() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03a, 10, 10, __ERR) 969 #define rd_dfe_1_wants_negative() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03b, 0, 15, __ERR) 970 #define rd_dfe_1_e() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03b, 2, 13, __ERR) 971 #define rd_dfe_1_o() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03b, 5, 13, __ERR) 972 #define rd_dfe_1_cmn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03b, 10, 10, __ERR) 973 #define rd_dfe_2_e() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03c, 2, 13, __ERR) 974 #define rd_dfe_2_o() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03c, 5, 13, __ERR) 975 #define rd_dfe_2_se() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03c, 9, 15, __ERR) 976 #define rd_dfe_2_so() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03c, 10, 15, __ERR) 977 #define rd_dfe_2_cmn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03c, 11, 11, __ERR) 978 #define rd_dfe_5_cmn() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd03d, 0, 11, __ERR) 979 #define rd_dfe_4_cmn() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd03d, 5, 11, __ERR) 980 #define rd_dfe_3_cmn() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd03d, 10, 10, __ERR) 981 #define rd_vga3_ctrl_bin() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03e, 4, 12, __ERR) 982 #define rd_vga_ctrl_bin() _eagle_tsc_pmd_rde_field_byte(pa, 0xd03e, 11, 11, __ERR) 983 #define rd_offset_fastacq() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 6, 15, __ERR) 984 #define wr_offset_fastacq(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0200, 9, wr_val) 985 #define rd_en_dfe_clk() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 7, 15, __ERR) 986 #define wr_en_dfe_clk(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0100, 8, wr_val) 987 #define rd_pf_hiz() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 8, 15, __ERR) 988 #define wr_pf_hiz(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0080, 7, wr_val) 989 #define rd_m1_thresh_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 9, 14, __ERR) 990 #define wr_m1_thresh_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0060, 5, wr_val) 991 #define rd_m1_thresh_zero() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 11, 15, __ERR) 992 #define wr_m1_thresh_zero(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0010, 4, wr_val) 993 #define rd_p1_thresh_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 12, 15, __ERR) 994 #define wr_p1_thresh_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0008, 3, wr_val) 995 #define rd_en_hgain() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 13, 15, __ERR) 996 #define wr_en_hgain(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0004, 2, wr_val) 997 #define rd_offset_pd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 14, 15, __ERR) 998 #define wr_offset_pd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0002, 1, wr_val) 999 #define rd_pd_ch_p1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd040, 15, 15, __ERR) 1000 #define wr_pd_ch_p1(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd040, 0x0001, 0, wr_val) 1001 #define rd_pf_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd041, 12, 12, __ERR) 1002 #define wr_pf_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd041, 0x000f, 0, wr_val) 1003 #define rd_pf2_lowp_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd042, 13, 13, __ERR) 1004 #define wr_pf2_lowp_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd042, 0x0007, 0, wr_val) 1005 #define rd_dfe_offset_adj_data_odd() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd043, 10, 10, __ERR) 1006 #define wr_dfe_offset_adj_data_odd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd043, 0x003f, 0, wr_val) 1007 #define rd_dfe_offset_adj_data_even() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd044, 10, 10, __ERR) 1008 #define wr_dfe_offset_adj_data_even(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd044, 0x003f, 0, wr_val) 1009 #define rd_dfe_offset_adj_p1_odd() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd045, 10, 10, __ERR) 1010 #define wr_dfe_offset_adj_p1_odd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd045, 0x003f, 0, wr_val) 1011 #define rd_dfe_offset_adj_p1_even() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd046, 10, 10, __ERR) 1012 #define wr_dfe_offset_adj_p1_even(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd046, 0x003f, 0, wr_val) 1013 #define rd_dfe_offset_adj_m1_odd() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd047, 10, 10, __ERR) 1014 #define wr_dfe_offset_adj_m1_odd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd047, 0x003f, 0, wr_val) 1015 #define rd_dfe_offset_adj_m1_even() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd048, 10, 10, __ERR) 1016 #define wr_dfe_offset_adj_m1_even(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd048, 0x003f, 0, wr_val) 1017 #define rd_dc_offset() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd049, 9, 9, __ERR) 1018 #define wr_dc_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd049, 0x007f, 0, wr_val) 1019 #define rdc_mdio_blk_addr() _eagle_tsc_pmd_rde_field(pa, 0xffdf, 1, 5, __ERR) 1020 #define wrc_mdio_blk_addr(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xffdf, 0x7ff0, 4, wr_val) 1021 #define rdc_mdio_function() _eagle_tsc_pmd_rde_field_byte(pa, 0x000d, 0, 14, __ERR) 1022 #define wrc_mdio_function(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0x000d, 0xc000, 14, wr_val) 1023 #define rdc_mdio_devad() _eagle_tsc_pmd_rde_field_byte(pa, 0x000d, 11, 11, __ERR) 1024 #define wrc_mdio_devad(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0x000d, 0x001f, 0, wr_val) 1025 #define rdc_mdio_addr_data() _eagle_tsc_pmd_rde_reg(pa, 0x000e, __ERR) 1026 #define wrc_mdio_addr_data(wr_val) eagle_tsc_pmd_wr_reg(pa, 0x000e, wr_val) 1027 #define rdc_mdio_maskdata() _eagle_tsc_pmd_rde_reg(pa, 0xffdb, __ERR) 1028 #define wrc_mdio_maskdata(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xffdb, wr_val) 1029 #define rdc_mdio_brcst_port_addr() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdc, 11, 11, __ERR) 1030 #define wrc_mdio_brcst_port_addr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdc, 0x001f, 0, wr_val) 1031 #define rdc_mdio_multi_prts_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 0, 15, __ERR) 1032 #define wrc_mdio_multi_prts_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x8000, 15, wr_val) 1033 #define rdc_mdio_multi_mmds_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 1, 15, __ERR) 1034 #define wrc_mdio_multi_mmds_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x4000, 14, wr_val) 1035 #define rdc_mdio_dev_pcs_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 9, 15, __ERR) 1036 #define wrc_mdio_dev_pcs_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0040, 6, wr_val) 1037 #define rdc_mdio_dev_dte_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 10, 15, __ERR) 1038 #define wrc_mdio_dev_dte_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0020, 5, wr_val) 1039 #define rdc_mdio_dev_phy_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 11, 15, __ERR) 1040 #define wrc_mdio_dev_phy_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0010, 4, wr_val) 1041 #define rdc_mdio_dev_an_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 12, 15, __ERR) 1042 #define wrc_mdio_dev_an_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0008, 3, wr_val) 1043 #define rdc_mdio_dev_pmd_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 13, 15, __ERR) 1044 #define wrc_mdio_dev_pmd_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0004, 2, wr_val) 1045 #define rdc_mdio_dev_cl22_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xffdd, 15, 15, __ERR) 1046 #define wrc_mdio_dev_cl22_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0001, 0, wr_val) 1047 #define rdc_mdio_aer() _eagle_tsc_pmd_rde_reg(pa, 0xffde, __ERR) 1048 #define wrc_mdio_aer(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xffde, wr_val) 1049 #define rdc_micro_ram_count() _eagle_tsc_pmd_rde_reg(pa, 0xd200, __ERR) 1050 #define wrc_micro_ram_count(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd200, wr_val) 1051 #define rdc_micro_ram_address() _eagle_tsc_pmd_rde_reg(pa, 0xd201, __ERR) 1052 #define wrc_micro_ram_address(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd201, wr_val) 1053 #define rdc_micro_init_cmd() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 0, 15, __ERR) 1054 #define wrc_micro_init_cmd(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x8000, 15, wr_val) 1055 #define rdc_micro_pmi_hp_ack_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 1, 15, __ERR) 1056 #define wrc_micro_pmi_hp_ack_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x4000, 14, wr_val) 1057 #define rdc_micro_pmi_hp_ack_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 2, 15, __ERR) 1058 #define wrc_micro_pmi_hp_ack_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x2000, 13, wr_val) 1059 #define rdc_micro_mdio_prog_ram_cs_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 3, 15, __ERR) 1060 #define wrc_micro_mdio_prog_ram_cs_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x1000, 12, wr_val) 1061 #define rdc_micro_mdio_prog_ram_cs_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 4, 15, __ERR) 1062 #define wrc_micro_mdio_prog_ram_cs_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0800, 11, wr_val) 1063 #define rdc_micro_mdio_autowakeup() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 5, 15, __ERR) 1064 #define wrc_micro_mdio_autowakeup(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0400, 10, wr_val) 1065 #define rdc_micro_byte_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 6, 15, __ERR) 1066 #define wrc_micro_byte_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0200, 9, wr_val) 1067 #define rdc_micro_mdio_ram_access_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 7, 14, __ERR) 1068 #define wrc_micro_mdio_ram_access_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0180, 7, wr_val) 1069 #define rdc_micro_mdio_ram_read_autoinc_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 9, 15, __ERR) 1070 #define wrc_micro_mdio_ram_read_autoinc_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0040, 6, wr_val) 1071 #define rdc_micro_mdio_dw8051_reset_n() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 11, 15, __ERR) 1072 #define wrc_micro_mdio_dw8051_reset_n(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0010, 4, wr_val) 1073 #define rdc_micro_write() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 12, 15, __ERR) 1074 #define wrc_micro_write(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0008, 3, wr_val) 1075 #define rdc_micro_read() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 13, 15, __ERR) 1076 #define wrc_micro_read(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0004, 2, wr_val) 1077 #define rdc_micro_stop() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 14, 15, __ERR) 1078 #define wrc_micro_stop(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0002, 1, wr_val) 1079 #define rdc_micro_run() _eagle_tsc_pmd_rde_field_byte(pa, 0xd202, 15, 15, __ERR) 1080 #define wrc_micro_run(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0001, 0, wr_val) 1081 #define rdc_micro_ram_wrdata() _eagle_tsc_pmd_rde_reg(pa, 0xd203, __ERR) 1082 #define wrc_micro_ram_wrdata(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd203, wr_val) 1083 #define rdc_micro_ram_rddata() _eagle_tsc_pmd_rde_reg(pa, 0xd204, __ERR) 1084 #define rdc_micro_init_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd205, 0, 15, __ERR) 1085 #define rdc_micro_fsm() _eagle_tsc_pmd_rde_field_byte(pa, 0xd205, 10, 12, __ERR) 1086 #define rdc_micro_err1() _eagle_tsc_pmd_rde_field_byte(pa, 0xd205, 14, 15, __ERR) 1087 #define rdc_micro_err0() _eagle_tsc_pmd_rde_field_byte(pa, 0xd205, 15, 15, __ERR) 1088 #define rdc_micro_status_muxed() _eagle_tsc_pmd_rde_reg(pa, 0xd206, __ERR) 1089 #define rdc_micro_mdio_uc_mailbox_msw() _eagle_tsc_pmd_rde_reg(pa, 0xd207, __ERR) 1090 #define wrc_micro_mdio_uc_mailbox_msw(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd207, wr_val) 1091 #define rdc_micro_mdio_uc_mailbox_lsw() _eagle_tsc_pmd_rde_reg(pa, 0xd208, __ERR) 1092 #define wrc_micro_mdio_uc_mailbox_lsw(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd208, wr_val) 1093 #define rdc_micro_uc_mdio_mailbox_msw() _eagle_tsc_pmd_rde_reg(pa, 0xd20b, __ERR) 1094 #define rdc_micro_uc_mdio_mailbox_lsw() _eagle_tsc_pmd_rde_reg(pa, 0xd209, __ERR) 1095 #define rdc_micro_srst_dw8051_to_pmi() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 0, 15, __ERR) 1096 #define wrc_micro_srst_dw8051_to_pmi(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x8000, 15, wr_val) 1097 #define rdc_micro_srst_mdio_program_access() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 1, 15, __ERR) 1098 #define wrc_micro_srst_mdio_program_access(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x4000, 14, wr_val) 1099 #define rdc_micro_srst_mdio_load_program_ram() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 2, 15, __ERR) 1100 #define wrc_micro_srst_mdio_load_program_ram(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x2000, 13, wr_val) 1101 #define rdc_micro_zero_rom_dataout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 3, 15, __ERR) 1102 #define wrc_micro_zero_rom_dataout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x1000, 12, wr_val) 1103 #define rdc_micro_ram_clk_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 4, 15, __ERR) 1104 #define wrc_micro_ram_clk_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x0800, 11, wr_val) 1105 #define rdc_micro_srst_mdio_dataram_access() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 5, 15, __ERR) 1106 #define wrc_micro_srst_mdio_dataram_access(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x0400, 10, wr_val) 1107 #define rdc_micro_pmi_ack_timeout_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20a, 12, 12, __ERR) 1108 #define wrc_micro_pmi_ack_timeout_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20a, 0x000f, 0, wr_val) 1109 #define rdc_micro_gen_status_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 0, 13, __ERR) 1110 #define wrc_micro_gen_status_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0xe000, 13, wr_val) 1111 #define rdc_micro_disable_ecc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 3, 15, __ERR) 1112 #define wrc_micro_disable_ecc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x1000, 12, wr_val) 1113 #define rdc_micro_inrush_current_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 4, 15, __ERR) 1114 #define wrc_micro_inrush_current_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0800, 11, wr_val) 1115 #define rdc_micro_inrush_current_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 5, 15, __ERR) 1116 #define wrc_micro_inrush_current_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0400, 10, wr_val) 1117 #define rdc_micro_pram_if_rstb() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 13, 15, __ERR) 1118 #define wrc_micro_pram_if_rstb(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0004, 2, wr_val) 1119 #define rdc_micro_pram_if_flop_bypass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 14, 15, __ERR) 1120 #define wrc_micro_pram_if_flop_bypass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0002, 1, wr_val) 1121 #define rdc_micro_pram_if_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20c, 15, 15, __ERR) 1122 #define wrc_micro_pram_if_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0001, 0, wr_val) 1123 #define rdc_micro_system_reset_n() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20d, 14, 15, __ERR) 1124 #define wrc_micro_system_reset_n(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20d, 0x0002, 1, wr_val) 1125 #define rdc_micro_system_clk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd20d, 15, 15, __ERR) 1126 #define wrc_micro_system_clk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd20d, 0x0001, 0, wr_val) 1127 #define rdc_micro_tempature_data() _eagle_tsc_pmd_rde_reg(pa, 0xd20e, __ERR) 1128 #define rdc_micro_program_ram_tm() _eagle_tsc_pmd_rde_field(pa, 0xd210, 2, 2, __ERR) 1129 #define wrc_micro_program_ram_tm(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd210, 0x3fff, 0, wr_val) 1130 #define rdc_micro_dataram_tm() _eagle_tsc_pmd_rde_field(pa, 0xd214, 6, 6, __ERR) 1131 #define wrc_micro_dataram_tm(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd214, 0x03ff, 0, wr_val) 1132 #define rdc_micro_iram_tm() _eagle_tsc_pmd_rde_field(pa, 0xd218, 6, 6, __ERR) 1133 #define wrc_micro_iram_tm(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd218, 0x03ff, 0, wr_val) 1134 #define rdc_patt_gen_seq_0() _eagle_tsc_pmd_rde_reg(pa, 0xd100, __ERR) 1135 #define wrc_patt_gen_seq_0(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd100, wr_val) 1136 #define rdc_patt_gen_seq_1() _eagle_tsc_pmd_rde_reg(pa, 0xd101, __ERR) 1137 #define wrc_patt_gen_seq_1(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd101, wr_val) 1138 #define rdc_patt_gen_seq_2() _eagle_tsc_pmd_rde_reg(pa, 0xd102, __ERR) 1139 #define wrc_patt_gen_seq_2(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd102, wr_val) 1140 #define rdc_patt_gen_seq_3() _eagle_tsc_pmd_rde_reg(pa, 0xd103, __ERR) 1141 #define wrc_patt_gen_seq_3(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd103, wr_val) 1142 #define rdc_patt_gen_seq_4() _eagle_tsc_pmd_rde_reg(pa, 0xd104, __ERR) 1143 #define wrc_patt_gen_seq_4(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd104, wr_val) 1144 #define rdc_patt_gen_seq_5() _eagle_tsc_pmd_rde_reg(pa, 0xd105, __ERR) 1145 #define wrc_patt_gen_seq_5(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd105, wr_val) 1146 #define rdc_patt_gen_seq_6() _eagle_tsc_pmd_rde_reg(pa, 0xd106, __ERR) 1147 #define wrc_patt_gen_seq_6(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd106, wr_val) 1148 #define rdc_patt_gen_seq_7() _eagle_tsc_pmd_rde_reg(pa, 0xd107, __ERR) 1149 #define wrc_patt_gen_seq_7(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd107, wr_val) 1150 #define rdc_patt_gen_seq_8() _eagle_tsc_pmd_rde_reg(pa, 0xd108, __ERR) 1151 #define wrc_patt_gen_seq_8(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd108, wr_val) 1152 #define rdc_patt_gen_seq_9() _eagle_tsc_pmd_rde_reg(pa, 0xd109, __ERR) 1153 #define wrc_patt_gen_seq_9(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd109, wr_val) 1154 #define rdc_patt_gen_seq_10() _eagle_tsc_pmd_rde_reg(pa, 0xd10a, __ERR) 1155 #define wrc_patt_gen_seq_10(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd10a, wr_val) 1156 #define rdc_patt_gen_seq_11() _eagle_tsc_pmd_rde_reg(pa, 0xd10b, __ERR) 1157 #define wrc_patt_gen_seq_11(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd10b, wr_val) 1158 #define rdc_patt_gen_seq_12() _eagle_tsc_pmd_rde_reg(pa, 0xd10c, __ERR) 1159 #define wrc_patt_gen_seq_12(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd10c, wr_val) 1160 #define rdc_patt_gen_seq_13() _eagle_tsc_pmd_rde_reg(pa, 0xd10d, __ERR) 1161 #define wrc_patt_gen_seq_13(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd10d, wr_val) 1162 #define rdc_patt_gen_seq_14() _eagle_tsc_pmd_rde_reg(pa, 0xd10e, __ERR) 1163 #define wrc_patt_gen_seq_14(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd10e, wr_val) 1164 #define rdc_refclk_divcnt_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd126, 13, 13, __ERR) 1165 #define wrc_refclk_divcnt_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd126, 0x0007, 0, wr_val) 1166 #define rdc_rescal_in() _eagle_tsc_pmd_rde_field_byte(pa, 0xd129, 4, 12, __ERR) 1167 #define rdc_cap_select() _eagle_tsc_pmd_rde_field_byte(pa, 0xd129, 8, 8, __ERR) 1168 #define rdc_dbg_pll_state_one_hot() _eagle_tsc_pmd_rde_field_byte(pa, 0xd12a, 0, 8, __ERR) 1169 #define rdc_dbg_cap_state_one_hot() _eagle_tsc_pmd_rde_field_byte(pa, 0xd12a, 8, 11, __ERR) 1170 #define rdc_dbg_fdbck() _eagle_tsc_pmd_rde_field_byte(pa, 0xd12a, 13, 15, __ERR) 1171 #define rdc_dbg_slowdn_change() _eagle_tsc_pmd_rde_field_byte(pa, 0xd12a, 14, 15, __ERR) 1172 #define rdc_dbg_slowdn() _eagle_tsc_pmd_rde_field_byte(pa, 0xd12a, 15, 15, __ERR) 1173 #define rdc_refclk_divcnt() _eagle_tsc_pmd_rde_field(pa, 0xd125, 2, 2, __ERR) 1174 #define wrc_refclk_divcnt(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd125, 0x3fff, 0, wr_val) 1175 #define rdc_pll_seq_start() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 0, 15, __ERR) 1176 #define wrc_pll_seq_start(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x8000, 15, wr_val) 1177 #define rdc_vco_done_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 1, 15, __ERR) 1178 #define wrc_vco_done_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x4000, 14, wr_val) 1179 #define rdc_freq_det_retry_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 2, 15, __ERR) 1180 #define wrc_freq_det_retry_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x2000, 13, wr_val) 1181 #define rdc_freq_det_restart_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 3, 15, __ERR) 1182 #define wrc_freq_det_restart_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x1000, 12, wr_val) 1183 #define rdc_freq_monitor_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 4, 15, __ERR) 1184 #define wrc_freq_monitor_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0800, 11, wr_val) 1185 #define rdc_slowdn_xor() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 5, 15, __ERR) 1186 #define wrc_slowdn_xor(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0400, 10, wr_val) 1187 #define rdc_vco_rst_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 6, 15, __ERR) 1188 #define wrc_vco_rst_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0200, 9, wr_val) 1189 #define rdc_pll_force_fdone_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 7, 15, __ERR) 1190 #define wrc_pll_force_fdone_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0100, 8, wr_val) 1191 #define rdc_pll_force_fdone() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 8, 15, __ERR) 1192 #define wrc_pll_force_fdone(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0080, 7, wr_val) 1193 #define rdc_pll_force_fpass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 9, 15, __ERR) 1194 #define wrc_pll_force_fpass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0040, 6, wr_val) 1195 #define rdc_pll_force_cap_done_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 10, 15, __ERR) 1196 #define wrc_pll_force_cap_done_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0020, 5, wr_val) 1197 #define rdc_pll_force_cap_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 11, 15, __ERR) 1198 #define wrc_pll_force_cap_done(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0010, 4, wr_val) 1199 #define rdc_pll_force_cap_pass_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 12, 15, __ERR) 1200 #define wrc_pll_force_cap_pass_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0008, 3, wr_val) 1201 #define rdc_pll_force_cap_pass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 13, 15, __ERR) 1202 #define wrc_pll_force_cap_pass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0004, 2, wr_val) 1203 #define rdc_pll_lock_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 14, 15, __ERR) 1204 #define wrc_pll_lock_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0002, 1, wr_val) 1205 #define rdc_pll_lock_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd124, 15, 15, __ERR) 1206 #define wrc_pll_lock_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd124, 0x0001, 0, wr_val) 1207 #define rdc_rescal_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd127, 7, 15, __ERR) 1208 #define wrc_rescal_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd127, 0x0100, 8, wr_val) 1209 #define rdc_rescal_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd127, 8, 12, __ERR) 1210 #define wrc_rescal_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd127, 0x00f0, 4, wr_val) 1211 #define rdc_pll_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd127, 12, 12, __ERR) 1212 #define wrc_pll_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd127, 0x000f, 0, wr_val) 1213 #define rdc_cap_select_m() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 0, 8, __ERR) 1214 #define wrc_cap_select_m(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0xff00, 8, wr_val) 1215 #define rdc_cap_select_m_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 8, 15, __ERR) 1216 #define wrc_cap_select_m_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0080, 7, wr_val) 1217 #define rdc_cap_force_slowdown_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 9, 15, __ERR) 1218 #define wrc_cap_force_slowdown_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0040, 6, wr_val) 1219 #define rdc_cap_force_slowdown() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 10, 15, __ERR) 1220 #define wrc_cap_force_slowdown(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0020, 5, wr_val) 1221 #define rdc_cap_retry_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 11, 15, __ERR) 1222 #define wrc_cap_retry_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0010, 4, wr_val) 1223 #define rdc_cap_restart() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 12, 15, __ERR) 1224 #define wrc_cap_restart(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0008, 3, wr_val) 1225 #define rdc_cap_seq_cya() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 13, 15, __ERR) 1226 #define wrc_cap_seq_cya(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0004, 2, wr_val) 1227 #define rdc_cap_cnt_mask_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 14, 15, __ERR) 1228 #define wrc_cap_cnt_mask_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0002, 1, wr_val) 1229 #define rdc_fast_search_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd123, 15, 15, __ERR) 1230 #define wrc_fast_search_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd123, 0x0001, 0, wr_val) 1231 #define rdc_lost_pll_lock_sm() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 0, 15, __ERR) 1232 #define rdc_cap_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 1, 15, __ERR) 1233 #define rdc_cap_pass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 2, 15, __ERR) 1234 #define rdc_freq_done_sm() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 3, 15, __ERR) 1235 #define rdc_freq_pass_sm() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 4, 15, __ERR) 1236 #define rdc_pll_seq_done() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 5, 15, __ERR) 1237 #define rdc_pll_seq_pass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 6, 15, __ERR) 1238 #define rdc_pll_lock() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 7, 15, __ERR) 1239 #define rdc_cap_done_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 9, 15, __ERR) 1240 #define rdc_cap_pass_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 10, 15, __ERR) 1241 #define rdc_freq_done_sm_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 11, 15, __ERR) 1242 #define rdc_freq_pass_sm_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 12, 15, __ERR) 1243 #define rdc_pll_seq_done_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 13, 15, __ERR) 1244 #define rdc_pll_seq_pass_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 14, 15, __ERR) 1245 #define rdc_pll_lock_lh_ll() _eagle_tsc_pmd_rde_field_byte(pa, 0xd128, 15, 15, __ERR) 1246 #define rdc_res_cal_cntr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd122, 0, 8, __ERR) 1247 #define wrc_res_cal_cntr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd122, 0xff00, 8, wr_val) 1248 #define rdc_win_cal_cntr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd122, 8, 8, __ERR) 1249 #define wrc_win_cal_cntr(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd122, 0x00ff, 0, wr_val) 1250 #define rdc_pre_freq_det_time() _eagle_tsc_pmd_rde_field_byte(pa, 0xd121, 0, 8, __ERR) 1251 #define wrc_pre_freq_det_time(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd121, 0xff00, 8, wr_val) 1252 #define rdc_retry_time() _eagle_tsc_pmd_rde_field_byte(pa, 0xd121, 8, 8, __ERR) 1253 #define wrc_retry_time(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd121, 0x00ff, 0, wr_val) 1254 #define rdc_vco_start_time() _eagle_tsc_pmd_rde_field_byte(pa, 0xd120, 0, 8, __ERR) 1255 #define wrc_vco_start_time(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd120, 0xff00, 8, wr_val) 1256 #define rdc_vco_step_time() _eagle_tsc_pmd_rde_field_byte(pa, 0xd120, 8, 8, __ERR) 1257 #define wrc_vco_step_time(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd120, 0x00ff, 0, wr_val) 1258 #define rd_signal_detect_filter_count() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c0, 11, 11, __ERR) 1259 #define wr_signal_detect_filter_count(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x001f, 0, wr_val) 1260 #define rd_los_filter_count() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c0, 3, 11, __ERR) 1261 #define wr_los_filter_count(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x1f00, 8, wr_val) 1262 #define rd_energy_detect_mask_count() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 0, 11, __ERR) 1263 #define wr_energy_detect_mask_count(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0xf800, 11, wr_val) 1264 #define rd_afe_signal_detect_dis() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 15, 15, __ERR) 1265 #define wr_afe_signal_detect_dis(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0001, 0, wr_val) 1266 #define rd_ext_los_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 14, 15, __ERR) 1267 #define wr_ext_los_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0002, 1, wr_val) 1268 #define rd_ext_los_inv() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 13, 15, __ERR) 1269 #define wr_ext_los_inv(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0004, 2, wr_val) 1270 #define rd_ignore_lp_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 12, 15, __ERR) 1271 #define wr_ignore_lp_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0008, 3, wr_val) 1272 #define rd_signal_detect_filter_1us() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 11, 15, __ERR) 1273 #define wr_signal_detect_filter_1us(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0010, 4, wr_val) 1274 #define rd_energy_detect_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 10, 15, __ERR) 1275 #define wr_energy_detect_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0020, 5, wr_val) 1276 #define rd_energy_detect_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 9, 15, __ERR) 1277 #define wr_energy_detect_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0040, 6, wr_val) 1278 #define rd_signal_detect_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 8, 15, __ERR) 1279 #define wr_signal_detect_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0080, 7, wr_val) 1280 #define rd_signal_detect_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c1, 7, 15, __ERR) 1281 #define wr_signal_detect_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0100, 8, wr_val) 1282 #define rd_los_thresh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c2, 13, 13, __ERR) 1283 #define wr_los_thresh(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0007, 0, wr_val) 1284 #define rd_signal_detect_thresh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c2, 9, 13, __ERR) 1285 #define wr_signal_detect_thresh(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0070, 4, wr_val) 1286 #define rd_hold_los_count() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c2, 5, 13, __ERR) 1287 #define wr_hold_los_count(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0700, 8, wr_val) 1288 #define rd_hold_sd_count() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c2, 2, 13, __ERR) 1289 #define wr_hold_sd_count(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x3800, 11, wr_val) 1290 #define rd_signal_detect() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 15, 15, __ERR) 1291 #define rd_signal_detect_change() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 14, 15, __ERR) 1292 #define rd_energy_detect() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 13, 15, __ERR) 1293 #define rd_energy_detect_change() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 12, 15, __ERR) 1294 #define rd_signal_detect_raw() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 11, 15, __ERR) 1295 #define rd_signal_detect_raw_change() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 10, 15, __ERR) 1296 #define rd_afe_sigdet_thresh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0c8, 5, 13, __ERR) 1297 #define rd_prbs_chk_clk_en_frc_on() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 4, 15, __ERR) 1298 #define wr_prbs_chk_clk_en_frc_on(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0800, 11, wr_val) 1299 #define rd_trnsum_error_count_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 5, 15, __ERR) 1300 #define wr_trnsum_error_count_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0400, 10, wr_val) 1301 #define rd_prbs_chk_err_cnt_burst_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 6, 15, __ERR) 1302 #define wr_prbs_chk_err_cnt_burst_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0200, 9, wr_val) 1303 #define rd_prbs_chk_en_auto_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 8, 15, __ERR) 1304 #define wr_prbs_chk_en_auto_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0080, 7, wr_val) 1305 #define rd_prbs_chk_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 9, 14, __ERR) 1306 #define wr_prbs_chk_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0060, 5, wr_val) 1307 #define rd_prbs_chk_inv() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 11, 15, __ERR) 1308 #define wr_prbs_chk_inv(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0010, 4, wr_val) 1309 #define rd_prbs_chk_mode_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 12, 13, __ERR) 1310 #define wr_prbs_chk_mode_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x000e, 1, wr_val) 1311 #define rd_prbs_chk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d1, 15, 15, __ERR) 1312 #define wr_prbs_chk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0001, 0, wr_val) 1313 #define rd_prbs_chk_lock_cnt() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d0, 11, 11, __ERR) 1314 #define wr_prbs_chk_lock_cnt(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x001f, 0, wr_val) 1315 #define rd_prbs_chk_ool_cnt() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d0, 3, 11, __ERR) 1316 #define wr_prbs_chk_ool_cnt(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x1f00, 8, wr_val) 1317 #define rd_dig_lpbk_pd_flt_bypass() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d2, 13, 15, __ERR) 1318 #define wr_dig_lpbk_pd_flt_bypass(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0004, 2, wr_val) 1319 #define rd_dig_lpbk_pd_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d2, 14, 15, __ERR) 1320 #define wr_dig_lpbk_pd_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0002, 1, wr_val) 1321 #define rd_dig_lpbk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d2, 15, 15, __ERR) 1322 #define wr_dig_lpbk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0001, 0, wr_val) 1323 #define rd_dbg_mask_dig_lpbk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d3, 13, 15, __ERR) 1324 #define wr_dbg_mask_dig_lpbk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0004, 2, wr_val) 1325 #define rd_rx_aggregator_bypass_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d3, 14, 15, __ERR) 1326 #define wr_rx_aggregator_bypass_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0002, 1, wr_val) 1327 #define rd_rx_pmd_dp_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d3, 15, 15, __ERR) 1328 #define wr_rx_pmd_dp_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d3, 0x0001, 0, wr_val) 1329 #define rd_prbs_chk_en_timeout() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d4, 3, 11, __ERR) 1330 #define wr_prbs_chk_en_timeout(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d4, 0x1f00, 8, wr_val) 1331 #define rd_prbs_chk_en_timer_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d4, 14, 14, __ERR) 1332 #define wr_prbs_chk_en_timer_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0d4, 0x0003, 0, wr_val) 1333 #define rd_dig_lpbk_pd_early_ind() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d8, 14, 15, __ERR) 1334 #define rd_dig_lpbk_pd_late_ind() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d8, 15, 15, __ERR) 1335 #define rd_prbs_chk_lock() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0d9, 15, 15, __ERR) 1336 #define rd_prbs_chk_lock_lost_lh() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0da, 0, 15, __ERR) 1337 #define rd_prbs_chk_err_cnt_msb() _eagle_tsc_pmd_rde_field(pa, 0xd0da, 1, 1, __ERR) 1338 #define rd_prbs_chk_err_cnt_lsb() _eagle_tsc_pmd_rde_reg(pa, 0xd0db, __ERR) 1339 #define rd_pmd_rx_lock() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0dc, 15, 15, __ERR) 1340 #define rd_pmd_rx_lock_change() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0dc, 14, 15, __ERR) 1341 #define rd_patt_gen_start_pos() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e0, 0, 12, __ERR) 1342 #define wr_patt_gen_start_pos(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0xf000, 12, wr_val) 1343 #define rd_patt_gen_stop_pos() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e0, 4, 12, __ERR) 1344 #define wr_patt_gen_stop_pos(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0x0f00, 8, wr_val) 1345 #define rd_patt_gen_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e0, 15, 15, __ERR) 1346 #define wr_patt_gen_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0x0001, 0, wr_val) 1347 #define rd_prbs_gen_err_ins() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e1, 10, 15, __ERR) 1348 #define wr_prbs_gen_err_ins(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0020, 5, wr_val) 1349 #define rd_prbs_gen_inv() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e1, 11, 15, __ERR) 1350 #define wr_prbs_gen_inv(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0010, 4, wr_val) 1351 #define rd_prbs_gen_mode_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e1, 12, 13, __ERR) 1352 #define wr_prbs_gen_mode_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x000e, 1, wr_val) 1353 #define rd_prbs_gen_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e1, 15, 15, __ERR) 1354 #define wr_prbs_gen_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0001, 0, wr_val) 1355 #define rd_rmt_lpbk_pd_frc_on() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e2, 13, 15, __ERR) 1356 #define wr_rmt_lpbk_pd_frc_on(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0004, 2, wr_val) 1357 #define rd_rmt_lpbk_pd_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e2, 14, 15, __ERR) 1358 #define wr_rmt_lpbk_pd_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0002, 1, wr_val) 1359 #define rd_rmt_lpbk_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e2, 15, 15, __ERR) 1360 #define wr_rmt_lpbk_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0001, 0, wr_val) 1361 #define rd_tx_mux_sel_order() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e3, 13, 15, __ERR) 1362 #define wr_tx_mux_sel_order(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e3, 0x0004, 2, wr_val) 1363 #define rd_tx_pcs_native_ana_frmt_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e3, 14, 15, __ERR) 1364 #define wr_tx_pcs_native_ana_frmt_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e3, 0x0002, 1, wr_val) 1365 #define rd_tx_pmd_dp_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e3, 15, 15, __ERR) 1366 #define wr_tx_pmd_dp_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e3, 0x0001, 0, wr_val) 1367 #define rd_tx_pi_loop_timing_src_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e4, 15, 15, __ERR) 1368 #define wr_tx_pi_loop_timing_src_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd0e4, 0x0001, 0, wr_val) 1369 #define rd_rmt_lpbk_pd_early_ind() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e8, 14, 15, __ERR) 1370 #define rd_rmt_lpbk_pd_late_ind() _eagle_tsc_pmd_rde_field_byte(pa, 0xd0e8, 15, 15, __ERR) 1371 #define rd_txfir_post_override() _eagle_tsc_pmd_rde_field_byte(pa, 0xd110, 5, 10, __ERR) 1372 #define wr_txfir_post_override(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x07e0, 5, wr_val) 1373 #define rd_txfir_pre_override() _eagle_tsc_pmd_rde_field_byte(pa, 0xd110, 11, 11, __ERR) 1374 #define wr_txfir_pre_override(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x001f, 0, wr_val) 1375 #define rd_txfir_override_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd111, 0, 15, __ERR) 1376 #define wr_txfir_override_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x8000, 15, wr_val) 1377 #define rd_txfir_post2() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd111, 4, 11, __ERR) 1378 #define wr_txfir_post2(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0f80, 7, wr_val) 1379 #define rd_txfir_main_override() _eagle_tsc_pmd_rde_field_byte(pa, 0xd111, 9, 9, __ERR) 1380 #define wr_txfir_main_override(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x007f, 0, wr_val) 1381 #define rd_txfir_post2_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd112, 0, 12, __ERR) 1382 #define wr_txfir_post2_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0xf000, 12, wr_val) 1383 #define rd_txfir_post_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd112, 4, 12, __ERR) 1384 #define wr_txfir_post_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0f00, 8, wr_val) 1385 #define rd_txfir_main_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd112, 8, 12, __ERR) 1386 #define wr_txfir_main_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x00f0, 4, wr_val) 1387 #define rd_txfir_pre_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd112, 12, 12, __ERR) 1388 #define wr_txfir_pre_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x000f, 0, wr_val) 1389 #define rd_txfir_post_after_ovr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd113, 5, 10, __ERR) 1390 #define rd_txfir_pre_after_ovr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd113, 11, 11, __ERR) 1391 #define rd_txfir_main_after_ovr() _eagle_tsc_pmd_rde_field_byte(pa, 0xd114, 9, 9, __ERR) 1392 #define rd_txfir_post_adjusted() _eagle_tsc_pmd_rde_field_byte(pa, 0xd115, 5, 10, __ERR) 1393 #define rd_txfir_pre_adjusted() _eagle_tsc_pmd_rde_field_byte(pa, 0xd115, 11, 11, __ERR) 1394 #define rd_txfir_post3_adjusted() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd116, 0, 12, __ERR) 1395 #define rd_txfir_post2_adjusted() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd116, 4, 11, __ERR) 1396 #define rd_txfir_main_adjusted() _eagle_tsc_pmd_rde_field_byte(pa, 0xd116, 9, 9, __ERR) 1397 #define rd_micro_tx_disable() _eagle_tsc_pmd_rde_field_byte(pa, 0xd117, 15, 15, __ERR) 1398 #define wr_micro_tx_disable(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x0001, 0, wr_val) 1399 #define rd_dp_reset_tx_disable_dis() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 3, 15, __ERR) 1400 #define wr_dp_reset_tx_disable_dis(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x1000, 12, wr_val) 1401 #define rd_tx_disable_output_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 4, 14, __ERR) 1402 #define wr_tx_disable_output_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x0c00, 10, wr_val) 1403 #define rd_tx_eee_alert_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 6, 15, __ERR) 1404 #define wr_tx_eee_alert_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x0200, 9, wr_val) 1405 #define rd_tx_eee_quiet_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 7, 15, __ERR) 1406 #define wr_tx_eee_quiet_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x0100, 8, wr_val) 1407 #define rd_tx_disable_timer_ctrl() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 8, 10, __ERR) 1408 #define wr_tx_disable_timer_ctrl(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x00fc, 2, wr_val) 1409 #define rd_pmd_tx_disable_pkill() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 14, 15, __ERR) 1410 #define wr_pmd_tx_disable_pkill(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x0002, 1, wr_val) 1411 #define rd_sdk_tx_disable() _eagle_tsc_pmd_rde_field_byte(pa, 0xd118, 15, 15, __ERR) 1412 #define wr_sdk_tx_disable(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd118, 0x0001, 0, wr_val) 1413 #define rd_txfir_post3_offset() _eagle_tsc_pmd_rde_field_byte(pa, 0xd119, 4, 12, __ERR) 1414 #define wr_txfir_post3_offset(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x0f00, 8, wr_val) 1415 #define rd_txfir_post3() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd119, 12, 12, __ERR) 1416 #define wr_txfir_post3(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd119, 0x000f, 0, wr_val) 1417 #define rdc_tx_pi_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 15, 15, __ERR) 1418 #define wrc_tx_pi_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0001, 0, wr_val) 1419 #define rdc_tx_pi_jitter_filter_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 14, 15, __ERR) 1420 #define wrc_tx_pi_jitter_filter_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0002, 1, wr_val) 1421 #define rdc_tx_pi_ext_ctrl_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 13, 15, __ERR) 1422 #define wrc_tx_pi_ext_ctrl_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0004, 2, wr_val) 1423 #define rdc_tx_pi_freq_override_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 12, 15, __ERR) 1424 #define wrc_tx_pi_freq_override_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0008, 3, wr_val) 1425 #define rdc_tx_pi_sj_gen_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 11, 15, __ERR) 1426 #define wrc_tx_pi_sj_gen_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0010, 4, wr_val) 1427 #define rdc_tx_pi_ssc_gen_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 10, 15, __ERR) 1428 #define wrc_tx_pi_ssc_gen_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0020, 5, wr_val) 1429 #define rdc_tx_pi_jit_ssc_freq_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 9, 15, __ERR) 1430 #define wrc_tx_pi_jit_ssc_freq_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0040, 6, wr_val) 1431 #define rdc_tx_pi_second_order_loop_en() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 8, 15, __ERR) 1432 #define wrc_tx_pi_second_order_loop_en(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0080, 7, wr_val) 1433 #define rdc_tx_pi_first_order_bwsel_integ() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 6, 14, __ERR) 1434 #define wrc_tx_pi_first_order_bwsel_integ(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0300, 8, wr_val) 1435 #define rdc_tx_pi_second_order_bwsel_integ() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 4, 14, __ERR) 1436 #define wrc_tx_pi_second_order_bwsel_integ(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x0c00, 10, wr_val) 1437 #define rdc_tx_pi_ext_phase_bwsel_integ() _eagle_tsc_pmd_rde_field_byte(pa, 0xd070, 1, 13, __ERR) 1438 #define wrc_tx_pi_ext_phase_bwsel_integ(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd070, 0x7000, 12, wr_val) 1439 #define rdc_tx_pi_freq_override_val() _eagle_tsc_pmd_rde_field_signed(pa, 0xd071, 1, 1, __ERR) 1440 #define wrc_tx_pi_freq_override_val(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd071, 0x7fff, 0, wr_val) 1441 #define rdc_tx_pi_jit_freq_idx() _eagle_tsc_pmd_rde_field_byte(pa, 0xd072, 10, 10, __ERR) 1442 #define wrc_tx_pi_jit_freq_idx(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd072, 0x003f, 0, wr_val) 1443 #define rdc_tx_pi_jit_amp() _eagle_tsc_pmd_rde_field_byte(pa, 0xd072, 2, 10, __ERR) 1444 #define wrc_tx_pi_jit_amp(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd072, 0x3f00, 8, wr_val) 1445 #define rdc_tx_pi_phase_override() _eagle_tsc_pmd_rde_field_byte(pa, 0xd073, 15, 15, __ERR) 1446 #define wrc_tx_pi_phase_override(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd073, 0x0001, 0, wr_val) 1447 #define rdc_tx_pi_phase_strobe() _eagle_tsc_pmd_rde_field_byte(pa, 0xd073, 14, 15, __ERR) 1448 #define wrc_tx_pi_phase_strobe(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd073, 0x0002, 1, wr_val) 1449 #define rdc_tx_pi_phase_step_dir() _eagle_tsc_pmd_rde_field_byte(pa, 0xd073, 13, 15, __ERR) 1450 #define wrc_tx_pi_phase_step_dir(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd073, 0x0004, 2, wr_val) 1451 #define rdc_tx_pi_phase_invert() _eagle_tsc_pmd_rde_field_byte(pa, 0xd073, 11, 15, __ERR) 1452 #define wrc_tx_pi_phase_invert(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd073, 0x0010, 4, wr_val) 1453 #define rdc_tx_pi_phase_step_num() _eagle_tsc_pmd_rde_field_byte(pa, 0xd073, 4, 12, __ERR) 1454 #define wrc_tx_pi_phase_step_num(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd073, 0x0f00, 8, wr_val) 1455 #define rdc_tx_pi_frz_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd074, 15, 15, __ERR) 1456 #define wrc_tx_pi_frz_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd074, 0x0001, 0, wr_val) 1457 #define rdc_tx_pi_frz_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd074, 14, 15, __ERR) 1458 #define wrc_tx_pi_frz_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd074, 0x0002, 1, wr_val) 1459 #define rdc_tx_pi_frz_mode() _eagle_tsc_pmd_rde_field_byte(pa, 0xd074, 13, 15, __ERR) 1460 #define wrc_tx_pi_frz_mode(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd074, 0x0004, 2, wr_val) 1461 #define rdc_tx_pi_reset_code_dbg() _eagle_tsc_pmd_rde_field_byte(pa, 0xd074, 12, 15, __ERR) 1462 #define wrc_tx_pi_reset_code_dbg(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd074, 0x0008, 3, wr_val) 1463 #define rdc_tx_pi_rmt_lpbk_bypass_flt() _eagle_tsc_pmd_rde_field_byte(pa, 0xd074, 11, 15, __ERR) 1464 #define wrc_tx_pi_rmt_lpbk_bypass_flt(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd074, 0x0010, 4, wr_val) 1465 #define rdc_tx_pi_frc_phase_step_mux_sel() _eagle_tsc_pmd_rde_field_byte(pa, 0xd074, 10, 15, __ERR) 1466 #define wrc_tx_pi_frc_phase_step_mux_sel(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd074, 0x0020, 5, wr_val) 1467 #define rdc_tx_pi_lane_sel_frc() _eagle_tsc_pmd_rde_field_byte(pa, 0xd076, 7, 15, __ERR) 1468 #define wrc_tx_pi_lane_sel_frc(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd076, 0x0100, 8, wr_val) 1469 #define rdc_tx_pi_lane_sel_frc_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd076, 11, 11, __ERR) 1470 #define wrc_tx_pi_lane_sel_frc_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd076, 0x001f, 0, wr_val) 1471 #define rdc_tx_pi_phase_cntr() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd078, 9, 9, __ERR) 1472 #define rdc_tx_pi_integ1_reg() _eagle_tsc_pmd_rde_field_signed(pa, 0xd079, 2, 2, __ERR) 1473 #define rdc_tx_pi_integ2_reg() _eagle_tsc_pmd_rde_field_signed(pa, 0xd07a, 1, 1, __ERR) 1474 #define rdc_tx_pi_phase_err() _eagle_tsc_pmd_rde_field_signed_byte(pa, 0xd07b, 10, 10, __ERR) 1475 #define rdc_post_tap_limit() _eagle_tsc_pmd_rde_field_byte(pa, 0xd130, 5, 10, __ERR) 1476 #define wrc_post_tap_limit(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x07e0, 5, wr_val) 1477 #define rdc_pre_tap_limit() _eagle_tsc_pmd_rde_field_byte(pa, 0xd130, 11, 11, __ERR) 1478 #define wrc_pre_tap_limit(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x001f, 0, wr_val) 1479 #define rdc_main_tap_limit() _eagle_tsc_pmd_rde_field_byte(pa, 0xd131, 9, 9, __ERR) 1480 #define wrc_main_tap_limit(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd131, 0x007f, 0, wr_val) 1481 #define rdc_pre_tap_preset_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd132, 5, 11, __ERR) 1482 #define wrc_pre_tap_preset_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd132, 0x07c0, 6, wr_val) 1483 #define rdc_post_tap_preset_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd132, 10, 10, __ERR) 1484 #define wrc_post_tap_preset_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd132, 0x003f, 0, wr_val) 1485 #define rdc_tap_sum_max_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd133, 1, 8, __ERR) 1486 #define wrc_tap_sum_max_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd133, 0x7f80, 7, wr_val) 1487 #define rdc_main_tap_min_val() _eagle_tsc_pmd_rde_field_byte(pa, 0xd133, 9, 9, __ERR) 1488 #define wrc_main_tap_min_val(wr_val) _eagle_tsc_pmd_mwr_reg_byte(pa, 0xd133, 0x007f, 0, wr_val) 1489 #define rdc_max_wait_timer_period() _eagle_tsc_pmd_rde_reg(pa, 0xd134, __ERR) 1490 #define wrc_max_wait_timer_period(wr_val) eagle_tsc_pmd_wr_reg(pa, 0xd134, wr_val) 1491 #define rdc_wait_cntr_limit() _eagle_tsc_pmd_rde_field(pa, 0xd135, 7, 7, __ERR) 1492 #define wrc_wait_cntr_limit(wr_val) eagle_tsc_pmd_mwr_reg(pa, 0xd135, 0x01ff, 0, wr_val) 1493 1494 #endif