eagle_cfg_seq.c (33589B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 /* 10 * $Copyright: (c) 2014 Broadcom Corporation All Rights Reserved.$ 11 * 12 */ 13 14 15 #include <phymod/phymod.h> 16 #include "eagle_cfg_seq.h" 17 #include <phymod/chip/bcmi_tsce_xgxs_defs.h> 18 #include "eagle_tsc_fields.h" 19 #include "eagle_tsc_dependencies.h" 20 #include "eagle_tsc_field_access.h" 21 22 /** Macro to execute a statement with automatic return of error LESTM(Local ESTM) to fix coverity error */ 23 #define LESTM(statement) do {err_code_t __err = ERR_CODE_NONE; statement; if (__err) return(__err); } while(0) 24 /** Macro to invoke a function with automatic return of error */ 25 #define LEFUN(fun) do {err_code_t __err = (fun); if (__err) return(__err); } while(0) 26 27 28 29 err_code_t eagle_uc_active_set(const phymod_access_t *pa, uint32_t enable) /* set microcontroller active or not */ 30 { 31 DIG_TOP_USER_CTL0r_t uc_active_reg; 32 33 DIG_TOP_USER_CTL0r_CLR(uc_active_reg); 34 DIG_TOP_USER_CTL0r_UC_ACTIVEf_SET(uc_active_reg, enable); 35 MODIFY_DIG_TOP_USER_CTL0r(pa, uc_active_reg); 36 37 return ERR_CODE_NONE; 38 } 39 40 err_code_t eagle_uc_active_get(const phymod_access_t *pa, uint32_t *enable) /* get microcontroller active or not */ 41 { 42 DIG_TOP_USER_CTL0r_t uc_active_reg; 43 44 DIG_TOP_USER_CTL0r_CLR(uc_active_reg); 45 READ_DIG_TOP_USER_CTL0r(pa, &uc_active_reg); 46 *enable = DIG_TOP_USER_CTL0r_UC_ACTIVEf_GET(uc_active_reg); 47 48 return ERR_CODE_NONE; 49 } 50 51 err_code_t eagle_uc_reset(const phymod_access_t *pa, uint32_t enable) /* set dw8501 reset */ 52 { 53 UC_COMMANDr_t command_reg; 54 55 UC_COMMANDr_CLR(command_reg); 56 UC_COMMANDr_MICRO_MDIO_DW8051_RESET_Nf_SET(command_reg, enable); 57 MODIFY_UC_COMMANDr(pa, command_reg); 58 59 return ERR_CODE_NONE; 60 } 61 62 err_code_t eagle_prbs_tx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data) 63 { 64 TLB_TX_PRBS_GEN_CFGr_t tmp_reg; 65 TLB_TX_PRBS_GEN_CFGr_CLR(tmp_reg); 66 READ_TLB_TX_PRBS_GEN_CFGr(pa, &tmp_reg); 67 *inv_data = TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_INVf_GET(tmp_reg); 68 69 return ERR_CODE_NONE; 70 } 71 72 err_code_t eagle_prbs_rx_inv_data_get(const phymod_access_t *pa, uint32_t *inv_data) 73 { 74 TLB_RX_PRBS_CHK_CFGr_t tmp_reg; 75 TLB_RX_PRBS_CHK_CFGr_CLR(tmp_reg); 76 READ_TLB_RX_PRBS_CHK_CFGr(pa, &tmp_reg); 77 *inv_data = TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_INVf_GET(tmp_reg); 78 return ERR_CODE_NONE; 79 } 80 81 82 err_code_t eagle_prbs_tx_poly_get(const phymod_access_t *pa, eagle_prbs_polynomial_type_t *prbs_poly) 83 { 84 TLB_TX_PRBS_GEN_CFGr_t tmp_reg; 85 TLB_TX_PRBS_GEN_CFGr_CLR(tmp_reg); 86 READ_TLB_TX_PRBS_GEN_CFGr(pa, &tmp_reg); 87 *prbs_poly = TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_MODE_SELf_GET(tmp_reg); 88 89 return ERR_CODE_NONE; 90 } 91 92 err_code_t eagle_prbs_rx_poly_get(const phymod_access_t *pa, eagle_prbs_polynomial_type_t *prbs_poly) 93 { 94 TLB_RX_PRBS_CHK_CFGr_t tmp_reg; 95 TLB_RX_PRBS_CHK_CFGr_CLR(tmp_reg); 96 READ_TLB_RX_PRBS_CHK_CFGr(pa, &tmp_reg); 97 *prbs_poly = TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_MODE_SELf_GET(tmp_reg); 98 return ERR_CODE_NONE; 99 } 100 101 err_code_t eagle_prbs_tx_enable_get(const phymod_access_t *pa, uint32_t *enable) 102 { 103 TLB_TX_PRBS_GEN_CFGr_t tmp_reg; 104 TLB_TX_PRBS_GEN_CFGr_CLR(tmp_reg); 105 READ_TLB_TX_PRBS_GEN_CFGr(pa, &tmp_reg); 106 *enable = TLB_TX_PRBS_GEN_CFGr_PRBS_GEN_ENf_GET(tmp_reg); 107 108 return ERR_CODE_NONE; 109 } 110 111 err_code_t eagle_prbs_rx_enable_get(const phymod_access_t *pa, uint32_t *enable) 112 { 113 TLB_RX_PRBS_CHK_CFGr_t tmp_reg; 114 TLB_RX_PRBS_CHK_CFGr_CLR(tmp_reg); 115 READ_TLB_RX_PRBS_CHK_CFGr(pa, &tmp_reg); 116 *enable = TLB_RX_PRBS_CHK_CFGr_PRBS_CHK_ENf_GET(tmp_reg); 117 return ERR_CODE_NONE; 118 } 119 120 err_code_t eagle_pll_mode_set(const phymod_access_t *pa, int pll_mode) /* PLL divider set */ 121 { 122 PLL_CAL_CTL7r_t eagle_xgxs_ctl_7_reg; 123 124 PLL_CAL_CTL7r_CLR(eagle_xgxs_ctl_7_reg); 125 PLL_CAL_CTL7r_PLL_MODEf_SET(eagle_xgxs_ctl_7_reg, pll_mode); 126 MODIFY_PLL_CAL_CTL7r(pa, eagle_xgxs_ctl_7_reg); 127 return ERR_CODE_NONE; 128 } 129 130 131 err_code_t eagle_core_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 132 { 133 DIG_TOP_USER_CTL0r_t reg; 134 135 DIG_TOP_USER_CTL0r_CLR(reg); 136 DIG_TOP_USER_CTL0r_CORE_DP_S_RSTBf_SET(reg, enable); 137 MODIFY_DIG_TOP_USER_CTL0r(pa, reg); 138 return ERR_CODE_NONE; 139 } 140 141 err_code_t eagle_lane_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 142 { 143 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_t reg_pwrdwn_ctrl; 144 145 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg_pwrdwn_ctrl); 146 CKRST_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg_pwrdwn_ctrl, enable); 147 MODIFY_CKRST_LN_CLK_RST_N_PWRDWN_CTLr(pa, reg_pwrdwn_ctrl); 148 149 return ERR_CODE_NONE; 150 } 151 152 err_code_t eagle_pram_flop_set(const phymod_access_t *pa, int value) /* release the pmd core soft reset */ 153 { 154 UC_COMMAND3r_t uc_reg; 155 UC_COMMAND3r_CLR(uc_reg); 156 UC_COMMAND3r_MICRO_PRAM_IF_FLOP_BYPASSf_SET(uc_reg, value); 157 MODIFY_UC_COMMAND3r(pa, uc_reg); 158 return ERR_CODE_NONE; 159 } 160 161 162 err_code_t eagle_pram_firmware_enable(const phymod_access_t *pa, int enable) /* release the pmd core soft reset */ 163 { 164 UC_COMMAND3r_t uc_reg; 165 /* UC_COMMAND4r_t reg; */ 166 UC_COMMAND3r_CLR(uc_reg); 167 /* UC_COMMAND4r_CLR(reg); */ 168 if(enable == 1) { 169 UC_COMMAND3r_MICRO_PRAM_IF_RSTBf_SET(uc_reg, 1); 170 UC_COMMAND3r_MICRO_PRAM_IF_ENf_SET(uc_reg, 1); 171 UC_COMMAND3r_MICRO_PRAM_IF_FLOP_BYPASSf_SET(uc_reg, 0); 172 /* 173 UC_COMMAND4r_MICRO_SYSTEM_CLK_ENf_SET(reg, 1); 174 UC_COMMAND4r_MICRO_SYSTEM_RESET_Nf_SET(reg, 1); 175 MODIFY_UC_COMMAND4r(pa, reg); 176 */ 177 } else { 178 UC_COMMAND3r_MICRO_PRAM_IF_RSTBf_SET(uc_reg, 0); 179 UC_COMMAND3r_MICRO_PRAM_IF_ENf_SET(uc_reg, 0); 180 UC_COMMAND3r_MICRO_PRAM_IF_FLOP_BYPASSf_SET(uc_reg, 1); 181 } 182 MODIFY_UC_COMMAND3r(pa, uc_reg); 183 return ERR_CODE_NONE; 184 } 185 186 err_code_t eagle_pmd_force_signal_detect(const phymod_access_t *pa, int enable) 187 { 188 SIGDET_CTL1r_t reg; 189 SIGDET_CTL1r_CLR(reg); 190 SIGDET_CTL1r_SIGNAL_DETECT_FRCf_SET(reg, enable); 191 SIGDET_CTL1r_SIGNAL_DETECT_FRC_VALf_SET(reg, enable); 192 MODIFY_SIGDET_CTL1r(pa, reg); 193 return ERR_CODE_NONE; 194 } 195 196 err_code_t eagle_pmd_loopback_get(const phymod_access_t *pa, uint32_t *enable) 197 { 198 TLB_RX_DIG_LPBK_CFGr_t reg; 199 READ_TLB_RX_DIG_LPBK_CFGr(pa, ®); 200 *enable = TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(reg); 201 return ERR_CODE_NONE; 202 } 203 204 err_code_t eagle_pmd_cl72_enable_get(const phymod_access_t *pa, uint32_t *enable) 205 { 206 CL72_TXBASE_R_PMD_CTLr_t reg; 207 READ_CL72_TXBASE_R_PMD_CTLr(pa, ®); 208 *enable = CL72_TXBASE_R_PMD_CTLr_CL72_IEEE_TRAINING_ENABLEf_GET(reg); 209 return ERR_CODE_NONE; 210 } 211 212 err_code_t eagle_pmd_cl72_receiver_status(const phymod_access_t *pa, uint32_t *status) 213 { 214 CL72_TXBASE_R_PMD_STSr_t reg; 215 READ_CL72_TXBASE_R_PMD_STSr(pa, ®); 216 *status = CL72_TXBASE_R_PMD_STSr_CL72_IEEE_RECEIVER_STATUSf_GET(reg); 217 return ERR_CODE_NONE; 218 } 219 220 err_code_t eagle_uc_init(const phymod_access_t *pa) 221 { 222 uint8_t result; 223 224 LEFUN(wrc_micro_system_clk_en(0x1)); /* Enable clock to micro */ 225 LEFUN(wrc_micro_system_reset_n(0x1)); /* De-assert reset to micro */ 226 LEFUN(wrc_micro_system_reset_n(0x0)); /* Assert reset to micro - Toggling micro reset*/ 227 LEFUN(wrc_micro_system_reset_n(0x1)); /* De-assert reset to micro */ 228 229 eagle_pram_flop_set(pa, 0x0); 230 LEFUN(wrc_micro_mdio_ram_access_mode(0x0)); /* Select Program Memory access mode - Program RAM load when Serdes DW8051 in reset */ 231 232 LEFUN(wrc_micro_ram_address(0x0)); /* RAM start address */ 233 LEFUN(wrc_micro_init_cmd(0x0)); /* Clear initialization command */ 234 LEFUN(wrc_micro_init_cmd(0x1)); /* Set initialization command */ 235 236 eagle_tsc_delay_us(4000); 237 238 LESTM(result = !rdc_micro_init_done()); 239 if (result) { /* Check if initialization done within 500us time interval */ 240 PHYMOD_DEBUG_ERROR(("ERR_CODE_MICRO_INIT_NOT_DONE\n")); 241 return (ERR_CODE_MICRO_INIT_NOT_DONE); /* Else issue error code */ 242 } 243 LEFUN(wrc_micro_init_cmd(0x0)); /* Clear initialization command */ 244 return ( ERR_CODE_NONE ); 245 246 } 247 248 249 /***********************************************/ 250 /* Microcode Init into Program RAM Functions */ 251 /***********************************************/ 252 253 /* uCode Load through Register (MDIO) Interface [Return Val = Error_Code (0 = PASS)] */ 254 err_code_t eagle_tsc_ucode_init( const phymod_access_t *pa ) { 255 256 uint8_t result; 257 258 LEFUN(wrc_micro_system_clk_en(0x1)); /* Enable clock to micro */ 259 LEFUN(wrc_micro_system_reset_n(0x1)); /* De-assert reset to micro */ 260 LEFUN(wrc_micro_system_reset_n(0x0)); /* Assert reset to micro - Toggling micro reset*/ 261 LEFUN(wrc_micro_system_reset_n(0x1)); /* De-assert reset to micro */ 262 263 LEFUN(wrc_micro_mdio_ram_access_mode(0x0)); /* Select Program Memory access mode - Program RAM load when Serdes DW8051 in reset */ 264 265 LEFUN(wrc_micro_ram_address(0x0)); /* RAM start address */ 266 LEFUN(wrc_micro_init_cmd(0x0)); /* Clear initialization command */ 267 LEFUN(wrc_micro_init_cmd(0x1)); /* Set initialization command */ 268 269 /* coverity[check_return] */ 270 eagle_tsc_delay_us(500); 271 LEFUN(wrc_micro_init_cmd(0x0)); /* Set initialization command */ 272 273 LESTM(result = !rdc_micro_init_done()); 274 275 if (result) { /* Check if initialization done within 500us time interval */ 276 PHYMOD_DEBUG_ERROR(("ERR_CODE_MICRO_INIT_NOT_DONE\n")); 277 return (ERR_CODE_MICRO_INIT_NOT_DONE); /* Else issue error code */ 278 } 279 280 return (ERR_CODE_NONE); 281 } 282 283 err_code_t eagle_pmd_ln_h_rstb_pkill_override( const phymod_access_t *pa, uint16_t val) 284 { 285 CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_t pin_ctl; 286 287 /* 288 * Work around per Magesh/Justin 289 * override input from PCS to allow uc_dsc_ready_for_cmd 290 * reg get written by UC 291 */ 292 CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_CLR(pin_ctl); 293 CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_PMD_LN_H_RSTB_PKILLf_SET(pin_ctl, val); 294 WRITE_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr(pa, pin_ctl); 295 return (ERR_CODE_NONE); 296 } 297 298 err_code_t eagle_tx_pi_control_get( const phymod_access_t *pa, int16_t* value) 299 { 300 TX_PI_CTL0r_t tx_pi_reg; 301 TX_PI_CTL1r_t tx_pi_value_reg; 302 303 READ_TX_PI_CTL0r(pa, &tx_pi_reg); 304 READ_TX_PI_CTL1r(pa, &tx_pi_value_reg); 305 if (TX_PI_CTL0r_TX_PI_ENf_GET(tx_pi_reg)) { 306 *value = TX_PI_CTL1r_TX_PI_FREQ_OVERRIDE_VALf_GET(tx_pi_value_reg); 307 } else { 308 *value = 0; 309 } 310 311 return (ERR_CODE_NONE); 312 } 313 314 315 316 err_code_t eagle_tsc_identify(const phymod_access_t *pa, eagle_rev_id0_t *rev_id0, eagle_rev_id1_t *rev_id1) 317 { 318 err_code_t __err; 319 320 rev_id0->revid_rev_letter =0; 321 rev_id0->revid_rev_number =0; 322 rev_id0->revid_bonding =0; 323 rev_id0->revid_process =0; 324 rev_id0->revid_model =0; 325 326 rev_id1->revid_multiplicity =0; 327 rev_id1->revid_mdio =0; 328 rev_id1->revid_micro =0; 329 rev_id1->revid_cl72 =0; 330 rev_id1->revid_pir =0; 331 rev_id1->revid_llp =0; 332 rev_id1->revid_eee =0; 333 334 __err=ERR_CODE_NONE; 335 336 rev_id0->revid_rev_letter =rdc_revid_rev_letter(); if(__err) return(__err); 337 rev_id0->revid_rev_number =rdc_revid_rev_number(); if(__err) return(__err); 338 rev_id0->revid_bonding =rdc_revid_bonding(); if(__err) return(__err); 339 rev_id0->revid_process =rdc_revid_process(); if(__err) return(__err); 340 rev_id0->revid_model =rdc_revid_model(); if(__err) return(__err); 341 342 rev_id1->revid_multiplicity =rdc_revid_multiplicity(); if(__err) return(__err); 343 rev_id1->revid_mdio =rdc_revid_mdio(); if(__err) return(__err); 344 rev_id1->revid_micro =rdc_revid_micro(); if(__err) return(__err); 345 rev_id1->revid_cl72 =rdc_revid_cl72(); if(__err) return(__err); 346 rev_id1->revid_pir =rdc_revid_pir(); if(__err) return(__err); 347 rev_id1->revid_llp =rdc_revid_llp(); if(__err) return(__err); 348 rev_id1->revid_eee =rdc_revid_eee(); if(__err) return(__err); 349 350 return ERR_CODE_NONE; 351 } 352 353 354 err_code_t eagle_tx_rx_polarity_set(const phymod_access_t *pa, uint32_t tx_pol, uint32_t rx_pol) 355 { 356 err_code_t __err; 357 __err=ERR_CODE_NONE; 358 __err = (uint32_t) wr_tx_pmd_dp_invert(tx_pol); 359 if(__err) return(__err); 360 __err = (uint32_t) wr_rx_pmd_dp_invert(rx_pol); 361 if(__err) return(__err); 362 363 return ERR_CODE_NONE; 364 } 365 366 err_code_t eagle_tx_rx_polarity_get(const phymod_access_t *pa, uint32_t *tx_pol, uint32_t *rx_pol) 367 { 368 err_code_t __err; 369 __err=ERR_CODE_NONE; 370 *tx_pol = (uint32_t) rd_tx_pmd_dp_invert(); 371 if(__err) return(__err); 372 *rx_pol = (uint32_t) rd_rx_pmd_dp_invert(); 373 if(__err) return(__err); 374 375 return ERR_CODE_NONE; 376 } 377 378 err_code_t eagle_force_tx_set_rst (const phymod_access_t *pa, uint32_t rst) 379 { 380 LEFUN(wr_afe_tx_reset_frc_val(rst)); 381 LEFUN(wr_afe_tx_reset_frc(0x1)); 382 return ERR_CODE_NONE; 383 } 384 385 err_code_t eagle_force_tx_get_rst (const phymod_access_t *pa, uint32_t *rst) 386 { 387 err_code_t __err; 388 __err=ERR_CODE_NONE; 389 *rst=(uint32_t) rd_afe_tx_reset_frc_val(); 390 return ERR_CODE_NONE; 391 } 392 393 err_code_t eagle_force_rx_set_rst (const phymod_access_t *pa, uint32_t rst) 394 { 395 LEFUN(wr_afe_rx_reset_frc_val(rst)); 396 LEFUN(wr_afe_rx_reset_frc(0x1)); 397 return ERR_CODE_NONE; 398 } 399 400 err_code_t eagle_force_rx_get_rst (const phymod_access_t *pa, uint32_t *rst) 401 { 402 err_code_t __err; 403 __err=ERR_CODE_NONE; 404 *rst=(uint32_t) rd_afe_rx_reset_frc_val(); 405 return ERR_CODE_NONE; 406 } 407 408 409 err_code_t eagle_pll_mode_get(const phymod_access_t *pa, uint32_t *pll_mode) 410 { 411 err_code_t __err; 412 __err=ERR_CODE_NONE; 413 *pll_mode=rdc_pll_mode(); 414 *pll_mode=rdc_ams_pll_fracn_sel(); 415 if(__err) return(__err); 416 417 return ERR_CODE_NONE; 418 } 419 420 421 err_code_t eagle_osr_mode_set(const phymod_access_t *pa, int osr_mode) 422 { 423 err_code_t __err; 424 __err=ERR_CODE_NONE; 425 __err=wr_osr_mode_frc_val(osr_mode); 426 if(__err) return(__err); 427 __err=wr_osr_mode_frc(1); 428 if(__err) return(__err); 429 430 return ERR_CODE_NONE; 431 } 432 433 err_code_t eagle_osr_mode_get(const phymod_access_t *pa, int *osr_mode) 434 { 435 int osr_forced; 436 err_code_t __err; 437 __err=ERR_CODE_NONE; 438 osr_forced = rd_osr_mode_frc(); 439 if(osr_forced) { 440 *osr_mode = rd_osr_mode_frc_val(); 441 if(__err) return(__err); 442 } else { 443 *osr_mode = rd_osr_mode_pin(); 444 if(__err) return(__err); 445 } 446 447 return ERR_CODE_NONE; 448 } 449 450 err_code_t eagle_tsc_dig_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk) 451 { 452 err_code_t __err; 453 __err=ERR_CODE_NONE; 454 *lpbk=rd_dig_lpbk_en(); 455 if(__err) return(__err); 456 457 return ERR_CODE_NONE; 458 } 459 460 err_code_t eagle_tsc_rmt_lpbk_get(const phymod_access_t *pa, uint32_t *lpbk) 461 { 462 err_code_t __err; 463 __err=ERR_CODE_NONE; 464 *lpbk=rd_rmt_lpbk_en(); 465 if(__err) return(__err); 466 467 return ERR_CODE_NONE; 468 } 469 470 err_code_t eagle_core_soft_reset(const phymod_access_t *pa) 471 { 472 err_code_t __err; 473 __err=ERR_CODE_NONE; 474 __err=wrc_core_dp_s_rstb(1); 475 if(__err) return(__err); 476 477 return ERR_CODE_NONE; 478 } 479 480 /* set powerdown for tx or rx */ 481 /* tx_rx == 1 => disable (enable) power for Tx */ 482 /* tx_rx != 0 => disable (enable) power for Rx */ 483 /* pwrdn == 0 => enable power */ 484 /* pwrdn == 1 => disable power */ 485 err_code_t eagle_tsc_pwrdn_set(const phymod_access_t *pa, int tx_rx, int pwrdn) 486 { 487 err_code_t __err; 488 __err=ERR_CODE_NONE; 489 if(tx_rx) { 490 __err = (uint32_t) wr_ln_tx_s_pwrdn(pwrdn); 491 } else { 492 __err = (uint32_t) wr_ln_rx_s_pwrdn(pwrdn); 493 } 494 if(__err) return(__err); 495 496 return ERR_CODE_NONE; 497 } 498 499 err_code_t eagle_tsc_pwrdn_get(const phymod_access_t *pa, power_status_t *pwrdn) 500 { 501 err_code_t __err; 502 __err=ERR_CODE_NONE; 503 pwrdn->pll_pwrdn = 0; 504 pwrdn->tx_s_pwrdn = 0; 505 pwrdn->rx_s_pwrdn = 0; 506 pwrdn->pll_pwrdn = rdc_afe_s_pll_pwrdn(); if(__err) return(__err); 507 pwrdn->tx_s_pwrdn = rd_ln_tx_s_pwrdn(); if(__err) return(__err); 508 pwrdn->rx_s_pwrdn = rd_ln_rx_s_pwrdn(); if(__err) return(__err); 509 510 return ERR_CODE_NONE; 511 } 512 513 err_code_t eagle_pcs_lane_swap_tx(const phymod_access_t *pa, uint32_t tx_lane_map) { 514 err_code_t __err; 515 uint32_t lane_addr_0, lane_addr_1, lane_addr_2, lane_addr_3; 516 517 __err=ERR_CODE_NONE; 518 lane_addr_0 = (tx_lane_map >> 16) & 0xf; 519 lane_addr_1 = (tx_lane_map >> 20) & 0xf; 520 lane_addr_2 = (tx_lane_map >> 24) & 0xf; 521 lane_addr_3 = (tx_lane_map >> 28) & 0xf; 522 523 __err=wrc_lane_addr_0(lane_addr_0); if(__err) return(__err); 524 __err=wrc_lane_addr_1(lane_addr_1); if(__err) return(__err); 525 __err=wrc_lane_addr_2(lane_addr_2); if(__err) return(__err); 526 __err=wrc_lane_addr_3(lane_addr_3); if(__err) return(__err); 527 528 return ERR_CODE_NONE; 529 } 530 531 err_code_t eagle_pmd_lane_swap (const phymod_access_t *pa, uint32_t lane_map) { 532 err_code_t __err; 533 uint32_t lane_0, lane_1, lane_2, lane_3; 534 535 __err=ERR_CODE_NONE; 536 lane_0 = ((lane_map >> 0) & 0x3); 537 lane_1 = ((lane_map >> 4) & 0x3); 538 lane_2 = ((lane_map >> 8) & 0x3); 539 lane_3 = ((lane_map >> 12) & 0x3); 540 541 __err=wrc_tx_lane_map_0(lane_0); if(__err) return(__err); 542 __err=wrc_tx_lane_map_1(lane_1); if(__err) return(__err); 543 __err=wrc_tx_lane_map_2(lane_2); if(__err) return(__err); 544 __err=wrc_tx_lane_map_3(lane_3); if(__err) return(__err); 545 546 return ERR_CODE_NONE; 547 } 548 549 err_code_t eagle_pmd_lane_swap_tx_get (const phymod_access_t *pa, uint32_t *lane_map) { 550 err_code_t __err; 551 uint32_t lane_0, lane_1, lane_2, lane_3; 552 553 __err=ERR_CODE_NONE; 554 555 lane_0=rdc_tx_lane_map_0(); if(__err) return(__err); 556 lane_1=rdc_tx_lane_map_1(); if(__err) return(__err); 557 lane_2=rdc_tx_lane_map_2(); if(__err) return(__err); 558 lane_3=rdc_tx_lane_map_3(); if(__err) return(__err); 559 560 *lane_map = ((lane_3 & 0x3) <<12)|((lane_2 & 0x3) <<8)|((lane_1 & 0x3) <<4)|((lane_0 & 0x3) <<0); 561 562 return ERR_CODE_NONE; 563 } 564 565 err_code_t eagle_lane_hard_soft_reset_release(const phymod_access_t *pa, uint32_t enable) /* release the pmd core soft reset */ 566 { 567 err_code_t __err; 568 __err=ERR_CODE_NONE; 569 __err=wr_ln_s_rstb(enable); if(__err) return(__err); 570 571 return ERR_CODE_NONE; 572 } 573 574 err_code_t eagle_clause72_control(const phymod_access_t *pa, uint32_t cl_72_en) /* CLAUSE_72_CONTROL */ 575 { 576 err_code_t __err; 577 578 __err=ERR_CODE_NONE; 579 if (cl_72_en) { 580 __err=wr_cl72_ieee_training_enable(1); if(__err) return(__err); 581 __err=wr_cl72_ieee_restart_training(1); if(__err) return(__err); 582 __err=wr_ln_dp_s_rstb(0); if(__err) return(__err); 583 __err=wr_ln_dp_s_rstb(1); if(__err) return(__err); 584 } else { 585 __err=wr_cl72_ieee_training_enable(0); if(__err) return(__err); 586 __err=wr_cl72_ieee_restart_training(0); if(__err) return(__err); 587 __err=wr_ln_dp_s_rstb(0); if(__err) return(__err); 588 __err=wr_ln_dp_s_rstb(1); if(__err) return(__err); 589 } 590 return ERR_CODE_NONE; 591 } 592 593 err_code_t eagle_clause72_control_get(const phymod_access_t *pa, uint32_t *cl_72_en) /* CLAUSE_72_CONTROL */ 594 { 595 err_code_t __err; 596 __err=ERR_CODE_NONE; 597 *cl_72_en = rd_cl72_ieee_training_enable(); if(__err) return(__err); 598 return ERR_CODE_NONE; 599 } 600 601 /** 602 @brief Init the PMD 603 @param pmd_touched If the PMD is already initialized 604 @returns The value ERR_CODE_NONE upon successful completion 605 @details Per core PMD resets (both datapath and entire core) 606 We only intend to use this function if the PMD has never been initialized. 607 */ 608 err_code_t eagle_pmd_reset_seq(const phymod_access_t *pa, int pmd_touched) 609 { 610 if (pmd_touched == 0) { 611 LEFUN(wrc_core_s_rstb(1)); 612 LEFUN(wrc_core_dp_s_rstb(1)); 613 } 614 return (ERR_CODE_NONE); 615 } 616 617 /** 618 @brief Enable the pll reset bit 619 @param enable Controls whether to reset PLL 620 @returns The value ERR_CODE_NONE upon successful completion 621 @details 622 Resets the PLL 623 */ 624 err_code_t eagle_pll_reset_enable_set (const phymod_access_t *pa, int enable) 625 { 626 LEFUN(wrc_afe_s_pll_reset_frc_val(enable)); 627 LEFUN(wrc_afe_s_pll_reset_frc(1)); 628 return (ERR_CODE_NONE); 629 } 630 631 /** 632 @brief Read PLL range 633 */ 634 err_code_t eagle_tsc_read_pll_range (const phymod_access_t *pa, uint32_t *pll_range) 635 { 636 err_code_t __err; 637 __err=ERR_CODE_NONE; 638 *pll_range = rdc_ams_pll_range(); 639 return (ERR_CODE_NONE); 640 } 641 642 /** 643 @brief Reag signal detect 644 */ 645 err_code_t eagle_tsc_signal_detect (const phymod_access_t *pa, uint32_t *signal_detect) 646 { 647 err_code_t __err; 648 __err=ERR_CODE_NONE; 649 *signal_detect = rd_signal_detect(); 650 return (ERR_CODE_NONE); 651 } 652 653 654 err_code_t eagle_tsc_ladder_setting_to_mV(const phymod_access_t *pa, int8_t y, int16_t* level) { 655 656 /* *level = _ladder_setting_to_mV(y,0); */ 657 *level = (y*300)/127; 658 659 return(ERR_CODE_NONE); 660 } 661 662 err_code_t eagle_pll_config_get(const phymod_access_t *pa,enum eagle_tsc_pll_enum *pll_mode) 663 { 664 err_code_t __err; 665 uint32_t fracn_sel; 666 uint8_t fracn_ndiv; 667 uint32_t pll_div; 668 uint32_t pll_vco_div2; 669 __err=ERR_CODE_NONE; 670 671 pll_div=rdc_pll_mode(); 672 fracn_sel=rdc_ams_pll_fracn_sel(); 673 fracn_ndiv=rdc_ams_pll_fracn_ndiv_int(); 674 pll_vco_div2=rdc_ams_pll_vco_div2(); 675 676 if(fracn_sel == 1) { 677 switch(fracn_ndiv) { 678 case 0x52: *pll_mode = EAGLE_TSC_pll_div_82p5x; 679 break; 680 case 0x57: *pll_mode = EAGLE_TSC_pll_div_87p5x; 681 break; 682 case 0x49: if(pll_vco_div2 == 0x1) 683 *pll_mode = EAGLE_TSC_pll_div_36p8x; 684 else 685 *pll_mode = EAGLE_TSC_pll_div_73p6x; 686 break; 687 case 0xc7: *pll_mode = EAGLE_TSC_pll_div_199p04x; 688 break; 689 default: return ((ERR_CODE_INVALID_PLL_CFG)); 690 break; 691 692 } 693 } else { 694 switch(pll_div){ 695 case 0x1: *pll_mode = EAGLE_TSC_pll_div_72x; 696 break; 697 case 0xc: *pll_mode = EAGLE_TSC_pll_div_70x; 698 break; 699 case 0xa: *pll_mode = EAGLE_TSC_pll_div_66x; 700 break; 701 case 0x9: *pll_mode = EAGLE_TSC_pll_div_64x; 702 break; 703 case 0x8: *pll_mode = EAGLE_TSC_pll_div_60x; 704 break; 705 case 0x6: *pll_mode = EAGLE_TSC_pll_div_52x; 706 break; 707 case 0x3: *pll_mode = EAGLE_TSC_pll_div_42x; 708 break; 709 case 0x2: *pll_mode = EAGLE_TSC_pll_div_40x; 710 break; 711 case 0xf: *pll_mode = EAGLE_TSC_pll_div_100x; 712 break; 713 case 0xe: *pll_mode = EAGLE_TSC_pll_div_92x; 714 break; 715 case 0xb: *pll_mode = EAGLE_TSC_pll_div_68x; 716 break; 717 case 0x5: *pll_mode = EAGLE_TSC_pll_div_50x; 718 break; 719 case 0x0: *pll_mode = EAGLE_TSC_pll_div_46x; 720 break; 721 case 0xd: *pll_mode = EAGLE_TSC_pll_div_80x; 722 break; 723 default: return ((ERR_CODE_INVALID_PLL_CFG)); 724 break; 725 } 726 } 727 728 if(__err) return(__err); 729 730 return ERR_CODE_NONE; 731 } 732 733 734 err_code_t eagle_tx_lane_control_set(const phymod_access_t *pa, uint32_t en) 735 { 736 err_code_t __err; 737 __err=ERR_CODE_NONE; 738 739 __err = wr_sdk_tx_disable(en); if(__err) return(__err); 740 741 return ERR_CODE_NONE; 742 } 743 744 745 err_code_t eagle_tx_lane_control_get(const phymod_access_t *pa, uint32_t* en) 746 { 747 err_code_t __err; 748 __err=ERR_CODE_NONE; 749 750 *en = rd_sdk_tx_disable(); if(__err) return(__err); 751 752 return ERR_CODE_NONE; 753 } 754 755 err_code_t eagle_rx_lane_control_set(const phymod_access_t *pa, uint32_t en) 756 { 757 err_code_t __err; 758 __err=ERR_CODE_NONE; 759 760 if(en) { 761 __err = wr_signal_detect_frc(1); if(__err) return(__err); 762 __err = wr_signal_detect_frc_val(0); if(__err) return(__err); 763 } else { 764 __err = wr_signal_detect_frc(0); if(__err) return(__err); 765 __err = wr_signal_detect_frc_val(0); if(__err) return(__err); 766 } 767 768 return ERR_CODE_NONE; 769 } 770 771 772 err_code_t eagle_rx_lane_control_get(const phymod_access_t *pa, uint32_t* en) 773 { 774 err_code_t __err; 775 __err=ERR_CODE_NONE; 776 777 *en = rd_signal_detect_frc(); if(__err) return(__err); 778 779 return ERR_CODE_NONE; 780 } 781 782 783 err_code_t eagle_tsc_get_vco (const phymod_phy_inf_config_t* config, uint32_t *vco_rate, enum eagle_tsc_pll_enum *new_pll_div, int16_t *new_os_mode) { 784 *vco_rate = 0; 785 *new_pll_div=0; 786 *new_os_mode = 0; 787 if(config->ref_clock == phymodRefClk156Mhz) { 788 switch (config->data_rate) { 789 790 case 1250 : /* speed 1.25G ; pll_div= 40 */ 791 *new_pll_div = EAGLE_TSC_pll_div_40x; *new_os_mode = 5 /*= OS5 */; *vco_rate = 1250; /* vco_rate = */ 792 break; 793 794 case 3125 : /* speed 3.125G ; pll_div= 60 */ 795 *new_pll_div = EAGLE_TSC_pll_div_40x; *new_os_mode = 1 /*= OS2 */; *vco_rate = 6250; /* vco_rate = */ 796 break; 797 798 case 5750 : /* speed 5.75G ; fracn pll= 73.6 */ 799 *new_pll_div = EAGLE_TSC_pll_div_73p6x; *new_os_mode = 1 /*= OS2 */; *vco_rate = 11500; /* vco_rate = 24 */ 800 break; 801 802 case 6250: /* speed 6.25G: pll_div=40 */ 803 *new_pll_div = EAGLE_TSC_pll_div_40x; *new_os_mode = 0 /*= OS2 */; *vco_rate = 6250; /* vco_rate= */ 804 break; 805 806 case 10312: /* speed 10.3G; pll_div = 66 */ 807 *new_pll_div = EAGLE_TSC_pll_div_66x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 10312; /* vco_rate = 19 */ 808 break; 809 810 case 10937: /* speed 10.937G ; pll_div= 70 */ 811 *new_pll_div = EAGLE_TSC_pll_div_70x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 109375; /* vco_rate = */ 812 break; 813 814 case 11250: /* speed 11.25G ; pll_div= 72 */ 815 *new_pll_div = EAGLE_TSC_pll_div_72x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 11250; /* vco_rate = */ 816 break; 817 818 case 11500: /* speed 11.5G ; fracn pll= 73.6 */ 819 *new_pll_div = EAGLE_TSC_pll_div_73p6x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 11500; /* vco_rate = 24 */ 820 break; 821 822 case 12500: /* speed 12.5G ; pll_div = 80 */ 823 *new_pll_div = EAGLE_TSC_pll_div_80x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 12500; /* vco_rate = */ 824 break; 825 826 default: 827 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d", (int)config->data_rate, config->ref_clock)); 828 return ERR_CODE_DIAG; 829 break; 830 } 831 } else if(config->ref_clock == phymodRefClk125Mhz) { 832 switch (config->data_rate) { 833 834 case 1250 : /* speed 1.25G ; pll_div= 50 */ 835 *new_pll_div = EAGLE_TSC_pll_div_50x; *new_os_mode = 5 /*= OS5 */; *vco_rate = 6250; /* vco_rate = */ 836 break; 837 838 case 3125 : /* speed 3.125G ; pll_div= 50 */ 839 *new_pll_div = EAGLE_TSC_pll_div_50x; *new_os_mode = 1 /*= OS2 */; *vco_rate = 6250; /* vco_rate = */ 840 break; 841 842 case 5750 : /* speed 5.75G ; pll_div= 46 */ 843 *new_pll_div = EAGLE_TSC_pll_div_46x; *new_os_mode = 0 /*= OS1 */; *vco_rate =5750; /* vco_rate = */ 844 break; 845 846 case 6250: /* speed 6.25G: pll_div=50 */ 847 *new_pll_div = EAGLE_TSC_pll_div_50x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 6250; /* vco_rate= 3 */ 848 break; 849 850 case 10312: /* speed 10.3G; fracn pll = 82.5 */ 851 *new_pll_div = EAGLE_TSC_pll_div_82p5x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 10312; /* vco_rate = 19 */ 852 break; 853 854 case 11500: /* speed 11.5G ; pll_div= 92 */ 855 *new_pll_div = EAGLE_TSC_pll_div_92x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 11500; /* vco_rate = 24 */ 856 break; 857 858 case 12500: /* speed 12.5G ; pll_div= 100 */ 859 *new_pll_div = EAGLE_TSC_pll_div_100x; *new_os_mode = 0 /*= OS1 */; *vco_rate = 12500; /* vco_rate = */ 860 break; 861 862 default: 863 PHYMOD_DEBUG_ERROR(("Unsupported speed :: %d :: at ref clk :: %d", (int)config->data_rate, config->ref_clock)); 864 return ERR_CODE_DIAG; 865 break; 866 } 867 } else { 868 PHYMOD_DEBUG_ERROR(("Unsupported ref clk :: %d\n", config->ref_clock)); 869 return ERR_CODE_DIAG; 870 } 871 return(ERR_CODE_NONE); 872 } 873 874 err_code_t eagle_pmd_tx_disable_pin_dis_set(const phymod_access_t *pa, uint32_t enable) { 875 err_code_t __err; 876 __err=ERR_CODE_NONE; 877 __err=wr_pmd_tx_disable_pkill(enable); if(__err) return(__err); 878 879 return ERR_CODE_NONE; 880 } 881 882 err_code_t eagle_pmd_tx_disable_pin_dis_get(const phymod_access_t *pa, uint32_t *enable) { 883 err_code_t __err; 884 __err=ERR_CODE_NONE; 885 *enable = rd_pmd_tx_disable_pkill(); if(__err) return(__err); 886 887 return ERR_CODE_NONE; 888 } 889 890 /* Get Enable/Disable Shared TX pattern generator */ 891 err_code_t eagle_tsc_tx_shared_patt_gen_en_get( const phymod_access_t *pa, uint8_t *enable) { 892 err_code_t __err; 893 894 *enable = rd_patt_gen_en(); if(__err) return(__err); 895 return ERR_CODE_NONE; 896 } 897 898 err_code_t eagle_tsc_config_shared_tx_pattern_idx_set( const phymod_access_t *pa, const uint32_t *pattern_len ) { 899 err_code_t __err; 900 uint8_t mode_sel; 901 902 __err=ERR_CODE_NONE; 903 904 905 if(*pattern_len==240) { 906 mode_sel = 11; 907 } else if (*pattern_len== 220 ) { 908 mode_sel = 10; 909 } else if (*pattern_len == 200) { 910 mode_sel = 9; 911 } else if (*pattern_len == 180) { 912 mode_sel = 8; 913 } else if (*pattern_len == 160) { 914 mode_sel = 7; 915 } else if (*pattern_len == 140) { 916 mode_sel = 6; 917 } else { 918 mode_sel = 0; 919 PHYMOD_DEBUG_ERROR(("Invalid length input!\n")); 920 return ERR_CODE_DIAG; 921 } 922 923 if(mode_sel !=0){ 924 __err = wr_patt_gen_start_pos(mode_sel); 925 } 926 if(__err) return(__err); 927 928 /* 929 for (pattern_idx=0;pattern_idx<PATTERN_MAX_SIZE;pattern_idx++) { 930 931 lsb = (uint16_t) (pattern[pattern_idx] & 0xffff); 932 msb = (uint16_t) ((pattern[pattern_idx]>>16) & 0xffff); 933 934 switch (pattern_idx) { 935 case 0: 936 __err=wrc_patt_gen_seq_14(msb); if(__err) return(__err); 937 __err=wrc_patt_gen_seq_13(lsb); if(__err) return(__err); 938 break; 939 case 1: 940 __err=wrc_patt_gen_seq_12(msb); if(__err) return(__err); 941 __err=wrc_patt_gen_seq_11(lsb); if(__err) return(__err); 942 break; 943 case 2: 944 __err=wrc_patt_gen_seq_10(msb); if(__err) return(__err); 945 __err=wrc_patt_gen_seq_9(lsb); if(__err) return(__err); 946 break; 947 case 3: 948 __err=wrc_patt_gen_seq_8(msb); if(__err) return(__err); 949 __err=wrc_patt_gen_seq_7(lsb); if(__err) return(__err); 950 break; 951 case 4: 952 __err=wrc_patt_gen_seq_6(msb); if(__err) return(__err); 953 __err=wrc_patt_gen_seq_5(lsb); if(__err) return(__err); 954 break; 955 case 5: 956 __err=wrc_patt_gen_seq_4(msb); if(__err) return(__err); 957 __err=wrc_patt_gen_seq_3(lsb); if(__err) return(__err); 958 break; 959 case 6: 960 __err=wrc_patt_gen_seq_2(msb); if(__err) return(__err); 961 __err=wrc_patt_gen_seq_1(lsb); if(__err) return(__err); 962 break; 963 case 7: 964 __err=wrc_patt_gen_seq_0(msb); if(__err) return(__err); 965 break; 966 */ /* Its a dead default and cause coverity defect 967 default: 968 PHYMOD_DEBUG_ERROR(("Wrong index value : Should be between 0 and 7\n")); 969 return ERR_CODE_DIAG; 970 break;*/ 971 /* } 972 }*/ 973 return ERR_CODE_NONE; 974 } 975 976 err_code_t eagle_tsc_config_shared_tx_pattern_idx_get( const phymod_access_t *pa, uint32_t *pattern_len, uint32_t *pattern) { 977 err_code_t __err; 978 uint8_t mode_sel; 979 uint32_t lsb = 0, msb = 0; 980 int pattern_idx; 981 982 __err=ERR_CODE_NONE; 983 984 mode_sel = rd_patt_gen_start_pos(); if(__err) return(__err); 985 986 mode_sel = 12 - mode_sel; 987 988 if(mode_sel == 6) { 989 *pattern_len = 140; 990 } else if (mode_sel == 5) { 991 *pattern_len = 160; 992 } else if (mode_sel == 4) { 993 *pattern_len = 180; 994 } else if (mode_sel == 3) { 995 *pattern_len = 200; 996 } else if (mode_sel == 2) { 997 *pattern_len = 220; 998 } else if (mode_sel == 1) { 999 *pattern_len = 240; 1000 } else { 1001 *pattern_len = 0; 1002 } 1003 1004 for (pattern_idx=0;pattern_idx<PATTERN_MAX_SIZE;pattern_idx++) { 1005 switch (pattern_idx) { 1006 case 0: 1007 msb=rdc_patt_gen_seq_14(); if(__err) return(__err); 1008 lsb=rdc_patt_gen_seq_13(); if(__err) return(__err); 1009 break; 1010 case 1: 1011 msb=rdc_patt_gen_seq_12(); if(__err) return(__err); 1012 lsb=rdc_patt_gen_seq_11(); if(__err) return(__err); 1013 break; 1014 case 2: 1015 msb=rdc_patt_gen_seq_10(); if(__err) return(__err); 1016 lsb=rdc_patt_gen_seq_9(); if(__err) return(__err); 1017 break; 1018 case 3: 1019 msb=rdc_patt_gen_seq_8(); if(__err) return(__err); 1020 lsb=rdc_patt_gen_seq_7(); if(__err) return(__err); 1021 break; 1022 case 4: 1023 msb=rdc_patt_gen_seq_6(); if(__err) return(__err); 1024 lsb=rdc_patt_gen_seq_5(); if(__err) return(__err); 1025 break; 1026 case 5: 1027 msb=rdc_patt_gen_seq_4(); if(__err) return(__err); 1028 lsb=rdc_patt_gen_seq_3(); if(__err) return(__err); 1029 break; 1030 case 6: 1031 msb=rdc_patt_gen_seq_2(); if(__err) return(__err); 1032 lsb=rdc_patt_gen_seq_1(); if(__err) return(__err); 1033 break; 1034 case 7: 1035 msb=rdc_patt_gen_seq_0(); if(__err) return(__err); 1036 lsb=0; 1037 break; 1038 /* Its a dead default and cause coverity defect 1039 default: 1040 PHYMOD_DEBUG_ERROR(("Wrong index value : Should be between 0 and 7\n")); 1041 return ERR_CODE_DIAG; 1042 break;*/ 1043 } 1044 1045 pattern[pattern_idx] = (msb <<16) | lsb; 1046 } 1047 1048 return ERR_CODE_NONE; 1049 } 1050 1051 err_code_t eagle_tsc_rx_ppm(const phymod_access_t *pa, int16_t *rx_ppm) 1052 { 1053 err_code_t __err; 1054 __err=ERR_CODE_NONE; 1055 *rx_ppm = rd_cdr_integ_reg() / 84; 1056 return (ERR_CODE_NONE); 1057 } 1058