dino.c (54471B)
1 /* 2 * 3 * 4 * 5 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 6 * 7 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 8 */ 9 10 #include <phymod/phymod.h> 11 #include <phymod/phymod_system.h> 12 #include <phymod/phymod_dispatch.h> 13 #include <phymod/phymod_diagnostics.h> 14 #include <phymod/phymod_diagnostics_dispatch.h> 15 #include <phymod/chip/dino.h> 16 17 #include "../tier1/bcmi_dino_defs.h" 18 #include "../tier1/dino_cfg_seq.h" 19 #include "../tier1/dino_diag_seq.h" 20 #include "../tier1/dino_serdes/common/srds_api_enum.h" 21 22 /** Core identify 23 * This function reads PMD Identifiers, Set is identified if 24 * dino identified. 25 * 26 * @param core Pointer to phymod core access structure 27 * @param core_id Core ID which is supplied by interface layer 28 * @param is_identified Flag variable to return device 29 * identification status 30 * 31 * @return PHYMOD_E_NONE successful function execution 32 */ 33 int dino_core_identify(const phymod_core_access_t* core, uint32_t core_id, uint32_t* is_identified) 34 { 35 const phymod_access_t *pm_acc = &core->access; 36 uint32_t chip_id = 0; 37 uint32_t rev_id = 0; 38 *is_identified = 0; 39 40 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pm_acc, &chip_id, &rev_id)); 41 if ((chip_id == DINO_CHIP_ID_82332) || 42 (chip_id == DINO_CHIP_ID_82793) || 43 (chip_id == DINO_CHIP_ID_82795)) { 44 *is_identified = 0x80000001; 45 } 46 47 return PHYMOD_E_NONE; 48 } 49 50 /** Core information 51 * This function gives the core version 52 * 53 * @param core Pointer to phymod core access structure 54 * @param info Pointer to core version 55 * 56 * @return PHYMOD_E_NONE successful function execution 57 */ 58 int dino_core_info_get(const phymod_core_access_t* core, phymod_core_info_t* info) 59 { 60 uint32_t chip_id = 0; 61 uint32_t rev_id = 0; 62 PMD_IDENTIFIERr_t id0; 63 IEEE_PMA_PMD_BLK0_PMD_IDENTIFIERr_t id1; 64 PHYMOD_MEMSET(&id0, 0, sizeof(PMD_IDENTIFIERr_t)); 65 PHYMOD_MEMSET(&id1, 0, sizeof(IEEE_PMA_PMD_BLK0_PMD_IDENTIFIERr_t)); 66 67 PHYMOD_IF_ERR_RETURN ( 68 dino_get_chipid(&core->access, &chip_id, &rev_id)); 69 info->serdes_id = chip_id; 70 info->core_version = phymodCoreVersionDino; 71 72 PHYMOD_IF_ERR_RETURN( 73 READ_IEEE_PMA_PMD_BLK0_PMD_IDENTIFIERr(&core->access, &id1)); 74 info->phy_id1 = id1.v[0]; 75 PHYMOD_IF_ERR_RETURN( 76 READ_PMD_IDENTIFIERr(&core->access, &id0)); 77 info->phy_id0 = id0.v[0]; 78 PHYMOD_STRCPY(info->name, "Dino"); 79 80 return PHYMOD_E_NONE; 81 } 82 83 84 /** Core Reset 85 * This function reset dino core, it support hard and soft reset 86 * 87 * @param core Pointer to phymod core access structure 88 * @param reset_mode Represent hard/soft reset to perform 89 * @param direction Represet direction of reset. dino ignore this parameter 90 * 91 * @return PHYMOD_E_NONE successful function execution 92 */ 93 int dino_core_reset_set(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 94 { 95 return _dino_core_reset_set(&core->access, reset_mode, direction); 96 97 } 98 99 int dino_core_reset_get(const phymod_core_access_t* core, phymod_reset_mode_t reset_mode, phymod_reset_direction_t* direction) 100 { 101 102 /* Place your code here */ 103 return PHYMOD_E_UNAVAIL; 104 } 105 106 /** Get Firmware info 107 * This function get the firmware information such as master firmware version and master checksum 108 * 109 * @param core Pointer to phymod core access structure 110 * @param fw_info Represent firmware version and checksum. 111 * 112 * @return PHYMOD_E_NONE successful function execution 113 */ 114 int dino_core_firmware_info_get(const phymod_core_access_t* core, phymod_core_firmware_info_t* fw_info) 115 { 116 FIRMWARE_VERSIONr_t firmware_version; 117 DWNLD_15r_t dwnld_15; 118 DWNLD_16r_t dwnld_16; 119 DWNLD_17r_t dwnld_17; 120 121 /* Read the firmware version */ 122 PHYMOD_IF_ERR_RETURN( 123 READ_FIRMWARE_VERSIONr(&core->access, &firmware_version)); 124 125 fw_info->fw_version = FIRMWARE_VERSIONr_FIRMWARE_VERSION_VALf_GET(firmware_version); 126 127 PHYMOD_IF_ERR_RETURN( 128 READ_DWNLD_15r(&core->access, &dwnld_15)); 129 PHYMOD_IF_ERR_RETURN( 130 READ_DWNLD_16r(&core->access, &dwnld_16)); 131 PHYMOD_IF_ERR_RETURN( 132 READ_DWNLD_17r(&core->access, &dwnld_17)); 133 134 if ((dwnld_15.v[0] == 0x600D) && (dwnld_16.v[0] == 0x600D) && (dwnld_17.v[0] == 0x600D)) { 135 fw_info->fw_crc = dwnld_15.v[0]; 136 } 137 138 return PHYMOD_E_NONE; 139 } 140 141 /** Set interface config 142 * This function sets interface configuration (interface, speed, frequency of 143 * operation, PT mode, BCM84793 etc). 144 * This is requried to put the chip into specific mode specified 145 * 146 * NOTE: Default system side interface type will be IEEE mode and speed is compatible with lane side configured speed. 147 * Ex: User configured 40G speed with interface type KR4 on lane side then system side speed is 40G and interface type is IEEE mode. 148 * 149 * @param phy Pointer to phymod phy access structure 150 * @param flags Reserved for future use 151 * @param config Interface config structure where user specifies 152 * - Interface Type 153 * - Speed 154 * - Frequency. 155 * - device_aux_modes : a structure that have auxilary mode details 156 * -> pass_thru : Set it to 0 for Gearbox and 1 for Passthrough 157 * 158 * @return PHYMOD_E_NONE successful function execution 159 */ 160 161 int dino_phy_interface_config_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_phy_inf_config_t* config) 162 { 163 return (_dino_phy_interface_config_set(phy, flags, config)); 164 } 165 166 /** Get interface config 167 * This function gets interface configuration (interface, speed, frequency of 168 * operation, PT mode). 169 * 170 * NOTE: Default system side interface type will be IEEE mode and speed is compatible with lane side configured speed. 171 * Ex: User configured 40G speed with interface type KR4 on lane side then system side speed is 40G and interface type is IEEE mode. 172 * 173 * @param phy Pointer to phymod phy access structure 174 * @param flags Reserved for future use 175 * @param ref_clock Reference Clock 176 * @param config Gets Interface config such as, 177 * - Interface Type 178 * - Speed 179 * - Frequency. 180 * - device_aux_modes : a structure that have auxilary mode details 181 * -> pass_thru : 0 for Gearbox and 1 for Passthrough 182 * 183 * @return PHYMOD_E_NONE successful function execution 184 */ 185 186 int dino_phy_interface_config_get(const phymod_phy_access_t* phy, uint32_t flags, uint32_t ref_clock, phymod_phy_inf_config_t* config) 187 { 188 int rv = PHYMOD_E_NONE; 189 phymod_phy_access_t phy_copy; 190 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 191 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 192 rv = _dino_phy_interface_config_get(&phy_copy, flags, config); 193 phy = &phy_copy; 194 return rv; 195 } 196 197 /** dino core initialization 198 * This function initialize the dino core by downlaoding the firmware. 199 * 200 * @param core Pointer to phymod core access structure 201 * @param init_config Init configuration specified by user 202 * @param core_status PMD status read from PHY chip 203 * 204 * @return PHYMOD_E_NONE successful function execution 205 */ 206 207 int dino_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config, const phymod_core_status_t* core_status) 208 { 209 return (_dino_core_init(core, init_config)); 210 } 211 212 int dino_phy_init(const phymod_phy_access_t* phy, const phymod_phy_init_config_t* init_config) 213 { 214 phymod_polarity_t polarity; 215 phymod_phy_access_t phy_copy; 216 217 PHYMOD_MEMSET(&polarity, 0, sizeof(phymod_polarity_t)); 218 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 219 220 if ((init_config->polarity.tx_polarity != 0) || 221 (init_config->polarity.rx_polarity != 0)) { 222 if ((init_config->interface.data_rate != DINO_SPD_100G) && 223 (init_config->interface.data_rate != DINO_SPD_106G)) { 224 PHYMOD_IF_ERR_RETURN( 225 dino_phy_polarity_get (phy, &polarity)); 226 polarity.rx_polarity &= ~(phy->access.lane_mask); 227 polarity.rx_polarity |= (init_config->polarity.rx_polarity & phy->access.lane_mask); 228 polarity.tx_polarity &= ~(phy->access.lane_mask); 229 polarity.tx_polarity |= (init_config->polarity.tx_polarity & phy->access.lane_mask); 230 } else { 231 polarity.rx_polarity = init_config->polarity.rx_polarity; 232 polarity.tx_polarity = init_config->polarity.tx_polarity; 233 } 234 235 PHYMOD_IF_ERR_RETURN( 236 dino_phy_polarity_set (phy, &polarity)); 237 } 238 239 /*enable/disable repeater/retimer*/ 240 if (init_config->op_mode == phymodOperationModeRetimer) { 241 PHYMOD_IF_ERR_RETURN 242 (_dino_phy_rptr_rtmr_mode_set(phy, phymodOperationModeRetimer)); 243 } else { 244 /* By default HW set it as repeater*/ 245 PHYMOD_IF_ERR_RETURN 246 (_dino_phy_rptr_rtmr_mode_set(phy, phymodOperationModeRepeater)); 247 } 248 249 /* Looback disable during phy_init to be defult */ 250 PHYMOD_IF_ERR_RETURN 251 (dino_phy_loopback_set(phy, phymodLoopbackGlobalPMD, DINO_DISABLE)); 252 PHYMOD_IF_ERR_RETURN 253 (dino_phy_loopback_set(phy, phymodLoopbackRemotePMD, DINO_DISABLE)); 254 /* system side interface bit shift */ 255 phy_copy.port_loc = phymodPortLocSys; 256 PHYMOD_IF_ERR_RETURN 257 (dino_phy_loopback_set(&phy_copy, phymodLoopbackGlobalPMD, DINO_DISABLE)); 258 PHYMOD_IF_ERR_RETURN 259 (dino_phy_loopback_set(&phy_copy, phymodLoopbackRemotePMD, DINO_DISABLE)); 260 return PHYMOD_E_NONE; 261 } 262 263 /** Set loopback 264 * This function is used to set a particular loopback mode 265 * 266 * @param phy Pointer to phymod phy access structure 267 * @param loopback Type of loopback 268 * 0 - Global loopback 269 * 1 - Global PMD loopback 270 * 2 - Remote PMD loopback 271 * 3 - Remote PCS loopback 272 * 4 - Digital PMD loopback 273 * @param enable Enable or disable 274 * 0 - disable 275 * 1 - enable 276 * 277 * @return PHYMOD_E_NONE successful function execution 278 */ 279 int dino_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable) 280 { 281 uint16_t lane = 0; 282 uint16_t lane_mask = 0; 283 uint16_t if_side = 0; 284 uint32_t ena_dis = 0; 285 int num_lanes = 0; 286 uint32_t chip_id = 0; 287 uint32_t rev_id = 0; 288 BCMI_DINO_FIRMWARE_ENr_t fw_en; 289 BCMI_DINO_DECD_MODE_STS0r_t mode_sts0; 290 uint16_t gpreg_data = 0; 291 const phymod_access_t *pa = &phy->access; 292 PHYMOD_MEMSET(&fw_en, 0 , sizeof(BCMI_DINO_FIRMWARE_ENr_t)); 293 PHYMOD_MEMSET(&mode_sts0, 0, sizeof(BCMI_DINO_DECD_MODE_STS0r_t)); 294 295 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 296 DINO_GET_INTF_SIDE(phy, if_side); 297 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 298 DINO_GET_NUM_LANES(chip_id, num_lanes); 299 300 PHYMOD_DEBUG_VERBOSE(("Dino looopback set\n")); 301 302 PHYMOD_IF_ERR_RETURN( 303 BCMI_DINO_READ_DECD_MODE_STS0r(pa, &mode_sts0)); 304 /* Check to see if the mode of operation is 100G PT. For 100G PT, 305 * dino_fw_enable needs to be called only once 306 */ 307 if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100Gf_GET(mode_sts0)) { 308 if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_PT_2TO11f_GET(mode_sts0)) { 309 lane_mask = DINO_100G_TYPE3_LANE_MASK; 310 } else if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_PT_1TO10f_GET(mode_sts0)) { 311 lane_mask = DINO_100G_TYPE2_LANE_MASK; 312 } else if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_PT_0TO9f_GET(mode_sts0)) { 313 lane_mask = DINO_100G_TYPE1_LANE_MASK; 314 } else { 315 lane_mask = DINO_100G_TYPE1_LANE_MASK; 316 } 317 if (enable) { 318 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 319 gpreg_data &= ~(DINO_FW_SM_ENABLE_MASK); 320 gpreg_data |= (DINO_FW_SM_ENABLE_MASK); 321 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 322 PHYMOD_IF_ERR_RETURN 323 (_dino_fw_enable(pa)); 324 } 325 for (lane = 0; lane < num_lanes; lane ++) { 326 if ((lane_mask & (1 << lane))) { 327 PHYMOD_IF_ERR_RETURN( 328 _dino_loopback_get(pa, if_side, lane, loopback, &ena_dis)); 329 if (ena_dis || enable) { 330 PHYMOD_IF_ERR_RETURN( 331 _dino_loopback_set(pa, if_side, lane, loopback, enable)); 332 } 333 } 334 } 335 if (!enable && ena_dis) { 336 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 337 gpreg_data &= ~(DINO_FW_SM_ENABLE_MASK); 338 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 339 PHYMOD_IF_ERR_RETURN 340 (_dino_fw_enable(pa)); 341 } 342 } else { 343 for (lane = 0; lane < num_lanes; lane ++) { 344 if ((lane_mask & (1 << lane))) { 345 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + lane), gpreg_data); 346 if (enable) { 347 gpreg_data &= ~(DINO_FW_SM_ENABLE_MASK); 348 gpreg_data |= (DINO_FW_SM_ENABLE_MASK); 349 } 350 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + lane), gpreg_data); 351 } 352 } 353 PHYMOD_IF_ERR_RETURN 354 (_dino_fw_enable(pa)); 355 356 for (lane = 0; lane < num_lanes; lane ++) { 357 if ((lane_mask & (1 << lane))) { 358 PHYMOD_IF_ERR_RETURN( 359 _dino_loopback_get(pa, if_side, lane, loopback, &ena_dis)); 360 if (ena_dis || enable) { 361 PHYMOD_IF_ERR_RETURN( 362 _dino_loopback_set(pa, if_side, lane, loopback, enable)); 363 } 364 } 365 } 366 367 for (lane = 0; lane < num_lanes; lane ++) { 368 if ((lane_mask & (1 << lane))) { 369 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + lane), gpreg_data); 370 if (!enable) { 371 gpreg_data &= ~(DINO_FW_SM_ENABLE_MASK); 372 } 373 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + lane), gpreg_data); 374 } 375 } 376 PHYMOD_IF_ERR_RETURN 377 (_dino_fw_enable(pa)); 378 } 379 380 return PHYMOD_E_NONE; 381 } 382 383 /** Get loopback 384 * This function is used to get the status of a particular loopback mode 385 * whether or not enabled 386 * 387 * @param phy Pointer to phymod phy access structure 388 * @param loopback Type of loopback 389 * 0 - Global loopback 390 * 1 - Global PMD loopback 391 * 2 - Remote PMD loopback 392 * 3 - Remote PCS loopback 393 * 4 - Digital PMD loopback 394 * @param enable Enable or disable 395 * 0 - disable 396 * 1 - enable 397 * 398 * @return PHYMOD_E_NONE successful function execution 399 */ 400 int dino_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable) 401 { 402 uint16_t lane = 0; 403 uint16_t lane_mask = 0; 404 uint16_t if_side = 0; 405 int num_lanes = 0; 406 uint32_t chip_id = 0; 407 uint32_t rev_id = 0; 408 const phymod_access_t *pa = &phy->access; 409 410 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 411 DINO_GET_INTF_SIDE(phy, if_side); 412 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 413 DINO_GET_NUM_LANES(chip_id, num_lanes); 414 415 for (lane = 0; lane < num_lanes; lane ++) { 416 if ((lane_mask & (1 << lane))) { 417 PHYMOD_IF_ERR_RETURN ( 418 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 419 PHYMOD_IF_ERR_RETURN( 420 _dino_loopback_get(pa, if_side, lane, loopback, enable)); 421 } 422 } 423 PHYMOD_IF_ERR_RETURN ( 424 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 425 426 return PHYMOD_E_NONE; 427 } 428 /** Get PHY RX PMD link status 429 * This function retrieves RX PMD lock status of dino 430 * 431 * @param phy Pointer to phymod phy access structure 432 * @param rx_pmd_locked Rx PMD Link status retrieved from dino 433 * 434 * @return PHYMOD_E_NONE successful function execution 435 */ 436 437 int dino_phy_rx_pmd_locked_get(const phymod_phy_access_t* phy, uint32_t* rx_pmd_locked) 438 { 439 uint16_t lane = 0; 440 uint16_t lane_mask = 0; 441 uint16_t if_side = 0; 442 int num_lanes = 0; 443 uint32_t chip_id = 0; 444 uint32_t rev_id = 0; 445 const phymod_access_t *pa = &phy->access; 446 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 447 DINO_GET_INTF_SIDE(phy, if_side); 448 *rx_pmd_locked = 1; 449 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 450 DINO_GET_NUM_LANES(chip_id, num_lanes); 451 452 for (lane = 0; lane < num_lanes; lane ++) { 453 if ((lane_mask & (1 << lane))) { 454 PHYMOD_IF_ERR_RETURN ( 455 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 456 PHYMOD_IF_ERR_RETURN( 457 _dino_rx_pmd_lock_get(pa, if_side, lane, rx_pmd_locked)); 458 } 459 } 460 PHYMOD_IF_ERR_RETURN ( 461 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 462 463 return PHYMOD_E_NONE; 464 } 465 466 /** Get PCS link status 467 * This function retrieves PCS link status of dino when PCS Monitor is enabled, 468 * This function return PMD lock when PCS monitor is disabled. 469 * 470 * @param phy Pointer to phymod phy access structure 471 * @param link_status Retrives PCS Link of dino 472 * 473 * @return PHYMOD_E_NONE successful function execution 474 */ 475 476 int dino_phy_link_status_get(const phymod_phy_access_t* phy, uint32_t* link_status) 477 { 478 uint16_t lane = 0; 479 uint16_t lane_mask = 0; 480 uint16_t if_side = 0; 481 int num_lanes = 0; 482 uint32_t chip_id = 0; 483 uint32_t rev_id = 0; 484 uint32_t enable = 0; 485 uint32_t lock_status = 0; 486 uint32_t lock_lost_lh = 0; 487 uint32_t error_count = 0; 488 const phymod_access_t *pa = &phy->access; 489 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 490 DINO_GET_INTF_SIDE(phy, if_side); 491 *link_status = 1; 492 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 493 DINO_GET_NUM_LANES(chip_id, num_lanes); 494 495 lock_status = 1; 496 lock_lost_lh = 1; 497 error_count = 0; 498 enable = 1; 499 500 for (lane = 0; lane < num_lanes; lane ++) { 501 if ((lane_mask & (1 << lane))) { 502 PHYMOD_IF_ERR_RETURN ( 503 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 504 PHYMOD_IF_ERR_RETURN( 505 _dino_get_rx_pmd_lock_status(pa, if_side, lane, link_status)); 506 PHYMOD_IF_ERR_RETURN ( 507 _dino_phy_link_mon_enable_get(pa, &enable)); 508 if (enable) { 509 PHYMOD_IF_ERR_RETURN ( 510 _dino_phy_link_mon_status_get(pa, &lock_status, &lock_lost_lh, &error_count)); 511 *link_status &= lock_status; 512 } 513 } 514 } 515 PHYMOD_IF_ERR_RETURN ( 516 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 517 518 return PHYMOD_E_NONE; 519 } 520 521 /** Read Register 522 * This function read user specified register based on the specified Device type 523 * 524 * @param phy Pointer to phymod phy access structure. 525 * @param reg_addr dino register address 526 * @param val Output parameter, represents the value of address specified 527 * 528 * @return PHYMOD_E_NONE successful function execution 529 */ 530 int dino_phy_reg_read(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t* val) 531 { 532 uint16_t dev_add = 0; 533 dev_add = (phy->access.devad) ? phy->access.devad : DINO_DEV_PMA_PMD; 534 535 if (dev_add == DINO_DEV_PMA_PMD) { 536 READ_DINO_PMA_PMD_REG(&phy->access, reg_addr, *val); 537 } else { 538 READ_DINO_AN_REG(&phy->access, reg_addr, *val); 539 } 540 541 return PHYMOD_E_NONE; 542 } 543 544 /** Write Register 545 * This function write user specified value to the specified address 546 * based on the specified Device type 547 * 548 * @param phy Pointer to phymod phy access structure. 549 * @param reg_addr dino register address 550 * @param val Represents the value to be written 551 * 552 * @return PHYMOD_E_NONE successful function execution 553 */ 554 int dino_phy_reg_write(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t val) 555 { 556 uint16_t dev_add = 0; 557 558 dev_add = (phy->access.devad) ? phy->access.devad : DINO_DEV_PMA_PMD; 559 if (dev_add == DINO_DEV_PMA_PMD) { 560 WRITE_DINO_PMA_PMD_REG(&phy->access, reg_addr, val); 561 } else { 562 WRITE_DINO_AN_REG(&phy->access, reg_addr, val); 563 } 564 565 return PHYMOD_E_NONE; 566 } 567 568 /** Retrives Revision 569 * This function retrives dino revision ID 570 * 571 * @param phy Pointer to phymod phy access structure. 572 * @param rev_id Output parameter, Represents the revision ID of dino. 573 * 574 * @return PHYMOD_E_NONE successful function execution 575 */ 576 int dino_phy_rev_id(const phymod_phy_access_t* phy, uint32_t *rev_id) 577 { 578 uint32_t chip_id = 0; 579 580 PHYMOD_IF_ERR_RETURN ( 581 dino_get_chipid(&phy->access, &chip_id, rev_id)); 582 583 return PHYMOD_E_NONE; 584 } 585 586 /** PHY status dump 587 * This function is used to display status dump of a core and for given lane 588 * 589 * @param phy Pointer to phymod phy access structure 590 * 591 * @return PHYMOD_E_NONE successful function execution 592 */ 593 int dino_phy_status_dump(const phymod_phy_access_t* phy) 594 { 595 uint16_t lane = 0; 596 uint16_t lane_mask = 0; 597 uint16_t if_side = 0; 598 int num_lanes = 0; 599 uint32_t chip_id = 0; 600 uint32_t rev_id = 0; 601 const phymod_access_t *pa = &phy->access; 602 603 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 604 DINO_GET_INTF_SIDE(phy, if_side); 605 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 606 DINO_GET_NUM_LANES(chip_id, num_lanes); 607 608 PHYMOD_DEBUG_VERBOSE(("**********************************************\n")); 609 PHYMOD_DEBUG_VERBOSE(("******* PHY status dump for PHY ID:%d ********\n", pa->addr)); 610 PHYMOD_DEBUG_VERBOSE(("**********************************************\n")); 611 PHYMOD_DEBUG_VERBOSE(("**** PHY status dump for interface side:%d ****\n", if_side)); 612 PHYMOD_DEBUG_VERBOSE(("***********************************************\n")); 613 614 /* For core status dump */ 615 for (lane = 0; lane < num_lanes; lane ++) { 616 if ((lane_mask & (1 << lane))) { 617 PHYMOD_IF_ERR_RETURN ( 618 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 619 PHYMOD_IF_ERR_RETURN( 620 _dino_phy_status_dump(pa, if_side, lane)); 621 } 622 } 623 624 PHYMOD_IF_ERR_RETURN ( 625 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 626 return PHYMOD_E_NONE; 627 } 628 int dino_phy_rx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t* rx_control) 629 { 630 uint16_t lane = 0; 631 uint16_t lane_mask = 0; 632 uint16_t if_side = 0; 633 int num_lanes = 0; 634 uint32_t chip_id = 0; 635 uint32_t rev_id = 0; 636 const phymod_access_t *pa = &phy->access; 637 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 638 DINO_GET_INTF_SIDE(phy, if_side); 639 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 640 DINO_GET_NUM_LANES(chip_id, num_lanes); 641 642 for (lane = 0; lane < num_lanes; lane ++) { 643 if ((lane_mask & (1 << lane))) { 644 PHYMOD_IF_ERR_RETURN ( 645 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 646 PHYMOD_IF_ERR_RETURN( 647 _dino_phy_rx_lane_control_get(pa, if_side, lane, rx_control)); 648 break; 649 } 650 } 651 PHYMOD_IF_ERR_RETURN ( 652 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 653 return PHYMOD_E_NONE; 654 } 655 656 int dino_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 657 { 658 return (_dino_phy_autoneg_set(phy, an)); 659 } 660 661 int dino_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an, uint32_t* an_done) 662 { 663 return (_dino_phy_autoneg_get(phy, an, an_done)); 664 } 665 666 int dino_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx) 667 { 668 uint16_t lane = 0; 669 uint16_t lane_mask = 0; 670 uint16_t if_side = 0; 671 int num_lanes = 0; 672 uint32_t chip_id = 0; 673 uint32_t rev_id = 0; 674 const phymod_access_t *pa = &phy->access; 675 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 676 DINO_GET_INTF_SIDE(phy, if_side); 677 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 678 DINO_GET_NUM_LANES(chip_id, num_lanes); 679 680 for (lane = 0; lane < num_lanes; lane ++) { 681 if ((lane_mask & (1 << lane))) { 682 PHYMOD_IF_ERR_RETURN(_dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 683 PHYMOD_IF_ERR_RETURN(_dino_phy_tx_set(pa, if_side, lane, tx)); 684 } 685 } 686 PHYMOD_IF_ERR_RETURN ( 687 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 688 689 return PHYMOD_E_NONE; 690 } 691 692 int dino_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx) 693 { 694 uint16_t lane = 0; 695 uint16_t lane_mask = 0; 696 uint16_t if_side = 0; 697 int num_lanes = 0; 698 uint32_t chip_id = 0; 699 uint32_t rev_id = 0; 700 const phymod_access_t *pa = &phy->access; 701 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 702 DINO_GET_INTF_SIDE(phy, if_side); 703 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 704 DINO_GET_NUM_LANES(chip_id, num_lanes); 705 706 for (lane = 0; lane < num_lanes; lane ++) { 707 if ((lane_mask & (1 << lane))) { 708 PHYMOD_IF_ERR_RETURN ( 709 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 710 PHYMOD_IF_ERR_RETURN( 711 _dino_phy_tx_get(pa, if_side, lane, tx)); 712 break; 713 } 714 } 715 PHYMOD_IF_ERR_RETURN ( 716 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 717 718 return PHYMOD_E_NONE; 719 } 720 721 int dino_phy_rx_set(const phymod_phy_access_t* phy, const phymod_rx_t* rx) 722 { 723 uint16_t lane = 0; 724 uint16_t lane_mask = 0; 725 uint16_t if_side = 0; 726 int num_lanes = 0; 727 uint32_t chip_id = 0; 728 uint32_t rev_id = 0; 729 const phymod_access_t *pa = &phy->access; 730 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 731 DINO_GET_INTF_SIDE(phy, if_side); 732 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 733 DINO_GET_NUM_LANES(chip_id, num_lanes); 734 735 for (lane = 0; lane < num_lanes; lane ++) { 736 if ((lane_mask & (1 << lane))) { 737 PHYMOD_IF_ERR_RETURN ( 738 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 739 PHYMOD_IF_ERR_RETURN( 740 _dino_phy_rx_set(pa, if_side, lane, rx)); 741 } 742 } 743 PHYMOD_IF_ERR_RETURN ( 744 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 745 746 return PHYMOD_E_NONE; 747 } 748 749 int dino_phy_rx_get(const phymod_phy_access_t* phy, phymod_rx_t* rx) 750 { 751 uint16_t lane = 0; 752 uint16_t lane_mask = 0; 753 uint16_t if_side = 0; 754 int num_lanes = 0; 755 uint32_t chip_id = 0; 756 uint32_t rev_id = 0; 757 const phymod_access_t *pa = &phy->access; 758 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 759 DINO_GET_INTF_SIDE(phy, if_side); 760 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 761 DINO_GET_NUM_LANES(chip_id, num_lanes); 762 763 for (lane = 0; lane < num_lanes; lane ++) { 764 if ((lane_mask & (1 << lane))) { 765 PHYMOD_IF_ERR_RETURN ( 766 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 767 PHYMOD_IF_ERR_RETURN( 768 _dino_phy_rx_get(pa, if_side, lane, rx)); 769 } 770 } 771 PHYMOD_IF_ERR_RETURN ( 772 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 773 774 return PHYMOD_E_NONE; 775 } 776 777 int dino_phy_rx_adaptation_resume(const phymod_phy_access_t* phy) 778 { 779 uint16_t lane = 0; 780 uint16_t lane_mask = 0; 781 uint16_t if_side = 0; 782 int num_lanes = 0; 783 uint32_t chip_id = 0; 784 uint32_t rev_id = 0; 785 const phymod_access_t *pa = &phy->access; 786 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 787 DINO_GET_INTF_SIDE(phy, if_side); 788 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 789 DINO_GET_NUM_LANES(chip_id, num_lanes); 790 791 for (lane = 0; lane < num_lanes; lane ++) { 792 if ((lane_mask & (1 << lane))) { 793 PHYMOD_IF_ERR_RETURN ( 794 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 795 PHYMOD_IF_ERR_RETURN( 796 _dino_phy_rx_adaptation_resume(pa, if_side, lane)); 797 } 798 } 799 PHYMOD_IF_ERR_RETURN ( 800 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 801 802 return PHYMOD_E_NONE; 803 } 804 805 int dino_phy_power_set(const phymod_phy_access_t* phy, const phymod_phy_power_t* power) 806 { 807 uint16_t lane = 0; 808 uint16_t lane_mask = 0; 809 uint16_t if_side = 0; 810 int num_lanes = 0; 811 uint32_t chip_id = 0; 812 uint32_t rev_id = 0; 813 const phymod_access_t *pa = &phy->access; 814 815 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 816 DINO_GET_INTF_SIDE(phy, if_side); 817 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 818 DINO_GET_NUM_LANES(chip_id, num_lanes); 819 820 for (lane = 0; lane < num_lanes; lane ++) { 821 if ((lane_mask & (1 << lane))) { 822 PHYMOD_IF_ERR_RETURN ( 823 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 824 PHYMOD_IF_ERR_RETURN( 825 _dino_phy_power_set(phy, if_side, lane, power)); 826 } 827 } 828 PHYMOD_IF_ERR_RETURN ( 829 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 830 831 return PHYMOD_E_NONE; 832 } 833 834 int dino_phy_power_get(const phymod_phy_access_t* phy, phymod_phy_power_t* power) 835 { 836 uint16_t lane = 0; 837 uint16_t lane_mask = 0; 838 uint16_t if_side = 0; 839 int num_lanes = 0; 840 uint32_t chip_id = 0; 841 uint32_t rev_id = 0; 842 const phymod_access_t *pa = &phy->access; 843 844 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 845 DINO_GET_INTF_SIDE(phy, if_side); 846 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 847 DINO_GET_NUM_LANES(chip_id, num_lanes); 848 849 for (lane = 0; lane < num_lanes; lane ++) { 850 if ((lane_mask & (1 << lane))) { 851 PHYMOD_IF_ERR_RETURN ( 852 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 853 PHYMOD_IF_ERR_RETURN( 854 _dino_phy_power_get(phy, if_side, lane, power)); 855 break; 856 } 857 } 858 PHYMOD_IF_ERR_RETURN ( 859 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 860 861 return PHYMOD_E_NONE; 862 } 863 864 int dino_phy_autoneg_ability_set(const phymod_phy_access_t* phy, const phymod_autoneg_ability_t* an_ability) 865 { 866 dino_an_ability_t dino_an_ability; 867 868 PHYMOD_MEMSET(&dino_an_ability, 0, sizeof(dino_an_ability)); 869 dino_an_ability.cl73_adv.an_fec = an_ability->an_fec; 870 dino_an_ability.cl73_adv.an_cl72 = an_ability->an_cl72; 871 dino_an_ability.an_master_lane = an_ability->an_master_lane; 872 873 874 /*check if sgmii or not */ 875 if (PHYMOD_AN_CAP_SGMII_GET(an_ability)){ 876 return PHYMOD_E_NONE; 877 } 878 879 /*next check pause */ 880 if (PHYMOD_AN_CAP_SYMM_PAUSE_GET(an_ability)) { 881 dino_an_ability.cl73_adv.an_pause = DINO_SYMM_PAUSE; 882 } else if (PHYMOD_AN_CAP_ASYM_PAUSE_GET(an_ability)) { 883 dino_an_ability.cl73_adv.an_pause = DINO_ASYM_PAUSE; 884 } else { 885 dino_an_ability.cl73_adv.an_pause = DINO_NO_PAUSE; 886 } 887 888 /*check cl73 and cl73 bam ability */ 889 if (PHYMOD_AN_CAP_100G_CR4_GET(an_ability->an_cap)) { 890 dino_an_ability.cl73_adv.an_base_speed = DINO_CL73_100GBASE_CR4; 891 } else if (PHYMOD_AN_CAP_100G_KR4_GET(an_ability->an_cap)) { 892 dino_an_ability.cl73_adv.an_base_speed = DINO_CL73_100GBASE_KR4; 893 } else if (PHYMOD_AN_CAP_100G_CR10_GET(an_ability->an_cap)) { 894 dino_an_ability.cl73_adv.an_base_speed = DINO_CL73_100GBASE_CR10; 895 } else if (PHYMOD_AN_CAP_40G_KR4_GET(an_ability->an_cap)) { 896 dino_an_ability.cl73_adv.an_base_speed = DINO_CL73_40GBASE_KR4; 897 } else if (PHYMOD_AN_CAP_40G_CR4_GET(an_ability->an_cap)) { 898 dino_an_ability.cl73_adv.an_base_speed = DINO_CL73_40GBASE_CR4; 899 } else if (PHYMOD_AN_CAP_10G_KR_GET(an_ability->an_cap)) { 900 901 } else if (PHYMOD_AN_CAP_1G_KX_GET(an_ability->an_cap)) { 902 903 } else if (an_ability->an_cap == 0) { 904 return PHYMOD_E_NONE; 905 } else { 906 return PHYMOD_E_PARAM; 907 } 908 909 PHYMOD_IF_ERR_RETURN 910 (_dino_phy_autoneg_ability_set(phy, &dino_an_ability)); 911 912 return PHYMOD_E_NONE; 913 } 914 915 int dino_phy_autoneg_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get_type) 916 { 917 dino_an_ability_t dino_an_ability; 918 919 PHYMOD_IF_ERR_RETURN( 920 _dino_phy_autoneg_ability_get(phy, &dino_an_ability)); 921 922 an_ability_get_type->an_fec = dino_an_ability.cl73_adv.an_fec; 923 an_ability_get_type->an_cl72 = dino_an_ability.cl73_adv.an_cl72; 924 an_ability_get_type->an_master_lane = dino_an_ability.an_master_lane; 925 switch (dino_an_ability.cl73_adv.an_pause) { 926 case DINO_ASYM_PAUSE: 927 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get_type); 928 break; 929 case DINO_SYMM_PAUSE: 930 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get_type); 931 break; 932 default: 933 break; 934 } 935 936 /*first check cl73 ability*/ 937 switch (dino_an_ability.cl73_adv.an_base_speed) { 938 case DINO_CL73_40GBASE_CR4: 939 PHYMOD_AN_CAP_40G_CR4_SET(an_ability_get_type->an_cap); 940 break; 941 case DINO_CL73_40GBASE_KR4: 942 PHYMOD_AN_CAP_40G_KR4_SET(an_ability_get_type->an_cap); 943 break; 944 case DINO_CL73_100GBASE_CR4: 945 PHYMOD_AN_CAP_100G_CR4_SET(an_ability_get_type->an_cap); 946 break; 947 case DINO_CL73_100GBASE_CR10: 948 PHYMOD_AN_CAP_100G_CR10_SET(an_ability_get_type->an_cap); 949 break; 950 case DINO_CL73_100GBASE_KR4: 951 PHYMOD_AN_CAP_100G_KR4_SET(an_ability_get_type->an_cap); 952 break; 953 default: 954 break; 955 } 956 return PHYMOD_E_NONE; 957 } 958 959 int dino_phy_autoneg_remote_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_ability_t* an_ability_get) 960 { 961 return _dino_phy_autoneg_remote_ability_get(phy, an_ability_get); 962 } 963 964 int dino_phy_media_type_tx_get(const phymod_phy_access_t* phy, phymod_media_typed_t media, phymod_tx_t* tx) 965 { 966 967 PHYMOD_MEMSET(tx, 0, sizeof(phymod_tx_t)); 968 969 tx->pre = 0x0; 970 tx->post = 0x0; 971 tx->main = 0x3c; 972 tx->post2 = 0x0; 973 tx->amp = 0xc; 974 975 return PHYMOD_E_NONE; 976 } 977 int dino_phy_reset_set(const phymod_phy_access_t* phy, const phymod_phy_reset_t* reset) 978 { 979 uint16_t lane = 0; 980 uint16_t lane_mask = 0; 981 uint16_t if_side = 0; 982 int num_lanes = 0; 983 uint32_t chip_id = 0; 984 uint32_t rev_id = 0; 985 const phymod_access_t *pa = &phy->access; 986 987 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 988 DINO_GET_INTF_SIDE(phy, if_side); 989 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 990 DINO_GET_NUM_LANES(chip_id, num_lanes); 991 992 for (lane = 0; lane < num_lanes; lane ++) { 993 if ((lane_mask & (1 << lane))) { 994 PHYMOD_IF_ERR_RETURN ( 995 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 996 PHYMOD_IF_ERR_RETURN( 997 _dino_phy_reset_set(pa, if_side, lane, reset)); 998 } 999 } 1000 PHYMOD_IF_ERR_RETURN ( 1001 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1002 1003 return PHYMOD_E_NONE; 1004 } 1005 int dino_phy_reset_get(const phymod_phy_access_t* phy, phymod_phy_reset_t* reset) 1006 { 1007 uint16_t lane = 0; 1008 uint16_t lane_mask = 0; 1009 uint16_t if_side = 0; 1010 int num_lanes = 0; 1011 uint32_t chip_id = 0; 1012 uint32_t rev_id = 0; 1013 const phymod_access_t *pa = &phy->access; 1014 1015 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1016 DINO_GET_INTF_SIDE(phy, if_side); 1017 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1018 DINO_GET_NUM_LANES(chip_id, num_lanes); 1019 1020 for (lane = 0; lane < num_lanes; lane ++) { 1021 if ((lane_mask & (1 << lane))) { 1022 PHYMOD_IF_ERR_RETURN ( 1023 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1024 PHYMOD_IF_ERR_RETURN( 1025 _dino_phy_reset_get(pa, if_side, lane, reset)); 1026 break; 1027 } 1028 } 1029 PHYMOD_IF_ERR_RETURN ( 1030 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1031 1032 return PHYMOD_E_NONE; 1033 } 1034 1035 int dino_phy_rx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t rx_control) 1036 { 1037 uint16_t lane = 0; 1038 uint16_t lane_mask = 0; 1039 uint16_t if_side = 0; 1040 int num_lanes = 0; 1041 uint32_t chip_id = 0; 1042 uint32_t rev_id = 0; 1043 const phymod_access_t *pa = &phy->access; 1044 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1045 DINO_GET_INTF_SIDE(phy, if_side); 1046 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1047 DINO_GET_NUM_LANES(chip_id, num_lanes); 1048 1049 for (lane = 0; lane < num_lanes; lane ++) { 1050 if ((lane_mask & (1 << lane))) { 1051 PHYMOD_IF_ERR_RETURN ( 1052 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1053 PHYMOD_IF_ERR_RETURN( 1054 _dino_phy_rx_lane_control_set(pa, if_side, lane, rx_control)); 1055 } 1056 } 1057 PHYMOD_IF_ERR_RETURN ( 1058 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1059 1060 return PHYMOD_E_NONE; 1061 } 1062 1063 int dino_phy_tx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t tx_control) 1064 { 1065 uint16_t lane = 0; 1066 uint16_t lane_mask = 0; 1067 uint16_t if_side = 0; 1068 int num_lanes = 0; 1069 uint32_t chip_id = 0; 1070 uint32_t rev_id = 0; 1071 const phymod_access_t *pa = &phy->access; 1072 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1073 DINO_GET_INTF_SIDE(phy, if_side); 1074 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1075 DINO_GET_NUM_LANES(chip_id, num_lanes); 1076 1077 for (lane = 0; lane < num_lanes; lane ++) { 1078 if ((lane_mask & (1 << lane))) { 1079 PHYMOD_IF_ERR_RETURN ( 1080 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1081 PHYMOD_IF_ERR_RETURN( 1082 _dino_phy_tx_lane_control_set(pa, if_side, lane, tx_control)); 1083 } 1084 } 1085 PHYMOD_IF_ERR_RETURN ( 1086 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1087 1088 return PHYMOD_E_NONE; 1089 } 1090 int dino_phy_tx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t* tx_control) 1091 { 1092 uint16_t lane = 0; 1093 uint16_t lane_mask = 0; 1094 uint16_t if_side = 0; 1095 int num_lanes = 0; 1096 uint32_t chip_id = 0; 1097 uint32_t rev_id = 0; 1098 const phymod_access_t *pa = &phy->access; 1099 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1100 DINO_GET_INTF_SIDE(phy, if_side); 1101 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1102 DINO_GET_NUM_LANES(chip_id, num_lanes); 1103 1104 for (lane = 0; lane < num_lanes; lane ++) { 1105 if ((lane_mask & (1 << lane))) { 1106 PHYMOD_IF_ERR_RETURN ( 1107 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1108 PHYMOD_IF_ERR_RETURN( 1109 _dino_phy_tx_lane_control_get(pa, if_side, lane, tx_control)); 1110 break; 1111 } 1112 } 1113 PHYMOD_IF_ERR_RETURN ( 1114 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1115 return PHYMOD_E_NONE; 1116 } 1117 1118 int dino_phy_polarity_set(const phymod_phy_access_t* phy, const phymod_polarity_t* polarity) 1119 { 1120 uint16_t lane = 0; 1121 uint16_t lane_mask = 0; 1122 int num_lanes = 0; 1123 uint32_t chip_id = 0; 1124 uint32_t rev_id = 0; 1125 uint16_t if_side = 0, tx_polarity = 0,rx_polarity = 0; 1126 const phymod_access_t *pa = &phy->access; 1127 1128 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1129 DINO_GET_INTF_SIDE(phy, if_side); 1130 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1131 DINO_GET_NUM_LANES(chip_id, num_lanes); 1132 1133 for (lane = 0; lane < num_lanes; lane ++) { 1134 if ((lane_mask & (1 << lane))) { 1135 PHYMOD_IF_ERR_RETURN ( 1136 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1137 if (polarity->tx_polarity != 0xFFFF) { 1138 tx_polarity = (polarity->tx_polarity & (1 << lane)) >> lane; 1139 } else { 1140 tx_polarity = 0xffff; 1141 } 1142 if (polarity->rx_polarity != 0xFFFF) { 1143 rx_polarity = (polarity->rx_polarity & (1 << lane)) >> lane; 1144 } else { 1145 rx_polarity = 0xffff; 1146 } 1147 PHYMOD_IF_ERR_RETURN( 1148 _dino_phy_polarity_set(pa, if_side, lane, tx_polarity, rx_polarity)); 1149 } 1150 } 1151 1152 PHYMOD_IF_ERR_RETURN ( 1153 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1154 1155 return PHYMOD_E_NONE; 1156 } 1157 int dino_phy_polarity_get(const phymod_phy_access_t* phy, phymod_polarity_t* polarity) 1158 { 1159 uint16_t lane = 0; 1160 uint16_t lane_mask = 0; 1161 int num_lanes = 0; 1162 uint32_t chip_id = 0; 1163 uint32_t rev_id = 0; 1164 uint16_t if_side = 0, tx_polarity = 0,rx_polarity = 0; 1165 const phymod_access_t *pa = &phy->access; 1166 1167 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1168 DINO_GET_INTF_SIDE(phy, if_side); 1169 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1170 DINO_GET_NUM_LANES(chip_id, num_lanes); 1171 polarity->tx_polarity = 0; 1172 polarity->rx_polarity = 0; 1173 1174 for (lane = 0; lane < num_lanes; lane ++) { 1175 if ((lane_mask & (1 << lane))) { 1176 PHYMOD_IF_ERR_RETURN ( 1177 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1178 PHYMOD_IF_ERR_RETURN( 1179 _dino_phy_polarity_get(pa, if_side, lane, &tx_polarity, &rx_polarity)); 1180 polarity->tx_polarity |= (tx_polarity << lane); 1181 polarity->rx_polarity |= (rx_polarity << lane); 1182 } 1183 } 1184 1185 PHYMOD_IF_ERR_RETURN ( 1186 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1187 1188 return PHYMOD_E_NONE; 1189 } 1190 int dino_phy_fec_enable_set(const phymod_phy_access_t* phy, uint32_t enable) 1191 { 1192 return _dino_phy_fec_set(phy, enable); 1193 } 1194 1195 int dino_phy_fec_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 1196 { 1197 return _dino_phy_fec_get(phy, enable); 1198 } 1199 1200 /* 1201 * @param flags Reserved for Furtuer use 1202 * @param operation Operation to perform on PLL sequencer 1203 * 1204 * @return PHYMOD_E_NONE successful function execution 1205 */ 1206 int dino_core_pll_sequencer_restart(const phymod_core_access_t* core, uint32_t flags, phymod_sequencer_operation_t operation) 1207 { 1208 uint16_t if_side = 0; 1209 const phymod_access_t *pa = &core->access; 1210 DINO_GET_INTF_SIDE(core, if_side); 1211 1212 PHYMOD_IF_ERR_RETURN( 1213 _dino_core_pll_sequencer_restart(pa, if_side, operation)); 1214 1215 return PHYMOD_E_NONE; 1216 } 1217 1218 int dino_phy_rx_restart(const phymod_phy_access_t* phy) 1219 { 1220 uint16_t if_side = 0; 1221 const phymod_access_t *pa = &phy->access; 1222 DINO_GET_INTF_SIDE(phy, if_side); 1223 1224 PHYMOD_IF_ERR_RETURN( 1225 _dino_core_pll_sequencer_restart(pa, if_side, phymodSeqOpRestart)); 1226 1227 return PHYMOD_E_NONE; 1228 } 1229 1230 int dino_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en) 1231 { 1232 return _dino_phy_cl72_set(phy, cl72_en); 1233 } 1234 1235 int dino_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en) 1236 { 1237 return _dino_phy_cl72_get(phy, cl72_en); 1238 } 1239 1240 int dino_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status) 1241 { 1242 uint16_t lane = 0; 1243 uint16_t lane_mask = 0; 1244 uint16_t if_side = 0; 1245 int num_lanes = 0; 1246 uint32_t chip_id = 0; 1247 uint32_t rev_id = 0; 1248 const phymod_access_t *pa = &phy->access; 1249 status->enabled = 1; 1250 status->locked = 1; 1251 1252 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1253 DINO_GET_INTF_SIDE(phy, if_side); 1254 PHYMOD_IF_ERR_RETURN (dino_get_chipid(&phy->access, &chip_id, &rev_id)); 1255 DINO_GET_NUM_LANES(chip_id, num_lanes); 1256 1257 for (lane = 0; lane < num_lanes; lane ++) { 1258 if (lane_mask & (1 << lane)) { 1259 PHYMOD_IF_ERR_RETURN ( 1260 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1261 PHYMOD_IF_ERR_RETURN( 1262 _dino_phy_cl72_status_get(phy, if_side, lane, status)); 1263 } 1264 } 1265 PHYMOD_IF_ERR_RETURN ( 1266 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1267 1268 return PHYMOD_E_NONE; 1269 } 1270 1271 int dino_phy_firmware_core_config_set(const phymod_phy_access_t* phy, phymod_firmware_core_config_t fw_config) 1272 { 1273 /* Place your code here */ 1274 1275 return PHYMOD_E_UNAVAIL; 1276 } 1277 1278 1279 int dino_phy_firmware_core_config_get(const phymod_phy_access_t* phy, phymod_firmware_core_config_t* fw_config) 1280 { 1281 /* Place your code here */ 1282 1283 return PHYMOD_E_UNAVAIL; 1284 } 1285 1286 1287 int dino_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 1288 { 1289 return _dino_phy_firmware_lane_config_set(phy, fw_config); 1290 } 1291 1292 1293 int dino_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_config) 1294 { 1295 return _dino_phy_firmware_lane_config_get(phy, fw_config); 1296 } 1297 int dino_phy_intr_enable_set(const phymod_phy_access_t* phy, uint32_t enable) 1298 { 1299 uint32_t intr_index = 0; 1300 #ifdef SA_PLP_SUPPORT 1301 uint32_t ena_dis = 0; 1302 ena_dis = (enable >> 31) & 0x1; 1303 #endif 1304 1305 #ifdef SA_PLP_SUPPORT 1306 for (intr_index = 0; intr_index < DINO_MAX_INTR_SUPPORT; intr_index ++) { 1307 if (ena_dis) { 1308 if (enable & (0x1 << intr_index)) { 1309 PHYMOD_IF_ERR_RETURN ( 1310 _dino_phy_intr_enable_set (phy, (0x1 << intr_index), 1)); 1311 } 1312 } else { 1313 if (enable & (0x1 << intr_index)) { 1314 PHYMOD_IF_ERR_RETURN ( 1315 _dino_phy_intr_enable_set (phy, (0x1 << intr_index), 0)); 1316 } 1317 } 1318 } 1319 #else 1320 for (intr_index = 0; intr_index < DINO_MAX_INTR_SUPPORT; intr_index ++) { 1321 if (enable & (0x1 << intr_index)) { 1322 PHYMOD_IF_ERR_RETURN ( 1323 _dino_phy_intr_enable_set (phy, (0x1 << intr_index), 1)); 1324 } else { 1325 PHYMOD_IF_ERR_RETURN ( 1326 _dino_phy_intr_enable_set (phy, (0x1 << intr_index), 0)); 1327 } 1328 } 1329 #endif 1330 1331 return PHYMOD_E_NONE; 1332 } 1333 1334 int dino_phy_intr_enable_get(const phymod_phy_access_t* phy, uint32_t* enable) 1335 { 1336 uint32_t intr_index = 0; 1337 uint32_t value = 0; 1338 1339 for (intr_index = 0; intr_index < DINO_MAX_INTR_SUPPORT; intr_index ++) { 1340 PHYMOD_IF_ERR_RETURN ( 1341 _dino_phy_intr_enable_get (phy, (0x1 << intr_index), &value)); 1342 if (value) { 1343 *enable |= (0x1 << intr_index); 1344 } 1345 } 1346 1347 return PHYMOD_E_NONE; 1348 } 1349 1350 int dino_phy_intr_status_get(const phymod_phy_access_t* phy, uint32_t* intr_status) 1351 { 1352 PHYMOD_IF_ERR_RETURN ( 1353 _dino_phy_intr_status_get (phy, intr_status)); 1354 1355 return PHYMOD_E_NONE; 1356 } 1357 1358 int dino_phy_intr_status_clear(const phymod_phy_access_t* phy, uint32_t intr_clr) 1359 { 1360 uint32_t intr_index = 0; 1361 1362 for (intr_index = 0; intr_index < DINO_MAX_INTR_SUPPORT; intr_index ++) { 1363 if (intr_clr & (0x1 << intr_index)) { 1364 PHYMOD_IF_ERR_RETURN ( 1365 _dino_phy_intr_status_clear (phy, (0x1 << intr_index))); 1366 } 1367 } 1368 1369 return PHYMOD_E_NONE; 1370 } 1371 1372 int dino_phy_i2c_read(const phymod_phy_access_t* phy, uint32_t flags, uint32_t addr, uint32_t offset, uint32_t size, uint8_t* data) 1373 { 1374 return _dino_phy_i2c_read(&phy->access, addr, offset, size, data); 1375 } 1376 1377 int dino_phy_i2c_write(const phymod_phy_access_t* phy, uint32_t flags, uint32_t addr, uint32_t offset, uint32_t size, const uint8_t* data) 1378 { 1379 return _dino_phy_i2c_write(&phy->access, addr, offset, size, data); 1380 } 1381 /*! \brief Config set for GPIO pins 1382 * This set of APIs are used to configure the GPIO pins and 1383 * drive the values (set) and obtain the set values (get) 1384 * These generic APIs are provided to the user to configure GPIOs based on need 1385 * User needs to provide direction an the pin number for a given pin 1386 * 1387 * @param phy Phymod phy access 1388 * @param gpio_mode It is 1 for output 2 for input 1389 * @param pin_no See below table for supported values` 1390 * 1391 * <table> 1392 * <caption id="multi_row">QSFP module 0 I/O Table</caption> 1393 * <tr><th>Pin number <th>Pin <th>Direction 1394 * </tr> 1395 * <tr> 1396 * <td> 18 </td> 1397 * <td> LPMode </td> 1398 * <td> Output </td> 1399 * </tr> 1400 * <tr> 1401 * <td> 21 </td> 1402 * <td> ModPrSl </td> 1403 * <td> Input </td> 1404 * </tr> 1405 * <tr> 1406 * <td> 1 </td> 1407 * <td> ResetL </td> 1408 * <td> Output </td> 1409 * </tr> 1410 * <tr> 1411 * <td> 0 </td> 1412 * <td> IntL </td> 1413 * <td> Input </td> 1414 * </tr> 1415 * </table> 1416 * 1417 * <table> 1418 * <caption id="multi_row">QSFP module 1 I/O Table</caption> 1419 * <tr><th>Pin number <th>Pin <th>Direction 1420 * </tr> 1421 * <tr> 1422 * <td> 19 </td> 1423 * <td> LPMode </td> 1424 * <td> Output </td> 1425 * </tr> 1426 * <tr> 1427 * <td> 25 </td> 1428 * <td> ModPrSl </td> 1429 * <td> Input </td> 1430 * </tr> 1431 * <tr> 1432 * <td> 9 </td> 1433 * <td> ResetL </td> 1434 * <td> Output </td> 1435 * </tr> 1436 * <tr> 1437 * <td> 8 </td> 1438 * <td> IntL </td> 1439 * <td> Input </td> 1440 * </tr> 1441 * </table> 1442 * 1443 * <table> 1444 * <caption id="multi_row">QSFP module 2 I/O Table</caption> 1445 * <tr><th>Pin number <th>Pin <th>Direction 1446 * </tr> 1447 * <tr> 1448 * <td> 20 </td> 1449 * <td> LPMode </td> 1450 * <td> Output </td> 1451 * </tr> 1452 * <tr> 1453 * <td> 29 </td> 1454 * <td> ModPrSl </td> 1455 * <td> Input </td> 1456 * </tr> 1457 * <tr> 1458 * <td> 17 </td> 1459 * <td> ResetL </td> 1460 * <td> Output </td> 1461 * </tr> 1462 * <tr> 1463 * <td> 16 </td> 1464 * <td> IntL </td> 1465 * <td> Input </td> 1466 * </tr> 1467 * </table> 1468 * 1469 * <table> 1470 * <caption id="multi_row">SFP module 4 I/O Table</caption> 1471 * <tr><th>Pin number <th>Pin <th>Direction 1472 * </tr> 1473 * <tr> 1474 * <td> 30 </td> 1475 * <td> Rx_LOS </td> 1476 * <td> Input </td> 1477 * </tr> 1478 * <tr> 1479 * <td> 22 </td> 1480 * <td> MOD_ABS </td> 1481 * <td> Input </td> 1482 * </tr> 1483 * <tr> 1484 * <td> 2 </td> 1485 * <td> TX_DISABLE </td> 1486 * <td> Output </td> 1487 * </tr> 1488 * <tr> 1489 * <td> 3 </td> 1490 * <td> TX_FAULT </td> 1491 * <td> Input </td> 1492 * </tr> 1493 * </table> 1494 * 1495 * <table> 1496 * <caption id="multi_row">SFP module 5 I/O Table</caption> 1497 * <tr><th>Pin number <th>Pin <th>Direction 1498 * </tr> 1499 * <tr> 1500 * <td> 31 </td> 1501 * <td> Rx_LOS </td> 1502 * <td> Input </td> 1503 * </tr> 1504 * <tr> 1505 * <td> 23 </td> 1506 * <td> MOD_ABS </td> 1507 * <td> Input </td> 1508 * </tr> 1509 * <tr> 1510 * <td> 4 </td> 1511 * <td> TX_DISABLE </td> 1512 * <td> Output </td> 1513 * </tr> 1514 * <tr> 1515 * <td> 5 </td> 1516 * <td> TX_FAULT </td> 1517 * <td> Input </td> 1518 * </tr> 1519 * </table> 1520 * 1521 * <table> 1522 * <caption id="multi_row">SFP module 6 I/O Table</caption> 1523 * <tr><th>Pin number <th>Pin <th>Direction 1524 * </tr> 1525 * <tr> 1526 * <td> 32 </td> 1527 * <td> Rx_LOS </td> 1528 * <td> Input </td> 1529 * </tr> 1530 * <tr> 1531 * <td> 24 </td> 1532 * <td> MOD_ABS </td> 1533 * <td> Input </td> 1534 * </tr> 1535 * <tr> 1536 * <td> 6 </td> 1537 * <td> TX_DISABLE </td> 1538 * <td> Output </td> 1539 * </tr> 1540 * <tr> 1541 * <td> 7 </td> 1542 * <td> TX_FAULT </td> 1543 * <td> Input </td> 1544 * </tr> 1545 * </table> 1546 * 1547 * <table> 1548 * <caption id="multi_row">SFP module 7 I/O Table</caption> 1549 * <tr><th>Pin number <th>Pin <th>Direction 1550 * </tr> 1551 * <tr> 1552 * <td> 33 </td> 1553 * <td> Rx_LOS </td> 1554 * <td> Input </td> 1555 * </tr> 1556 * <tr> 1557 * <td> 25 </td> 1558 * <td> MOD_ABS </td> 1559 * <td> Input </td> 1560 * </tr> 1561 * <tr> 1562 * <td> 8 </td> 1563 * <td> TX_DISABLE </td> 1564 * <td> Output </td> 1565 * </tr> 1566 * <tr> 1567 * <td> 9 </td> 1568 * <td> TX_FAULT </td> 1569 * <td> Input </td> 1570 * </tr> 1571 * </table> 1572 * 1573 * <table> 1574 * <caption id="multi_row">SFP module 8 I/O Table</caption> 1575 * <tr><th>Pin number <th>Pin <th>Direction 1576 * </tr> 1577 * <tr> 1578 * <td> 34 </td> 1579 * <td> Rx_LOS </td> 1580 * <td> Input </td> 1581 * </tr> 1582 * <tr> 1583 * <td> 26 </td> 1584 * <td> MOD_ABS </td> 1585 * <td> Input </td> 1586 * </tr> 1587 * <tr> 1588 * <td> 10 </td> 1589 * <td> TX_DISABLE </td> 1590 * <td> Output </td> 1591 * </tr> 1592 * <tr> 1593 * <td> 11 </td> 1594 * <td> TX_FAULT </td> 1595 * <td> Input </td> 1596 * </tr> 1597 * </table> 1598 * 1599 * <table> 1600 * <caption id="multi_row">SFP module 9 I/O Table</caption> 1601 * <tr><th>Pin number <th>Pin <th>Direction 1602 * </tr> 1603 * <tr> 1604 * <td> 35 </td> 1605 * <td> Rx_LOS </td> 1606 * <td> Input </td> 1607 * </tr> 1608 * <tr> 1609 * <td> 27 </td> 1610 * <td> MOD_ABS </td> 1611 * <td> Input </td> 1612 * </tr> 1613 * <tr> 1614 * <td> 12 </td> 1615 * <td> TX_DISABLE </td> 1616 * <td> Output </td> 1617 * </tr> 1618 * <tr> 1619 * <td> 13 </td> 1620 * <td> TX_FAULT </td> 1621 * <td> Input </td> 1622 * </tr> 1623 * </table> 1624 * 1625 * <table> 1626 * <caption id="multi_row">SFP module 10 I/O Table</caption> 1627 * <tr><th>Pin number <th>Pin <th>Direction 1628 * </tr> 1629 * <tr> 1630 * <td> 36 </td> 1631 * <td> Rx_LOS </td> 1632 * <td> Input </td> 1633 * </tr> 1634 * <tr> 1635 * <td> 28 </td> 1636 * <td> MOD_ABS </td> 1637 * <td> Input </td> 1638 * </tr> 1639 * <tr> 1640 * <td> 14 </td> 1641 * <td> TX_DISABLE </td> 1642 * <td> Output </td> 1643 * </tr> 1644 * <tr> 1645 * <td> 15 </td> 1646 * <td> TX_FAULT </td> 1647 * <td> Input </td> 1648 * </tr> 1649 * </table> 1650 * 1651 * <table> 1652 * <caption id="multi_row">SFP module 11 I/O Table</caption> 1653 * <tr><th>Pin number <th>Pin <th>Direction 1654 * </tr> 1655 * <tr> 1656 * <td> 37 </td> 1657 * <td> Rx_LOS </td> 1658 * <td> Input </td> 1659 * </tr> 1660 * <tr> 1661 * <td> 29 </td> 1662 * <td> MOD_ABS </td> 1663 * <td> Input </td> 1664 * </tr> 1665 * <tr> 1666 * <td> 16 </td> 1667 * <td> TX_DISABLE </td> 1668 * <td> Output </td> 1669 * </tr> 1670 * <tr> 1671 * <td> 17 </td> 1672 * <td> TX_FAULT </td> 1673 * <td> Input </td> 1674 * </tr> 1675 * </table> 1676 * 1677 * 1678 * @return PHYMOD_E_NONE (0) for success and corresponding error code on failure 1679 */ 1680 int dino_phy_gpio_config_set(const phymod_phy_access_t* phy, int pin_no, phymod_gpio_mode_t gpio_mode) 1681 { 1682 return _dino_phy_gpio_config_set(&phy->access, pin_no, gpio_mode); 1683 } 1684 1685 int dino_phy_gpio_config_get(const phymod_phy_access_t* phy, int pin_no, phymod_gpio_mode_t* gpio_mode) 1686 { 1687 return _dino_phy_gpio_config_get(&phy->access, pin_no, gpio_mode); 1688 } 1689 1690 int dino_phy_gpio_pin_value_set(const phymod_phy_access_t* phy, int pin_no, int value) 1691 { 1692 return _dino_phy_gpio_pin_value_set(&phy->access, pin_no, value); 1693 } 1694 1695 int dino_phy_gpio_pin_value_get(const phymod_phy_access_t* phy, int pin_no, int* value) 1696 { 1697 return _dino_phy_gpio_pin_value_get(&phy->access, pin_no, value); 1698 } 1699 1700 int dino_phy_multi_get(const phymod_phy_access_t* phy, phymod_multi_data_t* multi_data) 1701 { 1702 return _dino_phy_multi_get(&phy->access, multi_data); 1703 } 1704 1705 int dino_phy_op_mode_get(const phymod_phy_access_t* phy, phymod_operation_mode_t* op_mode) 1706 { 1707 return PHYMOD_E_UNAVAIL; 1708 }