dino_cfg_seq.h (28097B)
1 /*---------------------------------------------------------------------- 2 * 3 * Broadcom Corporation 4 * Proprietary and Confidential information 5 * All rights reserved 6 * This source file is the property of Broadcom Corporation, and 7 * may not be copied or distributed in any isomorphic form without the 8 * prior written consent of Broadcom Corporation. 9 *--------------------------------------------------------------------- 10 * File : dino_cfg_seq.h 11 * Description: c functions implementing Tier1 12 *---------------------------------------------------------------------*/ 13 /* 14 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 15 * 16 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 17 * 18 */ 19 20 21 #ifndef DINO_CFG_SEQ_H 22 #define DINO_CFG_SEQ_H 23 #include <phymod/phymod_acc.h> 24 #include "dino_serdes/common/srds_api_err_code.h" 25 #include "dino_types.h" 26 27 #define DEV1_SLICE_SLICE_ADR 0x8000 28 #define DINO_DEV_PMA_PMD 1 29 #define DINO_DEV_AN 7 30 #define DINO_FW_DLOAD_RETRY_CNT 1000 31 #define DINO_FW_ENABLE_RETRY_CNT 100 32 #define DINO_ENABLE 1 33 #define DINO_DISABLE 0 34 #define DINO_SPD_100G 100000 35 #define DINO_SPD_106G 106000 36 #define DINO_SPD_111G 111000 37 #define DINO_SPD_1G 1000 38 #define DINO_SPD_10G 10000 39 #define DINO_SPD_11G 11000 40 #define DINO_SPD_11P18G 11800 41 #define DINO_SPD_20G 20000 42 #define DINO_SPD_21G 21000 43 #define DINO_SPD_40G 40000 44 #define DINO_SPD_42G 42000 45 #define DINO_MAX_FALCON_LANE 4 46 #define DINO_MAX_MERLIN_LANE 4 47 #define DINO_MAX_CORE_LANE 4 48 #define DINO_MAX_LANE 12 49 #define DINO_FW_ALREADY_DOWNLOADED 0xFAD 50 #define DINO_PMD_ID0 0xAE02 51 #define DINO_PMD_ID1 0x5390 52 #define DINO_CHIP_ID_82332 0x82332 53 #define DINO_CHIP_ID_82793 0x82793 54 #define DINO_CHIP_ID_82795 0x82795 55 #define DINO_FW_HEADER_SIZE 32 56 #define DINO_40G_PORT0_LANE_MASK 0xf 57 #define DINO_40G_PORT1_LANE_MASK 0xf0 58 #define DINO_40G_PORT2_LANE_MASK 0xf00 59 #define DINO_100G_TYPE1_LANE_MASK 0x3ff 60 #define DINO_100G_TYPE2_LANE_MASK 0x7fe 61 #define DINO_100G_TYPE3_LANE_MASK 0xffc 62 #define DINO_LANE_MASK_ALL_LANES 0xfff 63 #define DINO_GPREG_0_ADR 0x8250 64 #define DINO_GPREG_F_ADR 0x825F 65 #define DINO_100G_CR10_AN_INSTANCE_MASK 0x3 66 #define DINO_100G_CR10_AN_INSTANCE_SHIFT 0 67 #define DINO_100G_SKIP_TX_TRAINING_MASK 0x10 68 #define DINO_40G_PORT0_SKIP_TX_TRAINING_MASK 0x10 69 #define DINO_40G_PORT1_SKIP_TX_TRAINING_MASK 0x20 70 #define DINO_40G_PORT2_SKIP_TX_TRAINING_MASK 0x40 71 #define DINO_100G_SKIP_TX_TRAINING_SHIFT 4 72 #define DINO_40G_PORT0_SKIP_TX_TRAINING_SHIFT 4 73 #define DINO_40G_PORT1_SKIP_TX_TRAINING_SHIFT 5 74 #define DINO_40G_PORT2_SKIP_TX_TRAINING_SHIFT 6 75 #define DINO_SW_GPREG_0_ADR 0x8b90 76 #define DINO_MER_PLL_MAP_VAL_REG_ADR 0x8b9f 77 #define DINO_REF_CLK_REG_ADR 0x8b9e 78 #define DINO_AN_MST_LANE_REG_ADR 0x8b9d 79 #define DINO_AN_MST_LANE_100G_MASK 0xf 80 #define DINO_AN_MST_LANE_100G_SHIFT 0 81 #define DINO_AN_MST_LANE_40G_P0_MASK 0xf0 82 #define DINO_AN_MST_LANE_40G_P0_SHIFT 4 83 #define DINO_AN_MST_LANE_40G_P1_MASK 0xf00 84 #define DINO_AN_MST_LANE_40G_P1_SHIFT 8 85 #define DINO_AN_MST_LANE_40G_P2_MASK 0xf000 86 #define DINO_AN_MST_LANE_40G_P2_SHIFT 12 87 #define DINO_REF_CLK_VAL_MASK 0x1f 88 #define DINO_REF_CLK_VAL_SHIFT 0 89 #define DINO_LINE_INTF_MASK 0x1f 90 #define DINO_LINE_INTF_SHIFT 0 91 #define DINO_SYS_INTF_MASK 0x3e0 92 #define DINO_SYS_INTF_SHIFT 5 93 #define DINO_DEV_OP_MODE_MASK 0xc00 94 #define DINO_DEV_OP_MODE_SHIFT 10 95 #define DINO_DEV_OP_MODE_PT 0 96 #define DINO_DEV_OP_MODE_GBOX 1 97 #define DINO_DEV_OP_MODE_INVALID 0xf 98 #define DINO_PHY_TYPE_MASK 0x3000 99 #define DINO_PHY_TYPE_SHIFT 12 100 #define DINO_PHY_TYPE_ETH 0 101 #define DINO_PHY_TYPE_HIGIG 1 102 #define DINO_PHY_TYPE_OTN 2 103 #define DINO_PHY_TYPE_INVALID 0xf 104 #define DINO_INTF_TYPE_SR 0 105 #define DINO_INTF_TYPE_LR 1 106 #define DINO_INTF_TYPE_ER 2 107 #define DINO_INTF_TYPE_CAUI4 3 108 #define DINO_INTF_TYPE_CAUI 4 109 #define DINO_INTF_TYPE_CAUI4_C2C 5 110 #define DINO_INTF_TYPE_CAUI4_C2M 6 111 #define DINO_INTF_TYPE_XLAUI 7 112 #define DINO_INTF_TYPE_XFI 8 113 #define DINO_INTF_TYPE_KX 9 114 #define DINO_INTF_TYPE_KR 10 115 #define DINO_INTF_TYPE_SFI 11 116 #define DINO_INTF_TYPE_XLPPI 12 117 #define DINO_INTF_TYPE_CX 13 118 #define DINO_INTF_TYPE_CR 14 119 #define DINO_INTF_TYPE_VSR 15 120 #define DINO_INTF_TYPE_OTN 16 121 #define DINO_INTF_TYPE_SGMII 17 122 #define DINO_LINE_DFE_OPTION_MASK 0xc00 123 #define DINO_LINE_DFE_OPTION_SHIFT 10 124 #define DINO_LINE_MEDIA_TYPE_MASK 0x300 125 #define DINO_LINE_MEDIA_TYPE_SHIFT 8 126 #define DINO_LINE_TX_TRAINING_MASK 0x1000 127 #define DINO_LINE_TX_TRAINING_SHIFT 12 128 #define DINO_LINE_TX_TIMING_MODE_MASK 0x6000 129 #define DINO_LINE_TX_TIMING_MODE_SHIFT 13 130 #define DINO_SYS_TX_TIMING_MODE_MASK 0x60 131 #define DINO_SYS_TX_TIMING_MODE_SHIFT 5 132 #define DINO_AN_MASK 0x8000 133 #define DINO_AN_SHIFT 15 134 #define DINO_SYS_DFE_OPTION_MASK 0xc 135 #define DINO_SYS_DFE_OPTION_SHIFT 2 136 #define DINO_SYS_MEDIA_TYPE_MASK 0x3 137 #define DINO_SYS_MEDIA_TYPE_SHIFT 0 138 #define DINO_SYS_TX_TRAINING_MASK 0x10 139 #define DINO_SYS_TX_TRAINING_SHIFT 4 140 #define DINO_FW_SM_ENABLE_MASK (1 << 7) 141 #define DINO_MODULE_CNTRL_RAM_NVR0_ADR 0x8800 142 #define DINO_MAX_INTR_SUPPORT 10 143 #define DINO_FRC_TRAINING_DELAY_MASK 0x3 144 #define DINO_FRC_TRAINING_DELAY_SHIFT 0 145 #define DINO_FRC_TRAINING_DELAY_3SEC 0 146 #define DINO_FRC_TRAINING_DELAY_6SEC 1 147 #define DINO_FRC_TRAINING_DELAY_9SEC 2 148 #define DINO_FRC_TRAINING_DELAY_12SEC 3 149 150 typedef enum { 151 MSGOUT_DONTCARE = 0x0000, 152 MSGOUT_GET_CNT = 0x8888, 153 MSGOUT_GET_LSB = 0xABCD, 154 MSGOUT_GET_MSB = 0x4321, 155 MSGOUT_GET_2B = 0xEEEE, 156 MSGOUT_GET_B = 0xF00D, 157 MSGOUT_ERR = 0x0BAD, 158 MSGOUT_NEXT = 0x2222, 159 MSGOUT_NOT_DWNLD = 0x0101, 160 MSGOUT_DWNLD_ALREADY = 0x0202, 161 MSGOUT_DWNLD_DONE = 0x0303, 162 MSGOUT_PRGRM_DONE = 0x0404, 163 MSGOUT_HDR_ERR = 0x0E0E, 164 MSGOUT_FLASH = 0xF1AC 165 } DINO_MSGOUT_E; 166 167 typedef enum { 168 DINO_SLICE_UNICAST = 0, 169 DINO_SLICE_MULTICAST = 1, 170 DINO_SLICE_BROADCAST = 2, 171 DINO_SLICE_RESET = 3, 172 DINO_CAST_INVALID = 4 173 }DINO_SLICE_OP_TYPE; 174 175 typedef enum { 176 DINO_IF_LINE = 0, 177 DINO_IF_SYS = 1 178 }DINO_IF_SIDE; 179 180 typedef enum { 181 DINO_AN_NONE = 0, 182 DINO_AN_CL73 = 1, 183 DINO_AN_PROP = 2 184 }DINO_AN_MODE; 185 186 typedef enum 187 { 188 SERDES_MEDIA_TYPE_BACK_PLANE = 0, /* KR link: back plane media */ 189 SERDES_MEDIA_TYPE_COPPER_CABLE = 1, /* CR link: direct-attached copper cable */ 190 SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS = 2, /* SR/LR link: optical fiber with reliable LOS detection */ 191 SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS = 3 /* SR/LR link: optical fiber with unreliable LOS detection */ 192 } DINO_MEDIA_TYPE; 193 194 typedef enum 195 { 196 SERDES_DFE_OPTION_NO_DFE = 0, /* no DFE is used */ 197 SERDES_DFE_OPTION_DFE = 1, /* DFE is enabled */ 198 SERDES_DFE_OPTION_BRDFE = 2, /* Force BRDFE mode, DFE will be on, too */ 199 /* only available in Falcon core */ 200 SERDES_DFE_OPTION_DFE_LP_MODE = 3 /* DFE is enabled in low-power mode */ 201 /* only available in Falcon core */ 202 /* DFE_LP_MODE and BRDEF are NOT supported in Merlin core, 203 * so all non-zero values has the same effect as 1 for Merlin core. 204 */ 205 } DINO_DFE_OPTION; 206 207 208 typedef enum { 209 DINO_PLL_MODE_64 = 0x0, /*4'b0000*/ 210 DINO_PLL_MODE_66 = 0x1, /*4'b0001*/ 211 DINO_PLL_MODE_80 = 0x2, /*4'b0010*/ 212 DINO_PLL_MODE_128 = 0x3, /*4'b0011*/ 213 DINO_PLL_MODE_132 = 0x4, /*4'b0100*/ 214 DINO_PLL_MODE_140 = 0x5, /*4'b0101*/ 215 DINO_PLL_MODE_160 = 0x6, /*4'b0110*/ 216 DINO_PLL_MODE_165 = 0x7, /*4'b0111*/ 217 DINO_PLL_MODE_168 = 0x8, /*4'b1000*/ 218 DINO_PLL_MODE_170 = 0x9, /*4'b1001*/ 219 DINO_PLL_MODE_175 = 0xa, /*4'b1010*/ 220 DINO_PLL_MODE_180 = 0xb, /*4'b1011*/ 221 DINO_PLL_MODE_184 = 0xc, /*4'b1100*/ 222 DINO_PLL_MODE_200 = 0xd, /*4'b1101*/ 223 DINO_PLL_MODE_224 = 0xe, /*4'b1110*/ 224 DINO_PLL_MODE_264 = 0xf, /*4'b1111*/ 225 DINO_PLL_MODE_33 = 0x10, 226 DINO_PLL_MODE_32 = 0x11, 227 DINO_PLL_MODE_16 = 0x12, 228 DINO_PLL_MODE_82P5 = 0x13, 229 DINO_PLL_MODE_40 = 0x14, 230 DINO_PLL_MODE_70 = 0x15, 231 DINO_PLL_MODE_INVALID = -1 232 } DINO_PLL_MODE_E; 233 234 typedef enum { 235 DINO_PORT0 = 0, 236 DINO_PORT1 = 1, 237 DINO_PORT2 = 2, 238 DINO_PORT3 = 3, 239 DINO_PORT4 = 4, 240 DINO_PORT5 = 5, 241 DINO_PORT6 = 6, 242 DINO_PORT7 = 7, 243 DINO_PORT8 = 8, 244 DINO_PORT9 = 9, 245 DINO_PORT10 = 10, 246 DINO_PORT11 = 11 247 } DINO_PORT_E; 248 249 #define DINO_IF_ERR_RETURN_FREE(B, A) \ 250 do { \ 251 int loc_err ; \ 252 if ((loc_err = (A)) != PHYMOD_E_NONE) \ 253 { if (B) { PHYMOD_FREE(B) ; } ; return loc_err ; } \ 254 } while (0) 255 256 #define DINO_IF_ERR_RETURN(A) \ 257 do { \ 258 if ((rv = (A)) != PHYMOD_E_NONE) \ 259 { goto ERR; } \ 260 } while (0) 261 262 #define DINO_RETURN_WITH_ERR(A, B) \ 263 do { \ 264 PHYMOD_DEBUG_ERROR(B); \ 265 rv = (A); \ 266 { goto ERR; } \ 267 } while (0) 268 269 270 #define DINO_GET_INTF_SIDE(phy, if_side) (if_side = (phy->port_loc == phymodPortLocSys) ? DINO_IF_SYS : DINO_IF_LINE) 271 272 #define DINO_GET_PORT_FROM_MODE(_C, _CHIP_ID, _PRT) \ 273 do { \ 274 if (_CHIP_ID == DINO_CHIP_ID_82332) { \ 275 if (_C->data_rate == DINO_SPD_100G || _C->data_rate == DINO_SPD_106G || _C->data_rate == DINO_SPD_111G) { \ 276 _PRT = 1; \ 277 } else if ((_C->data_rate == DINO_SPD_40G || _C->data_rate == DINO_SPD_42G)) { \ 278 _PRT = 3; \ 279 } else if (_C->data_rate == DINO_SPD_10G || _C->data_rate == DINO_SPD_11G || _C->data_rate == DINO_SPD_11P18G || _C->data_rate == DINO_SPD_1G) { \ 280 _PRT = 12; \ 281 } \ 282 } else if (_CHIP_ID == DINO_CHIP_ID_82793) { \ 283 if (_C->data_rate == DINO_SPD_100G || _C->data_rate == DINO_SPD_106G || _C->data_rate == DINO_SPD_111G) { \ 284 _PRT = 1; \ 285 } else if ((_C->data_rate == DINO_SPD_40G || _C->data_rate == DINO_SPD_42G)) { \ 286 _PRT = 2; \ 287 } else if (_C->data_rate == DINO_SPD_10G || _C->data_rate == DINO_SPD_11G || _C->data_rate == DINO_SPD_11P18G || _C->data_rate == DINO_SPD_1G) { \ 288 _PRT = 10; \ 289 } \ 290 } else { \ 291 if (_C->data_rate == DINO_SPD_100G || _C->data_rate == DINO_SPD_106G || _C->data_rate == DINO_SPD_111G) { \ 292 _PRT = 1; \ 293 } else if ((_C->data_rate == DINO_SPD_40G || _C->data_rate == DINO_SPD_42G)) { \ 294 _PRT = 1; \ 295 } else if (_C->data_rate == DINO_SPD_10G || _C->data_rate == DINO_SPD_11G || _C->data_rate == DINO_SPD_11P18G || _C->data_rate == DINO_SPD_1G) { \ 296 _PRT = 4; \ 297 } \ 298 } \ 299 }while(0); 300 301 302 #define DINO_IS_FALCON_SIDE(_IF, _LANE) ((_IF == DINO_IF_LINE) && (_LANE < DINO_MAX_FALCON_LANE)) 303 304 #define DINO_IS_BCAST_SET(_IF, _LM) \ 305 (((_IF == DINO_IF_SYS) && \ 306 ((_LM == 0xf) || (_LM == 0xf0) || (_LM == 0xf00) || (_LM == 0x3ff) || (_LM == 0x7fe) || (_LM == 0xffc))) || \ 307 ((_IF == DINO_IF_LINE) && ((_LM == 0xf) || (_LM == 0xf0) || (_LM == 0xf00)))) 308 309 #define READ_DINO_PMA_PMD_REG(acc, addr, value) \ 310 do { \ 311 uint32_t read_tmp; \ 312 PHYMOD_IF_ERR_RETURN \ 313 (PHYMOD_BUS_READ(acc, ((DINO_DEV_PMA_PMD << 16) | addr), &read_tmp)); \ 314 value = (read_tmp & 0xffff); \ 315 } while (0); 316 317 #define WRITE_DINO_PMA_PMD_REG(acc, addr, value) \ 318 PHYMOD_IF_ERR_RETURN \ 319 (PHYMOD_BUS_WRITE(acc, (DINO_DEV_PMA_PMD << 16) | addr, value)); 320 321 #define READ_DINO_AN_REG(acc, addr, value) \ 322 do { \ 323 uint32_t an_read_tmp; \ 324 PHYMOD_IF_ERR_RETURN \ 325 (PHYMOD_BUS_READ(acc, ((DINO_DEV_AN << 16) | addr), &an_read_tmp)); \ 326 value = (an_read_tmp & 0xffff); \ 327 } while (0); 328 329 #define WRITE_DINO_AN_REG(acc, addr, value) \ 330 PHYMOD_IF_ERR_RETURN \ 331 (PHYMOD_BUS_WRITE(acc, (DINO_DEV_AN << 16) | addr, value)); 332 333 #define DINO_GET_NUM_LANES(cid, nl) \ 334 do { \ 335 if (cid == DINO_CHIP_ID_82332) { \ 336 nl = 12; \ 337 } else { \ 338 nl = 10; \ 339 } \ 340 } while (0); 341 typedef enum { 342 DINO_CL73_NO_TECH = 0, 343 DINO_CL73_1000BASE_KX = 0x1, 344 DINO_CL73_10GBASE_KX4 = 0x2, 345 DINO_CL73_10GBASE_KR = 0x4, 346 DINO_CL73_40GBASE_KR4 = 0x8, 347 DINO_CL73_40GBASE_CR4 = 0x10, 348 DINO_CL73_100GBASE_CR10 = 0x20, 349 DINO_CL73_100GBASE_KP4 = 0x40, 350 DINO_CL73_100GBASE_KR4 = 0x80, 351 DINO_CL73_100GBASE_CR4 = 0x100 352 } DINO_CL73_SPEED_T; 353 354 typedef enum { 355 DINO_NO_PAUSE = 0, 356 DINO_ASYM_PAUSE, 357 DINO_SYMM_PAUSE, 358 DINO_ASYM_SYMM_PAUSE, 359 DINO_AN_PAUSE_COUNT 360 } DINO_AN_PAUSE_T; 361 362 typedef struct DINO_AN_ADV_ABILITY_S{ 363 DINO_CL73_SPEED_T an_base_speed; 364 DINO_AN_PAUSE_T an_pause; 365 uint16_t an_fec; 366 uint16_t an_cl72; 367 } dino_an_adv_ability_t; 368 369 typedef struct dino_an_ability_s { 370 dino_an_adv_ability_t cl73_adv; /*includes cl73 related */ 371 uint32_t an_master_lane; /* Master lane belongs to port. For 10 lane port[0-9], for 4 lane port [0-3], for 2 lane port [0-1]*/ 372 } dino_an_ability_t; 373 374 int dino_get_chipid(const phymod_access_t *pa, uint32_t *chipid, uint32_t *rev); 375 376 int _dino_wait_mst_msgout(const phymod_access_t *pa, DINO_MSGOUT_E exp_message, int poll_time); 377 378 int _dino_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config); 379 380 int _dino_set_slice_reg(const phymod_access_t* pa, DINO_SLICE_OP_TYPE slice_op_type, uint16_t if_side, uint16_t lane); 381 382 int _dino_rx_pmd_lock_get(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, uint32_t* rx_pmd_locked); 383 384 int _dino_get_rx_pmd_lock_status(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, uint32_t *link_sts); 385 386 int _dino_config_dut_mode_reg(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config); 387 388 int _dino_udms_config(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config, DINO_AN_MODE mode); 389 390 int _dino_phy_interface_config_set(const phymod_phy_access_t *phy, uint32_t flags, const phymod_phy_inf_config_t* config); 391 392 int dino_is_lane_mask_set(const phymod_phy_access_t *phy, uint16_t prt, const phymod_phy_inf_config_t *config); 393 394 int _dino_config_dut_mode_reg(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config); 395 396 int _dino_udms_config(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config, DINO_AN_MODE mode); 397 398 int _dino_interface_set(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config); 399 400 int _dino_phy_interface_config_set(const phymod_phy_access_t* pa, uint32_t flags, const phymod_phy_inf_config_t* config); 401 402 int _dino_phy_interface_config_get(phymod_phy_access_t *phy, uint32_t flags, phymod_phy_inf_config_t *config); 403 404 int _dino_configure_ref_clock(const phymod_access_t *pa, phymod_ref_clk_t ref_clk); 405 406 int _dino_get_pll_modes(const phymod_phy_access_t *phy, phymod_ref_clk_t ref_clk, const phymod_phy_inf_config_t *config, uint16_t *fal_pll_mode, uint16_t *mer_pll_mode); 407 408 int _dino_map_mer_pll_div(DINO_PLL_MODE_E pll_mode); 409 410 int _dino_config_pll_div(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t *config); 411 412 int _dino_core_reset_set(const phymod_access_t *pa, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction); 413 414 int _dino_fw_enable(const phymod_access_t *pa); 415 416 int _dino_save_interface(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t *config, phymod_interface_t intf); 417 418 int _dino_restore_interface(phymod_phy_access_t *phy, phymod_phy_inf_config_t *config, phymod_interface_t *intf); 419 420 int _dino_loopback_set(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, phymod_loopback_mode_t loopback, uint32_t enable); 421 422 int _dino_falcon_lpbk_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_loopback_mode_t loopback, uint32_t enable); 423 424 int _dino_merlin_lpbk_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_loopback_mode_t loopback, uint32_t enable); 425 426 int _dino_falcon_lpbk_get(const phymod_access_t *pa, uint16_t if_side, phymod_loopback_mode_t loopback, uint32_t* enable); 427 428 int _dino_merlin_lpbk_get(const phymod_access_t *pa, uint16_t if_side, phymod_loopback_mode_t loopback, uint32_t* enable); 429 430 int _dino_loopback_get(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, phymod_loopback_mode_t loopback, uint32_t *enable); 431 432 int _dino_phy_status_dump(const phymod_access_t *pa, uint16_t if_side, uint16_t lane); 433 434 int _dino_port_from_lane_map_get(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* cfg, uint16_t *port); 435 436 err_code_t _dino_merlin_read_pll_range(const phymod_access_t *pa, uint32_t *pll_range); 437 438 err_code_t _dino_falcon_read_pll_range(const phymod_access_t *pa, uint32_t *pll_range); 439 440 int _dino_restore_phy_type(const phymod_access_t *pa, phymod_phy_inf_config_t* config, uint16_t *phy_type); 441 442 int _dino_save_phy_type(const phymod_access_t *pa, const phymod_phy_inf_config_t *config); 443 444 int _dino_fifo_reset(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t *config); 445 446 int _dino_phy_polarity_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, uint16_t tx_polarity, uint16_t rx_polarity); 447 448 int _dino_phy_polarity_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, uint16_t *tx_polarity, uint16_t *rx_polarity); 449 450 int _dino_phy_fec_set(const phymod_phy_access_t* phy, uint16_t enable); 451 452 int _dino_phy_fec_get(const phymod_phy_access_t* phy, uint32_t *enable); 453 454 int _dino_phy_power_set(const phymod_phy_access_t* phy, uint16_t if_side, uint16_t lane, const phymod_phy_power_t* power); 455 456 int _dino_phy_power_get(const phymod_phy_access_t* phy, uint16_t if_side, uint16_t lane, phymod_phy_power_t* power); 457 458 int _dino_phy_reset_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, const phymod_phy_reset_t* reset); 459 460 int _dino_phy_reset_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_phy_reset_t* reset); 461 462 int _dino_core_pll_sequencer_restart(const phymod_access_t* pa, uint16_t if_side, phymod_sequencer_operation_t operation); 463 464 465 /*TX transmission control*/ 466 int _dino_phy_tx_lane_control_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_phy_tx_lane_control_t tx_control); 467 int _dino_phy_tx_lane_control_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_phy_tx_lane_control_t* tx_control); 468 469 /*Rx control*/ 470 int _dino_phy_rx_lane_control_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_phy_rx_lane_control_t rx_control); 471 472 int _dino_phy_rx_lane_control_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_phy_rx_lane_control_t* rx_control); 473 474 /*Set\Get TX Parameters*/ 475 int _dino_phy_tx_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, const phymod_tx_t* tx); 476 int _dino_phy_tx_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_tx_t* tx); 477 478 /*Set\Get RX Parameters*/ 479 int _dino_phy_rx_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, const phymod_rx_t* rx); 480 int _dino_phy_rx_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_rx_t* rx); 481 482 /*PHY Rx adaptation resume*/ 483 int _dino_phy_rx_adaptation_resume(const phymod_access_t* pa, uint16_t if_side, uint16_t lane); 484 485 486 int _dino_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en); 487 488 int _dino_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en); 489 490 int _dino_phy_cl72_status_get(const phymod_phy_access_t* phy, uint16_t if_side, uint16_t lane, phymod_cl72_status_t* status); 491 492 int _dino_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config); 493 494 int _dino_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_config); 495 496 int _dino_phy_autoneg_ability_set(const phymod_phy_access_t *phy, dino_an_ability_t *an_ability); 497 498 int _dino_phy_autoneg_set(const phymod_phy_access_t *phy, const phymod_autoneg_control_t* an); 499 500 int _dino_phy_autoneg_get(const phymod_phy_access_t *phy, phymod_autoneg_control_t* an, uint32_t *an_done); 501 502 int _dino_phy_autoneg_ability_get(const phymod_phy_access_t *phy, dino_an_ability_t *an_ablity); 503 504 int _dino_phy_autoneg_remote_ability_get(const phymod_phy_access_t *phy, phymod_autoneg_ability_t* an_ability_get); 505 506 int _dino_phy_intr_enable_set(const phymod_phy_access_t* phy, uint32_t intr_type, uint32_t enable); 507 508 int _dino_phy_intr_enable_get(const phymod_phy_access_t* phy, uint32_t intr_type, uint32_t* enable); 509 510 int _dino_phy_intr_status_get(const phymod_phy_access_t* phy, uint32_t* intr_status); 511 512 int _dino_phy_intr_status_clear(const phymod_phy_access_t* phy, uint32_t intr_type); 513 514 int _dino_get_intr_reg (const phymod_phy_access_t *phy, uint32_t intr_type, uint16_t *bit_pos, uint16_t *int_grp); 515 516 DINO_INTR_TYPE_E convert_phymod_to_dino( uint16_t intr_type, uint16_t intf_side, uint16_t lane_mask); 517 518 int _dino_set_module_command(const phymod_access_t *pa, uint16_t xfer_addr, uint32_t slv_addr, unsigned char xfer_cnt, DINO_I2CM_CMD_E cmd); 519 520 int _dino_phy_i2c_read(const phymod_access_t *pa, uint32_t slv_dev_addr, uint32_t start_addr, uint32_t no_of_bytes, uint8_t* read_data); 521 522 int _dino_phy_i2c_write(const phymod_access_t *pa, uint32_t slv_dev_addr, uint32_t start_addr, uint32_t no_of_bytes, const uint8_t* write_data); 523 524 int _dino_phy_rptr_rtmr_mode_set(const phymod_phy_access_t* phy, uint16_t op_mode); 525 526 int _dino_bcast_enable_set(const phymod_core_access_t* core, uint16_t bcast_en); 527 528 int _dino_phy_gpio_config_set(const phymod_access_t* pa, int pin_number, phymod_gpio_mode_t gpio_mode); 529 530 int _dino_phy_gpio_config_get(const phymod_access_t* pa, int pin_number, phymod_gpio_mode_t* gpio_mode); 531 532 int _dino_phy_gpio_pin_value_set(const phymod_access_t* pa, int pin_number, int value); 533 534 int _dino_phy_gpio_pin_value_get(const phymod_access_t* pa, int pin_number, int* value); 535 536 int _dino_cfg_fw_ull_dp(const phymod_core_access_t* core, uint16_t op_datapath); 537 538 int dino_download_prog_eeprom(const phymod_access_t *pa, uint8_t *new_fw, uint32_t fw_length, uint8_t prg_eeprom); 539 540 int _dino_phy_multi_get(const phymod_access_t* pa, phymod_multi_data_t* multi_data); 541 542 int _dino_phy_shift_pos_get(uint32_t lane_map, uint32_t *shift_pos); 543 544 #endif /* DINO_CFG_SEQ_H */