dino_cfg_seq.c (371795B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 8 /* 9 * 10 * 11 * This program is the proprietary software of Broadcom Corporation 12 * and/or its licensors, and may only be used, duplicated, modified 13 * or distributed pursuant to the terms and conditions of a separate, 14 * written license agreement executed between you and Broadcom 15 * (an "Authorized License"). Except as set forth in an Authorized 16 * License, Broadcom grants no license (express or implied), right 17 * to use, or waiver of any kind with respect to the Software, and 18 * Broadcom expressly reserves all rights in and to the Software 19 * and all intellectual property rights therein. IF YOU HAVE 20 * NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE 21 * IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE 22 * ALL USE OF THE SOFTWARE. 23 * 24 * Except as expressly set forth in the Authorized License, 25 * 26 * 1. This program, including its structure, sequence and organization, 27 * constitutes the valuable trade secrets of Broadcom, and you shall use 28 * all reasonable efforts to protect the confidentiality thereof, 29 * and to use this information only in connection with your use of 30 * Broadcom integrated circuit products. 31 * 32 * 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS 33 * PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, 34 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, 35 * OR OTHERWISE, WITH RESPECT TO THE SOFTWARE. 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THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING 50 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$ 51 */ 52 53 #include <phymod/phymod.h> 54 #include <phymod/phymod_system.h> 55 #include <phymod/phymod_diagnostics.h> 56 #include <phymod/phymod_reg.h> 57 #include "bcmi_dino_defs.h" 58 #include "dino_cfg_seq.h" 59 #include "dino_serdes/common/srds_api_enum.h" 60 #include "dino_serdes/merlin_dino_src/merlin_dino_functions.h" 61 #include "dino_serdes/falcon2_dino_src/falcon2_dino_functions.h" 62 63 /* uController's firmware */ 64 extern unsigned char dino_ucode_Dino[]; 65 extern unsigned short dino_ucode_Dino_len; 66 67 int dino_get_chipid (const phymod_access_t *pa, uint32_t *chipid, uint32_t *rev) 68 { 69 70 BCMI_DINO_CHIP_IDr_t cid; 71 BCMI_DINO_CHIP_REVISIONr_t rid; 72 73 PHYMOD_IF_ERR_RETURN( 74 BCMI_DINO_READ_CHIP_IDr(pa, &cid)); 75 PHYMOD_IF_ERR_RETURN( 76 BCMI_DINO_READ_CHIP_REVISIONr(pa, &rid)); 77 78 *chipid = (BCMI_DINO_CHIP_REVISIONr_CHIP_ID_19_16f_GET(rid) << 16 ) | 79 BCMI_DINO_CHIP_IDr_GET(cid); 80 *rev = BCMI_DINO_CHIP_REVISIONr_CHIP_REVf_GET(rid); 81 82 PHYMOD_DEBUG_VERBOSE(("CHIP ID: %x REV:%x\n", *chipid, *rev)); 83 84 return PHYMOD_E_NONE; 85 } 86 87 /** Wait master message out 88 * This function is to ensure whether master has sent the previous message 89 * out successfully 90 * 91 * @param pa Pointer to phymod access structure 92 * @param exp_message Expected message specified by user 93 * @param poll_time Poll interval 94 * 95 * @return PHYMOD_E_NONE successful function execution 96 */ 97 int _dino_wait_mst_msgout(const phymod_access_t *pa, 98 DINO_MSGOUT_E exp_message, 99 int poll_time) 100 { 101 int retry_count = DINO_FW_DLOAD_RETRY_CNT; 102 DINO_MSGOUT_E msgout = MSGOUT_DONTCARE; 103 BCMI_DINO_MST_MSGOUTr_t msgout_t; 104 105 do { 106 /* Read general control msg out Register */ 107 PHYMOD_IF_ERR_RETURN( 108 BCMI_DINO_READ_MST_MSGOUTr(pa,&msgout_t)); 109 msgout = BCMI_DINO_MST_MSGOUTr_MST_MSGOUT_VALf_GET(msgout_t); 110 /* wait before reading again */ 111 if (poll_time != 0) { 112 /* sleep for specified seconds*/ 113 PHYMOD_SLEEP(poll_time); 114 } 115 } while ((msgout != exp_message) && --retry_count); 116 117 if (!retry_count) { 118 if (exp_message == MSGOUT_PRGRM_DONE) { 119 PHYMOD_DEBUG_VERBOSE(("MSG OUT:%x \n",msgout)); 120 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, (_PHYMOD_MSG("Fusing Firmware failed"))); 121 } else { 122 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INIT, (_PHYMOD_MSG("Firmware download failed"))); 123 } 124 } 125 126 return PHYMOD_E_NONE; 127 } 128 129 int _dino_fw_enable(const phymod_access_t* pa) 130 { 131 uint16_t retry_cnt = DINO_FW_ENABLE_RETRY_CNT; 132 uint16_t data = 0; 133 BCMI_DINO_FIRMWARE_ENr_t fw_en; 134 PHYMOD_MEMSET(&fw_en, 0, sizeof(BCMI_DINO_FIRMWARE_ENr_t)); 135 136 do { 137 PHYMOD_IF_ERR_RETURN( 138 BCMI_DINO_READ_FIRMWARE_ENr(pa, &fw_en)); 139 data = BCMI_DINO_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 140 PHYMOD_USLEEP(100); 141 } while ((data != 0) && (retry_cnt--)); 142 if (retry_cnt == 0) { 143 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 144 (_PHYMOD_MSG("mode config failed, micro controller is busy.."))); 145 } 146 retry_cnt = DINO_FW_ENABLE_RETRY_CNT; 147 /* Set FW_ENABLE = 1 */ 148 PHYMOD_IF_ERR_RETURN( 149 BCMI_DINO_READ_FIRMWARE_ENr(pa, &fw_en)); 150 /* coverity[operator_confusion] */ 151 BCMI_DINO_FIRMWARE_ENr_FW_ENABLE_VALf_SET(fw_en, 1); 152 PHYMOD_IF_ERR_RETURN( 153 BCMI_DINO_WRITE_FIRMWARE_ENr(pa, fw_en)); 154 do { 155 PHYMOD_IF_ERR_RETURN( 156 BCMI_DINO_READ_FIRMWARE_ENr(pa, &fw_en)); 157 data = BCMI_DINO_FIRMWARE_ENr_FW_ENABLE_VALf_GET(fw_en); 158 PHYMOD_USLEEP(100); 159 } while ((data != 0) && (retry_cnt--)); 160 if (retry_cnt == 0) { 161 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 162 (_PHYMOD_MSG("mode config failed, micro controller is busy.."))); 163 } 164 165 return PHYMOD_E_NONE; 166 } 167 int _dino_core_reset_set(const phymod_access_t *pa, phymod_reset_mode_t reset_mode, phymod_reset_direction_t direction) 168 { 169 BCMI_DINO_GEN_CTL1r_t gen_ctrl; 170 PHYMOD_MEMSET(&gen_ctrl, 0, sizeof(BCMI_DINO_GEN_CTL1r_t)); 171 172 PHYMOD_IF_ERR_RETURN( 173 BCMI_DINO_READ_GEN_CTL1r(pa, &gen_ctrl)); 174 175 if (reset_mode == phymodResetModeHard) { 176 /*Reset for chip*/ 177 BCMI_DINO_GEN_CTL1r_RESETBf_SET(gen_ctrl, 0); 178 PHYMOD_IF_ERR_RETURN( 179 BCMI_DINO_WRITE_GEN_CTL1r(pa, gen_ctrl)); 180 /*Above chip reset resets the cores also !*/ 181 PHYMOD_USLEEP(10000); 182 } else if (reset_mode == phymodResetModeSoft) { 183 /*Reset registers*/ 184 BCMI_DINO_GEN_CTL1r_REG_RSTBf_SET(gen_ctrl, 0); 185 PHYMOD_IF_ERR_RETURN( 186 BCMI_DINO_WRITE_GEN_CTL1r(pa, gen_ctrl)); 187 } 188 189 return PHYMOD_E_NONE; 190 } 191 192 /** Download and Fuse firmware 193 * This function is used to download the firmware through I2C/MDIO 194 * and fuse it to SPI EEPROM if prg_eeprom flag is set 195 * 196 * @param pa Pointer to phymod access structure 197 * @param new_fw Pointer to firmware array 198 * @param fw_length Length of the firmware array 199 * @param prg_eeprom Flag used to program EEPROM 200 * 201 * @return num_bytes number of bytes successfully downloaded 202 */ 203 int dino_download_prog_eeprom(const phymod_access_t *pa, 204 uint8_t *new_fw, 205 uint32_t fw_length, 206 uint8_t prg_eeprom) 207 { 208 uint16_t num_bytes = 0; 209 uint16_t j = 0; 210 uint16_t data = 0; 211 uint16_t data1 = 0; 212 uint16_t data2 = 0; 213 uint16_t check_sum = 0; 214 int retry_count = DINO_FW_DLOAD_RETRY_CNT; 215 FIRMWARE_VERSIONr_t firmware_version; 216 BCMI_DINO_GEN_CTL2r_t gen_ctrl2; 217 BCMI_DINO_GEN_CTL3r_t gen_ctrl3; 218 BCMI_DINO_UC_BOOT_PORr_t boot_por; 219 BCMI_DINO_FIRMWARE_VERSIONr_t fw_ver; 220 BCMI_DINO_BOOTr_t boot; 221 BCMI_DINO_MST_MSGINr_t msg_in; 222 BCMI_DINO_SPI_CODE_LOAD_ENr_t spi_code_load_en; 223 BCMI_DINO_DWNLD_15r_t dwnld_15; 224 BCMI_DINO_DWNLD_16r_t dwnld_16; 225 BCMI_DINO_DWNLD_17r_t dwnld_17; 226 227 PHYMOD_MEMSET(&firmware_version, 0, sizeof(FIRMWARE_VERSIONr_t)); 228 PHYMOD_MEMSET(&boot_por, 0, sizeof(BCMI_DINO_UC_BOOT_PORr_t)); 229 PHYMOD_MEMSET(&msg_in, 0, sizeof(BCMI_DINO_MST_MSGINr_t)); 230 PHYMOD_MEMSET(&spi_code_load_en, 0, sizeof(BCMI_DINO_SPI_CODE_LOAD_ENr_t)); 231 PHYMOD_MEMSET(&gen_ctrl2, 0, sizeof(BCMI_DINO_GEN_CTL2r_t)); 232 PHYMOD_MEMSET(&gen_ctrl3, 0, sizeof(BCMI_DINO_GEN_CTL3r_t)); 233 PHYMOD_MEMSET(&boot, 0, sizeof(BCMI_DINO_BOOTr_t)); 234 PHYMOD_MEMSET(&fw_ver, 0, sizeof(BCMI_DINO_FIRMWARE_VERSIONr_t)); 235 PHYMOD_MEMSET(&spi_code_load_en, 0, sizeof(BCMI_DINO_SPI_CODE_LOAD_ENr_t)); 236 PHYMOD_MEMSET(&dwnld_15, 0, sizeof(BCMI_DINO_DWNLD_15r_t)); 237 PHYMOD_MEMSET(&dwnld_16, 0, sizeof(BCMI_DINO_DWNLD_16r_t)); 238 PHYMOD_MEMSET(&dwnld_17, 0, sizeof(BCMI_DINO_DWNLD_17r_t)); 239 240 /* STEP 1: Put Master under Reset */ 241 PHYMOD_IF_ERR_RETURN( 242 BCMI_DINO_READ_GEN_CTL2r(pa, &gen_ctrl2)); 243 /*resetting M0 micro*/ 244 BCMI_DINO_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2, 0); 245 /*resetting M0 micro perip*/ 246 BCMI_DINO_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2, 0); 247 PHYMOD_IF_ERR_RETURN( 248 BCMI_DINO_WRITE_GEN_CTL2r(pa, gen_ctrl2)); 249 250 /* STEP 2: Wait for any pending SPI download 251 * SPI download is not interrupted by Master Reset 252 * (this is a safety feature) so we need to wait its 253 * completion before starting the MDIO Download */ 254 do { 255 PHYMOD_IF_ERR_RETURN( 256 BCMI_DINO_READ_BOOTr(pa, &boot)); 257 data1 = BCMI_DINO_BOOTr_SERBOOT_BUSYf_GET(boot); 258 PHYMOD_USLEEP(500); 259 } while((data1 != 0) && (--retry_count)); 260 if (retry_count == 0) { 261 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 262 (_PHYMOD_MSG("ERR:SERBOOT BUSY BIT SET"))); 263 } 264 265 if(prg_eeprom) { 266 /* BCM82332 and BCM82793 do not have EEPROM. This feature will be added in future for BCM82795 */ 267 } 268 269 /* STEP 3: Program master enable, slave enable, broadcast enable bits */ 270 PHYMOD_IF_ERR_RETURN( 271 BCMI_DINO_READ_SPI_CODE_LOAD_ENr(pa, &spi_code_load_en)); 272 BCMI_DINO_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_SET(spi_code_load_en, 1); 273 BCMI_DINO_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_SET(spi_code_load_en, 0x3f); 274 PHYMOD_IF_ERR_RETURN( 275 BCMI_DINO_WRITE_SPI_CODE_LOAD_ENr(pa, spi_code_load_en)); 276 PHYMOD_IF_ERR_RETURN( 277 BCMI_DINO_READ_SPI_CODE_LOAD_ENr(pa, &spi_code_load_en)); 278 if ((BCMI_DINO_SPI_CODE_LOAD_ENr_SLV_CODE_DOWNLOAD_ENf_GET(spi_code_load_en) != 0x3f) || 279 !(BCMI_DINO_SPI_CODE_LOAD_ENr_MST_CODE_DOWNLOAD_ENf_GET(spi_code_load_en))) { 280 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 281 (_PHYMOD_MSG("ERR: BROADCAST ENABLE IS NOT SET"))); 282 } 283 284 /* STEP 4: Force master download done, slave download done bit to 0 285 * set external boot (serboot) to 1 */ 286 PHYMOD_IF_ERR_RETURN( 287 BCMI_DINO_READ_UC_BOOT_PORr(pa, &boot_por)); 288 /* Force Master New Download */ 289 BCMI_DINO_UC_BOOT_PORr_MST_DWLD_DONEf_SET(boot_por, 0); 290 /* Force Slave New Download */ 291 BCMI_DINO_UC_BOOT_PORr_SLV_DWLD_DONEf_SET(boot_por, 0); 292 /*set to 0 for mdio default download on reset*/ 293 BCMI_DINO_UC_BOOT_PORr_SPI_PORT_USEDf_SET(boot_por, 0); 294 BCMI_DINO_UC_BOOT_PORr_SLV_RST_ENf_SET(boot_por, 0); 295 BCMI_DINO_UC_BOOT_PORr_SERBOOTf_SET(boot_por, 1); 296 PHYMOD_IF_ERR_RETURN( 297 BCMI_DINO_WRITE_UC_BOOT_PORr(pa, boot_por)); 298 299 /* STEP 5: RELEASE Master under Reset */ 300 PHYMOD_IF_ERR_RETURN( 301 BCMI_DINO_READ_GEN_CTL2r(pa, &gen_ctrl2)); 302 BCMI_DINO_GEN_CTL2r_MST_UCP_RSTBf_SET(gen_ctrl2, 1); 303 PHYMOD_IF_ERR_RETURN( 304 BCMI_DINO_WRITE_GEN_CTL2r(pa, gen_ctrl2)); 305 PHYMOD_IF_ERR_RETURN( 306 BCMI_DINO_READ_GEN_CTL2r(pa, &gen_ctrl2)); 307 BCMI_DINO_GEN_CTL2r_MST_RSTBf_SET(gen_ctrl2, 1); 308 PHYMOD_IF_ERR_RETURN( 309 BCMI_DINO_WRITE_GEN_CTL2r(pa, gen_ctrl2)); 310 311 /* STEP 6: MDI/I2C Download */ 312 /* Waiting for serboot_busy */ 313 retry_count = DINO_FW_DLOAD_RETRY_CNT; 314 do { 315 PHYMOD_IF_ERR_RETURN( 316 BCMI_DINO_READ_BOOTr(pa, &boot)); 317 data1 = BCMI_DINO_BOOTr_SERBOOT_BUSYf_GET(boot); 318 PHYMOD_USLEEP(500); 319 } while ((data1 != 1) && (--retry_count)); 320 if (retry_count == 0) { 321 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 322 (_PHYMOD_MSG("ERR:SERBOOT BUSY BIT NOT SET"))); 323 return PHYMOD_E_FAIL; 324 } 325 326 PHYMOD_IF_ERR_RETURN 327 (_dino_wait_mst_msgout(pa, MSGOUT_FLASH, 0)); 328 /* coverity[operator_confusion] */ 329 BCMI_DINO_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in, 0); 330 PHYMOD_IF_ERR_RETURN( 331 BCMI_DINO_WRITE_MST_MSGINr(pa, msg_in)); 332 PHYMOD_IF_ERR_RETURN( 333 _dino_wait_mst_msgout(pa, MSGOUT_NEXT, 0)); 334 /* STEP 7: Program master and slave boot address */ 335 /* coverity[operator_confusion] */ 336 BCMI_DINO_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in, 0); 337 PHYMOD_IF_ERR_RETURN( 338 BCMI_DINO_WRITE_MST_MSGINr(pa, msg_in)); 339 340 num_bytes = fw_length; 341 /* STEP 8: Download the 32 byte header first */ 342 for (j = 0; j <= DINO_FW_HEADER_SIZE; j += 2) { 343 /*sending next ucode data*/ 344 data = (new_fw[j + 1] << 8) | new_fw[j]; 345 check_sum ^= new_fw[j] ^ new_fw[j + 1]; 346 /* Send next word */ 347 BCMI_DINO_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in, data); 348 PHYMOD_IF_ERR_RETURN( 349 BCMI_DINO_WRITE_MST_MSGINr(pa, msg_in)); 350 } 351 PHYMOD_USLEEP(2100); 352 /* STEP 9: Download the remaining portion of the firmware */ 353 for (j = DINO_FW_HEADER_SIZE + 2; j < num_bytes; j += 2) { 354 /*sending next ucode data*/ 355 data = (new_fw[j + 1] << 8) | new_fw[j]; 356 check_sum ^= new_fw[j] ^ new_fw[j + 1]; 357 /* Send next word */ 358 BCMI_DINO_MST_MSGINr_MST_MSGIN_VALf_SET(msg_in, data); 359 PHYMOD_IF_ERR_RETURN( 360 BCMI_DINO_WRITE_MST_MSGINr(pa, msg_in)); 361 if ((j % 32) == 0) { 362 PHYMOD_USLEEP(2100); 363 } 364 } 365 /* STEP 10: i) Verify whether the firmware download is done for master and slaves */ 366 retry_count = DINO_FW_DLOAD_RETRY_CNT; 367 do { 368 /* check download_done flags*/ 369 PHYMOD_IF_ERR_RETURN( 370 BCMI_DINO_READ_UC_BOOT_PORr(pa, &boot_por)); 371 if((BCMI_DINO_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por) == 1) && 372 (BCMI_DINO_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por) == 0x3f)){ 373 PHYMOD_DEBUG_VERBOSE(("Firmware Download Done\n")); 374 break; 375 } 376 } while (--retry_count); 377 378 if (!retry_count) { 379 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_INIT, (_PHYMOD_MSG("Firmware download failed"))); 380 } 381 382 /* STEP 11: ii) Verify serboot busy and serboot done once bits */ 383 retry_count = DINO_FW_DLOAD_RETRY_CNT; 384 do { 385 PHYMOD_IF_ERR_RETURN( 386 BCMI_DINO_READ_BOOTr(pa, &boot)); 387 data1 = BCMI_DINO_BOOTr_SERBOOT_BUSYf_GET(boot); 388 data2 = BCMI_DINO_BOOTr_SERBOOT_DONE_ONCEf_GET(boot); 389 PHYMOD_USLEEP(500); 390 } while (((data1 != 0) && (data2 == 1)) && (--retry_count)); 391 if (retry_count == 0) { 392 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 393 (_PHYMOD_MSG("ERR:SERBOOT BUSY BIT SET"))); 394 return PHYMOD_E_FAIL; 395 } 396 397 PHYMOD_IF_ERR_RETURN( 398 BCMI_DINO_READ_DWNLD_15r(pa, &dwnld_15)); 399 PHYMOD_IF_ERR_RETURN( 400 BCMI_DINO_READ_DWNLD_16r(pa, &dwnld_16)); 401 PHYMOD_IF_ERR_RETURN( 402 BCMI_DINO_READ_DWNLD_17r(pa, &dwnld_17)); 403 404 if ((BCMI_DINO_DWNLD_15r_DOWNLOAD_15f_GET(dwnld_15) != 0x600D) || 405 (BCMI_DINO_DWNLD_16r_DOWNLOAD_16f_GET(dwnld_16) != 0x600D) || 406 (BCMI_DINO_DWNLD_17r_DOWNLOAD_17f_GET(dwnld_17) != 0x600D)) { 407 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 408 (_PHYMOD_MSG("chksum Failed"))); 409 } 410 /* Read the firmware version */ 411 PHYMOD_IF_ERR_RETURN( 412 READ_FIRMWARE_VERSIONr(pa, &firmware_version)); 413 PHYMOD_DEBUG_VERBOSE(("Firmware Version: 0x%x\n", firmware_version.v[0])); 414 415 return PHYMOD_E_NONE; 416 } 417 418 int _dino_core_init(const phymod_core_access_t* core, 419 const phymod_core_init_config_t* init_config) 420 { 421 int rv = PHYMOD_E_NONE; 422 BCMI_DINO_DWNLD_15r_t dwnld_15; 423 BCMI_DINO_DWNLD_16r_t dwnld_16; 424 BCMI_DINO_DWNLD_17r_t dwnld_17; 425 BCMI_DINO_UC_BOOT_PORr_t boot_por; 426 BCMI_DINO_FIRMWARE_VERSIONr_t firmware_version; 427 uint16_t new_firmware_version = 0; 428 const phymod_access_t *pa = &core->access; 429 PHYMOD_MEMSET(&dwnld_15, 0, sizeof(BCMI_DINO_DWNLD_15r_t)); 430 PHYMOD_MEMSET(&dwnld_16, 0, sizeof(BCMI_DINO_DWNLD_16r_t)); 431 PHYMOD_MEMSET(&dwnld_17, 0, sizeof(BCMI_DINO_DWNLD_17r_t)); 432 PHYMOD_MEMSET(&boot_por, 0, sizeof(BCMI_DINO_UC_BOOT_PORr_t)); 433 PHYMOD_MEMSET(&firmware_version, 0, sizeof(BCMI_DINO_FIRMWARE_VERSIONr_t)); 434 435 /* Read the firmware version */ 436 PHYMOD_IF_ERR_RETURN( 437 READ_FIRMWARE_VERSIONr(pa, &firmware_version)); 438 new_firmware_version = (((dino_ucode_Dino[12] & 0xff) << 8) | (dino_ucode_Dino[13] & 0xff)); 439 switch(init_config->firmware_load_method) { 440 case phymodFirmwareLoadMethodInternal: 441 /* This case is added for unicast */ 442 /* Broadcast way of FW download sequence 443 * 1. Reset core for all cores 444 * 2. Enable the broadcast for all the cores 445 * 3. Download FW for one core in MDIO bus 446 * 4. Disable the broadcast and Verify the FW on all cores 447 */ 448 if (PHYMOD_CORE_INIT_F_FW_FORCE_DOWNLOAD_GET(init_config)){ 449 if (PHYMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD_GET(init_config)) { 450 /* Do chip hard reset and Resetting the Cores */ 451 PHYMOD_IF_ERR_RETURN( 452 _dino_core_reset_set(pa, phymodResetModeHard, phymodResetDirectionInOut)); 453 } else if (PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 454 PHYMOD_IF_ERR_RETURN( 455 _dino_bcast_enable_set(core, 1)); 456 } else if (PHYMOD_CORE_INIT_F_EXECUTE_FW_LOAD_GET(init_config)) { 457 PHYMOD_DEBUG_VERBOSE(("Starting Firmware download through MDIO, it takes few seconds...\n")); 458 rv = dino_download_prog_eeprom(pa, 459 dino_ucode_Dino, 460 dino_ucode_Dino_len, 461 0); 462 if ((rv != PHYMOD_E_NONE) && 463 (rv != DINO_FW_ALREADY_DOWNLOADED)) { 464 PHYMOD_RETURN_WITH_ERR(rv, 465 (_PHYMOD_MSG("firmware download failed"))); 466 } else { 467 if (rv == DINO_FW_ALREADY_DOWNLOADED) { 468 rv = PHYMOD_E_NONE; 469 } 470 return rv; 471 } 472 } else if (PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 473 /* check download_done flags again */ 474 PHYMOD_IF_ERR_RETURN( 475 BCMI_DINO_READ_UC_BOOT_PORr(pa, &boot_por)); 476 if((BCMI_DINO_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por) != 1) && 477 (BCMI_DINO_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por) != 0x3f)){ 478 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 479 (_PHYMOD_MSG("ERR:Firmware Download Done got cleared"))); 480 } 481 /* Read the firmware version */ 482 PHYMOD_IF_ERR_RETURN( 483 READ_FIRMWARE_VERSIONr(pa, &firmware_version)); 484 if (firmware_version.v[0] == 0x1) { 485 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 486 (_PHYMOD_MSG("ERR:Invalid Firmware version Downloaded"))); 487 } 488 PHYMOD_IF_ERR_RETURN( 489 BCMI_DINO_READ_DWNLD_15r(pa, &dwnld_15)); 490 PHYMOD_IF_ERR_RETURN( 491 BCMI_DINO_READ_DWNLD_16r(pa, &dwnld_16)); 492 PHYMOD_IF_ERR_RETURN( 493 BCMI_DINO_READ_DWNLD_17r(pa, &dwnld_17)); 494 if ((BCMI_DINO_DWNLD_15r_DOWNLOAD_15f_GET(dwnld_15) != 0x600D) || 495 (BCMI_DINO_DWNLD_16r_DOWNLOAD_16f_GET(dwnld_16) != 0x600D) || 496 (BCMI_DINO_DWNLD_17r_DOWNLOAD_17f_GET(dwnld_17) != 0x600D)) { 497 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 498 (_PHYMOD_MSG("chksum Failed"))); 499 } 500 } else if (PHYMOD_CORE_INIT_F_FW_LOAD_END_GET(init_config)) { 501 /* disable broadcast */ 502 PHYMOD_IF_ERR_RETURN( 503 _dino_bcast_enable_set(core, 0)); 504 PHYMOD_DIAG_OUT(("Firmware download success\n")); 505 } 506 } else if(PHYMOD_CORE_INIT_F_FW_AUTO_DOWNLOAD_GET(init_config) && new_firmware_version != firmware_version.v[0]){ 507 if (PHYMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD_GET(init_config)) { 508 /* Do chip hard reset and Resetting the Cores */ 509 PHYMOD_IF_ERR_RETURN( 510 _dino_core_reset_set(pa, phymodResetModeHard, phymodResetDirectionInOut)); 511 } else if (PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 512 PHYMOD_IF_ERR_RETURN( 513 _dino_bcast_enable_set(core, 1)); 514 } else if (PHYMOD_CORE_INIT_F_EXECUTE_FW_LOAD_GET(init_config)) { 515 PHYMOD_DEBUG_VERBOSE(("Starting Firmware download through MDIO, it takes few seconds...\n")); 516 rv = dino_download_prog_eeprom(pa, 517 dino_ucode_Dino, 518 dino_ucode_Dino_len, 519 0); 520 if ((rv != PHYMOD_E_NONE) && 521 (rv != DINO_FW_ALREADY_DOWNLOADED)) { 522 PHYMOD_RETURN_WITH_ERR(rv, 523 (_PHYMOD_MSG("firmware download failed"))); 524 } else { 525 if (rv == DINO_FW_ALREADY_DOWNLOADED) { 526 rv = PHYMOD_E_NONE; 527 } 528 return rv; 529 } 530 } else if (PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 531 /* check download_done flags again */ 532 PHYMOD_IF_ERR_RETURN( 533 BCMI_DINO_READ_UC_BOOT_PORr(pa, &boot_por)); 534 if((BCMI_DINO_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por) != 1) && 535 (BCMI_DINO_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por) != 0x3f)){ 536 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 537 (_PHYMOD_MSG("ERR:Firmware Download Done got cleared"))); 538 } 539 /* Read the firmware version */ 540 PHYMOD_IF_ERR_RETURN( 541 READ_FIRMWARE_VERSIONr(pa, &firmware_version)); 542 if (firmware_version.v[0] == 0x1) { 543 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 544 (_PHYMOD_MSG("ERR:Invalid Firmware version Downloaded"))); 545 } 546 PHYMOD_IF_ERR_RETURN( 547 BCMI_DINO_READ_DWNLD_15r(pa, &dwnld_15)); 548 PHYMOD_IF_ERR_RETURN( 549 BCMI_DINO_READ_DWNLD_16r(pa, &dwnld_16)); 550 PHYMOD_IF_ERR_RETURN( 551 BCMI_DINO_READ_DWNLD_17r(pa, &dwnld_17)); 552 if ((BCMI_DINO_DWNLD_15r_DOWNLOAD_15f_GET(dwnld_15) != 0x600D) || 553 (BCMI_DINO_DWNLD_16r_DOWNLOAD_16f_GET(dwnld_16) != 0x600D) || 554 (BCMI_DINO_DWNLD_17r_DOWNLOAD_17f_GET(dwnld_17) != 0x600D)) { 555 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 556 (_PHYMOD_MSG("chksum Failed"))); 557 } 558 } else if (PHYMOD_CORE_INIT_F_FW_LOAD_END_GET(init_config)) { 559 PHYMOD_DIAG_OUT(("Firmware download success\n")); 560 /* disable broadcast */ 561 PHYMOD_IF_ERR_RETURN( 562 _dino_bcast_enable_set(core, 0)); 563 } 564 } else if(firmware_version.v[0] == 1){ 565 if (PHYMOD_CORE_INIT_F_RESET_CORE_FOR_FW_LOAD_GET(init_config)) { 566 /* Do chip hard reset and Resetting the Cores */ 567 PHYMOD_IF_ERR_RETURN( 568 _dino_core_reset_set(pa, phymodResetModeHard, phymodResetDirectionInOut)); 569 } else if (PHYMOD_CORE_INIT_F_UNTIL_FW_LOAD_GET(init_config)) { 570 PHYMOD_IF_ERR_RETURN( 571 _dino_bcast_enable_set(core, 1)); 572 } else if (PHYMOD_CORE_INIT_F_EXECUTE_FW_LOAD_GET(init_config)) { 573 PHYMOD_DEBUG_VERBOSE(("Starting Firmware download through MDIO, it takes few seconds...\n")); 574 rv = dino_download_prog_eeprom(pa, 575 dino_ucode_Dino, 576 dino_ucode_Dino_len, 577 0); 578 if ((rv != PHYMOD_E_NONE) && 579 (rv != DINO_FW_ALREADY_DOWNLOADED)) { 580 PHYMOD_RETURN_WITH_ERR(rv, 581 (_PHYMOD_MSG("firmware download failed"))); 582 } else { 583 if (rv == DINO_FW_ALREADY_DOWNLOADED) { 584 rv = PHYMOD_E_NONE; 585 } 586 return rv; 587 } 588 } else if (PHYMOD_CORE_INIT_F_RESUME_AFTER_FW_LOAD_GET(init_config)) { 589 /* check download_done flags again */ 590 PHYMOD_IF_ERR_RETURN( 591 BCMI_DINO_READ_UC_BOOT_PORr(pa, &boot_por)); 592 if((BCMI_DINO_UC_BOOT_PORr_MST_DWLD_DONEf_GET(boot_por) != 1) && 593 (BCMI_DINO_UC_BOOT_PORr_SLV_DWLD_DONEf_GET(boot_por) != 0x3f)){ 594 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 595 (_PHYMOD_MSG("ERR:Firmware Download Done got cleared"))); 596 } 597 /* Read the firmware version */ 598 PHYMOD_IF_ERR_RETURN( 599 READ_FIRMWARE_VERSIONr(pa, &firmware_version)); 600 if (firmware_version.v[0] == 0x1) { 601 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 602 (_PHYMOD_MSG("ERR:Invalid Firmware version Downloaded"))); 603 } 604 PHYMOD_IF_ERR_RETURN( 605 BCMI_DINO_READ_DWNLD_15r(pa, &dwnld_15)); 606 PHYMOD_IF_ERR_RETURN( 607 BCMI_DINO_READ_DWNLD_16r(pa, &dwnld_16)); 608 PHYMOD_IF_ERR_RETURN( 609 BCMI_DINO_READ_DWNLD_17r(pa, &dwnld_17)); 610 if ((BCMI_DINO_DWNLD_15r_DOWNLOAD_15f_GET(dwnld_15) != 0x600D) || 611 (BCMI_DINO_DWNLD_16r_DOWNLOAD_16f_GET(dwnld_16) != 0x600D) || 612 (BCMI_DINO_DWNLD_17r_DOWNLOAD_17f_GET(dwnld_17) != 0x600D)) { 613 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_FAIL, 614 (_PHYMOD_MSG("chksum Failed"))); 615 } 616 } else if (PHYMOD_CORE_INIT_F_FW_LOAD_END_GET(init_config)) { 617 /* disable broadcast */ 618 PHYMOD_IF_ERR_RETURN( 619 _dino_bcast_enable_set(core, 0)); 620 PHYMOD_DIAG_OUT(("Firmware download success\n")); 621 } 622 } else { 623 if (firmware_version.v[0] != 0) { 624 PHYMOD_IF_ERR_RETURN( 625 _dino_bcast_enable_set(core, 0)); 626 } 627 } 628 break; 629 case phymodFirmwareLoadMethodExternal: 630 return PHYMOD_E_UNAVAIL; 631 break; 632 case phymodFirmwareLoadMethodNone: 633 break; 634 case phymodFirmwareLoadMethodProgEEPROM: 635 return PHYMOD_E_UNAVAIL; 636 break; 637 default: 638 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 639 (_PHYMOD_MSG("illegal fw load method"))); 640 } 641 PHYMOD_IF_ERR_RETURN ( 642 _dino_cfg_fw_ull_dp(core, init_config->op_datapath)); 643 644 return rv; 645 } 646 647 int _dino_set_slice_reg (const phymod_access_t* pa, DINO_SLICE_OP_TYPE slice_op_type, uint16_t if_side, uint16_t lane) 648 { 649 BCMI_DINO_SLICEr_t slice_reg; 650 BCMI_DINO_DECD_MODE_STS0r_t mode_sts0; 651 BCMI_DINO_DECD_MODE_STS1r_t mode_sts1; 652 BCMI_DINO_DECD_MODE_STS2r_t mode_sts2; 653 BCMI_DINO_DECD_MODE_STS3r_t mode_sts3; 654 BCMI_DINO_DECD_MODE_STS4r_t mode_sts4; 655 uint16_t sys_sel = 0; 656 uint16_t line_sel = 0; 657 uint16_t dev_type = 0; 658 uint16_t lane_mask = 0; 659 uint16_t slice_0 = 0; 660 uint16_t slice_1 = 0; 661 uint16_t slice_2 = 0; 662 PHYMOD_MEMSET(&slice_reg, 0, sizeof(BCMI_DINO_SLICEr_t)); 663 PHYMOD_MEMSET(&mode_sts0, 0, sizeof(BCMI_DINO_DECD_MODE_STS0r_t)); 664 PHYMOD_MEMSET(&mode_sts1, 0, sizeof(BCMI_DINO_DECD_MODE_STS1r_t)); 665 PHYMOD_MEMSET(&mode_sts2, 0, sizeof(BCMI_DINO_DECD_MODE_STS2r_t)); 666 PHYMOD_MEMSET(&mode_sts3, 0, sizeof(BCMI_DINO_DECD_MODE_STS3r_t)); 667 PHYMOD_MEMSET(&mode_sts4, 0, sizeof(BCMI_DINO_DECD_MODE_STS4r_t)); 668 669 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 670 671 PHYMOD_IF_ERR_RETURN( 672 BCMI_DINO_READ_DECD_MODE_STS0r(pa, &mode_sts0)); 673 PHYMOD_IF_ERR_RETURN( 674 BCMI_DINO_READ_DECD_MODE_STS1r(pa, &mode_sts1)); 675 PHYMOD_IF_ERR_RETURN( 676 BCMI_DINO_READ_DECD_MODE_STS2r(pa, &mode_sts2)); 677 PHYMOD_IF_ERR_RETURN( 678 BCMI_DINO_READ_DECD_MODE_STS3r(pa, &mode_sts3)); 679 PHYMOD_IF_ERR_RETURN( 680 BCMI_DINO_READ_DECD_MODE_STS4r(pa, &mode_sts4)); 681 682 if (slice_op_type == DINO_SLICE_RESET) { 683 slice_0 = 1; 684 PHYMOD_IF_ERR_RETURN( 685 BCMI_DINO_READ_SLICEr(pa, &slice_reg)); 686 if ((mode_sts0.v[0] & 0xff9) || 687 (mode_sts1.v[0] & 0xf) || 688 (mode_sts2.v[0] & 0xf)) { 689 slice_0 = 1; 690 } 691 if ((mode_sts0.v[0] & 0x2) || 692 (mode_sts1.v[0] & 0xf0) || 693 (mode_sts2.v[0] & 0xf0)) { 694 slice_1 = 1; 695 } 696 if ((mode_sts0.v[0] & 0x4) || 697 (mode_sts1.v[0] & 0xf00) || 698 (mode_sts2.v[0] & 0xf00)) { 699 slice_2 = 1; 700 } 701 BCMI_DINO_SLICEr_CLR(slice_reg); 702 BCMI_DINO_SLICEr_SYS_SELf_SET(slice_reg, 0); 703 BCMI_DINO_SLICEr_LIN_SELf_SET(slice_reg, 1); 704 BCMI_DINO_SLICEr_SLICE_0_SELf_SET(slice_reg, slice_0); 705 BCMI_DINO_SLICEr_SLICE_1_SELf_SET(slice_reg, slice_1); 706 BCMI_DINO_SLICEr_SLICE_2_SELf_SET(slice_reg, slice_2); 707 BCMI_DINO_SLICEr_LANE_SELf_SET(slice_reg, 0x1); 708 PHYMOD_IF_ERR_RETURN( 709 BCMI_DINO_WRITE_SLICEr(pa, slice_reg)); 710 return PHYMOD_E_NONE; 711 } 712 713 if (if_side == DINO_IF_SYS) { 714 sys_sel = 1; 715 line_sel = 0; 716 } else { 717 sys_sel = 0; 718 line_sel = 1; 719 } 720 721 dev_type = pa->devad; 722 if(!dev_type) { 723 dev_type = DINO_DEV_PMA_PMD; 724 } 725 726 if (slice_op_type == DINO_SLICE_BROADCAST) { 727 if (if_side == DINO_IF_SYS) { 728 if (lane_mask & DINO_40G_PORT0_LANE_MASK) { 729 slice_0 = 1; 730 } 731 if (lane_mask & DINO_40G_PORT1_LANE_MASK) { 732 slice_1 = 1; 733 } 734 if (lane_mask & DINO_40G_PORT2_LANE_MASK) { 735 slice_2 = 1; 736 } 737 if (lane_mask == DINO_40G_PORT0_LANE_MASK || 738 lane_mask == DINO_40G_PORT1_LANE_MASK || 739 lane_mask == DINO_40G_PORT2_LANE_MASK || 740 lane_mask == DINO_100G_TYPE1_LANE_MASK || 741 lane_mask == DINO_100G_TYPE2_LANE_MASK || 742 lane_mask == DINO_100G_TYPE3_LANE_MASK) { 743 lane_mask = DINO_40G_PORT0_LANE_MASK; 744 } else { 745 lane_mask = (1 << (lane % DINO_MAX_FALCON_LANE)); 746 } 747 } else { 748 if (lane < DINO_MAX_FALCON_LANE) { 749 slice_0 = 1; 750 } else if ((lane >= DINO_MAX_FALCON_LANE) && (lane < 8)) { 751 slice_1 = 1; 752 } else { 753 slice_2 = 1; 754 } 755 if (lane_mask == DINO_40G_PORT0_LANE_MASK || 756 lane_mask == DINO_40G_PORT1_LANE_MASK || 757 lane_mask == DINO_40G_PORT2_LANE_MASK) { 758 lane_mask = DINO_40G_PORT0_LANE_MASK; 759 } else { 760 lane_mask = (1 << (lane % DINO_MAX_FALCON_LANE)); 761 } 762 } 763 } else if (slice_op_type == DINO_SLICE_UNICAST) { 764 if (lane < DINO_MAX_FALCON_LANE) { 765 slice_0 = 1; 766 } else if ((lane >= DINO_MAX_FALCON_LANE) && (lane < 8)) { 767 slice_1 = 1; 768 } else { 769 slice_2 = 1; 770 } 771 lane_mask = (1 << (lane % DINO_MAX_FALCON_LANE)); 772 } 773 774 if (dev_type == DINO_DEV_PMA_PMD) { 775 PHYMOD_IF_ERR_RETURN( 776 BCMI_DINO_READ_SLICEr(pa, &slice_reg)); 777 BCMI_DINO_SLICEr_CLR(slice_reg); 778 BCMI_DINO_SLICEr_SYS_SELf_SET(slice_reg, sys_sel); 779 BCMI_DINO_SLICEr_LIN_SELf_SET(slice_reg, line_sel); 780 BCMI_DINO_SLICEr_SLICE_0_SELf_SET(slice_reg, slice_0); 781 BCMI_DINO_SLICEr_SLICE_1_SELf_SET(slice_reg, slice_1); 782 BCMI_DINO_SLICEr_SLICE_2_SELf_SET(slice_reg, slice_2); 783 BCMI_DINO_SLICEr_LANE_SELf_SET(slice_reg, lane_mask); 784 PHYMOD_IF_ERR_RETURN( 785 BCMI_DINO_WRITE_SLICEr(pa, slice_reg)); 786 PHYMOD_DEBUG_VERBOSE(("\n[-- slice = %x ===]\n", BCMI_DINO_SLICEr_GET(slice_reg))); 787 } else { 788 /* Needs to add AN slice sequence */ 789 } 790 791 return PHYMOD_E_NONE; 792 } 793 794 int _dino_fifo_reset(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t *config) { 795 uint16_t lane_mask = 0; 796 uint16_t if_side = 0; 797 uint16_t lane = 0; 798 const phymod_access_t *pa = &phy->access; 799 uint16_t data = 0; 800 BCMI_DINO_FIFO_RST_FRC_CTL1r_t fifo_rst_frc_ln; 801 BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_t fifo_rst_frcval_ln; 802 BCMI_DINO_FIFO_RST_FRC_CTL0r_t fifo_rst_frc_sys; 803 BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_t fifo_rst_frcval_sys; 804 PHYMOD_MEMSET(&fifo_rst_frc_ln, 0, sizeof(BCMI_DINO_FIFO_RST_FRC_CTL1r_t)); 805 PHYMOD_MEMSET(&fifo_rst_frcval_ln, 0, sizeof(BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_t)); 806 PHYMOD_MEMSET(&fifo_rst_frc_sys, 0, sizeof(BCMI_DINO_FIFO_RST_FRC_CTL0r_t)); 807 PHYMOD_MEMSET(&fifo_rst_frcval_sys, 0, sizeof(BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_t)); 808 809 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 810 DINO_GET_INTF_SIDE(phy, if_side); 811 812 if ((config->data_rate == DINO_SPD_100G) || (config->data_rate == DINO_SPD_106G) || (config->data_rate == DINO_SPD_111G)) { 813 lane_mask = 0xfff; 814 } 815 for (lane = 0; lane < DINO_MAX_LANE; lane++) { 816 if (lane_mask & (1 << lane)) { 817 if (if_side == DINO_IF_LINE) { 818 /* Set force val to 0*/ 819 PHYMOD_IF_ERR_RETURN( 820 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL1r(pa, &fifo_rst_frcval_ln)); 821 data = fifo_rst_frcval_ln.v[0]; 822 data &= ~(1 << lane); 823 BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_SET(fifo_rst_frcval_ln, data); 824 PHYMOD_IF_ERR_RETURN( 825 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL1r(pa, fifo_rst_frcval_ln)); 826 827 /* Set force to 1*/ 828 PHYMOD_IF_ERR_RETURN( 829 BCMI_DINO_READ_FIFO_RST_FRC_CTL1r(pa, &fifo_rst_frc_ln)); 830 data = fifo_rst_frc_ln.v[0]; 831 data |= (1 << lane); 832 BCMI_DINO_FIFO_RST_FRC_CTL1r_SET(fifo_rst_frc_ln, data); 833 PHYMOD_IF_ERR_RETURN( 834 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL1r(pa, fifo_rst_frc_ln)); 835 836 /* Set force val to default*/ 837 PHYMOD_IF_ERR_RETURN( 838 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL1r(pa, &fifo_rst_frcval_ln)); 839 data = fifo_rst_frcval_ln.v[0]; 840 data |= (1 << lane); 841 BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_SET(fifo_rst_frcval_ln, data); 842 PHYMOD_IF_ERR_RETURN( 843 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL1r(pa, fifo_rst_frcval_ln)); 844 845 /* Set force to default val*/ 846 PHYMOD_IF_ERR_RETURN( 847 BCMI_DINO_READ_FIFO_RST_FRC_CTL1r(pa, &fifo_rst_frc_ln)); 848 849 fifo_rst_frc_ln.v[0] &= ~(1 << lane); 850 PHYMOD_IF_ERR_RETURN( 851 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL1r(pa, fifo_rst_frc_ln)); 852 } else { 853 /* Set force val to 0*/ 854 PHYMOD_IF_ERR_RETURN( 855 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL0r(pa, &fifo_rst_frcval_sys)); 856 data = fifo_rst_frcval_sys.v[0]; 857 data &= ~(1 << lane); 858 BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_SET(fifo_rst_frcval_sys, data); 859 PHYMOD_IF_ERR_RETURN( 860 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL0r(pa, fifo_rst_frcval_sys)); 861 862 /* Set force to 1*/ 863 PHYMOD_IF_ERR_RETURN( 864 BCMI_DINO_READ_FIFO_RST_FRC_CTL0r(pa, &fifo_rst_frc_sys)); 865 data = fifo_rst_frc_sys.v[0]; 866 data |= (1 << lane); 867 BCMI_DINO_FIFO_RST_FRC_CTL0r_SET(fifo_rst_frc_sys, data); 868 PHYMOD_IF_ERR_RETURN( 869 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL0r(pa, fifo_rst_frc_sys)); 870 871 /* Set force val to default*/ 872 PHYMOD_IF_ERR_RETURN( 873 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL0r(pa, &fifo_rst_frcval_sys)); 874 data = fifo_rst_frcval_sys.v[0]; 875 data |= (1 << lane); 876 BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_SET(fifo_rst_frcval_sys, data); 877 PHYMOD_IF_ERR_RETURN( 878 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL0r(pa, fifo_rst_frcval_sys)); 879 880 /* Set force to default*/ 881 PHYMOD_IF_ERR_RETURN( 882 BCMI_DINO_READ_FIFO_RST_FRC_CTL0r(pa, &fifo_rst_frc_sys)); 883 fifo_rst_frc_sys.v[0] &= (1 << lane); 884 BCMI_DINO_FIFO_RST_FRC_CTL0r_SET(fifo_rst_frc_sys, data); 885 PHYMOD_IF_ERR_RETURN( 886 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL0r(pa, fifo_rst_frc_sys)); 887 } 888 } 889 } 890 return PHYMOD_E_NONE; 891 } 892 893 int _dino_phy_interface_config_set(const phymod_phy_access_t* phy, uint32_t flags, const phymod_phy_inf_config_t* config) 894 { 895 const phymod_access_t *pa = &phy->access; 896 897 898 PHYMOD_DEBUG_VERBOSE(("Configuring interface\n")); 899 /* Configure Ref Clock*/ 900 PHYMOD_DEBUG_VERBOSE(("Configuring REF clock %d\n",config->ref_clock)); 901 PHYMOD_IF_ERR_RETURN( 902 _dino_configure_ref_clock(&phy->access, config->ref_clock)); 903 904 /* Configure DUT MODE */ 905 PHYMOD_IF_ERR_RETURN( 906 _dino_config_dut_mode_reg(phy, config)); 907 908 /* Configure PLL Divider*/ 909 PHYMOD_IF_ERR_RETURN( 910 _dino_config_pll_div(phy, config)); 911 912 /* Configure Interface.*/ 913 PHYMOD_IF_ERR_RETURN( 914 _dino_interface_set(phy, config)); 915 916 /* store phy type */ 917 PHYMOD_IF_ERR_RETURN( 918 _dino_save_phy_type(pa, config)); 919 920 /* Do fifo reset */ 921 PHYMOD_IF_ERR_RETURN( 922 _dino_fifo_reset(phy, config)); 923 924 /* Set firmware enable */ 925 PHYMOD_IF_ERR_RETURN 926 (_dino_fw_enable(pa)); 927 928 return PHYMOD_E_NONE; 929 } 930 931 int _dino_interface_get(phymod_phy_access_t *phy, phymod_phy_inf_config_t *config, phymod_interface_t *intf) 932 { 933 PHYMOD_IF_ERR_RETURN( 934 _dino_restore_interface(phy, config, intf)); 935 936 return PHYMOD_E_NONE; 937 } 938 939 int _dino_phy_interface_config_get(phymod_phy_access_t *phy, uint32_t flags, phymod_phy_inf_config_t *config) 940 { 941 uint16_t if_side = 0; 942 uint16_t lane_mask = 0; 943 uint16_t lane = 0; 944 phymod_interface_t intf = 0; 945 uint16_t lane_index = 0; 946 uint32_t port_speed = 0; 947 uint16_t phy_type = 0; 948 uint16_t sw_gpreg_data = 0; 949 uint16_t mer_pll_mapval = 0; 950 uint16_t falcon_pll_mode = 0; 951 uint16_t reg_data = 0; 952 uint32_t chip_id = 0; 953 uint32_t rev = 0; 954 const phymod_access_t *pa = &phy->access; 955 BCMI_DINO_F25G_PLL_CAL_CTL7r_t falcon_pll_ctrl; 956 /* Get data rate, passthru, gearbox, get refclock, get intf side*/ 957 BCMI_DINO_DECD_MODE_STS0r_t mode_sts0; 958 BCMI_DINO_DECD_MODE_STS1r_t mode_sts1; 959 BCMI_DINO_DECD_MODE_STS2r_t mode_sts2; 960 BCMI_DINO_DECD_MODE_STS3r_t mode_sts3; 961 BCMI_DINO_DECD_MODE_STS4r_t mode_sts4; 962 PHYMOD_MEMSET(&mode_sts0, 0, sizeof(BCMI_DINO_DECD_MODE_STS0r_t)); 963 PHYMOD_MEMSET(&mode_sts1, 0, sizeof(BCMI_DINO_DECD_MODE_STS1r_t)); 964 PHYMOD_MEMSET(&mode_sts2, 0, sizeof(BCMI_DINO_DECD_MODE_STS2r_t)); 965 PHYMOD_MEMSET(&mode_sts3, 0, sizeof(BCMI_DINO_DECD_MODE_STS3r_t)); 966 PHYMOD_MEMSET(&mode_sts4, 0, sizeof(BCMI_DINO_DECD_MODE_STS4r_t)); 967 PHYMOD_MEMSET(&falcon_pll_ctrl, 0, sizeof(BCMI_DINO_F25G_PLL_CAL_CTL7r_t)); 968 969 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 970 DINO_GET_INTF_SIDE(phy, if_side); 971 972 PHYMOD_IF_ERR_RETURN(dino_get_chipid(&phy->access, &chip_id, &rev)); 973 974 if (!lane_mask) { 975 PHYMOD_DEBUG_VERBOSE(("Invalid Lanemask\n")); 976 return PHYMOD_E_PARAM; 977 } 978 PHYMOD_IF_ERR_RETURN( 979 BCMI_DINO_READ_DECD_MODE_STS0r(pa, &mode_sts0)); 980 PHYMOD_IF_ERR_RETURN( 981 BCMI_DINO_READ_DECD_MODE_STS1r(pa, &mode_sts1)); 982 PHYMOD_IF_ERR_RETURN( 983 BCMI_DINO_READ_DECD_MODE_STS2r(pa, &mode_sts2)); 984 PHYMOD_IF_ERR_RETURN( 985 BCMI_DINO_READ_DECD_MODE_STS3r(pa, &mode_sts3)); 986 PHYMOD_IF_ERR_RETURN( 987 BCMI_DINO_READ_DECD_MODE_STS4r(pa, &mode_sts4)); 988 989 if ((BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_PT_2TO11f_GET(mode_sts0)) || 990 (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_PT_1TO10f_GET(mode_sts0)) || 991 (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_PT_0TO9f_GET(mode_sts0))) { 992 config->data_rate = DINO_SPD_100G; 993 PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_CLR(phy); 994 } else if ((BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_GBOX_2TO11f_GET(mode_sts0)) || 995 (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_GBOX_1TO10f_GET(mode_sts0)) || 996 (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_GBOX_0TO9f_GET(mode_sts0))) { 997 config->data_rate = DINO_SPD_100G; 998 PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_SET(phy); 999 } else if (lane_mask == DINO_40G_PORT0_LANE_MASK) { 1000 if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_40G_MP0f_GET(mode_sts0)) { 1001 config->data_rate = DINO_SPD_40G; 1002 } 1003 } else if (lane_mask == DINO_40G_PORT1_LANE_MASK) { 1004 if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_40G_MP1f_GET(mode_sts0)) { 1005 config->data_rate = DINO_SPD_40G; 1006 } 1007 } else if (lane_mask == DINO_40G_PORT2_LANE_MASK) { 1008 if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_40G_MP2f_GET(mode_sts0)) { 1009 config->data_rate = DINO_SPD_40G; 1010 } 1011 } else { 1012 for (lane_index = 0; lane_index <= DINO_MAX_LANE; lane_index ++) { 1013 if (lane_mask & (0x1 << lane_index)) { 1014 switch (lane_index) { 1015 case DINO_PORT0: 1016 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP0_0f_GET(mode_sts1)) { 1017 config->data_rate = DINO_SPD_10G; 1018 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP0_0f_GET(mode_sts2)) { 1019 config->data_rate = DINO_SPD_1G; 1020 } 1021 break; 1022 case DINO_PORT1: 1023 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP0_1f_GET(mode_sts1)) { 1024 config->data_rate = DINO_SPD_10G; 1025 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP0_1f_GET(mode_sts2)) { 1026 config->data_rate = DINO_SPD_1G; 1027 } 1028 break; 1029 case DINO_PORT2: 1030 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP0_2f_GET(mode_sts1)) { 1031 config->data_rate = DINO_SPD_10G; 1032 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP0_2f_GET(mode_sts2)) { 1033 config->data_rate = DINO_SPD_1G; 1034 } 1035 break; 1036 case DINO_PORT3: 1037 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP0_3f_GET(mode_sts1)) { 1038 config->data_rate = DINO_SPD_10G; 1039 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP0_3f_GET(mode_sts2)) { 1040 config->data_rate = DINO_SPD_1G; 1041 } 1042 break; 1043 case DINO_PORT4: 1044 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP1_0f_GET(mode_sts1)) { 1045 config->data_rate = DINO_SPD_10G; 1046 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP1_0f_GET(mode_sts2)) { 1047 config->data_rate = DINO_SPD_1G; 1048 } 1049 break; 1050 case DINO_PORT5: 1051 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP1_1f_GET(mode_sts1)) { 1052 config->data_rate = DINO_SPD_10G; 1053 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP1_1f_GET(mode_sts2)) { 1054 config->data_rate = DINO_SPD_1G; 1055 } 1056 break; 1057 case DINO_PORT6: 1058 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP1_2f_GET(mode_sts1)) { 1059 config->data_rate = DINO_SPD_10G; 1060 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP1_2f_GET(mode_sts2)) { 1061 config->data_rate = DINO_SPD_1G; 1062 } 1063 break; 1064 case DINO_PORT7: 1065 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP1_3f_GET(mode_sts1)) { 1066 config->data_rate = DINO_SPD_10G; 1067 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP1_3f_GET(mode_sts2)) { 1068 config->data_rate = DINO_SPD_1G; 1069 } 1070 break; 1071 case DINO_PORT8: 1072 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP2_0f_GET(mode_sts1)) { 1073 config->data_rate = DINO_SPD_10G; 1074 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP2_0f_GET(mode_sts2)) { 1075 config->data_rate = DINO_SPD_1G; 1076 } 1077 break; 1078 case DINO_PORT9: 1079 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP2_1f_GET(mode_sts1)) { 1080 config->data_rate = DINO_SPD_10G; 1081 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP2_1f_GET(mode_sts2)) { 1082 config->data_rate = DINO_SPD_1G; 1083 } 1084 break; 1085 case DINO_PORT10: 1086 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP2_2f_GET(mode_sts1)) { 1087 config->data_rate = DINO_SPD_10G; 1088 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP2_2f_GET(mode_sts2)) { 1089 config->data_rate = DINO_SPD_1G; 1090 } 1091 break; 1092 case DINO_PORT11: 1093 if (BCMI_DINO_DECD_MODE_STS1r_DECODED_MODE_10G_MP2_3f_GET(mode_sts1)) { 1094 config->data_rate = DINO_SPD_10G; 1095 } else if (BCMI_DINO_DECD_MODE_STS2r_DECODED_MODE_1G_MP2_3f_GET(mode_sts2)) { 1096 config->data_rate = DINO_SPD_1G; 1097 } 1098 break; 1099 } 1100 } 1101 } 1102 } 1103 port_speed = config->data_rate; 1104 1105 /*Ethernet*/ 1106 config->interface_modes = 0; 1107 1108 PHYMOD_IF_ERR_RETURN( 1109 _dino_restore_phy_type(pa, config, &phy_type)); 1110 1111 /* Read the ref clock value from scratch register */ 1112 READ_DINO_PMA_PMD_REG(pa, DINO_REF_CLK_REG_ADR, sw_gpreg_data); 1113 config->ref_clock = ((sw_gpreg_data & DINO_REF_CLK_VAL_MASK) >> DINO_REF_CLK_VAL_SHIFT); 1114 1115 /* Read PLL value from register */ 1116 for (if_side = DINO_IF_LINE ; if_side <= DINO_IF_SYS ; if_side++) { 1117 for (lane = 0; lane < DINO_MAX_LANE ; lane += 4) { 1118 if (lane_mask & (0xf << lane)) { 1119 PHYMOD_IF_ERR_RETURN ( 1120 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1121 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 1122 /* Read the current pll mode program the pll only if the mode is not configured already */ 1123 PHYMOD_IF_ERR_RETURN( 1124 BCMI_DINO_READ_F25G_PLL_CAL_CTL7r(pa, &falcon_pll_ctrl)); 1125 falcon_pll_mode = BCMI_DINO_F25G_PLL_CAL_CTL7r_PLL_MODEf_GET(falcon_pll_ctrl); 1126 } else { 1127 /* Read current merlin PLL mode map val from scratch register*/ 1128 READ_DINO_PMA_PMD_REG(pa, DINO_MER_PLL_MAP_VAL_REG_ADR, reg_data); 1129 mer_pll_mapval = (reg_data & (0x3 << ((2*(lane/4)) + (8*if_side)))) >> ((2*(lane/4))+(8*if_side)); 1130 } 1131 PHYMOD_IF_ERR_RETURN ( 1132 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1133 break; 1134 } 1135 } 1136 } 1137 1138 for (lane_index = 0; lane_index <= DINO_MAX_LANE; lane_index ++) { 1139 if (lane_mask & (0xf << lane_index)) { 1140 if (phy_type == DINO_PHY_TYPE_HIGIG) { 1141 switch (config->ref_clock) { 1142 case phymodRefClk156Mhz: 1143 case phymodRefClk312Mhz: 1144 switch (port_speed) { 1145 case DINO_SPD_10G: 1146 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1147 if (falcon_pll_mode == DINO_PLL_MODE_140) { 1148 config->data_rate = DINO_SPD_11G; 1149 } else { 1150 config->data_rate = DINO_SPD_10G; 1151 } 1152 } else { 1153 if (mer_pll_mapval == 0x3) { 1154 config->data_rate = DINO_SPD_11G; 1155 } else { 1156 config->data_rate = DINO_SPD_10G; 1157 } 1158 } 1159 break; 1160 case DINO_SPD_40G: 1161 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1162 if (falcon_pll_mode == DINO_PLL_MODE_140) { 1163 config->data_rate = DINO_SPD_42G; 1164 } else { 1165 config->data_rate = DINO_SPD_40G; 1166 } 1167 } else { 1168 if (mer_pll_mapval == 0x3) { 1169 config->data_rate = DINO_SPD_42G; 1170 } else { 1171 config->data_rate = DINO_SPD_40G; 1172 } 1173 } 1174 break; 1175 case DINO_SPD_100G: 1176 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1177 if (falcon_pll_mode == DINO_PLL_MODE_175) { 1178 config->data_rate = DINO_SPD_106G; 1179 } else { 1180 config->data_rate = DINO_SPD_100G; 1181 } 1182 } else { 1183 if (mer_pll_mapval == 0x3) { 1184 config->data_rate = DINO_SPD_106G; 1185 } else { 1186 config->data_rate = DINO_SPD_100G; 1187 } 1188 } 1189 break; 1190 default: 1191 break; 1192 } 1193 break; 1194 default: 1195 break; 1196 } 1197 PHYMOD_INTF_MODES_HIGIG_SET(config); 1198 } else if (phy_type == DINO_PHY_TYPE_OTN) { 1199 switch (config->ref_clock) { 1200 case phymodRefClk174Mhz: 1201 case phymodRefClk349Mhz: 1202 case phymodRefClk698Mhz: 1203 switch (port_speed) { 1204 case DINO_SPD_10G: 1205 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1206 if (falcon_pll_mode == DINO_PLL_MODE_128) { 1207 config->data_rate = DINO_SPD_11P18G; 1208 } 1209 } else { 1210 if (mer_pll_mapval == 0x1) { 1211 config->data_rate = DINO_SPD_11P18G; 1212 } 1213 } 1214 break; 1215 case DINO_SPD_100G: 1216 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1217 if (falcon_pll_mode == DINO_PLL_MODE_160) { 1218 config->data_rate = DINO_SPD_111G; 1219 } 1220 } else { 1221 if (mer_pll_mapval == 0x1) { 1222 config->data_rate = DINO_SPD_111G; 1223 } 1224 } 1225 break; 1226 default: 1227 break; 1228 } 1229 break; 1230 default: 1231 break; 1232 } 1233 } else if (phy_type == DINO_PHY_TYPE_ETH) { 1234 switch (config->ref_clock) { 1235 case phymodRefClk156Mhz: 1236 case phymodRefClk312Mhz: 1237 switch (port_speed) { 1238 case DINO_SPD_10G: 1239 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1240 if (falcon_pll_mode == DINO_PLL_MODE_132) { 1241 config->data_rate = DINO_SPD_10G; 1242 } 1243 } else { 1244 if (mer_pll_mapval == 0x2) { 1245 config->data_rate = DINO_SPD_10G; 1246 } 1247 } 1248 break; 1249 case DINO_SPD_40G: 1250 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1251 if (falcon_pll_mode == DINO_PLL_MODE_132) { 1252 config->data_rate = DINO_SPD_40G; 1253 } 1254 } else { 1255 if (mer_pll_mapval == 0x2) { 1256 config->data_rate = DINO_SPD_40G; 1257 } 1258 } 1259 break; 1260 case DINO_SPD_100G: 1261 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1262 if (falcon_pll_mode == DINO_PLL_MODE_175) { 1263 config->data_rate = DINO_SPD_100G; 1264 } 1265 } else { 1266 if (mer_pll_mapval == 0x2) { 1267 config->data_rate = DINO_SPD_100G; 1268 } 1269 } 1270 break; 1271 default: 1272 break; 1273 } 1274 break; 1275 case phymodRefClk161Mhz: 1276 case phymodRefClk322Mhz: 1277 case phymodRefClk644Mhz: 1278 switch (port_speed) { 1279 case DINO_SPD_10G: 1280 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1281 if ((falcon_pll_mode == DINO_PLL_MODE_128) || 1282 ((config->ref_clock == phymodRefClk322Mhz) && 1283 (chip_id == DINO_CHIP_ID_82793) && 1284 (falcon_pll_mode == DINO_PLL_MODE_64))) { 1285 config->data_rate = DINO_SPD_10G; 1286 } 1287 } else { 1288 if (mer_pll_mapval == 0x1) { 1289 config->data_rate = DINO_SPD_10G; 1290 } 1291 } 1292 break; 1293 case DINO_SPD_40G: 1294 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1295 if ((falcon_pll_mode == DINO_PLL_MODE_128) || 1296 ((config->ref_clock == phymodRefClk322Mhz) && 1297 (chip_id == DINO_CHIP_ID_82793) && 1298 (falcon_pll_mode == DINO_PLL_MODE_64))) { 1299 config->data_rate = DINO_SPD_40G; 1300 } 1301 } else { 1302 if (mer_pll_mapval == 0x1) { 1303 config->data_rate = DINO_SPD_40G; 1304 } 1305 } 1306 break; 1307 case DINO_SPD_100G: 1308 if (DINO_IS_FALCON_SIDE(if_side, lane_index)) { 1309 if ((falcon_pll_mode == DINO_PLL_MODE_160) || 1310 ((config->ref_clock == phymodRefClk322Mhz) && 1311 (chip_id == DINO_CHIP_ID_82793) && 1312 (falcon_pll_mode == DINO_PLL_MODE_80))) { 1313 config->data_rate = DINO_SPD_100G; 1314 } 1315 } else { 1316 if (mer_pll_mapval == 0x1) { 1317 config->data_rate = DINO_SPD_100G; 1318 } 1319 } 1320 break; 1321 default: 1322 break; 1323 } 1324 break; 1325 default: 1326 break; 1327 } 1328 PHYMOD_INTF_MODES_HIGIG_CLR(config); 1329 PHYMOD_INTF_MODES_OTN_CLR(config); 1330 PHYMOD_INTF_MODES_FIBER_CLR(config); 1331 } 1332 break; 1333 } 1334 } 1335 PHYMOD_IF_ERR_RETURN( 1336 _dino_interface_get(phy, config, &intf)); 1337 config->interface_type = intf; 1338 1339 return PHYMOD_E_NONE; 1340 } 1341 1342 int _dino_configure_ref_clock(const phymod_access_t *pa, phymod_ref_clk_t ref_clk) 1343 { 1344 uint32_t rev = 0; 1345 uint32_t chip_id = 0; 1346 uint16_t sw_gpreg_data = 0; 1347 BCMI_DINO_CLK_SCALER_CTLr_t clk_ctrl; 1348 PHYMOD_MEMSET(&clk_ctrl, 0, sizeof(BCMI_DINO_CLK_SCALER_CTLr_t)); 1349 1350 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 1351 1352 switch (ref_clk) { 1353 case phymodRefClk156Mhz: 1354 case phymodRefClk312Mhz: 1355 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x320); 1356 break; 1357 case phymodRefClk161Mhz: 1358 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x340); 1359 break; 1360 case phymodRefClk322Mhz: 1361 if (chip_id == DINO_CHIP_ID_82793) { 1362 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x680); 1363 } else { 1364 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x340); 1365 } 1366 break; 1367 case phymodRefClk644Mhz: 1368 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x340); 1369 break; 1370 case phymodRefClk174Mhz: 1371 case phymodRefClk698Mhz: 1372 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x380); 1373 break; 1374 case phymodRefClk349Mhz: 1375 if (chip_id == DINO_CHIP_ID_82793) { 1376 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x700); 1377 } else { 1378 BCMI_DINO_CLK_SCALER_CTLr_CLOCK_SCALER_RATIOf_SET(clk_ctrl, 0x380); 1379 } 1380 break; 1381 default: 1382 return PHYMOD_E_PARAM; 1383 } 1384 PHYMOD_IF_ERR_RETURN( 1385 BCMI_DINO_WRITE_CLK_SCALER_CTLr(pa,clk_ctrl)); 1386 1387 /* Store the ref clock value in scratch register */ 1388 READ_DINO_PMA_PMD_REG(pa, DINO_REF_CLK_REG_ADR, sw_gpreg_data); 1389 sw_gpreg_data &= ~(DINO_REF_CLK_VAL_MASK); 1390 sw_gpreg_data |= (ref_clk << DINO_REF_CLK_VAL_SHIFT); 1391 WRITE_DINO_PMA_PMD_REG(pa, DINO_REF_CLK_REG_ADR, sw_gpreg_data); 1392 1393 return PHYMOD_E_NONE; 1394 } 1395 1396 /** Configure Dut Mode Register 1397 */ 1398 int _dino_config_dut_mode_reg(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config) 1399 { 1400 uint16_t no_of_ports = 0; 1401 uint16_t port_idx = 0; 1402 uint16_t lane_mask = 0; 1403 uint16_t if_side = 0; 1404 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 1405 uint16_t sw_gpreg_data = 0; 1406 uint32_t chip_id = 0; 1407 uint32_t rev = 0; 1408 BCMI_DINO_MODECTL0r_t mode_ctrl0; 1409 BCMI_DINO_MODECTL1r_t mode_ctrl1; 1410 BCMI_DINO_MODECTL2r_t mode_ctrl2; 1411 BCMI_DINO_MODECTL3r_t mode_ctrl3; 1412 phymod_phy_inf_config_t cfg; 1413 const phymod_access_t *pa = &phy->access; 1414 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_DINO_MODECTL0r_t)); 1415 PHYMOD_MEMSET(&mode_ctrl1, 0, sizeof(BCMI_DINO_MODECTL1r_t)); 1416 PHYMOD_MEMSET(&mode_ctrl2, 0, sizeof(BCMI_DINO_MODECTL2r_t)); 1417 PHYMOD_MEMSET(&mode_ctrl3, 0, sizeof(BCMI_DINO_MODECTL3r_t)); 1418 PHYMOD_MEMCPY(&cfg, config, sizeof(phymod_phy_inf_config_t)); 1419 1420 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1421 DINO_GET_INTF_SIDE(phy, if_side); 1422 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 1423 DINO_GET_PORT_FROM_MODE(config, chip_id, no_of_ports); 1424 1425 /* Store the device operation type into SW GPREG */ 1426 if (PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) { 1427 dev_op_mode = DINO_DEV_OP_MODE_GBOX; 1428 } else { 1429 dev_op_mode = DINO_DEV_OP_MODE_PT; 1430 } 1431 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 1432 sw_gpreg_data &= ~(DINO_DEV_OP_MODE_MASK); 1433 sw_gpreg_data |= (dev_op_mode << DINO_DEV_OP_MODE_SHIFT); 1434 WRITE_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 1435 1436 PHYMOD_IF_ERR_RETURN( 1437 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 1438 PHYMOD_IF_ERR_RETURN( 1439 BCMI_DINO_READ_MODECTL1r(pa, &mode_ctrl1)); 1440 PHYMOD_IF_ERR_RETURN( 1441 BCMI_DINO_READ_MODECTL2r(pa, &mode_ctrl2)); 1442 PHYMOD_IF_ERR_RETURN( 1443 BCMI_DINO_READ_MODECTL3r(pa, &mode_ctrl3)); 1444 1445 if ((config->data_rate != DINO_SPD_100G) && (config->data_rate != DINO_SPD_106G) && (config->data_rate != DINO_SPD_111G)) { 1446 /* To clear all 100G mode settings */ 1447 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1448 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1449 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1450 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1451 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1452 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1453 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 1454 /* Program Modes */ 1455 if (((config->data_rate == DINO_SPD_40G || config->data_rate == DINO_SPD_42G) && 1456 (lane_mask == DINO_40G_PORT0_LANE_MASK))) { 1457 BCMI_DINO_MODECTL1r_MODE_10G_MP0_0f_SET(mode_ctrl1, 0); 1458 BCMI_DINO_MODECTL1r_MODE_10G_MP0_1f_SET(mode_ctrl1, 0); 1459 BCMI_DINO_MODECTL1r_MODE_10G_MP0_2f_SET(mode_ctrl1, 0); 1460 BCMI_DINO_MODECTL1r_MODE_10G_MP0_3f_SET(mode_ctrl1, 0); 1461 BCMI_DINO_MODECTL2r_MODE_1G_MP0_0f_SET(mode_ctrl2, 0); 1462 BCMI_DINO_MODECTL2r_MODE_1G_MP0_1f_SET(mode_ctrl2, 0); 1463 BCMI_DINO_MODECTL2r_MODE_1G_MP0_2f_SET(mode_ctrl2, 0); 1464 BCMI_DINO_MODECTL2r_MODE_1G_MP0_3f_SET(mode_ctrl2, 0); 1465 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 1); 1466 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1467 } else if (((config->data_rate == DINO_SPD_40G || config->data_rate == DINO_SPD_42G) && 1468 (lane_mask == DINO_40G_PORT1_LANE_MASK))) { 1469 BCMI_DINO_MODECTL1r_MODE_10G_MP1_0f_SET(mode_ctrl1, 0); 1470 BCMI_DINO_MODECTL1r_MODE_10G_MP1_1f_SET(mode_ctrl1, 0); 1471 BCMI_DINO_MODECTL1r_MODE_10G_MP1_2f_SET(mode_ctrl1, 0); 1472 BCMI_DINO_MODECTL1r_MODE_10G_MP1_3f_SET(mode_ctrl1, 0); 1473 BCMI_DINO_MODECTL2r_MODE_1G_MP1_0f_SET(mode_ctrl2, 0); 1474 BCMI_DINO_MODECTL2r_MODE_1G_MP1_1f_SET(mode_ctrl2, 0); 1475 BCMI_DINO_MODECTL2r_MODE_1G_MP1_2f_SET(mode_ctrl2, 0); 1476 BCMI_DINO_MODECTL2r_MODE_1G_MP1_3f_SET(mode_ctrl2, 0); 1477 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 1); 1478 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1479 } else if (((config->data_rate == DINO_SPD_40G || config->data_rate == DINO_SPD_42G) && 1480 (lane_mask == DINO_40G_PORT2_LANE_MASK))) { 1481 BCMI_DINO_MODECTL1r_MODE_10G_MP2_0f_SET(mode_ctrl1, 0); 1482 BCMI_DINO_MODECTL1r_MODE_10G_MP2_1f_SET(mode_ctrl1, 0); 1483 BCMI_DINO_MODECTL1r_MODE_10G_MP2_2f_SET(mode_ctrl1, 0); 1484 BCMI_DINO_MODECTL1r_MODE_10G_MP2_3f_SET(mode_ctrl1, 0); 1485 BCMI_DINO_MODECTL2r_MODE_1G_MP2_0f_SET(mode_ctrl2, 0); 1486 BCMI_DINO_MODECTL2r_MODE_1G_MP2_1f_SET(mode_ctrl2, 0); 1487 BCMI_DINO_MODECTL2r_MODE_1G_MP2_2f_SET(mode_ctrl2, 0); 1488 BCMI_DINO_MODECTL2r_MODE_1G_MP2_3f_SET(mode_ctrl2, 0); 1489 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 1); 1490 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1491 } else if ((config->data_rate == DINO_SPD_10G) || (config->data_rate == DINO_SPD_11G) || (config->data_rate == DINO_SPD_11P18G)) { 1492 if ((lane_mask & (0x1 << port_idx))) { 1493 switch (port_idx) { 1494 case DINO_PORT0: 1495 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1496 BCMI_DINO_MODECTL2r_MODE_1G_MP0_0f_SET(mode_ctrl2, 0); 1497 BCMI_DINO_MODECTL1r_MODE_10G_MP0_0f_SET(mode_ctrl1, 1); 1498 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1499 break; 1500 case DINO_PORT1: 1501 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1502 BCMI_DINO_MODECTL2r_MODE_1G_MP0_1f_SET(mode_ctrl2, 0); 1503 BCMI_DINO_MODECTL1r_MODE_10G_MP0_1f_SET(mode_ctrl1, 1); 1504 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1505 break; 1506 case DINO_PORT2: 1507 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1508 BCMI_DINO_MODECTL2r_MODE_1G_MP0_2f_SET(mode_ctrl2, 0); 1509 BCMI_DINO_MODECTL1r_MODE_10G_MP0_2f_SET(mode_ctrl1, 1); 1510 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1511 break; 1512 case DINO_PORT3: 1513 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1514 BCMI_DINO_MODECTL2r_MODE_1G_MP0_3f_SET(mode_ctrl2, 0); 1515 BCMI_DINO_MODECTL1r_MODE_10G_MP0_3f_SET(mode_ctrl1, 1); 1516 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1517 break; 1518 case DINO_PORT4: 1519 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1520 BCMI_DINO_MODECTL2r_MODE_1G_MP1_0f_SET(mode_ctrl2, 0); 1521 BCMI_DINO_MODECTL1r_MODE_10G_MP1_0f_SET(mode_ctrl1, 1); 1522 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1523 break; 1524 case DINO_PORT5: 1525 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1526 BCMI_DINO_MODECTL2r_MODE_1G_MP1_1f_SET(mode_ctrl2, 0); 1527 BCMI_DINO_MODECTL1r_MODE_10G_MP1_1f_SET(mode_ctrl1, 1); 1528 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1529 break; 1530 case DINO_PORT6: 1531 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1532 BCMI_DINO_MODECTL2r_MODE_1G_MP1_2f_SET(mode_ctrl2, 0); 1533 BCMI_DINO_MODECTL1r_MODE_10G_MP1_2f_SET(mode_ctrl1, 1); 1534 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1535 break; 1536 case DINO_PORT7: 1537 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1538 BCMI_DINO_MODECTL2r_MODE_1G_MP1_3f_SET(mode_ctrl2, 0); 1539 BCMI_DINO_MODECTL1r_MODE_10G_MP1_3f_SET(mode_ctrl1, 1); 1540 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1541 break; 1542 case DINO_PORT8: 1543 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1544 BCMI_DINO_MODECTL2r_MODE_1G_MP2_0f_SET(mode_ctrl2, 0); 1545 BCMI_DINO_MODECTL1r_MODE_10G_MP2_0f_SET(mode_ctrl1, 1); 1546 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1547 break; 1548 case DINO_PORT9: 1549 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1550 BCMI_DINO_MODECTL2r_MODE_1G_MP2_1f_SET(mode_ctrl2, 0); 1551 BCMI_DINO_MODECTL1r_MODE_10G_MP2_1f_SET(mode_ctrl1, 1); 1552 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1553 break; 1554 case DINO_PORT10: 1555 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1556 BCMI_DINO_MODECTL2r_MODE_1G_MP2_2f_SET(mode_ctrl2, 0); 1557 BCMI_DINO_MODECTL1r_MODE_10G_MP2_2f_SET(mode_ctrl1, 1); 1558 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1559 break; 1560 case DINO_PORT11: 1561 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1562 BCMI_DINO_MODECTL2r_MODE_1G_MP2_3f_SET(mode_ctrl2, 0); 1563 BCMI_DINO_MODECTL1r_MODE_10G_MP2_3f_SET(mode_ctrl1, 1); 1564 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1565 break; 1566 } 1567 } 1568 } else if (config->data_rate == DINO_SPD_1G) { 1569 /* mode configuration for 1G */ 1570 if ((lane_mask & (0x1 << port_idx))) { 1571 switch (port_idx) { 1572 case DINO_PORT0: 1573 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1574 BCMI_DINO_MODECTL1r_MODE_10G_MP0_0f_SET(mode_ctrl1, 0); 1575 BCMI_DINO_MODECTL2r_MODE_1G_MP0_0f_SET(mode_ctrl2, 1); 1576 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1577 break; 1578 case DINO_PORT1: 1579 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1580 BCMI_DINO_MODECTL1r_MODE_10G_MP0_1f_SET(mode_ctrl1, 0); 1581 BCMI_DINO_MODECTL2r_MODE_1G_MP0_1f_SET(mode_ctrl2, 1); 1582 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1583 break; 1584 case DINO_PORT2: 1585 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1586 BCMI_DINO_MODECTL1r_MODE_10G_MP0_2f_SET(mode_ctrl1, 0); 1587 BCMI_DINO_MODECTL2r_MODE_1G_MP0_2f_SET(mode_ctrl2, 1); 1588 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1589 break; 1590 case DINO_PORT3: 1591 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1592 BCMI_DINO_MODECTL1r_MODE_10G_MP0_3f_SET(mode_ctrl1, 0); 1593 BCMI_DINO_MODECTL2r_MODE_1G_MP0_3f_SET(mode_ctrl2, 1); 1594 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1595 break; 1596 case DINO_PORT4: 1597 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1598 BCMI_DINO_MODECTL1r_MODE_10G_MP1_0f_SET(mode_ctrl1, 0); 1599 BCMI_DINO_MODECTL2r_MODE_1G_MP1_0f_SET(mode_ctrl2, 1); 1600 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1601 break; 1602 case DINO_PORT5: 1603 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1604 BCMI_DINO_MODECTL1r_MODE_10G_MP1_1f_SET(mode_ctrl1, 0); 1605 BCMI_DINO_MODECTL2r_MODE_1G_MP1_1f_SET(mode_ctrl2, 1); 1606 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1607 break; 1608 case DINO_PORT6: 1609 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1610 BCMI_DINO_MODECTL1r_MODE_10G_MP1_2f_SET(mode_ctrl1, 0); 1611 BCMI_DINO_MODECTL2r_MODE_1G_MP1_2f_SET(mode_ctrl2, 1); 1612 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1613 break; 1614 case DINO_PORT7: 1615 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1616 BCMI_DINO_MODECTL1r_MODE_10G_MP1_3f_SET(mode_ctrl1, 0); 1617 BCMI_DINO_MODECTL2r_MODE_1G_MP1_3f_SET(mode_ctrl2, 1); 1618 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 1619 break; 1620 case DINO_PORT8: 1621 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1622 BCMI_DINO_MODECTL1r_MODE_10G_MP2_0f_SET(mode_ctrl1, 0); 1623 BCMI_DINO_MODECTL2r_MODE_1G_MP2_0f_SET(mode_ctrl2, 1); 1624 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1625 break; 1626 case DINO_PORT9: 1627 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1628 BCMI_DINO_MODECTL1r_MODE_10G_MP2_1f_SET(mode_ctrl1, 0); 1629 BCMI_DINO_MODECTL2r_MODE_1G_MP2_1f_SET(mode_ctrl2, 1); 1630 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1631 break; 1632 case DINO_PORT10: 1633 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1634 BCMI_DINO_MODECTL1r_MODE_10G_MP2_2f_SET(mode_ctrl1, 0); 1635 BCMI_DINO_MODECTL2r_MODE_1G_MP2_2f_SET(mode_ctrl2, 1); 1636 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1637 break; 1638 case DINO_PORT11: 1639 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1640 BCMI_DINO_MODECTL1r_MODE_10G_MP2_3f_SET(mode_ctrl1, 0); 1641 BCMI_DINO_MODECTL2r_MODE_1G_MP2_3f_SET(mode_ctrl2, 1); 1642 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 1643 break; 1644 } 1645 } 1646 } else { 1647 /* Throw error as un supported mode */ 1648 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("Unsupported mode"))); 1649 } 1650 } 1651 } else { 1652 BCMI_DINO_MODECTL1r_CLR(mode_ctrl1); 1653 BCMI_DINO_MODECTL2r_CLR(mode_ctrl2); 1654 BCMI_DINO_MODECTL3r_CLR(mode_ctrl3); 1655 BCMI_DINO_MODECTL0r_MODE_40G_MP0f_SET(mode_ctrl0, 0); 1656 BCMI_DINO_MODECTL0r_MODE_40G_MP1f_SET(mode_ctrl0, 0); 1657 BCMI_DINO_MODECTL0r_MODE_40G_MP2f_SET(mode_ctrl0, 0); 1658 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 1659 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 0); 1660 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 0); 1661 if (PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) { /* 100G GBOX mode */ 1662 if (config->interface_modes & PHYMOD_INTF_MODES_TRIPLE_CORE) { 1663 if (if_side == DINO_IF_SYS) { 1664 if (config->interface_modes & PHYMOD_INTF_MODES_TC_442) { /*Dino system lanes 0-9*/ 1665 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 1); 1666 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1667 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1668 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1669 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1670 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1671 } else if (config->interface_modes & PHYMOD_INTF_MODES_TC_343) { /*Dino system lanes 1-10*/ 1672 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1673 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 1); 1674 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1675 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1676 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1677 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1678 } else if (config->interface_modes & PHYMOD_INTF_MODES_TC_244) { /*Dino system lanes 2-11*/ 1679 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1680 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1681 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 1); 1682 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1683 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1684 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1685 } else { 1686 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 1); 1687 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1688 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1689 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1690 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1691 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1692 } 1693 } else { 1694 if (config->interface_modes & PHYMOD_INTF_MODES_TC_442) { /*Dino system lanes 0-9*/ 1695 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 1); 1696 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1697 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1698 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1699 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1700 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1701 } else if (config->interface_modes & PHYMOD_INTF_MODES_TC_343) { /*Dino system lanes 1-10*/ 1702 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1703 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 1); 1704 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1705 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1706 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1707 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1708 } else if (config->interface_modes & PHYMOD_INTF_MODES_TC_244) { /*Dino system lanes 2-11*/ 1709 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1710 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1711 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 1); 1712 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1713 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1714 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1715 } 1716 if ((!(BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_GET(mode_ctrl0)) && 1717 !(BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_GET(mode_ctrl0)) && 1718 !(BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_GET(mode_ctrl0)))) { 1719 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 1); 1720 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1721 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1722 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1723 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1724 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1725 } 1726 } 1727 } else { 1728 PHYMOD_DEBUG_VERBOSE(("interface mode PHYMOD_INTF_MODES_TRIPLE_CORE is not set\n")); 1729 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 1); 1730 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1731 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1732 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1733 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1734 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1735 } 1736 } else { /* 100G PT mode */ 1737 if (config->interface_modes & PHYMOD_INTF_MODES_TC_442) { /*Dino system lanes 0-9*/ 1738 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 1); 1739 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1740 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1741 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1742 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1743 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1744 } else if (config->interface_modes & PHYMOD_INTF_MODES_TC_343) { /*Dino system lanes 1-10*/ 1745 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1746 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 1); 1747 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1748 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1749 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1750 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1751 } else if (config->interface_modes & PHYMOD_INTF_MODES_TC_244) { /*Dino system lanes 2-11*/ 1752 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 0); 1753 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1754 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 1); 1755 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1756 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1757 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1758 } else { 1759 BCMI_DINO_MODECTL0r_MODE_100G_PT_0TO9f_SET(mode_ctrl0, 1); 1760 BCMI_DINO_MODECTL0r_MODE_100G_PT_1TO10f_SET(mode_ctrl0, 0); 1761 BCMI_DINO_MODECTL0r_MODE_100G_PT_2TO11f_SET(mode_ctrl0, 0); 1762 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_0TO9f_SET(mode_ctrl0, 0); 1763 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_1TO10f_SET(mode_ctrl0, 0); 1764 BCMI_DINO_MODECTL0r_MODE_100G_GBOX_2TO11f_SET(mode_ctrl0, 0); 1765 } 1766 } 1767 } 1768 PHYMOD_IF_ERR_RETURN( 1769 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 1770 PHYMOD_IF_ERR_RETURN( 1771 BCMI_DINO_WRITE_MODECTL1r(pa, mode_ctrl1)); 1772 PHYMOD_IF_ERR_RETURN( 1773 BCMI_DINO_WRITE_MODECTL2r(pa, mode_ctrl2)); 1774 PHYMOD_IF_ERR_RETURN( 1775 BCMI_DINO_WRITE_MODECTL3r(pa, mode_ctrl3)); 1776 1777 return PHYMOD_E_NONE; 1778 } 1779 1780 int _dino_config_pll_div(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t *config) 1781 { 1782 uint16_t if_side = 0; 1783 uint16_t merlin_pll_mode = 0; 1784 uint16_t falcon_pll_mode = 0; 1785 uint16_t data = 0; 1786 uint16_t reg_data = 0; 1787 uint16_t lane_mask = 0; 1788 uint16_t lane = 0; 1789 uint16_t mer_pll_mapval = 0; 1790 int mer_curr_pll_mapval = 0; 1791 uint16_t retry_cnt = DINO_FW_DLOAD_RETRY_CNT; 1792 uint8_t falcon_curr_pll_mode = 0; 1793 phymod_phy_access_t phy_copy; 1794 phymod_ref_clk_t ref_clk = config->ref_clock; 1795 BCMI_DINO_SLICEr_t slice_reg; 1796 BCMI_DINO_RST_CTL_CORE_DPr_t rst_ctl_core_dp; 1797 BCMI_DINO_PLL_CTL3r_t pll_ctl3; 1798 BCMI_DINO_PLL_CTL8r_t pll_ctl8; 1799 BCMI_DINO_F25G_PLL_CAL_CTL_STS0r_t falcon_pll_sts; 1800 BCMI_DINO_PLL_CALSTS0r_t merlin_pll_sts; 1801 BCMI_DINO_F25G_PLL_CAL_CTL7r_t falcon_pll_ctrl; 1802 phymod_access_t *pa = (phymod_access_t*)&phy->access; 1803 PHYMOD_MEMSET(&slice_reg, 0, sizeof(BCMI_DINO_SLICEr_t)); 1804 PHYMOD_MEMSET(&rst_ctl_core_dp, 0, sizeof(BCMI_DINO_RST_CTL_CORE_DPr_t)); 1805 PHYMOD_MEMSET(&pll_ctl3, 0, sizeof(BCMI_DINO_PLL_CTL3r_t)); 1806 PHYMOD_MEMSET(&pll_ctl8, 0, sizeof(BCMI_DINO_PLL_CTL8r_t)); 1807 PHYMOD_MEMSET(&falcon_pll_ctrl, 0, sizeof(BCMI_DINO_F25G_PLL_CAL_CTL7r_t)); 1808 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 1809 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 1810 1811 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 1812 1813 if ((config->data_rate == DINO_SPD_100G) || 1814 (config->data_rate == DINO_SPD_106G) || 1815 (config->data_rate == DINO_SPD_111G)) { 1816 lane_mask = DINO_100G_TYPE1_LANE_MASK; 1817 } 1818 1819 /* Set pll_mode */ 1820 PHYMOD_IF_ERR_RETURN( 1821 _dino_get_pll_modes(phy, ref_clk, config, &falcon_pll_mode, &merlin_pll_mode)); 1822 for (if_side = DINO_IF_LINE ; if_side <= DINO_IF_SYS ; if_side++) { 1823 for (lane = 0; lane < DINO_MAX_LANE ; lane += 4) { 1824 if (lane_mask & (0xf << lane)) { 1825 PHYMOD_IF_ERR_RETURN ( 1826 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 1827 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 1828 /* Read the current pll mode program the pll only if the mode is not configured already */ 1829 PHYMOD_IF_ERR_RETURN( 1830 BCMI_DINO_READ_F25G_PLL_CAL_CTL7r(pa, &falcon_pll_ctrl)); 1831 falcon_curr_pll_mode = BCMI_DINO_F25G_PLL_CAL_CTL7r_PLL_MODEf_GET(falcon_pll_ctrl); 1832 if (falcon_curr_pll_mode == falcon_pll_mode) { 1833 continue; 1834 } 1835 /* 0xd11b . enable pll . Added macro in .h file */ 1836 PHYMOD_IF_ERR_RETURN( 1837 falcon2_dino_wrc_ams_pll_pwrdn(0)); 1838 /* write 0 to core_dp_s_rstb while pll config . Added macro in .h file*/ 1839 /* 0xd184 .wrc_falcon2_dino_core_dp_s_rstb(0); */ 1840 PHYMOD_IF_ERR_RETURN( 1841 falcon2_dino_wrc_core_dp_s_rstb(0)); 1842 1843 /* Set PLL div */ 1844 switch (falcon_pll_mode) { 1845 case DINO_PLL_MODE_64: 1846 PHYMOD_IF_ERR_RETURN ( 1847 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_64x_refc322)); 1848 break; 1849 case DINO_PLL_MODE_80: 1850 if (config->ref_clock == phymodRefClk322Mhz) { 1851 PHYMOD_IF_ERR_RETURN ( 1852 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_80x_refc322)); 1853 } else { 1854 PHYMOD_IF_ERR_RETURN ( 1855 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_80x)); 1856 } 1857 break; 1858 case DINO_PLL_MODE_160: 1859 if (config->data_rate == DINO_SPD_111G) { 1860 PHYMOD_IF_ERR_RETURN ( 1861 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_160x_refc174)); 1862 } else { 1863 PHYMOD_IF_ERR_RETURN ( 1864 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_160x)); 1865 } 1866 break; 1867 case DINO_PLL_MODE_132: 1868 PHYMOD_IF_ERR_RETURN ( 1869 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_132x)); 1870 break; 1871 case DINO_PLL_MODE_128: 1872 PHYMOD_IF_ERR_RETURN ( 1873 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_128x)); 1874 break; 1875 case DINO_PLL_MODE_140: 1876 PHYMOD_IF_ERR_RETURN ( 1877 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_140x)); 1878 break; 1879 case DINO_PLL_MODE_165: 1880 PHYMOD_IF_ERR_RETURN ( 1881 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_165x)); 1882 break; 1883 case DINO_PLL_MODE_168: 1884 PHYMOD_IF_ERR_RETURN ( 1885 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_168x)); 1886 break; 1887 case DINO_PLL_MODE_175: 1888 PHYMOD_IF_ERR_RETURN ( 1889 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_175x)); 1890 break; 1891 case DINO_PLL_MODE_180: 1892 PHYMOD_IF_ERR_RETURN ( 1893 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_180x)); 1894 break; 1895 case DINO_PLL_MODE_184: 1896 PHYMOD_IF_ERR_RETURN ( 1897 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_184x)); 1898 break; 1899 case DINO_PLL_MODE_200: 1900 PHYMOD_IF_ERR_RETURN ( 1901 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_200x)); 1902 break; 1903 case DINO_PLL_MODE_224: 1904 PHYMOD_IF_ERR_RETURN ( 1905 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_224x)); 1906 break; 1907 case DINO_PLL_MODE_264: 1908 PHYMOD_IF_ERR_RETURN ( 1909 falcon2_dino_configure_pll(pa, FALCON2_DINO_pll_div_264x)); 1910 break; 1911 default: 1912 return PHYMOD_E_PARAM; 1913 } 1914 /* write 1 to release core_dp_s_rstb after pll config*/ 1915 PHYMOD_IF_ERR_RETURN ( 1916 falcon2_dino_wrc_core_dp_s_rstb(1)); 1917 retry_cnt = DINO_FW_DLOAD_RETRY_CNT; 1918 /* Check for the PLL lock */ 1919 do { 1920 PHYMOD_IF_ERR_RETURN( 1921 BCMI_DINO_READ_F25G_PLL_CAL_CTL_STS0r(pa, &falcon_pll_sts)); 1922 data = BCMI_DINO_F25G_PLL_CAL_CTL_STS0r_PLL_LOCKf_GET(falcon_pll_sts); 1923 PHYMOD_USLEEP(100); 1924 } while((data != 1) && (retry_cnt--)); 1925 if (retry_cnt == 0) { 1926 PHYMOD_DEBUG_ERROR(("PLL LOCK failed for pll\n")); 1927 return PHYMOD_E_FAIL; 1928 } 1929 } else { 1930 /* Read current merlin PLL mode map val from scratch register*/ 1931 READ_DINO_PMA_PMD_REG(pa, DINO_MER_PLL_MAP_VAL_REG_ADR, reg_data); 1932 mer_curr_pll_mapval = (reg_data & (0x3 << ((2*(lane/4)) + (8*if_side)))) >> ((2*(lane/4))+(8*if_side)); 1933 mer_pll_mapval = _dino_map_mer_pll_div(merlin_pll_mode); 1934 if (mer_pll_mapval == mer_curr_pll_mapval) { 1935 continue; 1936 } 1937 /* write 0 to core_dp_s_rstb while pll config*/ 1938 PHYMOD_IF_ERR_RETURN( 1939 wrc_core_dp_s_rstb(0)); 1940 switch (mer_pll_mapval) { 1941 case 0x1: 1942 if ((config->data_rate == DINO_SPD_111G) || 1943 (config->data_rate == DINO_SPD_11P18G)) { 1944 PHYMOD_IF_ERR_RETURN( 1945 merlin_dino_configure_pll(pa, MERLIN_DINO_pll_11p181GHz_174p703MHz)); 1946 } else { 1947 PHYMOD_IF_ERR_RETURN( 1948 merlin_dino_configure_pll(pa, MERLIN_DINO_pll_10p3125GHz_161p132MHz)); 1949 } 1950 break; 1951 case 0x2: 1952 PHYMOD_IF_ERR_RETURN( 1953 merlin_dino_configure_pll(pa, MERLIN_DINO_pll_10p3125GHz_156p25MHz)); 1954 break; 1955 case 0x3: 1956 PHYMOD_IF_ERR_RETURN( 1957 merlin_dino_configure_pll(pa, MERLIN_DINO_pll_10p9375GHz_156p25MHz)); 1958 break; 1959 default: 1960 return PHYMOD_E_PARAM; 1961 } 1962 /* write 1 to core_dp_s_rstb after pll config*/ 1963 PHYMOD_IF_ERR_RETURN( 1964 wrc_core_dp_s_rstb(1)); 1965 1966 retry_cnt = DINO_FW_DLOAD_RETRY_CNT; 1967 do { 1968 PHYMOD_IF_ERR_RETURN( 1969 BCMI_DINO_READ_PLL_CALSTS0r(pa, &merlin_pll_sts)); 1970 data = BCMI_DINO_PLL_CALSTS0r_PLL_LOCKf_GET(merlin_pll_sts); 1971 PHYMOD_USLEEP(100); 1972 } while((data != 1) && (retry_cnt--)); 1973 if (retry_cnt == 0) { 1974 PHYMOD_DEBUG_ERROR(("PLL LOCK failed for pll\n")); 1975 return PHYMOD_E_FAIL; 1976 } 1977 /* store merlin pll map value into sctratch reg */ 1978 reg_data &= ~(0x3 << ((2*(lane/4))+(8*if_side))); 1979 reg_data |= (mer_pll_mapval << ((2*(lane/4))+(8*if_side))); 1980 WRITE_DINO_PMA_PMD_REG(pa, DINO_MER_PLL_MAP_VAL_REG_ADR, reg_data); 1981 } 1982 } 1983 } 1984 } 1985 PHYMOD_IF_ERR_RETURN ( 1986 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 1987 1988 return PHYMOD_E_NONE; 1989 } 1990 1991 int _dino_restore_phy_type(const phymod_access_t *pa, phymod_phy_inf_config_t* config, uint16_t *phy_type) { 1992 uint16_t sw_gpreg_data = 0; 1993 uint16_t port_idx = 0; 1994 uint16_t no_of_ports = 0; 1995 uint16_t lane_mask = 0; 1996 uint32_t chip_id = 0; 1997 uint32_t rev = 0; 1998 *phy_type = DINO_PHY_TYPE_INVALID; 1999 2000 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 2001 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 2002 DINO_GET_PORT_FROM_MODE(config, chip_id, no_of_ports); 2003 2004 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 2005 if (config->data_rate == DINO_SPD_100G || config->data_rate == DINO_SPD_106G || config->data_rate == DINO_SPD_111G) { 2006 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 2007 break; 2008 } else if (config->data_rate == DINO_SPD_40G || config->data_rate == DINO_SPD_42G) { 2009 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 2010 READ_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), sw_gpreg_data); 2011 break; 2012 } else { 2013 continue; 2014 } 2015 } else if (config->data_rate == DINO_SPD_10G || config->data_rate == DINO_SPD_11G || config->data_rate == DINO_SPD_11P18G || config->data_rate == DINO_SPD_1G) { 2016 if ((lane_mask & (0x1 << port_idx))) { 2017 READ_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + port_idx), sw_gpreg_data); 2018 break; 2019 } else { 2020 continue; 2021 } 2022 } else { 2023 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("Unsupported mode"))); 2024 } 2025 } 2026 2027 *phy_type = ((sw_gpreg_data & DINO_PHY_TYPE_MASK) >> DINO_PHY_TYPE_SHIFT); 2028 2029 return PHYMOD_E_NONE; 2030 } 2031 int _dino_save_phy_type(const phymod_access_t *pa, 2032 const phymod_phy_inf_config_t *config) 2033 { 2034 uint16_t lane_idx = 0; 2035 uint16_t sw_gpreg_data = 0; 2036 uint16_t lane_mask = 0; 2037 uint16_t phy_type = DINO_PHY_TYPE_INVALID; 2038 2039 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 2040 2041 if (PHYMOD_INTF_MODES_HIGIG_GET(config)) { 2042 phy_type = DINO_PHY_TYPE_HIGIG; 2043 } else if ((config->data_rate == DINO_SPD_111G) || 2044 (config->data_rate == DINO_SPD_11P18G)) { 2045 phy_type = DINO_PHY_TYPE_OTN; 2046 } else { 2047 phy_type = DINO_PHY_TYPE_ETH; 2048 } 2049 2050 if ((config->data_rate == DINO_SPD_100G) || 2051 (config->data_rate == DINO_SPD_106G) || 2052 (config->data_rate == DINO_SPD_111G)) { 2053 lane_mask = 0x1; 2054 } 2055 2056 for (lane_idx = 0; lane_idx < DINO_MAX_LANE; lane_idx++) { 2057 if (lane_mask & (1 << lane_idx)) { 2058 READ_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + lane_idx), sw_gpreg_data); 2059 sw_gpreg_data &= ~(DINO_PHY_TYPE_MASK); 2060 sw_gpreg_data |= (phy_type << DINO_PHY_TYPE_SHIFT); 2061 WRITE_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + lane_idx), sw_gpreg_data); 2062 } 2063 } 2064 2065 return PHYMOD_E_NONE; 2066 } 2067 int _dino_restore_interface(phymod_phy_access_t *phy, 2068 phymod_phy_inf_config_t *config, 2069 phymod_interface_t *intf) { 2070 uint16_t if_side = 0; 2071 uint16_t sw_gpreg_data = 0; 2072 uint16_t port_idx = 0; 2073 uint16_t no_of_ports = 0; 2074 const phymod_access_t *pa = &phy->access; 2075 uint16_t lane_mask = 0; 2076 uint16_t interface_type = DINO_INTF_TYPE_SR; 2077 uint32_t chip_id = 0; 2078 uint32_t rev = 0; 2079 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 2080 uint16_t gpreg_data = 0; 2081 2082 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 2083 DINO_GET_INTF_SIDE(phy, if_side); 2084 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 2085 DINO_GET_PORT_FROM_MODE(config, chip_id, no_of_ports); 2086 2087 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 2088 if (config->data_rate == DINO_SPD_100G || config->data_rate == DINO_SPD_106G || config->data_rate == DINO_SPD_111G) { 2089 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 2090 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 2091 break; 2092 } else if (config->data_rate == DINO_SPD_40G || config->data_rate == DINO_SPD_42G) { 2093 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 2094 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 2095 READ_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), sw_gpreg_data); 2096 break; 2097 } else { 2098 continue; 2099 } 2100 } else if (config->data_rate == DINO_SPD_10G || config->data_rate == DINO_SPD_11G || config->data_rate == DINO_SPD_11P18G || config->data_rate == DINO_SPD_1G) { 2101 if ((lane_mask & (0x1 << port_idx))) { 2102 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 2103 READ_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + port_idx), sw_gpreg_data); 2104 break; 2105 } else { 2106 continue; 2107 } 2108 } 2109 } 2110 2111 if (if_side == DINO_IF_LINE) { 2112 interface_type = ((sw_gpreg_data & DINO_LINE_INTF_MASK) >> DINO_LINE_INTF_SHIFT); 2113 media_type = ((gpreg_data & DINO_LINE_MEDIA_TYPE_MASK) >> DINO_LINE_MEDIA_TYPE_SHIFT); 2114 } else { 2115 interface_type = ((sw_gpreg_data & DINO_SYS_INTF_MASK) >> DINO_SYS_INTF_SHIFT); 2116 media_type = ((gpreg_data & DINO_SYS_MEDIA_TYPE_MASK) >> DINO_SYS_MEDIA_TYPE_SHIFT); 2117 } 2118 2119 if (media_type == SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS) { 2120 PHYMOD_INTF_MODES_UNRELIABLE_LOS_SET(config); 2121 } else { 2122 PHYMOD_INTF_MODES_UNRELIABLE_LOS_CLR(config); 2123 } 2124 2125 switch (interface_type) { 2126 case DINO_INTF_TYPE_SR: 2127 if (config->data_rate == DINO_SPD_1G || 2128 config->data_rate == DINO_SPD_10G || 2129 config->data_rate == DINO_SPD_11G || 2130 config->data_rate == DINO_SPD_11P18G) { 2131 *intf = phymodInterfaceSR; 2132 } else if (config->data_rate == DINO_SPD_40G || 2133 config->data_rate == DINO_SPD_42G) { 2134 *intf = phymodInterfaceSR4; 2135 } else if (config->data_rate == DINO_SPD_100G || 2136 config->data_rate == DINO_SPD_106G || 2137 config->data_rate == DINO_SPD_111G) { 2138 if ((PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) && 2139 (if_side == DINO_IF_LINE)) { 2140 *intf = phymodInterfaceSR4; 2141 } else { 2142 *intf = phymodInterfaceSR10; 2143 } 2144 } 2145 break; 2146 case DINO_INTF_TYPE_LR: 2147 if (config->data_rate == DINO_SPD_1G || 2148 config->data_rate == DINO_SPD_10G || 2149 config->data_rate == DINO_SPD_11G || 2150 config->data_rate == DINO_SPD_11P18G) { 2151 *intf = phymodInterfaceLR; 2152 } else if (config->data_rate == DINO_SPD_40G || 2153 config->data_rate == DINO_SPD_42G) { 2154 *intf = phymodInterfaceLR4; 2155 } else if (config->data_rate == DINO_SPD_100G || 2156 config->data_rate == DINO_SPD_106G || 2157 config->data_rate == DINO_SPD_111G) { 2158 if ((PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) && 2159 (if_side == DINO_IF_LINE)) { 2160 *intf = phymodInterfaceLR4; 2161 } else { 2162 *intf = phymodInterfaceLR10; 2163 } 2164 } 2165 break; 2166 case DINO_INTF_TYPE_ER: 2167 if (config->data_rate == DINO_SPD_1G || 2168 config->data_rate == DINO_SPD_10G || 2169 config->data_rate == DINO_SPD_11G || 2170 config->data_rate == DINO_SPD_11P18G) { 2171 *intf = phymodInterfaceER; 2172 } else if (config->data_rate == DINO_SPD_40G || 2173 config->data_rate == DINO_SPD_42G) { 2174 *intf = phymodInterfaceER4; 2175 } else if (config->data_rate == DINO_SPD_100G || 2176 config->data_rate == DINO_SPD_106G || 2177 config->data_rate == DINO_SPD_111G) { 2178 if ((PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) && 2179 (if_side == DINO_IF_LINE)) { 2180 *intf = phymodInterfaceER4; 2181 } else { 2182 /* *intf = phymodInterfaceER10; */ 2183 } 2184 } 2185 break; 2186 case DINO_INTF_TYPE_CAUI4: 2187 *intf = phymodInterfaceCAUI4; 2188 break; 2189 case DINO_INTF_TYPE_CAUI: 2190 *intf = phymodInterfaceCAUI; 2191 break; 2192 case DINO_INTF_TYPE_CAUI4_C2C: 2193 *intf = phymodInterfaceCAUI4_C2C; 2194 break; 2195 case DINO_INTF_TYPE_CAUI4_C2M: 2196 *intf = phymodInterfaceCAUI4_C2M; 2197 break; 2198 case DINO_INTF_TYPE_XLAUI: 2199 *intf = phymodInterfaceXLAUI; 2200 break; 2201 case DINO_INTF_TYPE_XFI: 2202 *intf = phymodInterfaceXFI; 2203 break; 2204 case DINO_INTF_TYPE_KR: 2205 if (config->data_rate == DINO_SPD_1G || 2206 config->data_rate == DINO_SPD_10G || 2207 config->data_rate == DINO_SPD_11G || 2208 config->data_rate == DINO_SPD_11P18G) { 2209 *intf = phymodInterfaceKR; 2210 } else if (config->data_rate == DINO_SPD_40G || 2211 config->data_rate == DINO_SPD_42G) { 2212 *intf = phymodInterfaceKR4; 2213 } else if (config->data_rate == DINO_SPD_100G || 2214 config->data_rate == DINO_SPD_106G || 2215 config->data_rate == DINO_SPD_111G) { 2216 if ((PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) && 2217 (if_side == DINO_IF_LINE)) { 2218 *intf = phymodInterfaceKR4; 2219 } else { 2220 *intf = phymodInterfaceKR10; 2221 } 2222 } 2223 break; 2224 case DINO_INTF_TYPE_KX: 2225 if (config->data_rate == DINO_SPD_1G) { 2226 *intf = phymodInterfaceKX; 2227 } 2228 break; 2229 case DINO_INTF_TYPE_SFI: 2230 *intf = phymodInterfaceSFI; 2231 break; 2232 case DINO_INTF_TYPE_XLPPI: 2233 *intf = phymodInterfaceXLPPI; 2234 break; 2235 case DINO_INTF_TYPE_CX: 2236 *intf = phymodInterfaceCX; 2237 break; 2238 case DINO_INTF_TYPE_CR: 2239 if (config->data_rate == DINO_SPD_1G || 2240 config->data_rate == DINO_SPD_10G || 2241 config->data_rate == DINO_SPD_11G || 2242 config->data_rate == DINO_SPD_11P18G) { 2243 *intf = phymodInterfaceCR; 2244 } else if (config->data_rate == DINO_SPD_40G || 2245 config->data_rate == DINO_SPD_42G) { 2246 *intf = phymodInterfaceCR4; 2247 } else if (config->data_rate == DINO_SPD_100G || 2248 config->data_rate == DINO_SPD_106G || 2249 config->data_rate == DINO_SPD_111G) { 2250 if ((PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) && 2251 (if_side == DINO_IF_LINE)) { 2252 *intf = phymodInterfaceCR4; 2253 } else { 2254 *intf = phymodInterfaceCR10; 2255 } 2256 } 2257 break; 2258 case DINO_INTF_TYPE_VSR: 2259 *intf = phymodInterfaceVSR; 2260 break; 2261 case DINO_INTF_TYPE_OTN: 2262 *intf = phymodInterfaceOTN; 2263 break; 2264 case DINO_INTF_TYPE_SGMII: 2265 if (config->data_rate == DINO_SPD_1G) { 2266 *intf = phymodInterfaceSGMII; 2267 } 2268 break; 2269 default: 2270 break; 2271 } 2272 return PHYMOD_E_NONE; 2273 } 2274 int _dino_save_interface(const phymod_phy_access_t *phy, 2275 const phymod_phy_inf_config_t* config, 2276 phymod_interface_t intf) 2277 { 2278 uint16_t lane_idx = 0; 2279 uint16_t if_side = 0; 2280 uint16_t sw_gpreg_data = 0; 2281 const phymod_access_t *pa = &phy->access; 2282 uint16_t lane_mask = 0; 2283 uint16_t interface_type = DINO_INTF_TYPE_SR; 2284 2285 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 2286 DINO_GET_INTF_SIDE(phy, if_side); 2287 2288 switch (intf) { 2289 case phymodInterfaceSR: 2290 case phymodInterfaceSR4: 2291 case phymodInterfaceSR10: 2292 interface_type = DINO_INTF_TYPE_SR; 2293 break; 2294 case phymodInterfaceLR: 2295 case phymodInterfaceLR4: 2296 case phymodInterfaceLR10: 2297 interface_type = DINO_INTF_TYPE_LR; 2298 break; 2299 case phymodInterfaceER: 2300 case phymodInterfaceER4: 2301 /* case phymodInterfaceER10: */ 2302 interface_type = DINO_INTF_TYPE_ER; 2303 break; 2304 case phymodInterfaceCAUI4: 2305 interface_type = DINO_INTF_TYPE_CAUI4; 2306 break; 2307 case phymodInterfaceCAUI: 2308 interface_type = DINO_INTF_TYPE_CAUI; 2309 break; 2310 case phymodInterfaceCAUI4_C2C: 2311 interface_type = DINO_INTF_TYPE_CAUI4_C2C; 2312 break; 2313 case phymodInterfaceCAUI4_C2M: 2314 interface_type = DINO_INTF_TYPE_CAUI4_C2M; 2315 break; 2316 case phymodInterfaceXLAUI: 2317 interface_type = DINO_INTF_TYPE_XLAUI; 2318 break; 2319 case phymodInterfaceXFI: 2320 interface_type = DINO_INTF_TYPE_XFI; 2321 break; 2322 case phymodInterfaceKX: 2323 interface_type = DINO_INTF_TYPE_KX; 2324 break; 2325 case phymodInterfaceKR: 2326 case phymodInterfaceKR10: 2327 case phymodInterfaceKR4: 2328 interface_type = DINO_INTF_TYPE_KR; 2329 break; 2330 case phymodInterfaceSFI: 2331 interface_type = DINO_INTF_TYPE_SFI; 2332 break; 2333 case phymodInterfaceXLPPI: 2334 interface_type = DINO_INTF_TYPE_XLPPI; 2335 break; 2336 case phymodInterfaceCX: 2337 interface_type = DINO_INTF_TYPE_CX; 2338 break; 2339 case phymodInterfaceCR: 2340 case phymodInterfaceCR4: 2341 case phymodInterfaceCR10: 2342 interface_type = DINO_INTF_TYPE_CR; 2343 break; 2344 case phymodInterfaceVSR: 2345 interface_type = DINO_INTF_TYPE_VSR; 2346 break; 2347 case phymodInterfaceOTN: 2348 interface_type = DINO_INTF_TYPE_OTN; 2349 break; 2350 case phymodInterfaceSGMII: 2351 interface_type = DINO_INTF_TYPE_SGMII; 2352 break; 2353 default: 2354 break; 2355 } 2356 2357 if ((config->data_rate == DINO_SPD_100G) || 2358 (config->data_rate == DINO_SPD_106G) || 2359 (config->data_rate == DINO_SPD_111G)) { 2360 lane_mask = 0x1; 2361 } 2362 2363 for (lane_idx = 0; lane_idx < DINO_MAX_LANE; lane_idx++) { 2364 if (lane_mask & (1 << lane_idx)) { 2365 READ_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + lane_idx), sw_gpreg_data); 2366 if (if_side == DINO_IF_LINE) { 2367 sw_gpreg_data &= ~(DINO_LINE_INTF_MASK); 2368 sw_gpreg_data |= (interface_type << DINO_LINE_INTF_SHIFT); 2369 } else { 2370 sw_gpreg_data &= ~(DINO_SYS_INTF_MASK); 2371 sw_gpreg_data |= (interface_type << DINO_SYS_INTF_SHIFT); 2372 } 2373 WRITE_DINO_PMA_PMD_REG(pa, (DINO_SW_GPREG_0_ADR + lane_idx), sw_gpreg_data); 2374 } 2375 } 2376 2377 return PHYMOD_E_NONE; 2378 } 2379 2380 int _dino_interface_set(const phymod_phy_access_t *phy, const phymod_phy_inf_config_t* config) 2381 { 2382 uint16_t DFE_option = SERDES_DFE_OPTION_NO_DFE; /*default to dfe disable*/ 2383 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 2384 uint16_t if_side = 0; 2385 uint16_t lane_mask = 0; 2386 uint16_t gpreg_data = 0; 2387 uint16_t port_idx = 0; 2388 uint16_t no_of_ports = 0; 2389 uint32_t chip_id = 0; 2390 uint32_t rev = 0; 2391 const phymod_access_t *pa = &phy->access; 2392 phymod_interface_t intf = config->interface_type; 2393 DINO_GET_INTF_SIDE(phy, if_side); 2394 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 2395 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 2396 DINO_GET_PORT_FROM_MODE(config, chip_id, no_of_ports); 2397 2398 if (intf == phymodInterfaceSR4 || intf == phymodInterfaceSR10 || 2399 intf == phymodInterfaceER4 || intf == phymodInterfaceLR10 || 2400 intf == phymodInterfaceLR || intf == phymodInterfaceLR4 || 2401 intf == phymodInterfaceSR || intf == phymodInterfaceER || 2402 intf == phymodInterfaceSFI || intf == phymodInterfaceXLPPI || intf == phymodInterfaceOTN) { 2403 if ((PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) && 2404 (if_side == DINO_IF_LINE) && 2405 (config->data_rate == DINO_SPD_111G)) { 2406 DFE_option = SERDES_DFE_OPTION_DFE; 2407 } else { 2408 DFE_option = SERDES_DFE_OPTION_NO_DFE; 2409 } 2410 if (config->interface_modes & PHYMOD_INTF_MODES_UNRELIABLE_LOS) { 2411 media_type = SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS; /*OPTICAL*/ 2412 } else { 2413 media_type = SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS; /*OPTICAL*/ 2414 } 2415 } else if (intf == phymodInterfaceCR4 || intf == phymodInterfaceCR || 2416 intf == phymodInterfaceCR10 || intf == phymodInterfaceCX || 2417 intf == phymodInterfaceSGMII) { 2418 media_type = SERDES_MEDIA_TYPE_COPPER_CABLE; /*Copper*/ 2419 DFE_option = SERDES_DFE_OPTION_DFE; 2420 } else if (intf == phymodInterfaceKX || intf == phymodInterfaceKR4 || intf == phymodInterfaceKR || 2421 intf == phymodInterfaceKR10) { 2422 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Back plane */ 2423 DFE_option = SERDES_DFE_OPTION_DFE; 2424 } else if (intf == phymodInterfaceCAUI4 || intf == phymodInterfaceCAUI || 2425 intf == phymodInterfaceCAUI4_C2M || intf == phymodInterfaceCAUI4_C2C || 2426 intf == phymodInterfaceVSR) { 2427 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Back plane */ 2428 DFE_option = SERDES_DFE_OPTION_DFE_LP_MODE; 2429 } else if (intf == phymodInterfaceXLAUI || 2430 intf == phymodInterfaceXFI) { 2431 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Back plane */ 2432 DFE_option = SERDES_DFE_OPTION_NO_DFE; 2433 } else { 2434 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, 2435 (_PHYMOD_MSG("Invalid interface type.."))); 2436 } 2437 2438 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 2439 if ((config->data_rate == DINO_SPD_100G) || 2440 (config->data_rate == DINO_SPD_106G) || 2441 (config->data_rate == DINO_SPD_111G)) { 2442 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 2443 /* Disable AN if it is enabled */ 2444 if (gpreg_data & DINO_AN_MASK) { 2445 gpreg_data &= ~(DINO_AN_MASK); 2446 } 2447 if (if_side == DINO_IF_LINE) { 2448 gpreg_data &= ~(DINO_LINE_MEDIA_TYPE_MASK); 2449 gpreg_data |= (media_type << DINO_LINE_MEDIA_TYPE_SHIFT); 2450 gpreg_data &= ~(DINO_LINE_DFE_OPTION_MASK); 2451 gpreg_data |= (DFE_option << DINO_LINE_DFE_OPTION_SHIFT); 2452 } else { 2453 gpreg_data &= ~(DINO_SYS_MEDIA_TYPE_MASK); 2454 gpreg_data |= (media_type << DINO_SYS_MEDIA_TYPE_SHIFT); 2455 gpreg_data &= ~(DINO_SYS_DFE_OPTION_MASK); 2456 gpreg_data |= (DFE_option << DINO_SYS_DFE_OPTION_SHIFT); 2457 } 2458 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 2459 break; 2460 } else if (config->data_rate == DINO_SPD_40G || config->data_rate == DINO_SPD_42G) { 2461 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 2462 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 2463 /* Disable AN if it is enabled */ 2464 if (gpreg_data & DINO_AN_MASK) { 2465 gpreg_data &= ~(DINO_AN_MASK); 2466 } 2467 if (if_side == DINO_IF_LINE) { 2468 gpreg_data &= ~(DINO_LINE_MEDIA_TYPE_MASK); 2469 gpreg_data |= (media_type << DINO_LINE_MEDIA_TYPE_SHIFT); 2470 gpreg_data &= ~(DINO_LINE_DFE_OPTION_MASK); 2471 gpreg_data |= (DFE_option << DINO_LINE_DFE_OPTION_SHIFT); 2472 } else { 2473 gpreg_data &= ~(DINO_SYS_MEDIA_TYPE_MASK); 2474 gpreg_data |= (media_type << DINO_SYS_MEDIA_TYPE_SHIFT); 2475 gpreg_data &= ~(DINO_SYS_DFE_OPTION_MASK); 2476 gpreg_data |= (DFE_option << DINO_SYS_DFE_OPTION_SHIFT); 2477 } 2478 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 2479 break; 2480 } else { 2481 continue; 2482 } 2483 } else if ((config->data_rate == DINO_SPD_10G) || 2484 (config->data_rate == DINO_SPD_11G) || 2485 (config->data_rate == DINO_SPD_11P18G) || 2486 (config->data_rate == DINO_SPD_1G)) { 2487 if ((lane_mask & (0x1 << port_idx))) { 2488 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 2489 /* Disable AN if it is enabled */ 2490 if (gpreg_data & DINO_AN_MASK) { 2491 gpreg_data &= ~(DINO_AN_MASK); 2492 } 2493 if (if_side == DINO_IF_LINE) { 2494 gpreg_data &= ~(DINO_LINE_MEDIA_TYPE_MASK); 2495 gpreg_data |= (media_type << DINO_LINE_MEDIA_TYPE_SHIFT); 2496 gpreg_data &= ~(DINO_LINE_DFE_OPTION_MASK); 2497 gpreg_data |= (DFE_option << DINO_LINE_DFE_OPTION_SHIFT); 2498 } else { 2499 gpreg_data &= ~(DINO_SYS_MEDIA_TYPE_MASK); 2500 gpreg_data |= (media_type << DINO_SYS_MEDIA_TYPE_SHIFT); 2501 gpreg_data &= ~(DINO_SYS_DFE_OPTION_MASK); 2502 gpreg_data |= (DFE_option << DINO_SYS_DFE_OPTION_SHIFT); 2503 } 2504 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 2505 break; 2506 } else { 2507 continue; 2508 } 2509 } else { 2510 /* Throw error as un supported mode */ 2511 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("Unsupported mode"))); 2512 } 2513 } 2514 2515 PHYMOD_IF_ERR_RETURN( 2516 _dino_save_interface(phy, config, intf)); 2517 2518 return PHYMOD_E_NONE; 2519 } 2520 2521 int _dino_get_pll_modes(const phymod_phy_access_t *phy, phymod_ref_clk_t ref_clk, const phymod_phy_inf_config_t *config, uint16_t *fal_pll_mode, uint16_t *mer_pll_mode) 2522 { 2523 uint32_t speed = config->data_rate; 2524 uint32_t chip_id = 0; 2525 uint32_t rev = 0; 2526 2527 PHYMOD_IF_ERR_RETURN(dino_get_chipid(&phy->access, &chip_id, &rev)); 2528 switch (ref_clk) { 2529 case phymodRefClk156Mhz: 2530 case phymodRefClk312Mhz: 2531 /* No OTN support on 156 and 312 */ 2532 if ((speed == DINO_SPD_111G) || (speed == DINO_SPD_11P18G)) { 2533 return PHYMOD_E_PARAM; 2534 } 2535 if (((speed == DINO_SPD_100G) || (speed == DINO_SPD_106G)) && 2536 (PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy))) { 2537 if (PHYMOD_INTF_MODES_HIGIG_GET(config) && (speed == DINO_SPD_106G)) { 2538 *fal_pll_mode = DINO_PLL_MODE_175; 2539 *mer_pll_mode = DINO_PLL_MODE_70; 2540 } else { 2541 *fal_pll_mode = DINO_PLL_MODE_165; 2542 *mer_pll_mode = DINO_PLL_MODE_66; 2543 } 2544 } else { 2545 /*-- Falcon Line Rate is 10G*/ 2546 if (PHYMOD_INTF_MODES_HIGIG_GET(config) && ((speed == DINO_SPD_11G) || (speed == DINO_SPD_42G) || (speed == DINO_SPD_106G))) { 2547 *fal_pll_mode = DINO_PLL_MODE_140; 2548 *mer_pll_mode = DINO_PLL_MODE_70; 2549 } else { /*IEEE MODE*/ 2550 *fal_pll_mode = DINO_PLL_MODE_132; 2551 *mer_pll_mode = DINO_PLL_MODE_66; 2552 } 2553 } 2554 break; 2555 case phymodRefClk161Mhz: 2556 case phymodRefClk322Mhz: 2557 case phymodRefClk644Mhz: 2558 /* No OTN or HIGIG Support on 161/322/644 */ 2559 if ((PHYMOD_INTF_MODES_HIGIG_GET(config)) || 2560 ((speed == DINO_SPD_111G) || (speed == DINO_SPD_11P18G))) { 2561 return PHYMOD_E_PARAM; 2562 } 2563 if (speed == DINO_SPD_100G) { 2564 /*IEEE MODE*/ 2565 if (PHYMOD_INTF_CONFIG_PHY_GEARBOX_ENABLE_GET(phy)) { 2566 if ((ref_clk == phymodRefClk322Mhz) && (chip_id == DINO_CHIP_ID_82793)) { 2567 *fal_pll_mode = DINO_PLL_MODE_80; 2568 *mer_pll_mode = DINO_PLL_MODE_64; 2569 } else { 2570 *fal_pll_mode = DINO_PLL_MODE_160; 2571 *mer_pll_mode = DINO_PLL_MODE_64; 2572 } 2573 } else { 2574 if ((ref_clk == phymodRefClk322Mhz) && (chip_id == DINO_CHIP_ID_82793)) { 2575 *fal_pll_mode = DINO_PLL_MODE_64; 2576 *mer_pll_mode = DINO_PLL_MODE_64; 2577 } else { 2578 *fal_pll_mode = DINO_PLL_MODE_128; 2579 *mer_pll_mode = DINO_PLL_MODE_64; 2580 } 2581 } 2582 } else { 2583 if ((ref_clk == phymodRefClk322Mhz) && (chip_id == DINO_CHIP_ID_82793)) { 2584 *fal_pll_mode = DINO_PLL_MODE_64; 2585 *mer_pll_mode = DINO_PLL_MODE_64; 2586 } else { 2587 *fal_pll_mode = DINO_PLL_MODE_128; 2588 *mer_pll_mode = DINO_PLL_MODE_64; 2589 } 2590 } 2591 break; 2592 case phymodRefClk174Mhz: 2593 case phymodRefClk349Mhz: 2594 case phymodRefClk698Mhz: 2595 if (speed == DINO_SPD_111G) { 2596 *fal_pll_mode = DINO_PLL_MODE_160; 2597 *mer_pll_mode = DINO_PLL_MODE_64; 2598 } else if (speed == DINO_SPD_11P18G) { 2599 *fal_pll_mode = DINO_PLL_MODE_128; 2600 *mer_pll_mode = DINO_PLL_MODE_64; 2601 } else { 2602 return PHYMOD_E_PARAM; 2603 } 2604 break; 2605 default: 2606 return PHYMOD_E_PARAM; 2607 } 2608 return PHYMOD_E_NONE; 2609 } 2610 /** Map Merlin PLL Division 2611 * @param pll_mode 2612 * @return Merlin PLL mode mapped value 2613 */ 2614 int _dino_map_mer_pll_div(DINO_PLL_MODE_E pll_mode) 2615 { 2616 switch (pll_mode) { 2617 case DINO_PLL_MODE_64: 2618 return 1; 2619 case DINO_PLL_MODE_66: 2620 return 2; 2621 case DINO_PLL_MODE_70: 2622 return 3; 2623 default: 2624 PHYMOD_DEBUG_VERBOSE(("PLLMODE %d not supported\n", pll_mode)); 2625 return PHYMOD_E_PARAM; 2626 } 2627 return PHYMOD_E_NONE; 2628 } 2629 2630 /** PMD lock get 2631 * 2632 * @param pa Pointer to phymod access structure 2633 * @param if_side interface side 0 - Line side 1- Sys side 2634 * @param lane lane number 2635 * @param rx_pmd_locked RX PMD locked 2636 * 2637 * @return PHYMOD_E_NONE successful function execution 2638 */ 2639 int _dino_rx_pmd_lock_get(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, uint32_t *rx_pmd_locked) 2640 { 2641 uint8_t pmd_lock = 1; 2642 2643 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 2644 PHYMOD_IF_ERR_RETURN(falcon2_dino_pmd_lock_status(pa, &pmd_lock)); 2645 *rx_pmd_locked &= pmd_lock; 2646 } else { 2647 PHYMOD_IF_ERR_RETURN(merlin_dino_pmd_lock_status(pa, &pmd_lock)); 2648 *rx_pmd_locked &= pmd_lock; 2649 } 2650 2651 return PHYMOD_E_NONE; 2652 } 2653 2654 int _dino_get_rx_pmd_lock_status(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, uint32_t *link_sts) 2655 { 2656 return _dino_rx_pmd_lock_get(pa, if_side, lane, link_sts); 2657 } 2658 2659 2660 int _dino_phy_status_dump(const phymod_access_t *pa, uint16_t if_side, uint16_t lane) 2661 { 2662 uint8_t trace_mem[768]; 2663 2664 USR_PRINTF(("**********************************************\n")); 2665 USR_PRINTF(("******* PHY status dump for PHY ID:%d ********\n", pa->addr)); 2666 USR_PRINTF(("**********************************************\n")); 2667 USR_PRINTF(("**** PHY status dump for interface side:%d ****\n", if_side)); 2668 USR_PRINTF(("***********************************************\n")); 2669 2670 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 2671 PHYMOD_IF_ERR_RETURN(falcon2_dino_display_core_config(pa)); 2672 PHYMOD_IF_ERR_RETURN(falcon2_dino_display_core_state(pa)); 2673 PHYMOD_DEBUG_VERBOSE(("Falcon Status dump\n")); 2674 PHYMOD_IF_ERR_RETURN(falcon2_dino_display_lane_state_hdr(pa)); 2675 PHYMOD_IF_ERR_RETURN(falcon2_dino_display_lane_state(pa)); 2676 PHYMOD_IF_ERR_RETURN(falcon2_dino_display_lane_config(pa)); 2677 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_event_log(pa, trace_mem, EVENT_LOG_HEX_AND_DECODED)); 2678 } else { 2679 PHYMOD_IF_ERR_RETURN(merlin_dino_display_core_config(pa)); 2680 PHYMOD_IF_ERR_RETURN(merlin_dino_display_core_state(pa)); 2681 PHYMOD_DEBUG_VERBOSE(("Merlin Status dump\n")); 2682 PHYMOD_IF_ERR_RETURN(merlin_dino_display_lane_state_hdr(pa)); 2683 PHYMOD_IF_ERR_RETURN(merlin_dino_display_lane_state(pa)); 2684 PHYMOD_IF_ERR_RETURN(merlin_dino_display_lane_config(pa)); 2685 PHYMOD_IF_ERR_RETURN(merlin_dino_read_event_log(pa, trace_mem, EVENT_LOG_HEX_AND_DECODED)); 2686 } 2687 2688 return PHYMOD_E_NONE; 2689 } 2690 2691 int _dino_loopback_set(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, phymod_loopback_mode_t loopback, uint32_t enable) 2692 { 2693 uint16_t data = 0; 2694 BCMI_DINO_FIFO_RST_FRC_CTL1r_t fifo_rst_frc_ln; 2695 BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_t fifo_rst_frcval_ln; 2696 BCMI_DINO_FIFO_RST_FRC_CTL0r_t fifo_rst_frc_sys; 2697 BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_t fifo_rst_frcval_sys; 2698 PHYMOD_MEMSET(&fifo_rst_frc_ln, 0, sizeof(BCMI_DINO_FIFO_RST_FRC_CTL1r_t)); 2699 PHYMOD_MEMSET(&fifo_rst_frcval_ln, 0, sizeof(BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_t)); 2700 PHYMOD_MEMSET(&fifo_rst_frc_sys, 0, sizeof(BCMI_DINO_FIFO_RST_FRC_CTL0r_t)); 2701 PHYMOD_MEMSET(&fifo_rst_frcval_sys, 0, sizeof(BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_t)); 2702 2703 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 2704 PHYMOD_IF_ERR_RETURN( 2705 _dino_falcon_lpbk_set(pa, if_side, lane, loopback, enable)); 2706 } else { 2707 PHYMOD_IF_ERR_RETURN( 2708 _dino_merlin_lpbk_set(pa, if_side, lane, loopback, enable)); 2709 } 2710 /* Perform FIFO reset on ingress and egress path */ 2711 /* Set force val to 0*/ 2712 PHYMOD_IF_ERR_RETURN( 2713 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL1r(pa, &fifo_rst_frcval_ln)); 2714 data = fifo_rst_frcval_ln.v[0]; 2715 data &= ~(1 << lane); 2716 BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_SET(fifo_rst_frcval_ln, data); 2717 PHYMOD_IF_ERR_RETURN( 2718 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL1r(pa, fifo_rst_frcval_ln)); 2719 2720 /* Set force to 1*/ 2721 PHYMOD_IF_ERR_RETURN( 2722 BCMI_DINO_READ_FIFO_RST_FRC_CTL1r(pa, &fifo_rst_frc_ln)); 2723 data = fifo_rst_frc_ln.v[0]; 2724 data |= (1 << lane); 2725 BCMI_DINO_FIFO_RST_FRC_CTL1r_SET(fifo_rst_frc_ln, data); 2726 2727 PHYMOD_IF_ERR_RETURN( 2728 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL1r(pa, fifo_rst_frc_ln)); 2729 2730 PHYMOD_USLEEP(50); 2731 /* Set force val to default*/ 2732 PHYMOD_IF_ERR_RETURN( 2733 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL1r(pa, &fifo_rst_frcval_ln)); 2734 data = fifo_rst_frcval_ln.v[0]; 2735 data |= (1 << lane); 2736 BCMI_DINO_FIFO_RST_FRCVAL_CTL1r_SET(fifo_rst_frcval_ln, data); 2737 PHYMOD_IF_ERR_RETURN( 2738 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL1r(pa, fifo_rst_frcval_ln)); 2739 2740 /* Set force to default*/ 2741 PHYMOD_IF_ERR_RETURN( 2742 BCMI_DINO_READ_FIFO_RST_FRC_CTL1r(pa, &fifo_rst_frc_ln)); 2743 data = fifo_rst_frc_ln.v[0]; 2744 data &= ~(1 << lane); 2745 BCMI_DINO_FIFO_RST_FRC_CTL1r_SET(fifo_rst_frc_ln, data); 2746 2747 PHYMOD_IF_ERR_RETURN( 2748 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL1r(pa, fifo_rst_frc_ln)); 2749 2750 /* Set force val to 0*/ 2751 PHYMOD_IF_ERR_RETURN( 2752 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL0r(pa, &fifo_rst_frcval_sys)); 2753 data = fifo_rst_frcval_sys.v[0]; 2754 data &= ~(1 << lane); 2755 BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_SET(fifo_rst_frcval_sys, data); 2756 PHYMOD_IF_ERR_RETURN( 2757 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL0r(pa, fifo_rst_frcval_sys)); 2758 2759 /* Set force to 1*/ 2760 PHYMOD_IF_ERR_RETURN( 2761 BCMI_DINO_READ_FIFO_RST_FRC_CTL0r(pa, &fifo_rst_frc_sys)); 2762 data = fifo_rst_frc_sys.v[0]; 2763 data |= (1 << lane); 2764 BCMI_DINO_FIFO_RST_FRC_CTL0r_SET(fifo_rst_frc_sys, data); 2765 PHYMOD_IF_ERR_RETURN( 2766 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL0r(pa, fifo_rst_frc_sys)); 2767 PHYMOD_USLEEP(50); 2768 2769 /* Set force val to default*/ 2770 PHYMOD_IF_ERR_RETURN( 2771 BCMI_DINO_READ_FIFO_RST_FRCVAL_CTL0r(pa, &fifo_rst_frcval_sys)); 2772 data = fifo_rst_frcval_sys.v[0]; 2773 data |= (1 << lane); 2774 BCMI_DINO_FIFO_RST_FRCVAL_CTL0r_SET(fifo_rst_frcval_sys, data); 2775 PHYMOD_IF_ERR_RETURN( 2776 BCMI_DINO_WRITE_FIFO_RST_FRCVAL_CTL0r(pa, fifo_rst_frcval_sys)); 2777 2778 /* Set force to default*/ 2779 PHYMOD_IF_ERR_RETURN( 2780 BCMI_DINO_READ_FIFO_RST_FRC_CTL0r(pa, &fifo_rst_frc_sys)); 2781 data = fifo_rst_frc_sys.v[0]; 2782 data &= ~(1 << lane); 2783 BCMI_DINO_FIFO_RST_FRC_CTL0r_SET(fifo_rst_frc_sys, data); 2784 PHYMOD_IF_ERR_RETURN( 2785 BCMI_DINO_WRITE_FIFO_RST_FRC_CTL0r(pa, fifo_rst_frc_sys)); 2786 2787 return PHYMOD_E_NONE; 2788 } 2789 2790 int _dino_loopback_get(const phymod_access_t *pa, uint16_t if_side, uint16_t lane, phymod_loopback_mode_t loopback, uint32_t* enable) 2791 { 2792 PHYMOD_IF_ERR_RETURN( 2793 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 2794 2795 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 2796 PHYMOD_IF_ERR_RETURN( 2797 _dino_falcon_lpbk_get(pa, if_side, loopback, enable)); 2798 } else { 2799 PHYMOD_IF_ERR_RETURN( 2800 _dino_merlin_lpbk_get(pa, if_side, loopback, enable)); 2801 } 2802 PHYMOD_IF_ERR_RETURN( 2803 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 2804 2805 return PHYMOD_E_NONE; 2806 } 2807 2808 int _dino_falcon_lpbk_get(const phymod_access_t *pa, uint16_t if_side, phymod_loopback_mode_t loopback, uint32_t* enable) 2809 { 2810 BCMI_DINO_F25G_TLB_RX_DIG_LPBK_CFGr_t dig_lpbk; 2811 BCMI_DINO_F25G_TLB_TX_RMT_LPBK_CFGr_t rmt_lpbk; 2812 PHYMOD_MEMSET(&dig_lpbk, 0, sizeof(BCMI_DINO_F25G_TLB_RX_DIG_LPBK_CFGr_t)); 2813 PHYMOD_MEMSET(&rmt_lpbk, 0, sizeof(BCMI_DINO_F25G_TLB_TX_RMT_LPBK_CFGr_t)); 2814 PHYMOD_DEBUG_VERBOSE(("Falcon loopback get\n")); 2815 2816 switch (loopback) { 2817 case phymodLoopbackRemotePMD: /* Falcon remote loopback set */ 2818 PHYMOD_IF_ERR_RETURN( 2819 BCMI_DINO_READ_F25G_TLB_TX_RMT_LPBK_CFGr(pa,&rmt_lpbk)); 2820 *enable = BCMI_DINO_F25G_TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(rmt_lpbk); 2821 break; 2822 case phymodLoopbackRemotePCS: 2823 return PHYMOD_E_UNAVAIL; 2824 break; 2825 case phymodLoopbackGlobal: 2826 case phymodLoopbackGlobalPMD: /* Falcon digital loopback set */ 2827 /* Falcon Digital loopback get */ 2828 PHYMOD_IF_ERR_RETURN( 2829 BCMI_DINO_READ_F25G_TLB_RX_DIG_LPBK_CFGr(pa, &dig_lpbk)); 2830 *enable = BCMI_DINO_F25G_TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(dig_lpbk); 2831 break; 2832 default : 2833 break; 2834 } 2835 2836 return PHYMOD_E_NONE; 2837 } 2838 2839 int _dino_merlin_lpbk_get(const phymod_access_t *pa, uint16_t if_side, phymod_loopback_mode_t loopback, uint32_t* enable) 2840 { 2841 BCMI_DINO_M10G_TLB_RX_DIG_LPBK_CFGr_t dig_lpbk; 2842 BCMI_DINO_M10G_TLB_TX_RMT_LPBK_CFGr_t rmt_lpbk; 2843 PHYMOD_MEMSET(&dig_lpbk, 0, sizeof(BCMI_DINO_M10G_TLB_RX_DIG_LPBK_CFGr_t)); 2844 PHYMOD_MEMSET(&rmt_lpbk, 0, sizeof(BCMI_DINO_M10G_TLB_TX_RMT_LPBK_CFGr_t)); 2845 PHYMOD_DEBUG_VERBOSE(("Falcon loopback get\n")); 2846 2847 switch (loopback) { 2848 case phymodLoopbackRemotePMD: /* Falcon remote loopback set */ 2849 PHYMOD_IF_ERR_RETURN( 2850 BCMI_DINO_READ_M10G_TLB_TX_RMT_LPBK_CFGr(pa,&rmt_lpbk)); 2851 *enable = BCMI_DINO_M10G_TLB_TX_RMT_LPBK_CFGr_RMT_LPBK_ENf_GET(rmt_lpbk); 2852 break; 2853 case phymodLoopbackRemotePCS: 2854 return PHYMOD_E_UNAVAIL; 2855 break; 2856 case phymodLoopbackGlobal: 2857 case phymodLoopbackGlobalPMD: /* Falcon digital loopback set */ 2858 /* Falcon Digital loopback get */ 2859 PHYMOD_IF_ERR_RETURN( 2860 BCMI_DINO_READ_M10G_TLB_RX_DIG_LPBK_CFGr(pa, &dig_lpbk)); 2861 *enable = BCMI_DINO_M10G_TLB_RX_DIG_LPBK_CFGr_DIG_LPBK_ENf_GET(dig_lpbk); 2862 break; 2863 default : 2864 break; 2865 } 2866 2867 return PHYMOD_E_NONE; 2868 } 2869 2870 2871 int _dino_falcon_lpbk_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, 2872 phymod_loopback_mode_t loopback, uint32_t enable) 2873 { 2874 uint16_t if_other_side = 0; 2875 uint16_t lane_index = 0; 2876 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 2877 uint16_t sw_gpreg_data = 0; 2878 uint16_t other_side_start_lane = 0; 2879 uint16_t other_side_end_lane = 0; 2880 BCMI_DINO_DECD_MODE_STS0r_t mode_sts0; 2881 PHYMOD_MEMSET(&mode_sts0, 0, sizeof(BCMI_DINO_DECD_MODE_STS0r_t)); 2882 2883 (if_side == DINO_IF_LINE) ? (if_other_side = DINO_IF_SYS) : (if_other_side = DINO_IF_LINE); 2884 2885 PHYMOD_DEBUG_VERBOSE(("Falcon loopback set\n")); 2886 2887 switch (loopback) { 2888 case phymodLoopbackRemotePMD: /* Falcon remote loopback set */ 2889 PHYMOD_IF_ERR_RETURN( 2890 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 2891 PHYMOD_IF_ERR_RETURN(falcon2_dino_rmt_lpbk(pa, enable)); 2892 PHYMOD_IF_ERR_RETURN( 2893 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 2894 break; 2895 case phymodLoopbackRemotePCS: 2896 return PHYMOD_E_UNAVAIL; 2897 break; 2898 case phymodLoopbackGlobal: 2899 case phymodLoopbackGlobalPMD: /* Falcon digital loopback set */ 2900 /* Read the GPREG to check if Gear box mode is set. 2901 * For GBOX mode , we need to program all system side lanes 2902 */ 2903 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 2904 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 2905 if (dev_op_mode == DINO_DEV_OP_MODE_GBOX) { 2906 PHYMOD_IF_ERR_RETURN( 2907 BCMI_DINO_READ_DECD_MODE_STS0r(pa, &mode_sts0)); 2908 if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_GBOX_2TO11f_GET(mode_sts0)) { 2909 other_side_start_lane = 2; 2910 other_side_end_lane = 11; 2911 } else if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_GBOX_1TO10f_GET(mode_sts0)) { 2912 other_side_start_lane = 1; 2913 other_side_end_lane = 10; 2914 } else if (BCMI_DINO_DECD_MODE_STS0r_DECODED_MODE_100G_GBOX_0TO9f_GET(mode_sts0)) { 2915 other_side_start_lane = 0; 2916 other_side_end_lane = 9; 2917 } else { 2918 other_side_start_lane = 0; 2919 other_side_end_lane = 9; 2920 } 2921 for (lane_index = other_side_start_lane; lane_index <= other_side_end_lane; lane_index++) { 2922 PHYMOD_IF_ERR_RETURN( 2923 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_other_side, lane_index)); 2924 PHYMOD_IF_ERR_RETURN(merlin_dino_dig_lpbk_rptr(pa, enable, DATA_IN_SIDE)); 2925 } 2926 } else { 2927 PHYMOD_IF_ERR_RETURN( 2928 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_other_side, lane)); 2929 PHYMOD_IF_ERR_RETURN(merlin_dino_dig_lpbk_rptr(pa, enable, DATA_IN_SIDE)); 2930 } 2931 PHYMOD_IF_ERR_RETURN( 2932 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 2933 PHYMOD_IF_ERR_RETURN(falcon2_dino_dig_lpbk_rptr(pa, enable, DIG_LPBK_SIDE)); 2934 /* Disable the prbs_chk_en_auto_mode while seting digital loopback */ 2935 PHYMOD_IF_ERR_RETURN(falcon2_dino_wr_prbs_chk_en_auto_mode((!enable))); 2936 /* TX disable while enabling digital loopback */ 2937 PHYMOD_IF_ERR_RETURN(falcon2_dino_wr_sdk_tx_disable(enable)); 2938 PHYMOD_IF_ERR_RETURN( 2939 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 2940 break; 2941 default : 2942 break; 2943 } 2944 2945 return PHYMOD_E_NONE; 2946 } 2947 2948 int _dino_merlin_lpbk_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, 2949 phymod_loopback_mode_t loopback, uint32_t enable) 2950 { 2951 uint16_t if_other_side = 0; 2952 uint16_t other_side_start_lane = 0; 2953 uint16_t other_side_end_lane = 0; 2954 uint16_t sw_gpreg_data = 0; 2955 uint16_t lane_index = 0; 2956 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 2957 2958 (if_side == DINO_IF_LINE) ? (if_other_side = DINO_IF_SYS) : (if_other_side = DINO_IF_LINE); 2959 2960 PHYMOD_DEBUG_VERBOSE(("Merlin loopback set\n")); 2961 2962 switch (loopback) { 2963 case phymodLoopbackRemotePMD: 2964 PHYMOD_IF_ERR_RETURN( 2965 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 2966 PHYMOD_IF_ERR_RETURN(merlin_dino_rmt_lpbk(pa, enable)); 2967 PHYMOD_IF_ERR_RETURN( 2968 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 2969 break; 2970 case phymodLoopbackRemotePCS: 2971 return PHYMOD_E_UNAVAIL; 2972 break; 2973 case phymodLoopbackGlobal: 2974 case phymodLoopbackGlobalPMD: 2975 /* Read the GPREG to check if Gear box mode is set. 2976 * For GBOX mode , we need to program only 4 line side lanes 2977 */ 2978 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 2979 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 2980 if ((if_side == DINO_IF_SYS) && (dev_op_mode == DINO_DEV_OP_MODE_GBOX)) { 2981 other_side_start_lane = 0; 2982 other_side_end_lane = 3; 2983 PHYMOD_IF_ERR_RETURN( 2984 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_other_side, lane)); 2985 for (lane_index = other_side_start_lane; lane_index <= other_side_end_lane; lane_index++) { 2986 PHYMOD_IF_ERR_RETURN( 2987 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_other_side, lane_index)); 2988 PHYMOD_IF_ERR_RETURN(falcon2_dino_dig_lpbk_rptr(pa, enable, DATA_IN_SIDE)); 2989 } 2990 } else { 2991 PHYMOD_IF_ERR_RETURN( 2992 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_other_side, lane)); 2993 if ((if_side == DINO_IF_SYS) && (lane < DINO_MAX_CORE_LANE)) { 2994 PHYMOD_IF_ERR_RETURN(falcon2_dino_dig_lpbk_rptr(pa, enable, DATA_IN_SIDE)); 2995 } else { 2996 PHYMOD_IF_ERR_RETURN(merlin_dino_dig_lpbk_rptr(pa, enable, DATA_IN_SIDE)); 2997 } 2998 } 2999 PHYMOD_IF_ERR_RETURN( 3000 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 3001 PHYMOD_IF_ERR_RETURN(merlin_dino_dig_lpbk_rptr(pa, enable, DIG_LPBK_SIDE)); 3002 /* Disable the prbs_chk_en_auto_mode while seting digital loopback */ 3003 PHYMOD_IF_ERR_RETURN(wr_prbs_chk_en_auto_mode((!enable))); 3004 /* TX disable while enabling digital loopback on the line side*/ 3005 if (if_side == DINO_IF_LINE) { 3006 PHYMOD_IF_ERR_RETURN(wr_sdk_tx_disable(enable)); 3007 } 3008 break; 3009 default : 3010 break; 3011 } 3012 PHYMOD_IF_ERR_RETURN( 3013 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 3014 3015 return PHYMOD_E_NONE; 3016 } 3017 3018 int _dino_phy_polarity_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, uint16_t tx_polarity, uint16_t rx_polarity) 3019 { 3020 BCMI_DINO_F25G_TLB_RX_TLB_RX_MISC_CFGr_t fal_rx_pol; 3021 BCMI_DINO_F25G_TLB_TX_TLB_TX_MISC_CFGr_t fal_tx_pol; 3022 BCMI_DINO_M10G_TLB_RX_TLB_RX_MISC_CFGr_t mer_rx_pol; 3023 BCMI_DINO_M10G_TLB_TX_TLB_TX_MISC_CFGr_t mer_tx_pol; 3024 3025 PHYMOD_MEMSET(&fal_rx_pol, 0, sizeof(fal_rx_pol)); 3026 PHYMOD_MEMSET(&fal_tx_pol, 0, sizeof(fal_tx_pol)); 3027 PHYMOD_MEMSET(&mer_tx_pol, 0, sizeof(mer_tx_pol)); 3028 PHYMOD_MEMSET(&mer_rx_pol, 0, sizeof(mer_rx_pol)); 3029 3030 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3031 if (tx_polarity != 0xFFFF) { 3032 PHYMOD_IF_ERR_RETURN( 3033 BCMI_DINO_READ_F25G_TLB_TX_TLB_TX_MISC_CFGr(pa, &fal_tx_pol)); 3034 BCMI_DINO_F25G_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(fal_tx_pol, tx_polarity); 3035 PHYMOD_IF_ERR_RETURN( 3036 BCMI_DINO_WRITE_F25G_TLB_TX_TLB_TX_MISC_CFGr(pa, fal_tx_pol)); 3037 } 3038 if (rx_polarity != 0xFFFF) { 3039 PHYMOD_IF_ERR_RETURN( 3040 BCMI_DINO_READ_F25G_TLB_RX_TLB_RX_MISC_CFGr(pa, &fal_rx_pol)); 3041 BCMI_DINO_F25G_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(fal_rx_pol, rx_polarity); 3042 PHYMOD_IF_ERR_RETURN( 3043 BCMI_DINO_WRITE_F25G_TLB_RX_TLB_RX_MISC_CFGr(pa, fal_rx_pol)); 3044 } 3045 } else { 3046 if (rx_polarity != 0xFFFF) { 3047 PHYMOD_IF_ERR_RETURN( 3048 BCMI_DINO_READ_M10G_TLB_RX_TLB_RX_MISC_CFGr(pa, &mer_rx_pol)); 3049 BCMI_DINO_M10G_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_SET(mer_rx_pol, rx_polarity); 3050 PHYMOD_IF_ERR_RETURN( 3051 BCMI_DINO_WRITE_M10G_TLB_RX_TLB_RX_MISC_CFGr(pa, mer_rx_pol)); 3052 } 3053 if (tx_polarity != 0xFFFF) { 3054 PHYMOD_IF_ERR_RETURN( 3055 BCMI_DINO_READ_M10G_TLB_TX_TLB_TX_MISC_CFGr(pa, &mer_tx_pol)); 3056 BCMI_DINO_M10G_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_SET(mer_tx_pol, tx_polarity); 3057 PHYMOD_IF_ERR_RETURN( 3058 BCMI_DINO_WRITE_M10G_TLB_TX_TLB_TX_MISC_CFGr(pa, mer_tx_pol)); 3059 } 3060 } 3061 return PHYMOD_E_NONE; 3062 } 3063 3064 int _dino_phy_polarity_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, uint16_t *tx_polarity, uint16_t *rx_polarity) 3065 { 3066 BCMI_DINO_F25G_TLB_RX_TLB_RX_MISC_CFGr_t fal_rx_pol; 3067 BCMI_DINO_F25G_TLB_TX_TLB_TX_MISC_CFGr_t fal_tx_pol; 3068 BCMI_DINO_M10G_TLB_RX_TLB_RX_MISC_CFGr_t mer_rx_pol; 3069 BCMI_DINO_M10G_TLB_TX_TLB_TX_MISC_CFGr_t mer_tx_pol; 3070 3071 PHYMOD_MEMSET(&fal_rx_pol, 0, sizeof(fal_rx_pol)); 3072 PHYMOD_MEMSET(&fal_tx_pol, 0, sizeof(fal_tx_pol)); 3073 PHYMOD_MEMSET(&mer_tx_pol, 0, sizeof(mer_tx_pol)); 3074 PHYMOD_MEMSET(&mer_rx_pol, 0, sizeof(mer_rx_pol)); 3075 3076 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3077 PHYMOD_IF_ERR_RETURN( 3078 BCMI_DINO_READ_F25G_TLB_TX_TLB_TX_MISC_CFGr(pa, &fal_tx_pol)); 3079 *tx_polarity = BCMI_DINO_F25G_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(fal_tx_pol); 3080 3081 PHYMOD_IF_ERR_RETURN( 3082 BCMI_DINO_READ_F25G_TLB_RX_TLB_RX_MISC_CFGr(pa, &fal_rx_pol)); 3083 *rx_polarity = BCMI_DINO_F25G_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(fal_rx_pol); 3084 } else { 3085 PHYMOD_IF_ERR_RETURN( 3086 BCMI_DINO_READ_M10G_TLB_RX_TLB_RX_MISC_CFGr(pa, &mer_rx_pol)); 3087 *rx_polarity = BCMI_DINO_M10G_TLB_RX_TLB_RX_MISC_CFGr_RX_PMD_DP_INVERTf_GET(mer_rx_pol); 3088 3089 PHYMOD_IF_ERR_RETURN( 3090 BCMI_DINO_READ_M10G_TLB_TX_TLB_TX_MISC_CFGr(pa, &mer_tx_pol)); 3091 *tx_polarity = BCMI_DINO_M10G_TLB_TX_TLB_TX_MISC_CFGr_TX_PMD_DP_INVERTf_GET(mer_tx_pol); 3092 } 3093 return PHYMOD_E_NONE; 3094 } 3095 3096 int _dino_phy_fec_set(const phymod_phy_access_t* phy, uint16_t enable) 3097 { 3098 BCMI_DINO_MODECTL0r_t modectrl0; 3099 3100 PHYMOD_MEMSET(&modectrl0, 0, sizeof(modectrl0)); 3101 3102 /* this may need to modify in AN mode*/ 3103 PHYMOD_IF_ERR_RETURN( 3104 BCMI_DINO_READ_MODECTL0r(&phy->access, &modectrl0)); 3105 BCMI_DINO_MODECTL0r_MODE_CL91_ENf_SET(modectrl0, enable); 3106 PHYMOD_IF_ERR_RETURN( 3107 BCMI_DINO_WRITE_MODECTL0r(&phy->access, modectrl0)); 3108 3109 PHYMOD_IF_ERR_RETURN( 3110 _dino_fw_enable(&phy->access)); 3111 3112 return PHYMOD_E_NONE; 3113 } 3114 3115 int _dino_phy_fec_get(const phymod_phy_access_t* phy, uint32_t *enable) 3116 { 3117 BCMI_DINO_MODECTL0r_t modectrl0; 3118 3119 PHYMOD_MEMSET(&modectrl0, 0, sizeof(modectrl0)); 3120 3121 PHYMOD_IF_ERR_RETURN( 3122 BCMI_DINO_READ_MODECTL0r(&phy->access, &modectrl0)); 3123 *enable = BCMI_DINO_MODECTL0r_MODE_CL91_ENf_GET(modectrl0); 3124 3125 return PHYMOD_E_NONE; 3126 } 3127 3128 int _dino_phy_power_set(const phymod_phy_access_t* phy, uint16_t if_side, uint16_t lane, const phymod_phy_power_t* power) 3129 { 3130 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_t mer_power; 3131 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_t fal_power; 3132 PHYMOD_MEMSET(&mer_power, 0, sizeof(mer_power)); 3133 PHYMOD_MEMSET(&fal_power, 0, sizeof(fal_power)); 3134 3135 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3136 if (power->tx != phymodPowerNoChange) { 3137 PHYMOD_IF_ERR_RETURN ( 3138 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, &fal_power)); 3139 if (power->tx == phymodPowerOff) { 3140 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(fal_power, 1); 3141 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(fal_power,1); 3142 } else if (power->tx == phymodPowerOn) { 3143 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(fal_power,0); 3144 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(fal_power, 0); 3145 } else if (power->tx == phymodPowerOffOn) { 3146 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(fal_power, 1); 3147 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(fal_power,1); 3148 PHYMOD_IF_ERR_RETURN ( 3149 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, fal_power)); 3150 PHYMOD_USLEEP(10); 3151 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(fal_power, 0); 3152 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(fal_power,0); 3153 } 3154 PHYMOD_IF_ERR_RETURN ( 3155 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, fal_power)); 3156 } 3157 if (power->rx != phymodPowerNoChange) { 3158 PHYMOD_IF_ERR_RETURN ( 3159 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, &fal_power)); 3160 if (power->rx == phymodPowerOff) { 3161 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(fal_power, 1); 3162 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(fal_power,1); 3163 } else if (power->rx == phymodPowerOn) { 3164 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(fal_power, 0); 3165 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(fal_power,0); 3166 } else if (power->rx == phymodPowerOffOn) { 3167 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(fal_power, 1); 3168 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(fal_power,1); 3169 PHYMOD_IF_ERR_RETURN ( 3170 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, fal_power)); 3171 PHYMOD_USLEEP(10); 3172 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(fal_power, 0); 3173 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(fal_power,0); 3174 } 3175 PHYMOD_IF_ERR_RETURN ( 3176 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, fal_power)); 3177 } 3178 } else { 3179 if (power->tx != phymodPowerNoChange) { 3180 PHYMOD_IF_ERR_RETURN ( 3181 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, &mer_power)); 3182 if (power->tx == phymodPowerOff) { 3183 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(mer_power, 1); 3184 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(mer_power,1); 3185 } else if (power->tx == phymodPowerOn) { 3186 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(mer_power,0); 3187 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(mer_power, 0); 3188 } else if (power->tx == phymodPowerOffOn) { 3189 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(mer_power, 1); 3190 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(mer_power,1); 3191 PHYMOD_IF_ERR_RETURN ( 3192 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, mer_power)); 3193 PHYMOD_USLEEP(10); 3194 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_SET(mer_power, 0); 3195 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_SET(mer_power,0); 3196 } 3197 PHYMOD_IF_ERR_RETURN ( 3198 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, mer_power)); 3199 } 3200 if (power->rx != phymodPowerNoChange) { 3201 PHYMOD_IF_ERR_RETURN ( 3202 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, &mer_power)); 3203 if (power->rx == phymodPowerOff) { 3204 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(mer_power, 1); 3205 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(mer_power,1); 3206 } else if (power->rx == phymodPowerOn) { 3207 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(mer_power, 0); 3208 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(mer_power,0); 3209 } else if (power->rx == phymodPowerOffOn) { 3210 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(mer_power, 1); 3211 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(mer_power,1); 3212 PHYMOD_IF_ERR_RETURN ( 3213 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, mer_power)); 3214 PHYMOD_USLEEP(10); 3215 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(mer_power, 0); 3216 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(mer_power,0); 3217 } 3218 PHYMOD_IF_ERR_RETURN ( 3219 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, mer_power)); 3220 } 3221 } 3222 return PHYMOD_E_NONE; 3223 } 3224 3225 int _dino_phy_power_get(const phymod_phy_access_t* phy, uint16_t if_side, uint16_t lane, phymod_phy_power_t* power) 3226 { 3227 uint16_t force = 0, pwr = 0; 3228 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_t mer_power; 3229 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_t fal_power; 3230 PHYMOD_MEMSET(&mer_power, 0 , sizeof(mer_power)); 3231 PHYMOD_MEMSET(&fal_power, 0 , sizeof(fal_power)); 3232 3233 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3234 PHYMOD_IF_ERR_RETURN ( 3235 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL2_PER_LANEr(&phy->access, &fal_power)); 3236 force = BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_GET(fal_power); 3237 pwr = BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_GET(fal_power); 3238 if (force && pwr) { 3239 power->tx = phymodPowerOff; 3240 } else { 3241 power->tx = phymodPowerOn; 3242 } 3243 force = BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_GET(fal_power); 3244 pwr = BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_GET(fal_power); 3245 if (force && pwr) { 3246 power->rx = phymodPowerOff; 3247 } else { 3248 power->rx = phymodPowerOn; 3249 } 3250 } else { 3251 PHYMOD_IF_ERR_RETURN ( 3252 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL2_PER_LANEr(&phy->access, &mer_power)); 3253 force = BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCf_GET(mer_power); 3254 pwr = BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_TX_H_PWRDN_FRCVALf_GET(mer_power); 3255 if (force && pwr) { 3256 power->tx = phymodPowerOff; 3257 } else { 3258 power->tx = phymodPowerOn; 3259 } 3260 force = BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_GET(mer_power); 3261 pwr = BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_GET(mer_power); 3262 if (force && pwr) { 3263 power->rx = phymodPowerOff; 3264 } else { 3265 power->rx = phymodPowerOn; 3266 } 3267 } 3268 3269 return PHYMOD_E_NONE; 3270 } 3271 3272 int _dino_phy_reset_set(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, const phymod_phy_reset_t* reset) 3273 { 3274 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3275 if (reset->tx == phymodResetDirectionIn) { 3276 PHYMOD_IF_ERR_RETURN( 3277 falcon2_dino_wr_ln_tx_dp_s_rstb(0)); 3278 } else if (reset->tx == phymodResetDirectionOut) { 3279 PHYMOD_IF_ERR_RETURN( 3280 falcon2_dino_wr_ln_tx_dp_s_rstb(1)); 3281 } else if (reset->tx == phymodResetDirectionInOut) { 3282 PHYMOD_IF_ERR_RETURN( 3283 falcon2_dino_wr_ln_tx_dp_s_rstb(0)); 3284 PHYMOD_USLEEP(10); 3285 PHYMOD_IF_ERR_RETURN( 3286 falcon2_dino_wr_ln_tx_dp_s_rstb(1)); 3287 } 3288 if (reset->rx == phymodResetDirectionIn) { 3289 PHYMOD_IF_ERR_RETURN( 3290 falcon2_dino_wr_ln_rx_dp_s_rstb(0)); 3291 } else if (reset->rx == phymodResetDirectionOut) { 3292 PHYMOD_IF_ERR_RETURN( 3293 falcon2_dino_wr_ln_rx_dp_s_rstb(1)); 3294 } else if (reset->rx == phymodResetDirectionInOut) { 3295 PHYMOD_IF_ERR_RETURN( 3296 falcon2_dino_wr_ln_rx_dp_s_rstb(0)); 3297 PHYMOD_USLEEP(10); 3298 PHYMOD_IF_ERR_RETURN( 3299 falcon2_dino_wr_ln_rx_dp_s_rstb(1)); 3300 3301 } 3302 } else { 3303 if (reset->tx == phymodResetDirectionIn) { 3304 PHYMOD_IF_ERR_RETURN(wr_ln_tx_dp_s_rstb(0)); 3305 } else if (reset->tx == phymodResetDirectionOut) { 3306 PHYMOD_IF_ERR_RETURN(wr_ln_tx_dp_s_rstb(1)); 3307 } else if (reset->tx == phymodResetDirectionInOut) { 3308 PHYMOD_IF_ERR_RETURN(wr_ln_tx_dp_s_rstb(0)); 3309 PHYMOD_USLEEP(10); 3310 PHYMOD_IF_ERR_RETURN(wr_ln_tx_dp_s_rstb(1)); 3311 } 3312 if (reset->rx == phymodResetDirectionIn) { 3313 PHYMOD_IF_ERR_RETURN(wr_ln_rx_dp_s_rstb(0)); 3314 } else if (reset->rx == phymodResetDirectionOut) { 3315 PHYMOD_IF_ERR_RETURN(wr_ln_rx_dp_s_rstb(1)); 3316 } else if (reset->rx == phymodResetDirectionInOut) { 3317 PHYMOD_IF_ERR_RETURN(wr_ln_rx_dp_s_rstb(0)); 3318 PHYMOD_USLEEP(10); 3319 PHYMOD_IF_ERR_RETURN(wr_ln_rx_dp_s_rstb(1)); 3320 } 3321 } 3322 3323 return PHYMOD_E_NONE; 3324 } 3325 3326 int _dino_phy_reset_get(const phymod_access_t* pa, uint16_t if_side, uint16_t lane, phymod_phy_reset_t* reset) 3327 { 3328 uint16_t dp_reset = 0,__err = 0 ; 3329 3330 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3331 dp_reset = falcon2_dino_rd_ln_tx_dp_s_rstb(); 3332 if (!dp_reset) { 3333 reset->tx = phymodResetDirectionIn; 3334 } else { 3335 reset->tx = phymodResetDirectionOut; 3336 } 3337 dp_reset = falcon2_dino_rd_ln_rx_dp_s_rstb(); 3338 if (!dp_reset) { 3339 reset->rx = phymodResetDirectionIn; 3340 } else { 3341 reset->rx = phymodResetDirectionOut; 3342 } 3343 } else { 3344 dp_reset = rd_ln_tx_dp_s_rstb(); 3345 if (!dp_reset) { 3346 reset->tx = phymodResetDirectionIn; 3347 } else { 3348 reset->tx = phymodResetDirectionOut; 3349 } 3350 dp_reset = rd_ln_rx_dp_s_rstb(); 3351 if (!dp_reset) { 3352 reset->rx = phymodResetDirectionIn; 3353 } else { 3354 reset->rx = phymodResetDirectionOut; 3355 } 3356 } 3357 3358 return PHYMOD_E_NONE; 3359 } 3360 3361 /*Start\Stop the sequencer*/ 3362 int _dino_core_pll_sequencer_restart(const phymod_access_t* pa, uint16_t if_side, 3363 phymod_sequencer_operation_t operation) 3364 { 3365 uint16_t lane = 0; 3366 uint16_t lane_mask = 0; 3367 BCMI_DINO_F25G_PLL_CAL_CTL4r_t fal_pll_ctrl; 3368 BCMI_DINO_PLL_CALCTL5r_t mer_pll_ctrl; 3369 BCMI_DINO_F25G_CORE_PLL_TOP_USER_CTLr_t fal_pll_top_usr_ctrl; 3370 BCMI_DINO_RST_CTL_CORE_DPr_t mer_rst_ctl_core_dp; 3371 3372 PHYMOD_MEMSET(&fal_pll_ctrl, 0, sizeof(BCMI_DINO_F25G_PLL_CAL_CTL4r_t)); 3373 PHYMOD_MEMSET(&mer_pll_ctrl, 0, sizeof(BCMI_DINO_PLL_CALCTL5r)); 3374 PHYMOD_MEMSET(&fal_pll_top_usr_ctrl, 0, sizeof(BCMI_DINO_F25G_CORE_PLL_TOP_USER_CTLr_t)); 3375 PHYMOD_MEMSET(&mer_rst_ctl_core_dp, 0, sizeof(BCMI_DINO_RST_CTL_CORE_DPr_t)); 3376 3377 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 3378 if (lane_mask == 0) { 3379 lane_mask = DINO_100G_TYPE1_LANE_MASK; 3380 } 3381 3382 for (lane = 0; lane < DINO_MAX_LANE ; lane += DINO_MAX_CORE_LANE) { 3383 if (lane_mask & (DINO_40G_PORT0_LANE_MASK << lane)) { 3384 switch (operation) { 3385 case phymodSeqOpStart: 3386 PHYMOD_IF_ERR_RETURN ( 3387 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 3388 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3389 PHYMOD_IF_ERR_RETURN( 3390 BCMI_DINO_READ_F25G_PLL_CAL_CTL4r(pa, &fal_pll_ctrl)); 3391 BCMI_DINO_F25G_PLL_CAL_CTL4r_PLL_SEQ_STARTf_SET(fal_pll_ctrl,1); 3392 PHYMOD_IF_ERR_RETURN( 3393 BCMI_DINO_WRITE_F25G_PLL_CAL_CTL4r(pa, fal_pll_ctrl)); 3394 } else { 3395 PHYMOD_IF_ERR_RETURN( 3396 BCMI_DINO_READ_PLL_CALCTL5r(pa, &mer_pll_ctrl)); 3397 BCMI_DINO_PLL_CALCTL5r_PLL_SEQ_STARTf_SET(mer_pll_ctrl, 1); 3398 PHYMOD_IF_ERR_RETURN( 3399 BCMI_DINO_WRITE_PLL_CALCTL5r(pa, mer_pll_ctrl)); 3400 } 3401 break; 3402 case phymodSeqOpStop: 3403 PHYMOD_IF_ERR_RETURN ( 3404 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 3405 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3406 PHYMOD_IF_ERR_RETURN( 3407 BCMI_DINO_READ_F25G_PLL_CAL_CTL4r(pa, &fal_pll_ctrl)); 3408 BCMI_DINO_F25G_PLL_CAL_CTL4r_PLL_SEQ_STARTf_SET(fal_pll_ctrl,0); 3409 PHYMOD_IF_ERR_RETURN( 3410 BCMI_DINO_WRITE_F25G_PLL_CAL_CTL4r(pa, fal_pll_ctrl)); 3411 } else { 3412 PHYMOD_IF_ERR_RETURN( 3413 BCMI_DINO_READ_PLL_CALCTL5r(pa, &mer_pll_ctrl)); 3414 BCMI_DINO_PLL_CALCTL5r_PLL_SEQ_STARTf_SET(mer_pll_ctrl, 0); 3415 PHYMOD_IF_ERR_RETURN( 3416 BCMI_DINO_WRITE_PLL_CALCTL5r(pa, mer_pll_ctrl)); 3417 } 3418 3419 break; 3420 case phymodSeqOpRestart: 3421 PHYMOD_IF_ERR_RETURN ( 3422 _dino_set_slice_reg (pa, DINO_SLICE_UNICAST, if_side, lane)); 3423 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3424 PHYMOD_IF_ERR_RETURN( 3425 BCMI_DINO_READ_F25G_CORE_PLL_TOP_USER_CTLr(pa, &fal_pll_top_usr_ctrl)); 3426 BCMI_DINO_F25G_CORE_PLL_TOP_USER_CTLr_CORE_DP_S_RSTBf_SET(fal_pll_top_usr_ctrl, 0); 3427 PHYMOD_IF_ERR_RETURN ( 3428 BCMI_DINO_WRITE_F25G_CORE_PLL_TOP_USER_CTLr(pa, fal_pll_top_usr_ctrl)); 3429 PHYMOD_USLEEP(1000); 3430 PHYMOD_IF_ERR_RETURN( 3431 BCMI_DINO_READ_F25G_CORE_PLL_TOP_USER_CTLr(pa, &fal_pll_top_usr_ctrl)); 3432 BCMI_DINO_F25G_CORE_PLL_TOP_USER_CTLr_CORE_DP_S_RSTBf_SET(fal_pll_top_usr_ctrl, 1); 3433 PHYMOD_IF_ERR_RETURN ( 3434 BCMI_DINO_WRITE_F25G_CORE_PLL_TOP_USER_CTLr(pa, fal_pll_top_usr_ctrl)); 3435 3436 } else { 3437 PHYMOD_IF_ERR_RETURN( 3438 BCMI_DINO_READ_RST_CTL_CORE_DPr(pa, &mer_rst_ctl_core_dp)); 3439 BCMI_DINO_RST_CTL_CORE_DPr_CORE_DP_S_RSTBf_SET(mer_rst_ctl_core_dp, 0); 3440 PHYMOD_IF_ERR_RETURN( 3441 BCMI_DINO_WRITE_RST_CTL_CORE_DPr(pa, mer_rst_ctl_core_dp)); 3442 PHYMOD_USLEEP(1000); 3443 PHYMOD_IF_ERR_RETURN( 3444 BCMI_DINO_READ_RST_CTL_CORE_DPr(pa, &mer_rst_ctl_core_dp)); 3445 BCMI_DINO_RST_CTL_CORE_DPr_CORE_DP_S_RSTBf_SET(mer_rst_ctl_core_dp, 1); 3446 PHYMOD_IF_ERR_RETURN( 3447 BCMI_DINO_WRITE_RST_CTL_CORE_DPr(pa, mer_rst_ctl_core_dp)); 3448 } 3449 3450 break; 3451 default: 3452 return PHYMOD_E_PARAM; 3453 } 3454 } 3455 } 3456 PHYMOD_IF_ERR_RETURN ( 3457 _dino_set_slice_reg (pa, DINO_SLICE_RESET, DINO_IF_LINE, 0)); 3458 3459 return PHYMOD_E_NONE; 3460 } 3461 3462 3463 /*TX transmission control*/ 3464 int _dino_phy_tx_lane_control_set(const phymod_access_t* pa, uint16_t if_side, 3465 uint16_t lane, phymod_phy_tx_lane_control_t tx_control) 3466 { 3467 BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_t mer_tx_disable; 3468 BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_t fal_tx_disable; 3469 BCMI_DINO_LN_DP_RST_CTL1r_t ln_dp_rst_ctrl1; 3470 BCMI_DINO_LN_DP_RST_CTL2r_t ln_dp_rst_ctrl2; 3471 PHYMOD_MEMSET(&mer_tx_disable, 0, sizeof(mer_tx_disable)); 3472 PHYMOD_MEMSET(&fal_tx_disable, 0, sizeof(fal_tx_disable)); 3473 PHYMOD_MEMSET(&ln_dp_rst_ctrl1, 0, sizeof(BCMI_DINO_LN_DP_RST_CTL1r_t)); 3474 PHYMOD_MEMSET(&ln_dp_rst_ctrl2, 0, sizeof(BCMI_DINO_LN_DP_RST_CTL2r_t)); 3475 3476 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3477 if (tx_control == phymodTxSquelchOn) { 3478 PHYMOD_IF_ERR_RETURN ( 3479 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, &fal_tx_disable)); 3480 BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_SET(fal_tx_disable, 1); 3481 BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_SET(fal_tx_disable, 1); 3482 PHYMOD_IF_ERR_RETURN ( 3483 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, fal_tx_disable)); 3484 } else if (tx_control == phymodTxSquelchOff) { 3485 PHYMOD_IF_ERR_RETURN ( 3486 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, &fal_tx_disable)); 3487 BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_SET(fal_tx_disable, 1); 3488 BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_SET(fal_tx_disable, 0); 3489 PHYMOD_IF_ERR_RETURN ( 3490 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, fal_tx_disable)); 3491 } else if (tx_control == phymodTxReset) { 3492 if (if_side == DINO_IF_LINE) { 3493 PHYMOD_IF_ERR_RETURN ( 3494 BCMI_DINO_READ_LN_DP_RST_CTL2r(pa, &ln_dp_rst_ctrl2)); 3495 BCMI_DINO_LN_DP_RST_CTL2r_MUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl2, (1 << lane)); 3496 PHYMOD_IF_ERR_RETURN ( 3497 BCMI_DINO_WRITE_LN_DP_RST_CTL2r(pa, ln_dp_rst_ctrl2)); 3498 } else { 3499 PHYMOD_IF_ERR_RETURN ( 3500 BCMI_DINO_READ_LN_DP_RST_CTL1r(pa, &ln_dp_rst_ctrl1)); 3501 BCMI_DINO_LN_DP_RST_CTL1r_DEMUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl1, (1 << lane)); 3502 PHYMOD_IF_ERR_RETURN ( 3503 BCMI_DINO_WRITE_LN_DP_RST_CTL1r(pa, ln_dp_rst_ctrl1)); 3504 } 3505 } else { 3506 return PHYMOD_E_UNAVAIL; 3507 } 3508 } else { 3509 if (tx_control == phymodTxSquelchOn) { 3510 PHYMOD_IF_ERR_RETURN ( 3511 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL1_PER_LANEr(pa, &mer_tx_disable)); 3512 BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_SET(mer_tx_disable, 1); 3513 BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_SET(mer_tx_disable, 1); 3514 PHYMOD_IF_ERR_RETURN ( 3515 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL1_PER_LANEr(pa, mer_tx_disable)); 3516 } else if (tx_control == phymodTxSquelchOff) { 3517 PHYMOD_IF_ERR_RETURN ( 3518 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL1_PER_LANEr(pa, &mer_tx_disable)); 3519 BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_SET(mer_tx_disable, 1); 3520 BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_SET(mer_tx_disable, 0); 3521 PHYMOD_IF_ERR_RETURN ( 3522 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL1_PER_LANEr(pa, mer_tx_disable)); 3523 } else if (tx_control == phymodTxReset) { 3524 if (if_side == DINO_IF_LINE) { 3525 PHYMOD_IF_ERR_RETURN ( 3526 BCMI_DINO_READ_LN_DP_RST_CTL2r(pa, &ln_dp_rst_ctrl2)); 3527 BCMI_DINO_LN_DP_RST_CTL2r_MUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl2, (1 << lane)); 3528 PHYMOD_IF_ERR_RETURN ( 3529 BCMI_DINO_WRITE_LN_DP_RST_CTL2r(pa, ln_dp_rst_ctrl2)); 3530 } else { 3531 PHYMOD_IF_ERR_RETURN ( 3532 BCMI_DINO_READ_LN_DP_RST_CTL1r(pa, &ln_dp_rst_ctrl1)); 3533 BCMI_DINO_LN_DP_RST_CTL1r_DEMUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl1, (1 << lane)); 3534 PHYMOD_IF_ERR_RETURN ( 3535 BCMI_DINO_WRITE_LN_DP_RST_CTL1r(pa, ln_dp_rst_ctrl1)); 3536 } 3537 } else { 3538 return PHYMOD_E_UNAVAIL; 3539 } 3540 } 3541 return PHYMOD_E_NONE; 3542 } 3543 3544 int _dino_phy_tx_lane_control_get(const phymod_access_t* pa, uint16_t if_side, 3545 uint16_t lane, phymod_phy_tx_lane_control_t* tx_control) 3546 { 3547 uint16_t tx_dis_frc = 0, tx_dis_frc_val = 0; 3548 BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_t mer_tx_disable; 3549 BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_t fal_tx_disable; 3550 PHYMOD_MEMSET(&mer_tx_disable, 0, sizeof(mer_tx_disable)); 3551 PHYMOD_MEMSET(&fal_tx_disable, 0, sizeof(fal_tx_disable)); 3552 3553 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3554 PHYMOD_IF_ERR_RETURN ( 3555 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL1_PER_LANEr(pa, &fal_tx_disable)); 3556 if (*tx_control == phymodTxSquelchOn || *tx_control == phymodTxSquelchOff) { 3557 tx_dis_frc = BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_GET(fal_tx_disable); 3558 tx_dis_frc_val = BCMI_DINO_FALCON_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_GET(fal_tx_disable); 3559 if (tx_dis_frc && tx_dis_frc_val) { 3560 *tx_control = phymodTxSquelchOn; 3561 } else { 3562 *tx_control = phymodTxSquelchOff; 3563 } 3564 } else { 3565 return PHYMOD_E_UNAVAIL; 3566 } 3567 } else { 3568 PHYMOD_IF_ERR_RETURN ( 3569 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL1_PER_LANEr(pa, &mer_tx_disable)); 3570 if (*tx_control == phymodTxSquelchOn || *tx_control == phymodTxSquelchOff) { 3571 tx_dis_frc = BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCf_GET(mer_tx_disable); 3572 tx_dis_frc_val = BCMI_DINO_MERLIN_IF_PER_LN_CTL1_PER_LANEr_PMD_TX_DISABLE_FRCVALf_GET(mer_tx_disable); 3573 if (tx_dis_frc && tx_dis_frc_val) { 3574 *tx_control = phymodTxSquelchOn; 3575 } else { 3576 *tx_control = phymodTxSquelchOff; 3577 } 3578 } else { 3579 return PHYMOD_E_UNAVAIL; 3580 } 3581 } 3582 return PHYMOD_E_NONE; 3583 } 3584 3585 /*Rx control*/ 3586 int _dino_phy_rx_lane_control_set(const phymod_access_t* pa, uint16_t if_side, 3587 uint16_t lane, phymod_phy_rx_lane_control_t rx_control) 3588 { 3589 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_t mer_power; 3590 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_t fal_power; 3591 BCMI_DINO_LN_DP_RST_CTL1r_t ln_dp_rst_ctrl1; 3592 BCMI_DINO_LN_DP_RST_CTL2r_t ln_dp_rst_ctrl2; 3593 PHYMOD_MEMSET(&mer_power, 0 , sizeof(mer_power)); 3594 PHYMOD_MEMSET(&fal_power, 0 , sizeof(fal_power)); 3595 PHYMOD_MEMSET(&ln_dp_rst_ctrl1, 0, sizeof(BCMI_DINO_LN_DP_RST_CTL1r_t)); 3596 PHYMOD_MEMSET(&ln_dp_rst_ctrl2, 0, sizeof(BCMI_DINO_LN_DP_RST_CTL2r_t)); 3597 3598 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3599 if (rx_control == phymodRxSquelchOff) { 3600 PHYMOD_IF_ERR_RETURN ( 3601 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL2_PER_LANEr(pa, &fal_power)); 3602 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(fal_power, 0); 3603 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(fal_power, 0); 3604 PHYMOD_IF_ERR_RETURN ( 3605 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL2_PER_LANEr(pa, fal_power)); 3606 3607 } else if (rx_control == phymodRxSquelchOn) { 3608 PHYMOD_IF_ERR_RETURN ( 3609 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL2_PER_LANEr(pa, &fal_power)); 3610 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(fal_power, 1); 3611 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(fal_power, 1); 3612 PHYMOD_IF_ERR_RETURN ( 3613 BCMI_DINO_WRITE_FALCON_IF_PER_LN_CTL2_PER_LANEr(pa, fal_power)); 3614 3615 } else if (rx_control == phymodRxReset) { 3616 if (if_side == DINO_IF_LINE) { 3617 PHYMOD_IF_ERR_RETURN ( 3618 BCMI_DINO_READ_LN_DP_RST_CTL1r(pa, &ln_dp_rst_ctrl1)); 3619 BCMI_DINO_LN_DP_RST_CTL1r_DEMUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl1, (1 << lane)); 3620 PHYMOD_IF_ERR_RETURN ( 3621 BCMI_DINO_WRITE_LN_DP_RST_CTL1r(pa, ln_dp_rst_ctrl1)); 3622 } else { 3623 PHYMOD_IF_ERR_RETURN ( 3624 BCMI_DINO_READ_LN_DP_RST_CTL2r(pa, &ln_dp_rst_ctrl2)); 3625 BCMI_DINO_LN_DP_RST_CTL2r_MUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl2, (1 << lane)); 3626 PHYMOD_IF_ERR_RETURN ( 3627 BCMI_DINO_WRITE_LN_DP_RST_CTL2r(pa, ln_dp_rst_ctrl2)); 3628 } 3629 } else { 3630 return PHYMOD_E_UNAVAIL; 3631 } 3632 } else { 3633 if (rx_control == phymodRxSquelchOff) { 3634 PHYMOD_IF_ERR_RETURN ( 3635 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL2_PER_LANEr(pa, &mer_power)); 3636 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(mer_power,0); 3637 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(mer_power, 0); 3638 PHYMOD_IF_ERR_RETURN ( 3639 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL2_PER_LANEr(pa, mer_power)); 3640 } else if (rx_control == phymodRxSquelchOn) { 3641 PHYMOD_IF_ERR_RETURN ( 3642 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL2_PER_LANEr(pa, &mer_power)); 3643 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_SET(mer_power, 1); 3644 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_SET(mer_power,1); 3645 PHYMOD_IF_ERR_RETURN ( 3646 BCMI_DINO_WRITE_MERLIN_IF_PER_LN_CTL2_PER_LANEr(pa, mer_power)); 3647 } else if (rx_control == phymodRxReset) { 3648 if (if_side == DINO_IF_LINE) { 3649 PHYMOD_IF_ERR_RETURN ( 3650 BCMI_DINO_READ_LN_DP_RST_CTL1r(pa, &ln_dp_rst_ctrl1)); 3651 BCMI_DINO_LN_DP_RST_CTL1r_DEMUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl1, (1 << lane)); 3652 PHYMOD_IF_ERR_RETURN ( 3653 BCMI_DINO_WRITE_LN_DP_RST_CTL1r(pa, ln_dp_rst_ctrl1)); 3654 } else { 3655 PHYMOD_IF_ERR_RETURN ( 3656 BCMI_DINO_READ_LN_DP_RST_CTL2r(pa, &ln_dp_rst_ctrl2)); 3657 BCMI_DINO_LN_DP_RST_CTL2r_MUX_ILANE_DP_RSTBf_SET(ln_dp_rst_ctrl2, (1 << lane)); 3658 PHYMOD_IF_ERR_RETURN ( 3659 BCMI_DINO_WRITE_LN_DP_RST_CTL2r(pa, ln_dp_rst_ctrl2)); 3660 } 3661 } else { 3662 return PHYMOD_E_UNAVAIL; 3663 } 3664 } 3665 3666 return PHYMOD_E_NONE; 3667 } 3668 3669 int _dino_phy_rx_lane_control_get(const phymod_access_t* pa, uint16_t if_side, 3670 uint16_t lane, phymod_phy_rx_lane_control_t* rx_control) 3671 { 3672 uint16_t force = 0, pwr = 0; 3673 BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_t mer_power; 3674 BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_t fal_power; 3675 PHYMOD_MEMSET(&mer_power, 0 , sizeof(mer_power)); 3676 PHYMOD_MEMSET(&fal_power, 0 , sizeof(fal_power)); 3677 3678 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3679 PHYMOD_IF_ERR_RETURN ( 3680 BCMI_DINO_READ_FALCON_IF_PER_LN_CTL2_PER_LANEr(pa, &fal_power)); 3681 if (*rx_control == phymodRxSquelchOn || *rx_control == phymodRxSquelchOff) { 3682 force = BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_GET(fal_power); 3683 pwr = BCMI_DINO_FALCON_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_GET(fal_power); 3684 if (force && pwr) { 3685 *rx_control = phymodRxSquelchOn; 3686 } else { 3687 *rx_control = phymodRxSquelchOff; 3688 } 3689 } else { 3690 return PHYMOD_E_UNAVAIL; 3691 } 3692 } else { 3693 PHYMOD_IF_ERR_RETURN ( 3694 BCMI_DINO_READ_MERLIN_IF_PER_LN_CTL2_PER_LANEr(pa, &mer_power)); 3695 if (*rx_control == phymodRxSquelchOn || *rx_control == phymodRxSquelchOff) { 3696 force = BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCf_GET(mer_power); 3697 pwr = BCMI_DINO_MERLIN_IF_PER_LN_CTL2_PER_LANEr_PMD_LN_RX_H_PWRDN_FRCVALf_GET(mer_power); 3698 if (force && pwr) { 3699 *rx_control = phymodRxSquelchOn; 3700 } else { 3701 *rx_control = phymodRxSquelchOff; 3702 } 3703 } else { 3704 return PHYMOD_E_UNAVAIL; 3705 } 3706 } 3707 3708 return PHYMOD_E_NONE; 3709 } 3710 3711 /*Set\Get TX Parameters*/ 3712 int _dino_phy_tx_set(const phymod_access_t* pa, uint16_t if_side, 3713 uint16_t lane, const phymod_tx_t* tx) 3714 { 3715 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3716 PHYMOD_DEBUG_VERBOSE(("Falcon TXFIR set\n")); 3717 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_tx_afe(pa, TX_AFE_PRE, (int8_t)tx->pre)); 3718 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_tx_afe(pa, TX_AFE_MAIN, (int8_t)tx->main)); 3719 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_tx_afe(pa, TX_AFE_POST1, (int8_t)tx->post)); 3720 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_tx_afe(pa, TX_AFE_POST2, (int8_t)tx->post2)); 3721 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_tx_afe(pa, TX_AFE_POST3, (int8_t)tx->post3)); 3722 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_tx_afe(pa, TX_AFE_AMP, (int8_t)tx->amp)); 3723 } else { 3724 PHYMOD_DEBUG_VERBOSE(("Merlin TXFIR set\n")); 3725 PHYMOD_IF_ERR_RETURN(merlin_dino_apply_txfir_cfg(pa, tx->pre, tx->main, tx->post, tx->post2)); 3726 } 3727 return PHYMOD_E_NONE; 3728 } 3729 3730 int _dino_phy_tx_get(const phymod_access_t* pa, uint16_t if_side, 3731 uint16_t lane, phymod_tx_t* tx) 3732 { 3733 int8_t value = 0; 3734 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3735 PHYMOD_DEBUG_VERBOSE(("Falcon TXFIR get\n")); 3736 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_tx_afe(pa, TX_AFE_PRE, &value)); 3737 tx->pre = value; 3738 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_tx_afe(pa, TX_AFE_MAIN, &value)); 3739 tx->main = value; 3740 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_tx_afe(pa, TX_AFE_POST1, &value)); 3741 tx->post = value; 3742 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_tx_afe(pa, TX_AFE_POST2, &value)); 3743 tx->post2 = value; 3744 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_tx_afe(pa, TX_AFE_POST3, &value)); 3745 tx->post3 = value; 3746 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_tx_afe(pa, TX_AFE_AMP, &value)); 3747 tx->amp = value; 3748 } else { 3749 PHYMOD_DEBUG_VERBOSE(("Merlin TXFIR get\n")); 3750 PHYMOD_IF_ERR_RETURN(merlin_dino_read_tx_afe(pa, TX_AFE_PRE, &value)); 3751 tx->pre = value; 3752 PHYMOD_IF_ERR_RETURN(merlin_dino_read_tx_afe(pa, TX_AFE_MAIN, &value)); 3753 tx->main = value; 3754 PHYMOD_IF_ERR_RETURN(merlin_dino_read_tx_afe(pa, TX_AFE_POST1, &value)); 3755 tx->post = value; 3756 PHYMOD_IF_ERR_RETURN(merlin_dino_read_tx_afe(pa, TX_AFE_POST2, &value)); 3757 tx->post2 = value; 3758 } 3759 return PHYMOD_E_NONE; 3760 } 3761 3762 /*Set\Get RX Parameters*/ 3763 int _dino_phy_rx_set(const phymod_access_t* pa, uint16_t if_side, 3764 uint16_t lane, const phymod_rx_t* rx) 3765 { 3766 uint16_t indx = 0; 3767 uint8_t MAX_MERLIN_DFES_TAPS = 5; 3768 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3769 /* FALCON RXFIR set */ 3770 PHYMOD_DEBUG_VERBOSE(("Falcon RXFIR set\n")); 3771 3772 /*params check*/ 3773 for (indx = 0 ; indx < PHYMOD_NUM_DFE_TAPS; indx++){ 3774 if(rx->dfe[indx].enable && (rx->num_of_dfe_taps > PHYMOD_NUM_DFE_TAPS)) { 3775 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal number of DFEs to set"))); 3776 } 3777 } 3778 3779 /*vga set*/ 3780 /* first stop the rx adaption */ 3781 PHYMOD_IF_ERR_RETURN(falcon2_dino_stop_rx_adaptation(pa, 1)); 3782 if (rx->vga.enable) { 3783 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_rx_afe(pa, RX_AFE_VGA, rx->vga.value)); 3784 } 3785 /*dfe set*/ 3786 for (indx = 0 ; indx < PHYMOD_NUM_DFE_TAPS; indx++){ 3787 if(rx->dfe[indx].enable){ 3788 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_rx_afe(pa, RX_AFE_DFE1+indx, rx->dfe[indx].value)); 3789 } 3790 } 3791 3792 /*peaking filter set*/ 3793 if(rx->peaking_filter.enable){ 3794 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_rx_afe(pa, RX_AFE_PF, rx->peaking_filter.value)); 3795 } 3796 3797 if(rx->low_freq_peaking_filter.enable){ 3798 PHYMOD_IF_ERR_RETURN(falcon2_dino_write_rx_afe(pa, RX_AFE_PF2, rx->low_freq_peaking_filter.value)); 3799 } 3800 } else { 3801 /* MERLIN RXFIR set*/ 3802 PHYMOD_DEBUG_VERBOSE(("Merlin RXFIR set\n")); 3803 3804 /*params check*/ 3805 for (indx = 0 ; indx < MAX_MERLIN_DFES_TAPS; indx++){ 3806 if(rx->dfe[indx].enable && (rx->num_of_dfe_taps > MAX_MERLIN_DFES_TAPS)) { 3807 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("illegal number of DFEs to set"))); 3808 } 3809 } 3810 3811 /* first stop the rx adaption */ 3812 PHYMOD_IF_ERR_RETURN(merlin_dino_stop_rx_adaptation(pa, 1)); 3813 /*vga set*/ 3814 if (rx->vga.enable) { 3815 PHYMOD_IF_ERR_RETURN(merlin_dino_write_rx_afe(pa, RX_AFE_VGA, rx->vga.value)); 3816 } 3817 /*dfe set*/ 3818 /* PHYMOD_NUM_DFE_TAPS are 14 but MERLING core has 5 only DFEs */ 3819 for (indx = 0 ; indx < MAX_MERLIN_DFES_TAPS; indx++){ 3820 if(rx->dfe[indx].enable){ 3821 PHYMOD_IF_ERR_RETURN(merlin_dino_write_rx_afe(pa, RX_AFE_DFE1+indx, rx->dfe[indx].value)); 3822 } 3823 } 3824 3825 /*peaking filter set*/ 3826 if(rx->peaking_filter.enable){ 3827 PHYMOD_IF_ERR_RETURN(merlin_dino_write_rx_afe(pa, RX_AFE_PF, rx->peaking_filter.value)); 3828 } 3829 3830 if(rx->low_freq_peaking_filter.enable){ 3831 PHYMOD_IF_ERR_RETURN(merlin_dino_write_rx_afe(pa, RX_AFE_PF2, rx->low_freq_peaking_filter.value)); 3832 } 3833 } 3834 return PHYMOD_E_NONE; 3835 } 3836 3837 int _dino_phy_rx_get(const phymod_access_t* pa, uint16_t if_side, 3838 uint16_t lane, phymod_rx_t* rx) 3839 { 3840 uint16_t indx = 0; 3841 int8_t dfe = 0; 3842 int8_t vga = 0; 3843 int8_t pf = 0; 3844 int8_t low_freq_pf = 0; 3845 uint32_t rx_adaptation = 0; 3846 int8_t MAX_MERLIN_DFES_TAPS = 5; 3847 3848 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3849 /* FALCON RXFIR get */ 3850 PHYMOD_DEBUG_VERBOSE(("Falcon RXFIR get\n")); 3851 3852 rx_adaptation = PHYMOD_RX_ADAPTATION_ON_GET(rx); 3853 PHYMOD_IF_ERR_RETURN(falcon2_dino_stop_rx_adaptation(pa, 1)); 3854 3855 /*vga get*/ 3856 rx->num_of_dfe_taps = PHYMOD_NUM_DFE_TAPS; 3857 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_rx_afe(pa, RX_AFE_VGA, &vga)); 3858 rx->vga.value = vga; 3859 rx->vga.enable = 1; 3860 3861 /*dfe get*/ 3862 for (indx = 0 ; indx < PHYMOD_NUM_DFE_TAPS; indx++){ 3863 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_rx_afe(pa, (RX_AFE_DFE1+indx), &dfe)); 3864 rx->dfe[indx].value = dfe; 3865 rx->dfe[indx].enable = 1; 3866 } 3867 3868 /*peaking filter get*/ 3869 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_rx_afe(pa, RX_AFE_PF, &pf)); 3870 rx->peaking_filter.value = pf; 3871 rx->peaking_filter.enable = 1; 3872 PHYMOD_IF_ERR_RETURN(falcon2_dino_read_rx_afe(pa, RX_AFE_PF2, &low_freq_pf)); 3873 rx->low_freq_peaking_filter.value = low_freq_pf; 3874 rx->low_freq_peaking_filter.enable = 1; 3875 3876 if (rx_adaptation) { 3877 PHYMOD_IF_ERR_RETURN(falcon2_dino_stop_rx_adaptation(pa, 0)); 3878 } 3879 } else { 3880 /* MERLIN RXFIR get */ 3881 PHYMOD_DEBUG_VERBOSE(("Merlin RXFIR get\n")); 3882 3883 rx_adaptation = PHYMOD_RX_ADAPTATION_ON_GET(rx); 3884 PHYMOD_IF_ERR_RETURN(merlin_dino_stop_rx_adaptation(pa, 1)); 3885 3886 /*vga get*/ 3887 /* PHYMOD_NUM_DFE_TAPS are 14 but MERLING has only 5 DFEs */ 3888 rx->num_of_dfe_taps = MAX_MERLIN_DFES_TAPS; 3889 PHYMOD_IF_ERR_RETURN(merlin_dino_read_rx_afe(pa, RX_AFE_VGA, &vga)); 3890 rx->vga.value = vga; 3891 rx->vga.enable = 1; 3892 3893 /*dfe get*/ 3894 for (indx = 0 ; indx < MAX_MERLIN_DFES_TAPS; indx++){ 3895 PHYMOD_IF_ERR_RETURN(merlin_dino_read_rx_afe(pa, (RX_AFE_DFE1+indx), &dfe)); 3896 rx->dfe[indx].value = dfe; 3897 rx->dfe[indx].enable = 1; 3898 } 3899 3900 /*peaking filter get*/ 3901 PHYMOD_IF_ERR_RETURN(merlin_dino_read_rx_afe(pa, RX_AFE_PF, &pf)); 3902 rx->peaking_filter.value = pf; 3903 rx->peaking_filter.enable = 1; 3904 PHYMOD_IF_ERR_RETURN(merlin_dino_read_rx_afe(pa, RX_AFE_PF2, &low_freq_pf)); 3905 rx->low_freq_peaking_filter.value = low_freq_pf; 3906 rx->low_freq_peaking_filter.enable = 1; 3907 3908 if (rx_adaptation) { 3909 PHYMOD_IF_ERR_RETURN(merlin_dino_stop_rx_adaptation(pa, 0)); 3910 } 3911 } 3912 return PHYMOD_E_NONE; 3913 } 3914 3915 /*PHY Rx adaptation resume*/ 3916 int _dino_phy_rx_adaptation_resume(const phymod_access_t* pa, uint16_t if_side, uint16_t lane) 3917 { 3918 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 3919 PHYMOD_DEBUG_VERBOSE(("Falcon RX RESUME set\n")); 3920 PHYMOD_IF_ERR_RETURN(falcon2_dino_stop_rx_adaptation(pa, 0)); 3921 } else { 3922 PHYMOD_DEBUG_VERBOSE(("Merlin RX RESUME set\n")); 3923 PHYMOD_IF_ERR_RETURN(merlin_dino_stop_rx_adaptation(pa, 0)); 3924 } 3925 return PHYMOD_E_NONE; 3926 } 3927 3928 int _dino_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en) 3929 { 3930 phymod_phy_inf_config_t config; 3931 uint16_t no_of_ports = 0; 3932 uint32_t flags = 0; 3933 uint16_t if_side = 0; 3934 uint16_t lane_mask = 0; 3935 uint16_t gpreg_data = 0; 3936 uint16_t port_idx = 0; 3937 uint32_t chip_id = 0; 3938 uint32_t rev = 0; 3939 phymod_phy_access_t phy_copy; 3940 BCMI_DINO_FIRMWARE_FEATURESr_t firmware_features; 3941 const phymod_access_t *pa = &phy_copy.access; 3942 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 3943 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 3944 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 3945 PHYMOD_MEMSET(&firmware_features, 0, sizeof(BCMI_DINO_FIRMWARE_FEATURESr_t)); 3946 DINO_GET_INTF_SIDE(phy, if_side); 3947 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 3948 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 3949 PHYMOD_IF_ERR_RETURN( 3950 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 3951 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 3952 3953 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 3954 if (config.data_rate == DINO_SPD_100G || config.data_rate == DINO_SPD_106G || config.data_rate == DINO_SPD_111G) { 3955 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 3956 if (if_side == DINO_IF_LINE) { 3957 gpreg_data &= ~(DINO_LINE_TX_TRAINING_MASK); 3958 gpreg_data |= (cl72_en << DINO_LINE_TX_TRAINING_SHIFT); 3959 } else { 3960 gpreg_data &= ~(DINO_SYS_TX_TRAINING_MASK); 3961 gpreg_data |= (cl72_en << DINO_SYS_TX_TRAINING_SHIFT); 3962 } 3963 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 3964 if ((config.data_rate == DINO_SPD_106G) && 3965 (config.interface_type == phymodInterfaceCR4)) { 3966 PHYMOD_IF_ERR_RETURN( 3967 BCMI_DINO_READ_FIRMWARE_FEATURESr(pa, &firmware_features)); 3968 firmware_features.v[0] &= ~(DINO_FRC_TRAINING_DELAY_MASK); 3969 firmware_features.v[0] |= (DINO_FRC_TRAINING_DELAY_6SEC << DINO_FRC_TRAINING_DELAY_SHIFT); 3970 PHYMOD_IF_ERR_RETURN( 3971 BCMI_DINO_WRITE_FIRMWARE_FEATURESr(pa, firmware_features)); 3972 } 3973 break; 3974 } else if (config.data_rate == DINO_SPD_40G || config.data_rate == DINO_SPD_42G) { 3975 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 3976 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 3977 if (if_side == DINO_IF_LINE) { 3978 gpreg_data &= ~(DINO_LINE_TX_TRAINING_MASK); 3979 gpreg_data |= (cl72_en << DINO_LINE_TX_TRAINING_SHIFT); 3980 } else { 3981 gpreg_data &= ~(DINO_SYS_TX_TRAINING_MASK); 3982 gpreg_data |= (cl72_en << DINO_SYS_TX_TRAINING_SHIFT); 3983 } 3984 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 3985 break; 3986 } else { 3987 continue; 3988 } 3989 } else if (config.data_rate == DINO_SPD_10G || config.data_rate == DINO_SPD_11G || config.data_rate == DINO_SPD_11P18G || config.data_rate == DINO_SPD_1G) { 3990 if ((lane_mask & (0x1 << port_idx))) { 3991 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 3992 if (if_side == DINO_IF_LINE) { 3993 gpreg_data &= ~(DINO_LINE_TX_TRAINING_MASK); 3994 gpreg_data |= (cl72_en << DINO_LINE_TX_TRAINING_SHIFT); 3995 } else { 3996 gpreg_data &= ~(DINO_SYS_TX_TRAINING_MASK); 3997 gpreg_data |= (cl72_en << DINO_SYS_TX_TRAINING_SHIFT); 3998 } 3999 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 4000 break; 4001 } else { 4002 continue; 4003 } 4004 } else { 4005 /* Throw error as un supported mode */ 4006 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("Unsupported mode"))); 4007 } 4008 } 4009 /* Set firmware enable */ 4010 PHYMOD_IF_ERR_RETURN 4011 (_dino_fw_enable(pa)); 4012 4013 return PHYMOD_E_NONE; 4014 } 4015 4016 int _dino_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en) 4017 { 4018 phymod_phy_inf_config_t config; 4019 uint16_t no_of_ports = 0; 4020 uint32_t flags = 0; 4021 uint16_t if_side = 0; 4022 uint16_t lane_mask = 0; 4023 uint16_t gpreg_data = 0; 4024 uint16_t port_idx = 0; 4025 uint32_t chip_id = 0; 4026 uint32_t rev = 0; 4027 phymod_phy_access_t phy_copy; 4028 const phymod_access_t *pa = &phy_copy.access; 4029 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4030 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4031 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4032 DINO_GET_INTF_SIDE(phy, if_side); 4033 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4034 PHYMOD_IF_ERR_RETURN( 4035 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4036 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4037 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4038 4039 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4040 if (config.data_rate == DINO_SPD_100G || config.data_rate == DINO_SPD_106G || config.data_rate == DINO_SPD_111G) { 4041 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4042 break; 4043 } else if (config.data_rate == DINO_SPD_40G || config.data_rate == DINO_SPD_42G) { 4044 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 4045 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 4046 break; 4047 } else { 4048 continue; 4049 } 4050 } else if (config.data_rate == DINO_SPD_10G || config.data_rate == DINO_SPD_11G || config.data_rate == DINO_SPD_11P18G || config.data_rate == DINO_SPD_1G) { 4051 if ((lane_mask & (0x1 << port_idx))) { 4052 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 4053 break; 4054 } 4055 } else { 4056 /* Throw error as un supported mode */ 4057 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("Unsupported mode"))); 4058 } 4059 } 4060 4061 if (if_side == DINO_IF_LINE) { 4062 *cl72_en = (((gpreg_data & DINO_LINE_TX_TRAINING_MASK) >> DINO_LINE_TX_TRAINING_SHIFT) & 0x1); 4063 } else { 4064 *cl72_en = ((gpreg_data & DINO_SYS_TX_TRAINING_MASK) >> DINO_SYS_TX_TRAINING_SHIFT); 4065 } 4066 4067 return PHYMOD_E_NONE; 4068 } 4069 4070 int _dino_phy_cl72_status_get(const phymod_phy_access_t* phy, uint16_t if_side, uint16_t lane, phymod_cl72_status_t* status) 4071 { 4072 uint32_t cl72_en = 0; 4073 BCMI_DINO_CL72_STS1r_t merlin_cl72_sts; 4074 BCMI_DINO_CL93N72_UR_CTL0r_t falcon_cl72_sts; 4075 const phymod_access_t *pa = &phy->access; 4076 PHYMOD_MEMSET(&merlin_cl72_sts, 0, sizeof(BCMI_DINO_CL72_STS1r_t)); 4077 PHYMOD_MEMSET(&falcon_cl72_sts, 0, sizeof(BCMI_DINO_CL93N72_UR_CTL0r_t)); 4078 4079 if (DINO_IS_FALCON_SIDE(if_side, lane)) { 4080 PHYMOD_IF_ERR_RETURN ( 4081 BCMI_DINO_READ_CL93N72_UR_CTL0r(pa, &falcon_cl72_sts)); 4082 status->locked &= BCMI_DINO_CL93N72_UR_CTL0r_CL93N72_RX_SIGNAL_OKf_GET(falcon_cl72_sts); 4083 } else { 4084 PHYMOD_IF_ERR_RETURN ( 4085 BCMI_DINO_READ_CL72_STS1r(pa, &merlin_cl72_sts)); 4086 status->locked &= BCMI_DINO_CL72_STS1r_CL72_SIGNAL_DETECTf_GET(merlin_cl72_sts); 4087 } 4088 4089 PHYMOD_IF_ERR_RETURN 4090 (_dino_phy_cl72_get(phy, &cl72_en)); 4091 4092 status->enabled &= cl72_en; 4093 status->locked &= cl72_en; 4094 4095 return PHYMOD_E_NONE; 4096 } 4097 4098 int _dino_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_config) 4099 { 4100 phymod_phy_inf_config_t config; 4101 uint16_t no_of_ports = 0; 4102 uint32_t flags = 0; 4103 uint16_t if_side = 0; 4104 uint16_t lane_mask = 0; 4105 uint16_t gpreg_data = 0; 4106 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 4107 uint16_t DFE_option = SERDES_DFE_OPTION_NO_DFE; /*default to dfe disable*/ 4108 uint16_t port_idx = 0; 4109 uint32_t chip_id = 0; 4110 uint32_t rev = 0; 4111 phymod_phy_access_t phy_copy; 4112 const phymod_access_t *pa = &phy_copy.access; 4113 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4114 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4115 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4116 DINO_GET_INTF_SIDE(phy, if_side); 4117 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4118 PHYMOD_IF_ERR_RETURN( 4119 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4120 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4121 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4122 4123 4124 if (fw_config.DfeOn == 0){ 4125 DFE_option = SERDES_DFE_OPTION_NO_DFE; 4126 } 4127 if (fw_config.DfeOn == 1 && 4128 fw_config.LpDfeOn == 0 && 4129 fw_config.ForceBrDfe == 0) { 4130 DFE_option = SERDES_DFE_OPTION_DFE; 4131 } 4132 if (fw_config.DfeOn == 1 && 4133 fw_config.LpDfeOn == 0 && 4134 fw_config.ForceBrDfe == 1) { 4135 DFE_option = SERDES_DFE_OPTION_BRDFE; 4136 } 4137 if (fw_config.DfeOn == 1 && 4138 fw_config.LpDfeOn == 1 && 4139 fw_config.ForceBrDfe == 0) { 4140 DFE_option = SERDES_DFE_OPTION_DFE_LP_MODE; 4141 } 4142 4143 switch(fw_config.MediaType) { 4144 case phymodFirmwareMediaTypeOptics: 4145 if (fw_config.UnreliableLos) { 4146 media_type = SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS; 4147 } else { 4148 media_type = SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS; 4149 } 4150 break; 4151 case phymodFirmwareMediaTypeCopperCable: 4152 media_type = SERDES_MEDIA_TYPE_COPPER_CABLE; 4153 break; 4154 case phymodFirmwareMediaTypePcbTraceBackPlane: 4155 media_type = SERDES_MEDIA_TYPE_BACK_PLANE; 4156 break; 4157 default: 4158 break; 4159 } 4160 4161 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4162 if ((config.data_rate == DINO_SPD_100G) || (config.data_rate == DINO_SPD_106G) || (config.data_rate == DINO_SPD_111G)) { 4163 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4164 if (if_side == DINO_IF_LINE) { 4165 gpreg_data &= ~(DINO_LINE_MEDIA_TYPE_MASK); 4166 gpreg_data |= (media_type << DINO_LINE_MEDIA_TYPE_SHIFT); 4167 gpreg_data &= ~(DINO_LINE_DFE_OPTION_MASK); 4168 gpreg_data |= (DFE_option << DINO_LINE_DFE_OPTION_SHIFT); 4169 } else { 4170 gpreg_data &= ~(DINO_SYS_MEDIA_TYPE_MASK); 4171 gpreg_data |= (media_type << DINO_SYS_MEDIA_TYPE_SHIFT); 4172 gpreg_data &= ~(DINO_SYS_DFE_OPTION_MASK); 4173 gpreg_data |= (DFE_option << DINO_SYS_DFE_OPTION_SHIFT); 4174 } 4175 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4176 break; 4177 } else if (config.data_rate == DINO_SPD_40G || config.data_rate == DINO_SPD_42G) { 4178 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 4179 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 4180 if (if_side == DINO_IF_LINE) { 4181 gpreg_data &= ~(DINO_LINE_MEDIA_TYPE_MASK); 4182 gpreg_data |= (media_type << DINO_LINE_MEDIA_TYPE_SHIFT); 4183 gpreg_data &= ~(DINO_LINE_DFE_OPTION_MASK); 4184 gpreg_data |= (DFE_option << DINO_LINE_DFE_OPTION_SHIFT); 4185 } else { 4186 gpreg_data &= ~(DINO_SYS_MEDIA_TYPE_MASK); 4187 gpreg_data |= (media_type << DINO_SYS_MEDIA_TYPE_SHIFT); 4188 gpreg_data &= ~(DINO_SYS_DFE_OPTION_MASK); 4189 gpreg_data |= (DFE_option << DINO_SYS_DFE_OPTION_SHIFT); 4190 } 4191 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 4192 break; 4193 } else { 4194 continue; 4195 } 4196 } else if (config.data_rate == DINO_SPD_10G || config.data_rate == DINO_SPD_11G || config.data_rate == DINO_SPD_11P18G || config.data_rate == DINO_SPD_1G) { 4197 if ((lane_mask & (0x1 << port_idx))) { 4198 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 4199 if (if_side == DINO_IF_LINE) { 4200 gpreg_data &= ~(DINO_LINE_MEDIA_TYPE_MASK); 4201 gpreg_data |= (media_type << DINO_LINE_MEDIA_TYPE_SHIFT); 4202 gpreg_data &= ~(DINO_LINE_DFE_OPTION_MASK); 4203 gpreg_data |= (DFE_option << DINO_LINE_DFE_OPTION_SHIFT); 4204 } else { 4205 gpreg_data &= ~(DINO_SYS_MEDIA_TYPE_MASK); 4206 gpreg_data |= (media_type << DINO_SYS_MEDIA_TYPE_SHIFT); 4207 gpreg_data &= ~(DINO_SYS_DFE_OPTION_MASK); 4208 gpreg_data |= (DFE_option << DINO_SYS_DFE_OPTION_SHIFT); 4209 } 4210 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 4211 break; 4212 } else { 4213 continue; 4214 } 4215 } else { 4216 /* Throw error as un supported mode */ 4217 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("Unsupported mode"))); 4218 } 4219 } 4220 4221 /* Set firmware enable */ 4222 PHYMOD_IF_ERR_RETURN 4223 (_dino_fw_enable(pa)); 4224 4225 return PHYMOD_E_NONE; 4226 } 4227 4228 int _dino_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_config) 4229 { 4230 phymod_phy_inf_config_t config; 4231 uint16_t no_of_ports = 0; 4232 uint32_t flags = 0; 4233 uint16_t if_side = 0; 4234 uint16_t lane_mask = 0; 4235 uint16_t gpreg_data = 0; 4236 uint16_t media_type = SERDES_MEDIA_TYPE_BACK_PLANE; /* Default to Back Plane */ 4237 uint16_t DFE_option = SERDES_DFE_OPTION_NO_DFE; /*default to dfe disable*/ 4238 uint16_t port_idx = 0; 4239 uint32_t chip_id = 0; 4240 uint32_t rev = 0; 4241 phymod_phy_access_t phy_copy; 4242 const phymod_access_t *pa = &phy_copy.access; 4243 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4244 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4245 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4246 DINO_GET_INTF_SIDE(phy, if_side); 4247 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4248 PHYMOD_IF_ERR_RETURN( 4249 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4250 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4251 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4252 4253 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4254 if ((config.data_rate == DINO_SPD_100G) || (config.data_rate == DINO_SPD_106G) || (config.data_rate == DINO_SPD_111G)) { 4255 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4256 if (if_side == DINO_IF_LINE) { 4257 media_type = (gpreg_data & DINO_LINE_MEDIA_TYPE_MASK) >> DINO_LINE_MEDIA_TYPE_SHIFT; 4258 DFE_option = (gpreg_data & DINO_LINE_DFE_OPTION_MASK) >> DINO_LINE_DFE_OPTION_SHIFT; 4259 } else { 4260 media_type = (gpreg_data & DINO_SYS_MEDIA_TYPE_MASK) >> DINO_SYS_MEDIA_TYPE_SHIFT; 4261 DFE_option = (gpreg_data & DINO_SYS_DFE_OPTION_MASK) >> DINO_SYS_DFE_OPTION_SHIFT; 4262 } 4263 break; 4264 } else if (config.data_rate == DINO_SPD_40G || config.data_rate == DINO_SPD_42G) { 4265 if ((lane_mask & (0xf << (port_idx * DINO_MAX_CORE_LANE)))) { 4266 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (port_idx * DINO_MAX_CORE_LANE)), gpreg_data); 4267 if (if_side == DINO_IF_LINE) { 4268 media_type = (gpreg_data & DINO_LINE_MEDIA_TYPE_MASK) >> DINO_LINE_MEDIA_TYPE_SHIFT; 4269 DFE_option = (gpreg_data & DINO_LINE_DFE_OPTION_MASK) >> DINO_LINE_DFE_OPTION_SHIFT; 4270 } else { 4271 media_type = (gpreg_data & DINO_SYS_MEDIA_TYPE_MASK) >> DINO_SYS_MEDIA_TYPE_SHIFT; 4272 DFE_option = (gpreg_data & DINO_SYS_DFE_OPTION_MASK) >> DINO_SYS_DFE_OPTION_SHIFT; 4273 } 4274 break; 4275 } else { 4276 continue; 4277 } 4278 } else if (config.data_rate == DINO_SPD_10G || config.data_rate == DINO_SPD_11G || config.data_rate == DINO_SPD_11P18G || config.data_rate == DINO_SPD_1G) { 4279 if ((lane_mask & (0x1 << port_idx))) { 4280 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + port_idx), gpreg_data); 4281 if (if_side == DINO_IF_LINE) { 4282 media_type = (gpreg_data & DINO_LINE_MEDIA_TYPE_MASK) >> DINO_LINE_MEDIA_TYPE_SHIFT; 4283 DFE_option = (gpreg_data & DINO_LINE_DFE_OPTION_MASK) >> DINO_LINE_DFE_OPTION_SHIFT; 4284 } else { 4285 media_type = (gpreg_data & DINO_SYS_MEDIA_TYPE_MASK) >> DINO_SYS_MEDIA_TYPE_SHIFT; 4286 DFE_option = (gpreg_data & DINO_SYS_DFE_OPTION_MASK) >> DINO_SYS_DFE_OPTION_SHIFT; 4287 } 4288 break; 4289 } else { 4290 continue; 4291 } 4292 } else { 4293 /* Throw error as un supported mode */ 4294 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, (_PHYMOD_MSG("Unsupported mode"))); 4295 } 4296 } 4297 4298 switch (DFE_option) { 4299 case SERDES_DFE_OPTION_NO_DFE: 4300 fw_config->DfeOn = 0; 4301 fw_config->ForceBrDfe = 0; 4302 fw_config->LpDfeOn = 0; 4303 break; 4304 case SERDES_DFE_OPTION_DFE: 4305 fw_config->DfeOn = 1; 4306 fw_config->ForceBrDfe = 0; 4307 fw_config->LpDfeOn = 0; 4308 break; 4309 case SERDES_DFE_OPTION_BRDFE: 4310 fw_config->DfeOn = 1; 4311 fw_config->ForceBrDfe = 1; 4312 fw_config->LpDfeOn = 0; 4313 break; 4314 case SERDES_DFE_OPTION_DFE_LP_MODE: 4315 fw_config->DfeOn = 1; 4316 fw_config->ForceBrDfe = 0; 4317 fw_config->LpDfeOn = 1; 4318 break; 4319 default: 4320 break; 4321 } 4322 4323 fw_config->UnreliableLos = 0; 4324 switch (media_type) { 4325 case SERDES_MEDIA_TYPE_BACK_PLANE: 4326 fw_config->MediaType = phymodFirmwareMediaTypePcbTraceBackPlane; 4327 break; 4328 case SERDES_MEDIA_TYPE_COPPER_CABLE: 4329 fw_config->MediaType = phymodFirmwareMediaTypeCopperCable; 4330 break; 4331 case SERDES_MEDIA_TYPE_OPTICAL_RELIABLE_LOS: 4332 fw_config->MediaType = phymodFirmwareMediaTypeOptics; 4333 break; 4334 case SERDES_MEDIA_TYPE_OPTICAL_UNRELIABLE_LOS: 4335 fw_config->MediaType = phymodFirmwareMediaTypeOptics; 4336 fw_config->UnreliableLos = 1; 4337 break; 4338 default: 4339 break; 4340 } 4341 4342 return PHYMOD_E_NONE; 4343 } 4344 4345 int _dino_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an) 4346 { 4347 phymod_phy_inf_config_t config; 4348 uint16_t lane_mask = 0; 4349 uint32_t flags = 0; 4350 uint16_t no_of_ports = 0; 4351 phymod_phy_access_t phy_copy; 4352 uint16_t gpreg_data = 0; 4353 uint16_t gpreg_f_data = 0; 4354 uint16_t sw_gpreg_data = 0; 4355 uint16_t mst_lane_reg_data = 0; 4356 uint16_t port_idx = 0; 4357 uint16_t an_mst_lane = 0; 4358 uint32_t chip_id = 0; 4359 uint32_t rev = 0; 4360 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 4361 BCMI_DINO_AN_LN_SELr_t an_mst_lane_sel; 4362 BCMI_DINO_MODECTL0r_t mode_ctrl0; 4363 const phymod_access_t *pa = &phy->access; 4364 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4365 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4366 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4367 PHYMOD_MEMSET(&an_mst_lane_sel, 0, sizeof(BCMI_DINO_AN_LN_SELr_t)); 4368 PHYMOD_MEMSET(&mode_ctrl0, 0, sizeof(BCMI_DINO_MODECTL0r_t)); 4369 4370 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4371 4372 PHYMOD_IF_ERR_RETURN( 4373 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4374 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4375 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4376 4377 if ((config.interface_type != phymodInterfaceKR4) && 4378 (config.interface_type != phymodInterfaceCR4) && 4379 (config.interface_type != phymodInterfaceCR10)) { 4380 return PHYMOD_E_NONE; 4381 } 4382 4383 if (an->an_mode == phymod_AN_MODE_CL73) { 4384 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4385 if ((config.data_rate == DINO_SPD_100G) && 4386 ((config.interface_type == phymodInterfaceKR4) || 4387 (config.interface_type == phymodInterfaceCR4) || 4388 (config.interface_type == phymodInterfaceCR10))) { 4389 /* Read the master lane from scratch register and program the master lane */ 4390 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 4391 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 4392 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4393 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_100G_MASK) >> DINO_AN_MST_LANE_100G_SHIFT; 4394 PHYMOD_IF_ERR_RETURN( 4395 BCMI_DINO_READ_AN_LN_SELr(pa, &an_mst_lane_sel)); 4396 if (dev_op_mode == DINO_DEV_OP_MODE_PT) { 4397 if (((lane_mask == DINO_100G_TYPE1_LANE_MASK) || ((lane_mask & 0xf) == 0xf)) || 4398 ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) || 4399 ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc))) { 4400 if ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) { 4401 an_mst_lane += 1; 4402 } 4403 if ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc)) { 4404 an_mst_lane += 2; 4405 } 4406 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4407 gpreg_f_data &= ~(DINO_100G_CR10_AN_INSTANCE_MASK); 4408 gpreg_f_data |= (an_mst_lane/DINO_MAX_CORE_LANE) << DINO_100G_CR10_AN_INSTANCE_SHIFT; 4409 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4410 switch (an_mst_lane/DINO_MAX_CORE_LANE) { 4411 case 0: 4412 BCMI_DINO_AN_LN_SELr_MP0_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, (an_mst_lane % DINO_MAX_CORE_LANE)); 4413 break; 4414 case 1: 4415 BCMI_DINO_AN_LN_SELr_MP1_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, (an_mst_lane % DINO_MAX_CORE_LANE)); 4416 break; 4417 case 2: 4418 BCMI_DINO_AN_LN_SELr_MP2_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, (an_mst_lane % DINO_MAX_CORE_LANE)); 4419 break; 4420 } 4421 } 4422 } else { 4423 BCMI_DINO_AN_LN_SELr_MP0_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, (an_mst_lane % DINO_MAX_CORE_LANE)); 4424 } 4425 4426 PHYMOD_IF_ERR_RETURN( 4427 BCMI_DINO_WRITE_AN_LN_SELr(pa, an_mst_lane_sel)); 4428 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4429 gpreg_data &= ~(DINO_AN_MASK); 4430 gpreg_data |= ((an->enable)<< DINO_AN_SHIFT); 4431 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4432 if (an->enable) { 4433 PHYMOD_IF_ERR_RETURN( 4434 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4435 if (dev_op_mode == DINO_DEV_OP_MODE_PT) { 4436 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 4437 } else { 4438 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 0); 4439 } 4440 PHYMOD_IF_ERR_RETURN( 4441 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4442 } else { 4443 PHYMOD_IF_ERR_RETURN( 4444 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4445 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 4446 PHYMOD_IF_ERR_RETURN( 4447 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4448 } 4449 break; 4450 } else if ((config.data_rate == DINO_SPD_40G) && 4451 (lane_mask == DINO_40G_PORT0_LANE_MASK) && 4452 ((config.interface_type == phymodInterfaceKR4) || 4453 (config.interface_type == phymodInterfaceCR4))) { 4454 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4455 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P0_MASK) >> DINO_AN_MST_LANE_40G_P0_SHIFT; 4456 PHYMOD_IF_ERR_RETURN( 4457 BCMI_DINO_READ_AN_LN_SELr(pa, &an_mst_lane_sel)); 4458 BCMI_DINO_AN_LN_SELr_MP0_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, an_mst_lane); 4459 PHYMOD_IF_ERR_RETURN( 4460 BCMI_DINO_WRITE_AN_LN_SELr(pa, an_mst_lane_sel)); 4461 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + DINO_PORT0), gpreg_data); 4462 gpreg_data &= ~(DINO_AN_MASK); 4463 gpreg_data |= ((an->enable) << DINO_AN_SHIFT); 4464 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + DINO_PORT0), gpreg_data); 4465 if (an->enable) { 4466 PHYMOD_IF_ERR_RETURN( 4467 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4468 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 0); 4469 PHYMOD_IF_ERR_RETURN( 4470 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4471 } else { 4472 PHYMOD_IF_ERR_RETURN( 4473 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4474 BCMI_DINO_MODECTL0r_UDMS_MP0_ENf_SET(mode_ctrl0, 1); 4475 PHYMOD_IF_ERR_RETURN( 4476 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4477 } 4478 break; 4479 } else if ((config.data_rate == DINO_SPD_40G) && 4480 (lane_mask == DINO_40G_PORT1_LANE_MASK) && 4481 ((config.interface_type == phymodInterfaceKR4) || 4482 (config.interface_type == phymodInterfaceCR4))) { 4483 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4484 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P1_MASK) >> DINO_AN_MST_LANE_40G_P1_SHIFT; 4485 PHYMOD_IF_ERR_RETURN( 4486 BCMI_DINO_READ_AN_LN_SELr(pa, &an_mst_lane_sel)); 4487 BCMI_DINO_AN_LN_SELr_MP1_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, an_mst_lane); 4488 PHYMOD_IF_ERR_RETURN( 4489 BCMI_DINO_WRITE_AN_LN_SELr(pa, an_mst_lane_sel)); 4490 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (DINO_PORT1 * DINO_MAX_CORE_LANE)), gpreg_data); 4491 gpreg_data &= ~(DINO_AN_MASK); 4492 gpreg_data |= ((an->enable) << DINO_AN_SHIFT); 4493 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (DINO_PORT1 * DINO_MAX_CORE_LANE)), gpreg_data); 4494 if (an->enable) { 4495 PHYMOD_IF_ERR_RETURN( 4496 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4497 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 0); 4498 PHYMOD_IF_ERR_RETURN( 4499 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4500 } else { 4501 PHYMOD_IF_ERR_RETURN( 4502 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4503 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 1); 4504 PHYMOD_IF_ERR_RETURN( 4505 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4506 } 4507 BCMI_DINO_MODECTL0r_UDMS_MP1_ENf_SET(mode_ctrl0, 0); 4508 break; 4509 } else if ((config.data_rate == DINO_SPD_40G) && 4510 (lane_mask == DINO_40G_PORT2_LANE_MASK) && 4511 ((config.interface_type == phymodInterfaceKR4) || 4512 (config.interface_type == phymodInterfaceCR4))) { 4513 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4514 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P2_MASK) >> DINO_AN_MST_LANE_40G_P2_SHIFT; 4515 PHYMOD_IF_ERR_RETURN( 4516 BCMI_DINO_READ_AN_LN_SELr(pa, &an_mst_lane_sel)); 4517 BCMI_DINO_AN_LN_SELr_MP2_AN_LANE_SEL0TO3f_SET(an_mst_lane_sel, an_mst_lane); 4518 PHYMOD_IF_ERR_RETURN( 4519 BCMI_DINO_WRITE_AN_LN_SELr(pa, an_mst_lane_sel)); 4520 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (DINO_PORT2 * DINO_MAX_CORE_LANE)), gpreg_data); 4521 gpreg_data &= ~(DINO_AN_MASK); 4522 gpreg_data |= ((an->enable) << DINO_AN_SHIFT); 4523 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (DINO_PORT2 * DINO_MAX_CORE_LANE)), gpreg_data); 4524 if (an->enable) { 4525 PHYMOD_IF_ERR_RETURN( 4526 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4527 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 0); 4528 PHYMOD_IF_ERR_RETURN( 4529 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4530 } else { 4531 PHYMOD_IF_ERR_RETURN( 4532 BCMI_DINO_READ_MODECTL0r(pa, &mode_ctrl0)); 4533 BCMI_DINO_MODECTL0r_UDMS_MP2_ENf_SET(mode_ctrl0, 1); 4534 PHYMOD_IF_ERR_RETURN( 4535 BCMI_DINO_WRITE_MODECTL0r(pa, mode_ctrl0)); 4536 } 4537 break; 4538 } 4539 } 4540 } 4541 4542 /*Setting the FW Enable to 1*/ 4543 if ((dev_op_mode == DINO_DEV_OP_MODE_PT) && 4544 (config.data_rate == DINO_SPD_100G) && 4545 (config.interface_type == phymodInterfaceCR10)) { 4546 if (((lane_mask == DINO_100G_TYPE1_LANE_MASK) || ((lane_mask & 0xf) == 0xf)) || 4547 ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) || 4548 ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc))) { 4549 PHYMOD_IF_ERR_RETURN(_dino_fw_enable(pa)); 4550 } 4551 } else { 4552 PHYMOD_IF_ERR_RETURN(_dino_fw_enable(pa)); 4553 } 4554 4555 return PHYMOD_E_NONE; 4556 } 4557 4558 int _dino_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an, uint32_t *an_done) 4559 { 4560 phymod_phy_inf_config_t config; 4561 uint16_t lane_mask = 0; 4562 uint32_t flags = 0; 4563 uint16_t no_of_ports = 0; 4564 uint16_t gpreg_data = 0; 4565 uint16_t port_idx = 0; 4566 uint16_t sw_gpreg_data = 0; 4567 uint16_t mst_lane_reg_data = 0; 4568 uint16_t an_mst_lane = 0; 4569 uint32_t chip_id = 0; 4570 uint32_t rev = 0; 4571 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 4572 phymod_phy_access_t phy_copy; 4573 BCMI_DINO_AN_STSr_t an_sts; 4574 BCMI_DINO_DEV7_SLICE_SLICEr_t an_slice; 4575 const phymod_access_t *pa = &phy->access; 4576 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4577 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4578 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4579 PHYMOD_MEMSET(&an_sts, 0, sizeof(BCMI_DINO_AN_STSr_t)); 4580 PHYMOD_MEMSET(&an_slice, 0, sizeof(BCMI_DINO_DEV7_SLICE_SLICEr_t)); 4581 4582 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4583 4584 PHYMOD_IF_ERR_RETURN( 4585 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4586 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4587 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4588 4589 if ((config.interface_type != phymodInterfaceKR4) && 4590 (config.interface_type != phymodInterfaceCR4) && 4591 (config.interface_type != phymodInterfaceCR10)) { 4592 return PHYMOD_E_NONE; 4593 } 4594 4595 PHYMOD_IF_ERR_RETURN ( 4596 BCMI_DINO_READ_DEV7_SLICE_SLICEr(pa, &an_slice)); 4597 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_0_SELf_SET(an_slice, 0); 4598 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_1_SELf_SET(an_slice, 0); 4599 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_2_SELf_SET(an_slice, 0); 4600 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 0); 4601 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 0); 4602 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 0); 4603 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4604 if ((config.data_rate == DINO_SPD_100G) && 4605 ((config.interface_type == phymodInterfaceKR4) || 4606 (config.interface_type == phymodInterfaceCR4) || 4607 (config.interface_type == phymodInterfaceCR10))) { 4608 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 4609 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_0_ADR, gpreg_data); 4610 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 4611 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4612 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_100G_MASK) >> DINO_AN_MST_LANE_100G_SHIFT; 4613 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 4614 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4615 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_0_SELf_SET(an_slice, 1); 4616 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4617 if (dev_op_mode == DINO_DEV_OP_MODE_PT) { 4618 if (((lane_mask == DINO_100G_TYPE1_LANE_MASK) || ((lane_mask & 0xf) == 0xf)) || 4619 ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) || 4620 ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc))) { 4621 if ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) { 4622 an_mst_lane += 1; 4623 } 4624 if ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc)) { 4625 an_mst_lane += 2; 4626 } 4627 switch(an_mst_lane/DINO_MAX_CORE_LANE) { 4628 case 0: 4629 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4630 break; 4631 case 1: 4632 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4633 break; 4634 case 2: 4635 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4636 break; 4637 } 4638 } 4639 } else { 4640 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4641 } 4642 break; 4643 } else if ((config.data_rate == DINO_SPD_40G) && 4644 (lane_mask == DINO_40G_PORT0_LANE_MASK) && 4645 ((config.interface_type == phymodInterfaceKR4) || 4646 (config.interface_type == phymodInterfaceCR4))) { 4647 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + DINO_PORT0), gpreg_data); 4648 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4649 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P0_MASK) >> DINO_AN_MST_LANE_40G_P0_SHIFT; 4650 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 4651 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4652 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4653 break; 4654 } else if ((config.data_rate == DINO_SPD_40G) && 4655 (lane_mask == DINO_40G_PORT1_LANE_MASK) && 4656 ((config.interface_type == phymodInterfaceKR4) || 4657 (config.interface_type == phymodInterfaceCR4))) { 4658 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (DINO_PORT1 * DINO_MAX_CORE_LANE)), gpreg_data); 4659 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4660 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P1_MASK) >> DINO_AN_MST_LANE_40G_P1_SHIFT; 4661 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 4662 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4663 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4664 break; 4665 } else if ((config.data_rate == DINO_SPD_40G) && 4666 (lane_mask == DINO_40G_PORT2_LANE_MASK) && 4667 ((config.interface_type == phymodInterfaceKR4) || 4668 (config.interface_type == phymodInterfaceCR4))) { 4669 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + (DINO_PORT2 * DINO_MAX_CORE_LANE)), gpreg_data); 4670 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4671 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P2_MASK) >> DINO_AN_MST_LANE_40G_P2_SHIFT; 4672 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 4673 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4674 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 4675 break; 4676 } 4677 } 4678 4679 /* AN enable status */ 4680 an->enable = (gpreg_data & DINO_AN_MASK) >> DINO_AN_SHIFT; 4681 4682 /* AN Mode */ 4683 an->an_mode = phymod_AN_MODE_CL73; 4684 4685 BCMI_DINO_DEV7_SLICE_SLICEr_LANE_SELf_SET(an_slice, (1 << (an_mst_lane % DINO_MAX_CORE_LANE))); 4686 4687 /* Set the AN slice with AN master lane */ 4688 PHYMOD_IF_ERR_RETURN ( 4689 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 4690 4691 /* Read the AN status */ 4692 PHYMOD_IF_ERR_RETURN ( 4693 BCMI_DINO_READ_AN_STSr(pa, &an_sts)); 4694 4695 if (BCMI_DINO_AN_STSr_AUTO_NEGOTIATIONCOMPLETEf_GET(an_sts)) { 4696 *an_done = 1; 4697 } else { 4698 *an_done = 0; 4699 } 4700 4701 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 4702 4703 PHYMOD_IF_ERR_RETURN ( 4704 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 4705 4706 4707 return PHYMOD_E_NONE; 4708 } 4709 4710 int _dino_phy_autoneg_ability_set(const phymod_phy_access_t* phy, dino_an_ability_t *an_ability) 4711 { 4712 phymod_phy_inf_config_t config; 4713 uint16_t lane_mask = 0; 4714 uint32_t flags = 0; 4715 phymod_phy_access_t phy_copy; 4716 uint16_t no_of_ports = 0; 4717 uint16_t sw_gpreg_data = 0; 4718 uint16_t mst_lane_reg_data = 0; 4719 uint16_t gpreg_f_data = 0; 4720 uint16_t port_idx = 0; 4721 uint32_t chip_id = 0; 4722 uint32_t rev = 0; 4723 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 4724 BCMI_DINO_AN_ADVERTISEMENT1r_t an_adv1; 4725 BCMI_DINO_AN_ADVERTISEMENT2r_t an_adv2; 4726 BCMI_DINO_AN_ADVERTISEMENT3r_t an_adv3; 4727 BCMI_DINO_DEV7_SLICE_SLICEr_t an_slice; 4728 const phymod_access_t *pa = &phy->access; 4729 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4730 PHYMOD_MEMSET(&an_adv1, 0, sizeof(BCMI_DINO_AN_ADVERTISEMENT1r_t)); 4731 PHYMOD_MEMSET(&an_adv2, 0, sizeof(BCMI_DINO_AN_ADVERTISEMENT2r_t)); 4732 PHYMOD_MEMSET(&an_adv3, 0, sizeof(BCMI_DINO_AN_ADVERTISEMENT3r_t)); 4733 PHYMOD_MEMSET(&an_slice, 0, sizeof(BCMI_DINO_DEV7_SLICE_SLICEr_t)); 4734 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4735 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4736 4737 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4738 4739 PHYMOD_IF_ERR_RETURN( 4740 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4741 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4742 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4743 4744 if ((config.interface_type != phymodInterfaceKR4) && 4745 (config.interface_type != phymodInterfaceCR4) && 4746 (config.interface_type != phymodInterfaceCR10)) { 4747 return PHYMOD_E_NONE; 4748 } 4749 4750 PHYMOD_IF_ERR_RETURN ( 4751 BCMI_DINO_READ_DEV7_SLICE_SLICEr(pa, &an_slice)); 4752 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_0_SELf_SET(an_slice, 0); 4753 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_1_SELf_SET(an_slice, 0); 4754 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_2_SELf_SET(an_slice, 0); 4755 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 0); 4756 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 0); 4757 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 0); 4758 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4759 if ((config.data_rate == DINO_SPD_100G) && 4760 ((config.interface_type == phymodInterfaceKR4) || 4761 (config.interface_type == phymodInterfaceCR4) || 4762 (config.interface_type == phymodInterfaceCR10))) { 4763 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 4764 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 4765 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4766 mst_lane_reg_data &= ~(DINO_AN_MST_LANE_100G_MASK); 4767 mst_lane_reg_data |= ((an_ability->an_master_lane)<< DINO_AN_MST_LANE_100G_SHIFT); 4768 WRITE_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4769 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4770 if (dev_op_mode == DINO_DEV_OP_MODE_PT) { 4771 if (((lane_mask == DINO_100G_TYPE1_LANE_MASK) || ((lane_mask & 0xf) == 0xf)) || 4772 ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) || 4773 ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc))) { 4774 if ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) { 4775 an_ability->an_master_lane += 1; 4776 } 4777 if ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc)) { 4778 an_ability->an_master_lane += 2; 4779 } 4780 switch (an_ability->an_master_lane/DINO_MAX_CORE_LANE) { 4781 case 0: 4782 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4783 break; 4784 case 1: 4785 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4786 break; 4787 case 2: 4788 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 4789 break; 4790 } 4791 } 4792 } else { 4793 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4794 } 4795 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4796 gpreg_f_data &= ~(DINO_100G_SKIP_TX_TRAINING_MASK); 4797 gpreg_f_data |= ((an_ability->cl73_adv.an_cl72) ? 0 : 1) << DINO_100G_SKIP_TX_TRAINING_SHIFT; 4798 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4799 break; 4800 } else if ((config.data_rate == DINO_SPD_40G) && 4801 (lane_mask == DINO_40G_PORT0_LANE_MASK) && 4802 ((config.interface_type == phymodInterfaceKR4) || 4803 (config.interface_type == phymodInterfaceCR4))) { 4804 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4805 mst_lane_reg_data &= ~(DINO_AN_MST_LANE_40G_P0_MASK); 4806 mst_lane_reg_data |= ((an_ability->an_master_lane)<< DINO_AN_MST_LANE_40G_P0_SHIFT); 4807 WRITE_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4808 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4809 gpreg_f_data &= ~(DINO_40G_PORT0_SKIP_TX_TRAINING_MASK); 4810 gpreg_f_data |= ((an_ability->cl73_adv.an_cl72) ? 0 : 1) << DINO_40G_PORT0_SKIP_TX_TRAINING_SHIFT; 4811 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4812 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4813 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4814 break; 4815 } else if ((config.data_rate == DINO_SPD_40G) && 4816 (lane_mask == DINO_40G_PORT1_LANE_MASK) && 4817 ((config.interface_type == phymodInterfaceKR4) || 4818 (config.interface_type == phymodInterfaceCR4))) { 4819 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4820 mst_lane_reg_data &= ~(DINO_AN_MST_LANE_40G_P1_MASK); 4821 mst_lane_reg_data |= ((an_ability->an_master_lane)<< DINO_AN_MST_LANE_40G_P1_SHIFT); 4822 WRITE_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4823 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4824 gpreg_f_data &= ~(DINO_40G_PORT1_SKIP_TX_TRAINING_MASK); 4825 gpreg_f_data |= ((an_ability->cl73_adv.an_cl72) ? 0 : 1) << DINO_40G_PORT1_SKIP_TX_TRAINING_SHIFT; 4826 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4827 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4828 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4829 break; 4830 } else if ((config.data_rate == DINO_SPD_40G) && 4831 (lane_mask == DINO_40G_PORT2_LANE_MASK) && 4832 ((config.interface_type == phymodInterfaceKR4) || 4833 (config.interface_type == phymodInterfaceCR4))) { 4834 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4835 mst_lane_reg_data &= ~(DINO_AN_MST_LANE_40G_P2_MASK); 4836 mst_lane_reg_data |= ((an_ability->an_master_lane)<< DINO_AN_MST_LANE_40G_P2_SHIFT); 4837 WRITE_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4838 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4839 gpreg_f_data &= ~(DINO_40G_PORT2_SKIP_TX_TRAINING_MASK); 4840 gpreg_f_data |= ((an_ability->cl73_adv.an_cl72) ? 0 : 1) << DINO_40G_PORT2_SKIP_TX_TRAINING_SHIFT; 4841 WRITE_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4842 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4843 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 4844 break; 4845 } 4846 } 4847 BCMI_DINO_DEV7_SLICE_SLICEr_LANE_SELf_SET(an_slice, (1 << (an_ability->an_master_lane % DINO_MAX_CORE_LANE))); 4848 /* Set the AN slice with AN master lane */ 4849 PHYMOD_IF_ERR_RETURN ( 4850 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 4851 PHYMOD_IF_ERR_RETURN ( 4852 BCMI_DINO_READ_AN_ADVERTISEMENT1r(pa, &an_adv1)); 4853 PHYMOD_IF_ERR_RETURN ( 4854 BCMI_DINO_READ_AN_ADVERTISEMENT2r(pa, &an_adv2)); 4855 PHYMOD_IF_ERR_RETURN ( 4856 BCMI_DINO_READ_AN_ADVERTISEMENT3r(pa, &an_adv3)); 4857 4858 BCMI_DINO_AN_ADVERTISEMENT1r_PAUSEf_SET(an_adv1, an_ability->cl73_adv.an_pause); 4859 BCMI_DINO_AN_ADVERTISEMENT2r_TECHABILITYf_SET(an_adv2, an_ability->cl73_adv.an_base_speed); 4860 BCMI_DINO_AN_ADVERTISEMENT3r_FEC_REQUESTEDf_SET(an_adv3, an_ability->cl73_adv.an_fec); 4861 4862 PHYMOD_IF_ERR_RETURN ( 4863 BCMI_DINO_WRITE_AN_ADVERTISEMENT1r(pa, an_adv1)); 4864 PHYMOD_IF_ERR_RETURN ( 4865 BCMI_DINO_WRITE_AN_ADVERTISEMENT2r(pa, an_adv2)); 4866 PHYMOD_IF_ERR_RETURN ( 4867 BCMI_DINO_WRITE_AN_ADVERTISEMENT3r(pa, an_adv3)); 4868 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 4869 PHYMOD_IF_ERR_RETURN ( 4870 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 4871 4872 return PHYMOD_E_NONE; 4873 } 4874 4875 int _dino_phy_autoneg_ability_get(const phymod_phy_access_t* phy, dino_an_ability_t *an_ability) 4876 { 4877 phymod_phy_inf_config_t config; 4878 uint16_t lane_mask = 0; 4879 uint32_t flags = 0; 4880 uint16_t port_idx = 0; 4881 uint16_t sw_gpreg_data = 0; 4882 uint16_t mst_lane_reg_data = 0; 4883 uint16_t gpreg_f_data = 0; 4884 uint16_t an_mst_lane = 0; 4885 uint16_t no_of_ports = 0; 4886 uint32_t chip_id = 0; 4887 uint32_t rev = 0; 4888 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 4889 phymod_phy_access_t phy_copy; 4890 BCMI_DINO_DEV7_SLICE_SLICEr_t an_slice; 4891 BCMI_DINO_AN_ADVERTISEMENT1r_t an_adv1; 4892 BCMI_DINO_AN_ADVERTISEMENT2r_t an_adv2; 4893 BCMI_DINO_AN_ADVERTISEMENT3r_t an_adv3; 4894 const phymod_access_t *pa = &phy->access; 4895 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 4896 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 4897 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 4898 PHYMOD_MEMSET(&an_slice, 0, sizeof(BCMI_DINO_DEV7_SLICE_SLICEr_t)); 4899 PHYMOD_MEMSET(&an_adv1, 0, sizeof(BCMI_DINO_AN_ADVERTISEMENT1r_t)); 4900 PHYMOD_MEMSET(&an_adv2, 0, sizeof(BCMI_DINO_AN_ADVERTISEMENT2r_t)); 4901 PHYMOD_MEMSET(&an_adv3, 0, sizeof(BCMI_DINO_AN_ADVERTISEMENT3r_t)); 4902 4903 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 4904 4905 PHYMOD_IF_ERR_RETURN( 4906 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 4907 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 4908 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 4909 4910 if ((config.interface_type != phymodInterfaceKR4) && 4911 (config.interface_type != phymodInterfaceCR4) && 4912 (config.interface_type != phymodInterfaceCR10)) { 4913 return PHYMOD_E_NONE; 4914 } 4915 4916 PHYMOD_IF_ERR_RETURN ( 4917 BCMI_DINO_READ_DEV7_SLICE_SLICEr(pa, &an_slice)); 4918 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_0_SELf_SET(an_slice, 0); 4919 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_1_SELf_SET(an_slice, 0); 4920 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_2_SELf_SET(an_slice, 0); 4921 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 0); 4922 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 0); 4923 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 0); 4924 READ_DINO_PMA_PMD_REG(pa, DINO_GPREG_F_ADR, gpreg_f_data); 4925 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 4926 if ((config.data_rate == DINO_SPD_100G) && 4927 ((config.interface_type == phymodInterfaceKR4) || 4928 (config.interface_type == phymodInterfaceCR4) || 4929 (config.interface_type == phymodInterfaceCR10))) { 4930 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 4931 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 4932 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4933 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_100G_MASK) >> DINO_AN_MST_LANE_100G_SHIFT; 4934 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4935 if (dev_op_mode == DINO_DEV_OP_MODE_PT) { 4936 if (((lane_mask == DINO_100G_TYPE1_LANE_MASK) || ((lane_mask & 0xf) == 0xf)) || 4937 ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) || 4938 ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc))) { 4939 if ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) { 4940 an_mst_lane += 1; 4941 } 4942 if ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc)) { 4943 an_mst_lane += 2; 4944 } 4945 switch (an_mst_lane/DINO_MAX_CORE_LANE) { 4946 case 0: 4947 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4948 break; 4949 case 1: 4950 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4951 break; 4952 case 2: 4953 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 4954 break; 4955 } 4956 } 4957 } else { 4958 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4959 } 4960 (gpreg_f_data & DINO_100G_SKIP_TX_TRAINING_MASK) ? (an_ability->cl73_adv.an_cl72 = 0): (an_ability->cl73_adv.an_cl72 = 1); 4961 break; 4962 } else if ((config.data_rate == DINO_SPD_40G) && 4963 (lane_mask == DINO_40G_PORT0_LANE_MASK)&& 4964 ((config.interface_type == phymodInterfaceKR4) || 4965 (config.interface_type == phymodInterfaceCR4))) { 4966 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4967 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P0_MASK) >> DINO_AN_MST_LANE_40G_P0_SHIFT; 4968 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4969 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 4970 (gpreg_f_data & DINO_40G_PORT0_SKIP_TX_TRAINING_MASK) ? (an_ability->cl73_adv.an_cl72 = 0): (an_ability->cl73_adv.an_cl72 = 1); 4971 break; 4972 } else if ((config.data_rate == DINO_SPD_40G) && 4973 (lane_mask == DINO_40G_PORT1_LANE_MASK) && 4974 ((config.interface_type == phymodInterfaceKR4) || 4975 (config.interface_type == phymodInterfaceCR4))) { 4976 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4977 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P1_MASK) >> DINO_AN_MST_LANE_40G_P1_SHIFT; 4978 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4979 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 4980 (gpreg_f_data & DINO_40G_PORT1_SKIP_TX_TRAINING_MASK) ? (an_ability->cl73_adv.an_cl72 = 0): (an_ability->cl73_adv.an_cl72 = 1); 4981 break; 4982 } else if ((config.data_rate == DINO_SPD_40G) && 4983 (lane_mask == DINO_40G_PORT2_LANE_MASK) && 4984 ((config.interface_type == phymodInterfaceKR4) || 4985 (config.interface_type == phymodInterfaceCR4))) { 4986 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 4987 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P2_MASK) >> DINO_AN_MST_LANE_40G_P2_SHIFT; 4988 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 4989 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 4990 (gpreg_f_data & DINO_40G_PORT2_SKIP_TX_TRAINING_MASK) ? (an_ability->cl73_adv.an_cl72 = 0): (an_ability->cl73_adv.an_cl72 = 1); 4991 break; 4992 } 4993 } 4994 BCMI_DINO_DEV7_SLICE_SLICEr_LANE_SELf_SET(an_slice, (1 << (an_mst_lane % DINO_MAX_CORE_LANE))); 4995 /* Set the AN slice with AN master lane */ 4996 PHYMOD_IF_ERR_RETURN ( 4997 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 4998 4999 /* Read AN ability */ 5000 PHYMOD_IF_ERR_RETURN ( 5001 BCMI_DINO_READ_AN_ADVERTISEMENT1r(pa, &an_adv1)); 5002 PHYMOD_IF_ERR_RETURN ( 5003 BCMI_DINO_READ_AN_ADVERTISEMENT2r(pa, &an_adv2)); 5004 PHYMOD_IF_ERR_RETURN ( 5005 BCMI_DINO_READ_AN_ADVERTISEMENT3r(pa, &an_adv3)); 5006 5007 an_ability->cl73_adv.an_pause = BCMI_DINO_AN_ADVERTISEMENT1r_PAUSEf_GET(an_adv1); 5008 an_ability->cl73_adv.an_base_speed = BCMI_DINO_AN_ADVERTISEMENT2r_TECHABILITYf_GET(an_adv2); 5009 an_ability->cl73_adv.an_fec = BCMI_DINO_AN_ADVERTISEMENT3r_FEC_REQUESTEDf_GET(an_adv3); 5010 if ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) { 5011 an_mst_lane -= 1; 5012 } 5013 if ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc)) { 5014 an_mst_lane -= 2; 5015 } 5016 /* Read AN master lane */ 5017 an_ability->an_master_lane = an_mst_lane; 5018 5019 /* Clear the slice */ 5020 BCMI_DINO_DEV7_SLICE_SLICEr_CLR(an_slice); 5021 PHYMOD_IF_ERR_RETURN ( 5022 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 5023 5024 return PHYMOD_E_NONE; 5025 } 5026 5027 int _dino_phy_autoneg_remote_ability_get(const phymod_phy_access_t *phy, phymod_autoneg_ability_t* an_ability_get) 5028 { 5029 phymod_phy_inf_config_t config; 5030 uint16_t lane_mask = 0; 5031 uint32_t flags = 0; 5032 uint16_t port_idx = 0; 5033 uint16_t sw_gpreg_data = 0; 5034 uint16_t mst_lane_reg_data = 0; 5035 uint16_t an_mst_lane = 0; 5036 uint16_t no_of_ports = 0; 5037 uint16_t an_bp_abl1 = 0; 5038 uint16_t an_bp_abl2 = 0; 5039 uint16_t an_bp_abl3 = 0; 5040 uint32_t chip_id = 0; 5041 uint32_t rev = 0; 5042 uint16_t dev_op_mode = DINO_DEV_OP_MODE_INVALID; 5043 BCMI_DINO_DEV7_SLICE_SLICEr_t an_slice; 5044 BCMI_DINO_AN_LP_BASE_PAGE_ABIL_1r_t base_page_ability1; 5045 BCMI_DINO_AN_LP_BASE_PAGE_ABIL_2r_t base_page_ability2; 5046 BCMI_DINO_AN_LP_BASE_PAGE_ABIL_3r_t base_page_ability3; 5047 const phymod_access_t *pa = &phy->access; 5048 phymod_phy_access_t phy_copy; 5049 PHYMOD_MEMSET(&phy_copy, 0, sizeof(phymod_phy_access_t)); 5050 PHYMOD_MEMCPY(&phy_copy, phy, sizeof(phymod_phy_access_t)); 5051 PHYMOD_MEMSET(&config, 0, sizeof(phymod_phy_inf_config_t)); 5052 PHYMOD_MEMSET(&an_slice, 0, sizeof(BCMI_DINO_DEV7_SLICE_SLICEr_t)); 5053 PHYMOD_MEMSET(&base_page_ability1, 0, sizeof(BCMI_DINO_AN_LP_BASE_PAGE_ABIL_1r_t)); 5054 PHYMOD_MEMSET(&base_page_ability2, 0, sizeof(BCMI_DINO_AN_LP_BASE_PAGE_ABIL_2r_t)); 5055 PHYMOD_MEMSET(&base_page_ability3, 0, sizeof(BCMI_DINO_AN_LP_BASE_PAGE_ABIL_3r_t)); 5056 5057 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5058 5059 PHYMOD_IF_ERR_RETURN( 5060 _dino_phy_interface_config_get(&phy_copy, flags, &config)); 5061 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 5062 DINO_GET_PORT_FROM_MODE((&config), chip_id, no_of_ports); 5063 5064 if ((config.interface_type != phymodInterfaceKR4) && 5065 (config.interface_type != phymodInterfaceCR4) && 5066 (config.interface_type != phymodInterfaceCR10)) { 5067 return PHYMOD_E_NONE; 5068 } 5069 5070 PHYMOD_IF_ERR_RETURN ( 5071 BCMI_DINO_READ_DEV7_SLICE_SLICEr(pa, &an_slice)); 5072 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_0_SELf_SET(an_slice, 0); 5073 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_1_SELf_SET(an_slice, 0); 5074 BCMI_DINO_DEV7_SLICE_SLICEr_SLICE_2_SELf_SET(an_slice, 0); 5075 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 0); 5076 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 0); 5077 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 0); 5078 for (port_idx = 0; port_idx < no_of_ports; port_idx++) { 5079 if ((config.data_rate == DINO_SPD_100G) && 5080 ((config.interface_type == phymodInterfaceKR4) || 5081 (config.interface_type == phymodInterfaceCR4) || 5082 (config.interface_type == phymodInterfaceCR10))) { 5083 READ_DINO_PMA_PMD_REG(pa, DINO_SW_GPREG_0_ADR, sw_gpreg_data); 5084 dev_op_mode = (sw_gpreg_data & DINO_DEV_OP_MODE_MASK) >> DINO_DEV_OP_MODE_SHIFT; 5085 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 5086 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_100G_MASK) >> DINO_AN_MST_LANE_100G_SHIFT; 5087 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 5088 if (dev_op_mode == DINO_DEV_OP_MODE_PT) { 5089 if (((lane_mask == DINO_100G_TYPE1_LANE_MASK) || ((lane_mask & 0xf) == 0xf)) || 5090 ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) || 5091 ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc))) { 5092 if ((lane_mask == DINO_100G_TYPE2_LANE_MASK) || ((lane_mask & 0xe) == 0xe)) { 5093 an_mst_lane += 1; 5094 } 5095 if ((lane_mask == DINO_100G_TYPE3_LANE_MASK) || ((lane_mask & 0xc) == 0xc)) { 5096 an_mst_lane += 2; 5097 } 5098 switch (an_mst_lane/DINO_MAX_CORE_LANE) { 5099 case 0: 5100 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 5101 break; 5102 case 1: 5103 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 5104 break; 5105 case 2: 5106 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 5107 break; 5108 } 5109 } 5110 } else { 5111 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 5112 } 5113 break; 5114 } else if ((config.data_rate == DINO_SPD_40G) && 5115 (lane_mask == DINO_40G_PORT0_LANE_MASK) && 5116 ((config.interface_type == phymodInterfaceKR4) || 5117 (config.interface_type == phymodInterfaceCR4))) { 5118 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 5119 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P0_MASK) >> DINO_AN_MST_LANE_40G_P0_SHIFT; 5120 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 5121 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_0f_SET(an_slice, 1); 5122 break; 5123 } else if ((config.data_rate == DINO_SPD_40G) && 5124 (lane_mask == DINO_40G_PORT1_LANE_MASK) && 5125 ((config.interface_type == phymodInterfaceKR4) || 5126 (config.interface_type == phymodInterfaceCR4))) { 5127 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 5128 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P1_MASK) >> DINO_AN_MST_LANE_40G_P1_SHIFT; 5129 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 5130 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_1f_SET(an_slice, 1); 5131 break; 5132 } else if ((config.data_rate == DINO_SPD_40G) && 5133 (lane_mask == DINO_40G_PORT2_LANE_MASK) && 5134 ((config.interface_type == phymodInterfaceKR4) || 5135 (config.interface_type == phymodInterfaceCR4))) { 5136 READ_DINO_PMA_PMD_REG(pa, DINO_AN_MST_LANE_REG_ADR, mst_lane_reg_data); 5137 an_mst_lane = (mst_lane_reg_data & DINO_AN_MST_LANE_40G_P2_MASK) >> DINO_AN_MST_LANE_40G_P2_SHIFT; 5138 BCMI_DINO_DEV7_SLICE_SLICEr_LIN_SELf_SET(an_slice, 1); 5139 BCMI_DINO_DEV7_SLICE_SLICEr_AN_PORT_2f_SET(an_slice, 1); 5140 break; 5141 } 5142 } 5143 BCMI_DINO_DEV7_SLICE_SLICEr_LANE_SELf_SET(an_slice, (1 << (an_mst_lane % DINO_MAX_CORE_LANE))); 5144 /* Set the AN slice with AN master lane */ 5145 PHYMOD_IF_ERR_RETURN ( 5146 BCMI_DINO_WRITE_DEV7_SLICE_SLICEr(pa, an_slice)); 5147 5148 PHYMOD_IF_ERR_RETURN( 5149 BCMI_DINO_READ_AN_LP_BASE_PAGE_ABIL_1r(pa, &base_page_ability1)); 5150 PHYMOD_IF_ERR_RETURN( 5151 BCMI_DINO_READ_AN_LP_BASE_PAGE_ABIL_2r(pa, &base_page_ability2)); 5152 PHYMOD_IF_ERR_RETURN( 5153 BCMI_DINO_READ_AN_LP_BASE_PAGE_ABIL_3r(pa, &base_page_ability3)); 5154 5155 an_bp_abl1 = BCMI_DINO_AN_LP_BASE_PAGE_ABIL_1r_D15_D0f_GET(base_page_ability1); 5156 an_bp_abl2 = BCMI_DINO_AN_LP_BASE_PAGE_ABIL_2r_D31_16f_GET(base_page_ability2); 5157 an_bp_abl3 = BCMI_DINO_AN_LP_BASE_PAGE_ABIL_3r_D47_32f_GET(base_page_ability3); 5158 5159 an_ability_get->an_fec = (an_bp_abl3 & 0xC000) >> 15; 5160 an_ability_get->an_cap = (an_bp_abl2 & 0xFFE0) >> 5; 5161 5162 if (an_bp_abl1& 0x400) { 5163 PHYMOD_AN_CAP_ASYM_PAUSE_SET(an_ability_get); 5164 } else if (an_bp_abl1 & 0x800) { 5165 PHYMOD_AN_CAP_SYMM_PAUSE_SET(an_ability_get); 5166 } 5167 5168 return PHYMOD_E_NONE; 5169 } 5170 5171 int _dino_get_intr_reg (const phymod_phy_access_t *phy, uint32_t intr_type, uint16_t *bit_pos, uint16_t *int_grp) 5172 { 5173 uint16_t lane_mask = 0; 5174 uint16_t intf_side = 0; 5175 const phymod_access_t *pa = &phy->access; 5176 5177 DINO_GET_INTF_SIDE(phy, intf_side); 5178 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5179 /* Get the interrupt bit postion in the reg and interrupt group */ 5180 switch (intr_type) { 5181 case PLL_LOCK_FOUND: 5182 if (intf_side == DINO_IF_SYS) { 5183 if (lane_mask & 0xf ) { 5184 *bit_pos = 0; 5185 *int_grp = SYS_LINK_CORE_0; 5186 } else if (lane_mask & 0xf0) { 5187 *bit_pos = 0; 5188 *int_grp = SYS_LINK_CORE_1; 5189 } else { 5190 *bit_pos = 0; 5191 *int_grp = SYS_LINK_CORE_2; 5192 } 5193 } else { 5194 if (lane_mask & 0xf ) { 5195 *bit_pos = 0; 5196 *int_grp = LINE_LINK_CORE_0; 5197 } else if (lane_mask & 0xf0) { 5198 *bit_pos = 0; 5199 *int_grp = LINE_LINK_CORE_1; 5200 } else { 5201 *bit_pos = 0; 5202 *int_grp = LINE_LINK_CORE_2; 5203 } 5204 } 5205 break; 5206 case PLL_LOCK_LOST: 5207 if (intf_side == DINO_IF_SYS) { 5208 if (lane_mask & 0xf ) { 5209 *bit_pos = 1; 5210 *int_grp = SYS_LINK_CORE_0; 5211 } else if (lane_mask & 0xf0) { 5212 *bit_pos = 1; 5213 *int_grp = SYS_LINK_CORE_1; 5214 } else { 5215 *bit_pos = 1; 5216 *int_grp = SYS_LINK_CORE_2; 5217 } 5218 } else { 5219 if (lane_mask & 0xf ) { 5220 *bit_pos = 1; 5221 *int_grp = LINE_LINK_CORE_0; 5222 } else if (lane_mask & 0xf0) { 5223 *bit_pos = 1; 5224 *int_grp = LINE_LINK_CORE_1; 5225 } else { 5226 *bit_pos = 1; 5227 *int_grp = LINE_LINK_CORE_2; 5228 } 5229 } 5230 break; 5231 case SIGDET_FOUND: 5232 if (intf_side == DINO_IF_SYS) { 5233 if (lane_mask & 0xf ) { 5234 *bit_pos = 2; 5235 *int_grp = SYS_LINK_CORE_0; 5236 } else if (lane_mask & 0xf0) { 5237 *bit_pos = 2; 5238 *int_grp = SYS_LINK_CORE_1; 5239 } else { 5240 *bit_pos = 2; 5241 *int_grp = SYS_LINK_CORE_2; 5242 } 5243 } else { 5244 if (lane_mask & 0xf ) { 5245 *bit_pos = 2; 5246 *int_grp = LINE_LINK_CORE_0; 5247 } else if (lane_mask & 0xf0) { 5248 *bit_pos = 2; 5249 *int_grp = LINE_LINK_CORE_1; 5250 } else { 5251 *bit_pos = 2; 5252 *int_grp = LINE_LINK_CORE_2; 5253 } 5254 } 5255 break; 5256 case SIGDET_LOST: 5257 if (intf_side == DINO_IF_SYS) { 5258 if (lane_mask & 0xf ) { 5259 *bit_pos = 3; 5260 *int_grp = SYS_LINK_CORE_0; 5261 } else if (lane_mask & 0xf0) { 5262 *bit_pos = 3; 5263 *int_grp = SYS_LINK_CORE_1; 5264 } else { 5265 *bit_pos = 3; 5266 *int_grp = SYS_LINK_CORE_2; 5267 } 5268 } else { 5269 if (lane_mask & 0xf ) { 5270 *bit_pos = 3; 5271 *int_grp = LINE_LINK_CORE_0; 5272 } else if (lane_mask & 0xf0) { 5273 *bit_pos = 3; 5274 *int_grp = LINE_LINK_CORE_1; 5275 } else { 5276 *bit_pos = 3; 5277 *int_grp = LINE_LINK_CORE_2; 5278 } 5279 } 5280 break; 5281 case PMD_LOCK_FOUND: 5282 if (intf_side == DINO_IF_SYS) { 5283 if (lane_mask & 0xf ) { 5284 *bit_pos = 4; 5285 *int_grp = SYS_LINK_CORE_0; 5286 } else if (lane_mask & 0xf0) { 5287 *bit_pos = 4; 5288 *int_grp = SYS_LINK_CORE_1; 5289 } else { 5290 *bit_pos = 4; 5291 *int_grp = SYS_LINK_CORE_2; 5292 } 5293 } else { 5294 if (lane_mask & 0xf ) { 5295 *bit_pos = 4; 5296 *int_grp = LINE_LINK_CORE_0; 5297 } else if (lane_mask & 0xf0) { 5298 *bit_pos = 4; 5299 *int_grp = LINE_LINK_CORE_1; 5300 } else { 5301 *bit_pos = 4; 5302 *int_grp = LINE_LINK_CORE_2; 5303 } 5304 } 5305 break; 5306 case PMD_LOCK_LOST: 5307 if (intf_side == DINO_IF_SYS) { 5308 if (lane_mask & 0xf ) { 5309 *bit_pos = 5; 5310 *int_grp = SYS_LINK_CORE_0; 5311 } else if (lane_mask & 0xf0) { 5312 *bit_pos = 5; 5313 *int_grp = SYS_LINK_CORE_1; 5314 } else { 5315 *bit_pos = 5; 5316 *int_grp = SYS_LINK_CORE_2; 5317 } 5318 } else { 5319 if (lane_mask & 0xf ) { 5320 *bit_pos = 5; 5321 *int_grp = LINE_LINK_CORE_0; 5322 } else if (lane_mask & 0xf0) { 5323 *bit_pos = 5; 5324 *int_grp = LINE_LINK_CORE_1; 5325 } else { 5326 *bit_pos = 5; 5327 *int_grp = LINE_LINK_CORE_2; 5328 } 5329 } 5330 break; 5331 case AN_COMPLETE: 5332 if (lane_mask & 0xf ) { 5333 *bit_pos = 0; 5334 *int_grp = AN_CORE_0_1_2; 5335 } else if (lane_mask & 0xf0) { 5336 *bit_pos = 1; 5337 *int_grp = AN_CORE_0_1_2; 5338 } else { 5339 *bit_pos = 2; 5340 *int_grp = AN_CORE_0_1_2; 5341 } 5342 break; 5343 case AN_RESTARTED: 5344 if (lane_mask & 0xf ) { 5345 *bit_pos = 3; 5346 *int_grp = AN_CORE_0_1_2; 5347 } else if (lane_mask & 0xf0) { 5348 *bit_pos = 4; 5349 *int_grp = AN_CORE_0_1_2; 5350 } else { 5351 *bit_pos = 5; 5352 *int_grp = AN_CORE_0_1_2; 5353 } 5354 break; 5355 case INT_DEMUX_FIFOERR: 5356 *bit_pos = 0; 5357 *int_grp = DP_MUX_DEMUX_FIFO; 5358 break; 5359 case INT_MUX_FIFOERR: 5360 *bit_pos = 1; 5361 *int_grp = DP_MUX_DEMUX_FIFO; 5362 break; 5363 default: 5364 return PHYMOD_E_PARAM; 5365 } 5366 5367 return PHYMOD_E_NONE; 5368 } 5369 int _dino_phy_intr_enable_set(const phymod_phy_access_t* phy, uint32_t intr_type, uint32_t enable) 5370 { 5371 uint16_t intr_grp = 0; 5372 uint16_t bit_pos = 0; 5373 uint16_t intr_mask = 0; 5374 uint16_t data = 0; 5375 const phymod_access_t *pa = &phy->access; 5376 BCMI_DINO_LIN_25G_0_EIERr_t line_25g_0_eier; 5377 BCMI_DINO_LIN_10G_1_EIERr_t line_10g_1_eier; 5378 BCMI_DINO_LIN_10G_2_EIERr_t line_10g_2_eier; 5379 BCMI_DINO_SYS_10G_0_EIERr_t sys_10g_0_eier; 5380 BCMI_DINO_SYS_10G_1_EIERr_t sys_10g_1_eier; 5381 BCMI_DINO_SYS_10G_2_EIERr_t sys_10g_2_eier; 5382 BCMI_DINO_LIN_MISC_2_EIERr_t line_misc_2_eier; 5383 BCMI_DINO_MISC_EIERr_t misc_eier; 5384 5385 PHYMOD_MEMSET(&line_25g_0_eier, 0, sizeof(BCMI_DINO_LIN_25G_0_EIERr_t)); 5386 PHYMOD_MEMSET(&line_10g_1_eier, 0, sizeof(BCMI_DINO_LIN_10G_1_EIERr_t)); 5387 PHYMOD_MEMSET(&line_10g_2_eier, 0, sizeof(BCMI_DINO_LIN_10G_2_EIERr_t)); 5388 PHYMOD_MEMSET(&sys_10g_0_eier, 0, sizeof(BCMI_DINO_SYS_10G_0_EIERr_t)); 5389 PHYMOD_MEMSET(&sys_10g_1_eier, 0, sizeof(BCMI_DINO_SYS_10G_1_EIERr_t)); 5390 PHYMOD_MEMSET(&sys_10g_2_eier, 0, sizeof(BCMI_DINO_SYS_10G_2_EIERr_t)); 5391 PHYMOD_MEMSET(&line_misc_2_eier, 0, sizeof(BCMI_DINO_LIN_MISC_2_EIERr_t)); 5392 PHYMOD_MEMSET(&misc_eier, 0, sizeof(BCMI_DINO_MISC_EIERr_t)); 5393 5394 /* Get the interrupt bit postion in the reg and interrupt group */ 5395 PHYMOD_IF_ERR_RETURN( 5396 _dino_get_intr_reg(phy, intr_type, &bit_pos, &intr_grp)); 5397 intr_mask = enable ? (0x1 << bit_pos) : (~(0x1 << bit_pos)); 5398 /* Interrupt enable get on specified interrupt group */ 5399 switch(intr_grp) { 5400 case LINE_LINK_CORE_0: 5401 PHYMOD_IF_ERR_RETURN( 5402 BCMI_DINO_READ_LIN_25G_0_EIERr(pa, &line_25g_0_eier)); 5403 data = (enable ? (intr_mask | BCMI_DINO_LIN_25G_0_EIERr_GET(line_25g_0_eier)) : (intr_mask & BCMI_DINO_LIN_25G_0_EIERr_GET(line_25g_0_eier))); 5404 BCMI_DINO_LIN_25G_0_EIERr_SET(line_25g_0_eier, data); 5405 PHYMOD_IF_ERR_RETURN( 5406 BCMI_DINO_WRITE_LIN_25G_0_EIERr(pa, line_25g_0_eier)); 5407 break; 5408 case LINE_LINK_CORE_1: 5409 PHYMOD_IF_ERR_RETURN( 5410 BCMI_DINO_READ_LIN_10G_1_EIERr(pa, &line_10g_1_eier)); 5411 data = (enable ? (intr_mask | BCMI_DINO_LIN_10G_1_EIERr_GET(line_10g_1_eier)) : (intr_mask & BCMI_DINO_LIN_10G_1_EIERr_GET(line_10g_1_eier))); 5412 BCMI_DINO_LIN_10G_1_EIERr_SET(line_10g_1_eier, data); 5413 PHYMOD_IF_ERR_RETURN( 5414 BCMI_DINO_WRITE_LIN_10G_1_EIERr(pa, line_10g_1_eier)); 5415 break; 5416 case LINE_LINK_CORE_2: 5417 PHYMOD_IF_ERR_RETURN( 5418 BCMI_DINO_READ_LIN_10G_2_EIERr(pa, &line_10g_2_eier)); 5419 data = (enable ? (intr_mask | BCMI_DINO_LIN_10G_2_EIERr_GET(line_10g_2_eier)) : (intr_mask & BCMI_DINO_LIN_10G_2_EIERr_GET(line_10g_2_eier))); 5420 BCMI_DINO_LIN_10G_2_EIERr_SET(line_10g_2_eier, data); 5421 PHYMOD_IF_ERR_RETURN( 5422 BCMI_DINO_WRITE_LIN_10G_2_EIERr(pa, line_10g_2_eier)); 5423 break; 5424 case SYS_LINK_CORE_0: 5425 PHYMOD_IF_ERR_RETURN( 5426 BCMI_DINO_READ_SYS_10G_0_EIERr(pa, &sys_10g_0_eier)); 5427 data = (enable ? (intr_mask | BCMI_DINO_SYS_10G_0_EIERr_GET(sys_10g_0_eier)) : (intr_mask & BCMI_DINO_SYS_10G_0_EIERr_GET(sys_10g_0_eier))); 5428 BCMI_DINO_SYS_10G_0_EIERr_SET(sys_10g_0_eier, data); 5429 PHYMOD_IF_ERR_RETURN( 5430 BCMI_DINO_WRITE_SYS_10G_0_EIERr(pa, sys_10g_0_eier)); 5431 break; 5432 case SYS_LINK_CORE_1: 5433 PHYMOD_IF_ERR_RETURN( 5434 BCMI_DINO_READ_SYS_10G_1_EIERr(pa, &sys_10g_1_eier)); 5435 data = (enable ? (intr_mask | BCMI_DINO_SYS_10G_1_EIERr_GET(sys_10g_1_eier)) : (intr_mask & BCMI_DINO_SYS_10G_1_EIERr_GET(sys_10g_1_eier))); 5436 BCMI_DINO_SYS_10G_1_EIERr_SET(sys_10g_1_eier, data); 5437 PHYMOD_IF_ERR_RETURN( 5438 BCMI_DINO_WRITE_SYS_10G_1_EIERr(pa, sys_10g_1_eier)); 5439 break; 5440 case SYS_LINK_CORE_2: 5441 PHYMOD_IF_ERR_RETURN( 5442 BCMI_DINO_READ_SYS_10G_2_EIERr(pa, &sys_10g_2_eier)); 5443 data = (enable ? (intr_mask | BCMI_DINO_SYS_10G_2_EIERr_GET(sys_10g_2_eier)) : (intr_mask & BCMI_DINO_SYS_10G_2_EIERr_GET(sys_10g_2_eier))); 5444 BCMI_DINO_SYS_10G_2_EIERr_SET(sys_10g_2_eier, data); 5445 PHYMOD_IF_ERR_RETURN( 5446 BCMI_DINO_WRITE_SYS_10G_2_EIERr(pa, sys_10g_2_eier)); 5447 break; 5448 case AN_CORE_0_1_2: 5449 PHYMOD_IF_ERR_RETURN( 5450 BCMI_DINO_READ_LIN_MISC_2_EIERr(pa, &line_misc_2_eier)); 5451 data = (enable ? (intr_mask | BCMI_DINO_LIN_MISC_2_EIERr_GET(line_misc_2_eier)) : (intr_mask & BCMI_DINO_LIN_MISC_2_EIERr_GET(line_misc_2_eier))); 5452 BCMI_DINO_LIN_MISC_2_EIERr_SET(line_misc_2_eier, data); 5453 PHYMOD_IF_ERR_RETURN( 5454 BCMI_DINO_WRITE_LIN_MISC_2_EIERr(pa, line_misc_2_eier)); 5455 break; 5456 case DP_MUX_DEMUX_FIFO: 5457 PHYMOD_IF_ERR_RETURN( 5458 BCMI_DINO_READ_MISC_EIERr(pa, &misc_eier)); 5459 data = (enable ? (intr_mask | BCMI_DINO_MISC_EIERr_GET(misc_eier)) : (intr_mask & BCMI_DINO_MISC_EIERr_GET(misc_eier))); 5460 BCMI_DINO_MISC_EIERr_SET(misc_eier, data); 5461 PHYMOD_IF_ERR_RETURN( 5462 BCMI_DINO_WRITE_MISC_EIERr(pa, misc_eier)); 5463 break; 5464 default: 5465 return PHYMOD_E_PARAM; 5466 } 5467 5468 return PHYMOD_E_NONE; 5469 } 5470 5471 int _dino_phy_intr_enable_get(const phymod_phy_access_t* phy, uint32_t intr_type, uint32_t* enable) 5472 { 5473 uint16_t intr_grp = 0; 5474 uint16_t bit_pos = 0; 5475 uint16_t data = 0; 5476 BCMI_DINO_LIN_25G_0_EIERr_t line_25g_0_eier; 5477 BCMI_DINO_LIN_10G_1_EIERr_t line_10g_1_eier; 5478 BCMI_DINO_LIN_10G_2_EIERr_t line_10g_2_eier; 5479 BCMI_DINO_SYS_10G_0_EIERr_t sys_10g_0_eier; 5480 BCMI_DINO_SYS_10G_1_EIERr_t sys_10g_1_eier; 5481 BCMI_DINO_SYS_10G_2_EIERr_t sys_10g_2_eier; 5482 BCMI_DINO_LIN_MISC_2_EIERr_t line_misc_2_eier; 5483 BCMI_DINO_MISC_EIERr_t misc_eier; 5484 const phymod_access_t *pa = &phy->access; 5485 5486 PHYMOD_MEMSET(&line_25g_0_eier, 0, sizeof(BCMI_DINO_LIN_25G_0_EIERr_t)); 5487 PHYMOD_MEMSET(&line_10g_1_eier, 0, sizeof(BCMI_DINO_LIN_10G_1_EIERr_t)); 5488 PHYMOD_MEMSET(&line_10g_2_eier, 0, sizeof(BCMI_DINO_LIN_10G_2_EIERr_t)); 5489 PHYMOD_MEMSET(&sys_10g_0_eier, 0, sizeof(BCMI_DINO_SYS_10G_0_EIERr_t)); 5490 PHYMOD_MEMSET(&sys_10g_1_eier, 0, sizeof(BCMI_DINO_SYS_10G_1_EIERr_t)); 5491 PHYMOD_MEMSET(&sys_10g_2_eier, 0, sizeof(BCMI_DINO_SYS_10G_2_EIERr_t)); 5492 PHYMOD_MEMSET(&line_misc_2_eier, 0, sizeof(BCMI_DINO_LIN_MISC_2_EIERr_t)); 5493 PHYMOD_MEMSET(&misc_eier, 0, sizeof(BCMI_DINO_MISC_EIERr_t)); 5494 5495 /* Get the interrupt bit postion in the reg and interrupt group */ 5496 PHYMOD_IF_ERR_RETURN( 5497 _dino_get_intr_reg(phy, intr_type, &bit_pos, &intr_grp)); 5498 /* Interrupt enable get on specified interrupt group */ 5499 switch(intr_grp) { 5500 case LINE_LINK_CORE_0: 5501 PHYMOD_IF_ERR_RETURN( 5502 BCMI_DINO_READ_LIN_25G_0_EIERr(pa, &line_25g_0_eier)); 5503 data = BCMI_DINO_LIN_25G_0_EIERr_GET(line_25g_0_eier); 5504 break; 5505 case LINE_LINK_CORE_1: 5506 PHYMOD_IF_ERR_RETURN( 5507 BCMI_DINO_READ_LIN_10G_1_EIERr(pa, &line_10g_1_eier)); 5508 data = BCMI_DINO_LIN_10G_1_EIERr_GET(line_10g_1_eier); 5509 break; 5510 case LINE_LINK_CORE_2: 5511 PHYMOD_IF_ERR_RETURN( 5512 BCMI_DINO_READ_LIN_10G_2_EIERr(pa, &line_10g_2_eier)); 5513 data = BCMI_DINO_LIN_10G_2_EIERr_GET(line_10g_2_eier); 5514 break; 5515 case SYS_LINK_CORE_0: 5516 PHYMOD_IF_ERR_RETURN( 5517 BCMI_DINO_READ_SYS_10G_0_EIERr(pa, &sys_10g_0_eier)); 5518 data = BCMI_DINO_SYS_10G_0_EIERr_GET(sys_10g_0_eier); 5519 break; 5520 case SYS_LINK_CORE_1: 5521 PHYMOD_IF_ERR_RETURN( 5522 BCMI_DINO_READ_SYS_10G_1_EIERr(pa, &sys_10g_1_eier)); 5523 data = BCMI_DINO_SYS_10G_1_EIERr_GET(sys_10g_1_eier); 5524 break; 5525 case SYS_LINK_CORE_2: 5526 PHYMOD_IF_ERR_RETURN( 5527 BCMI_DINO_READ_SYS_10G_2_EIERr(pa, &sys_10g_2_eier)); 5528 data = BCMI_DINO_SYS_10G_2_EIERr_GET(sys_10g_2_eier); 5529 break; 5530 case AN_CORE_0_1_2: 5531 PHYMOD_IF_ERR_RETURN( 5532 BCMI_DINO_READ_LIN_MISC_2_EIERr(pa, &line_misc_2_eier)); 5533 data = BCMI_DINO_LIN_MISC_2_EIERr_GET(line_misc_2_eier); 5534 break; 5535 case DP_MUX_DEMUX_FIFO: 5536 PHYMOD_IF_ERR_RETURN( 5537 BCMI_DINO_READ_MISC_EIERr(pa, &misc_eier)); 5538 data = BCMI_DINO_MISC_EIERr_GET(misc_eier); 5539 break; 5540 default: 5541 return PHYMOD_E_PARAM; 5542 } 5543 *enable = (data & (0x1 << bit_pos)) ? 1 : 0; 5544 5545 return PHYMOD_E_NONE; 5546 } 5547 5548 int _dino_phy_intr_status_get(const phymod_phy_access_t* phy, uint32_t* intr_status) 5549 { 5550 uint16_t intr_grp = 0; 5551 uint16_t bit_pos = 0; 5552 uint16_t data = 0; 5553 uint32_t event = 0; 5554 uint32_t intr_type = 0; 5555 uint32_t intr_index = 0; 5556 BCMI_DINO_LIN_25G_0_EISRr_t line_25g_0_eisr; 5557 BCMI_DINO_LIN_10G_1_EISRr_t line_10g_1_eisr; 5558 BCMI_DINO_LIN_10G_2_EISRr_t line_10g_2_eisr; 5559 BCMI_DINO_SYS_10G_0_EISRr_t sys_10g_0_eisr; 5560 BCMI_DINO_SYS_10G_1_EISRr_t sys_10g_1_eisr; 5561 BCMI_DINO_SYS_10G_2_EISRr_t sys_10g_2_eisr; 5562 BCMI_DINO_LIN_MISC_2_EISRr_t line_misc_2_eisr; 5563 BCMI_DINO_MISC_EISRr_t misc_eisr; 5564 BCMI_DINO_LIN_25G_0_EIPRr_t line_25g_0_eipr; 5565 BCMI_DINO_LIN_10G_1_EIPRr_t line_10g_1_eipr; 5566 BCMI_DINO_LIN_10G_2_EIPRr_t line_10g_2_eipr; 5567 BCMI_DINO_SYS_10G_0_EIPRr_t sys_10g_0_eipr; 5568 BCMI_DINO_SYS_10G_1_EIPRr_t sys_10g_1_eipr; 5569 BCMI_DINO_SYS_10G_2_EIPRr_t sys_10g_2_eipr; 5570 BCMI_DINO_LIN_MISC_2_EIPRr_t line_misc_2_eipr; 5571 BCMI_DINO_MISC_EIPRr_t misc_eipr; 5572 const phymod_access_t *pa = &phy->access; 5573 PHYMOD_MEMSET(&line_25g_0_eisr, 0, sizeof(BCMI_DINO_LIN_25G_0_EISRr_t)); 5574 PHYMOD_MEMSET(&line_10g_1_eisr, 0, sizeof(BCMI_DINO_LIN_10G_1_EISRr_t)); 5575 PHYMOD_MEMSET(&line_10g_2_eisr, 0, sizeof(BCMI_DINO_LIN_10G_2_EISRr_t)); 5576 PHYMOD_MEMSET(&sys_10g_0_eisr, 0, sizeof(BCMI_DINO_SYS_10G_0_EISRr_t)); 5577 PHYMOD_MEMSET(&sys_10g_1_eisr, 0, sizeof(BCMI_DINO_SYS_10G_1_EISRr_t)); 5578 PHYMOD_MEMSET(&sys_10g_2_eisr, 0, sizeof(BCMI_DINO_SYS_10G_2_EISRr_t)); 5579 PHYMOD_MEMSET(&line_misc_2_eisr, 0, sizeof(BCMI_DINO_LIN_MISC_2_EISRr_t)); 5580 PHYMOD_MEMSET(&misc_eisr, 0, sizeof(BCMI_DINO_MISC_EISRr_t)); 5581 PHYMOD_MEMSET(&line_25g_0_eipr, 0, sizeof(BCMI_DINO_LIN_25G_0_EIPRr_t)); 5582 PHYMOD_MEMSET(&line_10g_1_eipr, 0, sizeof(BCMI_DINO_LIN_10G_1_EIPRr_t)); 5583 PHYMOD_MEMSET(&line_10g_2_eipr, 0, sizeof(BCMI_DINO_LIN_10G_2_EIPRr_t)); 5584 PHYMOD_MEMSET(&sys_10g_0_eipr, 0, sizeof(BCMI_DINO_SYS_10G_0_EIPRr_t)); 5585 PHYMOD_MEMSET(&sys_10g_1_eipr, 0, sizeof(BCMI_DINO_SYS_10G_1_EIPRr_t)); 5586 PHYMOD_MEMSET(&sys_10g_2_eipr, 0, sizeof(BCMI_DINO_SYS_10G_2_EIPRr_t)); 5587 PHYMOD_MEMSET(&line_misc_2_eipr, 0, sizeof(BCMI_DINO_LIN_MISC_2_EIPRr_t)); 5588 PHYMOD_MEMSET(&misc_eipr, 0, sizeof(BCMI_DINO_MISC_EIPRr_t)); 5589 intr_type = (*intr_status) ? (*intr_status & 0x7FFFFFFF) : 0x7FFFFFFF; 5590 event = (*intr_status & 0x80000000) ? 1 : 0; 5591 *intr_status = 0; 5592 for (intr_index = 0; intr_index < DINO_MAX_INTR_SUPPORT; intr_index ++) { 5593 PHYMOD_IF_ERR_RETURN( 5594 _dino_get_intr_reg(phy, 1 << intr_index, &bit_pos, &intr_grp)); 5595 /* Interrupt enable get on specified interrupt group */ 5596 if (event) { 5597 switch(intr_grp) { 5598 case LINE_LINK_CORE_0: 5599 PHYMOD_IF_ERR_RETURN( 5600 BCMI_DINO_READ_LIN_25G_0_EISRr(pa, &line_25g_0_eisr)); 5601 data = BCMI_DINO_LIN_25G_0_EISRr_GET(line_25g_0_eisr); 5602 break; 5603 case LINE_LINK_CORE_1: 5604 PHYMOD_IF_ERR_RETURN( 5605 BCMI_DINO_READ_LIN_10G_1_EISRr(pa, &line_10g_1_eisr)); 5606 data = BCMI_DINO_LIN_10G_1_EISRr_GET(line_10g_1_eisr); 5607 break; 5608 case LINE_LINK_CORE_2: 5609 PHYMOD_IF_ERR_RETURN( 5610 BCMI_DINO_READ_LIN_10G_2_EISRr(pa, &line_10g_2_eisr)); 5611 data = BCMI_DINO_LIN_10G_2_EISRr_GET(line_10g_2_eisr); 5612 break; 5613 case SYS_LINK_CORE_0: 5614 PHYMOD_IF_ERR_RETURN( 5615 BCMI_DINO_READ_SYS_10G_0_EISRr(pa, &sys_10g_0_eisr)); 5616 data = BCMI_DINO_SYS_10G_0_EISRr_GET(sys_10g_0_eisr); 5617 break; 5618 case SYS_LINK_CORE_1: 5619 PHYMOD_IF_ERR_RETURN( 5620 BCMI_DINO_READ_SYS_10G_1_EISRr(pa, &sys_10g_1_eisr)); 5621 data = BCMI_DINO_SYS_10G_1_EISRr_GET(sys_10g_1_eisr); 5622 break; 5623 case SYS_LINK_CORE_2: 5624 PHYMOD_IF_ERR_RETURN( 5625 BCMI_DINO_READ_SYS_10G_2_EISRr(pa, &sys_10g_2_eisr)); 5626 data = BCMI_DINO_SYS_10G_2_EISRr_GET(sys_10g_2_eisr); 5627 break; 5628 case AN_CORE_0_1_2: 5629 PHYMOD_IF_ERR_RETURN( 5630 BCMI_DINO_READ_LIN_MISC_2_EISRr(pa, &line_misc_2_eisr)); 5631 data = BCMI_DINO_LIN_MISC_2_EISRr_GET(line_misc_2_eisr); 5632 break; 5633 case DP_MUX_DEMUX_FIFO: 5634 PHYMOD_IF_ERR_RETURN( 5635 BCMI_DINO_READ_MISC_EISRr(pa, &misc_eisr)); 5636 data = BCMI_DINO_MISC_EISRr_GET(misc_eisr); 5637 break; 5638 default: 5639 return PHYMOD_E_PARAM; 5640 } 5641 if (data & (0x1 << bit_pos)) { 5642 *intr_status |= (1 << intr_index); 5643 } else { 5644 *intr_status &= ~(1 << intr_index); 5645 } 5646 } else { 5647 if (intr_type & (1 << intr_index)) { 5648 switch(intr_grp) { 5649 case LINE_LINK_CORE_0: 5650 PHYMOD_IF_ERR_RETURN( 5651 BCMI_DINO_READ_LIN_25G_0_EIPRr(pa, &line_25g_0_eipr)); 5652 data = BCMI_DINO_LIN_25G_0_EIPRr_GET(line_25g_0_eipr); 5653 break; 5654 case LINE_LINK_CORE_1: 5655 PHYMOD_IF_ERR_RETURN( 5656 BCMI_DINO_READ_LIN_10G_1_EIPRr(pa, &line_10g_1_eipr)); 5657 data = BCMI_DINO_LIN_10G_1_EIPRr_GET(line_10g_1_eipr); 5658 break; 5659 case LINE_LINK_CORE_2: 5660 PHYMOD_IF_ERR_RETURN( 5661 BCMI_DINO_READ_LIN_10G_2_EIPRr(pa, &line_10g_2_eipr)); 5662 data = BCMI_DINO_LIN_10G_2_EIPRr_GET(line_10g_2_eipr); 5663 break; 5664 case SYS_LINK_CORE_0: 5665 PHYMOD_IF_ERR_RETURN( 5666 BCMI_DINO_READ_SYS_10G_0_EIPRr(pa, &sys_10g_0_eipr)); 5667 data = BCMI_DINO_SYS_10G_0_EIPRr_GET(sys_10g_0_eipr); 5668 break; 5669 case SYS_LINK_CORE_1: 5670 PHYMOD_IF_ERR_RETURN( 5671 BCMI_DINO_READ_SYS_10G_1_EIPRr(pa, &sys_10g_1_eipr)); 5672 data = BCMI_DINO_SYS_10G_1_EIPRr_GET(sys_10g_1_eipr); 5673 break; 5674 case SYS_LINK_CORE_2: 5675 PHYMOD_IF_ERR_RETURN( 5676 BCMI_DINO_READ_SYS_10G_2_EIPRr(pa, &sys_10g_2_eipr)); 5677 data = BCMI_DINO_SYS_10G_2_EIPRr_GET(sys_10g_2_eipr); 5678 break; 5679 case AN_CORE_0_1_2: 5680 PHYMOD_IF_ERR_RETURN( 5681 BCMI_DINO_READ_LIN_MISC_2_EIPRr(pa, &line_misc_2_eipr)); 5682 data = BCMI_DINO_LIN_MISC_2_EIPRr_GET(line_misc_2_eipr); 5683 break; 5684 case DP_MUX_DEMUX_FIFO: 5685 PHYMOD_IF_ERR_RETURN( 5686 BCMI_DINO_READ_MISC_EIPRr(pa, &misc_eipr)); 5687 data = BCMI_DINO_MISC_EIPRr_GET(misc_eipr); 5688 break; 5689 default: 5690 return PHYMOD_E_PARAM; 5691 } 5692 if (data & (0x1 << bit_pos)) { 5693 *intr_status |= (1 << intr_index); 5694 } else { 5695 *intr_status &= ~(1 << intr_index); 5696 } 5697 } 5698 } 5699 } 5700 5701 return PHYMOD_E_NONE; 5702 } 5703 5704 int _dino_phy_intr_status_clear(const phymod_phy_access_t* phy, uint32_t intr_type) 5705 { 5706 uint16_t intr_grp = 0; 5707 uint16_t bit_pos = 0; 5708 uint16_t intr_mask = 0; 5709 BCMI_DINO_LIN_25G_0_EISRr_t line_25g_0_eisr; 5710 BCMI_DINO_LIN_10G_1_EISRr_t line_10g_1_eisr; 5711 BCMI_DINO_LIN_10G_2_EISRr_t line_10g_2_eisr; 5712 BCMI_DINO_SYS_10G_0_EISRr_t sys_10g_0_eisr; 5713 BCMI_DINO_SYS_10G_1_EISRr_t sys_10g_1_eisr; 5714 BCMI_DINO_SYS_10G_2_EISRr_t sys_10g_2_eisr; 5715 BCMI_DINO_LIN_MISC_2_EISRr_t line_misc_2_eisr; 5716 BCMI_DINO_MISC_EISRr_t misc_eisr; 5717 const phymod_access_t *pa = &phy->access; 5718 5719 PHYMOD_MEMSET(&line_25g_0_eisr, 0, sizeof(BCMI_DINO_LIN_25G_0_EISRr_t)); 5720 PHYMOD_MEMSET(&line_10g_1_eisr, 0, sizeof(BCMI_DINO_LIN_10G_1_EISRr_t)); 5721 PHYMOD_MEMSET(&line_10g_2_eisr, 0, sizeof(BCMI_DINO_LIN_10G_2_EISRr_t)); 5722 PHYMOD_MEMSET(&sys_10g_0_eisr, 0, sizeof(BCMI_DINO_SYS_10G_0_EISRr_t)); 5723 PHYMOD_MEMSET(&sys_10g_1_eisr, 0, sizeof(BCMI_DINO_SYS_10G_1_EISRr_t)); 5724 PHYMOD_MEMSET(&sys_10g_2_eisr, 0, sizeof(BCMI_DINO_SYS_10G_2_EISRr_t)); 5725 PHYMOD_MEMSET(&line_misc_2_eisr, 0, sizeof(BCMI_DINO_LIN_MISC_2_EISRr_t)); 5726 PHYMOD_MEMSET(&misc_eisr, 0, sizeof(BCMI_DINO_MISC_EISRr_t)); 5727 5728 /* Get the interrupt bit postion in the reg and interrupt group */ 5729 PHYMOD_IF_ERR_RETURN( 5730 _dino_get_intr_reg(phy, intr_type, &bit_pos, &intr_grp)); 5731 intr_mask = 0x1 << bit_pos; 5732 /* Interrupt enable get on specified interrupt group */ 5733 switch(intr_grp) { 5734 case LINE_LINK_CORE_0: 5735 PHYMOD_IF_ERR_RETURN( 5736 BCMI_DINO_READ_LIN_25G_0_EISRr(pa, &line_25g_0_eisr)); 5737 BCMI_DINO_LIN_25G_0_EISRr_SET(line_25g_0_eisr, intr_mask); 5738 PHYMOD_IF_ERR_RETURN( 5739 BCMI_DINO_WRITE_LIN_25G_0_EISRr(pa, line_25g_0_eisr)); 5740 break; 5741 case LINE_LINK_CORE_1: 5742 PHYMOD_IF_ERR_RETURN( 5743 BCMI_DINO_READ_LIN_10G_1_EISRr(pa, &line_10g_1_eisr)); 5744 BCMI_DINO_LIN_10G_1_EISRr_SET(line_10g_1_eisr, intr_mask); 5745 PHYMOD_IF_ERR_RETURN( 5746 BCMI_DINO_WRITE_LIN_10G_1_EISRr(pa, line_10g_1_eisr)); 5747 break; 5748 case LINE_LINK_CORE_2: 5749 PHYMOD_IF_ERR_RETURN( 5750 BCMI_DINO_READ_LIN_10G_2_EISRr(pa, &line_10g_2_eisr)); 5751 BCMI_DINO_LIN_10G_2_EISRr_SET(line_10g_2_eisr, intr_mask); 5752 PHYMOD_IF_ERR_RETURN( 5753 BCMI_DINO_WRITE_LIN_10G_2_EISRr(pa, line_10g_2_eisr)); 5754 break; 5755 case SYS_LINK_CORE_0: 5756 PHYMOD_IF_ERR_RETURN( 5757 BCMI_DINO_READ_SYS_10G_0_EISRr(pa, &sys_10g_0_eisr)); 5758 BCMI_DINO_SYS_10G_0_EISRr_SET(sys_10g_0_eisr, intr_mask); 5759 PHYMOD_IF_ERR_RETURN( 5760 BCMI_DINO_WRITE_SYS_10G_0_EISRr(pa, sys_10g_0_eisr)); 5761 break; 5762 case SYS_LINK_CORE_1: 5763 PHYMOD_IF_ERR_RETURN( 5764 BCMI_DINO_READ_SYS_10G_1_EISRr(pa, &sys_10g_1_eisr)); 5765 BCMI_DINO_SYS_10G_1_EISRr_SET(sys_10g_1_eisr, intr_mask); 5766 PHYMOD_IF_ERR_RETURN( 5767 BCMI_DINO_WRITE_SYS_10G_1_EISRr(pa, sys_10g_1_eisr)); 5768 break; 5769 case SYS_LINK_CORE_2: 5770 PHYMOD_IF_ERR_RETURN( 5771 BCMI_DINO_READ_SYS_10G_2_EISRr(pa, &sys_10g_2_eisr)); 5772 BCMI_DINO_SYS_10G_2_EISRr_SET(sys_10g_2_eisr, intr_mask); 5773 PHYMOD_IF_ERR_RETURN( 5774 BCMI_DINO_WRITE_SYS_10G_2_EISRr(pa, sys_10g_2_eisr)); 5775 break; 5776 case AN_CORE_0_1_2: 5777 PHYMOD_IF_ERR_RETURN( 5778 BCMI_DINO_READ_LIN_MISC_2_EISRr(pa, &line_misc_2_eisr)); 5779 BCMI_DINO_LIN_MISC_2_EISRr_SET(line_misc_2_eisr, intr_mask); 5780 PHYMOD_IF_ERR_RETURN( 5781 BCMI_DINO_WRITE_LIN_MISC_2_EISRr(pa, line_misc_2_eisr)); 5782 break; 5783 case DP_MUX_DEMUX_FIFO: 5784 PHYMOD_IF_ERR_RETURN( 5785 BCMI_DINO_READ_MISC_EISRr(pa, &misc_eisr)); 5786 BCMI_DINO_MISC_EISRr_SET(misc_eisr, intr_mask); 5787 PHYMOD_IF_ERR_RETURN( 5788 BCMI_DINO_WRITE_MISC_EISRr(pa, misc_eisr)); 5789 break; 5790 default: 5791 return PHYMOD_E_PARAM; 5792 } 5793 5794 return PHYMOD_E_NONE; 5795 } 5796 5797 5798 int _dino_set_module_command(const phymod_access_t *pa, uint16_t xfer_addr, 5799 uint32_t slv_addr, unsigned char xfer_cnt, DINO_I2CM_CMD_E cmd) 5800 { 5801 BCMI_DINO_MODULE_CTL_CTLr_t module_ctrl; 5802 BCMI_DINO_MODULE_CTL_STSr_t mctrl_status; 5803 BCMI_DINO_XFER_CNTr_t mod_xfer_cnt; 5804 BCMI_DINO_ADDRr_t mod_add; 5805 BCMI_DINO_XFER_ADDRr_t mod_xfer_add; 5806 uint16_t retry_count = 500, data = 0; 5807 uint32_t wait_timeout_us = 0; 5808 wait_timeout_us = ((2*(xfer_cnt+1))*100)/5; 5809 5810 PHYMOD_MEMSET(&module_ctrl, 0, sizeof(BCMI_DINO_MODULE_CTL_CTLr_t)); 5811 PHYMOD_MEMSET(&mod_xfer_add, 0, sizeof(BCMI_DINO_XFER_ADDRr_t)); 5812 PHYMOD_MEMSET(&mod_xfer_cnt, 0, sizeof(BCMI_DINO_XFER_CNTr_t)); 5813 PHYMOD_MEMSET(&mctrl_status, 0, sizeof(BCMI_DINO_MODULE_CTL_STSr_t)); 5814 PHYMOD_MEMSET(&mod_add, 0, sizeof(BCMI_DINO_ADDRr_t)); 5815 if (cmd == DINO_FLUSH) { 5816 BCMI_DINO_MODULE_CTL_CTLr_SET(module_ctrl, 0xC000); 5817 PHYMOD_IF_ERR_RETURN( 5818 BCMI_DINO_WRITE_MODULE_CTL_CTLr(pa, module_ctrl)); 5819 } else { 5820 BCMI_DINO_XFER_ADDRr_SET(mod_xfer_add, xfer_addr); 5821 BCMI_DINO_XFER_CNTr_XFER_CNTf_SET(mod_xfer_cnt, xfer_cnt); 5822 PHYMOD_IF_ERR_RETURN( 5823 BCMI_DINO_WRITE_XFER_ADDRr(pa, mod_xfer_add)); 5824 PHYMOD_IF_ERR_RETURN( 5825 BCMI_DINO_WRITE_XFER_CNTr(pa, mod_xfer_cnt)); 5826 if (cmd == DINO_CURRENT_ADDRESS_READ) { 5827 BCMI_DINO_MODULE_CTL_CTLr_SET(module_ctrl, 0x8001); 5828 PHYMOD_IF_ERR_RETURN( 5829 BCMI_DINO_WRITE_MODULE_CTL_CTLr(pa, module_ctrl)); 5830 } else if (cmd == DINO_RANDOM_ADDRESS_READ ) { 5831 BCMI_DINO_ADDRr_SET(mod_add, slv_addr); 5832 BCMI_DINO_MODULE_CTL_CTLr_SET(module_ctrl, 0x8003); 5833 PHYMOD_IF_ERR_RETURN( 5834 BCMI_DINO_WRITE_ADDRr(pa,mod_add)); 5835 PHYMOD_IF_ERR_RETURN( 5836 BCMI_DINO_WRITE_MODULE_CTL_CTLr(pa,module_ctrl)); 5837 } else { 5838 BCMI_DINO_ADDRr_SET(mod_add, slv_addr); 5839 BCMI_DINO_MODULE_CTL_CTLr_SET(module_ctrl, 0x8022); 5840 PHYMOD_IF_ERR_RETURN( 5841 BCMI_DINO_WRITE_ADDRr(pa, mod_add)); 5842 PHYMOD_IF_ERR_RETURN( 5843 BCMI_DINO_WRITE_MODULE_CTL_CTLr(pa, module_ctrl)); 5844 } 5845 } 5846 5847 if ((cmd == DINO_CURRENT_ADDRESS_READ) || 5848 (cmd == DINO_RANDOM_ADDRESS_READ) || 5849 (cmd == DINO_I2C_WRITE)) { 5850 do { 5851 PHYMOD_IF_ERR_RETURN( 5852 BCMI_DINO_READ_MODULE_CTL_STSr(pa,&mctrl_status)); 5853 data = BCMI_DINO_MODULE_CTL_STSr_XACTION_DONEf_GET(mctrl_status); 5854 PHYMOD_USLEEP(wait_timeout_us); 5855 } while((data == 0) && --retry_count); 5856 if(!retry_count) { 5857 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_TIMEOUT, (_PHYMOD_MSG("Module controller: I2C transaction failed.."))); 5858 } 5859 } 5860 BCMI_DINO_MODULE_CTL_CTLr_SET(module_ctrl, 0x3); 5861 PHYMOD_IF_ERR_RETURN( 5862 BCMI_DINO_WRITE_MODULE_CTL_CTLr(pa, module_ctrl)); 5863 5864 return PHYMOD_E_NONE; 5865 } 5866 5867 int _dino_phy_i2c_read(const phymod_access_t *pa, uint32_t slv_dev_addr, uint32_t start_addr, uint32_t no_of_bytes, uint8_t* read_data) 5868 { 5869 uint32_t index = 0; 5870 uint16_t lane_mask = 0; 5871 uint32_t rd_data = 0; 5872 uint32_t lower_page_bytes = 0; 5873 uint32_t upper_page_bytes = 0; 5874 uint32_t upper_page_flag = 0; 5875 uint32_t lower_page_start_addr = 0; 5876 uint32_t upper_page_start_addr = 0; 5877 uint32_t lower_page_flag = 0; 5878 uint16_t START_OF_NVRAM = 0x0; 5879 BCMI_DINO_GEN_CTL3r_t gen_ctrl3; 5880 BCMI_DINO_GEN_CTL1r_t gen_ctrl1; 5881 BCMI_DINO_DEV_IDr_t dev_id; 5882 BCMI_DINO_XFER_ADDRr_t mod_xfer_add; 5883 BCMI_DINO_GENERAL_PURPOSE_IO_CTL0r_t io_ctrl0; 5884 BCMI_DINO_GENERAL_PURPOSE_IO_CTL1r_t io_ctrl1; 5885 BCMI_DINO_GENERAL_PURPOSE_IO_CTL2r_t io_ctrl2; 5886 BCMI_DINO_MCTL_RAM_MDIO_CTLr_t mctl_ram_mdio_ctrl; 5887 5888 PHYMOD_MEMSET(&io_ctrl0, 0, sizeof(BCMI_DINO_GENERAL_PURPOSE_IO_CTL0r_t)); 5889 PHYMOD_MEMSET(&io_ctrl1, 0, sizeof(BCMI_DINO_GENERAL_PURPOSE_IO_CTL1r_t)); 5890 PHYMOD_MEMSET(&io_ctrl2, 0, sizeof(BCMI_DINO_GENERAL_PURPOSE_IO_CTL2r_t)); 5891 PHYMOD_MEMSET(&gen_ctrl3, 0, sizeof(BCMI_DINO_GEN_CTL3r_t)); 5892 PHYMOD_MEMSET(&gen_ctrl1, 0, sizeof(BCMI_DINO_GEN_CTL1r_t)); 5893 PHYMOD_MEMSET(&dev_id, 0, sizeof(BCMI_DINO_DEV_IDr_t)); 5894 PHYMOD_MEMSET(&mod_xfer_add, 0, sizeof(BCMI_DINO_XFER_ADDRr_t)); 5895 PHYMOD_MEMSET(&mctl_ram_mdio_ctrl, 0, sizeof(BCMI_DINO_MCTL_RAM_MDIO_CTLr_t)); 5896 5897 if(start_addr > 255) { 5898 return PHYMOD_E_PARAM; 5899 } 5900 5901 /* qsfp mode or legacy mode */ 5902 PHYMOD_IF_ERR_RETURN( 5903 BCMI_DINO_READ_GEN_CTL3r(pa, &gen_ctrl3)); 5904 BCMI_DINO_GEN_CTL3r_QSFP_MODEf_SET(gen_ctrl3, 1); 5905 PHYMOD_IF_ERR_RETURN( 5906 BCMI_DINO_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 5907 5908 /* qsfp mode reset at begining */ 5909 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL1r(pa, &gen_ctrl1)); 5910 gen_ctrl1.v[0] &= ~(1 << 6); 5911 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 5912 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL1r(pa, &gen_ctrl1)); 5913 gen_ctrl1.v[0] |= (1 << 6); 5914 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 5915 5916 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 5917 5918 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL3r(pa, &gen_ctrl3)); 5919 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_MCTL_RAM_MDIO_CTLr(pa, &mctl_ram_mdio_ctrl)); 5920 switch (lane_mask) { 5921 case 0x3ff: 5922 case 0xffc: 5923 case 0x7fe: 5924 case 0xf: 5925 case 0x1: 5926 case 0x2: 5927 case 0x4: 5928 case 0x8: 5929 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL3Bf_SET(gen_ctrl3, 0); 5930 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL3Bf_SET(mctl_ram_mdio_ctrl, 0); 5931 break; 5932 case 0x10: 5933 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL4Bf_SET(gen_ctrl3, 0); 5934 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL4Bf_SET(mctl_ram_mdio_ctrl, 0); 5935 break; 5936 case 0x20: 5937 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL5Bf_SET(gen_ctrl3, 0); 5938 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL5Bf_SET(mctl_ram_mdio_ctrl, 0); 5939 break; 5940 case 0x40: 5941 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL6Bf_SET(gen_ctrl3, 0); 5942 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL6Bf_SET(mctl_ram_mdio_ctrl, 0); 5943 break; 5944 case 0x80: 5945 case 0xf0: 5946 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL7Bf_SET(gen_ctrl3, 0); 5947 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL7Bf_SET(mctl_ram_mdio_ctrl, 0); 5948 break; 5949 case 0x100: 5950 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL8Bf_SET(gen_ctrl3, 0); 5951 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL8Bf_SET(mctl_ram_mdio_ctrl, 0); 5952 break; 5953 case 0x200: 5954 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL9Bf_SET(gen_ctrl3, 0); 5955 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL9Bf_SET(mctl_ram_mdio_ctrl, 0); 5956 break; 5957 case 0x400: 5958 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL10Bf_SET(gen_ctrl3, 0); 5959 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL10Bf_SET(mctl_ram_mdio_ctrl, 0); 5960 break; 5961 case 0x800: 5962 case 0xf00: 5963 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL11Bf_SET(gen_ctrl3, 0); 5964 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL11Bf_SET(mctl_ram_mdio_ctrl, 0); 5965 break; 5966 } 5967 5968 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 5969 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_MCTL_RAM_MDIO_CTLr(pa, mctl_ram_mdio_ctrl)); 5970 /* Configure the slave device ID default is 0x50 */ 5971 PHYMOD_IF_ERR_RETURN( 5972 BCMI_DINO_READ_DEV_IDr(pa, &dev_id)); 5973 BCMI_DINO_DEV_IDr_SL_DEV_ADDf_SET(dev_id, slv_dev_addr); 5974 PHYMOD_IF_ERR_RETURN( 5975 BCMI_DINO_WRITE_DEV_IDr(pa, dev_id)); 5976 5977 if(no_of_bytes == 0) { 5978 /* Perform module controller reset and FLUSH */ 5979 PHYMOD_IF_ERR_RETURN( 5980 _dino_set_module_command(pa, 0, 0, 0, DINO_FLUSH)); 5981 } 5982 if ((no_of_bytes + start_addr) >= 256) { 5983 no_of_bytes = 255 - start_addr + 1; 5984 } 5985 5986 /* To determine page to be written is lower page or upper page or 5987 * both lower and upper page 5988 */ 5989 if ((start_addr+no_of_bytes - 1) > 127) { 5990 /* lower page */ 5991 if (start_addr <= 127) { 5992 lower_page_bytes = 127 - start_addr + 1; 5993 lower_page_flag = 1; 5994 lower_page_start_addr = start_addr; 5995 } 5996 /* upper page */ 5997 if ((start_addr + no_of_bytes) > 127) { 5998 upper_page_flag = 1; 5999 upper_page_bytes = no_of_bytes - lower_page_bytes; 6000 if(start_addr > 128) { 6001 upper_page_start_addr = start_addr; 6002 } else { 6003 upper_page_start_addr = 128; 6004 } 6005 } 6006 } else { /* only lower page */ 6007 lower_page_bytes = no_of_bytes; 6008 lower_page_flag = 1; 6009 lower_page_start_addr = start_addr; 6010 } 6011 6012 if (lower_page_flag) { 6013 PHYMOD_IF_ERR_RETURN( 6014 _dino_set_module_command(pa, DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 6015 lower_page_start_addr, lower_page_start_addr, lower_page_bytes - 1, DINO_RANDOM_ADDRESS_READ)); 6016 lower_page_flag = 0; 6017 } 6018 6019 /* Need to check with chip team how we can read upper page */ 6020 if (upper_page_flag) { 6021 PHYMOD_IF_ERR_RETURN( 6022 _dino_set_module_command(pa, DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 6023 upper_page_start_addr, upper_page_start_addr, upper_page_bytes - 1, DINO_RANDOM_ADDRESS_READ)); 6024 upper_page_flag = 0; 6025 } 6026 /* Read data from NVRAM using I2C*/ 6027 for (index = 0; index < no_of_bytes; index++) { 6028 PHYMOD_IF_ERR_RETURN( 6029 PHYMOD_BUS_READ(pa, 0x10000 + DINO_MODULE_CNTRL_RAM_NVR0_ADR + start_addr + index , &rd_data)); 6030 read_data[index] = (unsigned char) (rd_data & 0xff); 6031 } 6032 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL3r(pa, &gen_ctrl3)); 6033 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_MCTL_RAM_MDIO_CTLr(pa, &mctl_ram_mdio_ctrl)); 6034 switch (lane_mask) { 6035 case 0x3ff: 6036 case 0xffc: 6037 case 0x7fe: 6038 case 0xf: 6039 case 0x1: 6040 case 0x2: 6041 case 0x4: 6042 case 0x8: 6043 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL3Bf_SET(gen_ctrl3, 1); 6044 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL3Bf_SET(mctl_ram_mdio_ctrl, 1); 6045 break; 6046 case 0x10: 6047 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL4Bf_SET(gen_ctrl3, 1); 6048 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL4Bf_SET(mctl_ram_mdio_ctrl, 1); 6049 break; 6050 case 0x20: 6051 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL5Bf_SET(gen_ctrl3, 1); 6052 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL5Bf_SET(mctl_ram_mdio_ctrl, 1); 6053 break; 6054 case 0x40: 6055 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL6Bf_SET(gen_ctrl3, 1); 6056 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL6Bf_SET(mctl_ram_mdio_ctrl, 1); 6057 break; 6058 case 0x80: 6059 case 0xf0: 6060 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL7Bf_SET(gen_ctrl3, 1); 6061 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL7Bf_SET(mctl_ram_mdio_ctrl, 1); 6062 break; 6063 case 0x100: 6064 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL8Bf_SET(gen_ctrl3, 1); 6065 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL8Bf_SET(mctl_ram_mdio_ctrl, 1); 6066 break; 6067 case 0x200: 6068 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL9Bf_SET(gen_ctrl3, 1); 6069 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL9Bf_SET(mctl_ram_mdio_ctrl, 1); 6070 break; 6071 case 0x400: 6072 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL10Bf_SET(gen_ctrl3, 1); 6073 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL10Bf_SET(mctl_ram_mdio_ctrl, 1); 6074 break; 6075 case 0x800: 6076 case 0xf00: 6077 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL11Bf_SET(gen_ctrl3, 1); 6078 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL11Bf_SET(mctl_ram_mdio_ctrl, 1); 6079 break; 6080 } 6081 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 6082 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_MCTL_RAM_MDIO_CTLr(pa, mctl_ram_mdio_ctrl)); 6083 6084 return PHYMOD_E_NONE; 6085 } 6086 6087 int _dino_phy_i2c_write(const phymod_access_t *pa, uint32_t slv_dev_addr, uint32_t start_addr, uint32_t no_of_bytes, const uint8_t* write_data) 6088 { 6089 uint16_t lane_mask = 0; 6090 uint32_t index = 0; 6091 uint32_t lower_page_bytes = 0; 6092 uint32_t upper_page_bytes = 0; 6093 uint32_t upper_page_flag = 0; 6094 uint32_t lower_page_flag = 0; 6095 uint32_t lower_page_start_addr = 0; 6096 uint32_t upper_page_start_addr = 0; 6097 uint16_t START_OF_NVRAM = 0x0; 6098 BCMI_DINO_GEN_CTL3r_t gen_ctrl3; 6099 BCMI_DINO_GEN_CTL1r_t gen_ctrl1; 6100 BCMI_DINO_DEV_IDr_t dev_id; 6101 BCMI_DINO_XFER_ADDRr_t mod_xfer_add; 6102 BCMI_DINO_GENERAL_PURPOSE_IO_CTL0r_t io_ctrl0; 6103 BCMI_DINO_GENERAL_PURPOSE_IO_CTL1r_t io_ctrl1; 6104 BCMI_DINO_GENERAL_PURPOSE_IO_CTL2r_t io_ctrl2; 6105 BCMI_DINO_MCTL_RAM_MDIO_CTLr_t mctl_ram_mdio_ctrl; 6106 6107 PHYMOD_MEMSET(&io_ctrl0, 0, sizeof(BCMI_DINO_GENERAL_PURPOSE_IO_CTL0r_t)); 6108 PHYMOD_MEMSET(&io_ctrl1, 0, sizeof(BCMI_DINO_GENERAL_PURPOSE_IO_CTL1r_t)); 6109 PHYMOD_MEMSET(&io_ctrl2, 0, sizeof(BCMI_DINO_GENERAL_PURPOSE_IO_CTL2r_t)); 6110 PHYMOD_MEMSET(&gen_ctrl3, 0, sizeof(BCMI_DINO_GEN_CTL3r_t)); 6111 PHYMOD_MEMSET(&gen_ctrl1, 0, sizeof(BCMI_DINO_GEN_CTL1r_t)); 6112 PHYMOD_MEMSET(&dev_id, 0, sizeof(BCMI_DINO_DEV_IDr_t)); 6113 PHYMOD_MEMSET(&mod_xfer_add, 0, sizeof(BCMI_DINO_XFER_ADDRr_t)); 6114 PHYMOD_MEMSET(&mctl_ram_mdio_ctrl, 0, sizeof(BCMI_DINO_MCTL_RAM_MDIO_CTLr_t)); 6115 6116 if(start_addr > 255) { 6117 return PHYMOD_E_PARAM; 6118 } 6119 6120 /* qsfp mode or legacy mode */ 6121 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL3r(pa, &gen_ctrl3)); 6122 BCMI_DINO_GEN_CTL3r_QSFP_MODEf_SET(gen_ctrl3, 1); 6123 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 6124 6125 /* qsfp mode reset at begining */ 6126 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL1r(pa, &gen_ctrl1)); 6127 gen_ctrl1.v[0] &= ~(1 << 6); 6128 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 6129 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL1r(pa, &gen_ctrl1)); 6130 gen_ctrl1.v[0] |= (1 << 6); 6131 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL1r(pa, gen_ctrl1)); 6132 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6133 6134 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL3r(pa, &gen_ctrl3)); 6135 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_MCTL_RAM_MDIO_CTLr(pa, &mctl_ram_mdio_ctrl)); 6136 6137 switch (lane_mask) { 6138 case 0x3ff: 6139 case 0xffc: 6140 case 0x7fe: 6141 case 0xf: 6142 case 0x1: 6143 case 0x2: 6144 case 0x4: 6145 case 0x8: 6146 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL3Bf_SET(gen_ctrl3, 0); 6147 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL3Bf_SET(mctl_ram_mdio_ctrl, 0); 6148 break; 6149 case 0x10: 6150 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL4Bf_SET(gen_ctrl3, 0); 6151 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL4Bf_SET(mctl_ram_mdio_ctrl, 0); 6152 break; 6153 case 0x20: 6154 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL5Bf_SET(gen_ctrl3, 0); 6155 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL5Bf_SET(mctl_ram_mdio_ctrl, 0); 6156 break; 6157 case 0x40: 6158 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL6Bf_SET(gen_ctrl3, 0); 6159 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL6Bf_SET(mctl_ram_mdio_ctrl, 0); 6160 break; 6161 case 0x80: 6162 case 0xf0: 6163 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL7Bf_SET(gen_ctrl3, 0); 6164 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL7Bf_SET(mctl_ram_mdio_ctrl, 0); 6165 break; 6166 case 0x100: 6167 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL8Bf_SET(gen_ctrl3, 0); 6168 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL8Bf_SET(mctl_ram_mdio_ctrl, 0); 6169 break; 6170 case 0x200: 6171 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL9Bf_SET(gen_ctrl3, 0); 6172 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL9Bf_SET(mctl_ram_mdio_ctrl, 0); 6173 break; 6174 case 0x400: 6175 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL10Bf_SET(gen_ctrl3, 0); 6176 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL10Bf_SET(mctl_ram_mdio_ctrl, 0); 6177 break; 6178 case 0x800: 6179 case 0xf00: 6180 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL11Bf_SET(gen_ctrl3, 0); 6181 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL11Bf_SET(mctl_ram_mdio_ctrl, 0); 6182 break; 6183 } 6184 6185 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 6186 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_MCTL_RAM_MDIO_CTLr(pa, mctl_ram_mdio_ctrl)); 6187 6188 /* Configure the slave device ID default is 0x50 */ 6189 PHYMOD_IF_ERR_RETURN( 6190 BCMI_DINO_READ_DEV_IDr(pa, &dev_id)); 6191 BCMI_DINO_DEV_IDr_SL_DEV_ADDf_SET(dev_id, slv_dev_addr); 6192 PHYMOD_IF_ERR_RETURN( 6193 BCMI_DINO_WRITE_DEV_IDr(pa, dev_id)); 6194 6195 if(no_of_bytes == 0) { 6196 /* Perform module controller reset and FLUSH */ 6197 PHYMOD_IF_ERR_RETURN( 6198 _dino_set_module_command(pa, 0, 0, 0, DINO_FLUSH)); 6199 } 6200 /* if requested number of bytes are not within the boundary (0- 255) 6201 * need to calculate what maximum number of bytes can be taken into 6202 * account for reading or writing to module 6203 */ 6204 if ((no_of_bytes + start_addr) >= 256) { 6205 no_of_bytes = 255 - start_addr + 1; 6206 } 6207 6208 /* To determine page to be written is lower page or upper page or 6209 * both lower and upper page 6210 */ 6211 if ((start_addr + no_of_bytes - 1) > 127) { 6212 /* lower page */ 6213 if (start_addr <= 127) { 6214 lower_page_bytes = 127 - start_addr + 1; 6215 lower_page_flag = 1; 6216 lower_page_start_addr = start_addr; 6217 } 6218 /* upper page */ 6219 if ((start_addr + no_of_bytes) > 127) { 6220 upper_page_flag = 1; 6221 upper_page_bytes = no_of_bytes - lower_page_bytes; 6222 if(start_addr > 128) { 6223 upper_page_start_addr = start_addr; 6224 } else { 6225 upper_page_start_addr = 128; 6226 } 6227 } 6228 } else { /* only lower page */ 6229 lower_page_bytes = no_of_bytes; 6230 lower_page_flag = 1; 6231 lower_page_start_addr = start_addr; 6232 } 6233 6234 /* Write data to NVRAM */ 6235 for (index = 0; index < no_of_bytes; index++) { 6236 PHYMOD_IF_ERR_RETURN( 6237 PHYMOD_BUS_WRITE(pa,0x10000 + DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + start_addr + index, write_data[index])); 6238 } 6239 6240 if(lower_page_flag) { 6241 for (index = 0; index < (lower_page_bytes / 4); index ++) { 6242 PHYMOD_IF_ERR_RETURN( 6243 _dino_set_module_command(pa, DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 6244 lower_page_start_addr + (4 * index), lower_page_start_addr + (4 * index), 3, DINO_I2C_WRITE)); 6245 } 6246 if ((lower_page_bytes % 4) > 0) { 6247 PHYMOD_IF_ERR_RETURN( 6248 _dino_set_module_command(pa, DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 6249 lower_page_start_addr + (4 * index), lower_page_start_addr + (4 * index), 6250 ((lower_page_bytes % 4) - 1), DINO_I2C_WRITE)); 6251 } 6252 lower_page_flag = 0; 6253 } 6254 6255 if(upper_page_flag) { 6256 for (index = 0; index < (upper_page_bytes / 4); index++) { 6257 PHYMOD_IF_ERR_RETURN( 6258 _dino_set_module_command(pa, (DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 6259 upper_page_start_addr + (4 * index)), upper_page_start_addr + (4 * index), 3, DINO_I2C_WRITE)); 6260 } 6261 if ((upper_page_bytes%4) > 0) { 6262 PHYMOD_IF_ERR_RETURN( 6263 _dino_set_module_command(pa, (DINO_MODULE_CNTRL_RAM_NVR0_ADR + START_OF_NVRAM + 6264 upper_page_start_addr + (4 * index)), upper_page_start_addr + (4 * index), 6265 ((upper_page_bytes % 4) - 1), DINO_I2C_WRITE)); 6266 } 6267 upper_page_flag = 0; 6268 } 6269 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_GEN_CTL3r(pa, &gen_ctrl3)); 6270 PHYMOD_IF_ERR_RETURN(BCMI_DINO_READ_MCTL_RAM_MDIO_CTLr(pa, &mctl_ram_mdio_ctrl)); 6271 switch (lane_mask) { 6272 case 0x3ff: 6273 case 0xffc: 6274 case 0x7fe: 6275 case 0xf: 6276 case 0x1: 6277 case 0x2: 6278 case 0x4: 6279 case 0x8: 6280 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL3Bf_SET(gen_ctrl3, 1); 6281 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL3Bf_SET(mctl_ram_mdio_ctrl, 1); 6282 break; 6283 case 0x10: 6284 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL4Bf_SET(gen_ctrl3, 1); 6285 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL4Bf_SET(mctl_ram_mdio_ctrl, 1); 6286 break; 6287 case 0x20: 6288 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL5Bf_SET(gen_ctrl3, 1); 6289 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL5Bf_SET(mctl_ram_mdio_ctrl, 1); 6290 break; 6291 case 0x40: 6292 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL6Bf_SET(gen_ctrl3, 1); 6293 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL6Bf_SET(mctl_ram_mdio_ctrl, 1); 6294 break; 6295 case 0x80: 6296 case 0xf0: 6297 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL7Bf_SET(gen_ctrl3, 1); 6298 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL7Bf_SET(mctl_ram_mdio_ctrl, 1); 6299 break; 6300 case 0x100: 6301 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL8Bf_SET(gen_ctrl3, 1); 6302 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL8Bf_SET(mctl_ram_mdio_ctrl, 1); 6303 break; 6304 case 0x200: 6305 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL9Bf_SET(gen_ctrl3, 1); 6306 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL9Bf_SET(mctl_ram_mdio_ctrl, 1); 6307 break; 6308 case 0x400: 6309 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL10Bf_SET(gen_ctrl3, 1); 6310 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL10Bf_SET(mctl_ram_mdio_ctrl, 1); 6311 break; 6312 case 0x800: 6313 case 0xf00: 6314 BCMI_DINO_GEN_CTL3r_EXTMOD_SEL11Bf_SET(gen_ctrl3, 1); 6315 BCMI_DINO_MCTL_RAM_MDIO_CTLr_MD_EXTMOD_SEL11Bf_SET(mctl_ram_mdio_ctrl, 1); 6316 break; 6317 } 6318 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_GEN_CTL3r(pa, gen_ctrl3)); 6319 PHYMOD_IF_ERR_RETURN(BCMI_DINO_WRITE_MCTL_RAM_MDIO_CTLr(pa, mctl_ram_mdio_ctrl)); 6320 6321 return PHYMOD_E_NONE; 6322 } 6323 6324 int _dino_phy_rptr_rtmr_mode_set(const phymod_phy_access_t* phy, uint16_t op_mode) 6325 { 6326 phymod_phy_inf_config_t config_cpy; 6327 uint16_t rptr_rtmr_mode = 0; 6328 uint16_t lane_idx = 0; 6329 uint16_t lane_mask = 0; 6330 uint16_t gpreg_data = 0; 6331 int num_lanes = 0; 6332 uint32_t chip_id = 0; 6333 uint32_t rev_id = 0; 6334 const phymod_access_t *pa = &phy->access; 6335 PHYMOD_MEMSET(&config_cpy, 0, sizeof(phymod_phy_inf_config_t)); 6336 6337 lane_mask = PHYMOD_ACC_LANE_MASK(pa); 6338 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev_id)); 6339 DINO_GET_NUM_LANES(chip_id, num_lanes); 6340 rptr_rtmr_mode = (op_mode == phymodOperationModeRetimer) ? DINO_TX_RETIMER : DINO_TX_REPEATER; 6341 6342 /* Configure repeater/retimer mode on both line side and system side*/ 6343 for (lane_idx = 0; lane_idx < num_lanes; lane_idx++) { 6344 if ((lane_mask >> lane_idx) & 0x1) { 6345 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR+lane_idx), gpreg_data); 6346 if (((gpreg_data & DINO_LINE_TX_TIMING_MODE_MASK) >> DINO_LINE_TX_TIMING_MODE_SHIFT) == DINO_TX_REPEATER_ULL) { 6347 PHYMOD_DIAG_OUT(("ULL datapath is set:: This needs to be cleared for setting repeater/retimer mode \n")); 6348 return PHYMOD_E_NONE; 6349 } else { 6350 gpreg_data &= ~(DINO_LINE_TX_TIMING_MODE_MASK); 6351 gpreg_data |= (rptr_rtmr_mode << DINO_LINE_TX_TIMING_MODE_SHIFT); 6352 } 6353 if (((gpreg_data & DINO_SYS_TX_TIMING_MODE_MASK) >> DINO_SYS_TX_TIMING_MODE_SHIFT) == DINO_TX_REPEATER_ULL) { 6354 PHYMOD_DIAG_OUT(("ULL datapath is set:: This needs to be cleared for setting repeater/retimer mode \n")); 6355 return PHYMOD_E_NONE; 6356 } else { 6357 gpreg_data &= ~(DINO_SYS_TX_TIMING_MODE_MASK); 6358 gpreg_data |= (rptr_rtmr_mode << DINO_SYS_TX_TIMING_MODE_SHIFT); 6359 } 6360 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR+lane_idx), gpreg_data); 6361 } 6362 } 6363 /* Notify the firmware about the configurations */ 6364 PHYMOD_IF_ERR_RETURN(_dino_fw_enable(pa)); 6365 6366 return PHYMOD_E_NONE; 6367 } 6368 6369 int _dino_bcast_enable_set(const phymod_core_access_t* core, uint16_t bcast_en) 6370 { 6371 const phymod_access_t *pa = &core->access; 6372 BCMI_DINO_MDIO_PHYAD_CTLr_t mdio_phyad_ctl; 6373 PHYMOD_MEMSET(&mdio_phyad_ctl, 0, sizeof(BCMI_DINO_MDIO_PHYAD_CTLr_t)); 6374 PHYMOD_IF_ERR_RETURN( 6375 BCMI_DINO_READ_MDIO_PHYAD_CTLr(pa, &mdio_phyad_ctl)); 6376 BCMI_DINO_MDIO_PHYAD_CTLr_MDIO_BRDCST_ENf_SET(mdio_phyad_ctl, bcast_en); 6377 PHYMOD_IF_ERR_RETURN( 6378 BCMI_DINO_WRITE_MDIO_PHYAD_CTLr(pa, mdio_phyad_ctl)); 6379 6380 return PHYMOD_E_NONE; 6381 } 6382 int _dino_phy_gpio_config_set(const phymod_access_t* pa, int pin_number, phymod_gpio_mode_t gpio_mode) 6383 { 6384 uint16_t data = 0; 6385 uint32_t chip_id = 0; 6386 uint32_t rev = 0; 6387 BCMI_DINO_GPIO_0_CTLr_t pad_ctrl_gpio_0_ctrl; 6388 BCMI_DINO_GPIO_1_CTLr_t pad_ctrl_gpio_1_ctrl; 6389 BCMI_DINO_GPIO_2_CTLr_t pad_ctrl_gpio_2_ctrl; 6390 BCMI_DINO_GPIO_3_CTLr_t pad_ctrl_gpio_3_ctrl; 6391 BCMI_DINO_GPIO_4_CTLr_t pad_ctrl_gpio_4_ctrl; 6392 BCMI_DINO_GPIO_5_CTLr_t pad_ctrl_gpio_5_ctrl; 6393 BCMI_DINO_GPIO_6_CTLr_t pad_ctrl_gpio_6_ctrl; 6394 BCMI_DINO_GPIO_7_CTLr_t pad_ctrl_gpio_7_ctrl; 6395 BCMI_DINO_GPIO_8_CTLr_t pad_ctrl_gpio_8_ctrl; 6396 BCMI_DINO_GPIO_9_CTLr_t pad_ctrl_gpio_9_ctrl; 6397 BCMI_DINO_GPIO_10_CTLr_t pad_ctrl_gpio_10_ctrl; 6398 BCMI_DINO_GPIO_11_CTLr_t pad_ctrl_gpio_11_ctrl; 6399 BCMI_DINO_GPIO_12_CTLr_t pad_ctrl_gpio_12_ctrl; 6400 BCMI_DINO_GPIO_13_CTLr_t pad_ctrl_gpio_13_ctrl; 6401 BCMI_DINO_GPIO_14_CTLr_t pad_ctrl_gpio_14_ctrl; 6402 BCMI_DINO_GPIO_15_CTLr_t pad_ctrl_gpio_15_ctrl; 6403 BCMI_DINO_GPIO_16_CTLr_t pad_ctrl_gpio_16_ctrl; 6404 BCMI_DINO_GPIO_17_CTLr_t pad_ctrl_gpio_17_ctrl; 6405 BCMI_DINO_OPTXENB1_A_CTLr_t pad_ctrl_optxenb1_a; 6406 BCMI_DINO_OPTXENB1_B_CTLr_t pad_ctrl_optxenb1_b; 6407 BCMI_DINO_OPTXENB1_C_CTLr_t pad_ctrl_optxenb1_c; 6408 BCMI_DINO_MOD_ABS_3_CTLr_t pad_ctrl_mod_abs_3_ctrl; 6409 BCMI_DINO_MOD_ABS_4_CTLr_t pad_ctrl_mod_abs_4_ctrl; 6410 BCMI_DINO_MOD_ABS_5_CTLr_t pad_ctrl_mod_abs_5_ctrl; 6411 BCMI_DINO_MOD_ABS_6_CTLr_t pad_ctrl_mod_abs_6_ctrl; 6412 BCMI_DINO_MOD_ABS_7_CTLr_t pad_ctrl_mod_abs_7_ctrl; 6413 BCMI_DINO_MOD_ABS_8_CTLr_t pad_ctrl_mod_abs_8_ctrl; 6414 BCMI_DINO_MOD_ABS_9_CTLr_t pad_ctrl_mod_abs_9_ctrl; 6415 BCMI_DINO_MOD_ABS_10_CTLr_t pad_ctrl_mod_abs_10_ctrl; 6416 BCMI_DINO_MOD_ABS_11_CTLr_t pad_ctrl_mod_abs_11_ctrl; 6417 BCMI_DINO_OPRXLOS_4_CTLr_t pad_ctrl_oprxlos_4_ctrl; 6418 BCMI_DINO_OPRXLOS_5_CTLr_t pad_ctrl_oprxlos_5_ctrl; 6419 BCMI_DINO_OPRXLOS_6_CTLr_t pad_ctrl_oprxlos_6_ctrl; 6420 BCMI_DINO_OPRXLOS_7_CTLr_t pad_ctrl_oprxlos_7_ctrl; 6421 BCMI_DINO_OPRXLOS_8_CTLr_t pad_ctrl_oprxlos_8_ctrl; 6422 BCMI_DINO_OPRXLOS_9_CTLr_t pad_ctrl_oprxlos_9_ctrl; 6423 BCMI_DINO_OPRXLOS_10_CTLr_t pad_ctrl_oprxlos_10_ctrl; 6424 BCMI_DINO_OPRXLOS_11_CTLr_t pad_ctrl_oprxlos_11_ctrl; 6425 PHYMOD_MEMSET(&pad_ctrl_gpio_0_ctrl, 0, sizeof(BCMI_DINO_GPIO_0_CTLr_t)); 6426 PHYMOD_MEMSET(&pad_ctrl_gpio_1_ctrl, 0, sizeof(BCMI_DINO_GPIO_1_CTLr_t)); 6427 PHYMOD_MEMSET(&pad_ctrl_gpio_2_ctrl, 0, sizeof(BCMI_DINO_GPIO_2_CTLr_t)); 6428 PHYMOD_MEMSET(&pad_ctrl_gpio_3_ctrl, 0, sizeof(BCMI_DINO_GPIO_3_CTLr_t)); 6429 PHYMOD_MEMSET(&pad_ctrl_gpio_4_ctrl, 0, sizeof(BCMI_DINO_GPIO_4_CTLr_t)); 6430 PHYMOD_MEMSET(&pad_ctrl_gpio_5_ctrl, 0, sizeof(BCMI_DINO_GPIO_5_CTLr_t)); 6431 PHYMOD_MEMSET(&pad_ctrl_gpio_6_ctrl, 0, sizeof(BCMI_DINO_GPIO_6_CTLr_t)); 6432 PHYMOD_MEMSET(&pad_ctrl_gpio_7_ctrl, 0, sizeof(BCMI_DINO_GPIO_7_CTLr_t)); 6433 PHYMOD_MEMSET(&pad_ctrl_gpio_8_ctrl, 0, sizeof(BCMI_DINO_GPIO_8_CTLr_t)); 6434 PHYMOD_MEMSET(&pad_ctrl_gpio_9_ctrl, 0, sizeof(BCMI_DINO_GPIO_9_CTLr_t)); 6435 PHYMOD_MEMSET(&pad_ctrl_gpio_10_ctrl, 0, sizeof(BCMI_DINO_GPIO_10_CTLr_t)); 6436 PHYMOD_MEMSET(&pad_ctrl_gpio_11_ctrl, 0, sizeof(BCMI_DINO_GPIO_11_CTLr_t)); 6437 PHYMOD_MEMSET(&pad_ctrl_gpio_12_ctrl, 0, sizeof(BCMI_DINO_GPIO_12_CTLr_t)); 6438 PHYMOD_MEMSET(&pad_ctrl_gpio_13_ctrl, 0, sizeof(BCMI_DINO_GPIO_13_CTLr_t)); 6439 PHYMOD_MEMSET(&pad_ctrl_gpio_14_ctrl, 0, sizeof(BCMI_DINO_GPIO_14_CTLr_t)); 6440 PHYMOD_MEMSET(&pad_ctrl_gpio_15_ctrl, 0, sizeof(BCMI_DINO_GPIO_15_CTLr_t)); 6441 PHYMOD_MEMSET(&pad_ctrl_gpio_16_ctrl, 0, sizeof(BCMI_DINO_GPIO_16_CTLr_t)); 6442 PHYMOD_MEMSET(&pad_ctrl_gpio_17_ctrl, 0, sizeof(BCMI_DINO_GPIO_17_CTLr_t)); 6443 PHYMOD_MEMSET(&pad_ctrl_optxenb1_a, 0, sizeof(BCMI_DINO_OPTXENB1_A_CTLr_t)); 6444 PHYMOD_MEMSET(&pad_ctrl_optxenb1_b, 0, sizeof(BCMI_DINO_OPTXENB1_B_CTLr_t)); 6445 PHYMOD_MEMSET(&pad_ctrl_optxenb1_c, 0, sizeof(BCMI_DINO_OPTXENB1_C_CTLr_t)); 6446 PHYMOD_MEMSET(&pad_ctrl_mod_abs_3_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_3_CTLr_t)); 6447 PHYMOD_MEMSET(&pad_ctrl_mod_abs_4_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_4_CTLr_t)); 6448 PHYMOD_MEMSET(&pad_ctrl_mod_abs_5_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_5_CTLr_t)); 6449 PHYMOD_MEMSET(&pad_ctrl_mod_abs_6_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_6_CTLr_t)); 6450 PHYMOD_MEMSET(&pad_ctrl_mod_abs_7_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_7_CTLr_t)); 6451 PHYMOD_MEMSET(&pad_ctrl_mod_abs_8_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_8_CTLr_t)); 6452 PHYMOD_MEMSET(&pad_ctrl_mod_abs_9_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_9_CTLr_t)); 6453 PHYMOD_MEMSET(&pad_ctrl_mod_abs_10_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_10_CTLr_t)); 6454 PHYMOD_MEMSET(&pad_ctrl_mod_abs_11_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_11_CTLr_t)); 6455 PHYMOD_MEMSET(&pad_ctrl_oprxlos_4_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_4_CTLr_t)); 6456 PHYMOD_MEMSET(&pad_ctrl_oprxlos_5_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_5_CTLr_t)); 6457 PHYMOD_MEMSET(&pad_ctrl_oprxlos_6_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_6_CTLr_t)); 6458 PHYMOD_MEMSET(&pad_ctrl_oprxlos_7_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_7_CTLr_t)); 6459 PHYMOD_MEMSET(&pad_ctrl_oprxlos_8_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_8_CTLr_t)); 6460 PHYMOD_MEMSET(&pad_ctrl_oprxlos_9_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_9_CTLr_t)); 6461 PHYMOD_MEMSET(&pad_ctrl_oprxlos_10_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_10_CTLr_t)); 6462 PHYMOD_MEMSET(&pad_ctrl_oprxlos_11_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_11_CTLr_t)); 6463 6464 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 6465 if (chip_id == DINO_CHIP_ID_82793 && pin_number > 11) { 6466 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 6467 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 11)"))); 6468 } 6469 6470 if (chip_id == DINO_CHIP_ID_82332 && pin_number > 37) { 6471 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 6472 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 37)"))); 6473 } 6474 6475 switch (pin_number) { 6476 case 0: 6477 PHYMOD_IF_ERR_RETURN( 6478 BCMI_DINO_READ_GPIO_0_CTLr(pa, &pad_ctrl_gpio_0_ctrl)); 6479 break; 6480 case 1: 6481 PHYMOD_IF_ERR_RETURN( 6482 BCMI_DINO_READ_GPIO_1_CTLr(pa, &pad_ctrl_gpio_1_ctrl)); 6483 break; 6484 case 2: 6485 PHYMOD_IF_ERR_RETURN( 6486 BCMI_DINO_READ_GPIO_2_CTLr(pa, &pad_ctrl_gpio_2_ctrl)); 6487 break; 6488 case 3: 6489 PHYMOD_IF_ERR_RETURN( 6490 BCMI_DINO_READ_GPIO_3_CTLr(pa, &pad_ctrl_gpio_3_ctrl)); 6491 break; 6492 case 4: 6493 PHYMOD_IF_ERR_RETURN( 6494 BCMI_DINO_READ_GPIO_4_CTLr(pa, &pad_ctrl_gpio_4_ctrl)); 6495 break; 6496 case 5: 6497 PHYMOD_IF_ERR_RETURN( 6498 BCMI_DINO_READ_GPIO_5_CTLr(pa, &pad_ctrl_gpio_5_ctrl)); 6499 break; 6500 case 6: 6501 PHYMOD_IF_ERR_RETURN( 6502 BCMI_DINO_READ_GPIO_6_CTLr(pa, &pad_ctrl_gpio_6_ctrl)); 6503 break; 6504 case 7: 6505 PHYMOD_IF_ERR_RETURN( 6506 BCMI_DINO_READ_GPIO_7_CTLr(pa, &pad_ctrl_gpio_7_ctrl)); 6507 break; 6508 case 8: 6509 PHYMOD_IF_ERR_RETURN( 6510 BCMI_DINO_READ_GPIO_8_CTLr(pa, &pad_ctrl_gpio_8_ctrl)); 6511 break; 6512 case 9: 6513 PHYMOD_IF_ERR_RETURN( 6514 BCMI_DINO_READ_GPIO_9_CTLr(pa, &pad_ctrl_gpio_9_ctrl)); 6515 break; 6516 case 10: 6517 PHYMOD_IF_ERR_RETURN( 6518 BCMI_DINO_READ_GPIO_10_CTLr(pa, &pad_ctrl_gpio_10_ctrl)); 6519 break; 6520 case 11: 6521 PHYMOD_IF_ERR_RETURN( 6522 BCMI_DINO_READ_GPIO_11_CTLr(pa, &pad_ctrl_gpio_11_ctrl)); 6523 break; 6524 case 12: 6525 PHYMOD_IF_ERR_RETURN( 6526 BCMI_DINO_READ_GPIO_12_CTLr(pa, &pad_ctrl_gpio_12_ctrl)); 6527 break; 6528 case 13: 6529 PHYMOD_IF_ERR_RETURN( 6530 BCMI_DINO_READ_GPIO_13_CTLr(pa, &pad_ctrl_gpio_13_ctrl)); 6531 break; 6532 case 14: 6533 PHYMOD_IF_ERR_RETURN( 6534 BCMI_DINO_READ_GPIO_14_CTLr(pa, &pad_ctrl_gpio_14_ctrl)); 6535 break; 6536 case 15: 6537 PHYMOD_IF_ERR_RETURN( 6538 BCMI_DINO_READ_GPIO_15_CTLr(pa, &pad_ctrl_gpio_15_ctrl)); 6539 break; 6540 case 16: 6541 PHYMOD_IF_ERR_RETURN( 6542 BCMI_DINO_READ_GPIO_16_CTLr(pa, &pad_ctrl_gpio_16_ctrl)); 6543 break; 6544 case 17: 6545 PHYMOD_IF_ERR_RETURN( 6546 BCMI_DINO_READ_GPIO_17_CTLr(pa, &pad_ctrl_gpio_17_ctrl)); 6547 break; 6548 case 18: 6549 PHYMOD_IF_ERR_RETURN( 6550 BCMI_DINO_READ_OPTXENB1_A_CTLr(pa, &pad_ctrl_optxenb1_a)); 6551 break; 6552 case 19: 6553 PHYMOD_IF_ERR_RETURN( 6554 BCMI_DINO_READ_OPTXENB1_B_CTLr(pa, &pad_ctrl_optxenb1_b)); 6555 break; 6556 case 20: 6557 PHYMOD_IF_ERR_RETURN( 6558 BCMI_DINO_READ_OPTXENB1_C_CTLr(pa, &pad_ctrl_optxenb1_c)); 6559 break; 6560 case 21: 6561 PHYMOD_IF_ERR_RETURN( 6562 BCMI_DINO_READ_MOD_ABS_3_CTLr(pa, &pad_ctrl_mod_abs_3_ctrl)); 6563 break; 6564 case 22: 6565 PHYMOD_IF_ERR_RETURN( 6566 BCMI_DINO_READ_MOD_ABS_4_CTLr(pa, &pad_ctrl_mod_abs_4_ctrl)); 6567 break; 6568 case 23: 6569 PHYMOD_IF_ERR_RETURN( 6570 BCMI_DINO_READ_MOD_ABS_5_CTLr(pa, &pad_ctrl_mod_abs_5_ctrl)); 6571 break; 6572 case 24: 6573 PHYMOD_IF_ERR_RETURN( 6574 BCMI_DINO_READ_MOD_ABS_6_CTLr(pa, &pad_ctrl_mod_abs_6_ctrl)); 6575 break; 6576 case 25: 6577 PHYMOD_IF_ERR_RETURN( 6578 BCMI_DINO_READ_MOD_ABS_7_CTLr(pa, &pad_ctrl_mod_abs_7_ctrl)); 6579 break; 6580 case 26: 6581 PHYMOD_IF_ERR_RETURN( 6582 BCMI_DINO_READ_MOD_ABS_8_CTLr(pa, &pad_ctrl_mod_abs_8_ctrl)); 6583 break; 6584 case 27: 6585 PHYMOD_IF_ERR_RETURN( 6586 BCMI_DINO_READ_MOD_ABS_9_CTLr(pa, &pad_ctrl_mod_abs_9_ctrl)); 6587 break; 6588 case 28: 6589 PHYMOD_IF_ERR_RETURN( 6590 BCMI_DINO_READ_MOD_ABS_10_CTLr(pa, &pad_ctrl_mod_abs_10_ctrl)); 6591 break; 6592 case 29: 6593 PHYMOD_IF_ERR_RETURN( 6594 BCMI_DINO_READ_MOD_ABS_11_CTLr(pa, &pad_ctrl_mod_abs_11_ctrl)); 6595 break; 6596 case 30: 6597 PHYMOD_IF_ERR_RETURN( 6598 BCMI_DINO_READ_OPRXLOS_4_CTLr(pa, &pad_ctrl_oprxlos_4_ctrl)); 6599 break; 6600 case 31: 6601 PHYMOD_IF_ERR_RETURN( 6602 BCMI_DINO_READ_OPRXLOS_5_CTLr(pa, &pad_ctrl_oprxlos_5_ctrl)); 6603 break; 6604 case 32: 6605 PHYMOD_IF_ERR_RETURN( 6606 BCMI_DINO_READ_OPRXLOS_6_CTLr(pa, &pad_ctrl_oprxlos_6_ctrl)); 6607 break; 6608 case 33: 6609 PHYMOD_IF_ERR_RETURN( 6610 BCMI_DINO_READ_OPRXLOS_7_CTLr(pa, &pad_ctrl_oprxlos_7_ctrl)); 6611 break; 6612 case 34: 6613 PHYMOD_IF_ERR_RETURN( 6614 BCMI_DINO_READ_OPRXLOS_8_CTLr(pa, &pad_ctrl_oprxlos_8_ctrl)); 6615 break; 6616 case 35: 6617 PHYMOD_IF_ERR_RETURN( 6618 BCMI_DINO_READ_OPRXLOS_9_CTLr(pa, &pad_ctrl_oprxlos_9_ctrl)); 6619 break; 6620 case 36: 6621 PHYMOD_IF_ERR_RETURN( 6622 BCMI_DINO_READ_OPRXLOS_10_CTLr(pa, &pad_ctrl_oprxlos_10_ctrl)); 6623 break; 6624 case 37: 6625 PHYMOD_IF_ERR_RETURN( 6626 BCMI_DINO_READ_OPRXLOS_11_CTLr(pa, &pad_ctrl_oprxlos_11_ctrl)); 6627 break; 6628 default: 6629 return PHYMOD_E_PARAM; 6630 } 6631 6632 switch (gpio_mode) { 6633 case phymodGpioModeDisabled: 6634 return PHYMOD_E_NONE; 6635 case phymodGpioModeOutput: 6636 data = 0; 6637 break; 6638 case phymodGpioModeInput: 6639 data = 1; 6640 break; 6641 default: 6642 return PHYMOD_E_PARAM; 6643 } 6644 6645 switch (pin_number) { 6646 case 0: 6647 BCMI_DINO_GPIO_0_CTLr_GPIO_0_OEBf_SET(pad_ctrl_gpio_0_ctrl, data); 6648 PHYMOD_IF_ERR_RETURN( 6649 BCMI_DINO_WRITE_GPIO_0_CTLr(pa, pad_ctrl_gpio_0_ctrl)); 6650 break; 6651 case 1: 6652 BCMI_DINO_GPIO_1_CTLr_GPIO_1_OEBf_SET(pad_ctrl_gpio_1_ctrl, data); 6653 PHYMOD_IF_ERR_RETURN( 6654 BCMI_DINO_WRITE_GPIO_1_CTLr(pa,pad_ctrl_gpio_1_ctrl)); 6655 break; 6656 case 2: 6657 BCMI_DINO_GPIO_2_CTLr_GPIO_2_OEBf_SET(pad_ctrl_gpio_2_ctrl, data); 6658 PHYMOD_IF_ERR_RETURN( 6659 BCMI_DINO_WRITE_GPIO_2_CTLr(pa,pad_ctrl_gpio_2_ctrl)); 6660 break; 6661 case 3: 6662 BCMI_DINO_GPIO_3_CTLr_GPIO_3_OEBf_SET(pad_ctrl_gpio_3_ctrl, data); 6663 PHYMOD_IF_ERR_RETURN( 6664 BCMI_DINO_WRITE_GPIO_3_CTLr(pa,pad_ctrl_gpio_3_ctrl)); 6665 break; 6666 case 4: 6667 BCMI_DINO_GPIO_4_CTLr_GPIO_4_OEBf_SET(pad_ctrl_gpio_4_ctrl, data); 6668 PHYMOD_IF_ERR_RETURN( 6669 BCMI_DINO_WRITE_GPIO_4_CTLr(pa,pad_ctrl_gpio_4_ctrl)); 6670 break; 6671 case 5: 6672 BCMI_DINO_GPIO_5_CTLr_GPIO_5_OEBf_SET(pad_ctrl_gpio_5_ctrl, data); 6673 PHYMOD_IF_ERR_RETURN( 6674 BCMI_DINO_WRITE_GPIO_5_CTLr(pa,pad_ctrl_gpio_5_ctrl)); 6675 break; 6676 case 6: 6677 BCMI_DINO_GPIO_6_CTLr_GPIO_6_OEBf_SET(pad_ctrl_gpio_6_ctrl, data); 6678 PHYMOD_IF_ERR_RETURN( 6679 BCMI_DINO_WRITE_GPIO_6_CTLr(pa,pad_ctrl_gpio_6_ctrl)); 6680 break; 6681 case 7: 6682 BCMI_DINO_GPIO_7_CTLr_GPIO_7_OEBf_SET(pad_ctrl_gpio_7_ctrl, data); 6683 PHYMOD_IF_ERR_RETURN( 6684 BCMI_DINO_WRITE_GPIO_7_CTLr(pa,pad_ctrl_gpio_7_ctrl)); 6685 break; 6686 case 8: 6687 BCMI_DINO_GPIO_8_CTLr_GPIO_8_OEBf_SET(pad_ctrl_gpio_8_ctrl, data); 6688 PHYMOD_IF_ERR_RETURN( 6689 BCMI_DINO_WRITE_GPIO_8_CTLr(pa,pad_ctrl_gpio_8_ctrl)); 6690 break; 6691 case 9: 6692 BCMI_DINO_GPIO_9_CTLr_GPIO_9_OEBf_SET(pad_ctrl_gpio_9_ctrl, data); 6693 PHYMOD_IF_ERR_RETURN( 6694 BCMI_DINO_WRITE_GPIO_9_CTLr(pa,pad_ctrl_gpio_9_ctrl)); 6695 break; 6696 case 10: 6697 BCMI_DINO_GPIO_10_CTLr_GPIO_10_OEBf_SET(pad_ctrl_gpio_10_ctrl, data); 6698 PHYMOD_IF_ERR_RETURN( 6699 BCMI_DINO_WRITE_GPIO_10_CTLr(pa,pad_ctrl_gpio_10_ctrl)); 6700 break; 6701 case 11: 6702 BCMI_DINO_GPIO_11_CTLr_GPIO_11_OEBf_SET(pad_ctrl_gpio_11_ctrl, data); 6703 PHYMOD_IF_ERR_RETURN( 6704 BCMI_DINO_WRITE_GPIO_11_CTLr(pa,pad_ctrl_gpio_11_ctrl)); 6705 break; 6706 case 12: 6707 BCMI_DINO_GPIO_12_CTLr_GPIO_12_OEBf_SET(pad_ctrl_gpio_12_ctrl, data); 6708 PHYMOD_IF_ERR_RETURN( 6709 BCMI_DINO_WRITE_GPIO_12_CTLr(pa,pad_ctrl_gpio_12_ctrl)); 6710 break; 6711 case 13: 6712 BCMI_DINO_GPIO_13_CTLr_GPIO_13_OEBf_SET(pad_ctrl_gpio_13_ctrl, data); 6713 PHYMOD_IF_ERR_RETURN( 6714 BCMI_DINO_WRITE_GPIO_13_CTLr(pa,pad_ctrl_gpio_13_ctrl)); 6715 break; 6716 case 14: 6717 BCMI_DINO_GPIO_14_CTLr_GPIO_14_OEBf_SET(pad_ctrl_gpio_14_ctrl, data); 6718 PHYMOD_IF_ERR_RETURN( 6719 BCMI_DINO_WRITE_GPIO_14_CTLr(pa,pad_ctrl_gpio_14_ctrl)); 6720 break; 6721 case 15: 6722 BCMI_DINO_GPIO_15_CTLr_GPIO_15_OEBf_SET(pad_ctrl_gpio_15_ctrl, data); 6723 PHYMOD_IF_ERR_RETURN( 6724 BCMI_DINO_WRITE_GPIO_15_CTLr(pa,pad_ctrl_gpio_15_ctrl)); 6725 break; 6726 case 16: 6727 BCMI_DINO_GPIO_16_CTLr_GPIO_16_OEBf_SET(pad_ctrl_gpio_16_ctrl, data); 6728 PHYMOD_IF_ERR_RETURN( 6729 BCMI_DINO_WRITE_GPIO_16_CTLr(pa,pad_ctrl_gpio_16_ctrl)); 6730 break; 6731 case 17: 6732 BCMI_DINO_GPIO_17_CTLr_GPIO_17_OEBf_SET(pad_ctrl_gpio_17_ctrl, data); 6733 PHYMOD_IF_ERR_RETURN( 6734 BCMI_DINO_WRITE_GPIO_17_CTLr(pa,pad_ctrl_gpio_17_ctrl)); 6735 break; 6736 case 18: 6737 BCMI_DINO_OPTXENB1_A_CTLr_OPTXENB1_A_OEBf_SET(pad_ctrl_optxenb1_a, data); 6738 PHYMOD_IF_ERR_RETURN( 6739 BCMI_DINO_WRITE_OPTXENB1_A_CTLr(pa, pad_ctrl_optxenb1_a)); 6740 break; 6741 case 19: 6742 BCMI_DINO_OPTXENB1_B_CTLr_OPTXENB1_B_OEBf_SET(pad_ctrl_optxenb1_b, data); 6743 PHYMOD_IF_ERR_RETURN( 6744 BCMI_DINO_WRITE_OPTXENB1_B_CTLr(pa, pad_ctrl_optxenb1_b)); 6745 break; 6746 case 20: 6747 BCMI_DINO_OPTXENB1_C_CTLr_OPTXENB1_C_OEBf_SET(pad_ctrl_optxenb1_c, data); 6748 PHYMOD_IF_ERR_RETURN( 6749 BCMI_DINO_WRITE_OPTXENB1_C_CTLr(pa, pad_ctrl_optxenb1_c)); 6750 break; 6751 case 21: 6752 BCMI_DINO_MOD_ABS_3_CTLr_MOD_ABS_3_OEBf_SET(pad_ctrl_mod_abs_3_ctrl, data); 6753 PHYMOD_IF_ERR_RETURN( 6754 BCMI_DINO_WRITE_MOD_ABS_3_CTLr(pa, pad_ctrl_mod_abs_3_ctrl)); 6755 break; 6756 case 22: 6757 BCMI_DINO_MOD_ABS_4_CTLr_MOD_ABS_4_OEBf_SET(pad_ctrl_mod_abs_4_ctrl, data); 6758 PHYMOD_IF_ERR_RETURN( 6759 BCMI_DINO_WRITE_MOD_ABS_4_CTLr(pa, pad_ctrl_mod_abs_4_ctrl)); 6760 break; 6761 case 23: 6762 BCMI_DINO_MOD_ABS_5_CTLr_MOD_ABS_5_OEBf_SET(pad_ctrl_mod_abs_5_ctrl, data); 6763 PHYMOD_IF_ERR_RETURN( 6764 BCMI_DINO_WRITE_MOD_ABS_5_CTLr(pa, pad_ctrl_mod_abs_5_ctrl)); 6765 break; 6766 case 24: 6767 BCMI_DINO_MOD_ABS_6_CTLr_MOD_ABS_6_OEBf_SET(pad_ctrl_mod_abs_6_ctrl, data); 6768 PHYMOD_IF_ERR_RETURN( 6769 BCMI_DINO_WRITE_MOD_ABS_6_CTLr(pa, pad_ctrl_mod_abs_6_ctrl)); 6770 break; 6771 case 25: 6772 BCMI_DINO_MOD_ABS_7_CTLr_MOD_ABS_7_OEBf_SET(pad_ctrl_mod_abs_7_ctrl, data); 6773 PHYMOD_IF_ERR_RETURN( 6774 BCMI_DINO_WRITE_MOD_ABS_7_CTLr(pa, pad_ctrl_mod_abs_7_ctrl)); 6775 break; 6776 case 26: 6777 BCMI_DINO_MOD_ABS_8_CTLr_MOD_ABS_8_OEBf_SET(pad_ctrl_mod_abs_8_ctrl, data); 6778 PHYMOD_IF_ERR_RETURN( 6779 BCMI_DINO_WRITE_MOD_ABS_8_CTLr(pa, pad_ctrl_mod_abs_8_ctrl)); 6780 break; 6781 case 27: 6782 BCMI_DINO_MOD_ABS_9_CTLr_MOD_ABS_9_OEBf_SET(pad_ctrl_mod_abs_9_ctrl, data); 6783 PHYMOD_IF_ERR_RETURN( 6784 BCMI_DINO_WRITE_MOD_ABS_9_CTLr(pa, pad_ctrl_mod_abs_9_ctrl)); 6785 break; 6786 case 28: 6787 BCMI_DINO_MOD_ABS_10_CTLr_MOD_ABS_10_OEBf_SET(pad_ctrl_mod_abs_10_ctrl, data); 6788 PHYMOD_IF_ERR_RETURN( 6789 BCMI_DINO_WRITE_MOD_ABS_10_CTLr(pa, pad_ctrl_mod_abs_10_ctrl)); 6790 break; 6791 case 29: 6792 BCMI_DINO_MOD_ABS_11_CTLr_MOD_ABS_11_OEBf_SET(pad_ctrl_mod_abs_11_ctrl, data); 6793 PHYMOD_IF_ERR_RETURN( 6794 BCMI_DINO_WRITE_MOD_ABS_11_CTLr(pa, pad_ctrl_mod_abs_11_ctrl)); 6795 break; 6796 case 30: 6797 BCMI_DINO_OPRXLOS_4_CTLr_OPRXLOS_4_OEBf_SET(pad_ctrl_oprxlos_4_ctrl, data); 6798 PHYMOD_IF_ERR_RETURN( 6799 BCMI_DINO_WRITE_OPRXLOS_4_CTLr(pa, pad_ctrl_oprxlos_4_ctrl)); 6800 break; 6801 case 31: 6802 BCMI_DINO_OPRXLOS_5_CTLr_OPRXLOS_5_OEBf_SET(pad_ctrl_oprxlos_5_ctrl, data); 6803 PHYMOD_IF_ERR_RETURN( 6804 BCMI_DINO_WRITE_OPRXLOS_5_CTLr(pa, pad_ctrl_oprxlos_5_ctrl)); 6805 break; 6806 case 32: 6807 BCMI_DINO_OPRXLOS_6_CTLr_OPRXLOS_6_OEBf_SET(pad_ctrl_oprxlos_6_ctrl, data); 6808 PHYMOD_IF_ERR_RETURN( 6809 BCMI_DINO_WRITE_OPRXLOS_6_CTLr(pa, pad_ctrl_oprxlos_6_ctrl)); 6810 break; 6811 case 33: 6812 BCMI_DINO_OPRXLOS_7_CTLr_OPRXLOS_7_OEBf_SET(pad_ctrl_oprxlos_7_ctrl, data); 6813 PHYMOD_IF_ERR_RETURN( 6814 BCMI_DINO_WRITE_OPRXLOS_7_CTLr(pa, pad_ctrl_oprxlos_7_ctrl)); 6815 break; 6816 case 34: 6817 BCMI_DINO_OPRXLOS_8_CTLr_OPRXLOS_8_OEBf_SET(pad_ctrl_oprxlos_8_ctrl, data); 6818 PHYMOD_IF_ERR_RETURN( 6819 BCMI_DINO_WRITE_OPRXLOS_8_CTLr(pa, pad_ctrl_oprxlos_8_ctrl)); 6820 break; 6821 case 35: 6822 BCMI_DINO_OPRXLOS_9_CTLr_OPRXLOS_9_OEBf_SET(pad_ctrl_oprxlos_9_ctrl, data); 6823 PHYMOD_IF_ERR_RETURN( 6824 BCMI_DINO_WRITE_OPRXLOS_9_CTLr(pa, pad_ctrl_oprxlos_9_ctrl)); 6825 break; 6826 case 36: 6827 BCMI_DINO_OPRXLOS_10_CTLr_OPRXLOS_10_OEBf_SET(pad_ctrl_oprxlos_10_ctrl, data); 6828 PHYMOD_IF_ERR_RETURN( 6829 BCMI_DINO_WRITE_OPRXLOS_10_CTLr(pa, pad_ctrl_oprxlos_10_ctrl)); 6830 break; 6831 case 37: 6832 BCMI_DINO_OPRXLOS_11_CTLr_OPRXLOS_11_OEBf_SET(pad_ctrl_oprxlos_11_ctrl, data); 6833 PHYMOD_IF_ERR_RETURN( 6834 BCMI_DINO_WRITE_OPRXLOS_11_CTLr(pa, pad_ctrl_oprxlos_11_ctrl)); 6835 break; 6836 } 6837 6838 return PHYMOD_E_NONE; 6839 } 6840 6841 int _dino_phy_gpio_config_get(const phymod_access_t* pa, int pin_number, phymod_gpio_mode_t* gpio_mode) 6842 { 6843 uint16_t data = 0; 6844 uint32_t chip_id = 0; 6845 uint32_t rev = 0; 6846 BCMI_DINO_GPIO_0_CTLr_t pad_ctrl_gpio_0_ctrl; 6847 BCMI_DINO_GPIO_1_CTLr_t pad_ctrl_gpio_1_ctrl; 6848 BCMI_DINO_GPIO_2_CTLr_t pad_ctrl_gpio_2_ctrl; 6849 BCMI_DINO_GPIO_3_CTLr_t pad_ctrl_gpio_3_ctrl; 6850 BCMI_DINO_GPIO_4_CTLr_t pad_ctrl_gpio_4_ctrl; 6851 BCMI_DINO_GPIO_5_CTLr_t pad_ctrl_gpio_5_ctrl; 6852 BCMI_DINO_GPIO_6_CTLr_t pad_ctrl_gpio_6_ctrl; 6853 BCMI_DINO_GPIO_7_CTLr_t pad_ctrl_gpio_7_ctrl; 6854 BCMI_DINO_GPIO_8_CTLr_t pad_ctrl_gpio_8_ctrl; 6855 BCMI_DINO_GPIO_9_CTLr_t pad_ctrl_gpio_9_ctrl; 6856 BCMI_DINO_GPIO_10_CTLr_t pad_ctrl_gpio_10_ctrl; 6857 BCMI_DINO_GPIO_11_CTLr_t pad_ctrl_gpio_11_ctrl; 6858 BCMI_DINO_GPIO_12_CTLr_t pad_ctrl_gpio_12_ctrl; 6859 BCMI_DINO_GPIO_13_CTLr_t pad_ctrl_gpio_13_ctrl; 6860 BCMI_DINO_GPIO_14_CTLr_t pad_ctrl_gpio_14_ctrl; 6861 BCMI_DINO_GPIO_15_CTLr_t pad_ctrl_gpio_15_ctrl; 6862 BCMI_DINO_GPIO_16_CTLr_t pad_ctrl_gpio_16_ctrl; 6863 BCMI_DINO_GPIO_17_CTLr_t pad_ctrl_gpio_17_ctrl; 6864 BCMI_DINO_OPTXENB1_A_CTLr_t pad_ctrl_optxenb1_a; 6865 BCMI_DINO_OPTXENB1_B_CTLr_t pad_ctrl_optxenb1_b; 6866 BCMI_DINO_OPTXENB1_C_CTLr_t pad_ctrl_optxenb1_c; 6867 BCMI_DINO_MOD_ABS_3_CTLr_t pad_ctrl_mod_abs_3_ctrl; 6868 BCMI_DINO_MOD_ABS_4_CTLr_t pad_ctrl_mod_abs_4_ctrl; 6869 BCMI_DINO_MOD_ABS_5_CTLr_t pad_ctrl_mod_abs_5_ctrl; 6870 BCMI_DINO_MOD_ABS_6_CTLr_t pad_ctrl_mod_abs_6_ctrl; 6871 BCMI_DINO_MOD_ABS_7_CTLr_t pad_ctrl_mod_abs_7_ctrl; 6872 BCMI_DINO_MOD_ABS_8_CTLr_t pad_ctrl_mod_abs_8_ctrl; 6873 BCMI_DINO_MOD_ABS_9_CTLr_t pad_ctrl_mod_abs_9_ctrl; 6874 BCMI_DINO_MOD_ABS_10_CTLr_t pad_ctrl_mod_abs_10_ctrl; 6875 BCMI_DINO_MOD_ABS_11_CTLr_t pad_ctrl_mod_abs_11_ctrl; 6876 BCMI_DINO_OPRXLOS_4_CTLr_t pad_ctrl_oprxlos_4_ctrl; 6877 BCMI_DINO_OPRXLOS_5_CTLr_t pad_ctrl_oprxlos_5_ctrl; 6878 BCMI_DINO_OPRXLOS_6_CTLr_t pad_ctrl_oprxlos_6_ctrl; 6879 BCMI_DINO_OPRXLOS_7_CTLr_t pad_ctrl_oprxlos_7_ctrl; 6880 BCMI_DINO_OPRXLOS_8_CTLr_t pad_ctrl_oprxlos_8_ctrl; 6881 BCMI_DINO_OPRXLOS_9_CTLr_t pad_ctrl_oprxlos_9_ctrl; 6882 BCMI_DINO_OPRXLOS_10_CTLr_t pad_ctrl_oprxlos_10_ctrl; 6883 BCMI_DINO_OPRXLOS_11_CTLr_t pad_ctrl_oprxlos_11_ctrl; 6884 6885 PHYMOD_MEMSET(&pad_ctrl_gpio_0_ctrl, 0, sizeof(BCMI_DINO_GPIO_0_CTLr_t)); 6886 PHYMOD_MEMSET(&pad_ctrl_gpio_1_ctrl, 0, sizeof(BCMI_DINO_GPIO_1_CTLr_t)); 6887 PHYMOD_MEMSET(&pad_ctrl_gpio_2_ctrl, 0, sizeof(BCMI_DINO_GPIO_2_CTLr_t)); 6888 PHYMOD_MEMSET(&pad_ctrl_gpio_3_ctrl, 0, sizeof(BCMI_DINO_GPIO_3_CTLr_t)); 6889 PHYMOD_MEMSET(&pad_ctrl_gpio_4_ctrl, 0, sizeof(BCMI_DINO_GPIO_4_CTLr_t)); 6890 PHYMOD_MEMSET(&pad_ctrl_gpio_5_ctrl, 0, sizeof(BCMI_DINO_GPIO_5_CTLr_t)); 6891 PHYMOD_MEMSET(&pad_ctrl_gpio_6_ctrl, 0, sizeof(BCMI_DINO_GPIO_6_CTLr_t)); 6892 PHYMOD_MEMSET(&pad_ctrl_gpio_7_ctrl, 0, sizeof(BCMI_DINO_GPIO_7_CTLr_t)); 6893 PHYMOD_MEMSET(&pad_ctrl_gpio_8_ctrl, 0, sizeof(BCMI_DINO_GPIO_8_CTLr_t)); 6894 PHYMOD_MEMSET(&pad_ctrl_gpio_9_ctrl, 0, sizeof(BCMI_DINO_GPIO_9_CTLr_t)); 6895 PHYMOD_MEMSET(&pad_ctrl_gpio_10_ctrl, 0, sizeof(BCMI_DINO_GPIO_10_CTLr_t)); 6896 PHYMOD_MEMSET(&pad_ctrl_gpio_11_ctrl, 0, sizeof(BCMI_DINO_GPIO_11_CTLr_t)); 6897 PHYMOD_MEMSET(&pad_ctrl_gpio_12_ctrl, 0, sizeof(BCMI_DINO_GPIO_12_CTLr_t)); 6898 PHYMOD_MEMSET(&pad_ctrl_gpio_13_ctrl, 0, sizeof(BCMI_DINO_GPIO_13_CTLr_t)); 6899 PHYMOD_MEMSET(&pad_ctrl_gpio_14_ctrl, 0, sizeof(BCMI_DINO_GPIO_14_CTLr_t)); 6900 PHYMOD_MEMSET(&pad_ctrl_gpio_15_ctrl, 0, sizeof(BCMI_DINO_GPIO_15_CTLr_t)); 6901 PHYMOD_MEMSET(&pad_ctrl_gpio_16_ctrl, 0, sizeof(BCMI_DINO_GPIO_16_CTLr_t)); 6902 PHYMOD_MEMSET(&pad_ctrl_gpio_17_ctrl, 0, sizeof(BCMI_DINO_GPIO_17_CTLr_t)); 6903 PHYMOD_MEMSET(&pad_ctrl_optxenb1_a, 0, sizeof(BCMI_DINO_OPTXENB1_A_CTLr_t)); 6904 PHYMOD_MEMSET(&pad_ctrl_optxenb1_b, 0, sizeof(BCMI_DINO_OPTXENB1_B_CTLr_t)); 6905 PHYMOD_MEMSET(&pad_ctrl_optxenb1_c, 0, sizeof(BCMI_DINO_OPTXENB1_C_CTLr_t)); 6906 PHYMOD_MEMSET(&pad_ctrl_mod_abs_3_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_3_CTLr_t)); 6907 PHYMOD_MEMSET(&pad_ctrl_mod_abs_4_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_4_CTLr_t)); 6908 PHYMOD_MEMSET(&pad_ctrl_mod_abs_5_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_5_CTLr_t)); 6909 PHYMOD_MEMSET(&pad_ctrl_mod_abs_6_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_6_CTLr_t)); 6910 PHYMOD_MEMSET(&pad_ctrl_mod_abs_7_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_7_CTLr_t)); 6911 PHYMOD_MEMSET(&pad_ctrl_mod_abs_8_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_8_CTLr_t)); 6912 PHYMOD_MEMSET(&pad_ctrl_mod_abs_9_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_9_CTLr_t)); 6913 PHYMOD_MEMSET(&pad_ctrl_mod_abs_10_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_10_CTLr_t)); 6914 PHYMOD_MEMSET(&pad_ctrl_mod_abs_11_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_11_CTLr_t)); 6915 PHYMOD_MEMSET(&pad_ctrl_oprxlos_4_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_4_CTLr_t)); 6916 PHYMOD_MEMSET(&pad_ctrl_oprxlos_5_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_5_CTLr_t)); 6917 PHYMOD_MEMSET(&pad_ctrl_oprxlos_6_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_6_CTLr_t)); 6918 PHYMOD_MEMSET(&pad_ctrl_oprxlos_7_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_7_CTLr_t)); 6919 PHYMOD_MEMSET(&pad_ctrl_oprxlos_8_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_8_CTLr_t)); 6920 PHYMOD_MEMSET(&pad_ctrl_oprxlos_9_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_9_CTLr_t)); 6921 PHYMOD_MEMSET(&pad_ctrl_oprxlos_10_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_10_CTLr_t)); 6922 PHYMOD_MEMSET(&pad_ctrl_oprxlos_11_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_11_CTLr_t)); 6923 6924 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 6925 if (chip_id == DINO_CHIP_ID_82793 && pin_number > 11) { 6926 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 6927 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 11)"))); 6928 } 6929 6930 if (chip_id == DINO_CHIP_ID_82332 && pin_number > 37) { 6931 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 6932 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 37)"))); 6933 } 6934 6935 switch (pin_number) { 6936 case 0: 6937 PHYMOD_IF_ERR_RETURN( 6938 BCMI_DINO_READ_GPIO_0_CTLr(pa, &pad_ctrl_gpio_0_ctrl)); 6939 data = BCMI_DINO_GPIO_0_CTLr_GPIO_0_OEBf_GET(pad_ctrl_gpio_0_ctrl); 6940 break; 6941 case 1: 6942 PHYMOD_IF_ERR_RETURN( 6943 BCMI_DINO_READ_GPIO_1_CTLr(pa, &pad_ctrl_gpio_1_ctrl)); 6944 data = BCMI_DINO_GPIO_1_CTLr_GPIO_1_OEBf_GET(pad_ctrl_gpio_1_ctrl); 6945 break; 6946 case 2: 6947 PHYMOD_IF_ERR_RETURN( 6948 BCMI_DINO_READ_GPIO_2_CTLr(pa, &pad_ctrl_gpio_2_ctrl)); 6949 data = BCMI_DINO_GPIO_2_CTLr_GPIO_2_OEBf_GET(pad_ctrl_gpio_2_ctrl); 6950 break; 6951 case 3: 6952 PHYMOD_IF_ERR_RETURN( 6953 BCMI_DINO_READ_GPIO_3_CTLr(pa, &pad_ctrl_gpio_3_ctrl)); 6954 data = BCMI_DINO_GPIO_3_CTLr_GPIO_3_OEBf_GET(pad_ctrl_gpio_3_ctrl); 6955 break; 6956 case 4: 6957 PHYMOD_IF_ERR_RETURN( 6958 BCMI_DINO_READ_GPIO_4_CTLr(pa, &pad_ctrl_gpio_4_ctrl)); 6959 data = BCMI_DINO_GPIO_4_CTLr_GPIO_4_OEBf_GET(pad_ctrl_gpio_4_ctrl); 6960 break; 6961 case 5: 6962 PHYMOD_IF_ERR_RETURN( 6963 BCMI_DINO_READ_GPIO_5_CTLr(pa, &pad_ctrl_gpio_5_ctrl)); 6964 data = BCMI_DINO_GPIO_5_CTLr_GPIO_5_OEBf_GET(pad_ctrl_gpio_5_ctrl); 6965 break; 6966 case 6: 6967 PHYMOD_IF_ERR_RETURN( 6968 BCMI_DINO_READ_GPIO_6_CTLr(pa, &pad_ctrl_gpio_6_ctrl)); 6969 data = BCMI_DINO_GPIO_6_CTLr_GPIO_6_OEBf_GET(pad_ctrl_gpio_6_ctrl); 6970 break; 6971 case 7: 6972 PHYMOD_IF_ERR_RETURN( 6973 BCMI_DINO_READ_GPIO_7_CTLr(pa, &pad_ctrl_gpio_7_ctrl)); 6974 data = BCMI_DINO_GPIO_7_CTLr_GPIO_7_OEBf_GET(pad_ctrl_gpio_7_ctrl); 6975 break; 6976 case 8: 6977 PHYMOD_IF_ERR_RETURN( 6978 BCMI_DINO_READ_GPIO_8_CTLr(pa, &pad_ctrl_gpio_8_ctrl)); 6979 data = BCMI_DINO_GPIO_8_CTLr_GPIO_8_OEBf_GET(pad_ctrl_gpio_8_ctrl); 6980 break; 6981 case 9: 6982 PHYMOD_IF_ERR_RETURN( 6983 BCMI_DINO_READ_GPIO_9_CTLr(pa, &pad_ctrl_gpio_9_ctrl)); 6984 data = BCMI_DINO_GPIO_9_CTLr_GPIO_9_OEBf_GET(pad_ctrl_gpio_9_ctrl); 6985 break; 6986 case 10: 6987 PHYMOD_IF_ERR_RETURN( 6988 BCMI_DINO_READ_GPIO_10_CTLr(pa, &pad_ctrl_gpio_10_ctrl)); 6989 data = BCMI_DINO_GPIO_10_CTLr_GPIO_10_OEBf_GET(pad_ctrl_gpio_10_ctrl); 6990 break; 6991 case 11: 6992 PHYMOD_IF_ERR_RETURN( 6993 BCMI_DINO_READ_GPIO_11_CTLr(pa, &pad_ctrl_gpio_11_ctrl)); 6994 data = BCMI_DINO_GPIO_11_CTLr_GPIO_11_OEBf_GET(pad_ctrl_gpio_11_ctrl); 6995 break; 6996 case 12: 6997 PHYMOD_IF_ERR_RETURN( 6998 BCMI_DINO_READ_GPIO_12_CTLr(pa, &pad_ctrl_gpio_12_ctrl)); 6999 data = BCMI_DINO_GPIO_12_CTLr_GPIO_12_OEBf_GET(pad_ctrl_gpio_12_ctrl); 7000 break; 7001 case 13: 7002 PHYMOD_IF_ERR_RETURN( 7003 BCMI_DINO_READ_GPIO_13_CTLr(pa, &pad_ctrl_gpio_13_ctrl)); 7004 data = BCMI_DINO_GPIO_13_CTLr_GPIO_13_OEBf_GET(pad_ctrl_gpio_13_ctrl); 7005 break; 7006 case 14: 7007 PHYMOD_IF_ERR_RETURN( 7008 BCMI_DINO_READ_GPIO_14_CTLr(pa, &pad_ctrl_gpio_14_ctrl)); 7009 data = BCMI_DINO_GPIO_14_CTLr_GPIO_14_OEBf_GET(pad_ctrl_gpio_14_ctrl); 7010 break; 7011 case 15: 7012 PHYMOD_IF_ERR_RETURN( 7013 BCMI_DINO_READ_GPIO_15_CTLr(pa, &pad_ctrl_gpio_15_ctrl)); 7014 data = BCMI_DINO_GPIO_15_CTLr_GPIO_15_OEBf_GET(pad_ctrl_gpio_15_ctrl); 7015 break; 7016 case 16: 7017 PHYMOD_IF_ERR_RETURN( 7018 BCMI_DINO_READ_GPIO_16_CTLr(pa, &pad_ctrl_gpio_16_ctrl)); 7019 data = BCMI_DINO_GPIO_16_CTLr_GPIO_16_OEBf_GET(pad_ctrl_gpio_16_ctrl); 7020 break; 7021 case 17: 7022 PHYMOD_IF_ERR_RETURN( 7023 BCMI_DINO_READ_GPIO_17_CTLr(pa, &pad_ctrl_gpio_17_ctrl)); 7024 data = BCMI_DINO_GPIO_17_CTLr_GPIO_17_OEBf_GET(pad_ctrl_gpio_17_ctrl); 7025 break; 7026 case 18: 7027 PHYMOD_IF_ERR_RETURN( 7028 BCMI_DINO_READ_OPTXENB1_A_CTLr(pa, &pad_ctrl_optxenb1_a)); 7029 data = BCMI_DINO_OPTXENB1_A_CTLr_OPTXENB1_A_OEBf_GET(pad_ctrl_optxenb1_a); 7030 break; 7031 case 19: 7032 PHYMOD_IF_ERR_RETURN( 7033 BCMI_DINO_READ_OPTXENB1_B_CTLr(pa, &pad_ctrl_optxenb1_b)); 7034 data = BCMI_DINO_OPTXENB1_B_CTLr_OPTXENB1_B_OEBf_GET(pad_ctrl_optxenb1_b); 7035 break; 7036 case 20: 7037 PHYMOD_IF_ERR_RETURN( 7038 BCMI_DINO_READ_OPTXENB1_C_CTLr(pa, &pad_ctrl_optxenb1_c)); 7039 data = BCMI_DINO_OPTXENB1_C_CTLr_OPTXENB1_C_OEBf_GET(pad_ctrl_optxenb1_c); 7040 break; 7041 case 21: 7042 PHYMOD_IF_ERR_RETURN( 7043 BCMI_DINO_READ_MOD_ABS_3_CTLr(pa, &pad_ctrl_mod_abs_3_ctrl)); 7044 data = BCMI_DINO_MOD_ABS_3_CTLr_MOD_ABS_3_OEBf_GET(pad_ctrl_mod_abs_3_ctrl); 7045 break; 7046 case 22: 7047 PHYMOD_IF_ERR_RETURN( 7048 BCMI_DINO_READ_MOD_ABS_4_CTLr(pa, &pad_ctrl_mod_abs_4_ctrl)); 7049 data = BCMI_DINO_MOD_ABS_4_CTLr_MOD_ABS_4_OEBf_GET(pad_ctrl_mod_abs_4_ctrl); 7050 break; 7051 case 23: 7052 PHYMOD_IF_ERR_RETURN( 7053 BCMI_DINO_READ_MOD_ABS_5_CTLr(pa, &pad_ctrl_mod_abs_5_ctrl)); 7054 data = BCMI_DINO_MOD_ABS_5_CTLr_MOD_ABS_5_OEBf_GET(pad_ctrl_mod_abs_5_ctrl); 7055 break; 7056 case 24: 7057 PHYMOD_IF_ERR_RETURN( 7058 BCMI_DINO_READ_MOD_ABS_6_CTLr(pa, &pad_ctrl_mod_abs_6_ctrl)); 7059 data = BCMI_DINO_MOD_ABS_6_CTLr_MOD_ABS_6_OEBf_GET(pad_ctrl_mod_abs_6_ctrl); 7060 break; 7061 case 25: 7062 PHYMOD_IF_ERR_RETURN( 7063 BCMI_DINO_READ_MOD_ABS_7_CTLr(pa, &pad_ctrl_mod_abs_7_ctrl)); 7064 data = BCMI_DINO_MOD_ABS_7_CTLr_MOD_ABS_7_OEBf_GET(pad_ctrl_mod_abs_7_ctrl); 7065 break; 7066 case 26: 7067 PHYMOD_IF_ERR_RETURN( 7068 BCMI_DINO_READ_MOD_ABS_8_CTLr(pa, &pad_ctrl_mod_abs_8_ctrl)); 7069 data = BCMI_DINO_MOD_ABS_8_CTLr_MOD_ABS_8_OEBf_GET(pad_ctrl_mod_abs_8_ctrl); 7070 break; 7071 case 27: 7072 PHYMOD_IF_ERR_RETURN( 7073 BCMI_DINO_READ_MOD_ABS_9_CTLr(pa, &pad_ctrl_mod_abs_9_ctrl)); 7074 data = BCMI_DINO_MOD_ABS_9_CTLr_MOD_ABS_9_OEBf_GET(pad_ctrl_mod_abs_9_ctrl); 7075 break; 7076 case 28: 7077 PHYMOD_IF_ERR_RETURN( 7078 BCMI_DINO_READ_MOD_ABS_10_CTLr(pa, &pad_ctrl_mod_abs_10_ctrl)); 7079 data = BCMI_DINO_MOD_ABS_10_CTLr_MOD_ABS_10_OEBf_GET(pad_ctrl_mod_abs_10_ctrl); 7080 break; 7081 case 29: 7082 PHYMOD_IF_ERR_RETURN( 7083 BCMI_DINO_READ_MOD_ABS_11_CTLr(pa, &pad_ctrl_mod_abs_11_ctrl)); 7084 data = BCMI_DINO_MOD_ABS_11_CTLr_MOD_ABS_11_OEBf_GET(pad_ctrl_mod_abs_11_ctrl); 7085 break; 7086 case 30: 7087 PHYMOD_IF_ERR_RETURN( 7088 BCMI_DINO_READ_OPRXLOS_4_CTLr(pa, &pad_ctrl_oprxlos_4_ctrl)); 7089 data = BCMI_DINO_OPRXLOS_4_CTLr_OPRXLOS_4_OEBf_GET(pad_ctrl_oprxlos_4_ctrl); 7090 break; 7091 case 31: 7092 PHYMOD_IF_ERR_RETURN( 7093 BCMI_DINO_READ_OPRXLOS_5_CTLr(pa, &pad_ctrl_oprxlos_5_ctrl)); 7094 data = BCMI_DINO_OPRXLOS_5_CTLr_OPRXLOS_5_OEBf_GET(pad_ctrl_oprxlos_5_ctrl); 7095 break; 7096 case 32: 7097 PHYMOD_IF_ERR_RETURN( 7098 BCMI_DINO_READ_OPRXLOS_6_CTLr(pa, &pad_ctrl_oprxlos_6_ctrl)); 7099 data = BCMI_DINO_OPRXLOS_6_CTLr_OPRXLOS_6_OEBf_GET(pad_ctrl_oprxlos_6_ctrl); 7100 break; 7101 case 33: 7102 PHYMOD_IF_ERR_RETURN( 7103 BCMI_DINO_READ_OPRXLOS_7_CTLr(pa, &pad_ctrl_oprxlos_7_ctrl)); 7104 data = BCMI_DINO_OPRXLOS_7_CTLr_OPRXLOS_7_OEBf_GET(pad_ctrl_oprxlos_7_ctrl); 7105 break; 7106 case 34: 7107 PHYMOD_IF_ERR_RETURN( 7108 BCMI_DINO_READ_OPRXLOS_8_CTLr(pa, &pad_ctrl_oprxlos_8_ctrl)); 7109 data = BCMI_DINO_OPRXLOS_8_CTLr_OPRXLOS_8_OEBf_GET(pad_ctrl_oprxlos_8_ctrl); 7110 break; 7111 case 35: 7112 PHYMOD_IF_ERR_RETURN( 7113 BCMI_DINO_READ_OPRXLOS_9_CTLr(pa, &pad_ctrl_oprxlos_9_ctrl)); 7114 data = BCMI_DINO_OPRXLOS_9_CTLr_OPRXLOS_9_OEBf_GET(pad_ctrl_oprxlos_9_ctrl); 7115 break; 7116 case 36: 7117 PHYMOD_IF_ERR_RETURN( 7118 BCMI_DINO_READ_OPRXLOS_10_CTLr(pa, &pad_ctrl_oprxlos_10_ctrl)); 7119 data = BCMI_DINO_OPRXLOS_10_CTLr_OPRXLOS_10_OEBf_GET(pad_ctrl_oprxlos_10_ctrl); 7120 break; 7121 case 37: 7122 PHYMOD_IF_ERR_RETURN( 7123 BCMI_DINO_READ_OPRXLOS_11_CTLr(pa, &pad_ctrl_oprxlos_11_ctrl)); 7124 data = BCMI_DINO_OPRXLOS_11_CTLr_OPRXLOS_11_OEBf_GET(pad_ctrl_oprxlos_11_ctrl); 7125 break; 7126 default: 7127 return PHYMOD_E_PARAM; 7128 } 7129 7130 switch(data) { 7131 case 0: 7132 *gpio_mode = phymodGpioModeOutput; 7133 break; 7134 case 1: 7135 *gpio_mode = phymodGpioModeInput; 7136 break; 7137 /* coverity[dead_error_begin] */ 7138 default: 7139 break; 7140 } 7141 7142 return PHYMOD_E_NONE; 7143 } 7144 7145 int _dino_phy_gpio_pin_value_set(const phymod_access_t* pa, int pin_number, int value) 7146 { 7147 uint32_t chip_id = 0; 7148 uint32_t rev = 0; 7149 BCMI_DINO_GPIO_0_CTLr_t pad_ctrl_gpio_0_ctrl; 7150 BCMI_DINO_GPIO_1_CTLr_t pad_ctrl_gpio_1_ctrl; 7151 BCMI_DINO_GPIO_2_CTLr_t pad_ctrl_gpio_2_ctrl; 7152 BCMI_DINO_GPIO_3_CTLr_t pad_ctrl_gpio_3_ctrl; 7153 BCMI_DINO_GPIO_4_CTLr_t pad_ctrl_gpio_4_ctrl; 7154 BCMI_DINO_GPIO_5_CTLr_t pad_ctrl_gpio_5_ctrl; 7155 BCMI_DINO_GPIO_6_CTLr_t pad_ctrl_gpio_6_ctrl; 7156 BCMI_DINO_GPIO_7_CTLr_t pad_ctrl_gpio_7_ctrl; 7157 BCMI_DINO_GPIO_8_CTLr_t pad_ctrl_gpio_8_ctrl; 7158 BCMI_DINO_GPIO_9_CTLr_t pad_ctrl_gpio_9_ctrl; 7159 BCMI_DINO_GPIO_10_CTLr_t pad_ctrl_gpio_10_ctrl; 7160 BCMI_DINO_GPIO_11_CTLr_t pad_ctrl_gpio_11_ctrl; 7161 BCMI_DINO_GPIO_12_CTLr_t pad_ctrl_gpio_12_ctrl; 7162 BCMI_DINO_GPIO_13_CTLr_t pad_ctrl_gpio_13_ctrl; 7163 BCMI_DINO_GPIO_14_CTLr_t pad_ctrl_gpio_14_ctrl; 7164 BCMI_DINO_GPIO_15_CTLr_t pad_ctrl_gpio_15_ctrl; 7165 BCMI_DINO_GPIO_16_CTLr_t pad_ctrl_gpio_16_ctrl; 7166 BCMI_DINO_GPIO_17_CTLr_t pad_ctrl_gpio_17_ctrl; 7167 BCMI_DINO_OPTXENB1_A_CTLr_t pad_ctrl_optxenb1_a; 7168 BCMI_DINO_OPTXENB1_B_CTLr_t pad_ctrl_optxenb1_b; 7169 BCMI_DINO_OPTXENB1_C_CTLr_t pad_ctrl_optxenb1_c; 7170 BCMI_DINO_MOD_ABS_3_CTLr_t pad_ctrl_mod_abs_3_ctrl; 7171 BCMI_DINO_MOD_ABS_4_CTLr_t pad_ctrl_mod_abs_4_ctrl; 7172 BCMI_DINO_MOD_ABS_5_CTLr_t pad_ctrl_mod_abs_5_ctrl; 7173 BCMI_DINO_MOD_ABS_6_CTLr_t pad_ctrl_mod_abs_6_ctrl; 7174 BCMI_DINO_MOD_ABS_7_CTLr_t pad_ctrl_mod_abs_7_ctrl; 7175 BCMI_DINO_MOD_ABS_8_CTLr_t pad_ctrl_mod_abs_8_ctrl; 7176 BCMI_DINO_MOD_ABS_9_CTLr_t pad_ctrl_mod_abs_9_ctrl; 7177 BCMI_DINO_MOD_ABS_10_CTLr_t pad_ctrl_mod_abs_10_ctrl; 7178 BCMI_DINO_MOD_ABS_11_CTLr_t pad_ctrl_mod_abs_11_ctrl; 7179 BCMI_DINO_OPRXLOS_4_CTLr_t pad_ctrl_oprxlos_4_ctrl; 7180 BCMI_DINO_OPRXLOS_5_CTLr_t pad_ctrl_oprxlos_5_ctrl; 7181 BCMI_DINO_OPRXLOS_6_CTLr_t pad_ctrl_oprxlos_6_ctrl; 7182 BCMI_DINO_OPRXLOS_7_CTLr_t pad_ctrl_oprxlos_7_ctrl; 7183 BCMI_DINO_OPRXLOS_8_CTLr_t pad_ctrl_oprxlos_8_ctrl; 7184 BCMI_DINO_OPRXLOS_9_CTLr_t pad_ctrl_oprxlos_9_ctrl; 7185 BCMI_DINO_OPRXLOS_10_CTLr_t pad_ctrl_oprxlos_10_ctrl; 7186 BCMI_DINO_OPRXLOS_11_CTLr_t pad_ctrl_oprxlos_11_ctrl; 7187 7188 PHYMOD_MEMSET(&pad_ctrl_gpio_0_ctrl, 0, sizeof(BCMI_DINO_GPIO_0_CTLr_t)); 7189 PHYMOD_MEMSET(&pad_ctrl_gpio_1_ctrl, 0, sizeof(BCMI_DINO_GPIO_1_CTLr_t)); 7190 PHYMOD_MEMSET(&pad_ctrl_gpio_2_ctrl, 0, sizeof(BCMI_DINO_GPIO_2_CTLr_t)); 7191 PHYMOD_MEMSET(&pad_ctrl_gpio_3_ctrl, 0, sizeof(BCMI_DINO_GPIO_3_CTLr_t)); 7192 PHYMOD_MEMSET(&pad_ctrl_gpio_4_ctrl, 0, sizeof(BCMI_DINO_GPIO_4_CTLr_t)); 7193 PHYMOD_MEMSET(&pad_ctrl_gpio_5_ctrl, 0, sizeof(BCMI_DINO_GPIO_5_CTLr_t)); 7194 PHYMOD_MEMSET(&pad_ctrl_gpio_6_ctrl, 0, sizeof(BCMI_DINO_GPIO_6_CTLr_t)); 7195 PHYMOD_MEMSET(&pad_ctrl_gpio_7_ctrl, 0, sizeof(BCMI_DINO_GPIO_7_CTLr_t)); 7196 PHYMOD_MEMSET(&pad_ctrl_gpio_8_ctrl, 0, sizeof(BCMI_DINO_GPIO_8_CTLr_t)); 7197 PHYMOD_MEMSET(&pad_ctrl_gpio_9_ctrl, 0, sizeof(BCMI_DINO_GPIO_9_CTLr_t)); 7198 PHYMOD_MEMSET(&pad_ctrl_gpio_10_ctrl, 0, sizeof(BCMI_DINO_GPIO_10_CTLr_t)); 7199 PHYMOD_MEMSET(&pad_ctrl_gpio_11_ctrl, 0, sizeof(BCMI_DINO_GPIO_11_CTLr_t)); 7200 PHYMOD_MEMSET(&pad_ctrl_gpio_12_ctrl, 0, sizeof(BCMI_DINO_GPIO_12_CTLr_t)); 7201 PHYMOD_MEMSET(&pad_ctrl_gpio_13_ctrl, 0, sizeof(BCMI_DINO_GPIO_13_CTLr_t)); 7202 PHYMOD_MEMSET(&pad_ctrl_gpio_14_ctrl, 0, sizeof(BCMI_DINO_GPIO_14_CTLr_t)); 7203 PHYMOD_MEMSET(&pad_ctrl_gpio_15_ctrl, 0, sizeof(BCMI_DINO_GPIO_15_CTLr_t)); 7204 PHYMOD_MEMSET(&pad_ctrl_gpio_16_ctrl, 0, sizeof(BCMI_DINO_GPIO_16_CTLr_t)); 7205 PHYMOD_MEMSET(&pad_ctrl_gpio_17_ctrl, 0, sizeof(BCMI_DINO_GPIO_17_CTLr_t)); 7206 PHYMOD_MEMSET(&pad_ctrl_optxenb1_a, 0, sizeof(BCMI_DINO_OPTXENB1_A_CTLr_t)); 7207 PHYMOD_MEMSET(&pad_ctrl_optxenb1_b, 0, sizeof(BCMI_DINO_OPTXENB1_B_CTLr_t)); 7208 PHYMOD_MEMSET(&pad_ctrl_optxenb1_c, 0, sizeof(BCMI_DINO_OPTXENB1_C_CTLr_t)); 7209 PHYMOD_MEMSET(&pad_ctrl_mod_abs_3_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_3_CTLr_t)); 7210 PHYMOD_MEMSET(&pad_ctrl_mod_abs_4_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_4_CTLr_t)); 7211 PHYMOD_MEMSET(&pad_ctrl_mod_abs_5_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_5_CTLr_t)); 7212 PHYMOD_MEMSET(&pad_ctrl_mod_abs_6_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_6_CTLr_t)); 7213 PHYMOD_MEMSET(&pad_ctrl_mod_abs_7_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_7_CTLr_t)); 7214 PHYMOD_MEMSET(&pad_ctrl_mod_abs_8_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_8_CTLr_t)); 7215 PHYMOD_MEMSET(&pad_ctrl_mod_abs_9_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_9_CTLr_t)); 7216 PHYMOD_MEMSET(&pad_ctrl_mod_abs_10_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_10_CTLr_t)); 7217 PHYMOD_MEMSET(&pad_ctrl_mod_abs_11_ctrl, 0, sizeof(BCMI_DINO_MOD_ABS_11_CTLr_t)); 7218 PHYMOD_MEMSET(&pad_ctrl_oprxlos_4_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_4_CTLr_t)); 7219 PHYMOD_MEMSET(&pad_ctrl_oprxlos_5_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_5_CTLr_t)); 7220 PHYMOD_MEMSET(&pad_ctrl_oprxlos_6_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_6_CTLr_t)); 7221 PHYMOD_MEMSET(&pad_ctrl_oprxlos_7_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_7_CTLr_t)); 7222 PHYMOD_MEMSET(&pad_ctrl_oprxlos_8_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_8_CTLr_t)); 7223 PHYMOD_MEMSET(&pad_ctrl_oprxlos_9_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_9_CTLr_t)); 7224 PHYMOD_MEMSET(&pad_ctrl_oprxlos_10_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_10_CTLr_t)); 7225 PHYMOD_MEMSET(&pad_ctrl_oprxlos_11_ctrl, 0, sizeof(BCMI_DINO_OPRXLOS_11_CTLr_t)); 7226 7227 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 7228 if (chip_id == DINO_CHIP_ID_82793 && pin_number > 11) { 7229 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7230 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 11)"))); 7231 } 7232 7233 if (chip_id == DINO_CHIP_ID_82332 && pin_number > 37) { 7234 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7235 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 37)"))); 7236 } 7237 7238 switch (pin_number) { 7239 case 0: 7240 PHYMOD_IF_ERR_RETURN( 7241 BCMI_DINO_READ_GPIO_0_CTLr(pa, &pad_ctrl_gpio_0_ctrl)); 7242 BCMI_DINO_GPIO_0_CTLr_GPIO_0_IBOFf_SET(pad_ctrl_gpio_0_ctrl, 1); 7243 BCMI_DINO_GPIO_0_CTLr_GPIO_0_OUT_FRCVALf_SET(pad_ctrl_gpio_0_ctrl, value ? 1 : 0); 7244 PHYMOD_IF_ERR_RETURN( 7245 BCMI_DINO_WRITE_GPIO_0_CTLr(pa, pad_ctrl_gpio_0_ctrl)); 7246 break; 7247 case 1: 7248 PHYMOD_IF_ERR_RETURN( 7249 BCMI_DINO_READ_GPIO_1_CTLr(pa, &pad_ctrl_gpio_1_ctrl)); 7250 BCMI_DINO_GPIO_1_CTLr_GPIO_1_IBOFf_SET(pad_ctrl_gpio_1_ctrl, 1); 7251 BCMI_DINO_GPIO_1_CTLr_GPIO_1_OUT_FRCVALf_SET(pad_ctrl_gpio_1_ctrl, value ? 1 : 0); 7252 PHYMOD_IF_ERR_RETURN( 7253 BCMI_DINO_WRITE_GPIO_1_CTLr(pa,pad_ctrl_gpio_1_ctrl)); 7254 break; 7255 case 2: 7256 PHYMOD_IF_ERR_RETURN( 7257 BCMI_DINO_READ_GPIO_2_CTLr(pa, &pad_ctrl_gpio_2_ctrl)); 7258 BCMI_DINO_GPIO_2_CTLr_GPIO_2_IBOFf_SET(pad_ctrl_gpio_2_ctrl, 1); 7259 BCMI_DINO_GPIO_2_CTLr_GPIO_2_OUT_FRCVALf_SET(pad_ctrl_gpio_2_ctrl, value ? 1 : 0); 7260 PHYMOD_IF_ERR_RETURN( 7261 BCMI_DINO_WRITE_GPIO_2_CTLr(pa,pad_ctrl_gpio_2_ctrl)); 7262 break; 7263 case 3: 7264 PHYMOD_IF_ERR_RETURN( 7265 BCMI_DINO_READ_GPIO_3_CTLr(pa, &pad_ctrl_gpio_3_ctrl)); 7266 BCMI_DINO_GPIO_3_CTLr_GPIO_3_IBOFf_SET(pad_ctrl_gpio_3_ctrl, 1); 7267 BCMI_DINO_GPIO_3_CTLr_GPIO_3_OUT_FRCVALf_SET(pad_ctrl_gpio_3_ctrl, value ? 1 : 0); 7268 PHYMOD_IF_ERR_RETURN( 7269 BCMI_DINO_WRITE_GPIO_3_CTLr(pa,pad_ctrl_gpio_3_ctrl)); 7270 break; 7271 case 4: 7272 PHYMOD_IF_ERR_RETURN( 7273 BCMI_DINO_READ_GPIO_4_CTLr(pa, &pad_ctrl_gpio_4_ctrl)); 7274 BCMI_DINO_GPIO_4_CTLr_GPIO_4_IBOFf_SET(pad_ctrl_gpio_4_ctrl, 1); 7275 BCMI_DINO_GPIO_4_CTLr_GPIO_4_OUT_FRCVALf_SET(pad_ctrl_gpio_4_ctrl, value ? 1 : 0); 7276 PHYMOD_IF_ERR_RETURN( 7277 BCMI_DINO_WRITE_GPIO_4_CTLr(pa,pad_ctrl_gpio_4_ctrl)); 7278 break; 7279 case 5: 7280 PHYMOD_IF_ERR_RETURN( 7281 BCMI_DINO_READ_GPIO_5_CTLr(pa, &pad_ctrl_gpio_5_ctrl)); 7282 BCMI_DINO_GPIO_5_CTLr_GPIO_5_IBOFf_SET(pad_ctrl_gpio_5_ctrl, 1); 7283 BCMI_DINO_GPIO_5_CTLr_GPIO_5_OUT_FRCVALf_SET(pad_ctrl_gpio_5_ctrl, value ? 1 : 0); 7284 PHYMOD_IF_ERR_RETURN( 7285 BCMI_DINO_WRITE_GPIO_5_CTLr(pa,pad_ctrl_gpio_5_ctrl)); 7286 break; 7287 case 6: 7288 PHYMOD_IF_ERR_RETURN( 7289 BCMI_DINO_READ_GPIO_6_CTLr(pa, &pad_ctrl_gpio_6_ctrl)); 7290 BCMI_DINO_GPIO_6_CTLr_GPIO_6_IBOFf_SET(pad_ctrl_gpio_6_ctrl, 1); 7291 BCMI_DINO_GPIO_6_CTLr_GPIO_6_OUT_FRCVALf_SET(pad_ctrl_gpio_6_ctrl, value ? 1 : 0); 7292 PHYMOD_IF_ERR_RETURN( 7293 BCMI_DINO_WRITE_GPIO_6_CTLr(pa,pad_ctrl_gpio_6_ctrl)); 7294 break; 7295 case 7: 7296 PHYMOD_IF_ERR_RETURN( 7297 BCMI_DINO_READ_GPIO_7_CTLr(pa, &pad_ctrl_gpio_7_ctrl)); 7298 BCMI_DINO_GPIO_7_CTLr_GPIO_7_IBOFf_SET(pad_ctrl_gpio_7_ctrl, 1); 7299 BCMI_DINO_GPIO_7_CTLr_GPIO_7_OUT_FRCVALf_SET(pad_ctrl_gpio_7_ctrl, value ? 1 : 0); 7300 PHYMOD_IF_ERR_RETURN( 7301 BCMI_DINO_WRITE_GPIO_7_CTLr(pa,pad_ctrl_gpio_7_ctrl)); 7302 break; 7303 case 8: 7304 PHYMOD_IF_ERR_RETURN( 7305 BCMI_DINO_READ_GPIO_8_CTLr(pa, &pad_ctrl_gpio_8_ctrl)); 7306 BCMI_DINO_GPIO_8_CTLr_GPIO_8_IBOFf_SET(pad_ctrl_gpio_8_ctrl, 1); 7307 BCMI_DINO_GPIO_8_CTLr_GPIO_8_OUT_FRCVALf_SET(pad_ctrl_gpio_8_ctrl, value ? 1 : 0); 7308 PHYMOD_IF_ERR_RETURN( 7309 BCMI_DINO_WRITE_GPIO_8_CTLr(pa,pad_ctrl_gpio_8_ctrl)); 7310 break; 7311 case 9: 7312 PHYMOD_IF_ERR_RETURN( 7313 BCMI_DINO_READ_GPIO_9_CTLr(pa, &pad_ctrl_gpio_9_ctrl)); 7314 BCMI_DINO_GPIO_9_CTLr_GPIO_9_IBOFf_SET(pad_ctrl_gpio_9_ctrl, 1); 7315 BCMI_DINO_GPIO_9_CTLr_GPIO_9_OUT_FRCVALf_SET(pad_ctrl_gpio_9_ctrl, value ? 1 : 0); 7316 PHYMOD_IF_ERR_RETURN( 7317 BCMI_DINO_WRITE_GPIO_9_CTLr(pa,pad_ctrl_gpio_9_ctrl)); 7318 break; 7319 case 10: 7320 PHYMOD_IF_ERR_RETURN( 7321 BCMI_DINO_READ_GPIO_10_CTLr(pa, &pad_ctrl_gpio_10_ctrl)); 7322 BCMI_DINO_GPIO_10_CTLr_GPIO_10_IBOFf_SET(pad_ctrl_gpio_10_ctrl, 1); 7323 BCMI_DINO_GPIO_10_CTLr_GPIO_10_OUT_FRCVALf_SET(pad_ctrl_gpio_10_ctrl, value ? 1 : 0); 7324 PHYMOD_IF_ERR_RETURN( 7325 BCMI_DINO_WRITE_GPIO_10_CTLr(pa,pad_ctrl_gpio_10_ctrl)); 7326 break; 7327 case 11: 7328 PHYMOD_IF_ERR_RETURN( 7329 BCMI_DINO_READ_GPIO_11_CTLr(pa, &pad_ctrl_gpio_11_ctrl)); 7330 BCMI_DINO_GPIO_11_CTLr_GPIO_11_IBOFf_SET(pad_ctrl_gpio_11_ctrl, 1); 7331 BCMI_DINO_GPIO_11_CTLr_GPIO_11_OUT_FRCVALf_SET(pad_ctrl_gpio_11_ctrl, value ? 1 : 0); 7332 PHYMOD_IF_ERR_RETURN( 7333 BCMI_DINO_WRITE_GPIO_11_CTLr(pa,pad_ctrl_gpio_11_ctrl)); 7334 break; 7335 case 12: 7336 PHYMOD_IF_ERR_RETURN( 7337 BCMI_DINO_READ_GPIO_12_CTLr(pa, &pad_ctrl_gpio_12_ctrl)); 7338 BCMI_DINO_GPIO_12_CTLr_GPIO_12_IBOFf_SET(pad_ctrl_gpio_12_ctrl, 1); 7339 BCMI_DINO_GPIO_12_CTLr_GPIO_12_OUT_FRCVALf_SET(pad_ctrl_gpio_12_ctrl, value ? 1 : 0); 7340 PHYMOD_IF_ERR_RETURN( 7341 BCMI_DINO_WRITE_GPIO_12_CTLr(pa,pad_ctrl_gpio_12_ctrl)); 7342 break; 7343 case 13: 7344 PHYMOD_IF_ERR_RETURN( 7345 BCMI_DINO_READ_GPIO_13_CTLr(pa, &pad_ctrl_gpio_13_ctrl)); 7346 BCMI_DINO_GPIO_13_CTLr_GPIO_13_IBOFf_SET(pad_ctrl_gpio_13_ctrl, 1); 7347 BCMI_DINO_GPIO_13_CTLr_GPIO_13_OUT_FRCVALf_SET(pad_ctrl_gpio_13_ctrl, value ? 1 : 0); 7348 PHYMOD_IF_ERR_RETURN( 7349 BCMI_DINO_WRITE_GPIO_13_CTLr(pa,pad_ctrl_gpio_13_ctrl)); 7350 break; 7351 case 14: 7352 PHYMOD_IF_ERR_RETURN( 7353 BCMI_DINO_READ_GPIO_14_CTLr(pa, &pad_ctrl_gpio_14_ctrl)); 7354 BCMI_DINO_GPIO_14_CTLr_GPIO_14_IBOFf_SET(pad_ctrl_gpio_14_ctrl, 1); 7355 BCMI_DINO_GPIO_14_CTLr_GPIO_14_OUT_FRCVALf_SET(pad_ctrl_gpio_14_ctrl, value ? 1 : 0); 7356 PHYMOD_IF_ERR_RETURN( 7357 BCMI_DINO_WRITE_GPIO_14_CTLr(pa,pad_ctrl_gpio_14_ctrl)); 7358 break; 7359 case 15: 7360 PHYMOD_IF_ERR_RETURN( 7361 BCMI_DINO_READ_GPIO_15_CTLr(pa, &pad_ctrl_gpio_15_ctrl)); 7362 BCMI_DINO_GPIO_15_CTLr_GPIO_15_IBOFf_SET(pad_ctrl_gpio_15_ctrl, 1); 7363 BCMI_DINO_GPIO_15_CTLr_GPIO_15_OUT_FRCVALf_SET(pad_ctrl_gpio_15_ctrl, value ? 1 : 0); 7364 PHYMOD_IF_ERR_RETURN( 7365 BCMI_DINO_WRITE_GPIO_15_CTLr(pa,pad_ctrl_gpio_15_ctrl)); 7366 break; 7367 case 16: 7368 PHYMOD_IF_ERR_RETURN( 7369 BCMI_DINO_READ_GPIO_16_CTLr(pa, &pad_ctrl_gpio_16_ctrl)); 7370 BCMI_DINO_GPIO_16_CTLr_GPIO_16_IBOFf_SET(pad_ctrl_gpio_16_ctrl, 1); 7371 BCMI_DINO_GPIO_16_CTLr_GPIO_16_OUT_FRCVALf_SET(pad_ctrl_gpio_16_ctrl, value ? 1 : 0); 7372 PHYMOD_IF_ERR_RETURN( 7373 BCMI_DINO_WRITE_GPIO_16_CTLr(pa,pad_ctrl_gpio_16_ctrl)); 7374 break; 7375 case 17: 7376 PHYMOD_IF_ERR_RETURN( 7377 BCMI_DINO_READ_GPIO_17_CTLr(pa, &pad_ctrl_gpio_17_ctrl)); 7378 BCMI_DINO_GPIO_17_CTLr_GPIO_17_IBOFf_SET(pad_ctrl_gpio_17_ctrl, 1); 7379 BCMI_DINO_GPIO_17_CTLr_GPIO_17_OUT_FRCVALf_SET(pad_ctrl_gpio_17_ctrl, value ? 1 : 0); 7380 PHYMOD_IF_ERR_RETURN( 7381 BCMI_DINO_WRITE_GPIO_17_CTLr(pa,pad_ctrl_gpio_17_ctrl)); 7382 break; 7383 case 18: 7384 PHYMOD_IF_ERR_RETURN( 7385 BCMI_DINO_READ_OPTXENB1_A_CTLr(pa, &pad_ctrl_optxenb1_a)); 7386 BCMI_DINO_OPTXENB1_A_CTLr_OPTXENB1_A_IBOFf_SET(pad_ctrl_optxenb1_a, 1); 7387 BCMI_DINO_OPTXENB1_A_CTLr_OPTXENB1_A_OUT_FRCVALf_SET(pad_ctrl_optxenb1_a, value ? 1 : 0); 7388 PHYMOD_IF_ERR_RETURN( 7389 BCMI_DINO_WRITE_OPTXENB1_A_CTLr(pa, pad_ctrl_optxenb1_a)); 7390 break; 7391 case 19: 7392 PHYMOD_IF_ERR_RETURN( 7393 BCMI_DINO_READ_OPTXENB1_B_CTLr(pa, &pad_ctrl_optxenb1_b)); 7394 BCMI_DINO_OPTXENB1_B_CTLr_OPTXENB1_B_IBOFf_SET(pad_ctrl_optxenb1_b, 1); 7395 BCMI_DINO_OPTXENB1_B_CTLr_OPTXENB1_B_OUT_FRCVALf_SET(pad_ctrl_optxenb1_b, value ? 1 : 0); 7396 PHYMOD_IF_ERR_RETURN( 7397 BCMI_DINO_WRITE_OPTXENB1_B_CTLr(pa, pad_ctrl_optxenb1_b)); 7398 break; 7399 case 20: 7400 PHYMOD_IF_ERR_RETURN( 7401 BCMI_DINO_READ_OPTXENB1_C_CTLr(pa, &pad_ctrl_optxenb1_c)); 7402 BCMI_DINO_OPTXENB1_C_CTLr_OPTXENB1_C_IBOFf_SET(pad_ctrl_optxenb1_c, 1); 7403 BCMI_DINO_OPTXENB1_C_CTLr_OPTXENB1_C_OUT_FRCVALf_SET(pad_ctrl_optxenb1_c, value ? 1 : 0); 7404 PHYMOD_IF_ERR_RETURN( 7405 BCMI_DINO_WRITE_OPTXENB1_C_CTLr(pa, pad_ctrl_optxenb1_c)); 7406 break; 7407 case 21: 7408 PHYMOD_IF_ERR_RETURN( 7409 BCMI_DINO_READ_MOD_ABS_3_CTLr(pa, &pad_ctrl_mod_abs_3_ctrl)); 7410 BCMI_DINO_MOD_ABS_3_CTLr_MOD_ABS_3_IBOFf_SET(pad_ctrl_mod_abs_3_ctrl, 1); 7411 BCMI_DINO_MOD_ABS_3_CTLr_MOD_ABS_3_OUT_FRCVALf_SET(pad_ctrl_mod_abs_3_ctrl, value ? 1 : 0); 7412 PHYMOD_IF_ERR_RETURN( 7413 BCMI_DINO_WRITE_MOD_ABS_3_CTLr(pa, pad_ctrl_mod_abs_3_ctrl)); 7414 break; 7415 case 22: 7416 PHYMOD_IF_ERR_RETURN( 7417 BCMI_DINO_READ_MOD_ABS_4_CTLr(pa, &pad_ctrl_mod_abs_4_ctrl)); 7418 BCMI_DINO_MOD_ABS_4_CTLr_MOD_ABS_4_IBOFf_SET(pad_ctrl_mod_abs_4_ctrl, 1); 7419 BCMI_DINO_MOD_ABS_4_CTLr_MOD_ABS_4_OUT_FRCVALf_SET(pad_ctrl_mod_abs_4_ctrl, value ? 1 : 0); 7420 PHYMOD_IF_ERR_RETURN( 7421 BCMI_DINO_WRITE_MOD_ABS_4_CTLr(pa, pad_ctrl_mod_abs_4_ctrl)); 7422 break; 7423 case 23: 7424 PHYMOD_IF_ERR_RETURN( 7425 BCMI_DINO_READ_MOD_ABS_5_CTLr(pa, &pad_ctrl_mod_abs_5_ctrl)); 7426 BCMI_DINO_MOD_ABS_5_CTLr_MOD_ABS_5_IBOFf_SET(pad_ctrl_mod_abs_5_ctrl, 1); 7427 BCMI_DINO_MOD_ABS_5_CTLr_MOD_ABS_5_OUT_FRCVALf_SET(pad_ctrl_mod_abs_5_ctrl, value ? 1 : 0); 7428 PHYMOD_IF_ERR_RETURN( 7429 BCMI_DINO_WRITE_MOD_ABS_5_CTLr(pa, pad_ctrl_mod_abs_5_ctrl)); 7430 break; 7431 case 24: 7432 PHYMOD_IF_ERR_RETURN( 7433 BCMI_DINO_READ_MOD_ABS_6_CTLr(pa, &pad_ctrl_mod_abs_6_ctrl)); 7434 BCMI_DINO_MOD_ABS_6_CTLr_MOD_ABS_6_IBOFf_SET(pad_ctrl_mod_abs_6_ctrl, 1); 7435 BCMI_DINO_MOD_ABS_6_CTLr_MOD_ABS_6_OUT_FRCVALf_SET(pad_ctrl_mod_abs_6_ctrl, value ? 1 : 0); 7436 PHYMOD_IF_ERR_RETURN( 7437 BCMI_DINO_WRITE_MOD_ABS_6_CTLr(pa, pad_ctrl_mod_abs_6_ctrl)); 7438 break; 7439 case 25: 7440 PHYMOD_IF_ERR_RETURN( 7441 BCMI_DINO_READ_MOD_ABS_7_CTLr(pa, &pad_ctrl_mod_abs_7_ctrl)); 7442 BCMI_DINO_MOD_ABS_7_CTLr_MOD_ABS_7_IBOFf_SET(pad_ctrl_mod_abs_7_ctrl, 1); 7443 BCMI_DINO_MOD_ABS_7_CTLr_MOD_ABS_7_OUT_FRCVALf_SET(pad_ctrl_mod_abs_7_ctrl, value ? 1 : 0); 7444 PHYMOD_IF_ERR_RETURN( 7445 BCMI_DINO_WRITE_MOD_ABS_7_CTLr(pa, pad_ctrl_mod_abs_7_ctrl)); 7446 break; 7447 case 26: 7448 PHYMOD_IF_ERR_RETURN( 7449 BCMI_DINO_READ_MOD_ABS_8_CTLr(pa, &pad_ctrl_mod_abs_8_ctrl)); 7450 BCMI_DINO_MOD_ABS_8_CTLr_MOD_ABS_8_IBOFf_SET(pad_ctrl_mod_abs_8_ctrl,1 ); 7451 BCMI_DINO_MOD_ABS_8_CTLr_MOD_ABS_8_OUT_FRCVALf_SET(pad_ctrl_mod_abs_8_ctrl, value ? 1 : 0); 7452 PHYMOD_IF_ERR_RETURN( 7453 BCMI_DINO_WRITE_MOD_ABS_8_CTLr(pa, pad_ctrl_mod_abs_8_ctrl)); 7454 break; 7455 case 27: 7456 PHYMOD_IF_ERR_RETURN( 7457 BCMI_DINO_READ_MOD_ABS_9_CTLr(pa, &pad_ctrl_mod_abs_9_ctrl)); 7458 BCMI_DINO_MOD_ABS_9_CTLr_MOD_ABS_9_IBOFf_SET(pad_ctrl_mod_abs_9_ctrl, 1); 7459 BCMI_DINO_MOD_ABS_9_CTLr_MOD_ABS_9_OUT_FRCVALf_SET(pad_ctrl_mod_abs_9_ctrl, value ? 1 : 0); 7460 PHYMOD_IF_ERR_RETURN( 7461 BCMI_DINO_WRITE_MOD_ABS_9_CTLr(pa, pad_ctrl_mod_abs_9_ctrl)); 7462 break; 7463 case 28: 7464 PHYMOD_IF_ERR_RETURN( 7465 BCMI_DINO_READ_MOD_ABS_10_CTLr(pa, &pad_ctrl_mod_abs_10_ctrl)); 7466 BCMI_DINO_MOD_ABS_10_CTLr_MOD_ABS_10_IBOFf_SET(pad_ctrl_mod_abs_10_ctrl, 1); 7467 BCMI_DINO_MOD_ABS_10_CTLr_MOD_ABS_10_OUT_FRCVALf_SET(pad_ctrl_mod_abs_10_ctrl, value ? 1 : 0); 7468 PHYMOD_IF_ERR_RETURN( 7469 BCMI_DINO_WRITE_MOD_ABS_10_CTLr(pa, pad_ctrl_mod_abs_10_ctrl)); 7470 break; 7471 case 29: 7472 PHYMOD_IF_ERR_RETURN( 7473 BCMI_DINO_READ_MOD_ABS_11_CTLr(pa, &pad_ctrl_mod_abs_11_ctrl)); 7474 BCMI_DINO_MOD_ABS_11_CTLr_MOD_ABS_11_IBOFf_SET(pad_ctrl_mod_abs_11_ctrl, 1); 7475 BCMI_DINO_MOD_ABS_11_CTLr_MOD_ABS_11_OUT_FRCVALf_SET(pad_ctrl_mod_abs_11_ctrl, value ? 1 : 0); 7476 PHYMOD_IF_ERR_RETURN( 7477 BCMI_DINO_WRITE_MOD_ABS_11_CTLr(pa, pad_ctrl_mod_abs_11_ctrl)); 7478 break; 7479 case 30: 7480 PHYMOD_IF_ERR_RETURN( 7481 BCMI_DINO_READ_OPRXLOS_4_CTLr(pa, &pad_ctrl_oprxlos_4_ctrl)); 7482 BCMI_DINO_OPRXLOS_4_CTLr_OPRXLOS_4_IBOFf_SET(pad_ctrl_oprxlos_4_ctrl, 1); 7483 BCMI_DINO_OPRXLOS_4_CTLr_OPRXLOS_4_OUT_FRCVALf_SET(pad_ctrl_oprxlos_4_ctrl, value ? 1 : 0); 7484 PHYMOD_IF_ERR_RETURN( 7485 BCMI_DINO_WRITE_OPRXLOS_4_CTLr(pa, pad_ctrl_oprxlos_4_ctrl)); 7486 break; 7487 case 31: 7488 PHYMOD_IF_ERR_RETURN( 7489 BCMI_DINO_READ_OPRXLOS_5_CTLr(pa, &pad_ctrl_oprxlos_5_ctrl)); 7490 BCMI_DINO_OPRXLOS_5_CTLr_OPRXLOS_5_IBOFf_SET(pad_ctrl_oprxlos_5_ctrl, 1); 7491 BCMI_DINO_OPRXLOS_5_CTLr_OPRXLOS_5_OUT_FRCVALf_SET(pad_ctrl_oprxlos_5_ctrl, value ? 1 : 0); 7492 PHYMOD_IF_ERR_RETURN( 7493 BCMI_DINO_WRITE_OPRXLOS_5_CTLr(pa, pad_ctrl_oprxlos_5_ctrl)); 7494 break; 7495 case 32: 7496 PHYMOD_IF_ERR_RETURN( 7497 BCMI_DINO_READ_OPRXLOS_6_CTLr(pa, &pad_ctrl_oprxlos_6_ctrl)); 7498 BCMI_DINO_OPRXLOS_6_CTLr_OPRXLOS_6_IBOFf_SET(pad_ctrl_oprxlos_6_ctrl, 1); 7499 BCMI_DINO_OPRXLOS_6_CTLr_OPRXLOS_6_OUT_FRCVALf_SET(pad_ctrl_oprxlos_6_ctrl, value ? 1 : 0); 7500 PHYMOD_IF_ERR_RETURN( 7501 BCMI_DINO_WRITE_OPRXLOS_6_CTLr(pa, pad_ctrl_oprxlos_6_ctrl)); 7502 break; 7503 case 33: 7504 PHYMOD_IF_ERR_RETURN( 7505 BCMI_DINO_READ_OPRXLOS_7_CTLr(pa, &pad_ctrl_oprxlos_7_ctrl)); 7506 BCMI_DINO_OPRXLOS_7_CTLr_OPRXLOS_7_IBOFf_SET(pad_ctrl_oprxlos_7_ctrl, 1); 7507 BCMI_DINO_OPRXLOS_7_CTLr_OPRXLOS_7_OUT_FRCVALf_SET(pad_ctrl_oprxlos_7_ctrl, value ? 1 : 0); 7508 PHYMOD_IF_ERR_RETURN( 7509 BCMI_DINO_WRITE_OPRXLOS_7_CTLr(pa, pad_ctrl_oprxlos_7_ctrl)); 7510 break; 7511 case 34: 7512 PHYMOD_IF_ERR_RETURN( 7513 BCMI_DINO_READ_OPRXLOS_8_CTLr(pa, &pad_ctrl_oprxlos_8_ctrl)); 7514 BCMI_DINO_OPRXLOS_8_CTLr_OPRXLOS_8_IBOFf_SET(pad_ctrl_oprxlos_8_ctrl, 1); 7515 BCMI_DINO_OPRXLOS_8_CTLr_OPRXLOS_8_OUT_FRCVALf_SET(pad_ctrl_oprxlos_8_ctrl, value ? 1 : 0); 7516 PHYMOD_IF_ERR_RETURN( 7517 BCMI_DINO_WRITE_OPRXLOS_8_CTLr(pa, pad_ctrl_oprxlos_8_ctrl)); 7518 break; 7519 case 35: 7520 PHYMOD_IF_ERR_RETURN( 7521 BCMI_DINO_READ_OPRXLOS_9_CTLr(pa, &pad_ctrl_oprxlos_9_ctrl)); 7522 BCMI_DINO_OPRXLOS_9_CTLr_OPRXLOS_9_IBOFf_SET(pad_ctrl_oprxlos_9_ctrl, 1); 7523 BCMI_DINO_OPRXLOS_9_CTLr_OPRXLOS_9_OUT_FRCVALf_SET(pad_ctrl_oprxlos_9_ctrl, value ? 1 : 0); 7524 PHYMOD_IF_ERR_RETURN( 7525 BCMI_DINO_WRITE_OPRXLOS_9_CTLr(pa, pad_ctrl_oprxlos_9_ctrl)); 7526 break; 7527 case 36: 7528 PHYMOD_IF_ERR_RETURN( 7529 BCMI_DINO_READ_OPRXLOS_10_CTLr(pa, &pad_ctrl_oprxlos_10_ctrl)); 7530 BCMI_DINO_OPRXLOS_10_CTLr_OPRXLOS_10_IBOFf_SET(pad_ctrl_oprxlos_10_ctrl, 1); 7531 BCMI_DINO_OPRXLOS_10_CTLr_OPRXLOS_10_OUT_FRCVALf_SET(pad_ctrl_oprxlos_10_ctrl, value ? 1 : 0); 7532 PHYMOD_IF_ERR_RETURN( 7533 BCMI_DINO_WRITE_OPRXLOS_10_CTLr(pa, pad_ctrl_oprxlos_10_ctrl)); 7534 break; 7535 case 37: 7536 PHYMOD_IF_ERR_RETURN( 7537 BCMI_DINO_READ_OPRXLOS_11_CTLr(pa, &pad_ctrl_oprxlos_11_ctrl)); 7538 BCMI_DINO_OPRXLOS_11_CTLr_OPRXLOS_11_IBOFf_SET(pad_ctrl_oprxlos_11_ctrl, 1); 7539 BCMI_DINO_OPRXLOS_11_CTLr_OPRXLOS_11_OUT_FRCVALf_SET(pad_ctrl_oprxlos_11_ctrl, value ? 1 : 0); 7540 PHYMOD_IF_ERR_RETURN( 7541 BCMI_DINO_WRITE_OPRXLOS_11_CTLr(pa, pad_ctrl_oprxlos_11_ctrl)); 7542 break; 7543 default: 7544 return PHYMOD_E_PARAM; 7545 } 7546 7547 return PHYMOD_E_NONE; 7548 } 7549 7550 int _dino_phy_gpio_pin_value_get(const phymod_access_t* pa, int pin_number, int* value) 7551 { 7552 uint32_t chip_id = 0; 7553 uint32_t rev = 0; 7554 BCMI_DINO_GPIO_0_STSr_t pad_sts_gpio_0; 7555 BCMI_DINO_GPIO_1_STSr_t pad_sts_gpio_1; 7556 BCMI_DINO_GPIO_2_STSr_t pad_sts_gpio_2; 7557 BCMI_DINO_GPIO_3_STSr_t pad_sts_gpio_3; 7558 BCMI_DINO_GPIO_4_STSr_t pad_sts_gpio_4; 7559 BCMI_DINO_GPIO_5_STSr_t pad_sts_gpio_5; 7560 BCMI_DINO_GPIO_6_STSr_t pad_sts_gpio_6; 7561 BCMI_DINO_GPIO_7_STSr_t pad_sts_gpio_7; 7562 BCMI_DINO_GPIO_8_STSr_t pad_sts_gpio_8; 7563 BCMI_DINO_GPIO_9_STSr_t pad_sts_gpio_9; 7564 BCMI_DINO_GPIO_10_STSr_t pad_sts_gpio_10; 7565 BCMI_DINO_GPIO_11_STSr_t pad_sts_gpio_11; 7566 BCMI_DINO_GPIO_12_STSr_t pad_sts_gpio_12; 7567 BCMI_DINO_GPIO_13_STSr_t pad_sts_gpio_13; 7568 BCMI_DINO_GPIO_14_STSr_t pad_sts_gpio_14; 7569 BCMI_DINO_GPIO_15_STSr_t pad_sts_gpio_15; 7570 BCMI_DINO_GPIO_16_STSr_t pad_sts_gpio_16; 7571 BCMI_DINO_GPIO_17_STSr_t pad_sts_gpio_17; 7572 BCMI_DINO_OPTXENB1_A_STSr_t pad_sts_optxenb1_a; 7573 BCMI_DINO_OPTXENB1_B_STSr_t pad_sts_optxenb1_b; 7574 BCMI_DINO_OPTXENB1_C_STSr_t pad_sts_optxenb1_c; 7575 BCMI_DINO_MOD_ABS_3_STSr_t pad_sts_mod_abs_3; 7576 BCMI_DINO_MOD_ABS_4_STSr_t pad_sts_mod_abs_4; 7577 BCMI_DINO_MOD_ABS_5_STSr_t pad_sts_mod_abs_5; 7578 BCMI_DINO_MOD_ABS_6_STSr_t pad_sts_mod_abs_6; 7579 BCMI_DINO_MOD_ABS_7_STSr_t pad_sts_mod_abs_7; 7580 BCMI_DINO_MOD_ABS_8_STSr_t pad_sts_mod_abs_8; 7581 BCMI_DINO_MOD_ABS_9_STSr_t pad_sts_mod_abs_9; 7582 BCMI_DINO_MOD_ABS_10_STSr_t pad_sts_mod_abs_10; 7583 BCMI_DINO_MOD_ABS_11_STSr_t pad_sts_mod_abs_11; 7584 BCMI_DINO_OPRXLOS_4_STSr_t pad_sts_oprxlos_4; 7585 BCMI_DINO_OPRXLOS_5_STSr_t pad_sts_oprxlos_5; 7586 BCMI_DINO_OPRXLOS_6_STSr_t pad_sts_oprxlos_6; 7587 BCMI_DINO_OPRXLOS_7_STSr_t pad_sts_oprxlos_7; 7588 BCMI_DINO_OPRXLOS_8_STSr_t pad_sts_oprxlos_8; 7589 BCMI_DINO_OPRXLOS_9_STSr_t pad_sts_oprxlos_9; 7590 BCMI_DINO_OPRXLOS_10_STSr_t pad_sts_oprxlos_10; 7591 BCMI_DINO_OPRXLOS_11_STSr_t pad_sts_oprxlos_11; 7592 7593 PHYMOD_MEMSET(&pad_sts_gpio_0, 0, sizeof(BCMI_DINO_GPIO_0_STSr_t)); 7594 PHYMOD_MEMSET(&pad_sts_gpio_1, 0, sizeof(BCMI_DINO_GPIO_1_STSr_t)); 7595 PHYMOD_MEMSET(&pad_sts_gpio_2, 0, sizeof(BCMI_DINO_GPIO_2_STSr_t)); 7596 PHYMOD_MEMSET(&pad_sts_gpio_3, 0, sizeof(BCMI_DINO_GPIO_3_STSr_t)); 7597 PHYMOD_MEMSET(&pad_sts_gpio_4, 0, sizeof(BCMI_DINO_GPIO_4_STSr_t)); 7598 PHYMOD_MEMSET(&pad_sts_gpio_5, 0, sizeof(BCMI_DINO_GPIO_5_STSr_t)); 7599 PHYMOD_MEMSET(&pad_sts_gpio_6, 0, sizeof(BCMI_DINO_GPIO_6_STSr_t)); 7600 PHYMOD_MEMSET(&pad_sts_gpio_7, 0, sizeof(BCMI_DINO_GPIO_7_STSr_t)); 7601 PHYMOD_MEMSET(&pad_sts_gpio_8, 0, sizeof(BCMI_DINO_GPIO_8_STSr_t)); 7602 PHYMOD_MEMSET(&pad_sts_gpio_9, 0, sizeof(BCMI_DINO_GPIO_9_STSr_t)); 7603 PHYMOD_MEMSET(&pad_sts_gpio_10, 0, sizeof(BCMI_DINO_GPIO_10_STSr_t)); 7604 PHYMOD_MEMSET(&pad_sts_gpio_11, 0, sizeof(BCMI_DINO_GPIO_11_STSr_t)); 7605 PHYMOD_MEMSET(&pad_sts_gpio_12, 0, sizeof(BCMI_DINO_GPIO_12_STSr_t)); 7606 PHYMOD_MEMSET(&pad_sts_gpio_13, 0, sizeof(BCMI_DINO_GPIO_13_STSr_t)); 7607 PHYMOD_MEMSET(&pad_sts_gpio_14, 0, sizeof(BCMI_DINO_GPIO_14_STSr_t)); 7608 PHYMOD_MEMSET(&pad_sts_gpio_15, 0, sizeof(BCMI_DINO_GPIO_15_STSr_t)); 7609 PHYMOD_MEMSET(&pad_sts_gpio_16, 0, sizeof(BCMI_DINO_GPIO_16_STSr_t)); 7610 PHYMOD_MEMSET(&pad_sts_gpio_17, 0, sizeof(BCMI_DINO_GPIO_17_STSr_t)); 7611 PHYMOD_MEMSET(&pad_sts_optxenb1_a, 0, sizeof(BCMI_DINO_OPTXENB1_A_STSr_t)); 7612 PHYMOD_MEMSET(&pad_sts_optxenb1_b, 0, sizeof(BCMI_DINO_OPTXENB1_B_STSr_t)); 7613 PHYMOD_MEMSET(&pad_sts_optxenb1_c, 0, sizeof(BCMI_DINO_OPTXENB1_C_STSr_t)); 7614 PHYMOD_MEMSET(&pad_sts_mod_abs_3, 0, sizeof(BCMI_DINO_MOD_ABS_3_STSr_t)); 7615 PHYMOD_MEMSET(&pad_sts_mod_abs_4, 0, sizeof(BCMI_DINO_MOD_ABS_4_STSr_t)); 7616 PHYMOD_MEMSET(&pad_sts_mod_abs_5, 0, sizeof(BCMI_DINO_MOD_ABS_5_STSr_t)); 7617 PHYMOD_MEMSET(&pad_sts_mod_abs_6, 0, sizeof(BCMI_DINO_MOD_ABS_6_STSr_t)); 7618 PHYMOD_MEMSET(&pad_sts_mod_abs_7, 0, sizeof(BCMI_DINO_MOD_ABS_7_STSr_t)); 7619 PHYMOD_MEMSET(&pad_sts_mod_abs_8, 0, sizeof(BCMI_DINO_MOD_ABS_8_STSr_t)); 7620 PHYMOD_MEMSET(&pad_sts_mod_abs_9, 0, sizeof(BCMI_DINO_MOD_ABS_9_STSr_t)); 7621 PHYMOD_MEMSET(&pad_sts_mod_abs_10, 0, sizeof(BCMI_DINO_MOD_ABS_10_STSr_t)); 7622 PHYMOD_MEMSET(&pad_sts_mod_abs_11, 0, sizeof(BCMI_DINO_MOD_ABS_11_STSr_t)); 7623 PHYMOD_MEMSET(&pad_sts_oprxlos_4, 0, sizeof(BCMI_DINO_OPRXLOS_4_STSr_t)); 7624 PHYMOD_MEMSET(&pad_sts_oprxlos_5, 0, sizeof(BCMI_DINO_OPRXLOS_5_STSr_t)); 7625 PHYMOD_MEMSET(&pad_sts_oprxlos_6, 0, sizeof(BCMI_DINO_OPRXLOS_6_STSr_t)); 7626 PHYMOD_MEMSET(&pad_sts_oprxlos_7, 0, sizeof(BCMI_DINO_OPRXLOS_7_STSr_t)); 7627 PHYMOD_MEMSET(&pad_sts_oprxlos_8, 0, sizeof(BCMI_DINO_OPRXLOS_8_STSr_t)); 7628 PHYMOD_MEMSET(&pad_sts_oprxlos_9, 0, sizeof(BCMI_DINO_OPRXLOS_9_STSr_t)); 7629 PHYMOD_MEMSET(&pad_sts_oprxlos_10, 0, sizeof(BCMI_DINO_OPRXLOS_10_STSr_t)); 7630 PHYMOD_MEMSET(&pad_sts_oprxlos_11, 0, sizeof(BCMI_DINO_OPRXLOS_11_STSr_t)); 7631 7632 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev)); 7633 if (chip_id == DINO_CHIP_ID_82793 && pin_number > 11) { 7634 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7635 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 11)"))); 7636 } 7637 7638 if (chip_id == DINO_CHIP_ID_82332 && pin_number > 37) { 7639 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_CONFIG, 7640 (_PHYMOD_MSG("Invalid GPIO pin selected, Valid GPIOs are (0 - 37)"))); 7641 } 7642 7643 switch (pin_number) { 7644 case 0: 7645 PHYMOD_IF_ERR_RETURN( 7646 BCMI_DINO_READ_GPIO_0_STSr(pa, &pad_sts_gpio_0)); 7647 *value = BCMI_DINO_GPIO_0_STSr_GPIO_0_DINf_GET(pad_sts_gpio_0); 7648 break; 7649 case 1: 7650 PHYMOD_IF_ERR_RETURN( 7651 BCMI_DINO_READ_GPIO_1_STSr(pa, &pad_sts_gpio_1)); 7652 *value = BCMI_DINO_GPIO_1_STSr_GPIO_1_DINf_GET(pad_sts_gpio_1); 7653 break; 7654 case 2: 7655 PHYMOD_IF_ERR_RETURN( 7656 BCMI_DINO_READ_GPIO_2_STSr(pa, &pad_sts_gpio_2)); 7657 *value = BCMI_DINO_GPIO_2_STSr_GPIO_2_DINf_GET(pad_sts_gpio_2); 7658 break; 7659 case 3: 7660 PHYMOD_IF_ERR_RETURN( 7661 BCMI_DINO_READ_GPIO_3_STSr(pa, &pad_sts_gpio_3)); 7662 *value = BCMI_DINO_GPIO_3_STSr_GPIO_3_DINf_GET(pad_sts_gpio_3); 7663 break; 7664 case 4: 7665 PHYMOD_IF_ERR_RETURN( 7666 BCMI_DINO_READ_GPIO_4_STSr(pa, &pad_sts_gpio_4)); 7667 *value = BCMI_DINO_GPIO_4_STSr_GPIO_4_DINf_GET(pad_sts_gpio_4); 7668 break; 7669 case 5: 7670 PHYMOD_IF_ERR_RETURN( 7671 BCMI_DINO_READ_GPIO_5_STSr(pa, &pad_sts_gpio_5)); 7672 *value = BCMI_DINO_GPIO_5_STSr_GPIO_5_DINf_GET(pad_sts_gpio_5); 7673 break; 7674 case 6: 7675 PHYMOD_IF_ERR_RETURN( 7676 BCMI_DINO_READ_GPIO_6_STSr(pa, &pad_sts_gpio_6)); 7677 *value = BCMI_DINO_GPIO_6_STSr_GPIO_6_DINf_GET(pad_sts_gpio_6); 7678 break; 7679 case 7: 7680 PHYMOD_IF_ERR_RETURN( 7681 BCMI_DINO_READ_GPIO_7_STSr(pa, &pad_sts_gpio_7)); 7682 *value = BCMI_DINO_GPIO_7_STSr_GPIO_7_DINf_GET(pad_sts_gpio_7); 7683 break; 7684 case 8: 7685 PHYMOD_IF_ERR_RETURN( 7686 BCMI_DINO_READ_GPIO_8_STSr(pa, &pad_sts_gpio_8)); 7687 *value = BCMI_DINO_GPIO_8_STSr_GPIO_8_DINf_GET(pad_sts_gpio_8); 7688 break; 7689 case 9: 7690 PHYMOD_IF_ERR_RETURN( 7691 BCMI_DINO_READ_GPIO_9_STSr(pa, &pad_sts_gpio_9)); 7692 *value = BCMI_DINO_GPIO_9_STSr_GPIO_9_DINf_GET(pad_sts_gpio_9); 7693 break; 7694 case 10: 7695 PHYMOD_IF_ERR_RETURN( 7696 BCMI_DINO_READ_GPIO_10_STSr(pa, &pad_sts_gpio_10)); 7697 *value = BCMI_DINO_GPIO_10_STSr_GPIO_10_DINf_GET(pad_sts_gpio_10); 7698 break; 7699 case 11: 7700 PHYMOD_IF_ERR_RETURN( 7701 BCMI_DINO_READ_GPIO_11_STSr(pa, &pad_sts_gpio_11)); 7702 *value = BCMI_DINO_GPIO_11_STSr_GPIO_11_DINf_GET(pad_sts_gpio_11); 7703 break; 7704 case 12: 7705 PHYMOD_IF_ERR_RETURN( 7706 BCMI_DINO_READ_GPIO_12_STSr(pa, &pad_sts_gpio_12)); 7707 *value = BCMI_DINO_GPIO_12_STSr_GPIO_12_DINf_GET(pad_sts_gpio_12); 7708 break; 7709 case 13: 7710 PHYMOD_IF_ERR_RETURN( 7711 BCMI_DINO_READ_GPIO_13_STSr(pa, &pad_sts_gpio_13)); 7712 *value = BCMI_DINO_GPIO_13_STSr_GPIO_13_DINf_GET(pad_sts_gpio_13); 7713 break; 7714 case 14: 7715 PHYMOD_IF_ERR_RETURN( 7716 BCMI_DINO_READ_GPIO_14_STSr(pa, &pad_sts_gpio_14)); 7717 *value = BCMI_DINO_GPIO_14_STSr_GPIO_14_DINf_GET(pad_sts_gpio_14); 7718 break; 7719 case 15: 7720 PHYMOD_IF_ERR_RETURN( 7721 BCMI_DINO_READ_GPIO_15_STSr(pa, &pad_sts_gpio_15)); 7722 *value = BCMI_DINO_GPIO_15_STSr_GPIO_15_DINf_GET(pad_sts_gpio_15); 7723 break; 7724 case 16: 7725 PHYMOD_IF_ERR_RETURN( 7726 BCMI_DINO_READ_GPIO_16_STSr(pa, &pad_sts_gpio_16)); 7727 *value = BCMI_DINO_GPIO_16_STSr_GPIO_16_DINf_GET(pad_sts_gpio_16); 7728 break; 7729 case 17: 7730 PHYMOD_IF_ERR_RETURN( 7731 BCMI_DINO_READ_GPIO_17_STSr(pa, &pad_sts_gpio_17)); 7732 *value = BCMI_DINO_GPIO_17_STSr_GPIO_17_DINf_GET(pad_sts_gpio_17); 7733 break; 7734 case 18: 7735 PHYMOD_IF_ERR_RETURN( 7736 BCMI_DINO_READ_OPTXENB1_A_STSr(pa, &pad_sts_optxenb1_a)); 7737 *value = BCMI_DINO_OPTXENB1_A_STSr_OPTXENB1_A_DINf_GET(pad_sts_optxenb1_a); 7738 break; 7739 case 19: 7740 PHYMOD_IF_ERR_RETURN( 7741 BCMI_DINO_READ_OPTXENB1_B_STSr(pa, &pad_sts_optxenb1_b)); 7742 *value = BCMI_DINO_OPTXENB1_B_STSr_OPTXENB1_B_DINf_GET(pad_sts_optxenb1_b); 7743 break; 7744 case 20: 7745 PHYMOD_IF_ERR_RETURN( 7746 BCMI_DINO_READ_OPTXENB1_C_STSr(pa, &pad_sts_optxenb1_c)); 7747 *value = BCMI_DINO_OPTXENB1_C_STSr_OPTXENB1_C_DINf_GET(pad_sts_optxenb1_c); 7748 break; 7749 case 21: 7750 PHYMOD_IF_ERR_RETURN( 7751 BCMI_DINO_READ_MOD_ABS_3_STSr(pa, &pad_sts_mod_abs_3)); 7752 *value = BCMI_DINO_MOD_ABS_3_STSr_MOD_ABS_3_DINf_GET(pad_sts_mod_abs_3); 7753 break; 7754 case 22: 7755 PHYMOD_IF_ERR_RETURN( 7756 BCMI_DINO_READ_MOD_ABS_4_STSr(pa, &pad_sts_mod_abs_4)); 7757 *value = BCMI_DINO_MOD_ABS_4_STSr_MOD_ABS_4_DINf_GET(pad_sts_mod_abs_4); 7758 break; 7759 case 23: 7760 PHYMOD_IF_ERR_RETURN( 7761 BCMI_DINO_READ_MOD_ABS_5_STSr(pa, &pad_sts_mod_abs_5)); 7762 *value = BCMI_DINO_MOD_ABS_5_STSr_MOD_ABS_5_DINf_GET(pad_sts_mod_abs_5); 7763 break; 7764 case 24: 7765 PHYMOD_IF_ERR_RETURN( 7766 BCMI_DINO_READ_MOD_ABS_6_STSr(pa, &pad_sts_mod_abs_6)); 7767 *value = BCMI_DINO_MOD_ABS_6_STSr_MOD_ABS_6_DINf_GET(pad_sts_mod_abs_6); 7768 break; 7769 case 25: 7770 PHYMOD_IF_ERR_RETURN( 7771 BCMI_DINO_READ_MOD_ABS_7_STSr(pa, &pad_sts_mod_abs_7)); 7772 *value = BCMI_DINO_MOD_ABS_7_STSr_MOD_ABS_7_DINf_GET(pad_sts_mod_abs_7); 7773 break; 7774 case 26: 7775 PHYMOD_IF_ERR_RETURN( 7776 BCMI_DINO_READ_MOD_ABS_8_STSr(pa, &pad_sts_mod_abs_8)); 7777 *value = BCMI_DINO_MOD_ABS_8_STSr_MOD_ABS_8_DINf_GET(pad_sts_mod_abs_8); 7778 break; 7779 case 27: 7780 PHYMOD_IF_ERR_RETURN( 7781 BCMI_DINO_READ_MOD_ABS_9_STSr(pa, &pad_sts_mod_abs_9)); 7782 *value = BCMI_DINO_MOD_ABS_9_STSr_MOD_ABS_9_DINf_GET(pad_sts_mod_abs_9); 7783 break; 7784 case 28: 7785 PHYMOD_IF_ERR_RETURN( 7786 BCMI_DINO_READ_MOD_ABS_10_STSr(pa, &pad_sts_mod_abs_10)); 7787 *value = BCMI_DINO_MOD_ABS_10_STSr_MOD_ABS_10_DINf_GET(pad_sts_mod_abs_10); 7788 break; 7789 case 29: 7790 PHYMOD_IF_ERR_RETURN( 7791 BCMI_DINO_READ_MOD_ABS_11_STSr(pa, &pad_sts_mod_abs_11)); 7792 *value = BCMI_DINO_MOD_ABS_11_STSr_MOD_ABS_11_DINf_GET(pad_sts_mod_abs_11); 7793 break; 7794 case 30: 7795 PHYMOD_IF_ERR_RETURN( 7796 BCMI_DINO_READ_OPRXLOS_4_STSr(pa, &pad_sts_oprxlos_4)); 7797 *value = BCMI_DINO_OPRXLOS_4_STSr_OPRXLOS_4_DINf_GET(pad_sts_oprxlos_4); 7798 break; 7799 case 31: 7800 PHYMOD_IF_ERR_RETURN( 7801 BCMI_DINO_READ_OPRXLOS_5_STSr(pa, &pad_sts_oprxlos_5)); 7802 *value = BCMI_DINO_OPRXLOS_5_STSr_OPRXLOS_5_DINf_GET(pad_sts_oprxlos_5); 7803 break; 7804 case 32: 7805 PHYMOD_IF_ERR_RETURN( 7806 BCMI_DINO_READ_OPRXLOS_6_STSr(pa, &pad_sts_oprxlos_6)); 7807 *value = BCMI_DINO_OPRXLOS_6_STSr_OPRXLOS_6_DINf_GET(pad_sts_oprxlos_6); 7808 break; 7809 case 33: 7810 PHYMOD_IF_ERR_RETURN( 7811 BCMI_DINO_READ_OPRXLOS_7_STSr(pa, &pad_sts_oprxlos_7)); 7812 *value = BCMI_DINO_OPRXLOS_7_STSr_OPRXLOS_7_DINf_GET(pad_sts_oprxlos_7); 7813 break; 7814 case 34: 7815 PHYMOD_IF_ERR_RETURN( 7816 BCMI_DINO_READ_OPRXLOS_8_STSr(pa, &pad_sts_oprxlos_8)); 7817 *value = BCMI_DINO_OPRXLOS_8_STSr_OPRXLOS_8_DINf_GET(pad_sts_oprxlos_8); 7818 break; 7819 case 35: 7820 PHYMOD_IF_ERR_RETURN( 7821 BCMI_DINO_READ_OPRXLOS_9_STSr(pa, &pad_sts_oprxlos_9)); 7822 *value = BCMI_DINO_OPRXLOS_9_STSr_OPRXLOS_9_DINf_GET(pad_sts_oprxlos_9); 7823 break; 7824 case 36: 7825 PHYMOD_IF_ERR_RETURN( 7826 BCMI_DINO_READ_OPRXLOS_10_STSr(pa, &pad_sts_oprxlos_10)); 7827 *value = BCMI_DINO_OPRXLOS_10_STSr_OPRXLOS_10_DINf_GET(pad_sts_oprxlos_10); 7828 break; 7829 case 37: 7830 PHYMOD_IF_ERR_RETURN( 7831 BCMI_DINO_READ_OPRXLOS_11_STSr(pa, &pad_sts_oprxlos_11)); 7832 *value = BCMI_DINO_OPRXLOS_11_STSr_OPRXLOS_11_DINf_GET(pad_sts_oprxlos_11); 7833 break; 7834 default: 7835 return PHYMOD_E_PARAM; 7836 } 7837 7838 return PHYMOD_E_NONE; 7839 } 7840 7841 int _dino_cfg_fw_ull_dp(const phymod_core_access_t* core, uint16_t op_datapath) { 7842 uint16_t timing_mode = 0; 7843 uint16_t lane_idx = 0; 7844 uint16_t lane_mask = 0; 7845 uint16_t gpreg_data = 0; 7846 int num_lanes = 0; 7847 uint32_t chip_id = 0; 7848 uint32_t rev_id = 0; 7849 const phymod_access_t *pa = &core->access; 7850 7851 /* lane_mask = PHYMOD_ACC_LANE_MASK(pa); */ 7852 lane_mask = 0xfff; 7853 7854 PHYMOD_IF_ERR_RETURN(dino_get_chipid(pa, &chip_id, &rev_id)); 7855 DINO_GET_NUM_LANES(chip_id, num_lanes); 7856 7857 if (op_datapath == phymodDatapathNormal) { 7858 timing_mode = DINO_TX_REPEATER; 7859 } else if (op_datapath == phymodDatapathUll) { 7860 timing_mode = DINO_TX_REPEATER_ULL; 7861 } else { 7862 return PHYMOD_E_PARAM; 7863 } 7864 7865 /* Configure ULL datapath mode on the line side and system side*/ 7866 for (lane_idx = 0; lane_idx < num_lanes; lane_idx++) { 7867 if ((lane_mask >> lane_idx) & 0x1) { 7868 READ_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + lane_idx), gpreg_data); 7869 gpreg_data &= ~(DINO_LINE_TX_TIMING_MODE_MASK); 7870 gpreg_data |= (timing_mode << DINO_LINE_TX_TIMING_MODE_SHIFT); 7871 gpreg_data &= ~(DINO_SYS_TX_TIMING_MODE_MASK); 7872 gpreg_data |= (timing_mode << DINO_SYS_TX_TIMING_MODE_SHIFT); 7873 WRITE_DINO_PMA_PMD_REG(pa, (DINO_GPREG_0_ADR + lane_idx), gpreg_data); 7874 } 7875 } 7876 /* Notify the firmware about the configurations */ 7877 PHYMOD_IF_ERR_RETURN(_dino_fw_enable(pa)); 7878 7879 return PHYMOD_E_NONE; 7880 } 7881 int _dino_phy_multi_get(const phymod_access_t* pa, phymod_multi_data_t* multi_data) 7882 { 7883 PHYMOD_IF_ERR_RETURN 7884 (_dino_phy_i2c_read(pa, multi_data->dev_addr, multi_data->offset, multi_data->max_size, multi_data->data)); 7885 if (multi_data->actual_size) { 7886 (*(multi_data->actual_size)) = multi_data->max_size; 7887 } 7888 7889 return PHYMOD_E_NONE; 7890 } 7891