blackhawk_tsc_fields.h (401770B)
1 /************************************************************************************* 2 ************************************************************************************* 3 * * 4 * Revision : * 5 * * 6 * Description : Register access macros for BLACKHAWK_TSC 7 * * 8 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 9 * 10 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 11 * No portions of this material may be reproduced in any form without * 12 * the written permission of: * 13 * Broadcom Corporation * 14 * 5300 California Avenue * 15 * Irvine, CA 92617 * 16 * * 17 * All information contained in this document is Broadcom Corporation * 18 * company private proprietary, and trade secret. * 19 */ 20 21 /** @file blackhawk_tsc_fields.h 22 * Register access macros for BLACKHAWK_TSC 23 */ 24 25 /* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */ 26 27 #ifndef BLACKHAWK_TSC_FIELDS_H 28 #define BLACKHAWK_TSC_FIELDS_H 29 30 #define rdc_ams_pll_rescal_aux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,0,12,__ERR) 31 #define wrc_ams_pll_rescal_aux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0xf000,12,wr_val) 32 #define rdc_ams_pll_refclk_1x() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,4,15,__ERR) 33 #define wrc_ams_pll_refclk_1x(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0x0800,11,wr_val) 34 #define rdc_ams_pll_lpf_rz() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,5,14,__ERR) 35 #define wrc_ams_pll_lpf_rz(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0x0600,9,wr_val) 36 #define rdc_ams_pll_fp3_rh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,7,15,__ERR) 37 #define wrc_ams_pll_fp3_rh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0x0100,8,wr_val) 38 #define rdc_ams_pll_fp3_ctrl() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,8,12,__ERR) 39 #define wrc_ams_pll_fp3_ctrl(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0x00f0,4,wr_val) 40 #define rdc_ams_pll_cp_cmfdbk_iadj() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,12,14,__ERR) 41 #define wrc_ams_pll_cp_cmfdbk_iadj(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0x000c,2,wr_val) 42 #define rdc_ams_pll_set_clk4pcs() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd110,14,14,__ERR) 43 #define wrc_ams_pll_set_clk4pcs(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd110,0x0003,0,wr_val) 44 #define rdc_ams_pll_enable_ftune() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,0,15,__ERR) 45 #define wrc_ams_pll_enable_ftune(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x8000,15,wr_val) 46 #define rdc_ams_pll_reset() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,1,15,__ERR) 47 #define wrc_ams_pll_reset(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x4000,14,wr_val) 48 #define rdc_ams_pll_ivco() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,2,13,__ERR) 49 #define wrc_ams_pll_ivco(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x3800,11,wr_val) 50 #define rdc_ams_pll_test_vco2_cssw() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,5,15,__ERR) 51 #define wrc_ams_pll_test_vco2_cssw(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0400,10,wr_val) 52 #define rdc_ams_pll_vcoictrl() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,6,14,__ERR) 53 #define wrc_ams_pll_vcoictrl(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0300,8,wr_val) 54 #define rdc_ams_pll_vco2_15g() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,8,15,__ERR) 55 #define wrc_ams_pll_vco2_15g(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0080,7,wr_val) 56 #define rdc_ams_pll_muxdiv_ictrl_1() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,9,15,__ERR) 57 #define wrc_ams_pll_muxdiv_ictrl_1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0040,6,wr_val) 58 #define rdc_ams_pll_vco_res_cs() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,10,15,__ERR) 59 #define wrc_ams_pll_vco_res_cs(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0020,5,wr_val) 60 #define rdc_ams_pll_muxdiv_ictrl_0() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,11,15,__ERR) 61 #define wrc_ams_pll_muxdiv_ictrl_0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0010,4,wr_val) 62 #define rdc_ams_pll_drv_hv_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,12,15,__ERR) 63 #define wrc_ams_pll_drv_hv_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0008,3,wr_val) 64 #define rdc_ams_pll_comp_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd111,13,13,__ERR) 65 #define wrc_ams_pll_comp_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd111,0x0007,0,wr_val) 66 #define rdc_ams_pll_iqp() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd112,12,12,__ERR) 67 #define wrc_ams_pll_iqp(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd112,0x000f,0,wr_val) 68 #define rdc_ams_pll_force_rescal() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,0,15,__ERR) 69 #define wrc_ams_pll_force_rescal(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x8000,15,wr_val) 70 #define rdc_ams_pll_force_kvh_bw() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,1,15,__ERR) 71 #define wrc_ams_pll_force_kvh_bw(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x4000,14,wr_val) 72 #define rdc_ams_pll_kvh_force() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,2,14,__ERR) 73 #define wrc_ams_pll_kvh_force(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x3000,12,wr_val) 74 #define rdc_ams_pll_vddr_bgb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,4,15,__ERR) 75 #define wrc_ams_pll_vddr_bgb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x0800,11,wr_val) 76 #define rdc_ams_pll_test_vddr4bg() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,5,15,__ERR) 77 #define wrc_ams_pll_test_vddr4bg(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x0400,10,wr_val) 78 #define rdc_ams_pll_pll2rx_clkbw() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,6,14,__ERR) 79 #define wrc_ams_pll_pll2rx_clkbw(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x0300,8,wr_val) 80 #define rdc_ams_pll_bgr_ctatadj() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,8,12,__ERR) 81 #define wrc_ams_pll_bgr_ctatadj(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x00f0,4,wr_val) 82 #define rdc_ams_pll_bgr_ptatadj() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd114,12,12,__ERR) 83 #define wrc_ams_pll_bgr_ptatadj(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd114,0x000f,0,wr_val) 84 #define rdc_ams_pll_refclk_doubler() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,0,15,__ERR) 85 #define wrc_ams_pll_refclk_doubler(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x8000,15,wr_val) 86 #define rdc_ams_pll_doubler_res() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,1,13,__ERR) 87 #define wrc_ams_pll_doubler_res(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x7000,12,wr_val) 88 #define rdc_ams_pll_set_clk4pcs_msb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,4,15,__ERR) 89 #define wrc_ams_pll_set_clk4pcs_msb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0800,11,wr_val) 90 #define rdc_ams_pll_doubler_cap() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,5,13,__ERR) 91 #define wrc_ams_pll_doubler_cap(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0700,8,wr_val) 92 #define rdc_ams_pll_clk4sync_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,8,15,__ERR) 93 #define wrc_ams_pll_clk4sync_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0080,7,wr_val) 94 #define rdc_ams_pll_clk4sync_div() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,9,15,__ERR) 95 #define wrc_ams_pll_clk4sync_div(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0040,6,wr_val) 96 #define rdc_ams_pll_rterm300() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,10,15,__ERR) 97 #define wrc_ams_pll_rterm300(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0020,5,wr_val) 98 #define rdc_ams_pll_rtermhiz() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,11,15,__ERR) 99 #define wrc_ams_pll_rtermhiz(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0010,4,wr_val) 100 #define rdc_ams_pll_rterm400() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,12,15,__ERR) 101 #define wrc_ams_pll_rterm400(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0008,3,wr_val) 102 #define rdc_ams_pll_div4() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,13,15,__ERR) 103 #define wrc_ams_pll_div4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0004,2,wr_val) 104 #define rdc_ams_pll_div2() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,14,15,__ERR) 105 #define wrc_ams_pll_div2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0002,1,wr_val) 106 #define rdc_ams_pll_rterm200() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd116,15,15,__ERR) 107 #define wrc_ams_pll_rterm200(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd116,0x0001,0,wr_val) 108 #define rdc_ams_pll_mix3p1cr_ptatadj() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,0,11,__ERR) 109 #define wrc_ams_pll_mix3p1cr_ptatadj(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0xf800,11,wr_val) 110 #define rdc_ams_pll_mix3p1cr_ctatadj() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,5,11,__ERR) 111 #define wrc_ams_pll_mix3p1cr_ctatadj(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x07c0,6,wr_val) 112 #define rdc_ams_pll_vcodiv_refout() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,10,15,__ERR) 113 #define wrc_ams_pll_vcodiv_refout(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x0020,5,wr_val) 114 #define rdc_ams_pll_ndiv_frac_valid() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,11,15,__ERR) 115 #define wrc_ams_pll_ndiv_frac_valid(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x0010,4,wr_val) 116 #define rdc_ams_pll_pfd_ref_skew() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,12,15,__ERR) 117 #define wrc_ams_pll_pfd_ref_skew(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x0008,3,wr_val) 118 #define rdc_ams_pll_pfd_fb_skew() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,13,15,__ERR) 119 #define wrc_ams_pll_pfd_fb_skew(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x0004,2,wr_val) 120 #define rdc_ams_pll_pfd_skew_enlarge() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,14,15,__ERR) 121 #define wrc_ams_pll_pfd_skew_enlarge(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x0002,1,wr_val) 122 #define rdc_ams_pll_test_fracn_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd117,15,15,__ERR) 123 #define wrc_ams_pll_test_fracn_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd117,0x0001,0,wr_val) 124 #define rdc_ams_pll_fracn_div() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd118,__ERR) 125 #define wrc_ams_pll_fracn_div(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd118,wr_val) 126 #define rdc_ams_pll_fracn_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd119,0,15,__ERR) 127 #define wrc_ams_pll_fracn_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd119,0x8000,15,wr_val) 128 #define rdc_ams_pll_ditheren() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd119,1,15,__ERR) 129 #define wrc_ams_pll_ditheren(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd119,0x4000,14,wr_val) 130 #define rdc_ams_pll_fracn_ndiv_int() _blackhawk_tsc_pmd_rde_field(sa__, 0xd119,2,6,__ERR) 131 #define wrc_ams_pll_fracn_ndiv_int(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd119,0x3ff0,4,wr_val) 132 #define rdc_ams_pll_fracn_bypass() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd119,12,15,__ERR) 133 #define wrc_ams_pll_fracn_bypass(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd119,0x0008,3,wr_val) 134 #define rdc_ams_pll_fracn_divrange() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd119,13,15,__ERR) 135 #define wrc_ams_pll_fracn_divrange(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd119,0x0004,2,wr_val) 136 #define rdc_ams_pll_fracn_div_17_16() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd119,14,14,__ERR) 137 #define wrc_ams_pll_fracn_div_17_16(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd119,0x0003,0,wr_val) 138 #define rdc_ams_pll_pwrdn() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11b,13,15,__ERR) 139 #define wrc_ams_pll_pwrdn(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd11b,0x0004,2,wr_val) 140 #define rdc_ams_pll_div4_2_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11b,14,15,__ERR) 141 #define wrc_ams_pll_div4_2_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd11b,0x0002,1,wr_val) 142 #define rdc_ams_pll_rterm_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11b,15,15,__ERR) 143 #define wrc_ams_pll_rterm_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd11b,0x0001,0,wr_val) 144 #define rdc_ams_pll_kvh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11c,0,14,__ERR) 145 #define rdc_ams_pll_range() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11c,2,8,__ERR) 146 #define rdc_ams_pll_low() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11c,10,15,__ERR) 147 #define rdc_ams_pll_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd11c,11,11,__ERR) 148 #define rd_ams_rx_pf_max_bw() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c0,6,15,__ERR) 149 #define wr_ams_rx_pf_max_bw(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c0,0x0200,9,wr_val) 150 #define rd_ams_rx_vga3_ind() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c2,1,15,__ERR) 151 #define wr_ams_rx_vga3_ind(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c2,0x4000,14,wr_val) 152 #define rd_ams_rx_vga1_rescal_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c4,0,11,__ERR) 153 #define wr_ams_rx_vga1_rescal_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c4,0xf800,11,wr_val) 154 #define rd_ams_rx_vga0_rescal_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c4,5,11,__ERR) 155 #define wr_ams_rx_vga0_rescal_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c4,0x07c0,6,wr_val) 156 #define rd_ams_rx_sd_cal_pos() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c5,5,13,__ERR) 157 #define wr_ams_rx_sd_cal_pos(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c5,0x0700,8,wr_val) 158 #define rd_ams_rx_sd_cal_neg() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c5,8,13,__ERR) 159 #define wr_ams_rx_sd_cal_neg(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c5,0x00e0,5,wr_val) 160 #define rd_ams_rx_vga2_rescal_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c5,11,11,__ERR) 161 #define wr_ams_rx_vga2_rescal_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c5,0x001f,0,wr_val) 162 #define rd_ams_rx_dac4ck_phs_q() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c8,0,12,__ERR) 163 #define wr_ams_rx_dac4ck_phs_q(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c8,0xf000,12,wr_val) 164 #define rd_ams_rx_dac4ck_phs_i() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c8,4,12,__ERR) 165 #define wr_ams_rx_dac4ck_phs_i(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c8,0x0f00,8,wr_val) 166 #define rd_ams_rx_dac4ck_lms_q() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c8,8,12,__ERR) 167 #define wr_ams_rx_dac4ck_lms_q(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c8,0x00f0,4,wr_val) 168 #define rd_ams_rx_dac4ck_lms_i() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c8,12,12,__ERR) 169 #define wr_ams_rx_dac4ck_lms_i(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c8,0x000f,0,wr_val) 170 #define rd_ams_rx_dac4ck_dat_q() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c9,8,12,__ERR) 171 #define wr_ams_rx_dac4ck_dat_q(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c9,0x00f0,4,wr_val) 172 #define rd_ams_rx_dac4ck_dat_i() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0c9,12,12,__ERR) 173 #define wr_ams_rx_dac4ck_dat_i(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0c9,0x000f,0,wr_val) 174 #define rd_ams_rx_vga_bw_ctrl_ind() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ca,0,14,__ERR) 175 #define wr_ams_rx_vga_bw_ctrl_ind(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0ca,0xc000,14,wr_val) 176 #define rd_ams_rx_vga01_bw_ctrl_cap() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ca,2,14,__ERR) 177 #define wr_ams_rx_vga01_bw_ctrl_cap(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0ca,0x3000,12,wr_val) 178 #define rd_ams_rx_vga2_bw_ctrl_cap() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ca,4,15,__ERR) 179 #define wr_ams_rx_vga2_bw_ctrl_cap(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0ca,0x0800,11,wr_val) 180 #define rd_ams_rx_pf3_max_bw() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ca,7,15,__ERR) 181 #define wr_ams_rx_pf3_max_bw(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0ca,0x0100,8,wr_val) 182 #define rd_ams_rx_pf3_ctrl() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ca,12,12,__ERR) 183 #define wr_ams_rx_pf3_ctrl(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0ca,0x000f,0,wr_val) 184 #define rd_ams_tx_ticksel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d0,8,14,__ERR) 185 #define wr_ams_tx_ticksel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0d0,0x00c0,6,wr_val) 186 #define rd_ams_tx_spare_63_56() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d3,0,8,__ERR) 187 #define wr_ams_tx_spare_63_56(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0d3,0xff00,8,wr_val) 188 #define rd_ams_tx_sel_txmaster() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d3,8,15,__ERR) 189 #define wr_ams_tx_sel_txmaster(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0080,7,wr_val) 190 #define rd_ams_tx_spare_54() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d3,9,15,__ERR) 191 #define wr_ams_tx_spare_54(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0040,6,wr_val) 192 #define rd_ams_tx_pdet_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d3,10,15,__ERR) 193 #define wr_ams_tx_pdet_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0020,5,wr_val) 194 #define rd_ams_tx_spare_52_48() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d3,11,11,__ERR) 195 #define wr_ams_tx_spare_52_48(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0d3,0x001f,0,wr_val) 196 #define rd_ams_tx_lane_id() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d9,0,14,__ERR) 197 #define rd_ams_tx_spare_13() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d9,2,15,__ERR) 198 #define rd_ams_tx_drv_hv_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d9,3,15,__ERR) 199 #define rd_ams_tx_ana_rescal() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d9,4,12,__ERR) 200 #define rd_ams_tx_version_id() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0d9,8,8,__ERR) 201 #define rdc_pmd_core_mode() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd180,__ERR) 202 #define rdc_pmd_core_dp_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd182,14,15,__ERR) 203 #define wrc_pmd_core_dp_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd182,0x0002,1,wr_val) 204 #define rdc_core_hw_fw_handshake_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd184,0,15,__ERR) 205 #define wrc_core_hw_fw_handshake_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd184,0x8000,15,wr_val) 206 #define rdc_afe_s_pll_pwrdn() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd184,1,15,__ERR) 207 #define wrc_afe_s_pll_pwrdn(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd184,0x4000,14,wr_val) 208 #define rdc_core_dp_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd184,2,15,__ERR) 209 #define wrc_core_dp_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd184,0x2000,13,wr_val) 210 #define rdc_uc_ack_core_dp_reset() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd185,14,15,__ERR) 211 #define wrc_uc_ack_core_dp_reset(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd185,0x0002,1,wr_val) 212 #define rdc_uc_ack_core_cfg_done() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd185,15,15,__ERR) 213 #define wrc_uc_ack_core_cfg_done(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd185,0x0001,0,wr_val) 214 #define rdc_core_dp_reset_state() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd188,13,13,__ERR) 215 #define rdc_pll_pwrdn_or() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd189,15,15,__ERR) 216 #define rdc_pll_uc_core_config_core_cfg_from_pcs() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd18d,7,15,__ERR) 217 #define wrc_pll_uc_core_config_core_cfg_from_pcs(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd18d,0x0100,8,wr_val) 218 #define rdc_pll_uc_core_config_vco_rate() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd18d,8,8,__ERR) 219 #define wrc_pll_uc_core_config_vco_rate(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd18d,0x00ff,0,wr_val) 220 #define rdc_pll_cfg_fwapi_data1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd18e,__ERR) 221 #define wrc_pll_cfg_fwapi_data1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd18e,wr_val) 222 #define rdc_revid_rev_letter() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd100,0,14,__ERR) 223 #define rdc_revid_rev_number() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd100,2,13,__ERR) 224 #define rdc_revid_bonding() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd100,5,14,__ERR) 225 #define rdc_revid_process() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd100,7,13,__ERR) 226 #define rdc_revid_model() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd100,10,10,__ERR) 227 #define rdc_revid_multiplicity() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,0,12,__ERR) 228 #define rdc_revid_mdio() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,10,15,__ERR) 229 #define rdc_revid_micro() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,11,15,__ERR) 230 #define rdc_revid_cl72() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,12,15,__ERR) 231 #define rdc_revid_pir() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,13,15,__ERR) 232 #define rdc_revid_llp() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,14,15,__ERR) 233 #define rdc_revid_eee() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10a,15,15,__ERR) 234 #define rdc_revid2() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd10e,12,12,__ERR) 235 #define rdc_uc_active() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd101,14,15,__ERR) 236 #define wrc_uc_active(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd101,0x0002,1,wr_val) 237 #define rdc_core_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd101,15,15,__ERR) 238 #define wrc_core_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd101,0x0001,0,wr_val) 239 #define rdc_disable_ack_timeout() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd102,0,15,__ERR) 240 #define wrc_disable_ack_timeout(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd102,0x8000,15,wr_val) 241 #define rdc_pmd_mdio_trans_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd102,10,15,__ERR) 242 #define wrc_pmd_mdio_trans_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd102,0x0020,5,wr_val) 243 #define rdc_sup_rst_seq_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd102,11,15,__ERR) 244 #define wrc_sup_rst_seq_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd102,0x0010,4,wr_val) 245 #define rdc_sup_rst_seq_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd102,12,15,__ERR) 246 #define wrc_sup_rst_seq_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd102,0x0008,3,wr_val) 247 #define rdc_maskdata() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd103,__ERR) 248 #define wrc_maskdata(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd103,wr_val) 249 #define rdc_mdio_fast_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd104,3,15,__ERR) 250 #define wrc_mdio_fast_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd104,0x1000,12,wr_val) 251 #define rdc_mdio_fast_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd104,4,15,__ERR) 252 #define wrc_mdio_fast_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd104,0x0800,11,wr_val) 253 #define rdc_maskdata_bus_assign() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd104,5,15,__ERR) 254 #define wrc_maskdata_bus_assign(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd104,0x0400,10,wr_val) 255 #define rdc_heartbeat_count_1us() _blackhawk_tsc_pmd_rde_field(sa__, 0xd104,6,6,__ERR) 256 #define wrc_heartbeat_count_1us(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd104,0x03ff,0,wr_val) 257 #define rdc_lane_reset_released() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd108,1,15,__ERR) 258 #define rdc_lane_reset_released_index() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd108,3,11,__ERR) 259 #define rdc_tx_lane_reset_released() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd108,0,15,__ERR) 260 #define rdc_tx_lane_reset_released_index() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd108,8,11,__ERR) 261 #define rdc_tx_lane_addr_0() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd190,3,11,__ERR) 262 #define wrc_tx_lane_addr_0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd190,0x1f00,8,wr_val) 263 #define rdc_rx_lane_addr_0() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd190,11,11,__ERR) 264 #define wrc_rx_lane_addr_0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd190,0x001f,0,wr_val) 265 #define rdc_tx_lane_addr_1() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd191,3,11,__ERR) 266 #define wrc_tx_lane_addr_1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd191,0x1f00,8,wr_val) 267 #define rdc_rx_lane_addr_1() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd191,11,11,__ERR) 268 #define wrc_rx_lane_addr_1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd191,0x001f,0,wr_val) 269 #define rdc_tx_lane_addr_2() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd192,3,11,__ERR) 270 #define wrc_tx_lane_addr_2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd192,0x1f00,8,wr_val) 271 #define rdc_rx_lane_addr_2() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd192,11,11,__ERR) 272 #define wrc_rx_lane_addr_2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd192,0x001f,0,wr_val) 273 #define rdc_tx_lane_addr_3() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd193,3,11,__ERR) 274 #define wrc_tx_lane_addr_3(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd193,0x1f00,8,wr_val) 275 #define rdc_rx_lane_addr_3() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd193,11,11,__ERR) 276 #define wrc_rx_lane_addr_3(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd193,0x001f,0,wr_val) 277 #define rdc_tx_lane_addr_4() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd194,3,11,__ERR) 278 #define wrc_tx_lane_addr_4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd194,0x1f00,8,wr_val) 279 #define rdc_rx_lane_addr_4() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd194,11,11,__ERR) 280 #define wrc_rx_lane_addr_4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd194,0x001f,0,wr_val) 281 #define rdc_tx_lane_addr_5() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd195,3,11,__ERR) 282 #define wrc_tx_lane_addr_5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd195,0x1f00,8,wr_val) 283 #define rdc_rx_lane_addr_5() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd195,11,11,__ERR) 284 #define wrc_rx_lane_addr_5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd195,0x001f,0,wr_val) 285 #define rdc_tx_lane_addr_6() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd196,3,11,__ERR) 286 #define wrc_tx_lane_addr_6(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd196,0x1f00,8,wr_val) 287 #define rdc_rx_lane_addr_6() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd196,11,11,__ERR) 288 #define wrc_rx_lane_addr_6(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd196,0x001f,0,wr_val) 289 #define rdc_tx_lane_addr_7() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd197,3,11,__ERR) 290 #define wrc_tx_lane_addr_7(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd197,0x1f00,8,wr_val) 291 #define rdc_rx_lane_addr_7() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd197,11,11,__ERR) 292 #define wrc_rx_lane_addr_7(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd197,0x001f,0,wr_val) 293 #define rd_uc_dsc_supp_info() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd03d,0,8,__ERR) 294 #define wr_uc_dsc_supp_info(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd03d,0xff00,8,wr_val) 295 #define rd_uc_dsc_ready_for_cmd() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd03d,8,15,__ERR) 296 #define wr_uc_dsc_ready_for_cmd(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd03d,0x0080,7,wr_val) 297 #define rd_uc_dsc_error_found() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd03d,9,15,__ERR) 298 #define wr_uc_dsc_error_found(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd03d,0x0040,6,wr_val) 299 #define rd_uc_dsc_gp_uc_req() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd03d,10,10,__ERR) 300 #define wr_uc_dsc_gp_uc_req(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd03d,0x003f,0,wr_val) 301 #define rd_uc_dsc_data() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd03e,__ERR) 302 #define wr_uc_dsc_data(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd03e,wr_val) 303 #define rd_blw_gain() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd03b,1,1,__ERR) 304 #define rd_rxa_slicer_offset_adj_cal_d5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd005,2,10,__ERR) 305 #define wr_rxa_slicer_offset_adj_cal_d5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd005,0x3f00,8,wr_val) 306 #define rd_rxa_slicer_offset_adj_cal_d4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd005,10,10,__ERR) 307 #define wr_rxa_slicer_offset_adj_cal_d4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd005,0x003f,0,wr_val) 308 #define rd_rxa_slicer_offset_adj_cal_d3() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd006,2,10,__ERR) 309 #define wr_rxa_slicer_offset_adj_cal_d3(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd006,0x3f00,8,wr_val) 310 #define rd_rxa_slicer_offset_adj_cal_d2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd006,10,10,__ERR) 311 #define wr_rxa_slicer_offset_adj_cal_d2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd006,0x003f,0,wr_val) 312 #define rd_rxa_slicer_offset_adj_cal_d1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd007,2,10,__ERR) 313 #define wr_rxa_slicer_offset_adj_cal_d1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd007,0x3f00,8,wr_val) 314 #define rd_rxa_slicer_offset_adj_cal_d0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd007,10,10,__ERR) 315 #define wr_rxa_slicer_offset_adj_cal_d0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd007,0x003f,0,wr_val) 316 #define rd_rxa_slicer_offset_adj_cal_p2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd008,2,10,__ERR) 317 #define wr_rxa_slicer_offset_adj_cal_p2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd008,0x3f00,8,wr_val) 318 #define rd_rxa_slicer_offset_adj_cal_p1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd008,10,10,__ERR) 319 #define wr_rxa_slicer_offset_adj_cal_p1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd008,0x003f,0,wr_val) 320 #define rd_rxa_slicer_offset_adj_cal_p0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd009,2,10,__ERR) 321 #define wr_rxa_slicer_offset_adj_cal_p0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd009,0x3f00,8,wr_val) 322 #define rd_rxa_slicer_offset_adj_cal_lms() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd009,10,10,__ERR) 323 #define wr_rxa_slicer_offset_adj_cal_lms(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd009,0x003f,0,wr_val) 324 #define rd_rxb_slicer_offset_adj_cal_d5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00a,2,10,__ERR) 325 #define wr_rxb_slicer_offset_adj_cal_d5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00a,0x3f00,8,wr_val) 326 #define rd_rxb_slicer_offset_adj_cal_d4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00a,10,10,__ERR) 327 #define wr_rxb_slicer_offset_adj_cal_d4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00a,0x003f,0,wr_val) 328 #define rd_rxb_slicer_offset_adj_cal_d3() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00b,2,10,__ERR) 329 #define wr_rxb_slicer_offset_adj_cal_d3(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00b,0x3f00,8,wr_val) 330 #define rd_rxb_slicer_offset_adj_cal_d2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00b,10,10,__ERR) 331 #define wr_rxb_slicer_offset_adj_cal_d2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00b,0x003f,0,wr_val) 332 #define rd_rxb_slicer_offset_adj_cal_d1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00c,2,10,__ERR) 333 #define wr_rxb_slicer_offset_adj_cal_d1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00c,0x3f00,8,wr_val) 334 #define rd_rxb_slicer_offset_adj_cal_d0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00c,10,10,__ERR) 335 #define wr_rxb_slicer_offset_adj_cal_d0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00c,0x003f,0,wr_val) 336 #define rd_rxb_slicer_offset_adj_cal_p2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00d,2,10,__ERR) 337 #define wr_rxb_slicer_offset_adj_cal_p2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00d,0x3f00,8,wr_val) 338 #define rd_rxb_slicer_offset_adj_cal_p1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00d,10,10,__ERR) 339 #define wr_rxb_slicer_offset_adj_cal_p1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00d,0x003f,0,wr_val) 340 #define rd_rxb_slicer_offset_adj_cal_p0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00e,2,10,__ERR) 341 #define wr_rxb_slicer_offset_adj_cal_p0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00e,0x3f00,8,wr_val) 342 #define rd_rxb_slicer_offset_adj_cal_lms() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd00e,10,10,__ERR) 343 #define wr_rxb_slicer_offset_adj_cal_lms(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd00e,0x003f,0,wr_val) 344 #define rd_rxa_dfe_tap4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd013,6,11,__ERR) 345 #define wr_rxa_dfe_tap4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd013,0x03e0,5,wr_val) 346 #define rd_rxb_dfe_tap4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd013,11,11,__ERR) 347 #define wr_rxb_dfe_tap4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd013,0x001f,0,wr_val) 348 #define rd_rxc_dfe_tap4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd014,6,11,__ERR) 349 #define wr_rxc_dfe_tap4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd014,0x03e0,5,wr_val) 350 #define rd_rxd_dfe_tap4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd014,11,11,__ERR) 351 #define wr_rxd_dfe_tap4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd014,0x001f,0,wr_val) 352 #define rd_rxa_dfe_tap5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd015,0,12,__ERR) 353 #define wr_rxa_dfe_tap5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd015,0xf000,12,wr_val) 354 #define rd_rxb_dfe_tap5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd015,4,12,__ERR) 355 #define wr_rxb_dfe_tap5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd015,0x0f00,8,wr_val) 356 #define rd_rxc_dfe_tap5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd015,8,12,__ERR) 357 #define wr_rxc_dfe_tap5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd015,0x00f0,4,wr_val) 358 #define rd_rxd_dfe_tap5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd015,12,12,__ERR) 359 #define wr_rxd_dfe_tap5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd015,0x000f,0,wr_val) 360 #define rd_rxa_dfe_tap6() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd016,0,12,__ERR) 361 #define wr_rxa_dfe_tap6(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd016,0xf000,12,wr_val) 362 #define rd_rxb_dfe_tap6() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd016,4,12,__ERR) 363 #define wr_rxb_dfe_tap6(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd016,0x0f00,8,wr_val) 364 #define rd_rxc_dfe_tap6() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd016,8,12,__ERR) 365 #define wr_rxc_dfe_tap6(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd016,0x00f0,4,wr_val) 366 #define rd_rxd_dfe_tap6() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd016,12,12,__ERR) 367 #define wr_rxd_dfe_tap6(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd016,0x000f,0,wr_val) 368 #define rd_rxa_dfe_tap7() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd017,0,12,__ERR) 369 #define wr_rxa_dfe_tap7(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd017,0xf000,12,wr_val) 370 #define rd_rxb_dfe_tap7() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd017,4,12,__ERR) 371 #define wr_rxb_dfe_tap7(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd017,0x0f00,8,wr_val) 372 #define rd_rxc_dfe_tap7() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd017,8,12,__ERR) 373 #define wr_rxc_dfe_tap7(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd017,0x00f0,4,wr_val) 374 #define rd_rxd_dfe_tap7() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd017,12,12,__ERR) 375 #define wr_rxd_dfe_tap7(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd017,0x000f,0,wr_val) 376 #define rd_rxa_dfe_tap8() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd018,0,12,__ERR) 377 #define wr_rxa_dfe_tap8(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd018,0xf000,12,wr_val) 378 #define rd_rxb_dfe_tap8() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd018,4,12,__ERR) 379 #define wr_rxb_dfe_tap8(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd018,0x0f00,8,wr_val) 380 #define rd_rxc_dfe_tap8() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd018,8,12,__ERR) 381 #define wr_rxc_dfe_tap8(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd018,0x00f0,4,wr_val) 382 #define rd_rxd_dfe_tap8() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd018,12,12,__ERR) 383 #define wr_rxd_dfe_tap8(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd018,0x000f,0,wr_val) 384 #define rd_rxa_dfe_tap9() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd019,0,12,__ERR) 385 #define wr_rxa_dfe_tap9(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd019,0xf000,12,wr_val) 386 #define rd_rxb_dfe_tap9() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd019,4,12,__ERR) 387 #define wr_rxb_dfe_tap9(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd019,0x0f00,8,wr_val) 388 #define rd_rxc_dfe_tap9() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd019,8,12,__ERR) 389 #define wr_rxc_dfe_tap9(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd019,0x00f0,4,wr_val) 390 #define rd_rxd_dfe_tap9() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd019,12,12,__ERR) 391 #define wr_rxd_dfe_tap9(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd019,0x000f,0,wr_val) 392 #define rd_rxc_slicer_offset_adj_cal_d5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01a,2,10,__ERR) 393 #define wr_rxc_slicer_offset_adj_cal_d5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01a,0x3f00,8,wr_val) 394 #define rd_rxc_slicer_offset_adj_cal_d4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01a,10,10,__ERR) 395 #define wr_rxc_slicer_offset_adj_cal_d4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01a,0x003f,0,wr_val) 396 #define rd_rxc_slicer_offset_adj_cal_d3() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01b,2,10,__ERR) 397 #define wr_rxc_slicer_offset_adj_cal_d3(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01b,0x3f00,8,wr_val) 398 #define rd_rxc_slicer_offset_adj_cal_d2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01b,10,10,__ERR) 399 #define wr_rxc_slicer_offset_adj_cal_d2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01b,0x003f,0,wr_val) 400 #define rd_rxc_slicer_offset_adj_cal_d1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01c,2,10,__ERR) 401 #define wr_rxc_slicer_offset_adj_cal_d1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01c,0x3f00,8,wr_val) 402 #define rd_rxc_slicer_offset_adj_cal_d0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01c,10,10,__ERR) 403 #define wr_rxc_slicer_offset_adj_cal_d0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01c,0x003f,0,wr_val) 404 #define rd_rxc_slicer_offset_adj_cal_p2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01d,2,10,__ERR) 405 #define wr_rxc_slicer_offset_adj_cal_p2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01d,0x3f00,8,wr_val) 406 #define rd_rxc_slicer_offset_adj_cal_p1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01d,10,10,__ERR) 407 #define wr_rxc_slicer_offset_adj_cal_p1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01d,0x003f,0,wr_val) 408 #define rd_rxc_slicer_offset_adj_cal_p0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01e,2,10,__ERR) 409 #define wr_rxc_slicer_offset_adj_cal_p0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01e,0x3f00,8,wr_val) 410 #define rd_rxc_slicer_offset_adj_cal_lms() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd01e,10,10,__ERR) 411 #define wr_rxc_slicer_offset_adj_cal_lms(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd01e,0x003f,0,wr_val) 412 #define rd_rxa_dfe_tap10() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd020,0,12,__ERR) 413 #define wr_rxa_dfe_tap10(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd020,0xf000,12,wr_val) 414 #define rd_rxb_dfe_tap10() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd020,4,12,__ERR) 415 #define wr_rxb_dfe_tap10(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd020,0x0f00,8,wr_val) 416 #define rd_rxc_dfe_tap10() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd020,8,12,__ERR) 417 #define wr_rxc_dfe_tap10(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd020,0x00f0,4,wr_val) 418 #define rd_rxd_dfe_tap10() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd020,12,12,__ERR) 419 #define wr_rxd_dfe_tap10(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd020,0x000f,0,wr_val) 420 #define rd_rxa_dfe_tap11() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd021,0,12,__ERR) 421 #define wr_rxa_dfe_tap11(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd021,0xf000,12,wr_val) 422 #define rd_rxb_dfe_tap11() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd021,4,12,__ERR) 423 #define wr_rxb_dfe_tap11(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd021,0x0f00,8,wr_val) 424 #define rd_rxc_dfe_tap11() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd021,8,12,__ERR) 425 #define wr_rxc_dfe_tap11(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd021,0x00f0,4,wr_val) 426 #define rd_rxd_dfe_tap11() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd021,12,12,__ERR) 427 #define wr_rxd_dfe_tap11(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd021,0x000f,0,wr_val) 428 #define rd_rxa_dfe_tap12() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd022,0,12,__ERR) 429 #define wr_rxa_dfe_tap12(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd022,0xf000,12,wr_val) 430 #define rd_rxb_dfe_tap12() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd022,4,12,__ERR) 431 #define wr_rxb_dfe_tap12(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd022,0x0f00,8,wr_val) 432 #define rd_rxc_dfe_tap12() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd022,8,12,__ERR) 433 #define wr_rxc_dfe_tap12(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd022,0x00f0,4,wr_val) 434 #define rd_rxd_dfe_tap12() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd022,12,12,__ERR) 435 #define wr_rxd_dfe_tap12(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd022,0x000f,0,wr_val) 436 #define rd_rxa_dfe_tap13() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd023,0,12,__ERR) 437 #define wr_rxa_dfe_tap13(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd023,0xf000,12,wr_val) 438 #define rd_rxb_dfe_tap13() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd023,4,12,__ERR) 439 #define wr_rxb_dfe_tap13(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd023,0x0f00,8,wr_val) 440 #define rd_rxc_dfe_tap13() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd023,8,12,__ERR) 441 #define wr_rxc_dfe_tap13(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd023,0x00f0,4,wr_val) 442 #define rd_rxd_dfe_tap13() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd023,12,12,__ERR) 443 #define wr_rxd_dfe_tap13(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd023,0x000f,0,wr_val) 444 #define rd_rxa_dfe_tap14() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd024,0,12,__ERR) 445 #define wr_rxa_dfe_tap14(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd024,0xf000,12,wr_val) 446 #define rd_rxb_dfe_tap14() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd024,4,12,__ERR) 447 #define wr_rxb_dfe_tap14(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd024,0x0f00,8,wr_val) 448 #define rd_rxc_dfe_tap14() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd024,8,12,__ERR) 449 #define wr_rxc_dfe_tap14(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd024,0x00f0,4,wr_val) 450 #define rd_rxd_dfe_tap14() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd024,12,12,__ERR) 451 #define wr_rxd_dfe_tap14(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd024,0x000f,0,wr_val) 452 #define rd_rxa_dfe_tap7_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,0,14,__ERR) 453 #define wr_rxa_dfe_tap7_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0xc000,14,wr_val) 454 #define rd_rxa_dfe_tap8_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,2,14,__ERR) 455 #define wr_rxa_dfe_tap8_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x3000,12,wr_val) 456 #define rd_rxb_dfe_tap7_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,4,14,__ERR) 457 #define wr_rxb_dfe_tap7_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x0c00,10,wr_val) 458 #define rd_rxb_dfe_tap8_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,6,14,__ERR) 459 #define wr_rxb_dfe_tap8_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x0300,8,wr_val) 460 #define rd_rxc_dfe_tap7_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,8,14,__ERR) 461 #define wr_rxc_dfe_tap7_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x00c0,6,wr_val) 462 #define rd_rxc_dfe_tap8_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,10,14,__ERR) 463 #define wr_rxc_dfe_tap8_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x0030,4,wr_val) 464 #define rd_rxd_dfe_tap7_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,12,14,__ERR) 465 #define wr_rxd_dfe_tap7_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x000c,2,wr_val) 466 #define rd_rxd_dfe_tap8_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd025,14,14,__ERR) 467 #define wr_rxd_dfe_tap8_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd025,0x0003,0,wr_val) 468 #define rd_rxa_dfe_tap9_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,0,14,__ERR) 469 #define wr_rxa_dfe_tap9_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0xc000,14,wr_val) 470 #define rd_rxa_dfe_tap10_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,2,14,__ERR) 471 #define wr_rxa_dfe_tap10_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x3000,12,wr_val) 472 #define rd_rxb_dfe_tap9_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,4,14,__ERR) 473 #define wr_rxb_dfe_tap9_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x0c00,10,wr_val) 474 #define rd_rxb_dfe_tap10_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,6,14,__ERR) 475 #define wr_rxb_dfe_tap10_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x0300,8,wr_val) 476 #define rd_rxc_dfe_tap9_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,8,14,__ERR) 477 #define wr_rxc_dfe_tap9_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x00c0,6,wr_val) 478 #define rd_rxc_dfe_tap10_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,10,14,__ERR) 479 #define wr_rxc_dfe_tap10_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x0030,4,wr_val) 480 #define rd_rxd_dfe_tap9_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,12,14,__ERR) 481 #define wr_rxd_dfe_tap9_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x000c,2,wr_val) 482 #define rd_rxd_dfe_tap10_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd026,14,14,__ERR) 483 #define wr_rxd_dfe_tap10_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd026,0x0003,0,wr_val) 484 #define rd_rxa_dfe_tap11_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,0,14,__ERR) 485 #define wr_rxa_dfe_tap11_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0xc000,14,wr_val) 486 #define rd_rxa_dfe_tap12_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,2,14,__ERR) 487 #define wr_rxa_dfe_tap12_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x3000,12,wr_val) 488 #define rd_rxb_dfe_tap11_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,4,14,__ERR) 489 #define wr_rxb_dfe_tap11_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x0c00,10,wr_val) 490 #define rd_rxb_dfe_tap12_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,6,14,__ERR) 491 #define wr_rxb_dfe_tap12_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x0300,8,wr_val) 492 #define rd_rxc_dfe_tap11_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,8,14,__ERR) 493 #define wr_rxc_dfe_tap11_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x00c0,6,wr_val) 494 #define rd_rxc_dfe_tap12_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,10,14,__ERR) 495 #define wr_rxc_dfe_tap12_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x0030,4,wr_val) 496 #define rd_rxd_dfe_tap11_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,12,14,__ERR) 497 #define wr_rxd_dfe_tap11_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x000c,2,wr_val) 498 #define rd_rxd_dfe_tap12_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd027,14,14,__ERR) 499 #define wr_rxd_dfe_tap12_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd027,0x0003,0,wr_val) 500 #define rd_rxa_dfe_tap13_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,0,14,__ERR) 501 #define wr_rxa_dfe_tap13_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0xc000,14,wr_val) 502 #define rd_rxa_dfe_tap14_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,2,14,__ERR) 503 #define wr_rxa_dfe_tap14_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x3000,12,wr_val) 504 #define rd_rxb_dfe_tap13_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,4,14,__ERR) 505 #define wr_rxb_dfe_tap13_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x0c00,10,wr_val) 506 #define rd_rxb_dfe_tap14_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,6,14,__ERR) 507 #define wr_rxb_dfe_tap14_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x0300,8,wr_val) 508 #define rd_rxc_dfe_tap13_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,8,14,__ERR) 509 #define wr_rxc_dfe_tap13_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x00c0,6,wr_val) 510 #define rd_rxc_dfe_tap14_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,10,14,__ERR) 511 #define wr_rxc_dfe_tap14_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x0030,4,wr_val) 512 #define rd_rxd_dfe_tap13_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,12,14,__ERR) 513 #define wr_rxd_dfe_tap13_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x000c,2,wr_val) 514 #define rd_rxd_dfe_tap14_mux() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd028,14,14,__ERR) 515 #define wr_rxd_dfe_tap14_mux(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd028,0x0003,0,wr_val) 516 #define rd_rxd_slicer_offset_adj_cal_d5() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02a,2,10,__ERR) 517 #define wr_rxd_slicer_offset_adj_cal_d5(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02a,0x3f00,8,wr_val) 518 #define rd_rxd_slicer_offset_adj_cal_d4() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02a,10,10,__ERR) 519 #define wr_rxd_slicer_offset_adj_cal_d4(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02a,0x003f,0,wr_val) 520 #define rd_rxd_slicer_offset_adj_cal_d3() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02b,2,10,__ERR) 521 #define wr_rxd_slicer_offset_adj_cal_d3(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02b,0x3f00,8,wr_val) 522 #define rd_rxd_slicer_offset_adj_cal_d2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02b,10,10,__ERR) 523 #define wr_rxd_slicer_offset_adj_cal_d2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02b,0x003f,0,wr_val) 524 #define rd_rxd_slicer_offset_adj_cal_d1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02c,2,10,__ERR) 525 #define wr_rxd_slicer_offset_adj_cal_d1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02c,0x3f00,8,wr_val) 526 #define rd_rxd_slicer_offset_adj_cal_d0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02c,10,10,__ERR) 527 #define wr_rxd_slicer_offset_adj_cal_d0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02c,0x003f,0,wr_val) 528 #define rd_rxd_slicer_offset_adj_cal_p2() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02d,2,10,__ERR) 529 #define wr_rxd_slicer_offset_adj_cal_p2(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02d,0x3f00,8,wr_val) 530 #define rd_rxd_slicer_offset_adj_cal_p1() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02d,10,10,__ERR) 531 #define wr_rxd_slicer_offset_adj_cal_p1(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02d,0x003f,0,wr_val) 532 #define rd_rxd_slicer_offset_adj_cal_p0() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02e,2,10,__ERR) 533 #define wr_rxd_slicer_offset_adj_cal_p0(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02e,0x3f00,8,wr_val) 534 #define rd_rxd_slicer_offset_adj_cal_lms() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd02e,10,10,__ERR) 535 #define wr_rxd_slicer_offset_adj_cal_lms(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd02e,0x003f,0,wr_val) 536 #define rd_dc_offset_bin() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04c,8,8,__ERR) 537 #define rd_rx_vga_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04d,1,9,__ERR) 538 #define rd_rx_data23_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04d,8,8,__ERR) 539 #define rd_rx_data14_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04b,0,8,__ERR) 540 #define rd_rx_data05_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04b,8,8,__ERR) 541 #define rd_rx_phase1_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04a,0,8,__ERR) 542 #define rd_rx_phase02_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd04a,8,8,__ERR) 543 #define rd_rx_pi_disp_msb_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd053,2,15,__ERR) 544 #define wr_rx_pi_disp_msb_status(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd053,0x2000,13,wr_val) 545 #define rd_tx_pi_loop_timing_src_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd052,9,15,__ERR) 546 #define wr_tx_pi_loop_timing_src_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd052,0x0040,6,wr_val) 547 #define rd_rx_pam4_er_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd050,0,15,__ERR) 548 #define wr_rx_pam4_er_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd050,0x8000,15,wr_val) 549 #define rd_rx_nrz_vsr_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd050,1,15,__ERR) 550 #define wr_rx_nrz_vsr_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd050,0x4000,14,wr_val) 551 #define rd_cdr_integ_reg_clr() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd050,10,15,__ERR) 552 #define wr_cdr_integ_reg_clr(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd050,0x0020,5,wr_val) 553 #define rd_br_pd_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd050,13,15,__ERR) 554 #define wr_br_pd_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd050,0x0004,2,wr_val) 555 #define rd_os_pattern_enhanced() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd050,14,15,__ERR) 556 #define wr_os_pattern_enhanced(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd050,0x0002,1,wr_val) 557 #define rd_os_all_edges() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd050,15,15,__ERR) 558 #define wr_os_all_edges(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd050,0x0001,0,wr_val) 559 #define rd_rx_afe_override_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd05b,0,15,__ERR) 560 #define wr_rx_afe_override_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd05b,0x8000,15,wr_val) 561 #define rd_rx_afe_override_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd05b,1,8,__ERR) 562 #define wr_rx_afe_override_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd05b,0x7f80,7,wr_val) 563 #define rd_rx_afe_override_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd05b,12,12,__ERR) 564 #define wr_rx_afe_override_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd05b,0x000f,0,wr_val) 565 #define rd_rx_dsc_lock_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd061,15,15,__ERR) 566 #define wr_rx_dsc_lock_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd061,0x0001,0,wr_val) 567 #define rd_rx_dsc_lock_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd061,14,15,__ERR) 568 #define wr_rx_dsc_lock_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd061,0x0002,1,wr_val) 569 #define rd_freq_upd_en_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd061,7,15,__ERR) 570 #define wr_freq_upd_en_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd061,0x0100,8,wr_val) 571 #define rd_freq_upd_en_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd061,6,15,__ERR) 572 #define wr_freq_upd_en_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd061,0x0200,9,wr_val) 573 #define rd_rx_restart_pmd() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd069,15,15,__ERR) 574 #define wr_rx_restart_pmd(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd069,0x0001,0,wr_val) 575 #define rd_rx_restart_pmd_hold() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd069,14,15,__ERR) 576 #define wr_rx_restart_pmd_hold(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd069,0x0002,1,wr_val) 577 #define rd_dsc_state_one_hot() _blackhawk_tsc_pmd_rde_field(sa__, 0xd06b,6,6,__ERR) 578 #define rd_dsc_state() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd06e,0,11,__ERR) 579 #define rd_dsc_sm_scratch() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd06e,5,13,__ERR) 580 #define rd_dsc_sm_gp_uc_req() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd06e,9,10,__ERR) 581 #define rd_dsc_sm_ready_for_cmd() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd06e,15,15,__ERR) 582 #define rd_rx_pi_cnt_bin_pq() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd076,0,8,__ERR) 583 #define rd_rx_pi_cnt_bin_p() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd076,8,8,__ERR) 584 #define rd_rx_pi_cnt_bin_lq() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd077,0,8,__ERR) 585 #define rd_rx_pi_cnt_bin_l() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd077,8,8,__ERR) 586 #define rd_rx_pi_cnt_bin_dq() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd075,0,8,__ERR) 587 #define rd_rx_pi_cnt_bin_d() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd075,8,8,__ERR) 588 #define rd_rx_pi_cnt_bin_d_ld() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd071,0,8,__ERR) 589 #define rd_rx_pi_cnt_bin_l_ld() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd071,8,8,__ERR) 590 #define rd_rx_pi_cnt_bin_d_pd() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd070,0,8,__ERR) 591 #define rd_rx_pi_cnt_bin_p_pd() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd070,8,8,__ERR) 592 #define rd_cdr_integ_reg() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd078,0,0,__ERR) 593 #define rd_rx_pi_cnt_bin_d_perr() _blackhawk_tsc_pmd_rde_field(sa__, 0xd07a,0,7,__ERR) 594 #define rd_rxa_dfe_tap2_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07b,1,11,__ERR) 595 #define rd_rxb_dfe_tap2_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07b,6,11,__ERR) 596 #define rd_rxc_dfe_tap2_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07b,11,11,__ERR) 597 #define rd_rxd_dfe_tap2_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07c,1,11,__ERR) 598 #define rd_rxa_dfe_tap3_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07c,6,11,__ERR) 599 #define rd_rxb_dfe_tap3_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07c,11,11,__ERR) 600 #define rd_rxc_dfe_tap3_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07d,6,11,__ERR) 601 #define rd_rxd_dfe_tap3_status() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd07d,11,11,__ERR) 602 #define rd_lms_thresh_bin() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd0f8,6,6,__ERR) 603 #define rd_afe_lms_thresh_bin() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd0f9,8,8,__ERR) 604 #define rd_rxa_dfe_tap2_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd414,0,15,__ERR) 605 #define wr_rxa_dfe_tap2_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd414,0x8000,15,wr_val) 606 #define rd_rxa_dfe_tap2_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd414,1,11,__ERR) 607 #define wr_rxa_dfe_tap2_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd414,0x7c00,10,wr_val) 608 #define rd_rxb_dfe_tap2_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd414,6,11,__ERR) 609 #define wr_rxb_dfe_tap2_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd414,0x03e0,5,wr_val) 610 #define rd_rxc_dfe_tap2_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd414,11,11,__ERR) 611 #define wr_rxc_dfe_tap2_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd414,0x001f,0,wr_val) 612 #define rd_rxd_dfe_tap2_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd415,0,15,__ERR) 613 #define wr_rxd_dfe_tap2_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd415,0x8000,15,wr_val) 614 #define rd_rxd_dfe_tap2_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd415,1,11,__ERR) 615 #define wr_rxd_dfe_tap2_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd415,0x7c00,10,wr_val) 616 #define rd_rxa_dfe_tap3_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd415,6,11,__ERR) 617 #define wr_rxa_dfe_tap3_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd415,0x03e0,5,wr_val) 618 #define rd_rxb_dfe_tap3_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd415,11,11,__ERR) 619 #define wr_rxb_dfe_tap3_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd415,0x001f,0,wr_val) 620 #define rd_rxb_dfe_tap2_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd416,0,15,__ERR) 621 #define wr_rxb_dfe_tap2_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x8000,15,wr_val) 622 #define rd_rxc_dfe_tap2_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd416,1,15,__ERR) 623 #define wr_rxc_dfe_tap2_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x4000,14,wr_val) 624 #define rd_rxa_dfe_tap3_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd416,2,15,__ERR) 625 #define wr_rxa_dfe_tap3_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x2000,13,wr_val) 626 #define rd_rxb_dfe_tap3_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd416,3,15,__ERR) 627 #define wr_rxb_dfe_tap3_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x1000,12,wr_val) 628 #define rd_rxc_dfe_tap3_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd416,4,15,__ERR) 629 #define wr_rxc_dfe_tap3_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x0800,11,wr_val) 630 #define rd_rxd_dfe_tap3_write() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd416,5,15,__ERR) 631 #define wr_rxd_dfe_tap3_write(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x0400,10,wr_val) 632 #define rd_rxc_dfe_tap3_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd416,6,11,__ERR) 633 #define wr_rxc_dfe_tap3_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x03e0,5,wr_val) 634 #define rd_rxd_dfe_tap3_val() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd416,11,11,__ERR) 635 #define wr_rxd_dfe_tap3_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd416,0x001f,0,wr_val) 636 #define rd_rx_pf_ctrl_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd42e,1,11,__ERR) 637 #define wr_rx_pf_ctrl_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd42e,0x7c00,10,wr_val) 638 #define rd_rx_pf2_ctrl_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd42e,6,13,__ERR) 639 #define wr_rx_pf2_ctrl_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd42e,0x0380,7,wr_val) 640 #define rd_rx_vga_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd42e,9,9,__ERR) 641 #define wr_rx_vga_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd42e,0x007f,0,wr_val) 642 #define rd_dbg_fdbk_idx() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd400,0,14,__ERR) 643 #define wr_dbg_fdbk_idx(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd400,0xc000,14,wr_val) 644 #define rd_dbg_fdbk_idx_monitor_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd400,2,15,__ERR) 645 #define wr_dbg_fdbk_idx_monitor_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd400,0x2000,13,wr_val) 646 #define rd_frc_index_diffprec() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd400,3,15,__ERR) 647 #define wr_frc_index_diffprec(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd400,0x1000,12,wr_val) 648 #define rd_dbg_fdbk_data_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd401,8,15,__ERR) 649 #define wr_dbg_fdbk_data_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd401,0x0080,7,wr_val) 650 #define rd_dbg_fdbk_data_threshold() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd401,9,13,__ERR) 651 #define wr_dbg_fdbk_data_threshold(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd401,0x0070,4,wr_val) 652 #define rd_fdbk_counting_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd401,13,15,__ERR) 653 #define wr_fdbk_counting_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd401,0x0004,2,wr_val) 654 #define rd_dbg_fdbk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd401,15,15,__ERR) 655 #define wr_dbg_fdbk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd401,0x0001,0,wr_val) 656 #define rd_inlv_idx() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd402,8,8,__ERR) 657 #define wr_inlv_idx(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd402,0x00ff,0,wr_val) 658 #define rd_dbg_fdbk_counter_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd403,__ERR) 659 #define rd_dbg_fdbk_counter_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd404,__ERR) 660 #define rd_dbg_fdbk_counter_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd405,__ERR) 661 #define rd_dbg_fdbk_counter_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd406,__ERR) 662 #define rd_dbg_fdbk_counter_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd407,__ERR) 663 #define rd_dbg_fdbk_counter_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd408,__ERR) 664 #define rd_dbg_fdbk_idx_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd40a,7,15,__ERR) 665 #define rd_linktrn_ieee_lp_coeff_update() _blackhawk_tsc_pmd_rde_reg(sa__, 0x0098,__ERR) 666 #define rd_linktrn_ieee_lp_status_report() _blackhawk_tsc_pmd_rde_reg(sa__, 0x0099,__ERR) 667 #define rd_linktrn_ieee_training_enable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0x0096,14,15,__ERR) 668 #define wr_linktrn_ieee_training_enable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0x0096,0x0002,1,wr_val) 669 #define rd_linktrn_ieee_restart_training() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0x0096,15,15,__ERR) 670 #define wr_linktrn_ieee_restart_training(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0x0096,0x0001,0,wr_val) 671 #define rd_linktrn_ieee_training_failure() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0x0097,12,15,__ERR) 672 #define rd_linktrn_ieee_training_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0x0097,13,15,__ERR) 673 #define rd_linktrn_ieee_frame_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0x0097,14,15,__ERR) 674 #define rd_linktrn_ieee_receiver_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0x0097,15,15,__ERR) 675 #define rd_linktrn_ieee_ld_coeff_update() _blackhawk_tsc_pmd_rde_reg(sa__, 0x009a,__ERR) 676 #define rd_linktrn_ieee_ld_status_report() _blackhawk_tsc_pmd_rde_reg(sa__, 0x009b,__ERR) 677 #define rd_linktrn_sm_current_state() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd096,1,13,__ERR) 678 #define rd_linktrn_xmt_status_report_parity() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd096,10,15,__ERR) 679 #define rd_linktrn_xmt_coeff_update_parity() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd096,11,15,__ERR) 680 #define rd_linktrn_training_fsm_signal_detect() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd096,14,15,__ERR) 681 #define rd_linktrn_local_rx_ready() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd096,15,15,__ERR) 682 #define rdc_mdio_drv_comclk() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdc,0,15,__ERR) 683 #define wrc_mdio_drv_comclk(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdc,0x8000,15,wr_val) 684 #define rdc_mdio_brcst_port_addr() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdc,11,11,__ERR) 685 #define wrc_mdio_brcst_port_addr(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdc,0x001f,0,wr_val) 686 #define rdc_mdio_multi_prts_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,0,15,__ERR) 687 #define wrc_mdio_multi_prts_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x8000,15,wr_val) 688 #define rdc_mdio_multi_mmds_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,1,15,__ERR) 689 #define wrc_mdio_multi_mmds_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x4000,14,wr_val) 690 #define rdc_mdio_dev_pcs_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,9,15,__ERR) 691 #define wrc_mdio_dev_pcs_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x0040,6,wr_val) 692 #define rdc_mdio_dev_dte_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,10,15,__ERR) 693 #define wrc_mdio_dev_dte_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x0020,5,wr_val) 694 #define rdc_mdio_dev_phy_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,11,15,__ERR) 695 #define wrc_mdio_dev_phy_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x0010,4,wr_val) 696 #define rdc_mdio_dev_an_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,12,15,__ERR) 697 #define wrc_mdio_dev_an_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x0008,3,wr_val) 698 #define rdc_mdio_dev_pmd_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,13,15,__ERR) 699 #define wrc_mdio_dev_pmd_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x0004,2,wr_val) 700 #define rdc_mdio_dev_id0_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xffdd,15,15,__ERR) 701 #define wrc_mdio_dev_id0_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xffdd,0x0001,0,wr_val) 702 #define rdc_mdio_aer() _blackhawk_tsc_pmd_rde_field(sa__, 0xffde,5,5,__ERR) 703 #define wrc_mdio_aer(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xffde,0x07ff,0,wr_val) 704 #define rdc_micro_master_clk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd200,15,15,__ERR) 705 #define wrc_micro_master_clk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd200,0x0001,0,wr_val) 706 #define rdc_micro_pram_if_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd201,0,15,__ERR) 707 #define wrc_micro_pram_if_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd201,0x8000,15,wr_val) 708 #define rdc_micro_sw_timestamp_timer_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd201,1,15,__ERR) 709 #define wrc_micro_sw_timestamp_timer_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd201,0x4000,14,wr_val) 710 #define rdc_micro_master_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd201,15,15,__ERR) 711 #define wrc_micro_master_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd201,0x0001,0,wr_val) 712 #define rdc_micro_autoinc_rdaddr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd202,2,15,__ERR) 713 #define wrc_micro_autoinc_rdaddr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd202,0x2000,13,wr_val) 714 #define rdc_micro_autoinc_wraddr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd202,3,15,__ERR) 715 #define wrc_micro_autoinc_wraddr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd202,0x1000,12,wr_val) 716 #define rdc_micro_ra_init() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd202,6,14,__ERR) 717 #define wrc_micro_ra_init(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd202,0x0300,8,wr_val) 718 #define rdc_micro_ra_rddatasize() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd202,10,14,__ERR) 719 #define wrc_micro_ra_rddatasize(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd202,0x0030,4,wr_val) 720 #define rdc_micro_ra_wrdatasize() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd202,14,14,__ERR) 721 #define wrc_micro_ra_wrdatasize(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd202,0x0003,0,wr_val) 722 #define rdc_micro_ra_initdone() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd203,15,15,__ERR) 723 #define rdc_micro_ra_wraddr_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd204,__ERR) 724 #define wrc_micro_ra_wraddr_lsw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd204,wr_val) 725 #define rdc_micro_ra_wraddr_msw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd205,__ERR) 726 #define wrc_micro_ra_wraddr_msw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd205,wr_val) 727 #define rdc_micro_ra_wrdata_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd206,__ERR) 728 #define wrc_micro_ra_wrdata_lsw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd206,wr_val) 729 #define rdc_micro_ra_wrdata_msw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd207,__ERR) 730 #define wrc_micro_ra_wrdata_msw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd207,wr_val) 731 #define rdc_micro_ra_rdaddr_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd208,__ERR) 732 #define wrc_micro_ra_rdaddr_lsw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd208,wr_val) 733 #define rdc_micro_ra_rdaddr_msw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd209,__ERR) 734 #define wrc_micro_ra_rdaddr_msw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd209,wr_val) 735 #define rdc_micro_ra_rddata_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20a,__ERR) 736 #define rdc_micro_ra_rddata_msw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20b,__ERR) 737 #define rdc_micro_pramif_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd20c,15,15,__ERR) 738 #define wrc_micro_pramif_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd20c,0x0001,0,wr_val) 739 #define rdc_micro_pramif_ahb_wraddr_lsw() _blackhawk_tsc_pmd_rde_field(sa__, 0xd20d,0,2,__ERR) 740 #define wrc_micro_pramif_ahb_wraddr_lsw(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd20d,0xfffc,2,wr_val) 741 #define rdc_micro_pramif_ahb_wraddr_msw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20e,__ERR) 742 #define wrc_micro_pramif_ahb_wraddr_msw(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd20e,wr_val) 743 #define rdc_micro_pvt_tempdata_rmi() _blackhawk_tsc_pmd_rde_field(sa__, 0xd210,6,6,__ERR) 744 #define rdc_micro_ra_arg_microblk_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd211,9,13,__ERR) 745 #define wrc_micro_ra_arg_microblk_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd211,0x0070,4,wr_val) 746 #define rdc_micro_pmi_hp_ack_timeout_dis() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd211,15,15,__ERR) 747 #define wrc_micro_pmi_hp_ack_timeout_dis(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd211,0x0001,0,wr_val) 748 #define rdc_micro_pr_default_slave_error() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd212,14,15,__ERR) 749 #define rdc_micro_rmi_default_slave_error() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd212,15,15,__ERR) 750 #define rdc_micro_ra_autoinc_nxt_wraddr_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd213,__ERR) 751 #define rdc_micro_ra_autoinc_nxt_rdaddr_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd214,__ERR) 752 #define rdc_micro_pr_autoinc_nxt_wraddr_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd215,__ERR) 753 #define rdc_micro_pr_autoinc_nxt_wraddr_msb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21d,11,15,__ERR) 754 #define rdc_micro_ra_autoinc_nxt_rdaddr_msb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21d,13,15,__ERR) 755 #define rdc_micro_ra_autoinc_nxt_wraddr_msb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21d,15,15,__ERR) 756 #define rdc_micro_pvt_tempdata_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd216,3,15,__ERR) 757 #define wrc_micro_pvt_tempdata_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd216,0x1000,12,wr_val) 758 #define rdc_micro_pvt_tempdata_frcval() _blackhawk_tsc_pmd_rde_field(sa__, 0xd216,6,6,__ERR) 759 #define wrc_micro_pvt_tempdata_frcval(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd216,0x03ff,0,wr_val) 760 #define rdc_micro_cr_crc_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd217,13,15,__ERR) 761 #define wrc_micro_cr_crc_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd217,0x0004,2,wr_val) 762 #define rdc_micro_cr_crc_init() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd217,14,15,__ERR) 763 #define wrc_micro_cr_crc_init(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd217,0x0002,1,wr_val) 764 #define rdc_micro_cr_crc_calc_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd217,15,15,__ERR) 765 #define wrc_micro_cr_crc_calc_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd217,0x0001,0,wr_val) 766 #define rdc_micro_cr_crc_checksum() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd218,__ERR) 767 #define rdc_micro_m0p_default_slave_error_hresp_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,4,15,__ERR) 768 #define wrc_micro_m0p_default_slave_error_hresp_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0800,11,wr_val) 769 #define rdc_micro_pmi_hp_ack_timeout_hresp_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,5,15,__ERR) 770 #define wrc_micro_pmi_hp_ack_timeout_hresp_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0400,10,wr_val) 771 #define rdc_micro_pmi_hp_word_access_err_hresp_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,6,15,__ERR) 772 #define wrc_micro_pmi_hp_word_access_err_hresp_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0200,9,wr_val) 773 #define rdc_micro_pmi_hp_error_hresp_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,7,15,__ERR) 774 #define wrc_micro_pmi_hp_error_hresp_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0100,8,wr_val) 775 #define rdc_micro_m0p_default_slave_error_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,12,15,__ERR) 776 #define wrc_micro_m0p_default_slave_error_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0008,3,wr_val) 777 #define rdc_micro_pmi_hp_ack_timeout_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,13,15,__ERR) 778 #define wrc_micro_pmi_hp_ack_timeout_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0004,2,wr_val) 779 #define rdc_micro_pmi_hp_word_access_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,14,15,__ERR) 780 #define wrc_micro_pmi_hp_word_access_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0002,1,wr_val) 781 #define rdc_micro_pmi_hp_error_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd219,15,15,__ERR) 782 #define wrc_micro_pmi_hp_error_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd219,0x0001,0,wr_val) 783 #define rdc_micro_num_uc_cores() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21a,0,12,__ERR) 784 #define rdc_micro_uc_active_3() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21a,12,15,__ERR) 785 #define rdc_micro_uc_active_2() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21a,13,15,__ERR) 786 #define rdc_micro_uc_active_1() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21a,14,15,__ERR) 787 #define rdc_micro_uc_active_0() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21a,15,15,__ERR) 788 #define rdc_micro_debugger_id_lsw() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd21b,__ERR) 789 #define rdc_micro_debugger_id_msw() _blackhawk_tsc_pmd_rde_field(sa__, 0xd21c,4,4,__ERR) 790 #define rdc_micro_debugger_id_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21e,0,15,__ERR) 791 #define wrc_micro_debugger_id_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd21e,0x8000,15,wr_val) 792 #define rdc_micro_debugger_id_frcval() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd21e,8,8,__ERR) 793 #define wrc_micro_debugger_id_frcval(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd21e,0x00ff,0,wr_val) 794 #define rdc_micro_dr_ecc_debug_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,3,15,__ERR) 795 #define wrc_micro_dr_ecc_debug_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x1000,12,wr_val) 796 #define rdc_micro_dr_ecc_corrupt() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,4,14,__ERR) 797 #define wrc_micro_dr_ecc_corrupt(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x0c00,10,wr_val) 798 #define rdc_micro_dr_ecc_frc_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,6,15,__ERR) 799 #define wrc_micro_dr_ecc_frc_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x0200,9,wr_val) 800 #define rdc_micro_dr_eccg_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,7,15,__ERR) 801 #define wrc_micro_dr_eccg_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x0100,8,wr_val) 802 #define rdc_micro_cr_ecc_debug_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,11,15,__ERR) 803 #define wrc_micro_cr_ecc_debug_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x0010,4,wr_val) 804 #define rdc_micro_cr_ecc_corrupt() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,12,14,__ERR) 805 #define wrc_micro_cr_ecc_corrupt(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x000c,2,wr_val) 806 #define rdc_micro_cr_ecc_frc_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,14,15,__ERR) 807 #define wrc_micro_cr_ecc_frc_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x0002,1,wr_val) 808 #define rdc_micro_cr_eccg_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd220,15,15,__ERR) 809 #define wrc_micro_cr_eccg_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd220,0x0001,0,wr_val) 810 #define rdc_micro_ra_ecc_wrdata() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd221,9,9,__ERR) 811 #define wrc_micro_ra_ecc_wrdata(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd221,0x007f,0,wr_val) 812 #define rdc_micro_rmi_cr_ecc_address_status() _blackhawk_tsc_pmd_rde_field(sa__, 0xd222,0,2,__ERR) 813 #define rdc_micro_rmi_cr_ecc_address_status_16() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd223,0,15,__ERR) 814 #define rdc_micro_ra_ecc_rddata() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd223,9,9,__ERR) 815 #define rdc_micro_rmi_dr_ecc_address_status() _blackhawk_tsc_pmd_rde_field(sa__, 0xd224,0,2,__ERR) 816 #define rdc_micro_cr_tm() _blackhawk_tsc_pmd_rde_field(sa__, 0xd225,7,7,__ERR) 817 #define wrc_micro_cr_tm(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd225,0x01ff,0,wr_val) 818 #define rdc_micro_dr_tm() _blackhawk_tsc_pmd_rde_field(sa__, 0xd226,7,7,__ERR) 819 #define wrc_micro_dr_tm(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd226,0x01ff,0,wr_val) 820 #define rdc_micro_dr_lowpower_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,0,15,__ERR) 821 #define wrc_micro_dr_lowpower_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x8000,15,wr_val) 822 #define rdc_micro_dr_prif_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,4,15,__ERR) 823 #define wrc_micro_dr_prif_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0800,11,wr_val) 824 #define rdc_micro_dr_raif_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,5,15,__ERR) 825 #define wrc_micro_dr_raif_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0400,10,wr_val) 826 #define rdc_micro_dr_ignore_micro_code_writes() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,6,15,__ERR) 827 #define wrc_micro_dr_ignore_micro_code_writes(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0200,9,wr_val) 828 #define rdc_micro_dr_access_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,7,15,__ERR) 829 #define wrc_micro_dr_access_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0100,8,wr_val) 830 #define rdc_micro_cr_lowpower_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,8,15,__ERR) 831 #define wrc_micro_cr_lowpower_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0080,7,wr_val) 832 #define rdc_micro_cr_prif_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,12,15,__ERR) 833 #define wrc_micro_cr_prif_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0008,3,wr_val) 834 #define rdc_micro_cr_raif_prtsel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,13,15,__ERR) 835 #define wrc_micro_cr_raif_prtsel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0004,2,wr_val) 836 #define rdc_micro_cr_ignore_micro_code_writes() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,14,15,__ERR) 837 #define wrc_micro_cr_ignore_micro_code_writes(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0002,1,wr_val) 838 #define rdc_micro_cr_access_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd227,15,15,__ERR) 839 #define wrc_micro_cr_access_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd227,0x0001,0,wr_val) 840 #define rdc_micro_dr_code_size() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd228,1,9,__ERR) 841 #define wrc_micro_dr_code_size(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd228,0x7f00,8,wr_val) 842 #define rdc_micro_cr_data_size() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd228,9,9,__ERR) 843 #define wrc_micro_cr_data_size(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd228,0x007f,0,wr_val) 844 #define rdc_micro_core_stack_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22e,0,15,__ERR) 845 #define wrc_micro_core_stack_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd22e,0x8000,15,wr_val) 846 #define rdc_micro_core_stack_size() _blackhawk_tsc_pmd_rde_field(sa__, 0xd22e,2,4,__ERR) 847 #define wrc_micro_core_stack_size(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd22e,0x3ffc,2,wr_val) 848 #define rdc_micro_rmi_mbox_msgout_status_or() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,5,15,__ERR) 849 #define rdc_micro_rmi_m0p_systemresetreq_status_or() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,6,15,__ERR) 850 #define rdc_micro_rmi_m0p_lockup_status_or() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,7,15,__ERR) 851 #define rdc_micro_rmi_dr_ecc_multirow_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,9,15,__ERR) 852 #define rdc_micro_rmi_dr_ecc_uncorr_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,10,15,__ERR) 853 #define rdc_micro_rmi_dr_ecc_corr_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,11,15,__ERR) 854 #define rdc_micro_rmi_cr_ecc_multirow_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,13,15,__ERR) 855 #define rdc_micro_rmi_cr_ecc_uncorr_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,14,15,__ERR) 856 #define rdc_micro_rmi_cr_ecc_corr_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22a,15,15,__ERR) 857 #define rdc_micro_rmi_mbox_msgout_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,5,15,__ERR) 858 #define wrc_micro_rmi_mbox_msgout_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0400,10,wr_val) 859 #define rdc_micro_rmi_m0p_systemresetreq_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,6,15,__ERR) 860 #define wrc_micro_rmi_m0p_systemresetreq_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0200,9,wr_val) 861 #define rdc_micro_rmi_m0p_lockup_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,7,15,__ERR) 862 #define wrc_micro_rmi_m0p_lockup_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0100,8,wr_val) 863 #define rdc_micro_rmi_dr_ecc_multirow_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,9,15,__ERR) 864 #define wrc_micro_rmi_dr_ecc_multirow_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0040,6,wr_val) 865 #define rdc_micro_rmi_dr_ecc_uncorr_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,10,15,__ERR) 866 #define wrc_micro_rmi_dr_ecc_uncorr_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0020,5,wr_val) 867 #define rdc_micro_rmi_dr_ecc_corr_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,11,15,__ERR) 868 #define wrc_micro_rmi_dr_ecc_corr_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0010,4,wr_val) 869 #define rdc_micro_rmi_cr_ecc_multirow_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,13,15,__ERR) 870 #define wrc_micro_rmi_cr_ecc_multirow_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0004,2,wr_val) 871 #define rdc_micro_rmi_cr_ecc_uncorr_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,14,15,__ERR) 872 #define wrc_micro_rmi_cr_ecc_uncorr_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0002,1,wr_val) 873 #define rdc_micro_rmi_cr_ecc_corr_err_intr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd229,15,15,__ERR) 874 #define wrc_micro_rmi_cr_ecc_corr_err_intr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd229,0x0001,0,wr_val) 875 #define rdc_micro_pmi_hp_fast_bktobk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22b,13,15,__ERR) 876 #define wrc_micro_pmi_hp_fast_bktobk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd22b,0x0004,2,wr_val) 877 #define rdc_micro_pmi_hp_fast_read_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22b,15,15,__ERR) 878 #define wrc_micro_pmi_hp_fast_read_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd22b,0x0001,0,wr_val) 879 #define rdc_micro_silicon_debug_status_mux_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd22c,13,13,__ERR) 880 #define wrc_micro_silicon_debug_status_mux_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd22c,0x0007,0,wr_val) 881 #define rdc_micro_silicon_debug_status_muxed_data() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd22d,__ERR) 882 #define rdc_micro_msg0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd230,__ERR) 883 #define wrc_micro_msg0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd230,wr_val) 884 #define rdc_micro_msg1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd231,__ERR) 885 #define wrc_micro_msg1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd231,wr_val) 886 #define rdc_micro_msg2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd232,__ERR) 887 #define wrc_micro_msg2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd232,wr_val) 888 #define rdc_micro_msg3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd233,__ERR) 889 #define wrc_micro_msg3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd233,wr_val) 890 #define rdc_micro_core_clk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd240,15,15,__ERR) 891 #define wrc_micro_core_clk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd240,0x0001,0,wr_val) 892 #define rdc_micro_sw_pmi_hp_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd241,0,15,__ERR) 893 #define wrc_micro_sw_pmi_hp_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd241,0x8000,15,wr_val) 894 #define rdc_micro_dap_poreset_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd241,1,15,__ERR) 895 #define wrc_micro_dap_poreset_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd241,0x4000,14,wr_val) 896 #define rdc_micro_core_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd241,15,15,__ERR) 897 #define wrc_micro_core_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd241,0x0001,0,wr_val) 898 #define rdc_micro_m0p_default_slave_error_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd242,12,15,__ERR) 899 #define rdc_micro_pmi_hp_ack_timeout_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd242,13,15,__ERR) 900 #define rdc_micro_pmi_hp_word_access_err_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd242,14,15,__ERR) 901 #define rdc_micro_pmi_hp_error_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd242,15,15,__ERR) 902 #define rdc_micro_core_ln_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd243,8,8,__ERR) 903 #define wrc_micro_core_ln_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd243,0x00ff,0,wr_val) 904 #define rdc_micro_mbox_msgin_intr() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd244,15,15,__ERR) 905 #define wrc_micro_mbox_msgin_intr(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd244,0x0001,0,wr_val) 906 #define rdc_micro_pmd_signal_detect_wakeup_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,9,15,__ERR) 907 #define wrc_micro_pmd_signal_detect_wakeup_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0040,6,wr_val) 908 #define rdc_micro_dp_rclk20_rst_wakeup_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,10,15,__ERR) 909 #define wrc_micro_dp_rclk20_rst_wakeup_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0020,5,wr_val) 910 #define rdc_micro_m0p_wakeup() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,11,15,__ERR) 911 #define wrc_micro_m0p_wakeup(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0010,4,wr_val) 912 #define rdc_micro_m0p_gclk_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,12,15,__ERR) 913 #define wrc_micro_m0p_gclk_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0008,3,wr_val) 914 #define rdc_micro_m0p_gclk_frcval() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,13,15,__ERR) 915 #define wrc_micro_m0p_gclk_frcval(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0004,2,wr_val) 916 #define rdc_micro_sleepholdreq_n() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,14,15,__ERR) 917 #define wrc_micro_sleepholdreq_n(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0002,1,wr_val) 918 #define rdc_micro_wicenreq() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd245,15,15,__ERR) 919 #define wrc_micro_wicenreq(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd245,0x0001,0,wr_val) 920 #define rdc_micro_sleepdeep_LH() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd246,10,15,__ERR) 921 #define rdc_micro_sleeping_LH() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd246,11,15,__ERR) 922 #define rdc_micro_sleepdeep() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd246,12,15,__ERR) 923 #define rdc_micro_sleeping() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd246,13,15,__ERR) 924 #define rdc_micro_sleepholdack_n() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd246,14,15,__ERR) 925 #define rdc_micro_wicenack() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd246,15,15,__ERR) 926 #define rdc_micro_rmi_mbox_msgout_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd247,13,15,__ERR) 927 #define rdc_micro_rmi_m0p_systemresetreq_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd247,14,15,__ERR) 928 #define rdc_micro_rmi_m0p_lockup_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd247,15,15,__ERR) 929 #define rdc_micro_pmd_signal_detect_status_LH() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd248,0,8,__ERR) 930 #define rdc_micro_dp_rclk20_rst_status_LH() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd248,8,8,__ERR) 931 #define rdc_micro_status_stack_overflowed() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd24d,8,15,__ERR) 932 #define wrc_micro_status_stack_overflowed(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd24d,0x0080,7,wr_val) 933 #define rdc_micro_status_stack_overflowed_laneID() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd24d,9,13,__ERR) 934 #define wrc_micro_status_stack_overflowed_laneID(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd24d,0x0070,4,wr_val) 935 #define rdc_micro_status_hw_exception_occurred() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd24d,12,15,__ERR) 936 #define wrc_micro_status_hw_exception_occurred(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd24d,0x0008,3,wr_val) 937 #define rdc_micro_status_hw_exception_complete() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd24d,13,15,__ERR) 938 #define wrc_micro_status_hw_exception_complete(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd24d,0x0004,2,wr_val) 939 #define rdc_micro_status_sw_exception_occurred() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd24d,14,15,__ERR) 940 #define wrc_micro_status_sw_exception_occurred(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd24d,0x0002,1,wr_val) 941 #define rdc_micro_status_sw_exception_complete() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd24d,15,15,__ERR) 942 #define wrc_micro_status_sw_exception_complete(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd24d,0x0001,0,wr_val) 943 #define rdc_micro_core_cfg_fwapi_data1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd24e,__ERR) 944 #define wrc_micro_core_cfg_fwapi_data1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd24e,wr_val) 945 #define rdc_patt_gen_seq_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd120,__ERR) 946 #define wrc_patt_gen_seq_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd120,wr_val) 947 #define rdc_patt_gen_seq_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd121,__ERR) 948 #define wrc_patt_gen_seq_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd121,wr_val) 949 #define rdc_patt_gen_seq_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd122,__ERR) 950 #define wrc_patt_gen_seq_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd122,wr_val) 951 #define rdc_patt_gen_seq_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd123,__ERR) 952 #define wrc_patt_gen_seq_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd123,wr_val) 953 #define rdc_patt_gen_seq_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd124,__ERR) 954 #define wrc_patt_gen_seq_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd124,wr_val) 955 #define rdc_patt_gen_seq_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd125,__ERR) 956 #define wrc_patt_gen_seq_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd125,wr_val) 957 #define rdc_patt_gen_seq_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd126,__ERR) 958 #define wrc_patt_gen_seq_6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd126,wr_val) 959 #define rdc_patt_gen_seq_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd127,__ERR) 960 #define wrc_patt_gen_seq_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd127,wr_val) 961 #define rdc_patt_gen_seq_8() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd128,__ERR) 962 #define wrc_patt_gen_seq_8(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd128,wr_val) 963 #define rdc_patt_gen_seq_9() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd129,__ERR) 964 #define wrc_patt_gen_seq_9(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd129,wr_val) 965 #define rdc_patt_gen_seq_10() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12a,__ERR) 966 #define wrc_patt_gen_seq_10(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12a,wr_val) 967 #define rdc_patt_gen_seq_11() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12b,__ERR) 968 #define wrc_patt_gen_seq_11(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12b,wr_val) 969 #define rdc_patt_gen_seq_12() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12c,__ERR) 970 #define wrc_patt_gen_seq_12(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12c,wr_val) 971 #define rdc_patt_gen_seq_13() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12d,__ERR) 972 #define wrc_patt_gen_seq_13(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12d,wr_val) 973 #define rdc_patt_gen_seq_14() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12e,__ERR) 974 #define wrc_patt_gen_seq_14(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12e,wr_val) 975 #define rdc_vco_step_time() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd140,8,8,__ERR) 976 #define wrc_vco_step_time(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd140,0x00ff,0,wr_val) 977 #define rdc_refclk_divcnt() _blackhawk_tsc_pmd_rde_field(sa__, 0xd145,2,2,__ERR) 978 #define wrc_refclk_divcnt(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd145,0x3fff,0,wr_val) 979 #define rdc_rescal_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd147,5,15,__ERR) 980 #define wrc_rescal_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd147,0x0400,10,wr_val) 981 #define rdc_rescal_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd147,6,12,__ERR) 982 #define wrc_rescal_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd147,0x03c0,6,wr_val) 983 #define rdc_pll_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd147,11,11,__ERR) 984 #define wrc_pll_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd147,0x001f,0,wr_val) 985 #define rdc_lost_pll_lock_sm() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,0,15,__ERR) 986 #define rdc_cap_done() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,1,15,__ERR) 987 #define rdc_cap_pass() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,2,15,__ERR) 988 #define rdc_freq_done_sm() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,3,15,__ERR) 989 #define rdc_freq_pass_sm() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,4,15,__ERR) 990 #define rdc_pll_seq_done() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,5,15,__ERR) 991 #define rdc_pll_seq_pass() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,6,15,__ERR) 992 #define rdc_pll_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,7,15,__ERR) 993 #define rdc_cap_done_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,9,15,__ERR) 994 #define rdc_cap_pass_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,10,15,__ERR) 995 #define rdc_freq_done_sm_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,11,15,__ERR) 996 #define rdc_freq_pass_sm_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,12,15,__ERR) 997 #define rdc_pll_seq_done_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,13,15,__ERR) 998 #define rdc_pll_seq_pass_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,14,15,__ERR) 999 #define rdc_pll_lock_lh_ll() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd148,15,15,__ERR) 1000 #define rd_afe_sigdet_pwrdn() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a1,14,15,__ERR) 1001 #define wr_afe_sigdet_pwrdn(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a1,0x0002,1,wr_val) 1002 #define rd_ln_rx_s_pwrdn() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a1,15,15,__ERR) 1003 #define wr_ln_rx_s_pwrdn(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a1,0x0001,0,wr_val) 1004 #define rd_pmd_rx_clk_vld_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a7,11,15,__ERR) 1005 #define wr_pmd_rx_clk_vld_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a7,0x0010,4,wr_val) 1006 #define rd_pmd_rx_clk_vld_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a7,12,15,__ERR) 1007 #define wr_pmd_rx_clk_vld_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a7,0x0008,3,wr_val) 1008 #define rd_ln_rx_s_comclk_frc_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a7,13,15,__ERR) 1009 #define wr_ln_rx_s_comclk_frc_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a7,0x0004,2,wr_val) 1010 #define rd_ln_rx_s_comclk_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a7,14,15,__ERR) 1011 #define wr_ln_rx_s_comclk_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a7,0x0002,1,wr_val) 1012 #define rd_ln_rx_s_clkgate_frc_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a7,15,15,__ERR) 1013 #define wr_ln_rx_s_clkgate_frc_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a7,0x0001,0,wr_val) 1014 #define rd_sigdet_dp_rstb_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a4,13,15,__ERR) 1015 #define wr_sigdet_dp_rstb_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a4,0x0004,2,wr_val) 1016 #define rd_ln_rx_dp_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a4,14,15,__ERR) 1017 #define wr_ln_rx_dp_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a4,0x0002,1,wr_val) 1018 #define rd_ln_rx_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a4,15,15,__ERR) 1019 #define wr_ln_rx_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a4,0x0001,0,wr_val) 1020 #define rd_afe_rx_rclk20_pwrdn_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a2,10,15,__ERR) 1021 #define wr_afe_rx_rclk20_pwrdn_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a2,0x0020,5,wr_val) 1022 #define rd_afe_rx_rclk20_pwrdn_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a2,11,15,__ERR) 1023 #define wr_afe_rx_rclk20_pwrdn_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a2,0x0010,4,wr_val) 1024 #define rd_afe_rx_reset_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a2,12,15,__ERR) 1025 #define wr_afe_rx_reset_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a2,0x0008,3,wr_val) 1026 #define rd_afe_rx_reset_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a2,13,15,__ERR) 1027 #define wr_afe_rx_reset_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a2,0x0004,2,wr_val) 1028 #define rd_afe_rx_pwrdn_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a2,14,15,__ERR) 1029 #define wr_afe_rx_pwrdn_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a2,0x0002,1,wr_val) 1030 #define rd_afe_rx_pwrdn_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a2,15,15,__ERR) 1031 #define wr_afe_rx_pwrdn_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a2,0x0001,0,wr_val) 1032 #define rd_pmd_ln_rx_h_pwrdn_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1a3,15,15,__ERR) 1033 #define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1a3,0x0001,0,wr_val) 1034 #define rd_pmd_rx_lane_mode() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a8,__ERR) 1035 #define rd_lane_uc_config_force_nrz_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,0,15,__ERR) 1036 #define wr_lane_uc_config_force_nrz_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x8000,15,wr_val) 1037 #define rd_lane_uc_config_force_pam4_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,1,15,__ERR) 1038 #define wr_lane_uc_config_force_pam4_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x4000,14,wr_val) 1039 #define rd_lane_uc_config_lp_has_prec_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,2,15,__ERR) 1040 #define wr_lane_uc_config_lp_has_prec_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x2000,13,wr_val) 1041 #define rd_lane_uc_config_force_ns() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,3,15,__ERR) 1042 #define wr_lane_uc_config_force_ns(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x1000,12,wr_val) 1043 #define rd_lane_uc_config_force_es() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,4,15,__ERR) 1044 #define wr_lane_uc_config_force_es(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0800,11,wr_val) 1045 #define rd_lane_uc_config_cl72_restart_timeout_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,5,15,__ERR) 1046 #define wr_lane_uc_config_cl72_restart_timeout_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0400,10,wr_val) 1047 #define rd_lane_uc_config_cl72_auto_polarity_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,6,15,__ERR) 1048 #define wr_lane_uc_config_cl72_auto_polarity_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0200,9,wr_val) 1049 #define rd_lane_uc_config_scrambling_dis() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,7,15,__ERR) 1050 #define wr_lane_uc_config_scrambling_dis(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0100,8,wr_val) 1051 #define rd_lane_uc_config_unreliable_los() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,8,15,__ERR) 1052 #define wr_lane_uc_config_unreliable_los(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0080,7,wr_val) 1053 #define rd_lane_uc_config_media_type() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,9,14,__ERR) 1054 #define wr_lane_uc_config_media_type(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0060,5,wr_val) 1055 #define rd_lane_uc_config_force_brdfe_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,11,15,__ERR) 1056 #define wr_lane_uc_config_force_brdfe_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0010,4,wr_val) 1057 #define rd_lane_uc_config_dfe_lp_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,12,15,__ERR) 1058 #define wr_lane_uc_config_dfe_lp_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0008,3,wr_val) 1059 #define rd_lane_uc_config_dfe_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,13,15,__ERR) 1060 #define wr_lane_uc_config_dfe_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0004,2,wr_val) 1061 #define rd_lane_uc_config_an_enabled() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,14,15,__ERR) 1062 #define wr_lane_uc_config_an_enabled(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0002,1,wr_val) 1063 #define rd_lane_uc_config_lane_cfg_from_pcs() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ad,15,15,__ERR) 1064 #define wr_lane_uc_config_lane_cfg_from_pcs(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ad,0x0001,0,wr_val) 1065 #define rd_lane_cfg_fwapi_data1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1ae,__ERR) 1066 #define wr_lane_cfg_fwapi_data1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1ae,wr_val) 1067 #define rd_rx_osr_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c0,0,15,__ERR) 1068 #define wr_rx_osr_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c0,0x8000,15,wr_val) 1069 #define rd_rx_pam4_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c0,1,15,__ERR) 1070 #define wr_rx_pam4_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c0,0x4000,14,wr_val) 1071 #define rd_rx_pam4_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c0,9,13,__ERR) 1072 #define wr_rx_pam4_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c0,0x0070,4,wr_val) 1073 #define rd_rx_osr_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c0,12,12,__ERR) 1074 #define wr_rx_osr_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c0,0x000f,0,wr_val) 1075 #define rd_rx_ln_dp_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c1,15,15,__ERR) 1076 #define wr_rx_ln_dp_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c1,0x0001,0,wr_val) 1077 #define rd_rx_pll_select() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c7,15,15,__ERR) 1078 #define wr_rx_pll_select(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c7,0x0001,0,wr_val) 1079 #define rd_rx_hw_fw_handshake_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ce,14,15,__ERR) 1080 #define wr_rx_hw_fw_handshake_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ce,0x0002,1,wr_val) 1081 #define rd_rx_ln_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ce,15,15,__ERR) 1082 #define wr_rx_ln_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ce,0x0001,0,wr_val) 1083 #define rd_pmd_ln_rx_dp_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c3,14,15,__ERR) 1084 #define wr_pmd_ln_rx_dp_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c3,0x0002,1,wr_val) 1085 #define rd_pmd_ln_rx_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c3,15,15,__ERR) 1086 #define wr_pmd_ln_rx_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c3,0x0001,0,wr_val) 1087 #define rd_rx_uc_ack_lane_dp_reset() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c5,14,15,__ERR) 1088 #define wr_rx_uc_ack_lane_dp_reset(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c5,0x0002,1,wr_val) 1089 #define rd_rx_uc_ack_lane_cfg_done() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c5,15,15,__ERR) 1090 #define wr_rx_uc_ack_lane_cfg_done(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c5,0x0001,0,wr_val) 1091 #define rd_rx_lane_dp_reset_state() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c9,13,13,__ERR) 1092 #define rd_rx_lane_reg_reset_occurred() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1c6,15,15,__ERR) 1093 #define wr_rx_lane_reg_reset_occurred(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1c6,0x0001,0,wr_val) 1094 #define rd_rx_multicast_mask_control() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1ca,15,15,__ERR) 1095 #define wr_rx_multicast_mask_control(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1ca,0x0001,0,wr_val) 1096 #define rd_rx_multicast_mask_control_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1cb,0,15,__ERR) 1097 #define rd_rx_pam4_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1cb,9,13,__ERR) 1098 #define rd_rx_osr_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1cb,12,12,__ERR) 1099 #define rd_osr_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b0,0,15,__ERR) 1100 #define wr_osr_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b0,0x8000,15,wr_val) 1101 #define rd_pam4_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b0,1,15,__ERR) 1102 #define wr_pam4_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b0,0x4000,14,wr_val) 1103 #define rd_pam4_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b0,9,13,__ERR) 1104 #define wr_pam4_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0070,4,wr_val) 1105 #define rd_osr_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b0,12,12,__ERR) 1106 #define wr_osr_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b0,0x000f,0,wr_val) 1107 #define rd_ln_dp_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b1,15,15,__ERR) 1108 #define wr_ln_dp_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0001,0,wr_val) 1109 #define rd_pll_select() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b7,15,15,__ERR) 1110 #define wr_pll_select(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b7,0x0001,0,wr_val) 1111 #define rd_hw_fw_handshake_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0be,14,15,__ERR) 1112 #define wr_hw_fw_handshake_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0be,0x0002,1,wr_val) 1113 #define rd_ln_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0be,15,15,__ERR) 1114 #define wr_ln_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0be,0x0001,0,wr_val) 1115 #define rd_pmd_ln_dp_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b3,14,15,__ERR) 1116 #define wr_pmd_ln_dp_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0002,1,wr_val) 1117 #define rd_pmd_ln_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b3,15,15,__ERR) 1118 #define wr_pmd_ln_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0001,0,wr_val) 1119 #define rd_uc_ack_lane_dp_reset() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b5,14,15,__ERR) 1120 #define wr_uc_ack_lane_dp_reset(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0002,1,wr_val) 1121 #define rd_uc_ack_lane_cfg_done() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b5,15,15,__ERR) 1122 #define wr_uc_ack_lane_cfg_done(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0001,0,wr_val) 1123 #define rd_lane_dp_reset_state() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b9,13,13,__ERR) 1124 #define rd_lane_reg_reset_occurred() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0b6,15,15,__ERR) 1125 #define wr_lane_reg_reset_occurred(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0001,0,wr_val) 1126 #define rd_multicast_mask_control() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ba,15,15,__ERR) 1127 #define wr_multicast_mask_control(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0ba,0x0001,0,wr_val) 1128 #define rd_multicast_mask_control_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0bb,0,15,__ERR) 1129 #define rd_pam4_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0bb,9,13,__ERR) 1130 #define rd_osr_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0bb,12,12,__ERR) 1131 #define rd_afe_signal_detect_dis() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e1,15,15,__ERR) 1132 #define wr_afe_signal_detect_dis(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0001,0,wr_val) 1133 #define rd_ext_los_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e1,14,15,__ERR) 1134 #define wr_ext_los_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0002,1,wr_val) 1135 #define rd_ext_los_inv() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e1,13,15,__ERR) 1136 #define wr_ext_los_inv(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0004,2,wr_val) 1137 #define rd_signal_detect_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e1,8,15,__ERR) 1138 #define wr_signal_detect_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0080,7,wr_val) 1139 #define rd_signal_detect_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e1,7,15,__ERR) 1140 #define wr_signal_detect_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0100,8,wr_val) 1141 #define rd_los_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e2,13,13,__ERR) 1142 #define wr_los_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0007,0,wr_val) 1143 #define rd_signal_detect_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e2,9,13,__ERR) 1144 #define wr_signal_detect_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0070,4,wr_val) 1145 #define rd_signal_detect() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,15,15,__ERR) 1146 #define rd_signal_detect_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,14,15,__ERR) 1147 #define rd_signal_detect_raw() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,11,15,__ERR) 1148 #define rd_signal_detect_raw_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,10,15,__ERR) 1149 #define rd_ext_sigdet() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,9,15,__ERR) 1150 #define rd_ext_sigdet_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,8,15,__ERR) 1151 #define rd_afe_sigdet() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,7,15,__ERR) 1152 #define rd_afe_sigdet_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0e8,6,15,__ERR) 1153 #define rdc_tlb_err_aggr_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd310,0,14,__ERR) 1154 #define wrc_tlb_err_aggr_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd310,0xc000,14,wr_val) 1155 #define rdc_tlb_err_aggr_lanes_active() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd310,2,8,__ERR) 1156 #define wrc_tlb_err_aggr_lanes_active(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd310,0x3fc0,6,wr_val) 1157 #define rdc_tlb_err_aggr_error_count_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd310,10,12,__ERR) 1158 #define wrc_tlb_err_aggr_error_count_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd310,0x003c,2,wr_val) 1159 #define rdc_tlb_err_aggr_clear_error_analyzer_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd310,14,15,__ERR) 1160 #define wrc_tlb_err_aggr_clear_error_analyzer_status(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd310,0x0002,1,wr_val) 1161 #define rdc_tlb_err_aggr_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd310,15,15,__ERR) 1162 #define wrc_tlb_err_aggr_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd310,0x0001,0,wr_val) 1163 #define rdc_tlb_err_aggr_en_force() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,1,15,__ERR) 1164 #define wrc_tlb_err_aggr_en_force(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x4000,14,wr_val) 1165 #define rdc_tlb_err_aggr_delay_data_capture() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,2,14,__ERR) 1166 #define wrc_tlb_err_aggr_delay_data_capture(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x3000,12,wr_val) 1167 #define rdc_tlb_err_aggr_clk_out_of_sync_pattern_depth() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,4,13,__ERR) 1168 #define wrc_tlb_err_aggr_clk_out_of_sync_pattern_depth(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x0e00,9,wr_val) 1169 #define rdc_tlb_err_aggr_active_pattern_depth() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,7,13,__ERR) 1170 #define wrc_tlb_err_aggr_active_pattern_depth(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x01c0,6,wr_val) 1171 #define rdc_tlb_err_aggr_gclk_div2_en_ignore() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,10,15,__ERR) 1172 #define wrc_tlb_err_aggr_gclk_div2_en_ignore(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x0020,5,wr_val) 1173 #define rdc_tlb_err_aggr_clear_status_on_read() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,11,15,__ERR) 1174 #define wrc_tlb_err_aggr_clear_status_on_read(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x0010,4,wr_val) 1175 #define rdc_tlb_err_aggr_histogram_error_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd311,12,12,__ERR) 1176 #define wrc_tlb_err_aggr_histogram_error_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd311,0x000f,0,wr_val) 1177 #define rdc_tlb_err_aggr_clks_out_of_sync_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd315,10,15,__ERR) 1178 #define rdc_tlb_err_aggr_active_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd315,11,15,__ERR) 1179 #define rdc_tlb_err_aggr_count_error_hi() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd315,12,12,__ERR) 1180 #define rdc_tlb_err_aggr_count_error_lo() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd316,__ERR) 1181 #define rdc_tlb_err_aggr_count_histogram_error_offset_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31e,__ERR) 1182 #define rdc_tlb_err_aggr_count_histogram_error_offset_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31d,__ERR) 1183 #define rdc_tlb_err_aggr_count_histogram_error_offset_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31c,__ERR) 1184 #define rdc_tlb_err_aggr_count_histogram_error_offset_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31b,__ERR) 1185 #define rdc_tlb_err_aggr_count_histogram_error_offset_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31a,__ERR) 1186 #define rdc_tlb_err_aggr_count_histogram_error_offset_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd319,__ERR) 1187 #define rdc_tlb_err_aggr_count_histogram_error_offset_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd318,__ERR) 1188 #define rdc_tlb_err_aggr_count_histogram_error_offset_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd317,__ERR) 1189 #define rd_prbs_chk_burst_err_cnt_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,0,15,__ERR) 1190 #define wr_prbs_chk_burst_err_cnt_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x8000,15,wr_val) 1191 #define rd_prbs_chk_mode_sel_msb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,3,15,__ERR) 1192 #define wr_prbs_chk_mode_sel_msb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x1000,12,wr_val) 1193 #define rd_prbs_chk_clk_en_frc_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,4,15,__ERR) 1194 #define wr_prbs_chk_clk_en_frc_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0800,11,wr_val) 1195 #define rd_trnsum_error_count_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,5,15,__ERR) 1196 #define wr_trnsum_error_count_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0400,10,wr_val) 1197 #define rd_prbs_chk_err_cnt_burst_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,6,15,__ERR) 1198 #define wr_prbs_chk_err_cnt_burst_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0200,9,wr_val) 1199 #define rd_prbs_burst_len_chk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,7,15,__ERR) 1200 #define wr_prbs_burst_len_chk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0100,8,wr_val) 1201 #define rd_prbs_chk_en_auto_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,8,15,__ERR) 1202 #define wr_prbs_chk_en_auto_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0080,7,wr_val) 1203 #define rd_prbs_chk_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,9,14,__ERR) 1204 #define wr_prbs_chk_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0060,5,wr_val) 1205 #define rd_prbs_chk_inv() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,11,15,__ERR) 1206 #define wr_prbs_chk_inv(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0010,4,wr_val) 1207 #define rd_prbs_chk_mode_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,12,13,__ERR) 1208 #define wr_prbs_chk_mode_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x000e,1,wr_val) 1209 #define rd_prbs_chk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd161,15,15,__ERR) 1210 #define wr_prbs_chk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd161,0x0001,0,wr_val) 1211 #define rd_rx_trn_active_auto_mode_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd160,0,15,__ERR) 1212 #define wr_rx_trn_active_auto_mode_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd160,0x8000,15,wr_val) 1213 #define rd_prbs_chk_lock_cnt() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd160,11,11,__ERR) 1214 #define wr_prbs_chk_lock_cnt(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd160,0x001f,0,wr_val) 1215 #define rd_prbs_chk_ool_cnt() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd160,3,11,__ERR) 1216 #define wr_prbs_chk_ool_cnt(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd160,0x1f00,8,wr_val) 1217 #define rd_dig_lpbk_pd_bias_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd162,12,15,__ERR) 1218 #define wr_dig_lpbk_pd_bias_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd162,0x0008,3,wr_val) 1219 #define rd_dig_lpbk_pd_flt_bypass() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd162,13,15,__ERR) 1220 #define wr_dig_lpbk_pd_flt_bypass(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd162,0x0004,2,wr_val) 1221 #define rd_dig_lpbk_pd_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd162,14,15,__ERR) 1222 #define wr_dig_lpbk_pd_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd162,0x0002,1,wr_val) 1223 #define rd_dig_lpbk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd162,15,15,__ERR) 1224 #define wr_dig_lpbk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd162,0x0001,0,wr_val) 1225 #define rd_pam4_rx_symbol_bit_swap() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,8,15,__ERR) 1226 #define wr_pam4_rx_symbol_bit_swap(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0080,7,wr_val) 1227 #define rd_prbs_chk_auto_detect_relock_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,0,15,__ERR) 1228 #define wr_prbs_chk_auto_detect_relock_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x8000,15,wr_val) 1229 #define rd_prbs_chk_auto_detect_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,1,15,__ERR) 1230 #define wr_prbs_chk_auto_detect_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x4000,14,wr_val) 1231 #define rd_prbs_chk_auto_detect_cnt() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,3,11,__ERR) 1232 #define wr_prbs_chk_auto_detect_cnt(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x1f00,8,wr_val) 1233 #define rd_pam4_decoder_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,9,15,__ERR) 1234 #define wr_pam4_decoder_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0040,6,wr_val) 1235 #define rd_pam4_gray_dec_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,10,15,__ERR) 1236 #define wr_pam4_gray_dec_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0020,5,wr_val) 1237 #define rd_tlb_rx_nrz_ll_mode_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,11,15,__ERR) 1238 #define wr_tlb_rx_nrz_ll_mode_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0010,4,wr_val) 1239 #define rd_tlb_rx_diff_dec_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,12,15,__ERR) 1240 #define wr_tlb_rx_diff_dec_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0008,3,wr_val) 1241 #define rd_dbg_mask_dig_lpbk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,13,15,__ERR) 1242 #define wr_dbg_mask_dig_lpbk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0004,2,wr_val) 1243 #define rd_rx_descrambler_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,14,15,__ERR) 1244 #define wr_rx_descrambler_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0002,1,wr_val) 1245 #define rd_rx_pmd_dp_invert() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd163,15,15,__ERR) 1246 #define wr_rx_pmd_dp_invert(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd163,0x0001,0,wr_val) 1247 #define rd_prbs_chk_en_timeout() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd164,3,11,__ERR) 1248 #define wr_prbs_chk_en_timeout(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd164,0x1f00,8,wr_val) 1249 #define rd_prbs_chk_en_timer_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd164,14,14,__ERR) 1250 #define wr_prbs_chk_en_timer_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd164,0x0003,0,wr_val) 1251 #define rd_prbs_chk_mode_sel_msb_auto_detect() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd168,2,15,__ERR) 1252 #define rd_prbs_chk_mode_sel_auto_detect() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd168,3,13,__ERR) 1253 #define rd_prbs_chk_inv_auto_detect() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd168,6,15,__ERR) 1254 #define rd_prbs_chk_auto_detect_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd168,7,15,__ERR) 1255 #define rd_dig_lpbk_pd_early_ind() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd168,14,15,__ERR) 1256 #define rd_dig_lpbk_pd_late_ind() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd168,15,15,__ERR) 1257 #define rd_prbs_chk_err_cnt_no_clr() _blackhawk_tsc_pmd_rde_field(sa__, 0xd169,0,1,__ERR) 1258 #define rd_prbs_chk_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd169,15,15,__ERR) 1259 #define rd_prbs_chk_lock_lost_lh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd16a,0,15,__ERR) 1260 #define rd_prbs_chk_err_cnt_msb() _blackhawk_tsc_pmd_rde_field(sa__, 0xd16a,1,1,__ERR) 1261 #define rd_prbs_chk_err_cnt_lsb() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd16b,__ERR) 1262 #define rd_pmd_rx_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd16c,15,15,__ERR) 1263 #define rd_pmd_rx_lock_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd16c,14,15,__ERR) 1264 #define rd_dbg_pmd_rx_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd166,15,15,__ERR) 1265 #define rd_dbg_pmd_rx_lock_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd166,14,15,__ERR) 1266 #define rd_uc_pmd_rx_lock() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd167,15,15,__ERR) 1267 #define rd_uc_pmd_rx_lock_change() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd167,14,15,__ERR) 1268 #define rd_prbs_burst_err_length_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd16d,10,10,__ERR) 1269 #define rd_max_prbs_burst_err_length_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd16e,10,10,__ERR) 1270 #define rd_prbs_chk_burst_err_cnt() _blackhawk_tsc_pmd_rde_field(sa__, 0xd165,6,6,__ERR) 1271 #define rd_tlb_err_fec_size() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f0,0,10,__ERR) 1272 #define wr_tlb_err_fec_size(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f0,0xfc00,10,wr_val) 1273 #define rd_tlb_err_fec_l_r_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f0,6,15,__ERR) 1274 #define wr_tlb_err_fec_l_r_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f0,0x0200,9,wr_val) 1275 #define rd_tlb_err_fec_l_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f0,7,15,__ERR) 1276 #define wr_tlb_err_fec_l_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f0,0x0100,8,wr_val) 1277 #define rd_tlb_err_ignore_back_channel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f0,9,15,__ERR) 1278 #define wr_tlb_err_ignore_back_channel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f0,0x0040,6,wr_val) 1279 #define rd_tlb_err_error_count_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f0,10,12,__ERR) 1280 #define wr_tlb_err_error_count_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f0,0x003c,2,wr_val) 1281 #define rd_tlb_err_clear_error_analyzer_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f0,14,15,__ERR) 1282 #define wr_tlb_err_clear_error_analyzer_status(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f0,0x0002,1,wr_val) 1283 #define rd_tlb_err_clear_status_on_read() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f1,11,15,__ERR) 1284 #define wr_tlb_err_clear_status_on_read(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f1,0x0010,4,wr_val) 1285 #define rd_tlb_err_histogram_error_thresh() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f1,12,12,__ERR) 1286 #define wr_tlb_err_histogram_error_thresh(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1f1,0x000f,0,wr_val) 1287 #define rd_tlb_err_count_error_hi() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1f5,12,12,__ERR) 1288 #define rd_tlb_err_count_error_lo() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f6,__ERR) 1289 #define rd_tlb_err_count_histogram_error_offset_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fe,__ERR) 1290 #define rd_tlb_err_count_histogram_error_offset_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fd,__ERR) 1291 #define rd_tlb_err_count_histogram_error_offset_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fc,__ERR) 1292 #define rd_tlb_err_count_histogram_error_offset_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fb,__ERR) 1293 #define rd_tlb_err_count_histogram_error_offset_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fa,__ERR) 1294 #define rd_tlb_err_count_histogram_error_offset_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f9,__ERR) 1295 #define rd_tlb_err_count_histogram_error_offset_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f8,__ERR) 1296 #define rd_tlb_err_count_histogram_error_offset_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f7,__ERR) 1297 #define rd_patt_gen_start_pos() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd170,0,12,__ERR) 1298 #define wr_patt_gen_start_pos(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd170,0xf000,12,wr_val) 1299 #define rd_patt_gen_stop_pos() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd170,4,12,__ERR) 1300 #define wr_patt_gen_stop_pos(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd170,0x0f00,8,wr_val) 1301 #define rd_pam4_tx_jp03b_patt_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd170,8,15,__ERR) 1302 #define wr_pam4_tx_jp03b_patt_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd170,0x0080,7,wr_val) 1303 #define rd_pam4_tx_linearity_patt_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd170,9,15,__ERR) 1304 #define wr_pam4_tx_linearity_patt_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd170,0x0040,6,wr_val) 1305 #define rd_patt_gen_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd170,15,15,__ERR) 1306 #define wr_patt_gen_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd170,0x0001,0,wr_val) 1307 #define rd_prbs_gen_pause_strobe() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd171,0,15,__ERR) 1308 #define wr_prbs_gen_pause_strobe(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd171,0x8000,15,wr_val) 1309 #define rd_prbs_gen_mode_sel_msb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd171,3,15,__ERR) 1310 #define wr_prbs_gen_mode_sel_msb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd171,0x1000,12,wr_val) 1311 #define rd_prbs_gen_err_ins() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd171,10,15,__ERR) 1312 #define wr_prbs_gen_err_ins(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd171,0x0020,5,wr_val) 1313 #define rd_prbs_gen_inv() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd171,11,15,__ERR) 1314 #define wr_prbs_gen_inv(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd171,0x0010,4,wr_val) 1315 #define rd_prbs_gen_mode_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd171,12,13,__ERR) 1316 #define wr_prbs_gen_mode_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd171,0x000e,1,wr_val) 1317 #define rd_prbs_gen_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd171,15,15,__ERR) 1318 #define wr_prbs_gen_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd171,0x0001,0,wr_val) 1319 #define rd_rmt_lpbk_pd_frc_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd172,13,15,__ERR) 1320 #define wr_rmt_lpbk_pd_frc_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd172,0x0004,2,wr_val) 1321 #define rd_rmt_lpbk_pd_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd172,14,15,__ERR) 1322 #define wr_rmt_lpbk_pd_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd172,0x0002,1,wr_val) 1323 #define rd_rmt_lpbk_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd172,15,15,__ERR) 1324 #define wr_rmt_lpbk_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd172,0x0001,0,wr_val) 1325 #define rd_tx_trn_active_auto_mode_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd173,11,15,__ERR) 1326 #define wr_tx_trn_active_auto_mode_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd173,0x0010,4,wr_val) 1327 #define rd_tlb_tx_diff_enc_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd173,12,15,__ERR) 1328 #define wr_tlb_tx_diff_enc_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd173,0x0008,3,wr_val) 1329 #define rd_tx_mux_sel_order() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd173,13,15,__ERR) 1330 #define wr_tx_mux_sel_order(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd173,0x0004,2,wr_val) 1331 #define rd_tx_pcs_native_ana_frmt_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd173,14,15,__ERR) 1332 #define wr_tx_pcs_native_ana_frmt_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd173,0x0002,1,wr_val) 1333 #define rd_tx_pmd_dp_invert() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd173,15,15,__ERR) 1334 #define wr_tx_pmd_dp_invert(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd173,0x0001,0,wr_val) 1335 #define rd_pam4_tx_symbol_bit_swap() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd175,12,15,__ERR) 1336 #define wr_pam4_tx_symbol_bit_swap(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd175,0x0008,3,wr_val) 1337 #define rd_tx_scrambler_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd175,13,15,__ERR) 1338 #define wr_tx_scrambler_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd175,0x0004,2,wr_val) 1339 #define rd_pam4_precoder_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd175,14,15,__ERR) 1340 #define wr_pam4_precoder_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd175,0x0002,1,wr_val) 1341 #define rd_pam4_gray_enc_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd175,15,15,__ERR) 1342 #define wr_pam4_gray_enc_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd175,0x0001,0,wr_val) 1343 #define rd_rmt_lpbk_pd_early_ind() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd178,14,15,__ERR) 1344 #define rd_rmt_lpbk_pd_late_ind() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd178,15,15,__ERR) 1345 #define rd_afe_tx_reset_deassert() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b1,0,15,__ERR) 1346 #define wr_afe_tx_reset_deassert(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b1,0x8000,15,wr_val) 1347 #define rd_ln_tx_s_pwrdn() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b1,15,15,__ERR) 1348 #define wr_ln_tx_s_pwrdn(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b1,0x0001,0,wr_val) 1349 #define rd_pmd_tx_clk_vld_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b7,11,15,__ERR) 1350 #define wr_pmd_tx_clk_vld_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b7,0x0010,4,wr_val) 1351 #define rd_pmd_tx_clk_vld_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b7,12,15,__ERR) 1352 #define wr_pmd_tx_clk_vld_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b7,0x0008,3,wr_val) 1353 #define rd_ln_tx_s_comclk_frc_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b7,13,15,__ERR) 1354 #define wr_ln_tx_s_comclk_frc_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b7,0x0004,2,wr_val) 1355 #define rd_ln_tx_s_comclk_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b7,14,15,__ERR) 1356 #define wr_ln_tx_s_comclk_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b7,0x0002,1,wr_val) 1357 #define rd_ln_tx_s_clkgate_frc_on() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b7,15,15,__ERR) 1358 #define wr_ln_tx_s_clkgate_frc_on(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b7,0x0001,0,wr_val) 1359 #define rd_ln_tx_dp_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b4,14,15,__ERR) 1360 #define wr_ln_tx_dp_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b4,0x0002,1,wr_val) 1361 #define rd_ln_tx_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b4,15,15,__ERR) 1362 #define wr_ln_tx_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b4,0x0001,0,wr_val) 1363 #define rd_afe_tx_reset_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b2,12,15,__ERR) 1364 #define wr_afe_tx_reset_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b2,0x0008,3,wr_val) 1365 #define rd_afe_tx_reset_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b2,13,15,__ERR) 1366 #define wr_afe_tx_reset_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b2,0x0004,2,wr_val) 1367 #define rd_afe_tx_pwrdn_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b2,14,15,__ERR) 1368 #define wr_afe_tx_pwrdn_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b2,0x0002,1,wr_val) 1369 #define rd_afe_tx_pwrdn_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b2,15,15,__ERR) 1370 #define wr_afe_tx_pwrdn_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b2,0x0001,0,wr_val) 1371 #define rd_pmd_ln_tx_h_pwrdn_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1b3,15,15,__ERR) 1372 #define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1b3,0x0001,0,wr_val) 1373 #define rd_pmd_tx_lane_mode() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b8,__ERR) 1374 #define rd_tx_pi_loop_filter_stable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1bd,15,15,__ERR) 1375 #define wr_tx_pi_loop_filter_stable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1bd,0x0001,0,wr_val) 1376 #define rd_tx_eee_alert_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,0,15,__ERR) 1377 #define wr_tx_eee_alert_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x8000,15,wr_val) 1378 #define rd_tx_eee_quiet_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,1,15,__ERR) 1379 #define wr_tx_eee_quiet_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x4000,14,wr_val) 1380 #define rd_tx_disable_timer_ctrl() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,6,10,__ERR) 1381 #define wr_tx_disable_timer_ctrl(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x03f0,4,wr_val) 1382 #define rd_pmd_tx_disable_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,12,15,__ERR) 1383 #define wr_pmd_tx_disable_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x0008,3,wr_val) 1384 #define rd_dp_reset_tx_disable_dis() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,13,15,__ERR) 1385 #define wr_dp_reset_tx_disable_dis(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x0004,2,wr_val) 1386 #define rd_tx_disable_trigger() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,14,15,__ERR) 1387 #define wr_tx_disable_trigger(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x0002,1,wr_val) 1388 #define rd_micro_tx_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd130,15,15,__ERR) 1389 #define wr_micro_tx_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd130,0x0001,0,wr_val) 1390 #define rd_tx_disable_output_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd131,12,14,__ERR) 1391 #define wr_tx_disable_output_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd131,0x000c,2,wr_val) 1392 #define rd_sdk_tx_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd131,15,15,__ERR) 1393 #define wr_sdk_tx_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd131,0x0001,0,wr_val) 1394 #define rd_tx_elec_idle_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd132,14,15,__ERR) 1395 #define rd_tx_disable_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd132,15,15,__ERR) 1396 #define rd_txfir_test_data_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd133,0,15,__ERR) 1397 #define wr_txfir_test_data_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd133,0x8000,15,wr_val) 1398 #define rd_txfir_tap_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd133,2,14,__ERR) 1399 #define wr_txfir_tap_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd133,0x3000,12,wr_val) 1400 #define rd_txfir_tap_load() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd133,4,15,__ERR) 1401 #define wr_txfir_tap_load(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd133,0x0800,11,wr_val) 1402 #define rd_txfir_nrz_tap_range_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd133,5,15,__ERR) 1403 #define wr_txfir_nrz_tap_range_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd133,0x0400,10,wr_val) 1404 #define rd_txfir_tap0_coeff() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd133,7,7,__ERR) 1405 #define wr_txfir_tap0_coeff(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd133,0x01ff,0,wr_val) 1406 #define rd_txfir_tap1_coeff() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd134,7,7,__ERR) 1407 #define wr_txfir_tap1_coeff(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd134,0x01ff,0,wr_val) 1408 #define rd_txfir_tap2_coeff() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd135,7,7,__ERR) 1409 #define wr_txfir_tap2_coeff(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd135,0x01ff,0,wr_val) 1410 #define rd_txfir_tap3_coeff() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd136,7,7,__ERR) 1411 #define wr_txfir_tap3_coeff(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd136,0x01ff,0,wr_val) 1412 #define rd_txfir_tap4_coeff() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd137,7,7,__ERR) 1413 #define wr_txfir_tap4_coeff(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd137,0x01ff,0,wr_val) 1414 #define rd_txfir_tap5_coeff() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd138,7,7,__ERR) 1415 #define wr_txfir_tap5_coeff(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd138,0x01ff,0,wr_val) 1416 #define rd_txfir_level_shift_mode_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd139,0,15,__ERR) 1417 #define wr_txfir_level_shift_mode_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd139,0x8000,15,wr_val) 1418 #define rd_txfir_dc_adjust() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd139,1,9,__ERR) 1419 #define wr_txfir_dc_adjust(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd139,0x7f00,8,wr_val) 1420 #define rd_txfir_tap6_coeff() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd139,9,9,__ERR) 1421 #define wr_txfir_tap6_coeff(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd139,0x007f,0,wr_val) 1422 #define rd_txfir_tap7_coeff() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd13a,9,9,__ERR) 1423 #define wr_txfir_tap7_coeff(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd13a,0x007f,0,wr_val) 1424 #define rd_txfir_tap8_coeff() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd13b,9,9,__ERR) 1425 #define wr_txfir_tap8_coeff(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd13b,0x007f,0,wr_val) 1426 #define rd_txfir_tap9_coeff() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd13c,9,9,__ERR) 1427 #define wr_txfir_tap9_coeff(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd13c,0x007f,0,wr_val) 1428 #define rd_txfir_tap10_coeff() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd13d,9,9,__ERR) 1429 #define wr_txfir_tap10_coeff(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd13d,0x007f,0,wr_val) 1430 #define rd_txfir_tap11_coeff() _blackhawk_tsc_pmd_rde_field_signed_byte(sa__, 0xd13e,9,9,__ERR) 1431 #define wr_txfir_tap11_coeff(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd13e,0x007f,0,wr_val) 1432 #define rd_tx_pi_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,15,15,__ERR) 1433 #define wr_tx_pi_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0001,0,wr_val) 1434 #define rd_tx_pi_jitter_filter_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,14,15,__ERR) 1435 #define wr_tx_pi_jitter_filter_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0002,1,wr_val) 1436 #define rd_tx_pi_ext_ctrl_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,13,15,__ERR) 1437 #define wr_tx_pi_ext_ctrl_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0004,2,wr_val) 1438 #define rd_tx_pi_freq_override_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,12,15,__ERR) 1439 #define wr_tx_pi_freq_override_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0008,3,wr_val) 1440 #define rd_tx_pi_sj_gen_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,11,15,__ERR) 1441 #define wr_tx_pi_sj_gen_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0010,4,wr_val) 1442 #define rd_tx_pi_ssc_gen_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,10,15,__ERR) 1443 #define wr_tx_pi_ssc_gen_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0020,5,wr_val) 1444 #define rd_tx_pi_jit_ssc_freq_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,9,15,__ERR) 1445 #define wr_tx_pi_jit_ssc_freq_mode(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0040,6,wr_val) 1446 #define rd_tx_pi_second_order_loop_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,0,15,__ERR) 1447 #define wr_tx_pi_second_order_loop_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x8000,15,wr_val) 1448 #define rd_tx_pi_first_order_bwsel_integ() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,6,13,__ERR) 1449 #define wr_tx_pi_first_order_bwsel_integ(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0380,7,wr_val) 1450 #define rd_tx_pi_second_order_bwsel_integ() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,4,14,__ERR) 1451 #define wr_tx_pi_second_order_bwsel_integ(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0c00,10,wr_val) 1452 #define rd_tx_pi_ext_phase_bwsel_integ() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a0,1,13,__ERR) 1453 #define wr_tx_pi_ext_phase_bwsel_integ(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a0,0x7000,12,wr_val) 1454 #define rd_tx_pi_freq_override_val() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd0a1,1,1,__ERR) 1455 #define wr_tx_pi_freq_override_val(wr_val) blackhawk_tsc_pmd_mwr_reg(sa__, 0xd0a1,0x7fff,0,wr_val) 1456 #define rd_tx_pi_jit_freq_idx() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a2,10,10,__ERR) 1457 #define wr_tx_pi_jit_freq_idx(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a2,0x003f,0,wr_val) 1458 #define rd_tx_pi_jit_amp() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a2,2,10,__ERR) 1459 #define wr_tx_pi_jit_amp(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a2,0x3f00,8,wr_val) 1460 #define rd_tx_pi_hs_fifo_phserr_invert() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,14,15,__ERR) 1461 #define wr_tx_pi_hs_fifo_phserr_invert(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0002,1,wr_val) 1462 #define rd_tx_pi_repeater_mode_en() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,13,15,__ERR) 1463 #define wr_tx_pi_repeater_mode_en(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0004,2,wr_val) 1464 #define rd_tx_pi_ext_pd_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,12,15,__ERR) 1465 #define wr_tx_pi_ext_pd_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0008,3,wr_val) 1466 #define rd_tx_pi_hs_fifo_phserr_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,11,15,__ERR) 1467 #define wr_tx_pi_hs_fifo_phserr_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0010,4,wr_val) 1468 #define rd_tx_pi_ext_phase_step_cnt_invert() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,10,15,__ERR) 1469 #define wr_tx_pi_ext_phase_step_cnt_invert(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0020,5,wr_val) 1470 #define rd_tx_pi_ext_phase_step_cnt_sel() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,9,15,__ERR) 1471 #define wr_tx_pi_ext_phase_step_cnt_sel(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0040,6,wr_val) 1472 #define rd_tx_pi_ext_phase_step_cnt_full_bypass() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,8,15,__ERR) 1473 #define wr_tx_pi_ext_phase_step_cnt_full_bypass(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0080,7,wr_val) 1474 #define rd_afe_tx_fifo_resetb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,7,15,__ERR) 1475 #define wr_afe_tx_fifo_resetb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0100,8,wr_val) 1476 #define rd_afe_tx_fifo_resetb_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,6,15,__ERR) 1477 #define wr_afe_tx_fifo_resetb_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0200,9,wr_val) 1478 #define rd_tx_pi_pd_bypass_flt() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,5,15,__ERR) 1479 #define wr_tx_pi_pd_bypass_flt(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0400,10,wr_val) 1480 #define rd_tx_pi_pd_bypass_vco() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0a5,4,15,__ERR) 1481 #define wr_tx_pi_pd_bypass_vco(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0800,11,wr_val) 1482 #define rd_tx_pi_integ1_reg() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd0a9,2,2,__ERR) 1483 #define rd_tx_pi_integ2_reg() _blackhawk_tsc_pmd_rde_field_signed(sa__, 0xd0aa,1,1,__ERR) 1484 #define rd_st_afe_tx_fifo_resetb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ac,14,15,__ERR) 1485 #define rd_tx_pi_hs_fifo_phserr() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd0ac,15,15,__ERR) 1486 #define rd_tx_osr_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d0,0,15,__ERR) 1487 #define wr_tx_osr_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d0,0x8000,15,wr_val) 1488 #define rd_tx_pam4_mode_frc() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d0,1,15,__ERR) 1489 #define wr_tx_pam4_mode_frc(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d0,0x4000,14,wr_val) 1490 #define rd_tx_pam4_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d0,9,13,__ERR) 1491 #define wr_tx_pam4_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d0,0x0070,4,wr_val) 1492 #define rd_tx_osr_mode_frc_val() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d0,12,12,__ERR) 1493 #define wr_tx_osr_mode_frc_val(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d0,0x000f,0,wr_val) 1494 #define rd_tx_ln_dp_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d1,15,15,__ERR) 1495 #define wr_tx_ln_dp_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d1,0x0001,0,wr_val) 1496 #define rd_tx_pll_select() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d7,15,15,__ERR) 1497 #define wr_tx_pll_select(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d7,0x0001,0,wr_val) 1498 #define rd_tx_hw_fw_handshake_disable() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1de,14,15,__ERR) 1499 #define wr_tx_hw_fw_handshake_disable(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1de,0x0002,1,wr_val) 1500 #define rd_tx_ln_s_rstb() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1de,15,15,__ERR) 1501 #define wr_tx_ln_s_rstb(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1de,0x0001,0,wr_val) 1502 #define rd_pmd_ln_tx_dp_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d3,14,15,__ERR) 1503 #define wr_pmd_ln_tx_dp_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d3,0x0002,1,wr_val) 1504 #define rd_pmd_ln_tx_h_rstb_pkill() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d3,15,15,__ERR) 1505 #define wr_pmd_ln_tx_h_rstb_pkill(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d3,0x0001,0,wr_val) 1506 #define rd_tx_uc_ack_lane_dp_reset() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d5,14,15,__ERR) 1507 #define wr_tx_uc_ack_lane_dp_reset(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d5,0x0002,1,wr_val) 1508 #define rd_tx_uc_ack_lane_cfg_done() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d5,15,15,__ERR) 1509 #define wr_tx_uc_ack_lane_cfg_done(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d5,0x0001,0,wr_val) 1510 #define rd_tx_lane_dp_reset_state() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d9,13,13,__ERR) 1511 #define rd_tx_lane_reg_reset_occurred() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1d6,15,15,__ERR) 1512 #define wr_tx_lane_reg_reset_occurred(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1d6,0x0001,0,wr_val) 1513 #define rd_tx_multicast_mask_control() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1da,15,15,__ERR) 1514 #define wr_tx_multicast_mask_control(wr_val) _blackhawk_tsc_pmd_mwr_reg_byte(sa__, 0xd1da,0x0001,0,wr_val) 1515 #define rd_tx_multicast_mask_control_status() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1db,0,15,__ERR) 1516 #define rd_tx_pam4_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1db,9,13,__ERR) 1517 #define rd_tx_osr_mode() _blackhawk_tsc_pmd_rde_field_byte(sa__, 0xd1db,12,12,__ERR) 1518 1519 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd110,__ERR) 1520 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd110,wr_val) 1521 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd111,__ERR) 1522 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd111,wr_val) 1523 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd114,__ERR) 1524 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd114,wr_val) 1525 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd116,__ERR) 1526 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd116,wr_val) 1527 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd117,__ERR) 1528 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd117,wr_val) 1529 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_8() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd118,__ERR) 1530 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_8(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd118,wr_val) 1531 #define reg_rdc_AMS_PLL_COM_PLL_CONTROL_9() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd119,__ERR) 1532 #define reg_wrc_AMS_PLL_COM_PLL_CONTROL_9(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd119,wr_val) 1533 #define reg_rdc_AMS_PLL_COM_PLL_INTCTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd11b,__ERR) 1534 #define reg_wrc_AMS_PLL_COM_PLL_INTCTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd11b,wr_val) 1535 #define reg_rdc_AMS_PLL_COM_PLL_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd11c,__ERR) 1536 #define reg_wrc_AMS_PLL_COM_PLL_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd11c,wr_val) 1537 #define reg_rd_AMS_RX_RXCONTROL_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0c4,__ERR) 1538 #define reg_wr_AMS_RX_RXCONTROL_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0c4,wr_val) 1539 #define reg_rd_AMS_RX_RXCONTROL_8() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0c8,__ERR) 1540 #define reg_wr_AMS_RX_RXCONTROL_8(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0c8,wr_val) 1541 #define reg_rd_AMS_RX_RXCONTROL_10() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0ca,__ERR) 1542 #define reg_wr_AMS_RX_RXCONTROL_10(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0ca,wr_val) 1543 #define reg_rd_AMS_TX_TXCONTROL_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0d3,__ERR) 1544 #define reg_wr_AMS_TX_TXCONTROL_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0d3,wr_val) 1545 #define reg_rd_AMS_TX_TXSTATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0d9,__ERR) 1546 #define reg_wr_AMS_TX_TXSTATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0d9,wr_val) 1547 #define reg_rdc_CORE_PLL_COM_PMD_CORE_MODE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd180,__ERR) 1548 #define reg_wrc_CORE_PLL_COM_PMD_CORE_MODE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd180,wr_val) 1549 #define reg_rdc_CORE_PLL_COM_TOP_USER_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd184,__ERR) 1550 #define reg_wrc_CORE_PLL_COM_TOP_USER_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd184,wr_val) 1551 #define reg_rdc_CORE_PLL_COM_UC_ACK_CORE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd185,__ERR) 1552 #define reg_wrc_CORE_PLL_COM_UC_ACK_CORE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd185,wr_val) 1553 #define reg_rdc_CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd188,__ERR) 1554 #define reg_wrc_CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd188,wr_val) 1555 #define reg_rdc_CORE_PLL_COM_PLL_UC_CORE_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd18d,__ERR) 1556 #define reg_wrc_CORE_PLL_COM_PLL_UC_CORE_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd18d,wr_val) 1557 #define reg_rdc_CORE_PLL_COM_PLL_CFG_FWAPI_DATA1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd18e,__ERR) 1558 #define reg_wrc_CORE_PLL_COM_PLL_CFG_FWAPI_DATA1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd18e,wr_val) 1559 #define reg_rdc_DIG_COM_REVID0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd100,__ERR) 1560 #define reg_wrc_DIG_COM_REVID0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd100,wr_val) 1561 #define reg_rdc_DIG_COM_REVID1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd10a,__ERR) 1562 #define reg_wrc_DIG_COM_REVID1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd10a,wr_val) 1563 #define reg_rdc_DIG_COM_REVID2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd10e,__ERR) 1564 #define reg_wrc_DIG_COM_REVID2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd10e,wr_val) 1565 #define reg_rdc_DIG_COM_RESET_CONTROL_PMD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd101,__ERR) 1566 #define reg_wrc_DIG_COM_RESET_CONTROL_PMD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd101,wr_val) 1567 #define reg_rdc_DIG_COM_RESET_CONTROL_CORE_DP() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd102,__ERR) 1568 #define reg_wrc_DIG_COM_RESET_CONTROL_CORE_DP(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd102,wr_val) 1569 #define reg_rdc_DIG_COM_MASKDATA_REG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd103,__ERR) 1570 #define reg_wrc_DIG_COM_MASKDATA_REG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd103,wr_val) 1571 #define reg_rdc_DIG_COM_TOP_USER_CONTROL_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd104,__ERR) 1572 #define reg_wrc_DIG_COM_TOP_USER_CONTROL_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd104,wr_val) 1573 #define reg_rdc_DIG_COM_CORE_DP_RESET_STATE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd108,__ERR) 1574 #define reg_wrc_DIG_COM_CORE_DP_RESET_STATE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd108,wr_val) 1575 #define reg_rdc_DIG_COM_B_LANE_ADDR_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd190,__ERR) 1576 #define reg_wrc_DIG_COM_B_LANE_ADDR_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd190,wr_val) 1577 #define reg_rdc_DIG_COM_B_LANE_ADDR_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd191,__ERR) 1578 #define reg_wrc_DIG_COM_B_LANE_ADDR_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd191,wr_val) 1579 #define reg_rdc_DIG_COM_B_LANE_ADDR_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd192,__ERR) 1580 #define reg_wrc_DIG_COM_B_LANE_ADDR_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd192,wr_val) 1581 #define reg_rdc_DIG_COM_B_LANE_ADDR_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd193,__ERR) 1582 #define reg_wrc_DIG_COM_B_LANE_ADDR_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd193,wr_val) 1583 #define reg_rdc_DIG_COM_B_LANE_ADDR_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd194,__ERR) 1584 #define reg_wrc_DIG_COM_B_LANE_ADDR_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd194,wr_val) 1585 #define reg_rdc_DIG_COM_B_LANE_ADDR_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd195,__ERR) 1586 #define reg_wrc_DIG_COM_B_LANE_ADDR_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd195,wr_val) 1587 #define reg_rdc_DIG_COM_B_LANE_ADDR_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd196,__ERR) 1588 #define reg_wrc_DIG_COM_B_LANE_ADDR_6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd196,wr_val) 1589 #define reg_rdc_DIG_COM_B_LANE_ADDR_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd197,__ERR) 1590 #define reg_wrc_DIG_COM_B_LANE_ADDR_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd197,wr_val) 1591 #define reg_rd_DSC_A_DSC_UC_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd03d,__ERR) 1592 #define reg_wr_DSC_A_DSC_UC_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd03d,wr_val) 1593 #define reg_rd_DSC_A_DSC_SCRATCH() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd03e,__ERR) 1594 #define reg_wr_DSC_A_DSC_SCRATCH(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd03e,wr_val) 1595 #define reg_rd_DSC_A_BLW_STATUS_1_TYPE() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd03b,__ERR) 1596 #define reg_wr_DSC_A_BLW_STATUS_1_TYPE(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd03b,wr_val) 1597 #define reg_rd_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd005,__ERR) 1598 #define reg_wr_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd005,wr_val) 1599 #define reg_rd_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd006,__ERR) 1600 #define reg_wr_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd006,wr_val) 1601 #define reg_rd_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd007,__ERR) 1602 #define reg_wr_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd007,wr_val) 1603 #define reg_rd_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd008,__ERR) 1604 #define reg_wr_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd008,wr_val) 1605 #define reg_rd_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd009,__ERR) 1606 #define reg_wr_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd009,wr_val) 1607 #define reg_rd_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd00a,__ERR) 1608 #define reg_wr_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd00a,wr_val) 1609 #define reg_rd_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd00b,__ERR) 1610 #define reg_wr_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd00b,wr_val) 1611 #define reg_rd_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd00c,__ERR) 1612 #define reg_wr_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd00c,wr_val) 1613 #define reg_rd_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd00d,__ERR) 1614 #define reg_wr_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd00d,wr_val) 1615 #define reg_rd_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd00e,__ERR) 1616 #define reg_wr_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd00e,wr_val) 1617 #define reg_rd_DSC_AFE2_RX_DFE_TAP4_AB() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd013,__ERR) 1618 #define reg_wr_DSC_AFE2_RX_DFE_TAP4_AB(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd013,wr_val) 1619 #define reg_rd_DSC_AFE2_RX_DFE_TAP4_CD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd014,__ERR) 1620 #define reg_wr_DSC_AFE2_RX_DFE_TAP4_CD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd014,wr_val) 1621 #define reg_rd_DSC_AFE2_RX_DFE_TAP5_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd015,__ERR) 1622 #define reg_wr_DSC_AFE2_RX_DFE_TAP5_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd015,wr_val) 1623 #define reg_rd_DSC_AFE2_RX_DFE_TAP6_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd016,__ERR) 1624 #define reg_wr_DSC_AFE2_RX_DFE_TAP6_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd016,wr_val) 1625 #define reg_rd_DSC_AFE2_RX_DFE_TAP7_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd017,__ERR) 1626 #define reg_wr_DSC_AFE2_RX_DFE_TAP7_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd017,wr_val) 1627 #define reg_rd_DSC_AFE2_RX_DFE_TAP8_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd018,__ERR) 1628 #define reg_wr_DSC_AFE2_RX_DFE_TAP8_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd018,wr_val) 1629 #define reg_rd_DSC_AFE2_RX_DFE_TAP9_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd019,__ERR) 1630 #define reg_wr_DSC_AFE2_RX_DFE_TAP9_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd019,wr_val) 1631 #define reg_rd_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd01a,__ERR) 1632 #define reg_wr_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd01a,wr_val) 1633 #define reg_rd_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd01b,__ERR) 1634 #define reg_wr_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd01b,wr_val) 1635 #define reg_rd_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd01c,__ERR) 1636 #define reg_wr_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd01c,wr_val) 1637 #define reg_rd_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd01d,__ERR) 1638 #define reg_wr_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd01d,wr_val) 1639 #define reg_rd_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd01e,__ERR) 1640 #define reg_wr_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd01e,wr_val) 1641 #define reg_rd_DSC_AFE3_RX_DFE_TAP10_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd020,__ERR) 1642 #define reg_wr_DSC_AFE3_RX_DFE_TAP10_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd020,wr_val) 1643 #define reg_rd_DSC_AFE3_RX_DFE_TAP11_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd021,__ERR) 1644 #define reg_wr_DSC_AFE3_RX_DFE_TAP11_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd021,wr_val) 1645 #define reg_rd_DSC_AFE3_RX_DFE_TAP12_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd022,__ERR) 1646 #define reg_wr_DSC_AFE3_RX_DFE_TAP12_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd022,wr_val) 1647 #define reg_rd_DSC_AFE3_RX_DFE_TAP13_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd023,__ERR) 1648 #define reg_wr_DSC_AFE3_RX_DFE_TAP13_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd023,wr_val) 1649 #define reg_rd_DSC_AFE3_RX_DFE_TAP14_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd024,__ERR) 1650 #define reg_wr_DSC_AFE3_RX_DFE_TAP14_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd024,wr_val) 1651 #define reg_rd_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd025,__ERR) 1652 #define reg_wr_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd025,wr_val) 1653 #define reg_rd_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd026,__ERR) 1654 #define reg_wr_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd026,wr_val) 1655 #define reg_rd_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd027,__ERR) 1656 #define reg_wr_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd027,wr_val) 1657 #define reg_rd_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd028,__ERR) 1658 #define reg_wr_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd028,wr_val) 1659 #define reg_rd_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd02a,__ERR) 1660 #define reg_wr_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd02a,wr_val) 1661 #define reg_rd_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd02b,__ERR) 1662 #define reg_wr_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd02b,wr_val) 1663 #define reg_rd_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd02c,__ERR) 1664 #define reg_wr_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd02c,wr_val) 1665 #define reg_rd_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd02d,__ERR) 1666 #define reg_wr_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd02d,wr_val) 1667 #define reg_rd_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd02e,__ERR) 1668 #define reg_wr_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd02e,wr_val) 1669 #define reg_rd_DSC_B_DC_OFFSET_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd04c,__ERR) 1670 #define reg_wr_DSC_B_DC_OFFSET_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd04c,wr_val) 1671 #define reg_rd_DSC_B_VGA_D_THRESH_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd04d,__ERR) 1672 #define reg_wr_DSC_B_VGA_D_THRESH_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd04d,wr_val) 1673 #define reg_rd_DSC_B_VGA_DATA_THRESH_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd04b,__ERR) 1674 #define reg_wr_DSC_B_VGA_DATA_THRESH_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd04b,wr_val) 1675 #define reg_rd_DSC_B_VGA_PHASE_THRESH_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd04a,__ERR) 1676 #define reg_wr_DSC_B_VGA_PHASE_THRESH_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd04a,wr_val) 1677 #define reg_rd_DSC_C_CDR_CONTROL_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd050,__ERR) 1678 #define reg_wr_DSC_C_CDR_CONTROL_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd050,wr_val) 1679 #define reg_rd_DSC_C_SLICERS_WRITE_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd05b,__ERR) 1680 #define reg_wr_DSC_C_SLICERS_WRITE_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd05b,wr_val) 1681 #define reg_rd_DSC_D_DSC_SM_CTRL_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd061,__ERR) 1682 #define reg_wr_DSC_D_DSC_SM_CTRL_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd061,wr_val) 1683 #define reg_rd_DSC_D_DSC_SM_CTRL_9() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd069,__ERR) 1684 #define reg_wr_DSC_D_DSC_SM_CTRL_9(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd069,wr_val) 1685 #define reg_rd_DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd06b,__ERR) 1686 #define reg_wr_DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd06b,wr_val) 1687 #define reg_rd_DSC_D_DSC_SM_STATUS_DSC_STATE() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd06e,__ERR) 1688 #define reg_wr_DSC_D_DSC_SM_STATUS_DSC_STATE(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd06e,wr_val) 1689 #define reg_rd_DSC_E_RX_PI_CNT_BIN_P() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd076,__ERR) 1690 #define reg_wr_DSC_E_RX_PI_CNT_BIN_P(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd076,wr_val) 1691 #define reg_rd_DSC_E_RX_PI_CNT_BIN_L() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd077,__ERR) 1692 #define reg_wr_DSC_E_RX_PI_CNT_BIN_L(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd077,wr_val) 1693 #define reg_rd_DSC_E_RX_PI_CNT_BIN_D() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd075,__ERR) 1694 #define reg_wr_DSC_E_RX_PI_CNT_BIN_D(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd075,wr_val) 1695 #define reg_rd_DSC_E_RX_PI_CNT_BIN_LD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd071,__ERR) 1696 #define reg_wr_DSC_E_RX_PI_CNT_BIN_LD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd071,wr_val) 1697 #define reg_rd_DSC_E_RX_PI_CNT_BIN_PD() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd070,__ERR) 1698 #define reg_wr_DSC_E_RX_PI_CNT_BIN_PD(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd070,wr_val) 1699 #define reg_rd_DSC_E_CDR_STATUS_INTEG_REG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd078,__ERR) 1700 #define reg_wr_DSC_E_CDR_STATUS_INTEG_REG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd078,wr_val) 1701 #define reg_rd_DSC_E_RX_PI_CNTR_PHASE_ERR() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd07a,__ERR) 1702 #define reg_wr_DSC_E_RX_PI_CNTR_PHASE_ERR(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd07a,wr_val) 1703 #define reg_rd_DSC_E_RX_DFE_TAP2_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd07b,__ERR) 1704 #define reg_wr_DSC_E_RX_DFE_TAP2_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd07b,wr_val) 1705 #define reg_rd_DSC_E_RX_DFE_TAP2_3_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd07c,__ERR) 1706 #define reg_wr_DSC_E_RX_DFE_TAP2_3_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd07c,wr_val) 1707 #define reg_rd_DSC_E_RX_DFE_TAP3_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd07d,__ERR) 1708 #define reg_wr_DSC_E_RX_DFE_TAP3_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd07d,wr_val) 1709 #define reg_rd_DSC_F_LMS_THRESH_STS_REG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0f8,__ERR) 1710 #define reg_wr_DSC_F_LMS_THRESH_STS_REG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0f8,wr_val) 1711 #define reg_rd_DSC_F_LMS_THRESH_STS2_REG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0f9,__ERR) 1712 #define reg_wr_DSC_F_LMS_THRESH_STS2_REG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0f9,wr_val) 1713 #define reg_rd_DSC_G_RX_DFE_TAP2_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd414,__ERR) 1714 #define reg_wr_DSC_G_RX_DFE_TAP2_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd414,wr_val) 1715 #define reg_rd_DSC_G_RX_DFE_TAP2_3_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd415,__ERR) 1716 #define reg_wr_DSC_G_RX_DFE_TAP2_3_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd415,wr_val) 1717 #define reg_rd_DSC_G_RX_DFE_TAP3_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd416,__ERR) 1718 #define reg_wr_DSC_G_RX_DFE_TAP3_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd416,wr_val) 1719 #define reg_rd_DSC_H_RX_PF_CTRL_DC_OFFSET_AND_VGA() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd42e,__ERR) 1720 #define reg_wr_DSC_H_RX_PF_CTRL_DC_OFFSET_AND_VGA(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd42e,wr_val) 1721 #define reg_rd_DBG_FDBK_DBG_FDBK_PROCESSOR_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd400,__ERR) 1722 #define reg_wr_DBG_FDBK_DBG_FDBK_PROCESSOR_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd400,wr_val) 1723 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd401,__ERR) 1724 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd401,wr_val) 1725 #define reg_rd_DBG_FDBK_DBG_FDBK_CTRL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd402,__ERR) 1726 #define reg_wr_DBG_FDBK_DBG_FDBK_CTRL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd402,wr_val) 1727 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_0_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd403,__ERR) 1728 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_0_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd403,wr_val) 1729 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_1_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd404,__ERR) 1730 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_1_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd404,wr_val) 1731 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_2_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd405,__ERR) 1732 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_2_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd405,wr_val) 1733 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_3_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd406,__ERR) 1734 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_3_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd406,wr_val) 1735 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_4_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd407,__ERR) 1736 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_4_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd407,wr_val) 1737 #define reg_rd_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_5_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd408,__ERR) 1738 #define reg_wr_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_5_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd408,wr_val) 1739 #define reg_rd_DBG_FDBK_DBG_FDBK_PROCESSOR_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd40a,__ERR) 1740 #define reg_wr_DBG_FDBK_DBG_FDBK_PROCESSOR_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd40a,wr_val) 1741 #define reg_rd_LINKTRN_IEEE_RX_LINKTRNIR_BASE_R_LP_COEFF_UPDATE_REGISTER_152() _blackhawk_tsc_pmd_rde_reg(sa__, 0x0098,__ERR) 1742 #define reg_wr_LINKTRN_IEEE_RX_LINKTRNIR_BASE_R_LP_COEFF_UPDATE_REGISTER_152(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0x0098,wr_val) 1743 #define reg_rd_LINKTRN_IEEE_RX_LINKTRNIR_BASE_R_LP_STATUS_REPORT_REGISTER_153() _blackhawk_tsc_pmd_rde_reg(sa__, 0x0099,__ERR) 1744 #define reg_wr_LINKTRN_IEEE_RX_LINKTRNIR_BASE_R_LP_STATUS_REPORT_REGISTER_153(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0x0099,wr_val) 1745 #define reg_rd_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL_REGISTER_150() _blackhawk_tsc_pmd_rde_reg(sa__, 0x0096,__ERR) 1746 #define reg_wr_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL_REGISTER_150(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0x0096,wr_val) 1747 #define reg_rd_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS_REGISTER_151() _blackhawk_tsc_pmd_rde_reg(sa__, 0x0097,__ERR) 1748 #define reg_wr_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS_REGISTER_151(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0x0097,wr_val) 1749 #define reg_rd_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_LD_COEFF_UPDATE_REGISTER_154() _blackhawk_tsc_pmd_rde_reg(sa__, 0x009a,__ERR) 1750 #define reg_wr_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_LD_COEFF_UPDATE_REGISTER_154(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0x009a,wr_val) 1751 #define reg_rd_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_LD_STATUS_REPORT_REGISTER_155() _blackhawk_tsc_pmd_rde_reg(sa__, 0x009b,__ERR) 1752 #define reg_wr_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_LD_STATUS_REPORT_REGISTER_155(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0x009b,wr_val) 1753 #define reg_rd_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd096,__ERR) 1754 #define reg_wr_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd096,wr_val) 1755 #define reg_rdc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR() _blackhawk_tsc_pmd_rde_reg(sa__, 0xffdc,__ERR) 1756 #define reg_wrc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xffdc,wr_val) 1757 #define reg_rdc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT() _blackhawk_tsc_pmd_rde_reg(sa__, 0xffdd,__ERR) 1758 #define reg_wrc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xffdd,wr_val) 1759 #define reg_rdc_MDIO_MMDSEL_AER_COM_MDIO_AER() _blackhawk_tsc_pmd_rde_reg(sa__, 0xffde,__ERR) 1760 #define reg_wrc_MDIO_MMDSEL_AER_COM_MDIO_AER(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xffde,wr_val) 1761 #define reg_rdc_MICRO_A_COM_CLOCK_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd200,__ERR) 1762 #define reg_wrc_MICRO_A_COM_CLOCK_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd200,wr_val) 1763 #define reg_rdc_MICRO_A_COM_RESET_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd201,__ERR) 1764 #define reg_wrc_MICRO_A_COM_RESET_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd201,wr_val) 1765 #define reg_rdc_MICRO_A_COM_AHB_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd202,__ERR) 1766 #define reg_wrc_MICRO_A_COM_AHB_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd202,wr_val) 1767 #define reg_rdc_MICRO_A_COM_AHB_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd203,__ERR) 1768 #define reg_wrc_MICRO_A_COM_AHB_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd203,wr_val) 1769 #define reg_rdc_MICRO_A_COM_AHB_WRADDR_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd204,__ERR) 1770 #define reg_wrc_MICRO_A_COM_AHB_WRADDR_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd204,wr_val) 1771 #define reg_rdc_MICRO_A_COM_AHB_WRADDR_MSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd205,__ERR) 1772 #define reg_wrc_MICRO_A_COM_AHB_WRADDR_MSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd205,wr_val) 1773 #define reg_rdc_MICRO_A_COM_AHB_WRDATA_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd206,__ERR) 1774 #define reg_wrc_MICRO_A_COM_AHB_WRDATA_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd206,wr_val) 1775 #define reg_rdc_MICRO_A_COM_AHB_WRDATA_MSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd207,__ERR) 1776 #define reg_wrc_MICRO_A_COM_AHB_WRDATA_MSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd207,wr_val) 1777 #define reg_rdc_MICRO_A_COM_AHB_RDADDR_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd208,__ERR) 1778 #define reg_wrc_MICRO_A_COM_AHB_RDADDR_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd208,wr_val) 1779 #define reg_rdc_MICRO_A_COM_AHB_RDADDR_MSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd209,__ERR) 1780 #define reg_wrc_MICRO_A_COM_AHB_RDADDR_MSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd209,wr_val) 1781 #define reg_rdc_MICRO_A_COM_AHB_RDDATA_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20a,__ERR) 1782 #define reg_wrc_MICRO_A_COM_AHB_RDDATA_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd20a,wr_val) 1783 #define reg_rdc_MICRO_A_COM_AHB_RDDATA_MSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20b,__ERR) 1784 #define reg_wrc_MICRO_A_COM_AHB_RDDATA_MSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd20b,wr_val) 1785 #define reg_rdc_MICRO_A_COM_PRAMIF_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20c,__ERR) 1786 #define reg_wrc_MICRO_A_COM_PRAMIF_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd20c,wr_val) 1787 #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20d,__ERR) 1788 #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd20d,wr_val) 1789 #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd20e,__ERR) 1790 #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd20e,wr_val) 1791 #define reg_rdc_MICRO_B_COM_PVT_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd210,__ERR) 1792 #define reg_wrc_MICRO_B_COM_PVT_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd210,wr_val) 1793 #define reg_rdc_MICRO_B_COM_RMI_AHB_CONTROL1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd211,__ERR) 1794 #define reg_wrc_MICRO_B_COM_RMI_AHB_CONTROL1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd211,wr_val) 1795 #define reg_rdc_MICRO_B_COM_RMI_AHB_STATUS1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd212,__ERR) 1796 #define reg_wrc_MICRO_B_COM_RMI_AHB_STATUS1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd212,wr_val) 1797 #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd213,__ERR) 1798 #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd213,wr_val) 1799 #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd214,__ERR) 1800 #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd214,wr_val) 1801 #define reg_rdc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd215,__ERR) 1802 #define reg_wrc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd215,wr_val) 1803 #define reg_rdc_MICRO_B_COM_RMI_MICRO_MISC_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd21d,__ERR) 1804 #define reg_wrc_MICRO_B_COM_RMI_MICRO_MISC_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd21d,wr_val) 1805 #define reg_rdc_MICRO_B_COM_RMI_PVT_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd216,__ERR) 1806 #define reg_wrc_MICRO_B_COM_RMI_PVT_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd216,wr_val) 1807 #define reg_rdc_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd217,__ERR) 1808 #define reg_wrc_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd217,wr_val) 1809 #define reg_rdc_MICRO_B_COM_RMI_RAM_CR_CRCSTATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd218,__ERR) 1810 #define reg_wrc_MICRO_B_COM_RMI_RAM_CR_CRCSTATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd218,wr_val) 1811 #define reg_rdc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd219,__ERR) 1812 #define reg_wrc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd219,wr_val) 1813 #define reg_rdc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd21a,__ERR) 1814 #define reg_wrc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd21a,wr_val) 1815 #define reg_rdc_MICRO_B_COM_RMI_MICRO_DEBUGGER_ID_LSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd21b,__ERR) 1816 #define reg_wrc_MICRO_B_COM_RMI_MICRO_DEBUGGER_ID_LSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd21b,wr_val) 1817 #define reg_rdc_MICRO_B_COM_RMI_MICRO_DEBUGGER_ID_MSW() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd21c,__ERR) 1818 #define reg_wrc_MICRO_B_COM_RMI_MICRO_DEBUGGER_ID_MSW(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd21c,wr_val) 1819 #define reg_rdc_MICRO_B_COM_RMI_MICRO_DEBUGGER_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd21e,__ERR) 1820 #define reg_wrc_MICRO_B_COM_RMI_MICRO_DEBUGGER_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd21e,wr_val) 1821 #define reg_rdc_MICRO_C_COM_RAM_ECCCONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd220,__ERR) 1822 #define reg_wrc_MICRO_C_COM_RAM_ECCCONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd220,wr_val) 1823 #define reg_rdc_MICRO_C_COM_RAM_ECCCONTROL1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd221,__ERR) 1824 #define reg_wrc_MICRO_C_COM_RAM_ECCCONTROL1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd221,wr_val) 1825 #define reg_rdc_MICRO_C_COM_RAM_ECCSTATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd222,__ERR) 1826 #define reg_wrc_MICRO_C_COM_RAM_ECCSTATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd222,wr_val) 1827 #define reg_rdc_MICRO_C_COM_RAM_ECCSTATUS1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd223,__ERR) 1828 #define reg_wrc_MICRO_C_COM_RAM_ECCSTATUS1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd223,wr_val) 1829 #define reg_rdc_MICRO_C_COM_RAM_ECCSTATUS2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd224,__ERR) 1830 #define reg_wrc_MICRO_C_COM_RAM_ECCSTATUS2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd224,wr_val) 1831 #define reg_rdc_MICRO_C_COM_RAM_TESTIFCONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd225,__ERR) 1832 #define reg_wrc_MICRO_C_COM_RAM_TESTIFCONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd225,wr_val) 1833 #define reg_rdc_MICRO_C_COM_RAM_TESTIFCONTROL1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd226,__ERR) 1834 #define reg_wrc_MICRO_C_COM_RAM_TESTIFCONTROL1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd226,wr_val) 1835 #define reg_rdc_MICRO_C_COM_RAM_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd227,__ERR) 1836 #define reg_wrc_MICRO_C_COM_RAM_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd227,wr_val) 1837 #define reg_rdc_MICRO_C_COM_RAM_CONTROL1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd228,__ERR) 1838 #define reg_wrc_MICRO_C_COM_RAM_CONTROL1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd228,wr_val) 1839 #define reg_rdc_MICRO_C_COM_RAM_CONTROL2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd22e,__ERR) 1840 #define reg_wrc_MICRO_C_COM_RAM_CONTROL2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd22e,wr_val) 1841 #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd22a,__ERR) 1842 #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd22a,wr_val) 1843 #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd229,__ERR) 1844 #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd229,wr_val) 1845 #define reg_rdc_MICRO_C_COM_RMI_PMI_IF_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd22b,__ERR) 1846 #define reg_wrc_MICRO_C_COM_RMI_PMI_IF_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd22b,wr_val) 1847 #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd22c,__ERR) 1848 #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd22c,wr_val) 1849 #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd22d,__ERR) 1850 #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd22d,wr_val) 1851 #define reg_rdc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd230,__ERR) 1852 #define reg_wrc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd230,wr_val) 1853 #define reg_rdc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd231,__ERR) 1854 #define reg_wrc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd231,wr_val) 1855 #define reg_rdc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd232,__ERR) 1856 #define reg_wrc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd232,wr_val) 1857 #define reg_rdc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd233,__ERR) 1858 #define reg_wrc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd233,wr_val) 1859 #define reg_rdc_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd240,__ERR) 1860 #define reg_wrc_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd240,wr_val) 1861 #define reg_rdc_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd241,__ERR) 1862 #define reg_wrc_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd241,wr_val) 1863 #define reg_rdc_MICRO_E_COM_MICRO_CORE_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd242,__ERR) 1864 #define reg_wrc_MICRO_E_COM_MICRO_CORE_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd242,wr_val) 1865 #define reg_rdc_MICRO_E_COM_MICRO_CORE_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd243,__ERR) 1866 #define reg_wrc_MICRO_E_COM_MICRO_CORE_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd243,wr_val) 1867 #define reg_rdc_MICRO_E_COM_MICRO_CORE_MBOX_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd244,__ERR) 1868 #define reg_wrc_MICRO_E_COM_MICRO_CORE_MBOX_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd244,wr_val) 1869 #define reg_rdc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd245,__ERR) 1870 #define reg_wrc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd245,wr_val) 1871 #define reg_rdc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd246,__ERR) 1872 #define reg_wrc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd246,wr_val) 1873 #define reg_rdc_MICRO_E_COM_MICRO_CORE_STATUS1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd247,__ERR) 1874 #define reg_wrc_MICRO_E_COM_MICRO_CORE_STATUS1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd247,wr_val) 1875 #define reg_rdc_MICRO_E_COM_MICRO_CORE_STATUS2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd248,__ERR) 1876 #define reg_wrc_MICRO_E_COM_MICRO_CORE_STATUS2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd248,wr_val) 1877 #define reg_rdc_MICRO_E_COM_MICRO_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd24d,__ERR) 1878 #define reg_wrc_MICRO_E_COM_MICRO_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd24d,wr_val) 1879 #define reg_rdc_MICRO_E_COM_MICRO_CORE_CFG_FW_API_DATA1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd24e,__ERR) 1880 #define reg_wrc_MICRO_E_COM_MICRO_CORE_CFG_FW_API_DATA1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd24e,wr_val) 1881 #define reg_rdc_PATT_GEN_COM_SEQ_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd120,__ERR) 1882 #define reg_wrc_PATT_GEN_COM_SEQ_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd120,wr_val) 1883 #define reg_rdc_PATT_GEN_COM_SEQ_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd121,__ERR) 1884 #define reg_wrc_PATT_GEN_COM_SEQ_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd121,wr_val) 1885 #define reg_rdc_PATT_GEN_COM_SEQ_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd122,__ERR) 1886 #define reg_wrc_PATT_GEN_COM_SEQ_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd122,wr_val) 1887 #define reg_rdc_PATT_GEN_COM_SEQ_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd123,__ERR) 1888 #define reg_wrc_PATT_GEN_COM_SEQ_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd123,wr_val) 1889 #define reg_rdc_PATT_GEN_COM_SEQ_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd124,__ERR) 1890 #define reg_wrc_PATT_GEN_COM_SEQ_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd124,wr_val) 1891 #define reg_rdc_PATT_GEN_COM_SEQ_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd125,__ERR) 1892 #define reg_wrc_PATT_GEN_COM_SEQ_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd125,wr_val) 1893 #define reg_rdc_PATT_GEN_COM_SEQ_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd126,__ERR) 1894 #define reg_wrc_PATT_GEN_COM_SEQ_6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd126,wr_val) 1895 #define reg_rdc_PATT_GEN_COM_SEQ_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd127,__ERR) 1896 #define reg_wrc_PATT_GEN_COM_SEQ_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd127,wr_val) 1897 #define reg_rdc_PATT_GEN_COM_SEQ_8() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd128,__ERR) 1898 #define reg_wrc_PATT_GEN_COM_SEQ_8(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd128,wr_val) 1899 #define reg_rdc_PATT_GEN_COM_SEQ_9() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd129,__ERR) 1900 #define reg_wrc_PATT_GEN_COM_SEQ_9(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd129,wr_val) 1901 #define reg_rdc_PATT_GEN_COM_SEQ_10() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12a,__ERR) 1902 #define reg_wrc_PATT_GEN_COM_SEQ_10(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12a,wr_val) 1903 #define reg_rdc_PATT_GEN_COM_SEQ_11() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12b,__ERR) 1904 #define reg_wrc_PATT_GEN_COM_SEQ_11(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12b,wr_val) 1905 #define reg_rdc_PATT_GEN_COM_SEQ_12() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12c,__ERR) 1906 #define reg_wrc_PATT_GEN_COM_SEQ_12(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12c,wr_val) 1907 #define reg_rdc_PATT_GEN_COM_SEQ_13() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12d,__ERR) 1908 #define reg_wrc_PATT_GEN_COM_SEQ_13(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12d,wr_val) 1909 #define reg_rdc_PATT_GEN_COM_SEQ_14() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd12e,__ERR) 1910 #define reg_wrc_PATT_GEN_COM_SEQ_14(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd12e,wr_val) 1911 #define reg_rdc_PLL_CAL_COM_CTL_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd147,__ERR) 1912 #define reg_wrc_PLL_CAL_COM_CTL_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd147,wr_val) 1913 #define reg_rdc_PLL_CAL_COM_CTL_STATUS_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd148,__ERR) 1914 #define reg_wrc_PLL_CAL_COM_CTL_STATUS_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd148,wr_val) 1915 #define reg_rd_RX_CKRST_CTRL_TSC_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a1,__ERR) 1916 #define reg_wr_RX_CKRST_CTRL_TSC_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1a1,wr_val) 1917 #define reg_rd_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a7,__ERR) 1918 #define reg_wr_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1a7,wr_val) 1919 #define reg_rd_RX_CKRST_CTRL_TSC_RX_LANE_DEBUG_RESET_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a4,__ERR) 1920 #define reg_wr_RX_CKRST_CTRL_TSC_RX_LANE_DEBUG_RESET_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1a4,wr_val) 1921 #define reg_rd_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a2,__ERR) 1922 #define reg_wr_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1a2,wr_val) 1923 #define reg_rd_RX_CKRST_CTRL_TSC_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a3,__ERR) 1924 #define reg_wr_RX_CKRST_CTRL_TSC_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1a3,wr_val) 1925 #define reg_rd_RX_CKRST_CTRL_TSC_RX_PMD_LANE_MODE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1a8,__ERR) 1926 #define reg_wr_RX_CKRST_CTRL_TSC_RX_PMD_LANE_MODE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1a8,wr_val) 1927 #define reg_rd_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1ad,__ERR) 1928 #define reg_wr_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1ad,wr_val) 1929 #define reg_rd_RX_CKRST_CTRL_TSC_LANE_CFG_FWAPI_DATA1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1ae,__ERR) 1930 #define reg_wr_RX_CKRST_CTRL_TSC_LANE_CFG_FWAPI_DATA1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1ae,wr_val) 1931 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c0,__ERR) 1932 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c0,wr_val) 1933 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c1,__ERR) 1934 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c1,wr_val) 1935 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_PLL_SELECT_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c7,__ERR) 1936 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_PLL_SELECT_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c7,wr_val) 1937 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_LN_S_RSTB_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1ce,__ERR) 1938 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_LN_S_RSTB_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1ce,wr_val) 1939 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c3,__ERR) 1940 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c3,wr_val) 1941 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_UC_ACK_LANE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c5,__ERR) 1942 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_UC_ACK_LANE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c5,wr_val) 1943 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_DP_RESET_STATE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c9,__ERR) 1944 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c9,wr_val) 1945 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1c6,__ERR) 1946 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1c6,wr_val) 1947 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_MULTICAST_MASK_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1ca,__ERR) 1948 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_MULTICAST_MASK_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1ca,wr_val) 1949 #define reg_rd_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_STATUS_MC_MASK() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1cb,__ERR) 1950 #define reg_wr_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1cb,wr_val) 1951 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b0,__ERR) 1952 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b0,wr_val) 1953 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b1,__ERR) 1954 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b1,wr_val) 1955 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_PLL_SELECT_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b7,__ERR) 1956 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_PLL_SELECT_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b7,wr_val) 1957 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LN_S_RSTB_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0be,__ERR) 1958 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LN_S_RSTB_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0be,wr_val) 1959 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b3,__ERR) 1960 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b3,wr_val) 1961 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_UC_ACK_LANE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b5,__ERR) 1962 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_UC_ACK_LANE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b5,wr_val) 1963 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_DP_RESET_STATE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b9,__ERR) 1964 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b9,wr_val) 1965 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0b6,__ERR) 1966 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0b6,wr_val) 1967 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_MULTICAST_MASK_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0ba,__ERR) 1968 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_MULTICAST_MASK_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0ba,wr_val) 1969 #define reg_rd_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_STATUS_MC_MASK() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0bb,__ERR) 1970 #define reg_wr_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0bb,wr_val) 1971 #define reg_rd_SIGDET_SDCTRL_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0e2,__ERR) 1972 #define reg_wr_SIGDET_SDCTRL_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0e2,wr_val) 1973 #define reg_rd_SIGDET_SDSTATUS_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0e8,__ERR) 1974 #define reg_wr_SIGDET_SDSTATUS_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0e8,wr_val) 1975 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd310,__ERR) 1976 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd310,wr_val) 1977 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd311,__ERR) 1978 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd311,wr_val) 1979 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd315,__ERR) 1980 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd315,wr_val) 1981 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_LO() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd316,__ERR) 1982 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_LO(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd316,wr_val) 1983 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31e,__ERR) 1984 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd31e,wr_val) 1985 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31d,__ERR) 1986 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd31d,wr_val) 1987 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31c,__ERR) 1988 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd31c,wr_val) 1989 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31b,__ERR) 1990 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd31b,wr_val) 1991 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd31a,__ERR) 1992 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd31a,wr_val) 1993 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd319,__ERR) 1994 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd319,wr_val) 1995 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd318,__ERR) 1996 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd318,wr_val) 1997 #define reg_rdc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd317,__ERR) 1998 #define reg_wrc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd317,wr_val) 1999 #define reg_rd_TLB_RX_PRBS_CHK_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd161,__ERR) 2000 #define reg_wr_TLB_RX_PRBS_CHK_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd161,wr_val) 2001 #define reg_rd_TLB_RX_PRBS_CHK_CNT_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd160,__ERR) 2002 #define reg_wr_TLB_RX_PRBS_CHK_CNT_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd160,wr_val) 2003 #define reg_rd_TLB_RX_DIG_LPBK_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd162,__ERR) 2004 #define reg_wr_TLB_RX_DIG_LPBK_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd162,wr_val) 2005 #define reg_rd_TLB_RX_RXMISC_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd163,__ERR) 2006 #define reg_wr_TLB_RX_RXMISC_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd163,wr_val) 2007 #define reg_rd_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd164,__ERR) 2008 #define reg_wr_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd164,wr_val) 2009 #define reg_rd_TLB_RX_DIG_LPBK_PD_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd168,__ERR) 2010 #define reg_wr_TLB_RX_DIG_LPBK_PD_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd168,wr_val) 2011 #define reg_rd_TLB_RX_PRBS_CHK_LOCK_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd169,__ERR) 2012 #define reg_wr_TLB_RX_PRBS_CHK_LOCK_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd169,wr_val) 2013 #define reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd16a,__ERR) 2014 #define reg_wr_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd16a,wr_val) 2015 #define reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd16b,__ERR) 2016 #define reg_wr_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd16b,wr_val) 2017 #define reg_rd_TLB_RX_PMD_RX_LOCK_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd16c,__ERR) 2018 #define reg_wr_TLB_RX_PMD_RX_LOCK_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd16c,wr_val) 2019 #define reg_rd_TLB_RX_DBG_PMD_RX_LOCK_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd166,__ERR) 2020 #define reg_wr_TLB_RX_DBG_PMD_RX_LOCK_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd166,wr_val) 2021 #define reg_rd_TLB_RX_UC_PMD_RX_LOCK_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd167,__ERR) 2022 #define reg_wr_TLB_RX_UC_PMD_RX_LOCK_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd167,wr_val) 2023 #define reg_rd_TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd16d,__ERR) 2024 #define reg_wr_TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd16d,wr_val) 2025 #define reg_rd_TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd16e,__ERR) 2026 #define reg_wr_TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd16e,wr_val) 2027 #define reg_rd_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd165,__ERR) 2028 #define reg_wr_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd165,wr_val) 2029 #define reg_rd_TLB_RX_C_TLB_RX_C_CONFIG_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f0,__ERR) 2030 #define reg_wr_TLB_RX_C_TLB_RX_C_CONFIG_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f0,wr_val) 2031 #define reg_rd_TLB_RX_C_TLB_RX_C_CONFIG_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f1,__ERR) 2032 #define reg_wr_TLB_RX_C_TLB_RX_C_CONFIG_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f1,wr_val) 2033 #define reg_rd_TLB_RX_C_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f5,__ERR) 2034 #define reg_wr_TLB_RX_C_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f5,wr_val) 2035 #define reg_rd_TLB_RX_C_NUM_ERRORS_IN_FEC_FRAMES_STATUS_LO() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f6,__ERR) 2036 #define reg_wr_TLB_RX_C_NUM_ERRORS_IN_FEC_FRAMES_STATUS_LO(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f6,wr_val) 2037 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fe,__ERR) 2038 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1fe,wr_val) 2039 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fd,__ERR) 2040 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1fd,wr_val) 2041 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fc,__ERR) 2042 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1fc,wr_val) 2043 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fb,__ERR) 2044 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1fb,wr_val) 2045 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1fa,__ERR) 2046 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1fa,wr_val) 2047 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f9,__ERR) 2048 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f9,wr_val) 2049 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f8,__ERR) 2050 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f8,wr_val) 2051 #define reg_rd_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1f7,__ERR) 2052 #define reg_wr_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1f7,wr_val) 2053 #define reg_rd_TLB_TX_PATT_GEN_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd170,__ERR) 2054 #define reg_wr_TLB_TX_PATT_GEN_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd170,wr_val) 2055 #define reg_rd_TLB_TX_PRBS_GEN_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd171,__ERR) 2056 #define reg_wr_TLB_TX_PRBS_GEN_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd171,wr_val) 2057 #define reg_rd_TLB_TX_RMT_LPBK_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd172,__ERR) 2058 #define reg_wr_TLB_TX_RMT_LPBK_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd172,wr_val) 2059 #define reg_rd_TLB_TX_TXMISC_CONFIG() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd173,__ERR) 2060 #define reg_wr_TLB_TX_TXMISC_CONFIG(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd173,wr_val) 2061 #define reg_rd_TLB_TX_TLB_TX_PAM4_CONFIG_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd175,__ERR) 2062 #define reg_wr_TLB_TX_TLB_TX_PAM4_CONFIG_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd175,wr_val) 2063 #define reg_rd_TLB_TX_RMT_LPBK_PD_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd178,__ERR) 2064 #define reg_wr_TLB_TX_RMT_LPBK_PD_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd178,wr_val) 2065 #define reg_rd_TX_CKRST_CTRL_TSC_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b1,__ERR) 2066 #define reg_wr_TX_CKRST_CTRL_TSC_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1b1,wr_val) 2067 #define reg_rd_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b7,__ERR) 2068 #define reg_wr_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1b7,wr_val) 2069 #define reg_rd_TX_CKRST_CTRL_TSC_TX_LANE_DEBUG_RESET_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b4,__ERR) 2070 #define reg_wr_TX_CKRST_CTRL_TSC_TX_LANE_DEBUG_RESET_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1b4,wr_val) 2071 #define reg_rd_TX_CKRST_CTRL_TSC_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b2,__ERR) 2072 #define reg_wr_TX_CKRST_CTRL_TSC_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1b2,wr_val) 2073 #define reg_rd_TX_CKRST_CTRL_TSC_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b3,__ERR) 2074 #define reg_wr_TX_CKRST_CTRL_TSC_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1b3,wr_val) 2075 #define reg_rd_TX_CKRST_CTRL_TSC_TX_PMD_LANE_MODE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1b8,__ERR) 2076 #define reg_wr_TX_CKRST_CTRL_TSC_TX_PMD_LANE_MODE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1b8,wr_val) 2077 #define reg_rd_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_MISC_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1bd,__ERR) 2078 #define reg_wr_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_MISC_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1bd,wr_val) 2079 #define reg_rd_TX_FED_TXFIR_MICRO_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd130,__ERR) 2080 #define reg_wr_TX_FED_TXFIR_MICRO_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd130,wr_val) 2081 #define reg_rd_TX_FED_TXFIR_MISC_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd131,__ERR) 2082 #define reg_wr_TX_FED_TXFIR_MISC_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd131,wr_val) 2083 #define reg_rd_TX_FED_TXFIR_MISC_STATUS0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd132,__ERR) 2084 #define reg_wr_TX_FED_TXFIR_MISC_STATUS0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd132,wr_val) 2085 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd133,__ERR) 2086 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd133,wr_val) 2087 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd134,__ERR) 2088 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd134,wr_val) 2089 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd135,__ERR) 2090 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd135,wr_val) 2091 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL3() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd136,__ERR) 2092 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL3(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd136,wr_val) 2093 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd137,__ERR) 2094 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd137,wr_val) 2095 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd138,__ERR) 2096 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd138,wr_val) 2097 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL6() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd139,__ERR) 2098 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL6(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd139,wr_val) 2099 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL7() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd13a,__ERR) 2100 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL7(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd13a,wr_val) 2101 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL8() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd13b,__ERR) 2102 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL8(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd13b,wr_val) 2103 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL9() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd13c,__ERR) 2104 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL9(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd13c,wr_val) 2105 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL10() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd13d,__ERR) 2106 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL10(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd13d,wr_val) 2107 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL11() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd13e,__ERR) 2108 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL11(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd13e,wr_val) 2109 #define reg_rd_TX_PI_TSC_TXPICONTROL_0() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0a0,__ERR) 2110 #define reg_wr_TX_PI_TSC_TXPICONTROL_0(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0a0,wr_val) 2111 #define reg_rd_TX_PI_TSC_TXPICONTROL_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0a1,__ERR) 2112 #define reg_wr_TX_PI_TSC_TXPICONTROL_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0a1,wr_val) 2113 #define reg_rd_TX_PI_TSC_TXPICONTROL_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0a2,__ERR) 2114 #define reg_wr_TX_PI_TSC_TXPICONTROL_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0a2,wr_val) 2115 #define reg_rd_TX_PI_TSC_TXPICONTROL_5() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0a5,__ERR) 2116 #define reg_wr_TX_PI_TSC_TXPICONTROL_5(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0a5,wr_val) 2117 #define reg_rd_TX_PI_TSC_TXPISTATUS_1() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0a9,__ERR) 2118 #define reg_wr_TX_PI_TSC_TXPISTATUS_1(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0a9,wr_val) 2119 #define reg_rd_TX_PI_TSC_TXPISTATUS_2() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0aa,__ERR) 2120 #define reg_wr_TX_PI_TSC_TXPISTATUS_2(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0aa,wr_val) 2121 #define reg_rd_TX_PI_TSC_TXPISTATUS_4() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd0ac,__ERR) 2122 #define reg_wr_TX_PI_TSC_TXPISTATUS_4(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd0ac,wr_val) 2123 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d0,__ERR) 2124 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d0,wr_val) 2125 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d1,__ERR) 2126 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d1,wr_val) 2127 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_PLL_SELECT_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d7,__ERR) 2128 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_PLL_SELECT_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d7,wr_val) 2129 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_LN_S_RSTB_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1de,__ERR) 2130 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_LN_S_RSTB_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1de,wr_val) 2131 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d3,__ERR) 2132 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d3,wr_val) 2133 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_UC_ACK_LANE_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d5,__ERR) 2134 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_UC_ACK_LANE_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d5,wr_val) 2135 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_DP_RESET_STATE_STATUS() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d9,__ERR) 2136 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d9,wr_val) 2137 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1d6,__ERR) 2138 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1d6,wr_val) 2139 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_MULTICAST_MASK_CONTROL() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1da,__ERR) 2140 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_MULTICAST_MASK_CONTROL(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1da,wr_val) 2141 #define reg_rd_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_STATUS_MC_MASK() _blackhawk_tsc_pmd_rde_reg(sa__, 0xd1db,__ERR) 2142 #define reg_wr_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) blackhawk_tsc_pmd_wr_reg(sa__, 0xd1db,wr_val) 2143 2144 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_rescal_aux(reg_value) extract_field((reg_value),15,12) 2145 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_refclk_1x(reg_value) extract_field((reg_value),11,11) 2146 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_lpf_rz(reg_value) extract_field((reg_value),10,9) 2147 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_fp3_rh(reg_value) extract_field((reg_value),8,8) 2148 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_fp3_ctrl(reg_value) extract_field((reg_value),7,4) 2149 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_cp_cmfdbk_iadj(reg_value) extract_field((reg_value),3,2) 2150 #define exc_AMS_PLL_COM_PLL_CONTROL_0__ams_pll_set_clk4pcs(reg_value) extract_field((reg_value),1,0) 2151 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_enable_ftune(reg_value) extract_field((reg_value),15,15) 2152 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_reset(reg_value) extract_field((reg_value),14,14) 2153 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_ivco(reg_value) extract_field((reg_value),13,11) 2154 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_test_vco2_cssw(reg_value) extract_field((reg_value),10,10) 2155 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_vcoictrl(reg_value) extract_field((reg_value),9,8) 2156 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_vco2_15g(reg_value) extract_field((reg_value),7,7) 2157 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_muxdiv_ictrl_1(reg_value) extract_field((reg_value),6,6) 2158 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_vco_res_cs(reg_value) extract_field((reg_value),5,5) 2159 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_muxdiv_ictrl_0(reg_value) extract_field((reg_value),4,4) 2160 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_drv_hv_disable(reg_value) extract_field((reg_value),3,3) 2161 #define exc_AMS_PLL_COM_PLL_CONTROL_1__ams_pll_comp_thresh(reg_value) extract_field((reg_value),2,0) 2162 #define exc_AMS_PLL_COM_PLL_CONTROL_2__ams_pll_iqp(reg_value) extract_field((reg_value),3,0) 2163 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_force_rescal(reg_value) extract_field((reg_value),15,15) 2164 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_force_kvh_bw(reg_value) extract_field((reg_value),14,14) 2165 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_kvh_force(reg_value) extract_field((reg_value),13,12) 2166 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_vddr_bgb(reg_value) extract_field((reg_value),11,11) 2167 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_test_vddr4bg(reg_value) extract_field((reg_value),10,10) 2168 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_pll2rx_clkbw(reg_value) extract_field((reg_value),9,8) 2169 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_bgr_ctatadj(reg_value) extract_field((reg_value),7,4) 2170 #define exc_AMS_PLL_COM_PLL_CONTROL_4__ams_pll_bgr_ptatadj(reg_value) extract_field((reg_value),3,0) 2171 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_refclk_doubler(reg_value) extract_field((reg_value),15,15) 2172 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_doubler_res(reg_value) extract_field((reg_value),14,12) 2173 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_set_clk4pcs_msb(reg_value) extract_field((reg_value),11,11) 2174 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_doubler_cap(reg_value) extract_field((reg_value),10,8) 2175 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_clk4sync_en(reg_value) extract_field((reg_value),7,7) 2176 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_clk4sync_div(reg_value) extract_field((reg_value),6,6) 2177 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_rterm300(reg_value) extract_field((reg_value),5,5) 2178 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_rtermhiz(reg_value) extract_field((reg_value),4,4) 2179 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_rterm400(reg_value) extract_field((reg_value),3,3) 2180 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_div4(reg_value) extract_field((reg_value),2,2) 2181 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_div2(reg_value) extract_field((reg_value),1,1) 2182 #define exc_AMS_PLL_COM_PLL_CONTROL_6__ams_pll_rterm200(reg_value) extract_field((reg_value),0,0) 2183 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_mix3p1cr_ptatadj(reg_value) extract_field((reg_value),15,11) 2184 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_mix3p1cr_ctatadj(reg_value) extract_field((reg_value),10,6) 2185 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_vcodiv_refout(reg_value) extract_field((reg_value),5,5) 2186 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_ndiv_frac_valid(reg_value) extract_field((reg_value),4,4) 2187 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_pfd_ref_skew(reg_value) extract_field((reg_value),3,3) 2188 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_pfd_fb_skew(reg_value) extract_field((reg_value),2,2) 2189 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_pfd_skew_enlarge(reg_value) extract_field((reg_value),1,1) 2190 #define exc_AMS_PLL_COM_PLL_CONTROL_7__ams_pll_test_fracn_en(reg_value) extract_field((reg_value),0,0) 2191 #define exc_AMS_PLL_COM_PLL_CONTROL_8__ams_pll_fracn_div(reg_value) extract_field((reg_value),15,0) 2192 #define exc_AMS_PLL_COM_PLL_CONTROL_9__ams_pll_fracn_sel(reg_value) extract_field((reg_value),15,15) 2193 #define exc_AMS_PLL_COM_PLL_CONTROL_9__ams_pll_ditheren(reg_value) extract_field((reg_value),14,14) 2194 #define exc_AMS_PLL_COM_PLL_CONTROL_9__ams_pll_fracn_ndiv_int(reg_value) extract_field((reg_value),13,4) 2195 #define exc_AMS_PLL_COM_PLL_CONTROL_9__ams_pll_fracn_bypass(reg_value) extract_field((reg_value),3,3) 2196 #define exc_AMS_PLL_COM_PLL_CONTROL_9__ams_pll_fracn_divrange(reg_value) extract_field((reg_value),2,2) 2197 #define exc_AMS_PLL_COM_PLL_CONTROL_9__ams_pll_fracn_div_17_16(reg_value) extract_field((reg_value),1,0) 2198 #define exc_AMS_PLL_COM_PLL_INTCTRL__ams_pll_pwrdn(reg_value) extract_field((reg_value),2,2) 2199 #define exc_AMS_PLL_COM_PLL_INTCTRL__ams_pll_div4_2_sel(reg_value) extract_field((reg_value),1,1) 2200 #define exc_AMS_PLL_COM_PLL_INTCTRL__ams_pll_rterm_sel(reg_value) extract_field((reg_value),0,0) 2201 #define exc_AMS_PLL_COM_PLL_STATUS__ams_pll_kvh(reg_value) extract_field((reg_value),15,14) 2202 #define exc_AMS_PLL_COM_PLL_STATUS__ams_pll_range(reg_value) extract_field((reg_value),13,6) 2203 #define exc_AMS_PLL_COM_PLL_STATUS__ams_pll_low(reg_value) extract_field((reg_value),5,5) 2204 #define exc_AMS_PLL_COM_PLL_STATUS__ams_pll_mode(reg_value) extract_field((reg_value),4,0) 2205 #define ex_AMS_RX_RXCONTROL_0__ams_rx_pf_max_bw(reg_value) extract_field((reg_value),9,9) 2206 #define ex_AMS_RX_RXCONTROL_2__ams_rx_vga3_ind(reg_value) extract_field((reg_value),14,14) 2207 #define ex_AMS_RX_RXCONTROL_4__ams_rx_vga1_rescal_mux(reg_value) extract_field((reg_value),15,11) 2208 #define ex_AMS_RX_RXCONTROL_4__ams_rx_vga0_rescal_mux(reg_value) extract_field((reg_value),10,6) 2209 #define ex_AMS_RX_RXCONTROL_5__ams_rx_sd_cal_pos(reg_value) extract_field((reg_value),10,8) 2210 #define ex_AMS_RX_RXCONTROL_5__ams_rx_sd_cal_neg(reg_value) extract_field((reg_value),7,5) 2211 #define ex_AMS_RX_RXCONTROL_5__ams_rx_vga2_rescal_mux(reg_value) extract_field((reg_value),4,0) 2212 #define ex_AMS_RX_RXCONTROL_8__ams_rx_dac4ck_phs_q(reg_value) extract_field((reg_value),15,12) 2213 #define ex_AMS_RX_RXCONTROL_8__ams_rx_dac4ck_phs_i(reg_value) extract_field((reg_value),11,8) 2214 #define ex_AMS_RX_RXCONTROL_8__ams_rx_dac4ck_lms_q(reg_value) extract_field((reg_value),7,4) 2215 #define ex_AMS_RX_RXCONTROL_8__ams_rx_dac4ck_lms_i(reg_value) extract_field((reg_value),3,0) 2216 #define ex_AMS_RX_RXCONTROL_9__ams_rx_dac4ck_dat_q(reg_value) extract_field((reg_value),7,4) 2217 #define ex_AMS_RX_RXCONTROL_9__ams_rx_dac4ck_dat_i(reg_value) extract_field((reg_value),3,0) 2218 #define ex_AMS_RX_RXCONTROL_10__ams_rx_vga_bw_ctrl_ind(reg_value) extract_field((reg_value),15,14) 2219 #define ex_AMS_RX_RXCONTROL_10__ams_rx_vga01_bw_ctrl_cap(reg_value) extract_field((reg_value),13,12) 2220 #define ex_AMS_RX_RXCONTROL_10__ams_rx_vga2_bw_ctrl_cap(reg_value) extract_field((reg_value),11,11) 2221 #define ex_AMS_RX_RXCONTROL_10__ams_rx_pf3_max_bw(reg_value) extract_field((reg_value),8,8) 2222 #define ex_AMS_RX_RXCONTROL_10__ams_rx_pf3_ctrl(reg_value) extract_field((reg_value),3,0) 2223 #define ex_AMS_TX_TXCONTROL_0__ams_tx_ticksel(reg_value) extract_field((reg_value),7,6) 2224 #define ex_AMS_TX_TXCONTROL_3__ams_tx_spare_63_56(reg_value) extract_field((reg_value),15,8) 2225 #define ex_AMS_TX_TXCONTROL_3__ams_tx_sel_txmaster(reg_value) extract_field((reg_value),7,7) 2226 #define ex_AMS_TX_TXCONTROL_3__ams_tx_spare_54(reg_value) extract_field((reg_value),6,6) 2227 #define ex_AMS_TX_TXCONTROL_3__ams_tx_pdet_mode(reg_value) extract_field((reg_value),5,5) 2228 #define ex_AMS_TX_TXCONTROL_3__ams_tx_spare_52_48(reg_value) extract_field((reg_value),4,0) 2229 #define ex_AMS_TX_TXSTATUS__ams_tx_lane_id(reg_value) extract_field((reg_value),15,14) 2230 #define ex_AMS_TX_TXSTATUS__ams_tx_spare_13(reg_value) extract_field((reg_value),13,13) 2231 #define ex_AMS_TX_TXSTATUS__ams_tx_drv_hv_disable(reg_value) extract_field((reg_value),12,12) 2232 #define ex_AMS_TX_TXSTATUS__ams_tx_ana_rescal(reg_value) extract_field((reg_value),11,8) 2233 #define ex_AMS_TX_TXSTATUS__ams_tx_version_id(reg_value) extract_field((reg_value),7,0) 2234 #define exc_CORE_PLL_COM_PMD_CORE_MODE_STATUS__pmd_core_mode(reg_value) extract_field((reg_value),15,0) 2235 #define exc_CORE_PLL_COM_RESET_CONTROL_PLL_DP__pmd_core_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 2236 #define exc_CORE_PLL_COM_TOP_USER_CONTROL__core_hw_fw_handshake_disable(reg_value) extract_field((reg_value),15,15) 2237 #define exc_CORE_PLL_COM_TOP_USER_CONTROL__afe_s_pll_pwrdn(reg_value) extract_field((reg_value),14,14) 2238 #define exc_CORE_PLL_COM_TOP_USER_CONTROL__core_dp_s_rstb(reg_value) extract_field((reg_value),13,13) 2239 #define exc_CORE_PLL_COM_UC_ACK_CORE_CONTROL__uc_ack_core_dp_reset(reg_value) extract_field((reg_value),1,1) 2240 #define exc_CORE_PLL_COM_UC_ACK_CORE_CONTROL__uc_ack_core_cfg_done(reg_value) extract_field((reg_value),0,0) 2241 #define exc_CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS__core_dp_reset_state(reg_value) extract_field((reg_value),2,0) 2242 #define exc_CORE_PLL_COM_CORE_PLL_COM_STATUS_2__pll_pwrdn_or(reg_value) extract_field((reg_value),0,0) 2243 #define exc_CORE_PLL_COM_PLL_UC_CORE_CONFIG__pll_uc_core_config_core_cfg_from_pcs(reg_value) extract_field((reg_value),8,8) 2244 #define exc_CORE_PLL_COM_PLL_UC_CORE_CONFIG__pll_uc_core_config_vco_rate(reg_value) extract_field((reg_value),7,0) 2245 #define exc_CORE_PLL_COM_PLL_CFG_FWAPI_DATA1__pll_cfg_fwapi_data1(reg_value) extract_field((reg_value),15,0) 2246 #define exc_DIG_COM_REVID0__revid_rev_letter(reg_value) extract_field((reg_value),15,14) 2247 #define exc_DIG_COM_REVID0__revid_rev_number(reg_value) extract_field((reg_value),13,11) 2248 #define exc_DIG_COM_REVID0__revid_bonding(reg_value) extract_field((reg_value),10,9) 2249 #define exc_DIG_COM_REVID0__revid_process(reg_value) extract_field((reg_value),8,6) 2250 #define exc_DIG_COM_REVID0__revid_model(reg_value) extract_field((reg_value),5,0) 2251 #define exc_DIG_COM_REVID1__revid_multiplicity(reg_value) extract_field((reg_value),15,12) 2252 #define exc_DIG_COM_REVID1__revid_mdio(reg_value) extract_field((reg_value),5,5) 2253 #define exc_DIG_COM_REVID1__revid_micro(reg_value) extract_field((reg_value),4,4) 2254 #define exc_DIG_COM_REVID1__revid_cl72(reg_value) extract_field((reg_value),3,3) 2255 #define exc_DIG_COM_REVID1__revid_pir(reg_value) extract_field((reg_value),2,2) 2256 #define exc_DIG_COM_REVID1__revid_llp(reg_value) extract_field((reg_value),1,1) 2257 #define exc_DIG_COM_REVID1__revid_eee(reg_value) extract_field((reg_value),0,0) 2258 #define exc_DIG_COM_REVID2__revid2(reg_value) extract_field((reg_value),3,0) 2259 #define exc_DIG_COM_RESET_CONTROL_PMD__uc_active(reg_value) extract_field((reg_value),1,1) 2260 #define exc_DIG_COM_RESET_CONTROL_PMD__core_s_rstb(reg_value) extract_field((reg_value),0,0) 2261 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__disable_ack_timeout(reg_value) extract_field((reg_value),15,15) 2262 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_mdio_trans_pkill(reg_value) extract_field((reg_value),5,5) 2263 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc(reg_value) extract_field((reg_value),4,4) 2264 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc_val(reg_value) extract_field((reg_value),3,3) 2265 #define exc_DIG_COM_MASKDATA_REG__maskdata(reg_value) extract_field((reg_value),15,0) 2266 #define exc_DIG_COM_TOP_USER_CONTROL_0__mdio_fast_mode_frc(reg_value) extract_field((reg_value),12,12) 2267 #define exc_DIG_COM_TOP_USER_CONTROL_0__mdio_fast_mode_frc_val(reg_value) extract_field((reg_value),11,11) 2268 #define exc_DIG_COM_TOP_USER_CONTROL_0__maskdata_bus_assign(reg_value) extract_field((reg_value),10,10) 2269 #define exc_DIG_COM_TOP_USER_CONTROL_0__heartbeat_count_1us(reg_value) extract_field((reg_value),9,0) 2270 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released(reg_value) extract_field((reg_value),14,14) 2271 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released_index(reg_value) extract_field((reg_value),12,8) 2272 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released(reg_value) extract_field((reg_value),15,15) 2273 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released_index(reg_value) extract_field((reg_value),7,3) 2274 #define exc_DIG_COM_B_LANE_ADDR_0__tx_lane_addr_0(reg_value) extract_field((reg_value),12,8) 2275 #define exc_DIG_COM_B_LANE_ADDR_0__rx_lane_addr_0(reg_value) extract_field((reg_value),4,0) 2276 #define exc_DIG_COM_B_LANE_ADDR_1__tx_lane_addr_1(reg_value) extract_field((reg_value),12,8) 2277 #define exc_DIG_COM_B_LANE_ADDR_1__rx_lane_addr_1(reg_value) extract_field((reg_value),4,0) 2278 #define exc_DIG_COM_B_LANE_ADDR_2__tx_lane_addr_2(reg_value) extract_field((reg_value),12,8) 2279 #define exc_DIG_COM_B_LANE_ADDR_2__rx_lane_addr_2(reg_value) extract_field((reg_value),4,0) 2280 #define exc_DIG_COM_B_LANE_ADDR_3__tx_lane_addr_3(reg_value) extract_field((reg_value),12,8) 2281 #define exc_DIG_COM_B_LANE_ADDR_3__rx_lane_addr_3(reg_value) extract_field((reg_value),4,0) 2282 #define exc_DIG_COM_B_LANE_ADDR_4__tx_lane_addr_4(reg_value) extract_field((reg_value),12,8) 2283 #define exc_DIG_COM_B_LANE_ADDR_4__rx_lane_addr_4(reg_value) extract_field((reg_value),4,0) 2284 #define exc_DIG_COM_B_LANE_ADDR_5__tx_lane_addr_5(reg_value) extract_field((reg_value),12,8) 2285 #define exc_DIG_COM_B_LANE_ADDR_5__rx_lane_addr_5(reg_value) extract_field((reg_value),4,0) 2286 #define exc_DIG_COM_B_LANE_ADDR_6__tx_lane_addr_6(reg_value) extract_field((reg_value),12,8) 2287 #define exc_DIG_COM_B_LANE_ADDR_6__rx_lane_addr_6(reg_value) extract_field((reg_value),4,0) 2288 #define exc_DIG_COM_B_LANE_ADDR_7__tx_lane_addr_7(reg_value) extract_field((reg_value),12,8) 2289 #define exc_DIG_COM_B_LANE_ADDR_7__rx_lane_addr_7(reg_value) extract_field((reg_value),4,0) 2290 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_supp_info(reg_value) extract_field_signed((reg_value),15,8) 2291 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_ready_for_cmd(reg_value) extract_field((reg_value),7,7) 2292 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_error_found(reg_value) extract_field((reg_value),6,6) 2293 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_gp_uc_req(reg_value) extract_field((reg_value),5,0) 2294 #define ex_DSC_A_DSC_SCRATCH__uc_dsc_data(reg_value) extract_field((reg_value),15,0) 2295 #define ex_DSC_A_BLW_STATUS_1_TYPE__blw_gain(reg_value) extract_field_signed((reg_value),14,0) 2296 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_1__rxa_slicer_offset_adj_cal_d5(reg_value) extract_field_signed((reg_value),13,8) 2297 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_1__rxa_slicer_offset_adj_cal_d4(reg_value) extract_field_signed((reg_value),5,0) 2298 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_2__rxa_slicer_offset_adj_cal_d3(reg_value) extract_field_signed((reg_value),13,8) 2299 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_2__rxa_slicer_offset_adj_cal_d2(reg_value) extract_field_signed((reg_value),5,0) 2300 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_3__rxa_slicer_offset_adj_cal_d1(reg_value) extract_field_signed((reg_value),13,8) 2301 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_3__rxa_slicer_offset_adj_cal_d0(reg_value) extract_field_signed((reg_value),5,0) 2302 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_4__rxa_slicer_offset_adj_cal_p2(reg_value) extract_field_signed((reg_value),13,8) 2303 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_4__rxa_slicer_offset_adj_cal_p1(reg_value) extract_field_signed((reg_value),5,0) 2304 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_5__rxa_slicer_offset_adj_cal_p0(reg_value) extract_field_signed((reg_value),13,8) 2305 #define ex_DSC_AFE1_RXA_SLICER_OFFSET_ADJ_5__rxa_slicer_offset_adj_cal_lms(reg_value) extract_field_signed((reg_value),5,0) 2306 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_1__rxb_slicer_offset_adj_cal_d5(reg_value) extract_field_signed((reg_value),13,8) 2307 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_1__rxb_slicer_offset_adj_cal_d4(reg_value) extract_field_signed((reg_value),5,0) 2308 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_2__rxb_slicer_offset_adj_cal_d3(reg_value) extract_field_signed((reg_value),13,8) 2309 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_2__rxb_slicer_offset_adj_cal_d2(reg_value) extract_field_signed((reg_value),5,0) 2310 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_3__rxb_slicer_offset_adj_cal_d1(reg_value) extract_field_signed((reg_value),13,8) 2311 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_3__rxb_slicer_offset_adj_cal_d0(reg_value) extract_field_signed((reg_value),5,0) 2312 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_4__rxb_slicer_offset_adj_cal_p2(reg_value) extract_field_signed((reg_value),13,8) 2313 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_4__rxb_slicer_offset_adj_cal_p1(reg_value) extract_field_signed((reg_value),5,0) 2314 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_5__rxb_slicer_offset_adj_cal_p0(reg_value) extract_field_signed((reg_value),13,8) 2315 #define ex_DSC_AFE1_RXB_SLICER_OFFSET_ADJ_5__rxb_slicer_offset_adj_cal_lms(reg_value) extract_field_signed((reg_value),5,0) 2316 #define ex_DSC_AFE2_RX_DFE_TAP4_AB__rxa_dfe_tap4(reg_value) extract_field_signed((reg_value),9,5) 2317 #define ex_DSC_AFE2_RX_DFE_TAP4_AB__rxb_dfe_tap4(reg_value) extract_field_signed((reg_value),4,0) 2318 #define ex_DSC_AFE2_RX_DFE_TAP4_CD__rxc_dfe_tap4(reg_value) extract_field_signed((reg_value),9,5) 2319 #define ex_DSC_AFE2_RX_DFE_TAP4_CD__rxd_dfe_tap4(reg_value) extract_field_signed((reg_value),4,0) 2320 #define ex_DSC_AFE2_RX_DFE_TAP5_ABCD__rxa_dfe_tap5(reg_value) extract_field_signed((reg_value),15,12) 2321 #define ex_DSC_AFE2_RX_DFE_TAP5_ABCD__rxb_dfe_tap5(reg_value) extract_field_signed((reg_value),11,8) 2322 #define ex_DSC_AFE2_RX_DFE_TAP5_ABCD__rxc_dfe_tap5(reg_value) extract_field_signed((reg_value),7,4) 2323 #define ex_DSC_AFE2_RX_DFE_TAP5_ABCD__rxd_dfe_tap5(reg_value) extract_field_signed((reg_value),3,0) 2324 #define ex_DSC_AFE2_RX_DFE_TAP6_ABCD__rxa_dfe_tap6(reg_value) extract_field_signed((reg_value),15,12) 2325 #define ex_DSC_AFE2_RX_DFE_TAP6_ABCD__rxb_dfe_tap6(reg_value) extract_field_signed((reg_value),11,8) 2326 #define ex_DSC_AFE2_RX_DFE_TAP6_ABCD__rxc_dfe_tap6(reg_value) extract_field_signed((reg_value),7,4) 2327 #define ex_DSC_AFE2_RX_DFE_TAP6_ABCD__rxd_dfe_tap6(reg_value) extract_field_signed((reg_value),3,0) 2328 #define ex_DSC_AFE2_RX_DFE_TAP7_ABCD__rxa_dfe_tap7(reg_value) extract_field_signed((reg_value),15,12) 2329 #define ex_DSC_AFE2_RX_DFE_TAP7_ABCD__rxb_dfe_tap7(reg_value) extract_field_signed((reg_value),11,8) 2330 #define ex_DSC_AFE2_RX_DFE_TAP7_ABCD__rxc_dfe_tap7(reg_value) extract_field_signed((reg_value),7,4) 2331 #define ex_DSC_AFE2_RX_DFE_TAP7_ABCD__rxd_dfe_tap7(reg_value) extract_field_signed((reg_value),3,0) 2332 #define ex_DSC_AFE2_RX_DFE_TAP8_ABCD__rxa_dfe_tap8(reg_value) extract_field_signed((reg_value),15,12) 2333 #define ex_DSC_AFE2_RX_DFE_TAP8_ABCD__rxb_dfe_tap8(reg_value) extract_field_signed((reg_value),11,8) 2334 #define ex_DSC_AFE2_RX_DFE_TAP8_ABCD__rxc_dfe_tap8(reg_value) extract_field_signed((reg_value),7,4) 2335 #define ex_DSC_AFE2_RX_DFE_TAP8_ABCD__rxd_dfe_tap8(reg_value) extract_field_signed((reg_value),3,0) 2336 #define ex_DSC_AFE2_RX_DFE_TAP9_ABCD__rxa_dfe_tap9(reg_value) extract_field_signed((reg_value),15,12) 2337 #define ex_DSC_AFE2_RX_DFE_TAP9_ABCD__rxb_dfe_tap9(reg_value) extract_field_signed((reg_value),11,8) 2338 #define ex_DSC_AFE2_RX_DFE_TAP9_ABCD__rxc_dfe_tap9(reg_value) extract_field_signed((reg_value),7,4) 2339 #define ex_DSC_AFE2_RX_DFE_TAP9_ABCD__rxd_dfe_tap9(reg_value) extract_field_signed((reg_value),3,0) 2340 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_1__rxc_slicer_offset_adj_cal_d5(reg_value) extract_field_signed((reg_value),13,8) 2341 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_1__rxc_slicer_offset_adj_cal_d4(reg_value) extract_field_signed((reg_value),5,0) 2342 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_2__rxc_slicer_offset_adj_cal_d3(reg_value) extract_field_signed((reg_value),13,8) 2343 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_2__rxc_slicer_offset_adj_cal_d2(reg_value) extract_field_signed((reg_value),5,0) 2344 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_3__rxc_slicer_offset_adj_cal_d1(reg_value) extract_field_signed((reg_value),13,8) 2345 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_3__rxc_slicer_offset_adj_cal_d0(reg_value) extract_field_signed((reg_value),5,0) 2346 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_4__rxc_slicer_offset_adj_cal_p2(reg_value) extract_field_signed((reg_value),13,8) 2347 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_4__rxc_slicer_offset_adj_cal_p1(reg_value) extract_field_signed((reg_value),5,0) 2348 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_5__rxc_slicer_offset_adj_cal_p0(reg_value) extract_field_signed((reg_value),13,8) 2349 #define ex_DSC_AFE2_RXC_SLICER_OFFSET_ADJ_5__rxc_slicer_offset_adj_cal_lms(reg_value) extract_field_signed((reg_value),5,0) 2350 #define ex_DSC_AFE3_RX_DFE_TAP10_ABCD__rxa_dfe_tap10(reg_value) extract_field_signed((reg_value),15,12) 2351 #define ex_DSC_AFE3_RX_DFE_TAP10_ABCD__rxb_dfe_tap10(reg_value) extract_field_signed((reg_value),11,8) 2352 #define ex_DSC_AFE3_RX_DFE_TAP10_ABCD__rxc_dfe_tap10(reg_value) extract_field_signed((reg_value),7,4) 2353 #define ex_DSC_AFE3_RX_DFE_TAP10_ABCD__rxd_dfe_tap10(reg_value) extract_field_signed((reg_value),3,0) 2354 #define ex_DSC_AFE3_RX_DFE_TAP11_ABCD__rxa_dfe_tap11(reg_value) extract_field_signed((reg_value),15,12) 2355 #define ex_DSC_AFE3_RX_DFE_TAP11_ABCD__rxb_dfe_tap11(reg_value) extract_field_signed((reg_value),11,8) 2356 #define ex_DSC_AFE3_RX_DFE_TAP11_ABCD__rxc_dfe_tap11(reg_value) extract_field_signed((reg_value),7,4) 2357 #define ex_DSC_AFE3_RX_DFE_TAP11_ABCD__rxd_dfe_tap11(reg_value) extract_field_signed((reg_value),3,0) 2358 #define ex_DSC_AFE3_RX_DFE_TAP12_ABCD__rxa_dfe_tap12(reg_value) extract_field_signed((reg_value),15,12) 2359 #define ex_DSC_AFE3_RX_DFE_TAP12_ABCD__rxb_dfe_tap12(reg_value) extract_field_signed((reg_value),11,8) 2360 #define ex_DSC_AFE3_RX_DFE_TAP12_ABCD__rxc_dfe_tap12(reg_value) extract_field_signed((reg_value),7,4) 2361 #define ex_DSC_AFE3_RX_DFE_TAP12_ABCD__rxd_dfe_tap12(reg_value) extract_field_signed((reg_value),3,0) 2362 #define ex_DSC_AFE3_RX_DFE_TAP13_ABCD__rxa_dfe_tap13(reg_value) extract_field_signed((reg_value),15,12) 2363 #define ex_DSC_AFE3_RX_DFE_TAP13_ABCD__rxb_dfe_tap13(reg_value) extract_field_signed((reg_value),11,8) 2364 #define ex_DSC_AFE3_RX_DFE_TAP13_ABCD__rxc_dfe_tap13(reg_value) extract_field_signed((reg_value),7,4) 2365 #define ex_DSC_AFE3_RX_DFE_TAP13_ABCD__rxd_dfe_tap13(reg_value) extract_field_signed((reg_value),3,0) 2366 #define ex_DSC_AFE3_RX_DFE_TAP14_ABCD__rxa_dfe_tap14(reg_value) extract_field_signed((reg_value),15,12) 2367 #define ex_DSC_AFE3_RX_DFE_TAP14_ABCD__rxb_dfe_tap14(reg_value) extract_field_signed((reg_value),11,8) 2368 #define ex_DSC_AFE3_RX_DFE_TAP14_ABCD__rxc_dfe_tap14(reg_value) extract_field_signed((reg_value),7,4) 2369 #define ex_DSC_AFE3_RX_DFE_TAP14_ABCD__rxd_dfe_tap14(reg_value) extract_field_signed((reg_value),3,0) 2370 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxa_dfe_tap7_mux(reg_value) extract_field((reg_value),15,14) 2371 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxa_dfe_tap8_mux(reg_value) extract_field((reg_value),13,12) 2372 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxb_dfe_tap7_mux(reg_value) extract_field((reg_value),11,10) 2373 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxb_dfe_tap8_mux(reg_value) extract_field((reg_value),9,8) 2374 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxc_dfe_tap7_mux(reg_value) extract_field((reg_value),7,6) 2375 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxc_dfe_tap8_mux(reg_value) extract_field((reg_value),5,4) 2376 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxd_dfe_tap7_mux(reg_value) extract_field((reg_value),3,2) 2377 #define ex_DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD__rxd_dfe_tap8_mux(reg_value) extract_field((reg_value),1,0) 2378 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxa_dfe_tap9_mux(reg_value) extract_field((reg_value),15,14) 2379 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxa_dfe_tap10_mux(reg_value) extract_field((reg_value),13,12) 2380 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxb_dfe_tap9_mux(reg_value) extract_field((reg_value),11,10) 2381 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxb_dfe_tap10_mux(reg_value) extract_field((reg_value),9,8) 2382 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxc_dfe_tap9_mux(reg_value) extract_field((reg_value),7,6) 2383 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxc_dfe_tap10_mux(reg_value) extract_field((reg_value),5,4) 2384 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxd_dfe_tap9_mux(reg_value) extract_field((reg_value),3,2) 2385 #define ex_DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD__rxd_dfe_tap10_mux(reg_value) extract_field((reg_value),1,0) 2386 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxa_dfe_tap11_mux(reg_value) extract_field((reg_value),15,14) 2387 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxa_dfe_tap12_mux(reg_value) extract_field((reg_value),13,12) 2388 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxb_dfe_tap11_mux(reg_value) extract_field((reg_value),11,10) 2389 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxb_dfe_tap12_mux(reg_value) extract_field((reg_value),9,8) 2390 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxc_dfe_tap11_mux(reg_value) extract_field((reg_value),7,6) 2391 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxc_dfe_tap12_mux(reg_value) extract_field((reg_value),5,4) 2392 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxd_dfe_tap11_mux(reg_value) extract_field((reg_value),3,2) 2393 #define ex_DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD__rxd_dfe_tap12_mux(reg_value) extract_field((reg_value),1,0) 2394 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxa_dfe_tap13_mux(reg_value) extract_field((reg_value),15,14) 2395 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxa_dfe_tap14_mux(reg_value) extract_field((reg_value),13,12) 2396 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxb_dfe_tap13_mux(reg_value) extract_field((reg_value),11,10) 2397 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxb_dfe_tap14_mux(reg_value) extract_field((reg_value),9,8) 2398 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxc_dfe_tap13_mux(reg_value) extract_field((reg_value),7,6) 2399 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxc_dfe_tap14_mux(reg_value) extract_field((reg_value),5,4) 2400 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxd_dfe_tap13_mux(reg_value) extract_field((reg_value),3,2) 2401 #define ex_DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD__rxd_dfe_tap14_mux(reg_value) extract_field((reg_value),1,0) 2402 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_1__rxd_slicer_offset_adj_cal_d5(reg_value) extract_field_signed((reg_value),13,8) 2403 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_1__rxd_slicer_offset_adj_cal_d4(reg_value) extract_field_signed((reg_value),5,0) 2404 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_2__rxd_slicer_offset_adj_cal_d3(reg_value) extract_field_signed((reg_value),13,8) 2405 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_2__rxd_slicer_offset_adj_cal_d2(reg_value) extract_field_signed((reg_value),5,0) 2406 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_3__rxd_slicer_offset_adj_cal_d1(reg_value) extract_field_signed((reg_value),13,8) 2407 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_3__rxd_slicer_offset_adj_cal_d0(reg_value) extract_field_signed((reg_value),5,0) 2408 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_4__rxd_slicer_offset_adj_cal_p2(reg_value) extract_field_signed((reg_value),13,8) 2409 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_4__rxd_slicer_offset_adj_cal_p1(reg_value) extract_field_signed((reg_value),5,0) 2410 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_5__rxd_slicer_offset_adj_cal_p0(reg_value) extract_field_signed((reg_value),13,8) 2411 #define ex_DSC_AFE3_RXD_SLICER_OFFSET_ADJ_5__rxd_slicer_offset_adj_cal_lms(reg_value) extract_field_signed((reg_value),5,0) 2412 #define ex_DSC_B_DC_OFFSET_STATUS__dc_offset_bin(reg_value) extract_field_signed((reg_value),7,0) 2413 #define ex_DSC_B_VGA_D_THRESH_STATUS__rx_vga_status(reg_value) extract_field_signed((reg_value),14,8) 2414 #define ex_DSC_B_VGA_D_THRESH_STATUS__rx_data23_status(reg_value) extract_field_signed((reg_value),7,0) 2415 #define ex_DSC_B_VGA_DATA_THRESH_STATUS__rx_data14_status(reg_value) extract_field_signed((reg_value),15,8) 2416 #define ex_DSC_B_VGA_DATA_THRESH_STATUS__rx_data05_status(reg_value) extract_field_signed((reg_value),7,0) 2417 #define ex_DSC_B_VGA_PHASE_THRESH_STATUS__rx_phase1_status(reg_value) extract_field_signed((reg_value),15,8) 2418 #define ex_DSC_B_VGA_PHASE_THRESH_STATUS__rx_phase02_status(reg_value) extract_field_signed((reg_value),7,0) 2419 #define ex_DSC_C_RX_PI_CONTROL__rx_pi_disp_msb_status(reg_value) extract_field((reg_value),13,13) 2420 #define ex_DSC_C_CDR_CONTROL_2__tx_pi_loop_timing_src_sel(reg_value) extract_field((reg_value),6,6) 2421 #define ex_DSC_C_CDR_CONTROL_0__rx_pam4_er_mode(reg_value) extract_field((reg_value),15,15) 2422 #define ex_DSC_C_CDR_CONTROL_0__rx_nrz_vsr_mode(reg_value) extract_field((reg_value),14,14) 2423 #define ex_DSC_C_CDR_CONTROL_0__cdr_integ_reg_clr(reg_value) extract_field((reg_value),5,5) 2424 #define ex_DSC_C_CDR_CONTROL_0__br_pd_en(reg_value) extract_field((reg_value),2,2) 2425 #define ex_DSC_C_CDR_CONTROL_0__os_pattern_enhanced(reg_value) extract_field((reg_value),1,1) 2426 #define ex_DSC_C_CDR_CONTROL_0__os_all_edges(reg_value) extract_field((reg_value),0,0) 2427 #define ex_DSC_C_SLICERS_WRITE_CTRL__rx_afe_override_write(reg_value) extract_field((reg_value),15,15) 2428 #define ex_DSC_C_SLICERS_WRITE_CTRL__rx_afe_override_val(reg_value) extract_field_signed((reg_value),14,7) 2429 #define ex_DSC_C_SLICERS_WRITE_CTRL__rx_afe_override_sel(reg_value) extract_field((reg_value),3,0) 2430 #define ex_DSC_D_DSC_SM_CTRL_1__rx_dsc_lock_frc(reg_value) extract_field((reg_value),0,0) 2431 #define ex_DSC_D_DSC_SM_CTRL_1__rx_dsc_lock_frc_val(reg_value) extract_field((reg_value),1,1) 2432 #define ex_DSC_D_DSC_SM_CTRL_1__freq_upd_en_frc(reg_value) extract_field((reg_value),8,8) 2433 #define ex_DSC_D_DSC_SM_CTRL_1__freq_upd_en_frc_val(reg_value) extract_field((reg_value),9,9) 2434 #define ex_DSC_D_DSC_SM_CTRL_9__rx_restart_pmd(reg_value) extract_field((reg_value),0,0) 2435 #define ex_DSC_D_DSC_SM_CTRL_9__rx_restart_pmd_hold(reg_value) extract_field((reg_value),1,1) 2436 #define ex_DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT__dsc_state_one_hot(reg_value) extract_field((reg_value),9,0) 2437 #define ex_DSC_D_DSC_SM_STATUS_DSC_STATE__dsc_state(reg_value) extract_field((reg_value),15,11) 2438 #define ex_DSC_D_DSC_SM_STATUS_DSC_STATE__dsc_sm_scratch(reg_value) extract_field((reg_value),10,8) 2439 #define ex_DSC_D_DSC_SM_STATUS_DSC_STATE__dsc_sm_gp_uc_req(reg_value) extract_field((reg_value),6,1) 2440 #define ex_DSC_D_DSC_SM_STATUS_DSC_STATE__dsc_sm_ready_for_cmd(reg_value) extract_field((reg_value),0,0) 2441 #define ex_DSC_E_RX_PI_CNT_BIN_P__rx_pi_cnt_bin_pq(reg_value) extract_field((reg_value),15,8) 2442 #define ex_DSC_E_RX_PI_CNT_BIN_P__rx_pi_cnt_bin_p(reg_value) extract_field((reg_value),7,0) 2443 #define ex_DSC_E_RX_PI_CNT_BIN_L__rx_pi_cnt_bin_lq(reg_value) extract_field((reg_value),15,8) 2444 #define ex_DSC_E_RX_PI_CNT_BIN_L__rx_pi_cnt_bin_l(reg_value) extract_field((reg_value),7,0) 2445 #define ex_DSC_E_RX_PI_CNT_BIN_D__rx_pi_cnt_bin_dq(reg_value) extract_field((reg_value),15,8) 2446 #define ex_DSC_E_RX_PI_CNT_BIN_D__rx_pi_cnt_bin_d(reg_value) extract_field((reg_value),7,0) 2447 #define ex_DSC_E_RX_PI_CNT_BIN_LD__rx_pi_cnt_bin_d_ld(reg_value) extract_field((reg_value),15,8) 2448 #define ex_DSC_E_RX_PI_CNT_BIN_LD__rx_pi_cnt_bin_l_ld(reg_value) extract_field((reg_value),7,0) 2449 #define ex_DSC_E_RX_PI_CNT_BIN_PD__rx_pi_cnt_bin_d_pd(reg_value) extract_field((reg_value),15,8) 2450 #define ex_DSC_E_RX_PI_CNT_BIN_PD__rx_pi_cnt_bin_p_pd(reg_value) extract_field((reg_value),7,0) 2451 #define ex_DSC_E_CDR_STATUS_INTEG_REG__cdr_integ_reg(reg_value) extract_field_signed((reg_value),15,0) 2452 #define ex_DSC_E_RX_PI_CNTR_PHASE_ERR__rx_pi_cnt_bin_d_perr(reg_value) extract_field((reg_value),15,7) 2453 #define ex_DSC_E_RX_DFE_TAP2_STATUS__rxa_dfe_tap2_status(reg_value) extract_field_signed((reg_value),14,10) 2454 #define ex_DSC_E_RX_DFE_TAP2_STATUS__rxb_dfe_tap2_status(reg_value) extract_field_signed((reg_value),9,5) 2455 #define ex_DSC_E_RX_DFE_TAP2_STATUS__rxc_dfe_tap2_status(reg_value) extract_field_signed((reg_value),4,0) 2456 #define ex_DSC_E_RX_DFE_TAP2_3_STATUS__rxd_dfe_tap2_status(reg_value) extract_field_signed((reg_value),14,10) 2457 #define ex_DSC_E_RX_DFE_TAP2_3_STATUS__rxa_dfe_tap3_status(reg_value) extract_field_signed((reg_value),9,5) 2458 #define ex_DSC_E_RX_DFE_TAP2_3_STATUS__rxb_dfe_tap3_status(reg_value) extract_field_signed((reg_value),4,0) 2459 #define ex_DSC_E_RX_DFE_TAP3_STATUS__rxc_dfe_tap3_status(reg_value) extract_field_signed((reg_value),9,5) 2460 #define ex_DSC_E_RX_DFE_TAP3_STATUS__rxd_dfe_tap3_status(reg_value) extract_field_signed((reg_value),4,0) 2461 #define ex_DSC_F_LMS_THRESH_STS_REG__lms_thresh_bin(reg_value) extract_field_signed((reg_value),9,0) 2462 #define ex_DSC_F_LMS_THRESH_STS2_REG__afe_lms_thresh_bin(reg_value) extract_field_signed((reg_value),7,0) 2463 #define ex_DSC_G_RX_DFE_TAP2_CTRL__rxa_dfe_tap2_write(reg_value) extract_field((reg_value),15,15) 2464 #define ex_DSC_G_RX_DFE_TAP2_CTRL__rxa_dfe_tap2_val(reg_value) extract_field_signed((reg_value),14,10) 2465 #define ex_DSC_G_RX_DFE_TAP2_CTRL__rxb_dfe_tap2_val(reg_value) extract_field_signed((reg_value),9,5) 2466 #define ex_DSC_G_RX_DFE_TAP2_CTRL__rxc_dfe_tap2_val(reg_value) extract_field_signed((reg_value),4,0) 2467 #define ex_DSC_G_RX_DFE_TAP2_3_CTRL__rxd_dfe_tap2_write(reg_value) extract_field((reg_value),15,15) 2468 #define ex_DSC_G_RX_DFE_TAP2_3_CTRL__rxd_dfe_tap2_val(reg_value) extract_field_signed((reg_value),14,10) 2469 #define ex_DSC_G_RX_DFE_TAP2_3_CTRL__rxa_dfe_tap3_val(reg_value) extract_field_signed((reg_value),9,5) 2470 #define ex_DSC_G_RX_DFE_TAP2_3_CTRL__rxb_dfe_tap3_val(reg_value) extract_field_signed((reg_value),4,0) 2471 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxb_dfe_tap2_write(reg_value) extract_field((reg_value),15,15) 2472 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxc_dfe_tap2_write(reg_value) extract_field((reg_value),14,14) 2473 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxa_dfe_tap3_write(reg_value) extract_field((reg_value),13,13) 2474 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxb_dfe_tap3_write(reg_value) extract_field((reg_value),12,12) 2475 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxc_dfe_tap3_write(reg_value) extract_field((reg_value),11,11) 2476 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxd_dfe_tap3_write(reg_value) extract_field((reg_value),10,10) 2477 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxc_dfe_tap3_val(reg_value) extract_field_signed((reg_value),9,5) 2478 #define ex_DSC_G_RX_DFE_TAP3_CTRL__rxd_dfe_tap3_val(reg_value) extract_field_signed((reg_value),4,0) 2479 #define ex_DSC_H_RX_PF_CTRL_DC_OFFSET_AND_VGA__rx_pf_ctrl_val(reg_value) extract_field((reg_value),14,10) 2480 #define ex_DSC_H_RX_PF_CTRL_DC_OFFSET_AND_VGA__rx_pf2_ctrl_val(reg_value) extract_field((reg_value),9,7) 2481 #define ex_DSC_H_RX_PF_CTRL_DC_OFFSET_AND_VGA__rx_vga_val(reg_value) extract_field((reg_value),6,0) 2482 #define ex_DBG_FDBK_DBG_FDBK_PROCESSOR_CTRL__dbg_fdbk_idx(reg_value) extract_field((reg_value),15,14) 2483 #define ex_DBG_FDBK_DBG_FDBK_PROCESSOR_CTRL__dbg_fdbk_idx_monitor_en(reg_value) extract_field((reg_value),13,13) 2484 #define ex_DBG_FDBK_DBG_FDBK_PROCESSOR_CTRL__frc_index_diffprec(reg_value) extract_field((reg_value),12,12) 2485 #define ex_DBG_FDBK_DBG_FDBK_CNTR_CTRL__dbg_fdbk_data_sel(reg_value) extract_field((reg_value),7,7) 2486 #define ex_DBG_FDBK_DBG_FDBK_CNTR_CTRL__dbg_fdbk_data_threshold(reg_value) extract_field((reg_value),6,4) 2487 #define ex_DBG_FDBK_DBG_FDBK_CNTR_CTRL__fdbk_counting_mode(reg_value) extract_field((reg_value),2,2) 2488 #define ex_DBG_FDBK_DBG_FDBK_CNTR_CTRL__dbg_fdbk_en(reg_value) extract_field((reg_value),0,0) 2489 #define ex_DBG_FDBK_DBG_FDBK_CTRL__inlv_idx(reg_value) extract_field((reg_value),7,0) 2490 #define ex_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_0_STATUS__dbg_fdbk_counter_0(reg_value) extract_field((reg_value),15,0) 2491 #define ex_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_1_STATUS__dbg_fdbk_counter_1(reg_value) extract_field((reg_value),15,0) 2492 #define ex_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_2_STATUS__dbg_fdbk_counter_2(reg_value) extract_field((reg_value),15,0) 2493 #define ex_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_3_STATUS__dbg_fdbk_counter_3(reg_value) extract_field((reg_value),15,0) 2494 #define ex_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_4_STATUS__dbg_fdbk_counter_4(reg_value) extract_field((reg_value),15,0) 2495 #define ex_DBG_FDBK_DBG_FDBK_CNTR_COUNTER_5_STATUS__dbg_fdbk_counter_5(reg_value) extract_field((reg_value),15,0) 2496 #define ex_DBG_FDBK_DBG_FDBK_PROCESSOR_STATUS__dbg_fdbk_idx_lock(reg_value) extract_field((reg_value),8,8) 2497 #define ex_LINKTRN_IEEE_RX_LINKTRNIR_BASE_R_LP_COEFF_UPDATE_REGISTER_152__linktrn_ieee_lp_coeff_update(reg_value) extract_field((reg_value),15,0) 2498 #define ex_LINKTRN_IEEE_RX_LINKTRNIR_BASE_R_LP_STATUS_REPORT_REGISTER_153__linktrn_ieee_lp_status_report(reg_value) extract_field((reg_value),15,0) 2499 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL_REGISTER_150__linktrn_ieee_training_enable(reg_value) extract_field((reg_value),1,1) 2500 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL_REGISTER_150__linktrn_ieee_restart_training(reg_value) extract_field((reg_value),0,0) 2501 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS_REGISTER_151__linktrn_ieee_training_failure(reg_value) extract_field((reg_value),3,3) 2502 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS_REGISTER_151__linktrn_ieee_training_status(reg_value) extract_field((reg_value),2,2) 2503 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS_REGISTER_151__linktrn_ieee_frame_lock(reg_value) extract_field((reg_value),1,1) 2504 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS_REGISTER_151__linktrn_ieee_receiver_status(reg_value) extract_field((reg_value),0,0) 2505 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_LD_COEFF_UPDATE_REGISTER_154__linktrn_ieee_ld_coeff_update(reg_value) extract_field((reg_value),15,0) 2506 #define ex_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_LD_STATUS_REPORT_REGISTER_155__linktrn_ieee_ld_status_report(reg_value) extract_field((reg_value),15,0) 2507 #define ex_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER__linktrn_sm_current_state(reg_value) extract_field((reg_value),14,12) 2508 #define ex_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER__linktrn_xmt_status_report_parity(reg_value) extract_field((reg_value),5,5) 2509 #define ex_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER__linktrn_xmt_coeff_update_parity(reg_value) extract_field((reg_value),4,4) 2510 #define ex_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER__linktrn_training_fsm_signal_detect(reg_value) extract_field((reg_value),1,1) 2511 #define ex_LINKTRN_USER_TX_LINKTRNUT_STATUS0_REGISTER__linktrn_local_rx_ready(reg_value) extract_field((reg_value),0,0) 2512 #define exc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR__mdio_drv_comclk(reg_value) extract_field((reg_value),15,15) 2513 #define exc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR__mdio_brcst_port_addr(reg_value) extract_field((reg_value),4,0) 2514 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_multi_prts_en(reg_value) extract_field((reg_value),15,15) 2515 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_multi_mmds_en(reg_value) extract_field((reg_value),14,14) 2516 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_pcs_en(reg_value) extract_field((reg_value),6,6) 2517 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_dte_en(reg_value) extract_field((reg_value),5,5) 2518 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_phy_en(reg_value) extract_field((reg_value),4,4) 2519 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_an_en(reg_value) extract_field((reg_value),3,3) 2520 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_pmd_en(reg_value) extract_field((reg_value),2,2) 2521 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_id0_en(reg_value) extract_field((reg_value),0,0) 2522 #define exc_MDIO_MMDSEL_AER_COM_MDIO_AER__mdio_aer(reg_value) extract_field((reg_value),10,0) 2523 #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_master_clk_en(reg_value) extract_field((reg_value),0,0) 2524 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_pram_if_rstb(reg_value) extract_field((reg_value),15,15) 2525 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_sw_timestamp_timer_rstb(reg_value) extract_field((reg_value),14,14) 2526 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_master_rstb(reg_value) extract_field((reg_value),0,0) 2527 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_rdaddr_en(reg_value) extract_field((reg_value),13,13) 2528 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_wraddr_en(reg_value) extract_field((reg_value),12,12) 2529 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_init(reg_value) extract_field((reg_value),9,8) 2530 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_rddatasize(reg_value) extract_field((reg_value),5,4) 2531 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_wrdatasize(reg_value) extract_field((reg_value),1,0) 2532 #define exc_MICRO_A_COM_AHB_STATUS0__micro_ra_initdone(reg_value) extract_field((reg_value),0,0) 2533 #define exc_MICRO_A_COM_AHB_WRADDR_LSW__micro_ra_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 2534 #define exc_MICRO_A_COM_AHB_WRADDR_MSW__micro_ra_wraddr_msw(reg_value) extract_field((reg_value),15,0) 2535 #define exc_MICRO_A_COM_AHB_WRDATA_LSW__micro_ra_wrdata_lsw(reg_value) extract_field((reg_value),15,0) 2536 #define exc_MICRO_A_COM_AHB_WRDATA_MSW__micro_ra_wrdata_msw(reg_value) extract_field((reg_value),15,0) 2537 #define exc_MICRO_A_COM_AHB_RDADDR_LSW__micro_ra_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) 2538 #define exc_MICRO_A_COM_AHB_RDADDR_MSW__micro_ra_rdaddr_msw(reg_value) extract_field((reg_value),15,0) 2539 #define exc_MICRO_A_COM_AHB_RDDATA_LSW__micro_ra_rddata_lsw(reg_value) extract_field((reg_value),15,0) 2540 #define exc_MICRO_A_COM_AHB_RDDATA_MSW__micro_ra_rddata_msw(reg_value) extract_field((reg_value),15,0) 2541 #define exc_MICRO_A_COM_PRAMIF_CONTROL0__micro_pramif_en(reg_value) extract_field((reg_value),0,0) 2542 #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW__micro_pramif_ahb_wraddr_lsw(reg_value) extract_field((reg_value),15,2) 2543 #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW__micro_pramif_ahb_wraddr_msw(reg_value) extract_field((reg_value),15,0) 2544 #define exc_MICRO_B_COM_PVT_STATUS0__micro_pvt_tempdata_rmi(reg_value) extract_field((reg_value),9,0) 2545 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_ra_arg_microblk_sel(reg_value) extract_field((reg_value),6,4) 2546 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ack_timeout_dis(reg_value) extract_field((reg_value),0,0) 2547 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_pr_default_slave_error(reg_value) extract_field((reg_value),1,1) 2548 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_rmi_default_slave_error(reg_value) extract_field((reg_value),0,0) 2549 #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW__micro_ra_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 2550 #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW__micro_ra_autoinc_nxt_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) 2551 #define exc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW__micro_pr_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 2552 #define exc_MICRO_B_COM_RMI_MICRO_MISC_STATUS0__micro_pr_autoinc_nxt_wraddr_msb(reg_value) extract_field((reg_value),4,4) 2553 #define exc_MICRO_B_COM_RMI_MICRO_MISC_STATUS0__micro_ra_autoinc_nxt_rdaddr_msb(reg_value) extract_field((reg_value),2,2) 2554 #define exc_MICRO_B_COM_RMI_MICRO_MISC_STATUS0__micro_ra_autoinc_nxt_wraddr_msb(reg_value) extract_field((reg_value),0,0) 2555 #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frc(reg_value) extract_field((reg_value),12,12) 2556 #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frcval(reg_value) extract_field((reg_value),9,0) 2557 #define exc_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0__micro_cr_crc_prtsel(reg_value) extract_field((reg_value),2,2) 2558 #define exc_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0__micro_cr_crc_init(reg_value) extract_field((reg_value),1,1) 2559 #define exc_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0__micro_cr_crc_calc_en(reg_value) extract_field((reg_value),0,0) 2560 #define exc_MICRO_B_COM_RMI_RAM_CR_CRCSTATUS0__micro_cr_crc_checksum(reg_value) extract_field((reg_value),15,0) 2561 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_m0p_default_slave_error_hresp_en(reg_value) extract_field((reg_value),11,11) 2562 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_pmi_hp_ack_timeout_hresp_en(reg_value) extract_field((reg_value),10,10) 2563 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_pmi_hp_word_access_err_hresp_en(reg_value) extract_field((reg_value),9,9) 2564 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_pmi_hp_error_hresp_en(reg_value) extract_field((reg_value),8,8) 2565 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_m0p_default_slave_error_intr_en(reg_value) extract_field((reg_value),3,3) 2566 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_pmi_hp_ack_timeout_intr_en(reg_value) extract_field((reg_value),2,2) 2567 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_pmi_hp_word_access_err_intr_en(reg_value) extract_field((reg_value),1,1) 2568 #define exc_MICRO_B_COM_RMI_MICRO_HARDFAULT_CONTROL0__micro_pmi_hp_error_intr_en(reg_value) extract_field((reg_value),0,0) 2569 #define exc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0__micro_num_uc_cores(reg_value) extract_field((reg_value),15,12) 2570 #define exc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0__micro_uc_active_3(reg_value) extract_field((reg_value),3,3) 2571 #define exc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0__micro_uc_active_2(reg_value) extract_field((reg_value),2,2) 2572 #define exc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0__micro_uc_active_1(reg_value) extract_field((reg_value),1,1) 2573 #define exc_MICRO_B_COM_RMI_MICRO_SDK_STATUS0__micro_uc_active_0(reg_value) extract_field((reg_value),0,0) 2574 #define exc_MICRO_B_COM_RMI_MICRO_DEBUGGER_ID_LSW__micro_debugger_id_lsw(reg_value) extract_field((reg_value),15,0) 2575 #define exc_MICRO_B_COM_RMI_MICRO_DEBUGGER_ID_MSW__micro_debugger_id_msw(reg_value) extract_field((reg_value),11,0) 2576 #define exc_MICRO_B_COM_RMI_MICRO_DEBUGGER_CONTROL0__micro_debugger_id_frc(reg_value) extract_field((reg_value),15,15) 2577 #define exc_MICRO_B_COM_RMI_MICRO_DEBUGGER_CONTROL0__micro_debugger_id_frcval(reg_value) extract_field((reg_value),7,0) 2578 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_dr_ecc_debug_prtsel(reg_value) extract_field((reg_value),12,12) 2579 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_dr_ecc_corrupt(reg_value) extract_field((reg_value),11,10) 2580 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_dr_ecc_frc_disable(reg_value) extract_field((reg_value),9,9) 2581 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_dr_eccg_mode(reg_value) extract_field((reg_value),8,8) 2582 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_cr_ecc_debug_prtsel(reg_value) extract_field((reg_value),4,4) 2583 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_cr_ecc_corrupt(reg_value) extract_field((reg_value),3,2) 2584 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_cr_ecc_frc_disable(reg_value) extract_field((reg_value),1,1) 2585 #define exc_MICRO_C_COM_RAM_ECCCONTROL0__micro_cr_eccg_mode(reg_value) extract_field((reg_value),0,0) 2586 #define exc_MICRO_C_COM_RAM_ECCCONTROL1__micro_ra_ecc_wrdata(reg_value) extract_field((reg_value),6,0) 2587 #define exc_MICRO_C_COM_RAM_ECCSTATUS0__micro_rmi_cr_ecc_address_status(reg_value) extract_field((reg_value),15,2) 2588 #define exc_MICRO_C_COM_RAM_ECCSTATUS1__micro_rmi_cr_ecc_address_status_16(reg_value) extract_field((reg_value),15,15) 2589 #define exc_MICRO_C_COM_RAM_ECCSTATUS1__micro_ra_ecc_rddata(reg_value) extract_field((reg_value),6,0) 2590 #define exc_MICRO_C_COM_RAM_ECCSTATUS2__micro_rmi_dr_ecc_address_status(reg_value) extract_field((reg_value),15,2) 2591 #define exc_MICRO_C_COM_RAM_TESTIFCONTROL0__micro_cr_tm(reg_value) extract_field((reg_value),8,0) 2592 #define exc_MICRO_C_COM_RAM_TESTIFCONTROL1__micro_dr_tm(reg_value) extract_field((reg_value),8,0) 2593 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_lowpower_en(reg_value) extract_field((reg_value),15,15) 2594 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_prif_prtsel(reg_value) extract_field((reg_value),11,11) 2595 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_raif_prtsel(reg_value) extract_field((reg_value),10,10) 2596 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_ignore_micro_code_writes(reg_value) extract_field((reg_value),9,9) 2597 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_access_en(reg_value) extract_field((reg_value),8,8) 2598 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_cr_lowpower_en(reg_value) extract_field((reg_value),7,7) 2599 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_cr_prif_prtsel(reg_value) extract_field((reg_value),3,3) 2600 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_cr_raif_prtsel(reg_value) extract_field((reg_value),2,2) 2601 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_cr_ignore_micro_code_writes(reg_value) extract_field((reg_value),1,1) 2602 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_cr_access_en(reg_value) extract_field((reg_value),0,0) 2603 #define exc_MICRO_C_COM_RAM_CONTROL1__micro_dr_code_size(reg_value) extract_field((reg_value),14,8) 2604 #define exc_MICRO_C_COM_RAM_CONTROL1__micro_cr_data_size(reg_value) extract_field((reg_value),6,0) 2605 #define exc_MICRO_C_COM_RAM_CONTROL2__micro_core_stack_en(reg_value) extract_field((reg_value),15,15) 2606 #define exc_MICRO_C_COM_RAM_CONTROL2__micro_core_stack_size(reg_value) extract_field((reg_value),13,2) 2607 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_mbox_msgout_status_or(reg_value) extract_field((reg_value),10,10) 2608 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0p_systemresetreq_status_or(reg_value) extract_field((reg_value),9,9) 2609 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0p_lockup_status_or(reg_value) extract_field((reg_value),8,8) 2610 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_dr_ecc_multirow_err_status(reg_value) extract_field((reg_value),6,6) 2611 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_dr_ecc_uncorr_err_status(reg_value) extract_field((reg_value),5,5) 2612 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_dr_ecc_corr_err_status(reg_value) extract_field((reg_value),4,4) 2613 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_cr_ecc_multirow_err_status(reg_value) extract_field((reg_value),2,2) 2614 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_cr_ecc_uncorr_err_status(reg_value) extract_field((reg_value),1,1) 2615 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_cr_ecc_corr_err_status(reg_value) extract_field((reg_value),0,0) 2616 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_mbox_msgout_intr_en(reg_value) extract_field((reg_value),10,10) 2617 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0p_systemresetreq_intr_en(reg_value) extract_field((reg_value),9,9) 2618 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0p_lockup_intr_en(reg_value) extract_field((reg_value),8,8) 2619 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_dr_ecc_multirow_err_intr_en(reg_value) extract_field((reg_value),6,6) 2620 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_dr_ecc_uncorr_err_intr_en(reg_value) extract_field((reg_value),5,5) 2621 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_dr_ecc_corr_err_intr_en(reg_value) extract_field((reg_value),4,4) 2622 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_cr_ecc_multirow_err_intr_en(reg_value) extract_field((reg_value),2,2) 2623 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_cr_ecc_uncorr_err_intr_en(reg_value) extract_field((reg_value),1,1) 2624 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_cr_ecc_corr_err_intr_en(reg_value) extract_field((reg_value),0,0) 2625 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_bktobk_en(reg_value) extract_field((reg_value),2,2) 2626 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_read_en(reg_value) extract_field((reg_value),0,0) 2627 #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0__micro_silicon_debug_status_mux_sel(reg_value) extract_field((reg_value),2,0) 2628 #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0__micro_silicon_debug_status_muxed_data(reg_value) extract_field((reg_value),15,0) 2629 #define exc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL0__micro_msg0(reg_value) extract_field((reg_value),15,0) 2630 #define exc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL1__micro_msg1(reg_value) extract_field((reg_value),15,0) 2631 #define exc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL2__micro_msg2(reg_value) extract_field((reg_value),15,0) 2632 #define exc_MICRO_D_COM_RMI_MICRO_MSG_CONTROL3__micro_msg3(reg_value) extract_field((reg_value),15,0) 2633 #define exc_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0__micro_core_clk_en(reg_value) extract_field((reg_value),0,0) 2634 #define exc_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0__micro_sw_pmi_hp_rstb(reg_value) extract_field((reg_value),15,15) 2635 #define exc_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0__micro_dap_poreset_s_rstb(reg_value) extract_field((reg_value),14,14) 2636 #define exc_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0__micro_core_rstb(reg_value) extract_field((reg_value),0,0) 2637 #define exc_MICRO_E_COM_MICRO_CORE_STATUS0__micro_m0p_default_slave_error_status(reg_value) extract_field((reg_value),3,3) 2638 #define exc_MICRO_E_COM_MICRO_CORE_STATUS0__micro_pmi_hp_ack_timeout_status(reg_value) extract_field((reg_value),2,2) 2639 #define exc_MICRO_E_COM_MICRO_CORE_STATUS0__micro_pmi_hp_word_access_err_status(reg_value) extract_field((reg_value),1,1) 2640 #define exc_MICRO_E_COM_MICRO_CORE_STATUS0__micro_pmi_hp_error_status(reg_value) extract_field((reg_value),0,0) 2641 #define exc_MICRO_E_COM_MICRO_CORE_CONTROL0__micro_core_ln_sel(reg_value) extract_field((reg_value),7,0) 2642 #define exc_MICRO_E_COM_MICRO_CORE_MBOX_CONTROL0__micro_mbox_msgin_intr(reg_value) extract_field((reg_value),0,0) 2643 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_pmd_signal_detect_wakeup_en(reg_value) extract_field((reg_value),6,6) 2644 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_dp_rclk20_rst_wakeup_en(reg_value) extract_field((reg_value),5,5) 2645 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_m0p_wakeup(reg_value) extract_field((reg_value),4,4) 2646 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_m0p_gclk_frc(reg_value) extract_field((reg_value),3,3) 2647 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_m0p_gclk_frcval(reg_value) extract_field((reg_value),2,2) 2648 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_sleepholdreq_n(reg_value) extract_field((reg_value),1,1) 2649 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_CONTROL0__micro_wicenreq(reg_value) extract_field((reg_value),0,0) 2650 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0__micro_sleepdeep_LH(reg_value) extract_field((reg_value),5,5) 2651 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0__micro_sleeping_LH(reg_value) extract_field((reg_value),4,4) 2652 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0__micro_sleepdeep(reg_value) extract_field((reg_value),3,3) 2653 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0__micro_sleeping(reg_value) extract_field((reg_value),2,2) 2654 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0__micro_sleepholdack_n(reg_value) extract_field((reg_value),1,1) 2655 #define exc_MICRO_E_COM_MICRO_CORE_LOW_POWER_STATUS0__micro_wicenack(reg_value) extract_field((reg_value),0,0) 2656 #define exc_MICRO_E_COM_MICRO_CORE_STATUS1__micro_rmi_mbox_msgout_status(reg_value) extract_field((reg_value),2,2) 2657 #define exc_MICRO_E_COM_MICRO_CORE_STATUS1__micro_rmi_m0p_systemresetreq_status(reg_value) extract_field((reg_value),1,1) 2658 #define exc_MICRO_E_COM_MICRO_CORE_STATUS1__micro_rmi_m0p_lockup_status(reg_value) extract_field((reg_value),0,0) 2659 #define exc_MICRO_E_COM_MICRO_CORE_STATUS2__micro_pmd_signal_detect_status_LH(reg_value) extract_field((reg_value),15,8) 2660 #define exc_MICRO_E_COM_MICRO_CORE_STATUS2__micro_dp_rclk20_rst_status_LH(reg_value) extract_field((reg_value),7,0) 2661 #define exc_MICRO_E_COM_MICRO_STATUS__micro_status_stack_overflowed(reg_value) extract_field((reg_value),7,7) 2662 #define exc_MICRO_E_COM_MICRO_STATUS__micro_status_stack_overflowed_laneID(reg_value) extract_field((reg_value),6,4) 2663 #define exc_MICRO_E_COM_MICRO_STATUS__micro_status_hw_exception_occurred(reg_value) extract_field((reg_value),3,3) 2664 #define exc_MICRO_E_COM_MICRO_STATUS__micro_status_hw_exception_complete(reg_value) extract_field((reg_value),2,2) 2665 #define exc_MICRO_E_COM_MICRO_STATUS__micro_status_sw_exception_occurred(reg_value) extract_field((reg_value),1,1) 2666 #define exc_MICRO_E_COM_MICRO_STATUS__micro_status_sw_exception_complete(reg_value) extract_field((reg_value),0,0) 2667 #define exc_MICRO_E_COM_MICRO_CORE_CFG_FW_API_DATA1__micro_core_cfg_fwapi_data1(reg_value) extract_field((reg_value),15,0) 2668 #define exc_PATT_GEN_COM_SEQ_0__patt_gen_seq_0(reg_value) extract_field((reg_value),15,0) 2669 #define exc_PATT_GEN_COM_SEQ_1__patt_gen_seq_1(reg_value) extract_field((reg_value),15,0) 2670 #define exc_PATT_GEN_COM_SEQ_2__patt_gen_seq_2(reg_value) extract_field((reg_value),15,0) 2671 #define exc_PATT_GEN_COM_SEQ_3__patt_gen_seq_3(reg_value) extract_field((reg_value),15,0) 2672 #define exc_PATT_GEN_COM_SEQ_4__patt_gen_seq_4(reg_value) extract_field((reg_value),15,0) 2673 #define exc_PATT_GEN_COM_SEQ_5__patt_gen_seq_5(reg_value) extract_field((reg_value),15,0) 2674 #define exc_PATT_GEN_COM_SEQ_6__patt_gen_seq_6(reg_value) extract_field((reg_value),15,0) 2675 #define exc_PATT_GEN_COM_SEQ_7__patt_gen_seq_7(reg_value) extract_field((reg_value),15,0) 2676 #define exc_PATT_GEN_COM_SEQ_8__patt_gen_seq_8(reg_value) extract_field((reg_value),15,0) 2677 #define exc_PATT_GEN_COM_SEQ_9__patt_gen_seq_9(reg_value) extract_field((reg_value),15,0) 2678 #define exc_PATT_GEN_COM_SEQ_10__patt_gen_seq_10(reg_value) extract_field((reg_value),15,0) 2679 #define exc_PATT_GEN_COM_SEQ_11__patt_gen_seq_11(reg_value) extract_field((reg_value),15,0) 2680 #define exc_PATT_GEN_COM_SEQ_12__patt_gen_seq_12(reg_value) extract_field((reg_value),15,0) 2681 #define exc_PATT_GEN_COM_SEQ_13__patt_gen_seq_13(reg_value) extract_field((reg_value),15,0) 2682 #define exc_PATT_GEN_COM_SEQ_14__patt_gen_seq_14(reg_value) extract_field((reg_value),15,0) 2683 #define exc_PLL_CAL_COM_CTL_0__vco_step_time(reg_value) extract_field((reg_value),7,0) 2684 #define exc_PLL_CAL_COM_CTL_5__refclk_divcnt(reg_value) extract_field((reg_value),13,0) 2685 #define exc_PLL_CAL_COM_CTL_7__rescal_frc(reg_value) extract_field((reg_value),10,10) 2686 #define exc_PLL_CAL_COM_CTL_7__rescal_frc_val(reg_value) extract_field((reg_value),9,6) 2687 #define exc_PLL_CAL_COM_CTL_7__pll_mode(reg_value) extract_field((reg_value),4,0) 2688 #define exc_PLL_CAL_COM_CTL_STATUS_0__lost_pll_lock_sm(reg_value) extract_field((reg_value),15,15) 2689 #define exc_PLL_CAL_COM_CTL_STATUS_0__cap_done(reg_value) extract_field((reg_value),14,14) 2690 #define exc_PLL_CAL_COM_CTL_STATUS_0__cap_pass(reg_value) extract_field((reg_value),13,13) 2691 #define exc_PLL_CAL_COM_CTL_STATUS_0__freq_done_sm(reg_value) extract_field((reg_value),12,12) 2692 #define exc_PLL_CAL_COM_CTL_STATUS_0__freq_pass_sm(reg_value) extract_field((reg_value),11,11) 2693 #define exc_PLL_CAL_COM_CTL_STATUS_0__pll_seq_done(reg_value) extract_field((reg_value),10,10) 2694 #define exc_PLL_CAL_COM_CTL_STATUS_0__pll_seq_pass(reg_value) extract_field((reg_value),9,9) 2695 #define exc_PLL_CAL_COM_CTL_STATUS_0__pll_lock(reg_value) extract_field((reg_value),8,8) 2696 #define exc_PLL_CAL_COM_CTL_STATUS_0__cap_done_lh_ll(reg_value) extract_field((reg_value),6,6) 2697 #define exc_PLL_CAL_COM_CTL_STATUS_0__cap_pass_lh_ll(reg_value) extract_field((reg_value),5,5) 2698 #define exc_PLL_CAL_COM_CTL_STATUS_0__freq_done_sm_lh_ll(reg_value) extract_field((reg_value),4,4) 2699 #define exc_PLL_CAL_COM_CTL_STATUS_0__freq_pass_sm_lh_ll(reg_value) extract_field((reg_value),3,3) 2700 #define exc_PLL_CAL_COM_CTL_STATUS_0__pll_seq_done_lh_ll(reg_value) extract_field((reg_value),2,2) 2701 #define exc_PLL_CAL_COM_CTL_STATUS_0__pll_seq_pass_lh_ll(reg_value) extract_field((reg_value),1,1) 2702 #define exc_PLL_CAL_COM_CTL_STATUS_0__pll_lock_lh_ll(reg_value) extract_field((reg_value),0,0) 2703 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_sigdet_pwrdn(reg_value) extract_field((reg_value),1,1) 2704 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_rx_s_pwrdn(reg_value) extract_field((reg_value),0,0) 2705 #define ex_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) 2706 #define ex_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) 2707 #define ex_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) 2708 #define ex_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) 2709 #define ex_RX_CKRST_CTRL_TSC_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) 2710 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_DEBUG_RESET_CONTROL__sigdet_dp_rstb_en(reg_value) extract_field((reg_value),2,2) 2711 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) 2712 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_s_rstb(reg_value) extract_field((reg_value),0,0) 2713 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_rclk20_pwrdn_frc_val(reg_value) extract_field((reg_value),5,5) 2714 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_rclk20_pwrdn_frc(reg_value) extract_field((reg_value),4,4) 2715 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc_val(reg_value) extract_field((reg_value),3,3) 2716 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc(reg_value) extract_field((reg_value),2,2) 2717 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) 2718 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) 2719 #define ex_RX_CKRST_CTRL_TSC_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) 2720 #define ex_RX_CKRST_CTRL_TSC_RX_PMD_LANE_MODE_STATUS__pmd_rx_lane_mode(reg_value) extract_field((reg_value),15,0) 2721 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_force_nrz_mode(reg_value) extract_field((reg_value),15,15) 2722 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_force_pam4_mode(reg_value) extract_field((reg_value),14,14) 2723 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_lp_has_prec_en(reg_value) extract_field((reg_value),13,13) 2724 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_force_ns(reg_value) extract_field((reg_value),12,12) 2725 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_force_es(reg_value) extract_field((reg_value),11,11) 2726 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_cl72_restart_timeout_en(reg_value) extract_field((reg_value),10,10) 2727 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_cl72_auto_polarity_en(reg_value) extract_field((reg_value),9,9) 2728 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_scrambling_dis(reg_value) extract_field((reg_value),8,8) 2729 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_unreliable_los(reg_value) extract_field((reg_value),7,7) 2730 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_media_type(reg_value) extract_field((reg_value),6,5) 2731 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_force_brdfe_en(reg_value) extract_field((reg_value),4,4) 2732 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_dfe_lp_mode(reg_value) extract_field((reg_value),3,3) 2733 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_dfe_on(reg_value) extract_field((reg_value),2,2) 2734 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_an_enabled(reg_value) extract_field((reg_value),1,1) 2735 #define ex_RX_CKRST_CTRL_TSC_LANE_UC_CONFIG__lane_uc_config_lane_cfg_from_pcs(reg_value) extract_field((reg_value),0,0) 2736 #define ex_RX_CKRST_CTRL_TSC_LANE_CFG_FWAPI_DATA1__lane_cfg_fwapi_data1(reg_value) extract_field((reg_value),15,0) 2737 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) 2738 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_CONTROL__rx_pam4_mode_frc(reg_value) extract_field((reg_value),14,14) 2739 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_CONTROL__rx_pam4_mode_frc_val(reg_value) extract_field((reg_value),6,4) 2740 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 2741 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__rx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 2742 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_PLL_SELECT_CONTROL__rx_pll_select(reg_value) extract_field((reg_value),0,0) 2743 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LN_S_RSTB_CONTROL__rx_hw_fw_handshake_disable(reg_value) extract_field((reg_value),1,1) 2744 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LN_S_RSTB_CONTROL__rx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) 2745 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 2746 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 2747 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 2748 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 2749 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_DP_RESET_STATE_STATUS__rx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 2750 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL__rx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 2751 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_MULTICAST_MASK_CONTROL__rx_multicast_mask_control(reg_value) extract_field((reg_value),0,0) 2752 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_multicast_mask_control_status(reg_value) extract_field((reg_value),15,15) 2753 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_pam4_mode(reg_value) extract_field((reg_value),6,4) 2754 #define ex_RXCOM_CKRST_CTRL_TSC_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_osr_mode(reg_value) extract_field((reg_value),3,0) 2755 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc(reg_value) extract_field((reg_value),15,15) 2756 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_CONTROL__pam4_mode_frc(reg_value) extract_field((reg_value),14,14) 2757 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_CONTROL__pam4_mode_frc_val(reg_value) extract_field((reg_value),6,4) 2758 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 2759 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 2760 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_PLL_SELECT_CONTROL__pll_select(reg_value) extract_field((reg_value),0,0) 2761 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LN_S_RSTB_CONTROL__hw_fw_handshake_disable(reg_value) extract_field((reg_value),1,1) 2762 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LN_S_RSTB_CONTROL__ln_s_rstb(reg_value) extract_field((reg_value),0,0) 2763 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 2764 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 2765 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 2766 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 2767 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_DP_RESET_STATE_STATUS__lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 2768 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL__lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 2769 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_MULTICAST_MASK_CONTROL__multicast_mask_control(reg_value) extract_field((reg_value),0,0) 2770 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_STATUS_MC_MASK__multicast_mask_control_status(reg_value) extract_field((reg_value),15,15) 2771 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_STATUS_MC_MASK__pam4_mode(reg_value) extract_field((reg_value),6,4) 2772 #define ex_RXTXCOM_CKRST_CTRL_TSC_RXTXCOM_OSR_MODE_STATUS_MC_MASK__osr_mode(reg_value) extract_field((reg_value),3,0) 2773 #define ex_SIGDET_SDCTRL_1__afe_signal_detect_dis(reg_value) extract_field((reg_value),0,0) 2774 #define ex_SIGDET_SDCTRL_1__ext_los_en(reg_value) extract_field((reg_value),1,1) 2775 #define ex_SIGDET_SDCTRL_1__ext_los_inv(reg_value) extract_field((reg_value),2,2) 2776 #define ex_SIGDET_SDCTRL_1__signal_detect_frc(reg_value) extract_field((reg_value),7,7) 2777 #define ex_SIGDET_SDCTRL_1__signal_detect_frc_val(reg_value) extract_field((reg_value),8,8) 2778 #define ex_SIGDET_SDCTRL_2__los_thresh(reg_value) extract_field((reg_value),2,0) 2779 #define ex_SIGDET_SDCTRL_2__signal_detect_thresh(reg_value) extract_field((reg_value),6,4) 2780 #define ex_SIGDET_SDSTATUS_0__signal_detect(reg_value) extract_field((reg_value),0,0) 2781 #define ex_SIGDET_SDSTATUS_0__signal_detect_change(reg_value) extract_field((reg_value),1,1) 2782 #define ex_SIGDET_SDSTATUS_0__signal_detect_raw(reg_value) extract_field((reg_value),4,4) 2783 #define ex_SIGDET_SDSTATUS_0__signal_detect_raw_change(reg_value) extract_field((reg_value),5,5) 2784 #define ex_SIGDET_SDSTATUS_0__ext_sigdet(reg_value) extract_field((reg_value),6,6) 2785 #define ex_SIGDET_SDSTATUS_0__ext_sigdet_change(reg_value) extract_field((reg_value),7,7) 2786 #define ex_SIGDET_SDSTATUS_0__afe_sigdet(reg_value) extract_field((reg_value),8,8) 2787 #define ex_SIGDET_SDSTATUS_0__afe_sigdet_change(reg_value) extract_field((reg_value),9,9) 2788 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0__tlb_err_aggr_mode(reg_value) extract_field((reg_value),15,14) 2789 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0__tlb_err_aggr_lanes_active(reg_value) extract_field((reg_value),13,6) 2790 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0__tlb_err_aggr_error_count_thresh(reg_value) extract_field((reg_value),5,2) 2791 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0__tlb_err_aggr_clear_error_analyzer_status(reg_value) extract_field((reg_value),1,1) 2792 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_0__tlb_err_aggr_en(reg_value) extract_field((reg_value),0,0) 2793 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_en_force(reg_value) extract_field((reg_value),14,14) 2794 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_delay_data_capture(reg_value) extract_field((reg_value),13,12) 2795 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_clk_out_of_sync_pattern_depth(reg_value) extract_field((reg_value),11,9) 2796 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_active_pattern_depth(reg_value) extract_field((reg_value),8,6) 2797 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_gclk_div2_en_ignore(reg_value) extract_field((reg_value),5,5) 2798 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_clear_status_on_read(reg_value) extract_field((reg_value),4,4) 2799 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_CONFIG_1__tlb_err_aggr_histogram_error_thresh(reg_value) extract_field((reg_value),3,0) 2800 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI__tlb_err_aggr_clks_out_of_sync_status(reg_value) extract_field((reg_value),5,5) 2801 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI__tlb_err_aggr_active_status(reg_value) extract_field((reg_value),4,4) 2802 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI__tlb_err_aggr_count_error_hi(reg_value) extract_field((reg_value),3,0) 2803 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_NUM_ERRORS_IN_FEC_FRAMES_STATUS_LO__tlb_err_aggr_count_error_lo(reg_value) extract_field((reg_value),15,0) 2804 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_0__tlb_err_aggr_count_histogram_error_offset_0(reg_value) extract_field((reg_value),15,0) 2805 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_1__tlb_err_aggr_count_histogram_error_offset_1(reg_value) extract_field((reg_value),15,0) 2806 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_2__tlb_err_aggr_count_histogram_error_offset_2(reg_value) extract_field((reg_value),15,0) 2807 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_3__tlb_err_aggr_count_histogram_error_offset_3(reg_value) extract_field((reg_value),15,0) 2808 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_4__tlb_err_aggr_count_histogram_error_offset_4(reg_value) extract_field((reg_value),15,0) 2809 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_5__tlb_err_aggr_count_histogram_error_offset_5(reg_value) extract_field((reg_value),15,0) 2810 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_6__tlb_err_aggr_count_histogram_error_offset_6(reg_value) extract_field((reg_value),15,0) 2811 #define exc_TLB_ERR_AGGR_TLB_ERR_AGGR_COUNT_HISTOGRAM_ERROR_OFFSET_7__tlb_err_aggr_count_histogram_error_offset_7(reg_value) extract_field((reg_value),15,0) 2812 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_burst_err_cnt_en(reg_value) extract_field((reg_value),15,15) 2813 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode_sel_msb(reg_value) extract_field((reg_value),12,12) 2814 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_clk_en_frc_on(reg_value) extract_field((reg_value),11,11) 2815 #define ex_TLB_RX_PRBS_CHK_CONFIG__trnsum_error_count_en(reg_value) extract_field((reg_value),10,10) 2816 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_err_cnt_burst_mode(reg_value) extract_field((reg_value),9,9) 2817 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_burst_len_chk_en(reg_value) extract_field((reg_value),8,8) 2818 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_en_auto_mode(reg_value) extract_field((reg_value),7,7) 2819 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode(reg_value) extract_field((reg_value),6,5) 2820 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_inv(reg_value) extract_field((reg_value),4,4) 2821 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode_sel(reg_value) extract_field((reg_value),3,1) 2822 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_en(reg_value) extract_field((reg_value),0,0) 2823 #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__rx_trn_active_auto_mode_en(reg_value) extract_field((reg_value),15,15) 2824 #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__prbs_chk_lock_cnt(reg_value) extract_field((reg_value),4,0) 2825 #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__prbs_chk_ool_cnt(reg_value) extract_field((reg_value),12,8) 2826 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_bias_en(reg_value) extract_field((reg_value),3,3) 2827 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_flt_bypass(reg_value) extract_field((reg_value),2,2) 2828 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) 2829 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_en(reg_value) extract_field((reg_value),0,0) 2830 #define ex_TLB_RX_RXMISC_CONFIG__pam4_rx_symbol_bit_swap(reg_value) extract_field((reg_value),7,7) 2831 #define ex_TLB_RX_RXMISC_CONFIG__prbs_chk_auto_detect_relock_en(reg_value) extract_field((reg_value),15,15) 2832 #define ex_TLB_RX_RXMISC_CONFIG__prbs_chk_auto_detect_en(reg_value) extract_field((reg_value),14,14) 2833 #define ex_TLB_RX_RXMISC_CONFIG__prbs_chk_auto_detect_cnt(reg_value) extract_field((reg_value),12,8) 2834 #define ex_TLB_RX_RXMISC_CONFIG__pam4_decoder_en(reg_value) extract_field((reg_value),6,6) 2835 #define ex_TLB_RX_RXMISC_CONFIG__pam4_gray_dec_en(reg_value) extract_field((reg_value),5,5) 2836 #define ex_TLB_RX_RXMISC_CONFIG__tlb_rx_nrz_ll_mode_en(reg_value) extract_field((reg_value),4,4) 2837 #define ex_TLB_RX_RXMISC_CONFIG__tlb_rx_diff_dec_en(reg_value) extract_field((reg_value),3,3) 2838 #define ex_TLB_RX_RXMISC_CONFIG__dbg_mask_dig_lpbk_en(reg_value) extract_field((reg_value),2,2) 2839 #define ex_TLB_RX_RXMISC_CONFIG__rx_descrambler_en(reg_value) extract_field((reg_value),1,1) 2840 #define ex_TLB_RX_RXMISC_CONFIG__rx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) 2841 #define ex_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timeout(reg_value) extract_field((reg_value),12,8) 2842 #define ex_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timer_mode(reg_value) extract_field((reg_value),1,0) 2843 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__prbs_chk_mode_sel_msb_auto_detect(reg_value) extract_field((reg_value),13,13) 2844 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__prbs_chk_mode_sel_auto_detect(reg_value) extract_field((reg_value),12,10) 2845 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__prbs_chk_inv_auto_detect(reg_value) extract_field((reg_value),9,9) 2846 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__prbs_chk_auto_detect_lock(reg_value) extract_field((reg_value),8,8) 2847 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__dig_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) 2848 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__dig_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) 2849 #define ex_TLB_RX_PRBS_CHK_LOCK_STATUS__prbs_chk_err_cnt_no_clr(reg_value) extract_field((reg_value),15,1) 2850 #define ex_TLB_RX_PRBS_CHK_LOCK_STATUS__prbs_chk_lock(reg_value) extract_field((reg_value),0,0) 2851 #define ex_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_lock_lost_lh(reg_value) extract_field((reg_value),15,15) 2852 #define ex_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_err_cnt_msb(reg_value) extract_field((reg_value),14,0) 2853 #define ex_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS__prbs_chk_err_cnt_lsb(reg_value) extract_field((reg_value),15,0) 2854 #define ex_TLB_RX_PMD_RX_LOCK_STATUS__pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 2855 #define ex_TLB_RX_PMD_RX_LOCK_STATUS__pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 2856 #define ex_TLB_RX_DBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 2857 #define ex_TLB_RX_DBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 2858 #define ex_TLB_RX_UC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 2859 #define ex_TLB_RX_UC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 2860 #define ex_TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS__prbs_burst_err_length_status(reg_value) extract_field((reg_value),5,0) 2861 #define ex_TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS__max_prbs_burst_err_length_status(reg_value) extract_field((reg_value),5,0) 2862 #define ex_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS__prbs_chk_burst_err_cnt(reg_value) extract_field((reg_value),9,0) 2863 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_0__tlb_err_fec_size(reg_value) extract_field((reg_value),15,10) 2864 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_0__tlb_err_fec_l_r_en(reg_value) extract_field((reg_value),9,9) 2865 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_0__tlb_err_fec_l_en(reg_value) extract_field((reg_value),8,8) 2866 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_0__tlb_err_ignore_back_channel(reg_value) extract_field((reg_value),6,6) 2867 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_0__tlb_err_error_count_thresh(reg_value) extract_field((reg_value),5,2) 2868 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_0__tlb_err_clear_error_analyzer_status(reg_value) extract_field((reg_value),1,1) 2869 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_1__tlb_err_clear_status_on_read(reg_value) extract_field((reg_value),4,4) 2870 #define ex_TLB_RX_C_TLB_RX_C_CONFIG_1__tlb_err_histogram_error_thresh(reg_value) extract_field((reg_value),3,0) 2871 #define ex_TLB_RX_C_NUM_ERRORS_IN_FEC_FRAMES_STATUS_HI__tlb_err_count_error_hi(reg_value) extract_field((reg_value),3,0) 2872 #define ex_TLB_RX_C_NUM_ERRORS_IN_FEC_FRAMES_STATUS_LO__tlb_err_count_error_lo(reg_value) extract_field((reg_value),15,0) 2873 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_0__tlb_err_count_histogram_error_offset_0(reg_value) extract_field((reg_value),15,0) 2874 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_1__tlb_err_count_histogram_error_offset_1(reg_value) extract_field((reg_value),15,0) 2875 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_2__tlb_err_count_histogram_error_offset_2(reg_value) extract_field((reg_value),15,0) 2876 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_3__tlb_err_count_histogram_error_offset_3(reg_value) extract_field((reg_value),15,0) 2877 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_4__tlb_err_count_histogram_error_offset_4(reg_value) extract_field((reg_value),15,0) 2878 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_5__tlb_err_count_histogram_error_offset_5(reg_value) extract_field((reg_value),15,0) 2879 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_6__tlb_err_count_histogram_error_offset_6(reg_value) extract_field((reg_value),15,0) 2880 #define ex_TLB_RX_C_COUNT_HISTOGRAM_ERROR_OFFSET_7__tlb_err_count_histogram_error_offset_7(reg_value) extract_field((reg_value),15,0) 2881 #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_start_pos(reg_value) extract_field((reg_value),15,12) 2882 #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_stop_pos(reg_value) extract_field((reg_value),11,8) 2883 #define ex_TLB_TX_PATT_GEN_CONFIG__pam4_tx_jp03b_patt_en(reg_value) extract_field((reg_value),7,7) 2884 #define ex_TLB_TX_PATT_GEN_CONFIG__pam4_tx_linearity_patt_en(reg_value) extract_field((reg_value),6,6) 2885 #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_en(reg_value) extract_field((reg_value),0,0) 2886 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_pause_strobe(reg_value) extract_field((reg_value),15,15) 2887 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_mode_sel_msb(reg_value) extract_field((reg_value),12,12) 2888 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_err_ins(reg_value) extract_field((reg_value),5,5) 2889 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_inv(reg_value) extract_field((reg_value),4,4) 2890 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_mode_sel(reg_value) extract_field((reg_value),3,1) 2891 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_en(reg_value) extract_field((reg_value),0,0) 2892 #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_pd_frc_on(reg_value) extract_field((reg_value),2,2) 2893 #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) 2894 #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_en(reg_value) extract_field((reg_value),0,0) 2895 #define ex_TLB_TX_TXMISC_CONFIG__tx_trn_active_auto_mode_en(reg_value) extract_field((reg_value),4,4) 2896 #define ex_TLB_TX_TXMISC_CONFIG__tlb_tx_diff_enc_en(reg_value) extract_field((reg_value),3,3) 2897 #define ex_TLB_TX_TXMISC_CONFIG__tx_mux_sel_order(reg_value) extract_field((reg_value),2,2) 2898 #define ex_TLB_TX_TXMISC_CONFIG__tx_pcs_native_ana_frmt_en(reg_value) extract_field((reg_value),1,1) 2899 #define ex_TLB_TX_TXMISC_CONFIG__tx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) 2900 #define ex_TLB_TX_TLB_TX_PAM4_CONFIG_0__pam4_tx_symbol_bit_swap(reg_value) extract_field((reg_value),3,3) 2901 #define ex_TLB_TX_TLB_TX_PAM4_CONFIG_0__tx_scrambler_en(reg_value) extract_field((reg_value),2,2) 2902 #define ex_TLB_TX_TLB_TX_PAM4_CONFIG_0__pam4_precoder_en(reg_value) extract_field((reg_value),1,1) 2903 #define ex_TLB_TX_TLB_TX_PAM4_CONFIG_0__pam4_gray_enc_en(reg_value) extract_field((reg_value),0,0) 2904 #define ex_TLB_TX_RMT_LPBK_PD_STATUS__rmt_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) 2905 #define ex_TLB_TX_RMT_LPBK_PD_STATUS__rmt_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) 2906 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_tx_reset_deassert(reg_value) extract_field((reg_value),15,15) 2907 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_tx_s_pwrdn(reg_value) extract_field((reg_value),0,0) 2908 #define ex_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) 2909 #define ex_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) 2910 #define ex_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) 2911 #define ex_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) 2912 #define ex_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) 2913 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) 2914 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_s_rstb(reg_value) extract_field((reg_value),0,0) 2915 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc_val(reg_value) extract_field((reg_value),3,3) 2916 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc(reg_value) extract_field((reg_value),2,2) 2917 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) 2918 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) 2919 #define ex_TX_CKRST_CTRL_TSC_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) 2920 #define ex_TX_CKRST_CTRL_TSC_TX_PMD_LANE_MODE_STATUS__pmd_tx_lane_mode(reg_value) extract_field((reg_value),15,0) 2921 #define ex_TX_CKRST_CTRL_TSC_TX_CLOCK_N_RESET_MISC_CONTROL__tx_pi_loop_filter_stable(reg_value) extract_field((reg_value),0,0) 2922 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__tx_eee_alert_en(reg_value) extract_field((reg_value),15,15) 2923 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__tx_eee_quiet_en(reg_value) extract_field((reg_value),14,14) 2924 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__tx_disable_timer_ctrl(reg_value) extract_field((reg_value),9,4) 2925 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__pmd_tx_disable_pkill(reg_value) extract_field((reg_value),3,3) 2926 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__dp_reset_tx_disable_dis(reg_value) extract_field((reg_value),2,2) 2927 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__tx_disable_trigger(reg_value) extract_field((reg_value),1,1) 2928 #define ex_TX_FED_TXFIR_MICRO_CONTROL0__micro_tx_disable(reg_value) extract_field((reg_value),0,0) 2929 #define ex_TX_FED_TXFIR_MISC_CONTROL0__tx_disable_output_sel(reg_value) extract_field((reg_value),3,2) 2930 #define ex_TX_FED_TXFIR_MISC_CONTROL0__sdk_tx_disable(reg_value) extract_field((reg_value),0,0) 2931 #define ex_TX_FED_TXFIR_MISC_STATUS0__tx_elec_idle_status(reg_value) extract_field((reg_value),1,1) 2932 #define ex_TX_FED_TXFIR_MISC_STATUS0__tx_disable_status(reg_value) extract_field((reg_value),0,0) 2933 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_test_data_en(reg_value) extract_field((reg_value),15,15) 2934 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_tap_en(reg_value) extract_field((reg_value),13,12) 2935 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_tap_load(reg_value) extract_field((reg_value),11,11) 2936 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_nrz_tap_range_sel(reg_value) extract_field((reg_value),10,10) 2937 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_tap0_coeff(reg_value) extract_field_signed((reg_value),8,0) 2938 #define ex_TX_FED_TXFIR_TAP_CONTROL1__txfir_tap1_coeff(reg_value) extract_field_signed((reg_value),8,0) 2939 #define ex_TX_FED_TXFIR_TAP_CONTROL2__txfir_tap2_coeff(reg_value) extract_field_signed((reg_value),8,0) 2940 #define ex_TX_FED_TXFIR_TAP_CONTROL3__txfir_tap3_coeff(reg_value) extract_field_signed((reg_value),8,0) 2941 #define ex_TX_FED_TXFIR_TAP_CONTROL4__txfir_tap4_coeff(reg_value) extract_field_signed((reg_value),8,0) 2942 #define ex_TX_FED_TXFIR_TAP_CONTROL5__txfir_tap5_coeff(reg_value) extract_field_signed((reg_value),8,0) 2943 #define ex_TX_FED_TXFIR_TAP_CONTROL6__txfir_level_shift_mode_en(reg_value) extract_field((reg_value),15,15) 2944 #define ex_TX_FED_TXFIR_TAP_CONTROL6__txfir_dc_adjust(reg_value) extract_field_signed((reg_value),14,8) 2945 #define ex_TX_FED_TXFIR_TAP_CONTROL6__txfir_tap6_coeff(reg_value) extract_field_signed((reg_value),6,0) 2946 #define ex_TX_FED_TXFIR_TAP_CONTROL7__txfir_tap7_coeff(reg_value) extract_field_signed((reg_value),6,0) 2947 #define ex_TX_FED_TXFIR_TAP_CONTROL8__txfir_tap8_coeff(reg_value) extract_field_signed((reg_value),6,0) 2948 #define ex_TX_FED_TXFIR_TAP_CONTROL9__txfir_tap9_coeff(reg_value) extract_field_signed((reg_value),6,0) 2949 #define ex_TX_FED_TXFIR_TAP_CONTROL10__txfir_tap10_coeff(reg_value) extract_field_signed((reg_value),6,0) 2950 #define ex_TX_FED_TXFIR_TAP_CONTROL11__txfir_tap11_coeff(reg_value) extract_field_signed((reg_value),6,0) 2951 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_en(reg_value) extract_field((reg_value),0,0) 2952 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_jitter_filter_en(reg_value) extract_field((reg_value),1,1) 2953 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_ext_ctrl_en(reg_value) extract_field((reg_value),2,2) 2954 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_freq_override_en(reg_value) extract_field((reg_value),3,3) 2955 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_sj_gen_en(reg_value) extract_field((reg_value),4,4) 2956 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_ssc_gen_en(reg_value) extract_field((reg_value),5,5) 2957 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_jit_ssc_freq_mode(reg_value) extract_field((reg_value),6,6) 2958 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_second_order_loop_en(reg_value) extract_field((reg_value),15,15) 2959 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_first_order_bwsel_integ(reg_value) extract_field((reg_value),9,7) 2960 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_second_order_bwsel_integ(reg_value) extract_field((reg_value),11,10) 2961 #define ex_TX_PI_TSC_TXPICONTROL_0__tx_pi_ext_phase_bwsel_integ(reg_value) extract_field((reg_value),14,12) 2962 #define ex_TX_PI_TSC_TXPICONTROL_1__tx_pi_freq_override_val(reg_value) extract_field_signed((reg_value),14,0) 2963 #define ex_TX_PI_TSC_TXPICONTROL_2__tx_pi_jit_freq_idx(reg_value) extract_field((reg_value),5,0) 2964 #define ex_TX_PI_TSC_TXPICONTROL_2__tx_pi_jit_amp(reg_value) extract_field((reg_value),13,8) 2965 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_hs_fifo_phserr_invert(reg_value) extract_field((reg_value),1,1) 2966 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_repeater_mode_en(reg_value) extract_field((reg_value),2,2) 2967 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_ext_pd_sel(reg_value) extract_field((reg_value),3,3) 2968 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_hs_fifo_phserr_sel(reg_value) extract_field((reg_value),4,4) 2969 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_ext_phase_step_cnt_invert(reg_value) extract_field((reg_value),5,5) 2970 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_ext_phase_step_cnt_sel(reg_value) extract_field((reg_value),6,6) 2971 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_ext_phase_step_cnt_full_bypass(reg_value) extract_field((reg_value),7,7) 2972 #define ex_TX_PI_TSC_TXPICONTROL_5__afe_tx_fifo_resetb(reg_value) extract_field((reg_value),8,8) 2973 #define ex_TX_PI_TSC_TXPICONTROL_5__afe_tx_fifo_resetb_frc(reg_value) extract_field((reg_value),9,9) 2974 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_pd_bypass_flt(reg_value) extract_field((reg_value),10,10) 2975 #define ex_TX_PI_TSC_TXPICONTROL_5__tx_pi_pd_bypass_vco(reg_value) extract_field((reg_value),11,11) 2976 #define ex_TX_PI_TSC_TXPISTATUS_1__tx_pi_integ1_reg(reg_value) extract_field_signed((reg_value),13,0) 2977 #define ex_TX_PI_TSC_TXPISTATUS_2__tx_pi_integ2_reg(reg_value) extract_field_signed((reg_value),14,0) 2978 #define ex_TX_PI_TSC_TXPISTATUS_4__st_afe_tx_fifo_resetb(reg_value) extract_field((reg_value),1,1) 2979 #define ex_TX_PI_TSC_TXPISTATUS_4__tx_pi_hs_fifo_phserr(reg_value) extract_field((reg_value),0,0) 2980 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) 2981 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_CONTROL__tx_pam4_mode_frc(reg_value) extract_field((reg_value),14,14) 2982 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_CONTROL__tx_pam4_mode_frc_val(reg_value) extract_field((reg_value),6,4) 2983 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 2984 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__tx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 2985 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_PLL_SELECT_CONTROL__tx_pll_select(reg_value) extract_field((reg_value),0,0) 2986 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LN_S_RSTB_CONTROL__tx_hw_fw_handshake_disable(reg_value) extract_field((reg_value),1,1) 2987 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LN_S_RSTB_CONTROL__tx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) 2988 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 2989 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 2990 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 2991 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 2992 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_DP_RESET_STATE_STATUS__tx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 2993 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL__tx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 2994 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_MULTICAST_MASK_CONTROL__tx_multicast_mask_control(reg_value) extract_field((reg_value),0,0) 2995 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_multicast_mask_control_status(reg_value) extract_field((reg_value),15,15) 2996 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_pam4_mode(reg_value) extract_field((reg_value),6,4) 2997 #define ex_TXCOM_CKRST_CTRL_TSC_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_osr_mode(reg_value) extract_field((reg_value),3,0) 2998 2999 #endif