blackhawk_tsc_access.c (26468B)
1 /*********************************************************************************** 2 *********************************************************************************** 3 * File Name : blackhawk_tsc_access.c * 4 * Created On : 03 Nov 2015 * 5 * Created By : Brent Roberts * 6 * Description : APIs for Serdes IPs * 7 * Revision : * 8 * * 9 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 10 * 11 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 12 * No portions of this material may be reproduced in any form without * 13 * the written permission of: * 14 * Broadcom Corporation * 15 * 5300 California Avenue * 16 * Irvine, CA 92617 * 17 * * 18 * All information contained in this document is Broadcom Corporation * 19 * company private proprietary, and trade secret. * 20 */ 21 22 /** @file blackhawk_tsc_access.c 23 * Implementation of API uC access functions 24 */ 25 26 #include "blackhawk_tsc_access.h" 27 #include "blackhawk_tsc_common.h" 28 #include "blackhawk_tsc_functions.h" 29 #include "blackhawk_tsc_config.h" 30 #include "blackhawk_tsc_internal.h" 31 #include "blackhawk_tsc_internal_error.h" 32 #include "blackhawk_tsc_select_defns.h" 33 34 35 /******************************************************/ 36 /* Commands through Serdes FW DSC Command Interface */ 37 /******************************************************/ 38 39 err_code_t blackhawk_tsc_pmd_uc_cmd_return_immediate(srds_access_t *sa__, enum srds_pmd_uc_cmd_enum cmd, uint8_t supp_info) { 40 err_code_t err_code; 41 uint16_t cmddata; 42 43 err_code = blackhawk_tsc_INTERNAL_poll_uc_dsc_ready_for_cmd_equals_1(sa__, 1, cmd); /* Poll for uc_dsc_ready_for_cmd = 1 to indicate blackhawk_tsc ready for command */ 44 if (err_code) { 45 EFUN_PRINTF(("ERROR : DSC ready for command timed out (before cmd) cmd = %d, supp_info = x%02x err=%d !\n", cmd, supp_info, err_code)); 46 return (err_code); 47 } 48 /*EFUN(wr_uc_dsc_supp_info(supp_info)); */ /* Supplement info field */ 49 /*EFUN(wr_uc_dsc_error_found(0x0) ); */ /* Clear error found field */ 50 /*EFUN(wr_uc_dsc_gp_uc_req(cmd) ); */ /* Set command code */ 51 /*EFUN(wr_uc_dsc_ready_for_cmd(0x0) ); */ /* Issue command, by clearing "ready for command" field */ 52 cmddata = (((uint16_t)supp_info)<<8) | (uint16_t)cmd; /* Combine writes to single write instead of 4 RMW */ 53 54 EFUN(reg_wr_DSC_A_DSC_UC_CTRL(cmddata)); 55 56 return(ERR_CODE_NONE); 57 } 58 59 err_code_t blackhawk_tsc_pmd_uc_cmd(srds_access_t *sa__, enum srds_pmd_uc_cmd_enum cmd, uint8_t supp_info, uint32_t timeout_ms) { 60 61 EFUN(blackhawk_tsc_pmd_uc_cmd_return_immediate(sa__, cmd, supp_info)); /* Invoke blackhawk_tsc_uc_cmd and return control immediately */ 62 63 EFUN(blackhawk_tsc_INTERNAL_poll_uc_dsc_ready_for_cmd_equals_1(sa__, timeout_ms, cmd)); /* Poll for uc_dsc_ready_for_cmd = 1 to indicate blackhawk_tsc ready for command */ 64 65 return(ERR_CODE_NONE); 66 } 67 68 69 err_code_t blackhawk_tsc_pmd_uc_cmd_with_data_return_immediate(srds_access_t *sa__, enum srds_pmd_uc_cmd_enum cmd, uint8_t supp_info, uint16_t data) { 70 uint16_t cmddata; 71 err_code_t err_code; 72 73 err_code = blackhawk_tsc_INTERNAL_poll_uc_dsc_ready_for_cmd_equals_1(sa__, 1, cmd); /* Poll for uc_dsc_ready_for_cmd = 1 to indicate blackhawk_tsc ready for command */ 74 if (err_code) { 75 EFUN_PRINTF(("ERROR : DSC ready for command timed out (before cmd) cmd = %d, supp_info = x%02x, data = x%04x err=%d !\n", cmd, supp_info, data,err_code)); 76 return (err_code); 77 } 78 79 EFUN(wr_uc_dsc_data(data)); /* Write value written to uc_dsc_data field */ 80 /*EFUN(wr_uc_dsc_supp_info(supp_info)); */ /* Supplement info field */ 81 /*EFUN(wr_uc_dsc_error_found(0x0)); */ /* Clear error found field */ 82 /*EFUN(wr_uc_dsc_gp_uc_req(cmd)); */ /* Set command code */ 83 /*EFUN(wr_uc_dsc_ready_for_cmd(0x0)); */ /* Issue command, by clearing "ready for command" field */ 84 cmddata = (((uint16_t)supp_info)<<8) | (uint16_t)cmd; /* Combine writes to single write instead of 4 RMW */ 85 86 EFUN(reg_wr_DSC_A_DSC_UC_CTRL(cmddata)); 87 88 return(ERR_CODE_NONE); 89 } 90 91 92 err_code_t blackhawk_tsc_pmd_uc_cmd_with_data(srds_access_t *sa__, enum srds_pmd_uc_cmd_enum cmd, uint8_t supp_info, uint16_t data, uint32_t timeout_ms) { 93 94 EFUN(blackhawk_tsc_pmd_uc_cmd_with_data_return_immediate(sa__, cmd, supp_info, data)); /* Invoke blackhawk_tsc_uc_cmd and return control immediately */ 95 96 EFUN(blackhawk_tsc_INTERNAL_poll_uc_dsc_ready_for_cmd_equals_1(sa__, timeout_ms, cmd)); /* Poll for uc_dsc_ready_for_cmd = 1 to indicate blackhawk_tsc ready for command */ 97 return(ERR_CODE_NONE); 98 } 99 100 err_code_t blackhawk_tsc_pmd_uc_control_return_immediate(srds_access_t *sa__, enum srds_pmd_uc_ctrl_cmd_enum control) { 101 return(blackhawk_tsc_pmd_uc_cmd_return_immediate(sa__, CMD_UC_CTRL, (uint8_t) control)); 102 } 103 104 err_code_t blackhawk_tsc_pmd_uc_control(srds_access_t *sa__, enum srds_pmd_uc_ctrl_cmd_enum control, uint32_t timeout_ms) { 105 return(blackhawk_tsc_pmd_uc_cmd(sa__, CMD_UC_CTRL, (uint8_t) control, timeout_ms)); 106 } 107 108 err_code_t blackhawk_tsc_pmd_uc_diag_cmd(srds_access_t *sa__, enum srds_pmd_uc_diag_cmd_enum control, uint32_t timeout_ms) { 109 return(blackhawk_tsc_pmd_uc_cmd(sa__, CMD_DIAG_EN, (uint8_t) control, timeout_ms)); 110 } 111 112 /************************************************************/ 113 /* Serdes IP RAM access - Lane RAM Variables */ 114 /*----------------------------------------------------------*/ 115 /* - through Micro Register Interface for PMD IPs */ 116 /* - through Serdes FW DSC Command Interface for Gallardo */ 117 /************************************************************/ 118 119 /* This function returns the absolute address of lane RAM variables given the offset address and lane */ 120 uint16_t blackhawk_tsc_INTERNAL_get_lane_addr(srds_access_t *sa__, uint16_t addr, uint8_t lane) { 121 uint16_t lane_var_ram_base=0, lane_var_ram_size=0; 122 uint16_t lane_addr_offset = 0; 123 124 uint16_t grp_ram_size=0,lane_count=0; 125 srds_info_t * blackhawk_tsc_info_ptr = blackhawk_tsc_INTERNAL_get_blackhawk_tsc_info_ptr_with_check(sa__); 126 #ifdef PHYMOD_SUPPORT 127 if ( blackhawk_tsc_info_ptr == NULL ) { 128 blackhawk_tsc_init_blackhawk_tsc_info(sa__); 129 } else if (blackhawk_tsc_info_ptr->signature != SRDS_INFO_SIGNATURE) { 130 blackhawk_tsc_init_blackhawk_tsc_info(sa__); 131 } 132 #endif /* PHYMOD_SUPPORT */ 133 lane_var_ram_base = blackhawk_tsc_info_ptr->lane_var_ram_base; 134 lane_var_ram_size = blackhawk_tsc_info_ptr->lane_var_ram_size; 135 grp_ram_size = blackhawk_tsc_info_ptr->grp_ram_size; 136 lane_count = blackhawk_tsc_info_ptr->lane_count; 137 lane_addr_offset = lane_var_ram_base+addr+((lane%lane_count)*lane_var_ram_size) + (grp_ram_size*blackhawk_tsc_INTERNAL_grp_idx_from_lane(lane)); 138 return(lane_addr_offset); 139 } 140 141 /* Micro RAM Lane Byte Read */ 142 uint8_t blackhawk_tsc_rdbl_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 143 uint8_t rddata; 144 uint16_t lane_addr_offset = 0; 145 uint8_t lane; 146 147 if(!err_code_p) { 148 return(0); 149 } 150 151 { 152 lane = blackhawk_tsc_get_physical_lane(sa__); 153 lane_addr_offset = blackhawk_tsc_INTERNAL_get_lane_addr(sa__, addr,lane); 154 155 EPSTM(rddata = blackhawk_tsc_rdb_uc_ram(sa__, err_code_p, lane_addr_offset)); /* Use Micro register interface for reading RAM */ 156 return (rddata); 157 } 158 } 159 160 /* Micro RAM Lane Byte Signed Read */ 161 int8_t blackhawk_tsc_rdbls_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 162 return ((int8_t) blackhawk_tsc_rdbl_uc_var(sa__, err_code_p, addr)); 163 } 164 165 /* Micro RAM Lane Word Read */ 166 uint16_t blackhawk_tsc_rdwl_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 167 uint16_t rddata; 168 uint16_t lane_addr_offset = 0; 169 uint8_t lane; 170 171 if(!err_code_p) { 172 return(0); 173 } 174 if (addr%2 != 0) { /* Validate even address */ 175 *err_code_p = ERR_CODE_INVALID_RAM_ADDR; 176 return (0); 177 } 178 179 { 180 lane = blackhawk_tsc_get_physical_lane(sa__); 181 lane_addr_offset = blackhawk_tsc_INTERNAL_get_lane_addr(sa__, addr,lane); 182 183 EPSTM(rddata = blackhawk_tsc_rdw_uc_ram(sa__, err_code_p, lane_addr_offset)); /* Use Micro register interface for reading RAM */ 184 return (rddata); 185 } 186 } 187 188 189 /* Micro RAM Lane Word Signed Read */ 190 int16_t blackhawk_tsc_rdwls_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 191 return ((int16_t) blackhawk_tsc_rdwl_uc_var(sa__, err_code_p, addr)); 192 } 193 194 /* Micro RAM Lane Byte Write */ 195 err_code_t blackhawk_tsc_wrbl_uc_var(srds_access_t *sa__, uint16_t addr, uint8_t wr_val) { 196 uint16_t lane_addr_offset = 0; 197 uint8_t lane; 198 199 200 { 201 lane = blackhawk_tsc_get_physical_lane(sa__); 202 lane_addr_offset = blackhawk_tsc_INTERNAL_get_lane_addr(sa__, addr,lane); 203 204 return (blackhawk_tsc_wrb_uc_ram(sa__, lane_addr_offset, wr_val)); /* Use Micro register interface for writing RAM */ 205 } 206 } 207 208 /* Micro RAM Lane Byte Signed Write */ 209 err_code_t blackhawk_tsc_wrbls_uc_var(srds_access_t *sa__, uint16_t addr, int8_t wr_val) { 210 return (blackhawk_tsc_wrbl_uc_var(sa__, addr, wr_val)); 211 } 212 213 /* Micro RAM Lane Word Write */ 214 err_code_t blackhawk_tsc_wrwl_uc_var(srds_access_t *sa__, uint16_t addr, uint16_t wr_val) { 215 uint16_t lane_addr_offset = 0; 216 uint8_t lane; 217 218 if (addr%2 != 0) { /* Validate even address */ 219 return (blackhawk_tsc_error(sa__, ERR_CODE_INVALID_RAM_ADDR)); 220 } 221 222 { 223 lane = blackhawk_tsc_get_physical_lane(sa__); 224 lane_addr_offset = blackhawk_tsc_INTERNAL_get_lane_addr(sa__, addr,lane); 225 226 return (blackhawk_tsc_wrw_uc_ram(sa__, lane_addr_offset, wr_val)); /* Use Micro register interface for writing RAM */ 227 } 228 229 } 230 231 /* Micro RAM Lane Word Signed Write */ 232 err_code_t blackhawk_tsc_wrwls_uc_var(srds_access_t *sa__, uint16_t addr, int16_t wr_val) { 233 return (blackhawk_tsc_wrwl_uc_var(sa__, addr,wr_val)); 234 } 235 236 237 /************************************************************/ 238 /* Serdes IP RAM access - Micro RAM Variables */ 239 /*----------------------------------------------------------*/ 240 /* - through Micro Register Interface for PMD IPs */ 241 /************************************************************/ 242 243 /* This function returns the absolute address of uc RAM variables given the offset address and lane */ 244 uint16_t blackhawk_tsc_INTERNAL_get_uc_address(srds_access_t *sa__, uint16_t addr, uint8_t lane) { 245 uint16_t micro_var_ram_base=0, grp_ram_size=0; 246 uint16_t uc_addr_offset = 0; 247 srds_info_t * blackhawk_tsc_info_ptr = blackhawk_tsc_INTERNAL_get_blackhawk_tsc_info_ptr_with_check(sa__); 248 #ifdef PHYMOD_SUPPORT 249 if ( blackhawk_tsc_info_ptr == NULL ) { 250 blackhawk_tsc_init_blackhawk_tsc_info(sa__); 251 } else if (blackhawk_tsc_info_ptr->signature != SRDS_INFO_SIGNATURE) { 252 blackhawk_tsc_init_blackhawk_tsc_info(sa__); 253 } 254 #endif /* PHYMOD_SUPPORT */ 255 micro_var_ram_base = blackhawk_tsc_info_ptr->micro_var_ram_base; 256 grp_ram_size = blackhawk_tsc_info_ptr->grp_ram_size; 257 uc_addr_offset = micro_var_ram_base + addr + (grp_ram_size*blackhawk_tsc_INTERNAL_grp_idx_from_lane(lane)); 258 return(uc_addr_offset); 259 } 260 261 /* Micro RAM UC Byte Read */ 262 uint8_t blackhawk_tsc_rdbuc_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 263 uint8_t rddata; 264 uint16_t uc_addr_offset = 0; 265 uint8_t lane; 266 267 if(!err_code_p) { 268 return(0); 269 } 270 271 lane = blackhawk_tsc_get_physical_lane(sa__); 272 uc_addr_offset = blackhawk_tsc_INTERNAL_get_uc_address(sa__, addr,lane); 273 274 EPSTM(rddata = blackhawk_tsc_rdb_uc_ram(sa__, err_code_p, uc_addr_offset)); /* Use Micro register interface for reading RAM */ 275 return (rddata); 276 } 277 278 /* Micro RAM UC Byte Signed Read */ 279 int8_t blackhawk_tsc_rdbucs_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 280 return ((int8_t) blackhawk_tsc_rdbuc_uc_var(sa__, err_code_p, addr)); 281 } 282 283 /* Micro RAM UC Word Read */ 284 uint16_t blackhawk_tsc_rdwuc_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 285 uint16_t rddata; 286 uint16_t uc_addr_offset = 0; 287 uint8_t lane; 288 289 if(!err_code_p) { 290 return(0); 291 } 292 if (addr%2 != 0) { /* Validate even address */ 293 *err_code_p = ERR_CODE_INVALID_RAM_ADDR; 294 return (0); 295 } 296 297 lane = blackhawk_tsc_get_physical_lane(sa__); 298 uc_addr_offset = blackhawk_tsc_INTERNAL_get_uc_address(sa__, addr,lane); 299 300 EPSTM(rddata = blackhawk_tsc_rdw_uc_ram(sa__, err_code_p, uc_addr_offset)); /* Use Micro register interface for reading RAM */ 301 return (rddata); 302 } 303 304 305 /* Micro RAM UC Word Signed Read */ 306 int16_t blackhawk_tsc_rdwucs_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 307 return ((int16_t) blackhawk_tsc_rdwuc_uc_var(sa__, err_code_p, addr)); 308 } 309 310 /* Micro RAM UC Byte Write */ 311 err_code_t blackhawk_tsc_wrbuc_uc_var(srds_access_t *sa__, uint16_t addr, uint8_t wr_val) { 312 313 uint16_t uc_addr_offset = 0; 314 uint8_t lane; 315 316 lane = blackhawk_tsc_get_physical_lane(sa__); 317 uc_addr_offset = blackhawk_tsc_INTERNAL_get_uc_address(sa__, addr,lane); 318 319 return (blackhawk_tsc_wrb_uc_ram(sa__, uc_addr_offset, wr_val)); /* Use Micro register interface for writing RAM */ 320 } 321 322 /* Micro RAM UC Byte Signed Write */ 323 err_code_t blackhawk_tsc_wrbucs_uc_var(srds_access_t *sa__, uint16_t addr, int8_t wr_val) { 324 return (blackhawk_tsc_wrbuc_uc_var(sa__, addr, wr_val)); 325 } 326 327 /* Micro RAM UC Word Write */ 328 err_code_t blackhawk_tsc_wrwuc_uc_var(srds_access_t *sa__, uint16_t addr, uint16_t wr_val) { 329 uint16_t uc_addr_offset = 0; 330 uint8_t lane; 331 332 if (addr%2 != 0) { /* Validate even address */ 333 return (blackhawk_tsc_error(sa__, ERR_CODE_INVALID_RAM_ADDR)); 334 } 335 lane = blackhawk_tsc_get_physical_lane(sa__); 336 uc_addr_offset = blackhawk_tsc_INTERNAL_get_uc_address(sa__, addr,lane); 337 338 return (blackhawk_tsc_wrw_uc_ram(sa__, uc_addr_offset, wr_val)); /* Use Micro register interface for writing RAM */ 339 } 340 341 /* Micro RAM UC Word Signed Write */ 342 err_code_t blackhawk_tsc_wrwucs_uc_var(srds_access_t *sa__, uint16_t addr, int16_t wr_val) { 343 return (blackhawk_tsc_wrwuc_uc_var(sa__, addr,wr_val)); 344 } 345 346 347 348 /************************************************************/ 349 /* Serdes IP RAM access - Core RAM Variables */ 350 /*----------------------------------------------------------*/ 351 /* - through Micro Register Interface for PMD IPs */ 352 /* - through Serdes FW DSC Command Interface for Gallardo */ 353 /************************************************************/ 354 355 /* This function returns the absolute address of core RAM variables given the offset address and lane */ 356 uint16_t blackhawk_tsc_INTERNAL_get_core_address(srds_access_t *sa__, uint16_t addr, uint8_t lane) { 357 uint16_t core_var_ram_base=0; 358 uint16_t core_addr_offset = 0; 359 360 srds_info_t * blackhawk_tsc_info_ptr = blackhawk_tsc_INTERNAL_get_blackhawk_tsc_info_ptr_with_check(sa__); 361 #ifdef PHYMOD_SUPPORT 362 if ( blackhawk_tsc_info_ptr == NULL ) { 363 blackhawk_tsc_init_blackhawk_tsc_info(sa__); 364 } else if (blackhawk_tsc_info_ptr->signature != SRDS_INFO_SIGNATURE) { 365 blackhawk_tsc_init_blackhawk_tsc_info(sa__); 366 } 367 #endif /* PHYMOD_SUPPORT */ 368 core_var_ram_base = blackhawk_tsc_info_ptr->core_var_ram_base; 369 core_addr_offset = core_var_ram_base + addr; 370 371 UNUSED(lane); 372 return(core_addr_offset); 373 } 374 375 /* Micro RAM Core Byte Read */ 376 uint8_t blackhawk_tsc_rdbc_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint8_t addr) { 377 378 uint8_t rddata; 379 uint8_t lane; 380 uint16_t core_addr_offset; 381 if(!err_code_p) { 382 return(0); 383 } 384 385 { 386 lane = blackhawk_tsc_get_physical_lane(sa__); 387 core_addr_offset = blackhawk_tsc_INTERNAL_get_core_address(sa__, addr,lane); 388 EPSTM(rddata = blackhawk_tsc_rdb_uc_ram(sa__, err_code_p, core_addr_offset)); /* Use Micro register interface for reading RAM */ 389 return (rddata); 390 } 391 } 392 393 /* Micro RAM Core Byte Signed Read */ 394 int8_t blackhawk_tsc_rdbcs_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint8_t addr) { 395 return ((int8_t) blackhawk_tsc_rdbc_uc_var(sa__, err_code_p, addr)); 396 } 397 398 /* Micro RAM Core Word Read */ 399 uint16_t blackhawk_tsc_rdwc_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint8_t addr) { 400 uint16_t rddata; 401 uint8_t lane; 402 uint16_t core_addr_offset; 403 404 if(!err_code_p) { 405 return(0); 406 } 407 if (addr%2 != 0) { /* Validate even address */ 408 *err_code_p = ERR_CODE_INVALID_RAM_ADDR; 409 return (0); 410 } 411 412 { 413 lane = blackhawk_tsc_get_physical_lane(sa__); 414 core_addr_offset = blackhawk_tsc_INTERNAL_get_core_address(sa__, addr,lane); 415 416 EPSTM(rddata = blackhawk_tsc_rdw_uc_ram(sa__, err_code_p, core_addr_offset)); /* Use Micro register interface for reading RAM */ 417 return (rddata); 418 } 419 } 420 421 /* Micro RAM Core Word Signed Read */ 422 int16_t blackhawk_tsc_rdwcs_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint8_t addr) { 423 return ((int16_t) blackhawk_tsc_rdwc_uc_var(sa__, err_code_p, addr)); 424 } 425 426 /* Micro RAM Core Byte Write */ 427 err_code_t blackhawk_tsc_wrbc_uc_var(srds_access_t *sa__, uint8_t addr, uint8_t wr_val) { 428 uint8_t lane; 429 uint16_t core_addr_offset; 430 431 { 432 lane = blackhawk_tsc_get_physical_lane(sa__); 433 core_addr_offset = blackhawk_tsc_INTERNAL_get_core_address(sa__, addr,lane); 434 435 return (blackhawk_tsc_wrb_uc_ram(sa__, core_addr_offset, wr_val)); /* Use Micro register interface for writing RAM */ 436 } 437 438 } 439 440 441 /* Micro RAM Core Byte Signed Write */ 442 err_code_t blackhawk_tsc_wrbcs_uc_var(srds_access_t *sa__, uint8_t addr, int8_t wr_val) { 443 return (blackhawk_tsc_wrbc_uc_var(sa__, addr, wr_val)); 444 } 445 446 /* Micro RAM Core Word Write */ 447 err_code_t blackhawk_tsc_wrwc_uc_var(srds_access_t *sa__, uint8_t addr, uint16_t wr_val) { 448 uint8_t lane; 449 uint16_t core_addr_offset; 450 451 { 452 if (addr%2 != 0) { /* Validate even address */ 453 return (blackhawk_tsc_error(sa__, ERR_CODE_INVALID_RAM_ADDR)); 454 } 455 456 lane = blackhawk_tsc_get_physical_lane(sa__); 457 core_addr_offset = blackhawk_tsc_INTERNAL_get_core_address(sa__, addr,lane); 458 return (blackhawk_tsc_wrw_uc_ram(sa__, core_addr_offset, wr_val)); /* Use Micro register interface for writing RAM */ 459 } 460 } 461 462 /* Micro RAM Core Word Signed Write */ 463 err_code_t blackhawk_tsc_wrwcs_uc_var(srds_access_t *sa__, uint8_t addr, int16_t wr_val) { 464 return(blackhawk_tsc_wrwc_uc_var(sa__, addr,wr_val)); 465 } 466 467 /*********************************************************/ 468 /* Program RAM access through Micro Register Interface */ 469 /*********************************************************/ 470 471 /* Micro Program Ram Long Read */ 472 uint32_t blackhawk_tsc_rd_long_uc_prog_ram(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 473 uint32_t rddata; 474 if(!err_code_p) { 475 return(0); 476 } 477 *err_code_p = ERR_CODE_NONE; 478 EPFUN(wrc_micro_autoinc_rdaddr_en(1)); 479 EPFUN(wrc_micro_ra_rddatasize(0x1)); /* Select 16bit read datasize */ 480 EPFUN(wrc_micro_ra_rdaddr_msw(0)); /* Upper 16bits of ROM address to be read */ 481 EPFUN(wrc_micro_ra_rdaddr_lsw(addr)); /* Lower 16bits of ROM address to be read */ 482 EPSTM(rddata = rdc_micro_ra_rddata_lsw()); /* 16bit read data */ 483 EPSTM(rddata |= (rdc_micro_ra_rddata_lsw() << 16)); /* 16bit read data */ 484 return (rddata); 485 } 486 487 /* Micro Program RAM Block Read */ 488 err_code_t blackhawk_tsc_rdblk_uc_prog_ram(srds_access_t *sa__, uint8_t *mem, uint16_t addr, uint16_t cnt) { 489 blackhawk_tsc_INTERNAL_rdblk_callback_arg_t arg; 490 491 if(!mem) { 492 return(blackhawk_tsc_error(sa__, ERR_CODE_BAD_PTR_OR_INVALID_INPUT)); 493 } 494 495 arg.mem_ptr = mem; 496 arg.sa = sa__; 497 return blackhawk_tsc_INTERNAL_rdblk_uc_generic_ram(sa__, addr, cnt, 0, cnt, &arg, blackhawk_tsc_INTERNAL_rdblk_callback); 498 } 499 500 /*************************************************/ 501 /* RAM access through Micro Register Interface */ 502 /*************************************************/ 503 504 /* Micro RAM Long Write */ 505 err_code_t blackhawk_tsc_wr_long_uc_ram(srds_access_t *sa__, uint16_t offset, uint32_t value) { 506 EFUN(blackhawk_tsc_wrw_uc_ram(sa__, offset+2, value >> 16)); 507 EFUN(blackhawk_tsc_wrw_uc_ram(sa__, offset, value & 0xFFFF)); 508 return (ERR_CODE_NONE); 509 } 510 /* Micro RAM Word Write */ 511 err_code_t blackhawk_tsc_wrw_uc_ram(srds_access_t *sa__, uint16_t addr, uint16_t wr_val) { 512 513 EFUN(wrc_micro_autoinc_wraddr_en(0)); 514 EFUN(wrc_micro_ra_wrdatasize(0x1)); /* Select 16bit write datasize */ 515 EFUN(wrc_micro_ra_wraddr_msw(0x2000)); /* Upper 16bits of RAM address to be written to */ 516 EFUN(wrc_micro_ra_wraddr_lsw(addr)); /* Lower 16bits of RAM address to be written to */ 517 EFUN(wrc_micro_ra_wrdata_lsw(wr_val)); /* uC RAM lower 16bits write data */ 518 return (ERR_CODE_NONE); 519 } 520 521 /* Micro RAM Byte Write */ 522 err_code_t blackhawk_tsc_wrb_uc_ram(srds_access_t *sa__, uint16_t addr, uint8_t wr_val) { 523 EFUN(wrc_micro_autoinc_wraddr_en(0)); 524 EFUN(wrc_micro_ra_wrdatasize(0x0)); /* Select 8bit write datasize */ 525 EFUN(wrc_micro_ra_wraddr_msw(0x2000)); /* Upper 16bits of RAM address to be written to */ 526 EFUN(wrc_micro_ra_wraddr_lsw(addr)); /* Lower 16bits of RAM address to be written to */ 527 EFUN(wrc_micro_ra_wrdata_lsw(wr_val)); /* uC RAM lower 16bits write data */ 528 return (ERR_CODE_NONE); 529 } 530 531 /* Micro RAM Long Read */ 532 uint32_t blackhawk_tsc_rd_long_uc_ram(srds_access_t *sa__, err_code_t *err, uint16_t offset) { 533 uint32_t result; 534 ESTM(result = blackhawk_tsc_rdw_uc_ram(sa__, err, offset+2) << 16); 535 ESTM(result |= blackhawk_tsc_rdw_uc_ram(sa__, err, offset) & 0xFFFF); 536 return result; 537 } 538 /* Micro RAM Word Read */ 539 uint16_t blackhawk_tsc_rdw_uc_ram(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 540 uint16_t rddata; 541 if(!err_code_p) { 542 return(0); 543 } 544 *err_code_p = ERR_CODE_NONE; 545 EPFUN(wrc_micro_autoinc_rdaddr_en(0)); 546 EPFUN(wrc_micro_ra_rddatasize(0x1)); /* Select 16bit read datasize */ 547 EPFUN(wrc_micro_ra_rdaddr_msw(0x2000)); /* Upper 16bits of RAM address to be read */ 548 EPFUN(wrc_micro_ra_rdaddr_lsw(addr)); /* Lower 16bits of RAM address to be read */ 549 EPSTM(rddata = rdc_micro_ra_rddata_lsw()); /* 16bit read data */ 550 return (rddata); 551 } 552 553 /* Micro RAM Byte Read */ 554 uint8_t blackhawk_tsc_rdb_uc_ram(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 555 uint8_t rddata; 556 if(!err_code_p) { 557 return(0); 558 } 559 *err_code_p = ERR_CODE_NONE; 560 EPFUN(wrc_micro_autoinc_rdaddr_en(0)); 561 EPFUN(wrc_micro_ra_rddatasize(0x0)); /* Select 8bit read datasize */ 562 EPFUN(wrc_micro_ra_rdaddr_msw(0x2000)); /* Upper 16bits of RAM address to be read */ 563 EPFUN(wrc_micro_ra_rdaddr_lsw(addr)); /* Lower 16bits of RAM address to be read */ 564 EPSTM(rddata = (uint8_t) rdc_micro_ra_rddata_lsw()); /* 16bit read data */ 565 return (rddata); 566 } 567 568 /* Micro RAM Word Signed Write */ 569 err_code_t blackhawk_tsc_wrws_uc_ram(srds_access_t *sa__, uint16_t addr, int16_t wr_val) { 570 return (blackhawk_tsc_wrw_uc_ram(sa__, addr, wr_val)); 571 } 572 573 /* Micro RAM Byte Signed Write */ 574 err_code_t blackhawk_tsc_wrbs_uc_ram(srds_access_t *sa__, uint16_t addr, int8_t wr_val) { 575 return (blackhawk_tsc_wrb_uc_ram(sa__, addr, wr_val)); 576 } 577 578 /* Micro RAM Word Signed Read */ 579 int16_t blackhawk_tsc_rdws_uc_ram(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 580 return ((int16_t)blackhawk_tsc_rdw_uc_ram(sa__, err_code_p, addr)); 581 } 582 583 /* Micro RAM Byte Signed Read */ 584 int8_t blackhawk_tsc_rdbs_uc_ram(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr) { 585 return ((int8_t)blackhawk_tsc_rdb_uc_ram(sa__, err_code_p, addr)); 586 } 587 588 /* Micro RAM Block Read */ 589 err_code_t blackhawk_tsc_rdblk_uc_ram(srds_access_t *sa__, uint8_t *mem, uint16_t addr, uint16_t cnt) { 590 blackhawk_tsc_INTERNAL_rdblk_callback_arg_t arg; 591 592 if(!mem) { 593 return(blackhawk_tsc_error(sa__, ERR_CODE_BAD_PTR_OR_INVALID_INPUT)); 594 } 595 596 arg.mem_ptr = mem; 597 arg.sa = sa__; 598 return blackhawk_tsc_INTERNAL_rdblk_uc_generic_ram(sa__, (uint32_t)addr | 0x20000000, cnt, 0, cnt, &arg, blackhawk_tsc_INTERNAL_rdblk_callback); 599 } 600 601 /**************************/ 602 /* Temperature reading */ 603 /**************************/ 604 605 err_code_t blackhawk_tsc_read_die_temperature (srds_access_t *sa__, int16_t *die_temp) { 606 607 uint16_t die_temp_sensor_reading; 608 609 ESTM(die_temp_sensor_reading=rdc_micro_pvt_tempdata_rmi()); 610 *die_temp = _bin_to_degC(die_temp_sensor_reading); 611 612 return(ERR_CODE_NONE); 613 } 614 615 616 err_code_t blackhawk_tsc_read_die_temperature_double (srds_access_t *sa__, USR_DOUBLE *die_temp) { 617 #ifdef SERDES_API_FLOATING_POINT 618 uint16_t die_temp_sensor_reading; 619 620 ESTM(die_temp_sensor_reading=rdc_micro_pvt_tempdata_rmi()); 621 622 *die_temp = _bin_to_degC_double(die_temp_sensor_reading); 623 624 return(ERR_CODE_NONE); 625 #else 626 *die_temp = 0; 627 EFUN_PRINTF((" Function 'blackhawk_tsc_read_die_temperature_double' needs SERDES_API_FLOATING_POINT defined to operate \n")); 628 return(blackhawk_tsc_error(sa__, ERR_CODE_BAD_PTR_OR_INVALID_INPUT)); 629 #endif 630 } 631