blackhawk_cfg_seq.c (38685B)
1 /* 2 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 3 * 4 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 5 * 6 */ 7 8 /* 9 * 10 * 11 * 12 * This program is the proprietary software of Broadcom Corporation 13 * and/or its licensors, and may only be used, duplicated, modified 14 * or distributed pursuant to the terms and conditions of a separate, 15 * written license agreement executed between you and Broadcom 16 * (an "Authorized License"). Except as set forth in an Authorized 17 * License, Broadcom grants no license (express or implied), right 18 * to use, or waiver of any kind with respect to the Software, and 19 * Broadcom expressly reserves all rights in and to the Software 20 * and all intellectual property rights therein. IF YOU HAVE 21 * NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE 22 * IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE 23 * ALL USE OF THE SOFTWARE. 24 * 25 * Except as expressly set forth in the Authorized License, 26 * 27 * 1. This program, including its structure, sequence and organization, 28 * constitutes the valuable trade secrets of Broadcom, and you shall use 29 * all reasonable efforts to protect the confidentiality thereof, 30 * and to use this information only in connection with your use of 31 * Broadcom integrated circuit products. 32 * 33 * 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS 34 * PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, 35 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, 36 * OR OTHERWISE, WITH RESPECT TO THE SOFTWARE. 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THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING 51 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$ 52 */ 53 54 55 #include <phymod/phymod.h> 56 #include <phymod/phymod_system.h> 57 #include <phymod/chip/bcmi_blackhawk_xgxs_defs.h> 58 #include <phymod/phymod_util.h> 59 #include "blackhawk_cfg_seq.h" 60 #include "blackhawk_tsc_fields.h" 61 #include "blackhawk_tsc_field_access.h" 62 #include "blackhawk_tsc_dependencies.h" 63 #include "blackhawk_tsc_interface.h" 64 #include "blackhawk_tsc_functions.h" 65 #include "public/blackhawk_api_uc_vars_rdwr_defns_public.h" 66 67 68 err_code_t blackhawk_tx_rx_polarity_set( phymod_access_t *sa__, uint32_t tx_pol, uint32_t rx_pol) 69 { 70 err_code_t __err; 71 __err=ERR_CODE_NONE; 72 __err = (uint32_t) wr_tx_pmd_dp_invert(tx_pol); 73 if(__err) return(__err); 74 __err = (uint32_t) wr_rx_pmd_dp_invert(rx_pol); 75 if(__err) return(__err); 76 77 return ERR_CODE_NONE; 78 } 79 80 err_code_t blackhawk_lane_pll_selection_set( phymod_access_t *sa__, uint32_t pll_index) 81 { 82 err_code_t __err; 83 __err=ERR_CODE_NONE; 84 __err = (uint32_t) wr_pll_select(pll_index); 85 if(__err) return(__err); 86 87 return ERR_CODE_NONE; 88 } 89 90 err_code_t blackhawk_lane_pll_selection_get( phymod_access_t *sa__, uint32_t *pll_index) 91 { 92 err_code_t __err; 93 __err=ERR_CODE_NONE; 94 *pll_index = (uint32_t) rd_pll_select(); 95 if(__err) return(__err); 96 97 return ERR_CODE_NONE; 98 } 99 100 101 err_code_t blackhawk_tx_rx_polarity_get( phymod_access_t *sa__, uint32_t *tx_pol, uint32_t *rx_pol) 102 { 103 err_code_t __err; 104 __err=ERR_CODE_NONE; 105 *tx_pol = (uint32_t) rd_tx_pmd_dp_invert(); 106 if(__err) return(__err); 107 *rx_pol = (uint32_t) rd_rx_pmd_dp_invert(); 108 if(__err) return(__err); 109 return ERR_CODE_NONE; 110 111 } 112 113 err_code_t blackhawk_uc_active_set( phymod_access_t *sa__, uint32_t enable) 114 { 115 err_code_t __err; 116 __err=ERR_CODE_NONE; 117 __err=wrc_uc_active(enable); 118 if(__err) return(__err); 119 120 return ERR_CODE_NONE; 121 } 122 123 err_code_t blackhawk_uc_active_get( phymod_access_t *sa__, uint32_t *enable) 124 { 125 err_code_t __err; 126 __err=ERR_CODE_NONE; 127 *enable = (uint32_t) rdc_uc_active(); 128 if(__err) return(__err); 129 130 return ERR_CODE_NONE; 131 } 132 133 134 /* 135 err_code_t blackhawk_uc_reset( phymod_access_t *sa__, uint32_t enable) 136 { 137 return ERR_CODE_NONE; 138 } 139 */ 140 141 err_code_t blackhawk_force_tx_set_rst ( phymod_access_t *sa__, uint32_t rst) 142 { 143 return ERR_CODE_NONE; 144 } 145 146 err_code_t blackhawk_force_tx_get_rst ( phymod_access_t *sa__, uint32_t *rst) 147 { 148 return ERR_CODE_NONE; 149 } 150 151 err_code_t blackhawk_force_rx_set_rst ( phymod_access_t *sa__, uint32_t rst) 152 { 153 return ERR_CODE_NONE; 154 } 155 156 err_code_t blackhawk_force_rx_get_rst ( phymod_access_t *sa__, uint32_t *rst) 157 { 158 return ERR_CODE_NONE; 159 } 160 161 err_code_t blackhawk_prbs_tx_inv_data_get( phymod_access_t *sa__, uint32_t *inv_data) 162 { 163 return ERR_CODE_NONE; 164 } 165 166 err_code_t blackhawk_prbs_rx_inv_data_get( phymod_access_t *sa__, uint32_t *inv_data) 167 { 168 return ERR_CODE_NONE; 169 } 170 171 err_code_t blackhawk_prbs_tx_poly_get( phymod_access_t *sa__, blackhawk_prbs_polynomial_type_t *prbs_poly) 172 { 173 return ERR_CODE_NONE; 174 } 175 176 err_code_t blackhawk_prbs_rx_poly_get( phymod_access_t *sa__, blackhawk_prbs_polynomial_type_t *prbs_poly) 177 { 178 return ERR_CODE_NONE; 179 } 180 181 err_code_t blackhawk_prbs_tx_enable_get( phymod_access_t *sa__, uint32_t *enable) 182 { 183 return ERR_CODE_NONE; 184 } 185 186 err_code_t blackhawk_prbs_rx_enable_get( phymod_access_t *sa__, uint32_t *enable) 187 { 188 return ERR_CODE_NONE; 189 } 190 191 err_code_t blackhawk_pmd_force_signal_detect( phymod_access_t *sa__, uint8_t force_en, uint8_t force_val) 192 { 193 err_code_t __err; 194 __err=ERR_CODE_NONE; 195 __err = wr_signal_detect_frc(force_en); 196 if(__err) return(__err); 197 __err = wr_signal_detect_frc_val(force_val); 198 if(__err) return(__err); 199 200 return ERR_CODE_NONE; 201 } 202 203 err_code_t blackhawk_pmd_force_signal_detect_get( phymod_access_t *sa__, uint8_t *force_en, uint8_t *force_val) 204 { 205 err_code_t __err; 206 __err=ERR_CODE_NONE; 207 *force_en = rd_signal_detect_frc(); 208 if(__err) return(__err); 209 *force_val = rd_signal_detect_frc_val(); 210 if(__err) return(__err); 211 212 return ERR_CODE_NONE; 213 } 214 215 216 err_code_t blackhawk_pll_mode_set( phymod_access_t *sa__, int pll_mode) 217 { 218 return ERR_CODE_NONE; 219 } 220 221 err_code_t blackhawk_pll_mode_get( phymod_access_t *sa__, uint32_t *pll_mode) 222 { 223 return ERR_CODE_NONE; 224 } 225 226 err_code_t blackhawk_afe_pll_reg_set( phymod_access_t *sa__, const phymod_afe_pll_t *afe_pll) 227 { 228 229 AMS_PLL_PLL_CTL2r_t reg; 230 231 AMS_PLL_PLL_CTL2r_CLR(reg); 232 233 if(afe_pll->afe_pll_change_default) { 234 AMS_PLL_PLL_CTL2r_AMS_PLL_IQPf_SET(reg, afe_pll->ams_pll_iqp); 235 PHYMOD_IF_ERR_RETURN(MODIFY_AMS_PLL_PLL_CTL2r(sa__, reg)); 236 } 237 238 return ERR_CODE_NONE; 239 } 240 241 err_code_t blackhawk_afe_pll_reg_get( phymod_access_t *sa__, phymod_afe_pll_t *afe_pll) 242 { 243 return ERR_CODE_NONE; 244 } 245 246 247 err_code_t blackhawk_osr_mode_set( phymod_access_t *sa__, int osr_mode) 248 { 249 err_code_t __err; 250 __err=ERR_CODE_NONE; 251 __err=wr_osr_mode_frc_val(osr_mode); 252 if(__err) return(__err); 253 __err=wr_osr_mode_frc(1); 254 if(__err) return(__err); 255 256 return ERR_CODE_NONE; 257 } 258 259 err_code_t blackhawk_osr_mode_get( phymod_access_t *sa__, int *osr_mode) 260 { 261 int osr_forced; 262 err_code_t __err; 263 __err=ERR_CODE_NONE; 264 *osr_mode = 0; 265 osr_forced = rd_osr_mode_frc(); 266 if(osr_forced) { 267 *osr_mode = rd_osr_mode_frc_val(); 268 if(__err) return(__err); 269 } 270 return ERR_CODE_NONE; 271 } 272 273 err_code_t blackhawk_tsc_dig_lpbk_get( phymod_access_t *sa__, uint32_t *lpbk) 274 { 275 err_code_t __err; 276 __err=ERR_CODE_NONE; 277 *lpbk = rd_dig_lpbk_en(); 278 if(__err) return(__err); 279 return ERR_CODE_NONE; 280 } 281 282 err_code_t blackhawk_tsc_rmt_lpbk_get( phymod_access_t *sa__, uint32_t *lpbk) 283 { 284 err_code_t __err; 285 __err=ERR_CODE_NONE; 286 *lpbk = rd_rmt_lpbk_en(); 287 if(__err) return(__err); 288 289 return ERR_CODE_NONE; 290 } 291 292 err_code_t blackhawk_core_soft_reset( phymod_access_t *sa__) 293 { 294 return ERR_CODE_NONE; 295 } 296 297 err_code_t blackhawk_core_soft_reset_release( phymod_access_t *sa__, uint32_t enable) 298 { 299 return ERR_CODE_NONE; 300 } 301 302 err_code_t blackhawk_core_soft_reset_read( phymod_access_t *sa__, uint32_t *enable) 303 { 304 return ERR_CODE_NONE; 305 } 306 307 err_code_t blackhawk_lane_soft_reset_read( phymod_access_t *sa__, uint32_t *enable) 308 { 309 return ERR_CODE_NONE; 310 } 311 312 err_code_t blackhawk_pmd_tx_disable_pin_dis_set( phymod_access_t *sa__, uint32_t enable) 313 { 314 err_code_t __err; 315 __err=ERR_CODE_NONE; 316 __err=wr_pmd_tx_disable_pkill(enable); 317 if(__err) return(__err); 318 319 return ERR_CODE_NONE; 320 } 321 322 err_code_t blackhawk_pmd_tx_disable_pin_dis_get( phymod_access_t *sa__, uint32_t *enable) 323 { 324 err_code_t __err; 325 __err=ERR_CODE_NONE; 326 *enable = rd_pmd_tx_disable_pkill(); 327 if(__err) return(__err); 328 329 return ERR_CODE_NONE; 330 } 331 332 /* set powerdown for tx or rx */ 333 /* tx_rx == 1 => disable (enable) power for Tx */ 334 /* tx_rx != 0 => disable (enable) power for Rx */ 335 /* pwrdn == 0 => enable power */ 336 /* pwrdn == 1 => disable power */ 337 err_code_t blackhawk_tsc_pwrdn_set( phymod_access_t *sa__, int tx_rx, int pwrdn) 338 { 339 return ERR_CODE_NONE; 340 } 341 342 err_code_t blackhawk_tsc_pwrdn_get( phymod_access_t *sa__, power_status_t *pwrdn) 343 { 344 345 return ERR_CODE_NONE; 346 } 347 348 err_code_t blackhawk_pcs_lane_swap_tx( phymod_access_t *sa__, uint32_t tx_lane_map) 349 { 350 351 return ERR_CODE_NONE; 352 } 353 354 err_code_t blackhawk_pmd_loopback_get( phymod_access_t *sa__, uint32_t *enable) 355 { 356 return ERR_CODE_NONE; 357 } 358 359 err_code_t blackhawk_pmd_cl72_enable_get( phymod_access_t *sa__, uint32_t *enable) 360 { 361 return ERR_CODE_NONE; 362 } 363 364 err_code_t blackhawk_pmd_cl72_receiver_status( phymod_access_t *sa__, uint32_t *status) 365 { 366 err_code_t __err; 367 __err = ERR_CODE_NONE; 368 *status = rd_linktrn_ieee_receiver_status(); if(__err) return(__err); 369 return ERR_CODE_NONE; 370 } 371 372 err_code_t blackhawk_pram_firmware_enable( phymod_access_t *sa__, int enable, int wait) /* release the pmd core soft reset */ 373 { 374 err_code_t __err; 375 uint8_t micro_orig, num_micros, micro_idx; 376 377 __err = ERR_CODE_NONE; 378 if (enable == 1) { 379 __err = wrc_micro_pramif_ahb_wraddr_msw(0); if(__err) return(__err); 380 __err = wrc_micro_pramif_ahb_wraddr_lsw(0); if(__err) return(__err); 381 382 __err = wrc_micro_pram_if_rstb(1); if(__err) return(__err); 383 __err = wrc_micro_pramif_en(1); if(__err) return(__err); 384 385 EFUN(wrc_micro_cr_crc_prtsel(0)); 386 EFUN(wrc_micro_cr_crc_init(1)); /* Initialize the HW CRC calculation */ 387 EFUN(wrc_micro_cr_crc_init(0)); 388 EFUN(wrc_micro_cr_crc_calc_en(1)); 389 390 if (wait) { 391 PHYMOD_USLEEP(500); 392 } 393 } else { 394 /* block writing to program RAM */ 395 EFUN(wrc_micro_ra_wrdatasize(0x2)); /* Select 32bit transfers as default */ 396 __err = wrc_micro_cr_ignore_micro_code_writes(1); if(__err) return(__err); 397 __err = wrc_micro_pramif_en(0); if(__err) return(__err); 398 399 EFUN(wrc_micro_cr_crc_calc_en(0)); 400 401 micro_orig = blackhawk_tsc_get_micro_idx(sa__); 402 num_micros = rdc_micro_num_uc_cores(); 403 if(__err) return(__err); 404 for (micro_idx = 0; micro_idx < num_micros; micro_idx++) { 405 __err = blackhawk_tsc_set_micro_idx(sa__, micro_idx); 406 if(__err) return(__err); 407 __err = wrc_micro_core_clk_en(1); 408 if(__err) return(__err); 409 } 410 __err = blackhawk_tsc_set_micro_idx(sa__, micro_orig); 411 if(__err) return(__err); 412 } 413 return ERR_CODE_NONE; 414 } 415 416 417 err_code_t blackhawk_pmd_lane_swap ( phymod_access_t *sa__, uint32_t lane_map) { 418 419 return ERR_CODE_NONE; 420 } 421 422 err_code_t blackhawk_pmd_lane_map_get ( phymod_access_t *sa__, uint32_t *tx_lane_map, uint32_t *rx_lane_map) { 423 424 err_code_t __err; 425 uint32_t tmp_tx_lane = 0; 426 uint32_t tmp_rx_lane = 0; 427 *tx_lane_map = 0; 428 *rx_lane_map = 0; 429 430 __err = ERR_CODE_NONE; 431 tmp_tx_lane = rdc_tx_lane_addr_0( ); 432 if(__err) return(__err); 433 *tx_lane_map |= tmp_tx_lane ; 434 tmp_tx_lane = rdc_tx_lane_addr_1( ); 435 if(__err) return(__err); 436 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 1); 437 tmp_tx_lane = rdc_tx_lane_addr_2( ); 438 if(__err) return(__err); 439 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 2); 440 tmp_tx_lane = rdc_tx_lane_addr_3( ); 441 if(__err) return(__err); 442 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 3); 443 tmp_tx_lane = rdc_tx_lane_addr_4( ); 444 if(__err) return(__err); 445 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 4); 446 tmp_tx_lane = rdc_tx_lane_addr_5( ); 447 if(__err) return(__err); 448 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 5); 449 tmp_tx_lane = rdc_tx_lane_addr_6( ); 450 if(__err) return(__err); 451 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 6); 452 tmp_tx_lane = rdc_tx_lane_addr_7( ); 453 if(__err) return(__err); 454 *tx_lane_map |= (tmp_tx_lane & 0xf) << (4 * 7); 455 456 tmp_rx_lane = rdc_rx_lane_addr_0( ); 457 if(__err) return(__err); 458 *rx_lane_map |= (tmp_rx_lane & 0xf); 459 tmp_rx_lane = rdc_rx_lane_addr_1( ); 460 if(__err) return(__err); 461 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 1); 462 tmp_rx_lane = rdc_rx_lane_addr_2( ); 463 if(__err) return(__err); 464 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 2); 465 tmp_rx_lane = rdc_rx_lane_addr_3( ); 466 if(__err) return(__err); 467 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 3); 468 tmp_rx_lane = rdc_rx_lane_addr_4( ); 469 if(__err) return(__err); 470 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 4); 471 tmp_rx_lane = rdc_rx_lane_addr_5( ); 472 if(__err) return(__err); 473 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 5); 474 tmp_rx_lane = rdc_rx_lane_addr_6( ); 475 if(__err) return(__err); 476 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 6); 477 tmp_rx_lane = rdc_rx_lane_addr_7( ); 478 if(__err) return(__err); 479 *rx_lane_map |= (tmp_rx_lane & 0xf) << (4 * 7); 480 481 __err = ERR_CODE_NONE; 482 483 return ERR_CODE_NONE; 484 } 485 486 err_code_t blackhawk_tx_pi_control_get( phymod_access_t *sa__, int16_t* value) 487 { 488 err_code_t __err; 489 uint8_t override_enable; 490 491 __err = ERR_CODE_NONE; 492 493 override_enable = rd_tx_pi_freq_override_en(); 494 if(__err) return(__err); 495 if (override_enable) { 496 *value = rd_tx_pi_freq_override_val(); 497 if(__err) return(__err); 498 } else { 499 *value = 0; 500 } 501 return ERR_CODE_NONE; 502 } 503 504 err_code_t blackhawk_tsc_identify( phymod_access_t *sa__, blackhawk_rev_id0_t *rev_id0, blackhawk_rev_id1_t *rev_id1) 505 { 506 err_code_t __err; 507 508 rev_id0->revid_rev_letter =0; 509 rev_id0->revid_rev_number =0; 510 rev_id0->revid_bonding =0; 511 rev_id0->revid_process =0; 512 rev_id0->revid_model =0; 513 514 rev_id1->revid_multiplicity =0; 515 rev_id1->revid_mdio =0; 516 rev_id1->revid_micro =0; 517 rev_id1->revid_cl72 =0; 518 rev_id1->revid_pir =0; 519 rev_id1->revid_llp =0; 520 rev_id1->revid_eee =0; 521 522 __err=ERR_CODE_NONE; 523 524 rev_id0->revid_rev_letter =rdc_revid_rev_letter(); if(__err) return(__err); 525 rev_id0->revid_rev_number =rdc_revid_rev_number(); if(__err) return(__err); 526 rev_id0->revid_bonding =rdc_revid_bonding(); if(__err) return(__err); 527 rev_id0->revid_process =rdc_revid_process(); if(__err) return(__err); 528 rev_id0->revid_model =rdc_revid_model(); if(__err) return(__err); 529 530 rev_id1->revid_multiplicity =rdc_revid_multiplicity(); if(__err) return(__err); 531 rev_id1->revid_mdio =rdc_revid_mdio(); if(__err) return(__err); 532 rev_id1->revid_micro =rdc_revid_micro(); if(__err) return(__err); 533 rev_id1->revid_cl72 =rdc_revid_cl72(); if(__err) return(__err); 534 rev_id1->revid_pir =rdc_revid_pir(); if(__err) return(__err); 535 rev_id1->revid_llp =rdc_revid_llp(); if(__err) return(__err); 536 rev_id1->revid_eee =rdc_revid_eee(); if(__err) return(__err); 537 538 return ERR_CODE_NONE; 539 } 540 541 err_code_t blackhawk_pmd_ln_h_rstb_pkill_override( phymod_access_t *sa__, uint16_t val) 542 { 543 err_code_t __err; 544 /* 545 * Work around per Magesh/Justin 546 * override input from PCS to allow uc_dsc_ready_for_cmd 547 * reg get written by UC 548 */ 549 __err = ERR_CODE_NONE; 550 __err = wr_pmd_ln_h_rstb_pkill(val); 551 if(__err) return(__err); 552 return ERR_CODE_NONE; 553 } 554 555 err_code_t blackhawk_lane_soft_reset( phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 556 { 557 int i, start_lane, num_lane; 558 uint32_t reset_enable; 559 phymod_access_t phy_access_copy; 560 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_t reg; 561 562 PHYMOD_MEMCPY(&phy_access_copy, sa__, sizeof(phy_access_copy)); 563 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_CLR(reg); 564 565 if (enable) { 566 reset_enable = 0; 567 } else { 568 reset_enable = 1; 569 } 570 571 PHYMOD_IF_ERR_RETURN 572 (phymod_util_lane_config_get(sa__, &start_lane, &num_lane)); 573 for (i = 0; i < num_lane; i++) { 574 phy_access_copy.lane_mask = 1 << (start_lane + i); 575 if (!PHYMOD_LANEPBMP_MEMBER(sa__->lane_mask, start_lane + i)) { 576 continue; 577 } 578 RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr_LN_DP_S_RSTBf_SET(reg, reset_enable); 579 PHYMOD_IF_ERR_RETURN(MODIFY_RXTXCOM_LN_CLK_RST_N_PWRDWN_CTLr(&phy_access_copy, reg)); 580 } 581 return ERR_CODE_NONE; 582 } 583 584 err_code_t blackhawk_lane_soft_reset_get( phymod_access_t *sa__, uint32_t *enable) /* release the pmd core soft reset */ 585 { 586 err_code_t __err; 587 uint32_t data; 588 589 __err = ERR_CODE_NONE; 590 data = rd_ln_dp_s_rstb(); 591 if(__err) return(__err); 592 if (data) { 593 *enable = 0; 594 } else { 595 *enable = 1; 596 } 597 return ERR_CODE_NONE; 598 } 599 600 601 err_code_t blackhawk_lane_hard_soft_reset_release( phymod_access_t *sa__, uint32_t enable) /* release the pmd core soft reset */ 602 { 603 err_code_t __err; 604 __err = ERR_CODE_NONE; 605 __err = wr_ln_s_rstb(enable); 606 if(__err) return(__err); 607 608 return ERR_CODE_NONE; 609 } 610 611 err_code_t blackhawk_clause72_control( phymod_access_t *sa__, uint32_t cl_72_en) /* CLAUSE_72_CONTROL */ 612 { 613 err_code_t __err; 614 615 __err = ERR_CODE_NONE; 616 617 if (cl_72_en) { 618 __err = wr_linktrn_ieee_training_enable(1); 619 if(__err) return(__err); 620 } else { 621 __err = wr_linktrn_ieee_training_enable(0); 622 if(__err) return(__err); 623 } 624 625 return ERR_CODE_NONE; 626 } 627 628 err_code_t blackhawk_clause72_control_get( phymod_access_t *sa__, uint32_t *cl_72_en) /* CLAUSE_72_CONTROL */ 629 { 630 err_code_t __err; 631 __err = ERR_CODE_NONE; 632 *cl_72_en = rd_linktrn_ieee_training_enable(); 633 if(__err) return(__err); 634 635 return ERR_CODE_NONE; 636 } 637 638 err_code_t blackhawk_channel_loss_set( phymod_access_t *sa__, uint32_t loss_in_db) 639 { 640 err_code_t __err; 641 __err = ERR_CODE_NONE; 642 __err = wrv_blackhawk_tsc_usr_ctrl_pam4_chn_loss(sa__, loss_in_db); 643 if(__err) return(__err); 644 return ERR_CODE_NONE; 645 } 646 647 err_code_t blackhawk_channel_loss_get( phymod_access_t *sa__, uint32_t *loss_in_db) 648 { 649 err_code_t __err; 650 __err = ERR_CODE_NONE; 651 *loss_in_db = rdv_blackhawk_tsc_usr_ctrl_pam4_chn_loss(sa__); 652 if(__err) return(__err); 653 return ERR_CODE_NONE; 654 } 655 656 657 658 err_code_t blackhawk_electrical_idle_set( phymod_access_t *sa__, uint8_t en) 659 { 660 AMS_TX_TX_CTL2r_t reg; 661 662 AMS_TX_TX_CTL2r_CLR(reg); 663 AMS_TX_TX_CTL2r_AMS_TX_ELEC_IDLE_AUXf_SET(reg, en); 664 PHYMOD_IF_ERR_RETURN(MODIFY_AMS_TX_TX_CTL2r(sa__, reg)); 665 666 return ERR_CODE_NONE; 667 } 668 669 err_code_t blackhawk_electrical_idle_get( phymod_access_t *sa__, uint8_t *en) 670 { 671 AMS_TX_TX_CTL2r_t reg; 672 673 READ_AMS_TX_TX_CTL2r(sa__, ®); 674 *en = AMS_TX_TX_CTL2r_AMS_TX_ELEC_IDLE_AUXf_GET(reg); 675 676 return ERR_CODE_NONE; 677 } 678 679 680 /***********************************************/ 681 /* Microcode Init into Program RAM Functions */ 682 /***********************************************/ 683 684 /* uCode Load through Register (MDIO) Interface [Return Val = Error_Code (0 = PASS)] */ 685 err_code_t blackhawk_tsc_ucode_init( phymod_access_t *sa__ ) 686 { 687 err_code_t __err; 688 __err = ERR_CODE_NONE; 689 690 __err = wrc_micro_master_clk_en(0x1); if(__err) return(__err); /* Enable clock to microcontroller subsystem */ 691 __err = wrc_micro_master_rstb(0x1); if(__err) return(__err); /* De-assert reset to microcontroller sybsystem */ 692 __err = wrc_micro_master_rstb(0x0); if(__err) return(__err); /* Assert reset to microcontroller sybsystem - Toggling reset*/ 693 __err = wrc_micro_master_rstb(0x1); if(__err) return(__err); /* De-assert reset to microcontroller sybsystem */ 694 __err = wrc_micro_cr_access_en(1); if(__err) return(__err); /* allow access to Code RAM */ 695 696 __err = wrc_micro_ra_init(0x1); if(__err) return(__err); /* Set initialization command to initialize code RAM */ 697 __err = blackhawk_tsc_INTERNAL_poll_micro_ra_initdone(sa__, 250); /* Poll status of data RAM initialization */ 698 if(__err) return(__err); 699 700 __err = wrc_micro_ra_init(0x2); if(__err) return(__err); /* Write command for data RAM initialization */ 701 __err = blackhawk_tsc_INTERNAL_poll_micro_ra_initdone(sa__, 250); /* Poll status of data RAM initialization */ 702 if(__err) return(__err); 703 704 __err = wrc_micro_ra_init(0x0); if(__err) return(__err); /* Clear initialization command */ 705 706 __err = wrc_micro_cr_crc_prtsel(0); if(__err) return(__err); 707 __err = wrc_micro_cr_prif_prtsel(0); if(__err) return(__err); 708 __err = wrc_micro_cr_crc_init(1); if(__err) return(__err); /* initialize the HW CRC calculation */ 709 __err = wrc_micro_cr_crc_init(0); if(__err) return(__err); 710 __err = wrc_micro_cr_ignore_micro_code_writes(0); if(__err) return(__err); /* allow writing to program RAM */ 711 712 713 return (ERR_CODE_NONE); 714 } 715 716 /** 717 @brief Init the PMD 718 @param pmd_touched If the PMD is already initialized 719 @returns The value ERR_CODE_NONE upon successful completion 720 @details Per core PMD resets (both datapath and entire core) 721 We only intend to use this function if the PMD has never been initialized. 722 */ 723 err_code_t blackhawk_pmd_reset_seq( phymod_access_t *sa__, int pmd_touched) 724 { 725 err_code_t __err; 726 __err = ERR_CODE_NONE; 727 728 if (pmd_touched == 0) { 729 __err = wrc_core_s_rstb(1); if(__err) return(__err); 730 } 731 return (ERR_CODE_NONE); 732 } 733 734 735 /** 736 @brief Enable the pll reset bit 737 @param enable Controls whether to reset PLL 738 @returns The value ERR_CODE_NONE upon successful completion 739 @details 740 Resets the PLL 741 */ 742 err_code_t blackhawk_pll_reset_enable_set ( phymod_access_t *sa__, int enable) 743 { 744 return (ERR_CODE_NONE); 745 } 746 747 /** 748 @brief Read PLL range 749 */ 750 err_code_t blackhawk_tsc_read_pll_range ( phymod_access_t *sa__, uint32_t *pll_range) 751 { 752 return (ERR_CODE_NONE); 753 } 754 755 756 /** 757 @brief Reag signal detect 758 */ 759 err_code_t blackhawk_tsc_signal_detect( phymod_access_t *sa__, uint32_t *signal_detect) 760 { 761 err_code_t __err; 762 __err=ERR_CODE_NONE; 763 *signal_detect = rd_signal_detect(); 764 if(__err) return(__err); 765 return (ERR_CODE_NONE); 766 } 767 768 769 err_code_t blackhawk_tsc_ladder_setting_to_mV( phymod_access_t *sa__, int8_t y, int16_t* level) 770 { 771 772 return(ERR_CODE_NONE); 773 } 774 775 776 err_code_t blackhawk_tsc_get_vco ( phymod_phy_inf_config_t* config, uint32_t *vco_rate, uint32_t *new_pll_div, int16_t *new_os_mode) 777 { 778 return(ERR_CODE_NONE); 779 } 780 781 /* Get Enable/Disable Shared TX pattern generator */ 782 err_code_t blackhawk_tsc_tx_shared_patt_gen_en_get( phymod_access_t *sa__, uint8_t *enable) { 783 err_code_t __err; 784 __err=ERR_CODE_NONE; 785 *enable = rd_patt_gen_en(); 786 if(__err) return(__err); 787 return ERR_CODE_NONE; 788 } 789 790 err_code_t blackhawk_tsc_config_shared_tx_pattern_idx_set( phymod_access_t *sa__, uint32_t *sa__ttern_len) 791 { 792 return ERR_CODE_NONE; 793 } 794 795 err_code_t blackhawk_tsc_config_shared_tx_pattern_idx_get( phymod_access_t *sa__, uint32_t *pattern_len, uint32_t *pattern) { 796 err_code_t __err; 797 uint8_t mode_sel; 798 uint32_t lsb = 0, msb = 0; 799 uint16_t temp_lsb, temp_msb; 800 int pattern_idx; 801 802 __err=ERR_CODE_NONE; 803 804 mode_sel = rd_patt_gen_start_pos(); if(__err) return(__err); 805 806 mode_sel = 12 - mode_sel; 807 808 if(mode_sel == 6) { 809 *pattern_len = 140; 810 } else if (mode_sel == 5) { 811 *pattern_len = 160; 812 } else if (mode_sel == 4) { 813 *pattern_len = 180; 814 } else if (mode_sel == 3) { 815 *pattern_len = 200; 816 } else if (mode_sel == 2) { 817 *pattern_len = 220; 818 } else if (mode_sel == 1) { 819 *pattern_len = 240; 820 } else { 821 *pattern_len = 0; 822 } 823 824 for (pattern_idx=0;pattern_idx<PATTERN_MAX_SIZE;pattern_idx++) { 825 switch (pattern_idx) { 826 case 0: 827 msb=rdc_patt_gen_seq_14(); if(__err) return(__err); 828 lsb=rdc_patt_gen_seq_13(); if(__err) return(__err); 829 break; 830 case 1: 831 msb=rdc_patt_gen_seq_12(); if(__err) return(__err); 832 lsb=rdc_patt_gen_seq_11(); if(__err) return(__err); 833 break; 834 case 2: 835 msb=rdc_patt_gen_seq_10(); if(__err) return(__err); 836 lsb=rdc_patt_gen_seq_9(); if(__err) return(__err); 837 break; 838 case 3: 839 msb=rdc_patt_gen_seq_8(); if(__err) return(__err); 840 lsb=rdc_patt_gen_seq_7(); if(__err) return(__err); 841 break; 842 case 4: 843 msb=rdc_patt_gen_seq_6(); if(__err) return(__err); 844 lsb=rdc_patt_gen_seq_5(); if(__err) return(__err); 845 break; 846 case 5: 847 msb=rdc_patt_gen_seq_4(); if(__err) return(__err); 848 lsb=rdc_patt_gen_seq_3(); if(__err) return(__err); 849 break; 850 case 6: 851 msb=rdc_patt_gen_seq_2(); if(__err) return(__err); 852 lsb=rdc_patt_gen_seq_1(); if(__err) return(__err); 853 break; 854 case 7: 855 msb=rdc_patt_gen_seq_0(); if(__err) return(__err); 856 lsb=0; 857 break; 858 /* Its a dead default and cause coverity defect 859 default: 860 PHYMOD_DEBUG_ERROR(("Wrong index value : Should be between 0 and 7\n")); 861 return ERR_CODE_DIAG; 862 break;*/ 863 } 864 phymod_swap_bit(lsb, &temp_lsb); 865 phymod_swap_bit(msb, &temp_msb); 866 867 pattern[pattern_idx] = temp_lsb << 16 | temp_msb ; 868 } 869 870 return ERR_CODE_NONE; 871 } 872 873 /**********************************/ 874 /* Serdes TX disable/RX Restart */ 875 /**********************************/ 876 877 err_code_t blackhawk_tsc_tx_disable_get ( phymod_access_t *sa__, uint8_t *enable) 878 { 879 err_code_t __err; 880 881 __err=ERR_CODE_NONE; 882 *enable = (uint8_t) rd_sdk_tx_disable(); 883 if(__err) return(__err); 884 return ERR_CODE_NONE; 885 } 886 887 err_code_t blackhawk_refclk_set( phymod_access_t *sa__, phymod_ref_clk_t ref_clock) 888 { 889 DIG_TOP_USER_CTL0r_t dig_top_user_ctrl_reg; 890 DIG_TOP_USER_CTL0r_CLR(dig_top_user_ctrl_reg); 891 892 switch (ref_clock) { 893 case phymodRefClk156Mhz: 894 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_ctrl_reg, 0x271); 895 break; 896 case phymodRefClk125Mhz: 897 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_ctrl_reg, 0x1f4); 898 break; 899 case phymodRefClk312Mhz: 900 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_ctrl_reg, 0x271); 901 break; 902 default: 903 DIG_TOP_USER_CTL0r_HEARTBEAT_COUNT_1USf_SET(dig_top_user_ctrl_reg, 0x271); 904 break; 905 } 906 PHYMOD_IF_ERR_RETURN(MODIFY_DIG_TOP_USER_CTL0r(sa__, dig_top_user_ctrl_reg)); 907 908 return ERR_CODE_NONE; 909 } 910 911 err_code_t blackhawk_tsc_tx_nrz_mode_get(phymod_access_t *sa__, uint16_t *tx_nrz_mode) 912 { 913 TXFIR_TAP_CTL0r_t reg; 914 915 READ_TXFIR_TAP_CTL0r(sa__, ®); 916 *tx_nrz_mode = TXFIR_TAP_CTL0r_TXFIR_NRZ_TAP_RANGE_SELf_GET(reg); 917 return ERR_CODE_NONE; 918 } 919 920 err_code_t blackhawk_tsc_signalling_mode_status_get( phymod_access_t *sa__, phymod_phy_signalling_method_t *mode) 921 { 922 RXTXCOM_OSR_MODE_STS_MC_MASKr_t reg; 923 uint16_t temp_data = 0; 924 925 READ_RXTXCOM_OSR_MODE_STS_MC_MASKr(sa__, ®); 926 temp_data = RXTXCOM_OSR_MODE_STS_MC_MASKr_PAM4_MODEf_GET(reg); 927 if (temp_data) { 928 *mode = phymodSignallingMethodPAM4; 929 } else { 930 *mode = phymodSignallingMethodNRZ; 931 } 932 return ERR_CODE_NONE; 933 } 934 935 936 err_code_t blackhawk_tsc_tx_tap_mode_get( phymod_access_t *sa__, uint8_t *mode) 937 { 938 err_code_t __err; 939 940 __err=ERR_CODE_NONE; 941 *mode = (uint8_t) rd_txfir_tap_en(); 942 if(__err) return(__err); 943 return ERR_CODE_NONE; 944 } 945 946 947 err_code_t blackhawk_tsc_pam4_tx_pattern_enable_get( phymod_access_t *sa__, phymod_PAM4_tx_pattern_t pattern_type, uint32_t* enable) 948 { 949 err_code_t __err; 950 951 __err=ERR_CODE_NONE; 952 *enable = (uint8_t) rd_patt_gen_en(); 953 if(__err) return(__err); 954 if (*enable) { 955 switch (pattern_type) { 956 case phymod_PAM4TxPattern_JP03B: 957 *enable = rd_pam4_tx_jp03b_patt_en(); 958 if(__err) return(__err); 959 break; 960 case phymod_PAM4TxPattern_Linear: 961 *enable = rd_pam4_tx_linearity_patt_en(); 962 if(__err) return(__err); 963 break; 964 default: 965 PHYMOD_RETURN_WITH_ERR(PHYMOD_E_PARAM, (_PHYMOD_MSG("unsupported PAM4 tx pattern %u"), pattern_type)); 966 } 967 } 968 return ERR_CODE_NONE; 969 } 970 971 err_code_t blackhawk_tsc_tx_pam4_precoder_enable_set(phymod_access_t *sa__, int enable) 972 { 973 err_code_t __err; 974 975 __err = ERR_CODE_NONE; 976 977 __err = wr_pam4_precoder_en(enable); 978 if(__err) return(__err); 979 return ERR_CODE_NONE; 980 } 981 982 err_code_t blackhawk_tsc_tx_pam4_precoder_enable_get(phymod_access_t *sa__, int *enable) 983 { 984 err_code_t __err; 985 __err = ERR_CODE_NONE; 986 987 *enable = rd_pam4_precoder_en(); 988 if(__err) return(__err); 989 return ERR_CODE_NONE; 990 } 991 992 err_code_t blackhawk_micro_clk_source_select( phymod_access_t *sa__, uint32_t pll_index) 993 { 994 err_code_t __err; 995 uint16_t rdval; 996 997 rdval=rdcv_misc_ctrl_byte(); 998 /* first zero out bit2 which is the micro clk source bit */ 999 rdval &= ~0x4; 1000 rdval |= pll_index << 2; 1001 wrcv_misc_ctrl_byte(rdval); 1002 1003 return ERR_CODE_NONE; 1004 } 1005 1006 /* Get the PLL powerdown status */ 1007 err_code_t blackhawk_tsc_pll_pwrdn_get(phymod_access_t *sa__, uint32_t *is_pwrdn) 1008 { 1009 err_code_t __err; 1010 1011 __err = ERR_CODE_NONE; 1012 /* Either afs_s_pll_pwrdn or ams_pll_pwrdn is set, PLL is in power down state */ 1013 *is_pwrdn = rdc_afe_s_pll_pwrdn(); 1014 *is_pwrdn |= rdc_ams_pll_pwrdn(); 1015 if (__err) return (__err); 1016 1017 return ERR_CODE_NONE; 1018 } 1019 1020 /* Get the PLL lock status */ 1021 err_code_t blackhawk_tsc_pll_lock_get(phymod_access_t *sa__, uint32_t *pll_lock) 1022 { 1023 err_code_t __err; 1024 1025 __err = ERR_CODE_NONE; 1026 /* read PLL lock status */ 1027 *pll_lock = rdc_pll_lock(); 1028 *pll_lock = rdc_pll_lock(); 1029 if (__err) return (__err); 1030 1031 return ERR_CODE_NONE; 1032 } 1033 1034 err_code_t blackhawk_speed_config_get(uint32_t speed, int ref_clk_is_156p25, uint32_t *pll_multiplier, uint32_t *is_pam4, uint32_t *osr_mode) 1035 { 1036 if (ref_clk_is_156p25) { 1037 switch (speed) { 1038 case 10312: 1039 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_132; 1040 *is_pam4 = 0; 1041 *osr_mode = 1; 1042 break; 1043 case 11500: 1044 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_147P2; 1045 *is_pam4 = 0; 1046 *osr_mode = 1; 1047 break; 1048 case 12500: 1049 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_160; 1050 *is_pam4 = 0; 1051 *osr_mode = 1; 1052 break; 1053 case 20625: 1054 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_132; 1055 *is_pam4 = 0; 1056 *osr_mode = 0; 1057 break; 1058 case 23000: 1059 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_147P2; 1060 *is_pam4 = 0; 1061 *osr_mode = 0; 1062 break; 1063 case 25000: 1064 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_160; 1065 *is_pam4 = 0; 1066 *osr_mode = 0; 1067 break; 1068 case 25780: 1069 case 25781: 1070 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_165; 1071 *osr_mode = 0; 1072 *is_pam4 = 0; 1073 break; 1074 case 27343: 1075 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_175; 1076 *osr_mode = 0; 1077 *is_pam4 = 0; 1078 break; 1079 case 28125: 1080 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_180; 1081 *is_pam4 = 0; 1082 *osr_mode = 0; 1083 break; 1084 case 41250: 1085 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_132; 1086 *is_pam4 = 1; 1087 *osr_mode = 0; 1088 break; 1089 case 41875: 1090 return PHYMOD_E_CONFIG; 1091 break; 1092 case 45000: 1093 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_144; 1094 *is_pam4 = 1; 1095 *osr_mode = 0; 1096 break; 1097 case 46000: 1098 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_147P2; 1099 *is_pam4 = 1; 1100 *osr_mode = 0; 1101 break; 1102 case 50000: 1103 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_160; 1104 *is_pam4 = 1; 1105 *osr_mode = 0; 1106 break; 1107 case 51560: 1108 case 51562: 1109 case 51561: 1110 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_165; 1111 *is_pam4 = 1; 1112 *osr_mode = 0; 1113 break; 1114 case 53125: 1115 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_170; 1116 *is_pam4 = 1; 1117 *osr_mode = 0; 1118 break; 1119 case 56250: 1120 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_180; 1121 *is_pam4 = 1; 1122 *osr_mode = 0; 1123 break; 1124 default: 1125 return PHYMOD_E_CONFIG; 1126 break; 1127 } 1128 } else { 1129 switch (speed) { 1130 case 10312: 1131 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_66; 1132 *is_pam4 = 0; 1133 *osr_mode = 1; 1134 break; 1135 case 11500: 1136 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_73P6; 1137 *is_pam4 = 0; 1138 *osr_mode = 1; 1139 break; 1140 case 12500: 1141 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_80; 1142 *is_pam4 = 0; 1143 *osr_mode = 1; 1144 break; 1145 case 20625: 1146 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_66; 1147 *is_pam4 = 0; 1148 *osr_mode = 0; 1149 break; 1150 case 23000: 1151 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_73P6; 1152 *is_pam4 = 0; 1153 *osr_mode = 0; 1154 break; 1155 case 25000: 1156 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_80; 1157 *is_pam4 = 0; 1158 *osr_mode = 0; 1159 break; 1160 case 25780: 1161 case 25781: 1162 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_82P5; 1163 *osr_mode = 0; 1164 *is_pam4 = 0; 1165 break; 1166 case 27343: 1167 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_87P5; 1168 *osr_mode = 0; 1169 *is_pam4 = 0; 1170 break; 1171 case 28125: 1172 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_90; 1173 *is_pam4 = 0; 1174 *osr_mode = 0; 1175 break; 1176 case 41250: 1177 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_66; 1178 *is_pam4 = 1; 1179 *osr_mode = 0; 1180 break; 1181 case 41875: 1182 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_67; 1183 *is_pam4 = 1; 1184 *osr_mode = 0; 1185 break; 1186 case 45000: 1187 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_72; 1188 *is_pam4 = 1; 1189 *osr_mode = 0; 1190 break; 1191 case 46000: 1192 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_73P6; 1193 *is_pam4 = 1; 1194 *osr_mode = 0; 1195 break; 1196 case 50000: 1197 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_80; 1198 *is_pam4 = 1; 1199 *osr_mode = 0; 1200 break; 1201 case 51560: 1202 case 51562: 1203 case 51561: 1204 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_82P5; 1205 *is_pam4 = 1; 1206 *osr_mode = 0; 1207 break; 1208 case 53125: 1209 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_85; 1210 *is_pam4 = 1; 1211 *osr_mode = 0; 1212 break; 1213 case 56250: 1214 *pll_multiplier = BLACKHAWK_TSC_PLL_DIV_90; 1215 *is_pam4 = 1; 1216 *osr_mode = 0; 1217 break; 1218 default: 1219 return PHYMOD_E_CONFIG; 1220 break; 1221 } 1222 } 1223 1224 return PHYMOD_E_NONE; 1225 } 1226 1227 err_code_t blackhawk_tsc_lane_cfg_fwapi_data1_set( phymod_access_t *sa__, uint32_t val) 1228 { 1229 err_code_t __err; 1230 1231 __err = ERR_CODE_NONE; 1232 __err = wr_lane_cfg_fwapi_data1(val); 1233 if(__err) return(__err); 1234 1235 return ERR_CODE_NONE; 1236 } 1237 1238 err_code_t blackhawk_tsc_enable_pass_through_configuration(phymod_access_t *sa__, int enable) 1239 { 1240 err_code_t __err; 1241 uint16_t write_val; 1242 __err = ERR_CODE_NONE; 1243 1244 write_val = enable? 0x9 : 0x0; 1245 __err = wrv_blackhawk_tsc_usr_ctrl_unused_word(sa__, write_val); 1246 if(__err) return(__err); 1247 1248 return ERR_CODE_NONE; 1249 } 1250 1251 /* Locks TX_PI to Loop timing, external CDR */ 1252 err_code_t blackhawk_tsc_ext_loop_timing(phymod_access_t *sa__, uint8_t enable) 1253 { 1254 uint8_t is_enable = enable ? 0x1 : 0x0; 1255 1256 EFUN(wr_tx_pi_repeater_mode_en(is_enable)); 1257 EFUN(wr_tx_pi_jitter_filter_en(is_enable)); /* Jitter filter enable to lock freq */ 1258 EFUN(wr_tx_pi_en(is_enable)); 1259 EFUN(wr_tx_pi_loop_timing_src_sel(is_enable)); /* RX phase_sum_val_logic enable */ 1260 1261 return (ERR_CODE_NONE); 1262 } 1263 1264 err_code_t blackhawk_tsc_error_analyzer_status_clear(phymod_access_t *sa__) 1265 { 1266 err_code_t __err; 1267 1268 __err = ERR_CODE_NONE; 1269 __err = wr_tlb_err_clear_error_analyzer_status(1); 1270 if(__err) return(__err); 1271 1272 return ERR_CODE_NONE; 1273 } 1274 1275 err_code_t blackhawk_tsc_rx_ppm(phymod_access_t *sa__, int16_t *rx_ppm) 1276 { 1277 err_code_t __err; 1278 __err=ERR_CODE_NONE; 1279 *rx_ppm = rd_cdr_integ_reg() / 84; 1280 if(__err) return(__err); 1281 return (ERR_CODE_NONE); 1282 } 1283 1284 /* Set/Get clk4sync_en, clk4sync_div */ 1285 err_code_t blackhawk_tsc_clk4sync_enable_set(phymod_access_t *sa__, uint32_t en, uint32_t div) 1286 { 1287 err_code_t __err; 1288 1289 __err = ERR_CODE_NONE; 1290 1291 __err = wrc_ams_pll_clk4sync_en(en); 1292 if (__err) return (__err); 1293 __err = wrc_ams_pll_clk4sync_div(div); 1294 if (__err) return (__err); 1295 1296 return ERR_CODE_NONE; 1297 } 1298 1299 err_code_t blackhawk_tsc_clk4sync_enable_get(phymod_access_t *sa__, uint32_t *en, uint32_t *div) 1300 { 1301 err_code_t __err; 1302 1303 __err = ERR_CODE_NONE; 1304 1305 *en = rdc_ams_pll_clk4sync_en(); 1306 if (__err) return (__err); 1307 *div = rdc_ams_pll_clk4sync_div(); 1308 if (__err) return (__err); 1309 1310 return ERR_CODE_NONE; 1311 } 1312 1313 err_code_t blackhawk_ams_version_get(phymod_access_t *sa__, uint32_t *ams_version) 1314 { 1315 err_code_t __err; 1316 1317 __err = ERR_CODE_NONE; 1318 *ams_version = rd_ams_tx_version_id(); 1319 if (__err) return (__err); 1320 1321 return ERR_CODE_NONE; 1322 } 1323