merlin16_pcieg3_pwr_mgt.c (5315B)
1 /************************************************************************************** 2 ************************************************************************************** 3 * File Name : merlin16_pcieg3_pwr_mgt.c * 4 * Created On : 04 Nov 2015 * 5 * Created By : Brent Roberts * 6 * Description : APIs for Serdes IPs * 7 * Revision : * 8 * * 9 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 10 * 11 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 12 * No portions of this material may be reproduced in any form without * 13 * the written permission of: * 14 * Broadcom Corporation * 15 * 5300 California Avenue * 16 * Irvine, CA 92617 * 17 * * 18 * All information contained in this document is Broadcom Corporation * 19 * company private proprietary, and trade secret. * 20 */ 21 22 /** @file merlin16_pcieg3_pwr_mgt.c 23 * Implementation of API power management functions 24 */ 25 26 #include "merlin16_pcieg3_pwr_mgt.h" 27 #include "merlin16_pcieg3_common.h" 28 #include "merlin16_pcieg3_functions.h" 29 #include "merlin16_pcieg3_internal.h" 30 #include "merlin16_pcieg3_internal_error.h" 31 #include "merlin16_pcieg3_select_defns.h" 32 #include "merlin16_pcieg3_config.h" 33 34 /***************************/ 35 /* Configure Serdes IDDQ */ 36 /***************************/ 37 38 err_code_t merlin16_pcieg3_core_config_for_iddq(srds_access_t *sa__) { 39 40 EFUN(wrc_ams_pll_pwrdn(0x1)); 41 return (ERR_CODE_NONE); 42 } 43 44 45 err_code_t merlin16_pcieg3_lane_config_for_iddq(srds_access_t *sa__) { 46 47 /* Use frc/frc_val to force all RX and TX clk_vld signals to 0 */ 48 EFUN(wr_pmd_rx_clk_vld_frc_val(0x0)); 49 EFUN(wr_pmd_rx_clk_vld_frc(0x1)); 50 EFUN(wr_pmd_tx_clk_vld_frc_val(0x0)); 51 EFUN(wr_pmd_tx_clk_vld_frc(0x1)); 52 53 /* Use frc/frc_val to force all pmd_rx_lock signals to 0 */ 54 EFUN(wr_rx_dsc_lock_frc_val(0x0)); 55 EFUN(wr_rx_dsc_lock_frc(0x1)); 56 57 /* Switch all the lane clocks to comclk by writing to RX/TX comclk_sel registers */ 58 EFUN(wr_ln_rx_s_comclk_sel(0x1)); 59 EFUN(wr_ln_tx_s_comclk_sel(0x1)); 60 61 /* Assert all the AFE pwrdn/reset pins using frc/frc_val to make sure AFE is in lowest possible power mode */ 62 EFUN(wr_afe_tx_pwrdn_frc_val(0x1)); 63 EFUN(wr_afe_tx_pwrdn_frc(0x1)); 64 EFUN(wr_afe_rx_pwrdn_frc_val(0x1)); 65 EFUN(wr_afe_rx_pwrdn_frc(0x1)); 66 EFUN(wr_afe_tx_reset_frc_val(0x1)); 67 EFUN(wr_afe_tx_reset_frc(0x1)); 68 EFUN(wr_afe_rx_reset_frc_val(0x1)); 69 EFUN(wr_afe_rx_reset_frc(0x1)); 70 71 /* Set pmd_iddq pin to enable IDDQ */ 72 return (ERR_CODE_NONE); 73 } 74 75 /****************************************************/ 76 /* Serdes Powerdown, ClockGate and Deep_Powerdown */ 77 /****************************************************/ 78 79 err_code_t merlin16_pcieg3_core_pwrdn(srds_access_t *sa__, enum srds_core_pwrdn_mode_enum mode) { 80 switch(mode) { 81 case PWR_ON: 82 EFUN(merlin16_pcieg3_INTERNAL_core_clkgate(sa__, 0)); 83 EFUN(wrc_afe_s_pll_pwrdn(0x0)); 84 EFUN(merlin16_pcieg3_core_dp_reset(sa__, 0x0)); 85 break; 86 case PWRDN: 87 EFUN(merlin16_pcieg3_core_dp_reset(sa__, 1)); 88 EFUN(USR_DELAY_NS(500)); /* wait >50 comclk cycles */ 89 EFUN(wrc_afe_s_pll_pwrdn(0x1)); 90 break; 91 case PWRDN_DEEP: 92 EFUN(merlin16_pcieg3_core_dp_reset(sa__, 1)); 93 EFUN(USR_DELAY_NS(500)); /* wait >50 comclk cycles */ 94 EFUN(wrc_afe_s_pll_pwrdn(0x1)); 95 EFUN(merlin16_pcieg3_INTERNAL_core_clkgate(sa__, 1)); 96 break; 97 default: 98 EFUN(_error(ERR_CODE_BAD_PTR_OR_INVALID_INPUT)); 99 break; 100 } 101 return ERR_CODE_NONE; 102 } 103 104 err_code_t merlin16_pcieg3_lane_pwrdn(srds_access_t *sa__, enum srds_core_pwrdn_mode_enum mode) { 105 106 switch(mode) { 107 case PWR_ON: 108 EFUN(wr_ln_tx_s_pwrdn(0x0)); 109 EFUN(wr_ln_rx_s_pwrdn(0x0)); 110 EFUN(merlin16_pcieg3_INTERNAL_lane_clkgate(sa__, 0)); 111 break; 112 case PWRDN: 113 /* do the RX first, since that is what is most users care about */ 114 EFUN(wr_ln_rx_s_pwrdn(0x1)); 115 EFUN(wr_ln_tx_s_pwrdn(0x1)); 116 break; 117 case PWRDN_DEEP: 118 /* do the RX first, since that is what is most users care about */ 119 EFUN(wr_ln_rx_s_pwrdn(0x1)); 120 EFUN(wr_ln_tx_s_pwrdn(0x1)); 121 EFUN(merlin16_pcieg3_INTERNAL_lane_clkgate(sa__, 1)); 122 EFUN(wr_ln_dp_s_rstb(0x0)); 123 break; 124 case PWRDN_TX: 125 EFUN(wr_ln_tx_s_pwrdn(0x1)); 126 break; 127 case PWRDN_RX: 128 EFUN(wr_ln_rx_s_pwrdn(0x1)); 129 break; 130 default : 131 return(_error(ERR_CODE_BAD_PTR_OR_INVALID_INPUT)); 132 } 133 return (ERR_CODE_NONE); 134 }