merlin16_pcieg3_internal.h (38048B)
1 /********************************************************************************** 2 ********************************************************************************** 3 * * 4 * Revision : * 5 * * 6 * Description : Internal API functions * 7 * * 8 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 9 * 10 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 11 * No portions of this material may be reproduced in any form without * 12 * the written permission of: * 13 * Broadcom Corporation * 14 * 5300 California Avenue * 15 * Irvine, CA 92617 * 16 * * 17 * All information contained in this document is Broadcom Corporation * 18 * company private proprietary, and trade secret. * 19 */ 20 21 /** @file merlin16_pcieg3_internal.h 22 * Internal API functions 23 */ 24 25 #ifndef MERLIN16_PCIEG3_API_INTERNAL_H 26 #define MERLIN16_PCIEG3_API_INTERNAL_H 27 28 #include "merlin16_pcieg3_ipconfig.h" 29 #include "merlin16_pcieg3_select_defns.h" 30 #include "common/srds_api_err_code.h" 31 #include "common/srds_api_uc_common.h" 32 #include "common/srds_api_types.h" 33 #include "merlin16_pcieg3_enum.h" 34 #include "merlin16_pcieg3_types.h" 35 #include "merlin16_pcieg3_usr_includes.h" 36 37 38 /*------------------------------*/ 39 /** Serdes OSR Mode Structure */ 40 /*------------------------------*/ 41 typedef struct { 42 /** TX OSR Mode */ 43 uint8_t tx; 44 /** RX OSR Mode */ 45 uint8_t rx; 46 /** OSR Mode for TX and RX (used when both TX and RX should have same OSR Mode) */ 47 uint8_t tx_rx; 48 }merlin16_pcieg3_osr_mode_st; 49 50 /*------------------------------*/ 51 /** Serdes Lane State Structure */ 52 /*------------------------------*/ 53 typedef struct { 54 /** uC lane configuration */ 55 uint16_t ucv_config; 56 /** uC lane status */ 57 uint8_t ucv_status; 58 /** Frequency offset of local reference clock with respect to RX data in ppm */ 59 int16_t rx_ppm; 60 /** Vertical threshold voltage of p1 slicer (mV) */ 61 int16_t p1_lvl; 62 /** Vertical threshold voltage of m1 slicer (mV) [Used to read out 'channel loss hint' in PAM4 mode] */ 63 int16_t m1_lvl; 64 /** Link time in milliseconds */ 65 uint16_t link_time; 66 /** OSR Mode */ 67 merlin16_pcieg3_osr_mode_st osr_mode; 68 /** Signal Detect */ 69 uint8_t sig_det; 70 /** Signal Detect Change */ 71 uint8_t sig_det_chg; 72 /** PMD RX Lock */ 73 uint8_t rx_lock; 74 /** PMD RX Lock Change */ 75 uint8_t rx_lock_chg; 76 /** Delay of zero crossing slicer, m1, wrt to data in PI codes */ 77 int8_t clk90; 78 /** Delay of diagnostic/lms slicer, p1, wrt to data in PI codes */ 79 int8_t clkp1; 80 /** Peaking Filter Main Settings */ 81 int8_t pf_main; 82 /** Peaking Filter Hiz mode enable */ 83 int8_t pf_hiz; 84 /** Low Frequency Peaking filter control */ 85 int8_t pf2_ctrl; 86 /** Variable Gain Amplifier settings */ 87 int8_t vga; 88 /** DC offset DAC control value */ 89 int8_t dc_offset; 90 /** P1 eyediag status */ 91 int8_t p1_lvl_ctrl; 92 /** DFE tap 1 value */ 93 int8_t dfe1; 94 /** DFE tap 2 value */ 95 int8_t dfe2; 96 /** DFE tap 3 value */ 97 int8_t dfe3; 98 /** DFE tap 4 value */ 99 int8_t dfe4; 100 /** DFE tap 5 value */ 101 int8_t dfe5; 102 /** DFE tap 6 value */ 103 int8_t dfe6; 104 /** DFE tap 1 Duty Cycle Distortion */ 105 int8_t dfe1_dcd; 106 /** DFE tap 2 Duty Cycle Distortion */ 107 int8_t dfe2_dcd; 108 /** Slicer calibration control codes (p1 even) */ 109 int8_t pe; 110 /** Slicer calibration control codes (data even) */ 111 int8_t ze; 112 /** Slicer calibration control codes (m1 even) */ 113 int8_t me; 114 /** Slicer calibration control codes (p1 odd) */ 115 int8_t po; 116 /** Slicer calibration control codes (data odd) */ 117 int8_t zo; 118 /** Slicer calibration control codes (m1 odd) */ 119 int8_t mo; 120 /** Frequency offset of local reference clock with respect to TX data in ppm */ 121 int16_t tx_ppm; 122 /** TX equalization FIR pre tap weight */ 123 int8_t txfir_pre; 124 /** TX equalization FIR main tap weight */ 125 int8_t txfir_main; 126 /** TX equalization FIR post1 tap weight */ 127 int8_t txfir_post1; 128 /** TX equalization FIR post2 tap weight */ 129 int8_t txfir_post2; 130 /** TX equalization FIR post3 tap weight */ 131 int8_t txfir_post3; 132 /** TX equalization FIR rpara tap weight */ 133 int8_t txfir_rpara; 134 /** Horizontal left eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 135 uint16_t heye_left; 136 /** Horizontal right eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 137 uint16_t heye_right; 138 /** Vertical upper eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 139 uint16_t veye_upper; 140 /** Vertical lower eye margin @ 1e-5 as seen by internal diagnostic slicer in mUI and mV */ 141 uint16_t veye_lower; 142 /** Baud Rate Phase Detector enable */ 143 uint8_t br_pd_en; 144 /** lane_reset_state **/ 145 uint8_t reset_state; 146 /** uC stopped state **/ 147 uint8_t stop_state; 148 /** Sigdet offset correction - positive **/ 149 uint8_t soc_pos; 150 /** Sigdet offset correction - negative **/ 151 uint8_t soc_neg; 152 /** Rate select */ 153 uint8_t rate_select; 154 /* First read of dsc_one_hot_0 */ 155 uint16_t dsc_one_hot_0_0; 156 /* Second read of dsc_one_hot_0 */ 157 uint16_t dsc_one_hot_0_1; 158 } merlin16_pcieg3_lane_state_st; 159 160 /*------------------------------*/ 161 /** Serdes Core State Structure */ 162 /*------------------------------*/ 163 typedef struct { 164 /** Core DP Reset State */ 165 uint8_t core_reset; 166 /** PLL Powerdown enable */ 167 uint8_t pll_pwrdn; 168 /** Micro active enable */ 169 uint8_t uc_active; 170 /** Comclk Frequency in Mhz */ 171 uint16_t comclk_mhz; 172 /** uCode Major Version number */ 173 uint16_t ucode_version; 174 /** uCode Minor Version number */ 175 uint8_t ucode_minor_version; 176 /** AFE Hardware version */ 177 uint8_t afe_hardware_version; 178 /** uC Die Temperature Index */ 179 uint8_t temp_idx; 180 /** Average Die Temperature (13-bit format) */ 181 int16_t avg_tmon; 182 /** Analog Resistor Calibration value */ 183 uint8_t rescal; 184 /** VCO Rate in MHz */ 185 uint16_t vco_rate_mhz; 186 /** Analog VCO Range */ 187 uint8_t analog_vco_range; 188 /** PLL Divider value. (Same encoding as enum #merlin16_pcieg3_pll_div_enum.) */ 189 uint32_t pll_div; 190 /** PLL Lock */ 191 uint8_t pll_lock; 192 uint8_t pll_lock_chg; 193 /** Live die temperature in Celsius */ 194 int16_t die_temp; 195 /** Core Status Variable */ 196 uint8_t core_status; 197 /** Rate select */ 198 uint8_t rate_select; 199 } merlin16_pcieg3_core_state_st; 200 201 /**************************************************************************** 202 * @name Direct RAM Access 203 * 204 * Cores/chips with a built-in microcontroller afford direct, memory-mapped 205 * access to the firmware control/status RAM variables. 206 */ 207 /**@{*/ 208 209 210 /** Base of core variable block, MERLIN16 variant. */ 211 #define CORE_VAR_RAM_BASE (0x400) 212 /** Base of lane variable block, MERLIN16 variant. */ 213 #define LANE_VAR_RAM_BASE (0x500) 214 /** Size of lane variable block, MERLIN16 variant. */ 215 #define LANE_VAR_RAM_SIZE (0x100) 216 217 218 /**@}*/ 219 220 typedef struct { 221 uint32_t signature; 222 uint32_t diag_mem_ram_base; 223 uint32_t diag_mem_ram_size; 224 uint32_t core_var_ram_base; /* Must be the same as CORE_VAR_RAM_BASE */ 225 uint32_t core_var_ram_size; 226 uint32_t lane_var_ram_base; /* Must be the same as LANE_VAR_RAM_BASE */ 227 uint32_t lane_var_ram_size; /* Must be the same as LANE_VAR_RAM_SIZE */ 228 uint32_t trace_mem_ram_base; 229 uint32_t trace_mem_ram_size; 230 uint32_t micro_var_ram_base; 231 uint8_t lane_count; 232 uint8_t trace_memory_descending_writes; 233 uint8_t micro_count; 234 uint8_t micro_var_ram_size; 235 uint16_t grp_ram_size; 236 } merlin16_pcieg3_info_t; 237 238 #define SRDS_INFO_SIGNATURE (0x50c1ab1e) 239 240 241 /** Retrieve the num_bits_per_ms useful for BER calculations 242 * There is some Error in the calculation because only VCO rate in Mhz is stored. 243 * @param sa__ is an opaque state vector passed through to device access functions. 244 * @param *num_bits_per_ms is pointer to uint64_t which is used to store the num_bits_per_ms 245 * @return Serdes Info pointer 246 */ 247 err_code_t merlin16_pcieg3_INTERNAL_get_num_bits_per_ms(srds_access_t *sa__, uint32_t *num_bits_per_ms); 248 249 /** Check PRBS status and print BER 250 * @param sa__ is an opaque state vector passed through to device access functions. 251 * @param time_ms is the amount of time to delay for BER calculation 252 * @return Serdes Info pointer 253 */ 254 err_code_t merlin16_pcieg3_INTERNAL_display_BER(srds_access_t *sa__, uint16_t time_ms); 255 256 /** Check PRBS status and print BER 257 * @param sa__ is an opaque state vector passed through to device access functions. 258 * @param time_ms is the amount of time to delay for BER calculation 259 * @param string is a pointer to char array of length >=10 in which to place string. 260 * @return Serdes Info pointer 261 */ 262 err_code_t merlin16_pcieg3_INTERNAL_get_BER_string(srds_access_t *sa__, uint16_t time_ms, char *string); 263 264 /** Check PRBS status and provide number of errors and number of bits for BER calculation 265 * @param sa__ is an opaque state vector passed through to device access functions. 266 * @param time_ms is the amount of time to delay for BER calculation 267 * @param ber_data is a struct that contains number of errors and number of bits as elements 268 * @return Error code, if generated (returns ERR_CODE_NONE if no errors) 269 */ 270 err_code_t merlin16_pcieg3_INTERNAL_get_BER_data(srds_access_t *sa__, uint16_t time_ms, struct ber_data_st *ber_data); 271 272 /** Get Serdes Info pointer 273 * @return Serdes Info pointer 274 */ 275 merlin16_pcieg3_info_t *merlin16_pcieg3_INTERNAL_get_merlin16_pcieg3_info_ptr(void); 276 277 /** Verify the internal merlin16_pcieg3_info. 278 * @return Error code, if generated (returns ERR_CODE_NONE if no errors) 279 */ 280 err_code_t merlin16_pcieg3_INTERNAL_verify_merlin16_pcieg3_info(merlin16_pcieg3_info_t const *test_info); 281 282 /** Read AFE HW Version. 283 * @param sa__ is an opaque state vector passed through to device access functions. 284 * @param *afe_hw_version AFE HW Version used 285 * @return Error Code, if generated (returns ERR_CODE_NONE if no errors) 286 */ 287 err_code_t merlin16_pcieg3_INTERNAL_get_afe_hw_version(srds_access_t *sa__, uint8_t *afe_hw_version); 288 289 /** Check if the micro's operations on that lane are stopped. 290 * @param sa__ is an opaque state vector passed through to device access functions. 291 * @return err_code Error Code "ERR_CODE_UC_NOT_STOPPED" returned if micro NOT stopped 292 */ 293 err_code_t merlin16_pcieg3_INTERNAL_check_uc_lane_stopped(srds_access_t *sa__); 294 295 /** Calculate the mode_sel parameter for tx pattern generator. 296 * @param *mode_sel Mode select to be used for generating required pattern 297 * @param *zero_pad_len Length of zero padding to be used for generating required pattern 298 * @param patt_length Desired Pattern length 299 * @return Error Code, if generated (returns ERR_CODE_NONE if no errors) 300 */ 301 err_code_t merlin16_pcieg3_INTERNAL_calc_patt_gen_mode_sel(uint8_t *mode_sel, uint8_t *zero_pad_len, uint8_t patt_length); 302 303 304 /*-------------------*/ 305 /* Ladder controls */ 306 /*-------------------*/ 307 /** Converts a ladder setting to mV, given the range. 308 * @param sa__ is an opaque state vector passed through to device access functions. 309 * @param ctrl is the threshold control (-31..31) maps to -RANGE to RANGE in non-uniform steps 310 * @param range_250 determines the range 0 = +/-150mV, 1 = +/-250mV 311 * @return ladder threshold voltage in mV 312 */ 313 int16_t merlin16_pcieg3_INTERNAL_ladder_setting_to_mV(srds_access_t *sa__, int8_t ctrl, uint8_t range_250); 314 315 /** Get the P1 slicer vertical level. 316 * @param sa__ is an opaque state vector passed through to device access functions. 317 * @param *val 8 bit signed value 318 * @return Error Code, if generated (returns ERR_CODE_NONE if no errors) 319 */ 320 err_code_t merlin16_pcieg3_INTERNAL_get_p1_threshold(srds_access_t *sa__, int8_t *val); 321 322 323 /*-----------------------*/ 324 /* TX_PI and ULL Setup */ 325 /*-----------------------*/ 326 327 328 /*-----------------------------------------*/ 329 /* APIs used in Config Shared TX Pattern */ 330 /*-----------------------------------------*/ 331 332 /** Compute Binary string for a Hex value ['0' to 'F']. 333 * @param var Hex value to be converted to Binary (eg: '6', 'A', ...) 334 * @param bin Binary string returned by API (eg: '0110', '1010', ...) 335 * @return Error Code generated by invalid hex variable (returns ERR_CODE_NONE if no errors) 336 */ 337 err_code_t merlin16_pcieg3_INTERNAL_compute_bin(char var, char bin[]); 338 339 /** Compute Hex value for a Binary string ['0000' to '1111']. 340 * @param bin Binary string to be coverted (eg: '0110', '1010', ...) 341 * @param *hex Hex value calculated from the input Binary string 342 * @return Error Code generated by invalid Binary string (returns ERR_CODE_NONE if no errors) 343 */ 344 err_code_t merlin16_pcieg3_INTERNAL_compute_hex(char bin[], uint8_t *hex); 345 346 /** Check micro state and request micro to stop 347 * @param sa__ is an opaque state vector passed through to device access functions. 348 * @param graceful select the method for stopping (1=graceful stop; 0=Immediate) 349 * @param *err_code_p pointer to err_code variable which will be returned. 350 */ 351 uint8_t merlin16_pcieg3_INTERNAL_stop_micro(srds_access_t *sa__, uint8_t graceful, err_code_t *err_code_p); 352 /*-----------------------------------*/ 353 /* APIs used in Read Event Logger */ 354 /*-----------------------------------*/ 355 356 /* State variable for dumping event log. 357 * This must be initialized with zeros. 358 */ 359 typedef struct { 360 uint16_t index, line_start_index; 361 } merlin16_pcieg3_INTERNAL_event_log_dump_state_t; 362 363 /** Callback function for dumping event log, intended to be called by merlin16_pcieg3_INTERNAL_read_event_log_with_callback. 364 * It must also be called once after, with a byte count of 0, to finish printing. 365 * @param *arg is a merlin16_pcieg3_INTERNAL_event_log_dump_state_t pointer for holding state. 366 * @param byte_count is the number of bytes to dump. 367 * -# This function is called repeatedly with a byte count of 2 with U16 values to dump. 368 * -# This function may then be called with a byte count of 1 if the event log has an odd number of bytes. 369 * -# Finally, this function must be called with a byte count of 0 to finish up. 370 * @param data is the event log data to dump. 371 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 372 */ 373 err_code_t merlin16_pcieg3_INTERNAL_event_log_dump_callback(void *arg, uint8_t byte_count, uint16_t data); 374 375 /** Get Event Log from uC, and call callback for every two bytes. 376 * @param sa__ is an opaque state vector passed through to device access functions. 377 * @param micro_num is the number of the microcontroller whose event log should be read. 378 * @param bypass_micro is 1 if the micro should not be involved (by stopping event log). 379 * This mode works even when the micro is hung, and it does not consume the event log. 380 * @param *arg is passed as the first argument to callback 381 * @param *callback is called with all of the data read, two bytes at a time. 382 * The last call of callback may have one byte; in that case, the upper byte is undefined. 383 * The call is in the form: callback(arg, byte_count, data) 384 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 385 */ 386 err_code_t merlin16_pcieg3_INTERNAL_read_event_log_with_callback(srds_access_t *sa__, 387 uint8_t micro_num, 388 uint8_t bypass_micro, 389 void *arg, 390 err_code_t (*callback)(void *, uint8_t, uint16_t)); 391 392 /** Convert float8 to usigned int32. 393 * uint32 = 1.XXX * 2^Y where float8 bits are XXXYYYYY 394 * @param input Float8 number 395 * @return Usigned 32bit number 396 */ 397 uint32_t merlin16_pcieg3_INTERNAL_float8_to_int32(float8_t input); 398 399 /** Convert uint8_t to 8-bit gray code. 400 * @param input Unsigned 8-bit number 401 * @return 8-bit gray code number 402 */ 403 uint8_t merlin16_pcieg3_INTERNAL_uint8_to_gray(uint8_t input); 404 405 /** Convert 8-bit gray code to uint8_t. 406 * @param input 8-bit gray code number 407 * @return Unsigned 8-bit number 408 */ 409 uint8_t merlin16_pcieg3_INTERNAL_gray_to_uint8(uint8_t input); 410 411 412 #ifdef TO_FLOATS 413 /*-----------------------------------*/ 414 /* APIs used in uC data conversion */ 415 /*-----------------------------------*/ 416 417 /** Convert usigned int32 to float8. 418 * uint32 = 1.XXX * 2^Y where float8 bits are XXXYYYYY 419 * @param input Unsigned int 420 * @return Float8 8 bit representations of 32bit number 421 */ 422 float8_t merlin16_pcieg3_INTERNAL_int32_to_float8(uint32_t input); 423 #endif 424 425 /** Convert float12 to usigned int32. 426 * uint32 = XXXXXXXX * 2^YYYY where float12 bits X=byte and Y=multi 427 * @param byte Float8 8bit 428 * @param multi 4 bit multipier 429 * @return Usigned 32bit number 430 */ 431 uint32_t merlin16_pcieg3_INTERNAL_float12_to_uint32(uint8_t byte, uint8_t multi); 432 433 #ifdef TO_FLOATS 434 /** Convert usigned int32 to float12. 435 * uint32 = XXXXXXXX * 2^YYYY where float12 bits X=byte and Y=multi 436 * @param input Unsigned int32 437 * @param *multi Pointer to byte and the multiplier is returned 438 * @return Float12 8 bit representations of 32bit number 439 */ 440 uint8_t merlin16_pcieg3_INTERNAL_uint32_to_float12(uint32_t input, uint8_t *multi); 441 #endif 442 443 /*-----------------------------*/ 444 /* Read / Display Core state */ 445 /*-----------------------------*/ 446 /** Read current merlin16_pcieg3 core status. 447 * @param sa__ is an opaque state vector passed through to device access functions. 448 * @param *istate Current merlin16_pcieg3 core status read back and populated by the API 449 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 450 */ 451 err_code_t merlin16_pcieg3_INTERNAL_read_core_state(srds_access_t *sa__, merlin16_pcieg3_core_state_st *istate); 452 453 454 /** Display current core state. 455 * Reads and displays all important core state values. 456 * @param sa__ is an opaque state vector passed through to device access functions. 457 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 458 */ 459 err_code_t merlin16_pcieg3_INTERNAL_display_core_state_no_newline(srds_access_t *sa__); 460 461 /*-----------------------------*/ 462 /* Read / Display Lane state */ 463 /*-----------------------------*/ 464 /** Read current merlin16_pcieg3 lane status. 465 * @param sa__ is an opaque state vector passed through to device access functions. 466 * @param *istate Current merlin16_pcieg3 lane status read back and populated by the API 467 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 468 */ 469 err_code_t merlin16_pcieg3_INTERNAL_read_lane_state(srds_access_t *sa__, merlin16_pcieg3_lane_state_st *istate); 470 471 472 /*-----------------*/ 473 /* Get OSR mode */ 474 /*-----------------*/ 475 /** Read current merlin16_pcieg3 lane status. 476 * @param sa__ is an opaque state vector passed through to device access functions. 477 * @param *mode Returns with the osr mode structure 478 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 479 */ 480 err_code_t merlin16_pcieg3_INTERNAL_get_osr_mode(srds_access_t *sa__, merlin16_pcieg3_osr_mode_st *mode); 481 482 483 /*-------------------*/ 484 /* Get LCK status */ 485 /*-------------------*/ 486 /** Read current PMD Lock and PMD Lock change status of a lane. 487 * @param sa__ is an opaque state vector passed through to device access functions. 488 * @param *pmd_lock Current merlin16_pcieg3 lane pmd_rx_lock status read back and populated by the API 489 * @param *pmd_lock_chg Current merlin16_pcieg3 lane pmd_rx_lock_change status read back and populated by the API 490 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 491 */ 492 err_code_t merlin16_pcieg3_INTERNAL_pmd_lock_status(srds_access_t *sa__, uint8_t *pmd_lock, uint8_t *pmd_lock_chg); 493 494 /** Read current Signal_detect and Signal_detect change status of a lane. 495 * @param sa__ is an opaque state vector passed through to device access functions. 496 * @param *sig_det Current merlin16_pcieg3 lane signal_detect status read back and populated by the API 497 * @param *sig_det_chg Current merlin16_pcieg3 lane signal_detect_change status read back and populated by the API 498 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 499 */ 500 err_code_t merlin16_pcieg3_INTERNAL_sigdet_status(srds_access_t *sa__, uint8_t *sig_det, uint8_t *sig_det_chg); 501 502 /** Read current PLL Lock and PLL Lock change status of a core. 503 * @param sa__ is an opaque state vector passed through to device access functions. 504 * @param *pll_lock Current merlin16_pcieg3 lane pll_lock status read back and populated by the API 505 * @param *pll_lock_chg Current merlin16_pcieg3 lane pll_lock_change status read back and populated by the API 506 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 507 */ 508 err_code_t merlin16_pcieg3_INTERNAL_pll_lock_status(srds_access_t *sa__, uint8_t *pll_lock, uint8_t *pll_lock_chg); 509 510 /** Display current lane state. 511 * Reads and displays all important lane state values. 512 * @param sa__ is an opaque state vector passed through to device access functions. 513 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 514 */ 515 err_code_t merlin16_pcieg3_INTERNAL_display_lane_state_no_newline(srds_access_t *sa__); 516 517 518 /** Serdes Core ClockGate. 519 * Along with merlin16_pcieg3_core_clkgate(), all lanes should also be clock gated using merlin16_pcieg3_lane_clkgate() to complete a Core Clockgate 520 * @param sa__ is an opaque state vector passed through to device access functions. 521 * @param enable Enable clockgate (1 = Enable clokgate; 0 = Disable clockgate) 522 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 523 */ 524 err_code_t merlin16_pcieg3_INTERNAL_core_clkgate(srds_access_t *sa__, uint8_t enable); 525 526 /** Serdes Lane ClockGate. 527 * @param sa__ is an opaque state vector passed through to device access functions. 528 * @param enable Enable lane clockgate (1 = Enable clockgate; 0 = Disable clockgate) 529 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 530 */ 531 err_code_t merlin16_pcieg3_INTERNAL_lane_clkgate(srds_access_t *sa__, uint8_t enable); 532 533 534 /*--------------------*/ 535 /* Get/Set PF status */ 536 /*--------------------*/ 537 /** Set function for PF. 538 * @param sa__ is an opaque state vector passed through to device access functions. 539 * @param val Signed input value 540 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 541 */ 542 err_code_t merlin16_pcieg3_INTERNAL_set_rx_pf_main(srds_access_t *sa__, uint8_t val); 543 544 /** Get function for PF 545 * @param sa__ is an opaque state vector passed through to device access functions. 546 * @param *val PF read value 547 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 548 */ 549 err_code_t merlin16_pcieg3_INTERNAL_get_rx_pf_main(srds_access_t *sa__, int8_t *val); 550 551 /** Set function for PF2. 552 * @param sa__ is an opaque state vector passed through to device access functions. 553 * @param val signed input value 554 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 555 */ 556 err_code_t merlin16_pcieg3_INTERNAL_set_rx_pf2(srds_access_t *sa__, uint8_t val); 557 558 /** Get function for PF2. 559 * @param sa__ is an opaque state vector passed through to device access functions. 560 * @param *val PF2 read value 561 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 562 */ 563 err_code_t merlin16_pcieg3_INTERNAL_get_rx_pf2(srds_access_t *sa__, int8_t *val); 564 565 566 567 /*-------------------*/ 568 /* Get/Set VGA/DFE */ 569 /*-------------------*/ 570 /** Set function for VGA. 571 * @param sa__ is an opaque state vector passed through to device access functions. 572 * @param val signed input value 573 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 574 */ 575 err_code_t merlin16_pcieg3_INTERNAL_set_rx_vga(srds_access_t *sa__, uint8_t val); 576 577 /** Get function for VGA. 578 * @param sa__ is an opaque state vector passed through to device access functions. 579 * @param *val VGA read value 580 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 581 */ 582 err_code_t merlin16_pcieg3_INTERNAL_get_rx_vga(srds_access_t *sa__, int8_t *val); 583 584 585 /** Set function for DFE Tap1. 586 * @param sa__ is an opaque state vector passed through to device access functions. 587 * @param val signed input value 588 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 589 */ 590 err_code_t merlin16_pcieg3_INTERNAL_set_rx_dfe1(srds_access_t *sa__, int8_t val); 591 592 /** Get function for DFE Tap1. 593 * @param sa__ is an opaque state vector passed through to device access functions. 594 * @param *val DFE1 read value 595 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 596 */ 597 err_code_t merlin16_pcieg3_INTERNAL_get_rx_dfe1(srds_access_t *sa__, int8_t *val); 598 599 /** Set function for DFE Tap2. 600 * @param sa__ is an opaque state vector passed through to device access functions. 601 * @param val signed input value 602 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 603 */ 604 err_code_t merlin16_pcieg3_INTERNAL_set_rx_dfe2(srds_access_t *sa__, int8_t val); 605 606 /** Get function for DFE Tap2. 607 * @param sa__ is an opaque state vector passed through to device access functions. 608 * @param *val DFE2 read value 609 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 610 */ 611 err_code_t merlin16_pcieg3_INTERNAL_get_rx_dfe2(srds_access_t *sa__, int8_t *val); 612 613 /** Set function for DFE Tap3. 614 * @param sa__ is an opaque state vector passed through to device access functions. 615 * @param val signed input value 616 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 617 */ 618 err_code_t merlin16_pcieg3_INTERNAL_set_rx_dfe3(srds_access_t *sa__, int8_t val); 619 620 /** Get function for DFE Tap3. 621 * @param sa__ is an opaque state vector passed through to device access functions. 622 * @param *val DFE3 read value 623 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 624 */ 625 err_code_t merlin16_pcieg3_INTERNAL_get_rx_dfe3(srds_access_t *sa__, int8_t *val); 626 627 /** Set function for DFE Tap4. 628 * @param sa__ is an opaque state vector passed through to device access functions. 629 * @param val signed input value 630 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 631 */ 632 err_code_t merlin16_pcieg3_INTERNAL_set_rx_dfe4(srds_access_t *sa__, int8_t val); 633 634 /** Get function for DFE Tap4. 635 * @param sa__ is an opaque state vector passed through to device access functions. 636 * @param *val DFE4 read value 637 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 638 */ 639 err_code_t merlin16_pcieg3_INTERNAL_get_rx_dfe4(srds_access_t *sa__, int8_t *val); 640 641 /** Set function for DFE Tap5. 642 * @param sa__ is an opaque state vector passed through to device access functions. 643 * @param val signed input value 644 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 645 */ 646 err_code_t merlin16_pcieg3_INTERNAL_set_rx_dfe5(srds_access_t *sa__, int8_t val); 647 648 /** Get function for DFE Tap5 649 * @param sa__ is an opaque state vector passed through to device access functions. 650 * @param *val DFE5 read value 651 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 652 */ 653 err_code_t merlin16_pcieg3_INTERNAL_get_rx_dfe5(srds_access_t *sa__, int8_t *val); 654 655 656 /*----------------------*/ 657 /* Get/Set TXFIR Taps */ 658 /*----------------------*/ 659 660 661 uint8_t merlin16_pcieg3_INTERNAL_rdb_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr); 662 uint16_t merlin16_pcieg3_INTERNAL_rdw_uc_var(srds_access_t *sa__, err_code_t *err_code_p, uint16_t addr); 663 err_code_t merlin16_pcieg3_INTERNAL_wrb_uc_var(srds_access_t *sa__, uint16_t addr, uint8_t wr_val); 664 err_code_t merlin16_pcieg3_INTERNAL_wrw_uc_var(srds_access_t *sa__, uint16_t addr, uint16_t wr_val); 665 666 /*--------------------------*/ 667 /* Register field polling */ 668 /*--------------------------*/ 669 670 err_code_t merlin16_pcieg3_INTERNAL_print_uc_dsc_error(srds_access_t *sa__, enum srds_pmd_uc_cmd_enum cmd); 671 672 /** Polls lane variable "usr_diag_status" to verify data is available in uC diag buffer. 673 * Define macro CUSTOM_REG_POLLING to replace the default implementation provided in merlin16_pcieg3_internal.c. 674 * 675 * @param sa__ is an opaque state vector passed through to device access functions. 676 * @param *status returns a status byte \n 677 * bit 15 - indicates the ey scan is complete \n 678 * bit 14-0 - reserved for debug 679 * 680 * @param timeout_ms Maximum time interval in milliseconds for which the polling is done 681 * @return Error code generated by polling function (returns ERR_CODE_NONE if no errors) 682 */ 683 err_code_t merlin16_pcieg3_INTERNAL_poll_diag_done(srds_access_t *sa__, uint16_t *status, uint32_t timeout_ms); 684 685 /** Polls for register field "uc_dsc_ready_for_cmd" to be 1 within the time interval specified by timeout_ms. 686 * Function returns 0 if polling passes, else it returns error code. 687 * Define macro CUSTOM_REG_POLLING to replace the default implementation provided in merlin16_pcieg3_internal.c. 688 * @param sa__ is an opaque state vector passed through to device access functions. 689 * @param timeout_ms Maximum time interval in milliseconds for which the polling is done 690 * @param cmd The command that was issued; this is used for error reporting. 691 * @return Error code generated by polling function (returns ERR_CODE_NONE if no errors) 692 */ 693 err_code_t merlin16_pcieg3_INTERNAL_poll_uc_dsc_ready_for_cmd_equals_1(srds_access_t *sa__, uint32_t timeout_ms, enum srds_pmd_uc_cmd_enum cmd); 694 695 /** Polls for register field "dsc_state" to be "DSC_STATE_UC_TUNE" 696 * within the time interval specified by timeout_ms. 697 * Function returns 0 if polling passes, else it returns error code. 698 * Define macro CUSTOM_REG_POLLING to replace the default implementation provided in merlin16_pcieg3_internal.c. 699 * @param sa__ is an opaque state vector passed through to device access functions. 700 * @param timeout_ms Maximum time interval in milliseconds for which the polling is done 701 * @return Error code generated by polling function (returns ERR_CODE_NONE if no errors) 702 */ 703 err_code_t merlin16_pcieg3_INTERNAL_poll_dsc_state_equals_uc_tune(srds_access_t *sa__, uint32_t timeout_ms); 704 705 706 /** Polls for register field "micro_ra_initdone" to be 1 within the time interval specified by timeout_ms. 707 * Function returns 0 if polling passes, else it returns error code. 708 * Define macro CUSTOM_REG_POLLING to replace the default implementation provided in merlin16_pcieg3_internal.c. 709 * @param sa__ is an opaque state vector passed through to device access functions. 710 * @param timeout_ms Maximum time interval in milliseconds for which the polling is done 711 * @return Error code generated by polling function (returns ERR_CODE_NONE if no errors) 712 */ 713 err_code_t merlin16_pcieg3_INTERNAL_poll_micro_ra_initdone(srds_access_t *sa__, uint32_t timeout_ms); 714 715 716 /*--------------------------------*/ 717 /* RAM Block Read with Callback */ 718 /*--------------------------------*/ 719 720 /* Utilities to account for endianness when reading from uc RAM */ 721 static const int merlin16_pcieg3_endian_const = 1; 722 #define is_big_endian() ((*(char*)&merlin16_pcieg3_endian_const) == 0) 723 #define get_endian_offset(addr) (is_big_endian() ? \ 724 (\ 725 (((USR_UINTPTR)(addr))%4 == 0) ? 3 : \ 726 (((USR_UINTPTR)(addr))%4 == 1) ? 1 : \ 727 (((USR_UINTPTR)(addr))%4 == 2) ? -1 : \ 728 (((USR_UINTPTR)(addr))%4 == 3) ? -3 : \ 729 0) \ 730 : 0) 731 732 typedef struct { 733 uint8_t *mem_ptr; 734 } merlin16_pcieg3_INTERNAL_rdblk_callback_arg_t; 735 736 /** Callback function for reading uc RAM memory by merlin16_pcieg3_INTERNAL_rdblk_uc_generic_ram(). 737 * @param *arg is a merlin16_pcieg3_INTERNAL_rdblk_callback_arg_t pointer for holding state. 738 * @param byte_count is the number of bytes to store. 739 * -# This function is called repeatedly with a byte count of 2 with U16 values to store. 740 * -# This function may then be called with a byte count of 1 if there are an odd number of bytes. 741 * @param data is the RAM data to store. 742 * @return Error Code generated by API (returns ERR_CODE_NONE if no errors) 743 */ 744 err_code_t merlin16_pcieg3_INTERNAL_rdblk_callback(void *arg, uint8_t byte_count, uint16_t data); 745 746 /** Block RAM read through Micro Register Interface, suitable for program RAM or non-program RAM. 747 * This reads a block of RAM, possibly starting midway through it and wrapping back to the beginning. 748 * The order of operations is: 749 * -# RAM will be read from (block_addr+start_offset) to (block_addr+block_size-1), 750 * up to cnt bytes. 751 * -# RAM will be read from block_addr to (block_addr+block_size-1), repeating 752 * indefinitely, until cnt bytes total are read. 753 * @param sa__ is an opaque state vector passed through to device access functions. 754 * @param block_addr Address of RAM block to be read. 755 * For program RAM, the upper 16 bits are 0x0000. Otherwise, the upper 16 bits are 0x2000. 756 * @param block_size Length of RAM block to read. 757 * @param start_offset Offset within RAM block to start reading 758 * @param cnt Number of bytes to be read 759 * @param *arg is passed as the first argument to callback 760 * @param *callback is called with all of the data read, two bytes at a time. 761 * The last call of callback may have one byte; in that case, the upper byte is undefined. 762 * The call is in the form: callback(arg, byte_count, data) 763 * @return Error Code generated by API or the callback (returns ERR_CODE_NONE if no errors) 764 */ 765 err_code_t merlin16_pcieg3_INTERNAL_rdblk_uc_generic_ram(srds_access_t *sa__, 766 uint32_t block_addr, 767 uint16_t block_size, 768 uint16_t start_offset, 769 uint16_t cnt, 770 void *arg, 771 err_code_t (*callback)(void *, uint8_t, uint16_t)); 772 773 /** Block RAM read through Micro Register Interface, suitable for program RAM or non-program RAM. 774 * This reads a block of RAM, possibly starting midway through it and wrapping back to the beginning. 775 * The order of operations is: 776 * -# RAM will be read from (block_addr+start_offset) down to block_addr, up to cnt bytes. 777 * -# RAM will be read from (block_addr+block_size-1) down to block_addr, repeating 778 * indefinitely, until cnt bytes total are read. 779 * In other words, this is the same as merlin16_pcieg3_INTERNAL_rdblk_uc_generic_ram(), but reading in descending address order. 780 * @param sa__ is an opaque state vector passed through to device access functions. 781 * @param block_addr Address of RAM block to be read. 782 * For program RAM, the upper 16 bits are 0x0000. Otherwise, the upper 16 bits are 0x2000. 783 * @param block_size Length of RAM block to read. 784 * @param start_offset Offset within RAM block to start reading 785 * @param cnt Number of bytes to be read 786 * @param *arg is passed as the first argument to callback 787 * @param *callback is called with all of the data read, two bytes at a time. 788 * The last call of callback may have one byte; in that case, the upper byte is undefined. 789 * The call is in the form: callback(arg, byte_count, data) 790 * @return Error Code generated by API or the callback (returns ERR_CODE_NONE if no errors) 791 */ 792 err_code_t merlin16_pcieg3_INTERNAL_rdblk_uc_generic_ram_descending(srds_access_t *sa__, 793 uint32_t block_addr, 794 uint16_t block_size, 795 uint16_t start_offset, 796 uint16_t cnt, 797 void *arg, 798 err_code_t (*callback)(void *, uint8_t, uint16_t)); 799 800 /** Retrieve micro index based on lane index. 801 * @param lane Lane index 802 * @return Micro index 803 */ 804 uint8_t merlin16_pcieg3_INTERNAL_grp_idx_from_lane(uint8_t lane); 805 806 807 808 /*-------------------*/ 809 /* Name resolution */ 810 /*-------------------*/ 811 812 /* For bitfields that differ for different cores, these macros are defined to resolve the bitfield. */ 813 814 #if defined(wr_rx_pf_ctrl) 815 # define WR_RX_PF_CTRL wr_rx_pf_ctrl 816 # define RD_RX_PF_CTRL rd_rx_pf_ctrl 817 # define WR_RX_PF2_CTRL wr_rx_pf2_ctrl 818 # define RD_RX_PF2_CTRL rd_rx_pf2_ctrl 819 #elif defined(wr_rx_pf_ctrl_val) 820 # define WR_RX_PF_CTRL wr_rx_pf_ctrl_val 821 # define RD_RX_PF_CTRL rd_rx_pf_ctrl_val 822 # define WR_RX_PF2_CTRL wr_rx_pf2_ctrl_val 823 # define RD_RX_PF2_CTRL rd_rx_pf2_ctrl_val 824 #elif defined(wr_pf_ctrl) 825 # define WR_RX_PF_CTRL wr_pf_ctrl 826 # define RD_RX_PF_CTRL rd_pf_ctrl 827 # define WR_RX_PF2_CTRL wr_pf2_lowp_ctrl 828 # define RD_RX_PF2_CTRL rd_pf2_lowp_ctrl 829 #else 830 # error "Could not find write to pf_ctrl bitfield." 831 #endif 832 833 #if defined(reg_rd_TLB_RX_RXPRBS_CHK_ERR_CNT_MSB_STATUS) 834 # define REG_RD_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS reg_rd_TLB_RX_RXPRBS_CHK_ERR_CNT_MSB_STATUS 835 # define REG_RD_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS reg_rd_TLB_RX_RXPRBS_CHK_ERR_CNT_LSB_STATUS 836 #elif defined(reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS) 837 # define REG_RD_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS 838 # define REG_RD_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS 839 #else 840 # error "Could not find PRBS_CHK_ERR_CNT_MSB_STATUS." 841 #endif 842 843 #endif