merlin16_pcieg3_fields.h (770554B)
1 /************************************************************************************* 2 ************************************************************************************* 3 * * 4 * Revision : * 5 * * 6 * Description : Register access macros for MERLIN16_PCIEG3 7 * * 8 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 9 * 10 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 11 * No portions of this material may be reproduced in any form without * 12 * the written permission of: * 13 * Broadcom Corporation * 14 * 5300 California Avenue * 15 * Irvine, CA 92617 * 16 * * 17 * All information contained in this document is Broadcom Corporation * 18 * company private proprietary, and trade secret. * 19 */ 20 21 /** @file merlin16_pcieg3_fields.h 22 * Register access macros for MERLIN16_PCIEG3 23 */ 24 25 /* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */ 26 27 #ifndef MERLIN16_PCIEG3_FIELDS_H 28 #define MERLIN16_PCIEG3_FIELDS_H 29 30 #define rd_ams_rx_term_lowzvdd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,0,15,__ERR) 31 #define wr_ams_rx_term_lowzvdd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x8000,15,wr_val) 32 #define rd_ams_rx_term_lowzgnd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,1,15,__ERR) 33 #define wr_ams_rx_term_lowzgnd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x4000,14,wr_val) 34 #define rd_ams_rx_term_cmult_ena() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,2,15,__ERR) 35 #define wr_ams_rx_term_cmult_ena(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x2000,13,wr_val) 36 #define rd_ams_rx_term_cm_ena() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,3,15,__ERR) 37 #define wr_ams_rx_term_cm_ena(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x1000,12,wr_val) 38 #define rd_ams_rx_en_rxck_test() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,4,14,__ERR) 39 #define wr_ams_rx_en_rxck_test(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0c00,10,wr_val) 40 #define rd_ams_rx_en_rxck_testport() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,6,15,__ERR) 41 #define wr_ams_rx_en_rxck_testport(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0200,9,wr_val) 42 #define rd_ams_rx_spare_0_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,7,12,__ERR) 43 #define wr_ams_rx_spare_0_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x01e0,5,wr_val) 44 #define rd_ams_rx_rcm_sum() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,11,15,__ERR) 45 #define wr_ams_rx_rcm_sum(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0010,4,wr_val) 46 #define rd_ams_rx_sigdet_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,12,15,__ERR) 47 #define wr_ams_rx_sigdet_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0008,3,wr_val) 48 #define rd_ams_rx_sigdet_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,13,15,__ERR) 49 #define wr_ams_rx_sigdet_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0004,2,wr_val) 50 #define rd_ams_rx_cm_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,14,15,__ERR) 51 #define wr_ams_rx_cm_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0002,1,wr_val) 52 #define rd_ams_rx_sum_pseudo_diff() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd090,15,15,__ERR) 53 #define wr_ams_rx_sum_pseudo_diff(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd090,0x0001,0,wr_val) 54 #define rd_ams_rx_curr_dfe_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd091,2,13,__ERR) 55 #define wr_ams_rx_curr_dfe_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd091,0x3800,11,wr_val) 56 #define rd_ams_rx_spare_1_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd091,5,13,__ERR) 57 #define wr_ams_rx_spare_1_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd091,0x0700,8,wr_val) 58 #define rd_ams_rx_curr_pi() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd091,8,13,__ERR) 59 #define wr_ams_rx_curr_pi(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd091,0x00e0,5,wr_val) 60 #define rd_ams_rx_curr_ctle() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd091,11,13,__ERR) 61 #define wr_ams_rx_curr_ctle(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd091,0x001c,2,wr_val) 62 #define rd_ams_rx_vga_en_hgain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd091,14,15,__ERR) 63 #define wr_ams_rx_vga_en_hgain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd091,0x0002,1,wr_val) 64 #define rd_ams_rx_vga_out_idle() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd091,15,15,__ERR) 65 #define wr_ams_rx_vga_out_idle(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd091,0x0001,0,wr_val) 66 #define rd_ams_rx_spare_2_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd092,0,14,__ERR) 67 #define wr_ams_rx_spare_2_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd092,0xc000,14,wr_val) 68 #define rd_ams_rx_en_dfe_tap_fb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd092,2,11,__ERR) 69 #define wr_ams_rx_en_dfe_tap_fb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd092,0x3e00,9,wr_val) 70 #define rd_ams_rx_curr_vga() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd092,7,13,__ERR) 71 #define wr_ams_rx_curr_vga(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd092,0x01c0,6,wr_val) 72 #define rd_ams_rx_curr_dfe_summer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd092,10,13,__ERR) 73 #define wr_ams_rx_curr_dfe_summer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd092,0x0038,3,wr_val) 74 #define rd_ams_rx_curr_dfe_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd092,13,13,__ERR) 75 #define wr_ams_rx_curr_dfe_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd092,0x0007,0,wr_val) 76 #define rd_ams_rx_ll_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,1,15,__ERR) 77 #define wr_ams_rx_ll_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x4000,14,wr_val) 78 #define rd_ams_rx_seli1p25dfe() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,2,15,__ERR) 79 #define wr_ams_rx_seli1p25dfe(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x2000,13,wr_val) 80 #define rd_ams_rx_i4deadzone() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,3,15,__ERR) 81 #define wr_ams_rx_i4deadzone(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x1000,12,wr_val) 82 #define rd_ams_rx_curr_sigdet() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,4,13,__ERR) 83 #define wr_ams_rx_curr_sigdet(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0e00,9,wr_val) 84 #define rd_ams_rx_curr_vddr_afe() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,7,13,__ERR) 85 #define wr_ams_rx_curr_vddr_afe(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x01c0,6,wr_val) 86 #define rd_ams_rx_os2x_mode_even_odd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,10,15,__ERR) 87 #define wr_ams_rx_os2x_mode_even_odd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0020,5,wr_val) 88 #define rd_ams_rx_dfe_os2x_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,11,15,__ERR) 89 #define wr_ams_rx_dfe_os2x_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0010,4,wr_val) 90 #define rd_ams_rx_en_20b_demux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,12,15,__ERR) 91 #define wr_ams_rx_en_20b_demux(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0008,3,wr_val) 92 #define rd_ams_rx_en_clk16() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,13,15,__ERR) 93 #define wr_ams_rx_en_clk16(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0004,2,wr_val) 94 #define rd_ams_rx_en_clk33() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,14,15,__ERR) 95 #define wr_ams_rx_en_clk33(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0002,1,wr_val) 96 #define rd_ams_rx_en_vcctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd093,15,15,__ERR) 97 #define wr_ams_rx_en_vcctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd093,0x0001,0,wr_val) 98 #define rd_ams_rx_vga_pon() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd094,0,12,__ERR) 99 #define wr_ams_rx_vga_pon(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd094,0xf000,12,wr_val) 100 #define rd_ams_rx_oc_2x() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd094,4,15,__ERR) 101 #define wr_ams_rx_oc_2x(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd094,0x0800,11,wr_val) 102 #define rd_ams_rx_spare_4_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd094,5,13,__ERR) 103 #define wr_ams_rx_spare_4_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd094,0x0700,8,wr_val) 104 #define rd_ams_rx_en_recclkdiv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd094,8,15,__ERR) 105 #define wr_ams_rx_en_recclkdiv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd094,0x0080,7,wr_val) 106 #define rd_ams_rx_div3o4o5() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd094,9,14,__ERR) 107 #define wr_ams_rx_div3o4o5(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd094,0x0060,5,wr_val) 108 #define rd_ams_rx_recclkdiv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd094,11,11,__ERR) 109 #define wr_ams_rx_recclkdiv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd094,0x001f,0,wr_val) 110 #define rd_ams_rx_dcc2_phase_flip() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,0,15,__ERR) 111 #define wr_ams_rx_dcc2_phase_flip(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x8000,15,wr_val) 112 #define rd_ams_rx_slcr_calib_range_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,1,15,__ERR) 113 #define wr_ams_rx_slcr_calib_range_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x4000,14,wr_val) 114 #define rd_ams_rx_pi_pd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,2,15,__ERR) 115 #define wr_ams_rx_pi_pd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x2000,13,wr_val) 116 #define rd_ams_rx_dcc1_phase_flip() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,3,15,__ERR) 117 #define wr_ams_rx_dcc1_phase_flip(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x1000,12,wr_val) 118 #define rd_ams_rx_en_dfeclk() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,4,15,__ERR) 119 #define wr_ams_rx_en_dfeclk(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x0800,11,wr_val) 120 #define rd_ams_rx_ctle_gain_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,5,12,__ERR) 121 #define wr_ams_rx_ctle_gain_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x0780,7,wr_val) 122 #define rd_ams_rx_curr_in_offset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,9,13,__ERR) 123 #define wr_ams_rx_curr_in_offset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x0070,4,wr_val) 124 #define rd_ams_rx_pon() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd095,12,12,__ERR) 125 #define wr_ams_rx_pon(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd095,0x000f,0,wr_val) 126 #define rd_ams_rx_sigdet_offset_correction_pos() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd096,3,11,__ERR) 127 #define wr_ams_rx_sigdet_offset_correction_pos(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd096,0x1f00,8,wr_val) 128 #define rd_ams_rx_sigdet_calibration_select() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd096,8,15,__ERR) 129 #define wr_ams_rx_sigdet_calibration_select(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd096,0x0080,7,wr_val) 130 #define rd_ams_rx_sum_gain_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd096,9,12,__ERR) 131 #define wr_ams_rx_sum_gain_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd096,0x0078,3,wr_val) 132 #define rd_ams_rx_en_sigdet_calib() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd096,13,15,__ERR) 133 #define wr_ams_rx_en_sigdet_calib(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd096,0x0004,2,wr_val) 134 #define rd_ams_rx_hiz_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd096,14,15,__ERR) 135 #define wr_ams_rx_hiz_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd096,0x0002,1,wr_val) 136 #define rd_ams_rx_m1_sign() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd096,15,15,__ERR) 137 #define wr_ams_rx_m1_sign(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd096,0x0001,0,wr_val) 138 #define rd_ams_rx_spare_7_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd097,2,12,__ERR) 139 #define wr_ams_rx_spare_7_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd097,0x3c00,10,wr_val) 140 #define rd_ams_rx_sigdet_threshold() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd097,6,11,__ERR) 141 #define wr_ams_rx_sigdet_threshold(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd097,0x03e0,5,wr_val) 142 #define rd_ams_rx_sigdet_offset_correction_neg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd097,11,11,__ERR) 143 #define wr_ams_rx_sigdet_offset_correction_neg(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd097,0x001f,0,wr_val) 144 #define rd_ams_rx_rxpon_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd098,14,15,__ERR) 145 #define wr_ams_rx_rxpon_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd098,0x0002,1,wr_val) 146 #define rd_ams_rx_vgapon_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd098,15,15,__ERR) 147 #define wr_ams_rx_vgapon_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd098,0x0001,0,wr_val) 148 #define rd_ams_rx_vgapon_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd099,8,12,__ERR) 149 #define rd_ams_rx_rxpon_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd099,12,12,__ERR) 150 #define rd_ams_tx_lowlatency_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,0,15,__ERR) 151 #define wr_ams_tx_lowlatency_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x8000,15,wr_val) 152 #define rd_ams_tx_fifo_resetb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,1,15,__ERR) 153 #define wr_ams_tx_fifo_resetb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x4000,14,wr_val) 154 #define rd_ams_tx_ll_fifo_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,2,13,__ERR) 155 #define wr_ams_tx_ll_fifo_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x3800,11,wr_val) 156 #define rd_ams_tx_ll_fifo_zero_out() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,5,15,__ERR) 157 #define wr_ams_tx_ll_fifo_zero_out(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0400,10,wr_val) 158 #define rd_ams_tx_ll_polarity_flip() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,6,15,__ERR) 159 #define wr_ams_tx_ll_polarity_flip(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0200,9,wr_val) 160 #define rd_ams_tx_ll_selpath_tx() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,7,15,__ERR) 161 #define wr_ams_tx_ll_selpath_tx(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0100,8,wr_val) 162 #define rd_ams_tx_enable_os_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,8,15,__ERR) 163 #define wr_ams_tx_enable_os_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0080,7,wr_val) 164 #define rd_ams_tx_pon() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,9,12,__ERR) 165 #define wr_ams_tx_pon(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0078,3,wr_val) 166 #define rd_ams_tx_ticksel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,13,14,__ERR) 167 #define wr_ams_tx_ticksel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0006,1,wr_val) 168 #define rd_ams_tx_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a0,15,15,__ERR) 169 #define wr_ams_tx_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0001,0,wr_val) 170 #define rd_ams_tx_en_slow() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,1,12,__ERR) 171 #define wr_ams_tx_en_slow(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x7800,11,wr_val) 172 #define rd_ams_tx_en_wclk33() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,5,15,__ERR) 173 #define wr_ams_tx_en_wclk33(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0400,10,wr_val) 174 #define rd_ams_tx_en_wclk20() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,6,15,__ERR) 175 #define wr_ams_tx_en_wclk20(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0200,9,wr_val) 176 #define rd_ams_tx_en_wclk16() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,7,15,__ERR) 177 #define wr_ams_tx_en_wclk16(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0100,8,wr_val) 178 #define rd_ams_tx_testclk_ena() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,8,15,__ERR) 179 #define wr_ams_tx_testclk_ena(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0080,7,wr_val) 180 #define rd_ams_tx_testsel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,9,14,__ERR) 181 #define wr_ams_tx_testsel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0060,5,wr_val) 182 #define rd_ams_tx_cntrl_rxdetect_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,11,15,__ERR) 183 #define wr_ams_tx_cntrl_rxdetect_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0010,4,wr_val) 184 #define rd_ams_tx_rxdtct_th_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,12,14,__ERR) 185 #define wr_ams_tx_rxdtct_th_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x000c,2,wr_val) 186 #define rd_ams_tx_en_high_current() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,14,15,__ERR) 187 #define wr_ams_tx_en_high_current(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0002,1,wr_val) 188 #define rd_ams_tx_enable_os_4() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a1,15,15,__ERR) 189 #define wr_ams_tx_enable_os_4(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0001,0,wr_val) 190 #define rd_ams_tx_fifo_phsdetect_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a2,1,15,__ERR) 191 #define wr_ams_tx_fifo_phsdetect_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a2,0x4000,14,wr_val) 192 #define rd_ams_tx_ibias_pibuf_cntl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a2,2,13,__ERR) 193 #define wr_ams_tx_ibias_pibuf_cntl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a2,0x3800,11,wr_val) 194 #define rd_ams_tx_ibias_pi_cntl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a2,5,13,__ERR) 195 #define wr_ams_tx_ibias_pi_cntl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a2,0x0700,8,wr_val) 196 #define rd_ams_tx_ibias_opamp_cntl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a2,8,13,__ERR) 197 #define wr_ams_tx_ibias_opamp_cntl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a2,0x00e0,5,wr_val) 198 #define rd_ams_tx_dcc_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a2,11,15,__ERR) 199 #define wr_ams_tx_dcc_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a2,0x0010,4,wr_val) 200 #define rd_ams_tx_en_hpf() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a2,12,12,__ERR) 201 #define wr_ams_tx_en_hpf(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a2,0x000f,0,wr_val) 202 #define rd_ams_tx_refcalm() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a3,2,12,__ERR) 203 #define wr_ams_tx_refcalm(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a3,0x3c00,10,wr_val) 204 #define rd_ams_tx_refcalp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a3,6,12,__ERR) 205 #define wr_ams_tx_refcalp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a3,0x03c0,6,wr_val) 206 #define rd_ams_tx_refcalshunt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a3,10,12,__ERR) 207 #define wr_ams_tx_refcalshunt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a3,0x003c,2,wr_val) 208 #define rd_ams_tx_spare_3_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a3,14,14,__ERR) 209 #define wr_ams_tx_spare_3_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a3,0x0003,0,wr_val) 210 #define rd_ams_tx_shntpost2_post2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a4,0,12,__ERR) 211 #define wr_ams_tx_shntpost2_post2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a4,0xf000,12,wr_val) 212 #define rd_ams_tx_shntpost1_post1pre() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a4,4,10,__ERR) 213 #define wr_ams_tx_shntpost1_post1pre(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a4,0x0fc0,6,wr_val) 214 #define rd_ams_tx_shntpre_post1pre() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a4,10,10,__ERR) 215 #define wr_ams_tx_shntpre_post1pre(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a4,0x003f,0,wr_val) 216 #define rd_ams_tx_post2to1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a5,2,15,__ERR) 217 #define wr_ams_tx_post2to1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a5,0x2000,13,wr_val) 218 #define rd_ams_tx_en_pre() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a5,3,15,__ERR) 219 #define wr_ams_tx_en_pre(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a5,0x1000,12,wr_val) 220 #define rd_ams_tx_en_post1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a5,4,15,__ERR) 221 #define wr_ams_tx_en_post1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0800,11,wr_val) 222 #define rd_ams_tx_en_post2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a5,5,15,__ERR) 223 #define wr_ams_tx_en_post2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0400,10,wr_val) 224 #define rd_ams_tx_shntmain_post2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a5,6,12,__ERR) 225 #define wr_ams_tx_shntmain_post2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a5,0x03c0,6,wr_val) 226 #define rd_ams_tx_shntmain_post1pre() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a5,10,10,__ERR) 227 #define wr_ams_tx_shntmain_post1pre(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a5,0x003f,0,wr_val) 228 #define rd_ams_tx_shntpost1_post1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a6,0,11,__ERR) 229 #define wr_ams_tx_shntpost1_post1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a6,0xf800,11,wr_val) 230 #define rd_ams_tx_dis_cal() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a6,5,11,__ERR) 231 #define wr_ams_tx_dis_cal(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a6,0x07c0,6,wr_val) 232 #define rd_ams_tx_spare_6_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a6,10,12,__ERR) 233 #define wr_ams_tx_spare_6_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a6,0x003c,2,wr_val) 234 #define rd_ams_tx_pd_phasedet() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a6,14,15,__ERR) 235 #define wr_ams_tx_pd_phasedet(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a6,0x0002,1,wr_val) 236 #define rd_ams_tx_en_shuntmode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a6,15,15,__ERR) 237 #define wr_ams_tx_en_shuntmode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a6,0x0001,0,wr_val) 238 #define rd_ams_tx_refcalpcs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a7,3,12,__ERR) 239 #define wr_ams_tx_refcalpcs(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a7,0x1e00,9,wr_val) 240 #define rd_ams_tx_refcalmcs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a7,7,12,__ERR) 241 #define wr_ams_tx_refcalmcs(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a7,0x01e0,5,wr_val) 242 #define rd_ams_tx_shntmain_post1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a7,11,11,__ERR) 243 #define wr_ams_tx_shntmain_post1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a7,0x001f,0,wr_val) 244 #define rd_ams_tx_spare_8_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a8,7,8,__ERR) 245 #define wr_ams_tx_spare_8_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a8,0x01fe,1,wr_val) 246 #define rd_ams_tx_shnten_main() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a8,15,15,__ERR) 247 #define wr_ams_tx_shnten_main(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a8,0x0001,0,wr_val) 248 #define rd_ams_tx_sel_txmaster() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a9,12,15,__ERR) 249 #define wr_ams_tx_sel_txmaster(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0008,3,wr_val) 250 #define rd_ams_tx_auto_ll_selpath_tx_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a9,13,15,__ERR) 251 #define wr_ams_tx_auto_ll_selpath_tx_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0004,2,wr_val) 252 #define rd_ams_tx_txpon_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0a9,14,15,__ERR) 253 #define wr_ams_tx_txpon_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0002,1,wr_val) 254 #define rd_ams_tx_rescal() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0aa,8,12,__ERR) 255 #define rd_ams_tx_txpon_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0aa,12,12,__ERR) 256 #define rdc_ams_pll_cpar() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b0,0,14,__ERR) 257 #define wrc_ams_pll_cpar(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b0,0xc000,14,wr_val) 258 #define rdc_ams_pll_term_cm_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b0,2,15,__ERR) 259 #define wrc_ams_pll_term_cm_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b0,0x2000,13,wr_val) 260 #define rdc_ams_pll_spare_0_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b0,3,15,__ERR) 261 #define wrc_ams_pll_spare_0_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b0,0x1000,12,wr_val) 262 #define rdc_ams_pll_rpar() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b0,4,13,__ERR) 263 #define wrc_ams_pll_rpar(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0e00,9,wr_val) 264 #define rdc_ams_pll_lc_refclk_adj_1_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b0,7,14,__ERR) 265 #define wrc_ams_pll_lc_refclk_adj_1_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0180,7,wr_val) 266 #define rdc_ams_pll_spare_0_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b0,9,9,__ERR) 267 #define wrc_ams_pll_spare_0_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b0,0x007f,0,wr_val) 268 #define rdc_ams_pll_en_hcur_vco() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,0,15,__ERR) 269 #define wrc_ams_pll_en_hcur_vco(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x8000,15,wr_val) 270 #define rdc_ams_pll_enb_10t() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,1,15,__ERR) 271 #define wrc_ams_pll_enb_10t(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x4000,14,wr_val) 272 #define rdc_ams_pll_enb_8t() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,2,15,__ERR) 273 #define wrc_ams_pll_enb_8t(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x2000,13,wr_val) 274 #define rdc_ams_pll_vco_range() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,3,9,__ERR) 275 #define wrc_ams_pll_vco_range(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x1fc0,6,wr_val) 276 #define rdc_ams_pll_en_8p5g_vco() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,10,15,__ERR) 277 #define wrc_ams_pll_en_8p5g_vco(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0020,5,wr_val) 278 #define rdc_ams_pll_spare_1_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,11,15,__ERR) 279 #define wrc_ams_pll_spare_1_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0010,4,wr_val) 280 #define rdc_ams_pll_curr_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b1,12,12,__ERR) 281 #define wrc_ams_pll_curr_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b1,0x000f,0,wr_val) 282 #define rdc_ams_pll_en_i4iqbuf() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,0,14,__ERR) 283 #define wrc_ams_pll_en_i4iqbuf(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0xc000,14,wr_val) 284 #define rdc_ams_pll_vcobuf_pon() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,2,12,__ERR) 285 #define wrc_ams_pll_vcobuf_pon(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0x3c00,10,wr_val) 286 #define rdc_ams_pll_clkvco_cal_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,6,15,__ERR) 287 #define wrc_ams_pll_clkvco_cal_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0200,9,wr_val) 288 #define rdc_ams_pll_en_cmos_refclk_ch_hiz() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,7,15,__ERR) 289 #define wrc_ams_pll_en_cmos_refclk_ch_hiz(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0100,8,wr_val) 290 #define rdc_ams_pll_calib_adj() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,8,13,__ERR) 291 #define wrc_ams_pll_calib_adj(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0x00e0,5,wr_val) 292 #define rdc_ams_pll_en_8p5g() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,11,15,__ERR) 293 #define wrc_ams_pll_en_8p5g(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0010,4,wr_val) 294 #define rdc_ams_pll_vco_pon() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b2,12,12,__ERR) 295 #define wrc_ams_pll_vco_pon(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b2,0x000f,0,wr_val) 296 #define rdc_ams_pll_en_mmd_halfrate() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,0,15,__ERR) 297 #define wrc_ams_pll_en_mmd_halfrate(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x8000,15,wr_val) 298 #define rdc_ams_pll_cp_bias() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,1,13,__ERR) 299 #define wrc_ams_pll_cp_bias(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x7000,12,wr_val) 300 #define rdc_ams_pll_spare_3_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,4,15,__ERR) 301 #define wrc_ams_pll_spare_3_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0800,11,wr_val) 302 #define rdc_ams_pll_ref_cmos_hz() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,5,15,__ERR) 303 #define wrc_ams_pll_ref_cmos_hz(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0400,10,wr_val) 304 #define rdc_ams_pll_ref_cml_pd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,6,15,__ERR) 305 #define wrc_ams_pll_ref_cml_pd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0200,9,wr_val) 306 #define rdc_ams_pll_clksel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,7,15,__ERR) 307 #define wrc_ams_pll_clksel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0100,8,wr_val) 308 #define rdc_ams_pll_en_rclk_refout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,8,15,__ERR) 309 #define wrc_ams_pll_en_rclk_refout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0080,7,wr_val) 310 #define rdc_ams_pll_en_cmos_refout_overwr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,9,15,__ERR) 311 #define wrc_ams_pll_en_cmos_refout_overwr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0040,6,wr_val) 312 #define rdc_ams_pll_en_cml_refout_overwr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,10,15,__ERR) 313 #define wrc_ams_pll_en_cml_refout_overwr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0020,5,wr_val) 314 #define rdc_ams_pll_en_test_frac_clk() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,11,15,__ERR) 315 #define wrc_ams_pll_en_test_frac_clk(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0010,4,wr_val) 316 #define rdc_ams_pll_enb_16t() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,12,15,__ERR) 317 #define wrc_ams_pll_enb_16t(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0008,3,wr_val) 318 #define rdc_ams_pll_band_iqbuf_ctr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b3,13,13,__ERR) 319 #define wrc_ams_pll_band_iqbuf_ctr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0007,0,wr_val) 320 #define rdc_ams_pll_test_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,1,13,__ERR) 321 #define wrc_ams_pll_test_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x7000,12,wr_val) 322 #define rdc_ams_pll_test_amp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,4,14,__ERR) 323 #define wrc_ams_pll_test_amp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0c00,10,wr_val) 324 #define rdc_ams_pll_vco_test_clk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,6,15,__ERR) 325 #define wrc_ams_pll_vco_test_clk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0200,9,wr_val) 326 #define rdc_ams_pll_bias_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,7,15,__ERR) 327 #define wrc_ams_pll_bias_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0100,8,wr_val) 328 #define rdc_ams_pll_spare4_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,8,15,__ERR) 329 #define wrc_ams_pll_spare4_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0080,7,wr_val) 330 #define rdc_ams_pll_bias_vdd_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,9,14,__ERR) 331 #define wrc_ams_pll_bias_vdd_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0060,5,wr_val) 332 #define rdc_ams_pll_spare4_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,11,15,__ERR) 333 #define wrc_ams_pll_spare4_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0010,4,wr_val) 334 #define rdc_ams_pll_cp_opamp_bias() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,12,14,__ERR) 335 #define wrc_ams_pll_cp_opamp_bias(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x000c,2,wr_val) 336 #define rdc_ams_pll_lc_refclk_adj_3_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b4,14,14,__ERR) 337 #define wrc_ams_pll_lc_refclk_adj_3_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0003,0,wr_val) 338 #define rdc_ams_pll_refdiv_test_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,3,13,__ERR) 339 #define wrc_ams_pll_refdiv_test_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x1c00,10,wr_val) 340 #define rdc_ams_pll_pwdb_extr_d2c() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,6,15,__ERR) 341 #define wrc_ams_pll_pwdb_extr_d2c(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0200,9,wr_val) 342 #define rdc_ams_pll_en_refout_div() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,7,15,__ERR) 343 #define wrc_ams_pll_en_refout_div(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0100,8,wr_val) 344 #define rdc_ams_pll_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,8,15,__ERR) 345 #define wrc_ams_pll_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0080,7,wr_val) 346 #define rdc_ams_pll_term_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,9,14,__ERR) 347 #define wrc_ams_pll_term_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0060,5,wr_val) 348 #define rdc_ams_pll_test_sel_overwrite() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,11,15,__ERR) 349 #define wrc_ams_pll_test_sel_overwrite(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0010,4,wr_val) 350 #define rdc_ams_pll_test_vc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,12,15,__ERR) 351 #define wrc_ams_pll_test_vc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0008,3,wr_val) 352 #define rdc_ams_pll_refout_div_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b5,13,13,__ERR) 353 #define wrc_ams_pll_refout_div_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0007,0,wr_val) 354 #define rdc_ams_pll_i_ndiv_frac_l() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,0,12,__ERR) 355 #define wrc_ams_pll_i_ndiv_frac_l(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0xf000,12,wr_val) 356 #define rdc_ams_pll_pfd_offset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,4,14,__ERR) 357 #define wrc_ams_pll_pfd_offset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0c00,10,wr_val) 358 #define rdc_ams_pll_spare6_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,6,15,__ERR) 359 #define wrc_ams_pll_spare6_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0200,9,wr_val) 360 #define rdc_ams_pll_pfd_offset_enlarge() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,7,15,__ERR) 361 #define wrc_ams_pll_pfd_offset_enlarge(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0100,8,wr_val) 362 #define rdc_ams_pll_vco_i_boost() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,8,14,__ERR) 363 #define wrc_ams_pll_vco_i_boost(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0x00c0,6,wr_val) 364 #define rdc_ams_pll_vco_gm_boost() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,10,14,__ERR) 365 #define wrc_ams_pll_vco_gm_boost(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0030,4,wr_val) 366 #define rdc_ams_pll_pon() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b6,12,12,__ERR) 367 #define wrc_ams_pll_pon(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b6,0x000f,0,wr_val) 368 #define rdc_ams_pll_i_ndiv_frac_h() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0b7,2,2,__ERR) 369 #define wrc_ams_pll_i_ndiv_frac_h(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd0b7,0x3fff,0,wr_val) 370 #define rdc_ams_pll_i_ndiv_dither_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b8,0,15,__ERR) 371 #define wrc_ams_pll_i_ndiv_dither_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b8,0x8000,15,wr_val) 372 #define rdc_ams_pll_i_pll_sdm_pwrdnb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b8,1,15,__ERR) 373 #define wrc_ams_pll_i_pll_sdm_pwrdnb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b8,0x4000,14,wr_val) 374 #define rdc_ams_pll_vcofb_div() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b8,2,14,__ERR) 375 #define wrc_ams_pll_vcofb_div(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b8,0x3000,12,wr_val) 376 #define rdc_ams_pll_cml_refclk_bias() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b8,4,14,__ERR) 377 #define wrc_ams_pll_cml_refclk_bias(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b8,0x0c00,10,wr_val) 378 #define rdc_ams_pll_i_ndiv_int() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0b8,6,6,__ERR) 379 #define wrc_ams_pll_i_ndiv_int(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd0b8,0x03ff,0,wr_val) 380 #define rdc_ams_pll_cml_refclk_adj() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,0,14,__ERR) 381 #define wrc_ams_pll_cml_refclk_adj(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0xc000,14,wr_val) 382 #define rdc_ams_pll_bias_iq_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,2,13,__ERR) 383 #define wrc_ams_pll_bias_iq_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0x3800,11,wr_val) 384 #define rdc_ams_pll_bias_div_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,5,13,__ERR) 385 #define wrc_ams_pll_bias_div_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0700,8,wr_val) 386 #define rdc_ams_pll_vco_supply_adj() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,8,15,__ERR) 387 #define wrc_ams_pll_vco_supply_adj(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0080,7,wr_val) 388 #define rdc_ams_pll_sel_fp3cap() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,9,12,__ERR) 389 #define wrc_ams_pll_sel_fp3cap(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0078,3,wr_val) 390 #define rdc_ams_pll_i_pll_frac_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,13,14,__ERR) 391 #define wrc_ams_pll_i_pll_frac_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0006,1,wr_val) 392 #define rdc_ams_pll_mmd_resetb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0b9,15,15,__ERR) 393 #define wrc_ams_pll_mmd_resetb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0001,0,wr_val) 394 #define rdc_ams_pll_tx_clkmaster_ovrd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ba,5,15,__ERR) 395 #define wrc_ams_pll_tx_clkmaster_ovrd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0ba,0x0400,10,wr_val) 396 #define rdc_ams_pll_tx_clkmaster_ctrl_a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ba,6,14,__ERR) 397 #define wrc_ams_pll_tx_clkmaster_ctrl_a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0ba,0x0300,8,wr_val) 398 #define rdc_ams_pll_tx_clkmaster_ctrl_b() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ba,8,14,__ERR) 399 #define wrc_ams_pll_tx_clkmaster_ctrl_b(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0ba,0x00c0,6,wr_val) 400 #define rdc_ams_pll_refclk_in_bias() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ba,10,10,__ERR) 401 #define wrc_ams_pll_refclk_in_bias(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0ba,0x003f,0,wr_val) 402 #define rdc_ams_pll_refclk_term_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0be,12,15,__ERR) 403 #define wrc_ams_pll_refclk_term_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0be,0x0008,3,wr_val) 404 #define rdc_ams_pll_refclk_div_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0be,13,15,__ERR) 405 #define wrc_ams_pll_refclk_div_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0be,0x0004,2,wr_val) 406 #define rdc_ams_pll_refclk_div2_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0be,14,15,__ERR) 407 #define wrc_ams_pll_refclk_div2_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0be,0x0002,1,wr_val) 408 #define rdc_ams_pll_refclk_div4_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0be,15,15,__ERR) 409 #define wrc_ams_pll_refclk_div4_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0be,0x0001,0,wr_val) 410 #define rdc_ams_pll_afe_rev_id() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0bf,12,12,__ERR) 411 #define rdc_tx_lane_addr_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd150,3,11,__ERR) 412 #define wrc_tx_lane_addr_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd150,0x1f00,8,wr_val) 413 #define rdc_rx_lane_addr_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd150,11,11,__ERR) 414 #define wrc_rx_lane_addr_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd150,0x001f,0,wr_val) 415 #define rdc_tx_lane_addr_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd151,3,11,__ERR) 416 #define wrc_tx_lane_addr_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd151,0x1f00,8,wr_val) 417 #define rdc_rx_lane_addr_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd151,11,11,__ERR) 418 #define wrc_rx_lane_addr_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd151,0x001f,0,wr_val) 419 #define rdc_tx_lane_addr_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd152,3,11,__ERR) 420 #define wrc_tx_lane_addr_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd152,0x1f00,8,wr_val) 421 #define rdc_rx_lane_addr_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd152,11,11,__ERR) 422 #define wrc_rx_lane_addr_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd152,0x001f,0,wr_val) 423 #define rdc_tx_lane_addr_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd153,3,11,__ERR) 424 #define wrc_tx_lane_addr_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd153,0x1f00,8,wr_val) 425 #define rdc_rx_lane_addr_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd153,11,11,__ERR) 426 #define wrc_rx_lane_addr_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd153,0x001f,0,wr_val) 427 #define rdc_revid_rev_letter() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f0,0,14,__ERR) 428 #define rdc_revid_rev_number() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f0,2,13,__ERR) 429 #define rdc_revid_bonding() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f0,5,14,__ERR) 430 #define rdc_revid_process() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f0,7,13,__ERR) 431 #define rdc_revid_model() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f0,10,10,__ERR) 432 #define rdc_revid_multiplicity() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,0,12,__ERR) 433 #define rdc_revid_mdio() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,10,15,__ERR) 434 #define rdc_revid_micro() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,11,15,__ERR) 435 #define rdc_revid_cl72() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,12,15,__ERR) 436 #define rdc_revid_pir() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,13,15,__ERR) 437 #define rdc_revid_llp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,14,15,__ERR) 438 #define rdc_revid_eee() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fa,15,15,__ERR) 439 #define rdc_revid2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0fe,12,12,__ERR) 440 #define rdc_ana_txclk_reset_enable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f1,0,15,__ERR) 441 #define wrc_ana_txclk_reset_enable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f1,0x8000,15,wr_val) 442 #define rdc_core_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f1,15,15,__ERR) 443 #define wrc_core_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f1,0x0001,0,wr_val) 444 #define rdc_disable_ack_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,0,15,__ERR) 445 #define wrc_disable_ack_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x8000,15,wr_val) 446 #define rdc_pmd_vcoclk16_vld_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,5,15,__ERR) 447 #define wrc_pmd_vcoclk16_vld_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0400,10,wr_val) 448 #define rdc_pmd_vcoclk16_vld_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,6,15,__ERR) 449 #define wrc_pmd_vcoclk16_vld_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0200,9,wr_val) 450 #define rdc_vcoclk16_s_comclk_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,7,15,__ERR) 451 #define wrc_vcoclk16_s_comclk_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0100,8,wr_val) 452 #define rdc_vcoclk16_s_comclk_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,8,15,__ERR) 453 #define wrc_vcoclk16_s_comclk_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0080,7,wr_val) 454 #define rdc_pmd_mdio_trans_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,10,15,__ERR) 455 #define wrc_pmd_mdio_trans_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0020,5,wr_val) 456 #define rdc_sup_rst_seq_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,11,15,__ERR) 457 #define wrc_sup_rst_seq_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0010,4,wr_val) 458 #define rdc_sup_rst_seq_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,12,15,__ERR) 459 #define wrc_sup_rst_seq_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0008,3,wr_val) 460 #define rdc_pmd_core_dp_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f2,14,15,__ERR) 461 #define wrc_pmd_core_dp_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0002,1,wr_val) 462 #define rdc_maskdata() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f3,__ERR) 463 #define wrc_maskdata(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f3,wr_val) 464 #define rdc_uc_active() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f4,0,15,__ERR) 465 #define wrc_uc_active(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f4,0x8000,15,wr_val) 466 #define rdc_afe_s_pll_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f4,1,15,__ERR) 467 #define wrc_afe_s_pll_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f4,0x4000,14,wr_val) 468 #define rdc_core_dp_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f4,2,15,__ERR) 469 #define wrc_core_dp_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f4,0x2000,13,wr_val) 470 #define rdc_maskdata_bus_assign() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f4,4,14,__ERR) 471 #define wrc_maskdata_bus_assign(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f4,0x0c00,10,wr_val) 472 #define rdc_heartbeat_count_1us() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0f4,6,6,__ERR) 473 #define wrc_heartbeat_count_1us(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd0f4,0x03ff,0,wr_val) 474 #define rdc_uc_ack_core_dp_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f5,14,15,__ERR) 475 #define wrc_uc_ack_core_dp_reset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f5,0x0002,1,wr_val) 476 #define rdc_uc_ack_core_cfg_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f5,15,15,__ERR) 477 #define wrc_uc_ack_core_cfg_done(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f5,0x0001,0,wr_val) 478 #define rdc_lane_reset_released() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f8,1,15,__ERR) 479 #define rdc_lane_reset_released_index() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f8,3,11,__ERR) 480 #define rdc_tx_lane_reset_released() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f8,0,15,__ERR) 481 #define rdc_tx_lane_reset_released_index() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f8,8,11,__ERR) 482 #define rdc_core_dp_reset_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f8,13,13,__ERR) 483 #define rdc_core_reg_reset_occurred() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f6,15,15,__ERR) 484 #define wrc_core_reg_reset_occurred(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f6,0x0001,0,wr_val) 485 #define rdc_rst_seq_dis_flt_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f7,0,14,__ERR) 486 #define wrc_rst_seq_dis_flt_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f7,0xc000,14,wr_val) 487 #define rdc_pwrdn_seq_timer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f7,4,13,__ERR) 488 #define wrc_pwrdn_seq_timer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0e00,9,wr_val) 489 #define rdc_dsc_pwrdn_seq_timer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f7,7,13,__ERR) 490 #define wrc_dsc_pwrdn_seq_timer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f7,0x01c0,6,wr_val) 491 #define rdc_dsc_rst_seq_timer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f7,10,13,__ERR) 492 #define wrc_dsc_rst_seq_timer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0038,3,wr_val) 493 #define rdc_rst_seq_timer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0f7,13,13,__ERR) 494 #define wrc_rst_seq_timer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0007,0,wr_val) 495 #define rdc_pmd_core_mode() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f9,__ERR) 496 #define rd_cdr_integ_reg() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd005,0,0,__ERR) 497 #define rd_cdr_phase_err() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd006,10,10,__ERR) 498 #define rd_cnt_bin_p1_dreg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd007,1,9,__ERR) 499 #define rd_cnt_bin_d_dreg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd007,9,9,__ERR) 500 #define rd_cnt_bin_m1_preg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd008,1,9,__ERR) 501 #define rd_cnt_bin_p1_preg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd008,9,9,__ERR) 502 #define rd_cnt_bin_d_mreg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd009,1,9,__ERR) 503 #define rd_cnt_bin_m1_mreg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd009,9,9,__ERR) 504 #define rd_cnt_d_minus_p1() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd00a,0,8,__ERR) 505 #define rd_cnt_d_minus_m1() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd00a,8,8,__ERR) 506 #define rd_cdr_lm_thr_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,5,13,__ERR) 507 #define wr_cdr_lm_thr_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0700,8,wr_val) 508 #define rd_cdr_freq_override_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,8,15,__ERR) 509 #define wr_cdr_freq_override_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0080,7,wr_val) 510 #define rd_cdr_integ_sat_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,9,15,__ERR) 511 #define wr_cdr_integ_sat_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0040,6,wr_val) 512 #define rd_cdr_phase_err_frz() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,10,15,__ERR) 513 #define wr_cdr_phase_err_frz(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0020,5,wr_val) 514 #define rd_cdr_integ_reg_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,11,15,__ERR) 515 #define wr_cdr_integ_reg_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0010,4,wr_val) 516 #define rd_cdr_freq_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,13,15,__ERR) 517 #define wr_cdr_freq_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0004,2,wr_val) 518 #define rd_br_pd_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,14,15,__ERR) 519 #define wr_br_pd_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0002,1,wr_val) 520 #define rd_cdr_phase_sat_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd001,15,15,__ERR) 521 #define wr_cdr_phase_sat_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd001,0x0001,0,wr_val) 522 #define rd_cdr_freq_override_val() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd002,0,1,__ERR) 523 #define wr_cdr_freq_override_val(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd002,0xfffe,1,wr_val) 524 #define rd_dfe_vga_unfreeze() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd002,15,15,__ERR) 525 #define wr_dfe_vga_unfreeze(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd002,0x0001,0,wr_val) 526 #define rd_osx2p_pherr_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd003,6,14,__ERR) 527 #define wr_osx2p_pherr_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd003,0x0300,8,wr_val) 528 #define rd_pattern_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd003,8,12,__ERR) 529 #define wr_pattern_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd003,0x00f0,4,wr_val) 530 #define rd_phase_err_offset_mult_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd003,14,15,__ERR) 531 #define wr_phase_err_offset_mult_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd003,0x0002,1,wr_val) 532 #define rd_cdr_zero_polarity() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd003,15,15,__ERR) 533 #define wr_cdr_zero_polarity(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd003,0x0001,0,wr_val) 534 #define rd_edge_count_refless_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,0,15,__ERR) 535 #define wr_edge_count_refless_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x8000,15,wr_val) 536 #define rd_trnsum_eye_closure_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,2,14,__ERR) 537 #define wr_trnsum_eye_closure_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x3000,12,wr_val) 538 #define rd_swap_lms_data() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,4,15,__ERR) 539 #define wr_swap_lms_data(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x0800,11,wr_val) 540 #define rd_swap_lms_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,5,15,__ERR) 541 #define wr_swap_lms_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x0400,10,wr_val) 542 #define rd_trnsum_prbs_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,9,14,__ERR) 543 #define wr_trnsum_prbs_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x0060,5,wr_val) 544 #define rd_trnsum_eye_close_prev_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,11,15,__ERR) 545 #define wr_trnsum_eye_close_prev_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x0010,4,wr_val) 546 #define rd_trnsum_pattern_match_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,12,14,__ERR) 547 #define wr_trnsum_pattern_match_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x000c,2,wr_val) 548 #define rd_trnsum_disable_sm_clear() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,14,15,__ERR) 549 #define wr_trnsum_disable_sm_clear(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x0002,1,wr_val) 550 #define rd_trnsum_clr_sc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00b,15,15,__ERR) 551 #define wr_trnsum_clr_sc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00b,0x0001,0,wr_val) 552 #define rd_rx_pi_manual_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd004,0,15,__ERR) 553 #define wr_rx_pi_manual_reset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd004,0x8000,15,wr_val) 554 #define rd_rx_pi_slicers_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd004,1,13,__ERR) 555 #define wr_rx_pi_slicers_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd004,0x7000,12,wr_val) 556 #define rd_rx_pi_manual_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd004,4,15,__ERR) 557 #define wr_rx_pi_manual_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd004,0x0800,11,wr_val) 558 #define rd_rx_pi_phase_step_dir() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd004,5,15,__ERR) 559 #define wr_rx_pi_phase_step_dir(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd004,0x0400,10,wr_val) 560 #define rd_rx_pi_manual_strobe() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd004,6,15,__ERR) 561 #define wr_rx_pi_manual_strobe(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd004,0x0200,9,wr_val) 562 #define rd_rx_pi_phase_step_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd004,9,9,__ERR) 563 #define wr_rx_pi_phase_step_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd004,0x007f,0,wr_val) 564 #define rd_uc_dsc_supp_info() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00d,0,8,__ERR) 565 #define wr_uc_dsc_supp_info(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00d,0xff00,8,wr_val) 566 #define rd_uc_dsc_ready_for_cmd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00d,8,15,__ERR) 567 #define wr_uc_dsc_ready_for_cmd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00d,0x0080,7,wr_val) 568 #define rd_uc_dsc_error_found() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00d,9,15,__ERR) 569 #define wr_uc_dsc_error_found(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00d,0x0040,6,wr_val) 570 #define rd_uc_dsc_gp_uc_req() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd00d,10,10,__ERR) 571 #define wr_uc_dsc_gp_uc_req(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd00d,0x003f,0,wr_val) 572 #define rd_uc_dsc_data() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd00e,__ERR) 573 #define wr_uc_dsc_data(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd00e,wr_val) 574 #define rd_uc_facq_ack() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,15,15,__ERR) 575 #define wr_uc_facq_ack(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0001,0,wr_val) 576 #define rd_eee_mode_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,14,15,__ERR) 577 #define wr_eee_mode_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0002,1,wr_val) 578 #define rd_eee_quiet_rx_afe_pwrdwn_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,13,15,__ERR) 579 #define wr_eee_quiet_rx_afe_pwrdwn_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0004,2,wr_val) 580 #define rd_ignore_rx_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,12,15,__ERR) 581 #define wr_ignore_rx_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0008,3,wr_val) 582 #define rd_cl72_timer_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,11,15,__ERR) 583 #define wr_cl72_timer_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0010,4,wr_val) 584 #define rd_uc_tune_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,10,15,__ERR) 585 #define wr_uc_tune_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0020,5,wr_val) 586 #define rd_hw_tune_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,9,15,__ERR) 587 #define wr_hw_tune_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0040,6,wr_val) 588 #define rd_uc_trnsum_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,8,15,__ERR) 589 #define wr_uc_trnsum_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0080,7,wr_val) 590 #define rd_eee_measure_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,7,15,__ERR) 591 #define wr_eee_measure_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0100,8,wr_val) 592 #define rd_slicer_cal_done_clear() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,6,15,__ERR) 593 #define wr_slicer_cal_done_clear(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0200,9,wr_val) 594 #define rd_slicer_cal_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,5,15,__ERR) 595 #define wr_slicer_cal_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0400,10,wr_val) 596 #define rd_uc_ack_dsc_eee_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,4,15,__ERR) 597 #define wr_uc_ack_dsc_eee_done(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x0800,11,wr_val) 598 #define rd_uc_ack_dsc_restart() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,2,15,__ERR) 599 #define wr_uc_ack_dsc_restart(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x2000,13,wr_val) 600 #define rd_uc_ack_dsc_config() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,1,15,__ERR) 601 #define wr_uc_ack_dsc_config(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x4000,14,wr_val) 602 #define rd_set_meas_incomplete() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd010,0,15,__ERR) 603 #define wr_set_meas_incomplete(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd010,0x8000,15,wr_val) 604 #define rd_rx_dsc_lock_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,15,15,__ERR) 605 #define wr_rx_dsc_lock_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0001,0,wr_val) 606 #define rd_rx_dsc_lock_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,14,15,__ERR) 607 #define wr_rx_dsc_lock_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0002,1,wr_val) 608 #define rd_dsc_clr_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,13,15,__ERR) 609 #define wr_dsc_clr_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0004,2,wr_val) 610 #define rd_dsc_clr_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,12,15,__ERR) 611 #define wr_dsc_clr_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0008,3,wr_val) 612 #define rd_trnsum_frz_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,11,15,__ERR) 613 #define wr_trnsum_frz_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0010,4,wr_val) 614 #define rd_trnsum_frz_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,10,15,__ERR) 615 #define wr_trnsum_frz_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0020,5,wr_val) 616 #define rd_timer_done_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,9,15,__ERR) 617 #define wr_timer_done_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0040,6,wr_val) 618 #define rd_timer_done_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,8,15,__ERR) 619 #define wr_timer_done_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0080,7,wr_val) 620 #define rd_freq_upd_en_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,7,15,__ERR) 621 #define wr_freq_upd_en_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0100,8,wr_val) 622 #define rd_freq_upd_en_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,6,15,__ERR) 623 #define wr_freq_upd_en_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0200,9,wr_val) 624 #define rd_cdr_frz_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,5,15,__ERR) 625 #define wr_cdr_frz_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0400,10,wr_val) 626 #define rd_cdr_frz_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,4,15,__ERR) 627 #define wr_cdr_frz_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x0800,11,wr_val) 628 #define rd_trnsum_clr_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,3,15,__ERR) 629 #define wr_trnsum_clr_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x1000,12,wr_val) 630 #define rd_trnsum_clr_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd011,2,15,__ERR) 631 #define wr_trnsum_clr_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd011,0x2000,13,wr_val) 632 #define rd_eee_lfsr_cnt() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd012,3,3,__ERR) 633 #define wr_eee_lfsr_cnt(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd012,0x1fff,0,wr_val) 634 #define rd_measure_lfsr_cnt() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd013,3,3,__ERR) 635 #define wr_measure_lfsr_cnt(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd013,0x1fff,0,wr_val) 636 #define rd_acq_cdr_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd014,11,11,__ERR) 637 #define wr_acq_cdr_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd014,0x001f,0,wr_val) 638 #define rd_cdr_settle_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd014,6,11,__ERR) 639 #define wr_cdr_settle_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd014,0x03e0,5,wr_val) 640 #define rd_hw_tune_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd014,1,11,__ERR) 641 #define wr_hw_tune_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd014,0x7c00,10,wr_val) 642 #define rd_measure_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd015,11,11,__ERR) 643 #define wr_measure_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd015,0x001f,0,wr_val) 644 #define rd_eee_acq_cdr_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd015,6,11,__ERR) 645 #define wr_eee_acq_cdr_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd015,0x03e0,5,wr_val) 646 #define rd_eee_cdr_settle_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd015,1,11,__ERR) 647 #define wr_eee_cdr_settle_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd015,0x7c00,10,wr_val) 648 #define rd_eee_hw_tune_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd016,11,11,__ERR) 649 #define wr_eee_hw_tune_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd016,0x001f,0,wr_val) 650 #define rd_eee_ana_pwr_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd016,1,11,__ERR) 651 #define wr_eee_ana_pwr_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd016,0x7c00,10,wr_val) 652 #define rd_slicer_cal_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd016,6,11,__ERR) 653 #define wr_slicer_cal_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd016,0x03e0,5,wr_val) 654 #define rd_cdr_bwsel_integ_acqcdr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd017,12,12,__ERR) 655 #define wr_cdr_bwsel_integ_acqcdr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd017,0x000f,0,wr_val) 656 #define rd_cdr_bwsel_integ_eee_acqcdr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd017,8,12,__ERR) 657 #define wr_cdr_bwsel_integ_eee_acqcdr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd017,0x00f0,4,wr_val) 658 #define rd_cdr_bwsel_integ_norm() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd017,4,12,__ERR) 659 #define wr_cdr_bwsel_integ_norm(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd017,0x0f00,8,wr_val) 660 #define rd_cdr_bwsel_prop_acqcdr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd017,2,14,__ERR) 661 #define wr_cdr_bwsel_prop_acqcdr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd017,0x3000,12,wr_val) 662 #define rd_cdr_bwsel_prop_norm() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd017,0,14,__ERR) 663 #define wr_cdr_bwsel_prop_norm(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd017,0xc000,14,wr_val) 664 #define rd_phase_err_offset() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd018,12,12,__ERR) 665 #define wr_phase_err_offset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd018,0x000f,0,wr_val) 666 #define rd_eee_phase_err_offset() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd018,8,12,__ERR) 667 #define wr_eee_phase_err_offset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd018,0x00f0,4,wr_val) 668 #define rd_phase_err_offset_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd018,6,14,__ERR) 669 #define wr_phase_err_offset_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd018,0x0300,8,wr_val) 670 #define rd_eee_phase_err_offset_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd018,4,14,__ERR) 671 #define wr_eee_phase_err_offset_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd018,0x0c00,10,wr_val) 672 #define rd_cdr_bwsel_prop_eee_acqcdr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd018,0,14,__ERR) 673 #define wr_cdr_bwsel_prop_eee_acqcdr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd018,0xc000,14,wr_val) 674 #define rd_dcoff_cal_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd019,1,11,__ERR) 675 #define wr_dcoff_cal_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd019,0x7c00,10,wr_val) 676 #define rd_rx_restart_pmd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd019,15,15,__ERR) 677 #define wr_rx_restart_pmd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd019,0x0001,0,wr_val) 678 #define rd_rx_restart_pmd_hold() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd019,14,15,__ERR) 679 #define wr_rx_restart_pmd_hold(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd019,0x0002,1,wr_val) 680 #define rd_dsc_state_one_hot_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd01b,__ERR) 681 #define rd_dsc_state_one_hot_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01c,14,14,__ERR) 682 #define rd_restart_pi_ext_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01d,15,15,__ERR) 683 #define rd_restart_sigdet() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01d,14,15,__ERR) 684 #define rd_restart_pmd_restart() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01d,13,15,__ERR) 685 #define rd_eee_quiet_from_eee_states() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01d,12,15,__ERR) 686 #define rd_dsc_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01e,0,11,__ERR) 687 #define rd_dsc_sm_ready_for_cmd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01e,8,15,__ERR) 688 #define rd_cdr_lm_outoflock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01e,9,15,__ERR) 689 #define rd_dsc_sm_scratch() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01e,5,13,__ERR) 690 #define rd_dsc_sm_gp_uc_req() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01e,10,10,__ERR) 691 #define rd_eee_measure_cnt() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd01a,0,7,__ERR) 692 #define rd_slicer_cal_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01a,13,15,__ERR) 693 #define rd_meas_incomplete() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01a,14,15,__ERR) 694 #define rd_rx_dsc_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd01a,15,15,__ERR) 695 #define rd_dfe_1_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,0,15,__ERR) 696 #define wr_dfe_1_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x8000,15,wr_val) 697 #define rd_dfe_1_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,1,14,__ERR) 698 #define wr_dfe_1_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x6000,13,wr_val) 699 #define rd_dfe_1_gradient_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,3,15,__ERR) 700 #define wr_dfe_1_gradient_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x1000,12,wr_val) 701 #define rd_dfe_1_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,4,14,__ERR) 702 #define wr_dfe_1_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x0c00,10,wr_val) 703 #define rd_dfe_1_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,6,15,__ERR) 704 #define wr_dfe_1_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x0200,9,wr_val) 705 #define rd_dfe_1_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,7,15,__ERR) 706 #define wr_dfe_1_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x0100,8,wr_val) 707 #define rd_dfe_1_cmn_only() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,14,15,__ERR) 708 #define wr_dfe_1_cmn_only(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x0002,1,wr_val) 709 #define rd_dfe_1_acc_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd021,15,15,__ERR) 710 #define wr_dfe_1_acc_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd021,0x0001,0,wr_val) 711 #define rd_dfe_2_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,0,15,__ERR) 712 #define wr_dfe_2_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x8000,15,wr_val) 713 #define rd_dfe_2_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,1,14,__ERR) 714 #define wr_dfe_2_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x6000,13,wr_val) 715 #define rd_dfe_2_gradient_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,3,15,__ERR) 716 #define wr_dfe_2_gradient_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x1000,12,wr_val) 717 #define rd_dfe_2_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,4,14,__ERR) 718 #define wr_dfe_2_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x0c00,10,wr_val) 719 #define rd_dfe_2_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,6,15,__ERR) 720 #define wr_dfe_2_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x0200,9,wr_val) 721 #define rd_dfe_2_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,7,15,__ERR) 722 #define wr_dfe_2_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x0100,8,wr_val) 723 #define rd_dfe_2_cmn_only() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,14,15,__ERR) 724 #define wr_dfe_2_cmn_only(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x0002,1,wr_val) 725 #define rd_dfe_2_acc_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd022,15,15,__ERR) 726 #define wr_dfe_2_acc_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd022,0x0001,0,wr_val) 727 #define rd_dfe_3_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,0,15,__ERR) 728 #define wr_dfe_3_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x8000,15,wr_val) 729 #define rd_dfe_3_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,1,14,__ERR) 730 #define wr_dfe_3_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x6000,13,wr_val) 731 #define rd_dfe_3_gradient_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,3,15,__ERR) 732 #define wr_dfe_3_gradient_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x1000,12,wr_val) 733 #define rd_dfe_3_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,4,14,__ERR) 734 #define wr_dfe_3_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x0c00,10,wr_val) 735 #define rd_dfe_3_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,6,15,__ERR) 736 #define wr_dfe_3_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x0200,9,wr_val) 737 #define rd_dfe_3_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,7,15,__ERR) 738 #define wr_dfe_3_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x0100,8,wr_val) 739 #define rd_dfe_3_acc_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd023,15,15,__ERR) 740 #define wr_dfe_3_acc_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd023,0x0001,0,wr_val) 741 #define rd_dfe_4_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,0,15,__ERR) 742 #define wr_dfe_4_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x8000,15,wr_val) 743 #define rd_dfe_4_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,1,14,__ERR) 744 #define wr_dfe_4_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x6000,13,wr_val) 745 #define rd_dfe_4_gradient_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,3,15,__ERR) 746 #define wr_dfe_4_gradient_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x1000,12,wr_val) 747 #define rd_dfe_4_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,4,14,__ERR) 748 #define wr_dfe_4_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x0c00,10,wr_val) 749 #define rd_dfe_4_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,6,15,__ERR) 750 #define wr_dfe_4_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x0200,9,wr_val) 751 #define rd_dfe_4_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,7,15,__ERR) 752 #define wr_dfe_4_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x0100,8,wr_val) 753 #define rd_dfe_4_acc_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd024,15,15,__ERR) 754 #define wr_dfe_4_acc_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd024,0x0001,0,wr_val) 755 #define rd_dfe_5_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,0,15,__ERR) 756 #define wr_dfe_5_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x8000,15,wr_val) 757 #define rd_dfe_5_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,1,14,__ERR) 758 #define wr_dfe_5_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x6000,13,wr_val) 759 #define rd_dfe_5_gradient_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,3,15,__ERR) 760 #define wr_dfe_5_gradient_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x1000,12,wr_val) 761 #define rd_dfe_5_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,4,14,__ERR) 762 #define wr_dfe_5_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x0c00,10,wr_val) 763 #define rd_dfe_5_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,6,15,__ERR) 764 #define wr_dfe_5_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x0200,9,wr_val) 765 #define rd_dfe_5_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,7,15,__ERR) 766 #define wr_dfe_5_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x0100,8,wr_val) 767 #define rd_dfe_5_acc_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd025,15,15,__ERR) 768 #define wr_dfe_5_acc_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd025,0x0001,0,wr_val) 769 #define rd_dfe_pattern_bit_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd026,2,10,__ERR) 770 #define wr_dfe_pattern_bit_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd026,0x3f00,8,wr_val) 771 #define rd_dfe_pattern() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd026,10,10,__ERR) 772 #define wr_dfe_pattern(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd026,0x003f,0,wr_val) 773 #define rd_dfe_acc_hys_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,0,15,__ERR) 774 #define wr_dfe_acc_hys_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x8000,15,wr_val) 775 #define rd_dfe_allow_simult() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,1,15,__ERR) 776 #define wr_dfe_allow_simult(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x4000,14,wr_val) 777 #define rd_dfe_update_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,2,15,__ERR) 778 #define wr_dfe_update_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x2000,13,wr_val) 779 #define rd_dfe_eye_closure_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,8,14,__ERR) 780 #define wr_dfe_eye_closure_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x00c0,6,wr_val) 781 #define rd_dfe_hw_eye_closure_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,10,15,__ERR) 782 #define wr_dfe_hw_eye_closure_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x0020,5,wr_val) 783 #define rd_dfe_leaky_lms_upd_dur() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,11,12,__ERR) 784 #define wr_dfe_leaky_lms_upd_dur(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x001e,1,wr_val) 785 #define rd_dfe_leaky_lms_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd020,15,15,__ERR) 786 #define wr_dfe_leaky_lms_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd020,0x0001,0,wr_val) 787 #define rd_hwtune_ovr_write_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02b,0,15,__ERR) 788 #define wr_hwtune_ovr_write_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02b,0x8000,15,wr_val) 789 #define rd_hwtune_ovr_write_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02b,2,11,__ERR) 790 #define wr_hwtune_ovr_write_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02b,0x3e00,9,wr_val) 791 #define rd_hwtune_ovr_write_val() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd02b,7,7,__ERR) 792 #define wr_hwtune_ovr_write_val(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd02b,0x01ff,0,wr_val) 793 #define rd_vga_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,0,15,__ERR) 794 #define wr_vga_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x8000,15,wr_val) 795 #define rd_vga_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,1,14,__ERR) 796 #define wr_vga_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x6000,13,wr_val) 797 #define rd_vga_p1_gradient_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,3,15,__ERR) 798 #define wr_vga_p1_gradient_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x1000,12,wr_val) 799 #define rd_vga_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,4,14,__ERR) 800 #define wr_vga_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x0c00,10,wr_val) 801 #define rd_vga_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,6,15,__ERR) 802 #define wr_vga_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x0200,9,wr_val) 803 #define rd_vga_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,7,15,__ERR) 804 #define wr_vga_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x0100,8,wr_val) 805 #define rd_vga_update_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,8,14,__ERR) 806 #define wr_vga_update_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x00c0,6,wr_val) 807 #define rd_vga_affected_by_dfe1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,11,15,__ERR) 808 #define wr_vga_affected_by_dfe1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x0010,4,wr_val) 809 #define rd_vga_update_style() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,12,14,__ERR) 810 #define wr_vga_update_style(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x000c,2,wr_val) 811 #define rd_vga_acc_hys_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,14,15,__ERR) 812 #define wr_vga_acc_hys_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x0002,1,wr_val) 813 #define rd_vga_p1_acc_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02c,15,15,__ERR) 814 #define wr_vga_p1_acc_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02c,0x0001,0,wr_val) 815 #define rd_p1_eyediag_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02d,0,15,__ERR) 816 #define wr_p1_eyediag_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02d,0x8000,15,wr_val) 817 #define rd_vga_pattern_bit_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02d,8,12,__ERR) 818 #define wr_vga_pattern_bit_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02d,0x00f0,4,wr_val) 819 #define rd_vga_pattern() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02d,12,12,__ERR) 820 #define wr_vga_pattern(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02d,0x000f,0,wr_val) 821 #define rd_p1_hwtune_max() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd02e,0,10,__ERR) 822 #define wr_p1_hwtune_max(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02e,0xfc00,10,wr_val) 823 #define rd_p1_off_3levelq_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02e,7,15,__ERR) 824 #define wr_p1_off_3levelq_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02e,0x0100,8,wr_val) 825 #define rd_p1_offset_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02e,8,15,__ERR) 826 #define wr_p1_offset_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02e,0x0080,7,wr_val) 827 #define rd_p1_offset() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd02e,9,9,__ERR) 828 #define wr_p1_offset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02e,0x007f,0,wr_val) 829 #define rd_p1_hwtune_min() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd027,0,10,__ERR) 830 #define wr_p1_hwtune_min(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd027,0xfc00,10,wr_val) 831 #define rd_vga_op_short_norm() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd027,8,15,__ERR) 832 #define wr_vga_op_short_norm(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd027,0x0080,7,wr_val) 833 #define rd_vga_op_short_offcal() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd027,9,15,__ERR) 834 #define wr_vga_op_short_offcal(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd027,0x0040,6,wr_val) 835 #define rd_vga_hwtune_min() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd027,10,10,__ERR) 836 #define wr_vga_hwtune_min(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd027,0x003f,0,wr_val) 837 #define rd_hw_slicer_offset_grad_inv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,8,15,__ERR) 838 #define wr_hw_slicer_offset_grad_inv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x0080,7,wr_val) 839 #define rd_hw_slicer_offset_inv_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,9,15,__ERR) 840 #define wr_hw_slicer_offset_inv_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x0040,6,wr_val) 841 #define rd_hw_slicer_offset_inv_m1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,10,15,__ERR) 842 #define wr_hw_slicer_offset_inv_m1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x0020,5,wr_val) 843 #define rd_hw_slicer_offset_inv_data() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,11,15,__ERR) 844 #define wr_hw_slicer_offset_inv_data(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x0010,4,wr_val) 845 #define rd_hw_slicer_offset_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,12,14,__ERR) 846 #define wr_hw_slicer_offset_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x000c,2,wr_val) 847 #define rd_hw_slicer_offset_hys_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,14,15,__ERR) 848 #define wr_hw_slicer_offset_hys_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x0002,1,wr_val) 849 #define rd_hw_slicer_offset_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd02a,15,15,__ERR) 850 #define wr_hw_slicer_offset_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd02a,0x0001,0,wr_val) 851 #define rd_dc_offset_pattern_bit_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,0,12,__ERR) 852 #define wr_dc_offset_pattern_bit_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0xf000,12,wr_val) 853 #define rd_dc_offset_pattern() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,4,12,__ERR) 854 #define wr_dc_offset_pattern(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x0f00,8,wr_val) 855 #define rd_hw_dc_offset_grad_inv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,9,15,__ERR) 856 #define wr_hw_dc_offset_grad_inv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x0040,6,wr_val) 857 #define rd_dc_offset_pattern_inv_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,10,15,__ERR) 858 #define wr_dc_offset_pattern_inv_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x0020,5,wr_val) 859 #define rd_dc_offset_inv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,11,15,__ERR) 860 #define wr_dc_offset_inv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x0010,4,wr_val) 861 #define rd_hw_dc_offset_err_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,12,14,__ERR) 862 #define wr_hw_dc_offset_err_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x000c,2,wr_val) 863 #define rd_hw_dc_offset_hys_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,14,15,__ERR) 864 #define wr_hw_dc_offset_hys_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x0002,1,wr_val) 865 #define rd_dc_offset_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd029,15,15,__ERR) 866 #define wr_dc_offset_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd029,0x0001,0,wr_val) 867 #define rd_trnsum_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,0,15,__ERR) 868 #define wr_trnsum_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x8000,15,wr_val) 869 #define rd_trnsum_err_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,1,13,__ERR) 870 #define wr_trnsum_err_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x7000,12,wr_val) 871 #define rd_trnsum_random_tapsel_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,4,15,__ERR) 872 #define wr_trnsum_random_tapsel_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x0800,11,wr_val) 873 #define rd_trnsum_inv_pattern_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,5,15,__ERR) 874 #define wr_trnsum_inv_pattern_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x0400,10,wr_val) 875 #define rd_trnsum_pattern_full_check_off() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,6,15,__ERR) 876 #define wr_trnsum_pattern_full_check_off(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x0200,9,wr_val) 877 #define rd_trnsum_edge_pattern_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,7,15,__ERR) 878 #define wr_trnsum_edge_pattern_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x0100,8,wr_val) 879 #define rd_trnsum_gain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,8,14,__ERR) 880 #define wr_trnsum_gain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x00c0,6,wr_val) 881 #define rd_trnsum_eye_closure_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,10,15,__ERR) 882 #define wr_trnsum_eye_closure_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x0020,5,wr_val) 883 #define rd_cdr_qphase_mult_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,11,15,__ERR) 884 #define wr_cdr_qphase_mult_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x0010,4,wr_val) 885 #define rd_trnsum_tap_range_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd030,12,14,__ERR) 886 #define wr_trnsum_tap_range_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd030,0x000c,2,wr_val) 887 #define rd_trnsum_pattern() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd031,0,8,__ERR) 888 #define wr_trnsum_pattern(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd031,0xff00,8,wr_val) 889 #define rd_trnsum_pattern_bit_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd031,8,8,__ERR) 890 #define wr_trnsum_pattern_bit_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd031,0x00ff,0,wr_val) 891 #define rd_trnsum_tap_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd032,0,8,__ERR) 892 #define wr_trnsum_tap_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd032,0xff00,8,wr_val) 893 #define rd_trnsum_tap_sign() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd032,8,8,__ERR) 894 #define wr_trnsum_tap_sign(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd032,0x00ff,0,wr_val) 895 #define rd_tdr_cycle_bin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd033,0,12,__ERR) 896 #define wr_tdr_cycle_bin(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd033,0xf000,12,wr_val) 897 #define rd_tdr_cycle_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd033,4,12,__ERR) 898 #define wr_tdr_cycle_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd033,0x0f00,8,wr_val) 899 #define rd_tdr_trnsum_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd033,8,15,__ERR) 900 #define wr_tdr_trnsum_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd033,0x0080,7,wr_val) 901 #define rd_tdr_bit_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd033,9,11,__ERR) 902 #define wr_tdr_bit_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd033,0x007c,2,wr_val) 903 #define rd_trnsum_unsigned_flip() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd033,14,15,__ERR) 904 #define wr_trnsum_unsigned_flip(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd033,0x0002,1,wr_val) 905 #define rd_trnsum_unsigned_corr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd033,15,15,__ERR) 906 #define wr_trnsum_unsigned_corr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd033,0x0001,0,wr_val) 907 #define rd_trnsum_e_high() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd034,0,0,__ERR) 908 #define rd_trnsum_e_low() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd035,8,8,__ERR) 909 #define rd_trnsum_o_high() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd036,0,0,__ERR) 910 #define rd_trnsum_o_low() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd037,8,8,__ERR) 911 #define rd_trnsum_high() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd038,0,0,__ERR) 912 #define rd_trnsum_low() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd039,6,6,__ERR) 913 #define rd_p1_wants_to_go_high() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03a,0,15,__ERR) 914 #define rd_p1_wants_to_go_low() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03a,1,15,__ERR) 915 #define rd_p1_eyediag_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd03a,2,10,__ERR) 916 #define rd_vga_wants_to_go_low() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03a,9,15,__ERR) 917 #define rd_vga_bin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03a,10,10,__ERR) 918 #define rd_dfe_1_wants_negative() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03b,0,15,__ERR) 919 #define rd_dfe_1_e() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03b,2,13,__ERR) 920 #define rd_dfe_1_o() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03b,5,13,__ERR) 921 #define rd_dfe_1_cmn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03b,10,10,__ERR) 922 #define rd_dfe_2_e() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03c,2,13,__ERR) 923 #define rd_dfe_2_o() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03c,5,13,__ERR) 924 #define rd_dfe_2_se() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03c,9,15,__ERR) 925 #define rd_dfe_2_so() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03c,10,15,__ERR) 926 #define rd_dfe_2_cmn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03c,11,11,__ERR) 927 #define rd_dfe_5_cmn() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd03d,0,11,__ERR) 928 #define rd_dfe_4_cmn() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd03d,5,11,__ERR) 929 #define rd_dfe_3_cmn() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd03d,10,10,__ERR) 930 #define rd_vga3_ctrl_bin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03e,4,12,__ERR) 931 #define rd_vga2_ctrl_bin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03e,8,12,__ERR) 932 #define rd_vga1_ctrl_bin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd03e,12,12,__ERR) 933 #define rd_pf_hiz() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,8,15,__ERR) 934 #define wr_pf_hiz(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0080,7,wr_val) 935 #define rd_m1_thresh_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,9,14,__ERR) 936 #define wr_m1_thresh_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0060,5,wr_val) 937 #define rd_m1_thresh_zero() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,11,15,__ERR) 938 #define wr_m1_thresh_zero(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0010,4,wr_val) 939 #define rd_p1_thresh_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,12,15,__ERR) 940 #define wr_p1_thresh_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0008,3,wr_val) 941 #define rd_en_hgain() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,13,15,__ERR) 942 #define wr_en_hgain(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0004,2,wr_val) 943 #define rd_offset_pd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,14,15,__ERR) 944 #define wr_offset_pd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0002,1,wr_val) 945 #define rd_pd_ch_p1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd040,15,15,__ERR) 946 #define wr_pd_ch_p1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd040,0x0001,0,wr_val) 947 #define rd_pf_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd041,12,12,__ERR) 948 #define wr_pf_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd041,0x000f,0,wr_val) 949 #define rd_pf2_lowp_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd042,13,13,__ERR) 950 #define wr_pf2_lowp_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd042,0x0007,0,wr_val) 951 #define rd_data_offset_odd_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd141,10,10,__ERR) 952 #define rd_data_offset_evn_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd142,10,10,__ERR) 953 #define rd_p1_offset_odd_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd143,10,10,__ERR) 954 #define rd_p1_offset_evn_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd144,10,10,__ERR) 955 #define rd_m1_offset_odd_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd145,10,10,__ERR) 956 #define rd_m1_offset_evn_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd146,10,10,__ERR) 957 #define rd_dc_offset_bin() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd147,9,9,__ERR) 958 #define rd_L1_phase_err_offset_en_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,0,14,__ERR) 959 #define wr_L1_phase_err_offset_en_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0xc000,14,wr_val) 960 #define rd_L1_phase_err_offset_en_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,2,14,__ERR) 961 #define wr_L1_phase_err_offset_en_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x3000,12,wr_val) 962 #define rd_L0s_phase_err_offset_en_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,4,14,__ERR) 963 #define wr_L0s_phase_err_offset_en_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x0c00,10,wr_val) 964 #define rd_L0s_phase_err_offset_en_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,6,14,__ERR) 965 #define wr_L0s_phase_err_offset_en_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x0300,8,wr_val) 966 #define rd_L0s_phase_err_offset_en_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,8,14,__ERR) 967 #define wr_L0s_phase_err_offset_en_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x00c0,6,wr_val) 968 #define rd_phase_err_offset_en_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,10,14,__ERR) 969 #define wr_phase_err_offset_en_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x0030,4,wr_val) 970 #define rd_phase_err_offset_en_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,12,14,__ERR) 971 #define wr_phase_err_offset_en_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x000c,2,wr_val) 972 #define rd_phase_err_offset_en_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd260,14,14,__ERR) 973 #define wr_phase_err_offset_en_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd260,0x0003,0,wr_val) 974 #define rd_RxL1Active_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd261,0,15,__ERR) 975 #define wr_RxL1Active_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd261,0x8000,15,wr_val) 976 #define rd_RxL1Active_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd261,1,15,__ERR) 977 #define wr_RxL1Active_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd261,0x4000,14,wr_val) 978 #define rd_phase_err_offset_G3() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd261,2,12,__ERR) 979 #define wr_phase_err_offset_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd261,0x3c00,10,wr_val) 980 #define rd_phase_err_offset_G2() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd261,6,12,__ERR) 981 #define wr_phase_err_offset_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd261,0x03c0,6,wr_val) 982 #define rd_phase_err_offset_G1() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd261,10,12,__ERR) 983 #define wr_phase_err_offset_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd261,0x003c,2,wr_val) 984 #define rd_L1_phase_err_offset_en_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd261,14,14,__ERR) 985 #define wr_L1_phase_err_offset_en_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd261,0x0003,0,wr_val) 986 #define rd_L1_phase_err_offset_G1() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd262,0,12,__ERR) 987 #define wr_L1_phase_err_offset_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd262,0xf000,12,wr_val) 988 #define rd_L0s_phase_err_offset_G3() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd262,4,12,__ERR) 989 #define wr_L0s_phase_err_offset_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd262,0x0f00,8,wr_val) 990 #define rd_L0s_phase_err_offset_G2() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd262,8,12,__ERR) 991 #define wr_L0s_phase_err_offset_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd262,0x00f0,4,wr_val) 992 #define rd_L0s_phase_err_offset_G1() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd262,12,12,__ERR) 993 #define wr_L0s_phase_err_offset_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd262,0x000f,0,wr_val) 994 #define rd_RxL0sL1Failure_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,0,15,__ERR) 995 #define wr_RxL0sL1Failure_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x8000,15,wr_val) 996 #define rd_RxL0sL1Failure_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,1,15,__ERR) 997 #define wr_RxL0sL1Failure_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x4000,14,wr_val) 998 #define rd_dc_offset_frz_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,2,15,__ERR) 999 #define wr_dc_offset_frz_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x2000,13,wr_val) 1000 #define rd_dc_offset_frz_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,3,15,__ERR) 1001 #define wr_dc_offset_frz_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x1000,12,wr_val) 1002 #define rd_dfe_frz_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,4,15,__ERR) 1003 #define wr_dfe_frz_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x0800,11,wr_val) 1004 #define rd_dfe_frz_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,5,15,__ERR) 1005 #define wr_dfe_frz_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x0400,10,wr_val) 1006 #define rd_vga_frz_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,6,15,__ERR) 1007 #define wr_vga_frz_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x0200,9,wr_val) 1008 #define rd_vga_frz_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd263,7,15,__ERR) 1009 #define wr_vga_frz_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x0100,8,wr_val) 1010 #define rd_L1_phase_err_offset_G3() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd263,8,12,__ERR) 1011 #define wr_L1_phase_err_offset_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x00f0,4,wr_val) 1012 #define rd_L1_phase_err_offset_G2() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd263,12,12,__ERR) 1013 #define wr_L1_phase_err_offset_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd263,0x000f,0,wr_val) 1014 #define rd_RxL0sActive_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd264,1,15,__ERR) 1015 #define wr_RxL0sActive_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd264,0x4000,14,wr_val) 1016 #define rd_RxL0sActive_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd264,2,15,__ERR) 1017 #define wr_RxL0sActive_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd264,0x2000,13,wr_val) 1018 #define rd_L0sL1_lfsr_cnt_G2() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd264,3,3,__ERR) 1019 #define wr_L0sL1_lfsr_cnt_G2(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd264,0x1fff,0,wr_val) 1020 #define rd_L0sL1_lfsr_cnt_G3() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd265,3,3,__ERR) 1021 #define wr_L0sL1_lfsr_cnt_G3(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd265,0x1fff,0,wr_val) 1022 #define rd_hwtune_en_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd266,0,15,__ERR) 1023 #define wr_hwtune_en_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd266,0x8000,15,wr_val) 1024 #define rd_ucuse_en_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd266,1,15,__ERR) 1025 #define wr_ucuse_en_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd266,0x4000,14,wr_val) 1026 #define rd_use_facq_done_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd266,2,15,__ERR) 1027 #define wr_use_facq_done_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd266,0x2000,13,wr_val) 1028 #define rd_norm_lfsr_cnt_G1G2() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd266,3,3,__ERR) 1029 #define wr_norm_lfsr_cnt_G1G2(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd266,0x1fff,0,wr_val) 1030 #define rd_facq_en_disable_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd267,0,15,__ERR) 1031 #define wr_facq_en_disable_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd267,0x8000,15,wr_val) 1032 #define rd_facq_en_disable_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd267,1,15,__ERR) 1033 #define wr_facq_en_disable_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd267,0x4000,14,wr_val) 1034 #define rd_facq_en_disable_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd267,2,15,__ERR) 1035 #define wr_facq_en_disable_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd267,0x2000,13,wr_val) 1036 #define rd_norm_lfsr_cnt_G3() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd267,3,3,__ERR) 1037 #define wr_norm_lfsr_cnt_G3(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd267,0x1fff,0,wr_val) 1038 #define rd_cdr_peak_polarity() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd268,0,15,__ERR) 1039 #define wr_cdr_peak_polarity(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd268,0x8000,15,wr_val) 1040 #define rd_L1_cdr_sttl_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd268,1,11,__ERR) 1041 #define wr_L1_cdr_sttl_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd268,0x7c00,10,wr_val) 1042 #define rd_L1_cdr_sttl_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd268,6,11,__ERR) 1043 #define wr_L1_cdr_sttl_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd268,0x03e0,5,wr_val) 1044 #define rd_L1_cdr_sttl_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd268,11,11,__ERR) 1045 #define wr_L1_cdr_sttl_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd268,0x001f,0,wr_val) 1046 #define rd_dfe_acc_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd269,0,15,__ERR) 1047 #define wr_dfe_acc_reset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd269,0x8000,15,wr_val) 1048 #define rd_slicer_offset_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd269,1,11,__ERR) 1049 #define wr_slicer_offset_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd269,0x7c00,10,wr_val) 1050 #define rd_slicer_offset_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd269,6,11,__ERR) 1051 #define wr_slicer_offset_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd269,0x03e0,5,wr_val) 1052 #define rd_slicer_offset_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd269,11,11,__ERR) 1053 #define wr_slicer_offset_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd269,0x001f,0,wr_val) 1054 #define rd_dc_offset_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26a,1,11,__ERR) 1055 #define wr_dc_offset_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26a,0x7c00,10,wr_val) 1056 #define rd_dc_offset_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26a,6,11,__ERR) 1057 #define wr_dc_offset_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26a,0x03e0,5,wr_val) 1058 #define rd_dc_offset_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26a,11,11,__ERR) 1059 #define wr_dc_offset_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26a,0x001f,0,wr_val) 1060 #define rd_adj_pi_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26b,0,15,__ERR) 1061 #define wr_adj_pi_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26b,0x8000,15,wr_val) 1062 #define rd_step_dir() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26b,1,15,__ERR) 1063 #define wr_step_dir(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26b,0x4000,14,wr_val) 1064 #define rd_m1_minus_d_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26b,2,9,__ERR) 1065 #define wr_m1_minus_d_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26b,0x3f80,7,wr_val) 1066 #define rd_m1_minus_d_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26b,9,9,__ERR) 1067 #define wr_m1_minus_d_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26b,0x007f,0,wr_val) 1068 #define rd_dc_offset_use_odd_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26c,4,15,__ERR) 1069 #define wr_dc_offset_use_odd_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26c,0x0800,11,wr_val) 1070 #define rd_dc_offset_use_even_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26c,5,15,__ERR) 1071 #define wr_dc_offset_use_even_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26c,0x0400,10,wr_val) 1072 #define rd_dc_offset_use_odd_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26c,6,15,__ERR) 1073 #define wr_dc_offset_use_odd_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26c,0x0200,9,wr_val) 1074 #define rd_dc_offset_use_even_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26c,7,15,__ERR) 1075 #define wr_dc_offset_use_even_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26c,0x0100,8,wr_val) 1076 #define rd_dsc_sm_manual_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26c,8,15,__ERR) 1077 #define wr_dsc_sm_manual_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26c,0x0080,7,wr_val) 1078 #define rd_m1_minus_d_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26c,9,9,__ERR) 1079 #define wr_m1_minus_d_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26c,0x007f,0,wr_val) 1080 #define rd_dsc_sm_tmux_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26d,0,15,__ERR) 1081 #define wr_dsc_sm_tmux_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26d,0x8000,15,wr_val) 1082 #define rd_cdr_zero_from_m1_slicer_g2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26d,1,15,__ERR) 1083 #define wr_cdr_zero_from_m1_slicer_g2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26d,0x4000,14,wr_val) 1084 #define rd_cdr_zero_from_m1_slicer_g1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26d,2,15,__ERR) 1085 #define wr_cdr_zero_from_m1_slicer_g1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26d,0x2000,13,wr_val) 1086 #define rd_L0sL1_lfsr_cnt_G1() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd26d,3,3,__ERR) 1087 #define wr_L0sL1_lfsr_cnt_G1(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd26d,0x1fff,0,wr_val) 1088 #define rd_sigdet_frc_init() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,0,15,__ERR) 1089 #define wr_sigdet_frc_init(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x8000,15,wr_val) 1090 #define rd_disable_L0s_exit() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,1,15,__ERR) 1091 #define wr_disable_L0s_exit(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x4000,14,wr_val) 1092 #define rd_disable_L1_exit() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,2,15,__ERR) 1093 #define wr_disable_L1_exit(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x2000,13,wr_val) 1094 #define rd_dsc_slicer_offset_done_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,3,15,__ERR) 1095 #define wr_dsc_slicer_offset_done_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x1000,12,wr_val) 1096 #define rd_dsc_slicer_offset_done_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,4,15,__ERR) 1097 #define wr_dsc_slicer_offset_done_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x0800,11,wr_val) 1098 #define rd_dsc_slicer_offset_cnt_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,5,15,__ERR) 1099 #define wr_dsc_slicer_offset_cnt_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x0400,10,wr_val) 1100 #define rd_dsc_slicer_offset_cnt_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,6,13,__ERR) 1101 #define wr_dsc_slicer_offset_cnt_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x0380,7,wr_val) 1102 #define rd_redo_slicer_calibration() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,9,15,__ERR) 1103 #define wr_redo_slicer_calibration(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x0040,6,wr_val) 1104 #define rd_slicer_calibration_mask() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd26e,10,10,__ERR) 1105 #define wr_slicer_calibration_mask(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd26e,0x003f,0,wr_val) 1106 #define rd_cdr_pattern_sel_lock_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd270,0,12,__ERR) 1107 #define wr_cdr_pattern_sel_lock_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd270,0xf000,12,wr_val) 1108 #define rd_cdr_pattern_sel_steady_state_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd270,4,12,__ERR) 1109 #define wr_cdr_pattern_sel_steady_state_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd270,0x0f00,8,wr_val) 1110 #define rd_cdr_pattern_sel_steady_state_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd270,8,12,__ERR) 1111 #define wr_cdr_pattern_sel_steady_state_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd270,0x00f0,4,wr_val) 1112 #define rd_cdr_pattern_sel_steady_state_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd270,12,12,__ERR) 1113 #define wr_cdr_pattern_sel_steady_state_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd270,0x000f,0,wr_val) 1114 #define rd_dsc_sm_pause_entry() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd271,0,15,__ERR) 1115 #define wr_dsc_sm_pause_entry(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd271,0x8000,15,wr_val) 1116 #define rd_dsc_sm_pause_exit() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd271,1,15,__ERR) 1117 #define wr_dsc_sm_pause_exit(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd271,0x4000,14,wr_val) 1118 #define rd_dsc_lock_in_uc_tune() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd271,2,13,__ERR) 1119 #define wr_dsc_lock_in_uc_tune(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd271,0x3800,11,wr_val) 1120 #define rd_dsc_lock_in_hw_tune() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd271,5,13,__ERR) 1121 #define wr_dsc_lock_in_hw_tune(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd271,0x0700,8,wr_val) 1122 #define rd_cdr_pattern_sel_lock_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd271,8,12,__ERR) 1123 #define wr_cdr_pattern_sel_lock_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd271,0x00f0,4,wr_val) 1124 #define rd_cdr_pattern_sel_lock_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd271,12,12,__ERR) 1125 #define wr_cdr_pattern_sel_lock_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd271,0x000f,0,wr_val) 1126 #define rd_dfe_clken_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,0,15,__ERR) 1127 #define wr_dfe_clken_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x8000,15,wr_val) 1128 #define rd_dfe_clken_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,1,15,__ERR) 1129 #define wr_dfe_clken_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x4000,14,wr_val) 1130 #define rd_rx_pi_step_size_norm_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,2,14,__ERR) 1131 #define wr_rx_pi_step_size_norm_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x3000,12,wr_val) 1132 #define rd_rx_pi_step_size_norm_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,4,14,__ERR) 1133 #define wr_rx_pi_step_size_norm_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x0c00,10,wr_val) 1134 #define rd_rx_pi_step_size_norm_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,6,14,__ERR) 1135 #define wr_rx_pi_step_size_norm_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x0300,8,wr_val) 1136 #define rd_rx_pi_step_size_facq_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,8,14,__ERR) 1137 #define wr_rx_pi_step_size_facq_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x00c0,6,wr_val) 1138 #define rd_rx_pi_step_size_facq_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,10,14,__ERR) 1139 #define wr_rx_pi_step_size_facq_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x0030,4,wr_val) 1140 #define rd_rx_pi_step_size_facq_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd272,12,14,__ERR) 1141 #define wr_rx_pi_step_size_facq_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd272,0x000c,2,wr_val) 1142 #define rd_pcie_g1_condition_mask_e() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd273,6,6,__ERR) 1143 #define wr_pcie_g1_condition_mask_e(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd273,0x03ff,0,wr_val) 1144 #define rd_pcie_g1_condition_mask_o() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd274,6,6,__ERR) 1145 #define wr_pcie_g1_condition_mask_o(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd274,0x03ff,0,wr_val) 1146 #define rd_vga_op_short() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd275,12,15,__ERR) 1147 #define rd_RxFastAcqEnable_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd275,13,15,__ERR) 1148 #define rd_RxFastAcqEnable_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd275,14,15,__ERR) 1149 #define rd_RxFastAcqEnable_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd275,15,15,__ERR) 1150 #define rd_rx_hist_00() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd280,__ERR) 1151 #define rd_rx_hist_01() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd281,__ERR) 1152 #define rd_rx_hist_02() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd282,__ERR) 1153 #define rd_rx_hist_03() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd283,__ERR) 1154 #define rd_rx_hist_04() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd284,__ERR) 1155 #define rd_rx_hist_05() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd285,__ERR) 1156 #define rd_rx_hist_06() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd286,__ERR) 1157 #define rd_rx_hist_07() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd287,__ERR) 1158 #define rd_rx_hist_08() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd288,__ERR) 1159 #define rd_rx_hist_09() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd289,__ERR) 1160 #define rd_rx_hist_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28a,__ERR) 1161 #define rd_rx_hist_11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28b,__ERR) 1162 #define rd_rx_hist_12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28c,__ERR) 1163 #define rd_rx_hist_13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28d,__ERR) 1164 #define rd_rg_hist_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd28e,12,15,__ERR) 1165 #define wr_rg_hist_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd28e,0x0008,3,wr_val) 1166 #define rd_rg_hist_stop() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd28e,13,15,__ERR) 1167 #define wr_rg_hist_stop(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd28e,0x0004,2,wr_val) 1168 #define rd_rg_hist_rd_mux_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd28e,14,14,__ERR) 1169 #define wr_rg_hist_rd_mux_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd28e,0x0003,0,wr_val) 1170 #define rd_uc_adj_pi() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd290,0,15,__ERR) 1171 #define wr_uc_adj_pi(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd290,0x8000,15,wr_val) 1172 #define rd_acq_cdr_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd290,1,11,__ERR) 1173 #define wr_acq_cdr_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd290,0x7c00,10,wr_val) 1174 #define rd_acq_cdr_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd290,6,11,__ERR) 1175 #define wr_acq_cdr_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd290,0x03e0,5,wr_val) 1176 #define rd_acq_cdr_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd290,11,11,__ERR) 1177 #define wr_acq_cdr_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd290,0x001f,0,wr_val) 1178 #define rd_cdr_settle_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd291,1,11,__ERR) 1179 #define wr_cdr_settle_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd291,0x7c00,10,wr_val) 1180 #define rd_cdr_settle_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd291,6,11,__ERR) 1181 #define wr_cdr_settle_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd291,0x03e0,5,wr_val) 1182 #define rd_cdr_settle_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd291,11,11,__ERR) 1183 #define wr_cdr_settle_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd291,0x001f,0,wr_val) 1184 #define rd_hw_tune_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd292,1,11,__ERR) 1185 #define wr_hw_tune_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd292,0x7c00,10,wr_val) 1186 #define rd_hw_tune_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd292,6,11,__ERR) 1187 #define wr_hw_tune_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd292,0x03e0,5,wr_val) 1188 #define rd_hw_tune_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd292,11,11,__ERR) 1189 #define wr_hw_tune_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd292,0x001f,0,wr_val) 1190 #define rd_facq_wait_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd293,1,11,__ERR) 1191 #define wr_facq_wait_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd293,0x7c00,10,wr_val) 1192 #define rd_facq_wait_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd293,6,11,__ERR) 1193 #define wr_facq_wait_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd293,0x03e0,5,wr_val) 1194 #define rd_facq_wait_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd293,11,11,__ERR) 1195 #define wr_facq_wait_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd293,0x001f,0,wr_val) 1196 #define rd_L0s_acq_cdr_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd294,1,11,__ERR) 1197 #define wr_L0s_acq_cdr_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd294,0x7c00,10,wr_val) 1198 #define rd_L0s_acq_cdr_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd294,6,11,__ERR) 1199 #define wr_L0s_acq_cdr_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd294,0x03e0,5,wr_val) 1200 #define rd_L0s_acq_cdr_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd294,11,11,__ERR) 1201 #define wr_L0s_acq_cdr_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd294,0x001f,0,wr_val) 1202 #define rd_L1_acq_cdr_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd295,1,11,__ERR) 1203 #define wr_L1_acq_cdr_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd295,0x7c00,10,wr_val) 1204 #define rd_L1_acq_cdr_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd295,6,11,__ERR) 1205 #define wr_L1_acq_cdr_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd295,0x03e0,5,wr_val) 1206 #define rd_L1_acq_cdr_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd295,11,11,__ERR) 1207 #define wr_L1_acq_cdr_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd295,0x001f,0,wr_val) 1208 #define rd_L0s_cdr_sttl_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd296,1,11,__ERR) 1209 #define wr_L0s_cdr_sttl_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd296,0x7c00,10,wr_val) 1210 #define rd_L0s_cdr_sttl_timeout_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd296,6,11,__ERR) 1211 #define wr_L0s_cdr_sttl_timeout_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd296,0x03e0,5,wr_val) 1212 #define rd_L0s_cdr_sttl_timeout_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd296,11,11,__ERR) 1213 #define wr_L0s_cdr_sttl_timeout_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd296,0x001f,0,wr_val) 1214 #define rd_L1_hw_tune_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd297,1,11,__ERR) 1215 #define wr_L1_hw_tune_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd297,0x7c00,10,wr_val) 1216 #define rd_L0s_hw_tune_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd297,6,11,__ERR) 1217 #define wr_L0s_hw_tune_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd297,0x03e0,5,wr_val) 1218 #define rd_measure_timeout_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd297,11,11,__ERR) 1219 #define wr_measure_timeout_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd297,0x001f,0,wr_val) 1220 #define rd_cdr_bwsel_prop_L0s_acqcdr_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,0,14,__ERR) 1221 #define wr_cdr_bwsel_prop_L0s_acqcdr_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0xc000,14,wr_val) 1222 #define rd_cdr_bwsel_prop_L0s_acqcdr_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,2,14,__ERR) 1223 #define wr_cdr_bwsel_prop_L0s_acqcdr_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x3000,12,wr_val) 1224 #define rd_cdr_bwsel_prop_norm_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,4,14,__ERR) 1225 #define wr_cdr_bwsel_prop_norm_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x0c00,10,wr_val) 1226 #define rd_cdr_bwsel_prop_norm_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,6,14,__ERR) 1227 #define wr_cdr_bwsel_prop_norm_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x0300,8,wr_val) 1228 #define rd_cdr_bwsel_prop_norm_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,8,14,__ERR) 1229 #define wr_cdr_bwsel_prop_norm_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x00c0,6,wr_val) 1230 #define rd_cdr_bwsel_prop_acqcdr_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,10,14,__ERR) 1231 #define wr_cdr_bwsel_prop_acqcdr_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x0030,4,wr_val) 1232 #define rd_cdr_bwsel_prop_acqcdr_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,12,14,__ERR) 1233 #define wr_cdr_bwsel_prop_acqcdr_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x000c,2,wr_val) 1234 #define rd_cdr_bwsel_prop_acqcdr_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd298,14,14,__ERR) 1235 #define wr_cdr_bwsel_prop_acqcdr_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd298,0x0003,0,wr_val) 1236 #define rd_cdr_bwsel_prop_L0s_acqcdr_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,14,14,__ERR) 1237 #define wr_cdr_bwsel_prop_L0s_acqcdr_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x0003,0,wr_val) 1238 #define rd_cdr_bwsel_prop_L1_acqcdr_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,12,14,__ERR) 1239 #define wr_cdr_bwsel_prop_L1_acqcdr_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x000c,2,wr_val) 1240 #define rd_cdr_bwsel_prop_L1_acqcdr_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,10,14,__ERR) 1241 #define wr_cdr_bwsel_prop_L1_acqcdr_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x0030,4,wr_val) 1242 #define rd_cdr_bwsel_prop_L1_acqcdr_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,8,14,__ERR) 1243 #define wr_cdr_bwsel_prop_L1_acqcdr_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x00c0,6,wr_val) 1244 #define rd_cdr_bwsel_prop_L0s_cdrsttl_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,6,14,__ERR) 1245 #define wr_cdr_bwsel_prop_L0s_cdrsttl_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x0300,8,wr_val) 1246 #define rd_cdr_bwsel_prop_L0s_cdrsttl_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,4,14,__ERR) 1247 #define wr_cdr_bwsel_prop_L0s_cdrsttl_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x0c00,10,wr_val) 1248 #define rd_cdr_bwsel_prop_L0s_cdrsttl_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,2,14,__ERR) 1249 #define wr_cdr_bwsel_prop_L0s_cdrsttl_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0x3000,12,wr_val) 1250 #define rd_cdr_bwsel_prop_L1_cdrsttl_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd299,0,14,__ERR) 1251 #define wr_cdr_bwsel_prop_L1_cdrsttl_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd299,0xc000,14,wr_val) 1252 #define rd_cdr_bwsel_integ_acqcdr_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29a,0,12,__ERR) 1253 #define wr_cdr_bwsel_integ_acqcdr_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29a,0xf000,12,wr_val) 1254 #define rd_cdr_bwsel_integ_acqcdr_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29a,4,12,__ERR) 1255 #define wr_cdr_bwsel_integ_acqcdr_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29a,0x0f00,8,wr_val) 1256 #define rd_cdr_bwsel_integ_acqcdr_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29a,8,12,__ERR) 1257 #define wr_cdr_bwsel_integ_acqcdr_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29a,0x00f0,4,wr_val) 1258 #define rd_cdr_bwsel_prop_L1_cdrsttl_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29a,12,14,__ERR) 1259 #define wr_cdr_bwsel_prop_L1_cdrsttl_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29a,0x000c,2,wr_val) 1260 #define rd_cdr_bwsel_prop_L1_cdrsttl_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29a,14,14,__ERR) 1261 #define wr_cdr_bwsel_prop_L1_cdrsttl_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29a,0x0003,0,wr_val) 1262 #define rd_cdr_bwsel_integ_L0s_acqcdr_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29b,0,12,__ERR) 1263 #define wr_cdr_bwsel_integ_L0s_acqcdr_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29b,0xf000,12,wr_val) 1264 #define rd_cdr_bwsel_integ_norm_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29b,4,12,__ERR) 1265 #define wr_cdr_bwsel_integ_norm_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29b,0x0f00,8,wr_val) 1266 #define rd_cdr_bwsel_integ_norm_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29b,8,12,__ERR) 1267 #define wr_cdr_bwsel_integ_norm_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29b,0x00f0,4,wr_val) 1268 #define rd_cdr_bwsel_integ_norm_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29b,12,12,__ERR) 1269 #define wr_cdr_bwsel_integ_norm_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29b,0x000f,0,wr_val) 1270 #define rd_cdr_bwsel_integ_L1_acqcdr_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29c,0,12,__ERR) 1271 #define wr_cdr_bwsel_integ_L1_acqcdr_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29c,0xf000,12,wr_val) 1272 #define rd_cdr_bwsel_integ_L1_acqcdr_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29c,4,12,__ERR) 1273 #define wr_cdr_bwsel_integ_L1_acqcdr_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29c,0x0f00,8,wr_val) 1274 #define rd_cdr_bwsel_integ_L0s_acqcdr_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29c,8,12,__ERR) 1275 #define wr_cdr_bwsel_integ_L0s_acqcdr_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29c,0x00f0,4,wr_val) 1276 #define rd_cdr_bwsel_integ_L0s_acqcdr_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29c,12,12,__ERR) 1277 #define wr_cdr_bwsel_integ_L0s_acqcdr_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29c,0x000f,0,wr_val) 1278 #define rd_cdr_bwsel_integ_L0s_cdrsttl_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29d,0,12,__ERR) 1279 #define wr_cdr_bwsel_integ_L0s_cdrsttl_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29d,0xf000,12,wr_val) 1280 #define rd_cdr_bwsel_integ_L0s_cdrsttl_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29d,4,12,__ERR) 1281 #define wr_cdr_bwsel_integ_L0s_cdrsttl_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29d,0x0f00,8,wr_val) 1282 #define rd_cdr_bwsel_integ_L0s_cdrsttl_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29d,8,12,__ERR) 1283 #define wr_cdr_bwsel_integ_L0s_cdrsttl_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29d,0x00f0,4,wr_val) 1284 #define rd_cdr_bwsel_integ_L1_acqcdr_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29d,12,12,__ERR) 1285 #define wr_cdr_bwsel_integ_L1_acqcdr_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29d,0x000f,0,wr_val) 1286 #define rd_cdr_bwsel_integ_L1_cdrsttl_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29e,4,12,__ERR) 1287 #define wr_cdr_bwsel_integ_L1_cdrsttl_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29e,0x0f00,8,wr_val) 1288 #define rd_cdr_bwsel_integ_L1_cdrsttl_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29e,8,12,__ERR) 1289 #define wr_cdr_bwsel_integ_L1_cdrsttl_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29e,0x00f0,4,wr_val) 1290 #define rd_cdr_bwsel_integ_L1_cdrsttl_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd29e,12,12,__ERR) 1291 #define wr_cdr_bwsel_integ_L1_cdrsttl_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd29e,0x000f,0,wr_val) 1292 #define rdc_mdio_blk_addr() _merlin16_pcieg3_pmd_rde_field(sa__, 0xffdf,1,5,__ERR) 1293 #define wrc_mdio_blk_addr(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xffdf,0x7ff0,4,wr_val) 1294 #define rdc_mdio_brcst_port_addr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdc,11,11,__ERR) 1295 #define wrc_mdio_brcst_port_addr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdc,0x001f,0,wr_val) 1296 #define rdc_mdio_multi_prts_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,0,15,__ERR) 1297 #define wrc_mdio_multi_prts_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x8000,15,wr_val) 1298 #define rdc_mdio_multi_mmds_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,1,15,__ERR) 1299 #define wrc_mdio_multi_mmds_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x4000,14,wr_val) 1300 #define rdc_mdio_dev_pcs_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,9,15,__ERR) 1301 #define wrc_mdio_dev_pcs_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x0040,6,wr_val) 1302 #define rdc_mdio_dev_dte_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,10,15,__ERR) 1303 #define wrc_mdio_dev_dte_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x0020,5,wr_val) 1304 #define rdc_mdio_dev_phy_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,11,15,__ERR) 1305 #define wrc_mdio_dev_phy_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x0010,4,wr_val) 1306 #define rdc_mdio_dev_an_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,12,15,__ERR) 1307 #define wrc_mdio_dev_an_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x0008,3,wr_val) 1308 #define rdc_mdio_dev_pmd_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,13,15,__ERR) 1309 #define wrc_mdio_dev_pmd_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x0004,2,wr_val) 1310 #define rdc_mdio_dev_cl22_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xffdd,15,15,__ERR) 1311 #define wrc_mdio_dev_cl22_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xffdd,0x0001,0,wr_val) 1312 #define rdc_mdio_aer() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xffde,__ERR) 1313 #define wrc_mdio_aer(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xffde,wr_val) 1314 #define rdc_micro_core_clk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd200,14,15,__ERR) 1315 #define wrc_micro_core_clk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd200,0x0002,1,wr_val) 1316 #define rdc_micro_master_clk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd200,15,15,__ERR) 1317 #define wrc_micro_master_clk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd200,0x0001,0,wr_val) 1318 #define rdc_micro_pram_if_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd201,12,15,__ERR) 1319 #define wrc_micro_pram_if_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd201,0x0008,3,wr_val) 1320 #define rdc_micro_core_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd201,14,15,__ERR) 1321 #define wrc_micro_core_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd201,0x0002,1,wr_val) 1322 #define rdc_micro_master_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd201,15,15,__ERR) 1323 #define wrc_micro_master_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd201,0x0001,0,wr_val) 1324 #define rdc_micro_autoinc_rdaddr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd202,2,15,__ERR) 1325 #define wrc_micro_autoinc_rdaddr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd202,0x2000,13,wr_val) 1326 #define rdc_micro_autoinc_wraddr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd202,3,15,__ERR) 1327 #define wrc_micro_autoinc_wraddr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd202,0x1000,12,wr_val) 1328 #define rdc_micro_ra_init() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd202,6,14,__ERR) 1329 #define wrc_micro_ra_init(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd202,0x0300,8,wr_val) 1330 #define rdc_micro_ra_rddatasize() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd202,10,14,__ERR) 1331 #define wrc_micro_ra_rddatasize(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd202,0x0030,4,wr_val) 1332 #define rdc_micro_ra_wrdatasize() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd202,14,14,__ERR) 1333 #define wrc_micro_ra_wrdatasize(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd202,0x0003,0,wr_val) 1334 #define rdc_micro_ra_initdone() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd203,15,15,__ERR) 1335 #define rdc_micro_ra_wraddr_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd204,__ERR) 1336 #define wrc_micro_ra_wraddr_lsw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd204,wr_val) 1337 #define rdc_micro_ra_wraddr_msw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd205,__ERR) 1338 #define wrc_micro_ra_wraddr_msw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd205,wr_val) 1339 #define rdc_micro_ra_wrdata_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd206,__ERR) 1340 #define wrc_micro_ra_wrdata_lsw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd206,wr_val) 1341 #define rdc_micro_ra_wrdata_msw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd207,__ERR) 1342 #define wrc_micro_ra_wrdata_msw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd207,wr_val) 1343 #define rdc_micro_ra_rdaddr_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd208,__ERR) 1344 #define wrc_micro_ra_rdaddr_lsw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd208,wr_val) 1345 #define rdc_micro_ra_rdaddr_msw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd209,__ERR) 1346 #define wrc_micro_ra_rdaddr_msw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd209,wr_val) 1347 #define rdc_micro_ra_rddata_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20a,__ERR) 1348 #define rdc_micro_ra_rddata_msw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20b,__ERR) 1349 #define rdc_micro_pramif_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd20c,15,15,__ERR) 1350 #define wrc_micro_pramif_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd20c,0x0001,0,wr_val) 1351 #define rdc_micro_pramif_ahb_wraddr_lsw() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd20d,0,2,__ERR) 1352 #define wrc_micro_pramif_ahb_wraddr_lsw(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd20d,0xfffc,2,wr_val) 1353 #define rdc_micro_pramif_ahb_wraddr_msw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20e,__ERR) 1354 #define wrc_micro_pramif_ahb_wraddr_msw(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd20e,wr_val) 1355 #define rdc_micro_pvt_tempdata_rmi() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd210,6,6,__ERR) 1356 #define rdc_micro_rmi_to_micro_mbox0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd211,__ERR) 1357 #define wrc_micro_rmi_to_micro_mbox0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd211,wr_val) 1358 #define rdc_micro_rmi_to_micro_mbox1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd212,__ERR) 1359 #define wrc_micro_rmi_to_micro_mbox1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd212,wr_val) 1360 #define rdc_micro_to_rmi_mbox0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd213,__ERR) 1361 #define rdc_micro_to_rmi_mbox1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd214,__ERR) 1362 #define rdc_micro_gen_intr_rmi_mbox1wr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd215,13,15,__ERR) 1363 #define wrc_micro_gen_intr_rmi_mbox1wr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd215,0x0004,2,wr_val) 1364 #define rdc_micro_gen_intr_rmi_mbox0wr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd215,14,15,__ERR) 1365 #define wrc_micro_gen_intr_rmi_mbox0wr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd215,0x0002,1,wr_val) 1366 #define rdc_micro_rmi_mbox_send_msgin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd215,15,15,__ERR) 1367 #define wrc_micro_rmi_mbox_send_msgin(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd215,0x0001,0,wr_val) 1368 #define rdc_micro_pmi_hp_ext_ack_timeout_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd216,11,15,__ERR) 1369 #define wrc_micro_pmi_hp_ext_ack_timeout_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd216,0x0010,4,wr_val) 1370 #define rdc_micro_pmi_hp_ack_timeout_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd216,12,15,__ERR) 1371 #define wrc_micro_pmi_hp_ack_timeout_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd216,0x0008,3,wr_val) 1372 #define rdc_micro_sw_pmi_hp_ext_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd216,13,15,__ERR) 1373 #define wrc_micro_sw_pmi_hp_ext_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd216,0x0004,2,wr_val) 1374 #define rdc_micro_sw_pmi_hp_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd216,14,15,__ERR) 1375 #define wrc_micro_sw_pmi_hp_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd216,0x0002,1,wr_val) 1376 #define rdc_micro_m0_hresp_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd216,15,15,__ERR) 1377 #define wrc_micro_m0_hresp_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd216,0x0001,0,wr_val) 1378 #define rdc_micro_pr_default_slave_error() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd217,13,15,__ERR) 1379 #define rdc_micro_rmi_default_slave_error() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd217,14,15,__ERR) 1380 #define rdc_micro_m0_default_slave_error() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd217,15,15,__ERR) 1381 #define rdc_micro_ra_autoinc_nxt_wraddr_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd218,__ERR) 1382 #define rdc_micro_ra_autoinc_nxt_rdaddr_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd219,__ERR) 1383 #define rdc_micro_pr_autoinc_nxt_wraddr_lsw() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd21a,__ERR) 1384 #define rdc_micro_pvt_tempdata_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd21b,3,15,__ERR) 1385 #define wrc_micro_pvt_tempdata_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd21b,0x1000,12,wr_val) 1386 #define rdc_micro_pvt_tempdata_frcval() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd21b,6,6,__ERR) 1387 #define wrc_micro_pvt_tempdata_frcval(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd21b,0x03ff,0,wr_val) 1388 #define rdc_micro_ecc_corrupt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd220,10,14,__ERR) 1389 #define wrc_micro_ecc_corrupt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd220,0x0030,4,wr_val) 1390 #define rdc_micro_ecc_frc_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd220,14,15,__ERR) 1391 #define wrc_micro_ecc_frc_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd220,0x0002,1,wr_val) 1392 #define rdc_micro_eccg_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd220,15,15,__ERR) 1393 #define wrc_micro_eccg_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd220,0x0001,0,wr_val) 1394 #define rdc_micro_ra_ecc_wrdata() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd221,9,9,__ERR) 1395 #define wrc_micro_ra_ecc_wrdata(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd221,0x007f,0,wr_val) 1396 #define rdc_micro_code_ram_ecc_address() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd222,1,1,__ERR) 1397 #define rdc_micro_ra_ecc_rddata() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd223,9,9,__ERR) 1398 #define rdc_micro_code_ram_tm() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd224,9,9,__ERR) 1399 #define wrc_micro_code_ram_tm(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd224,0x007f,0,wr_val) 1400 #define rdc_micro_ignore_m0_code_writes() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd225,0,15,__ERR) 1401 #define wrc_micro_ignore_m0_code_writes(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd225,0x8000,15,wr_val) 1402 #define rdc_micro_ramclk_noninv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd225,1,15,__ERR) 1403 #define wrc_micro_ramclk_noninv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd225,0x4000,14,wr_val) 1404 #define rdc_micro_dr_size() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd225,2,10,__ERR) 1405 #define wrc_micro_dr_size(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd225,0x3f00,8,wr_val) 1406 #define rdc_micro_protect_fwcode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd225,14,15,__ERR) 1407 #define wrc_micro_protect_fwcode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd225,0x0002,1,wr_val) 1408 #define rdc_micro_dr_looktab_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd225,15,15,__ERR) 1409 #define wrc_micro_dr_looktab_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd225,0x0001,0,wr_val) 1410 #define rdc_micro_rmi_m0_systemresetreq_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd227,6,15,__ERR) 1411 #define rdc_micro_rmi_m0_lockup_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd227,7,15,__ERR) 1412 #define rdc_micro_rmi_ecc_multirow_err_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd227,9,15,__ERR) 1413 #define rdc_micro_rmi_ecc_uncorr_err_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd227,10,15,__ERR) 1414 #define rdc_micro_rmi_ecc_corr_err_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd227,11,15,__ERR) 1415 #define rdc_micro_rmi_mbox_msgout_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd227,15,15,__ERR) 1416 #define rdc_micro_rmi_m0_systemresetreq_intr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd226,6,15,__ERR) 1417 #define wrc_micro_rmi_m0_systemresetreq_intr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd226,0x0200,9,wr_val) 1418 #define rdc_micro_rmi_m0_lockup_intr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd226,7,15,__ERR) 1419 #define wrc_micro_rmi_m0_lockup_intr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd226,0x0100,8,wr_val) 1420 #define rdc_micro_rmi_ecc_multirow_err_intr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd226,9,15,__ERR) 1421 #define wrc_micro_rmi_ecc_multirow_err_intr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd226,0x0040,6,wr_val) 1422 #define rdc_micro_rmi_ecc_uncorr_err_intr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd226,10,15,__ERR) 1423 #define wrc_micro_rmi_ecc_uncorr_err_intr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd226,0x0020,5,wr_val) 1424 #define rdc_micro_rmi_ecc_corr_err_intr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd226,11,15,__ERR) 1425 #define wrc_micro_rmi_ecc_corr_err_intr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd226,0x0010,4,wr_val) 1426 #define rdc_micro_rmi_mbox_msgout_intr_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd226,15,15,__ERR) 1427 #define wrc_micro_rmi_mbox_msgout_intr_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd226,0x0001,0,wr_val) 1428 #define rdc_micro_pmi_hp_ext_fast_bktobk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd228,5,15,__ERR) 1429 #define wrc_micro_pmi_hp_ext_fast_bktobk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd228,0x0400,10,wr_val) 1430 #define rdc_micro_pmi_hp_ext_fast_dual_meta_ff_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd228,6,15,__ERR) 1431 #define wrc_micro_pmi_hp_ext_fast_dual_meta_ff_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd228,0x0200,9,wr_val) 1432 #define rdc_micro_pmi_hp_ext_fast_read_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd228,7,15,__ERR) 1433 #define wrc_micro_pmi_hp_ext_fast_read_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd228,0x0100,8,wr_val) 1434 #define rdc_micro_pmi_hp_fast_bktobk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd228,13,15,__ERR) 1435 #define wrc_micro_pmi_hp_fast_bktobk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd228,0x0004,2,wr_val) 1436 #define rdc_micro_pmi_hp_fast_dual_meta_ff_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd228,14,15,__ERR) 1437 #define wrc_micro_pmi_hp_fast_dual_meta_ff_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd228,0x0002,1,wr_val) 1438 #define rdc_micro_pmi_hp_fast_read_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd228,15,15,__ERR) 1439 #define wrc_micro_pmi_hp_fast_read_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd228,0x0001,0,wr_val) 1440 #define rdc_micro_silicon_debug_status_mux_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd229,14,14,__ERR) 1441 #define wrc_micro_silicon_debug_status_mux_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd229,0x0003,0,wr_val) 1442 #define rdc_micro_silicon_debug_status_muxed_data() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd22a,__ERR) 1443 #define rd_uc_gen3_rdy() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd240,15,15,__ERR) 1444 #define wr_uc_gen3_rdy(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd240,0x0001,0,wr_val) 1445 #define rd_eval_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd241,0,15,__ERR) 1446 #define wr_eval_done(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd241,0x8000,15,wr_val) 1447 #define rd_eval_err_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd241,1,15,__ERR) 1448 #define wr_eval_err_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd241,0x4000,14,wr_val) 1449 #define rd_fdbk_dir_chg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd241,2,10,__ERR) 1450 #define wr_fdbk_dir_chg(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd241,0x3f00,8,wr_val) 1451 #define rd_fig_merit() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd241,8,8,__ERR) 1452 #define wr_fig_merit(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd241,0x00ff,0,wr_val) 1453 #define rd_pf2_lowp_ctrl_g2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd242,0,13,__ERR) 1454 #define wr_pf2_lowp_ctrl_g2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd242,0xe000,13,wr_val) 1455 #define rd_rx_pf_hiz_g2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd242,3,15,__ERR) 1456 #define wr_rx_pf_hiz_g2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd242,0x1000,12,wr_val) 1457 #define rd_pf_ctrl_g2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd242,4,12,__ERR) 1458 #define wr_pf_ctrl_g2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd242,0x0f00,8,wr_val) 1459 #define rd_pf2_lowp_ctrl_g1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd242,8,13,__ERR) 1460 #define wr_pf2_lowp_ctrl_g1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd242,0x00e0,5,wr_val) 1461 #define rd_rx_pf_hiz_g1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd242,11,15,__ERR) 1462 #define wr_rx_pf_hiz_g1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd242,0x0010,4,wr_val) 1463 #define rd_pf_ctrl_g1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd242,12,12,__ERR) 1464 #define wr_pf_ctrl_g1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd242,0x000f,0,wr_val) 1465 #define rd_rx_en_dfe_clk_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd243,2,15,__ERR) 1466 #define wr_rx_en_dfe_clk_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd243,0x2000,13,wr_val) 1467 #define rd_rx_m1_thresh_zero_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd243,3,15,__ERR) 1468 #define wr_rx_m1_thresh_zero_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd243,0x1000,12,wr_val) 1469 #define rd_rx_vga3_ctrl_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd243,4,12,__ERR) 1470 #define wr_rx_vga3_ctrl_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd243,0x0f00,8,wr_val) 1471 #define rd_rx_vga2_ctrl_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd243,8,12,__ERR) 1472 #define wr_rx_vga2_ctrl_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd243,0x00f0,4,wr_val) 1473 #define rd_rx_vga1_ctrl_G1G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd243,12,12,__ERR) 1474 #define wr_rx_vga1_ctrl_G1G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd243,0x000f,0,wr_val) 1475 #define rd_lp_main_coeff() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd244,2,10,__ERR) 1476 #define rd_lp_pre_coeff() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd244,10,10,__ERR) 1477 #define rd_rx_hint() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd245,1,13,__ERR) 1478 #define rd_lp_post_coeff() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd245,10,10,__ERR) 1479 #define rd_tx_lf() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd246,2,10,__ERR) 1480 #define rd_lp_fs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd246,10,10,__ERR) 1481 #define rd_err_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd247,12,15,__ERR) 1482 #define rd_eq_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd247,13,15,__ERR) 1483 #define rd_eval_err() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd247,14,15,__ERR) 1484 #define rd_eq_eval() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd247,15,15,__ERR) 1485 #define rd_rate_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd250,2,14,__ERR) 1486 #define rd_rx_sigdet() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd250,5,13,__ERR) 1487 #define rd_rx_sigdet_st() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd250,8,13,__ERR) 1488 #define rd_uc_dbg_dsc_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd250,11,11,__ERR) 1489 #define rd_micro_dbg1() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd251,0,1,__ERR) 1490 #define wr_micro_dbg1(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd251,0xfffe,1,wr_val) 1491 #define rd_micro_2lane_ena_type() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd251,15,15,__ERR) 1492 #define wr_micro_2lane_ena_type(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd251,0x0001,0,wr_val) 1493 #define rd_micro_dbg2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd252,__ERR) 1494 #define wr_micro_dbg2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd252,wr_val) 1495 #define rd_micro_dbg3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd253,__ERR) 1496 #define wr_micro_dbg3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd253,wr_val) 1497 #define rd_micro_dbg4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd254,__ERR) 1498 #define wr_micro_dbg4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd254,wr_val) 1499 #define rd_micro_dbg5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd255,__ERR) 1500 #define wr_micro_dbg5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd255,wr_val) 1501 #define rd_micro_dbg6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd256,__ERR) 1502 #define wr_micro_dbg6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd256,wr_val) 1503 #define rd_micro_dbg7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd257,__ERR) 1504 #define wr_micro_dbg7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd257,wr_val) 1505 #define rd_micro_dbg8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd258,__ERR) 1506 #define wr_micro_dbg8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd258,wr_val) 1507 #define rd_micro_dbg9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd259,__ERR) 1508 #define wr_micro_dbg9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd259,wr_val) 1509 #define rd_micro_dbg10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25a,__ERR) 1510 #define wr_micro_dbg10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25a,wr_val) 1511 #define rd_micro_dbg11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25b,__ERR) 1512 #define wr_micro_dbg11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25b,wr_val) 1513 #define rd_micro_dbg12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25c,__ERR) 1514 #define wr_micro_dbg12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25c,wr_val) 1515 #define rd_micro_dbg13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25d,__ERR) 1516 #define wr_micro_dbg13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25d,wr_val) 1517 #define rd_micro_dbg14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25e,__ERR) 1518 #define wr_micro_dbg14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25e,wr_val) 1519 #define rdc_uc_version() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd230,__ERR) 1520 #define wrc_uc_version(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd230,wr_val) 1521 #define rdc_err_clr3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,0,15,__ERR) 1522 #define rdc_err_clr2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,1,15,__ERR) 1523 #define rdc_err_clr1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,2,15,__ERR) 1524 #define rdc_err_clr0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,3,15,__ERR) 1525 #define rdc_eq_done_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,4,15,__ERR) 1526 #define rdc_eq_done_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,5,15,__ERR) 1527 #define rdc_eq_done_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,6,15,__ERR) 1528 #define rdc_eq_done_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,7,15,__ERR) 1529 #define rdc_eval_err_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,8,15,__ERR) 1530 #define rdc_eval_err_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,9,15,__ERR) 1531 #define rdc_eval_err_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,10,15,__ERR) 1532 #define rdc_eval_err_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,11,15,__ERR) 1533 #define rdc_eq_eval_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,12,15,__ERR) 1534 #define rdc_eq_eval_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,13,15,__ERR) 1535 #define rdc_eq_eval_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,14,15,__ERR) 1536 #define rdc_eq_eval_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd231,15,15,__ERR) 1537 #define rdc_patt_gen_seq_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd100,__ERR) 1538 #define wrc_patt_gen_seq_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd100,wr_val) 1539 #define rdc_patt_gen_seq_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd101,__ERR) 1540 #define wrc_patt_gen_seq_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd101,wr_val) 1541 #define rdc_patt_gen_seq_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd102,__ERR) 1542 #define wrc_patt_gen_seq_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd102,wr_val) 1543 #define rdc_patt_gen_seq_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd103,__ERR) 1544 #define wrc_patt_gen_seq_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd103,wr_val) 1545 #define rdc_patt_gen_seq_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd104,__ERR) 1546 #define wrc_patt_gen_seq_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd104,wr_val) 1547 #define rdc_patt_gen_seq_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd105,__ERR) 1548 #define wrc_patt_gen_seq_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd105,wr_val) 1549 #define rdc_patt_gen_seq_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd106,__ERR) 1550 #define wrc_patt_gen_seq_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd106,wr_val) 1551 #define rdc_patt_gen_seq_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd107,__ERR) 1552 #define wrc_patt_gen_seq_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd107,wr_val) 1553 #define rdc_patt_gen_seq_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd108,__ERR) 1554 #define wrc_patt_gen_seq_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd108,wr_val) 1555 #define rdc_patt_gen_seq_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd109,__ERR) 1556 #define wrc_patt_gen_seq_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd109,wr_val) 1557 #define rdc_patt_gen_seq_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10a,__ERR) 1558 #define wrc_patt_gen_seq_10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10a,wr_val) 1559 #define rdc_patt_gen_seq_11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10b,__ERR) 1560 #define wrc_patt_gen_seq_11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10b,wr_val) 1561 #define rdc_patt_gen_seq_12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10c,__ERR) 1562 #define wrc_patt_gen_seq_12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10c,wr_val) 1563 #define rdc_patt_gen_seq_13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10d,__ERR) 1564 #define wrc_patt_gen_seq_13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10d,wr_val) 1565 #define rdc_patt_gen_seq_14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10e,__ERR) 1566 #define wrc_patt_gen_seq_14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10e,wr_val) 1567 #define rdexc_rst_sw() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,0,15,__ERR) 1568 #define wrexc_rst_sw(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x8000,15,wr_val) 1569 #define rdexc_rst_sw_UC() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,1,15,__ERR) 1570 #define wrexc_rst_sw_UC(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x4000,14,wr_val) 1571 #define rdexc_rst_sw_MDIO() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,2,15,__ERR) 1572 #define wrexc_rst_sw_MDIO(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x2000,13,wr_val) 1573 #define rdexc_pwrdwn_sw_10g() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,4,15,__ERR) 1574 #define wrexc_pwrdwn_sw_10g(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x0800,11,wr_val) 1575 #define rdexc_pll_tca_master_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,12,15,__ERR) 1576 #define wrexc_pll_tca_master_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x0008,3,wr_val) 1577 #define rdexc_pll_tca_master_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,13,15,__ERR) 1578 #define wrexc_pll_tca_master_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x0004,2,wr_val) 1579 #define rdexc_mdio_rx_hiz_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,14,15,__ERR) 1580 #define wrexc_mdio_rx_hiz_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x0002,1,wr_val) 1581 #define rdexc_mdio_ucclk_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1000,15,15,__ERR) 1582 #define wrexc_mdio_ucclk_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1000,0x0001,0,wr_val) 1583 #define rdexc_rxsigdet() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1003,__ERR) 1584 #define rdexc_ln_status() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1004,__ERR) 1585 #define rdexc_ln_status2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1005,__ERR) 1586 #define rdexc_mdio_ser_SAM_ovrd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1006,15,15,__ERR) 1587 #define wrexc_mdio_ser_SAM_ovrd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1006,0x0001,0,wr_val) 1588 #define rdexc_PllRangeHolding_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1007,0,9,__ERR) 1589 #define rdexc_PllRangeHolding_G3_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1007,7,9,__ERR) 1590 #define rdexc_rate_sel_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1007,14,14,__ERR) 1591 #define rdexc_pgen_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,0,15,__ERR) 1592 #define wrexc_pgen_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x8000,15,wr_val) 1593 #define rdexc_pcmp_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,1,15,__ERR) 1594 #define wrexc_pcmp_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x4000,14,wr_val) 1595 #define rdexc_start_sequencer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,2,15,__ERR) 1596 #define wrexc_start_sequencer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x2000,13,wr_val) 1597 #define rdexc_reset_anlg_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,3,15,__ERR) 1598 #define wrexc_reset_anlg_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x1000,12,wr_val) 1599 #define rdexc_pll_bypass_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,8,15,__ERR) 1600 #define wrexc_pll_bypass_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0080,7,wr_val) 1601 #define rdexc_mdio_iddq_ovrd_select() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,9,15,__ERR) 1602 #define wrexc_mdio_iddq_ovrd_select(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0040,6,wr_val) 1603 #define rdexc_mdio_iddq_ovrd_value() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,10,15,__ERR) 1604 #define wrexc_mdio_iddq_ovrd_value(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0020,5,wr_val) 1605 #define rdexc_mdio_cont_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,11,15,__ERR) 1606 #define wrexc_mdio_cont_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0010,4,wr_val) 1607 #define rdexc_cdet_en10g() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,12,15,__ERR) 1608 #define wrexc_cdet_en10g(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0008,3,wr_val) 1609 #define rdexc_eden10g() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,13,15,__ERR) 1610 #define wrexc_eden10g(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0004,2,wr_val) 1611 #define rdexc_dsc_reset_enable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1100,15,15,__ERR) 1612 #define wrexc_dsc_reset_enable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1100,0x0001,0,wr_val) 1613 #define rdexc_status() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1101,__ERR) 1614 #define rdexc_enable_uC_freeze() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,8,15,__ERR) 1615 #define wrexc_enable_uC_freeze(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0080,7,wr_val) 1616 #define rdexc_deassert_ResetUc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,9,15,__ERR) 1617 #define wrexc_deassert_ResetUc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0040,6,wr_val) 1618 #define rdexc_L1PLLPowerdown_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,10,15,__ERR) 1619 #define wrexc_L1PLLPowerdown_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0020,5,wr_val) 1620 #define rdexc_L1PLLPowerdown_mdio() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,11,15,__ERR) 1621 #define wrexc_L1PLLPowerdown_mdio(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0010,4,wr_val) 1622 #define rdexc_BlockRealignOverride() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,12,15,__ERR) 1623 #define wrexc_BlockRealignOverride(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0008,3,wr_val) 1624 #define rdexc_mdio_G3_BlockRealign() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,13,15,__ERR) 1625 #define wrexc_mdio_G3_BlockRealign(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0004,2,wr_val) 1626 #define rdexc_tx_G3_fts_SDS() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,14,15,__ERR) 1627 #define wrexc_tx_G3_fts_SDS(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0002,1,wr_val) 1628 #define rdexc_tx_G3_fts_no_EIEOS() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1102,15,15,__ERR) 1629 #define wrexc_tx_G3_fts_no_EIEOS(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1102,0x0001,0,wr_val) 1630 #define rdexc_status2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1103,__ERR) 1631 #define rdexc_gpio_sel() _merlin16_pcieg3_pmd_rde_field(sa__, 0x1104,7,7,__ERR) 1632 #define wrexc_gpio_sel(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0x1104,0x01ff,0,wr_val) 1633 #define rdexc_mdio_gpio_sts() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1105,__ERR) 1634 #define rdexc_dbg_lane_sel3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1106,0,12,__ERR) 1635 #define wrexc_dbg_lane_sel3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1106,0xf000,12,wr_val) 1636 #define rdexc_dbg_lane_sel2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1106,4,12,__ERR) 1637 #define wrexc_dbg_lane_sel2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1106,0x0f00,8,wr_val) 1638 #define rdexc_dbg_lane_sel1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1106,8,12,__ERR) 1639 #define wrexc_dbg_lane_sel1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1106,0x00f0,4,wr_val) 1640 #define rdexc_dbg_lane_sel0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1106,12,12,__ERR) 1641 #define wrexc_dbg_lane_sel0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1106,0x000f,0,wr_val) 1642 #define rdexc_dbg_lane_sel7() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1107,0,12,__ERR) 1643 #define wrexc_dbg_lane_sel7(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1107,0xf000,12,wr_val) 1644 #define rdexc_dbg_lane_sel6() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1107,4,12,__ERR) 1645 #define wrexc_dbg_lane_sel6(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1107,0x0f00,8,wr_val) 1646 #define rdexc_dbg_lane_sel5() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1107,8,12,__ERR) 1647 #define wrexc_dbg_lane_sel5(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1107,0x00f0,4,wr_val) 1648 #define rdexc_dbg_lane_sel4() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1107,12,12,__ERR) 1649 #define wrexc_dbg_lane_sel4(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1107,0x000f,0,wr_val) 1650 #define rdexc_dbg_lane_sel11() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1108,0,12,__ERR) 1651 #define wrexc_dbg_lane_sel11(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1108,0xf000,12,wr_val) 1652 #define rdexc_dbg_lane_sel10() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1108,4,12,__ERR) 1653 #define wrexc_dbg_lane_sel10(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1108,0x0f00,8,wr_val) 1654 #define rdexc_dbg_lane_sel9() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1108,8,12,__ERR) 1655 #define wrexc_dbg_lane_sel9(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1108,0x00f0,4,wr_val) 1656 #define rdexc_dbg_lane_sel8() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1108,12,12,__ERR) 1657 #define wrexc_dbg_lane_sel8(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1108,0x000f,0,wr_val) 1658 #define rdexc_dbg_lane_sel15() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1109,0,12,__ERR) 1659 #define wrexc_dbg_lane_sel15(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1109,0xf000,12,wr_val) 1660 #define rdexc_dbg_lane_sel14() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1109,4,12,__ERR) 1661 #define wrexc_dbg_lane_sel14(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1109,0x0f00,8,wr_val) 1662 #define rdexc_dbg_lane_sel13() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1109,8,12,__ERR) 1663 #define wrexc_dbg_lane_sel13(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1109,0x00f0,4,wr_val) 1664 #define rdexc_dbg_lane_sel12() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1109,12,12,__ERR) 1665 #define wrexc_dbg_lane_sel12(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1109,0x000f,0,wr_val) 1666 #define rdexc_dbg_info_sel3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110a,0,12,__ERR) 1667 #define wrexc_dbg_info_sel3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110a,0xf000,12,wr_val) 1668 #define rdexc_dbg_info_sel2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110a,4,12,__ERR) 1669 #define wrexc_dbg_info_sel2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110a,0x0f00,8,wr_val) 1670 #define rdexc_dbg_info_sel1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110a,8,12,__ERR) 1671 #define wrexc_dbg_info_sel1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110a,0x00f0,4,wr_val) 1672 #define rdexc_dbg_info_sel0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110a,12,12,__ERR) 1673 #define wrexc_dbg_info_sel0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110a,0x000f,0,wr_val) 1674 #define rdexc_dbg_info_sel7() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110b,0,12,__ERR) 1675 #define wrexc_dbg_info_sel7(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110b,0xf000,12,wr_val) 1676 #define rdexc_dbg_info_sel6() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110b,4,12,__ERR) 1677 #define wrexc_dbg_info_sel6(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110b,0x0f00,8,wr_val) 1678 #define rdexc_dbg_info_sel5() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110b,8,12,__ERR) 1679 #define wrexc_dbg_info_sel5(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110b,0x00f0,4,wr_val) 1680 #define rdexc_dbg_info_sel4() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110b,12,12,__ERR) 1681 #define wrexc_dbg_info_sel4(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110b,0x000f,0,wr_val) 1682 #define rdexc_dbg_info_sel11() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110c,0,12,__ERR) 1683 #define wrexc_dbg_info_sel11(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110c,0xf000,12,wr_val) 1684 #define rdexc_dbg_info_sel10() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110c,4,12,__ERR) 1685 #define wrexc_dbg_info_sel10(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110c,0x0f00,8,wr_val) 1686 #define rdexc_dbg_info_sel9() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110c,8,12,__ERR) 1687 #define wrexc_dbg_info_sel9(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110c,0x00f0,4,wr_val) 1688 #define rdexc_dbg_info_sel8() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110c,12,12,__ERR) 1689 #define wrexc_dbg_info_sel8(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110c,0x000f,0,wr_val) 1690 #define rdexc_dbg_info_sel15() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110d,0,12,__ERR) 1691 #define wrexc_dbg_info_sel15(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110d,0xf000,12,wr_val) 1692 #define rdexc_dbg_info_sel14() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110d,4,12,__ERR) 1693 #define wrexc_dbg_info_sel14(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110d,0x0f00,8,wr_val) 1694 #define rdexc_dbg_info_sel13() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110d,8,12,__ERR) 1695 #define wrexc_dbg_info_sel13(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110d,0x00f0,4,wr_val) 1696 #define rdexc_dbg_info_sel12() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110d,12,12,__ERR) 1697 #define wrexc_dbg_info_sel12(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110d,0x000f,0,wr_val) 1698 #define rdexc_dbg_misc_tmux_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110e,14,15,__ERR) 1699 #define wrexc_dbg_misc_tmux_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110e,0x0002,1,wr_val) 1700 #define rdexc_dbg_data_ena() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x110e,15,15,__ERR) 1701 #define wrexc_dbg_data_ena(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x110e,0x0001,0,wr_val) 1702 #define rdexc_lfckcnt() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1200,__ERR) 1703 #define wrexc_lfckcnt(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1200,wr_val) 1704 #define rdexc_mdio_LTTSM_NoVoltIsland() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1201,0,8,__ERR) 1705 #define wrexc_mdio_LTTSM_NoVoltIsland(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1201,0xff00,8,wr_val) 1706 #define rdexc_mdio_LTTSM_L23Ready() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1201,8,8,__ERR) 1707 #define wrexc_mdio_LTTSM_L23Ready(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1201,0x00ff,0,wr_val) 1708 #define rdexc_mdio_LTTSM_FwPwrDn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1202,0,8,__ERR) 1709 #define wrexc_mdio_LTTSM_FwPwrDn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1202,0xff00,8,wr_val) 1710 #define rdexc_mdio_LTTSM_LinkPwrDn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1202,8,8,__ERR) 1711 #define wrexc_mdio_LTTSM_LinkPwrDn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1202,0x00ff,0,wr_val) 1712 #define rdexc_mdio_LTTSM_L1NoClkReqPllPwrDn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1203,0,8,__ERR) 1713 #define wrexc_mdio_LTTSM_L1NoClkReqPllPwrDn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1203,0xff00,8,wr_val) 1714 #define rdexc_mdio_LTTSM_L1NoClkReq() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1203,8,8,__ERR) 1715 #define wrexc_mdio_LTTSM_L1NoClkReq(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1203,0x00ff,0,wr_val) 1716 #define rdexc_mdio_LTTSM_P0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1204,0,8,__ERR) 1717 #define wrexc_mdio_LTTSM_P0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1204,0xff00,8,wr_val) 1718 #define rdexc_mdio_LTTSM_L1ClkReq() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1204,8,8,__ERR) 1719 #define wrexc_mdio_LTTSM_L1ClkReq(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1204,0x00ff,0,wr_val) 1720 #define rdexc_mdio_RefclkSenseBypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,0,15,__ERR) 1721 #define wrexc_mdio_RefclkSenseBypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x8000,15,wr_val) 1722 #define rdexc_mdio_TxIdleCtrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,1,12,__ERR) 1723 #define wrexc_mdio_TxIdleCtrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x7800,11,wr_val) 1724 #define rdexc_mdio_ClkReq_tmp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,5,15,__ERR) 1725 #define wrexc_mdio_ClkReq_tmp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0400,10,wr_val) 1726 #define rdexc_mdio_ClkReqMdioSel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,6,15,__ERR) 1727 #define wrexc_mdio_ClkReqMdioSel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0200,9,wr_val) 1728 #define rdexc_mdio_AuxClkEnable_tmp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,7,15,__ERR) 1729 #define wrexc_mdio_AuxClkEnable_tmp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0100,8,wr_val) 1730 #define rdexc_mdio_AuxClkEnableMdioSel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,8,15,__ERR) 1731 #define wrexc_mdio_AuxClkEnableMdioSel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0080,7,wr_val) 1732 #define rdexc_mdio_AuxPowerDownP1PllEnableMdioSel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,9,15,__ERR) 1733 #define wrexc_mdio_AuxPowerDownP1PllEnableMdioSel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0040,6,wr_val) 1734 #define rdexc_mdio_LTTSM_L1AnaPwrDnPll() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,10,13,__ERR) 1735 #define wrexc_mdio_LTTSM_L1AnaPwrDnPll(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0038,3,wr_val) 1736 #define rdexc_mdio_LTTSM_L1AnaPwrDn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1205,13,13,__ERR) 1737 #define wrexc_mdio_LTTSM_L1AnaPwrDn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1205,0x0007,0,wr_val) 1738 #define rdexc_mdio_pwrdn_pll_timer_dfs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1206,0,8,__ERR) 1739 #define wrexc_mdio_pwrdn_pll_timer_dfs(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1206,0xff00,8,wr_val) 1740 #define rdexc_mdio_RcPllPd_ovrd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1206,8,15,__ERR) 1741 #define wrexc_mdio_RcPllPd_ovrd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1206,0x0080,7,wr_val) 1742 #define rdexc_mdio_RcPllPd_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1206,9,15,__ERR) 1743 #define wrexc_mdio_RcPllPd_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1206,0x0040,6,wr_val) 1744 #define rdexc_mdio_tx_cmn_mode_force_P2ClkReqEntry_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1206,10,15,__ERR) 1745 #define wrexc_mdio_tx_cmn_mode_force_P2ClkReqEntry_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1206,0x0020,5,wr_val) 1746 #define rdexc_mdio_RefclkSense_onecomp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1206,14,15,__ERR) 1747 #define wrexc_mdio_RefclkSense_onecomp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1206,0x0002,1,wr_val) 1748 #define rdexc_mdio_RefclkSenseEventClr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1206,15,15,__ERR) 1749 #define wrexc_mdio_RefclkSenseEventClr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1206,0x0001,0,wr_val) 1750 #define rdexc_mdio_pwrdn_refclk_timer_dfs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1207,0,8,__ERR) 1751 #define wrexc_mdio_pwrdn_refclk_timer_dfs(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1207,0xff00,8,wr_val) 1752 #define rdexc_mdio_pwr_mgmt_spare_dfs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1207,8,12,__ERR) 1753 #define wrexc_mdio_pwr_mgmt_spare_dfs(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1207,0x00f0,4,wr_val) 1754 #define rdexc_mdio_pm_P2_Wait4Pclk_tmr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1207,12,12,__ERR) 1755 #define wrexc_mdio_pm_P2_Wait4Pclk_tmr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1207,0x000f,0,wr_val) 1756 #define rdexc_mdio_RefclkSense_M() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1208,__ERR) 1757 #define wrexc_mdio_RefclkSense_M(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1208,wr_val) 1758 #define rdexc_mdio_RefclkSense_N() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1209,__ERR) 1759 #define wrexc_mdio_RefclkSense_N(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1209,wr_val) 1760 #define rdexc_mdio_RefclkSenseEventCnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x120a,12,12,__ERR) 1761 #define rdexc_mdio_RefclkSenseCnt() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x120b,__ERR) 1762 #define rdexc_mdio_byp_pipe_io() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,0,15,__ERR) 1763 #define wrexc_mdio_byp_pipe_io(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x8000,15,wr_val) 1764 #define rdexc_pwrdown_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,1,15,__ERR) 1765 #define wrexc_pwrdown_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x4000,14,wr_val) 1766 #define rdexc_tx_idle_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,2,15,__ERR) 1767 #define wrexc_tx_idle_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x2000,13,wr_val) 1768 #define rdexc_rloop_pipe_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,3,15,__ERR) 1769 #define wrexc_rloop_pipe_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x1000,12,wr_val) 1770 #define rdexc_gloop_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,4,15,__ERR) 1771 #define wrexc_gloop_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0800,11,wr_val) 1772 #define rdexc_tx_comp_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,5,15,__ERR) 1773 #define wrexc_tx_comp_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0400,10,wr_val) 1774 #define rdexc_mdio_RxElectIdleRloopEn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,8,15,__ERR) 1775 #define wrexc_mdio_RxElectIdleRloopEn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0080,7,wr_val) 1776 #define rdexc_StandAloneMode_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,9,15,__ERR) 1777 #define wrexc_StandAloneMode_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0040,6,wr_val) 1778 #define rdexc_PllTuningBypass_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,10,15,__ERR) 1779 #define wrexc_PllTuningBypass_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0020,5,wr_val) 1780 #define rdexc_lfck_rx_sel_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,11,15,__ERR) 1781 #define wrexc_lfck_rx_sel_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0010,4,wr_val) 1782 #define rdexc_mdio_DeviceType_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,12,15,__ERR) 1783 #define wrexc_mdio_DeviceType_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0008,3,wr_val) 1784 #define rdexc_mdio_DeviceType() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1300,13,13,__ERR) 1785 #define wrexc_mdio_DeviceType(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1300,0x0007,0,wr_val) 1786 #define rdexc_spares_pcie3_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,0,10,__ERR) 1787 #define wrexc_spares_pcie3_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0xfc00,10,wr_val) 1788 #define rdexc_mdio_pmi_select_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,6,15,__ERR) 1789 #define wrexc_mdio_pmi_select_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0x0200,9,wr_val) 1790 #define rdexc_mdio_pmi_select_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,7,15,__ERR) 1791 #define wrexc_mdio_pmi_select_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0x0100,8,wr_val) 1792 #define rdexc_mdio_RC_refclk_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,11,15,__ERR) 1793 #define wrexc_mdio_RC_refclk_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0x0010,4,wr_val) 1794 #define rdexc_mdio_RC_refclk_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,12,15,__ERR) 1795 #define wrexc_mdio_RC_refclk_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0x0008,3,wr_val) 1796 #define rdexc_RateSelect_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,13,15,__ERR) 1797 #define wrexc_RateSelect_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0x0004,2,wr_val) 1798 #define rdexc_mdioRateSelect() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1301,14,14,__ERR) 1799 #define wrexc_mdioRateSelect(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1301,0x0003,0,wr_val) 1800 #define rdexc_spares_pcie3_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1302,__ERR) 1801 #define wrexc_spares_pcie3_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1302,wr_val) 1802 #define rdexc_mdio_gloop() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1303,__ERR) 1803 #define wrexc_mdio_gloop(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1303,wr_val) 1804 #define rdexc_rloop1g() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1304,__ERR) 1805 #define wrexc_rloop1g(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1304,wr_val) 1806 #define rdexc_mdio_rloop_pipe() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1305,__ERR) 1807 #define wrexc_mdio_rloop_pipe(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1305,wr_val) 1808 #define rdexc_gen2_ctrl6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1306,__ERR) 1809 #define wrexc_gen2_ctrl6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1306,wr_val) 1810 #define rdexc_DisablePmRxFastAcq() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1307,__ERR) 1811 #define wrexc_DisablePmRxFastAcq(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1307,wr_val) 1812 #define rdexc_mdioRxFastAcqEnable() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1308,__ERR) 1813 #define wrexc_mdioRxFastAcqEnable(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1308,wr_val) 1814 #define rdexc_mdioRxSeqStart() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1309,__ERR) 1815 #define wrexc_mdioRxSeqStart(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1309,wr_val) 1816 #define rdexc_mdio_TxElectIdle_r() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130a,__ERR) 1817 #define wrexc_mdio_TxElectIdle_r(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130a,wr_val) 1818 #define rdexc_mdio_TxComp_r() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130b,__ERR) 1819 #define wrexc_mdio_TxComp_r(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130b,wr_val) 1820 #define rdexc_mdio_PowerDown_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130c,__ERR) 1821 #define wrexc_mdio_PowerDown_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130c,wr_val) 1822 #define rdexc_mdio_PowerDown_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130d,__ERR) 1823 #define wrexc_mdio_PowerDown_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130d,wr_val) 1824 #define rdexc_gen2_ctrl14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130e,__ERR) 1825 #define wrexc_gen2_ctrl14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130e,wr_val) 1826 #define rdexc_lane_ctrl0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1400,__ERR) 1827 #define wrexc_lane_ctrl0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1400,wr_val) 1828 #define rdexc_lane_ctrl1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1401,__ERR) 1829 #define wrexc_lane_ctrl1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1401,wr_val) 1830 #define rdexc_eden1g() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1402,__ERR) 1831 #define wrexc_eden1g(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1402,wr_val) 1832 #define rdexc_cdet_en1g() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1403,__ERR) 1833 #define wrexc_cdet_en1g(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1403,wr_val) 1834 #define rdexc_pwrdwn_rx_r() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1404,__ERR) 1835 #define wrexc_pwrdwn_rx_r(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1404,wr_val) 1836 #define rdexc_pwrdwn_tx_r() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1405,__ERR) 1837 #define wrexc_pwrdwn_tx_r(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1405,wr_val) 1838 #define rdexc_pwrdwn_10g_pll_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1406,14,15,__ERR) 1839 #define wrexc_pwrdwn_10g_pll_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1406,0x0002,1,wr_val) 1840 #define rdexc_pwrdwn_pll_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1406,15,15,__ERR) 1841 #define wrexc_pwrdwn_pll_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1406,0x0001,0,wr_val) 1842 #define rdexc_rst_sw_ln() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1407,__ERR) 1843 #define wrexc_rst_sw_ln(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1407,wr_val) 1844 #define rdexc_reset_anlg_r_ln() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1408,__ERR) 1845 #define wrexc_reset_anlg_r_ln(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1408,wr_val) 1846 #define rdexc_mdio_cont_en3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1409,4,15,__ERR) 1847 #define wrexc_mdio_cont_en3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1409,0x0800,11,wr_val) 1848 #define rdexc_TxBeaconData() _merlin16_pcieg3_pmd_rde_field(sa__, 0x1409,6,6,__ERR) 1849 #define wrexc_TxBeaconData(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0x1409,0x03ff,0,wr_val) 1850 #define rdexc_common_clock_fifo_shrink() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x140a,13,15,__ERR) 1851 #define wrexc_common_clock_fifo_shrink(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x140a,0x0004,2,wr_val) 1852 #define rdexc_gp_in0_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x140a,14,15,__ERR) 1853 #define wrexc_gp_in0_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x140a,0x0002,1,wr_val) 1854 #define rdexc_enable_mdwr4rst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x140a,15,15,__ERR) 1855 #define wrexc_enable_mdwr4rst(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x140a,0x0001,0,wr_val) 1856 #define rdexc_elastic_autorst_en() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140b,__ERR) 1857 #define wrexc_elastic_autorst_en(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140b,wr_val) 1858 #define rdexc_comma_adj_fsm_sel() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140c,__ERR) 1859 #define wrexc_comma_adj_fsm_sel(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140c,wr_val) 1860 #define rdexc_RcvrDetectTimeout() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140d,__ERR) 1861 #define wrexc_RcvrDetectTimeout(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140d,wr_val) 1862 #define rdexc_lane_ctrl14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140e,__ERR) 1863 #define wrexc_lane_ctrl14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140e,wr_val) 1864 #define rdexc_lane_ctrl15() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1500,__ERR) 1865 #define wrexc_lane_ctrl15(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1500,wr_val) 1866 #define rdexc_prbs_en() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1501,__ERR) 1867 #define wrexc_prbs_en(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1501,wr_val) 1868 #define rdexc_prbs_inv() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1502,__ERR) 1869 #define wrexc_prbs_inv(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1502,wr_val) 1870 #define rdexc_prbs_order15a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,0,15,__ERR) 1871 #define wrexc_prbs_order15a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x8000,15,wr_val) 1872 #define rdexc_prbs_order14a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,1,15,__ERR) 1873 #define wrexc_prbs_order14a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x4000,14,wr_val) 1874 #define rdexc_prbs_order13a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,2,15,__ERR) 1875 #define wrexc_prbs_order13a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x2000,13,wr_val) 1876 #define rdexc_prbs_order12a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,3,15,__ERR) 1877 #define wrexc_prbs_order12a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x1000,12,wr_val) 1878 #define rdexc_prbs_order11a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,4,15,__ERR) 1879 #define wrexc_prbs_order11a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0800,11,wr_val) 1880 #define rdexc_prbs_order10a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,5,15,__ERR) 1881 #define wrexc_prbs_order10a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0400,10,wr_val) 1882 #define rdexc_prbs_order9a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,6,15,__ERR) 1883 #define wrexc_prbs_order9a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0200,9,wr_val) 1884 #define rdexc_prbs_order8a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,7,15,__ERR) 1885 #define wrexc_prbs_order8a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0100,8,wr_val) 1886 #define rdexc_prbs_order7a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,8,15,__ERR) 1887 #define wrexc_prbs_order7a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0080,7,wr_val) 1888 #define rdexc_prbs_order6a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,9,15,__ERR) 1889 #define wrexc_prbs_order6a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0040,6,wr_val) 1890 #define rdexc_prbs_order5a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,10,15,__ERR) 1891 #define wrexc_prbs_order5a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0020,5,wr_val) 1892 #define rdexc_prbs_order4a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,11,15,__ERR) 1893 #define wrexc_prbs_order4a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0010,4,wr_val) 1894 #define rdexc_prbs_order3a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,12,15,__ERR) 1895 #define wrexc_prbs_order3a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0008,3,wr_val) 1896 #define rdexc_prbs_order2a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,13,15,__ERR) 1897 #define wrexc_prbs_order2a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0004,2,wr_val) 1898 #define rdexc_prbs_order1a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,14,15,__ERR) 1899 #define wrexc_prbs_order1a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0002,1,wr_val) 1900 #define rdexc_prbs_order0a() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1503,15,15,__ERR) 1901 #define wrexc_prbs_order0a(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1503,0x0001,0,wr_val) 1902 #define rdexc_prbs_order7() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,0,14,__ERR) 1903 #define wrexc_prbs_order7(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0xc000,14,wr_val) 1904 #define rdexc_prbs_order6() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,2,14,__ERR) 1905 #define wrexc_prbs_order6(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x3000,12,wr_val) 1906 #define rdexc_prbs_order5() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,4,14,__ERR) 1907 #define wrexc_prbs_order5(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x0c00,10,wr_val) 1908 #define rdexc_prbs_order4() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,6,14,__ERR) 1909 #define wrexc_prbs_order4(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x0300,8,wr_val) 1910 #define rdexc_prbs_order3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,8,14,__ERR) 1911 #define wrexc_prbs_order3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x00c0,6,wr_val) 1912 #define rdexc_prbs_order2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,10,14,__ERR) 1913 #define wrexc_prbs_order2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x0030,4,wr_val) 1914 #define rdexc_prbs_order1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,12,14,__ERR) 1915 #define wrexc_prbs_order1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x000c,2,wr_val) 1916 #define rdexc_prbs_order0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1504,14,14,__ERR) 1917 #define wrexc_prbs_order0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1504,0x0003,0,wr_val) 1918 #define rdexc_prbs_order15() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,0,14,__ERR) 1919 #define wrexc_prbs_order15(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0xc000,14,wr_val) 1920 #define rdexc_prbs_order14() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,2,14,__ERR) 1921 #define wrexc_prbs_order14(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x3000,12,wr_val) 1922 #define rdexc_prbs_order13() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,4,14,__ERR) 1923 #define wrexc_prbs_order13(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x0c00,10,wr_val) 1924 #define rdexc_prbs_order12() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,6,14,__ERR) 1925 #define wrexc_prbs_order12(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x0300,8,wr_val) 1926 #define rdexc_prbs_order11() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,8,14,__ERR) 1927 #define wrexc_prbs_order11(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x00c0,6,wr_val) 1928 #define rdexc_prbs_order10() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,10,14,__ERR) 1929 #define wrexc_prbs_order10(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x0030,4,wr_val) 1930 #define rdexc_prbs_order9() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,12,14,__ERR) 1931 #define wrexc_prbs_order9(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x000c,2,wr_val) 1932 #define rdexc_prbs_order8() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1505,14,14,__ERR) 1933 #define wrexc_prbs_order8(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1505,0x0003,0,wr_val) 1934 #define rdexc_lfck_sigdet_sel_mdio_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,0,15,__ERR) 1935 #define wrexc_lfck_sigdet_sel_mdio_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x8000,15,wr_val) 1936 #define rdexc_mdio_lfck_sigdet_sel_cnt0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,2,15,__ERR) 1937 #define wrexc_mdio_lfck_sigdet_sel_cnt0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x2000,13,wr_val) 1938 #define rdexc_mdio_lfck_sigdet_sel_refclk() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,3,15,__ERR) 1939 #define wrexc_mdio_lfck_sigdet_sel_refclk(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x1000,12,wr_val) 1940 #define rdexc_ext_pwrdn_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,5,15,__ERR) 1941 #define wrexc_ext_pwrdn_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0400,10,wr_val) 1942 #define rdexc_pwrdn_safe_dis_tmp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,6,15,__ERR) 1943 #define wrexc_pwrdn_safe_dis_tmp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0200,9,wr_val) 1944 #define rdexc_pwrdn_clks_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,7,15,__ERR) 1945 #define wrexc_pwrdn_clks_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0100,8,wr_val) 1946 #define rdexc_pll_lock_rstb_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,9,15,__ERR) 1947 #define wrexc_pll_lock_rstb_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0040,6,wr_val) 1948 #define rdexc_lfck_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,10,15,__ERR) 1949 #define wrexc_lfck_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0020,5,wr_val) 1950 #define rdexc_rx_snoop_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,11,15,__ERR) 1951 #define wrexc_rx_snoop_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0010,4,wr_val) 1952 #define rdexc_mdio_StandAloneMode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,12,15,__ERR) 1953 #define wrexc_mdio_StandAloneMode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0008,3,wr_val) 1954 #define rdexc_mdio_PllTuningBypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,13,15,__ERR) 1955 #define wrexc_mdio_PllTuningBypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0004,2,wr_val) 1956 #define rdexc_mdio_lfck_rx_sel_cnt0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,14,15,__ERR) 1957 #define wrexc_mdio_lfck_rx_sel_cnt0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0002,1,wr_val) 1958 #define rdexc_mdio_lfck_rx_sel_refclk() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1506,15,15,__ERR) 1959 #define wrexc_mdio_lfck_rx_sel_refclk(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1506,0x0001,0,wr_val) 1960 #define rdexc_comp_start() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1507,0,15,__ERR) 1961 #define wrexc_comp_start(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1507,0x8000,15,wr_val) 1962 #define rdexc_tmux_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1507,10,10,__ERR) 1963 #define wrexc_tmux_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1507,0x003f,0,wr_val) 1964 #define rdexc_comp_delay3_11() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1508,0,12,__ERR) 1965 #define wrexc_comp_delay3_11(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1508,0xf000,12,wr_val) 1966 #define rdexc_comp_delay2_10() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1508,4,12,__ERR) 1967 #define wrexc_comp_delay2_10(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1508,0x0f00,8,wr_val) 1968 #define rdexc_comp_delay1_9() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1508,8,12,__ERR) 1969 #define wrexc_comp_delay1_9(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1508,0x00f0,4,wr_val) 1970 #define rdexc_comp_delay0_8() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1508,12,12,__ERR) 1971 #define wrexc_comp_delay0_8(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1508,0x000f,0,wr_val) 1972 #define rdexc_comp_delay7_15() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1509,0,12,__ERR) 1973 #define wrexc_comp_delay7_15(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1509,0xf000,12,wr_val) 1974 #define rdexc_comp_delay6_14() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1509,4,12,__ERR) 1975 #define wrexc_comp_delay6_14(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1509,0x0f00,8,wr_val) 1976 #define rdexc_comp_delay5_13() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1509,8,12,__ERR) 1977 #define wrexc_comp_delay5_13(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1509,0x00f0,4,wr_val) 1978 #define rdexc_comp_delay4_12() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1509,12,12,__ERR) 1979 #define wrexc_comp_delay4_12(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1509,0x000f,0,wr_val) 1980 #define rdexc_comp_type() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x150a,__ERR) 1981 #define wrexc_comp_type(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x150a,wr_val) 1982 #define rdexc_comp_enable() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x150b,__ERR) 1983 #define wrexc_comp_enable(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x150b,wr_val) 1984 #define rdexc_XGXS_fe_tmux() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x150e,__ERR) 1985 #define rdexc_pmd_rx_dme_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1600,0,15,__ERR) 1986 #define wrexc_pmd_rx_dme_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1600,0x8000,15,wr_val) 1987 #define rdexc_pmd_rx_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1600,1,15,__ERR) 1988 #define wrexc_pmd_rx_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1600,0x4000,14,wr_val) 1989 #define rdexc_pmd_tx_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1600,2,14,__ERR) 1990 #define wrexc_pmd_tx_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1600,0x3000,12,wr_val) 1991 #define rdexc_pmd_osr_mode_gen3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1600,4,12,__ERR) 1992 #define wrexc_pmd_osr_mode_gen3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1600,0x0f00,8,wr_val) 1993 #define rdexc_pmd_osr_mode_gen2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1600,8,12,__ERR) 1994 #define wrexc_pmd_osr_mode_gen2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1600,0x00f0,4,wr_val) 1995 #define rdexc_pmd_osr_mode_gen1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1600,12,12,__ERR) 1996 #define wrexc_pmd_osr_mode_gen1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1600,0x000f,0,wr_val) 1997 #define rdexc_pcie_pmd_lane_mode() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1601,__ERR) 1998 #define wrexc_pcie_pmd_lane_mode(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1601,wr_val) 1999 #define rdexc_pcie_pmd_core_mode() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1602,__ERR) 2000 #define wrexc_pcie_pmd_core_mode(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1602,wr_val) 2001 #define rdexc_mdio_pll_lock_dly() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,4,15,__ERR) 2002 #define wrexc_mdio_pll_lock_dly(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x0800,11,wr_val) 2003 #define rdexc_core_config_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,5,15,__ERR) 2004 #define wrexc_core_config_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x0400,10,wr_val) 2005 #define rdexc_core_config_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,6,12,__ERR) 2006 #define wrexc_core_config_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x03c0,6,wr_val) 2007 #define rdexc_tca_use_ext_pd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,10,15,__ERR) 2008 #define wrexc_tca_use_ext_pd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x0020,5,wr_val) 2009 #define rdexc_ref_cmos_clk_HZ() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,11,15,__ERR) 2010 #define wrexc_ref_cmos_clk_HZ(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x0010,4,wr_val) 2011 #define rdexc_refsel_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,12,15,__ERR) 2012 #define wrexc_refsel_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x0008,3,wr_val) 2013 #define rdexc_refsel_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1603,13,13,__ERR) 2014 #define wrexc_refsel_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1603,0x0007,0,wr_val) 2015 #define rdexc_tx_coeff_lo() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1700,__ERR) 2016 #define wrexc_tx_coeff_lo(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1700,wr_val) 2017 #define rdexc_tx_coeff_ovrd_ena() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1701,0,15,__ERR) 2018 #define wrexc_tx_coeff_ovrd_ena(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1701,0x8000,15,wr_val) 2019 #define rdexc_tx_coeff_hi() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1701,10,10,__ERR) 2020 #define wrexc_tx_coeff_hi(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1701,0x003f,0,wr_val) 2021 #define rdexc_rx_clk_repeater_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1702,__ERR) 2022 #define wrexc_rx_clk_repeater_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1702,wr_val) 2023 #define rdexc_rx_clk_repeater_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1703,__ERR) 2024 #define wrexc_rx_clk_repeater_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1703,wr_val) 2025 #define rdexc_rx_clk_repeater_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1704,__ERR) 2026 #define wrexc_rx_clk_repeater_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1704,wr_val) 2027 #define rdexc_rx_clk_repeater_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1705,__ERR) 2028 #define wrexc_rx_clk_repeater_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1705,wr_val) 2029 #define rdexc_rx_clk_repeater_BW_gen12() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1706,14,14,__ERR) 2030 #define wrexc_rx_clk_repeater_BW_gen12(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1706,0x0003,0,wr_val) 2031 #define rdexc_rx_clk_repeater_BW_gen3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x1706,12,14,__ERR) 2032 #define wrexc_rx_clk_repeater_BW_gen3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x1706,0x000c,2,wr_val) 2033 #define rdexc_spare_bits() _merlin16_pcieg3_pmd_rde_field(sa__, 0x1706,0,4,__ERR) 2034 #define wrexc_spare_bits(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0x1706,0xfff0,4,wr_val) 2035 #define rdexc_spare_ctrl0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1707,__ERR) 2036 #define wrexc_spare_ctrl0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1707,wr_val) 2037 #define rdexc_spare_ctrl1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1708,__ERR) 2038 #define wrexc_spare_ctrl1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1708,wr_val) 2039 #define rdexc_spare_ctrl2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1709,__ERR) 2040 #define wrexc_spare_ctrl2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1709,wr_val) 2041 #define rdexc_spare_ctrl3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x170a,__ERR) 2042 #define wrexc_spare_ctrl3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x170a,wr_val) 2043 #define rdc_cal_th() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd120,0,14,__ERR) 2044 #define wrc_cal_th(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd120,0xc000,14,wr_val) 2045 #define rdc_pll_cal_jump_ena() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd120,2,15,__ERR) 2046 #define wrc_pll_cal_jump_ena(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd120,0x2000,13,wr_val) 2047 #define rdc_calib_step_time() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd120,3,3,__ERR) 2048 #define wrc_calib_step_time(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd120,0x1fff,0,wr_val) 2049 #define rdc_freqdet_time() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd121,__ERR) 2050 #define wrc_freqdet_time(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd121,wr_val) 2051 #define rdc_calib_cap_charge_time() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd122,4,4,__ERR) 2052 #define wrc_calib_cap_charge_time(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd122,0x0fff,0,wr_val) 2053 #define rdc_ext_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd123,0,12,__ERR) 2054 #define wrc_ext_state(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd123,0xf000,12,wr_val) 2055 #define rdc_accel_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd123,4,15,__ERR) 2056 #define wrc_accel_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd123,0x0800,11,wr_val) 2057 #define rdc_debug_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd123,5,15,__ERR) 2058 #define wrc_debug_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd123,0x0400,10,wr_val) 2059 #define rdc_freqdet_time_msb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd123,6,15,__ERR) 2060 #define wrc_freqdet_time_msb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd123,0x0200,9,wr_val) 2061 #define rdc_freqdet_win() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd123,8,8,__ERR) 2062 #define wrc_freqdet_win(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd123,0x00ff,0,wr_val) 2063 #define rdc_halfstep_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,0,15,__ERR) 2064 #define wrc_halfstep_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x8000,15,wr_val) 2065 #define rdc_pll_force_cap_pass_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,1,15,__ERR) 2066 #define wrc_pll_force_cap_pass_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x4000,14,wr_val) 2067 #define rdc_pll_force_cap_pass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,2,15,__ERR) 2068 #define wrc_pll_force_cap_pass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x2000,13,wr_val) 2069 #define rdc_cal_pause_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,3,15,__ERR) 2070 #define wrc_cal_pause_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x1000,12,wr_val) 2071 #define rdc_cal_pause_rel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,4,15,__ERR) 2072 #define wrc_cal_pause_rel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x0800,11,wr_val) 2073 #define rdc_cap_delay() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,5,15,__ERR) 2074 #define wrc_cap_delay(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x0400,10,wr_val) 2075 #define rdc_calib_start() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,6,15,__ERR) 2076 #define wrc_calib_start(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x0200,9,wr_val) 2077 #define rdc_en_calib_n() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,7,15,__ERR) 2078 #define wrc_en_calib_n(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x0100,8,wr_val) 2079 #define rdc_ext_range() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd124,9,9,__ERR) 2080 #define wrc_ext_range(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd124,0x007f,0,wr_val) 2081 #define rdc_pll_seq_start() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,0,15,__ERR) 2082 #define wrc_pll_seq_start(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x8000,15,wr_val) 2083 #define rdc_lkdt_pause_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,1,15,__ERR) 2084 #define wrc_lkdt_pause_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x4000,14,wr_val) 2085 #define rdc_lkdt_pause_rel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,2,15,__ERR) 2086 #define wrc_lkdt_pause_rel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x2000,13,wr_val) 2087 #define rdc_vco_rst_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,3,15,__ERR) 2088 #define wrc_vco_rst_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x1000,12,wr_val) 2089 #define rdc_autocal_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,7,15,__ERR) 2090 #define wrc_autocal_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x0100,8,wr_val) 2091 #define rdc_autocal_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,8,13,__ERR) 2092 #define wrc_autocal_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x00e0,5,wr_val) 2093 #define rdc_lkdt_byp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,11,15,__ERR) 2094 #define wrc_lkdt_byp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x0010,4,wr_val) 2095 #define rdc_pll_lock_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,12,15,__ERR) 2096 #define wrc_pll_lock_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x0008,3,wr_val) 2097 #define rdc_pll_lock_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,13,15,__ERR) 2098 #define wrc_pll_lock_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x0004,2,wr_val) 2099 #define rdc_pllforce_fdone() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,14,15,__ERR) 2100 #define wrc_pllforce_fdone(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x0002,1,wr_val) 2101 #define rdc_pllforce_fdone_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd125,15,15,__ERR) 2102 #define wrc_pllforce_fdone_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd125,0x0001,0,wr_val) 2103 #define rdc_band_iqbuf_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd126,8,15,__ERR) 2104 #define wrc_band_iqbuf_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd126,0x0080,7,wr_val) 2105 #define rdc_vcorange_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd126,9,15,__ERR) 2106 #define wrc_vcorange_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd126,0x0040,6,wr_val) 2107 #define rdc_vcobufpon_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd126,10,15,__ERR) 2108 #define wrc_vcobufpon_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd126,0x0020,5,wr_val) 2109 #define rdc_vcopon_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd126,12,15,__ERR) 2110 #define wrc_vcopon_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd126,0x0008,3,wr_val) 2111 #define rdc_pllpon_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd126,14,15,__ERR) 2112 #define wrc_pllpon_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd126,0x0002,1,wr_val) 2113 #define rdc_pll_fail_stky() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd128,0,15,__ERR) 2114 #define rdc_cal_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd128,1,12,__ERR) 2115 #define rdc_cal_valid() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd128,5,15,__ERR) 2116 #define rdc_pll_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd128,6,15,__ERR) 2117 #define rdc_pll_lock_bar_stky() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd128,7,15,__ERR) 2118 #define rdc_pll_range() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd128,9,9,__ERR) 2119 #define rdc_lkdtref_counter_msb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd129,0,15,__ERR) 2120 #define rdc_lkdtvco_counter_msb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd129,1,15,__ERR) 2121 #define rdc_calref_counter() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd129,3,3,__ERR) 2122 #define rdc_band_iqbuf_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd12a,0,13,__ERR) 2123 #define rdc_calvco_counter() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd12a,3,3,__ERR) 2124 #define rdc_lkdtref_counter() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12b,__ERR) 2125 #define rdc_lkdtvco_counter() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12c,__ERR) 2126 #define rdc_vcobufpon_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd12d,2,12,__ERR) 2127 #define rdc_calstate_onehot() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd12d,6,6,__ERR) 2128 #define rdc_pll_pwrdn_or() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd12e,0,15,__ERR) 2129 #define rdc_vco_range_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd12e,1,9,__ERR) 2130 #define rdc_vcopon_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd12e,8,12,__ERR) 2131 #define rdc_pllpon_mux() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd12e,12,12,__ERR) 2132 #define rdexc_reg_desc() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x0000,__ERR) 2133 #define wrexc_reg_desc(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x0000,wr_val) 2134 #define rd_afe_sigdet_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd161,14,15,__ERR) 2135 #define wr_afe_sigdet_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd161,0x0002,1,wr_val) 2136 #define rd_ln_rx_s_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd161,15,15,__ERR) 2137 #define wr_ln_rx_s_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd161,0x0001,0,wr_val) 2138 #define rd_pmd_rx_clk_vld_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd167,11,15,__ERR) 2139 #define wr_pmd_rx_clk_vld_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd167,0x0010,4,wr_val) 2140 #define rd_pmd_rx_clk_vld_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd167,12,15,__ERR) 2141 #define wr_pmd_rx_clk_vld_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd167,0x0008,3,wr_val) 2142 #define rd_ln_rx_s_comclk_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd167,13,15,__ERR) 2143 #define wr_ln_rx_s_comclk_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd167,0x0004,2,wr_val) 2144 #define rd_ln_rx_s_comclk_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd167,14,15,__ERR) 2145 #define wr_ln_rx_s_comclk_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd167,0x0002,1,wr_val) 2146 #define rd_ln_rx_s_clkgate_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd167,15,15,__ERR) 2147 #define wr_ln_rx_s_clkgate_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd167,0x0001,0,wr_val) 2148 #define rd_sigdet_dp_rstb_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd164,13,15,__ERR) 2149 #define wr_sigdet_dp_rstb_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd164,0x0004,2,wr_val) 2150 #define rd_ln_rx_dp_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd164,14,15,__ERR) 2151 #define wr_ln_rx_dp_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd164,0x0002,1,wr_val) 2152 #define rd_ln_rx_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd164,15,15,__ERR) 2153 #define wr_ln_rx_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd164,0x0001,0,wr_val) 2154 #define rd_afe_rx_reset_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd162,12,15,__ERR) 2155 #define wr_afe_rx_reset_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd162,0x0008,3,wr_val) 2156 #define rd_afe_rx_reset_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd162,13,15,__ERR) 2157 #define wr_afe_rx_reset_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd162,0x0004,2,wr_val) 2158 #define rd_afe_rx_pwrdn_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd162,14,15,__ERR) 2159 #define wr_afe_rx_pwrdn_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd162,0x0002,1,wr_val) 2160 #define rd_afe_rx_pwrdn_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd162,15,15,__ERR) 2161 #define wr_afe_rx_pwrdn_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd162,0x0001,0,wr_val) 2162 #define rd_pmd_ln_rx_h_pwrdn_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd163,15,15,__ERR) 2163 #define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd163,0x0001,0,wr_val) 2164 #define rd_pmd_lane_mode() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd168,__ERR) 2165 #define rd_afe_rx_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd16c,14,15,__ERR) 2166 #define rd_afe_rx_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd16c,15,15,__ERR) 2167 #define rdex_status1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7000,__ERR) 2168 #define rdex_status_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7001,__ERR) 2169 #define rdex_status3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7002,__ERR) 2170 #define rdex_Status1Sel_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7003,0,13,__ERR) 2171 #define wrex_Status1Sel_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7003,0xe000,13,wr_val) 2172 #define rdex_testMuxSelect_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7003,4,12,__ERR) 2173 #define wrex_testMuxSelect_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7003,0x0f00,8,wr_val) 2174 #define rdex_tpctrl_SM0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7003,8,15,__ERR) 2175 #define wrex_tpctrl_SM0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7003,0x0080,7,wr_val) 2176 #define rdex_tpctrl_SM1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7003,9,13,__ERR) 2177 #define wrex_tpctrl_SM1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7003,0x0070,4,wr_val) 2178 #define rdex_mdio_rx_G3_RxDataValidRealign() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7003,12,15,__ERR) 2179 #define wrex_mdio_rx_G3_RxDataValidRealign(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7003,0x0008,3,wr_val) 2180 #define rdex_Status2Sel_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7003,13,13,__ERR) 2181 #define wrex_Status2Sel_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7003,0x0007,0,wr_val) 2182 #define rdex_forceDecodeOn_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,0,15,__ERR) 2183 #define wrex_forceDecodeOn_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x8000,15,wr_val) 2184 #define rdex_err_max_cnt_sel_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,5,13,__ERR) 2185 #define wrex_err_max_cnt_sel_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0700,8,wr_val) 2186 #define rdex_clear_err_cnt_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,8,15,__ERR) 2187 #define wrex_clear_err_cnt_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0080,7,wr_val) 2188 #define rdex_auto_clear_err_cnt_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,9,15,__ERR) 2189 #define wrex_auto_clear_err_cnt_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0040,6,wr_val) 2190 #define rdex_mdio_ckcmp_mdio_rst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,12,15,__ERR) 2191 #define wrex_mdio_ckcmp_mdio_rst(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0008,3,wr_val) 2192 #define rdex_mdio_ckcmp_afrst_ptr_err_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,13,15,__ERR) 2193 #define wrex_mdio_ckcmp_afrst_ptr_err_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0004,2,wr_val) 2194 #define rdex_mdio_ckcmp_afrst_phaseptr_err_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,14,15,__ERR) 2195 #define wrex_mdio_ckcmp_afrst_phaseptr_err_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0002,1,wr_val) 2196 #define rdex_mdio_ckcmp_phase_only_en_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7004,15,15,__ERR) 2197 #define wrex_mdio_ckcmp_phase_only_en_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7004,0x0001,0,wr_val) 2198 #define rdex_prbs_seed_ld_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,0,15,__ERR) 2199 #define wrex_prbs_seed_ld_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x8000,15,wr_val) 2200 #define rdex_packet_count_en_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,1,15,__ERR) 2201 #define wrex_packet_count_en_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x4000,14,wr_val) 2202 #define rdex_RxErrDisparity_dis_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,2,15,__ERR) 2203 #define wrex_RxErrDisparity_dis_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x2000,13,wr_val) 2204 #define rdex_prbs_clr_dis_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,3,15,__ERR) 2205 #define wrex_prbs_clr_dis_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x1000,12,wr_val) 2206 #define rdex_rxd_dec_sel_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,4,15,__ERR) 2207 #define wrex_rxd_dec_sel_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0800,11,wr_val) 2208 #define rdex_cgbad_tst_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,5,15,__ERR) 2209 #define wrex_cgbad_tst_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0400,10,wr_val) 2210 #define rdex_Emon_en_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,6,15,__ERR) 2211 #define wrex_Emon_en_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0200,9,wr_val) 2212 #define rdex_prbs_en_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,7,15,__ERR) 2213 #define wrex_prbs_en_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0100,8,wr_val) 2214 #define rdex_cgbad_en_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,8,15,__ERR) 2215 #define wrex_cgbad_en_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0080,7,wr_val) 2216 #define rdex_fpat_md_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,9,15,__ERR) 2217 #define wrex_fpat_md_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0040,6,wr_val) 2218 #define rdex_useRxSeqDone_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,10,15,__ERR) 2219 #define wrex_useRxSeqDone_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0020,5,wr_val) 2220 #define rdex_useSigdet_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,11,15,__ERR) 2221 #define wrex_useSigdet_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0010,4,wr_val) 2222 #define rdex_commonClockMode_force_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,14,15,__ERR) 2223 #define wrex_commonClockMode_force_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0002,1,wr_val) 2224 #define rdex_commonClockMode_force_value() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7005,15,15,__ERR) 2225 #define wrex_commonClockMode_force_value(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7005,0x0001,0,wr_val) 2226 #define rdex_prbs_L0s_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,0,15,__ERR) 2227 #define wrex_prbs_L0s_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x8000,15,wr_val) 2228 #define rdex_comma_mask_force_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,1,15,__ERR) 2229 #define wrex_comma_mask_force_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x4000,14,wr_val) 2230 #define rdex_comma_mask_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,2,15,__ERR) 2231 #define wrex_comma_mask_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x2000,13,wr_val) 2232 #define rdex_statMuxRegDis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,3,15,__ERR) 2233 #define wrex_statMuxRegDis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x1000,12,wr_val) 2234 #define rdex_sync_status_force_r_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,4,15,__ERR) 2235 #define wrex_sync_status_force_r_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0800,11,wr_val) 2236 #define rdex_sync_status_force_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,5,15,__ERR) 2237 #define wrex_sync_status_force_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0400,10,wr_val) 2238 #define rdex_comma_adj_en_force_ext_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,6,15,__ERR) 2239 #define wrex_comma_adj_en_force_ext_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0200,9,wr_val) 2240 #define rdex_comma_adj_en_force_sync_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,7,15,__ERR) 2241 #define wrex_comma_adj_en_force_sync_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0100,8,wr_val) 2242 #define rdex_comma_adj_en_force_r_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,8,15,__ERR) 2243 #define wrex_comma_adj_en_force_r_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0080,7,wr_val) 2244 #define rdex_comma_adj_en_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,9,15,__ERR) 2245 #define wrex_comma_adj_en_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0040,6,wr_val) 2246 #define rdex_link_en_force_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,10,15,__ERR) 2247 #define wrex_link_en_force_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0020,5,wr_val) 2248 #define rdex_link_en_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,11,15,__ERR) 2249 #define wrex_link_en_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0010,4,wr_val) 2250 #define rdex_rx_polarity_force_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,12,15,__ERR) 2251 #define wrex_rx_polarity_force_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0008,3,wr_val) 2252 #define rdex_rx_polarity_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,13,15,__ERR) 2253 #define wrex_rx_polarity_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0004,2,wr_val) 2254 #define rdex_rxd1g_dec_dis_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7006,15,15,__ERR) 2255 #define wrex_rxd1g_dec_dis_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7006,0x0001,0,wr_val) 2256 #define rdex_mdio_tcSelect() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7007,0,8,__ERR) 2257 #define wrex_mdio_tcSelect(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7007,0xff00,8,wr_val) 2258 #define rdex_ana_rx_mdio_sel_fts_L0S() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7007,8,15,__ERR) 2259 #define wrex_ana_rx_mdio_sel_fts_L0S(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7007,0x0080,7,wr_val) 2260 #define rdex_mdio_DisableOvUnFlow() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7007,9,15,__ERR) 2261 #define wrex_mdio_DisableOvUnFlow(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7007,0x0040,6,wr_val) 2262 #define rdex_mdio_rx_G3_BlockStatusDis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7007,10,15,__ERR) 2263 #define wrex_mdio_rx_G3_BlockStatusDis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7007,0x0020,5,wr_val) 2264 #define rdex_ana_rx_mdio_sel_com_num() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7008,0,14,__ERR) 2265 #define wrex_ana_rx_mdio_sel_com_num(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7008,0xc000,14,wr_val) 2266 #define rdex_ckcmp_event_clr_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7008,7,15,__ERR) 2267 #define wrex_ckcmp_event_clr_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7008,0x0100,8,wr_val) 2268 #define rdex_ckcmp_wr_event_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7008,8,12,__ERR) 2269 #define wrex_ckcmp_wr_event_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7008,0x00f0,4,wr_val) 2270 #define rdex_ckcmp_rd_event_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7008,12,12,__ERR) 2271 #define wrex_ckcmp_rd_event_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7008,0x000f,0,wr_val) 2272 #define rdex_rg_gbox_sw_rst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,2,15,__ERR) 2273 #define wrex_rg_gbox_sw_rst(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x2000,13,wr_val) 2274 #define rdex_rx_gbox_afrst_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,3,15,__ERR) 2275 #define wrex_rx_gbox_afrst_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x1000,12,wr_val) 2276 #define rdex_lsm_sh_invalid_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,4,13,__ERR) 2277 #define wrex_lsm_sh_invalid_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x0e00,9,wr_val) 2278 #define rdex_lsm_tm_clk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,7,15,__ERR) 2279 #define wrex_lsm_tm_clk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x0100,8,wr_val) 2280 #define rdex_lsm_tm_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,8,12,__ERR) 2281 #define wrex_lsm_tm_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x00f0,4,wr_val) 2282 #define rdex_lsm_sreg_field_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,12,14,__ERR) 2283 #define wrex_lsm_sreg_field_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x000c,2,wr_val) 2284 #define rdex_lsm_afrst_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,14,15,__ERR) 2285 #define wrex_lsm_afrst_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x0002,1,wr_val) 2286 #define rdex_lsm_sw_frst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7200,15,15,__ERR) 2287 #define wrex_lsm_sw_frst(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x7200,0x0001,0,wr_val) 2288 #define rdex_lsm_status() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7201,__ERR) 2289 #define rdex_rx_gbox_afrst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7202,13,15,__ERR) 2290 #define rdex_rx_gbox_unflow() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7202,14,15,__ERR) 2291 #define rdex_rx_gbox_ovflow() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x7202,15,15,__ERR) 2292 #define rd_rx_osr_mode_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd180,0,15,__ERR) 2293 #define wr_rx_osr_mode_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd180,0x8000,15,wr_val) 2294 #define rd_rx_osr_mode_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd180,12,12,__ERR) 2295 #define wr_rx_osr_mode_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd180,0x000f,0,wr_val) 2296 #define rd_rx_ln_dp_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd181,15,15,__ERR) 2297 #define wr_rx_ln_dp_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd181,0x0001,0,wr_val) 2298 #define rd_rx_ln_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd18e,15,15,__ERR) 2299 #define wr_rx_ln_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd18e,0x0001,0,wr_val) 2300 #define rd_pmd_ln_rx_dp_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd183,14,15,__ERR) 2301 #define wr_pmd_ln_rx_dp_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd183,0x0002,1,wr_val) 2302 #define rd_pmd_ln_rx_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd183,15,15,__ERR) 2303 #define wr_pmd_ln_rx_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd183,0x0001,0,wr_val) 2304 #define rd_rx_uc_ack_lane_dp_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd185,14,15,__ERR) 2305 #define wr_rx_uc_ack_lane_dp_reset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd185,0x0002,1,wr_val) 2306 #define rd_rx_uc_ack_lane_cfg_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd185,15,15,__ERR) 2307 #define wr_rx_uc_ack_lane_cfg_done(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd185,0x0001,0,wr_val) 2308 #define rd_rx_lane_dp_reset_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd189,13,13,__ERR) 2309 #define rd_rx_lane_reg_reset_occurred() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd186,15,15,__ERR) 2310 #define wr_rx_lane_reg_reset_occurred(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd186,0x0001,0,wr_val) 2311 #define rd_rx_multicast_mask_control() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd18a,15,15,__ERR) 2312 #define wr_rx_multicast_mask_control(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd18a,0x0001,0,wr_val) 2313 #define rd_rx_multicast_mask_control_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd18b,11,15,__ERR) 2314 #define rd_rx_osr_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd18b,12,12,__ERR) 2315 #define rd_rx_osr_mode_pin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd18c,12,12,__ERR) 2316 #define rd_osr_mode_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd080,0,15,__ERR) 2317 #define wr_osr_mode_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd080,0x8000,15,wr_val) 2318 #define rd_osr_mode_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd080,12,12,__ERR) 2319 #define wr_osr_mode_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd080,0x000f,0,wr_val) 2320 #define rd_ln_dp_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd081,15,15,__ERR) 2321 #define wr_ln_dp_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd081,0x0001,0,wr_val) 2322 #define rd_ln_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd08e,15,15,__ERR) 2323 #define wr_ln_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd08e,0x0001,0,wr_val) 2324 #define rd_pmd_ln_dp_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd083,14,15,__ERR) 2325 #define wr_pmd_ln_dp_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd083,0x0002,1,wr_val) 2326 #define rd_pmd_ln_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd083,15,15,__ERR) 2327 #define wr_pmd_ln_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd083,0x0001,0,wr_val) 2328 #define rd_uc_ack_lane_dp_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd085,14,15,__ERR) 2329 #define wr_uc_ack_lane_dp_reset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd085,0x0002,1,wr_val) 2330 #define rd_uc_ack_lane_cfg_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd085,15,15,__ERR) 2331 #define wr_uc_ack_lane_cfg_done(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd085,0x0001,0,wr_val) 2332 #define rd_lane_dp_reset_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd089,13,13,__ERR) 2333 #define rd_lane_reg_reset_occurred() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd086,15,15,__ERR) 2334 #define wr_lane_reg_reset_occurred(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd086,0x0001,0,wr_val) 2335 #define rd_multicast_mask_control() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd08a,15,15,__ERR) 2336 #define wr_multicast_mask_control(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd08a,0x0001,0,wr_val) 2337 #define rd_multicast_mask_control_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd08b,11,15,__ERR) 2338 #define rd_osr_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd08b,12,12,__ERR) 2339 #define rd_osr_mode_pin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd08c,12,12,__ERR) 2340 #define rd_rg_sigdet_tsc_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c3,0,15,__ERR) 2341 #define wr_rg_sigdet_tsc_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c3,0x8000,15,wr_val) 2342 #define rd_rg_sigdet_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c3,1,15,__ERR) 2343 #define wr_rg_sigdet_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c3,0x4000,14,wr_val) 2344 #define rd_rg_sigdet_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c3,2,15,__ERR) 2345 #define wr_rg_sigdet_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c3,0x2000,13,wr_val) 2346 #define rd_rg_rxinfeidledis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c3,3,15,__ERR) 2347 #define wr_rg_rxinfeidledis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c3,0x1000,12,wr_val) 2348 #define rd_rg_rxl0sl1failure_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c3,4,15,__ERR) 2349 #define wr_rg_rxl0sl1failure_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c3,0x0800,11,wr_val) 2350 #define rd_rg_rx_afe_pwrdn_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c3,5,15,__ERR) 2351 #define wr_rg_rx_afe_pwrdn_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c3,0x0400,10,wr_val) 2352 #define rd_rg_rxl0sl1failure_cnt() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0c3,6,6,__ERR) 2353 #define wr_rg_rxl0sl1failure_cnt(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd0c3,0x03ff,0,wr_val) 2354 #define rd_rg_sigdet_plllock_tmr() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c4,__ERR) 2355 #define wr_rg_sigdet_plllock_tmr(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c4,wr_val) 2356 #define rd_rg_sigdet_eieos_tmr() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0c5,0,6,__ERR) 2357 #define wr_rg_sigdet_eieos_tmr(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd0c5,0xffc0,6,wr_val) 2358 #define rd_rg_sigdet_wait_tmr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c5,10,10,__ERR) 2359 #define wr_rg_sigdet_wait_tmr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c5,0x003f,0,wr_val) 2360 #define rd_rg_sigdet_tggl_cnt_clr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,0,15,__ERR) 2361 #define wr_rg_sigdet_tggl_cnt_clr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x8000,15,wr_val) 2362 #define rd_rg_sigdet_filter_sel_gen1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,1,15,__ERR) 2363 #define wr_rg_sigdet_filter_sel_gen1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x4000,14,wr_val) 2364 #define rd_rg_sigdet_filter_sel_gen2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,2,15,__ERR) 2365 #define wr_rg_sigdet_filter_sel_gen2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x2000,13,wr_val) 2366 #define rd_rg_sigdet_filter_sel_gen3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,3,15,__ERR) 2367 #define wr_rg_sigdet_filter_sel_gen3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x1000,12,wr_val) 2368 #define rd_rg_sigdet_sm_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,4,15,__ERR) 2369 #define wr_rg_sigdet_sm_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x0800,11,wr_val) 2370 #define rd_rg_sigdet_sm_rst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,5,15,__ERR) 2371 #define wr_rg_sigdet_sm_rst(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x0400,10,wr_val) 2372 #define rd_rg_eieos_det_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,6,15,__ERR) 2373 #define wr_rg_eieos_det_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x0200,9,wr_val) 2374 #define rd_rg_eieos_detect_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,7,12,__ERR) 2375 #define wr_rg_eieos_detect_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x01e0,5,wr_val) 2376 #define rd_rg_eios_det_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,11,15,__ERR) 2377 #define wr_rg_eios_det_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x0010,4,wr_val) 2378 #define rd_rg_eios_detect_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,12,15,__ERR) 2379 #define wr_rg_eios_detect_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x0008,3,wr_val) 2380 #define rd_rg_eios_detect_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c6,13,13,__ERR) 2381 #define wr_rg_eios_detect_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c6,0x0007,0,wr_val) 2382 #define rd_rg_sigdet_cnt_src_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c7,0,14,__ERR) 2383 #define wr_rg_sigdet_cnt_src_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c7,0xc000,14,wr_val) 2384 #define rd_rg_sigdet_raw_qlfy_len_refclk() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c7,2,14,__ERR) 2385 #define wr_rg_sigdet_raw_qlfy_len_refclk(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c7,0x3000,12,wr_val) 2386 #define rd_rg_sigdet_filter_len_refclk_gen1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c7,4,12,__ERR) 2387 #define wr_rg_sigdet_filter_len_refclk_gen1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c7,0x0f00,8,wr_val) 2388 #define rd_rg_sigdet_filter_len_refclk_gen2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c7,8,12,__ERR) 2389 #define wr_rg_sigdet_filter_len_refclk_gen2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c7,0x00f0,4,wr_val) 2390 #define rd_rg_sigdet_filter_len_refclk_gen3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c7,12,12,__ERR) 2391 #define wr_rg_sigdet_filter_len_refclk_gen3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c7,0x000f,0,wr_val) 2392 #define rd_rg_sigdet_raw_qlfy_len_auxclk() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c8,2,14,__ERR) 2393 #define wr_rg_sigdet_raw_qlfy_len_auxclk(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c8,0x3000,12,wr_val) 2394 #define rd_rg_sigdet_filter_len_auxclk_gen1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c8,4,12,__ERR) 2395 #define wr_rg_sigdet_filter_len_auxclk_gen1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c8,0x0f00,8,wr_val) 2396 #define rd_rg_sigdet_filter_len_auxclk_gen2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c8,8,12,__ERR) 2397 #define wr_rg_sigdet_filter_len_auxclk_gen2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c8,0x00f0,4,wr_val) 2398 #define rd_rg_sigdet_filter_len_auxclk_gen3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c8,12,12,__ERR) 2399 #define wr_rg_sigdet_filter_len_auxclk_gen3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c8,0x000f,0,wr_val) 2400 #define rd_rg_rloop_sigdet_sm_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c9,0,15,__ERR) 2401 #define wr_rg_rloop_sigdet_sm_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c9,0x8000,15,wr_val) 2402 #define rd_rg_sigdet_thresh_gen2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c9,1,11,__ERR) 2403 #define wr_rg_sigdet_thresh_gen2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c9,0x7c00,10,wr_val) 2404 #define rd_rg_sigdet_thresh_gen3_hi() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c9,6,11,__ERR) 2405 #define wr_rg_sigdet_thresh_gen3_hi(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c9,0x03e0,5,wr_val) 2406 #define rd_rg_sigdet_thresh_gen3_lo() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0c9,11,11,__ERR) 2407 #define wr_rg_sigdet_thresh_gen3_lo(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0c9,0x001f,0,wr_val) 2408 #define rd_rg_sigdet_deassert_tmr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0cd,10,10,__ERR) 2409 #define wr_rg_sigdet_deassert_tmr(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0cd,0x003f,0,wr_val) 2410 #define rd_rg_sigdet_deassert_tmr_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0cd,9,15,__ERR) 2411 #define wr_rg_sigdet_deassert_tmr_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0cd,0x0040,6,wr_val) 2412 #define rd_rg_sigdet_thresh_gen1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0cd,4,11,__ERR) 2413 #define wr_rg_sigdet_thresh_gen1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0cd,0x0f80,7,wr_val) 2414 #define rd_spares_sigdet() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0cd,0,12,__ERR) 2415 #define wr_spares_sigdet(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0cd,0xf000,12,wr_val) 2416 #define rd_afe_sigdet_thresh_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ca,3,11,__ERR) 2417 #define rd_rx_sigdet_mac() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ca,13,15,__ERR) 2418 #define rd_rx_sigdet_dsc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ca,14,15,__ERR) 2419 #define rd_afe_sigdet_raw() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0ca,15,15,__ERR) 2420 #define rd_rg_sigdet_tggl_cnt() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0cb,__ERR) 2421 #define rd_prbs_chk_burst_err_cnt_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,0,15,__ERR) 2422 #define wr_prbs_chk_burst_err_cnt_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x8000,15,wr_val) 2423 #define rd_prbs_chk_clk_en_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,4,15,__ERR) 2424 #define wr_prbs_chk_clk_en_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0800,11,wr_val) 2425 #define rd_trnsum_error_count_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,5,15,__ERR) 2426 #define wr_trnsum_error_count_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0400,10,wr_val) 2427 #define rd_prbs_chk_err_cnt_burst_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,6,15,__ERR) 2428 #define wr_prbs_chk_err_cnt_burst_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0200,9,wr_val) 2429 #define rd_prbs_chk_en_auto_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,8,15,__ERR) 2430 #define wr_prbs_chk_en_auto_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0080,7,wr_val) 2431 #define rd_prbs_chk_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,9,14,__ERR) 2432 #define wr_prbs_chk_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0060,5,wr_val) 2433 #define rd_prbs_chk_inv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,11,15,__ERR) 2434 #define wr_prbs_chk_inv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0010,4,wr_val) 2435 #define rd_prbs_chk_mode_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,12,13,__ERR) 2436 #define wr_prbs_chk_mode_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x000e,1,wr_val) 2437 #define rd_prbs_chk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d1,15,15,__ERR) 2438 #define wr_prbs_chk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0001,0,wr_val) 2439 #define rd_prbs_chk_lock_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d0,11,11,__ERR) 2440 #define wr_prbs_chk_lock_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d0,0x001f,0,wr_val) 2441 #define rd_prbs_chk_ool_cnt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d0,3,11,__ERR) 2442 #define wr_prbs_chk_ool_cnt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d0,0x1f00,8,wr_val) 2443 #define rd_dig_lpbk_pd_bias_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d2,12,15,__ERR) 2444 #define wr_dig_lpbk_pd_bias_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0008,3,wr_val) 2445 #define rd_dig_lpbk_pd_flt_bypass() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d2,13,15,__ERR) 2446 #define wr_dig_lpbk_pd_flt_bypass(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0004,2,wr_val) 2447 #define rd_dig_lpbk_pd_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d2,14,15,__ERR) 2448 #define wr_dig_lpbk_pd_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0002,1,wr_val) 2449 #define rd_dig_lpbk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d2,15,15,__ERR) 2450 #define wr_dig_lpbk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0001,0,wr_val) 2451 #define rd_dbg_mask_dig_lpbk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d3,13,15,__ERR) 2452 #define wr_dbg_mask_dig_lpbk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0004,2,wr_val) 2453 #define rd_rx_aggregator_bypass_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d3,14,15,__ERR) 2454 #define wr_rx_aggregator_bypass_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0002,1,wr_val) 2455 #define rd_rx_pmd_dp_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d3,15,15,__ERR) 2456 #define wr_rx_pmd_dp_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0001,0,wr_val) 2457 #define rd_prbs_chk_en_timeout() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d4,3,11,__ERR) 2458 #define wr_prbs_chk_en_timeout(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d4,0x1f00,8,wr_val) 2459 #define rd_prbs_chk_en_timer_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d4,14,14,__ERR) 2460 #define wr_prbs_chk_en_timer_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0d4,0x0003,0,wr_val) 2461 #define rd_dig_lpbk_pd_early_ind() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d8,14,15,__ERR) 2462 #define rd_dig_lpbk_pd_late_ind() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d8,15,15,__ERR) 2463 #define rd_prbs_chk_err_cnt_no_clr() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0d9,0,1,__ERR) 2464 #define rd_prbs_chk_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d9,15,15,__ERR) 2465 #define rd_prbs_chk_lock_lost_lh() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0da,0,15,__ERR) 2466 #define rd_prbs_chk_err_cnt_msb() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0da,1,1,__ERR) 2467 #define rd_prbs_chk_err_cnt_lsb() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0db,__ERR) 2468 #define rd_pmd_rx_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0dc,15,15,__ERR) 2469 #define rd_pmd_rx_lock_change() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0dc,14,15,__ERR) 2470 #define rd_dbg_pmd_rx_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d6,15,15,__ERR) 2471 #define rd_dbg_pmd_rx_lock_change() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d6,14,15,__ERR) 2472 #define rd_uc_pmd_rx_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d7,15,15,__ERR) 2473 #define rd_uc_pmd_rx_lock_change() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0d7,14,15,__ERR) 2474 #define rd_prbs_chk_burst_err_cnt() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd0d5,6,6,__ERR) 2475 #define rd_patt_gen_start_pos() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e0,0,12,__ERR) 2476 #define wr_patt_gen_start_pos(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e0,0xf000,12,wr_val) 2477 #define rd_patt_gen_stop_pos() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e0,4,12,__ERR) 2478 #define wr_patt_gen_stop_pos(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e0,0x0f00,8,wr_val) 2479 #define rd_patt_gen_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e0,15,15,__ERR) 2480 #define wr_patt_gen_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e0,0x0001,0,wr_val) 2481 #define rd_prbs_gen_err_ins() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e1,10,15,__ERR) 2482 #define wr_prbs_gen_err_ins(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0020,5,wr_val) 2483 #define rd_prbs_gen_inv() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e1,11,15,__ERR) 2484 #define wr_prbs_gen_inv(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0010,4,wr_val) 2485 #define rd_prbs_gen_mode_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e1,12,13,__ERR) 2486 #define wr_prbs_gen_mode_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e1,0x000e,1,wr_val) 2487 #define rd_prbs_gen_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e1,15,15,__ERR) 2488 #define wr_prbs_gen_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0001,0,wr_val) 2489 #define rd_rmt_lpbk_pd_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e2,13,15,__ERR) 2490 #define wr_rmt_lpbk_pd_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0004,2,wr_val) 2491 #define rd_rmt_lpbk_pd_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e2,14,15,__ERR) 2492 #define wr_rmt_lpbk_pd_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0002,1,wr_val) 2493 #define rd_rmt_lpbk_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e2,15,15,__ERR) 2494 #define wr_rmt_lpbk_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0001,0,wr_val) 2495 #define rd_tx_mux_sel_order() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e3,13,15,__ERR) 2496 #define wr_tx_mux_sel_order(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0004,2,wr_val) 2497 #define rd_tx_pcs_native_ana_frmt_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e3,14,15,__ERR) 2498 #define wr_tx_pcs_native_ana_frmt_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0002,1,wr_val) 2499 #define rd_tx_pmd_dp_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e3,15,15,__ERR) 2500 #define wr_tx_pmd_dp_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0001,0,wr_val) 2501 #define rd_rmt_lpbk_pd_early_ind() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e8,14,15,__ERR) 2502 #define rd_rmt_lpbk_pd_late_ind() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd0e8,15,15,__ERR) 2503 #define rd_afe_tx_reset_deassert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd171,0,15,__ERR) 2504 #define wr_afe_tx_reset_deassert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd171,0x8000,15,wr_val) 2505 #define rd_ln_tx_s_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd171,15,15,__ERR) 2506 #define wr_ln_tx_s_pwrdn(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd171,0x0001,0,wr_val) 2507 #define rd_pmd_tx_clk_vld_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd177,11,15,__ERR) 2508 #define wr_pmd_tx_clk_vld_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd177,0x0010,4,wr_val) 2509 #define rd_pmd_tx_clk_vld_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd177,12,15,__ERR) 2510 #define wr_pmd_tx_clk_vld_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd177,0x0008,3,wr_val) 2511 #define rd_ln_tx_s_comclk_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd177,13,15,__ERR) 2512 #define wr_ln_tx_s_comclk_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd177,0x0004,2,wr_val) 2513 #define rd_ln_tx_s_comclk_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd177,14,15,__ERR) 2514 #define wr_ln_tx_s_comclk_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd177,0x0002,1,wr_val) 2515 #define rd_ln_tx_s_clkgate_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd177,15,15,__ERR) 2516 #define wr_ln_tx_s_clkgate_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd177,0x0001,0,wr_val) 2517 #define rd_ln_tx_dp_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd174,14,15,__ERR) 2518 #define wr_ln_tx_dp_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd174,0x0002,1,wr_val) 2519 #define rd_ln_tx_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd174,15,15,__ERR) 2520 #define wr_ln_tx_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd174,0x0001,0,wr_val) 2521 #define rd_afe_txclk_reset_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd172,10,15,__ERR) 2522 #define wr_afe_txclk_reset_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd172,0x0020,5,wr_val) 2523 #define rd_afe_txclk_reset_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd172,11,15,__ERR) 2524 #define wr_afe_txclk_reset_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd172,0x0010,4,wr_val) 2525 #define rd_afe_tx_reset_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd172,12,15,__ERR) 2526 #define wr_afe_tx_reset_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd172,0x0008,3,wr_val) 2527 #define rd_afe_tx_reset_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd172,13,15,__ERR) 2528 #define wr_afe_tx_reset_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd172,0x0004,2,wr_val) 2529 #define rd_afe_tx_pwrdn_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd172,14,15,__ERR) 2530 #define wr_afe_tx_pwrdn_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd172,0x0002,1,wr_val) 2531 #define rd_afe_tx_pwrdn_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd172,15,15,__ERR) 2532 #define wr_afe_tx_pwrdn_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd172,0x0001,0,wr_val) 2533 #define rd_pmd_ln_tx_h_pwrdn_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd173,15,15,__ERR) 2534 #define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd173,0x0001,0,wr_val) 2535 #define rd_afe_txclk_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd17c,13,15,__ERR) 2536 #define rd_afe_tx_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd17c,14,15,__ERR) 2537 #define rd_afe_tx_pwrdn() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd17c,15,15,__ERR) 2538 #define rd_tx_pi_loop_filter_stable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd17d,15,15,__ERR) 2539 #define wr_tx_pi_loop_filter_stable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd17d,0x0001,0,wr_val) 2540 #define rd_fir_main_extent_0() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd300,1,1,__ERR) 2541 #define wr_fir_main_extent_0(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd300,0x7fff,0,wr_val) 2542 #define rd_fir_main_extent_1() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd301,1,1,__ERR) 2543 #define wr_fir_main_extent_1(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd301,0x7fff,0,wr_val) 2544 #define rd_fir_main_extent_2() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd302,1,1,__ERR) 2545 #define wr_fir_main_extent_2(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd302,0x7fff,0,wr_val) 2546 #define rd_fir_main_extent_3() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd303,1,1,__ERR) 2547 #define wr_fir_main_extent_3(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd303,0x7fff,0,wr_val) 2548 #define rd_fir_main_extent_4() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd304,1,1,__ERR) 2549 #define wr_fir_main_extent_4(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd304,0x7fff,0,wr_val) 2550 #define rd_fir_main_extent_5() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd305,1,1,__ERR) 2551 #define wr_fir_main_extent_5(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd305,0x7fff,0,wr_val) 2552 #define rd_fir_pre_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd310,10,10,__ERR) 2553 #define wr_fir_pre_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd310,0x003f,0,wr_val) 2554 #define rd_fir_pre_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd310,4,10,__ERR) 2555 #define wr_fir_pre_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd310,0x0fc0,6,wr_val) 2556 #define rd_fir_pre_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd311,10,10,__ERR) 2557 #define wr_fir_pre_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd311,0x003f,0,wr_val) 2558 #define rd_fir_pre_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd311,4,10,__ERR) 2559 #define wr_fir_pre_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd311,0x0fc0,6,wr_val) 2560 #define rd_fir_pre_4() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd312,10,10,__ERR) 2561 #define wr_fir_pre_4(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd312,0x003f,0,wr_val) 2562 #define rd_fir_pre_5() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd312,4,10,__ERR) 2563 #define wr_fir_pre_5(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd312,0x0fc0,6,wr_val) 2564 #define rd_fir_pre_6() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd313,10,10,__ERR) 2565 #define wr_fir_pre_6(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd313,0x003f,0,wr_val) 2566 #define rd_fir_pre_7() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd313,4,10,__ERR) 2567 #define wr_fir_pre_7(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd313,0x0fc0,6,wr_val) 2568 #define rd_fir_pre_8() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd314,10,10,__ERR) 2569 #define wr_fir_pre_8(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd314,0x003f,0,wr_val) 2570 #define rd_fir_pre_9() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd314,4,10,__ERR) 2571 #define wr_fir_pre_9(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd314,0x0fc0,6,wr_val) 2572 #define rd_fir_pre_10() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd315,10,10,__ERR) 2573 #define wr_fir_pre_10(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd315,0x003f,0,wr_val) 2574 #define rd_reg_main_post1pre_default() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd316,10,10,__ERR) 2575 #define wr_reg_main_post1pre_default(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd316,0x003f,0,wr_val) 2576 #define rd_reg_main_cs() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd316,7,13,__ERR) 2577 #define wr_reg_main_cs(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd316,0x01c0,6,wr_val) 2578 #define rd_reg_en_main() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd316,6,15,__ERR) 2579 #define wr_reg_en_main(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd316,0x0200,9,wr_val) 2580 #define rd_reg_ovrd() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd317,15,15,__ERR) 2581 #define wr_reg_ovrd(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd317,0x0001,0,wr_val) 2582 #define rd_fir_post_extent_0() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd320,1,1,__ERR) 2583 #define wr_fir_post_extent_0(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd320,0x7fff,0,wr_val) 2584 #define rd_fir_post_extent_1() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd321,1,1,__ERR) 2585 #define wr_fir_post_extent_1(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd321,0x7fff,0,wr_val) 2586 #define rd_fir_post_extent_2() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd322,1,1,__ERR) 2587 #define wr_fir_post_extent_2(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd322,0x7fff,0,wr_val) 2588 #define rd_fir_post_extent_3() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd323,1,1,__ERR) 2589 #define wr_fir_post_extent_3(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd323,0x7fff,0,wr_val) 2590 #define rd_fir_post_extent_4() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd324,1,1,__ERR) 2591 #define wr_fir_post_extent_4(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd324,0x7fff,0,wr_val) 2592 #define rd_fir_post_extent_5() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd325,1,1,__ERR) 2593 #define wr_fir_post_extent_5(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd325,0x7fff,0,wr_val) 2594 #define rd_fir_post_0() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd330,1,1,__ERR) 2595 #define wr_fir_post_0(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd330,0x7fff,0,wr_val) 2596 #define rd_fir_post_1() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd331,1,1,__ERR) 2597 #define wr_fir_post_1(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd331,0x7fff,0,wr_val) 2598 #define rd_fir_post_2() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd332,1,1,__ERR) 2599 #define wr_fir_post_2(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd332,0x7fff,0,wr_val) 2600 #define rd_fir_post_3() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd333,1,1,__ERR) 2601 #define wr_fir_post_3(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd333,0x7fff,0,wr_val) 2602 #define rd_fir_post_4() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd334,1,1,__ERR) 2603 #define wr_fir_post_4(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd334,0x7fff,0,wr_val) 2604 #define rd_fir_post_5() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd335,1,1,__ERR) 2605 #define wr_fir_post_5(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd335,0x7fff,0,wr_val) 2606 #define rd_fir_post_6() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd336,1,1,__ERR) 2607 #define wr_fir_post_6(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd336,0x7fff,0,wr_val) 2608 #define rd_fir_post_7() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd337,1,1,__ERR) 2609 #define wr_fir_post_7(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd337,0x7fff,0,wr_val) 2610 #define rd_fir_post_8() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd338,1,1,__ERR) 2611 #define wr_fir_post_8(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd338,0x7fff,0,wr_val) 2612 #define rd_fir_post_9() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd339,1,1,__ERR) 2613 #define wr_fir_post_9(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd339,0x7fff,0,wr_val) 2614 #define rd_fir_post_10() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd33a,1,1,__ERR) 2615 #define wr_fir_post_10(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd33a,0x7fff,0,wr_val) 2616 #define rd_fir_post_11() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd33b,1,1,__ERR) 2617 #define wr_fir_post_11(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd33b,0x7fff,0,wr_val) 2618 #define rd_fir_post_12() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd33c,1,1,__ERR) 2619 #define wr_fir_post_12(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd33c,0x7fff,0,wr_val) 2620 #define rd_fir_post_13() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd33d,1,1,__ERR) 2621 #define wr_fir_post_13(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd33d,0x7fff,0,wr_val) 2622 #define rd_fir_post_14() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd33e,1,1,__ERR) 2623 #define wr_fir_post_14(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd33e,0x7fff,0,wr_val) 2624 #define rd_fir_post_15() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd340,1,1,__ERR) 2625 #define wr_fir_post_15(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd340,0x7fff,0,wr_val) 2626 #define rd_fir_post_16() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd341,1,1,__ERR) 2627 #define wr_fir_post_16(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd341,0x7fff,0,wr_val) 2628 #define rd_fir_post_17() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd342,1,1,__ERR) 2629 #define wr_fir_post_17(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd342,0x7fff,0,wr_val) 2630 #define rd_fir_post_18() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd343,1,1,__ERR) 2631 #define wr_fir_post_18(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd343,0x7fff,0,wr_val) 2632 #define rd_fir_post_19() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd344,1,1,__ERR) 2633 #define wr_fir_post_19(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd344,0x7fff,0,wr_val) 2634 #define rd_fir_post_20() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd345,1,1,__ERR) 2635 #define wr_fir_post_20(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd345,0x7fff,0,wr_val) 2636 #define rd_fir_post_21() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd346,1,1,__ERR) 2637 #define wr_fir_post_21(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd346,0x7fff,0,wr_val) 2638 #define rd_fir_post_22() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd347,1,1,__ERR) 2639 #define wr_fir_post_22(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd347,0x7fff,0,wr_val) 2640 #define rd_fir_post_23() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd348,1,1,__ERR) 2641 #define wr_fir_post_23(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd348,0x7fff,0,wr_val) 2642 #define rd_fir_post_24() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd349,1,1,__ERR) 2643 #define wr_fir_post_24(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd349,0x7fff,0,wr_val) 2644 #define rd_pre_post1pre_default() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd34a,10,10,__ERR) 2645 #define wr_pre_post1pre_default(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd34a,0x003f,0,wr_val) 2646 #define rd_post1_post1pre_default() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd34a,4,10,__ERR) 2647 #define wr_post1_post1pre_default(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd34a,0x0fc0,6,wr_val) 2648 #define rd_fir_pre_extent_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd350,10,10,__ERR) 2649 #define wr_fir_pre_extent_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd350,0x003f,0,wr_val) 2650 #define rd_fir_pre_extent_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd351,10,10,__ERR) 2651 #define wr_fir_pre_extent_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd351,0x003f,0,wr_val) 2652 #define rd_fir_pre_extent_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd352,10,10,__ERR) 2653 #define wr_fir_pre_extent_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd352,0x003f,0,wr_val) 2654 #define rd_fir_pre_extent_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd353,10,10,__ERR) 2655 #define wr_fir_pre_extent_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd353,0x003f,0,wr_val) 2656 #define rd_fir_pre_extent_4() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd354,10,10,__ERR) 2657 #define wr_fir_pre_extent_4(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd354,0x003f,0,wr_val) 2658 #define rd_fir_pre_extent_5() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd355,10,10,__ERR) 2659 #define wr_fir_pre_extent_5(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd355,0x003f,0,wr_val) 2660 #define rdex_gloopback() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,7,15,__ERR) 2661 #define rdex_dig2ana_tx_ElecIdle() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,9,15,__ERR) 2662 #define rdex_setTxCnxTest() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,10,15,__ERR) 2663 #define rdex_dig2ana_tx_setTxCnxTest() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,11,15,__ERR) 2664 #define rdex_rxCnxDetect() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,12,15,__ERR) 2665 #define rdex_ana2dig_tx_rxCnxDetect() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,13,15,__ERR) 2666 #define rdex_rltxferr_stky() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,14,15,__ERR) 2667 #define rdex_txpll_lock() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5000,15,15,__ERR) 2668 #define rdex_mdata0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5002,__ERR) 2669 #define wrex_mdata0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5002,wr_val) 2670 #define rdex_mdata1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5003,__ERR) 2671 #define wrex_mdata1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5003,wr_val) 2672 #define rdex_eq_coeff() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5005,__ERR) 2673 #define rdex_mdio_force_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,0,15,__ERR) 2674 #define wrex_mdio_force_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x8000,15,wr_val) 2675 #define rdex_L0s_test_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,1,15,__ERR) 2676 #define wrex_L0s_test_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x4000,14,wr_val) 2677 #define rdex_setTxCnxTest_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,2,15,__ERR) 2678 #define wrex_setTxCnxTest_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x2000,13,wr_val) 2679 #define rdex_mdio_tx_ElecIdle() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,3,15,__ERR) 2680 #define wrex_mdio_tx_ElecIdle(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x1000,12,wr_val) 2681 #define rdex_fts_en_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,5,15,__ERR) 2682 #define wrex_fts_en_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0400,10,wr_val) 2683 #define rdex_gloopOutDis_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,6,15,__ERR) 2684 #define wrex_gloopOutDis_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0200,9,wr_val) 2685 #define rdex_prbs_enb_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,7,15,__ERR) 2686 #define wrex_prbs_enb_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0100,8,wr_val) 2687 #define rdex_pkt_en_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,8,15,__ERR) 2688 #define wrex_pkt_en_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0080,7,wr_val) 2689 #define rdex_pkt_strt_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,9,15,__ERR) 2690 #define wrex_pkt_strt_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0040,6,wr_val) 2691 #define rdex_txpol_flip() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,10,15,__ERR) 2692 #define wrex_txpol_flip(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0020,5,wr_val) 2693 #define rdex_force_disError_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,11,15,__ERR) 2694 #define wrex_force_disError_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0010,4,wr_val) 2695 #define rdex_eden_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,12,15,__ERR) 2696 #define wrex_eden_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0008,3,wr_val) 2697 #define rdex_eden_force_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,13,15,__ERR) 2698 #define wrex_eden_force_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0004,2,wr_val) 2699 #define rdex_txpat_seq_en_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,14,15,__ERR) 2700 #define wrex_txpat_seq_en_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0002,1,wr_val) 2701 #define rdex_tx_mdata_en_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5001,15,15,__ERR) 2702 #define wrex_tx_mdata_en_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5001,0x0001,0,wr_val) 2703 #define rdex_txTestMuxSelect() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,0,13,__ERR) 2704 #define wrex_txTestMuxSelect(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0xe000,13,wr_val) 2705 #define rdex_rlfifo_tstsel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,3,13,__ERR) 2706 #define wrex_rlfifo_tstsel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x1c00,10,wr_val) 2707 #define rdex_prbs_seed_ld() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,6,15,__ERR) 2708 #define wrex_prbs_seed_ld(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0200,9,wr_val) 2709 #define rdex_L0s_timer_ld() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,7,15,__ERR) 2710 #define wrex_L0s_timer_ld(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0100,8,wr_val) 2711 #define rdex_pktBurst_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,8,15,__ERR) 2712 #define wrex_pktBurst_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0080,7,wr_val) 2713 #define rdex_pktRndm_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,9,15,__ERR) 2714 #define wrex_pktRndm_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0040,6,wr_val) 2715 #define rdex_ipgLngth() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,10,14,__ERR) 2716 #define wrex_ipgLngth(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0030,4,wr_val) 2717 #define rdex_rxCnxDetect_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,12,15,__ERR) 2718 #define wrex_rxCnxDetect_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0008,3,wr_val) 2719 #define rdex_rxCnxDetect_force_r() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,13,15,__ERR) 2720 #define wrex_rxCnxDetect_force_r(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0004,2,wr_val) 2721 #define rdex_pre_emph_stair_rev_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,14,15,__ERR) 2722 #define wrex_pre_emph_stair_rev_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0002,1,wr_val) 2723 #define rdex_mdio_txmargin_SM() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5006,15,15,__ERR) 2724 #define wrex_mdio_txmargin_SM(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5006,0x0001,0,wr_val) 2725 #define rdex_tx_delay_fall_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5007,0,13,__ERR) 2726 #define wrex_tx_delay_fall_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5007,0xe000,13,wr_val) 2727 #define rdex_rloop_delay_fall_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5007,3,11,__ERR) 2728 #define wrex_rloop_delay_fall_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5007,0x1f00,8,wr_val) 2729 #define rdex_tx_delay_rise_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5007,8,13,__ERR) 2730 #define wrex_tx_delay_rise_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5007,0x00e0,5,wr_val) 2731 #define rdex_rloop_delay_rise_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5007,11,11,__ERR) 2732 #define wrex_rloop_delay_rise_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5007,0x001f,0,wr_val) 2733 #define rdex_tx_delay_fall_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5008,0,13,__ERR) 2734 #define wrex_tx_delay_fall_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5008,0xe000,13,wr_val) 2735 #define rdex_rloop_delay_fall_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5008,3,11,__ERR) 2736 #define wrex_rloop_delay_fall_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5008,0x1f00,8,wr_val) 2737 #define rdex_tx_delay_rise_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5008,8,13,__ERR) 2738 #define wrex_tx_delay_rise_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5008,0x00e0,5,wr_val) 2739 #define rdex_rloop_delay_rise_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5008,11,11,__ERR) 2740 #define wrex_rloop_delay_rise_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5008,0x001f,0,wr_val) 2741 #define rdex_tx_delay_fall_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5009,0,13,__ERR) 2742 #define wrex_tx_delay_fall_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5009,0xe000,13,wr_val) 2743 #define rdex_rloop_delay_fall_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5009,3,11,__ERR) 2744 #define wrex_rloop_delay_fall_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5009,0x1f00,8,wr_val) 2745 #define rdex_tx_delay_rise_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5009,8,13,__ERR) 2746 #define wrex_tx_delay_rise_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5009,0x00e0,5,wr_val) 2747 #define rdex_rloop_delay_rise_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x5009,11,11,__ERR) 2748 #define wrex_rloop_delay_rise_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x5009,0x001f,0,wr_val) 2749 #define rdex_rising_half_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500a,10,15,__ERR) 2750 #define wrex_rising_half_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500a,0x0020,5,wr_val) 2751 #define rdex_falling_half_G3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500a,11,15,__ERR) 2752 #define wrex_falling_half_G3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500a,0x0010,4,wr_val) 2753 #define rdex_rising_half_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500a,12,15,__ERR) 2754 #define wrex_rising_half_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500a,0x0008,3,wr_val) 2755 #define rdex_falling_half_G2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500a,13,15,__ERR) 2756 #define wrex_falling_half_G2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500a,0x0004,2,wr_val) 2757 #define rdex_rising_half_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500a,14,15,__ERR) 2758 #define wrex_rising_half_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500a,0x0002,1,wr_val) 2759 #define rdex_falling_half_G1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500a,15,15,__ERR) 2760 #define wrex_falling_half_G1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500a,0x0001,0,wr_val) 2761 #define rdex_tx_g3_ei_fifo_rst_cya() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500b,0,15,__ERR) 2762 #define wrex_tx_g3_ei_fifo_rst_cya(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500b,0x8000,15,wr_val) 2763 #define rdex_tx_g3f_tm_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500b,11,13,__ERR) 2764 #define wrex_tx_g3f_tm_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500b,0x001c,2,wr_val) 2765 #define rdex_tx_g3f_sw_rst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500b,14,15,__ERR) 2766 #define wrex_tx_g3f_sw_rst(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500b,0x0002,1,wr_val) 2767 #define rdex_tx_g3f_afrst_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500b,15,15,__ERR) 2768 #define wrex_tx_g3f_afrst_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0x500b,0x0001,0,wr_val) 2769 #define rdex_tx_g3f_afrst() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500c,13,15,__ERR) 2770 #define rdex_tx_g3f_unflow() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500c,14,15,__ERR) 2771 #define rdex_tx_g3f_ovflow() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0x500c,15,15,__ERR) 2772 #define rd_txfir_post2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd110,12,12,__ERR) 2773 #define wr_txfir_post2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd110,0x000f,0,wr_val) 2774 #define rd_convert_taps_to_afe_error() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd111,9,15,__ERR) 2775 #define wr_convert_taps_to_afe_error(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd111,0x0040,6,wr_val) 2776 #define rd_convert_taps_to_afe_int_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd111,10,15,__ERR) 2777 #define wr_convert_taps_to_afe_int_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd111,0x0020,5,wr_val) 2778 #define rd_convert_taps_to_afe() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd111,11,15,__ERR) 2779 #define wr_convert_taps_to_afe(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd111,0x0010,4,wr_val) 2780 #define rd_tx_disable_output_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd111,12,14,__ERR) 2781 #define wr_tx_disable_output_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd111,0x000c,2,wr_val) 2782 #define rd_sdk_tx_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd111,15,15,__ERR) 2783 #define wr_sdk_tx_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd111,0x0001,0,wr_val) 2784 #define rd_tx_elec_idle_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd112,14,15,__ERR) 2785 #define rd_tx_disable_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd112,15,15,__ERR) 2786 #define rd_tx_eee_alert_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,0,15,__ERR) 2787 #define wr_tx_eee_alert_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x8000,15,wr_val) 2788 #define rd_tx_eee_quiet_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,1,15,__ERR) 2789 #define wr_tx_eee_quiet_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x4000,14,wr_val) 2790 #define rd_tx_disable_timer_ctrl() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,6,10,__ERR) 2791 #define wr_tx_disable_timer_ctrl(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x03f0,4,wr_val) 2792 #define rd_pmd_tx_disable_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,12,15,__ERR) 2793 #define wr_pmd_tx_disable_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x0008,3,wr_val) 2794 #define rd_dp_reset_tx_disable_dis() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,13,15,__ERR) 2795 #define wr_dp_reset_tx_disable_dis(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x0004,2,wr_val) 2796 #define rd_tx_disable_trigger() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,14,15,__ERR) 2797 #define wr_tx_disable_trigger(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x0002,1,wr_val) 2798 #define rd_micro_tx_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd113,15,15,__ERR) 2799 #define wr_micro_tx_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd113,0x0001,0,wr_val) 2800 #define rd_txfir_dc_level_post2_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,8,15,__ERR) 2801 #define wr_txfir_dc_level_post2_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0080,7,wr_val) 2802 #define rd_txfir_post2_post2_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,9,15,__ERR) 2803 #define wr_txfir_post2_post2_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0040,6,wr_val) 2804 #define rd_txfir_dc_level_post2_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,10,15,__ERR) 2805 #define wr_txfir_dc_level_post2_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0020,5,wr_val) 2806 #define rd_txfir_post2_post2_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,11,15,__ERR) 2807 #define wr_txfir_post2_post2_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0010,4,wr_val) 2808 #define rd_txfir_dc_level_post2_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,12,15,__ERR) 2809 #define wr_txfir_dc_level_post2_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0008,3,wr_val) 2810 #define rd_txfir_post2_post2_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,13,15,__ERR) 2811 #define wr_txfir_post2_post2_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0004,2,wr_val) 2812 #define rd_txfir_dc_level_post2_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,14,15,__ERR) 2813 #define wr_txfir_dc_level_post2_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0002,1,wr_val) 2814 #define rd_txfir_post2_post2_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11b,15,15,__ERR) 2815 #define wr_txfir_post2_post2_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11b,0x0001,0,wr_val) 2816 #define rd_txfir_dc_level_post1pre_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,1,15,__ERR) 2817 #define wr_txfir_dc_level_post1pre_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x4000,14,wr_val) 2818 #define rd_txfir_post1_post1pre_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,2,15,__ERR) 2819 #define wr_txfir_post1_post1pre_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x2000,13,wr_val) 2820 #define rd_txfir_pre_post1pre_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,3,15,__ERR) 2821 #define wr_txfir_pre_post1pre_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x1000,12,wr_val) 2822 #define rd_txfir_dc_level_post1_2x_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,6,15,__ERR) 2823 #define wr_txfir_dc_level_post1_2x_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0200,9,wr_val) 2824 #define rd_txfir_post1_post1_2x_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,7,15,__ERR) 2825 #define wr_txfir_post1_post1_2x_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0100,8,wr_val) 2826 #define rd_txfir_dc_level_post1_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,8,15,__ERR) 2827 #define wr_txfir_dc_level_post1_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0080,7,wr_val) 2828 #define rd_txfir_post1_post1_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,9,15,__ERR) 2829 #define wr_txfir_post1_post1_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0040,6,wr_val) 2830 #define rd_txfir_dc_level_post1_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,10,15,__ERR) 2831 #define wr_txfir_dc_level_post1_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0020,5,wr_val) 2832 #define rd_txfir_post1_post1_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,11,15,__ERR) 2833 #define wr_txfir_post1_post1_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0010,4,wr_val) 2834 #define rd_txfir_dc_level_post1_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,12,15,__ERR) 2835 #define wr_txfir_dc_level_post1_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0008,3,wr_val) 2836 #define rd_txfir_post1_post1_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,13,15,__ERR) 2837 #define wr_txfir_post1_post1_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0004,2,wr_val) 2838 #define rd_txfir_dc_level_post1_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,14,15,__ERR) 2839 #define wr_txfir_dc_level_post1_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0002,1,wr_val) 2840 #define rd_txfir_post1_post1_1x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11c,15,15,__ERR) 2841 #define wr_txfir_post1_post1_1x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11c,0x0001,0,wr_val) 2842 #define rd_txfir_dc_level_post1pre_2x_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,1,15,__ERR) 2843 #define wr_txfir_dc_level_post1pre_2x_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x4000,14,wr_val) 2844 #define rd_txfir_post1_post1pre_2x_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,2,15,__ERR) 2845 #define wr_txfir_post1_post1pre_2x_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x2000,13,wr_val) 2846 #define rd_txfir_pre_post1pre_2x_3() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,3,15,__ERR) 2847 #define wr_txfir_pre_post1pre_2x_3(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x1000,12,wr_val) 2848 #define rd_txfir_dc_level_post1pre_2x_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,4,15,__ERR) 2849 #define wr_txfir_dc_level_post1pre_2x_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0800,11,wr_val) 2850 #define rd_txfir_post1_post1pre_2x_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,5,15,__ERR) 2851 #define wr_txfir_post1_post1pre_2x_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0400,10,wr_val) 2852 #define rd_txfir_pre_post1pre_2x_2() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,6,15,__ERR) 2853 #define wr_txfir_pre_post1pre_2x_2(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0200,9,wr_val) 2854 #define rd_txfir_dc_level_post1pre_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,7,15,__ERR) 2855 #define wr_txfir_dc_level_post1pre_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0100,8,wr_val) 2856 #define rd_txfir_post1_post1pre_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,8,15,__ERR) 2857 #define wr_txfir_post1_post1pre_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0080,7,wr_val) 2858 #define rd_txfir_pre_post1pre_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,9,15,__ERR) 2859 #define wr_txfir_pre_post1pre_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0040,6,wr_val) 2860 #define rd_txfir_dc_level_post1pre_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,10,15,__ERR) 2861 #define wr_txfir_dc_level_post1pre_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0020,5,wr_val) 2862 #define rd_txfir_post1_post1pre_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,11,15,__ERR) 2863 #define wr_txfir_post1_post1pre_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0010,4,wr_val) 2864 #define rd_txfir_pre_post1pre_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,12,15,__ERR) 2865 #define wr_txfir_pre_post1pre_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0008,3,wr_val) 2866 #define rd_txfir_dc_level_post1pre_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,13,15,__ERR) 2867 #define wr_txfir_dc_level_post1pre_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0004,2,wr_val) 2868 #define rd_txfir_post1_post1pre_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,14,15,__ERR) 2869 #define wr_txfir_post1_post1pre_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0002,1,wr_val) 2870 #define rd_txfir_pre_post1pre_1x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11d,15,15,__ERR) 2871 #define wr_txfir_pre_post1pre_1x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11d,0x0001,0,wr_val) 2872 #define rd_txfir_dc_level_2x_1() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11e,12,15,__ERR) 2873 #define wr_txfir_dc_level_2x_1(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11e,0x0008,3,wr_val) 2874 #define rd_txfir_dc_level_2x_0() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11e,13,15,__ERR) 2875 #define wr_txfir_dc_level_2x_0(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11e,0x0004,2,wr_val) 2876 #define rd_txfir_dc_level_1x() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11e,14,15,__ERR) 2877 #define wr_txfir_dc_level_1x(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11e,0x0002,1,wr_val) 2878 #define rd_txfir_dc_level_0p5x() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd11e,15,15,__ERR) 2879 #define wr_txfir_dc_level_0p5x(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd11e,0x0001,0,wr_val) 2880 #define rd_tx_pi_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,15,15,__ERR) 2881 #define wr_tx_pi_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0001,0,wr_val) 2882 #define rd_tx_pi_jitter_filter_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,14,15,__ERR) 2883 #define wr_tx_pi_jitter_filter_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0002,1,wr_val) 2884 #define rd_tx_pi_ext_ctrl_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,13,15,__ERR) 2885 #define wr_tx_pi_ext_ctrl_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0004,2,wr_val) 2886 #define rd_tx_pi_freq_override_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,12,15,__ERR) 2887 #define wr_tx_pi_freq_override_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0008,3,wr_val) 2888 #define rd_tx_pi_sj_gen_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,11,15,__ERR) 2889 #define wr_tx_pi_sj_gen_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0010,4,wr_val) 2890 #define rd_tx_pi_ssc_gen_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,10,15,__ERR) 2891 #define wr_tx_pi_ssc_gen_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0020,5,wr_val) 2892 #define rd_tx_pi_jit_ssc_freq_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,9,15,__ERR) 2893 #define wr_tx_pi_jit_ssc_freq_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0040,6,wr_val) 2894 #define rd_tx_pi_reset_code_dbg() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,8,15,__ERR) 2895 #define wr_tx_pi_reset_code_dbg(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0080,7,wr_val) 2896 #define rd_tx_pi_second_order_loop_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,7,15,__ERR) 2897 #define wr_tx_pi_second_order_loop_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0100,8,wr_val) 2898 #define rd_tx_pi_first_order_bwsel_integ() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,4,14,__ERR) 2899 #define wr_tx_pi_first_order_bwsel_integ(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x0c00,10,wr_val) 2900 #define rd_tx_pi_second_order_bwsel_integ() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,2,14,__ERR) 2901 #define wr_tx_pi_second_order_bwsel_integ(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x3000,12,wr_val) 2902 #define rd_tx_pi_frc_phase_step_mux_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd070,0,15,__ERR) 2903 #define wr_tx_pi_frc_phase_step_mux_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd070,0x8000,15,wr_val) 2904 #define rd_tx_pi_freq_override_val() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd071,1,1,__ERR) 2905 #define wr_tx_pi_freq_override_val(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd071,0x7fff,0,wr_val) 2906 #define rd_tx_pi_jit_freq_idx() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd072,10,10,__ERR) 2907 #define wr_tx_pi_jit_freq_idx(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd072,0x003f,0,wr_val) 2908 #define rd_tx_pi_jit_amp() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd072,2,10,__ERR) 2909 #define wr_tx_pi_jit_amp(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd072,0x3f00,8,wr_val) 2910 #define rd_tx_pi_phase_override() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd073,15,15,__ERR) 2911 #define wr_tx_pi_phase_override(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd073,0x0001,0,wr_val) 2912 #define rd_tx_pi_phase_strobe() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd073,14,15,__ERR) 2913 #define wr_tx_pi_phase_strobe(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd073,0x0002,1,wr_val) 2914 #define rd_tx_pi_phase_step_dir() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd073,13,15,__ERR) 2915 #define wr_tx_pi_phase_step_dir(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd073,0x0004,2,wr_val) 2916 #define rd_tx_pi_phase_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd073,11,15,__ERR) 2917 #define wr_tx_pi_phase_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd073,0x0010,4,wr_val) 2918 #define rd_tx_pi_phase_step_num() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd073,4,12,__ERR) 2919 #define wr_tx_pi_phase_step_num(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd073,0x0f00,8,wr_val) 2920 #define rd_tx_pi_ext_phase_bwsel_integ() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd073,1,13,__ERR) 2921 #define wr_tx_pi_ext_phase_bwsel_integ(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd073,0x7000,12,wr_val) 2922 #define rd_tx_pi_frz_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd074,15,15,__ERR) 2923 #define wr_tx_pi_frz_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd074,0x0001,0,wr_val) 2924 #define rd_tx_pi_frz_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd074,14,15,__ERR) 2925 #define wr_tx_pi_frz_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd074,0x0002,1,wr_val) 2926 #define rd_tx_pi_frz_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd074,13,15,__ERR) 2927 #define wr_tx_pi_frz_mode(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd074,0x0004,2,wr_val) 2928 #define rd_tx_pi_hs_fifo_phserr_invert() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,14,15,__ERR) 2929 #define wr_tx_pi_hs_fifo_phserr_invert(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0002,1,wr_val) 2930 #define rd_tx_pi_repeater_mode_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,13,15,__ERR) 2931 #define wr_tx_pi_repeater_mode_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0004,2,wr_val) 2932 #define rd_tx_pi_ext_pd_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,12,15,__ERR) 2933 #define wr_tx_pi_ext_pd_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0008,3,wr_val) 2934 #define rd_afe_tx_fifo_resetb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,7,15,__ERR) 2935 #define wr_afe_tx_fifo_resetb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0100,8,wr_val) 2936 #define rd_afe_tx_fifo_resetb_frc_on() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,6,15,__ERR) 2937 #define wr_afe_tx_fifo_resetb_frc_on(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0200,9,wr_val) 2938 #define rd_tx_pi_pd_bypass_flt() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,5,15,__ERR) 2939 #define wr_tx_pi_pd_bypass_flt(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0400,10,wr_val) 2940 #define rd_tx_pi_pd_bypass_vco() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd075,4,15,__ERR) 2941 #define wr_tx_pi_pd_bypass_vco(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd075,0x0800,11,wr_val) 2942 #define rd_tx_pi_phase_cntr() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd078,9,9,__ERR) 2943 #define rd_tx_pi_integ1_reg() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd079,2,2,__ERR) 2944 #define rd_tx_pi_integ2_reg() _merlin16_pcieg3_pmd_rde_field_signed(sa__, 0xd07a,1,1,__ERR) 2945 #define rd_tx_pi_phase_err() _merlin16_pcieg3_pmd_rde_field_signed_byte(sa__, 0xd07b,10,10,__ERR) 2946 #define rd_st_afe_tx_fifo_resetb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd07c,14,15,__ERR) 2947 #define rd_tx_pi_hs_fifo_phserr() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd07c,15,15,__ERR) 2948 #define rd_tx_fifo_ovfb_fall_edge_lh() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd07d,14,15,__ERR) 2949 #define rd_tx_fifo_ovfb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd07d,15,15,__ERR) 2950 #define rd_ana_tca_power_on_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a0,9,15,__ERR) 2951 #define wr_ana_tca_power_on_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a0,0x0040,6,wr_val) 2952 #define rd_tca_done_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a0,10,15,__ERR) 2953 #define wr_tca_done_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a0,0x0020,5,wr_val) 2954 #define rd_tca_done_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a0,11,15,__ERR) 2955 #define wr_tca_done_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a0,0x0010,4,wr_val) 2956 #define rd_tca_timer_sel() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a0,12,14,__ERR) 2957 #define wr_tca_timer_sel(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a0,0x000c,2,wr_val) 2958 #define rd_tca_restart() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a0,14,15,__ERR) 2959 #define wr_tca_restart(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a0,0x0002,1,wr_val) 2960 #define rd_tca_disable() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a0,15,15,__ERR) 2961 #define wr_tca_disable(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a0,0x0001,0,wr_val) 2962 #define rd_tca_wait_timer() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd1a1,2,2,__ERR) 2963 #define wr_tca_wait_timer(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd1a1,0x3fff,0,wr_val) 2964 #define rd_tca_coarse_timer() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd1a2,2,2,__ERR) 2965 #define wr_tca_coarse_timer(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd1a2,0x3fff,0,wr_val) 2966 #define rd_tca_fine_timer() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd1a3,2,2,__ERR) 2967 #define wr_tca_fine_timer(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd1a3,0x3fff,0,wr_val) 2968 #define rd_phserr_win_coarse() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a4,0,9,__ERR) 2969 #define wr_phserr_win_coarse(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a4,0xfe00,9,wr_val) 2970 #define rd_phserr_win_fine() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a4,7,9,__ERR) 2971 #define wr_phserr_win_fine(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a4,0x01fc,2,wr_val) 2972 #define rd_fine_done_by_timer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a4,14,15,__ERR) 2973 #define wr_fine_done_by_timer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a4,0x0002,1,wr_val) 2974 #define rd_coarse_done_by_timer() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a4,15,15,__ERR) 2975 #define wr_coarse_done_by_timer(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a4,0x0001,0,wr_val) 2976 #define rd_tx_pi_offset_en() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a5,0,15,__ERR) 2977 #define wr_tx_pi_offset_en(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a5,0x8000,15,wr_val) 2978 #define rd_tx_pi_offset_dir() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a5,1,15,__ERR) 2979 #define wr_tx_pi_offset_dir(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a5,0x4000,14,wr_val) 2980 #define rd_tx_pi_shift_num() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a5,2,12,__ERR) 2981 #define wr_tx_pi_shift_num(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd1a5,0x3c00,10,wr_val) 2982 #define rd_tx_pi_offset_num() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd1a5,6,6,__ERR) 2983 #define wr_tx_pi_offset_num(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd1a5,0x03ff,0,wr_val) 2984 #define rd_tca_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd1a6,13,13,__ERR) 2985 #define rd_tx_osr_mode_frc() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd190,0,15,__ERR) 2986 #define wr_tx_osr_mode_frc(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd190,0x8000,15,wr_val) 2987 #define rd_tx_osr_mode_frc_val() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd190,12,12,__ERR) 2988 #define wr_tx_osr_mode_frc_val(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd190,0x000f,0,wr_val) 2989 #define rd_tx_ln_dp_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd191,15,15,__ERR) 2990 #define wr_tx_ln_dp_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd191,0x0001,0,wr_val) 2991 #define rd_tx_ln_s_rstb() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd19e,15,15,__ERR) 2992 #define wr_tx_ln_s_rstb(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd19e,0x0001,0,wr_val) 2993 #define rd_pmd_ln_tx_dp_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd193,14,15,__ERR) 2994 #define wr_pmd_ln_tx_dp_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd193,0x0002,1,wr_val) 2995 #define rd_pmd_ln_tx_h_rstb_pkill() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd193,15,15,__ERR) 2996 #define wr_pmd_ln_tx_h_rstb_pkill(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd193,0x0001,0,wr_val) 2997 #define rd_tx_uc_ack_lane_dp_reset() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd195,14,15,__ERR) 2998 #define wr_tx_uc_ack_lane_dp_reset(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd195,0x0002,1,wr_val) 2999 #define rd_tx_uc_ack_lane_cfg_done() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd195,15,15,__ERR) 3000 #define wr_tx_uc_ack_lane_cfg_done(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd195,0x0001,0,wr_val) 3001 #define rd_tx_lane_dp_reset_state() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd199,13,13,__ERR) 3002 #define rd_tx_lane_reg_reset_occurred() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd196,15,15,__ERR) 3003 #define wr_tx_lane_reg_reset_occurred(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd196,0x0001,0,wr_val) 3004 #define rd_tx_multicast_mask_control() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd19a,15,15,__ERR) 3005 #define wr_tx_multicast_mask_control(wr_val) _merlin16_pcieg3_pmd_mwr_reg_byte(sa__, 0xd19a,0x0001,0,wr_val) 3006 #define rd_tx_multicast_mask_control_status() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd19b,11,15,__ERR) 3007 #define rd_tx_osr_mode() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd19b,12,12,__ERR) 3008 #define rd_tx_osr_mode_pin() _merlin16_pcieg3_pmd_rde_field_byte(sa__, 0xd19c,12,12,__ERR) 3009 #define rdc_txcom_cl72_max_wait_timer_period() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd130,__ERR) 3010 #define wrc_txcom_cl72_max_wait_timer_period(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd130,wr_val) 3011 #define rdc_txcom_cl72_wait_cntr_limit() _merlin16_pcieg3_pmd_rde_field(sa__, 0xd131,7,7,__ERR) 3012 #define wrc_txcom_cl72_wait_cntr_limit(wr_val) merlin16_pcieg3_pmd_mwr_reg(sa__, 0xd131,0x01ff,0,wr_val) 3013 3014 #define reg_rd_AMS_RX_RX_CTRL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd090,__ERR) 3015 #define reg_wr_AMS_RX_RX_CTRL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd090,wr_val) 3016 #define reg_rd_AMS_RX_RX_CTRL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd091,__ERR) 3017 #define reg_wr_AMS_RX_RX_CTRL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd091,wr_val) 3018 #define reg_rd_AMS_RX_RX_CTRL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd092,__ERR) 3019 #define reg_wr_AMS_RX_RX_CTRL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd092,wr_val) 3020 #define reg_rd_AMS_RX_RX_CTRL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd093,__ERR) 3021 #define reg_wr_AMS_RX_RX_CTRL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd093,wr_val) 3022 #define reg_rd_AMS_RX_RX_CTRL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd094,__ERR) 3023 #define reg_wr_AMS_RX_RX_CTRL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd094,wr_val) 3024 #define reg_rd_AMS_RX_RX_CTRL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd095,__ERR) 3025 #define reg_wr_AMS_RX_RX_CTRL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd095,wr_val) 3026 #define reg_rd_AMS_RX_RX_CTRL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd096,__ERR) 3027 #define reg_wr_AMS_RX_RX_CTRL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd096,wr_val) 3028 #define reg_rd_AMS_RX_RX_CTRL_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd097,__ERR) 3029 #define reg_wr_AMS_RX_RX_CTRL_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd097,wr_val) 3030 #define reg_rd_AMS_RX_RX_INT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd098,__ERR) 3031 #define reg_wr_AMS_RX_RX_INT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd098,wr_val) 3032 #define reg_rd_AMS_RX_RX_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd099,__ERR) 3033 #define reg_wr_AMS_RX_RX_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd099,wr_val) 3034 #define reg_rd_AMS_TX_TX_CTRL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a0,__ERR) 3035 #define reg_wr_AMS_TX_TX_CTRL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a0,wr_val) 3036 #define reg_rd_AMS_TX_TX_CTRL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a1,__ERR) 3037 #define reg_wr_AMS_TX_TX_CTRL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a1,wr_val) 3038 #define reg_rd_AMS_TX_TX_CTRL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a2,__ERR) 3039 #define reg_wr_AMS_TX_TX_CTRL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a2,wr_val) 3040 #define reg_rd_AMS_TX_TX_CTRL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a3,__ERR) 3041 #define reg_wr_AMS_TX_TX_CTRL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a3,wr_val) 3042 #define reg_rd_AMS_TX_TX_CTRL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a4,__ERR) 3043 #define reg_wr_AMS_TX_TX_CTRL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a4,wr_val) 3044 #define reg_rd_AMS_TX_TX_CTRL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a5,__ERR) 3045 #define reg_wr_AMS_TX_TX_CTRL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a5,wr_val) 3046 #define reg_rd_AMS_TX_TX_CTRL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a6,__ERR) 3047 #define reg_wr_AMS_TX_TX_CTRL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a6,wr_val) 3048 #define reg_rd_AMS_TX_TX_CTRL_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a7,__ERR) 3049 #define reg_wr_AMS_TX_TX_CTRL_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a7,wr_val) 3050 #define reg_rd_AMS_TX_TX_CTRL_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a8,__ERR) 3051 #define reg_wr_AMS_TX_TX_CTRL_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a8,wr_val) 3052 #define reg_rd_AMS_TX_TX_INT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0a9,__ERR) 3053 #define reg_wr_AMS_TX_TX_INT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0a9,wr_val) 3054 #define reg_rd_AMS_TX_TX_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0aa,__ERR) 3055 #define reg_wr_AMS_TX_TX_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0aa,wr_val) 3056 #define reg_rdc_AMS_COM_PLL_CTRL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b0,__ERR) 3057 #define reg_wrc_AMS_COM_PLL_CTRL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b0,wr_val) 3058 #define reg_rdc_AMS_COM_PLL_CTRL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b1,__ERR) 3059 #define reg_wrc_AMS_COM_PLL_CTRL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b1,wr_val) 3060 #define reg_rdc_AMS_COM_PLL_CTRL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b2,__ERR) 3061 #define reg_wrc_AMS_COM_PLL_CTRL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b2,wr_val) 3062 #define reg_rdc_AMS_COM_PLL_CTRL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b3,__ERR) 3063 #define reg_wrc_AMS_COM_PLL_CTRL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b3,wr_val) 3064 #define reg_rdc_AMS_COM_PLL_CTRL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b4,__ERR) 3065 #define reg_wrc_AMS_COM_PLL_CTRL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b4,wr_val) 3066 #define reg_rdc_AMS_COM_PLL_CTRL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b5,__ERR) 3067 #define reg_wrc_AMS_COM_PLL_CTRL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b5,wr_val) 3068 #define reg_rdc_AMS_COM_PLL_CTRL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b6,__ERR) 3069 #define reg_wrc_AMS_COM_PLL_CTRL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b6,wr_val) 3070 #define reg_rdc_AMS_COM_PLL_CTRL_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b7,__ERR) 3071 #define reg_wrc_AMS_COM_PLL_CTRL_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b7,wr_val) 3072 #define reg_rdc_AMS_COM_PLL_CTRL_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b8,__ERR) 3073 #define reg_wrc_AMS_COM_PLL_CTRL_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b8,wr_val) 3074 #define reg_rdc_AMS_COM_PLL_CTRL_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0b9,__ERR) 3075 #define reg_wrc_AMS_COM_PLL_CTRL_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0b9,wr_val) 3076 #define reg_rdc_AMS_COM_PLL_CTRL_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0ba,__ERR) 3077 #define reg_wrc_AMS_COM_PLL_CTRL_10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0ba,wr_val) 3078 #define reg_rdc_AMS_COM_PLL_INT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0be,__ERR) 3079 #define reg_wrc_AMS_COM_PLL_INT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0be,wr_val) 3080 #define reg_rdc_AMS_COM_PLL_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0bf,__ERR) 3081 #define reg_wrc_AMS_COM_PLL_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0bf,wr_val) 3082 #define reg_rdc_DIG_COM_B_LANE_ADDR_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd150,__ERR) 3083 #define reg_wrc_DIG_COM_B_LANE_ADDR_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd150,wr_val) 3084 #define reg_rdc_DIG_COM_B_LANE_ADDR_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd151,__ERR) 3085 #define reg_wrc_DIG_COM_B_LANE_ADDR_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd151,wr_val) 3086 #define reg_rdc_DIG_COM_B_LANE_ADDR_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd152,__ERR) 3087 #define reg_wrc_DIG_COM_B_LANE_ADDR_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd152,wr_val) 3088 #define reg_rdc_DIG_COM_B_LANE_ADDR_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd153,__ERR) 3089 #define reg_wrc_DIG_COM_B_LANE_ADDR_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd153,wr_val) 3090 #define reg_rdc_DIG_COM_REVID0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f0,__ERR) 3091 #define reg_wrc_DIG_COM_REVID0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f0,wr_val) 3092 #define reg_rdc_DIG_COM_REVID1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0fa,__ERR) 3093 #define reg_wrc_DIG_COM_REVID1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0fa,wr_val) 3094 #define reg_rdc_DIG_COM_REVID2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0fe,__ERR) 3095 #define reg_wrc_DIG_COM_REVID2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0fe,wr_val) 3096 #define reg_rdc_DIG_COM_RESET_CONTROL_PMD() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f1,__ERR) 3097 #define reg_wrc_DIG_COM_RESET_CONTROL_PMD(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f1,wr_val) 3098 #define reg_rdc_DIG_COM_RESET_CONTROL_CORE_DP() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f2,__ERR) 3099 #define reg_wrc_DIG_COM_RESET_CONTROL_CORE_DP(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f2,wr_val) 3100 #define reg_rdc_DIG_COM_MASKDATA_REG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f3,__ERR) 3101 #define reg_wrc_DIG_COM_MASKDATA_REG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f3,wr_val) 3102 #define reg_rdc_DIG_COM_TOP_USER_CONTROL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f4,__ERR) 3103 #define reg_wrc_DIG_COM_TOP_USER_CONTROL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f4,wr_val) 3104 #define reg_rdc_DIG_COM_UC_ACK_CORE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f5,__ERR) 3105 #define reg_wrc_DIG_COM_UC_ACK_CORE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f5,wr_val) 3106 #define reg_rdc_DIG_COM_CORE_DP_RESET_STATE_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f8,__ERR) 3107 #define reg_wrc_DIG_COM_CORE_DP_RESET_STATE_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f8,wr_val) 3108 #define reg_rdc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f6,__ERR) 3109 #define reg_wrc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f6,wr_val) 3110 #define reg_rdc_DIG_COM_RST_SEQ_TIMER_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f7,__ERR) 3111 #define reg_wrc_DIG_COM_RST_SEQ_TIMER_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f7,wr_val) 3112 #define reg_rdc_DIG_COM_PMD_CORE_MODE_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0f9,__ERR) 3113 #define reg_wrc_DIG_COM_PMD_CORE_MODE_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0f9,wr_val) 3114 #define reg_rd_DSC_A_CDR_STATUS_INTEG_REG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd005,__ERR) 3115 #define reg_wr_DSC_A_CDR_STATUS_INTEG_REG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd005,wr_val) 3116 #define reg_rd_DSC_A_CDR_STATUS_PHASE_ERROR() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd006,__ERR) 3117 #define reg_wr_DSC_A_CDR_STATUS_PHASE_ERROR(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd006,wr_val) 3118 #define reg_rd_DSC_A_RX_PI_CNT_BIN_D() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd007,__ERR) 3119 #define reg_wr_DSC_A_RX_PI_CNT_BIN_D(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd007,wr_val) 3120 #define reg_rd_DSC_A_RX_PI_CNT_BIN_P() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd008,__ERR) 3121 #define reg_wr_DSC_A_RX_PI_CNT_BIN_P(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd008,wr_val) 3122 #define reg_rd_DSC_A_RX_PI_CNT_BIN_M() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd009,__ERR) 3123 #define reg_wr_DSC_A_RX_PI_CNT_BIN_M(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd009,wr_val) 3124 #define reg_rd_DSC_A_RX_PI_DIFF_BIN() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd00a,__ERR) 3125 #define reg_wr_DSC_A_RX_PI_DIFF_BIN(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd00a,wr_val) 3126 #define reg_rd_DSC_A_CDR_CONTROL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd001,__ERR) 3127 #define reg_wr_DSC_A_CDR_CONTROL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd001,wr_val) 3128 #define reg_rd_DSC_A_CDR_CONTROL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd002,__ERR) 3129 #define reg_wr_DSC_A_CDR_CONTROL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd002,wr_val) 3130 #define reg_rd_DSC_A_CDR_CONTROL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd003,__ERR) 3131 #define reg_wr_DSC_A_CDR_CONTROL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd003,wr_val) 3132 #define reg_rd_DSC_A_TRNSUM_CNTL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd00b,__ERR) 3133 #define reg_wr_DSC_A_TRNSUM_CNTL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd00b,wr_val) 3134 #define reg_rd_DSC_A_RX_PI_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd004,__ERR) 3135 #define reg_wr_DSC_A_RX_PI_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd004,wr_val) 3136 #define reg_rd_DSC_A_DSC_UC_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd00d,__ERR) 3137 #define reg_wr_DSC_A_DSC_UC_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd00d,wr_val) 3138 #define reg_rd_DSC_A_DSC_SCRATCH() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd00e,__ERR) 3139 #define reg_wr_DSC_A_DSC_SCRATCH(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd00e,wr_val) 3140 #define reg_rd_DSC_B_DSC_SM_CTRL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd010,__ERR) 3141 #define reg_wr_DSC_B_DSC_SM_CTRL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd010,wr_val) 3142 #define reg_rd_DSC_B_DSC_SM_CTRL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd011,__ERR) 3143 #define reg_wr_DSC_B_DSC_SM_CTRL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd011,wr_val) 3144 #define reg_rd_DSC_B_DSC_SM_CTRL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd012,__ERR) 3145 #define reg_wr_DSC_B_DSC_SM_CTRL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd012,wr_val) 3146 #define reg_rd_DSC_B_DSC_SM_CTRL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd013,__ERR) 3147 #define reg_wr_DSC_B_DSC_SM_CTRL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd013,wr_val) 3148 #define reg_rd_DSC_B_DSC_SM_CTRL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd014,__ERR) 3149 #define reg_wr_DSC_B_DSC_SM_CTRL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd014,wr_val) 3150 #define reg_rd_DSC_B_DSC_SM_CTRL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd015,__ERR) 3151 #define reg_wr_DSC_B_DSC_SM_CTRL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd015,wr_val) 3152 #define reg_rd_DSC_B_DSC_SM_CTRL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd016,__ERR) 3153 #define reg_wr_DSC_B_DSC_SM_CTRL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd016,wr_val) 3154 #define reg_rd_DSC_B_DSC_SM_CTRL_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd017,__ERR) 3155 #define reg_wr_DSC_B_DSC_SM_CTRL_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd017,wr_val) 3156 #define reg_rd_DSC_B_DSC_SM_CTRL_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd018,__ERR) 3157 #define reg_wr_DSC_B_DSC_SM_CTRL_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd018,wr_val) 3158 #define reg_rd_DSC_B_DSC_SM_CTRL_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd019,__ERR) 3159 #define reg_wr_DSC_B_DSC_SM_CTRL_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd019,wr_val) 3160 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd01b,__ERR) 3161 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd01b,wr_val) 3162 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd01c,__ERR) 3163 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd01c,wr_val) 3164 #define reg_rd_DSC_B_DSC_SM_STATUS_RESTART() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd01d,__ERR) 3165 #define reg_wr_DSC_B_DSC_SM_STATUS_RESTART(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd01d,wr_val) 3166 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd01e,__ERR) 3167 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd01e,wr_val) 3168 #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_LOCK() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd01a,__ERR) 3169 #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_LOCK(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd01a,wr_val) 3170 #define reg_rd_DSC_C_DFE_1_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd021,__ERR) 3171 #define reg_wr_DSC_C_DFE_1_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd021,wr_val) 3172 #define reg_rd_DSC_C_DFE_2_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd022,__ERR) 3173 #define reg_wr_DSC_C_DFE_2_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd022,wr_val) 3174 #define reg_rd_DSC_C_DFE_3_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd023,__ERR) 3175 #define reg_wr_DSC_C_DFE_3_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd023,wr_val) 3176 #define reg_rd_DSC_C_DFE_4_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd024,__ERR) 3177 #define reg_wr_DSC_C_DFE_4_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd024,wr_val) 3178 #define reg_rd_DSC_C_DFE_5_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd025,__ERR) 3179 #define reg_wr_DSC_C_DFE_5_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd025,wr_val) 3180 #define reg_rd_DSC_C_DFE_PAT_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd026,__ERR) 3181 #define reg_wr_DSC_C_DFE_PAT_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd026,wr_val) 3182 #define reg_rd_DSC_C_DFE_COMMON_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd020,__ERR) 3183 #define reg_wr_DSC_C_DFE_COMMON_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd020,wr_val) 3184 #define reg_rd_DSC_C_HWTUNE_OVR_OVERRIDE() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd02b,__ERR) 3185 #define reg_wr_DSC_C_HWTUNE_OVR_OVERRIDE(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd02b,wr_val) 3186 #define reg_rd_DSC_C_VGA_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd02c,__ERR) 3187 #define reg_wr_DSC_C_VGA_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd02c,wr_val) 3188 #define reg_rd_DSC_C_VGA_PAT_EYEDIAG_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd02d,__ERR) 3189 #define reg_wr_DSC_C_VGA_PAT_EYEDIAG_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd02d,wr_val) 3190 #define reg_rd_DSC_C_P1_FRAC_OFFS_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd02e,__ERR) 3191 #define reg_wr_DSC_C_P1_FRAC_OFFS_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd02e,wr_val) 3192 #define reg_rd_DSC_C_VGA_P1_MISC_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd027,__ERR) 3193 #define reg_wr_DSC_C_VGA_P1_MISC_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd027,wr_val) 3194 #define reg_rd_DSC_C_SLICER_OFFSET_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd02a,__ERR) 3195 #define reg_wr_DSC_C_SLICER_OFFSET_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd02a,wr_val) 3196 #define reg_rd_DSC_C_DC_SLICER_OFFSET_CTL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd029,__ERR) 3197 #define reg_wr_DSC_C_DC_SLICER_OFFSET_CTL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd029,wr_val) 3198 #define reg_rd_DSC_D_TRNSUM_CTL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd030,__ERR) 3199 #define reg_wr_DSC_D_TRNSUM_CTL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd030,wr_val) 3200 #define reg_rd_DSC_D_TRNSUM_CTL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd031,__ERR) 3201 #define reg_wr_DSC_D_TRNSUM_CTL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd031,wr_val) 3202 #define reg_rd_DSC_D_TRNSUM_CTL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd032,__ERR) 3203 #define reg_wr_DSC_D_TRNSUM_CTL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd032,wr_val) 3204 #define reg_rd_DSC_D_TRNSUM_CTL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd033,__ERR) 3205 #define reg_wr_DSC_D_TRNSUM_CTL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd033,wr_val) 3206 #define reg_rd_DSC_D_TRNSUM_STS_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd034,__ERR) 3207 #define reg_wr_DSC_D_TRNSUM_STS_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd034,wr_val) 3208 #define reg_rd_DSC_D_TRNSUM_STS_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd035,__ERR) 3209 #define reg_wr_DSC_D_TRNSUM_STS_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd035,wr_val) 3210 #define reg_rd_DSC_D_TRNSUM_STS_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd036,__ERR) 3211 #define reg_wr_DSC_D_TRNSUM_STS_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd036,wr_val) 3212 #define reg_rd_DSC_D_TRNSUM_STS_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd037,__ERR) 3213 #define reg_wr_DSC_D_TRNSUM_STS_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd037,wr_val) 3214 #define reg_rd_DSC_D_TRNSUM_STS_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd038,__ERR) 3215 #define reg_wr_DSC_D_TRNSUM_STS_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd038,wr_val) 3216 #define reg_rd_DSC_D_TRNSUM_STS_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd039,__ERR) 3217 #define reg_wr_DSC_D_TRNSUM_STS_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd039,wr_val) 3218 #define reg_rd_DSC_D_VGA_P1EYEDIAG_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd03a,__ERR) 3219 #define reg_wr_DSC_D_VGA_P1EYEDIAG_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd03a,wr_val) 3220 #define reg_rd_DSC_D_DFE_1_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd03b,__ERR) 3221 #define reg_wr_DSC_D_DFE_1_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd03b,wr_val) 3222 #define reg_rd_DSC_D_DFE_2_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd03c,__ERR) 3223 #define reg_wr_DSC_D_DFE_2_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd03c,wr_val) 3224 #define reg_rd_DSC_D_DFE_3_4_5_STS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd03d,__ERR) 3225 #define reg_wr_DSC_D_DFE_3_4_5_STS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd03d,wr_val) 3226 #define reg_rd_DSC_D_VGA_TAP_BIN() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd03e,__ERR) 3227 #define reg_wr_DSC_D_VGA_TAP_BIN(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd03e,wr_val) 3228 #define reg_rd_DSC_E_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd040,__ERR) 3229 #define reg_wr_DSC_E_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd040,wr_val) 3230 #define reg_rd_DSC_E_PF_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd041,__ERR) 3231 #define reg_wr_DSC_E_PF_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd041,wr_val) 3232 #define reg_rd_DSC_E_PF2_LOWP_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd042,__ERR) 3233 #define reg_wr_DSC_E_PF2_LOWP_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd042,wr_val) 3234 #define reg_rd_DSC_F_DSC_F_DATA_ODD_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd141,__ERR) 3235 #define reg_wr_DSC_F_DSC_F_DATA_ODD_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd141,wr_val) 3236 #define reg_rd_DSC_F_DSC_F_DATA_EVEN_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd142,__ERR) 3237 #define reg_wr_DSC_F_DSC_F_DATA_EVEN_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd142,wr_val) 3238 #define reg_rd_DSC_F_DSC_F_P1_ODD_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd143,__ERR) 3239 #define reg_wr_DSC_F_DSC_F_P1_ODD_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd143,wr_val) 3240 #define reg_rd_DSC_F_DSC_F_P1_EVEN_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd144,__ERR) 3241 #define reg_wr_DSC_F_DSC_F_P1_EVEN_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd144,wr_val) 3242 #define reg_rd_DSC_F_DSC_F_M1_ODD_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd145,__ERR) 3243 #define reg_wr_DSC_F_DSC_F_M1_ODD_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd145,wr_val) 3244 #define reg_rd_DSC_F_DSC_F_M1_EVEN_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd146,__ERR) 3245 #define reg_wr_DSC_F_DSC_F_M1_EVEN_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd146,wr_val) 3246 #define reg_rd_DSC_F_DSC_F_DC_OFFSET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd147,__ERR) 3247 #define reg_wr_DSC_F_DSC_F_DC_OFFSET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd147,wr_val) 3248 #define reg_rd_DSC_G_DSC_SM_CTL_15() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd260,__ERR) 3249 #define reg_wr_DSC_G_DSC_SM_CTL_15(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd260,wr_val) 3250 #define reg_rd_DSC_G_DSC_SM_CTL_16() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd261,__ERR) 3251 #define reg_wr_DSC_G_DSC_SM_CTL_16(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd261,wr_val) 3252 #define reg_rd_DSC_G_DSC_SM_CTL_17() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd262,__ERR) 3253 #define reg_wr_DSC_G_DSC_SM_CTL_17(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd262,wr_val) 3254 #define reg_rd_DSC_G_DSC_SM_CTL_18() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd263,__ERR) 3255 #define reg_wr_DSC_G_DSC_SM_CTL_18(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd263,wr_val) 3256 #define reg_rd_DSC_G_DSC_SM_CTL_19() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd264,__ERR) 3257 #define reg_wr_DSC_G_DSC_SM_CTL_19(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd264,wr_val) 3258 #define reg_rd_DSC_G_DSC_SM_CTL_20() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd265,__ERR) 3259 #define reg_wr_DSC_G_DSC_SM_CTL_20(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd265,wr_val) 3260 #define reg_rd_DSC_G_DSC_SM_CTL_21() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd266,__ERR) 3261 #define reg_wr_DSC_G_DSC_SM_CTL_21(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd266,wr_val) 3262 #define reg_rd_DSC_G_DSC_SM_CTL_22() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd267,__ERR) 3263 #define reg_wr_DSC_G_DSC_SM_CTL_22(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd267,wr_val) 3264 #define reg_rd_DSC_G_DSC_SM_CTL_23() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd268,__ERR) 3265 #define reg_wr_DSC_G_DSC_SM_CTL_23(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd268,wr_val) 3266 #define reg_rd_DSC_G_DSC_SM_CTL_24() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd269,__ERR) 3267 #define reg_wr_DSC_G_DSC_SM_CTL_24(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd269,wr_val) 3268 #define reg_rd_DSC_G_DSC_SM_CTL_25() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd26a,__ERR) 3269 #define reg_wr_DSC_G_DSC_SM_CTL_25(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd26a,wr_val) 3270 #define reg_rd_DSC_G_DSC_SM_CTL_26() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd26b,__ERR) 3271 #define reg_wr_DSC_G_DSC_SM_CTL_26(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd26b,wr_val) 3272 #define reg_rd_DSC_G_DSC_SM_CTL_27() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd26c,__ERR) 3273 #define reg_wr_DSC_G_DSC_SM_CTL_27(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd26c,wr_val) 3274 #define reg_rd_DSC_G_DSC_SM_CTL_28() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd26d,__ERR) 3275 #define reg_wr_DSC_G_DSC_SM_CTL_28(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd26d,wr_val) 3276 #define reg_rd_DSC_G_DSC_SM_CTL_29() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd26e,__ERR) 3277 #define reg_wr_DSC_G_DSC_SM_CTL_29(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd26e,wr_val) 3278 #define reg_rd_DSC_H_DSC_SM_CTL_30() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd270,__ERR) 3279 #define reg_wr_DSC_H_DSC_SM_CTL_30(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd270,wr_val) 3280 #define reg_rd_DSC_H_DSC_SM_CTL_31() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd271,__ERR) 3281 #define reg_wr_DSC_H_DSC_SM_CTL_31(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd271,wr_val) 3282 #define reg_rd_DSC_H_DSC_SM_CTL_32() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd272,__ERR) 3283 #define reg_wr_DSC_H_DSC_SM_CTL_32(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd272,wr_val) 3284 #define reg_rd_DSC_H_DSC_SM_CTL_33() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd273,__ERR) 3285 #define reg_wr_DSC_H_DSC_SM_CTL_33(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd273,wr_val) 3286 #define reg_rd_DSC_H_DSC_SM_CTL_34() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd274,__ERR) 3287 #define reg_wr_DSC_H_DSC_SM_CTL_34(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd274,wr_val) 3288 #define reg_rd_DSC_H_DSC_SM_STATUS_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd275,__ERR) 3289 #define reg_wr_DSC_H_DSC_SM_STATUS_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd275,wr_val) 3290 #define reg_rd_DSC_I_RX_HIST_STAT_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd280,__ERR) 3291 #define reg_wr_DSC_I_RX_HIST_STAT_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd280,wr_val) 3292 #define reg_rd_DSC_I_RX_HIST_STAT_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd281,__ERR) 3293 #define reg_wr_DSC_I_RX_HIST_STAT_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd281,wr_val) 3294 #define reg_rd_DSC_I_RX_HIST_STAT_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd282,__ERR) 3295 #define reg_wr_DSC_I_RX_HIST_STAT_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd282,wr_val) 3296 #define reg_rd_DSC_I_RX_HIST_STAT_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd283,__ERR) 3297 #define reg_wr_DSC_I_RX_HIST_STAT_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd283,wr_val) 3298 #define reg_rd_DSC_I_RX_HIST_STAT_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd284,__ERR) 3299 #define reg_wr_DSC_I_RX_HIST_STAT_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd284,wr_val) 3300 #define reg_rd_DSC_I_RX_HIST_STAT_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd285,__ERR) 3301 #define reg_wr_DSC_I_RX_HIST_STAT_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd285,wr_val) 3302 #define reg_rd_DSC_I_RX_HIST_STAT_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd286,__ERR) 3303 #define reg_wr_DSC_I_RX_HIST_STAT_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd286,wr_val) 3304 #define reg_rd_DSC_I_RX_HIST_STAT_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd287,__ERR) 3305 #define reg_wr_DSC_I_RX_HIST_STAT_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd287,wr_val) 3306 #define reg_rd_DSC_I_RX_HIST_STAT_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd288,__ERR) 3307 #define reg_wr_DSC_I_RX_HIST_STAT_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd288,wr_val) 3308 #define reg_rd_DSC_I_RX_HIST_STAT_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd289,__ERR) 3309 #define reg_wr_DSC_I_RX_HIST_STAT_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd289,wr_val) 3310 #define reg_rd_DSC_I_RX_HIST_STAT_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28a,__ERR) 3311 #define reg_wr_DSC_I_RX_HIST_STAT_10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd28a,wr_val) 3312 #define reg_rd_DSC_I_RX_HIST_STAT_11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28b,__ERR) 3313 #define reg_wr_DSC_I_RX_HIST_STAT_11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd28b,wr_val) 3314 #define reg_rd_DSC_I_RX_HIST_STAT_12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28c,__ERR) 3315 #define reg_wr_DSC_I_RX_HIST_STAT_12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd28c,wr_val) 3316 #define reg_rd_DSC_I_RX_HIST_STAT_13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28d,__ERR) 3317 #define reg_wr_DSC_I_RX_HIST_STAT_13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd28d,wr_val) 3318 #define reg_rd_DSC_I_RX_HIST_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd28e,__ERR) 3319 #define reg_wr_DSC_I_RX_HIST_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd28e,wr_val) 3320 #define reg_rd_DSC_J_DSC_SM_CTL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd290,__ERR) 3321 #define reg_wr_DSC_J_DSC_SM_CTL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd290,wr_val) 3322 #define reg_rd_DSC_J_DSC_SM_CTL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd291,__ERR) 3323 #define reg_wr_DSC_J_DSC_SM_CTL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd291,wr_val) 3324 #define reg_rd_DSC_J_DSC_SM_CTL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd292,__ERR) 3325 #define reg_wr_DSC_J_DSC_SM_CTL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd292,wr_val) 3326 #define reg_rd_DSC_J_DSC_SM_CTL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd293,__ERR) 3327 #define reg_wr_DSC_J_DSC_SM_CTL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd293,wr_val) 3328 #define reg_rd_DSC_J_DSC_SM_CTL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd294,__ERR) 3329 #define reg_wr_DSC_J_DSC_SM_CTL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd294,wr_val) 3330 #define reg_rd_DSC_J_DSC_SM_CTL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd295,__ERR) 3331 #define reg_wr_DSC_J_DSC_SM_CTL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd295,wr_val) 3332 #define reg_rd_DSC_J_DSC_SM_CTL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd296,__ERR) 3333 #define reg_wr_DSC_J_DSC_SM_CTL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd296,wr_val) 3334 #define reg_rd_DSC_J_DSC_SM_CTL_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd297,__ERR) 3335 #define reg_wr_DSC_J_DSC_SM_CTL_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd297,wr_val) 3336 #define reg_rd_DSC_J_DSC_SM_CTL_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd298,__ERR) 3337 #define reg_wr_DSC_J_DSC_SM_CTL_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd298,wr_val) 3338 #define reg_rd_DSC_J_DSC_SM_CTL_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd299,__ERR) 3339 #define reg_wr_DSC_J_DSC_SM_CTL_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd299,wr_val) 3340 #define reg_rd_DSC_J_DSC_SM_CTL_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd29a,__ERR) 3341 #define reg_wr_DSC_J_DSC_SM_CTL_10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd29a,wr_val) 3342 #define reg_rd_DSC_J_DSC_SM_CTL_11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd29b,__ERR) 3343 #define reg_wr_DSC_J_DSC_SM_CTL_11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd29b,wr_val) 3344 #define reg_rd_DSC_J_DSC_SM_CTL_12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd29c,__ERR) 3345 #define reg_wr_DSC_J_DSC_SM_CTL_12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd29c,wr_val) 3346 #define reg_rd_DSC_J_DSC_SM_CTL_13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd29d,__ERR) 3347 #define reg_wr_DSC_J_DSC_SM_CTL_13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd29d,wr_val) 3348 #define reg_rd_DSC_J_DSC_SM_CTL_14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd29e,__ERR) 3349 #define reg_wr_DSC_J_DSC_SM_CTL_14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd29e,wr_val) 3350 #define reg_rdc_MDIO_BLK_ADDR_COM_BLK_ADDR() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xffdf,__ERR) 3351 #define reg_wrc_MDIO_BLK_ADDR_COM_BLK_ADDR(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xffdf,wr_val) 3352 #define reg_rdc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xffdc,__ERR) 3353 #define reg_wrc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xffdc,wr_val) 3354 #define reg_rdc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xffdd,__ERR) 3355 #define reg_wrc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xffdd,wr_val) 3356 #define reg_rdc_MDIO_MMDSEL_AER_COM_MDIO_AER() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xffde,__ERR) 3357 #define reg_wrc_MDIO_MMDSEL_AER_COM_MDIO_AER(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xffde,wr_val) 3358 #define reg_rdc_MICRO_A_COM_CLOCK_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd200,__ERR) 3359 #define reg_wrc_MICRO_A_COM_CLOCK_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd200,wr_val) 3360 #define reg_rdc_MICRO_A_COM_RESET_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd201,__ERR) 3361 #define reg_wrc_MICRO_A_COM_RESET_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd201,wr_val) 3362 #define reg_rdc_MICRO_A_COM_AHB_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd202,__ERR) 3363 #define reg_wrc_MICRO_A_COM_AHB_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd202,wr_val) 3364 #define reg_rdc_MICRO_A_COM_AHB_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd203,__ERR) 3365 #define reg_wrc_MICRO_A_COM_AHB_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd203,wr_val) 3366 #define reg_rdc_MICRO_A_COM_AHB_WRADDR_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd204,__ERR) 3367 #define reg_wrc_MICRO_A_COM_AHB_WRADDR_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd204,wr_val) 3368 #define reg_rdc_MICRO_A_COM_AHB_WRADDR_MSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd205,__ERR) 3369 #define reg_wrc_MICRO_A_COM_AHB_WRADDR_MSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd205,wr_val) 3370 #define reg_rdc_MICRO_A_COM_AHB_WRDATA_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd206,__ERR) 3371 #define reg_wrc_MICRO_A_COM_AHB_WRDATA_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd206,wr_val) 3372 #define reg_rdc_MICRO_A_COM_AHB_WRDATA_MSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd207,__ERR) 3373 #define reg_wrc_MICRO_A_COM_AHB_WRDATA_MSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd207,wr_val) 3374 #define reg_rdc_MICRO_A_COM_AHB_RDADDR_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd208,__ERR) 3375 #define reg_wrc_MICRO_A_COM_AHB_RDADDR_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd208,wr_val) 3376 #define reg_rdc_MICRO_A_COM_AHB_RDADDR_MSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd209,__ERR) 3377 #define reg_wrc_MICRO_A_COM_AHB_RDADDR_MSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd209,wr_val) 3378 #define reg_rdc_MICRO_A_COM_AHB_RDDATA_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20a,__ERR) 3379 #define reg_wrc_MICRO_A_COM_AHB_RDDATA_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd20a,wr_val) 3380 #define reg_rdc_MICRO_A_COM_AHB_RDDATA_MSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20b,__ERR) 3381 #define reg_wrc_MICRO_A_COM_AHB_RDDATA_MSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd20b,wr_val) 3382 #define reg_rdc_MICRO_A_COM_PRAMIF_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20c,__ERR) 3383 #define reg_wrc_MICRO_A_COM_PRAMIF_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd20c,wr_val) 3384 #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20d,__ERR) 3385 #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd20d,wr_val) 3386 #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd20e,__ERR) 3387 #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd20e,wr_val) 3388 #define reg_rdc_MICRO_B_COM_PVT_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd210,__ERR) 3389 #define reg_wrc_MICRO_B_COM_PVT_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd210,wr_val) 3390 #define reg_rdc_MICRO_B_COM_RMI_TO_MICRO_MBOX0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd211,__ERR) 3391 #define reg_wrc_MICRO_B_COM_RMI_TO_MICRO_MBOX0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd211,wr_val) 3392 #define reg_rdc_MICRO_B_COM_RMI_TO_MICRO_MBOX1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd212,__ERR) 3393 #define reg_wrc_MICRO_B_COM_RMI_TO_MICRO_MBOX1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd212,wr_val) 3394 #define reg_rdc_MICRO_B_COM_MICRO_TO_RMI_MBOX0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd213,__ERR) 3395 #define reg_wrc_MICRO_B_COM_MICRO_TO_RMI_MBOX0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd213,wr_val) 3396 #define reg_rdc_MICRO_B_COM_MICRO_TO_RMI_MBOX1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd214,__ERR) 3397 #define reg_wrc_MICRO_B_COM_MICRO_TO_RMI_MBOX1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd214,wr_val) 3398 #define reg_rdc_MICRO_B_COM_RMI_MBOX_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd215,__ERR) 3399 #define reg_wrc_MICRO_B_COM_RMI_MBOX_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd215,wr_val) 3400 #define reg_rdc_MICRO_B_COM_RMI_AHB_CONTROL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd216,__ERR) 3401 #define reg_wrc_MICRO_B_COM_RMI_AHB_CONTROL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd216,wr_val) 3402 #define reg_rdc_MICRO_B_COM_RMI_AHB_STATUS1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd217,__ERR) 3403 #define reg_wrc_MICRO_B_COM_RMI_AHB_STATUS1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd217,wr_val) 3404 #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd218,__ERR) 3405 #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd218,wr_val) 3406 #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd219,__ERR) 3407 #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd219,wr_val) 3408 #define reg_rdc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd21a,__ERR) 3409 #define reg_wrc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd21a,wr_val) 3410 #define reg_rdc_MICRO_B_COM_RMI_PVT_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd21b,__ERR) 3411 #define reg_wrc_MICRO_B_COM_RMI_PVT_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd21b,wr_val) 3412 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCCONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd220,__ERR) 3413 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCCONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd220,wr_val) 3414 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCCONTRO1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd221,__ERR) 3415 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCCONTRO1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd221,wr_val) 3416 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCSTATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd222,__ERR) 3417 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCSTATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd222,wr_val) 3418 #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCSTATUS1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd223,__ERR) 3419 #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCSTATUS1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd223,wr_val) 3420 #define reg_rdc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd224,__ERR) 3421 #define reg_wrc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd224,wr_val) 3422 #define reg_rdc_MICRO_C_COM_RAM_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd225,__ERR) 3423 #define reg_wrc_MICRO_C_COM_RAM_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd225,wr_val) 3424 #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd227,__ERR) 3425 #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd227,wr_val) 3426 #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd226,__ERR) 3427 #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd226,wr_val) 3428 #define reg_rdc_MICRO_C_COM_RMI_PMI_IF_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd228,__ERR) 3429 #define reg_wrc_MICRO_C_COM_RMI_PMI_IF_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd228,wr_val) 3430 #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd229,__ERR) 3431 #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd229,wr_val) 3432 #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd22a,__ERR) 3433 #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd22a,wr_val) 3434 #define reg_rd_MICRO_CTRL0_UC_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd240,__ERR) 3435 #define reg_wr_MICRO_CTRL0_UC_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd240,wr_val) 3436 #define reg_rd_MICRO_CTRL0_UC_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd241,__ERR) 3437 #define reg_wr_MICRO_CTRL0_UC_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd241,wr_val) 3438 #define reg_rd_MICRO_CTRL0_UC_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd242,__ERR) 3439 #define reg_wr_MICRO_CTRL0_UC_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd242,wr_val) 3440 #define reg_rd_MICRO_CTRL0_UC_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd243,__ERR) 3441 #define reg_wr_MICRO_CTRL0_UC_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd243,wr_val) 3442 #define reg_rd_MICRO_CTRL0_LP_INFO0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd244,__ERR) 3443 #define reg_wr_MICRO_CTRL0_LP_INFO0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd244,wr_val) 3444 #define reg_rd_MICRO_CTRL0_LP_INFO1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd245,__ERR) 3445 #define reg_wr_MICRO_CTRL0_LP_INFO1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd245,wr_val) 3446 #define reg_rd_MICRO_CTRL0_LP_INFO2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd246,__ERR) 3447 #define reg_wr_MICRO_CTRL0_LP_INFO2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd246,wr_val) 3448 #define reg_rd_MICRO_CTRL0_UC_EVAL_STAT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd247,__ERR) 3449 #define reg_wr_MICRO_CTRL0_UC_EVAL_STAT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd247,wr_val) 3450 #define reg_rd_MICRO_DBG_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd250,__ERR) 3451 #define reg_wr_MICRO_DBG_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd250,wr_val) 3452 #define reg_rd_MICRO_DBG_MICRO_DEBUG1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd251,__ERR) 3453 #define reg_wr_MICRO_DBG_MICRO_DEBUG1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd251,wr_val) 3454 #define reg_rd_MICRO_DBG_MICRO_DEBUG2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd252,__ERR) 3455 #define reg_wr_MICRO_DBG_MICRO_DEBUG2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd252,wr_val) 3456 #define reg_rd_MICRO_DBG_MICRO_DEBUG3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd253,__ERR) 3457 #define reg_wr_MICRO_DBG_MICRO_DEBUG3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd253,wr_val) 3458 #define reg_rd_MICRO_DBG_MICRO_DEBUG4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd254,__ERR) 3459 #define reg_wr_MICRO_DBG_MICRO_DEBUG4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd254,wr_val) 3460 #define reg_rd_MICRO_DBG_MICRO_DEBUG5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd255,__ERR) 3461 #define reg_wr_MICRO_DBG_MICRO_DEBUG5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd255,wr_val) 3462 #define reg_rd_MICRO_DBG_MICRO_DEBUG6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd256,__ERR) 3463 #define reg_wr_MICRO_DBG_MICRO_DEBUG6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd256,wr_val) 3464 #define reg_rd_MICRO_DBG_MICRO_DEBUG7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd257,__ERR) 3465 #define reg_wr_MICRO_DBG_MICRO_DEBUG7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd257,wr_val) 3466 #define reg_rd_MICRO_DBG_MICRO_DEBUG8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd258,__ERR) 3467 #define reg_wr_MICRO_DBG_MICRO_DEBUG8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd258,wr_val) 3468 #define reg_rd_MICRO_DBG_MICRO_DEBUG9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd259,__ERR) 3469 #define reg_wr_MICRO_DBG_MICRO_DEBUG9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd259,wr_val) 3470 #define reg_rd_MICRO_DBG_MICRO_DEBUG10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25a,__ERR) 3471 #define reg_wr_MICRO_DBG_MICRO_DEBUG10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25a,wr_val) 3472 #define reg_rd_MICRO_DBG_MICRO_DEBUG11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25b,__ERR) 3473 #define reg_wr_MICRO_DBG_MICRO_DEBUG11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25b,wr_val) 3474 #define reg_rd_MICRO_DBG_MICRO_DEBUG12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25c,__ERR) 3475 #define reg_wr_MICRO_DBG_MICRO_DEBUG12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25c,wr_val) 3476 #define reg_rd_MICRO_DBG_MICRO_DEBUG13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25d,__ERR) 3477 #define reg_wr_MICRO_DBG_MICRO_DEBUG13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25d,wr_val) 3478 #define reg_rd_MICRO_DBG_MICRO_DEBUG14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd25e,__ERR) 3479 #define reg_wr_MICRO_DBG_MICRO_DEBUG14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd25e,wr_val) 3480 #define reg_rdc_MICRO_INFO_COM_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd230,__ERR) 3481 #define reg_wrc_MICRO_INFO_COM_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd230,wr_val) 3482 #define reg_rdc_MICRO_INFO_COM_EVAL_STAT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd231,__ERR) 3483 #define reg_wrc_MICRO_INFO_COM_EVAL_STAT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd231,wr_val) 3484 #define reg_rdc_PATT_GEN_COM_SEQ_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd100,__ERR) 3485 #define reg_wrc_PATT_GEN_COM_SEQ_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd100,wr_val) 3486 #define reg_rdc_PATT_GEN_COM_SEQ_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd101,__ERR) 3487 #define reg_wrc_PATT_GEN_COM_SEQ_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd101,wr_val) 3488 #define reg_rdc_PATT_GEN_COM_SEQ_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd102,__ERR) 3489 #define reg_wrc_PATT_GEN_COM_SEQ_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd102,wr_val) 3490 #define reg_rdc_PATT_GEN_COM_SEQ_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd103,__ERR) 3491 #define reg_wrc_PATT_GEN_COM_SEQ_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd103,wr_val) 3492 #define reg_rdc_PATT_GEN_COM_SEQ_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd104,__ERR) 3493 #define reg_wrc_PATT_GEN_COM_SEQ_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd104,wr_val) 3494 #define reg_rdc_PATT_GEN_COM_SEQ_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd105,__ERR) 3495 #define reg_wrc_PATT_GEN_COM_SEQ_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd105,wr_val) 3496 #define reg_rdc_PATT_GEN_COM_SEQ_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd106,__ERR) 3497 #define reg_wrc_PATT_GEN_COM_SEQ_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd106,wr_val) 3498 #define reg_rdc_PATT_GEN_COM_SEQ_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd107,__ERR) 3499 #define reg_wrc_PATT_GEN_COM_SEQ_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd107,wr_val) 3500 #define reg_rdc_PATT_GEN_COM_SEQ_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd108,__ERR) 3501 #define reg_wrc_PATT_GEN_COM_SEQ_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd108,wr_val) 3502 #define reg_rdc_PATT_GEN_COM_SEQ_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd109,__ERR) 3503 #define reg_wrc_PATT_GEN_COM_SEQ_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd109,wr_val) 3504 #define reg_rdc_PATT_GEN_COM_SEQ_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10a,__ERR) 3505 #define reg_wrc_PATT_GEN_COM_SEQ_10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10a,wr_val) 3506 #define reg_rdc_PATT_GEN_COM_SEQ_11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10b,__ERR) 3507 #define reg_wrc_PATT_GEN_COM_SEQ_11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10b,wr_val) 3508 #define reg_rdc_PATT_GEN_COM_SEQ_12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10c,__ERR) 3509 #define reg_wrc_PATT_GEN_COM_SEQ_12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10c,wr_val) 3510 #define reg_rdc_PATT_GEN_COM_SEQ_13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10d,__ERR) 3511 #define reg_wrc_PATT_GEN_COM_SEQ_13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10d,wr_val) 3512 #define reg_rdc_PATT_GEN_COM_SEQ_14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd10e,__ERR) 3513 #define reg_wrc_PATT_GEN_COM_SEQ_14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd10e,wr_val) 3514 #define reg_rdexc_PCIE_BLK0_EXT_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1000,__ERR) 3515 #define reg_wrexc_PCIE_BLK0_EXT_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1000,wr_val) 3516 #define reg_rdexc_PCIE_BLK0_EXT_RXSIGDET() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1003,__ERR) 3517 #define reg_wrexc_PCIE_BLK0_EXT_RXSIGDET(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1003,wr_val) 3518 #define reg_rdexc_PCIE_BLK0_EXT_LNSTATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1004,__ERR) 3519 #define reg_wrexc_PCIE_BLK0_EXT_LNSTATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1004,wr_val) 3520 #define reg_rdexc_PCIE_BLK0_EXT_LNSTATUS2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1005,__ERR) 3521 #define reg_wrexc_PCIE_BLK0_EXT_LNSTATUS2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1005,wr_val) 3522 #define reg_rdexc_PCIE_BLK0_EXT_MDIO_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1006,__ERR) 3523 #define reg_wrexc_PCIE_BLK0_EXT_MDIO_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1006,wr_val) 3524 #define reg_rdexc_PCIE_BLK0_EXT_RATE_SEL_STAT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1007,__ERR) 3525 #define reg_wrexc_PCIE_BLK0_EXT_RATE_SEL_STAT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1007,wr_val) 3526 #define reg_rdexc_PCIE_BLK1_EXT_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1100,__ERR) 3527 #define reg_wrexc_PCIE_BLK1_EXT_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1100,wr_val) 3528 #define reg_rdexc_PCIE_BLK1_EXT_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1101,__ERR) 3529 #define reg_wrexc_PCIE_BLK1_EXT_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1101,wr_val) 3530 #define reg_rdexc_PCIE_BLK1_EXT_MISCCONTROL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1102,__ERR) 3531 #define reg_wrexc_PCIE_BLK1_EXT_MISCCONTROL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1102,wr_val) 3532 #define reg_rdexc_PCIE_BLK1_EXT_STATUS_REG2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1103,__ERR) 3533 #define reg_wrexc_PCIE_BLK1_EXT_STATUS_REG2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1103,wr_val) 3534 #define reg_rdexc_PCIE_BLK1_EXT_GPIO_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1104,__ERR) 3535 #define reg_wrexc_PCIE_BLK1_EXT_GPIO_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1104,wr_val) 3536 #define reg_rdexc_PCIE_BLK1_EXT_GPIO_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1105,__ERR) 3537 #define reg_wrexc_PCIE_BLK1_EXT_GPIO_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1105,wr_val) 3538 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1106,__ERR) 3539 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1106,wr_val) 3540 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1107,__ERR) 3541 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1107,wr_val) 3542 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1108,__ERR) 3543 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1108,wr_val) 3544 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1109,__ERR) 3545 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1109,wr_val) 3546 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x110a,__ERR) 3547 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x110a,wr_val) 3548 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x110b,__ERR) 3549 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x110b,wr_val) 3550 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x110c,__ERR) 3551 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x110c,wr_val) 3552 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x110d,__ERR) 3553 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x110d,wr_val) 3554 #define reg_rdexc_PCIE_BLK1_EXT_DBG_CTRL8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x110e,__ERR) 3555 #define reg_wrexc_PCIE_BLK1_EXT_DBG_CTRL8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x110e,wr_val) 3556 #define reg_rdexc_PCIE_BLK2_EXT_LFCKCNT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1200,__ERR) 3557 #define reg_wrexc_PCIE_BLK2_EXT_LFCKCNT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1200,wr_val) 3558 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1201,__ERR) 3559 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1201,wr_val) 3560 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1202,__ERR) 3561 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1202,wr_val) 3562 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1203,__ERR) 3563 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1203,wr_val) 3564 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1204,__ERR) 3565 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1204,wr_val) 3566 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1205,__ERR) 3567 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1205,wr_val) 3568 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1206,__ERR) 3569 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1206,wr_val) 3570 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1207,__ERR) 3571 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1207,wr_val) 3572 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1208,__ERR) 3573 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1208,wr_val) 3574 #define reg_rdexc_PCIE_BLK2_EXT_PWRMGMT8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1209,__ERR) 3575 #define reg_wrexc_PCIE_BLK2_EXT_PWRMGMT8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1209,wr_val) 3576 #define reg_rdexc_PCIE_BLK2_EXT_REFCLKSENSE_STAT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x120a,__ERR) 3577 #define reg_wrexc_PCIE_BLK2_EXT_REFCLKSENSE_STAT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x120a,wr_val) 3578 #define reg_rdexc_PCIE_BLK2_EXT_REFCLKSENSE_STAT2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x120b,__ERR) 3579 #define reg_wrexc_PCIE_BLK2_EXT_REFCLKSENSE_STAT2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x120b,wr_val) 3580 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1300,__ERR) 3581 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1300,wr_val) 3582 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1301,__ERR) 3583 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1301,wr_val) 3584 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1302,__ERR) 3585 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1302,wr_val) 3586 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1303,__ERR) 3587 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1303,wr_val) 3588 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1304,__ERR) 3589 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1304,wr_val) 3590 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1305,__ERR) 3591 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1305,wr_val) 3592 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1306,__ERR) 3593 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1306,wr_val) 3594 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1307,__ERR) 3595 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1307,wr_val) 3596 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1308,__ERR) 3597 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1308,wr_val) 3598 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1309,__ERR) 3599 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1309,wr_val) 3600 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130a,__ERR) 3601 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130a,wr_val) 3602 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130b,__ERR) 3603 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130b,wr_val) 3604 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130c,__ERR) 3605 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130c,wr_val) 3606 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130d,__ERR) 3607 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130d,wr_val) 3608 #define reg_rdexc_PCIE_BLK3_EXT_GEN2CTRL14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x130e,__ERR) 3609 #define reg_wrexc_PCIE_BLK3_EXT_GEN2CTRL14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x130e,wr_val) 3610 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1400,__ERR) 3611 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1400,wr_val) 3612 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1401,__ERR) 3613 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1401,wr_val) 3614 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1402,__ERR) 3615 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1402,wr_val) 3616 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1403,__ERR) 3617 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1403,wr_val) 3618 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1404,__ERR) 3619 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1404,wr_val) 3620 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1405,__ERR) 3621 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1405,wr_val) 3622 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1406,__ERR) 3623 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1406,wr_val) 3624 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1407,__ERR) 3625 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1407,wr_val) 3626 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1408,__ERR) 3627 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1408,wr_val) 3628 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1409,__ERR) 3629 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1409,wr_val) 3630 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140a,__ERR) 3631 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140a,wr_val) 3632 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140b,__ERR) 3633 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140b,wr_val) 3634 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140c,__ERR) 3635 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140c,wr_val) 3636 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140d,__ERR) 3637 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140d,wr_val) 3638 #define reg_rdexc_PCIE_BLK4_EXT_LANECTRL14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x140e,__ERR) 3639 #define reg_wrexc_PCIE_BLK4_EXT_LANECTRL14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x140e,wr_val) 3640 #define reg_rdexc_PCIE_BLK5_EXT_LANECTRL15() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1500,__ERR) 3641 #define reg_wrexc_PCIE_BLK5_EXT_LANECTRL15(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1500,wr_val) 3642 #define reg_rdexc_PCIE_BLK5_EXT_LANEPRBS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1501,__ERR) 3643 #define reg_wrexc_PCIE_BLK5_EXT_LANEPRBS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1501,wr_val) 3644 #define reg_rdexc_PCIE_BLK5_EXT_LANEPRBS1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1502,__ERR) 3645 #define reg_wrexc_PCIE_BLK5_EXT_LANEPRBS1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1502,wr_val) 3646 #define reg_rdexc_PCIE_BLK5_EXT_LANEPRBS2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1503,__ERR) 3647 #define reg_wrexc_PCIE_BLK5_EXT_LANEPRBS2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1503,wr_val) 3648 #define reg_rdexc_PCIE_BLK5_EXT_LANEPRBS3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1504,__ERR) 3649 #define reg_wrexc_PCIE_BLK5_EXT_LANEPRBS3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1504,wr_val) 3650 #define reg_rdexc_PCIE_BLK5_EXT_LANEPRBS4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1505,__ERR) 3651 #define reg_wrexc_PCIE_BLK5_EXT_LANEPRBS4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1505,wr_val) 3652 #define reg_rdexc_PCIE_BLK5_EXT_LANETEST0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1506,__ERR) 3653 #define reg_wrexc_PCIE_BLK5_EXT_LANETEST0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1506,wr_val) 3654 #define reg_rdexc_PCIE_BLK5_EXT_LANETEST1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1507,__ERR) 3655 #define reg_wrexc_PCIE_BLK5_EXT_LANETEST1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1507,wr_val) 3656 #define reg_rdexc_PCIE_BLK5_EXT_COMP_DELAY0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1508,__ERR) 3657 #define reg_wrexc_PCIE_BLK5_EXT_COMP_DELAY0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1508,wr_val) 3658 #define reg_rdexc_PCIE_BLK5_EXT_COMP_DELAY1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1509,__ERR) 3659 #define reg_wrexc_PCIE_BLK5_EXT_COMP_DELAY1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1509,wr_val) 3660 #define reg_rdexc_PCIE_BLK5_EXT_COMP_TYPE() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x150a,__ERR) 3661 #define reg_wrexc_PCIE_BLK5_EXT_COMP_TYPE(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x150a,wr_val) 3662 #define reg_rdexc_PCIE_BLK5_EXT_COMP_ENABLE() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x150b,__ERR) 3663 #define reg_wrexc_PCIE_BLK5_EXT_COMP_ENABLE(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x150b,wr_val) 3664 #define reg_rdexc_PCIE_BLK5_EXT_XGXS_FE_TMUX() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x150e,__ERR) 3665 #define reg_wrexc_PCIE_BLK5_EXT_XGXS_FE_TMUX(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x150e,wr_val) 3666 #define reg_rdexc_PCIE_BLK6_EXT_PMD_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1600,__ERR) 3667 #define reg_wrexc_PCIE_BLK6_EXT_PMD_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1600,wr_val) 3668 #define reg_rdexc_PCIE_BLK6_EXT_PMD_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1601,__ERR) 3669 #define reg_wrexc_PCIE_BLK6_EXT_PMD_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1601,wr_val) 3670 #define reg_rdexc_PCIE_BLK6_EXT_PMD_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1602,__ERR) 3671 #define reg_wrexc_PCIE_BLK6_EXT_PMD_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1602,wr_val) 3672 #define reg_rdexc_PCIE_BLK6_EXT_ANA_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1603,__ERR) 3673 #define reg_wrexc_PCIE_BLK6_EXT_ANA_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1603,wr_val) 3674 #define reg_rdexc_PCIE_BLK7_EXT_TX_COEFF_LO() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1700,__ERR) 3675 #define reg_wrexc_PCIE_BLK7_EXT_TX_COEFF_LO(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1700,wr_val) 3676 #define reg_rdexc_PCIE_BLK7_EXT_TX_COEFF_HI() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1701,__ERR) 3677 #define reg_wrexc_PCIE_BLK7_EXT_TX_COEFF_HI(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1701,wr_val) 3678 #define reg_rdexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1702,__ERR) 3679 #define reg_wrexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1702,wr_val) 3680 #define reg_rdexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1703,__ERR) 3681 #define reg_wrexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1703,wr_val) 3682 #define reg_rdexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1704,__ERR) 3683 #define reg_wrexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1704,wr_val) 3684 #define reg_rdexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1705,__ERR) 3685 #define reg_wrexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1705,wr_val) 3686 #define reg_rdexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_BW() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1706,__ERR) 3687 #define reg_wrexc_PCIE_BLK7_EXT_RX_CLK_REPEATER_BW(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1706,wr_val) 3688 #define reg_rdexc_PCIE_BLK7_EXT_SPARE_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1707,__ERR) 3689 #define reg_wrexc_PCIE_BLK7_EXT_SPARE_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1707,wr_val) 3690 #define reg_rdexc_PCIE_BLK7_EXT_SPARE_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1708,__ERR) 3691 #define reg_wrexc_PCIE_BLK7_EXT_SPARE_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1708,wr_val) 3692 #define reg_rdexc_PCIE_BLK7_EXT_SPARE_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x1709,__ERR) 3693 #define reg_wrexc_PCIE_BLK7_EXT_SPARE_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x1709,wr_val) 3694 #define reg_rdexc_PCIE_BLK7_EXT_SPARE_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x170a,__ERR) 3695 #define reg_wrexc_PCIE_BLK7_EXT_SPARE_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x170a,wr_val) 3696 #define reg_rdc_PLL_CAL_COM_CTL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd120,__ERR) 3697 #define reg_wrc_PLL_CAL_COM_CTL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd120,wr_val) 3698 #define reg_rdc_PLL_CAL_COM_CTL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd121,__ERR) 3699 #define reg_wrc_PLL_CAL_COM_CTL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd121,wr_val) 3700 #define reg_rdc_PLL_CAL_COM_CTL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd122,__ERR) 3701 #define reg_wrc_PLL_CAL_COM_CTL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd122,wr_val) 3702 #define reg_rdc_PLL_CAL_COM_CTL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd123,__ERR) 3703 #define reg_wrc_PLL_CAL_COM_CTL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd123,wr_val) 3704 #define reg_rdc_PLL_CAL_COM_CTL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd124,__ERR) 3705 #define reg_wrc_PLL_CAL_COM_CTL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd124,wr_val) 3706 #define reg_rdc_PLL_CAL_COM_CTL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd125,__ERR) 3707 #define reg_wrc_PLL_CAL_COM_CTL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd125,wr_val) 3708 #define reg_rdc_PLL_CAL_COM_CTL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd126,__ERR) 3709 #define reg_wrc_PLL_CAL_COM_CTL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd126,wr_val) 3710 #define reg_rdc_PLL_CAL_COM_STS_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd128,__ERR) 3711 #define reg_wrc_PLL_CAL_COM_STS_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd128,wr_val) 3712 #define reg_rdc_PLL_CAL_COM_STS_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd129,__ERR) 3713 #define reg_wrc_PLL_CAL_COM_STS_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd129,wr_val) 3714 #define reg_rdc_PLL_CAL_COM_STS_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12a,__ERR) 3715 #define reg_wrc_PLL_CAL_COM_STS_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd12a,wr_val) 3716 #define reg_rdc_PLL_CAL_COM_STS_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12b,__ERR) 3717 #define reg_wrc_PLL_CAL_COM_STS_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd12b,wr_val) 3718 #define reg_rdc_PLL_CAL_COM_STS_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12c,__ERR) 3719 #define reg_wrc_PLL_CAL_COM_STS_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd12c,wr_val) 3720 #define reg_rdc_PLL_CAL_COM_STS_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12d,__ERR) 3721 #define reg_wrc_PLL_CAL_COM_STS_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd12d,wr_val) 3722 #define reg_rdc_PLL_CAL_COM_STS_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd12e,__ERR) 3723 #define reg_wrc_PLL_CAL_COM_STS_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd12e,wr_val) 3724 #define reg_rdexc_REGISTER_INFO_EXT_INFO() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x0000,__ERR) 3725 #define reg_wrexc_REGISTER_INFO_EXT_INFO(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x0000,wr_val) 3726 #define reg_rd_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd161,__ERR) 3727 #define reg_wr_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd161,wr_val) 3728 #define reg_rd_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd167,__ERR) 3729 #define reg_wr_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd167,wr_val) 3730 #define reg_rd_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd164,__ERR) 3731 #define reg_wr_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd164,wr_val) 3732 #define reg_rd_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd162,__ERR) 3733 #define reg_wr_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd162,wr_val) 3734 #define reg_rd_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd163,__ERR) 3735 #define reg_wr_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd163,wr_val) 3736 #define reg_rd_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd168,__ERR) 3737 #define reg_wr_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd168,wr_val) 3738 #define reg_rd_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd16c,__ERR) 3739 #define reg_wr_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd16c,wr_val) 3740 #define reg_rdex_RX_DFE0_EXT_RXSTATUS1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7000,__ERR) 3741 #define reg_wrex_RX_DFE0_EXT_RXSTATUS1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7000,wr_val) 3742 #define reg_rdex_RX_DFE0_EXT_RXSTATUS2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7001,__ERR) 3743 #define reg_wrex_RX_DFE0_EXT_RXSTATUS2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7001,wr_val) 3744 #define reg_rdex_RX_DFE0_EXT_RXSTATUS3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7002,__ERR) 3745 #define reg_wrex_RX_DFE0_EXT_RXSTATUS3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7002,wr_val) 3746 #define reg_rdex_RX_DFE0_EXT_RXCONTROL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7003,__ERR) 3747 #define reg_wrex_RX_DFE0_EXT_RXCONTROL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7003,wr_val) 3748 #define reg_rdex_RX_DFE0_EXT_RXCONTROL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7004,__ERR) 3749 #define reg_wrex_RX_DFE0_EXT_RXCONTROL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7004,wr_val) 3750 #define reg_rdex_RX_DFE0_EXT_RXCONTROL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7005,__ERR) 3751 #define reg_wrex_RX_DFE0_EXT_RXCONTROL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7005,wr_val) 3752 #define reg_rdex_RX_DFE0_EXT_RXCONTROL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7006,__ERR) 3753 #define reg_wrex_RX_DFE0_EXT_RXCONTROL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7006,wr_val) 3754 #define reg_rdex_RX_DFE0_EXT_RXCONTROL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7007,__ERR) 3755 #define reg_wrex_RX_DFE0_EXT_RXCONTROL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7007,wr_val) 3756 #define reg_rdex_RX_DFE0_EXT_RXCONTROL6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7008,__ERR) 3757 #define reg_wrex_RX_DFE0_EXT_RXCONTROL6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7008,wr_val) 3758 #define reg_rdex_RX_DFE2_EXT_CONTROL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7200,__ERR) 3759 #define reg_wrex_RX_DFE2_EXT_CONTROL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7200,wr_val) 3760 #define reg_rdex_RX_DFE2_EXT_STATUS1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7201,__ERR) 3761 #define reg_wrex_RX_DFE2_EXT_STATUS1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7201,wr_val) 3762 #define reg_rdex_RX_DFE2_EXT_STATUS2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x7202,__ERR) 3763 #define reg_wrex_RX_DFE2_EXT_STATUS2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x7202,wr_val) 3764 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd180,__ERR) 3765 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd180,wr_val) 3766 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd181,__ERR) 3767 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd181,wr_val) 3768 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd18e,__ERR) 3769 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd18e,wr_val) 3770 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd183,__ERR) 3771 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd183,wr_val) 3772 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd185,__ERR) 3773 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd185,wr_val) 3774 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd189,__ERR) 3775 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd189,wr_val) 3776 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd186,__ERR) 3777 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd186,wr_val) 3778 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd18a,__ERR) 3779 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd18a,wr_val) 3780 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd18b,__ERR) 3781 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd18b,wr_val) 3782 #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd18c,__ERR) 3783 #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd18c,wr_val) 3784 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd080,__ERR) 3785 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd080,wr_val) 3786 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd081,__ERR) 3787 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd081,wr_val) 3788 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd08e,__ERR) 3789 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd08e,wr_val) 3790 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd083,__ERR) 3791 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd083,wr_val) 3792 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd085,__ERR) 3793 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd085,wr_val) 3794 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd089,__ERR) 3795 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd089,wr_val) 3796 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd086,__ERR) 3797 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd086,wr_val) 3798 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd08a,__ERR) 3799 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd08a,wr_val) 3800 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd08b,__ERR) 3801 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd08b,wr_val) 3802 #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd08c,__ERR) 3803 #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd08c,wr_val) 3804 #define reg_rd_SIGDET_CTRL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c3,__ERR) 3805 #define reg_wr_SIGDET_CTRL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c3,wr_val) 3806 #define reg_rd_SIGDET_CTRL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c4,__ERR) 3807 #define reg_wr_SIGDET_CTRL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c4,wr_val) 3808 #define reg_rd_SIGDET_CTRL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c5,__ERR) 3809 #define reg_wr_SIGDET_CTRL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c5,wr_val) 3810 #define reg_rd_SIGDET_CTRL_6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c6,__ERR) 3811 #define reg_wr_SIGDET_CTRL_6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c6,wr_val) 3812 #define reg_rd_SIGDET_CTRL_7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c7,__ERR) 3813 #define reg_wr_SIGDET_CTRL_7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c7,wr_val) 3814 #define reg_rd_SIGDET_CTRL_8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c8,__ERR) 3815 #define reg_wr_SIGDET_CTRL_8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c8,wr_val) 3816 #define reg_rd_SIGDET_CTRL_9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0c9,__ERR) 3817 #define reg_wr_SIGDET_CTRL_9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0c9,wr_val) 3818 #define reg_rd_SIGDET_CTRL_10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0cd,__ERR) 3819 #define reg_wr_SIGDET_CTRL_10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0cd,wr_val) 3820 #define reg_rd_SIGDET_SIGDET_STAT_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0ca,__ERR) 3821 #define reg_wr_SIGDET_SIGDET_STAT_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0ca,wr_val) 3822 #define reg_rd_SIGDET_SIGDET_STAT_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0cb,__ERR) 3823 #define reg_wr_SIGDET_SIGDET_STAT_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0cb,wr_val) 3824 #define reg_rd_TLB_RX_PRBS_CHK_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d1,__ERR) 3825 #define reg_wr_TLB_RX_PRBS_CHK_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d1,wr_val) 3826 #define reg_rd_TLB_RX_PRBS_CHK_CNT_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d0,__ERR) 3827 #define reg_wr_TLB_RX_PRBS_CHK_CNT_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d0,wr_val) 3828 #define reg_rd_TLB_RX_DIG_LPBK_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d2,__ERR) 3829 #define reg_wr_TLB_RX_DIG_LPBK_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d2,wr_val) 3830 #define reg_rd_TLB_RX_TLB_RX_MISC_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d3,__ERR) 3831 #define reg_wr_TLB_RX_TLB_RX_MISC_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d3,wr_val) 3832 #define reg_rd_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d4,__ERR) 3833 #define reg_wr_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d4,wr_val) 3834 #define reg_rd_TLB_RX_DIG_LPBK_PD_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d8,__ERR) 3835 #define reg_wr_TLB_RX_DIG_LPBK_PD_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d8,wr_val) 3836 #define reg_rd_TLB_RX_PRBS_CHK_LOCK_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d9,__ERR) 3837 #define reg_wr_TLB_RX_PRBS_CHK_LOCK_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d9,wr_val) 3838 #define reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0da,__ERR) 3839 #define reg_wr_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0da,wr_val) 3840 #define reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0db,__ERR) 3841 #define reg_wr_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0db,wr_val) 3842 #define reg_rd_TLB_RX_PMD_RX_LOCK_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0dc,__ERR) 3843 #define reg_wr_TLB_RX_PMD_RX_LOCK_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0dc,wr_val) 3844 #define reg_rd_TLB_RX_DBG_PMD_RX_LOCK_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d6,__ERR) 3845 #define reg_wr_TLB_RX_DBG_PMD_RX_LOCK_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d6,wr_val) 3846 #define reg_rd_TLB_RX_UC_PMD_RX_LOCK_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d7,__ERR) 3847 #define reg_wr_TLB_RX_UC_PMD_RX_LOCK_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d7,wr_val) 3848 #define reg_rd_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0d5,__ERR) 3849 #define reg_wr_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0d5,wr_val) 3850 #define reg_rd_TLB_TX_PATT_GEN_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0e0,__ERR) 3851 #define reg_wr_TLB_TX_PATT_GEN_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0e0,wr_val) 3852 #define reg_rd_TLB_TX_PRBS_GEN_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0e1,__ERR) 3853 #define reg_wr_TLB_TX_PRBS_GEN_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0e1,wr_val) 3854 #define reg_rd_TLB_TX_RMT_LPBK_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0e2,__ERR) 3855 #define reg_wr_TLB_TX_RMT_LPBK_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0e2,wr_val) 3856 #define reg_rd_TLB_TX_TLB_TX_MISC_CONFIG() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0e3,__ERR) 3857 #define reg_wr_TLB_TX_TLB_TX_MISC_CONFIG(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0e3,wr_val) 3858 #define reg_rd_TLB_TX_RMT_LPBK_PD_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd0e8,__ERR) 3859 #define reg_wr_TLB_TX_RMT_LPBK_PD_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd0e8,wr_val) 3860 #define reg_rd_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd171,__ERR) 3861 #define reg_wr_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd171,wr_val) 3862 #define reg_rd_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd177,__ERR) 3863 #define reg_wr_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd177,wr_val) 3864 #define reg_rd_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd174,__ERR) 3865 #define reg_wr_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd174,wr_val) 3866 #define reg_rd_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd172,__ERR) 3867 #define reg_wr_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd172,wr_val) 3868 #define reg_rd_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd173,__ERR) 3869 #define reg_wr_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd173,wr_val) 3870 #define reg_rd_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd17c,__ERR) 3871 #define reg_wr_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd17c,wr_val) 3872 #define reg_rd_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd17d,__ERR) 3873 #define reg_wr_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd17d,wr_val) 3874 #define reg_rd_TX_COEFF_MAIN_MAIN_EXTENT_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd300,__ERR) 3875 #define reg_wr_TX_COEFF_MAIN_MAIN_EXTENT_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd300,wr_val) 3876 #define reg_rd_TX_COEFF_MAIN_MAIN_EXTENT_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd301,__ERR) 3877 #define reg_wr_TX_COEFF_MAIN_MAIN_EXTENT_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd301,wr_val) 3878 #define reg_rd_TX_COEFF_MAIN_MAIN_EXTENT_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd302,__ERR) 3879 #define reg_wr_TX_COEFF_MAIN_MAIN_EXTENT_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd302,wr_val) 3880 #define reg_rd_TX_COEFF_MAIN_MAIN_EXTENT_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd303,__ERR) 3881 #define reg_wr_TX_COEFF_MAIN_MAIN_EXTENT_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd303,wr_val) 3882 #define reg_rd_TX_COEFF_MAIN_MAIN_EXTENT_CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd304,__ERR) 3883 #define reg_wr_TX_COEFF_MAIN_MAIN_EXTENT_CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd304,wr_val) 3884 #define reg_rd_TX_COEFF_MAIN_MAIN_EXTENT_CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd305,__ERR) 3885 #define reg_wr_TX_COEFF_MAIN_MAIN_EXTENT_CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd305,wr_val) 3886 #define reg_rd_TX_COEFF_PM_PRE_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd310,__ERR) 3887 #define reg_wr_TX_COEFF_PM_PRE_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd310,wr_val) 3888 #define reg_rd_TX_COEFF_PM_PRE_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd311,__ERR) 3889 #define reg_wr_TX_COEFF_PM_PRE_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd311,wr_val) 3890 #define reg_rd_TX_COEFF_PM_PRE_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd312,__ERR) 3891 #define reg_wr_TX_COEFF_PM_PRE_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd312,wr_val) 3892 #define reg_rd_TX_COEFF_PM_PRE_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd313,__ERR) 3893 #define reg_wr_TX_COEFF_PM_PRE_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd313,wr_val) 3894 #define reg_rd_TX_COEFF_PM_PRE_CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd314,__ERR) 3895 #define reg_wr_TX_COEFF_PM_PRE_CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd314,wr_val) 3896 #define reg_rd_TX_COEFF_PM_PRE_CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd315,__ERR) 3897 #define reg_wr_TX_COEFF_PM_PRE_CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd315,wr_val) 3898 #define reg_rd_TX_COEFF_PM_REGMAIN_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd316,__ERR) 3899 #define reg_wr_TX_COEFF_PM_REGMAIN_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd316,wr_val) 3900 #define reg_rd_TX_COEFF_PM_REGOVRD_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd317,__ERR) 3901 #define reg_wr_TX_COEFF_PM_REGOVRD_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd317,wr_val) 3902 #define reg_rd_TX_COEFF_POST_POST_EXTENT_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd320,__ERR) 3903 #define reg_wr_TX_COEFF_POST_POST_EXTENT_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd320,wr_val) 3904 #define reg_rd_TX_COEFF_POST_POST_EXTENT_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd321,__ERR) 3905 #define reg_wr_TX_COEFF_POST_POST_EXTENT_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd321,wr_val) 3906 #define reg_rd_TX_COEFF_POST_POST_EXTENT_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd322,__ERR) 3907 #define reg_wr_TX_COEFF_POST_POST_EXTENT_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd322,wr_val) 3908 #define reg_rd_TX_COEFF_POST_POST_EXTENT_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd323,__ERR) 3909 #define reg_wr_TX_COEFF_POST_POST_EXTENT_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd323,wr_val) 3910 #define reg_rd_TX_COEFF_POST_POST_EXTENT_CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd324,__ERR) 3911 #define reg_wr_TX_COEFF_POST_POST_EXTENT_CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd324,wr_val) 3912 #define reg_rd_TX_COEFF_POST_POST_EXTENT_CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd325,__ERR) 3913 #define reg_wr_TX_COEFF_POST_POST_EXTENT_CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd325,wr_val) 3914 #define reg_rd_TX_COEFF_POSTA_POST_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd330,__ERR) 3915 #define reg_wr_TX_COEFF_POSTA_POST_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd330,wr_val) 3916 #define reg_rd_TX_COEFF_POSTA_POST_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd331,__ERR) 3917 #define reg_wr_TX_COEFF_POSTA_POST_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd331,wr_val) 3918 #define reg_rd_TX_COEFF_POSTA_POST_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd332,__ERR) 3919 #define reg_wr_TX_COEFF_POSTA_POST_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd332,wr_val) 3920 #define reg_rd_TX_COEFF_POSTA_POST_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd333,__ERR) 3921 #define reg_wr_TX_COEFF_POSTA_POST_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd333,wr_val) 3922 #define reg_rd_TX_COEFF_POSTA_POST_CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd334,__ERR) 3923 #define reg_wr_TX_COEFF_POSTA_POST_CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd334,wr_val) 3924 #define reg_rd_TX_COEFF_POSTA_POST_CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd335,__ERR) 3925 #define reg_wr_TX_COEFF_POSTA_POST_CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd335,wr_val) 3926 #define reg_rd_TX_COEFF_POSTA_POST_CTRL6() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd336,__ERR) 3927 #define reg_wr_TX_COEFF_POSTA_POST_CTRL6(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd336,wr_val) 3928 #define reg_rd_TX_COEFF_POSTA_POST_CTRL7() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd337,__ERR) 3929 #define reg_wr_TX_COEFF_POSTA_POST_CTRL7(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd337,wr_val) 3930 #define reg_rd_TX_COEFF_POSTA_POST_CTRL8() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd338,__ERR) 3931 #define reg_wr_TX_COEFF_POSTA_POST_CTRL8(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd338,wr_val) 3932 #define reg_rd_TX_COEFF_POSTA_POST_CTRL9() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd339,__ERR) 3933 #define reg_wr_TX_COEFF_POSTA_POST_CTRL9(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd339,wr_val) 3934 #define reg_rd_TX_COEFF_POSTA_POST_CTRL10() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd33a,__ERR) 3935 #define reg_wr_TX_COEFF_POSTA_POST_CTRL10(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd33a,wr_val) 3936 #define reg_rd_TX_COEFF_POSTA_POST_CTRL11() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd33b,__ERR) 3937 #define reg_wr_TX_COEFF_POSTA_POST_CTRL11(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd33b,wr_val) 3938 #define reg_rd_TX_COEFF_POSTA_POST_CTRL12() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd33c,__ERR) 3939 #define reg_wr_TX_COEFF_POSTA_POST_CTRL12(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd33c,wr_val) 3940 #define reg_rd_TX_COEFF_POSTA_POST_CTRL13() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd33d,__ERR) 3941 #define reg_wr_TX_COEFF_POSTA_POST_CTRL13(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd33d,wr_val) 3942 #define reg_rd_TX_COEFF_POSTA_POST_CTRL14() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd33e,__ERR) 3943 #define reg_wr_TX_COEFF_POSTA_POST_CTRL14(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd33e,wr_val) 3944 #define reg_rd_TX_COEFF_POSTB_POST_CTRL15() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd340,__ERR) 3945 #define reg_wr_TX_COEFF_POSTB_POST_CTRL15(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd340,wr_val) 3946 #define reg_rd_TX_COEFF_POSTB_POST_CTRL16() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd341,__ERR) 3947 #define reg_wr_TX_COEFF_POSTB_POST_CTRL16(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd341,wr_val) 3948 #define reg_rd_TX_COEFF_POSTB_POST_CTRL17() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd342,__ERR) 3949 #define reg_wr_TX_COEFF_POSTB_POST_CTRL17(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd342,wr_val) 3950 #define reg_rd_TX_COEFF_POSTB_POST_CTRL18() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd343,__ERR) 3951 #define reg_wr_TX_COEFF_POSTB_POST_CTRL18(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd343,wr_val) 3952 #define reg_rd_TX_COEFF_POSTB_POST_CTRL19() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd344,__ERR) 3953 #define reg_wr_TX_COEFF_POSTB_POST_CTRL19(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd344,wr_val) 3954 #define reg_rd_TX_COEFF_POSTB_POST_CTRL20() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd345,__ERR) 3955 #define reg_wr_TX_COEFF_POSTB_POST_CTRL20(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd345,wr_val) 3956 #define reg_rd_TX_COEFF_POSTB_POST_CTRL21() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd346,__ERR) 3957 #define reg_wr_TX_COEFF_POSTB_POST_CTRL21(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd346,wr_val) 3958 #define reg_rd_TX_COEFF_POSTB_POST_CTRL22() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd347,__ERR) 3959 #define reg_wr_TX_COEFF_POSTB_POST_CTRL22(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd347,wr_val) 3960 #define reg_rd_TX_COEFF_POSTB_POST_CTRL23() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd348,__ERR) 3961 #define reg_wr_TX_COEFF_POSTB_POST_CTRL23(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd348,wr_val) 3962 #define reg_rd_TX_COEFF_POSTB_POST_CTRL24() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd349,__ERR) 3963 #define reg_wr_TX_COEFF_POSTB_POST_CTRL24(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd349,wr_val) 3964 #define reg_rd_TX_COEFF_POSTB_REG_PRE_POST_CTRL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd34a,__ERR) 3965 #define reg_wr_TX_COEFF_POSTB_REG_PRE_POST_CTRL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd34a,wr_val) 3966 #define reg_rd_TX_COEFF_PRE_PRE_EXTENT_CTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd350,__ERR) 3967 #define reg_wr_TX_COEFF_PRE_PRE_EXTENT_CTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd350,wr_val) 3968 #define reg_rd_TX_COEFF_PRE_PRE_EXTENT_CTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd351,__ERR) 3969 #define reg_wr_TX_COEFF_PRE_PRE_EXTENT_CTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd351,wr_val) 3970 #define reg_rd_TX_COEFF_PRE_PRE_EXTENT_CTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd352,__ERR) 3971 #define reg_wr_TX_COEFF_PRE_PRE_EXTENT_CTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd352,wr_val) 3972 #define reg_rd_TX_COEFF_PRE_PRE_EXTENT_CTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd353,__ERR) 3973 #define reg_wr_TX_COEFF_PRE_PRE_EXTENT_CTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd353,wr_val) 3974 #define reg_rd_TX_COEFF_PRE_PRE_EXTENT_CTRL4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd354,__ERR) 3975 #define reg_wr_TX_COEFF_PRE_PRE_EXTENT_CTRL4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd354,wr_val) 3976 #define reg_rd_TX_COEFF_PRE_PRE_EXTENT_CTRL5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd355,__ERR) 3977 #define reg_wr_TX_COEFF_PRE_PRE_EXTENT_CTRL5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd355,wr_val) 3978 #define reg_rdex_TX_DFE0_EXT_TXSTATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5000,__ERR) 3979 #define reg_wrex_TX_DFE0_EXT_TXSTATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5000,wr_val) 3980 #define reg_rdex_TX_DFE0_EXT_MDATA0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5002,__ERR) 3981 #define reg_wrex_TX_DFE0_EXT_MDATA0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5002,wr_val) 3982 #define reg_rdex_TX_DFE0_EXT_MDATA1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5003,__ERR) 3983 #define reg_wrex_TX_DFE0_EXT_MDATA1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5003,wr_val) 3984 #define reg_rdex_TX_DFE0_EXT_EQ_COEFFICIENT() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5005,__ERR) 3985 #define reg_wrex_TX_DFE0_EXT_EQ_COEFFICIENT(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5005,wr_val) 3986 #define reg_rdex_TX_DFE0_EXT_TXCONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5001,__ERR) 3987 #define reg_wrex_TX_DFE0_EXT_TXCONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5001,wr_val) 3988 #define reg_rdex_TX_DFE0_EXT_TXCONTROL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5006,__ERR) 3989 #define reg_wrex_TX_DFE0_EXT_TXCONTROL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5006,wr_val) 3990 #define reg_rdex_TX_DFE0_EXT_TXCTRL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5007,__ERR) 3991 #define reg_wrex_TX_DFE0_EXT_TXCTRL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5007,wr_val) 3992 #define reg_rdex_TX_DFE0_EXT_TXCTRL1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5008,__ERR) 3993 #define reg_wrex_TX_DFE0_EXT_TXCTRL1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5008,wr_val) 3994 #define reg_rdex_TX_DFE0_EXT_TXCTRL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x5009,__ERR) 3995 #define reg_wrex_TX_DFE0_EXT_TXCTRL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x5009,wr_val) 3996 #define reg_rdex_TX_DFE0_EXT_TXCTRL3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x500a,__ERR) 3997 #define reg_wrex_TX_DFE0_EXT_TXCTRL3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x500a,wr_val) 3998 #define reg_rdex_TX_DFE0_EXT_TXCONTROL2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x500b,__ERR) 3999 #define reg_wrex_TX_DFE0_EXT_TXCONTROL2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x500b,wr_val) 4000 #define reg_rdex_TX_DFE0_EXT_TXSTATUS2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0x500c,__ERR) 4001 #define reg_wrex_TX_DFE0_EXT_TXSTATUS2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0x500c,wr_val) 4002 #define reg_rd_TX_FED_TXFIR_TAP_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd110,__ERR) 4003 #define reg_wr_TX_FED_TXFIR_TAP_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd110,wr_val) 4004 #define reg_rd_TX_FED_MISC_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd111,__ERR) 4005 #define reg_wr_TX_FED_MISC_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd111,wr_val) 4006 #define reg_rd_TX_FED_MISC_STATUS0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd112,__ERR) 4007 #define reg_wr_TX_FED_MISC_STATUS0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd112,wr_val) 4008 #define reg_rd_TX_FED_MICRO_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd113,__ERR) 4009 #define reg_wr_TX_FED_MICRO_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd113,wr_val) 4010 #define reg_rd_TX_FED_POST2_AFE_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd11b,__ERR) 4011 #define reg_wr_TX_FED_POST2_AFE_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd11b,wr_val) 4012 #define reg_rd_TX_FED_POST1_AFE_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd11c,__ERR) 4013 #define reg_wr_TX_FED_POST1_AFE_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd11c,wr_val) 4014 #define reg_rd_TX_FED_POST1PRE_AFE_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd11d,__ERR) 4015 #define reg_wr_TX_FED_POST1PRE_AFE_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd11d,wr_val) 4016 #define reg_rd_TX_FED_DC_LEVEL_AFE_CONTROL0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd11e,__ERR) 4017 #define reg_wr_TX_FED_DC_LEVEL_AFE_CONTROL0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd11e,wr_val) 4018 #define reg_rd_TX_PI_CONTROL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd070,__ERR) 4019 #define reg_wr_TX_PI_CONTROL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd070,wr_val) 4020 #define reg_rd_TX_PI_CONTROL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd071,__ERR) 4021 #define reg_wr_TX_PI_CONTROL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd071,wr_val) 4022 #define reg_rd_TX_PI_CONTROL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd072,__ERR) 4023 #define reg_wr_TX_PI_CONTROL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd072,wr_val) 4024 #define reg_rd_TX_PI_CONTROL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd073,__ERR) 4025 #define reg_wr_TX_PI_CONTROL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd073,wr_val) 4026 #define reg_rd_TX_PI_CONTROL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd074,__ERR) 4027 #define reg_wr_TX_PI_CONTROL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd074,wr_val) 4028 #define reg_rd_TX_PI_CONTROL_5() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd075,__ERR) 4029 #define reg_wr_TX_PI_CONTROL_5(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd075,wr_val) 4030 #define reg_rd_TX_PI_STATUS_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd078,__ERR) 4031 #define reg_wr_TX_PI_STATUS_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd078,wr_val) 4032 #define reg_rd_TX_PI_STATUS_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd079,__ERR) 4033 #define reg_wr_TX_PI_STATUS_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd079,wr_val) 4034 #define reg_rd_TX_PI_STATUS_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd07a,__ERR) 4035 #define reg_wr_TX_PI_STATUS_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd07a,wr_val) 4036 #define reg_rd_TX_PI_STATUS_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd07b,__ERR) 4037 #define reg_wr_TX_PI_STATUS_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd07b,wr_val) 4038 #define reg_rd_TX_PI_STATUS_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd07c,__ERR) 4039 #define reg_wr_TX_PI_STATUS_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd07c,wr_val) 4040 #define reg_rd_TX_PI_TX_FIFO_OVFB_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd07d,__ERR) 4041 #define reg_wr_TX_PI_TX_FIFO_OVFB_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd07d,wr_val) 4042 #define reg_rd_TX_TCA_TX_TCA_CONTROL_0() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a0,__ERR) 4043 #define reg_wr_TX_TCA_TX_TCA_CONTROL_0(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a0,wr_val) 4044 #define reg_rd_TX_TCA_TX_TCA_CONTROL_1() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a1,__ERR) 4045 #define reg_wr_TX_TCA_TX_TCA_CONTROL_1(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a1,wr_val) 4046 #define reg_rd_TX_TCA_TX_TCA_CONTROL_2() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a2,__ERR) 4047 #define reg_wr_TX_TCA_TX_TCA_CONTROL_2(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a2,wr_val) 4048 #define reg_rd_TX_TCA_TX_TCA_CONTROL_3() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a3,__ERR) 4049 #define reg_wr_TX_TCA_TX_TCA_CONTROL_3(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a3,wr_val) 4050 #define reg_rd_TX_TCA_TX_TCA_CONTROL_4() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a4,__ERR) 4051 #define reg_wr_TX_TCA_TX_TCA_CONTROL_4(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a4,wr_val) 4052 #define reg_rd_TX_TCA_TX_PI_OFFSET_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a5,__ERR) 4053 #define reg_wr_TX_TCA_TX_PI_OFFSET_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a5,wr_val) 4054 #define reg_rd_TX_TCA_TX_TCA_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd1a6,__ERR) 4055 #define reg_wr_TX_TCA_TX_TCA_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd1a6,wr_val) 4056 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd190,__ERR) 4057 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd190,wr_val) 4058 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd191,__ERR) 4059 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd191,wr_val) 4060 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd19e,__ERR) 4061 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd19e,wr_val) 4062 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd193,__ERR) 4063 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd193,wr_val) 4064 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd195,__ERR) 4065 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd195,wr_val) 4066 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd199,__ERR) 4067 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd199,wr_val) 4068 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd196,__ERR) 4069 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd196,wr_val) 4070 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd19a,__ERR) 4071 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd19a,wr_val) 4072 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd19b,__ERR) 4073 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd19b,wr_val) 4074 #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd19c,__ERR) 4075 #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd19c,wr_val) 4076 #define reg_rdc_TX_COM_TXCOM_CONTROL0_REGISTER() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd130,__ERR) 4077 #define reg_wrc_TX_COM_TXCOM_CONTROL0_REGISTER(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd130,wr_val) 4078 #define reg_rdc_TX_COM_TXCOM_CONTROL1_REGISTER() _merlin16_pcieg3_pmd_rde_reg(sa__, 0xd131,__ERR) 4079 #define reg_wrc_TX_COM_TXCOM_CONTROL1_REGISTER(wr_val) merlin16_pcieg3_pmd_wr_reg(sa__, 0xd131,wr_val) 4080 4081 #define ex_AMS_RX_RX_CTRL_0__ams_rx_term_lowzvdd(reg_value) extract_field((reg_value),15,15) 4082 #define ex_AMS_RX_RX_CTRL_0__ams_rx_term_lowzgnd(reg_value) extract_field((reg_value),14,14) 4083 #define ex_AMS_RX_RX_CTRL_0__ams_rx_term_cmult_ena(reg_value) extract_field((reg_value),13,13) 4084 #define ex_AMS_RX_RX_CTRL_0__ams_rx_term_cm_ena(reg_value) extract_field((reg_value),12,12) 4085 #define ex_AMS_RX_RX_CTRL_0__ams_rx_en_rxck_test(reg_value) extract_field((reg_value),11,10) 4086 #define ex_AMS_RX_RX_CTRL_0__ams_rx_en_rxck_testport(reg_value) extract_field((reg_value),9,9) 4087 #define ex_AMS_RX_RX_CTRL_0__ams_rx_spare_0_2(reg_value) extract_field((reg_value),8,5) 4088 #define ex_AMS_RX_RX_CTRL_0__ams_rx_rcm_sum(reg_value) extract_field((reg_value),4,4) 4089 #define ex_AMS_RX_RX_CTRL_0__ams_rx_sigdet_bypass(reg_value) extract_field((reg_value),3,3) 4090 #define ex_AMS_RX_RX_CTRL_0__ams_rx_sigdet_pwrdn(reg_value) extract_field((reg_value),2,2) 4091 #define ex_AMS_RX_RX_CTRL_0__ams_rx_cm_sel(reg_value) extract_field((reg_value),1,1) 4092 #define ex_AMS_RX_RX_CTRL_0__ams_rx_sum_pseudo_diff(reg_value) extract_field((reg_value),0,0) 4093 #define ex_AMS_RX_RX_CTRL_1__ams_rx_curr_dfe_2(reg_value) extract_field((reg_value),13,11) 4094 #define ex_AMS_RX_RX_CTRL_1__ams_rx_spare_1_0(reg_value) extract_field((reg_value),10,8) 4095 #define ex_AMS_RX_RX_CTRL_1__ams_rx_curr_pi(reg_value) extract_field((reg_value),7,5) 4096 #define ex_AMS_RX_RX_CTRL_1__ams_rx_curr_ctle(reg_value) extract_field((reg_value),4,2) 4097 #define ex_AMS_RX_RX_CTRL_1__ams_rx_vga_en_hgain(reg_value) extract_field((reg_value),1,1) 4098 #define ex_AMS_RX_RX_CTRL_1__ams_rx_vga_out_idle(reg_value) extract_field((reg_value),0,0) 4099 #define ex_AMS_RX_RX_CTRL_2__ams_rx_spare_2_0(reg_value) extract_field((reg_value),15,14) 4100 #define ex_AMS_RX_RX_CTRL_2__ams_rx_en_dfe_tap_fb(reg_value) extract_field((reg_value),13,9) 4101 #define ex_AMS_RX_RX_CTRL_2__ams_rx_curr_vga(reg_value) extract_field((reg_value),8,6) 4102 #define ex_AMS_RX_RX_CTRL_2__ams_rx_curr_dfe_summer(reg_value) extract_field((reg_value),5,3) 4103 #define ex_AMS_RX_RX_CTRL_2__ams_rx_curr_dfe_1(reg_value) extract_field((reg_value),2,0) 4104 #define ex_AMS_RX_RX_CTRL_3__ams_rx_ll_en(reg_value) extract_field((reg_value),14,14) 4105 #define ex_AMS_RX_RX_CTRL_3__ams_rx_seli1p25dfe(reg_value) extract_field((reg_value),13,13) 4106 #define ex_AMS_RX_RX_CTRL_3__ams_rx_i4deadzone(reg_value) extract_field((reg_value),12,12) 4107 #define ex_AMS_RX_RX_CTRL_3__ams_rx_curr_sigdet(reg_value) extract_field((reg_value),11,9) 4108 #define ex_AMS_RX_RX_CTRL_3__ams_rx_curr_vddr_afe(reg_value) extract_field((reg_value),8,6) 4109 #define ex_AMS_RX_RX_CTRL_3__ams_rx_os2x_mode_even_odd(reg_value) extract_field((reg_value),5,5) 4110 #define ex_AMS_RX_RX_CTRL_3__ams_rx_dfe_os2x_mode(reg_value) extract_field((reg_value),4,4) 4111 #define ex_AMS_RX_RX_CTRL_3__ams_rx_en_20b_demux(reg_value) extract_field((reg_value),3,3) 4112 #define ex_AMS_RX_RX_CTRL_3__ams_rx_en_clk16(reg_value) extract_field((reg_value),2,2) 4113 #define ex_AMS_RX_RX_CTRL_3__ams_rx_en_clk33(reg_value) extract_field((reg_value),1,1) 4114 #define ex_AMS_RX_RX_CTRL_3__ams_rx_en_vcctrl(reg_value) extract_field((reg_value),0,0) 4115 #define ex_AMS_RX_RX_CTRL_4__ams_rx_vga_pon(reg_value) extract_field((reg_value),15,12) 4116 #define ex_AMS_RX_RX_CTRL_4__ams_rx_oc_2x(reg_value) extract_field((reg_value),11,11) 4117 #define ex_AMS_RX_RX_CTRL_4__ams_rx_spare_4_0(reg_value) extract_field((reg_value),10,8) 4118 #define ex_AMS_RX_RX_CTRL_4__ams_rx_en_recclkdiv(reg_value) extract_field((reg_value),7,7) 4119 #define ex_AMS_RX_RX_CTRL_4__ams_rx_div3o4o5(reg_value) extract_field((reg_value),6,5) 4120 #define ex_AMS_RX_RX_CTRL_4__ams_rx_recclkdiv(reg_value) extract_field((reg_value),4,0) 4121 #define ex_AMS_RX_RX_CTRL_5__ams_rx_dcc2_phase_flip(reg_value) extract_field((reg_value),15,15) 4122 #define ex_AMS_RX_RX_CTRL_5__ams_rx_slcr_calib_range_sel(reg_value) extract_field((reg_value),14,14) 4123 #define ex_AMS_RX_RX_CTRL_5__ams_rx_pi_pd(reg_value) extract_field((reg_value),13,13) 4124 #define ex_AMS_RX_RX_CTRL_5__ams_rx_dcc1_phase_flip(reg_value) extract_field((reg_value),12,12) 4125 #define ex_AMS_RX_RX_CTRL_5__ams_rx_en_dfeclk(reg_value) extract_field((reg_value),11,11) 4126 #define ex_AMS_RX_RX_CTRL_5__ams_rx_ctle_gain_ctrl(reg_value) extract_field((reg_value),10,7) 4127 #define ex_AMS_RX_RX_CTRL_5__ams_rx_curr_in_offset(reg_value) extract_field((reg_value),6,4) 4128 #define ex_AMS_RX_RX_CTRL_5__ams_rx_pon(reg_value) extract_field((reg_value),3,0) 4129 #define ex_AMS_RX_RX_CTRL_6__ams_rx_sigdet_offset_correction_pos(reg_value) extract_field((reg_value),12,8) 4130 #define ex_AMS_RX_RX_CTRL_6__ams_rx_sigdet_calibration_select(reg_value) extract_field((reg_value),7,7) 4131 #define ex_AMS_RX_RX_CTRL_6__ams_rx_sum_gain_ctrl(reg_value) extract_field((reg_value),6,3) 4132 #define ex_AMS_RX_RX_CTRL_6__ams_rx_en_sigdet_calib(reg_value) extract_field((reg_value),2,2) 4133 #define ex_AMS_RX_RX_CTRL_6__ams_rx_hiz_1(reg_value) extract_field((reg_value),1,1) 4134 #define ex_AMS_RX_RX_CTRL_6__ams_rx_m1_sign(reg_value) extract_field((reg_value),0,0) 4135 #define ex_AMS_RX_RX_CTRL_7__ams_rx_spare_7_0(reg_value) extract_field((reg_value),13,10) 4136 #define ex_AMS_RX_RX_CTRL_7__ams_rx_sigdet_threshold(reg_value) extract_field((reg_value),9,5) 4137 #define ex_AMS_RX_RX_CTRL_7__ams_rx_sigdet_offset_correction_neg(reg_value) extract_field((reg_value),4,0) 4138 #define ex_AMS_RX_RX_INT__ams_rx_rxpon_sel(reg_value) extract_field((reg_value),1,1) 4139 #define ex_AMS_RX_RX_INT__ams_rx_vgapon_sel(reg_value) extract_field((reg_value),0,0) 4140 #define ex_AMS_RX_RX_STS__ams_rx_vgapon_mux(reg_value) extract_field((reg_value),7,4) 4141 #define ex_AMS_RX_RX_STS__ams_rx_rxpon_mux(reg_value) extract_field((reg_value),3,0) 4142 #define ex_AMS_TX_TX_CTRL_0__ams_tx_lowlatency_en(reg_value) extract_field((reg_value),15,15) 4143 #define ex_AMS_TX_TX_CTRL_0__ams_tx_fifo_resetb(reg_value) extract_field((reg_value),14,14) 4144 #define ex_AMS_TX_TX_CTRL_0__ams_tx_ll_fifo_ctrl(reg_value) extract_field((reg_value),13,11) 4145 #define ex_AMS_TX_TX_CTRL_0__ams_tx_ll_fifo_zero_out(reg_value) extract_field((reg_value),10,10) 4146 #define ex_AMS_TX_TX_CTRL_0__ams_tx_ll_polarity_flip(reg_value) extract_field((reg_value),9,9) 4147 #define ex_AMS_TX_TX_CTRL_0__ams_tx_ll_selpath_tx(reg_value) extract_field((reg_value),8,8) 4148 #define ex_AMS_TX_TX_CTRL_0__ams_tx_enable_os_2(reg_value) extract_field((reg_value),7,7) 4149 #define ex_AMS_TX_TX_CTRL_0__ams_tx_pon(reg_value) extract_field((reg_value),6,3) 4150 #define ex_AMS_TX_TX_CTRL_0__ams_tx_ticksel(reg_value) extract_field((reg_value),2,1) 4151 #define ex_AMS_TX_TX_CTRL_0__ams_tx_pwrdn(reg_value) extract_field((reg_value),0,0) 4152 #define ex_AMS_TX_TX_CTRL_1__ams_tx_en_slow(reg_value) extract_field((reg_value),14,11) 4153 #define ex_AMS_TX_TX_CTRL_1__ams_tx_en_wclk33(reg_value) extract_field((reg_value),10,10) 4154 #define ex_AMS_TX_TX_CTRL_1__ams_tx_en_wclk20(reg_value) extract_field((reg_value),9,9) 4155 #define ex_AMS_TX_TX_CTRL_1__ams_tx_en_wclk16(reg_value) extract_field((reg_value),8,8) 4156 #define ex_AMS_TX_TX_CTRL_1__ams_tx_testclk_ena(reg_value) extract_field((reg_value),7,7) 4157 #define ex_AMS_TX_TX_CTRL_1__ams_tx_testsel(reg_value) extract_field((reg_value),6,5) 4158 #define ex_AMS_TX_TX_CTRL_1__ams_tx_cntrl_rxdetect_en(reg_value) extract_field((reg_value),4,4) 4159 #define ex_AMS_TX_TX_CTRL_1__ams_tx_rxdtct_th_sel(reg_value) extract_field((reg_value),3,2) 4160 #define ex_AMS_TX_TX_CTRL_1__ams_tx_en_high_current(reg_value) extract_field((reg_value),1,1) 4161 #define ex_AMS_TX_TX_CTRL_1__ams_tx_enable_os_4(reg_value) extract_field((reg_value),0,0) 4162 #define ex_AMS_TX_TX_CTRL_2__ams_tx_fifo_phsdetect_mode(reg_value) extract_field((reg_value),14,14) 4163 #define ex_AMS_TX_TX_CTRL_2__ams_tx_ibias_pibuf_cntl(reg_value) extract_field((reg_value),13,11) 4164 #define ex_AMS_TX_TX_CTRL_2__ams_tx_ibias_pi_cntl(reg_value) extract_field((reg_value),10,8) 4165 #define ex_AMS_TX_TX_CTRL_2__ams_tx_ibias_opamp_cntl(reg_value) extract_field((reg_value),7,5) 4166 #define ex_AMS_TX_TX_CTRL_2__ams_tx_dcc_en(reg_value) extract_field((reg_value),4,4) 4167 #define ex_AMS_TX_TX_CTRL_2__ams_tx_en_hpf(reg_value) extract_field((reg_value),3,0) 4168 #define ex_AMS_TX_TX_CTRL_3__ams_tx_refcalm(reg_value) extract_field((reg_value),13,10) 4169 #define ex_AMS_TX_TX_CTRL_3__ams_tx_refcalp(reg_value) extract_field((reg_value),9,6) 4170 #define ex_AMS_TX_TX_CTRL_3__ams_tx_refcalshunt(reg_value) extract_field((reg_value),5,2) 4171 #define ex_AMS_TX_TX_CTRL_3__ams_tx_spare_3_0(reg_value) extract_field((reg_value),1,0) 4172 #define ex_AMS_TX_TX_CTRL_4__ams_tx_shntpost2_post2(reg_value) extract_field((reg_value),15,12) 4173 #define ex_AMS_TX_TX_CTRL_4__ams_tx_shntpost1_post1pre(reg_value) extract_field((reg_value),11,6) 4174 #define ex_AMS_TX_TX_CTRL_4__ams_tx_shntpre_post1pre(reg_value) extract_field((reg_value),5,0) 4175 #define ex_AMS_TX_TX_CTRL_5__ams_tx_post2to1(reg_value) extract_field((reg_value),13,13) 4176 #define ex_AMS_TX_TX_CTRL_5__ams_tx_en_pre(reg_value) extract_field((reg_value),12,12) 4177 #define ex_AMS_TX_TX_CTRL_5__ams_tx_en_post1(reg_value) extract_field((reg_value),11,11) 4178 #define ex_AMS_TX_TX_CTRL_5__ams_tx_en_post2(reg_value) extract_field((reg_value),10,10) 4179 #define ex_AMS_TX_TX_CTRL_5__ams_tx_shntmain_post2(reg_value) extract_field((reg_value),9,6) 4180 #define ex_AMS_TX_TX_CTRL_5__ams_tx_shntmain_post1pre(reg_value) extract_field((reg_value),5,0) 4181 #define ex_AMS_TX_TX_CTRL_6__ams_tx_shntpost1_post1(reg_value) extract_field((reg_value),15,11) 4182 #define ex_AMS_TX_TX_CTRL_6__ams_tx_dis_cal(reg_value) extract_field((reg_value),10,6) 4183 #define ex_AMS_TX_TX_CTRL_6__ams_tx_spare_6_0(reg_value) extract_field((reg_value),5,2) 4184 #define ex_AMS_TX_TX_CTRL_6__ams_tx_pd_phasedet(reg_value) extract_field((reg_value),1,1) 4185 #define ex_AMS_TX_TX_CTRL_6__ams_tx_en_shuntmode(reg_value) extract_field((reg_value),0,0) 4186 #define ex_AMS_TX_TX_CTRL_7__ams_tx_refcalpcs(reg_value) extract_field((reg_value),12,9) 4187 #define ex_AMS_TX_TX_CTRL_7__ams_tx_refcalmcs(reg_value) extract_field((reg_value),8,5) 4188 #define ex_AMS_TX_TX_CTRL_7__ams_tx_shntmain_post1(reg_value) extract_field((reg_value),4,0) 4189 #define ex_AMS_TX_TX_CTRL_8__ams_tx_spare_8_0(reg_value) extract_field((reg_value),8,1) 4190 #define ex_AMS_TX_TX_CTRL_8__ams_tx_shnten_main(reg_value) extract_field((reg_value),0,0) 4191 #define ex_AMS_TX_TX_INT__ams_tx_sel_txmaster(reg_value) extract_field((reg_value),3,3) 4192 #define ex_AMS_TX_TX_INT__ams_tx_auto_ll_selpath_tx_dis(reg_value) extract_field((reg_value),2,2) 4193 #define ex_AMS_TX_TX_INT__ams_tx_txpon_sel(reg_value) extract_field((reg_value),1,1) 4194 #define ex_AMS_TX_TX_STS__ams_tx_rescal(reg_value) extract_field((reg_value),7,4) 4195 #define ex_AMS_TX_TX_STS__ams_tx_txpon_mux(reg_value) extract_field((reg_value),3,0) 4196 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_cpar(reg_value) extract_field((reg_value),15,14) 4197 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_term_cm_en(reg_value) extract_field((reg_value),13,13) 4198 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_spare_0_1(reg_value) extract_field((reg_value),12,12) 4199 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_rpar(reg_value) extract_field((reg_value),11,9) 4200 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_lc_refclk_adj_1_0(reg_value) extract_field((reg_value),8,7) 4201 #define exc_AMS_COM_PLL_CTRL_0__ams_pll_spare_0_0(reg_value) extract_field((reg_value),6,0) 4202 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_en_hcur_vco(reg_value) extract_field((reg_value),15,15) 4203 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_enb_10t(reg_value) extract_field((reg_value),14,14) 4204 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_enb_8t(reg_value) extract_field((reg_value),13,13) 4205 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_vco_range(reg_value) extract_field((reg_value),12,6) 4206 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_en_8p5g_vco(reg_value) extract_field((reg_value),5,5) 4207 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_spare_1_0(reg_value) extract_field((reg_value),4,4) 4208 #define exc_AMS_COM_PLL_CTRL_1__ams_pll_curr_sel(reg_value) extract_field((reg_value),3,0) 4209 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_i4iqbuf(reg_value) extract_field((reg_value),15,14) 4210 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_vcobuf_pon(reg_value) extract_field((reg_value),13,10) 4211 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_clkvco_cal_invert(reg_value) extract_field((reg_value),9,9) 4212 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_cmos_refclk_ch_hiz(reg_value) extract_field((reg_value),8,8) 4213 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_calib_adj(reg_value) extract_field((reg_value),7,5) 4214 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_8p5g(reg_value) extract_field((reg_value),4,4) 4215 #define exc_AMS_COM_PLL_CTRL_2__ams_pll_vco_pon(reg_value) extract_field((reg_value),3,0) 4216 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_mmd_halfrate(reg_value) extract_field((reg_value),15,15) 4217 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_cp_bias(reg_value) extract_field((reg_value),14,12) 4218 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_spare_3_0(reg_value) extract_field((reg_value),11,11) 4219 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cmos_hz(reg_value) extract_field((reg_value),10,10) 4220 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cml_pd(reg_value) extract_field((reg_value),9,9) 4221 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_clksel(reg_value) extract_field((reg_value),8,8) 4222 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_rclk_refout(reg_value) extract_field((reg_value),7,7) 4223 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_cmos_refout_overwr(reg_value) extract_field((reg_value),6,6) 4224 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_cml_refout_overwr(reg_value) extract_field((reg_value),5,5) 4225 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_test_frac_clk(reg_value) extract_field((reg_value),4,4) 4226 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_enb_16t(reg_value) extract_field((reg_value),3,3) 4227 #define exc_AMS_COM_PLL_CTRL_3__ams_pll_band_iqbuf_ctr(reg_value) extract_field((reg_value),2,0) 4228 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_test_sel(reg_value) extract_field((reg_value),14,12) 4229 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_test_amp(reg_value) extract_field((reg_value),11,10) 4230 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_vco_test_clk_en(reg_value) extract_field((reg_value),9,9) 4231 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_bias_en(reg_value) extract_field((reg_value),8,8) 4232 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_spare4_2(reg_value) extract_field((reg_value),7,7) 4233 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_bias_vdd_sel(reg_value) extract_field((reg_value),6,5) 4234 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_spare4_1(reg_value) extract_field((reg_value),4,4) 4235 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_cp_opamp_bias(reg_value) extract_field((reg_value),3,2) 4236 #define exc_AMS_COM_PLL_CTRL_4__ams_pll_lc_refclk_adj_3_2(reg_value) extract_field((reg_value),1,0) 4237 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_refdiv_test_sel(reg_value) extract_field((reg_value),12,10) 4238 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_pwdb_extr_d2c(reg_value) extract_field((reg_value),9,9) 4239 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_en_refout_div(reg_value) extract_field((reg_value),8,8) 4240 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_pwrdn(reg_value) extract_field((reg_value),7,7) 4241 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_term_sel(reg_value) extract_field((reg_value),6,5) 4242 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_test_sel_overwrite(reg_value) extract_field((reg_value),4,4) 4243 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_test_vc(reg_value) extract_field((reg_value),3,3) 4244 #define exc_AMS_COM_PLL_CTRL_5__ams_pll_refout_div_sel(reg_value) extract_field((reg_value),2,0) 4245 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_ndiv_frac_l(reg_value) extract_field((reg_value),15,12) 4246 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_pfd_offset(reg_value) extract_field((reg_value),11,10) 4247 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_spare6_1(reg_value) extract_field((reg_value),9,9) 4248 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_pfd_offset_enlarge(reg_value) extract_field((reg_value),8,8) 4249 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_vco_i_boost(reg_value) extract_field((reg_value),7,6) 4250 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_vco_gm_boost(reg_value) extract_field((reg_value),5,4) 4251 #define exc_AMS_COM_PLL_CTRL_6__ams_pll_pon(reg_value) extract_field((reg_value),3,0) 4252 #define exc_AMS_COM_PLL_CTRL_7__ams_pll_i_ndiv_frac_h(reg_value) extract_field((reg_value),13,0) 4253 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_ndiv_dither_en(reg_value) extract_field((reg_value),15,15) 4254 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_pll_sdm_pwrdnb(reg_value) extract_field((reg_value),14,14) 4255 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_vcofb_div(reg_value) extract_field((reg_value),13,12) 4256 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_cml_refclk_bias(reg_value) extract_field((reg_value),11,10) 4257 #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_ndiv_int(reg_value) extract_field((reg_value),9,0) 4258 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_cml_refclk_adj(reg_value) extract_field((reg_value),15,14) 4259 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_bias_iq_ctrl(reg_value) extract_field((reg_value),13,11) 4260 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_bias_div_ctrl(reg_value) extract_field((reg_value),10,8) 4261 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_vco_supply_adj(reg_value) extract_field((reg_value),7,7) 4262 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_sel_fp3cap(reg_value) extract_field((reg_value),6,3) 4263 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_i_pll_frac_mode(reg_value) extract_field((reg_value),2,1) 4264 #define exc_AMS_COM_PLL_CTRL_9__ams_pll_mmd_resetb(reg_value) extract_field((reg_value),0,0) 4265 #define exc_AMS_COM_PLL_CTRL_10__ams_pll_tx_clkmaster_ovrd(reg_value) extract_field((reg_value),10,10) 4266 #define exc_AMS_COM_PLL_CTRL_10__ams_pll_tx_clkmaster_ctrl_a(reg_value) extract_field((reg_value),9,8) 4267 #define exc_AMS_COM_PLL_CTRL_10__ams_pll_tx_clkmaster_ctrl_b(reg_value) extract_field((reg_value),7,6) 4268 #define exc_AMS_COM_PLL_CTRL_10__ams_pll_refclk_in_bias(reg_value) extract_field((reg_value),5,0) 4269 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_term_frc(reg_value) extract_field((reg_value),3,3) 4270 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div_frc(reg_value) extract_field((reg_value),2,2) 4271 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div2_frc_val(reg_value) extract_field((reg_value),1,1) 4272 #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div4_frc_val(reg_value) extract_field((reg_value),0,0) 4273 #define exc_AMS_COM_PLL_STS__ams_pll_afe_rev_id(reg_value) extract_field((reg_value),3,0) 4274 #define exc_DIG_COM_B_LANE_ADDR_0__tx_lane_addr_0(reg_value) extract_field((reg_value),12,8) 4275 #define exc_DIG_COM_B_LANE_ADDR_0__rx_lane_addr_0(reg_value) extract_field((reg_value),4,0) 4276 #define exc_DIG_COM_B_LANE_ADDR_1__tx_lane_addr_1(reg_value) extract_field((reg_value),12,8) 4277 #define exc_DIG_COM_B_LANE_ADDR_1__rx_lane_addr_1(reg_value) extract_field((reg_value),4,0) 4278 #define exc_DIG_COM_B_LANE_ADDR_2__tx_lane_addr_2(reg_value) extract_field((reg_value),12,8) 4279 #define exc_DIG_COM_B_LANE_ADDR_2__rx_lane_addr_2(reg_value) extract_field((reg_value),4,0) 4280 #define exc_DIG_COM_B_LANE_ADDR_3__tx_lane_addr_3(reg_value) extract_field((reg_value),12,8) 4281 #define exc_DIG_COM_B_LANE_ADDR_3__rx_lane_addr_3(reg_value) extract_field((reg_value),4,0) 4282 #define exc_DIG_COM_REVID0__revid_rev_letter(reg_value) extract_field((reg_value),15,14) 4283 #define exc_DIG_COM_REVID0__revid_rev_number(reg_value) extract_field((reg_value),13,11) 4284 #define exc_DIG_COM_REVID0__revid_bonding(reg_value) extract_field((reg_value),10,9) 4285 #define exc_DIG_COM_REVID0__revid_process(reg_value) extract_field((reg_value),8,6) 4286 #define exc_DIG_COM_REVID0__revid_model(reg_value) extract_field((reg_value),5,0) 4287 #define exc_DIG_COM_REVID1__revid_multiplicity(reg_value) extract_field((reg_value),15,12) 4288 #define exc_DIG_COM_REVID1__revid_mdio(reg_value) extract_field((reg_value),5,5) 4289 #define exc_DIG_COM_REVID1__revid_micro(reg_value) extract_field((reg_value),4,4) 4290 #define exc_DIG_COM_REVID1__revid_cl72(reg_value) extract_field((reg_value),3,3) 4291 #define exc_DIG_COM_REVID1__revid_pir(reg_value) extract_field((reg_value),2,2) 4292 #define exc_DIG_COM_REVID1__revid_llp(reg_value) extract_field((reg_value),1,1) 4293 #define exc_DIG_COM_REVID1__revid_eee(reg_value) extract_field((reg_value),0,0) 4294 #define exc_DIG_COM_REVID2__revid2(reg_value) extract_field((reg_value),3,0) 4295 #define exc_DIG_COM_RESET_CONTROL_PMD__ana_txclk_reset_enable(reg_value) extract_field((reg_value),15,15) 4296 #define exc_DIG_COM_RESET_CONTROL_PMD__core_s_rstb(reg_value) extract_field((reg_value),0,0) 4297 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__disable_ack_timeout(reg_value) extract_field((reg_value),15,15) 4298 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_vcoclk16_vld_frc_val(reg_value) extract_field((reg_value),10,10) 4299 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_vcoclk16_vld_frc(reg_value) extract_field((reg_value),9,9) 4300 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__vcoclk16_s_comclk_frc_on(reg_value) extract_field((reg_value),8,8) 4301 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__vcoclk16_s_comclk_sel(reg_value) extract_field((reg_value),7,7) 4302 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_mdio_trans_pkill(reg_value) extract_field((reg_value),5,5) 4303 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc(reg_value) extract_field((reg_value),4,4) 4304 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc_val(reg_value) extract_field((reg_value),3,3) 4305 #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_core_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 4306 #define exc_DIG_COM_MASKDATA_REG__maskdata(reg_value) extract_field((reg_value),15,0) 4307 #define exc_DIG_COM_TOP_USER_CONTROL_0__uc_active(reg_value) extract_field((reg_value),15,15) 4308 #define exc_DIG_COM_TOP_USER_CONTROL_0__afe_s_pll_pwrdn(reg_value) extract_field((reg_value),14,14) 4309 #define exc_DIG_COM_TOP_USER_CONTROL_0__core_dp_s_rstb(reg_value) extract_field((reg_value),13,13) 4310 #define exc_DIG_COM_TOP_USER_CONTROL_0__maskdata_bus_assign(reg_value) extract_field((reg_value),11,10) 4311 #define exc_DIG_COM_TOP_USER_CONTROL_0__heartbeat_count_1us(reg_value) extract_field((reg_value),9,0) 4312 #define exc_DIG_COM_UC_ACK_CORE_CONTROL__uc_ack_core_dp_reset(reg_value) extract_field((reg_value),1,1) 4313 #define exc_DIG_COM_UC_ACK_CORE_CONTROL__uc_ack_core_cfg_done(reg_value) extract_field((reg_value),0,0) 4314 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released(reg_value) extract_field((reg_value),14,14) 4315 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released_index(reg_value) extract_field((reg_value),12,8) 4316 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released(reg_value) extract_field((reg_value),15,15) 4317 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released_index(reg_value) extract_field((reg_value),7,3) 4318 #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__core_dp_reset_state(reg_value) extract_field((reg_value),2,0) 4319 #define exc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL__core_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 4320 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__rst_seq_dis_flt_mode(reg_value) extract_field((reg_value),15,14) 4321 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__pwrdn_seq_timer(reg_value) extract_field((reg_value),11,9) 4322 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__dsc_pwrdn_seq_timer(reg_value) extract_field((reg_value),8,6) 4323 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__dsc_rst_seq_timer(reg_value) extract_field((reg_value),5,3) 4324 #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__rst_seq_timer(reg_value) extract_field((reg_value),2,0) 4325 #define exc_DIG_COM_PMD_CORE_MODE_STATUS__pmd_core_mode(reg_value) extract_field((reg_value),15,0) 4326 #define ex_DSC_A_CDR_STATUS_INTEG_REG__cdr_integ_reg(reg_value) extract_field_signed((reg_value),15,0) 4327 #define ex_DSC_A_CDR_STATUS_PHASE_ERROR__cdr_phase_err(reg_value) extract_field_signed((reg_value),5,0) 4328 #define ex_DSC_A_RX_PI_CNT_BIN_D__cnt_bin_p1_dreg(reg_value) extract_field((reg_value),14,8) 4329 #define ex_DSC_A_RX_PI_CNT_BIN_D__cnt_bin_d_dreg(reg_value) extract_field((reg_value),6,0) 4330 #define ex_DSC_A_RX_PI_CNT_BIN_P__cnt_bin_m1_preg(reg_value) extract_field((reg_value),14,8) 4331 #define ex_DSC_A_RX_PI_CNT_BIN_P__cnt_bin_p1_preg(reg_value) extract_field((reg_value),6,0) 4332 #define ex_DSC_A_RX_PI_CNT_BIN_M__cnt_bin_d_mreg(reg_value) extract_field((reg_value),14,8) 4333 #define ex_DSC_A_RX_PI_CNT_BIN_M__cnt_bin_m1_mreg(reg_value) extract_field((reg_value),6,0) 4334 #define ex_DSC_A_RX_PI_DIFF_BIN__cnt_d_minus_p1(reg_value) extract_field_signed((reg_value),15,8) 4335 #define ex_DSC_A_RX_PI_DIFF_BIN__cnt_d_minus_m1(reg_value) extract_field_signed((reg_value),7,0) 4336 #define ex_DSC_A_CDR_CONTROL_0__cdr_lm_thr_sel(reg_value) extract_field((reg_value),10,8) 4337 #define ex_DSC_A_CDR_CONTROL_0__cdr_freq_override_en(reg_value) extract_field((reg_value),7,7) 4338 #define ex_DSC_A_CDR_CONTROL_0__cdr_integ_sat_sel(reg_value) extract_field((reg_value),6,6) 4339 #define ex_DSC_A_CDR_CONTROL_0__cdr_phase_err_frz(reg_value) extract_field((reg_value),5,5) 4340 #define ex_DSC_A_CDR_CONTROL_0__cdr_integ_reg_clr(reg_value) extract_field((reg_value),4,4) 4341 #define ex_DSC_A_CDR_CONTROL_0__cdr_freq_en(reg_value) extract_field((reg_value),2,2) 4342 #define ex_DSC_A_CDR_CONTROL_0__br_pd_en(reg_value) extract_field((reg_value),1,1) 4343 #define ex_DSC_A_CDR_CONTROL_0__cdr_phase_sat_ctrl(reg_value) extract_field((reg_value),0,0) 4344 #define ex_DSC_A_CDR_CONTROL_1__cdr_freq_override_val(reg_value) extract_field_signed((reg_value),15,1) 4345 #define ex_DSC_A_CDR_CONTROL_1__dfe_vga_unfreeze(reg_value) extract_field((reg_value),0,0) 4346 #define ex_DSC_A_CDR_CONTROL_2__osx2p_pherr_gain(reg_value) extract_field((reg_value),9,8) 4347 #define ex_DSC_A_CDR_CONTROL_2__pattern_sel(reg_value) extract_field((reg_value),7,4) 4348 #define ex_DSC_A_CDR_CONTROL_2__phase_err_offset_mult_2(reg_value) extract_field((reg_value),1,1) 4349 #define ex_DSC_A_CDR_CONTROL_2__cdr_zero_polarity(reg_value) extract_field((reg_value),0,0) 4350 #define ex_DSC_A_TRNSUM_CNTL_5__edge_count_refless_en(reg_value) extract_field((reg_value),15,15) 4351 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_eye_closure_err_sel(reg_value) extract_field((reg_value),13,12) 4352 #define ex_DSC_A_TRNSUM_CNTL_5__swap_lms_data(reg_value) extract_field((reg_value),11,11) 4353 #define ex_DSC_A_TRNSUM_CNTL_5__swap_lms_m1(reg_value) extract_field((reg_value),10,10) 4354 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_prbs_sel(reg_value) extract_field((reg_value),6,5) 4355 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_eye_close_prev_en(reg_value) extract_field((reg_value),4,4) 4356 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_pattern_match_sel(reg_value) extract_field((reg_value),3,2) 4357 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_disable_sm_clear(reg_value) extract_field((reg_value),1,1) 4358 #define ex_DSC_A_TRNSUM_CNTL_5__trnsum_clr_sc(reg_value) extract_field((reg_value),0,0) 4359 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_reset(reg_value) extract_field((reg_value),15,15) 4360 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_slicers_en(reg_value) extract_field((reg_value),14,12) 4361 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_mode(reg_value) extract_field((reg_value),11,11) 4362 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_phase_step_dir(reg_value) extract_field((reg_value),10,10) 4363 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_strobe(reg_value) extract_field((reg_value),9,9) 4364 #define ex_DSC_A_RX_PI_CONTROL__rx_pi_phase_step_cnt(reg_value) extract_field((reg_value),6,0) 4365 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_supp_info(reg_value) extract_field((reg_value),15,8) 4366 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_ready_for_cmd(reg_value) extract_field((reg_value),7,7) 4367 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_error_found(reg_value) extract_field((reg_value),6,6) 4368 #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_gp_uc_req(reg_value) extract_field((reg_value),5,0) 4369 #define ex_DSC_A_DSC_SCRATCH__uc_dsc_data(reg_value) extract_field((reg_value),15,0) 4370 #define ex_DSC_B_DSC_SM_CTRL_0__uc_facq_ack(reg_value) extract_field((reg_value),0,0) 4371 #define ex_DSC_B_DSC_SM_CTRL_0__eee_mode_en(reg_value) extract_field((reg_value),1,1) 4372 #define ex_DSC_B_DSC_SM_CTRL_0__eee_quiet_rx_afe_pwrdwn_val(reg_value) extract_field((reg_value),2,2) 4373 #define ex_DSC_B_DSC_SM_CTRL_0__ignore_rx_mode(reg_value) extract_field((reg_value),3,3) 4374 #define ex_DSC_B_DSC_SM_CTRL_0__cl72_timer_en(reg_value) extract_field((reg_value),4,4) 4375 #define ex_DSC_B_DSC_SM_CTRL_0__uc_tune_en(reg_value) extract_field((reg_value),5,5) 4376 #define ex_DSC_B_DSC_SM_CTRL_0__hw_tune_en(reg_value) extract_field((reg_value),6,6) 4377 #define ex_DSC_B_DSC_SM_CTRL_0__uc_trnsum_en(reg_value) extract_field((reg_value),7,7) 4378 #define ex_DSC_B_DSC_SM_CTRL_0__eee_measure_en(reg_value) extract_field((reg_value),8,8) 4379 #define ex_DSC_B_DSC_SM_CTRL_0__slicer_cal_done_clear(reg_value) extract_field((reg_value),9,9) 4380 #define ex_DSC_B_DSC_SM_CTRL_0__slicer_cal_bypass(reg_value) extract_field((reg_value),10,10) 4381 #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_eee_done(reg_value) extract_field((reg_value),11,11) 4382 #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_restart(reg_value) extract_field((reg_value),13,13) 4383 #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_config(reg_value) extract_field((reg_value),14,14) 4384 #define ex_DSC_B_DSC_SM_CTRL_0__set_meas_incomplete(reg_value) extract_field((reg_value),15,15) 4385 #define ex_DSC_B_DSC_SM_CTRL_1__rx_dsc_lock_frc(reg_value) extract_field((reg_value),0,0) 4386 #define ex_DSC_B_DSC_SM_CTRL_1__rx_dsc_lock_frc_val(reg_value) extract_field((reg_value),1,1) 4387 #define ex_DSC_B_DSC_SM_CTRL_1__dsc_clr_frc(reg_value) extract_field((reg_value),2,2) 4388 #define ex_DSC_B_DSC_SM_CTRL_1__dsc_clr_frc_val(reg_value) extract_field((reg_value),3,3) 4389 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_frz_frc(reg_value) extract_field((reg_value),4,4) 4390 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_frz_frc_val(reg_value) extract_field((reg_value),5,5) 4391 #define ex_DSC_B_DSC_SM_CTRL_1__timer_done_frc(reg_value) extract_field((reg_value),6,6) 4392 #define ex_DSC_B_DSC_SM_CTRL_1__timer_done_frc_val(reg_value) extract_field((reg_value),7,7) 4393 #define ex_DSC_B_DSC_SM_CTRL_1__freq_upd_en_frc(reg_value) extract_field((reg_value),8,8) 4394 #define ex_DSC_B_DSC_SM_CTRL_1__freq_upd_en_frc_val(reg_value) extract_field((reg_value),9,9) 4395 #define ex_DSC_B_DSC_SM_CTRL_1__cdr_frz_frc(reg_value) extract_field((reg_value),10,10) 4396 #define ex_DSC_B_DSC_SM_CTRL_1__cdr_frz_frc_val(reg_value) extract_field((reg_value),11,11) 4397 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_clr_frc(reg_value) extract_field((reg_value),12,12) 4398 #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_clr_frc_val(reg_value) extract_field((reg_value),13,13) 4399 #define ex_DSC_B_DSC_SM_CTRL_2__eee_lfsr_cnt(reg_value) extract_field((reg_value),12,0) 4400 #define ex_DSC_B_DSC_SM_CTRL_3__measure_lfsr_cnt(reg_value) extract_field((reg_value),12,0) 4401 #define ex_DSC_B_DSC_SM_CTRL_4__acq_cdr_timeout(reg_value) extract_field((reg_value),4,0) 4402 #define ex_DSC_B_DSC_SM_CTRL_4__cdr_settle_timeout(reg_value) extract_field((reg_value),9,5) 4403 #define ex_DSC_B_DSC_SM_CTRL_4__hw_tune_timeout(reg_value) extract_field((reg_value),14,10) 4404 #define ex_DSC_B_DSC_SM_CTRL_5__measure_timeout(reg_value) extract_field((reg_value),4,0) 4405 #define ex_DSC_B_DSC_SM_CTRL_5__eee_acq_cdr_timeout(reg_value) extract_field((reg_value),9,5) 4406 #define ex_DSC_B_DSC_SM_CTRL_5__eee_cdr_settle_timeout(reg_value) extract_field((reg_value),14,10) 4407 #define ex_DSC_B_DSC_SM_CTRL_6__eee_hw_tune_timeout(reg_value) extract_field((reg_value),4,0) 4408 #define ex_DSC_B_DSC_SM_CTRL_6__eee_ana_pwr_timeout(reg_value) extract_field((reg_value),14,10) 4409 #define ex_DSC_B_DSC_SM_CTRL_6__slicer_cal_timeout(reg_value) extract_field((reg_value),9,5) 4410 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_acqcdr(reg_value) extract_field((reg_value),3,0) 4411 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_eee_acqcdr(reg_value) extract_field((reg_value),7,4) 4412 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_norm(reg_value) extract_field((reg_value),11,8) 4413 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_prop_acqcdr(reg_value) extract_field((reg_value),13,12) 4414 #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_prop_norm(reg_value) extract_field((reg_value),15,14) 4415 #define ex_DSC_B_DSC_SM_CTRL_8__phase_err_offset(reg_value) extract_field_signed((reg_value),3,0) 4416 #define ex_DSC_B_DSC_SM_CTRL_8__eee_phase_err_offset(reg_value) extract_field_signed((reg_value),7,4) 4417 #define ex_DSC_B_DSC_SM_CTRL_8__phase_err_offset_en(reg_value) extract_field((reg_value),9,8) 4418 #define ex_DSC_B_DSC_SM_CTRL_8__eee_phase_err_offset_en(reg_value) extract_field((reg_value),11,10) 4419 #define ex_DSC_B_DSC_SM_CTRL_8__cdr_bwsel_prop_eee_acqcdr(reg_value) extract_field((reg_value),15,14) 4420 #define ex_DSC_B_DSC_SM_CTRL_9__dcoff_cal_timeout(reg_value) extract_field((reg_value),14,10) 4421 #define ex_DSC_B_DSC_SM_CTRL_9__rx_restart_pmd(reg_value) extract_field((reg_value),0,0) 4422 #define ex_DSC_B_DSC_SM_CTRL_9__rx_restart_pmd_hold(reg_value) extract_field((reg_value),1,1) 4423 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0__dsc_state_one_hot_0(reg_value) extract_field((reg_value),15,0) 4424 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1__dsc_state_one_hot_1(reg_value) extract_field((reg_value),1,0) 4425 #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_pi_ext_mode(reg_value) extract_field((reg_value),0,0) 4426 #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_sigdet(reg_value) extract_field((reg_value),1,1) 4427 #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_pmd_restart(reg_value) extract_field((reg_value),2,2) 4428 #define ex_DSC_B_DSC_SM_STATUS_RESTART__eee_quiet_from_eee_states(reg_value) extract_field((reg_value),3,3) 4429 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_state(reg_value) extract_field((reg_value),15,11) 4430 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_ready_for_cmd(reg_value) extract_field((reg_value),7,7) 4431 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__cdr_lm_outoflock(reg_value) extract_field((reg_value),6,6) 4432 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_scratch(reg_value) extract_field((reg_value),10,8) 4433 #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_gp_uc_req(reg_value) extract_field((reg_value),5,0) 4434 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__eee_measure_cnt(reg_value) extract_field((reg_value),15,7) 4435 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__slicer_cal_done(reg_value) extract_field((reg_value),2,2) 4436 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__meas_incomplete(reg_value) extract_field((reg_value),1,1) 4437 #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__rx_dsc_lock(reg_value) extract_field((reg_value),0,0) 4438 #define ex_DSC_C_DFE_1_CTL__dfe_1_en(reg_value) extract_field((reg_value),15,15) 4439 #define ex_DSC_C_DFE_1_CTL__dfe_1_err_sel(reg_value) extract_field((reg_value),14,13) 4440 #define ex_DSC_C_DFE_1_CTL__dfe_1_gradient_invert(reg_value) extract_field((reg_value),12,12) 4441 #define ex_DSC_C_DFE_1_CTL__dfe_1_err_gain(reg_value) extract_field((reg_value),11,10) 4442 #define ex_DSC_C_DFE_1_CTL__dfe_1_inv_m1(reg_value) extract_field((reg_value),9,9) 4443 #define ex_DSC_C_DFE_1_CTL__dfe_1_inv_p1(reg_value) extract_field((reg_value),8,8) 4444 #define ex_DSC_C_DFE_1_CTL__dfe_1_cmn_only(reg_value) extract_field((reg_value),1,1) 4445 #define ex_DSC_C_DFE_1_CTL__dfe_1_acc_clr(reg_value) extract_field((reg_value),0,0) 4446 #define ex_DSC_C_DFE_2_CTL__dfe_2_en(reg_value) extract_field((reg_value),15,15) 4447 #define ex_DSC_C_DFE_2_CTL__dfe_2_err_sel(reg_value) extract_field((reg_value),14,13) 4448 #define ex_DSC_C_DFE_2_CTL__dfe_2_gradient_invert(reg_value) extract_field((reg_value),12,12) 4449 #define ex_DSC_C_DFE_2_CTL__dfe_2_err_gain(reg_value) extract_field((reg_value),11,10) 4450 #define ex_DSC_C_DFE_2_CTL__dfe_2_inv_m1(reg_value) extract_field((reg_value),9,9) 4451 #define ex_DSC_C_DFE_2_CTL__dfe_2_inv_p1(reg_value) extract_field((reg_value),8,8) 4452 #define ex_DSC_C_DFE_2_CTL__dfe_2_cmn_only(reg_value) extract_field((reg_value),1,1) 4453 #define ex_DSC_C_DFE_2_CTL__dfe_2_acc_clr(reg_value) extract_field((reg_value),0,0) 4454 #define ex_DSC_C_DFE_3_CTL__dfe_3_en(reg_value) extract_field((reg_value),15,15) 4455 #define ex_DSC_C_DFE_3_CTL__dfe_3_err_sel(reg_value) extract_field((reg_value),14,13) 4456 #define ex_DSC_C_DFE_3_CTL__dfe_3_gradient_invert(reg_value) extract_field((reg_value),12,12) 4457 #define ex_DSC_C_DFE_3_CTL__dfe_3_err_gain(reg_value) extract_field((reg_value),11,10) 4458 #define ex_DSC_C_DFE_3_CTL__dfe_3_inv_m1(reg_value) extract_field((reg_value),9,9) 4459 #define ex_DSC_C_DFE_3_CTL__dfe_3_inv_p1(reg_value) extract_field((reg_value),8,8) 4460 #define ex_DSC_C_DFE_3_CTL__dfe_3_acc_clr(reg_value) extract_field((reg_value),0,0) 4461 #define ex_DSC_C_DFE_4_CTL__dfe_4_en(reg_value) extract_field((reg_value),15,15) 4462 #define ex_DSC_C_DFE_4_CTL__dfe_4_err_sel(reg_value) extract_field((reg_value),14,13) 4463 #define ex_DSC_C_DFE_4_CTL__dfe_4_gradient_invert(reg_value) extract_field((reg_value),12,12) 4464 #define ex_DSC_C_DFE_4_CTL__dfe_4_err_gain(reg_value) extract_field((reg_value),11,10) 4465 #define ex_DSC_C_DFE_4_CTL__dfe_4_inv_m1(reg_value) extract_field((reg_value),9,9) 4466 #define ex_DSC_C_DFE_4_CTL__dfe_4_inv_p1(reg_value) extract_field((reg_value),8,8) 4467 #define ex_DSC_C_DFE_4_CTL__dfe_4_acc_clr(reg_value) extract_field((reg_value),0,0) 4468 #define ex_DSC_C_DFE_5_CTL__dfe_5_en(reg_value) extract_field((reg_value),15,15) 4469 #define ex_DSC_C_DFE_5_CTL__dfe_5_err_sel(reg_value) extract_field((reg_value),14,13) 4470 #define ex_DSC_C_DFE_5_CTL__dfe_5_gradient_invert(reg_value) extract_field((reg_value),12,12) 4471 #define ex_DSC_C_DFE_5_CTL__dfe_5_err_gain(reg_value) extract_field((reg_value),11,10) 4472 #define ex_DSC_C_DFE_5_CTL__dfe_5_inv_m1(reg_value) extract_field((reg_value),9,9) 4473 #define ex_DSC_C_DFE_5_CTL__dfe_5_inv_p1(reg_value) extract_field((reg_value),8,8) 4474 #define ex_DSC_C_DFE_5_CTL__dfe_5_acc_clr(reg_value) extract_field((reg_value),0,0) 4475 #define ex_DSC_C_DFE_PAT_CTL__dfe_pattern_bit_en(reg_value) extract_field((reg_value),13,8) 4476 #define ex_DSC_C_DFE_PAT_CTL__dfe_pattern(reg_value) extract_field((reg_value),5,0) 4477 #define ex_DSC_C_DFE_COMMON_CTL__dfe_acc_hys_en(reg_value) extract_field((reg_value),15,15) 4478 #define ex_DSC_C_DFE_COMMON_CTL__dfe_allow_simult(reg_value) extract_field((reg_value),14,14) 4479 #define ex_DSC_C_DFE_COMMON_CTL__dfe_update_gain(reg_value) extract_field((reg_value),13,13) 4480 #define ex_DSC_C_DFE_COMMON_CTL__dfe_eye_closure_err_sel(reg_value) extract_field((reg_value),7,6) 4481 #define ex_DSC_C_DFE_COMMON_CTL__dfe_hw_eye_closure_en(reg_value) extract_field((reg_value),5,5) 4482 #define ex_DSC_C_DFE_COMMON_CTL__dfe_leaky_lms_upd_dur(reg_value) extract_field((reg_value),4,1) 4483 #define ex_DSC_C_DFE_COMMON_CTL__dfe_leaky_lms_en(reg_value) extract_field((reg_value),0,0) 4484 #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_en(reg_value) extract_field((reg_value),15,15) 4485 #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_sel(reg_value) extract_field((reg_value),13,9) 4486 #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_val(reg_value) extract_field((reg_value),8,0) 4487 #define ex_DSC_C_VGA_CTL__vga_en(reg_value) extract_field((reg_value),15,15) 4488 #define ex_DSC_C_VGA_CTL__vga_err_sel(reg_value) extract_field((reg_value),14,13) 4489 #define ex_DSC_C_VGA_CTL__vga_p1_gradient_invert(reg_value) extract_field((reg_value),12,12) 4490 #define ex_DSC_C_VGA_CTL__vga_err_gain(reg_value) extract_field((reg_value),11,10) 4491 #define ex_DSC_C_VGA_CTL__vga_inv_m1(reg_value) extract_field((reg_value),9,9) 4492 #define ex_DSC_C_VGA_CTL__vga_inv_p1(reg_value) extract_field((reg_value),8,8) 4493 #define ex_DSC_C_VGA_CTL__vga_update_gain(reg_value) extract_field((reg_value),7,6) 4494 #define ex_DSC_C_VGA_CTL__vga_affected_by_dfe1(reg_value) extract_field((reg_value),4,4) 4495 #define ex_DSC_C_VGA_CTL__vga_update_style(reg_value) extract_field((reg_value),3,2) 4496 #define ex_DSC_C_VGA_CTL__vga_acc_hys_en(reg_value) extract_field((reg_value),1,1) 4497 #define ex_DSC_C_VGA_CTL__vga_p1_acc_clr(reg_value) extract_field((reg_value),0,0) 4498 #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__p1_eyediag_en(reg_value) extract_field((reg_value),15,15) 4499 #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__vga_pattern_bit_en(reg_value) extract_field((reg_value),7,4) 4500 #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__vga_pattern(reg_value) extract_field((reg_value),3,0) 4501 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_hwtune_max(reg_value) extract_field_signed((reg_value),15,10) 4502 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_off_3levelq_en(reg_value) extract_field((reg_value),8,8) 4503 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_offset_en(reg_value) extract_field((reg_value),7,7) 4504 #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_offset(reg_value) extract_field_signed((reg_value),6,0) 4505 #define ex_DSC_C_VGA_P1_MISC_CONTROL__p1_hwtune_min(reg_value) extract_field_signed((reg_value),15,10) 4506 #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_op_short_norm(reg_value) extract_field((reg_value),7,7) 4507 #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_op_short_offcal(reg_value) extract_field((reg_value),6,6) 4508 #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_hwtune_min(reg_value) extract_field_signed((reg_value),5,0) 4509 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_grad_inv(reg_value) extract_field((reg_value),7,7) 4510 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_p1(reg_value) extract_field((reg_value),6,6) 4511 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_m1(reg_value) extract_field((reg_value),5,5) 4512 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_data(reg_value) extract_field((reg_value),4,4) 4513 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_err_gain(reg_value) extract_field((reg_value),3,2) 4514 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_hys_en(reg_value) extract_field((reg_value),1,1) 4515 #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_en(reg_value) extract_field((reg_value),0,0) 4516 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern_bit_en(reg_value) extract_field((reg_value),15,12) 4517 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern(reg_value) extract_field((reg_value),11,8) 4518 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_grad_inv(reg_value) extract_field((reg_value),6,6) 4519 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern_inv_en(reg_value) extract_field((reg_value),5,5) 4520 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_inv(reg_value) extract_field((reg_value),4,4) 4521 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_err_gain(reg_value) extract_field((reg_value),3,2) 4522 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_hys_en(reg_value) extract_field((reg_value),1,1) 4523 #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_en(reg_value) extract_field((reg_value),0,0) 4524 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_en(reg_value) extract_field((reg_value),15,15) 4525 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_err_sel(reg_value) extract_field((reg_value),14,12) 4526 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_random_tapsel_disable(reg_value) extract_field((reg_value),11,11) 4527 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_inv_pattern_en(reg_value) extract_field((reg_value),10,10) 4528 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_pattern_full_check_off(reg_value) extract_field((reg_value),9,9) 4529 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_edge_pattern_en(reg_value) extract_field((reg_value),8,8) 4530 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_gain(reg_value) extract_field((reg_value),7,6) 4531 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_eye_closure_en(reg_value) extract_field((reg_value),5,5) 4532 #define ex_DSC_D_TRNSUM_CTL_1__cdr_qphase_mult_en(reg_value) extract_field((reg_value),4,4) 4533 #define ex_DSC_D_TRNSUM_CTL_1__trnsum_tap_range_sel(reg_value) extract_field((reg_value),3,2) 4534 #define ex_DSC_D_TRNSUM_CTL_2__trnsum_pattern(reg_value) extract_field((reg_value),15,8) 4535 #define ex_DSC_D_TRNSUM_CTL_2__trnsum_pattern_bit_en(reg_value) extract_field((reg_value),7,0) 4536 #define ex_DSC_D_TRNSUM_CTL_3__trnsum_tap_en(reg_value) extract_field((reg_value),15,8) 4537 #define ex_DSC_D_TRNSUM_CTL_3__trnsum_tap_sign(reg_value) extract_field((reg_value),7,0) 4538 #define ex_DSC_D_TRNSUM_CTL_4__tdr_cycle_bin(reg_value) extract_field((reg_value),15,12) 4539 #define ex_DSC_D_TRNSUM_CTL_4__tdr_cycle_sel(reg_value) extract_field((reg_value),11,8) 4540 #define ex_DSC_D_TRNSUM_CTL_4__tdr_trnsum_en(reg_value) extract_field((reg_value),7,7) 4541 #define ex_DSC_D_TRNSUM_CTL_4__tdr_bit_sel(reg_value) extract_field((reg_value),6,2) 4542 #define ex_DSC_D_TRNSUM_CTL_4__trnsum_unsigned_flip(reg_value) extract_field((reg_value),1,1) 4543 #define ex_DSC_D_TRNSUM_CTL_4__trnsum_unsigned_corr(reg_value) extract_field((reg_value),0,0) 4544 #define ex_DSC_D_TRNSUM_STS_1__trnsum_e_high(reg_value) extract_field_signed((reg_value),15,0) 4545 #define ex_DSC_D_TRNSUM_STS_2__trnsum_e_low(reg_value) extract_field((reg_value),7,0) 4546 #define ex_DSC_D_TRNSUM_STS_3__trnsum_o_high(reg_value) extract_field_signed((reg_value),15,0) 4547 #define ex_DSC_D_TRNSUM_STS_4__trnsum_o_low(reg_value) extract_field((reg_value),7,0) 4548 #define ex_DSC_D_TRNSUM_STS_5__trnsum_high(reg_value) extract_field_signed((reg_value),15,0) 4549 #define ex_DSC_D_TRNSUM_STS_6__trnsum_low(reg_value) extract_field((reg_value),9,0) 4550 #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_wants_to_go_high(reg_value) extract_field((reg_value),15,15) 4551 #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_wants_to_go_low(reg_value) extract_field((reg_value),14,14) 4552 #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_eyediag_bin(reg_value) extract_field_signed((reg_value),13,8) 4553 #define ex_DSC_D_VGA_P1EYEDIAG_STS__vga_wants_to_go_low(reg_value) extract_field((reg_value),6,6) 4554 #define ex_DSC_D_VGA_P1EYEDIAG_STS__vga_bin(reg_value) extract_field((reg_value),5,0) 4555 #define ex_DSC_D_DFE_1_STS__dfe_1_wants_negative(reg_value) extract_field((reg_value),15,15) 4556 #define ex_DSC_D_DFE_1_STS__dfe_1_e(reg_value) extract_field((reg_value),13,11) 4557 #define ex_DSC_D_DFE_1_STS__dfe_1_o(reg_value) extract_field((reg_value),10,8) 4558 #define ex_DSC_D_DFE_1_STS__dfe_1_cmn(reg_value) extract_field((reg_value),5,0) 4559 #define ex_DSC_D_DFE_2_STS__dfe_2_e(reg_value) extract_field((reg_value),13,11) 4560 #define ex_DSC_D_DFE_2_STS__dfe_2_o(reg_value) extract_field((reg_value),10,8) 4561 #define ex_DSC_D_DFE_2_STS__dfe_2_se(reg_value) extract_field((reg_value),6,6) 4562 #define ex_DSC_D_DFE_2_STS__dfe_2_so(reg_value) extract_field((reg_value),5,5) 4563 #define ex_DSC_D_DFE_2_STS__dfe_2_cmn(reg_value) extract_field((reg_value),4,0) 4564 #define ex_DSC_D_DFE_3_4_5_STS__dfe_5_cmn(reg_value) extract_field_signed((reg_value),15,11) 4565 #define ex_DSC_D_DFE_3_4_5_STS__dfe_4_cmn(reg_value) extract_field_signed((reg_value),10,6) 4566 #define ex_DSC_D_DFE_3_4_5_STS__dfe_3_cmn(reg_value) extract_field_signed((reg_value),5,0) 4567 #define ex_DSC_D_VGA_TAP_BIN__vga3_ctrl_bin(reg_value) extract_field((reg_value),11,8) 4568 #define ex_DSC_D_VGA_TAP_BIN__vga2_ctrl_bin(reg_value) extract_field((reg_value),7,4) 4569 #define ex_DSC_D_VGA_TAP_BIN__vga1_ctrl_bin(reg_value) extract_field((reg_value),3,0) 4570 #define ex_DSC_E_CTRL__pf_hiz(reg_value) extract_field((reg_value),7,7) 4571 #define ex_DSC_E_CTRL__m1_thresh_sel(reg_value) extract_field((reg_value),6,5) 4572 #define ex_DSC_E_CTRL__m1_thresh_zero(reg_value) extract_field((reg_value),4,4) 4573 #define ex_DSC_E_CTRL__p1_thresh_sel(reg_value) extract_field((reg_value),3,3) 4574 #define ex_DSC_E_CTRL__en_hgain(reg_value) extract_field((reg_value),2,2) 4575 #define ex_DSC_E_CTRL__offset_pd(reg_value) extract_field((reg_value),1,1) 4576 #define ex_DSC_E_CTRL__pd_ch_p1(reg_value) extract_field((reg_value),0,0) 4577 #define ex_DSC_E_PF_CTRL__pf_ctrl(reg_value) extract_field((reg_value),3,0) 4578 #define ex_DSC_E_PF2_LOWP_CTRL__pf2_lowp_ctrl(reg_value) extract_field((reg_value),2,0) 4579 #define ex_DSC_F_DSC_F_DATA_ODD_OFFSET__data_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) 4580 #define ex_DSC_F_DSC_F_DATA_EVEN_OFFSET__data_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) 4581 #define ex_DSC_F_DSC_F_P1_ODD_OFFSET__p1_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) 4582 #define ex_DSC_F_DSC_F_P1_EVEN_OFFSET__p1_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) 4583 #define ex_DSC_F_DSC_F_M1_ODD_OFFSET__m1_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) 4584 #define ex_DSC_F_DSC_F_M1_EVEN_OFFSET__m1_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) 4585 #define ex_DSC_F_DSC_F_DC_OFFSET__dc_offset_bin(reg_value) extract_field_signed((reg_value),6,0) 4586 #define ex_DSC_G_DSC_SM_CTL_15__L1_phase_err_offset_en_G2(reg_value) extract_field((reg_value),15,14) 4587 #define ex_DSC_G_DSC_SM_CTL_15__L1_phase_err_offset_en_G1(reg_value) extract_field((reg_value),13,12) 4588 #define ex_DSC_G_DSC_SM_CTL_15__L0s_phase_err_offset_en_G3(reg_value) extract_field((reg_value),11,10) 4589 #define ex_DSC_G_DSC_SM_CTL_15__L0s_phase_err_offset_en_G2(reg_value) extract_field((reg_value),9,8) 4590 #define ex_DSC_G_DSC_SM_CTL_15__L0s_phase_err_offset_en_G1(reg_value) extract_field((reg_value),7,6) 4591 #define ex_DSC_G_DSC_SM_CTL_15__phase_err_offset_en_G3(reg_value) extract_field((reg_value),5,4) 4592 #define ex_DSC_G_DSC_SM_CTL_15__phase_err_offset_en_G2(reg_value) extract_field((reg_value),3,2) 4593 #define ex_DSC_G_DSC_SM_CTL_15__phase_err_offset_en_G1(reg_value) extract_field((reg_value),1,0) 4594 #define ex_DSC_G_DSC_SM_CTL_16__RxL1Active_frc(reg_value) extract_field((reg_value),15,15) 4595 #define ex_DSC_G_DSC_SM_CTL_16__RxL1Active_frc_val(reg_value) extract_field((reg_value),14,14) 4596 #define ex_DSC_G_DSC_SM_CTL_16__phase_err_offset_G3(reg_value) extract_field_signed((reg_value),13,10) 4597 #define ex_DSC_G_DSC_SM_CTL_16__phase_err_offset_G2(reg_value) extract_field_signed((reg_value),9,6) 4598 #define ex_DSC_G_DSC_SM_CTL_16__phase_err_offset_G1(reg_value) extract_field_signed((reg_value),5,2) 4599 #define ex_DSC_G_DSC_SM_CTL_16__L1_phase_err_offset_en_G3(reg_value) extract_field((reg_value),1,0) 4600 #define ex_DSC_G_DSC_SM_CTL_17__L1_phase_err_offset_G1(reg_value) extract_field_signed((reg_value),15,12) 4601 #define ex_DSC_G_DSC_SM_CTL_17__L0s_phase_err_offset_G3(reg_value) extract_field_signed((reg_value),11,8) 4602 #define ex_DSC_G_DSC_SM_CTL_17__L0s_phase_err_offset_G2(reg_value) extract_field_signed((reg_value),7,4) 4603 #define ex_DSC_G_DSC_SM_CTL_17__L0s_phase_err_offset_G1(reg_value) extract_field_signed((reg_value),3,0) 4604 #define ex_DSC_G_DSC_SM_CTL_18__RxL0sL1Failure_frc(reg_value) extract_field((reg_value),15,15) 4605 #define ex_DSC_G_DSC_SM_CTL_18__RxL0sL1Failure_frc_val(reg_value) extract_field((reg_value),14,14) 4606 #define ex_DSC_G_DSC_SM_CTL_18__dc_offset_frz_frc(reg_value) extract_field((reg_value),13,13) 4607 #define ex_DSC_G_DSC_SM_CTL_18__dc_offset_frz_frc_val(reg_value) extract_field((reg_value),12,12) 4608 #define ex_DSC_G_DSC_SM_CTL_18__dfe_frz_frc(reg_value) extract_field((reg_value),11,11) 4609 #define ex_DSC_G_DSC_SM_CTL_18__dfe_frz_frc_val(reg_value) extract_field((reg_value),10,10) 4610 #define ex_DSC_G_DSC_SM_CTL_18__vga_frz_frc(reg_value) extract_field((reg_value),9,9) 4611 #define ex_DSC_G_DSC_SM_CTL_18__vga_frz_frc_val(reg_value) extract_field((reg_value),8,8) 4612 #define ex_DSC_G_DSC_SM_CTL_18__L1_phase_err_offset_G3(reg_value) extract_field_signed((reg_value),7,4) 4613 #define ex_DSC_G_DSC_SM_CTL_18__L1_phase_err_offset_G2(reg_value) extract_field_signed((reg_value),3,0) 4614 #define ex_DSC_G_DSC_SM_CTL_19__RxL0sActive_frc(reg_value) extract_field((reg_value),14,14) 4615 #define ex_DSC_G_DSC_SM_CTL_19__RxL0sActive_frc_val(reg_value) extract_field((reg_value),13,13) 4616 #define ex_DSC_G_DSC_SM_CTL_19__L0sL1_lfsr_cnt_G2(reg_value) extract_field((reg_value),12,0) 4617 #define ex_DSC_G_DSC_SM_CTL_20__L0sL1_lfsr_cnt_G3(reg_value) extract_field((reg_value),12,0) 4618 #define ex_DSC_G_DSC_SM_CTL_21__hwtune_en_G1G2(reg_value) extract_field((reg_value),15,15) 4619 #define ex_DSC_G_DSC_SM_CTL_21__ucuse_en_G1G2(reg_value) extract_field((reg_value),14,14) 4620 #define ex_DSC_G_DSC_SM_CTL_21__use_facq_done_G1G2(reg_value) extract_field((reg_value),13,13) 4621 #define ex_DSC_G_DSC_SM_CTL_21__norm_lfsr_cnt_G1G2(reg_value) extract_field((reg_value),12,0) 4622 #define ex_DSC_G_DSC_SM_CTL_22__facq_en_disable_G3(reg_value) extract_field((reg_value),15,15) 4623 #define ex_DSC_G_DSC_SM_CTL_22__facq_en_disable_G2(reg_value) extract_field((reg_value),14,14) 4624 #define ex_DSC_G_DSC_SM_CTL_22__facq_en_disable_G1(reg_value) extract_field((reg_value),13,13) 4625 #define ex_DSC_G_DSC_SM_CTL_22__norm_lfsr_cnt_G3(reg_value) extract_field((reg_value),12,0) 4626 #define ex_DSC_G_DSC_SM_CTL_23__cdr_peak_polarity(reg_value) extract_field((reg_value),15,15) 4627 #define ex_DSC_G_DSC_SM_CTL_23__L1_cdr_sttl_timeout_G3(reg_value) extract_field((reg_value),14,10) 4628 #define ex_DSC_G_DSC_SM_CTL_23__L1_cdr_sttl_timeout_G2(reg_value) extract_field((reg_value),9,5) 4629 #define ex_DSC_G_DSC_SM_CTL_23__L1_cdr_sttl_timeout_G1(reg_value) extract_field((reg_value),4,0) 4630 #define ex_DSC_G_DSC_SM_CTL_24__dfe_acc_reset(reg_value) extract_field((reg_value),15,15) 4631 #define ex_DSC_G_DSC_SM_CTL_24__slicer_offset_timeout_G3(reg_value) extract_field((reg_value),14,10) 4632 #define ex_DSC_G_DSC_SM_CTL_24__slicer_offset_timeout_G2(reg_value) extract_field((reg_value),9,5) 4633 #define ex_DSC_G_DSC_SM_CTL_24__slicer_offset_timeout_G1(reg_value) extract_field((reg_value),4,0) 4634 #define ex_DSC_G_DSC_SM_CTL_25__dc_offset_timeout_G3(reg_value) extract_field((reg_value),14,10) 4635 #define ex_DSC_G_DSC_SM_CTL_25__dc_offset_timeout_G2(reg_value) extract_field((reg_value),9,5) 4636 #define ex_DSC_G_DSC_SM_CTL_25__dc_offset_timeout_G1(reg_value) extract_field((reg_value),4,0) 4637 #define ex_DSC_G_DSC_SM_CTL_26__adj_pi_en(reg_value) extract_field((reg_value),15,15) 4638 #define ex_DSC_G_DSC_SM_CTL_26__step_dir(reg_value) extract_field((reg_value),14,14) 4639 #define ex_DSC_G_DSC_SM_CTL_26__m1_minus_d_G2(reg_value) extract_field((reg_value),13,7) 4640 #define ex_DSC_G_DSC_SM_CTL_26__m1_minus_d_G1(reg_value) extract_field((reg_value),6,0) 4641 #define ex_DSC_G_DSC_SM_CTL_27__dc_offset_use_odd_G3(reg_value) extract_field((reg_value),11,11) 4642 #define ex_DSC_G_DSC_SM_CTL_27__dc_offset_use_even_G3(reg_value) extract_field((reg_value),10,10) 4643 #define ex_DSC_G_DSC_SM_CTL_27__dc_offset_use_odd_G1G2(reg_value) extract_field((reg_value),9,9) 4644 #define ex_DSC_G_DSC_SM_CTL_27__dc_offset_use_even_G1G2(reg_value) extract_field((reg_value),8,8) 4645 #define ex_DSC_G_DSC_SM_CTL_27__dsc_sm_manual_mode(reg_value) extract_field((reg_value),7,7) 4646 #define ex_DSC_G_DSC_SM_CTL_27__m1_minus_d_G3(reg_value) extract_field((reg_value),6,0) 4647 #define ex_DSC_G_DSC_SM_CTL_28__dsc_sm_tmux_sel(reg_value) extract_field((reg_value),15,15) 4648 #define ex_DSC_G_DSC_SM_CTL_28__cdr_zero_from_m1_slicer_g2(reg_value) extract_field((reg_value),14,14) 4649 #define ex_DSC_G_DSC_SM_CTL_28__cdr_zero_from_m1_slicer_g1(reg_value) extract_field((reg_value),13,13) 4650 #define ex_DSC_G_DSC_SM_CTL_28__L0sL1_lfsr_cnt_G1(reg_value) extract_field((reg_value),12,0) 4651 #define ex_DSC_G_DSC_SM_CTL_29__sigdet_frc_init(reg_value) extract_field((reg_value),15,15) 4652 #define ex_DSC_G_DSC_SM_CTL_29__disable_L0s_exit(reg_value) extract_field((reg_value),14,14) 4653 #define ex_DSC_G_DSC_SM_CTL_29__disable_L1_exit(reg_value) extract_field((reg_value),13,13) 4654 #define ex_DSC_G_DSC_SM_CTL_29__dsc_slicer_offset_done_frc(reg_value) extract_field((reg_value),12,12) 4655 #define ex_DSC_G_DSC_SM_CTL_29__dsc_slicer_offset_done_frc_val(reg_value) extract_field((reg_value),11,11) 4656 #define ex_DSC_G_DSC_SM_CTL_29__dsc_slicer_offset_cnt_frc(reg_value) extract_field((reg_value),10,10) 4657 #define ex_DSC_G_DSC_SM_CTL_29__dsc_slicer_offset_cnt_frc_val(reg_value) extract_field((reg_value),9,7) 4658 #define ex_DSC_G_DSC_SM_CTL_29__redo_slicer_calibration(reg_value) extract_field((reg_value),6,6) 4659 #define ex_DSC_G_DSC_SM_CTL_29__slicer_calibration_mask(reg_value) extract_field((reg_value),5,0) 4660 #define ex_DSC_H_DSC_SM_CTL_30__cdr_pattern_sel_lock_G3(reg_value) extract_field((reg_value),15,12) 4661 #define ex_DSC_H_DSC_SM_CTL_30__cdr_pattern_sel_steady_state_G3(reg_value) extract_field((reg_value),11,8) 4662 #define ex_DSC_H_DSC_SM_CTL_30__cdr_pattern_sel_steady_state_G2(reg_value) extract_field((reg_value),7,4) 4663 #define ex_DSC_H_DSC_SM_CTL_30__cdr_pattern_sel_steady_state_G1(reg_value) extract_field((reg_value),3,0) 4664 #define ex_DSC_H_DSC_SM_CTL_31__dsc_sm_pause_entry(reg_value) extract_field((reg_value),15,15) 4665 #define ex_DSC_H_DSC_SM_CTL_31__dsc_sm_pause_exit(reg_value) extract_field((reg_value),14,14) 4666 #define ex_DSC_H_DSC_SM_CTL_31__dsc_lock_in_uc_tune(reg_value) extract_field((reg_value),13,11) 4667 #define ex_DSC_H_DSC_SM_CTL_31__dsc_lock_in_hw_tune(reg_value) extract_field((reg_value),10,8) 4668 #define ex_DSC_H_DSC_SM_CTL_31__cdr_pattern_sel_lock_G2(reg_value) extract_field((reg_value),7,4) 4669 #define ex_DSC_H_DSC_SM_CTL_31__cdr_pattern_sel_lock_G1(reg_value) extract_field((reg_value),3,0) 4670 #define ex_DSC_H_DSC_SM_CTL_32__dfe_clken_frc(reg_value) extract_field((reg_value),15,15) 4671 #define ex_DSC_H_DSC_SM_CTL_32__dfe_clken_frc_val(reg_value) extract_field((reg_value),14,14) 4672 #define ex_DSC_H_DSC_SM_CTL_32__rx_pi_step_size_norm_G3(reg_value) extract_field((reg_value),13,12) 4673 #define ex_DSC_H_DSC_SM_CTL_32__rx_pi_step_size_norm_G2(reg_value) extract_field((reg_value),11,10) 4674 #define ex_DSC_H_DSC_SM_CTL_32__rx_pi_step_size_norm_G1(reg_value) extract_field((reg_value),9,8) 4675 #define ex_DSC_H_DSC_SM_CTL_32__rx_pi_step_size_facq_G3(reg_value) extract_field((reg_value),7,6) 4676 #define ex_DSC_H_DSC_SM_CTL_32__rx_pi_step_size_facq_G2(reg_value) extract_field((reg_value),5,4) 4677 #define ex_DSC_H_DSC_SM_CTL_32__rx_pi_step_size_facq_G1(reg_value) extract_field((reg_value),3,2) 4678 #define ex_DSC_H_DSC_SM_CTL_33__pcie_g1_condition_mask_e(reg_value) extract_field((reg_value),9,0) 4679 #define ex_DSC_H_DSC_SM_CTL_34__pcie_g1_condition_mask_o(reg_value) extract_field((reg_value),9,0) 4680 #define ex_DSC_H_DSC_SM_STATUS_0__vga_op_short(reg_value) extract_field((reg_value),3,3) 4681 #define ex_DSC_H_DSC_SM_STATUS_0__RxFastAcqEnable_mux(reg_value) extract_field((reg_value),2,2) 4682 #define ex_DSC_H_DSC_SM_STATUS_0__RxFastAcqEnable_G1G2(reg_value) extract_field((reg_value),1,1) 4683 #define ex_DSC_H_DSC_SM_STATUS_0__RxFastAcqEnable_G3(reg_value) extract_field((reg_value),0,0) 4684 #define ex_DSC_I_RX_HIST_STAT_0__rx_hist_00(reg_value) extract_field((reg_value),15,0) 4685 #define ex_DSC_I_RX_HIST_STAT_1__rx_hist_01(reg_value) extract_field((reg_value),15,0) 4686 #define ex_DSC_I_RX_HIST_STAT_2__rx_hist_02(reg_value) extract_field((reg_value),15,0) 4687 #define ex_DSC_I_RX_HIST_STAT_3__rx_hist_03(reg_value) extract_field((reg_value),15,0) 4688 #define ex_DSC_I_RX_HIST_STAT_4__rx_hist_04(reg_value) extract_field((reg_value),15,0) 4689 #define ex_DSC_I_RX_HIST_STAT_5__rx_hist_05(reg_value) extract_field((reg_value),15,0) 4690 #define ex_DSC_I_RX_HIST_STAT_6__rx_hist_06(reg_value) extract_field((reg_value),15,0) 4691 #define ex_DSC_I_RX_HIST_STAT_7__rx_hist_07(reg_value) extract_field((reg_value),15,0) 4692 #define ex_DSC_I_RX_HIST_STAT_8__rx_hist_08(reg_value) extract_field((reg_value),15,0) 4693 #define ex_DSC_I_RX_HIST_STAT_9__rx_hist_09(reg_value) extract_field((reg_value),15,0) 4694 #define ex_DSC_I_RX_HIST_STAT_10__rx_hist_10(reg_value) extract_field((reg_value),15,0) 4695 #define ex_DSC_I_RX_HIST_STAT_11__rx_hist_11(reg_value) extract_field((reg_value),15,0) 4696 #define ex_DSC_I_RX_HIST_STAT_12__rx_hist_12(reg_value) extract_field((reg_value),15,0) 4697 #define ex_DSC_I_RX_HIST_STAT_13__rx_hist_13(reg_value) extract_field((reg_value),15,0) 4698 #define ex_DSC_I_RX_HIST_CTRL__rg_hist_clr(reg_value) extract_field((reg_value),3,3) 4699 #define ex_DSC_I_RX_HIST_CTRL__rg_hist_stop(reg_value) extract_field((reg_value),2,2) 4700 #define ex_DSC_I_RX_HIST_CTRL__rg_hist_rd_mux_sel(reg_value) extract_field((reg_value),1,0) 4701 #define ex_DSC_J_DSC_SM_CTL_0__uc_adj_pi(reg_value) extract_field((reg_value),15,15) 4702 #define ex_DSC_J_DSC_SM_CTL_0__acq_cdr_timeout_G3(reg_value) extract_field((reg_value),14,10) 4703 #define ex_DSC_J_DSC_SM_CTL_0__acq_cdr_timeout_G2(reg_value) extract_field((reg_value),9,5) 4704 #define ex_DSC_J_DSC_SM_CTL_0__acq_cdr_timeout_G1(reg_value) extract_field((reg_value),4,0) 4705 #define ex_DSC_J_DSC_SM_CTL_1__cdr_settle_timeout_G3(reg_value) extract_field((reg_value),14,10) 4706 #define ex_DSC_J_DSC_SM_CTL_1__cdr_settle_timeout_G2(reg_value) extract_field((reg_value),9,5) 4707 #define ex_DSC_J_DSC_SM_CTL_1__cdr_settle_timeout_G1(reg_value) extract_field((reg_value),4,0) 4708 #define ex_DSC_J_DSC_SM_CTL_2__hw_tune_timeout_G3(reg_value) extract_field((reg_value),14,10) 4709 #define ex_DSC_J_DSC_SM_CTL_2__hw_tune_timeout_G2(reg_value) extract_field((reg_value),9,5) 4710 #define ex_DSC_J_DSC_SM_CTL_2__hw_tune_timeout_G1(reg_value) extract_field((reg_value),4,0) 4711 #define ex_DSC_J_DSC_SM_CTL_3__facq_wait_timeout_G3(reg_value) extract_field((reg_value),14,10) 4712 #define ex_DSC_J_DSC_SM_CTL_3__facq_wait_timeout_G2(reg_value) extract_field((reg_value),9,5) 4713 #define ex_DSC_J_DSC_SM_CTL_3__facq_wait_timeout_G1(reg_value) extract_field((reg_value),4,0) 4714 #define ex_DSC_J_DSC_SM_CTL_4__L0s_acq_cdr_timeout_G3(reg_value) extract_field((reg_value),14,10) 4715 #define ex_DSC_J_DSC_SM_CTL_4__L0s_acq_cdr_timeout_G2(reg_value) extract_field((reg_value),9,5) 4716 #define ex_DSC_J_DSC_SM_CTL_4__L0s_acq_cdr_timeout_G1(reg_value) extract_field((reg_value),4,0) 4717 #define ex_DSC_J_DSC_SM_CTL_5__L1_acq_cdr_timeout_G3(reg_value) extract_field((reg_value),14,10) 4718 #define ex_DSC_J_DSC_SM_CTL_5__L1_acq_cdr_timeout_G2(reg_value) extract_field((reg_value),9,5) 4719 #define ex_DSC_J_DSC_SM_CTL_5__L1_acq_cdr_timeout_G1(reg_value) extract_field((reg_value),4,0) 4720 #define ex_DSC_J_DSC_SM_CTL_6__L0s_cdr_sttl_timeout_G3(reg_value) extract_field((reg_value),14,10) 4721 #define ex_DSC_J_DSC_SM_CTL_6__L0s_cdr_sttl_timeout_G2(reg_value) extract_field((reg_value),9,5) 4722 #define ex_DSC_J_DSC_SM_CTL_6__L0s_cdr_sttl_timeout_G1(reg_value) extract_field((reg_value),4,0) 4723 #define ex_DSC_J_DSC_SM_CTL_7__L1_hw_tune_timeout_G3(reg_value) extract_field((reg_value),14,10) 4724 #define ex_DSC_J_DSC_SM_CTL_7__L0s_hw_tune_timeout_G3(reg_value) extract_field((reg_value),9,5) 4725 #define ex_DSC_J_DSC_SM_CTL_7__measure_timeout_G3(reg_value) extract_field((reg_value),4,0) 4726 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_L0s_acqcdr_G2(reg_value) extract_field((reg_value),15,14) 4727 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_L0s_acqcdr_G1(reg_value) extract_field((reg_value),13,12) 4728 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_norm_G3(reg_value) extract_field((reg_value),11,10) 4729 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_norm_G2(reg_value) extract_field((reg_value),9,8) 4730 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_norm_G1(reg_value) extract_field((reg_value),7,6) 4731 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_acqcdr_G3(reg_value) extract_field((reg_value),5,4) 4732 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_acqcdr_G2(reg_value) extract_field((reg_value),3,2) 4733 #define ex_DSC_J_DSC_SM_CTL_8__cdr_bwsel_prop_acqcdr_G1(reg_value) extract_field((reg_value),1,0) 4734 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L0s_acqcdr_G3(reg_value) extract_field((reg_value),1,0) 4735 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L1_acqcdr_G1(reg_value) extract_field((reg_value),3,2) 4736 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L1_acqcdr_G2(reg_value) extract_field((reg_value),5,4) 4737 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L1_acqcdr_G3(reg_value) extract_field((reg_value),7,6) 4738 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L0s_cdrsttl_G1(reg_value) extract_field((reg_value),9,8) 4739 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L0s_cdrsttl_G2(reg_value) extract_field((reg_value),11,10) 4740 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L0s_cdrsttl_G3(reg_value) extract_field((reg_value),13,12) 4741 #define ex_DSC_J_DSC_SM_CTL_9__cdr_bwsel_prop_L1_cdrsttl_G1(reg_value) extract_field((reg_value),15,14) 4742 #define ex_DSC_J_DSC_SM_CTL_10__cdr_bwsel_integ_acqcdr_G3(reg_value) extract_field((reg_value),15,12) 4743 #define ex_DSC_J_DSC_SM_CTL_10__cdr_bwsel_integ_acqcdr_G2(reg_value) extract_field((reg_value),11,8) 4744 #define ex_DSC_J_DSC_SM_CTL_10__cdr_bwsel_integ_acqcdr_G1(reg_value) extract_field((reg_value),7,4) 4745 #define ex_DSC_J_DSC_SM_CTL_10__cdr_bwsel_prop_L1_cdrsttl_G3(reg_value) extract_field((reg_value),3,2) 4746 #define ex_DSC_J_DSC_SM_CTL_10__cdr_bwsel_prop_L1_cdrsttl_G2(reg_value) extract_field((reg_value),1,0) 4747 #define ex_DSC_J_DSC_SM_CTL_11__cdr_bwsel_integ_L0s_acqcdr_G1(reg_value) extract_field((reg_value),15,12) 4748 #define ex_DSC_J_DSC_SM_CTL_11__cdr_bwsel_integ_norm_G3(reg_value) extract_field((reg_value),11,8) 4749 #define ex_DSC_J_DSC_SM_CTL_11__cdr_bwsel_integ_norm_G2(reg_value) extract_field((reg_value),7,4) 4750 #define ex_DSC_J_DSC_SM_CTL_11__cdr_bwsel_integ_norm_G1(reg_value) extract_field((reg_value),3,0) 4751 #define ex_DSC_J_DSC_SM_CTL_12__cdr_bwsel_integ_L1_acqcdr_G2(reg_value) extract_field((reg_value),15,12) 4752 #define ex_DSC_J_DSC_SM_CTL_12__cdr_bwsel_integ_L1_acqcdr_G1(reg_value) extract_field((reg_value),11,8) 4753 #define ex_DSC_J_DSC_SM_CTL_12__cdr_bwsel_integ_L0s_acqcdr_G3(reg_value) extract_field((reg_value),7,4) 4754 #define ex_DSC_J_DSC_SM_CTL_12__cdr_bwsel_integ_L0s_acqcdr_G2(reg_value) extract_field((reg_value),3,0) 4755 #define ex_DSC_J_DSC_SM_CTL_13__cdr_bwsel_integ_L0s_cdrsttl_G3(reg_value) extract_field((reg_value),15,12) 4756 #define ex_DSC_J_DSC_SM_CTL_13__cdr_bwsel_integ_L0s_cdrsttl_G2(reg_value) extract_field((reg_value),11,8) 4757 #define ex_DSC_J_DSC_SM_CTL_13__cdr_bwsel_integ_L0s_cdrsttl_G1(reg_value) extract_field((reg_value),7,4) 4758 #define ex_DSC_J_DSC_SM_CTL_13__cdr_bwsel_integ_L1_acqcdr_G3(reg_value) extract_field((reg_value),3,0) 4759 #define ex_DSC_J_DSC_SM_CTL_14__cdr_bwsel_integ_L1_cdrsttl_G3(reg_value) extract_field((reg_value),11,8) 4760 #define ex_DSC_J_DSC_SM_CTL_14__cdr_bwsel_integ_L1_cdrsttl_G2(reg_value) extract_field((reg_value),7,4) 4761 #define ex_DSC_J_DSC_SM_CTL_14__cdr_bwsel_integ_L1_cdrsttl_G1(reg_value) extract_field((reg_value),3,0) 4762 #define exc_MDIO_BLK_ADDR_COM_BLK_ADDR__mdio_blk_addr(reg_value) extract_field((reg_value),14,4) 4763 #define exc_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR__mdio_brcst_port_addr(reg_value) extract_field((reg_value),4,0) 4764 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_multi_prts_en(reg_value) extract_field((reg_value),15,15) 4765 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_multi_mmds_en(reg_value) extract_field((reg_value),14,14) 4766 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_pcs_en(reg_value) extract_field((reg_value),6,6) 4767 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_dte_en(reg_value) extract_field((reg_value),5,5) 4768 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_phy_en(reg_value) extract_field((reg_value),4,4) 4769 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_an_en(reg_value) extract_field((reg_value),3,3) 4770 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_pmd_en(reg_value) extract_field((reg_value),2,2) 4771 #define exc_MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT__mdio_dev_cl22_en(reg_value) extract_field((reg_value),0,0) 4772 #define exc_MDIO_MMDSEL_AER_COM_MDIO_AER__mdio_aer(reg_value) extract_field((reg_value),15,0) 4773 #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_core_clk_en(reg_value) extract_field((reg_value),1,1) 4774 #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_master_clk_en(reg_value) extract_field((reg_value),0,0) 4775 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_pram_if_rstb(reg_value) extract_field((reg_value),3,3) 4776 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_core_rstb(reg_value) extract_field((reg_value),1,1) 4777 #define exc_MICRO_A_COM_RESET_CONTROL0__micro_master_rstb(reg_value) extract_field((reg_value),0,0) 4778 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_rdaddr_en(reg_value) extract_field((reg_value),13,13) 4779 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_wraddr_en(reg_value) extract_field((reg_value),12,12) 4780 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_init(reg_value) extract_field((reg_value),9,8) 4781 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_rddatasize(reg_value) extract_field((reg_value),5,4) 4782 #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_wrdatasize(reg_value) extract_field((reg_value),1,0) 4783 #define exc_MICRO_A_COM_AHB_STATUS0__micro_ra_initdone(reg_value) extract_field((reg_value),0,0) 4784 #define exc_MICRO_A_COM_AHB_WRADDR_LSW__micro_ra_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 4785 #define exc_MICRO_A_COM_AHB_WRADDR_MSW__micro_ra_wraddr_msw(reg_value) extract_field((reg_value),15,0) 4786 #define exc_MICRO_A_COM_AHB_WRDATA_LSW__micro_ra_wrdata_lsw(reg_value) extract_field((reg_value),15,0) 4787 #define exc_MICRO_A_COM_AHB_WRDATA_MSW__micro_ra_wrdata_msw(reg_value) extract_field((reg_value),15,0) 4788 #define exc_MICRO_A_COM_AHB_RDADDR_LSW__micro_ra_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) 4789 #define exc_MICRO_A_COM_AHB_RDADDR_MSW__micro_ra_rdaddr_msw(reg_value) extract_field((reg_value),15,0) 4790 #define exc_MICRO_A_COM_AHB_RDDATA_LSW__micro_ra_rddata_lsw(reg_value) extract_field((reg_value),15,0) 4791 #define exc_MICRO_A_COM_AHB_RDDATA_MSW__micro_ra_rddata_msw(reg_value) extract_field((reg_value),15,0) 4792 #define exc_MICRO_A_COM_PRAMIF_CONTROL0__micro_pramif_en(reg_value) extract_field((reg_value),0,0) 4793 #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW__micro_pramif_ahb_wraddr_lsw(reg_value) extract_field((reg_value),15,2) 4794 #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW__micro_pramif_ahb_wraddr_msw(reg_value) extract_field((reg_value),15,0) 4795 #define exc_MICRO_B_COM_PVT_STATUS0__micro_pvt_tempdata_rmi(reg_value) extract_field((reg_value),9,0) 4796 #define exc_MICRO_B_COM_RMI_TO_MICRO_MBOX0__micro_rmi_to_micro_mbox0(reg_value) extract_field((reg_value),15,0) 4797 #define exc_MICRO_B_COM_RMI_TO_MICRO_MBOX1__micro_rmi_to_micro_mbox1(reg_value) extract_field((reg_value),15,0) 4798 #define exc_MICRO_B_COM_MICRO_TO_RMI_MBOX0__micro_to_rmi_mbox0(reg_value) extract_field((reg_value),15,0) 4799 #define exc_MICRO_B_COM_MICRO_TO_RMI_MBOX1__micro_to_rmi_mbox1(reg_value) extract_field((reg_value),15,0) 4800 #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_gen_intr_rmi_mbox1wr(reg_value) extract_field((reg_value),2,2) 4801 #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_gen_intr_rmi_mbox0wr(reg_value) extract_field((reg_value),1,1) 4802 #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_rmi_mbox_send_msgin(reg_value) extract_field((reg_value),0,0) 4803 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ext_ack_timeout_dis(reg_value) extract_field((reg_value),4,4) 4804 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ack_timeout_dis(reg_value) extract_field((reg_value),3,3) 4805 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_sw_pmi_hp_ext_rstb(reg_value) extract_field((reg_value),2,2) 4806 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_sw_pmi_hp_rstb(reg_value) extract_field((reg_value),1,1) 4807 #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_m0_hresp_en(reg_value) extract_field((reg_value),0,0) 4808 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_pr_default_slave_error(reg_value) extract_field((reg_value),2,2) 4809 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_rmi_default_slave_error(reg_value) extract_field((reg_value),1,1) 4810 #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_m0_default_slave_error(reg_value) extract_field((reg_value),0,0) 4811 #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW__micro_ra_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 4812 #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW__micro_ra_autoinc_nxt_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) 4813 #define exc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW__micro_pr_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) 4814 #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frc(reg_value) extract_field((reg_value),12,12) 4815 #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frcval(reg_value) extract_field((reg_value),9,0) 4816 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_ecc_corrupt(reg_value) extract_field((reg_value),5,4) 4817 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_ecc_frc_disable(reg_value) extract_field((reg_value),1,1) 4818 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_eccg_mode(reg_value) extract_field((reg_value),0,0) 4819 #define exc_MICRO_C_COM_CODE_RAM_ECCCONTRO1__micro_ra_ecc_wrdata(reg_value) extract_field((reg_value),6,0) 4820 #define exc_MICRO_C_COM_CODE_RAM_ECCSTATUS0__micro_code_ram_ecc_address(reg_value) extract_field((reg_value),14,0) 4821 #define exc_MICRO_C_COM_CODE_RAM_ECCSTATUS1__micro_ra_ecc_rddata(reg_value) extract_field((reg_value),6,0) 4822 #define exc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0__micro_code_ram_tm(reg_value) extract_field((reg_value),6,0) 4823 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_ignore_m0_code_writes(reg_value) extract_field((reg_value),15,15) 4824 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_ramclk_noninv(reg_value) extract_field((reg_value),14,14) 4825 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_size(reg_value) extract_field((reg_value),13,8) 4826 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_protect_fwcode(reg_value) extract_field((reg_value),1,1) 4827 #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_looktab_en(reg_value) extract_field((reg_value),0,0) 4828 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0_systemresetreq_status(reg_value) extract_field((reg_value),9,9) 4829 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0_lockup_status(reg_value) extract_field((reg_value),8,8) 4830 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_multirow_err_status(reg_value) extract_field((reg_value),6,6) 4831 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_uncorr_err_status(reg_value) extract_field((reg_value),5,5) 4832 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_corr_err_status(reg_value) extract_field((reg_value),4,4) 4833 #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_mbox_msgout_status(reg_value) extract_field((reg_value),0,0) 4834 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0_systemresetreq_intr_en(reg_value) extract_field((reg_value),9,9) 4835 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0_lockup_intr_en(reg_value) extract_field((reg_value),8,8) 4836 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_multirow_err_intr_en(reg_value) extract_field((reg_value),6,6) 4837 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_uncorr_err_intr_en(reg_value) extract_field((reg_value),5,5) 4838 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_corr_err_intr_en(reg_value) extract_field((reg_value),4,4) 4839 #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_mbox_msgout_intr_en(reg_value) extract_field((reg_value),0,0) 4840 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_bktobk_en(reg_value) extract_field((reg_value),10,10) 4841 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_dual_meta_ff_en(reg_value) extract_field((reg_value),9,9) 4842 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_read_en(reg_value) extract_field((reg_value),8,8) 4843 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_bktobk_en(reg_value) extract_field((reg_value),2,2) 4844 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_dual_meta_ff_en(reg_value) extract_field((reg_value),1,1) 4845 #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_read_en(reg_value) extract_field((reg_value),0,0) 4846 #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0__micro_silicon_debug_status_mux_sel(reg_value) extract_field((reg_value),1,0) 4847 #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0__micro_silicon_debug_status_muxed_data(reg_value) extract_field((reg_value),15,0) 4848 #define ex_MICRO_CTRL0_UC_CTRL0__uc_gen3_rdy(reg_value) extract_field((reg_value),0,0) 4849 #define ex_MICRO_CTRL0_UC_CTRL1__eval_done(reg_value) extract_field((reg_value),15,15) 4850 #define ex_MICRO_CTRL0_UC_CTRL1__eval_err_clr(reg_value) extract_field((reg_value),14,14) 4851 #define ex_MICRO_CTRL0_UC_CTRL1__fdbk_dir_chg(reg_value) extract_field((reg_value),13,8) 4852 #define ex_MICRO_CTRL0_UC_CTRL1__fig_merit(reg_value) extract_field((reg_value),7,0) 4853 #define ex_MICRO_CTRL0_UC_CTRL2__pf2_lowp_ctrl_g2(reg_value) extract_field((reg_value),15,13) 4854 #define ex_MICRO_CTRL0_UC_CTRL2__rx_pf_hiz_g2(reg_value) extract_field((reg_value),12,12) 4855 #define ex_MICRO_CTRL0_UC_CTRL2__pf_ctrl_g2(reg_value) extract_field((reg_value),11,8) 4856 #define ex_MICRO_CTRL0_UC_CTRL2__pf2_lowp_ctrl_g1(reg_value) extract_field((reg_value),7,5) 4857 #define ex_MICRO_CTRL0_UC_CTRL2__rx_pf_hiz_g1(reg_value) extract_field((reg_value),4,4) 4858 #define ex_MICRO_CTRL0_UC_CTRL2__pf_ctrl_g1(reg_value) extract_field((reg_value),3,0) 4859 #define ex_MICRO_CTRL0_UC_CTRL3__rx_en_dfe_clk_G1G2(reg_value) extract_field((reg_value),13,13) 4860 #define ex_MICRO_CTRL0_UC_CTRL3__rx_m1_thresh_zero_G1G2(reg_value) extract_field((reg_value),12,12) 4861 #define ex_MICRO_CTRL0_UC_CTRL3__rx_vga3_ctrl_G1G2(reg_value) extract_field((reg_value),11,8) 4862 #define ex_MICRO_CTRL0_UC_CTRL3__rx_vga2_ctrl_G1G2(reg_value) extract_field((reg_value),7,4) 4863 #define ex_MICRO_CTRL0_UC_CTRL3__rx_vga1_ctrl_G1G2(reg_value) extract_field((reg_value),3,0) 4864 #define ex_MICRO_CTRL0_LP_INFO0__lp_main_coeff(reg_value) extract_field((reg_value),13,8) 4865 #define ex_MICRO_CTRL0_LP_INFO0__lp_pre_coeff(reg_value) extract_field((reg_value),5,0) 4866 #define ex_MICRO_CTRL0_LP_INFO1__rx_hint(reg_value) extract_field((reg_value),14,12) 4867 #define ex_MICRO_CTRL0_LP_INFO1__lp_post_coeff(reg_value) extract_field((reg_value),5,0) 4868 #define ex_MICRO_CTRL0_LP_INFO2__tx_lf(reg_value) extract_field((reg_value),13,8) 4869 #define ex_MICRO_CTRL0_LP_INFO2__lp_fs(reg_value) extract_field((reg_value),5,0) 4870 #define ex_MICRO_CTRL0_UC_EVAL_STAT__err_clr(reg_value) extract_field((reg_value),3,3) 4871 #define ex_MICRO_CTRL0_UC_EVAL_STAT__eq_done(reg_value) extract_field((reg_value),2,2) 4872 #define ex_MICRO_CTRL0_UC_EVAL_STAT__eval_err(reg_value) extract_field((reg_value),1,1) 4873 #define ex_MICRO_CTRL0_UC_EVAL_STAT__eq_eval(reg_value) extract_field((reg_value),0,0) 4874 #define ex_MICRO_DBG_STATUS0__rate_sel(reg_value) extract_field((reg_value),13,12) 4875 #define ex_MICRO_DBG_STATUS0__rx_sigdet(reg_value) extract_field((reg_value),10,8) 4876 #define ex_MICRO_DBG_STATUS0__rx_sigdet_st(reg_value) extract_field((reg_value),7,5) 4877 #define ex_MICRO_DBG_STATUS0__uc_dbg_dsc_state(reg_value) extract_field((reg_value),4,0) 4878 #define ex_MICRO_DBG_MICRO_DEBUG1__micro_dbg1(reg_value) extract_field((reg_value),15,1) 4879 #define ex_MICRO_DBG_MICRO_DEBUG1__micro_2lane_ena_type(reg_value) extract_field((reg_value),0,0) 4880 #define ex_MICRO_DBG_MICRO_DEBUG2__micro_dbg2(reg_value) extract_field((reg_value),15,0) 4881 #define ex_MICRO_DBG_MICRO_DEBUG3__micro_dbg3(reg_value) extract_field((reg_value),15,0) 4882 #define ex_MICRO_DBG_MICRO_DEBUG4__micro_dbg4(reg_value) extract_field((reg_value),15,0) 4883 #define ex_MICRO_DBG_MICRO_DEBUG5__micro_dbg5(reg_value) extract_field((reg_value),15,0) 4884 #define ex_MICRO_DBG_MICRO_DEBUG6__micro_dbg6(reg_value) extract_field((reg_value),15,0) 4885 #define ex_MICRO_DBG_MICRO_DEBUG7__micro_dbg7(reg_value) extract_field((reg_value),15,0) 4886 #define ex_MICRO_DBG_MICRO_DEBUG8__micro_dbg8(reg_value) extract_field((reg_value),15,0) 4887 #define ex_MICRO_DBG_MICRO_DEBUG9__micro_dbg9(reg_value) extract_field((reg_value),15,0) 4888 #define ex_MICRO_DBG_MICRO_DEBUG10__micro_dbg10(reg_value) extract_field((reg_value),15,0) 4889 #define ex_MICRO_DBG_MICRO_DEBUG11__micro_dbg11(reg_value) extract_field((reg_value),15,0) 4890 #define ex_MICRO_DBG_MICRO_DEBUG12__micro_dbg12(reg_value) extract_field((reg_value),15,0) 4891 #define ex_MICRO_DBG_MICRO_DEBUG13__micro_dbg13(reg_value) extract_field((reg_value),15,0) 4892 #define ex_MICRO_DBG_MICRO_DEBUG14__micro_dbg14(reg_value) extract_field((reg_value),15,0) 4893 #define exc_MICRO_INFO_COM_CTRL0__uc_version(reg_value) extract_field((reg_value),15,0) 4894 #define exc_MICRO_INFO_COM_EVAL_STAT__err_clr3(reg_value) extract_field((reg_value),15,15) 4895 #define exc_MICRO_INFO_COM_EVAL_STAT__err_clr2(reg_value) extract_field((reg_value),14,14) 4896 #define exc_MICRO_INFO_COM_EVAL_STAT__err_clr1(reg_value) extract_field((reg_value),13,13) 4897 #define exc_MICRO_INFO_COM_EVAL_STAT__err_clr0(reg_value) extract_field((reg_value),12,12) 4898 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_done_3(reg_value) extract_field((reg_value),11,11) 4899 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_done_2(reg_value) extract_field((reg_value),10,10) 4900 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_done_1(reg_value) extract_field((reg_value),9,9) 4901 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_done_0(reg_value) extract_field((reg_value),8,8) 4902 #define exc_MICRO_INFO_COM_EVAL_STAT__eval_err_3(reg_value) extract_field((reg_value),7,7) 4903 #define exc_MICRO_INFO_COM_EVAL_STAT__eval_err_2(reg_value) extract_field((reg_value),6,6) 4904 #define exc_MICRO_INFO_COM_EVAL_STAT__eval_err_1(reg_value) extract_field((reg_value),5,5) 4905 #define exc_MICRO_INFO_COM_EVAL_STAT__eval_err_0(reg_value) extract_field((reg_value),4,4) 4906 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_eval_3(reg_value) extract_field((reg_value),3,3) 4907 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_eval_2(reg_value) extract_field((reg_value),2,2) 4908 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_eval_1(reg_value) extract_field((reg_value),1,1) 4909 #define exc_MICRO_INFO_COM_EVAL_STAT__eq_eval_0(reg_value) extract_field((reg_value),0,0) 4910 #define exc_PATT_GEN_COM_SEQ_0__patt_gen_seq_0(reg_value) extract_field((reg_value),15,0) 4911 #define exc_PATT_GEN_COM_SEQ_1__patt_gen_seq_1(reg_value) extract_field((reg_value),15,0) 4912 #define exc_PATT_GEN_COM_SEQ_2__patt_gen_seq_2(reg_value) extract_field((reg_value),15,0) 4913 #define exc_PATT_GEN_COM_SEQ_3__patt_gen_seq_3(reg_value) extract_field((reg_value),15,0) 4914 #define exc_PATT_GEN_COM_SEQ_4__patt_gen_seq_4(reg_value) extract_field((reg_value),15,0) 4915 #define exc_PATT_GEN_COM_SEQ_5__patt_gen_seq_5(reg_value) extract_field((reg_value),15,0) 4916 #define exc_PATT_GEN_COM_SEQ_6__patt_gen_seq_6(reg_value) extract_field((reg_value),15,0) 4917 #define exc_PATT_GEN_COM_SEQ_7__patt_gen_seq_7(reg_value) extract_field((reg_value),15,0) 4918 #define exc_PATT_GEN_COM_SEQ_8__patt_gen_seq_8(reg_value) extract_field((reg_value),15,0) 4919 #define exc_PATT_GEN_COM_SEQ_9__patt_gen_seq_9(reg_value) extract_field((reg_value),15,0) 4920 #define exc_PATT_GEN_COM_SEQ_10__patt_gen_seq_10(reg_value) extract_field((reg_value),15,0) 4921 #define exc_PATT_GEN_COM_SEQ_11__patt_gen_seq_11(reg_value) extract_field((reg_value),15,0) 4922 #define exc_PATT_GEN_COM_SEQ_12__patt_gen_seq_12(reg_value) extract_field((reg_value),15,0) 4923 #define exc_PATT_GEN_COM_SEQ_13__patt_gen_seq_13(reg_value) extract_field((reg_value),15,0) 4924 #define exc_PATT_GEN_COM_SEQ_14__patt_gen_seq_14(reg_value) extract_field((reg_value),15,0) 4925 #define ex_PCIE_BLK0_EXT_CTRL1__rst_sw(reg_value) extract_field((reg_value),15,15) 4926 #define ex_PCIE_BLK0_EXT_CTRL1__rst_sw_UC(reg_value) extract_field((reg_value),14,14) 4927 #define ex_PCIE_BLK0_EXT_CTRL1__rst_sw_MDIO(reg_value) extract_field((reg_value),13,13) 4928 #define ex_PCIE_BLK0_EXT_CTRL1__pwrdwn_sw_10g(reg_value) extract_field((reg_value),11,11) 4929 #define ex_PCIE_BLK0_EXT_CTRL1__pll_tca_master_frc(reg_value) extract_field((reg_value),3,3) 4930 #define ex_PCIE_BLK0_EXT_CTRL1__pll_tca_master_frc_val(reg_value) extract_field((reg_value),2,2) 4931 #define ex_PCIE_BLK0_EXT_CTRL1__mdio_rx_hiz_disable(reg_value) extract_field((reg_value),1,1) 4932 #define ex_PCIE_BLK0_EXT_CTRL1__mdio_ucclk_sel(reg_value) extract_field((reg_value),0,0) 4933 #define ex_PCIE_BLK0_EXT_RXSIGDET__rxsigdet(reg_value) extract_field((reg_value),15,0) 4934 #define ex_PCIE_BLK0_EXT_LNSTATUS__ln_status(reg_value) extract_field((reg_value),15,0) 4935 #define ex_PCIE_BLK0_EXT_LNSTATUS2__ln_status2(reg_value) extract_field((reg_value),15,0) 4936 #define ex_PCIE_BLK0_EXT_MDIO_CTRL0__mdio_ser_SAM_ovrd(reg_value) extract_field((reg_value),0,0) 4937 #define ex_PCIE_BLK0_EXT_RATE_SEL_STAT__PllRangeHolding_status(reg_value) extract_field((reg_value),15,9) 4938 #define ex_PCIE_BLK0_EXT_RATE_SEL_STAT__PllRangeHolding_G3_status(reg_value) extract_field((reg_value),8,2) 4939 #define ex_PCIE_BLK0_EXT_RATE_SEL_STAT__rate_sel_status(reg_value) extract_field((reg_value),1,0) 4940 #define ex_PCIE_BLK1_EXT_CONTROL__pgen_en(reg_value) extract_field((reg_value),15,15) 4941 #define ex_PCIE_BLK1_EXT_CONTROL__pcmp_en(reg_value) extract_field((reg_value),14,14) 4942 #define ex_PCIE_BLK1_EXT_CONTROL__start_sequencer(reg_value) extract_field((reg_value),13,13) 4943 #define ex_PCIE_BLK1_EXT_CONTROL__reset_anlg_r(reg_value) extract_field((reg_value),12,12) 4944 #define ex_PCIE_BLK1_EXT_CONTROL__pll_bypass_r(reg_value) extract_field((reg_value),7,7) 4945 #define ex_PCIE_BLK1_EXT_CONTROL__mdio_iddq_ovrd_select(reg_value) extract_field((reg_value),6,6) 4946 #define ex_PCIE_BLK1_EXT_CONTROL__mdio_iddq_ovrd_value(reg_value) extract_field((reg_value),5,5) 4947 #define ex_PCIE_BLK1_EXT_CONTROL__mdio_cont_en(reg_value) extract_field((reg_value),4,4) 4948 #define ex_PCIE_BLK1_EXT_CONTROL__cdet_en10g(reg_value) extract_field((reg_value),3,3) 4949 #define ex_PCIE_BLK1_EXT_CONTROL__eden10g(reg_value) extract_field((reg_value),2,2) 4950 #define ex_PCIE_BLK1_EXT_CONTROL__dsc_reset_enable(reg_value) extract_field((reg_value),0,0) 4951 #define ex_PCIE_BLK1_EXT_STATUS__status(reg_value) extract_field((reg_value),15,0) 4952 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__enable_uC_freeze(reg_value) extract_field((reg_value),7,7) 4953 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__deassert_ResetUc(reg_value) extract_field((reg_value),6,6) 4954 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__L1PLLPowerdown_sel(reg_value) extract_field((reg_value),5,5) 4955 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__L1PLLPowerdown_mdio(reg_value) extract_field((reg_value),4,4) 4956 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__BlockRealignOverride(reg_value) extract_field((reg_value),3,3) 4957 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__mdio_G3_BlockRealign(reg_value) extract_field((reg_value),2,2) 4958 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__tx_G3_fts_SDS(reg_value) extract_field((reg_value),1,1) 4959 #define ex_PCIE_BLK1_EXT_MISCCONTROL1__tx_G3_fts_no_EIEOS(reg_value) extract_field((reg_value),0,0) 4960 #define ex_PCIE_BLK1_EXT_STATUS_REG2__status2(reg_value) extract_field((reg_value),15,0) 4961 #define ex_PCIE_BLK1_EXT_GPIO_CTRL0__gpio_sel(reg_value) extract_field((reg_value),8,0) 4962 #define ex_PCIE_BLK1_EXT_GPIO_STATUS0__mdio_gpio_sts(reg_value) extract_field((reg_value),15,0) 4963 #define ex_PCIE_BLK1_EXT_DBG_CTRL0__dbg_lane_sel3(reg_value) extract_field((reg_value),15,12) 4964 #define ex_PCIE_BLK1_EXT_DBG_CTRL0__dbg_lane_sel2(reg_value) extract_field((reg_value),11,8) 4965 #define ex_PCIE_BLK1_EXT_DBG_CTRL0__dbg_lane_sel1(reg_value) extract_field((reg_value),7,4) 4966 #define ex_PCIE_BLK1_EXT_DBG_CTRL0__dbg_lane_sel0(reg_value) extract_field((reg_value),3,0) 4967 #define ex_PCIE_BLK1_EXT_DBG_CTRL1__dbg_lane_sel7(reg_value) extract_field((reg_value),15,12) 4968 #define ex_PCIE_BLK1_EXT_DBG_CTRL1__dbg_lane_sel6(reg_value) extract_field((reg_value),11,8) 4969 #define ex_PCIE_BLK1_EXT_DBG_CTRL1__dbg_lane_sel5(reg_value) extract_field((reg_value),7,4) 4970 #define ex_PCIE_BLK1_EXT_DBG_CTRL1__dbg_lane_sel4(reg_value) extract_field((reg_value),3,0) 4971 #define ex_PCIE_BLK1_EXT_DBG_CTRL2__dbg_lane_sel11(reg_value) extract_field((reg_value),15,12) 4972 #define ex_PCIE_BLK1_EXT_DBG_CTRL2__dbg_lane_sel10(reg_value) extract_field((reg_value),11,8) 4973 #define ex_PCIE_BLK1_EXT_DBG_CTRL2__dbg_lane_sel9(reg_value) extract_field((reg_value),7,4) 4974 #define ex_PCIE_BLK1_EXT_DBG_CTRL2__dbg_lane_sel8(reg_value) extract_field((reg_value),3,0) 4975 #define ex_PCIE_BLK1_EXT_DBG_CTRL3__dbg_lane_sel15(reg_value) extract_field((reg_value),15,12) 4976 #define ex_PCIE_BLK1_EXT_DBG_CTRL3__dbg_lane_sel14(reg_value) extract_field((reg_value),11,8) 4977 #define ex_PCIE_BLK1_EXT_DBG_CTRL3__dbg_lane_sel13(reg_value) extract_field((reg_value),7,4) 4978 #define ex_PCIE_BLK1_EXT_DBG_CTRL3__dbg_lane_sel12(reg_value) extract_field((reg_value),3,0) 4979 #define ex_PCIE_BLK1_EXT_DBG_CTRL4__dbg_info_sel3(reg_value) extract_field((reg_value),15,12) 4980 #define ex_PCIE_BLK1_EXT_DBG_CTRL4__dbg_info_sel2(reg_value) extract_field((reg_value),11,8) 4981 #define ex_PCIE_BLK1_EXT_DBG_CTRL4__dbg_info_sel1(reg_value) extract_field((reg_value),7,4) 4982 #define ex_PCIE_BLK1_EXT_DBG_CTRL4__dbg_info_sel0(reg_value) extract_field((reg_value),3,0) 4983 #define ex_PCIE_BLK1_EXT_DBG_CTRL5__dbg_info_sel7(reg_value) extract_field((reg_value),15,12) 4984 #define ex_PCIE_BLK1_EXT_DBG_CTRL5__dbg_info_sel6(reg_value) extract_field((reg_value),11,8) 4985 #define ex_PCIE_BLK1_EXT_DBG_CTRL5__dbg_info_sel5(reg_value) extract_field((reg_value),7,4) 4986 #define ex_PCIE_BLK1_EXT_DBG_CTRL5__dbg_info_sel4(reg_value) extract_field((reg_value),3,0) 4987 #define ex_PCIE_BLK1_EXT_DBG_CTRL6__dbg_info_sel11(reg_value) extract_field((reg_value),15,12) 4988 #define ex_PCIE_BLK1_EXT_DBG_CTRL6__dbg_info_sel10(reg_value) extract_field((reg_value),11,8) 4989 #define ex_PCIE_BLK1_EXT_DBG_CTRL6__dbg_info_sel9(reg_value) extract_field((reg_value),7,4) 4990 #define ex_PCIE_BLK1_EXT_DBG_CTRL6__dbg_info_sel8(reg_value) extract_field((reg_value),3,0) 4991 #define ex_PCIE_BLK1_EXT_DBG_CTRL7__dbg_info_sel15(reg_value) extract_field((reg_value),15,12) 4992 #define ex_PCIE_BLK1_EXT_DBG_CTRL7__dbg_info_sel14(reg_value) extract_field((reg_value),11,8) 4993 #define ex_PCIE_BLK1_EXT_DBG_CTRL7__dbg_info_sel13(reg_value) extract_field((reg_value),7,4) 4994 #define ex_PCIE_BLK1_EXT_DBG_CTRL7__dbg_info_sel12(reg_value) extract_field((reg_value),3,0) 4995 #define ex_PCIE_BLK1_EXT_DBG_CTRL8__dbg_misc_tmux_sel(reg_value) extract_field((reg_value),1,1) 4996 #define ex_PCIE_BLK1_EXT_DBG_CTRL8__dbg_data_ena(reg_value) extract_field((reg_value),0,0) 4997 #define ex_PCIE_BLK2_EXT_LFCKCNT__lfckcnt(reg_value) extract_field((reg_value),15,0) 4998 #define ex_PCIE_BLK2_EXT_PWRMGMT0__mdio_LTTSM_NoVoltIsland(reg_value) extract_field((reg_value),15,8) 4999 #define ex_PCIE_BLK2_EXT_PWRMGMT0__mdio_LTTSM_L23Ready(reg_value) extract_field((reg_value),7,0) 5000 #define ex_PCIE_BLK2_EXT_PWRMGMT1__mdio_LTTSM_FwPwrDn(reg_value) extract_field((reg_value),15,8) 5001 #define ex_PCIE_BLK2_EXT_PWRMGMT1__mdio_LTTSM_LinkPwrDn(reg_value) extract_field((reg_value),7,0) 5002 #define ex_PCIE_BLK2_EXT_PWRMGMT2__mdio_LTTSM_L1NoClkReqPllPwrDn(reg_value) extract_field((reg_value),15,8) 5003 #define ex_PCIE_BLK2_EXT_PWRMGMT2__mdio_LTTSM_L1NoClkReq(reg_value) extract_field((reg_value),7,0) 5004 #define ex_PCIE_BLK2_EXT_PWRMGMT3__mdio_LTTSM_P0(reg_value) extract_field((reg_value),15,8) 5005 #define ex_PCIE_BLK2_EXT_PWRMGMT3__mdio_LTTSM_L1ClkReq(reg_value) extract_field((reg_value),7,0) 5006 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_RefclkSenseBypass(reg_value) extract_field((reg_value),15,15) 5007 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_TxIdleCtrl(reg_value) extract_field((reg_value),14,11) 5008 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_ClkReq_tmp(reg_value) extract_field((reg_value),10,10) 5009 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_ClkReqMdioSel(reg_value) extract_field((reg_value),9,9) 5010 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_AuxClkEnable_tmp(reg_value) extract_field((reg_value),8,8) 5011 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_AuxClkEnableMdioSel(reg_value) extract_field((reg_value),7,7) 5012 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_AuxPowerDownP1PllEnableMdioSel(reg_value) extract_field((reg_value),6,6) 5013 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_LTTSM_L1AnaPwrDnPll(reg_value) extract_field((reg_value),5,3) 5014 #define ex_PCIE_BLK2_EXT_PWRMGMT4__mdio_LTTSM_L1AnaPwrDn(reg_value) extract_field((reg_value),2,0) 5015 #define ex_PCIE_BLK2_EXT_PWRMGMT5__mdio_pwrdn_pll_timer_dfs(reg_value) extract_field((reg_value),15,8) 5016 #define ex_PCIE_BLK2_EXT_PWRMGMT5__mdio_RcPllPd_ovrd(reg_value) extract_field((reg_value),7,7) 5017 #define ex_PCIE_BLK2_EXT_PWRMGMT5__mdio_RcPllPd_val(reg_value) extract_field((reg_value),6,6) 5018 #define ex_PCIE_BLK2_EXT_PWRMGMT5__mdio_tx_cmn_mode_force_P2ClkReqEntry_en(reg_value) extract_field((reg_value),5,5) 5019 #define ex_PCIE_BLK2_EXT_PWRMGMT5__mdio_RefclkSense_onecomp(reg_value) extract_field((reg_value),1,1) 5020 #define ex_PCIE_BLK2_EXT_PWRMGMT5__mdio_RefclkSenseEventClr(reg_value) extract_field((reg_value),0,0) 5021 #define ex_PCIE_BLK2_EXT_PWRMGMT6__mdio_pwrdn_refclk_timer_dfs(reg_value) extract_field((reg_value),15,8) 5022 #define ex_PCIE_BLK2_EXT_PWRMGMT6__mdio_pwr_mgmt_spare_dfs(reg_value) extract_field((reg_value),7,4) 5023 #define ex_PCIE_BLK2_EXT_PWRMGMT6__mdio_pm_P2_Wait4Pclk_tmr(reg_value) extract_field((reg_value),3,0) 5024 #define ex_PCIE_BLK2_EXT_PWRMGMT7__mdio_RefclkSense_M(reg_value) extract_field((reg_value),15,0) 5025 #define ex_PCIE_BLK2_EXT_PWRMGMT8__mdio_RefclkSense_N(reg_value) extract_field((reg_value),15,0) 5026 #define ex_PCIE_BLK2_EXT_REFCLKSENSE_STAT__mdio_RefclkSenseEventCnt(reg_value) extract_field((reg_value),3,0) 5027 #define ex_PCIE_BLK2_EXT_REFCLKSENSE_STAT2__mdio_RefclkSenseCnt(reg_value) extract_field((reg_value),15,0) 5028 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__mdio_byp_pipe_io(reg_value) extract_field((reg_value),15,15) 5029 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__pwrdown_mdio_sel(reg_value) extract_field((reg_value),14,14) 5030 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__tx_idle_mdio_sel(reg_value) extract_field((reg_value),13,13) 5031 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__rloop_pipe_mdio_sel(reg_value) extract_field((reg_value),12,12) 5032 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__gloop_mdio_sel(reg_value) extract_field((reg_value),11,11) 5033 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__tx_comp_mdio_sel(reg_value) extract_field((reg_value),10,10) 5034 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__mdio_RxElectIdleRloopEn(reg_value) extract_field((reg_value),7,7) 5035 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__StandAloneMode_mdio_sel(reg_value) extract_field((reg_value),6,6) 5036 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__PllTuningBypass_mdio_sel(reg_value) extract_field((reg_value),5,5) 5037 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__lfck_rx_sel_mdio_sel(reg_value) extract_field((reg_value),4,4) 5038 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__mdio_DeviceType_sel(reg_value) extract_field((reg_value),3,3) 5039 #define ex_PCIE_BLK3_EXT_GEN2CTRL0__mdio_DeviceType(reg_value) extract_field((reg_value),2,0) 5040 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__spares_pcie3_1(reg_value) extract_field((reg_value),15,10) 5041 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__mdio_pmi_select_sel(reg_value) extract_field((reg_value),9,9) 5042 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__mdio_pmi_select_val(reg_value) extract_field((reg_value),8,8) 5043 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__mdio_RC_refclk_sel(reg_value) extract_field((reg_value),4,4) 5044 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__mdio_RC_refclk_val(reg_value) extract_field((reg_value),3,3) 5045 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__RateSelect_mdio_sel(reg_value) extract_field((reg_value),2,2) 5046 #define ex_PCIE_BLK3_EXT_GEN2CTRL1__mdioRateSelect(reg_value) extract_field((reg_value),1,0) 5047 #define ex_PCIE_BLK3_EXT_GEN2CTRL2__spares_pcie3_2(reg_value) extract_field((reg_value),15,0) 5048 #define ex_PCIE_BLK3_EXT_GEN2CTRL3__mdio_gloop(reg_value) extract_field((reg_value),15,0) 5049 #define ex_PCIE_BLK3_EXT_GEN2CTRL4__rloop1g(reg_value) extract_field((reg_value),15,0) 5050 #define ex_PCIE_BLK3_EXT_GEN2CTRL5__mdio_rloop_pipe(reg_value) extract_field((reg_value),15,0) 5051 #define ex_PCIE_BLK3_EXT_GEN2CTRL6__gen2_ctrl6(reg_value) extract_field((reg_value),15,0) 5052 #define ex_PCIE_BLK3_EXT_GEN2CTRL7__DisablePmRxFastAcq(reg_value) extract_field((reg_value),15,0) 5053 #define ex_PCIE_BLK3_EXT_GEN2CTRL8__mdioRxFastAcqEnable(reg_value) extract_field((reg_value),15,0) 5054 #define ex_PCIE_BLK3_EXT_GEN2CTRL9__mdioRxSeqStart(reg_value) extract_field((reg_value),15,0) 5055 #define ex_PCIE_BLK3_EXT_GEN2CTRL10__mdio_TxElectIdle_r(reg_value) extract_field((reg_value),15,0) 5056 #define ex_PCIE_BLK3_EXT_GEN2CTRL11__mdio_TxComp_r(reg_value) extract_field((reg_value),15,0) 5057 #define ex_PCIE_BLK3_EXT_GEN2CTRL12__mdio_PowerDown_0(reg_value) extract_field((reg_value),15,0) 5058 #define ex_PCIE_BLK3_EXT_GEN2CTRL13__mdio_PowerDown_1(reg_value) extract_field((reg_value),15,0) 5059 #define ex_PCIE_BLK3_EXT_GEN2CTRL14__gen2_ctrl14(reg_value) extract_field((reg_value),15,0) 5060 #define ex_PCIE_BLK4_EXT_LANECTRL0__lane_ctrl0(reg_value) extract_field((reg_value),15,0) 5061 #define ex_PCIE_BLK4_EXT_LANECTRL1__lane_ctrl1(reg_value) extract_field((reg_value),15,0) 5062 #define ex_PCIE_BLK4_EXT_LANECTRL2__eden1g(reg_value) extract_field((reg_value),15,0) 5063 #define ex_PCIE_BLK4_EXT_LANECTRL3__cdet_en1g(reg_value) extract_field((reg_value),15,0) 5064 #define ex_PCIE_BLK4_EXT_LANECTRL4__pwrdwn_rx_r(reg_value) extract_field((reg_value),15,0) 5065 #define ex_PCIE_BLK4_EXT_LANECTRL5__pwrdwn_tx_r(reg_value) extract_field((reg_value),15,0) 5066 #define ex_PCIE_BLK4_EXT_LANECTRL6__pwrdwn_10g_pll_dis(reg_value) extract_field((reg_value),1,1) 5067 #define ex_PCIE_BLK4_EXT_LANECTRL6__pwrdwn_pll_r(reg_value) extract_field((reg_value),0,0) 5068 #define ex_PCIE_BLK4_EXT_LANECTRL7__rst_sw_ln(reg_value) extract_field((reg_value),15,0) 5069 #define ex_PCIE_BLK4_EXT_LANECTRL8__reset_anlg_r_ln(reg_value) extract_field((reg_value),15,0) 5070 #define ex_PCIE_BLK4_EXT_LANECTRL9__mdio_cont_en3(reg_value) extract_field((reg_value),11,11) 5071 #define ex_PCIE_BLK4_EXT_LANECTRL9__TxBeaconData(reg_value) extract_field((reg_value),9,0) 5072 #define ex_PCIE_BLK4_EXT_LANECTRL10__common_clock_fifo_shrink(reg_value) extract_field((reg_value),2,2) 5073 #define ex_PCIE_BLK4_EXT_LANECTRL10__gp_in0_disable(reg_value) extract_field((reg_value),1,1) 5074 #define ex_PCIE_BLK4_EXT_LANECTRL10__enable_mdwr4rst(reg_value) extract_field((reg_value),0,0) 5075 #define ex_PCIE_BLK4_EXT_LANECTRL11__elastic_autorst_en(reg_value) extract_field((reg_value),15,0) 5076 #define ex_PCIE_BLK4_EXT_LANECTRL12__comma_adj_fsm_sel(reg_value) extract_field((reg_value),15,0) 5077 #define ex_PCIE_BLK4_EXT_LANECTRL13__RcvrDetectTimeout(reg_value) extract_field((reg_value),15,0) 5078 #define ex_PCIE_BLK4_EXT_LANECTRL14__lane_ctrl14(reg_value) extract_field((reg_value),15,0) 5079 #define ex_PCIE_BLK5_EXT_LANECTRL15__lane_ctrl15(reg_value) extract_field((reg_value),15,0) 5080 #define ex_PCIE_BLK5_EXT_LANEPRBS0__prbs_en(reg_value) extract_field((reg_value),15,0) 5081 #define ex_PCIE_BLK5_EXT_LANEPRBS1__prbs_inv(reg_value) extract_field((reg_value),15,0) 5082 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order15a(reg_value) extract_field((reg_value),15,15) 5083 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order14a(reg_value) extract_field((reg_value),14,14) 5084 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order13a(reg_value) extract_field((reg_value),13,13) 5085 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order12a(reg_value) extract_field((reg_value),12,12) 5086 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order11a(reg_value) extract_field((reg_value),11,11) 5087 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order10a(reg_value) extract_field((reg_value),10,10) 5088 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order9a(reg_value) extract_field((reg_value),9,9) 5089 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order8a(reg_value) extract_field((reg_value),8,8) 5090 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order7a(reg_value) extract_field((reg_value),7,7) 5091 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order6a(reg_value) extract_field((reg_value),6,6) 5092 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order5a(reg_value) extract_field((reg_value),5,5) 5093 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order4a(reg_value) extract_field((reg_value),4,4) 5094 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order3a(reg_value) extract_field((reg_value),3,3) 5095 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order2a(reg_value) extract_field((reg_value),2,2) 5096 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order1a(reg_value) extract_field((reg_value),1,1) 5097 #define ex_PCIE_BLK5_EXT_LANEPRBS2__prbs_order0a(reg_value) extract_field((reg_value),0,0) 5098 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order7(reg_value) extract_field((reg_value),15,14) 5099 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order6(reg_value) extract_field((reg_value),13,12) 5100 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order5(reg_value) extract_field((reg_value),11,10) 5101 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order4(reg_value) extract_field((reg_value),9,8) 5102 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order3(reg_value) extract_field((reg_value),7,6) 5103 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order2(reg_value) extract_field((reg_value),5,4) 5104 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order1(reg_value) extract_field((reg_value),3,2) 5105 #define ex_PCIE_BLK5_EXT_LANEPRBS3__prbs_order0(reg_value) extract_field((reg_value),1,0) 5106 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order15(reg_value) extract_field((reg_value),15,14) 5107 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order14(reg_value) extract_field((reg_value),13,12) 5108 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order13(reg_value) extract_field((reg_value),11,10) 5109 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order12(reg_value) extract_field((reg_value),9,8) 5110 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order11(reg_value) extract_field((reg_value),7,6) 5111 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order10(reg_value) extract_field((reg_value),5,4) 5112 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order9(reg_value) extract_field((reg_value),3,2) 5113 #define ex_PCIE_BLK5_EXT_LANEPRBS4__prbs_order8(reg_value) extract_field((reg_value),1,0) 5114 #define ex_PCIE_BLK5_EXT_LANETEST0__lfck_sigdet_sel_mdio_sel(reg_value) extract_field((reg_value),15,15) 5115 #define ex_PCIE_BLK5_EXT_LANETEST0__mdio_lfck_sigdet_sel_cnt0(reg_value) extract_field((reg_value),13,13) 5116 #define ex_PCIE_BLK5_EXT_LANETEST0__mdio_lfck_sigdet_sel_refclk(reg_value) extract_field((reg_value),12,12) 5117 #define ex_PCIE_BLK5_EXT_LANETEST0__ext_pwrdn_dis(reg_value) extract_field((reg_value),10,10) 5118 #define ex_PCIE_BLK5_EXT_LANETEST0__pwrdn_safe_dis_tmp(reg_value) extract_field((reg_value),9,9) 5119 #define ex_PCIE_BLK5_EXT_LANETEST0__pwrdn_clks_en(reg_value) extract_field((reg_value),8,8) 5120 #define ex_PCIE_BLK5_EXT_LANETEST0__pll_lock_rstb_r(reg_value) extract_field((reg_value),6,6) 5121 #define ex_PCIE_BLK5_EXT_LANETEST0__lfck_bypass(reg_value) extract_field((reg_value),5,5) 5122 #define ex_PCIE_BLK5_EXT_LANETEST0__rx_snoop_en(reg_value) extract_field((reg_value),4,4) 5123 #define ex_PCIE_BLK5_EXT_LANETEST0__mdio_StandAloneMode(reg_value) extract_field((reg_value),3,3) 5124 #define ex_PCIE_BLK5_EXT_LANETEST0__mdio_PllTuningBypass(reg_value) extract_field((reg_value),2,2) 5125 #define ex_PCIE_BLK5_EXT_LANETEST0__mdio_lfck_rx_sel_cnt0(reg_value) extract_field((reg_value),1,1) 5126 #define ex_PCIE_BLK5_EXT_LANETEST0__mdio_lfck_rx_sel_refclk(reg_value) extract_field((reg_value),0,0) 5127 #define ex_PCIE_BLK5_EXT_LANETEST1__comp_start(reg_value) extract_field((reg_value),15,15) 5128 #define ex_PCIE_BLK5_EXT_LANETEST1__tmux_sel(reg_value) extract_field((reg_value),5,0) 5129 #define ex_PCIE_BLK5_EXT_COMP_DELAY0__comp_delay3_11(reg_value) extract_field((reg_value),15,12) 5130 #define ex_PCIE_BLK5_EXT_COMP_DELAY0__comp_delay2_10(reg_value) extract_field((reg_value),11,8) 5131 #define ex_PCIE_BLK5_EXT_COMP_DELAY0__comp_delay1_9(reg_value) extract_field((reg_value),7,4) 5132 #define ex_PCIE_BLK5_EXT_COMP_DELAY0__comp_delay0_8(reg_value) extract_field((reg_value),3,0) 5133 #define ex_PCIE_BLK5_EXT_COMP_DELAY1__comp_delay7_15(reg_value) extract_field((reg_value),15,12) 5134 #define ex_PCIE_BLK5_EXT_COMP_DELAY1__comp_delay6_14(reg_value) extract_field((reg_value),11,8) 5135 #define ex_PCIE_BLK5_EXT_COMP_DELAY1__comp_delay5_13(reg_value) extract_field((reg_value),7,4) 5136 #define ex_PCIE_BLK5_EXT_COMP_DELAY1__comp_delay4_12(reg_value) extract_field((reg_value),3,0) 5137 #define ex_PCIE_BLK5_EXT_COMP_TYPE__comp_type(reg_value) extract_field((reg_value),15,0) 5138 #define ex_PCIE_BLK5_EXT_COMP_ENABLE__comp_enable(reg_value) extract_field((reg_value),15,0) 5139 #define ex_PCIE_BLK5_EXT_XGXS_FE_TMUX__XGXS_fe_tmux(reg_value) extract_field((reg_value),15,0) 5140 #define ex_PCIE_BLK6_EXT_PMD_CTRL0__pmd_rx_dme_en(reg_value) extract_field((reg_value),15,15) 5141 #define ex_PCIE_BLK6_EXT_PMD_CTRL0__pmd_rx_mode(reg_value) extract_field((reg_value),14,14) 5142 #define ex_PCIE_BLK6_EXT_PMD_CTRL0__pmd_tx_mode(reg_value) extract_field((reg_value),13,12) 5143 #define ex_PCIE_BLK6_EXT_PMD_CTRL0__pmd_osr_mode_gen3(reg_value) extract_field((reg_value),11,8) 5144 #define ex_PCIE_BLK6_EXT_PMD_CTRL0__pmd_osr_mode_gen2(reg_value) extract_field((reg_value),7,4) 5145 #define ex_PCIE_BLK6_EXT_PMD_CTRL0__pmd_osr_mode_gen1(reg_value) extract_field((reg_value),3,0) 5146 #define ex_PCIE_BLK6_EXT_PMD_CTRL1__pcie_pmd_lane_mode(reg_value) extract_field((reg_value),15,0) 5147 #define ex_PCIE_BLK6_EXT_PMD_CTRL2__pcie_pmd_core_mode(reg_value) extract_field((reg_value),15,0) 5148 #define ex_PCIE_BLK6_EXT_ANA_CTRL__mdio_pll_lock_dly(reg_value) extract_field((reg_value),11,11) 5149 #define ex_PCIE_BLK6_EXT_ANA_CTRL__core_config_frc(reg_value) extract_field((reg_value),10,10) 5150 #define ex_PCIE_BLK6_EXT_ANA_CTRL__core_config_frc_val(reg_value) extract_field((reg_value),9,6) 5151 #define ex_PCIE_BLK6_EXT_ANA_CTRL__tca_use_ext_pd(reg_value) extract_field((reg_value),5,5) 5152 #define ex_PCIE_BLK6_EXT_ANA_CTRL__ref_cmos_clk_HZ(reg_value) extract_field((reg_value),4,4) 5153 #define ex_PCIE_BLK6_EXT_ANA_CTRL__refsel_frc(reg_value) extract_field((reg_value),3,3) 5154 #define ex_PCIE_BLK6_EXT_ANA_CTRL__refsel_frc_val(reg_value) extract_field((reg_value),2,0) 5155 #define ex_PCIE_BLK7_EXT_TX_COEFF_LO__tx_coeff_lo(reg_value) extract_field((reg_value),15,0) 5156 #define ex_PCIE_BLK7_EXT_TX_COEFF_HI__tx_coeff_ovrd_ena(reg_value) extract_field((reg_value),15,15) 5157 #define ex_PCIE_BLK7_EXT_TX_COEFF_HI__tx_coeff_hi(reg_value) extract_field((reg_value),5,0) 5158 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_0__rx_clk_repeater_0(reg_value) extract_field((reg_value),15,0) 5159 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_1__rx_clk_repeater_1(reg_value) extract_field((reg_value),15,0) 5160 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_2__rx_clk_repeater_2(reg_value) extract_field((reg_value),15,0) 5161 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_3__rx_clk_repeater_3(reg_value) extract_field((reg_value),15,0) 5162 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_BW__rx_clk_repeater_BW_gen12(reg_value) extract_field((reg_value),1,0) 5163 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_BW__rx_clk_repeater_BW_gen3(reg_value) extract_field((reg_value),3,2) 5164 #define ex_PCIE_BLK7_EXT_RX_CLK_REPEATER_BW__spare_bits(reg_value) extract_field((reg_value),15,4) 5165 #define ex_PCIE_BLK7_EXT_SPARE_CTRL0__spare_ctrl0(reg_value) extract_field((reg_value),15,0) 5166 #define ex_PCIE_BLK7_EXT_SPARE_CTRL1__spare_ctrl1(reg_value) extract_field((reg_value),15,0) 5167 #define ex_PCIE_BLK7_EXT_SPARE_CTRL2__spare_ctrl2(reg_value) extract_field((reg_value),15,0) 5168 #define ex_PCIE_BLK7_EXT_SPARE_CTRL3__spare_ctrl3(reg_value) extract_field((reg_value),15,0) 5169 #define exc_PLL_CAL_COM_CTL_0__cal_th(reg_value) extract_field((reg_value),15,14) 5170 #define exc_PLL_CAL_COM_CTL_0__pll_cal_jump_ena(reg_value) extract_field((reg_value),13,13) 5171 #define exc_PLL_CAL_COM_CTL_0__calib_step_time(reg_value) extract_field((reg_value),12,0) 5172 #define exc_PLL_CAL_COM_CTL_1__freqdet_time(reg_value) extract_field((reg_value),15,0) 5173 #define exc_PLL_CAL_COM_CTL_2__calib_cap_charge_time(reg_value) extract_field((reg_value),11,0) 5174 #define exc_PLL_CAL_COM_CTL_3__ext_state(reg_value) extract_field((reg_value),15,12) 5175 #define exc_PLL_CAL_COM_CTL_3__accel_en(reg_value) extract_field((reg_value),11,11) 5176 #define exc_PLL_CAL_COM_CTL_3__debug_clr(reg_value) extract_field((reg_value),10,10) 5177 #define exc_PLL_CAL_COM_CTL_3__freqdet_time_msb(reg_value) extract_field((reg_value),9,9) 5178 #define exc_PLL_CAL_COM_CTL_3__freqdet_win(reg_value) extract_field((reg_value),7,0) 5179 #define exc_PLL_CAL_COM_CTL_4__halfstep_en(reg_value) extract_field((reg_value),15,15) 5180 #define exc_PLL_CAL_COM_CTL_4__pll_force_cap_pass_en(reg_value) extract_field((reg_value),14,14) 5181 #define exc_PLL_CAL_COM_CTL_4__pll_force_cap_pass(reg_value) extract_field((reg_value),13,13) 5182 #define exc_PLL_CAL_COM_CTL_4__cal_pause_en(reg_value) extract_field((reg_value),12,12) 5183 #define exc_PLL_CAL_COM_CTL_4__cal_pause_rel(reg_value) extract_field((reg_value),11,11) 5184 #define exc_PLL_CAL_COM_CTL_4__cap_delay(reg_value) extract_field((reg_value),10,10) 5185 #define exc_PLL_CAL_COM_CTL_4__calib_start(reg_value) extract_field((reg_value),9,9) 5186 #define exc_PLL_CAL_COM_CTL_4__en_calib_n(reg_value) extract_field((reg_value),8,8) 5187 #define exc_PLL_CAL_COM_CTL_4__ext_range(reg_value) extract_field((reg_value),6,0) 5188 #define exc_PLL_CAL_COM_CTL_5__pll_seq_start(reg_value) extract_field((reg_value),15,15) 5189 #define exc_PLL_CAL_COM_CTL_5__lkdt_pause_en(reg_value) extract_field((reg_value),14,14) 5190 #define exc_PLL_CAL_COM_CTL_5__lkdt_pause_rel(reg_value) extract_field((reg_value),13,13) 5191 #define exc_PLL_CAL_COM_CTL_5__vco_rst_en(reg_value) extract_field((reg_value),12,12) 5192 #define exc_PLL_CAL_COM_CTL_5__autocal_en(reg_value) extract_field((reg_value),8,8) 5193 #define exc_PLL_CAL_COM_CTL_5__autocal_cnt(reg_value) extract_field((reg_value),7,5) 5194 #define exc_PLL_CAL_COM_CTL_5__lkdt_byp(reg_value) extract_field((reg_value),4,4) 5195 #define exc_PLL_CAL_COM_CTL_5__pll_lock_frc_val(reg_value) extract_field((reg_value),3,3) 5196 #define exc_PLL_CAL_COM_CTL_5__pll_lock_frc(reg_value) extract_field((reg_value),2,2) 5197 #define exc_PLL_CAL_COM_CTL_5__pllforce_fdone(reg_value) extract_field((reg_value),1,1) 5198 #define exc_PLL_CAL_COM_CTL_5__pllforce_fdone_en(reg_value) extract_field((reg_value),0,0) 5199 #define exc_PLL_CAL_COM_CTL_6__band_iqbuf_sel(reg_value) extract_field((reg_value),7,7) 5200 #define exc_PLL_CAL_COM_CTL_6__vcorange_sel(reg_value) extract_field((reg_value),6,6) 5201 #define exc_PLL_CAL_COM_CTL_6__vcobufpon_sel(reg_value) extract_field((reg_value),5,5) 5202 #define exc_PLL_CAL_COM_CTL_6__vcopon_sel(reg_value) extract_field((reg_value),3,3) 5203 #define exc_PLL_CAL_COM_CTL_6__pllpon_sel(reg_value) extract_field((reg_value),1,1) 5204 #define exc_PLL_CAL_COM_STS_0__pll_fail_stky(reg_value) extract_field((reg_value),15,15) 5205 #define exc_PLL_CAL_COM_STS_0__cal_state(reg_value) extract_field((reg_value),14,11) 5206 #define exc_PLL_CAL_COM_STS_0__cal_valid(reg_value) extract_field((reg_value),10,10) 5207 #define exc_PLL_CAL_COM_STS_0__pll_lock(reg_value) extract_field((reg_value),9,9) 5208 #define exc_PLL_CAL_COM_STS_0__pll_lock_bar_stky(reg_value) extract_field((reg_value),8,8) 5209 #define exc_PLL_CAL_COM_STS_0__pll_range(reg_value) extract_field((reg_value),6,0) 5210 #define exc_PLL_CAL_COM_STS_1__lkdtref_counter_msb(reg_value) extract_field((reg_value),15,15) 5211 #define exc_PLL_CAL_COM_STS_1__lkdtvco_counter_msb(reg_value) extract_field((reg_value),14,14) 5212 #define exc_PLL_CAL_COM_STS_1__calref_counter(reg_value) extract_field((reg_value),12,0) 5213 #define exc_PLL_CAL_COM_STS_2__band_iqbuf_mux(reg_value) extract_field((reg_value),15,13) 5214 #define exc_PLL_CAL_COM_STS_2__calvco_counter(reg_value) extract_field((reg_value),12,0) 5215 #define exc_PLL_CAL_COM_STS_3__lkdtref_counter(reg_value) extract_field((reg_value),15,0) 5216 #define exc_PLL_CAL_COM_STS_4__lkdtvco_counter(reg_value) extract_field((reg_value),15,0) 5217 #define exc_PLL_CAL_COM_STS_5__vcobufpon_mux(reg_value) extract_field((reg_value),13,10) 5218 #define exc_PLL_CAL_COM_STS_5__calstate_onehot(reg_value) extract_field((reg_value),9,0) 5219 #define exc_PLL_CAL_COM_STS_6__pll_pwrdn_or(reg_value) extract_field((reg_value),15,15) 5220 #define exc_PLL_CAL_COM_STS_6__vco_range_mux(reg_value) extract_field((reg_value),14,8) 5221 #define exc_PLL_CAL_COM_STS_6__vcopon_mux(reg_value) extract_field((reg_value),7,4) 5222 #define exc_PLL_CAL_COM_STS_6__pllpon_mux(reg_value) extract_field((reg_value),3,0) 5223 #define ex_REGISTER_INFO_EXT_INFO__reg_desc(reg_value) extract_field((reg_value),15,0) 5224 #define ex_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_sigdet_pwrdn(reg_value) extract_field((reg_value),1,1) 5225 #define ex_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_rx_s_pwrdn(reg_value) extract_field((reg_value),0,0) 5226 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) 5227 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) 5228 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) 5229 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) 5230 #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) 5231 #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__sigdet_dp_rstb_en(reg_value) extract_field((reg_value),2,2) 5232 #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) 5233 #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_s_rstb(reg_value) extract_field((reg_value),0,0) 5234 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc_val(reg_value) extract_field((reg_value),3,3) 5235 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc(reg_value) extract_field((reg_value),2,2) 5236 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) 5237 #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) 5238 #define ex_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) 5239 #define ex_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS__pmd_lane_mode(reg_value) extract_field((reg_value),15,0) 5240 #define ex_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_rx_reset(reg_value) extract_field((reg_value),1,1) 5241 #define ex_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_rx_pwrdn(reg_value) extract_field((reg_value),0,0) 5242 #define ex_RX_DFE0_EXT_RXSTATUS1__status1(reg_value) extract_field((reg_value),15,0) 5243 #define ex_RX_DFE0_EXT_RXSTATUS2__status_2(reg_value) extract_field((reg_value),15,0) 5244 #define ex_RX_DFE0_EXT_RXSTATUS3__status3(reg_value) extract_field((reg_value),15,0) 5245 #define ex_RX_DFE0_EXT_RXCONTROL1__Status1Sel_SM(reg_value) extract_field((reg_value),15,13) 5246 #define ex_RX_DFE0_EXT_RXCONTROL1__testMuxSelect_SM(reg_value) extract_field((reg_value),11,8) 5247 #define ex_RX_DFE0_EXT_RXCONTROL1__tpctrl_SM0(reg_value) extract_field((reg_value),7,7) 5248 #define ex_RX_DFE0_EXT_RXCONTROL1__tpctrl_SM1(reg_value) extract_field((reg_value),6,4) 5249 #define ex_RX_DFE0_EXT_RXCONTROL1__mdio_rx_G3_RxDataValidRealign(reg_value) extract_field((reg_value),3,3) 5250 #define ex_RX_DFE0_EXT_RXCONTROL1__Status2Sel_SM(reg_value) extract_field((reg_value),2,0) 5251 #define ex_RX_DFE0_EXT_RXCONTROL2__forceDecodeOn_SM(reg_value) extract_field((reg_value),15,15) 5252 #define ex_RX_DFE0_EXT_RXCONTROL2__err_max_cnt_sel_SM(reg_value) extract_field((reg_value),10,8) 5253 #define ex_RX_DFE0_EXT_RXCONTROL2__clear_err_cnt_SM(reg_value) extract_field((reg_value),7,7) 5254 #define ex_RX_DFE0_EXT_RXCONTROL2__auto_clear_err_cnt_SM(reg_value) extract_field((reg_value),6,6) 5255 #define ex_RX_DFE0_EXT_RXCONTROL2__mdio_ckcmp_mdio_rst(reg_value) extract_field((reg_value),3,3) 5256 #define ex_RX_DFE0_EXT_RXCONTROL2__mdio_ckcmp_afrst_ptr_err_en(reg_value) extract_field((reg_value),2,2) 5257 #define ex_RX_DFE0_EXT_RXCONTROL2__mdio_ckcmp_afrst_phaseptr_err_en(reg_value) extract_field((reg_value),1,1) 5258 #define ex_RX_DFE0_EXT_RXCONTROL2__mdio_ckcmp_phase_only_en_SM(reg_value) extract_field((reg_value),0,0) 5259 #define ex_RX_DFE0_EXT_RXCONTROL3__prbs_seed_ld_SM(reg_value) extract_field((reg_value),15,15) 5260 #define ex_RX_DFE0_EXT_RXCONTROL3__packet_count_en_SM(reg_value) extract_field((reg_value),14,14) 5261 #define ex_RX_DFE0_EXT_RXCONTROL3__RxErrDisparity_dis_SM(reg_value) extract_field((reg_value),13,13) 5262 #define ex_RX_DFE0_EXT_RXCONTROL3__prbs_clr_dis_r(reg_value) extract_field((reg_value),12,12) 5263 #define ex_RX_DFE0_EXT_RXCONTROL3__rxd_dec_sel_r(reg_value) extract_field((reg_value),11,11) 5264 #define ex_RX_DFE0_EXT_RXCONTROL3__cgbad_tst_SM(reg_value) extract_field((reg_value),10,10) 5265 #define ex_RX_DFE0_EXT_RXCONTROL3__Emon_en_r(reg_value) extract_field((reg_value),9,9) 5266 #define ex_RX_DFE0_EXT_RXCONTROL3__prbs_en_r(reg_value) extract_field((reg_value),8,8) 5267 #define ex_RX_DFE0_EXT_RXCONTROL3__cgbad_en_SM(reg_value) extract_field((reg_value),7,7) 5268 #define ex_RX_DFE0_EXT_RXCONTROL3__fpat_md_SM(reg_value) extract_field((reg_value),6,6) 5269 #define ex_RX_DFE0_EXT_RXCONTROL3__useRxSeqDone_SM(reg_value) extract_field((reg_value),5,5) 5270 #define ex_RX_DFE0_EXT_RXCONTROL3__useSigdet_SM(reg_value) extract_field((reg_value),4,4) 5271 #define ex_RX_DFE0_EXT_RXCONTROL3__commonClockMode_force_SM(reg_value) extract_field((reg_value),1,1) 5272 #define ex_RX_DFE0_EXT_RXCONTROL3__commonClockMode_force_value(reg_value) extract_field((reg_value),0,0) 5273 #define ex_RX_DFE0_EXT_RXCONTROL4__prbs_L0s_SM(reg_value) extract_field((reg_value),15,15) 5274 #define ex_RX_DFE0_EXT_RXCONTROL4__comma_mask_force_r(reg_value) extract_field((reg_value),14,14) 5275 #define ex_RX_DFE0_EXT_RXCONTROL4__comma_mask_r(reg_value) extract_field((reg_value),13,13) 5276 #define ex_RX_DFE0_EXT_RXCONTROL4__statMuxRegDis(reg_value) extract_field((reg_value),12,12) 5277 #define ex_RX_DFE0_EXT_RXCONTROL4__sync_status_force_r_SM(reg_value) extract_field((reg_value),11,11) 5278 #define ex_RX_DFE0_EXT_RXCONTROL4__sync_status_force_r(reg_value) extract_field((reg_value),10,10) 5279 #define ex_RX_DFE0_EXT_RXCONTROL4__comma_adj_en_force_ext_SM(reg_value) extract_field((reg_value),9,9) 5280 #define ex_RX_DFE0_EXT_RXCONTROL4__comma_adj_en_force_sync_SM(reg_value) extract_field((reg_value),8,8) 5281 #define ex_RX_DFE0_EXT_RXCONTROL4__comma_adj_en_force_r_SM(reg_value) extract_field((reg_value),7,7) 5282 #define ex_RX_DFE0_EXT_RXCONTROL4__comma_adj_en_r(reg_value) extract_field((reg_value),6,6) 5283 #define ex_RX_DFE0_EXT_RXCONTROL4__link_en_force_SM(reg_value) extract_field((reg_value),5,5) 5284 #define ex_RX_DFE0_EXT_RXCONTROL4__link_en_r(reg_value) extract_field((reg_value),4,4) 5285 #define ex_RX_DFE0_EXT_RXCONTROL4__rx_polarity_force_SM(reg_value) extract_field((reg_value),3,3) 5286 #define ex_RX_DFE0_EXT_RXCONTROL4__rx_polarity_r(reg_value) extract_field((reg_value),2,2) 5287 #define ex_RX_DFE0_EXT_RXCONTROL4__rxd1g_dec_dis_SM(reg_value) extract_field((reg_value),0,0) 5288 #define ex_RX_DFE0_EXT_RXCONTROL5__mdio_tcSelect(reg_value) extract_field((reg_value),15,8) 5289 #define ex_RX_DFE0_EXT_RXCONTROL5__ana_rx_mdio_sel_fts_L0S(reg_value) extract_field((reg_value),7,7) 5290 #define ex_RX_DFE0_EXT_RXCONTROL5__mdio_DisableOvUnFlow(reg_value) extract_field((reg_value),6,6) 5291 #define ex_RX_DFE0_EXT_RXCONTROL5__mdio_rx_G3_BlockStatusDis(reg_value) extract_field((reg_value),5,5) 5292 #define ex_RX_DFE0_EXT_RXCONTROL6__ana_rx_mdio_sel_com_num(reg_value) extract_field((reg_value),15,14) 5293 #define ex_RX_DFE0_EXT_RXCONTROL6__ckcmp_event_clr_dis(reg_value) extract_field((reg_value),8,8) 5294 #define ex_RX_DFE0_EXT_RXCONTROL6__ckcmp_wr_event_sel(reg_value) extract_field((reg_value),7,4) 5295 #define ex_RX_DFE0_EXT_RXCONTROL6__ckcmp_rd_event_sel(reg_value) extract_field((reg_value),3,0) 5296 #define ex_RX_DFE2_EXT_CONTROL1__rg_gbox_sw_rst(reg_value) extract_field((reg_value),13,13) 5297 #define ex_RX_DFE2_EXT_CONTROL1__rx_gbox_afrst_en(reg_value) extract_field((reg_value),12,12) 5298 #define ex_RX_DFE2_EXT_CONTROL1__lsm_sh_invalid_cnt(reg_value) extract_field((reg_value),11,9) 5299 #define ex_RX_DFE2_EXT_CONTROL1__lsm_tm_clk_en(reg_value) extract_field((reg_value),8,8) 5300 #define ex_RX_DFE2_EXT_CONTROL1__lsm_tm_sel(reg_value) extract_field((reg_value),7,4) 5301 #define ex_RX_DFE2_EXT_CONTROL1__lsm_sreg_field_sel(reg_value) extract_field((reg_value),3,2) 5302 #define ex_RX_DFE2_EXT_CONTROL1__lsm_afrst_en(reg_value) extract_field((reg_value),1,1) 5303 #define ex_RX_DFE2_EXT_CONTROL1__lsm_sw_frst(reg_value) extract_field((reg_value),0,0) 5304 #define ex_RX_DFE2_EXT_STATUS1__lsm_status(reg_value) extract_field((reg_value),15,0) 5305 #define ex_RX_DFE2_EXT_STATUS2__rx_gbox_afrst(reg_value) extract_field((reg_value),2,2) 5306 #define ex_RX_DFE2_EXT_STATUS2__rx_gbox_unflow(reg_value) extract_field((reg_value),1,1) 5307 #define ex_RX_DFE2_EXT_STATUS2__rx_gbox_ovflow(reg_value) extract_field((reg_value),0,0) 5308 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) 5309 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 5310 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__rx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 5311 #define ex_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL__rx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) 5312 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 5313 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 5314 #define ex_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 5315 #define ex_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 5316 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS__rx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 5317 #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL__rx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 5318 #define ex_RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL__rx_multicast_mask_control(reg_value) extract_field((reg_value),0,0) 5319 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_multicast_mask_control_status(reg_value) extract_field((reg_value),4,4) 5320 #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_osr_mode(reg_value) extract_field((reg_value),3,0) 5321 #define ex_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__rx_osr_mode_pin(reg_value) extract_field((reg_value),3,0) 5322 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc(reg_value) extract_field((reg_value),15,15) 5323 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 5324 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 5325 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL__ln_s_rstb(reg_value) extract_field((reg_value),0,0) 5326 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 5327 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 5328 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 5329 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 5330 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS__lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 5331 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL__lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 5332 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL__multicast_mask_control(reg_value) extract_field((reg_value),0,0) 5333 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK__multicast_mask_control_status(reg_value) extract_field((reg_value),4,4) 5334 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK__osr_mode(reg_value) extract_field((reg_value),3,0) 5335 #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__osr_mode_pin(reg_value) extract_field((reg_value),3,0) 5336 #define ex_SIGDET_CTRL_3__rg_sigdet_tsc_sel(reg_value) extract_field((reg_value),15,15) 5337 #define ex_SIGDET_CTRL_3__rg_sigdet_frc(reg_value) extract_field((reg_value),14,14) 5338 #define ex_SIGDET_CTRL_3__rg_sigdet_frc_val(reg_value) extract_field((reg_value),13,13) 5339 #define ex_SIGDET_CTRL_3__rg_rxinfeidledis(reg_value) extract_field((reg_value),12,12) 5340 #define ex_SIGDET_CTRL_3__rg_rxl0sl1failure_dis(reg_value) extract_field((reg_value),11,11) 5341 #define ex_SIGDET_CTRL_3__rg_rx_afe_pwrdn_bypass(reg_value) extract_field((reg_value),10,10) 5342 #define ex_SIGDET_CTRL_3__rg_rxl0sl1failure_cnt(reg_value) extract_field((reg_value),9,0) 5343 #define ex_SIGDET_CTRL_4__rg_sigdet_plllock_tmr(reg_value) extract_field((reg_value),15,0) 5344 #define ex_SIGDET_CTRL_5__rg_sigdet_eieos_tmr(reg_value) extract_field((reg_value),15,6) 5345 #define ex_SIGDET_CTRL_5__rg_sigdet_wait_tmr(reg_value) extract_field((reg_value),5,0) 5346 #define ex_SIGDET_CTRL_6__rg_sigdet_tggl_cnt_clr(reg_value) extract_field((reg_value),15,15) 5347 #define ex_SIGDET_CTRL_6__rg_sigdet_filter_sel_gen1(reg_value) extract_field((reg_value),14,14) 5348 #define ex_SIGDET_CTRL_6__rg_sigdet_filter_sel_gen2(reg_value) extract_field((reg_value),13,13) 5349 #define ex_SIGDET_CTRL_6__rg_sigdet_filter_sel_gen3(reg_value) extract_field((reg_value),12,12) 5350 #define ex_SIGDET_CTRL_6__rg_sigdet_sm_sel(reg_value) extract_field((reg_value),11,11) 5351 #define ex_SIGDET_CTRL_6__rg_sigdet_sm_rst(reg_value) extract_field((reg_value),10,10) 5352 #define ex_SIGDET_CTRL_6__rg_eieos_det_bypass(reg_value) extract_field((reg_value),9,9) 5353 #define ex_SIGDET_CTRL_6__rg_eieos_detect_cnt(reg_value) extract_field((reg_value),8,5) 5354 #define ex_SIGDET_CTRL_6__rg_eios_det_bypass(reg_value) extract_field((reg_value),4,4) 5355 #define ex_SIGDET_CTRL_6__rg_eios_detect_sel(reg_value) extract_field((reg_value),3,3) 5356 #define ex_SIGDET_CTRL_6__rg_eios_detect_cnt(reg_value) extract_field((reg_value),2,0) 5357 #define ex_SIGDET_CTRL_7__rg_sigdet_cnt_src_sel(reg_value) extract_field((reg_value),15,14) 5358 #define ex_SIGDET_CTRL_7__rg_sigdet_raw_qlfy_len_refclk(reg_value) extract_field((reg_value),13,12) 5359 #define ex_SIGDET_CTRL_7__rg_sigdet_filter_len_refclk_gen1(reg_value) extract_field((reg_value),11,8) 5360 #define ex_SIGDET_CTRL_7__rg_sigdet_filter_len_refclk_gen2(reg_value) extract_field((reg_value),7,4) 5361 #define ex_SIGDET_CTRL_7__rg_sigdet_filter_len_refclk_gen3(reg_value) extract_field((reg_value),3,0) 5362 #define ex_SIGDET_CTRL_8__rg_sigdet_raw_qlfy_len_auxclk(reg_value) extract_field((reg_value),13,12) 5363 #define ex_SIGDET_CTRL_8__rg_sigdet_filter_len_auxclk_gen1(reg_value) extract_field((reg_value),11,8) 5364 #define ex_SIGDET_CTRL_8__rg_sigdet_filter_len_auxclk_gen2(reg_value) extract_field((reg_value),7,4) 5365 #define ex_SIGDET_CTRL_8__rg_sigdet_filter_len_auxclk_gen3(reg_value) extract_field((reg_value),3,0) 5366 #define ex_SIGDET_CTRL_9__rg_rloop_sigdet_sm_sel(reg_value) extract_field((reg_value),15,15) 5367 #define ex_SIGDET_CTRL_9__rg_sigdet_thresh_gen2(reg_value) extract_field((reg_value),14,10) 5368 #define ex_SIGDET_CTRL_9__rg_sigdet_thresh_gen3_hi(reg_value) extract_field((reg_value),9,5) 5369 #define ex_SIGDET_CTRL_9__rg_sigdet_thresh_gen3_lo(reg_value) extract_field((reg_value),4,0) 5370 #define ex_SIGDET_CTRL_10__rg_sigdet_deassert_tmr(reg_value) extract_field((reg_value),5,0) 5371 #define ex_SIGDET_CTRL_10__rg_sigdet_deassert_tmr_sel(reg_value) extract_field((reg_value),6,6) 5372 #define ex_SIGDET_CTRL_10__rg_sigdet_thresh_gen1(reg_value) extract_field((reg_value),11,7) 5373 #define ex_SIGDET_CTRL_10__spares_sigdet(reg_value) extract_field((reg_value),15,12) 5374 #define ex_SIGDET_SIGDET_STAT_0__afe_sigdet_thresh_1(reg_value) extract_field((reg_value),12,8) 5375 #define ex_SIGDET_SIGDET_STAT_0__rx_sigdet_mac(reg_value) extract_field((reg_value),2,2) 5376 #define ex_SIGDET_SIGDET_STAT_0__rx_sigdet_dsc(reg_value) extract_field((reg_value),1,1) 5377 #define ex_SIGDET_SIGDET_STAT_0__afe_sigdet_raw(reg_value) extract_field((reg_value),0,0) 5378 #define ex_SIGDET_SIGDET_STAT_1__rg_sigdet_tggl_cnt(reg_value) extract_field((reg_value),15,0) 5379 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_burst_err_cnt_en(reg_value) extract_field((reg_value),15,15) 5380 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_clk_en_frc_on(reg_value) extract_field((reg_value),11,11) 5381 #define ex_TLB_RX_PRBS_CHK_CONFIG__trnsum_error_count_en(reg_value) extract_field((reg_value),10,10) 5382 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_err_cnt_burst_mode(reg_value) extract_field((reg_value),9,9) 5383 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_en_auto_mode(reg_value) extract_field((reg_value),7,7) 5384 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode(reg_value) extract_field((reg_value),6,5) 5385 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_inv(reg_value) extract_field((reg_value),4,4) 5386 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode_sel(reg_value) extract_field((reg_value),3,1) 5387 #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_en(reg_value) extract_field((reg_value),0,0) 5388 #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__prbs_chk_lock_cnt(reg_value) extract_field((reg_value),4,0) 5389 #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__prbs_chk_ool_cnt(reg_value) extract_field((reg_value),12,8) 5390 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_bias_en(reg_value) extract_field((reg_value),3,3) 5391 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_flt_bypass(reg_value) extract_field((reg_value),2,2) 5392 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) 5393 #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_en(reg_value) extract_field((reg_value),0,0) 5394 #define ex_TLB_RX_TLB_RX_MISC_CONFIG__dbg_mask_dig_lpbk_en(reg_value) extract_field((reg_value),2,2) 5395 #define ex_TLB_RX_TLB_RX_MISC_CONFIG__rx_aggregator_bypass_en(reg_value) extract_field((reg_value),1,1) 5396 #define ex_TLB_RX_TLB_RX_MISC_CONFIG__rx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) 5397 #define ex_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timeout(reg_value) extract_field((reg_value),12,8) 5398 #define ex_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timer_mode(reg_value) extract_field((reg_value),1,0) 5399 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__dig_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) 5400 #define ex_TLB_RX_DIG_LPBK_PD_STATUS__dig_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) 5401 #define ex_TLB_RX_PRBS_CHK_LOCK_STATUS__prbs_chk_err_cnt_no_clr(reg_value) extract_field((reg_value),15,1) 5402 #define ex_TLB_RX_PRBS_CHK_LOCK_STATUS__prbs_chk_lock(reg_value) extract_field((reg_value),0,0) 5403 #define ex_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_lock_lost_lh(reg_value) extract_field((reg_value),15,15) 5404 #define ex_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_err_cnt_msb(reg_value) extract_field((reg_value),14,0) 5405 #define ex_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS__prbs_chk_err_cnt_lsb(reg_value) extract_field((reg_value),15,0) 5406 #define ex_TLB_RX_PMD_RX_LOCK_STATUS__pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 5407 #define ex_TLB_RX_PMD_RX_LOCK_STATUS__pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 5408 #define ex_TLB_RX_DBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 5409 #define ex_TLB_RX_DBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 5410 #define ex_TLB_RX_UC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) 5411 #define ex_TLB_RX_UC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) 5412 #define ex_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS__prbs_chk_burst_err_cnt(reg_value) extract_field((reg_value),9,0) 5413 #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_start_pos(reg_value) extract_field((reg_value),15,12) 5414 #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_stop_pos(reg_value) extract_field((reg_value),11,8) 5415 #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_en(reg_value) extract_field((reg_value),0,0) 5416 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_err_ins(reg_value) extract_field((reg_value),5,5) 5417 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_inv(reg_value) extract_field((reg_value),4,4) 5418 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_mode_sel(reg_value) extract_field((reg_value),3,1) 5419 #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_en(reg_value) extract_field((reg_value),0,0) 5420 #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_pd_frc_on(reg_value) extract_field((reg_value),2,2) 5421 #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) 5422 #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_en(reg_value) extract_field((reg_value),0,0) 5423 #define ex_TLB_TX_TLB_TX_MISC_CONFIG__tx_mux_sel_order(reg_value) extract_field((reg_value),2,2) 5424 #define ex_TLB_TX_TLB_TX_MISC_CONFIG__tx_pcs_native_ana_frmt_en(reg_value) extract_field((reg_value),1,1) 5425 #define ex_TLB_TX_TLB_TX_MISC_CONFIG__tx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) 5426 #define ex_TLB_TX_RMT_LPBK_PD_STATUS__rmt_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) 5427 #define ex_TLB_TX_RMT_LPBK_PD_STATUS__rmt_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) 5428 #define ex_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_tx_reset_deassert(reg_value) extract_field((reg_value),15,15) 5429 #define ex_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_tx_s_pwrdn(reg_value) extract_field((reg_value),0,0) 5430 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) 5431 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) 5432 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) 5433 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) 5434 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) 5435 #define ex_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) 5436 #define ex_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_s_rstb(reg_value) extract_field((reg_value),0,0) 5437 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_txclk_reset_frc_val(reg_value) extract_field((reg_value),5,5) 5438 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_txclk_reset_frc(reg_value) extract_field((reg_value),4,4) 5439 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc_val(reg_value) extract_field((reg_value),3,3) 5440 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc(reg_value) extract_field((reg_value),2,2) 5441 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) 5442 #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) 5443 #define ex_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) 5444 #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_txclk_reset(reg_value) extract_field((reg_value),2,2) 5445 #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_tx_reset(reg_value) extract_field((reg_value),1,1) 5446 #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_tx_pwrdn(reg_value) extract_field((reg_value),0,0) 5447 #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL__tx_pi_loop_filter_stable(reg_value) extract_field((reg_value),0,0) 5448 #define ex_TX_COEFF_MAIN_MAIN_EXTENT_CTRL0__fir_main_extent_0(reg_value) extract_field((reg_value),14,0) 5449 #define ex_TX_COEFF_MAIN_MAIN_EXTENT_CTRL1__fir_main_extent_1(reg_value) extract_field((reg_value),14,0) 5450 #define ex_TX_COEFF_MAIN_MAIN_EXTENT_CTRL2__fir_main_extent_2(reg_value) extract_field((reg_value),14,0) 5451 #define ex_TX_COEFF_MAIN_MAIN_EXTENT_CTRL3__fir_main_extent_3(reg_value) extract_field((reg_value),14,0) 5452 #define ex_TX_COEFF_MAIN_MAIN_EXTENT_CTRL4__fir_main_extent_4(reg_value) extract_field((reg_value),14,0) 5453 #define ex_TX_COEFF_MAIN_MAIN_EXTENT_CTRL5__fir_main_extent_5(reg_value) extract_field((reg_value),14,0) 5454 #define ex_TX_COEFF_PM_PRE_CTRL0__fir_pre_0(reg_value) extract_field((reg_value),5,0) 5455 #define ex_TX_COEFF_PM_PRE_CTRL0__fir_pre_1(reg_value) extract_field((reg_value),11,6) 5456 #define ex_TX_COEFF_PM_PRE_CTRL1__fir_pre_2(reg_value) extract_field((reg_value),5,0) 5457 #define ex_TX_COEFF_PM_PRE_CTRL1__fir_pre_3(reg_value) extract_field((reg_value),11,6) 5458 #define ex_TX_COEFF_PM_PRE_CTRL2__fir_pre_4(reg_value) extract_field((reg_value),5,0) 5459 #define ex_TX_COEFF_PM_PRE_CTRL2__fir_pre_5(reg_value) extract_field((reg_value),11,6) 5460 #define ex_TX_COEFF_PM_PRE_CTRL3__fir_pre_6(reg_value) extract_field((reg_value),5,0) 5461 #define ex_TX_COEFF_PM_PRE_CTRL3__fir_pre_7(reg_value) extract_field((reg_value),11,6) 5462 #define ex_TX_COEFF_PM_PRE_CTRL4__fir_pre_8(reg_value) extract_field((reg_value),5,0) 5463 #define ex_TX_COEFF_PM_PRE_CTRL4__fir_pre_9(reg_value) extract_field((reg_value),11,6) 5464 #define ex_TX_COEFF_PM_PRE_CTRL5__fir_pre_10(reg_value) extract_field((reg_value),5,0) 5465 #define ex_TX_COEFF_PM_REGMAIN_CTRL0__reg_main_post1pre_default(reg_value) extract_field((reg_value),5,0) 5466 #define ex_TX_COEFF_PM_REGMAIN_CTRL0__reg_main_cs(reg_value) extract_field((reg_value),8,6) 5467 #define ex_TX_COEFF_PM_REGMAIN_CTRL0__reg_en_main(reg_value) extract_field((reg_value),9,9) 5468 #define ex_TX_COEFF_PM_REGOVRD_CTRL__reg_ovrd(reg_value) extract_field((reg_value),0,0) 5469 #define ex_TX_COEFF_POST_POST_EXTENT_CTRL0__fir_post_extent_0(reg_value) extract_field((reg_value),14,0) 5470 #define ex_TX_COEFF_POST_POST_EXTENT_CTRL1__fir_post_extent_1(reg_value) extract_field((reg_value),14,0) 5471 #define ex_TX_COEFF_POST_POST_EXTENT_CTRL2__fir_post_extent_2(reg_value) extract_field((reg_value),14,0) 5472 #define ex_TX_COEFF_POST_POST_EXTENT_CTRL3__fir_post_extent_3(reg_value) extract_field((reg_value),14,0) 5473 #define ex_TX_COEFF_POST_POST_EXTENT_CTRL4__fir_post_extent_4(reg_value) extract_field((reg_value),14,0) 5474 #define ex_TX_COEFF_POST_POST_EXTENT_CTRL5__fir_post_extent_5(reg_value) extract_field((reg_value),14,0) 5475 #define ex_TX_COEFF_POSTA_POST_CTRL0__fir_post_0(reg_value) extract_field((reg_value),14,0) 5476 #define ex_TX_COEFF_POSTA_POST_CTRL1__fir_post_1(reg_value) extract_field((reg_value),14,0) 5477 #define ex_TX_COEFF_POSTA_POST_CTRL2__fir_post_2(reg_value) extract_field((reg_value),14,0) 5478 #define ex_TX_COEFF_POSTA_POST_CTRL3__fir_post_3(reg_value) extract_field((reg_value),14,0) 5479 #define ex_TX_COEFF_POSTA_POST_CTRL4__fir_post_4(reg_value) extract_field((reg_value),14,0) 5480 #define ex_TX_COEFF_POSTA_POST_CTRL5__fir_post_5(reg_value) extract_field((reg_value),14,0) 5481 #define ex_TX_COEFF_POSTA_POST_CTRL6__fir_post_6(reg_value) extract_field((reg_value),14,0) 5482 #define ex_TX_COEFF_POSTA_POST_CTRL7__fir_post_7(reg_value) extract_field((reg_value),14,0) 5483 #define ex_TX_COEFF_POSTA_POST_CTRL8__fir_post_8(reg_value) extract_field((reg_value),14,0) 5484 #define ex_TX_COEFF_POSTA_POST_CTRL9__fir_post_9(reg_value) extract_field((reg_value),14,0) 5485 #define ex_TX_COEFF_POSTA_POST_CTRL10__fir_post_10(reg_value) extract_field((reg_value),14,0) 5486 #define ex_TX_COEFF_POSTA_POST_CTRL11__fir_post_11(reg_value) extract_field((reg_value),14,0) 5487 #define ex_TX_COEFF_POSTA_POST_CTRL12__fir_post_12(reg_value) extract_field((reg_value),14,0) 5488 #define ex_TX_COEFF_POSTA_POST_CTRL13__fir_post_13(reg_value) extract_field((reg_value),14,0) 5489 #define ex_TX_COEFF_POSTA_POST_CTRL14__fir_post_14(reg_value) extract_field((reg_value),14,0) 5490 #define ex_TX_COEFF_POSTB_POST_CTRL15__fir_post_15(reg_value) extract_field((reg_value),14,0) 5491 #define ex_TX_COEFF_POSTB_POST_CTRL16__fir_post_16(reg_value) extract_field((reg_value),14,0) 5492 #define ex_TX_COEFF_POSTB_POST_CTRL17__fir_post_17(reg_value) extract_field((reg_value),14,0) 5493 #define ex_TX_COEFF_POSTB_POST_CTRL18__fir_post_18(reg_value) extract_field((reg_value),14,0) 5494 #define ex_TX_COEFF_POSTB_POST_CTRL19__fir_post_19(reg_value) extract_field((reg_value),14,0) 5495 #define ex_TX_COEFF_POSTB_POST_CTRL20__fir_post_20(reg_value) extract_field((reg_value),14,0) 5496 #define ex_TX_COEFF_POSTB_POST_CTRL21__fir_post_21(reg_value) extract_field((reg_value),14,0) 5497 #define ex_TX_COEFF_POSTB_POST_CTRL22__fir_post_22(reg_value) extract_field((reg_value),14,0) 5498 #define ex_TX_COEFF_POSTB_POST_CTRL23__fir_post_23(reg_value) extract_field((reg_value),14,0) 5499 #define ex_TX_COEFF_POSTB_POST_CTRL24__fir_post_24(reg_value) extract_field((reg_value),14,0) 5500 #define ex_TX_COEFF_POSTB_REG_PRE_POST_CTRL__pre_post1pre_default(reg_value) extract_field((reg_value),5,0) 5501 #define ex_TX_COEFF_POSTB_REG_PRE_POST_CTRL__post1_post1pre_default(reg_value) extract_field((reg_value),11,6) 5502 #define ex_TX_COEFF_PRE_PRE_EXTENT_CTRL0__fir_pre_extent_0(reg_value) extract_field((reg_value),5,0) 5503 #define ex_TX_COEFF_PRE_PRE_EXTENT_CTRL1__fir_pre_extent_1(reg_value) extract_field((reg_value),5,0) 5504 #define ex_TX_COEFF_PRE_PRE_EXTENT_CTRL2__fir_pre_extent_2(reg_value) extract_field((reg_value),5,0) 5505 #define ex_TX_COEFF_PRE_PRE_EXTENT_CTRL3__fir_pre_extent_3(reg_value) extract_field((reg_value),5,0) 5506 #define ex_TX_COEFF_PRE_PRE_EXTENT_CTRL4__fir_pre_extent_4(reg_value) extract_field((reg_value),5,0) 5507 #define ex_TX_COEFF_PRE_PRE_EXTENT_CTRL5__fir_pre_extent_5(reg_value) extract_field((reg_value),5,0) 5508 #define ex_TX_DFE0_EXT_TXSTATUS0__gloopback(reg_value) extract_field((reg_value),8,8) 5509 #define ex_TX_DFE0_EXT_TXSTATUS0__dig2ana_tx_ElecIdle(reg_value) extract_field((reg_value),6,6) 5510 #define ex_TX_DFE0_EXT_TXSTATUS0__setTxCnxTest(reg_value) extract_field((reg_value),5,5) 5511 #define ex_TX_DFE0_EXT_TXSTATUS0__dig2ana_tx_setTxCnxTest(reg_value) extract_field((reg_value),4,4) 5512 #define ex_TX_DFE0_EXT_TXSTATUS0__rxCnxDetect(reg_value) extract_field((reg_value),3,3) 5513 #define ex_TX_DFE0_EXT_TXSTATUS0__ana2dig_tx_rxCnxDetect(reg_value) extract_field((reg_value),2,2) 5514 #define ex_TX_DFE0_EXT_TXSTATUS0__rltxferr_stky(reg_value) extract_field((reg_value),1,1) 5515 #define ex_TX_DFE0_EXT_TXSTATUS0__txpll_lock(reg_value) extract_field((reg_value),0,0) 5516 #define ex_TX_DFE0_EXT_MDATA0__mdata0(reg_value) extract_field((reg_value),15,0) 5517 #define ex_TX_DFE0_EXT_MDATA1__mdata1(reg_value) extract_field((reg_value),15,0) 5518 #define ex_TX_DFE0_EXT_EQ_COEFFICIENT__eq_coeff(reg_value) extract_field((reg_value),15,0) 5519 #define ex_TX_DFE0_EXT_TXCONTROL0__mdio_force_SM(reg_value) extract_field((reg_value),15,15) 5520 #define ex_TX_DFE0_EXT_TXCONTROL0__L0s_test_SM(reg_value) extract_field((reg_value),14,14) 5521 #define ex_TX_DFE0_EXT_TXCONTROL0__setTxCnxTest_SM(reg_value) extract_field((reg_value),13,13) 5522 #define ex_TX_DFE0_EXT_TXCONTROL0__mdio_tx_ElecIdle(reg_value) extract_field((reg_value),12,12) 5523 #define ex_TX_DFE0_EXT_TXCONTROL0__fts_en_SM(reg_value) extract_field((reg_value),10,10) 5524 #define ex_TX_DFE0_EXT_TXCONTROL0__gloopOutDis_r(reg_value) extract_field((reg_value),9,9) 5525 #define ex_TX_DFE0_EXT_TXCONTROL0__prbs_enb_r(reg_value) extract_field((reg_value),8,8) 5526 #define ex_TX_DFE0_EXT_TXCONTROL0__pkt_en_r(reg_value) extract_field((reg_value),7,7) 5527 #define ex_TX_DFE0_EXT_TXCONTROL0__pkt_strt_r(reg_value) extract_field((reg_value),6,6) 5528 #define ex_TX_DFE0_EXT_TXCONTROL0__txpol_flip(reg_value) extract_field((reg_value),5,5) 5529 #define ex_TX_DFE0_EXT_TXCONTROL0__force_disError_SM(reg_value) extract_field((reg_value),4,4) 5530 #define ex_TX_DFE0_EXT_TXCONTROL0__eden_r(reg_value) extract_field((reg_value),3,3) 5531 #define ex_TX_DFE0_EXT_TXCONTROL0__eden_force_r(reg_value) extract_field((reg_value),2,2) 5532 #define ex_TX_DFE0_EXT_TXCONTROL0__txpat_seq_en_SM(reg_value) extract_field((reg_value),1,1) 5533 #define ex_TX_DFE0_EXT_TXCONTROL0__tx_mdata_en_SM(reg_value) extract_field((reg_value),0,0) 5534 #define ex_TX_DFE0_EXT_TXCONTROL1__txTestMuxSelect(reg_value) extract_field((reg_value),15,13) 5535 #define ex_TX_DFE0_EXT_TXCONTROL1__rlfifo_tstsel(reg_value) extract_field((reg_value),12,10) 5536 #define ex_TX_DFE0_EXT_TXCONTROL1__prbs_seed_ld(reg_value) extract_field((reg_value),9,9) 5537 #define ex_TX_DFE0_EXT_TXCONTROL1__L0s_timer_ld(reg_value) extract_field((reg_value),8,8) 5538 #define ex_TX_DFE0_EXT_TXCONTROL1__pktBurst_en(reg_value) extract_field((reg_value),7,7) 5539 #define ex_TX_DFE0_EXT_TXCONTROL1__pktRndm_en(reg_value) extract_field((reg_value),6,6) 5540 #define ex_TX_DFE0_EXT_TXCONTROL1__ipgLngth(reg_value) extract_field((reg_value),5,4) 5541 #define ex_TX_DFE0_EXT_TXCONTROL1__rxCnxDetect_r(reg_value) extract_field((reg_value),3,3) 5542 #define ex_TX_DFE0_EXT_TXCONTROL1__rxCnxDetect_force_r(reg_value) extract_field((reg_value),2,2) 5543 #define ex_TX_DFE0_EXT_TXCONTROL1__pre_emph_stair_rev_en(reg_value) extract_field((reg_value),1,1) 5544 #define ex_TX_DFE0_EXT_TXCONTROL1__mdio_txmargin_SM(reg_value) extract_field((reg_value),0,0) 5545 #define ex_TX_DFE0_EXT_TXCTRL0__tx_delay_fall_G1(reg_value) extract_field((reg_value),15,13) 5546 #define ex_TX_DFE0_EXT_TXCTRL0__rloop_delay_fall_G1(reg_value) extract_field((reg_value),12,8) 5547 #define ex_TX_DFE0_EXT_TXCTRL0__tx_delay_rise_G1(reg_value) extract_field((reg_value),7,5) 5548 #define ex_TX_DFE0_EXT_TXCTRL0__rloop_delay_rise_G1(reg_value) extract_field((reg_value),4,0) 5549 #define ex_TX_DFE0_EXT_TXCTRL1__tx_delay_fall_G2(reg_value) extract_field((reg_value),15,13) 5550 #define ex_TX_DFE0_EXT_TXCTRL1__rloop_delay_fall_G2(reg_value) extract_field((reg_value),12,8) 5551 #define ex_TX_DFE0_EXT_TXCTRL1__tx_delay_rise_G2(reg_value) extract_field((reg_value),7,5) 5552 #define ex_TX_DFE0_EXT_TXCTRL1__rloop_delay_rise_G2(reg_value) extract_field((reg_value),4,0) 5553 #define ex_TX_DFE0_EXT_TXCTRL2__tx_delay_fall_G3(reg_value) extract_field((reg_value),15,13) 5554 #define ex_TX_DFE0_EXT_TXCTRL2__rloop_delay_fall_G3(reg_value) extract_field((reg_value),12,8) 5555 #define ex_TX_DFE0_EXT_TXCTRL2__tx_delay_rise_G3(reg_value) extract_field((reg_value),7,5) 5556 #define ex_TX_DFE0_EXT_TXCTRL2__rloop_delay_rise_G3(reg_value) extract_field((reg_value),4,0) 5557 #define ex_TX_DFE0_EXT_TXCTRL3__rising_half_G3(reg_value) extract_field((reg_value),5,5) 5558 #define ex_TX_DFE0_EXT_TXCTRL3__falling_half_G3(reg_value) extract_field((reg_value),4,4) 5559 #define ex_TX_DFE0_EXT_TXCTRL3__rising_half_G2(reg_value) extract_field((reg_value),3,3) 5560 #define ex_TX_DFE0_EXT_TXCTRL3__falling_half_G2(reg_value) extract_field((reg_value),2,2) 5561 #define ex_TX_DFE0_EXT_TXCTRL3__rising_half_G1(reg_value) extract_field((reg_value),1,1) 5562 #define ex_TX_DFE0_EXT_TXCTRL3__falling_half_G1(reg_value) extract_field((reg_value),0,0) 5563 #define ex_TX_DFE0_EXT_TXCONTROL2__tx_g3_ei_fifo_rst_cya(reg_value) extract_field((reg_value),15,15) 5564 #define ex_TX_DFE0_EXT_TXCONTROL2__tx_g3f_tm_sel(reg_value) extract_field((reg_value),4,2) 5565 #define ex_TX_DFE0_EXT_TXCONTROL2__tx_g3f_sw_rst(reg_value) extract_field((reg_value),1,1) 5566 #define ex_TX_DFE0_EXT_TXCONTROL2__tx_g3f_afrst_en(reg_value) extract_field((reg_value),0,0) 5567 #define ex_TX_DFE0_EXT_TXSTATUS2__tx_g3f_afrst(reg_value) extract_field((reg_value),2,2) 5568 #define ex_TX_DFE0_EXT_TXSTATUS2__tx_g3f_unflow(reg_value) extract_field((reg_value),1,1) 5569 #define ex_TX_DFE0_EXT_TXSTATUS2__tx_g3f_ovflow(reg_value) extract_field((reg_value),0,0) 5570 #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_post2(reg_value) extract_field((reg_value),3,0) 5571 #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe_error(reg_value) extract_field((reg_value),6,6) 5572 #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe_int_en(reg_value) extract_field((reg_value),5,5) 5573 #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe(reg_value) extract_field((reg_value),4,4) 5574 #define ex_TX_FED_MISC_CONTROL0__tx_disable_output_sel(reg_value) extract_field((reg_value),3,2) 5575 #define ex_TX_FED_MISC_CONTROL0__sdk_tx_disable(reg_value) extract_field((reg_value),0,0) 5576 #define ex_TX_FED_MISC_STATUS0__tx_elec_idle_status(reg_value) extract_field((reg_value),1,1) 5577 #define ex_TX_FED_MISC_STATUS0__tx_disable_status(reg_value) extract_field((reg_value),0,0) 5578 #define ex_TX_FED_MICRO_CONTROL0__tx_eee_alert_en(reg_value) extract_field((reg_value),15,15) 5579 #define ex_TX_FED_MICRO_CONTROL0__tx_eee_quiet_en(reg_value) extract_field((reg_value),14,14) 5580 #define ex_TX_FED_MICRO_CONTROL0__tx_disable_timer_ctrl(reg_value) extract_field((reg_value),9,4) 5581 #define ex_TX_FED_MICRO_CONTROL0__pmd_tx_disable_pkill(reg_value) extract_field((reg_value),3,3) 5582 #define ex_TX_FED_MICRO_CONTROL0__dp_reset_tx_disable_dis(reg_value) extract_field((reg_value),2,2) 5583 #define ex_TX_FED_MICRO_CONTROL0__tx_disable_trigger(reg_value) extract_field((reg_value),1,1) 5584 #define ex_TX_FED_MICRO_CONTROL0__micro_tx_disable(reg_value) extract_field((reg_value),0,0) 5585 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_2x_1(reg_value) extract_field((reg_value),7,7) 5586 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_2x_1(reg_value) extract_field((reg_value),6,6) 5587 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_2x_0(reg_value) extract_field((reg_value),5,5) 5588 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_2x_0(reg_value) extract_field((reg_value),4,4) 5589 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_1x_1(reg_value) extract_field((reg_value),3,3) 5590 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_1x_1(reg_value) extract_field((reg_value),2,2) 5591 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_1x_0(reg_value) extract_field((reg_value),1,1) 5592 #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_1x_0(reg_value) extract_field((reg_value),0,0) 5593 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1pre_1x_0(reg_value) extract_field((reg_value),14,14) 5594 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1pre_1x_0(reg_value) extract_field((reg_value),13,13) 5595 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_pre_post1pre_1x_0(reg_value) extract_field((reg_value),12,12) 5596 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_2(reg_value) extract_field((reg_value),9,9) 5597 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_2(reg_value) extract_field((reg_value),8,8) 5598 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_1(reg_value) extract_field((reg_value),7,7) 5599 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_1(reg_value) extract_field((reg_value),6,6) 5600 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_0(reg_value) extract_field((reg_value),5,5) 5601 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_0(reg_value) extract_field((reg_value),4,4) 5602 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_1x_1(reg_value) extract_field((reg_value),3,3) 5603 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_1x_1(reg_value) extract_field((reg_value),2,2) 5604 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_1x_0(reg_value) extract_field((reg_value),1,1) 5605 #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_1x_0(reg_value) extract_field((reg_value),0,0) 5606 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_3(reg_value) extract_field((reg_value),14,14) 5607 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_3(reg_value) extract_field((reg_value),13,13) 5608 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_3(reg_value) extract_field((reg_value),12,12) 5609 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_2(reg_value) extract_field((reg_value),11,11) 5610 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_2(reg_value) extract_field((reg_value),10,10) 5611 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_2(reg_value) extract_field((reg_value),9,9) 5612 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_1(reg_value) extract_field((reg_value),8,8) 5613 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_1(reg_value) extract_field((reg_value),7,7) 5614 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_1(reg_value) extract_field((reg_value),6,6) 5615 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_0(reg_value) extract_field((reg_value),5,5) 5616 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_0(reg_value) extract_field((reg_value),4,4) 5617 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_0(reg_value) extract_field((reg_value),3,3) 5618 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_1x_1(reg_value) extract_field((reg_value),2,2) 5619 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_1x_1(reg_value) extract_field((reg_value),1,1) 5620 #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_1x_1(reg_value) extract_field((reg_value),0,0) 5621 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_2x_1(reg_value) extract_field((reg_value),3,3) 5622 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_2x_0(reg_value) extract_field((reg_value),2,2) 5623 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_1x(reg_value) extract_field((reg_value),1,1) 5624 #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_0p5x(reg_value) extract_field((reg_value),0,0) 5625 #define ex_TX_PI_CONTROL_0__tx_pi_en(reg_value) extract_field((reg_value),0,0) 5626 #define ex_TX_PI_CONTROL_0__tx_pi_jitter_filter_en(reg_value) extract_field((reg_value),1,1) 5627 #define ex_TX_PI_CONTROL_0__tx_pi_ext_ctrl_en(reg_value) extract_field((reg_value),2,2) 5628 #define ex_TX_PI_CONTROL_0__tx_pi_freq_override_en(reg_value) extract_field((reg_value),3,3) 5629 #define ex_TX_PI_CONTROL_0__tx_pi_sj_gen_en(reg_value) extract_field((reg_value),4,4) 5630 #define ex_TX_PI_CONTROL_0__tx_pi_ssc_gen_en(reg_value) extract_field((reg_value),5,5) 5631 #define ex_TX_PI_CONTROL_0__tx_pi_jit_ssc_freq_mode(reg_value) extract_field((reg_value),6,6) 5632 #define ex_TX_PI_CONTROL_0__tx_pi_reset_code_dbg(reg_value) extract_field((reg_value),7,7) 5633 #define ex_TX_PI_CONTROL_0__tx_pi_second_order_loop_en(reg_value) extract_field((reg_value),8,8) 5634 #define ex_TX_PI_CONTROL_0__tx_pi_first_order_bwsel_integ(reg_value) extract_field((reg_value),11,10) 5635 #define ex_TX_PI_CONTROL_0__tx_pi_second_order_bwsel_integ(reg_value) extract_field((reg_value),13,12) 5636 #define ex_TX_PI_CONTROL_0__tx_pi_frc_phase_step_mux_sel(reg_value) extract_field((reg_value),15,15) 5637 #define ex_TX_PI_CONTROL_1__tx_pi_freq_override_val(reg_value) extract_field_signed((reg_value),14,0) 5638 #define ex_TX_PI_CONTROL_2__tx_pi_jit_freq_idx(reg_value) extract_field((reg_value),5,0) 5639 #define ex_TX_PI_CONTROL_2__tx_pi_jit_amp(reg_value) extract_field((reg_value),13,8) 5640 #define ex_TX_PI_CONTROL_3__tx_pi_phase_override(reg_value) extract_field((reg_value),0,0) 5641 #define ex_TX_PI_CONTROL_3__tx_pi_phase_strobe(reg_value) extract_field((reg_value),1,1) 5642 #define ex_TX_PI_CONTROL_3__tx_pi_phase_step_dir(reg_value) extract_field((reg_value),2,2) 5643 #define ex_TX_PI_CONTROL_3__tx_pi_phase_invert(reg_value) extract_field((reg_value),4,4) 5644 #define ex_TX_PI_CONTROL_3__tx_pi_phase_step_num(reg_value) extract_field((reg_value),11,8) 5645 #define ex_TX_PI_CONTROL_3__tx_pi_ext_phase_bwsel_integ(reg_value) extract_field((reg_value),14,12) 5646 #define ex_TX_PI_CONTROL_4__tx_pi_frz_frc(reg_value) extract_field((reg_value),0,0) 5647 #define ex_TX_PI_CONTROL_4__tx_pi_frz_frc_val(reg_value) extract_field((reg_value),1,1) 5648 #define ex_TX_PI_CONTROL_4__tx_pi_frz_mode(reg_value) extract_field((reg_value),2,2) 5649 #define ex_TX_PI_CONTROL_5__tx_pi_hs_fifo_phserr_invert(reg_value) extract_field((reg_value),1,1) 5650 #define ex_TX_PI_CONTROL_5__tx_pi_repeater_mode_en(reg_value) extract_field((reg_value),2,2) 5651 #define ex_TX_PI_CONTROL_5__tx_pi_ext_pd_sel(reg_value) extract_field((reg_value),3,3) 5652 #define ex_TX_PI_CONTROL_5__afe_tx_fifo_resetb(reg_value) extract_field((reg_value),8,8) 5653 #define ex_TX_PI_CONTROL_5__afe_tx_fifo_resetb_frc_on(reg_value) extract_field((reg_value),9,9) 5654 #define ex_TX_PI_CONTROL_5__tx_pi_pd_bypass_flt(reg_value) extract_field((reg_value),10,10) 5655 #define ex_TX_PI_CONTROL_5__tx_pi_pd_bypass_vco(reg_value) extract_field((reg_value),11,11) 5656 #define ex_TX_PI_STATUS_0__tx_pi_phase_cntr(reg_value) extract_field_signed((reg_value),6,0) 5657 #define ex_TX_PI_STATUS_1__tx_pi_integ1_reg(reg_value) extract_field_signed((reg_value),13,0) 5658 #define ex_TX_PI_STATUS_2__tx_pi_integ2_reg(reg_value) extract_field_signed((reg_value),14,0) 5659 #define ex_TX_PI_STATUS_3__tx_pi_phase_err(reg_value) extract_field_signed((reg_value),5,0) 5660 #define ex_TX_PI_STATUS_4__st_afe_tx_fifo_resetb(reg_value) extract_field((reg_value),1,1) 5661 #define ex_TX_PI_STATUS_4__tx_pi_hs_fifo_phserr(reg_value) extract_field((reg_value),0,0) 5662 #define ex_TX_PI_TX_FIFO_OVFB_STATUS__tx_fifo_ovfb_fall_edge_lh(reg_value) extract_field((reg_value),1,1) 5663 #define ex_TX_PI_TX_FIFO_OVFB_STATUS__tx_fifo_ovfb(reg_value) extract_field((reg_value),0,0) 5664 #define ex_TX_TCA_TX_TCA_CONTROL_0__ana_tca_power_on_frc(reg_value) extract_field((reg_value),6,6) 5665 #define ex_TX_TCA_TX_TCA_CONTROL_0__tca_done_frc_val(reg_value) extract_field((reg_value),5,5) 5666 #define ex_TX_TCA_TX_TCA_CONTROL_0__tca_done_frc(reg_value) extract_field((reg_value),4,4) 5667 #define ex_TX_TCA_TX_TCA_CONTROL_0__tca_timer_sel(reg_value) extract_field((reg_value),3,2) 5668 #define ex_TX_TCA_TX_TCA_CONTROL_0__tca_restart(reg_value) extract_field((reg_value),1,1) 5669 #define ex_TX_TCA_TX_TCA_CONTROL_0__tca_disable(reg_value) extract_field((reg_value),0,0) 5670 #define ex_TX_TCA_TX_TCA_CONTROL_1__tca_wait_timer(reg_value) extract_field((reg_value),13,0) 5671 #define ex_TX_TCA_TX_TCA_CONTROL_2__tca_coarse_timer(reg_value) extract_field((reg_value),13,0) 5672 #define ex_TX_TCA_TX_TCA_CONTROL_3__tca_fine_timer(reg_value) extract_field((reg_value),13,0) 5673 #define ex_TX_TCA_TX_TCA_CONTROL_4__phserr_win_coarse(reg_value) extract_field((reg_value),15,9) 5674 #define ex_TX_TCA_TX_TCA_CONTROL_4__phserr_win_fine(reg_value) extract_field((reg_value),8,2) 5675 #define ex_TX_TCA_TX_TCA_CONTROL_4__fine_done_by_timer(reg_value) extract_field((reg_value),1,1) 5676 #define ex_TX_TCA_TX_TCA_CONTROL_4__coarse_done_by_timer(reg_value) extract_field((reg_value),0,0) 5677 #define ex_TX_TCA_TX_PI_OFFSET_CONTROL__tx_pi_offset_en(reg_value) extract_field((reg_value),15,15) 5678 #define ex_TX_TCA_TX_PI_OFFSET_CONTROL__tx_pi_offset_dir(reg_value) extract_field((reg_value),14,14) 5679 #define ex_TX_TCA_TX_PI_OFFSET_CONTROL__tx_pi_shift_num(reg_value) extract_field((reg_value),13,10) 5680 #define ex_TX_TCA_TX_PI_OFFSET_CONTROL__tx_pi_offset_num(reg_value) extract_field((reg_value),9,0) 5681 #define ex_TX_TCA_TX_TCA_STATUS__tca_state(reg_value) extract_field((reg_value),2,0) 5682 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) 5683 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) 5684 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__tx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) 5685 #define ex_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL__tx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) 5686 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) 5687 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) 5688 #define ex_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) 5689 #define ex_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) 5690 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS__tx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) 5691 #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL__tx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) 5692 #define ex_TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL__tx_multicast_mask_control(reg_value) extract_field((reg_value),0,0) 5693 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_multicast_mask_control_status(reg_value) extract_field((reg_value),4,4) 5694 #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_osr_mode(reg_value) extract_field((reg_value),3,0) 5695 #define ex_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__tx_osr_mode_pin(reg_value) extract_field((reg_value),3,0) 5696 #define exc_TX_COM_TXCOM_CONTROL0_REGISTER__txcom_cl72_max_wait_timer_period(reg_value) extract_field((reg_value),15,0) 5697 #define exc_TX_COM_TXCOM_CONTROL1_REGISTER__txcom_cl72_wait_cntr_limit(reg_value) extract_field((reg_value),8,0) 5698 5699 #endif