merlin16_pcieg3_enum.h (6235B)
1 /****************************************************************************** 2 ****************************************************************************** 3 * Revision : * 4 * * 5 * Description : Enum types used by Serdes API functions * 6 * * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2019 Broadcom Inc. All rights reserved. * 10 * No portions of this material may be reproduced in any form without * 11 * the written permission of: * 12 * Broadcom Corporation * 13 * 5300 California Avenue * 14 * Irvine, CA 92617 * 15 * * 16 * All information contained in this document is Broadcom Corporation * 17 * company private proprietary, and trade secret. * 18 */ 19 20 /** @file merlin16_pcieg3_enum.h 21 * Enum types used by Serdes API functions 22 */ 23 24 #ifndef MERLIN16_PCIEG3_API_ENUM_H 25 #define MERLIN16_PCIEG3_API_ENUM_H 26 27 #include "merlin16_pcieg3_ipconfig.h" 28 #ifdef __KERNEL__ 29 #include <linux/types.h> 30 #else 31 #ifndef EXCLUDE_STD_HEADERS 32 #include <stdint.h> 33 #endif 34 #endif 35 36 37 enum merlin16_pcieg3_pll_refclk_enum { 38 MERLIN16_PCIEG3_PLL_REFCLK_UNKNOWN = 0, /* Refclk value to be determined by API. */ 39 MERLIN16_PCIEG3_PLL_REFCLK_50MHZ = 0x00100032UL, /* 50 MHz */ 40 MERLIN16_PCIEG3_PLL_REFCLK_125MHZ = 0x0010007DUL, /* 125 MHz */ 41 MERLIN16_PCIEG3_PLL_REFCLK_156P25MHZ = 0x00400271UL, /* 156.25 MHz */ 42 MERLIN16_PCIEG3_PLL_REFCLK_161P1328125MHZ = 0x08005091UL /* 161.1328125 MHz */ 43 }; 44 45 46 enum merlin16_pcieg3_pll_div_enum { 47 MERLIN16_PCIEG3_PLL_DIV_UNKNOWN = 0, /* Divide value to be determined by API. */ 48 MERLIN16_PCIEG3_PLL_DIV_52P751515 = (int)0xC0634034, /* Divide by 52.751515 */ 49 MERLIN16_PCIEG3_PLL_DIV_54P4 = (int)0x66668036, /* Divide by 54.4 */ 50 MERLIN16_PCIEG3_PLL_DIV_58P181818 = (int)0x2E8BC03A, /* Divide by 58.181818 */ 51 MERLIN16_PCIEG3_PLL_DIV_60 = (int)0x0000003C, /* Divide by 60 */ 52 MERLIN16_PCIEG3_PLL_DIV_62P060606 = (int)0x0F84003E, /* Divide by 62.060606 */ 53 MERLIN16_PCIEG3_PLL_DIV_64 = (int)0x00000040, /* Divide by 64 */ 54 MERLIN16_PCIEG3_PLL_DIV_66 = (int)0x00000042, /* Divide by 66 */ 55 MERLIN16_PCIEG3_PLL_DIV_66P460703 = (int)0x75F0C042, /* Divide by 66.460703 */ 56 MERLIN16_PCIEG3_PLL_DIV_66P743079 = (int)0xBE3A8042, /* Divide by 66.743079 */ 57 MERLIN16_PCIEG3_PLL_DIV_67P878788 = (int)0xE0F84043, /* Divide by 67.878788 */ 58 MERLIN16_PCIEG3_PLL_DIV_68 = (int)0x00000044, /* Divide by 68 */ 59 MERLIN16_PCIEG3_PLL_DIV_68P537598 = (int)0x89A00044, /* Divide by 68.537598 */ 60 MERLIN16_PCIEG3_PLL_DIV_68P570764 = (int)0x921D8044, /* Divide by 68.570764 */ 61 MERLIN16_PCIEG3_PLL_DIV_68P828796 = (int)0xD42C0044, /* Divide by 68.828796 */ 62 MERLIN16_PCIEG3_PLL_DIV_68P856242 = (int)0xDB32C044, /* Divide by 68.856242 */ 63 MERLIN16_PCIEG3_PLL_DIV_69P152458 = (int)0x27078045, /* Divide by 69.152458 */ 64 MERLIN16_PCIEG3_PLL_DIV_69P389964 = (int)0x63D4C045, /* Divide by 69.389964 */ 65 MERLIN16_PCIEG3_PLL_DIV_69P818182 = (int)0xD1748045, /* Divide by 69.818182 */ 66 MERLIN16_PCIEG3_PLL_DIV_70 = (int)0x00000046, /* Divide by 70 */ 67 MERLIN16_PCIEG3_PLL_DIV_70P713596 = (int)0xB6AE4046, /* Divide by 70.713596 */ 68 MERLIN16_PCIEG3_PLL_DIV_71P008 = (int)0x020C4047, /* Divide by 71.008 */ 69 MERLIN16_PCIEG3_PLL_DIV_71P112952 = (int)0x1CEA8047, /* Divide by 71.P112952 */ 70 MERLIN16_PCIEG3_PLL_DIV_71P31347 = (int)0x503F8047, /* Divide by 71.31347 */ 71 MERLIN16_PCIEG3_PLL_DIV_71P5584 = (int)0x8EF34047, /* Divide by 71.5584 */ 72 MERLIN16_PCIEG3_PLL_DIV_72 = (int)0x00000048, /* Divide by 72 */ 73 MERLIN16_PCIEG3_PLL_DIV_73P335232 = (int)0x55D1C049, /* Divide by 73.335232 */ 74 MERLIN16_PCIEG3_PLL_DIV_73P6 = (int)0x9999C049, /* Divide by 73.6 */ 75 MERLIN16_PCIEG3_PLL_DIV_75 = (int)0x0000004B, /* Divide by 75 */ 76 MERLIN16_PCIEG3_PLL_DIV_80 = (int)0x00000050, /* Divide by 80 */ 77 MERLIN16_PCIEG3_PLL_DIV_82P5 = (int)0x80000052, /* Divide by 82.5 */ 78 MERLIN16_PCIEG3_PLL_DIV_85P671997 = (int)0xAC080055, /* Divide by 85.671997 */ 79 MERLIN16_PCIEG3_PLL_DIV_86P036 = (int)0x09374056, /* Divide by 86.036 */ 80 MERLIN16_PCIEG3_PLL_DIV_87P5 = (int)0x80000057, /* Divide by 87.5 */ 81 MERLIN16_PCIEG3_PLL_DIV_88P392 = (int)0x645A4058, /* Divide by 88.392 */ 82 MERLIN16_PCIEG3_PLL_DIV_88P76 = (int)0xC28F8058, /* Divide by 88.76 */ 83 MERLIN16_PCIEG3_PLL_DIV_89P141838 = (int)0x244F8059, /* Divide by 89.141838 */ 84 MERLIN16_PCIEG3_PLL_DIV_89P447998 = (int)0x72B00059, /* Divide by 89.447998 */ 85 MERLIN16_PCIEG3_PLL_DIV_90 = (int)0x0000005A, /* Divide by 90 */ 86 MERLIN16_PCIEG3_PLL_DIV_91P669037 = (int)0xAB46005B, /* Divide by 91.669037 */ 87 MERLIN16_PCIEG3_PLL_DIV_92 = (int)0x0000005C, /* Divide by 92 */ 88 MERLIN16_PCIEG3_PLL_DIV_100 = (int)0x00000064, /* Divide by 100 */ 89 MERLIN16_PCIEG3_PLL_DIV_170 = (int)0x000000AA, /* Divide by 170 */ 90 MERLIN16_PCIEG3_PLL_DIV_187P5 = (int)0x800000BB, /* Divide by 187.5 */ 91 MERLIN16_PCIEG3_PLL_DIV_200 = (int)0x000000C8, /* Divide by 200 */ 92 MERLIN16_PCIEG3_PLL_DIV_206P25 = (int)0x400000CE /* Divide by 206.25 */ 93 }; 94 95 /** TX AFE Settings Enum */ 96 enum merlin16_pcieg3_tx_afe_settings_enum { 97 TX_AFE_PRE, 98 TX_AFE_MAIN, 99 TX_AFE_POST1, 100 TX_AFE_POST2, 101 TX_AFE_POST3, 102 TX_AFE_RPARA 103 }; 104 105 106 107 #endif