merlin16_pcieg3_registers.html (1271335B)
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You must edit the source file for changes to be made to this file. 21 * 22 * 23 * 24 * Compiled with: RDB Utility 5.0 25 * RDB Parser 3.0 26 * rdb2html.pm 3.0 27 * Perl Interpreter 5.008008 28 * Operating System linux 29 * 30 * Spec Versions: ams_rx 1 31 * ams_tx 1 32 * amscom 1 33 * digcom_b_exp8 1 34 * digcom_exp8 1 35 * dsc_a 1 36 * dsc_b 1 37 * dsc_c 1 38 * dsc_d 1 39 * dsc_e 1 40 * dsc_f 1 41 * dsc_g 1 42 * dsc_h 1 43 * dsc_i 1 44 * dsc_j 1 45 * mdio_blk_addr 1 46 * mdio_mmdsel_aer_com 1 47 * micro_a_rmi 1 48 * micro_b_rmi 1 49 * micro_c_rmi 1 50 * micro_ctrl0 1 51 * micro_dbg 1 52 * micro_info 1 53 * patt_gen 1 54 * pcie0 1 55 * pcie1 1 56 * pcie2 1 57 * pcie3 1 58 * pcie4 1 59 * pcie5 1 60 * pcie6 1 61 * pcie7 1 62 * pll_cal 1 63 * reg_info 1 64 * rx_ckrst_ctrl 1 65 * rx_dfe0 1 66 * rx_dfe2 1 67 * rxcom_ckrst_ctrl 1 68 * rxtxcom_ckrst_ctrl 1 69 * sigdet_pcie 1 70 * tlb_rx 1 71 * tlb_tx 1 72 * tx_ckrst_ctrl 1 73 * tx_coeff_main_extent 1 74 * tx_coeff_pm 1 75 * tx_coeff_post_extent 1 76 * tx_coeff_posta 1 77 * tx_coeff_postb 1 78 * tx_coeff_pre_extent 1 79 * tx_dfe0 1 80 * tx_fed_exp8 1 81 * tx_pi 1 82 * tx_tca 1 83 * txcom_ckrst_ctrl 1 84 * txcom_exp8 1 85 * 86 * Revision History: 87 * 88 * $brcm_Log: $ 89 * 90 ***************************************************************************/ 91 92 !------> 93 <html> 94 <head> 95 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1"> 96 <meta name="generator" content="Adobe GoLive 5"> 97 <title>pcie_gen3</title> 98 <link rel="stylesheet" href="brcm.css"> 99 </head> 100 <p> 101 <HTML> 102 103 <HEAD> 104 <STYLE TYPE="text/css"> 105 HR {page-break-after: always} 106 </STYLE> 107 108 <STYLE> 109 <!-- 110 .VT { 111 writing-mode: tb-rl; 112 font-family: Verdana, Tahoma, 'Trebuchet MS', Arial, Helvetica, sans-serif; 113 font-weight: 400; 114 font-size: x-small; } 115 --> 116 </STYLE> 117 </HEAD> 118 119 <STYLE> 120 <!-- 121 .HT { 122 writing-mode: lr-tb; 123 font-family: Verdana, Tahoma, 'Trebuchet MS', Arial, Helvetica, sans-serif; 124 font-weight: 300; 125 font-size: x-small; } 126 --> 127 </STYLE> 128 </HEAD> 129 130 <h1><a NAME="pcie_gen3">pcie_gen3: pcie_gen3 Registers Map</a></h1> 131 <table border=1 align=center width=100% cellpadding=0> 132 <tr bgcolor="#C0CFF0"><td align=center width=60%><b>Block </b></td><td align=center width=20%><b>Start - End Offset</b></td><td align=center width=20%><b>Start - End Address</b></td></tr> 133 <tr> 134 <td align=left>      <b>REG_INFO_BLK: Description of Register Addressing</b></td><td align=center>0x0000 - 0x000F</td><td align=center>0x0000 - 0x000F</td></tr> 135 <tr> 136 <td align=left>            <A HREF="#REGISTER_INFO_EXT Registers">REGISTER_INFO_EXT</A></td><td align=center>0x0000 - 0x0000</td><td align=center>0x0000 - 0x0000</td></tr> 137 <tr> 138 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0x0010 - 0x0FFF</td><td align=center>0x0010 - 0x0FFF</td></tr> 139 <tr> 140 <td align=left>      <b>PCIE_BLOCK</b></td><td align=center>0x1000 - 0x17FF</td><td align=center>0x1000 - 0x17FF</td></tr> 141 <tr> 142 <td align=left>            <A HREF="#PCIE_BLK0_EXT Registers">PCIE_BLK0_EXT</A></td><td align=center>0x1000 - 0x1007</td><td align=center>0x1000 - 0x1007</td></tr> 143 <tr> 144 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1010 - 0x10FF</td><td align=center>0x1010 - 0x10FF</td></tr> 145 <tr> 146 <td align=left>            <A HREF="#PCIE_BLK1_EXT Registers">PCIE_BLK1_EXT</A></td><td align=center>0x1100 - 0x110E</td><td align=center>0x1100 - 0x110E</td></tr> 147 <tr> 148 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1110 - 0x11FF</td><td align=center>0x1110 - 0x11FF</td></tr> 149 <tr> 150 <td align=left>            <A HREF="#PCIE_BLK2_EXT Registers">PCIE_BLK2_EXT</A></td><td align=center>0x1200 - 0x120B</td><td align=center>0x1200 - 0x120B</td></tr> 151 <tr> 152 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1210 - 0x12FF</td><td align=center>0x1210 - 0x12FF</td></tr> 153 <tr> 154 <td align=left>            <A HREF="#PCIE_BLK3_EXT Registers">PCIE_BLK3_EXT</A></td><td align=center>0x1300 - 0x130E</td><td align=center>0x1300 - 0x130E</td></tr> 155 <tr> 156 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1310 - 0x13FF</td><td align=center>0x1310 - 0x13FF</td></tr> 157 <tr> 158 <td align=left>            <A HREF="#PCIE_BLK4_EXT Registers">PCIE_BLK4_EXT</A></td><td align=center>0x1400 - 0x140E</td><td align=center>0x1400 - 0x140E</td></tr> 159 <tr> 160 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1410 - 0x14FF</td><td align=center>0x1410 - 0x14FF</td></tr> 161 <tr> 162 <td align=left>            <A HREF="#PCIE_BLK5_EXT Registers">PCIE_BLK5_EXT</A></td><td align=center>0x1500 - 0x150E</td><td align=center>0x1500 - 0x150E</td></tr> 163 <tr> 164 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1510 - 0x15FF</td><td align=center>0x1510 - 0x15FF</td></tr> 165 <tr> 166 <td align=left>            <A HREF="#PCIE_BLK6_EXT Registers">PCIE_BLK6_EXT</A></td><td align=center>0x1600 - 0x1603</td><td align=center>0x1600 - 0x1603</td></tr> 167 <tr> 168 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x1610 - 0x16FF</td><td align=center>0x1610 - 0x16FF</td></tr> 169 <tr> 170 <td align=left>            <A HREF="#PCIE_BLK7_EXT Registers">PCIE_BLK7_EXT</A></td><td align=center>0x1700 - 0x170A</td><td align=center>0x1700 - 0x170A</td></tr> 171 <tr> 172 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0x1710 - 0x4FFF</td><td align=center>0x1710 - 0x4FFF</td></tr> 173 <tr> 174 <td align=left>      <b>TX_DFE: TX Local Registers (One Copy Per Lane)</b></td><td align=center>0x5000 - 0x5FFF</td><td align=center>0x5000 - 0x5FFF</td></tr> 175 <tr> 176 <td align=left>            <A HREF="#TX_DFE0_EXT Registers">TX_DFE0_EXT</A></td><td align=center>0x5000 - 0x500C</td><td align=center>0x5000 - 0x500C</td></tr> 177 <tr> 178 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0x5010 - 0x6FFF</td><td align=center>0x5010 - 0x6FFF</td></tr> 179 <tr> 180 <td align=left>      <b>RX_DFE: RX DFE Registers (One Copy Per Lane)</b></td><td align=center>0x7000 - 0x7FFF</td><td align=center>0x7000 - 0x7FFF</td></tr> 181 <tr> 182 <td align=left>            <A HREF="#RX_DFE0_EXT Registers">RX_DFE0_EXT</A></td><td align=center>0x7000 - 0x7008</td><td align=center>0x7000 - 0x7008</td></tr> 183 <tr> 184 <td bgcolor=#CCCCCC align=left>            Reserved</td><td align=center>0x7010 - 0x71FF</td><td align=center>0x7010 - 0x71FF</td></tr> 185 <tr> 186 <td align=left>            <A HREF="#RX_DFE2_EXT Registers">RX_DFE2_EXT</A></td><td align=center>0x7200 - 0x7202</td><td align=center>0x7200 - 0x7202</td></tr> 187 <tr> 188 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0x7210 - 0xCFFF</td><td align=center>0x7210 - 0xCFFF</td></tr> 189 <tr> 190 <td align=left>      <b>dsc_blk</b></td><td align=center>0xD000 - 0xD04F</td><td align=center>0xD000 - 0xD04F</td></tr> 191 <tr> 192 <td align=left>            <A HREF="#DSC_A Registers">DSC_A: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD000 - 0xD00E</td><td align=center>0xD000 - 0xD00E</td></tr> 193 <tr> 194 <td align=left>            <A HREF="#DSC_B Registers">DSC_B: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD010 - 0xD01E</td><td align=center>0xD010 - 0xD01E</td></tr> 195 <tr> 196 <td align=left>            <A HREF="#DSC_C Registers">DSC_C: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD020 - 0xD02E</td><td align=center>0xD020 - 0xD02E</td></tr> 197 <tr> 198 <td align=left>            <A HREF="#DSC_D Registers">DSC_D: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD030 - 0xD03E</td><td align=center>0xD030 - 0xD03E</td></tr> 199 <tr> 200 <td align=left>            <A HREF="#DSC_E Registers">DSC_E: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD040 - 0xD042</td><td align=center>0xD040 - 0xD042</td></tr> 201 <tr> 202 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0xD050 - 0xD06F</td><td align=center>0xD050 - 0xD06F</td></tr> 203 <tr> 204 <td align=left>      <b>tx_pi_blk</b></td><td align=center>0xD070 - 0xD07F</td><td align=center>0xD070 - 0xD07F</td></tr> 205 <tr> 206 <td align=left>            <A HREF="#TX_PI Registers">TX_PI: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD070 - 0xD07D</td><td align=center>0xD070 - 0xD07D</td></tr> 207 <tr> 208 <td align=left>      <b>rxtxcom_ckrst_ctrl_blk</b></td><td align=center>0xD080 - 0xD08F</td><td align=center>0xD080 - 0xD08F</td></tr> 209 <tr> 210 <td align=left>            <A HREF="#RXTXCOM_CKRST_CTRL Registers">RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl 211 blocks.</A></td><td align=center>0xD080 - 0xD08E</td><td align=center>0xD080 - 0xD08E</td></tr> 212 <tr> 213 <td align=left>      <b>ams_blk</b></td><td align=center>0xD090 - 0xD0BF</td><td align=center>0xD090 - 0xD0BF</td></tr> 214 <tr> 215 <td align=left>            <A HREF="#AMS_RX Registers">AMS_RX: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD090 - 0xD099</td><td align=center>0xD090 - 0xD099</td></tr> 216 <tr> 217 <td align=left>            <A HREF="#AMS_TX Registers">AMS_TX: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD0A0 - 0xD0AA</td><td align=center>0xD0A0 - 0xD0AA</td></tr> 218 <tr> 219 <td align=left>            <A HREF="#AMS_COM Registers">AMS_COM: common register block for all lanes</A></td><td align=center>0xD0B0 - 0xD0BF</td><td align=center>0xD0B0 - 0xD0BF</td></tr> 220 <tr> 221 <td align=left>      <b>sigdet_blk</b></td><td align=center>0xD0C0 - 0xD0CF</td><td align=center>0xD0C0 - 0xD0CF</td></tr> 222 <tr> 223 <td align=left>            <A HREF="#SIGDET Registers">SIGDET: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD0C0 - 0xD0CD</td><td align=center>0xD0C0 - 0xD0CD</td></tr> 224 <tr> 225 <td align=left>      <b>tlb_blk</b></td><td align=center>0xD0D0 - 0xD0EF</td><td align=center>0xD0D0 - 0xD0EF</td></tr> 226 <tr> 227 <td align=left>            <A HREF="#TLB_RX Registers">TLB_RX: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD0D0 - 0xD0DC</td><td align=center>0xD0D0 - 0xD0DC</td></tr> 228 <tr> 229 <td align=left>            <A HREF="#TLB_TX Registers">TLB_TX: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD0E0 - 0xD0E8</td><td align=center>0xD0E0 - 0xD0E8</td></tr> 230 <tr> 231 <td align=left>      <b>digcom_blk</b></td><td align=center>0xD0F0 - 0xD0FF</td><td align=center>0xD0F0 - 0xD0FF</td></tr> 232 <tr> 233 <td align=left>            <A HREF="#DIG_COM Registers">DIG_COM: common register block for all lanes</A></td><td align=center>0xD0F0 - 0xD0FE</td><td align=center>0xD0F0 - 0xD0FE</td></tr> 234 <tr> 235 <td align=left>      <b>patt_gen_blk</b></td><td align=center>0xD100 - 0xD10F</td><td align=center>0xD100 - 0xD10F</td></tr> 236 <tr> 237 <td align=left>            <A HREF="#PATT_GEN_COM Registers">PATT_GEN_COM: common register block for all lanes</A></td><td align=center>0xD100 - 0xD10E</td><td align=center>0xD100 - 0xD10E</td></tr> 238 <tr> 239 <td align=left>      <b>tx_fed_blk</b></td><td align=center>0xD110 - 0xD11F</td><td align=center>0xD110 - 0xD11F</td></tr> 240 <tr> 241 <td align=left>            <A HREF="#TX_FED Registers">TX_FED: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD110 - 0xD11E</td><td align=center>0xD110 - 0xD11E</td></tr> 242 <tr> 243 <td align=left>      <b>pll_cal_blk</b></td><td align=center>0xD120 - 0xD12F</td><td align=center>0xD120 - 0xD12F</td></tr> 244 <tr> 245 <td align=left>            <A HREF="#PLL_CAL_COM Registers">PLL_CAL_COM: common register block for all lanes</A></td><td align=center>0xD120 - 0xD12E</td><td align=center>0xD120 - 0xD12E</td></tr> 246 <tr> 247 <td align=left>      <b>txcom_blk</b></td><td align=center>0xD130 - 0xD13F</td><td align=center>0xD130 - 0xD13F</td></tr> 248 <tr> 249 <td align=left>            <A HREF="#TX_COM Registers">TX_COM: common register block for all lanes</A></td><td align=center>0xD130 - 0xD131</td><td align=center>0xD130 - 0xD131</td></tr> 250 <tr> 251 <td align=left>      <b>dsc_f_blk</b></td><td align=center>0xD140 - 0xD14F</td><td align=center>0xD140 - 0xD14F</td></tr> 252 <tr> 253 <td align=left>            <A HREF="#DSC_F Registers">DSC_F: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD140 - 0xD147</td><td align=center>0xD140 - 0xD147</td></tr> 254 <tr> 255 <td align=left>      <b>digcom_b_blk</b></td><td align=center>0xD150 - 0xD15F</td><td align=center>0xD150 - 0xD15F</td></tr> 256 <tr> 257 <td align=left>            <A HREF="#DIG_COM_B Registers">DIG_COM_B: common register block for all lanes</A></td><td align=center>0xD150 - 0xD153</td><td align=center>0xD150 - 0xD153</td></tr> 258 <tr> 259 <td align=left>      <b>ckrst_ctrl_blk</b></td><td align=center>0xD160 - 0xD19F</td><td align=center>0xD160 - 0xD19F</td></tr> 260 <tr> 261 <td align=left>            <A HREF="#RX_CKRST_CTRL Registers">RX_CKRST_CTRL: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD160 - 0xD16C</td><td align=center>0xD160 - 0xD16C</td></tr> 262 <tr> 263 <td align=left>            <A HREF="#TX_CKRST_CTRL Registers">TX_CKRST_CTRL: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD170 - 0xD17D</td><td align=center>0xD170 - 0xD17D</td></tr> 264 <tr> 265 <td align=left>            <A HREF="#RXCOM_CKRST_CTRL Registers">RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD180 - 0xD18E</td><td align=center>0xD180 - 0xD18E</td></tr> 266 <tr> 267 <td align=left>            <A HREF="#TXCOM_CKRST_CTRL Registers">TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD190 - 0xD19E</td><td align=center>0xD190 - 0xD19E</td></tr> 268 <tr> 269 <td align=left>      <b>tx_tca_blk</b></td><td align=center>0xD1A0 - 0xD1AF</td><td align=center>0xD1A0 - 0xD1AF</td></tr> 270 <tr> 271 <td align=left>            <A HREF="#TX_TCA Registers">TX_TCA: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD1A0 - 0xD1A6</td><td align=center>0xD1A0 - 0xD1A6</td></tr> 272 <tr> 273 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0xD1B0 - 0xD1FF</td><td align=center>0xD1B0 - 0xD1FF</td></tr> 274 <tr> 275 <td align=left>      <b>micro_blk</b></td><td align=center>0xD200 - 0xD25F</td><td align=center>0xD200 - 0xD25F</td></tr> 276 <tr> 277 <td align=left>            <A HREF="#MICRO_A_COM Registers">MICRO_A_COM: common register block for all lanes within each Micro Top</A></td><td align=center>0xD200 - 0xD20E</td><td align=center>0xD200 - 0xD20E</td></tr> 278 <tr> 279 <td align=left>            <A HREF="#MICRO_B_COM Registers">MICRO_B_COM: common register block for all lanes within each Micro Top</A></td><td align=center>0xD210 - 0xD21B</td><td align=center>0xD210 - 0xD21B</td></tr> 280 <tr> 281 <td align=left>            <A HREF="#MICRO_C_COM Registers">MICRO_C_COM: common register block for all lanes within each Micro Top</A></td><td align=center>0xD220 - 0xD22A</td><td align=center>0xD220 - 0xD22A</td></tr> 282 <tr> 283 <td align=left>            <A HREF="#MICRO_INFO_COM Registers">MICRO_INFO_COM: Status Register for all Lanes  within each Micro Top</A></td><td align=center>0xD230 - 0xD231</td><td align=center>0xD230 - 0xD231</td></tr> 284 <tr> 285 <td align=left>            <A HREF="#MICRO_CTRL0 Registers">MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top</A></td><td align=center>0xD240 - 0xD247</td><td align=center>0xD240 - 0xD247</td></tr> 286 <tr> 287 <td align=left>            <A HREF="#MICRO_DBG Registers">MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top</A></td><td align=center>0xD250 - 0xD25E</td><td align=center>0xD250 - 0xD25E</td></tr> 288 <tr> 289 <td align=left>      <b>dsc_g_j_blk</b></td><td align=center>0xD260 - 0xD29F</td><td align=center>0xD260 - 0xD29F</td></tr> 290 <tr> 291 <td align=left>            <A HREF="#DSC_G Registers">DSC_G: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD260 - 0xD26E</td><td align=center>0xD260 - 0xD26E</td></tr> 292 <tr> 293 <td align=left>            <A HREF="#DSC_H Registers">DSC_H: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD270 - 0xD275</td><td align=center>0xD270 - 0xD275</td></tr> 294 <tr> 295 <td align=left>            <A HREF="#DSC_I Registers">DSC_I: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD280 - 0xD28E</td><td align=center>0xD280 - 0xD28E</td></tr> 296 <tr> 297 <td align=left>            <A HREF="#DSC_J Registers">DSC_J: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD290 - 0xD29E</td><td align=center>0xD290 - 0xD29E</td></tr> 298 <tr> 299 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0xD2A0 - 0xD2FF</td><td align=center>0xD2A0 - 0xD2FF</td></tr> 300 <tr> 301 <td align=left>      <b>tx_coeff_blk</b></td><td align=center>0xD300 - 0xD35F</td><td align=center>0xD300 - 0xD35F</td></tr> 302 <tr> 303 <td align=left>            <A HREF="#TX_COEFF_MAIN Registers">TX_COEFF_MAIN: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD300 - 0xD305</td><td align=center>0xD300 - 0xD305</td></tr> 304 <tr> 305 <td align=left>            <A HREF="#TX_COEFF_PM Registers">TX_COEFF_PM: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD310 - 0xD317</td><td align=center>0xD310 - 0xD317</td></tr> 306 <tr> 307 <td align=left>            <A HREF="#TX_COEFF_POST Registers">TX_COEFF_POST: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD320 - 0xD325</td><td align=center>0xD320 - 0xD325</td></tr> 308 <tr> 309 <td align=left>            <A HREF="#TX_COEFF_POSTA Registers">TX_COEFF_POSTA: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD330 - 0xD33E</td><td align=center>0xD330 - 0xD33E</td></tr> 310 <tr> 311 <td align=left>            <A HREF="#TX_COEFF_POSTB Registers">TX_COEFF_POSTB: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD340 - 0xD34A</td><td align=center>0xD340 - 0xD34A</td></tr> 312 <tr> 313 <td align=left>            <A HREF="#TX_COEFF_PRE Registers">TX_COEFF_PRE: per lane register block [One Copy Per Lane]</A></td><td align=center>0xD350 - 0xD355</td><td align=center>0xD350 - 0xD355</td></tr> 314 <tr> 315 <td bgcolor=#CCCCCC align=left>      Reserved</td><td align=center>0xD360 - 0xFFCF</td><td align=center>0xD360 - 0xFFCF</td></tr> 316 <tr> 317 <td align=left>      <b>mdio</b></td><td align=center>0xFFD0 - 0xFFDF</td><td align=center>0xFFD0 - 0xFFDF</td></tr> 318 <tr> 319 <td align=left>            <A HREF="#MDIO_MMDSEL_AER_COM Registers">MDIO_MMDSEL_AER_COM: common register block for all lanes</A></td><td align=center>0xFFD0 - 0xFFDE</td><td align=center>0xFFD0 - 0xFFDE</td></tr> 320 <tr> 321 <td align=left>            <A HREF="#MDIO_BLK_ADDR_COM Registers">MDIO_BLK_ADDR_COM: common register block for all lanes</A></td><td align=center>0xFFD0 - 0xFFDF</td><td align=center>0xFFD0 - 0xFFDF</td></tr> 322 </table><p> 323 <hr> 324 <H1><a NAME="REGISTER_INFO_EXT Registers">REGISTER_INFO_EXT Registers</a></H1> 325 <table border=1 align=center width=100% cellpadding=0> 326 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 327 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 328 <tr> 329 <td align=center>0x0000</td><td><A HREF="#REGISTER_INFO_EXT_INFO">REGISTER_INFO_EXT_INFO</A><br>Register Setup Information</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">reg_desc</div> </td> <td align=center>16'h0000</td></tr> 330 </table><p> 331 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 332 <hr> 333 <b><a NAME="REGISTER_INFO_EXT_INFO">REGISTER_INFO_EXT_INFO - Register Setup Information</a></b><br> 334 Address Offset = 32'h0000_0000<br> 335 Physical Address = 32'h0000_0000<br> 336 Reset Value = 16'h0000<br> 337 Access = RW (16-bit only)<br> 338 <table border=1 align=center width=100% cellpadding=0> 339 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 340 <tr bgcolor=WHITE> 341 <td bgcolor=WHITE align=center valign=top>15:00</td> 342 <td align=left valign=top>RW</td> 343 <td align=left valign=top>reg_desc</td> 344 <td align=left> 345 The following info describes the mapping of the registers<br> 346   Block addressing description<br> 347     - This spreadsheet defines all registers as 16'h0000, but is broken down as:<br> 348       Block [15:4] <br> 349       Lane   [7:4] <br> 350       Reg    [3:0] <br> 351         i.e. <br> 352         access PCIE 0x1102<br> 353         block - 0x110<br> 354         lane -  0x0, for this register lane is not valid and value applies to all lanes<br> 355         reg -   0x12, the '1' is added to indicate SERDES register. <br> 356   There are 2 types of registers:<br> 357     1. General registers that apply to all lanes<br> 358     2. Lane specific registers<br> 359 Reset value is 0x0.</td></tr> 360 </table><p> 361 <A HREF="#REGISTER_INFO_EXT Registers">Return to REGISTER_INFO_EXT Table</A><p> 362 <hr> 363 <H1><a NAME="PCIE_BLK0_EXT Registers">PCIE_BLK0_EXT Registers</a></H1> 364 <table border=1 align=center width=100% cellpadding=0> 365 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 366 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 367 <tr> 368 <td align=center>0x1000</td><td><A HREF="#PCIE_BLK0_EXT_CTRL1">PCIE_BLK0_EXT_CTRL1</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rst_sw</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rst_sw_UC</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rst_sw_MDIO</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pwrdwn_sw_10g</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_tca_master_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_tca_master_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_rx_hiz_disable</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ucclk_sel</div> </td> <td align=center>16'h0000</td></tr> 369 <tr> 370 <td align=center>0x1001</td><td>PCIE_BLK0_EXT_CTRL2<br>Register</td><td bgcolor=#CCCCCC align=center colspan="16"><div class="HT">reserved</div> </td> <td align=center>16'h0000</td></tr> 371 <tr> 372 <td align=center>0x1002</td><td>PCIE_BLK0_EXT_CTRL3<br>Register</td><td bgcolor=#CCCCCC align=center colspan="16"><div class="HT">reserved</div> </td> <td align=center>16'h0000</td></tr> 373 <tr> 374 <td align=center>0x1003</td><td><A HREF="#PCIE_BLK0_EXT_RXSIGDET">PCIE_BLK0_EXT_RXSIGDET</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rxsigdet</div> </td> <td align=center>16'h0000</td></tr> 375 <tr> 376 <td align=center>0x1004</td><td><A HREF="#PCIE_BLK0_EXT_LNSTATUS">PCIE_BLK0_EXT_LNSTATUS</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">ln_status</div> </td> <td align=center>16'h0000</td></tr> 377 <tr> 378 <td align=center>0x1005</td><td><A HREF="#PCIE_BLK0_EXT_LNSTATUS2">PCIE_BLK0_EXT_LNSTATUS2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">ln_status2</div> </td> <td align=center>16'h0000</td></tr> 379 <tr> 380 <td align=center>0x1006</td><td><A HREF="#PCIE_BLK0_EXT_MDIO_CTRL0">PCIE_BLK0_EXT_MDIO_CTRL0</A><br>StandAloneMode Override</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ser_SAM_ovrd</div> </td> <td align=center>16'h0000</td></tr> 381 <tr> 382 <td align=center>0x1007</td><td><A HREF="#PCIE_BLK0_EXT_RATE_SEL_STAT">PCIE_BLK0_EXT_RATE_SEL_STAT</A><br>RateSelect Status</td><td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">PllRangeHolding_status</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">PllRangeHolding_G3_status</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rate_sel_status</div> </td> <td align=center>16'h0000</td></tr> 383 </table><p> 384 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 385 <hr> 386 <b><a NAME="PCIE_BLK0_EXT_CTRL1">PCIE_BLK0_EXT_CTRL1 - Register</a></b><br> 387 Address Offset = 32'h0000_1000<br> 388 Physical Address = 32'h0000_1000<br> 389 Reset Value = 16'h0000<br> 390 Access = RW (16-bit only)<br> 391 <table border=1 align=center width=100% cellpadding=0> 392 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 393 <tr bgcolor=WHITE> 394 <td bgcolor=WHITE align=center valign=top>15</td> 395 <td align=left valign=top>RW</td> 396 <td align=left valign=top>rst_sw</td> 397 <td align=left> 398 When set will initiate logic reset and will be cleared after 16 refclks by resetting this register<br> 399 Reset value is 0x0.</td></tr> 400 <tr bgcolor=WHITE> 401 <td bgcolor=WHITE align=center valign=top>14</td> 402 <td align=left valign=top>RW</td> 403 <td align=left valign=top>rst_sw_UC</td> 404 <td align=left> 405 Will reset the MicroController and will be cleared same as bit 15<br> 406 Reset value is 0x0.</td></tr> 407 <tr bgcolor=WHITE> 408 <td bgcolor=WHITE align=center valign=top>13</td> 409 <td align=left valign=top>RW</td> 410 <td align=left valign=top>rst_sw_MDIO</td> 411 <td align=left> 412 Will reset the MDIO and will be cleared same as bit 15<br> 413 Reset value is 0x0.</td></tr> 414 <tr bgcolor=WHITE> 415 <td bgcolor=WHITE align=center valign=top>12</td> 416 <td align=left valign=top>RSVD</td> 417 <td align=left valign=top>Reserved</td> 418 <td align=left> 419 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 420 <tr bgcolor=WHITE> 421 <td bgcolor=WHITE align=center valign=top>11</td> 422 <td align=left valign=top>RW</td> 423 <td align=left valign=top>pwrdwn_sw_10g</td> 424 <td align=left> 425 tbd<br> 426 Reset value is 0x0.</td></tr> 427 <tr bgcolor=WHITE> 428 <td bgcolor=WHITE align=center valign=top>10:04</td> 429 <td align=left valign=top>RSVD</td> 430 <td align=left valign=top>Reserved</td> 431 <td align=left> 432 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 433 <tr bgcolor=WHITE> 434 <td bgcolor=WHITE align=center valign=top>03</td> 435 <td align=left valign=top>RW</td> 436 <td align=left valign=top>pll_tca_master_frc</td> 437 <td align=left> 438 force pll_ctrl[164]<br> 439 Reset value is 0x0.</td></tr> 440 <tr bgcolor=WHITE> 441 <td bgcolor=WHITE align=center valign=top>02</td> 442 <td align=left valign=top>RW</td> 443 <td align=left valign=top>pll_tca_master_frc_val</td> 444 <td align=left> 445 force pll_ctrl[164] value<br> 446 Reset value is 0x0.</td></tr> 447 <tr bgcolor=WHITE> 448 <td bgcolor=WHITE align=center valign=top>01</td> 449 <td align=left valign=top>RW</td> 450 <td align=left valign=top>mdio_rx_hiz_disable</td> 451 <td align=left> 452 mdio_rx_hiz_disable: 0=rx=hiZ during perst#(default), 1=rx=normal<br> 453 Reset value is 0x0.</td></tr> 454 <tr bgcolor=WHITE> 455 <td bgcolor=WHITE align=center valign=top>00</td> 456 <td align=left valign=top>RW</td> 457 <td align=left valign=top>mdio_ucclk_sel</td> 458 <td align=left> 459 mdio_ucclk_sel: 0=refclk2x, 1=250MHz<br> 460 Reset value is 0x0.</td></tr> 461 </table><p> 462 <A HREF="#PCIE_BLK0_EXT Registers">Return to PCIE_BLK0_EXT Table</A><p> 463 <hr> 464 <b><a NAME="PCIE_BLK0_EXT_RXSIGDET">PCIE_BLK0_EXT_RXSIGDET - Register</a></b><br> 465 Address Offset = 32'h0000_1003<br> 466 Physical Address = 32'h0000_1003<br> 467 Reset Value = 16'h0000<br> 468 Access = RO (16-bit only)<br> 469 <table border=1 align=center width=100% cellpadding=0> 470 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 471 <tr bgcolor=WHITE> 472 <td bgcolor=WHITE align=center valign=top>15:00</td> 473 <td align=left valign=top>RO</td> 474 <td align=left valign=top>rxsigdet</td> 475 <td align=left> 476 tbd<br> 477 Reset value is 0x0.</td></tr> 478 </table><p> 479 <A HREF="#PCIE_BLK0_EXT Registers">Return to PCIE_BLK0_EXT Table</A><p> 480 <hr> 481 <b><a NAME="PCIE_BLK0_EXT_LNSTATUS">PCIE_BLK0_EXT_LNSTATUS - Register</a></b><br> 482 Address Offset = 32'h0000_1004<br> 483 Physical Address = 32'h0000_1004<br> 484 Reset Value = 16'h0000<br> 485 Access = RO (16-bit only)<br> 486 <table border=1 align=center width=100% cellpadding=0> 487 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 488 <tr bgcolor=WHITE> 489 <td bgcolor=WHITE align=center valign=top>15:00</td> 490 <td align=left valign=top>RO</td> 491 <td align=left valign=top>ln_status</td> 492 <td align=left> 493 tbd<br> 494 Reset value is 0x0.</td></tr> 495 </table><p> 496 <A HREF="#PCIE_BLK0_EXT Registers">Return to PCIE_BLK0_EXT Table</A><p> 497 <hr> 498 <b><a NAME="PCIE_BLK0_EXT_LNSTATUS2">PCIE_BLK0_EXT_LNSTATUS2 - Register</a></b><br> 499 Address Offset = 32'h0000_1005<br> 500 Physical Address = 32'h0000_1005<br> 501 Reset Value = 16'h0000<br> 502 Access = RO (16-bit only)<br> 503 <table border=1 align=center width=100% cellpadding=0> 504 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 505 <tr bgcolor=WHITE> 506 <td bgcolor=WHITE align=center valign=top>15:00</td> 507 <td align=left valign=top>RO</td> 508 <td align=left valign=top>ln_status2</td> 509 <td align=left> 510 tbd<br> 511 Reset value is 0x0.</td></tr> 512 </table><p> 513 <A HREF="#PCIE_BLK0_EXT Registers">Return to PCIE_BLK0_EXT Table</A><p> 514 <hr> 515 <b><a NAME="PCIE_BLK0_EXT_MDIO_CTRL0">PCIE_BLK0_EXT_MDIO_CTRL0 - StandAloneMode Override</a></b><br> 516 Address Offset = 32'h0000_1006<br> 517 Physical Address = 32'h0000_1006<br> 518 Reset Value = 16'h0000<br> 519 Access = RW (16-bit only)<br> 520 <table border=1 align=center width=100% cellpadding=0> 521 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 522 <tr bgcolor=WHITE> 523 <td bgcolor=WHITE align=center valign=top>15:01</td> 524 <td align=left valign=top>RSVD</td> 525 <td align=left valign=top>Reserved</td> 526 <td align=left> 527 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 528 <tr bgcolor=WHITE> 529 <td bgcolor=WHITE align=center valign=top>00</td> 530 <td align=left valign=top>RW</td> 531 <td align=left valign=top>mdio_ser_SAM_ovrd</td> 532 <td align=left> 533 Setting this bit will FLIP the StandAloneMode bit for MDIO controls ONLY<br> 534 StandAloneMode^mdio_ser_SAM_ovrd<br> 535       0^0 = 0<br> 536       0^1 = 1<br> 537       1^0 = 1<br> 538       1^1 = 0<br> 539 Reset value is 0x0.</td></tr> 540 </table><p> 541 <A HREF="#PCIE_BLK0_EXT Registers">Return to PCIE_BLK0_EXT Table</A><p> 542 <hr> 543 <b><a NAME="PCIE_BLK0_EXT_RATE_SEL_STAT">PCIE_BLK0_EXT_RATE_SEL_STAT - RateSelect Status</a></b><br> 544 Address Offset = 32'h0000_1007<br> 545 Physical Address = 32'h0000_1007<br> 546 Reset Value = 16'h0000<br> 547 Access = RO (16-bit only)<br> 548 <table border=1 align=center width=100% cellpadding=0> 549 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 550 <tr bgcolor=WHITE> 551 <td bgcolor=WHITE align=center valign=top>15:09</td> 552 <td align=left valign=top>RO</td> 553 <td align=left valign=top>PllRangeHolding_status</td> 554 <td align=left> 555 Pll range value in Gen1/Gen2<br> 556 Reset value is 0x0.</td></tr> 557 <tr bgcolor=WHITE> 558 <td bgcolor=WHITE align=center valign=top>08:02</td> 559 <td align=left valign=top>RO</td> 560 <td align=left valign=top>PllRangeHolding_G3_status</td> 561 <td align=left> 562 Pll range value in Gen3<br> 563 Reset value is 0x0.</td></tr> 564 <tr bgcolor=WHITE> 565 <td bgcolor=WHITE align=center valign=top>01:00</td> 566 <td align=left valign=top>RO</td> 567 <td align=left valign=top>rate_sel_status</td> 568 <td align=left> 569 Rate Select Status<br> 570   00 = Gen1<br> 571   01 = Gen2<br> 572   10 = Gen3<br> 573 Reset value is 0x0.</td></tr> 574 </table><p> 575 <A HREF="#PCIE_BLK0_EXT Registers">Return to PCIE_BLK0_EXT Table</A><p> 576 <hr> 577 <H1><a NAME="PCIE_BLK1_EXT Registers">PCIE_BLK1_EXT Registers</a></H1> 578 <table border=1 align=center width=100% cellpadding=0> 579 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 580 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 581 <tr> 582 <td align=center>0x1100</td><td><A HREF="#PCIE_BLK1_EXT_CONTROL">PCIE_BLK1_EXT_CONTROL</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pgen_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pcmp_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">start_sequencer</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">reset_anlg_r</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_bypass_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_iddq_ovrd_select</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_iddq_ovrd_value</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_cont_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdet_en10g</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eden10g</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_reset_enable</div> </td> <td align=center>16'h200c</td></tr> 583 <tr> 584 <td align=center>0x1101</td><td><A HREF="#PCIE_BLK1_EXT_STATUS">PCIE_BLK1_EXT_STATUS</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">status</div> </td> <td align=center>16'h8000</td></tr> 585 <tr> 586 <td align=center>0x1102</td><td><A HREF="#PCIE_BLK1_EXT_MISCCONTROL1">PCIE_BLK1_EXT_MISCCONTROL1</A><br>Register</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">enable_uC_freeze</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">deassert_ResetUc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">L1PLLPowerdown_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">L1PLLPowerdown_mdio</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">BlockRealignOverride</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_G3_BlockRealign</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_G3_fts_SDS</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_G3_fts_no_EIEOS</div> </td> <td align=center>16'h0000</td></tr> 587 <tr> 588 <td align=center>0x1103</td><td><A HREF="#PCIE_BLK1_EXT_STATUS_REG2">PCIE_BLK1_EXT_STATUS_REG2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">status2</div> </td> <td align=center>16'h0000</td></tr> 589 <tr> 590 <td align=center>0x1104</td><td><A HREF="#PCIE_BLK1_EXT_GPIO_CTRL0">PCIE_BLK1_EXT_GPIO_CTRL0</A><br>GPIO Status Select Control Register</td><td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="9"><div class="HT">gpio_sel</div> </td> <td align=center>16'h0000</td></tr> 591 <tr> 592 <td align=center>0x1105</td><td><A HREF="#PCIE_BLK1_EXT_GPIO_STATUS0">PCIE_BLK1_EXT_GPIO_STATUS0</A><br>GPIO Status Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_gpio_sts</div> </td> <td align=center>16'h0000</td></tr> 593 <tr> 594 <td align=center>0x1106</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL0">PCIE_BLK1_EXT_DBG_CTRL0</A><br>Debug Data Control 0 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel0</div> </td> <td align=center>16'h3210</td></tr> 595 <tr> 596 <td align=center>0x1107</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL1">PCIE_BLK1_EXT_DBG_CTRL1</A><br>Debug Data Control 1 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel7</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel6</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel5</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel4</div> </td> <td align=center>16'h7654</td></tr> 597 <tr> 598 <td align=center>0x1108</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL2">PCIE_BLK1_EXT_DBG_CTRL2</A><br>Debug Data Control 2 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel11</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel10</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel9</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel8</div> </td> <td align=center>16'hba98</td></tr> 599 <tr> 600 <td align=center>0x1109</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL3">PCIE_BLK1_EXT_DBG_CTRL3</A><br>Debug Data Control 3 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel15</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel14</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel13</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_lane_sel12</div> </td> <td align=center>16'hfedc</td></tr> 601 <tr> 602 <td align=center>0x110A</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL4">PCIE_BLK1_EXT_DBG_CTRL4</A><br>Debug Data Control 0 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel0</div> </td> <td align=center>16'h3210</td></tr> 603 <tr> 604 <td align=center>0x110B</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL5">PCIE_BLK1_EXT_DBG_CTRL5</A><br>Debug Data Control 1 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel7</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel6</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel5</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel4</div> </td> <td align=center>16'h7654</td></tr> 605 <tr> 606 <td align=center>0x110C</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL6">PCIE_BLK1_EXT_DBG_CTRL6</A><br>Debug Data Control 2 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel11</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel10</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel9</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel8</div> </td> <td align=center>16'hba98</td></tr> 607 <tr> 608 <td align=center>0x110D</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL7">PCIE_BLK1_EXT_DBG_CTRL7</A><br>Debug Data Control 3 Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel15</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel14</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel13</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dbg_info_sel12</div> </td> <td align=center>16'hfedc</td></tr> 609 <tr> 610 <td align=center>0x110E</td><td><A HREF="#PCIE_BLK1_EXT_DBG_CTRL8">PCIE_BLK1_EXT_DBG_CTRL8</A><br>Debug Data Control 3 Register</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dbg_misc_tmux_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dbg_data_ena</div> </td> <td align=center>16'h0000</td></tr> 611 </table><p> 612 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 613 <hr> 614 <b><a NAME="PCIE_BLK1_EXT_CONTROL">PCIE_BLK1_EXT_CONTROL - Register</a></b><br> 615 Address Offset = 32'h0000_1100<br> 616 Physical Address = 32'h0000_1100<br> 617 Reset Value = 16'h200c<br> 618 Access = RW (16-bit only)<br> 619 <table border=1 align=center width=100% cellpadding=0> 620 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 621 <tr bgcolor=WHITE> 622 <td bgcolor=WHITE align=center valign=top>15</td> 623 <td align=left valign=top>RW</td> 624 <td align=left valign=top>pgen_en</td> 625 <td align=left> 626 Reset value is 0x0.</td></tr> 627 <tr bgcolor=WHITE> 628 <td bgcolor=WHITE align=center valign=top>14</td> 629 <td align=left valign=top>RW</td> 630 <td align=left valign=top>pcmp_en</td> 631 <td align=left> 632 Reset value is 0x0.</td></tr> 633 <tr bgcolor=WHITE> 634 <td bgcolor=WHITE align=center valign=top>13</td> 635 <td align=left valign=top>RW</td> 636 <td align=left valign=top>start_sequencer</td> 637 <td align=left> 638 Reset value is 0x1.</td></tr> 639 <tr bgcolor=WHITE> 640 <td bgcolor=WHITE align=center valign=top>12</td> 641 <td align=left valign=top>RW</td> 642 <td align=left valign=top>reset_anlg_r</td> 643 <td align=left> 644 Reset value is 0x0.</td></tr> 645 <tr bgcolor=WHITE> 646 <td bgcolor=WHITE align=center valign=top>11:08</td> 647 <td align=left valign=top>RSVD</td> 648 <td align=left valign=top>Reserved</td> 649 <td align=left> 650 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 651 <tr bgcolor=WHITE> 652 <td bgcolor=WHITE align=center valign=top>07</td> 653 <td align=left valign=top>RW</td> 654 <td align=left valign=top>pll_bypass_r</td> 655 <td align=left> 656 Reset value is 0x0.</td></tr> 657 <tr bgcolor=WHITE> 658 <td bgcolor=WHITE align=center valign=top>06</td> 659 <td align=left valign=top>RW</td> 660 <td align=left valign=top>mdio_iddq_ovrd_select</td> 661 <td align=left> 662 1= use the mdio_iddq_ovrd_value for Iddq_SAM <br> 663 Reset value is 0x0.</td></tr> 664 <tr bgcolor=WHITE> 665 <td bgcolor=WHITE align=center valign=top>05</td> 666 <td align=left valign=top>RW</td> 667 <td align=left valign=top>mdio_iddq_ovrd_value</td> 668 <td align=left> 669 value to be used when mdio_iddq_ovrd_select is high<br> 670 Reset value is 0x0.</td></tr> 671 <tr bgcolor=WHITE> 672 <td bgcolor=WHITE align=center valign=top>04</td> 673 <td align=left valign=top>RW</td> 674 <td align=left valign=top>mdio_cont_en</td> 675 <td align=left> 676 Reset value is 0x0.</td></tr> 677 <tr bgcolor=WHITE> 678 <td bgcolor=WHITE align=center valign=top>03</td> 679 <td align=left valign=top>RW</td> 680 <td align=left valign=top>cdet_en10g</td> 681 <td align=left> 682 Reset value is 0x1.</td></tr> 683 <tr bgcolor=WHITE> 684 <td bgcolor=WHITE align=center valign=top>02</td> 685 <td align=left valign=top>RW</td> 686 <td align=left valign=top>eden10g</td> 687 <td align=left> 688 Reset value is 0x1.</td></tr> 689 <tr bgcolor=WHITE> 690 <td bgcolor=WHITE align=center valign=top>01</td> 691 <td align=left valign=top>RSVD</td> 692 <td align=left valign=top>Reserved</td> 693 <td align=left> 694 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 695 <tr bgcolor=WHITE> 696 <td bgcolor=WHITE align=center valign=top>00</td> 697 <td align=left valign=top>RW</td> 698 <td align=left valign=top>dsc_reset_enable</td> 699 <td align=left> 700 1'b0: DSC will not reset when pll lock is broken.<br> 701 1'b1: DSC will reset when pll lock is broken.<br> 702 Reset value is 0x0.</td></tr> 703 </table><p> 704 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 705 <hr> 706 <b><a NAME="PCIE_BLK1_EXT_STATUS">PCIE_BLK1_EXT_STATUS - Register</a></b><br> 707 Address Offset = 32'h0000_1101<br> 708 Physical Address = 32'h0000_1101<br> 709 Reset Value = 16'h8000<br> 710 Access = RO (16-bit only)<br> 711 <table border=1 align=center width=100% cellpadding=0> 712 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 713 <tr bgcolor=WHITE> 714 <td bgcolor=WHITE align=center valign=top>15:00</td> 715 <td align=left valign=top>RO</td> 716 <td align=left valign=top>status</td> 717 <td align=left> 718 tbd<br> 719 Reset value is 0x8000.</td></tr> 720 </table><p> 721 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 722 <hr> 723 <b><a NAME="PCIE_BLK1_EXT_MISCCONTROL1">PCIE_BLK1_EXT_MISCCONTROL1 - Register</a></b><br> 724 Address Offset = 32'h0000_1102<br> 725 Physical Address = 32'h0000_1102<br> 726 Reset Value = 16'h0000<br> 727 Access = RW (16-bit only)<br> 728 <table border=1 align=center width=100% cellpadding=0> 729 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 730 <tr bgcolor=WHITE> 731 <td bgcolor=WHITE align=center valign=top>15:08</td> 732 <td align=left valign=top>RSVD</td> 733 <td align=left valign=top>Reserved</td> 734 <td align=left> 735 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 736 <tr bgcolor=WHITE> 737 <td bgcolor=WHITE align=center valign=top>07</td> 738 <td align=left valign=top>RW</td> 739 <td align=left valign=top>enable_uC_freeze</td> 740 <td align=left> 741 enable uC/pcb freeze<br> 742 Reset value is 0x0.</td></tr> 743 <tr bgcolor=WHITE> 744 <td bgcolor=WHITE align=center valign=top>06</td> 745 <td align=left valign=top>RW</td> 746 <td align=left valign=top>deassert_ResetUc</td> 747 <td align=left> 748 deassert_ResetUc<br> 749 Reset value is 0x0.</td></tr> 750 <tr bgcolor=WHITE> 751 <td bgcolor=WHITE align=center valign=top>05</td> 752 <td align=left valign=top>RW</td> 753 <td align=left valign=top>L1PLLPowerdown_sel</td> 754 <td align=left> 755 L1PLLPowerdown_mdio_sel<br> 756 Reset value is 0x0.</td></tr> 757 <tr bgcolor=WHITE> 758 <td bgcolor=WHITE align=center valign=top>04</td> 759 <td align=left valign=top>RW</td> 760 <td align=left valign=top>L1PLLPowerdown_mdio</td> 761 <td align=left> 762 L1PLLPowerdown_mdio<br> 763 Reset value is 0x0.</td></tr> 764 <tr bgcolor=WHITE> 765 <td bgcolor=WHITE align=center valign=top>03</td> 766 <td align=left valign=top>RW</td> 767 <td align=left valign=top>BlockRealignOverride</td> 768 <td align=left> 769 Reset value is 0x0.</td></tr> 770 <tr bgcolor=WHITE> 771 <td bgcolor=WHITE align=center valign=top>02</td> 772 <td align=left valign=top>RW</td> 773 <td align=left valign=top>mdio_G3_BlockRealign</td> 774 <td align=left> 775 Reset value is 0x0.</td></tr> 776 <tr bgcolor=WHITE> 777 <td bgcolor=WHITE align=center valign=top>01</td> 778 <td align=left valign=top>RW</td> 779 <td align=left valign=top>tx_G3_fts_SDS</td> 780 <td align=left> 781 Reset value is 0x0.</td></tr> 782 <tr bgcolor=WHITE> 783 <td bgcolor=WHITE align=center valign=top>00</td> 784 <td align=left valign=top>RW</td> 785 <td align=left valign=top>tx_G3_fts_no_EIEOS</td> 786 <td align=left> 787 Reset value is 0x0.</td></tr> 788 </table><p> 789 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 790 <hr> 791 <b><a NAME="PCIE_BLK1_EXT_STATUS_REG2">PCIE_BLK1_EXT_STATUS_REG2 - Register</a></b><br> 792 Address Offset = 32'h0000_1103<br> 793 Physical Address = 32'h0000_1103<br> 794 Reset Value = 16'h0000<br> 795 Access = RO (16-bit only)<br> 796 <table border=1 align=center width=100% cellpadding=0> 797 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 798 <tr bgcolor=WHITE> 799 <td bgcolor=WHITE align=center valign=top>15:00</td> 800 <td align=left valign=top>RO</td> 801 <td align=left valign=top>status2</td> 802 <td align=left> 803 tbd<br> 804 Reset value is 0x0.</td></tr> 805 </table><p> 806 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 807 <hr> 808 <b><a NAME="PCIE_BLK1_EXT_GPIO_CTRL0">PCIE_BLK1_EXT_GPIO_CTRL0 - GPIO Status Select Control Register</a></b><br> 809 Address Offset = 32'h0000_1104<br> 810 Physical Address = 32'h0000_1104<br> 811 Reset Value = 16'h0000<br> 812 Access = RW (16-bit only)<br> 813 <table border=1 align=center width=100% cellpadding=0> 814 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 815 <tr bgcolor=WHITE> 816 <td bgcolor=WHITE align=center valign=top>15:09</td> 817 <td align=left valign=top>RSVD</td> 818 <td align=left valign=top>Reserved</td> 819 <td align=left> 820 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 821 <tr bgcolor=WHITE> 822 <td bgcolor=WHITE align=center valign=top>08:00</td> 823 <td align=left valign=top>RW</td> 824 <td align=left valign=top>gpio_sel</td> 825 <td align=left> 826 Selects which GPIO Status to view<br> 827 Reset value is 0x0.</td></tr> 828 </table><p> 829 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 830 <hr> 831 <b><a NAME="PCIE_BLK1_EXT_GPIO_STATUS0">PCIE_BLK1_EXT_GPIO_STATUS0 - GPIO Status Register</a></b><br> 832 Address Offset = 32'h0000_1105<br> 833 Physical Address = 32'h0000_1105<br> 834 Reset Value = 16'h0000<br> 835 Access = RO (16-bit only)<br> 836 <table border=1 align=center width=100% cellpadding=0> 837 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 838 <tr bgcolor=WHITE> 839 <td bgcolor=WHITE align=center valign=top>15:00</td> 840 <td align=left valign=top>RO</td> 841 <td align=left valign=top>mdio_gpio_sts</td> 842 <td align=left> 843 Reset value is 0x0.</td></tr> 844 </table><p> 845 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 846 <hr> 847 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL0">PCIE_BLK1_EXT_DBG_CTRL0 - Debug Data Control 0 Register</a></b><br> 848 Address Offset = 32'h0000_1106<br> 849 Physical Address = 32'h0000_1106<br> 850 Reset Value = 16'h3210<br> 851 Access = RW (16-bit only)<br> 852 <table border=1 align=center width=100% cellpadding=0> 853 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 854 <tr bgcolor=WHITE> 855 <td bgcolor=WHITE align=center valign=top>15:12</td> 856 <td align=left valign=top>RW</td> 857 <td align=left valign=top>dbg_lane_sel3</td> 858 <td align=left> 859 Selects 16bits of lane debug info<br> 860 Reset value is 0x3.</td></tr> 861 <tr bgcolor=WHITE> 862 <td bgcolor=WHITE align=center valign=top>11:08</td> 863 <td align=left valign=top>RW</td> 864 <td align=left valign=top>dbg_lane_sel2</td> 865 <td align=left> 866 Selects 16bits of lane debug info<br> 867 Reset value is 0x2.</td></tr> 868 <tr bgcolor=WHITE> 869 <td bgcolor=WHITE align=center valign=top>07:04</td> 870 <td align=left valign=top>RW</td> 871 <td align=left valign=top>dbg_lane_sel1</td> 872 <td align=left> 873 Selects 16bits of lane debug info<br> 874 Reset value is 0x1.</td></tr> 875 <tr bgcolor=WHITE> 876 <td bgcolor=WHITE align=center valign=top>03:00</td> 877 <td align=left valign=top>RW</td> 878 <td align=left valign=top>dbg_lane_sel0</td> 879 <td align=left> 880 Selects 16bits of lane debug info<br> 881 4'h0 : lane 0  debug<br> 882 4'h1 : lane 1  debug<br> 883 4'h2 : lane 2  debug<br> 884 4'h3 : lane 3  debug<br> 885 4'h4 : lane 4  debug<br> 886 4'h5 : lane 5  debug<br> 887 4'h6 : lane 6  debug<br> 888 4'h7 : lane 7  debug<br> 889 4'h8 : lane 8  debug<br> 890 4'h9 : lane 9  debug<br> 891 4'ha : lane 10 debug<br> 892 4'hb : lane 11 debug<br> 893 4'hc : lane 12 debug<br> 894 4'hd : lane 13 debug<br> 895 4'he : lane 14 debug<br> 896 4'hf : lane 15 debug<br> 897 Reset value is 0x0.</td></tr> 898 </table><p> 899 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 900 <hr> 901 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL1">PCIE_BLK1_EXT_DBG_CTRL1 - Debug Data Control 1 Register</a></b><br> 902 Address Offset = 32'h0000_1107<br> 903 Physical Address = 32'h0000_1107<br> 904 Reset Value = 16'h7654<br> 905 Access = RW (16-bit only)<br> 906 <table border=1 align=center width=100% cellpadding=0> 907 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 908 <tr bgcolor=WHITE> 909 <td bgcolor=WHITE align=center valign=top>15:12</td> 910 <td align=left valign=top>RW</td> 911 <td align=left valign=top>dbg_lane_sel7</td> 912 <td align=left> 913 Selects 16bits of lane debug info<br> 914 Reset value is 0x7.</td></tr> 915 <tr bgcolor=WHITE> 916 <td bgcolor=WHITE align=center valign=top>11:08</td> 917 <td align=left valign=top>RW</td> 918 <td align=left valign=top>dbg_lane_sel6</td> 919 <td align=left> 920 Selects 16bits of lane debug info<br> 921 Reset value is 0x6.</td></tr> 922 <tr bgcolor=WHITE> 923 <td bgcolor=WHITE align=center valign=top>07:04</td> 924 <td align=left valign=top>RW</td> 925 <td align=left valign=top>dbg_lane_sel5</td> 926 <td align=left> 927 Selects 16bits of lane debug info<br> 928 Reset value is 0x5.</td></tr> 929 <tr bgcolor=WHITE> 930 <td bgcolor=WHITE align=center valign=top>03:00</td> 931 <td align=left valign=top>RW</td> 932 <td align=left valign=top>dbg_lane_sel4</td> 933 <td align=left> 934 Selects 16bits of lane debug info<br> 935 Reset value is 0x4.</td></tr> 936 </table><p> 937 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 938 <hr> 939 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL2">PCIE_BLK1_EXT_DBG_CTRL2 - Debug Data Control 2 Register</a></b><br> 940 Address Offset = 32'h0000_1108<br> 941 Physical Address = 32'h0000_1108<br> 942 Reset Value = 16'hba98<br> 943 Access = RW (16-bit only)<br> 944 <table border=1 align=center width=100% cellpadding=0> 945 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 946 <tr bgcolor=WHITE> 947 <td bgcolor=WHITE align=center valign=top>15:12</td> 948 <td align=left valign=top>RW</td> 949 <td align=left valign=top>dbg_lane_sel11</td> 950 <td align=left> 951 Selects 16bits of lane debug info<br> 952 Reset value is 0xb.</td></tr> 953 <tr bgcolor=WHITE> 954 <td bgcolor=WHITE align=center valign=top>11:08</td> 955 <td align=left valign=top>RW</td> 956 <td align=left valign=top>dbg_lane_sel10</td> 957 <td align=left> 958 Selects 16bits of lane debug info<br> 959 Reset value is 0xa.</td></tr> 960 <tr bgcolor=WHITE> 961 <td bgcolor=WHITE align=center valign=top>07:04</td> 962 <td align=left valign=top>RW</td> 963 <td align=left valign=top>dbg_lane_sel9</td> 964 <td align=left> 965 Selects 16bits of lane debug info<br> 966 Reset value is 0x9.</td></tr> 967 <tr bgcolor=WHITE> 968 <td bgcolor=WHITE align=center valign=top>03:00</td> 969 <td align=left valign=top>RW</td> 970 <td align=left valign=top>dbg_lane_sel8</td> 971 <td align=left> 972 Selects 16bits of lane debug info<br> 973 Reset value is 0x8.</td></tr> 974 </table><p> 975 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 976 <hr> 977 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL3">PCIE_BLK1_EXT_DBG_CTRL3 - Debug Data Control 3 Register</a></b><br> 978 Address Offset = 32'h0000_1109<br> 979 Physical Address = 32'h0000_1109<br> 980 Reset Value = 16'hfedc<br> 981 Access = RW (16-bit only)<br> 982 <table border=1 align=center width=100% cellpadding=0> 983 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 984 <tr bgcolor=WHITE> 985 <td bgcolor=WHITE align=center valign=top>15:12</td> 986 <td align=left valign=top>RW</td> 987 <td align=left valign=top>dbg_lane_sel15</td> 988 <td align=left> 989 Selects 16bits of lane debug info<br> 990 Reset value is 0xf.</td></tr> 991 <tr bgcolor=WHITE> 992 <td bgcolor=WHITE align=center valign=top>11:08</td> 993 <td align=left valign=top>RW</td> 994 <td align=left valign=top>dbg_lane_sel14</td> 995 <td align=left> 996 Selects 16bits of lane debug info<br> 997 Reset value is 0xe.</td></tr> 998 <tr bgcolor=WHITE> 999 <td bgcolor=WHITE align=center valign=top>07:04</td> 1000 <td align=left valign=top>RW</td> 1001 <td align=left valign=top>dbg_lane_sel13</td> 1002 <td align=left> 1003 Selects 16bits of lane debug info<br> 1004 Reset value is 0xd.</td></tr> 1005 <tr bgcolor=WHITE> 1006 <td bgcolor=WHITE align=center valign=top>03:00</td> 1007 <td align=left valign=top>RW</td> 1008 <td align=left valign=top>dbg_lane_sel12</td> 1009 <td align=left> 1010 Selects 16bits of lane debug info<br> 1011 Reset value is 0xc.</td></tr> 1012 </table><p> 1013 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 1014 <hr> 1015 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL4">PCIE_BLK1_EXT_DBG_CTRL4 - Debug Data Control 0 Register</a></b><br> 1016 Address Offset = 32'h0000_110a<br> 1017 Physical Address = 32'h0000_110a<br> 1018 Reset Value = 16'h3210<br> 1019 Access = RW (16-bit only)<br> 1020 <table border=1 align=center width=100% cellpadding=0> 1021 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1022 <tr bgcolor=WHITE> 1023 <td bgcolor=WHITE align=center valign=top>15:12</td> 1024 <td align=left valign=top>RW</td> 1025 <td align=left valign=top>dbg_info_sel3</td> 1026 <td align=left> 1027 Selects which 16bits of debug info being used<br> 1028 Reset value is 0x3.</td></tr> 1029 <tr bgcolor=WHITE> 1030 <td bgcolor=WHITE align=center valign=top>11:08</td> 1031 <td align=left valign=top>RW</td> 1032 <td align=left valign=top>dbg_info_sel2</td> 1033 <td align=left> 1034 Selects which 16bits of debug info being used<br> 1035 Reset value is 0x2.</td></tr> 1036 <tr bgcolor=WHITE> 1037 <td bgcolor=WHITE align=center valign=top>07:04</td> 1038 <td align=left valign=top>RW</td> 1039 <td align=left valign=top>dbg_info_sel1</td> 1040 <td align=left> 1041 Selects which 16bits of debug info being used<br> 1042 Reset value is 0x1.</td></tr> 1043 <tr bgcolor=WHITE> 1044 <td bgcolor=WHITE align=center valign=top>03:00</td> 1045 <td align=left valign=top>RW</td> 1046 <td align=left valign=top>dbg_info_sel0</td> 1047 <td align=left> 1048 Selects which 16bits of debug info being used<br> 1049 4'h0 : RX Debug Info<br> 1050 4'h1 : TX Debug Info<br> 1051 4'h2 : ?? Debug Info<br> 1052 Reset value is 0x0.</td></tr> 1053 </table><p> 1054 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 1055 <hr> 1056 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL5">PCIE_BLK1_EXT_DBG_CTRL5 - Debug Data Control 1 Register</a></b><br> 1057 Address Offset = 32'h0000_110b<br> 1058 Physical Address = 32'h0000_110b<br> 1059 Reset Value = 16'h7654<br> 1060 Access = RW (16-bit only)<br> 1061 <table border=1 align=center width=100% cellpadding=0> 1062 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1063 <tr bgcolor=WHITE> 1064 <td bgcolor=WHITE align=center valign=top>15:12</td> 1065 <td align=left valign=top>RW</td> 1066 <td align=left valign=top>dbg_info_sel7</td> 1067 <td align=left> 1068 Selects which 16bits of debug info being used<br> 1069 Reset value is 0x7.</td></tr> 1070 <tr bgcolor=WHITE> 1071 <td bgcolor=WHITE align=center valign=top>11:08</td> 1072 <td align=left valign=top>RW</td> 1073 <td align=left valign=top>dbg_info_sel6</td> 1074 <td align=left> 1075 Selects which 16bits of debug info being used<br> 1076 Reset value is 0x6.</td></tr> 1077 <tr bgcolor=WHITE> 1078 <td bgcolor=WHITE align=center valign=top>07:04</td> 1079 <td align=left valign=top>RW</td> 1080 <td align=left valign=top>dbg_info_sel5</td> 1081 <td align=left> 1082 Selects which 16bits of debug info being used<br> 1083 Reset value is 0x5.</td></tr> 1084 <tr bgcolor=WHITE> 1085 <td bgcolor=WHITE align=center valign=top>03:00</td> 1086 <td align=left valign=top>RW</td> 1087 <td align=left valign=top>dbg_info_sel4</td> 1088 <td align=left> 1089 Selects which 16bits of debug info being used<br> 1090 Reset value is 0x4.</td></tr> 1091 </table><p> 1092 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 1093 <hr> 1094 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL6">PCIE_BLK1_EXT_DBG_CTRL6 - Debug Data Control 2 Register</a></b><br> 1095 Address Offset = 32'h0000_110c<br> 1096 Physical Address = 32'h0000_110c<br> 1097 Reset Value = 16'hba98<br> 1098 Access = RW (16-bit only)<br> 1099 <table border=1 align=center width=100% cellpadding=0> 1100 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1101 <tr bgcolor=WHITE> 1102 <td bgcolor=WHITE align=center valign=top>15:12</td> 1103 <td align=left valign=top>RW</td> 1104 <td align=left valign=top>dbg_info_sel11</td> 1105 <td align=left> 1106 Selects which 16bits of debug info being used<br> 1107 Reset value is 0xb.</td></tr> 1108 <tr bgcolor=WHITE> 1109 <td bgcolor=WHITE align=center valign=top>11:08</td> 1110 <td align=left valign=top>RW</td> 1111 <td align=left valign=top>dbg_info_sel10</td> 1112 <td align=left> 1113 Selects which 16bits of debug info being used<br> 1114 Reset value is 0xa.</td></tr> 1115 <tr bgcolor=WHITE> 1116 <td bgcolor=WHITE align=center valign=top>07:04</td> 1117 <td align=left valign=top>RW</td> 1118 <td align=left valign=top>dbg_info_sel9</td> 1119 <td align=left> 1120 Selects which 16bits of debug info being used<br> 1121 Reset value is 0x9.</td></tr> 1122 <tr bgcolor=WHITE> 1123 <td bgcolor=WHITE align=center valign=top>03:00</td> 1124 <td align=left valign=top>RW</td> 1125 <td align=left valign=top>dbg_info_sel8</td> 1126 <td align=left> 1127 Selects which 16bits of debug info being used<br> 1128 Reset value is 0x8.</td></tr> 1129 </table><p> 1130 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 1131 <hr> 1132 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL7">PCIE_BLK1_EXT_DBG_CTRL7 - Debug Data Control 3 Register</a></b><br> 1133 Address Offset = 32'h0000_110d<br> 1134 Physical Address = 32'h0000_110d<br> 1135 Reset Value = 16'hfedc<br> 1136 Access = RW (16-bit only)<br> 1137 <table border=1 align=center width=100% cellpadding=0> 1138 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1139 <tr bgcolor=WHITE> 1140 <td bgcolor=WHITE align=center valign=top>15:12</td> 1141 <td align=left valign=top>RW</td> 1142 <td align=left valign=top>dbg_info_sel15</td> 1143 <td align=left> 1144 Selects which 16bits of debug info being used<br> 1145 Reset value is 0xf.</td></tr> 1146 <tr bgcolor=WHITE> 1147 <td bgcolor=WHITE align=center valign=top>11:08</td> 1148 <td align=left valign=top>RW</td> 1149 <td align=left valign=top>dbg_info_sel14</td> 1150 <td align=left> 1151 Selects which 16bits of debug info being used<br> 1152 Reset value is 0xe.</td></tr> 1153 <tr bgcolor=WHITE> 1154 <td bgcolor=WHITE align=center valign=top>07:04</td> 1155 <td align=left valign=top>RW</td> 1156 <td align=left valign=top>dbg_info_sel13</td> 1157 <td align=left> 1158 Selects which 16bits of debug info being used<br> 1159 Reset value is 0xd.</td></tr> 1160 <tr bgcolor=WHITE> 1161 <td bgcolor=WHITE align=center valign=top>03:00</td> 1162 <td align=left valign=top>RW</td> 1163 <td align=left valign=top>dbg_info_sel12</td> 1164 <td align=left> 1165 Selects which 16bits of debug info being used<br> 1166 Reset value is 0xc.</td></tr> 1167 </table><p> 1168 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 1169 <hr> 1170 <b><a NAME="PCIE_BLK1_EXT_DBG_CTRL8">PCIE_BLK1_EXT_DBG_CTRL8 - Debug Data Control 3 Register</a></b><br> 1171 Address Offset = 32'h0000_110e<br> 1172 Physical Address = 32'h0000_110e<br> 1173 Reset Value = 16'h0000<br> 1174 Access = RW (16-bit only)<br> 1175 <table border=1 align=center width=100% cellpadding=0> 1176 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1177 <tr bgcolor=WHITE> 1178 <td bgcolor=WHITE align=center valign=top>15:02</td> 1179 <td align=left valign=top>RSVD</td> 1180 <td align=left valign=top>Reserved</td> 1181 <td align=left> 1182 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 1183 <tr bgcolor=WHITE> 1184 <td bgcolor=WHITE align=center valign=top>01</td> 1185 <td align=left valign=top>RW</td> 1186 <td align=left valign=top>dbg_misc_tmux_sel</td> 1187 <td align=left> 1188 1: {pm_RateSelect, pcie_phy_lnk_pll_lock, pcie_chp_phy_core_config, pcie_chp_phy_pll_lock_ext, <br> 1189     pcie_phy_lnk_phy_status_3, pcie_phy_lnk_phy_status_0, TxElectIdle_3,TxElectIdle_1,TxElectIdle_0} <br> 1190 0: {pm_RateSelect, pcie_phy_refclk_sense_req, pcie_phy_refclk_sense_ack, rx_G3_FrameLock, <br> 1191     pmd_rxSeqDone_str, pmd_rx_sigdet_mac} <br> 1192 Reset value is 0x0.</td></tr> 1193 <tr bgcolor=WHITE> 1194 <td bgcolor=WHITE align=center valign=top>00</td> 1195 <td align=left valign=top>RW</td> 1196 <td align=left valign=top>dbg_data_ena</td> 1197 <td align=left> 1198 Enables the DL/PL debug data<br> 1199 Assert after Debug Data controls have been configured<br> 1200 Reset value is 0x0.</td></tr> 1201 </table><p> 1202 <A HREF="#PCIE_BLK1_EXT Registers">Return to PCIE_BLK1_EXT Table</A><p> 1203 <hr> 1204 <H1><a NAME="PCIE_BLK2_EXT Registers">PCIE_BLK2_EXT Registers</a></H1> 1205 <table border=1 align=center width=100% cellpadding=0> 1206 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 1207 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 1208 <tr> 1209 <td align=center>0x1200</td><td><A HREF="#PCIE_BLK2_EXT_LFCKCNT">PCIE_BLK2_EXT_LFCKCNT</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lfckcnt</div> </td> <td align=center>16'h00ff</td></tr> 1210 <tr> 1211 <td align=center>0x1201</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT0">PCIE_BLK2_EXT_PWRMGMT0</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_NoVoltIsland</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_L23Ready</div> </td> <td align=center>16'h7f64</td></tr> 1212 <tr> 1213 <td align=center>0x1202</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT1">PCIE_BLK2_EXT_PWRMGMT1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_FwPwrDn</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_LinkPwrDn</div> </td> <td align=center>16'h7764</td></tr> 1214 <tr> 1215 <td align=center>0x1203</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT2">PCIE_BLK2_EXT_PWRMGMT2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_L1NoClkReqPllPwrDn</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_L1NoClkReq</div> </td> <td align=center>16'h2000</td></tr> 1216 <tr> 1217 <td align=center>0x1204</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT3">PCIE_BLK2_EXT_PWRMGMT3</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_P0</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_LTTSM_L1ClkReq</div> </td> <td align=center>16'h007c</td></tr> 1218 <tr> 1219 <td align=center>0x1205</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT4">PCIE_BLK2_EXT_PWRMGMT4</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RefclkSenseBypass</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">mdio_TxIdleCtrl</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ClkReq_tmp</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ClkReqMdioSel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_AuxClkEnable_tmp</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_AuxClkEnableMdioSel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_AuxPowerDownP1PllEnableMdioSel</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">mdio_LTTSM_L1AnaPwrDnPll</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">mdio_LTTSM_L1AnaPwrDn</div> </td> <td align=center>16'h0028</td></tr> 1220 <tr> 1221 <td align=center>0x1206</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT5">PCIE_BLK2_EXT_PWRMGMT5</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_pwrdn_pll_timer_dfs</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RcPllPd_ovrd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RcPllPd_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_tx_cmn_mode_force_P2ClkReqEntry_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RefclkSense_onecomp</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RefclkSenseEventClr</div> </td> <td align=center>16'h1800</td></tr> 1222 <tr> 1223 <td align=center>0x1207</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT6">PCIE_BLK2_EXT_PWRMGMT6</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_pwrdn_refclk_timer_dfs</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">mdio_pwr_mgmt_spare_dfs</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">mdio_pm_P2_Wait4Pclk_tmr</div> </td> <td align=center>16'h050f</td></tr> 1224 <tr> 1225 <td align=center>0x1208</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT7">PCIE_BLK2_EXT_PWRMGMT7</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_RefclkSense_M</div> </td> <td align=center>16'h000f</td></tr> 1226 <tr> 1227 <td align=center>0x1209</td><td><A HREF="#PCIE_BLK2_EXT_PWRMGMT8">PCIE_BLK2_EXT_PWRMGMT8</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_RefclkSense_N</div> </td> <td align=center>16'h000f</td></tr> 1228 <tr> 1229 <td align=center>0x120A</td><td><A HREF="#PCIE_BLK2_EXT_REFCLKSENSE_STAT">PCIE_BLK2_EXT_REFCLKSENSE_STAT</A><br>Register</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">mdio_RefclkSenseEventCnt</div> </td> <td align=center>16'h0000</td></tr> 1230 <tr> 1231 <td align=center>0x120B</td><td><A HREF="#PCIE_BLK2_EXT_REFCLKSENSE_STAT2">PCIE_BLK2_EXT_REFCLKSENSE_STAT2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_RefclkSenseCnt</div> </td> <td align=center>16'h0000</td></tr> 1232 </table><p> 1233 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 1234 <hr> 1235 <b><a NAME="PCIE_BLK2_EXT_LFCKCNT">PCIE_BLK2_EXT_LFCKCNT - Register</a></b><br> 1236 Address Offset = 32'h0000_1200<br> 1237 Physical Address = 32'h0000_1200<br> 1238 Reset Value = 16'h00ff<br> 1239 Access = RW (16-bit only)<br> 1240 <table border=1 align=center width=100% cellpadding=0> 1241 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1242 <tr bgcolor=WHITE> 1243 <td bgcolor=WHITE align=center valign=top>15:00</td> 1244 <td align=left valign=top>RW</td> 1245 <td align=left valign=top>lfckcnt</td> 1246 <td align=left> 1247 tbd<br> 1248 Reset value is 0xff.</td></tr> 1249 </table><p> 1250 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1251 <hr> 1252 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT0">PCIE_BLK2_EXT_PWRMGMT0 - Register</a></b><br> 1253 Address Offset = 32'h0000_1201<br> 1254 Physical Address = 32'h0000_1201<br> 1255 Reset Value = 16'h7f64<br> 1256 Access = RW (16-bit only)<br> 1257 <table border=1 align=center width=100% cellpadding=0> 1258 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1259 <tr bgcolor=WHITE> 1260 <td bgcolor=WHITE align=center valign=top>15:08</td> 1261 <td align=left valign=top>RW</td> 1262 <td align=left valign=top>mdio_LTTSM_NoVoltIsland</td> 1263 <td align=left> 1264 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1265 Reset value is 0x7f.</td></tr> 1266 <tr bgcolor=WHITE> 1267 <td bgcolor=WHITE align=center valign=top>07:00</td> 1268 <td align=left valign=top>RW</td> 1269 <td align=left valign=top>mdio_LTTSM_L23Ready</td> 1270 <td align=left> 1271 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1272 Reset value is 0x64.</td></tr> 1273 </table><p> 1274 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1275 <hr> 1276 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT1">PCIE_BLK2_EXT_PWRMGMT1 - Register</a></b><br> 1277 Address Offset = 32'h0000_1202<br> 1278 Physical Address = 32'h0000_1202<br> 1279 Reset Value = 16'h7764<br> 1280 Access = RW (16-bit only)<br> 1281 <table border=1 align=center width=100% cellpadding=0> 1282 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1283 <tr bgcolor=WHITE> 1284 <td bgcolor=WHITE align=center valign=top>15:08</td> 1285 <td align=left valign=top>RW</td> 1286 <td align=left valign=top>mdio_LTTSM_FwPwrDn</td> 1287 <td align=left> 1288 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1289 Reset value is 0x77.</td></tr> 1290 <tr bgcolor=WHITE> 1291 <td bgcolor=WHITE align=center valign=top>07:00</td> 1292 <td align=left valign=top>RW</td> 1293 <td align=left valign=top>mdio_LTTSM_LinkPwrDn</td> 1294 <td align=left> 1295 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1296 Reset value is 0x64.</td></tr> 1297 </table><p> 1298 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1299 <hr> 1300 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT2">PCIE_BLK2_EXT_PWRMGMT2 - Register</a></b><br> 1301 Address Offset = 32'h0000_1203<br> 1302 Physical Address = 32'h0000_1203<br> 1303 Reset Value = 16'h2000<br> 1304 Access = RW (16-bit only)<br> 1305 <table border=1 align=center width=100% cellpadding=0> 1306 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1307 <tr bgcolor=WHITE> 1308 <td bgcolor=WHITE align=center valign=top>15:08</td> 1309 <td align=left valign=top>RW</td> 1310 <td align=left valign=top>mdio_LTTSM_L1NoClkReqPllPwrDn</td> 1311 <td align=left> 1312 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1313 Reset value is 0x20.</td></tr> 1314 <tr bgcolor=WHITE> 1315 <td bgcolor=WHITE align=center valign=top>07:00</td> 1316 <td align=left valign=top>RW</td> 1317 <td align=left valign=top>mdio_LTTSM_L1NoClkReq</td> 1318 <td align=left> 1319 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1320 Reset value is 0x0.</td></tr> 1321 </table><p> 1322 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1323 <hr> 1324 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT3">PCIE_BLK2_EXT_PWRMGMT3 - Register</a></b><br> 1325 Address Offset = 32'h0000_1204<br> 1326 Physical Address = 32'h0000_1204<br> 1327 Reset Value = 16'h007c<br> 1328 Access = RW (16-bit only)<br> 1329 <table border=1 align=center width=100% cellpadding=0> 1330 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1331 <tr bgcolor=WHITE> 1332 <td bgcolor=WHITE align=center valign=top>15:08</td> 1333 <td align=left valign=top>RW</td> 1334 <td align=left valign=top>mdio_LTTSM_P0</td> 1335 <td align=left> 1336 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1337 Reset value is 0x0.</td></tr> 1338 <tr bgcolor=WHITE> 1339 <td bgcolor=WHITE align=center valign=top>07:00</td> 1340 <td align=left valign=top>RW</td> 1341 <td align=left valign=top>mdio_LTTSM_L1ClkReq</td> 1342 <td align=left> 1343 mapped as {2 {1'b0, pm_pwrdn, pm_reset_pll, pm_refclk_pd, tx0_pwrdn, rx0_pwrdn, rx0_sigdet_pd, rx0_hi_Z} }<br> 1344 Reset value is 0x7c.</td></tr> 1345 </table><p> 1346 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1347 <hr> 1348 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT4">PCIE_BLK2_EXT_PWRMGMT4 - Register</a></b><br> 1349 Address Offset = 32'h0000_1205<br> 1350 Physical Address = 32'h0000_1205<br> 1351 Reset Value = 16'h0028<br> 1352 Access = RW (16-bit only)<br> 1353 <table border=1 align=center width=100% cellpadding=0> 1354 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1355 <tr bgcolor=WHITE> 1356 <td bgcolor=WHITE align=center valign=top>15</td> 1357 <td align=left valign=top>RW</td> 1358 <td align=left valign=top>mdio_RefclkSenseBypass</td> 1359 <td align=left> 1360 used for Bypassing the RefclkSense <br> 1361 Reset value is 0x0.</td></tr> 1362 <tr bgcolor=WHITE> 1363 <td bgcolor=WHITE align=center valign=top>14:11</td> 1364 <td align=left valign=top>RW</td> 1365 <td align=left valign=top>mdio_TxIdleCtrl</td> 1366 <td align=left> 1367 Reset value is 0x0.</td></tr> 1368 <tr bgcolor=WHITE> 1369 <td bgcolor=WHITE align=center valign=top>10</td> 1370 <td align=left valign=top>RW</td> 1371 <td align=left valign=top>mdio_ClkReq_tmp</td> 1372 <td align=left> 1373 Reset value is 0x0.</td></tr> 1374 <tr bgcolor=WHITE> 1375 <td bgcolor=WHITE align=center valign=top>09</td> 1376 <td align=left valign=top>RW</td> 1377 <td align=left valign=top>mdio_ClkReqMdioSel</td> 1378 <td align=left> 1379 Reset value is 0x0.</td></tr> 1380 <tr bgcolor=WHITE> 1381 <td bgcolor=WHITE align=center valign=top>08</td> 1382 <td align=left valign=top>RW</td> 1383 <td align=left valign=top>mdio_AuxClkEnable_tmp</td> 1384 <td align=left> 1385 Reset value is 0x0.</td></tr> 1386 <tr bgcolor=WHITE> 1387 <td bgcolor=WHITE align=center valign=top>07</td> 1388 <td align=left valign=top>RW</td> 1389 <td align=left valign=top>mdio_AuxClkEnableMdioSel</td> 1390 <td align=left> 1391 Reset value is 0x0.</td></tr> 1392 <tr bgcolor=WHITE> 1393 <td bgcolor=WHITE align=center valign=top>06</td> 1394 <td align=left valign=top>RW</td> 1395 <td align=left valign=top>mdio_AuxPowerDownP1PllEnableMdioSel</td> 1396 <td align=left> 1397 used for select and is assigned to signal<br> 1398 Reset value is 0x0.</td></tr> 1399 <tr bgcolor=WHITE> 1400 <td bgcolor=WHITE align=center valign=top>05:03</td> 1401 <td align=left valign=top>RW</td> 1402 <td align=left valign=top>mdio_LTTSM_L1AnaPwrDnPll</td> 1403 <td align=left> 1404 Reset value is 0x5.</td></tr> 1405 <tr bgcolor=WHITE> 1406 <td bgcolor=WHITE align=center valign=top>02:00</td> 1407 <td align=left valign=top>RW</td> 1408 <td align=left valign=top>mdio_LTTSM_L1AnaPwrDn</td> 1409 <td align=left> 1410 Reset value is 0x0.</td></tr> 1411 </table><p> 1412 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1413 <hr> 1414 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT5">PCIE_BLK2_EXT_PWRMGMT5 - Register</a></b><br> 1415 Address Offset = 32'h0000_1206<br> 1416 Physical Address = 32'h0000_1206<br> 1417 Reset Value = 16'h1800<br> 1418 Access = RW (16-bit only)<br> 1419 <table border=1 align=center width=100% cellpadding=0> 1420 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1421 <tr bgcolor=WHITE> 1422 <td bgcolor=WHITE align=center valign=top>15:08</td> 1423 <td align=left valign=top>RW</td> 1424 <td align=left valign=top>mdio_pwrdn_pll_timer_dfs</td> 1425 <td align=left> 1426 mdio_pwrdn_pll_timer_dfs<br> 1427 Reset value is 0x18.</td></tr> 1428 <tr bgcolor=WHITE> 1429 <td bgcolor=WHITE align=center valign=top>07</td> 1430 <td align=left valign=top>RW</td> 1431 <td align=left valign=top>mdio_RcPllPd_ovrd</td> 1432 <td align=left> 1433 mdio_RcPllPd_ovrd<br> 1434 Reset value is 0x0.</td></tr> 1435 <tr bgcolor=WHITE> 1436 <td bgcolor=WHITE align=center valign=top>06</td> 1437 <td align=left valign=top>RW</td> 1438 <td align=left valign=top>mdio_RcPllPd_val</td> 1439 <td align=left> 1440 mdio_RcPllPd_val<br> 1441 Reset value is 0x0.</td></tr> 1442 <tr bgcolor=WHITE> 1443 <td bgcolor=WHITE align=center valign=top>05</td> 1444 <td align=left valign=top>RW</td> 1445 <td align=left valign=top>mdio_tx_cmn_mode_force_P2ClkReqEntry_en</td> 1446 <td align=left> 1447 Reset value is 0x0.</td></tr> 1448 <tr bgcolor=WHITE> 1449 <td bgcolor=WHITE align=center valign=top>04:02</td> 1450 <td align=left valign=top>RSVD</td> 1451 <td align=left valign=top>Reserved</td> 1452 <td align=left> 1453 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 1454 <tr bgcolor=WHITE> 1455 <td bgcolor=WHITE align=center valign=top>01</td> 1456 <td align=left valign=top>RW</td> 1457 <td align=left valign=top>mdio_RefclkSense_onecomp</td> 1458 <td align=left> 1459 set the RefclkSense threshold value<br> 1460 Reset value is 0x0.</td></tr> 1461 <tr bgcolor=WHITE> 1462 <td bgcolor=WHITE align=center valign=top>00</td> 1463 <td align=left valign=top>RW</td> 1464 <td align=left valign=top>mdio_RefclkSenseEventClr</td> 1465 <td align=left> 1466 clear the RefclkSense event counter<br> 1467 Reset value is 0x0.</td></tr> 1468 </table><p> 1469 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1470 <hr> 1471 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT6">PCIE_BLK2_EXT_PWRMGMT6 - Register</a></b><br> 1472 Address Offset = 32'h0000_1207<br> 1473 Physical Address = 32'h0000_1207<br> 1474 Reset Value = 16'h050f<br> 1475 Access = RW (16-bit only)<br> 1476 <table border=1 align=center width=100% cellpadding=0> 1477 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1478 <tr bgcolor=WHITE> 1479 <td bgcolor=WHITE align=center valign=top>15:08</td> 1480 <td align=left valign=top>RW</td> 1481 <td align=left valign=top>mdio_pwrdn_refclk_timer_dfs</td> 1482 <td align=left> 1483 mdio_pwrdn_refclk_timer_dfs<br> 1484 Reset value is 0x5.</td></tr> 1485 <tr bgcolor=WHITE> 1486 <td bgcolor=WHITE align=center valign=top>07:04</td> 1487 <td align=left valign=top>RW</td> 1488 <td align=left valign=top>mdio_pwr_mgmt_spare_dfs</td> 1489 <td align=left> 1490 mdio_pwr_mgmt_spare_dfs<br> 1491 Reset value is 0x0.</td></tr> 1492 <tr bgcolor=WHITE> 1493 <td bgcolor=WHITE align=center valign=top>03:00</td> 1494 <td align=left valign=top>RW</td> 1495 <td align=left valign=top>mdio_pm_P2_Wait4Pclk_tmr</td> 1496 <td align=left> 1497 <br> 1498 Reset value is 0xf.</td></tr> 1499 </table><p> 1500 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1501 <hr> 1502 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT7">PCIE_BLK2_EXT_PWRMGMT7 - Register</a></b><br> 1503 Address Offset = 32'h0000_1208<br> 1504 Physical Address = 32'h0000_1208<br> 1505 Reset Value = 16'h000f<br> 1506 Access = RW (16-bit only)<br> 1507 <table border=1 align=center width=100% cellpadding=0> 1508 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1509 <tr bgcolor=WHITE> 1510 <td bgcolor=WHITE align=center valign=top>15:00</td> 1511 <td align=left valign=top>RW</td> 1512 <td align=left valign=top>mdio_RefclkSense_M</td> 1513 <td align=left> 1514 mdio_RefclkSense_M(cnt for auxclk)Vulcan: 0x0003(auxclk=20MHz)TD3:    0x0007(auxclk=50MHz)<br> 1515 Reset value is 0xf.</td></tr> 1516 </table><p> 1517 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1518 <hr> 1519 <b><a NAME="PCIE_BLK2_EXT_PWRMGMT8">PCIE_BLK2_EXT_PWRMGMT8 - Register</a></b><br> 1520 Address Offset = 32'h0000_1209<br> 1521 Physical Address = 32'h0000_1209<br> 1522 Reset Value = 16'h000f<br> 1523 Access = RW (16-bit only)<br> 1524 <table border=1 align=center width=100% cellpadding=0> 1525 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1526 <tr bgcolor=WHITE> 1527 <td bgcolor=WHITE align=center valign=top>15:00</td> 1528 <td align=left valign=top>RW</td> 1529 <td align=left valign=top>mdio_RefclkSense_N</td> 1530 <td align=left> 1531 mdio_RefclkSense_N(cnt for refclk)Vulcan: 0x000F(refclk=100MHz)TD3:    0x000F(refclk=100MHz)<br> 1532 Reset value is 0xf.</td></tr> 1533 </table><p> 1534 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1535 <hr> 1536 <b><a NAME="PCIE_BLK2_EXT_REFCLKSENSE_STAT">PCIE_BLK2_EXT_REFCLKSENSE_STAT - Register</a></b><br> 1537 Address Offset = 32'h0000_120a<br> 1538 Physical Address = 32'h0000_120a<br> 1539 Reset Value = 16'h0000<br> 1540 Access = RO (16-bit only)<br> 1541 <table border=1 align=center width=100% cellpadding=0> 1542 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1543 <tr bgcolor=WHITE> 1544 <td bgcolor=WHITE align=center valign=top>15:04</td> 1545 <td align=left valign=top>RSVD</td> 1546 <td align=left valign=top>Reserved</td> 1547 <td align=left> 1548 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 1549 <tr bgcolor=WHITE> 1550 <td bgcolor=WHITE align=center valign=top>03:00</td> 1551 <td align=left valign=top>RO</td> 1552 <td align=left valign=top>mdio_RefclkSenseEventCnt</td> 1553 <td align=left> 1554 Number of ACKs sent<br> 1555 Reset value is 0x0.</td></tr> 1556 </table><p> 1557 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1558 <hr> 1559 <b><a NAME="PCIE_BLK2_EXT_REFCLKSENSE_STAT2">PCIE_BLK2_EXT_REFCLKSENSE_STAT2 - Register</a></b><br> 1560 Address Offset = 32'h0000_120b<br> 1561 Physical Address = 32'h0000_120b<br> 1562 Reset Value = 16'h0000<br> 1563 Access = RO (16-bit only)<br> 1564 <table border=1 align=center width=100% cellpadding=0> 1565 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1566 <tr bgcolor=WHITE> 1567 <td bgcolor=WHITE align=center valign=top>15:00</td> 1568 <td align=left valign=top>RO</td> 1569 <td align=left valign=top>mdio_RefclkSenseCnt</td> 1570 <td align=left> 1571 <br> 1572 Reset value is 0x0.</td></tr> 1573 </table><p> 1574 <A HREF="#PCIE_BLK2_EXT Registers">Return to PCIE_BLK2_EXT Table</A><p> 1575 <hr> 1576 <H1><a NAME="PCIE_BLK3_EXT Registers">PCIE_BLK3_EXT Registers</a></H1> 1577 <table border=1 align=center width=100% cellpadding=0> 1578 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 1579 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 1580 <tr> 1581 <td align=center>0x1300</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL0">PCIE_BLK3_EXT_GEN2CTRL0</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_byp_pipe_io</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pwrdown_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_idle_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rloop_pipe_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">gloop_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_comp_mdio_sel</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RxElectIdleRloopEn</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">StandAloneMode_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">PllTuningBypass_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lfck_rx_sel_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_DeviceType_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">mdio_DeviceType</div> </td> <td align=center>16'h0080</td></tr> 1582 <tr> 1583 <td align=center>0x1301</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL1">PCIE_BLK3_EXT_GEN2CTRL1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">spares_pcie3_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_pmi_select_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_pmi_select_val</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RC_refclk_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_RC_refclk_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RateSelect_mdio_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">mdioRateSelect</div> </td> <td align=center>16'h0000</td></tr> 1584 <tr> 1585 <td align=center>0x1302</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL2">PCIE_BLK3_EXT_GEN2CTRL2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">spares_pcie3_2</div> </td> <td align=center>16'h0000</td></tr> 1586 <tr> 1587 <td align=center>0x1303</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL3">PCIE_BLK3_EXT_GEN2CTRL3</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_gloop</div> </td> <td align=center>16'h0000</td></tr> 1588 <tr> 1589 <td align=center>0x1304</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL4">PCIE_BLK3_EXT_GEN2CTRL4</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rloop1g</div> </td> <td align=center>16'h0000</td></tr> 1590 <tr> 1591 <td align=center>0x1305</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL5">PCIE_BLK3_EXT_GEN2CTRL5</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_rloop_pipe</div> </td> <td align=center>16'h0000</td></tr> 1592 <tr> 1593 <td align=center>0x1306</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL6">PCIE_BLK3_EXT_GEN2CTRL6</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">gen2_ctrl6</div> </td> <td align=center>16'h0000</td></tr> 1594 <tr> 1595 <td align=center>0x1307</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL7">PCIE_BLK3_EXT_GEN2CTRL7</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">DisablePmRxFastAcq</div> </td> <td align=center>16'h0000</td></tr> 1596 <tr> 1597 <td align=center>0x1308</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL8">PCIE_BLK3_EXT_GEN2CTRL8</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdioRxFastAcqEnable</div> </td> <td align=center>16'h0000</td></tr> 1598 <tr> 1599 <td align=center>0x1309</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL9">PCIE_BLK3_EXT_GEN2CTRL9</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdioRxSeqStart</div> </td> <td align=center>16'hffff</td></tr> 1600 <tr> 1601 <td align=center>0x130A</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL10">PCIE_BLK3_EXT_GEN2CTRL10</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_TxElectIdle_r</div> </td> <td align=center>16'h0000</td></tr> 1602 <tr> 1603 <td align=center>0x130B</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL11">PCIE_BLK3_EXT_GEN2CTRL11</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_TxComp_r</div> </td> <td align=center>16'h0000</td></tr> 1604 <tr> 1605 <td align=center>0x130C</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL12">PCIE_BLK3_EXT_GEN2CTRL12</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_PowerDown_0</div> </td> <td align=center>16'h0000</td></tr> 1606 <tr> 1607 <td align=center>0x130D</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL13">PCIE_BLK3_EXT_GEN2CTRL13</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_PowerDown_1</div> </td> <td align=center>16'h0000</td></tr> 1608 <tr> 1609 <td align=center>0x130E</td><td><A HREF="#PCIE_BLK3_EXT_GEN2CTRL14">PCIE_BLK3_EXT_GEN2CTRL14</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">gen2_ctrl14</div> </td> <td align=center>16'h0000</td></tr> 1610 </table><p> 1611 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 1612 <hr> 1613 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL0">PCIE_BLK3_EXT_GEN2CTRL0 - Register</a></b><br> 1614 Address Offset = 32'h0000_1300<br> 1615 Physical Address = 32'h0000_1300<br> 1616 Reset Value = 16'h0080<br> 1617 Access = RW (16-bit only)<br> 1618 <table border=1 align=center width=100% cellpadding=0> 1619 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1620 <tr bgcolor=WHITE> 1621 <td bgcolor=WHITE align=center valign=top>15</td> 1622 <td align=left valign=top>RW</td> 1623 <td align=left valign=top>mdio_byp_pipe_io</td> 1624 <td align=left> 1625 tbd<br> 1626 Reset value is 0x0.</td></tr> 1627 <tr bgcolor=WHITE> 1628 <td bgcolor=WHITE align=center valign=top>14</td> 1629 <td align=left valign=top>RW</td> 1630 <td align=left valign=top>pwrdown_mdio_sel</td> 1631 <td align=left> 1632 tbd<br> 1633 Reset value is 0x0.</td></tr> 1634 <tr bgcolor=WHITE> 1635 <td bgcolor=WHITE align=center valign=top>13</td> 1636 <td align=left valign=top>RW</td> 1637 <td align=left valign=top>tx_idle_mdio_sel</td> 1638 <td align=left> 1639 tbd<br> 1640 Reset value is 0x0.</td></tr> 1641 <tr bgcolor=WHITE> 1642 <td bgcolor=WHITE align=center valign=top>12</td> 1643 <td align=left valign=top>RW</td> 1644 <td align=left valign=top>rloop_pipe_mdio_sel</td> 1645 <td align=left> 1646 tbd<br> 1647 Reset value is 0x0.</td></tr> 1648 <tr bgcolor=WHITE> 1649 <td bgcolor=WHITE align=center valign=top>11</td> 1650 <td align=left valign=top>RW</td> 1651 <td align=left valign=top>gloop_mdio_sel</td> 1652 <td align=left> 1653 tbd<br> 1654 Reset value is 0x0.</td></tr> 1655 <tr bgcolor=WHITE> 1656 <td bgcolor=WHITE align=center valign=top>10</td> 1657 <td align=left valign=top>RW</td> 1658 <td align=left valign=top>tx_comp_mdio_sel</td> 1659 <td align=left> 1660 tbd<br> 1661 Reset value is 0x0.</td></tr> 1662 <tr bgcolor=WHITE> 1663 <td bgcolor=WHITE align=center valign=top>09:08</td> 1664 <td align=left valign=top>RSVD</td> 1665 <td align=left valign=top>Reserved</td> 1666 <td align=left> 1667 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 1668 <tr bgcolor=WHITE> 1669 <td bgcolor=WHITE align=center valign=top>07</td> 1670 <td align=left valign=top>RW</td> 1671 <td align=left valign=top>mdio_RxElectIdleRloopEn</td> 1672 <td align=left> 1673 tbd<br> 1674 Reset value is 0x1.</td></tr> 1675 <tr bgcolor=WHITE> 1676 <td bgcolor=WHITE align=center valign=top>06</td> 1677 <td align=left valign=top>RW</td> 1678 <td align=left valign=top>StandAloneMode_mdio_sel</td> 1679 <td align=left> 1680 tbd<br> 1681 Reset value is 0x0.</td></tr> 1682 <tr bgcolor=WHITE> 1683 <td bgcolor=WHITE align=center valign=top>05</td> 1684 <td align=left valign=top>RW</td> 1685 <td align=left valign=top>PllTuningBypass_mdio_sel</td> 1686 <td align=left> 1687 tbd<br> 1688 Reset value is 0x0.</td></tr> 1689 <tr bgcolor=WHITE> 1690 <td bgcolor=WHITE align=center valign=top>04</td> 1691 <td align=left valign=top>RW</td> 1692 <td align=left valign=top>lfck_rx_sel_mdio_sel</td> 1693 <td align=left> 1694 tbd<br> 1695 Reset value is 0x0.</td></tr> 1696 <tr bgcolor=WHITE> 1697 <td bgcolor=WHITE align=center valign=top>03</td> 1698 <td align=left valign=top>RW</td> 1699 <td align=left valign=top>mdio_DeviceType_sel</td> 1700 <td align=left> 1701 tbd<br> 1702 Reset value is 0x0.</td></tr> 1703 <tr bgcolor=WHITE> 1704 <td bgcolor=WHITE align=center valign=top>02:00</td> 1705 <td align=left valign=top>RW</td> 1706 <td align=left valign=top>mdio_DeviceType</td> 1707 <td align=left> 1708 tbd<br> 1709 Reset value is 0x0.</td></tr> 1710 </table><p> 1711 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1712 <hr> 1713 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL1">PCIE_BLK3_EXT_GEN2CTRL1 - Register</a></b><br> 1714 Address Offset = 32'h0000_1301<br> 1715 Physical Address = 32'h0000_1301<br> 1716 Reset Value = 16'h0000<br> 1717 Access = RW (16-bit only)<br> 1718 <table border=1 align=center width=100% cellpadding=0> 1719 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1720 <tr bgcolor=WHITE> 1721 <td bgcolor=WHITE align=center valign=top>15:10</td> 1722 <td align=left valign=top>RW</td> 1723 <td align=left valign=top>spares_pcie3_1</td> 1724 <td align=left> 1725 <br> 1726 Reset value is 0x0.</td></tr> 1727 <tr bgcolor=WHITE> 1728 <td bgcolor=WHITE align=center valign=top>09</td> 1729 <td align=left valign=top>RW</td> 1730 <td align=left valign=top>mdio_pmi_select_sel</td> 1731 <td align=left> 1732 mdio_pmi_select ovrd select<br> 1733 Reset value is 0x0.</td></tr> 1734 <tr bgcolor=WHITE> 1735 <td bgcolor=WHITE align=center valign=top>08</td> 1736 <td align=left valign=top>RW</td> 1737 <td align=left valign=top>mdio_pmi_select_val</td> 1738 <td align=left> 1739 mdio_pmi_select ovrd value<br> 1740 Reset value is 0x0.</td></tr> 1741 <tr bgcolor=WHITE> 1742 <td bgcolor=WHITE align=center valign=top>07:05</td> 1743 <td align=left valign=top>RSVD</td> 1744 <td align=left valign=top>Reserved</td> 1745 <td align=left> 1746 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 1747 <tr bgcolor=WHITE> 1748 <td bgcolor=WHITE align=center valign=top>04</td> 1749 <td align=left valign=top>RW</td> 1750 <td align=left valign=top>mdio_RC_refclk_sel</td> 1751 <td align=left> 1752 <br> 1753 Reset value is 0x0.</td></tr> 1754 <tr bgcolor=WHITE> 1755 <td bgcolor=WHITE align=center valign=top>03</td> 1756 <td align=left valign=top>RW</td> 1757 <td align=left valign=top>mdio_RC_refclk_val</td> 1758 <td align=left> 1759 <br> 1760 Reset value is 0x0.</td></tr> 1761 <tr bgcolor=WHITE> 1762 <td bgcolor=WHITE align=center valign=top>02</td> 1763 <td align=left valign=top>RW</td> 1764 <td align=left valign=top>RateSelect_mdio_sel</td> 1765 <td align=left> 1766 RateSelect ovrd select<br> 1767 Reset value is 0x0.</td></tr> 1768 <tr bgcolor=WHITE> 1769 <td bgcolor=WHITE align=center valign=top>01:00</td> 1770 <td align=left valign=top>RW</td> 1771 <td align=left valign=top>mdioRateSelect</td> 1772 <td align=left> 1773 RateSelect ovrd value<br> 1774 Reset value is 0x0.</td></tr> 1775 </table><p> 1776 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1777 <hr> 1778 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL2">PCIE_BLK3_EXT_GEN2CTRL2 - Register</a></b><br> 1779 Address Offset = 32'h0000_1302<br> 1780 Physical Address = 32'h0000_1302<br> 1781 Reset Value = 16'h0000<br> 1782 Access = RW (16-bit only)<br> 1783 <table border=1 align=center width=100% cellpadding=0> 1784 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1785 <tr bgcolor=WHITE> 1786 <td bgcolor=WHITE align=center valign=top>15:00</td> 1787 <td align=left valign=top>RW</td> 1788 <td align=left valign=top>spares_pcie3_2</td> 1789 <td align=left> 1790 <br> 1791 Reset value is 0x0.</td></tr> 1792 </table><p> 1793 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1794 <hr> 1795 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL3">PCIE_BLK3_EXT_GEN2CTRL3 - Register</a></b><br> 1796 Address Offset = 32'h0000_1303<br> 1797 Physical Address = 32'h0000_1303<br> 1798 Reset Value = 16'h0000<br> 1799 Access = RW (16-bit only)<br> 1800 <table border=1 align=center width=100% cellpadding=0> 1801 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1802 <tr bgcolor=WHITE> 1803 <td bgcolor=WHITE align=center valign=top>15:00</td> 1804 <td align=left valign=top>RW</td> 1805 <td align=left valign=top>mdio_gloop</td> 1806 <td align=left> 1807 tbd<br> 1808 Reset value is 0x0.</td></tr> 1809 </table><p> 1810 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1811 <hr> 1812 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL4">PCIE_BLK3_EXT_GEN2CTRL4 - Register</a></b><br> 1813 Address Offset = 32'h0000_1304<br> 1814 Physical Address = 32'h0000_1304<br> 1815 Reset Value = 16'h0000<br> 1816 Access = RW (16-bit only)<br> 1817 <table border=1 align=center width=100% cellpadding=0> 1818 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1819 <tr bgcolor=WHITE> 1820 <td bgcolor=WHITE align=center valign=top>15:00</td> 1821 <td align=left valign=top>RW</td> 1822 <td align=left valign=top>rloop1g</td> 1823 <td align=left> 1824 tbd<br> 1825 Reset value is 0x0.</td></tr> 1826 </table><p> 1827 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1828 <hr> 1829 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL5">PCIE_BLK3_EXT_GEN2CTRL5 - Register</a></b><br> 1830 Address Offset = 32'h0000_1305<br> 1831 Physical Address = 32'h0000_1305<br> 1832 Reset Value = 16'h0000<br> 1833 Access = RW (16-bit only)<br> 1834 <table border=1 align=center width=100% cellpadding=0> 1835 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1836 <tr bgcolor=WHITE> 1837 <td bgcolor=WHITE align=center valign=top>15:00</td> 1838 <td align=left valign=top>RW</td> 1839 <td align=left valign=top>mdio_rloop_pipe</td> 1840 <td align=left> 1841 tbd<br> 1842 Reset value is 0x0.</td></tr> 1843 </table><p> 1844 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1845 <hr> 1846 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL6">PCIE_BLK3_EXT_GEN2CTRL6 - Register</a></b><br> 1847 Address Offset = 32'h0000_1306<br> 1848 Physical Address = 32'h0000_1306<br> 1849 Reset Value = 16'h0000<br> 1850 Access = RW (16-bit only)<br> 1851 <table border=1 align=center width=100% cellpadding=0> 1852 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1853 <tr bgcolor=WHITE> 1854 <td bgcolor=WHITE align=center valign=top>15:00</td> 1855 <td align=left valign=top>RW</td> 1856 <td align=left valign=top>gen2_ctrl6</td> 1857 <td align=left> 1858 unused<br> 1859 Reset value is 0x0.</td></tr> 1860 </table><p> 1861 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1862 <hr> 1863 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL7">PCIE_BLK3_EXT_GEN2CTRL7 - Register</a></b><br> 1864 Address Offset = 32'h0000_1307<br> 1865 Physical Address = 32'h0000_1307<br> 1866 Reset Value = 16'h0000<br> 1867 Access = RW (16-bit only)<br> 1868 <table border=1 align=center width=100% cellpadding=0> 1869 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1870 <tr bgcolor=WHITE> 1871 <td bgcolor=WHITE align=center valign=top>15:00</td> 1872 <td align=left valign=top>RW</td> 1873 <td align=left valign=top>DisablePmRxFastAcq</td> 1874 <td align=left> 1875 tbd<br> 1876 Reset value is 0x0.</td></tr> 1877 </table><p> 1878 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1879 <hr> 1880 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL8">PCIE_BLK3_EXT_GEN2CTRL8 - Register</a></b><br> 1881 Address Offset = 32'h0000_1308<br> 1882 Physical Address = 32'h0000_1308<br> 1883 Reset Value = 16'h0000<br> 1884 Access = RW (16-bit only)<br> 1885 <table border=1 align=center width=100% cellpadding=0> 1886 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1887 <tr bgcolor=WHITE> 1888 <td bgcolor=WHITE align=center valign=top>15:00</td> 1889 <td align=left valign=top>RW</td> 1890 <td align=left valign=top>mdioRxFastAcqEnable</td> 1891 <td align=left> 1892 tbd<br> 1893 Reset value is 0x0.</td></tr> 1894 </table><p> 1895 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1896 <hr> 1897 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL9">PCIE_BLK3_EXT_GEN2CTRL9 - Register</a></b><br> 1898 Address Offset = 32'h0000_1309<br> 1899 Physical Address = 32'h0000_1309<br> 1900 Reset Value = 16'hffff<br> 1901 Access = RW (16-bit only)<br> 1902 <table border=1 align=center width=100% cellpadding=0> 1903 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1904 <tr bgcolor=WHITE> 1905 <td bgcolor=WHITE align=center valign=top>15:00</td> 1906 <td align=left valign=top>RW</td> 1907 <td align=left valign=top>mdioRxSeqStart</td> 1908 <td align=left> 1909 tbd<br> 1910 Reset value is 0xffff.</td></tr> 1911 </table><p> 1912 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1913 <hr> 1914 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL10">PCIE_BLK3_EXT_GEN2CTRL10 - Register</a></b><br> 1915 Address Offset = 32'h0000_130a<br> 1916 Physical Address = 32'h0000_130a<br> 1917 Reset Value = 16'h0000<br> 1918 Access = RW (16-bit only)<br> 1919 <table border=1 align=center width=100% cellpadding=0> 1920 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1921 <tr bgcolor=WHITE> 1922 <td bgcolor=WHITE align=center valign=top>15:00</td> 1923 <td align=left valign=top>RW</td> 1924 <td align=left valign=top>mdio_TxElectIdle_r</td> 1925 <td align=left> 1926 tbd<br> 1927 Reset value is 0x0.</td></tr> 1928 </table><p> 1929 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1930 <hr> 1931 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL11">PCIE_BLK3_EXT_GEN2CTRL11 - Register</a></b><br> 1932 Address Offset = 32'h0000_130b<br> 1933 Physical Address = 32'h0000_130b<br> 1934 Reset Value = 16'h0000<br> 1935 Access = RW (16-bit only)<br> 1936 <table border=1 align=center width=100% cellpadding=0> 1937 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1938 <tr bgcolor=WHITE> 1939 <td bgcolor=WHITE align=center valign=top>15:00</td> 1940 <td align=left valign=top>RW</td> 1941 <td align=left valign=top>mdio_TxComp_r</td> 1942 <td align=left> 1943 tbd<br> 1944 Reset value is 0x0.</td></tr> 1945 </table><p> 1946 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1947 <hr> 1948 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL12">PCIE_BLK3_EXT_GEN2CTRL12 - Register</a></b><br> 1949 Address Offset = 32'h0000_130c<br> 1950 Physical Address = 32'h0000_130c<br> 1951 Reset Value = 16'h0000<br> 1952 Access = RW (16-bit only)<br> 1953 <table border=1 align=center width=100% cellpadding=0> 1954 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1955 <tr bgcolor=WHITE> 1956 <td bgcolor=WHITE align=center valign=top>15:00</td> 1957 <td align=left valign=top>RW</td> 1958 <td align=left valign=top>mdio_PowerDown_0</td> 1959 <td align=left> 1960 tbd<br> 1961 Reset value is 0x0.</td></tr> 1962 </table><p> 1963 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1964 <hr> 1965 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL13">PCIE_BLK3_EXT_GEN2CTRL13 - Register</a></b><br> 1966 Address Offset = 32'h0000_130d<br> 1967 Physical Address = 32'h0000_130d<br> 1968 Reset Value = 16'h0000<br> 1969 Access = RW (16-bit only)<br> 1970 <table border=1 align=center width=100% cellpadding=0> 1971 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1972 <tr bgcolor=WHITE> 1973 <td bgcolor=WHITE align=center valign=top>15:00</td> 1974 <td align=left valign=top>RW</td> 1975 <td align=left valign=top>mdio_PowerDown_1</td> 1976 <td align=left> 1977 tbd<br> 1978 Reset value is 0x0.</td></tr> 1979 </table><p> 1980 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1981 <hr> 1982 <b><a NAME="PCIE_BLK3_EXT_GEN2CTRL14">PCIE_BLK3_EXT_GEN2CTRL14 - Register</a></b><br> 1983 Address Offset = 32'h0000_130e<br> 1984 Physical Address = 32'h0000_130e<br> 1985 Reset Value = 16'h0000<br> 1986 Access = RW (16-bit only)<br> 1987 <table border=1 align=center width=100% cellpadding=0> 1988 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 1989 <tr bgcolor=WHITE> 1990 <td bgcolor=WHITE align=center valign=top>15:00</td> 1991 <td align=left valign=top>RW</td> 1992 <td align=left valign=top>gen2_ctrl14</td> 1993 <td align=left> 1994 unused<br> 1995 Reset value is 0x0.</td></tr> 1996 </table><p> 1997 <A HREF="#PCIE_BLK3_EXT Registers">Return to PCIE_BLK3_EXT Table</A><p> 1998 <hr> 1999 <H1><a NAME="PCIE_BLK4_EXT Registers">PCIE_BLK4_EXT Registers</a></H1> 2000 <table border=1 align=center width=100% cellpadding=0> 2001 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 2002 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 2003 <tr> 2004 <td align=center>0x1400</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL0">PCIE_BLK4_EXT_LANECTRL0</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lane_ctrl0</div> </td> <td align=center>16'h0000</td></tr> 2005 <tr> 2006 <td align=center>0x1401</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL1">PCIE_BLK4_EXT_LANECTRL1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lane_ctrl1</div> </td> <td align=center>16'h0000</td></tr> 2007 <tr> 2008 <td align=center>0x1402</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL2">PCIE_BLK4_EXT_LANECTRL2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">eden1g</div> </td> <td align=center>16'hffff</td></tr> 2009 <tr> 2010 <td align=center>0x1403</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL3">PCIE_BLK4_EXT_LANECTRL3</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">cdet_en1g</div> </td> <td align=center>16'hffff</td></tr> 2011 <tr> 2012 <td align=center>0x1404</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL4">PCIE_BLK4_EXT_LANECTRL4</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">pwrdwn_rx_r</div> </td> <td align=center>16'h0000</td></tr> 2013 <tr> 2014 <td align=center>0x1405</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL5">PCIE_BLK4_EXT_LANECTRL5</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">pwrdwn_tx_r</div> </td> <td align=center>16'h0000</td></tr> 2015 <tr> 2016 <td align=center>0x1406</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL6">PCIE_BLK4_EXT_LANECTRL6</A><br>Register</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pwrdwn_10g_pll_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pwrdwn_pll_r</div> </td> <td align=center>16'h0000</td></tr> 2017 <tr> 2018 <td align=center>0x1407</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL7">PCIE_BLK4_EXT_LANECTRL7</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rst_sw_ln</div> </td> <td align=center>16'h0000</td></tr> 2019 <tr> 2020 <td align=center>0x1408</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL8">PCIE_BLK4_EXT_LANECTRL8</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">reset_anlg_r_ln</div> </td> <td align=center>16'h0000</td></tr> 2021 <tr> 2022 <td align=center>0x1409</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL9">PCIE_BLK4_EXT_LANECTRL9</A><br>Register</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_cont_en3</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">TxBeaconData</div> </td> <td align=center>16'h0000</td></tr> 2023 <tr> 2024 <td align=center>0x140A</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL10">PCIE_BLK4_EXT_LANECTRL10</A><br>Register</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">common_clock_fifo_shrink</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">gp_in0_disable</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">enable_mdwr4rst</div> </td> <td align=center>16'h0003</td></tr> 2025 <tr> 2026 <td align=center>0x140B</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL11">PCIE_BLK4_EXT_LANECTRL11</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">elastic_autorst_en</div> </td> <td align=center>16'hffff</td></tr> 2027 <tr> 2028 <td align=center>0x140C</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL12">PCIE_BLK4_EXT_LANECTRL12</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">comma_adj_fsm_sel</div> </td> <td align=center>16'h0000</td></tr> 2029 <tr> 2030 <td align=center>0x140D</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL13">PCIE_BLK4_EXT_LANECTRL13</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">RcvrDetectTimeout</div> </td> <td align=center>16'h007e</td></tr> 2031 <tr> 2032 <td align=center>0x140E</td><td><A HREF="#PCIE_BLK4_EXT_LANECTRL14">PCIE_BLK4_EXT_LANECTRL14</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lane_ctrl14</div> </td> <td align=center>16'h0000</td></tr> 2033 </table><p> 2034 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 2035 <hr> 2036 <b><a NAME="PCIE_BLK4_EXT_LANECTRL0">PCIE_BLK4_EXT_LANECTRL0 - Register</a></b><br> 2037 Address Offset = 32'h0000_1400<br> 2038 Physical Address = 32'h0000_1400<br> 2039 Reset Value = 16'h0000<br> 2040 Access = RW (16-bit only)<br> 2041 <table border=1 align=center width=100% cellpadding=0> 2042 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2043 <tr bgcolor=WHITE> 2044 <td bgcolor=WHITE align=center valign=top>15:00</td> 2045 <td align=left valign=top>RW</td> 2046 <td align=left valign=top>lane_ctrl0</td> 2047 <td align=left> 2048 unused<br> 2049 Reset value is 0x0.</td></tr> 2050 </table><p> 2051 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2052 <hr> 2053 <b><a NAME="PCIE_BLK4_EXT_LANECTRL1">PCIE_BLK4_EXT_LANECTRL1 - Register</a></b><br> 2054 Address Offset = 32'h0000_1401<br> 2055 Physical Address = 32'h0000_1401<br> 2056 Reset Value = 16'h0000<br> 2057 Access = RW (16-bit only)<br> 2058 <table border=1 align=center width=100% cellpadding=0> 2059 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2060 <tr bgcolor=WHITE> 2061 <td bgcolor=WHITE align=center valign=top>15:00</td> 2062 <td align=left valign=top>RW</td> 2063 <td align=left valign=top>lane_ctrl1</td> 2064 <td align=left> 2065 unused<br> 2066 Reset value is 0x0.</td></tr> 2067 </table><p> 2068 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2069 <hr> 2070 <b><a NAME="PCIE_BLK4_EXT_LANECTRL2">PCIE_BLK4_EXT_LANECTRL2 - Register</a></b><br> 2071 Address Offset = 32'h0000_1402<br> 2072 Physical Address = 32'h0000_1402<br> 2073 Reset Value = 16'hffff<br> 2074 Access = RW (16-bit only)<br> 2075 <table border=1 align=center width=100% cellpadding=0> 2076 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2077 <tr bgcolor=WHITE> 2078 <td bgcolor=WHITE align=center valign=top>15:00</td> 2079 <td align=left valign=top>RW</td> 2080 <td align=left valign=top>eden1g</td> 2081 <td align=left> 2082 tbd<br> 2083 Reset value is 0xffff.</td></tr> 2084 </table><p> 2085 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2086 <hr> 2087 <b><a NAME="PCIE_BLK4_EXT_LANECTRL3">PCIE_BLK4_EXT_LANECTRL3 - Register</a></b><br> 2088 Address Offset = 32'h0000_1403<br> 2089 Physical Address = 32'h0000_1403<br> 2090 Reset Value = 16'hffff<br> 2091 Access = RW (16-bit only)<br> 2092 <table border=1 align=center width=100% cellpadding=0> 2093 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2094 <tr bgcolor=WHITE> 2095 <td bgcolor=WHITE align=center valign=top>15:00</td> 2096 <td align=left valign=top>RW</td> 2097 <td align=left valign=top>cdet_en1g</td> 2098 <td align=left> 2099 tbd<br> 2100 Reset value is 0xffff.</td></tr> 2101 </table><p> 2102 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2103 <hr> 2104 <b><a NAME="PCIE_BLK4_EXT_LANECTRL4">PCIE_BLK4_EXT_LANECTRL4 - Register</a></b><br> 2105 Address Offset = 32'h0000_1404<br> 2106 Physical Address = 32'h0000_1404<br> 2107 Reset Value = 16'h0000<br> 2108 Access = RW (16-bit only)<br> 2109 <table border=1 align=center width=100% cellpadding=0> 2110 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2111 <tr bgcolor=WHITE> 2112 <td bgcolor=WHITE align=center valign=top>15:00</td> 2113 <td align=left valign=top>RW</td> 2114 <td align=left valign=top>pwrdwn_rx_r</td> 2115 <td align=left> 2116 tbd<br> 2117 Reset value is 0x0.</td></tr> 2118 </table><p> 2119 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2120 <hr> 2121 <b><a NAME="PCIE_BLK4_EXT_LANECTRL5">PCIE_BLK4_EXT_LANECTRL5 - Register</a></b><br> 2122 Address Offset = 32'h0000_1405<br> 2123 Physical Address = 32'h0000_1405<br> 2124 Reset Value = 16'h0000<br> 2125 Access = RW (16-bit only)<br> 2126 <table border=1 align=center width=100% cellpadding=0> 2127 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2128 <tr bgcolor=WHITE> 2129 <td bgcolor=WHITE align=center valign=top>15:00</td> 2130 <td align=left valign=top>RW</td> 2131 <td align=left valign=top>pwrdwn_tx_r</td> 2132 <td align=left> 2133 tbd<br> 2134 Reset value is 0x0.</td></tr> 2135 </table><p> 2136 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2137 <hr> 2138 <b><a NAME="PCIE_BLK4_EXT_LANECTRL6">PCIE_BLK4_EXT_LANECTRL6 - Register</a></b><br> 2139 Address Offset = 32'h0000_1406<br> 2140 Physical Address = 32'h0000_1406<br> 2141 Reset Value = 16'h0000<br> 2142 Access = RW (16-bit only)<br> 2143 <table border=1 align=center width=100% cellpadding=0> 2144 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2145 <tr bgcolor=WHITE> 2146 <td bgcolor=WHITE align=center valign=top>15:02</td> 2147 <td align=left valign=top>RSVD</td> 2148 <td align=left valign=top>Reserved</td> 2149 <td align=left> 2150 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 2151 <tr bgcolor=WHITE> 2152 <td bgcolor=WHITE align=center valign=top>01</td> 2153 <td align=left valign=top>RW</td> 2154 <td align=left valign=top>pwrdwn_10g_pll_dis</td> 2155 <td align=left> 2156 tbd<br> 2157 Reset value is 0x0.</td></tr> 2158 <tr bgcolor=WHITE> 2159 <td bgcolor=WHITE align=center valign=top>00</td> 2160 <td align=left valign=top>RW</td> 2161 <td align=left valign=top>pwrdwn_pll_r</td> 2162 <td align=left> 2163 tbd<br> 2164 Reset value is 0x0.</td></tr> 2165 </table><p> 2166 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2167 <hr> 2168 <b><a NAME="PCIE_BLK4_EXT_LANECTRL7">PCIE_BLK4_EXT_LANECTRL7 - Register</a></b><br> 2169 Address Offset = 32'h0000_1407<br> 2170 Physical Address = 32'h0000_1407<br> 2171 Reset Value = 16'h0000<br> 2172 Access = RW (16-bit only)<br> 2173 <table border=1 align=center width=100% cellpadding=0> 2174 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2175 <tr bgcolor=WHITE> 2176 <td bgcolor=WHITE align=center valign=top>15:00</td> 2177 <td align=left valign=top>RW</td> 2178 <td align=left valign=top>rst_sw_ln</td> 2179 <td align=left> 2180 tbd<br> 2181 Reset value is 0x0.</td></tr> 2182 </table><p> 2183 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2184 <hr> 2185 <b><a NAME="PCIE_BLK4_EXT_LANECTRL8">PCIE_BLK4_EXT_LANECTRL8 - Register</a></b><br> 2186 Address Offset = 32'h0000_1408<br> 2187 Physical Address = 32'h0000_1408<br> 2188 Reset Value = 16'h0000<br> 2189 Access = RW (16-bit only)<br> 2190 <table border=1 align=center width=100% cellpadding=0> 2191 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2192 <tr bgcolor=WHITE> 2193 <td bgcolor=WHITE align=center valign=top>15:00</td> 2194 <td align=left valign=top>RW</td> 2195 <td align=left valign=top>reset_anlg_r_ln</td> 2196 <td align=left> 2197 tbd<br> 2198 Reset value is 0x0.</td></tr> 2199 </table><p> 2200 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2201 <hr> 2202 <b><a NAME="PCIE_BLK4_EXT_LANECTRL9">PCIE_BLK4_EXT_LANECTRL9 - Register</a></b><br> 2203 Address Offset = 32'h0000_1409<br> 2204 Physical Address = 32'h0000_1409<br> 2205 Reset Value = 16'h0000<br> 2206 Access = RW (16-bit only)<br> 2207 <table border=1 align=center width=100% cellpadding=0> 2208 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2209 <tr bgcolor=WHITE> 2210 <td bgcolor=WHITE align=center valign=top>15:12</td> 2211 <td align=left valign=top>RSVD</td> 2212 <td align=left valign=top>Reserved</td> 2213 <td align=left> 2214 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 2215 <tr bgcolor=WHITE> 2216 <td bgcolor=WHITE align=center valign=top>11</td> 2217 <td align=left valign=top>RW</td> 2218 <td align=left valign=top>mdio_cont_en3</td> 2219 <td align=left> 2220 tbd<br> 2221 Reset value is 0x0.</td></tr> 2222 <tr bgcolor=WHITE> 2223 <td bgcolor=WHITE align=center valign=top>10</td> 2224 <td align=left valign=top>RSVD</td> 2225 <td align=left valign=top>Reserved</td> 2226 <td align=left> 2227 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 2228 <tr bgcolor=WHITE> 2229 <td bgcolor=WHITE align=center valign=top>09:00</td> 2230 <td align=left valign=top>RW</td> 2231 <td align=left valign=top>TxBeaconData</td> 2232 <td align=left> 2233 tbd<br> 2234 Reset value is 0x0.</td></tr> 2235 </table><p> 2236 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2237 <hr> 2238 <b><a NAME="PCIE_BLK4_EXT_LANECTRL10">PCIE_BLK4_EXT_LANECTRL10 - Register</a></b><br> 2239 Address Offset = 32'h0000_140a<br> 2240 Physical Address = 32'h0000_140a<br> 2241 Reset Value = 16'h0003<br> 2242 Access = RW (16-bit only)<br> 2243 <table border=1 align=center width=100% cellpadding=0> 2244 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2245 <tr bgcolor=WHITE> 2246 <td bgcolor=WHITE align=center valign=top>15:03</td> 2247 <td align=left valign=top>RSVD</td> 2248 <td align=left valign=top>Reserved</td> 2249 <td align=left> 2250 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 2251 <tr bgcolor=WHITE> 2252 <td bgcolor=WHITE align=center valign=top>02</td> 2253 <td align=left valign=top>RW</td> 2254 <td align=left valign=top>common_clock_fifo_shrink</td> 2255 <td align=left> 2256 common_clock_fifo_shrink<br> 2257 Reset value is 0x0.</td></tr> 2258 <tr bgcolor=WHITE> 2259 <td bgcolor=WHITE align=center valign=top>01</td> 2260 <td align=left valign=top>RW</td> 2261 <td align=left valign=top>gp_in0_disable</td> 2262 <td align=left> 2263 gp_in0_disable<br> 2264 Reset value is 0x1.</td></tr> 2265 <tr bgcolor=WHITE> 2266 <td bgcolor=WHITE align=center valign=top>00</td> 2267 <td align=left valign=top>RW</td> 2268 <td align=left valign=top>enable_mdwr4rst</td> 2269 <td align=left> 2270 enable_mdwr4rst<br> 2271 Reset value is 0x1.</td></tr> 2272 </table><p> 2273 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2274 <hr> 2275 <b><a NAME="PCIE_BLK4_EXT_LANECTRL11">PCIE_BLK4_EXT_LANECTRL11 - Register</a></b><br> 2276 Address Offset = 32'h0000_140b<br> 2277 Physical Address = 32'h0000_140b<br> 2278 Reset Value = 16'hffff<br> 2279 Access = RW (16-bit only)<br> 2280 <table border=1 align=center width=100% cellpadding=0> 2281 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2282 <tr bgcolor=WHITE> 2283 <td bgcolor=WHITE align=center valign=top>15:00</td> 2284 <td align=left valign=top>RW</td> 2285 <td align=left valign=top>elastic_autorst_en</td> 2286 <td align=left> 2287 tbd<br> 2288 Reset value is 0xffff.</td></tr> 2289 </table><p> 2290 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2291 <hr> 2292 <b><a NAME="PCIE_BLK4_EXT_LANECTRL12">PCIE_BLK4_EXT_LANECTRL12 - Register</a></b><br> 2293 Address Offset = 32'h0000_140c<br> 2294 Physical Address = 32'h0000_140c<br> 2295 Reset Value = 16'h0000<br> 2296 Access = RW (16-bit only)<br> 2297 <table border=1 align=center width=100% cellpadding=0> 2298 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2299 <tr bgcolor=WHITE> 2300 <td bgcolor=WHITE align=center valign=top>15:00</td> 2301 <td align=left valign=top>RW</td> 2302 <td align=left valign=top>comma_adj_fsm_sel</td> 2303 <td align=left> 2304 tbd<br> 2305 Reset value is 0x0.</td></tr> 2306 </table><p> 2307 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2308 <hr> 2309 <b><a NAME="PCIE_BLK4_EXT_LANECTRL13">PCIE_BLK4_EXT_LANECTRL13 - Register</a></b><br> 2310 Address Offset = 32'h0000_140d<br> 2311 Physical Address = 32'h0000_140d<br> 2312 Reset Value = 16'h007e<br> 2313 Access = RW (16-bit only)<br> 2314 <table border=1 align=center width=100% cellpadding=0> 2315 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2316 <tr bgcolor=WHITE> 2317 <td bgcolor=WHITE align=center valign=top>15:00</td> 2318 <td align=left valign=top>RW</td> 2319 <td align=left valign=top>RcvrDetectTimeout</td> 2320 <td align=left> 2321 tbd<br> 2322 Reset value is 0x7e.</td></tr> 2323 </table><p> 2324 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2325 <hr> 2326 <b><a NAME="PCIE_BLK4_EXT_LANECTRL14">PCIE_BLK4_EXT_LANECTRL14 - Register</a></b><br> 2327 Address Offset = 32'h0000_140e<br> 2328 Physical Address = 32'h0000_140e<br> 2329 Reset Value = 16'h0000<br> 2330 Access = RW (16-bit only)<br> 2331 <table border=1 align=center width=100% cellpadding=0> 2332 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2333 <tr bgcolor=WHITE> 2334 <td bgcolor=WHITE align=center valign=top>15:00</td> 2335 <td align=left valign=top>RW</td> 2336 <td align=left valign=top>lane_ctrl14</td> 2337 <td align=left> 2338 unused<br> 2339 Reset value is 0x0.</td></tr> 2340 </table><p> 2341 <A HREF="#PCIE_BLK4_EXT Registers">Return to PCIE_BLK4_EXT Table</A><p> 2342 <hr> 2343 <H1><a NAME="PCIE_BLK5_EXT Registers">PCIE_BLK5_EXT Registers</a></H1> 2344 <table border=1 align=center width=100% cellpadding=0> 2345 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 2346 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 2347 <tr> 2348 <td align=center>0x1500</td><td><A HREF="#PCIE_BLK5_EXT_LANECTRL15">PCIE_BLK5_EXT_LANECTRL15</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lane_ctrl15</div> </td> <td align=center>16'h0000</td></tr> 2349 <tr> 2350 <td align=center>0x1501</td><td><A HREF="#PCIE_BLK5_EXT_LANEPRBS0">PCIE_BLK5_EXT_LANEPRBS0</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">prbs_en</div> </td> <td align=center>16'h0000</td></tr> 2351 <tr> 2352 <td align=center>0x1502</td><td><A HREF="#PCIE_BLK5_EXT_LANEPRBS1">PCIE_BLK5_EXT_LANEPRBS1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">prbs_inv</div> </td> <td align=center>16'h0000</td></tr> 2353 <tr> 2354 <td align=center>0x1503</td><td><A HREF="#PCIE_BLK5_EXT_LANEPRBS2">PCIE_BLK5_EXT_LANEPRBS2</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order15a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order14a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order13a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order12a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order11a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order10a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order9a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order8a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order7a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order6a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order5a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order4a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order3a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order2a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order1a</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_order0a</div> </td> <td align=center>16'h0000</td></tr> 2355 <tr> 2356 <td align=center>0x1504</td><td><A HREF="#PCIE_BLK5_EXT_LANEPRBS3">PCIE_BLK5_EXT_LANEPRBS3</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order7</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order6</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order5</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order4</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order0</div> </td> <td align=center>16'h0000</td></tr> 2357 <tr> 2358 <td align=center>0x1505</td><td><A HREF="#PCIE_BLK5_EXT_LANEPRBS4">PCIE_BLK5_EXT_LANEPRBS4</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order15</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order14</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order13</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order12</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order11</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order10</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order9</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_order8</div> </td> <td align=center>16'h0000</td></tr> 2359 <tr> 2360 <td align=center>0x1506</td><td><A HREF="#PCIE_BLK5_EXT_LANETEST0">PCIE_BLK5_EXT_LANETEST0</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lfck_sigdet_sel_mdio_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_lfck_sigdet_sel_cnt0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_lfck_sigdet_sel_refclk</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ext_pwrdn_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pwrdn_safe_dis_tmp</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pwrdn_clks_en</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_lock_rstb_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lfck_bypass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_snoop_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_StandAloneMode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_PllTuningBypass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_lfck_rx_sel_cnt0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_lfck_rx_sel_refclk</div> </td> <td align=center>16'h1220</td></tr> 2361 <tr> 2362 <td align=center>0x1507</td><td><A HREF="#PCIE_BLK5_EXT_LANETEST1">PCIE_BLK5_EXT_LANETEST1</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comp_start</div> </td> <td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tmux_sel</div> </td> <td align=center>16'h0000</td></tr> 2363 <tr> 2364 <td align=center>0x1508</td><td><A HREF="#PCIE_BLK5_EXT_COMP_DELAY0">PCIE_BLK5_EXT_COMP_DELAY0</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay3_11</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay2_10</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay1_9</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay0_8</div> </td> <td align=center>16'h3210</td></tr> 2365 <tr> 2366 <td align=center>0x1509</td><td><A HREF="#PCIE_BLK5_EXT_COMP_DELAY1">PCIE_BLK5_EXT_COMP_DELAY1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay7_15</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay6_14</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay5_13</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">comp_delay4_12</div> </td> <td align=center>16'h7654</td></tr> 2367 <tr> 2368 <td align=center>0x150A</td><td><A HREF="#PCIE_BLK5_EXT_COMP_TYPE">PCIE_BLK5_EXT_COMP_TYPE</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">comp_type</div> </td> <td align=center>16'h0000</td></tr> 2369 <tr> 2370 <td align=center>0x150B</td><td><A HREF="#PCIE_BLK5_EXT_COMP_ENABLE">PCIE_BLK5_EXT_COMP_ENABLE</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">comp_enable</div> </td> <td align=center>16'h0000</td></tr> 2371 <tr> 2372 <td align=center>0x150E</td><td><A HREF="#PCIE_BLK5_EXT_XGXS_FE_TMUX">PCIE_BLK5_EXT_XGXS_FE_TMUX</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">XGXS_fe_tmux</div> </td> <td align=center>16'h0000</td></tr> 2373 </table><p> 2374 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 2375 <hr> 2376 <b><a NAME="PCIE_BLK5_EXT_LANECTRL15">PCIE_BLK5_EXT_LANECTRL15 - Register</a></b><br> 2377 Address Offset = 32'h0000_1500<br> 2378 Physical Address = 32'h0000_1500<br> 2379 Reset Value = 16'h0000<br> 2380 Access = RW (16-bit only)<br> 2381 <table border=1 align=center width=100% cellpadding=0> 2382 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2383 <tr bgcolor=WHITE> 2384 <td bgcolor=WHITE align=center valign=top>15:00</td> 2385 <td align=left valign=top>RW</td> 2386 <td align=left valign=top>lane_ctrl15</td> 2387 <td align=left> 2388 unused<br> 2389 Reset value is 0x0.</td></tr> 2390 </table><p> 2391 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2392 <hr> 2393 <b><a NAME="PCIE_BLK5_EXT_LANEPRBS0">PCIE_BLK5_EXT_LANEPRBS0 - Register</a></b><br> 2394 Address Offset = 32'h0000_1501<br> 2395 Physical Address = 32'h0000_1501<br> 2396 Reset Value = 16'h0000<br> 2397 Access = RW (16-bit only)<br> 2398 <table border=1 align=center width=100% cellpadding=0> 2399 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2400 <tr bgcolor=WHITE> 2401 <td bgcolor=WHITE align=center valign=top>15:00</td> 2402 <td align=left valign=top>RW</td> 2403 <td align=left valign=top>prbs_en</td> 2404 <td align=left> 2405 tbd<br> 2406 Reset value is 0x0.</td></tr> 2407 </table><p> 2408 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2409 <hr> 2410 <b><a NAME="PCIE_BLK5_EXT_LANEPRBS1">PCIE_BLK5_EXT_LANEPRBS1 - Register</a></b><br> 2411 Address Offset = 32'h0000_1502<br> 2412 Physical Address = 32'h0000_1502<br> 2413 Reset Value = 16'h0000<br> 2414 Access = RW (16-bit only)<br> 2415 <table border=1 align=center width=100% cellpadding=0> 2416 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2417 <tr bgcolor=WHITE> 2418 <td bgcolor=WHITE align=center valign=top>15:00</td> 2419 <td align=left valign=top>RW</td> 2420 <td align=left valign=top>prbs_inv</td> 2421 <td align=left> 2422 tbd<br> 2423 Reset value is 0x0.</td></tr> 2424 </table><p> 2425 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2426 <hr> 2427 <b><a NAME="PCIE_BLK5_EXT_LANEPRBS2">PCIE_BLK5_EXT_LANEPRBS2 - Register</a></b><br> 2428 Address Offset = 32'h0000_1503<br> 2429 Physical Address = 32'h0000_1503<br> 2430 Reset Value = 16'h0000<br> 2431 Access = RW (16-bit only)<br> 2432 <table border=1 align=center width=100% cellpadding=0> 2433 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2434 <tr bgcolor=WHITE> 2435 <td bgcolor=WHITE align=center valign=top>15</td> 2436 <td align=left valign=top>RW</td> 2437 <td align=left valign=top>prbs_order15a</td> 2438 <td align=left> 2439 This bit was added to add more PRBS patterns<br> 2440 must be used in association with registers 0x14 & 0x15<br> 2441 Set when using PRBS 9,10,&11<br> 2442 Reset value is 0x0.</td></tr> 2443 <tr bgcolor=WHITE> 2444 <td bgcolor=WHITE align=center valign=top>14</td> 2445 <td align=left valign=top>RW</td> 2446 <td align=left valign=top>prbs_order14a</td> 2447 <td align=left> 2448 This bit was added to add more PRBS patterns<br> 2449 must be used in association with registers 0x14 & 0x15<br> 2450 Set when using PRBS 9,10,&11<br> 2451 Reset value is 0x0.</td></tr> 2452 <tr bgcolor=WHITE> 2453 <td bgcolor=WHITE align=center valign=top>13</td> 2454 <td align=left valign=top>RW</td> 2455 <td align=left valign=top>prbs_order13a</td> 2456 <td align=left> 2457 This bit was added to add more PRBS patterns<br> 2458 must be used in association with registers 0x14 & 0x15<br> 2459 Set when using PRBS 9,10,&11<br> 2460 Reset value is 0x0.</td></tr> 2461 <tr bgcolor=WHITE> 2462 <td bgcolor=WHITE align=center valign=top>12</td> 2463 <td align=left valign=top>RW</td> 2464 <td align=left valign=top>prbs_order12a</td> 2465 <td align=left> 2466 This bit was added to add more PRBS patterns<br> 2467 must be used in association with registers 0x14 & 0x15<br> 2468 Set when using PRBS 9,10,&11<br> 2469 Reset value is 0x0.</td></tr> 2470 <tr bgcolor=WHITE> 2471 <td bgcolor=WHITE align=center valign=top>11</td> 2472 <td align=left valign=top>RW</td> 2473 <td align=left valign=top>prbs_order11a</td> 2474 <td align=left> 2475 This bit was added to add more PRBS patterns<br> 2476 must be used in association with registers 0x14 & 0x15<br> 2477 Set when using PRBS 9,10,&11<br> 2478 Reset value is 0x0.</td></tr> 2479 <tr bgcolor=WHITE> 2480 <td bgcolor=WHITE align=center valign=top>10</td> 2481 <td align=left valign=top>RW</td> 2482 <td align=left valign=top>prbs_order10a</td> 2483 <td align=left> 2484 This bit was added to add more PRBS patterns<br> 2485 must be used in association with registers 0x14 & 0x15<br> 2486 Set when using PRBS 9,10,&11<br> 2487 Reset value is 0x0.</td></tr> 2488 <tr bgcolor=WHITE> 2489 <td bgcolor=WHITE align=center valign=top>09</td> 2490 <td align=left valign=top>RW</td> 2491 <td align=left valign=top>prbs_order9a</td> 2492 <td align=left> 2493 This bit was added to add more PRBS patterns<br> 2494 must be used in association with registers 0x14 & 0x15<br> 2495 Set when using PRBS 9,10,&11<br> 2496 Reset value is 0x0.</td></tr> 2497 <tr bgcolor=WHITE> 2498 <td bgcolor=WHITE align=center valign=top>08</td> 2499 <td align=left valign=top>RW</td> 2500 <td align=left valign=top>prbs_order8a</td> 2501 <td align=left> 2502 This bit was added to add more PRBS patterns<br> 2503 must be used in association with registers 0x14 & 0x15<br> 2504 Set when using PRBS 9,10,&11<br> 2505 Reset value is 0x0.</td></tr> 2506 <tr bgcolor=WHITE> 2507 <td bgcolor=WHITE align=center valign=top>07</td> 2508 <td align=left valign=top>RW</td> 2509 <td align=left valign=top>prbs_order7a</td> 2510 <td align=left> 2511 This bit was added to add more PRBS patterns<br> 2512 must be used in association with registers 0x14 & 0x15<br> 2513 Set when using PRBS 9,10,&11<br> 2514 Reset value is 0x0.</td></tr> 2515 <tr bgcolor=WHITE> 2516 <td bgcolor=WHITE align=center valign=top>06</td> 2517 <td align=left valign=top>RW</td> 2518 <td align=left valign=top>prbs_order6a</td> 2519 <td align=left> 2520 This bit was added to add more PRBS patterns<br> 2521 must be used in association with registers 0x14 & 0x15<br> 2522 Set when using PRBS 9,10,&11<br> 2523 Reset value is 0x0.</td></tr> 2524 <tr bgcolor=WHITE> 2525 <td bgcolor=WHITE align=center valign=top>05</td> 2526 <td align=left valign=top>RW</td> 2527 <td align=left valign=top>prbs_order5a</td> 2528 <td align=left> 2529 This bit was added to add more PRBS patterns<br> 2530 must be used in association with registers 0x14 & 0x15<br> 2531 Set when using PRBS 9,10,&11<br> 2532 Reset value is 0x0.</td></tr> 2533 <tr bgcolor=WHITE> 2534 <td bgcolor=WHITE align=center valign=top>04</td> 2535 <td align=left valign=top>RW</td> 2536 <td align=left valign=top>prbs_order4a</td> 2537 <td align=left> 2538 This bit was added to add more PRBS patterns<br> 2539 must be used in association with registers 0x14 & 0x15<br> 2540 Set when using PRBS 9,10,&11<br> 2541 Reset value is 0x0.</td></tr> 2542 <tr bgcolor=WHITE> 2543 <td bgcolor=WHITE align=center valign=top>03</td> 2544 <td align=left valign=top>RW</td> 2545 <td align=left valign=top>prbs_order3a</td> 2546 <td align=left> 2547 This bit was added to add more PRBS patterns<br> 2548 must be used in association with registers 0x14 & 0x15<br> 2549 Set when using PRBS 9,10,&11<br> 2550 Reset value is 0x0.</td></tr> 2551 <tr bgcolor=WHITE> 2552 <td bgcolor=WHITE align=center valign=top>02</td> 2553 <td align=left valign=top>RW</td> 2554 <td align=left valign=top>prbs_order2a</td> 2555 <td align=left> 2556 This bit was added to add more PRBS patterns<br> 2557 must be used in association with registers 0x14 & 0x15<br> 2558 Set when using PRBS 9,10,&11<br> 2559 Reset value is 0x0.</td></tr> 2560 <tr bgcolor=WHITE> 2561 <td bgcolor=WHITE align=center valign=top>01</td> 2562 <td align=left valign=top>RW</td> 2563 <td align=left valign=top>prbs_order1a</td> 2564 <td align=left> 2565 This bit was added to add more PRBS patterns<br> 2566 must be used in association with registers 0x14 & 0x15<br> 2567 Set when using PRBS 9,10,&11<br> 2568 Reset value is 0x0.</td></tr> 2569 <tr bgcolor=WHITE> 2570 <td bgcolor=WHITE align=center valign=top>00</td> 2571 <td align=left valign=top>RW</td> 2572 <td align=left valign=top>prbs_order0a</td> 2573 <td align=left> 2574 This bit was added to add more PRBS patterns<br> 2575 must be used in association with registers 0x14 & 0x15<br> 2576 Set when using PRBS 9,10,&11<br> 2577 prbs_orderXa    prbs_orderX<br> 2578      0                   xx       - PRBS 7,15,23,&31 are used<br> 2579      1                   00       - PRBS 9<br> 2580      1                   01       - PRBS 10<br> 2581      1                   10       - PRBS 11<br> 2582 Reset value is 0x0.</td></tr> 2583 </table><p> 2584 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2585 <hr> 2586 <b><a NAME="PCIE_BLK5_EXT_LANEPRBS3">PCIE_BLK5_EXT_LANEPRBS3 - Register</a></b><br> 2587 Address Offset = 32'h0000_1504<br> 2588 Physical Address = 32'h0000_1504<br> 2589 Reset Value = 16'h0000<br> 2590 Access = RW (16-bit only)<br> 2591 <table border=1 align=center width=100% cellpadding=0> 2592 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2593 <tr bgcolor=WHITE> 2594 <td bgcolor=WHITE align=center valign=top>15:14</td> 2595 <td align=left valign=top>RW</td> 2596 <td align=left valign=top>prbs_order7</td> 2597 <td align=left> 2598 Select PRBS pattern<br> 2599 Reset value is 0x0.</td></tr> 2600 <tr bgcolor=WHITE> 2601 <td bgcolor=WHITE align=center valign=top>13:12</td> 2602 <td align=left valign=top>RW</td> 2603 <td align=left valign=top>prbs_order6</td> 2604 <td align=left> 2605 Select PRBS pattern<br> 2606 Reset value is 0x0.</td></tr> 2607 <tr bgcolor=WHITE> 2608 <td bgcolor=WHITE align=center valign=top>11:10</td> 2609 <td align=left valign=top>RW</td> 2610 <td align=left valign=top>prbs_order5</td> 2611 <td align=left> 2612 Select PRBS pattern<br> 2613 Reset value is 0x0.</td></tr> 2614 <tr bgcolor=WHITE> 2615 <td bgcolor=WHITE align=center valign=top>09:08</td> 2616 <td align=left valign=top>RW</td> 2617 <td align=left valign=top>prbs_order4</td> 2618 <td align=left> 2619 Select PRBS pattern<br> 2620 Reset value is 0x0.</td></tr> 2621 <tr bgcolor=WHITE> 2622 <td bgcolor=WHITE align=center valign=top>07:06</td> 2623 <td align=left valign=top>RW</td> 2624 <td align=left valign=top>prbs_order3</td> 2625 <td align=left> 2626 Select PRBS pattern<br> 2627 Reset value is 0x0.</td></tr> 2628 <tr bgcolor=WHITE> 2629 <td bgcolor=WHITE align=center valign=top>05:04</td> 2630 <td align=left valign=top>RW</td> 2631 <td align=left valign=top>prbs_order2</td> 2632 <td align=left> 2633 Select PRBS pattern<br> 2634 Reset value is 0x0.</td></tr> 2635 <tr bgcolor=WHITE> 2636 <td bgcolor=WHITE align=center valign=top>03:02</td> 2637 <td align=left valign=top>RW</td> 2638 <td align=left valign=top>prbs_order1</td> 2639 <td align=left> 2640 Select PRBS pattern<br> 2641 Reset value is 0x0.</td></tr> 2642 <tr bgcolor=WHITE> 2643 <td bgcolor=WHITE align=center valign=top>01:00</td> 2644 <td align=left valign=top>RW</td> 2645 <td align=left valign=top>prbs_order0</td> 2646 <td align=left> 2647 Select PRBS pattern<br> 2648 prbs_orderXa(0x13)    prbs_orderX<br> 2649      0                     00       - PRBS 7<br> 2650      0                     01       - PRBS 15<br> 2651      0                     10       - PRBS 23<br> 2652      0                     11       - PRBS 31<br> 2653      1                     00       - PRBS 9<br> 2654      1                     01       - PRBS 10<br> 2655      1                     10       - PRBS 11<br> 2656 tbd<br> 2657 Reset value is 0x0.</td></tr> 2658 </table><p> 2659 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2660 <hr> 2661 <b><a NAME="PCIE_BLK5_EXT_LANEPRBS4">PCIE_BLK5_EXT_LANEPRBS4 - Register</a></b><br> 2662 Address Offset = 32'h0000_1505<br> 2663 Physical Address = 32'h0000_1505<br> 2664 Reset Value = 16'h0000<br> 2665 Access = RW (16-bit only)<br> 2666 <table border=1 align=center width=100% cellpadding=0> 2667 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2668 <tr bgcolor=WHITE> 2669 <td bgcolor=WHITE align=center valign=top>15:14</td> 2670 <td align=left valign=top>RW</td> 2671 <td align=left valign=top>prbs_order15</td> 2672 <td align=left> 2673 Select PRBS pattern<br> 2674 Reset value is 0x0.</td></tr> 2675 <tr bgcolor=WHITE> 2676 <td bgcolor=WHITE align=center valign=top>13:12</td> 2677 <td align=left valign=top>RW</td> 2678 <td align=left valign=top>prbs_order14</td> 2679 <td align=left> 2680 Select PRBS pattern<br> 2681 Reset value is 0x0.</td></tr> 2682 <tr bgcolor=WHITE> 2683 <td bgcolor=WHITE align=center valign=top>11:10</td> 2684 <td align=left valign=top>RW</td> 2685 <td align=left valign=top>prbs_order13</td> 2686 <td align=left> 2687 Select PRBS pattern<br> 2688 Reset value is 0x0.</td></tr> 2689 <tr bgcolor=WHITE> 2690 <td bgcolor=WHITE align=center valign=top>09:08</td> 2691 <td align=left valign=top>RW</td> 2692 <td align=left valign=top>prbs_order12</td> 2693 <td align=left> 2694 Select PRBS pattern<br> 2695 Reset value is 0x0.</td></tr> 2696 <tr bgcolor=WHITE> 2697 <td bgcolor=WHITE align=center valign=top>07:06</td> 2698 <td align=left valign=top>RW</td> 2699 <td align=left valign=top>prbs_order11</td> 2700 <td align=left> 2701 Select PRBS pattern<br> 2702 Reset value is 0x0.</td></tr> 2703 <tr bgcolor=WHITE> 2704 <td bgcolor=WHITE align=center valign=top>05:04</td> 2705 <td align=left valign=top>RW</td> 2706 <td align=left valign=top>prbs_order10</td> 2707 <td align=left> 2708 Select PRBS pattern<br> 2709 Reset value is 0x0.</td></tr> 2710 <tr bgcolor=WHITE> 2711 <td bgcolor=WHITE align=center valign=top>03:02</td> 2712 <td align=left valign=top>RW</td> 2713 <td align=left valign=top>prbs_order9</td> 2714 <td align=left> 2715 Select PRBS pattern<br> 2716 Reset value is 0x0.</td></tr> 2717 <tr bgcolor=WHITE> 2718 <td bgcolor=WHITE align=center valign=top>01:00</td> 2719 <td align=left valign=top>RW</td> 2720 <td align=left valign=top>prbs_order8</td> 2721 <td align=left> 2722 Select PRBS pattern<br> 2723 Reset value is 0x0.</td></tr> 2724 </table><p> 2725 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2726 <hr> 2727 <b><a NAME="PCIE_BLK5_EXT_LANETEST0">PCIE_BLK5_EXT_LANETEST0 - Register</a></b><br> 2728 Address Offset = 32'h0000_1506<br> 2729 Physical Address = 32'h0000_1506<br> 2730 Reset Value = 16'h1220<br> 2731 Access = RW (16-bit only)<br> 2732 <table border=1 align=center width=100% cellpadding=0> 2733 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2734 <tr bgcolor=WHITE> 2735 <td bgcolor=WHITE align=center valign=top>15</td> 2736 <td align=left valign=top>RW</td> 2737 <td align=left valign=top>lfck_sigdet_sel_mdio_sel</td> 2738 <td align=left> 2739 tbd<br> 2740 Reset value is 0x0.</td></tr> 2741 <tr bgcolor=WHITE> 2742 <td bgcolor=WHITE align=center valign=top>14</td> 2743 <td align=left valign=top>RSVD</td> 2744 <td align=left valign=top>Reserved</td> 2745 <td align=left> 2746 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 2747 <tr bgcolor=WHITE> 2748 <td bgcolor=WHITE align=center valign=top>13</td> 2749 <td align=left valign=top>RW</td> 2750 <td align=left valign=top>mdio_lfck_sigdet_sel_cnt0</td> 2751 <td align=left> 2752 tbd<br> 2753 Reset value is 0x0.</td></tr> 2754 <tr bgcolor=WHITE> 2755 <td bgcolor=WHITE align=center valign=top>12</td> 2756 <td align=left valign=top>RW</td> 2757 <td align=left valign=top>mdio_lfck_sigdet_sel_refclk</td> 2758 <td align=left> 2759 tbd<br> 2760 Reset value is 0x1.</td></tr> 2761 <tr bgcolor=WHITE> 2762 <td bgcolor=WHITE align=center valign=top>11</td> 2763 <td align=left valign=top>RSVD</td> 2764 <td align=left valign=top>Reserved</td> 2765 <td align=left> 2766 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 2767 <tr bgcolor=WHITE> 2768 <td bgcolor=WHITE align=center valign=top>10</td> 2769 <td align=left valign=top>RW</td> 2770 <td align=left valign=top>ext_pwrdn_dis</td> 2771 <td align=left> 2772 tbd<br> 2773 Reset value is 0x0.</td></tr> 2774 <tr bgcolor=WHITE> 2775 <td bgcolor=WHITE align=center valign=top>09</td> 2776 <td align=left valign=top>RW</td> 2777 <td align=left valign=top>pwrdn_safe_dis_tmp</td> 2778 <td align=left> 2779 tbd<br> 2780 Reset value is 0x1.</td></tr> 2781 <tr bgcolor=WHITE> 2782 <td bgcolor=WHITE align=center valign=top>08</td> 2783 <td align=left valign=top>RW</td> 2784 <td align=left valign=top>pwrdn_clks_en</td> 2785 <td align=left> 2786 tbd<br> 2787 Reset value is 0x0.</td></tr> 2788 <tr bgcolor=WHITE> 2789 <td bgcolor=WHITE align=center valign=top>07</td> 2790 <td align=left valign=top>RSVD</td> 2791 <td align=left valign=top>Reserved</td> 2792 <td align=left> 2793 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 2794 <tr bgcolor=WHITE> 2795 <td bgcolor=WHITE align=center valign=top>06</td> 2796 <td align=left valign=top>RW</td> 2797 <td align=left valign=top>pll_lock_rstb_r</td> 2798 <td align=left> 2799 tbd<br> 2800 Reset value is 0x0.</td></tr> 2801 <tr bgcolor=WHITE> 2802 <td bgcolor=WHITE align=center valign=top>05</td> 2803 <td align=left valign=top>RW</td> 2804 <td align=left valign=top>lfck_bypass</td> 2805 <td align=left> 2806 tbd<br> 2807 Reset value is 0x1.</td></tr> 2808 <tr bgcolor=WHITE> 2809 <td bgcolor=WHITE align=center valign=top>04</td> 2810 <td align=left valign=top>RW</td> 2811 <td align=left valign=top>rx_snoop_en</td> 2812 <td align=left> 2813 tbd<br> 2814 Reset value is 0x0.</td></tr> 2815 <tr bgcolor=WHITE> 2816 <td bgcolor=WHITE align=center valign=top>03</td> 2817 <td align=left valign=top>RW</td> 2818 <td align=left valign=top>mdio_StandAloneMode</td> 2819 <td align=left> 2820 tbd<br> 2821 Reset value is 0x0.</td></tr> 2822 <tr bgcolor=WHITE> 2823 <td bgcolor=WHITE align=center valign=top>02</td> 2824 <td align=left valign=top>RW</td> 2825 <td align=left valign=top>mdio_PllTuningBypass</td> 2826 <td align=left> 2827 tbd<br> 2828 Reset value is 0x0.</td></tr> 2829 <tr bgcolor=WHITE> 2830 <td bgcolor=WHITE align=center valign=top>01</td> 2831 <td align=left valign=top>RW</td> 2832 <td align=left valign=top>mdio_lfck_rx_sel_cnt0</td> 2833 <td align=left> 2834 tbd<br> 2835 Reset value is 0x0.</td></tr> 2836 <tr bgcolor=WHITE> 2837 <td bgcolor=WHITE align=center valign=top>00</td> 2838 <td align=left valign=top>RW</td> 2839 <td align=left valign=top>mdio_lfck_rx_sel_refclk</td> 2840 <td align=left> 2841 tbd<br> 2842 Reset value is 0x0.</td></tr> 2843 </table><p> 2844 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2845 <hr> 2846 <b><a NAME="PCIE_BLK5_EXT_LANETEST1">PCIE_BLK5_EXT_LANETEST1 - Register</a></b><br> 2847 Address Offset = 32'h0000_1507<br> 2848 Physical Address = 32'h0000_1507<br> 2849 Reset Value = 16'h0000<br> 2850 Access = RW (16-bit only)<br> 2851 <table border=1 align=center width=100% cellpadding=0> 2852 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2853 <tr bgcolor=WHITE> 2854 <td bgcolor=WHITE align=center valign=top>15</td> 2855 <td align=left valign=top>RW</td> 2856 <td align=left valign=top>comp_start</td> 2857 <td align=left> 2858 tbd<br> 2859 Reset value is 0x0.</td></tr> 2860 <tr bgcolor=WHITE> 2861 <td bgcolor=WHITE align=center valign=top>14:06</td> 2862 <td align=left valign=top>RSVD</td> 2863 <td align=left valign=top>Reserved</td> 2864 <td align=left> 2865 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 2866 <tr bgcolor=WHITE> 2867 <td bgcolor=WHITE align=center valign=top>05:00</td> 2868 <td align=left valign=top>RW</td> 2869 <td align=left valign=top>tmux_sel</td> 2870 <td align=left> 2871 tbd<br> 2872 Reset value is 0x0.</td></tr> 2873 </table><p> 2874 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2875 <hr> 2876 <b><a NAME="PCIE_BLK5_EXT_COMP_DELAY0">PCIE_BLK5_EXT_COMP_DELAY0 - Register</a></b><br> 2877 Address Offset = 32'h0000_1508<br> 2878 Physical Address = 32'h0000_1508<br> 2879 Reset Value = 16'h3210<br> 2880 Access = RW (16-bit only)<br> 2881 <table border=1 align=center width=100% cellpadding=0> 2882 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2883 <tr bgcolor=WHITE> 2884 <td bgcolor=WHITE align=center valign=top>15:12</td> 2885 <td align=left valign=top>RW</td> 2886 <td align=left valign=top>comp_delay3_11</td> 2887 <td align=left> 2888 tbd<br> 2889 Reset value is 0x3.</td></tr> 2890 <tr bgcolor=WHITE> 2891 <td bgcolor=WHITE align=center valign=top>11:08</td> 2892 <td align=left valign=top>RW</td> 2893 <td align=left valign=top>comp_delay2_10</td> 2894 <td align=left> 2895 tbd<br> 2896 Reset value is 0x2.</td></tr> 2897 <tr bgcolor=WHITE> 2898 <td bgcolor=WHITE align=center valign=top>07:04</td> 2899 <td align=left valign=top>RW</td> 2900 <td align=left valign=top>comp_delay1_9</td> 2901 <td align=left> 2902 tbd<br> 2903 Reset value is 0x1.</td></tr> 2904 <tr bgcolor=WHITE> 2905 <td bgcolor=WHITE align=center valign=top>03:00</td> 2906 <td align=left valign=top>RW</td> 2907 <td align=left valign=top>comp_delay0_8</td> 2908 <td align=left> 2909 tbd<br> 2910 Reset value is 0x0.</td></tr> 2911 </table><p> 2912 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2913 <hr> 2914 <b><a NAME="PCIE_BLK5_EXT_COMP_DELAY1">PCIE_BLK5_EXT_COMP_DELAY1 - Register</a></b><br> 2915 Address Offset = 32'h0000_1509<br> 2916 Physical Address = 32'h0000_1509<br> 2917 Reset Value = 16'h7654<br> 2918 Access = RW (16-bit only)<br> 2919 <table border=1 align=center width=100% cellpadding=0> 2920 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2921 <tr bgcolor=WHITE> 2922 <td bgcolor=WHITE align=center valign=top>15:12</td> 2923 <td align=left valign=top>RW</td> 2924 <td align=left valign=top>comp_delay7_15</td> 2925 <td align=left> 2926 tbd<br> 2927 Reset value is 0x7.</td></tr> 2928 <tr bgcolor=WHITE> 2929 <td bgcolor=WHITE align=center valign=top>11:08</td> 2930 <td align=left valign=top>RW</td> 2931 <td align=left valign=top>comp_delay6_14</td> 2932 <td align=left> 2933 tbd<br> 2934 Reset value is 0x6.</td></tr> 2935 <tr bgcolor=WHITE> 2936 <td bgcolor=WHITE align=center valign=top>07:04</td> 2937 <td align=left valign=top>RW</td> 2938 <td align=left valign=top>comp_delay5_13</td> 2939 <td align=left> 2940 tbd<br> 2941 Reset value is 0x5.</td></tr> 2942 <tr bgcolor=WHITE> 2943 <td bgcolor=WHITE align=center valign=top>03:00</td> 2944 <td align=left valign=top>RW</td> 2945 <td align=left valign=top>comp_delay4_12</td> 2946 <td align=left> 2947 tbd<br> 2948 Reset value is 0x4.</td></tr> 2949 </table><p> 2950 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2951 <hr> 2952 <b><a NAME="PCIE_BLK5_EXT_COMP_TYPE">PCIE_BLK5_EXT_COMP_TYPE - Register</a></b><br> 2953 Address Offset = 32'h0000_150a<br> 2954 Physical Address = 32'h0000_150a<br> 2955 Reset Value = 16'h0000<br> 2956 Access = RW (16-bit only)<br> 2957 <table border=1 align=center width=100% cellpadding=0> 2958 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2959 <tr bgcolor=WHITE> 2960 <td bgcolor=WHITE align=center valign=top>15:00</td> 2961 <td align=left valign=top>RW</td> 2962 <td align=left valign=top>comp_type</td> 2963 <td align=left> 2964 tbd<br> 2965 Reset value is 0x0.</td></tr> 2966 </table><p> 2967 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2968 <hr> 2969 <b><a NAME="PCIE_BLK5_EXT_COMP_ENABLE">PCIE_BLK5_EXT_COMP_ENABLE - Register</a></b><br> 2970 Address Offset = 32'h0000_150b<br> 2971 Physical Address = 32'h0000_150b<br> 2972 Reset Value = 16'h0000<br> 2973 Access = RW (16-bit only)<br> 2974 <table border=1 align=center width=100% cellpadding=0> 2975 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2976 <tr bgcolor=WHITE> 2977 <td bgcolor=WHITE align=center valign=top>15:00</td> 2978 <td align=left valign=top>RW</td> 2979 <td align=left valign=top>comp_enable</td> 2980 <td align=left> 2981 tbd<br> 2982 Reset value is 0x0.</td></tr> 2983 </table><p> 2984 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 2985 <hr> 2986 <b><a NAME="PCIE_BLK5_EXT_XGXS_FE_TMUX">PCIE_BLK5_EXT_XGXS_FE_TMUX - Register</a></b><br> 2987 Address Offset = 32'h0000_150e<br> 2988 Physical Address = 32'h0000_150e<br> 2989 Reset Value = 16'h0000<br> 2990 Access = RO (16-bit only)<br> 2991 <table border=1 align=center width=100% cellpadding=0> 2992 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 2993 <tr bgcolor=WHITE> 2994 <td bgcolor=WHITE align=center valign=top>15:00</td> 2995 <td align=left valign=top>RO</td> 2996 <td align=left valign=top>XGXS_fe_tmux</td> 2997 <td align=left> 2998 tbd<br> 2999 Reset value is 0x0.</td></tr> 3000 </table><p> 3001 <A HREF="#PCIE_BLK5_EXT Registers">Return to PCIE_BLK5_EXT Table</A><p> 3002 <hr> 3003 <H1><a NAME="PCIE_BLK6_EXT Registers">PCIE_BLK6_EXT Registers</a></H1> 3004 <table border=1 align=center width=100% cellpadding=0> 3005 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 3006 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 3007 <tr> 3008 <td align=center>0x1600</td><td><A HREF="#PCIE_BLK6_EXT_PMD_CTRL0">PCIE_BLK6_EXT_PMD_CTRL0</A><br>PMD Control 0 Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_rx_dme_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_rx_mode</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">pmd_tx_mode</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pmd_osr_mode_gen3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pmd_osr_mode_gen2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pmd_osr_mode_gen1</div> </td> <td align=center>16'h0014</td></tr> 3009 <tr> 3010 <td align=center>0x1601</td><td><A HREF="#PCIE_BLK6_EXT_PMD_CTRL1">PCIE_BLK6_EXT_PMD_CTRL1</A><br>PMD Control 1 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">pcie_pmd_lane_mode</div> </td> <td align=center>16'h0000</td></tr> 3011 <tr> 3012 <td align=center>0x1602</td><td><A HREF="#PCIE_BLK6_EXT_PMD_CTRL2">PCIE_BLK6_EXT_PMD_CTRL2</A><br>PMD Control 2 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">pcie_pmd_core_mode</div> </td> <td align=center>16'h0000</td></tr> 3013 <tr> 3014 <td align=center>0x1603</td><td><A HREF="#PCIE_BLK6_EXT_ANA_CTRL">PCIE_BLK6_EXT_ANA_CTRL</A><br>Analog Control Register</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_pll_lock_dly</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">core_config_frc</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">core_config_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tca_use_ext_pd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ref_cmos_clk_HZ</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">refsel_frc</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">refsel_frc_val</div> </td> <td align=center>16'h0000</td></tr> 3015 </table><p> 3016 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 3017 <hr> 3018 <b><a NAME="PCIE_BLK6_EXT_PMD_CTRL0">PCIE_BLK6_EXT_PMD_CTRL0 - PMD Control 0 Register</a></b><br> 3019 Address Offset = 32'h0000_1600<br> 3020 Physical Address = 32'h0000_1600<br> 3021 Reset Value = 16'h0014<br> 3022 Access = RW (16-bit only)<br> 3023 <table border=1 align=center width=100% cellpadding=0> 3024 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3025 <tr bgcolor=WHITE> 3026 <td bgcolor=WHITE align=center valign=top>15</td> 3027 <td align=left valign=top>RW</td> 3028 <td align=left valign=top>pmd_rx_dme_en</td> 3029 <td align=left> 3030 tbd<br> 3031 Reset value is 0x0.</td></tr> 3032 <tr bgcolor=WHITE> 3033 <td bgcolor=WHITE align=center valign=top>14</td> 3034 <td align=left valign=top>RW</td> 3035 <td align=left valign=top>pmd_rx_mode</td> 3036 <td align=left> 3037 tbd<br> 3038 Reset value is 0x0.</td></tr> 3039 <tr bgcolor=WHITE> 3040 <td bgcolor=WHITE align=center valign=top>13:12</td> 3041 <td align=left valign=top>RW</td> 3042 <td align=left valign=top>pmd_tx_mode</td> 3043 <td align=left> 3044 tbd<br> 3045 Reset value is 0x0.</td></tr> 3046 <tr bgcolor=WHITE> 3047 <td bgcolor=WHITE align=center valign=top>11:08</td> 3048 <td align=left valign=top>RW</td> 3049 <td align=left valign=top>pmd_osr_mode_gen3</td> 3050 <td align=left> 3051 tbd<br> 3052 Reset value is 0x0.</td></tr> 3053 <tr bgcolor=WHITE> 3054 <td bgcolor=WHITE align=center valign=top>07:04</td> 3055 <td align=left valign=top>RW</td> 3056 <td align=left valign=top>pmd_osr_mode_gen2</td> 3057 <td align=left> 3058 tbd<br> 3059 Reset value is 0x1.</td></tr> 3060 <tr bgcolor=WHITE> 3061 <td bgcolor=WHITE align=center valign=top>03:00</td> 3062 <td align=left valign=top>RW</td> 3063 <td align=left valign=top>pmd_osr_mode_gen1</td> 3064 <td align=left> 3065 tbd<br> 3066 Reset value is 0x4.</td></tr> 3067 </table><p> 3068 <A HREF="#PCIE_BLK6_EXT Registers">Return to PCIE_BLK6_EXT Table</A><p> 3069 <hr> 3070 <b><a NAME="PCIE_BLK6_EXT_PMD_CTRL1">PCIE_BLK6_EXT_PMD_CTRL1 - PMD Control 1 Register</a></b><br> 3071 Address Offset = 32'h0000_1601<br> 3072 Physical Address = 32'h0000_1601<br> 3073 Reset Value = 16'h0000<br> 3074 Access = RW (16-bit only)<br> 3075 <table border=1 align=center width=100% cellpadding=0> 3076 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3077 <tr bgcolor=WHITE> 3078 <td bgcolor=WHITE align=center valign=top>15:00</td> 3079 <td align=left valign=top>RW</td> 3080 <td align=left valign=top>pcie_pmd_lane_mode</td> 3081 <td align=left> 3082 tbd<br> 3083 Reset value is 0x0.</td></tr> 3084 </table><p> 3085 <A HREF="#PCIE_BLK6_EXT Registers">Return to PCIE_BLK6_EXT Table</A><p> 3086 <hr> 3087 <b><a NAME="PCIE_BLK6_EXT_PMD_CTRL2">PCIE_BLK6_EXT_PMD_CTRL2 - PMD Control 2 Register</a></b><br> 3088 Address Offset = 32'h0000_1602<br> 3089 Physical Address = 32'h0000_1602<br> 3090 Reset Value = 16'h0000<br> 3091 Access = RW (16-bit only)<br> 3092 <table border=1 align=center width=100% cellpadding=0> 3093 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3094 <tr bgcolor=WHITE> 3095 <td bgcolor=WHITE align=center valign=top>15:00</td> 3096 <td align=left valign=top>RW</td> 3097 <td align=left valign=top>pcie_pmd_core_mode</td> 3098 <td align=left> 3099 tbd<br> 3100 Reset value is 0x0.</td></tr> 3101 </table><p> 3102 <A HREF="#PCIE_BLK6_EXT Registers">Return to PCIE_BLK6_EXT Table</A><p> 3103 <hr> 3104 <b><a NAME="PCIE_BLK6_EXT_ANA_CTRL">PCIE_BLK6_EXT_ANA_CTRL - Analog Control Register</a></b><br> 3105 Address Offset = 32'h0000_1603<br> 3106 Physical Address = 32'h0000_1603<br> 3107 Reset Value = 16'h0000<br> 3108 Access = RW (16-bit only)<br> 3109 <table border=1 align=center width=100% cellpadding=0> 3110 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3111 <tr bgcolor=WHITE> 3112 <td bgcolor=WHITE align=center valign=top>15:12</td> 3113 <td align=left valign=top>RSVD</td> 3114 <td align=left valign=top>Reserved</td> 3115 <td align=left> 3116 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 3117 <tr bgcolor=WHITE> 3118 <td bgcolor=WHITE align=center valign=top>11</td> 3119 <td align=left valign=top>RW</td> 3120 <td align=left valign=top>mdio_pll_lock_dly</td> 3121 <td align=left> 3122 Extend pll lock time<br> 3123 Reset value is 0x0.</td></tr> 3124 <tr bgcolor=WHITE> 3125 <td bgcolor=WHITE align=center valign=top>10</td> 3126 <td align=left valign=top>RW</td> 3127 <td align=left valign=top>core_config_frc</td> 3128 <td align=left> 3129 Override pcie_chp_phy_core_config <br> 3130 Reset value is 0x0.</td></tr> 3131 <tr bgcolor=WHITE> 3132 <td bgcolor=WHITE align=center valign=top>09:06</td> 3133 <td align=left valign=top>RW</td> 3134 <td align=left valign=top>core_config_frc_val</td> 3135 <td align=left> 3136 Override pcie_chp_phy_core_config value <br> 3137 Reset value is 0x0.</td></tr> 3138 <tr bgcolor=WHITE> 3139 <td bgcolor=WHITE align=center valign=top>05</td> 3140 <td align=left valign=top>RW</td> 3141 <td align=left valign=top>tca_use_ext_pd</td> 3142 <td align=left> 3143 Aligned tx lane clocks with lane0 tx clock<br> 3144 Reset value is 0x0.</td></tr> 3145 <tr bgcolor=WHITE> 3146 <td bgcolor=WHITE align=center valign=top>04</td> 3147 <td align=left valign=top>RW</td> 3148 <td align=left valign=top>ref_cmos_clk_HZ</td> 3149 <td align=left> 3150 0: Drive the CMOS Clock Channel.  1: CMOS clock channel is off. <br> 3151 Reset value is 0x0.</td></tr> 3152 <tr bgcolor=WHITE> 3153 <td bgcolor=WHITE align=center valign=top>03</td> 3154 <td align=left valign=top>RW</td> 3155 <td align=left valign=top>refsel_frc</td> 3156 <td align=left> 3157 Override i_refsel <br> 3158 Reset value is 0x0.</td></tr> 3159 <tr bgcolor=WHITE> 3160 <td bgcolor=WHITE align=center valign=top>02:00</td> 3161 <td align=left valign=top>RW</td> 3162 <td align=left valign=top>refsel_frc_val</td> 3163 <td align=left> 3164 Override i_refsel value<br> 3165 Reset value is 0x0.</td></tr> 3166 </table><p> 3167 <A HREF="#PCIE_BLK6_EXT Registers">Return to PCIE_BLK6_EXT Table</A><p> 3168 <hr> 3169 <H1><a NAME="PCIE_BLK7_EXT Registers">PCIE_BLK7_EXT Registers</a></H1> 3170 <table border=1 align=center width=100% cellpadding=0> 3171 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 3172 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 3173 <tr> 3174 <td align=center>0x1700</td><td><A HREF="#PCIE_BLK7_EXT_TX_COEFF_LO">PCIE_BLK7_EXT_TX_COEFF_LO</A><br>tx_coeff_lo Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">tx_coeff_lo</div> </td> <td align=center>16'hca80</td></tr> 3175 <tr> 3176 <td align=center>0x1701</td><td><A HREF="#PCIE_BLK7_EXT_TX_COEFF_HI">PCIE_BLK7_EXT_TX_COEFF_HI</A><br>tx_coeff_hi Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_coeff_ovrd_ena</div> </td> <td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tx_coeff_hi</div> </td> <td align=center>16'h0001</td></tr> 3177 <tr> 3178 <td align=center>0x1702</td><td><A HREF="#PCIE_BLK7_EXT_RX_CLK_REPEATER_0">PCIE_BLK7_EXT_RX_CLK_REPEATER_0</A><br>rx_clk_repeater_0 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_clk_repeater_0</div> </td> <td align=center>16'h0000</td></tr> 3179 <tr> 3180 <td align=center>0x1703</td><td><A HREF="#PCIE_BLK7_EXT_RX_CLK_REPEATER_1">PCIE_BLK7_EXT_RX_CLK_REPEATER_1</A><br>rx_clk_repeater_1 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_clk_repeater_1</div> </td> <td align=center>16'h7a00</td></tr> 3181 <tr> 3182 <td align=center>0x1704</td><td><A HREF="#PCIE_BLK7_EXT_RX_CLK_REPEATER_2">PCIE_BLK7_EXT_RX_CLK_REPEATER_2</A><br>rx_clk_repeater_2 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_clk_repeater_2</div> </td> <td align=center>16'h1df7</td></tr> 3183 <tr> 3184 <td align=center>0x1705</td><td><A HREF="#PCIE_BLK7_EXT_RX_CLK_REPEATER_3">PCIE_BLK7_EXT_RX_CLK_REPEATER_3</A><br>rx_clk_repeater_3 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_clk_repeater_3</div> </td> <td align=center>16'h7000</td></tr> 3185 <tr> 3186 <td align=center>0x1706</td><td><A HREF="#PCIE_BLK7_EXT_RX_CLK_REPEATER_BW">PCIE_BLK7_EXT_RX_CLK_REPEATER_BW</A><br>PCIE7 rx_clk_repeater_BW Register</td><td bgcolor=#FFFFFF align=center colspan="12"><div class="HT">spare_bits</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_clk_repeater_BW_gen3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_clk_repeater_BW_gen12</div> </td> <td align=center>16'h0003</td></tr> 3187 <tr> 3188 <td align=center>0x1707</td><td><A HREF="#PCIE_BLK7_EXT_SPARE_CTRL0">PCIE_BLK7_EXT_SPARE_CTRL0</A><br>PCIE7 spare_ctrl0 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">spare_ctrl0</div> </td> <td align=center>16'h0000</td></tr> 3189 <tr> 3190 <td align=center>0x1708</td><td><A HREF="#PCIE_BLK7_EXT_SPARE_CTRL1">PCIE_BLK7_EXT_SPARE_CTRL1</A><br>PCIE7 spare_ctrl1 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">spare_ctrl1</div> </td> <td align=center>16'h0000</td></tr> 3191 <tr> 3192 <td align=center>0x1709</td><td><A HREF="#PCIE_BLK7_EXT_SPARE_CTRL2">PCIE_BLK7_EXT_SPARE_CTRL2</A><br>PCIE7 spare_ctrl2 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">spare_ctrl2</div> </td> <td align=center>16'h0000</td></tr> 3193 <tr> 3194 <td align=center>0x170A</td><td><A HREF="#PCIE_BLK7_EXT_SPARE_CTRL3">PCIE_BLK7_EXT_SPARE_CTRL3</A><br>PCIE7 spare_ctrl3 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">spare_ctrl3</div> </td> <td align=center>16'h0000</td></tr> 3195 </table><p> 3196 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 3197 <hr> 3198 <b><a NAME="PCIE_BLK7_EXT_TX_COEFF_LO">PCIE_BLK7_EXT_TX_COEFF_LO - tx_coeff_lo Register</a></b><br> 3199 Address Offset = 32'h0000_1700<br> 3200 Physical Address = 32'h0000_1700<br> 3201 Reset Value = 16'hca80<br> 3202 Access = RW (16-bit only)<br> 3203 <table border=1 align=center width=100% cellpadding=0> 3204 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3205 <tr bgcolor=WHITE> 3206 <td bgcolor=WHITE align=center valign=top>15:00</td> 3207 <td align=left valign=top>RW</td> 3208 <td align=left valign=top>tx_coeff_lo</td> 3209 <td align=left> 3210 tx coeff[15:0]<br> 3211 Reset value is 0xca80.</td></tr> 3212 </table><p> 3213 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3214 <hr> 3215 <b><a NAME="PCIE_BLK7_EXT_TX_COEFF_HI">PCIE_BLK7_EXT_TX_COEFF_HI - tx_coeff_hi Register</a></b><br> 3216 Address Offset = 32'h0000_1701<br> 3217 Physical Address = 32'h0000_1701<br> 3218 Reset Value = 16'h0001<br> 3219 Access = RW (16-bit only)<br> 3220 <table border=1 align=center width=100% cellpadding=0> 3221 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3222 <tr bgcolor=WHITE> 3223 <td bgcolor=WHITE align=center valign=top>15</td> 3224 <td align=left valign=top>RW</td> 3225 <td align=left valign=top>tx_coeff_ovrd_ena</td> 3226 <td align=left> 3227 When asserted will override TxDeemph with values<br> 3228 in tx_coeff[21:0]<br> 3229 Reset value is 0x0.</td></tr> 3230 <tr bgcolor=WHITE> 3231 <td bgcolor=WHITE align=center valign=top>14:06</td> 3232 <td align=left valign=top>RSVD</td> 3233 <td align=left valign=top>Reserved</td> 3234 <td align=left> 3235 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 3236 <tr bgcolor=WHITE> 3237 <td bgcolor=WHITE align=center valign=top>05:00</td> 3238 <td align=left valign=top>RW</td> 3239 <td align=left valign=top>tx_coeff_hi</td> 3240 <td align=left> 3241 tx coeff[21:16]<br> 3242 Reset value is 0x1.</td></tr> 3243 </table><p> 3244 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3245 <hr> 3246 <b><a NAME="PCIE_BLK7_EXT_RX_CLK_REPEATER_0">PCIE_BLK7_EXT_RX_CLK_REPEATER_0 - rx_clk_repeater_0 Register</a></b><br> 3247 Address Offset = 32'h0000_1702<br> 3248 Physical Address = 32'h0000_1702<br> 3249 Reset Value = 16'h0000<br> 3250 Access = RW (16-bit only)<br> 3251 <table border=1 align=center width=100% cellpadding=0> 3252 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3253 <tr bgcolor=WHITE> 3254 <td bgcolor=WHITE align=center valign=top>15:00</td> 3255 <td align=left valign=top>RW</td> 3256 <td align=left valign=top>rx_clk_repeater_0</td> 3257 <td align=left> 3258 Rx clk repeater ctrl type_0 at rx_ctrl[95:80]<br> 3259 Reset value is 0x0.</td></tr> 3260 </table><p> 3261 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3262 <hr> 3263 <b><a NAME="PCIE_BLK7_EXT_RX_CLK_REPEATER_1">PCIE_BLK7_EXT_RX_CLK_REPEATER_1 - rx_clk_repeater_1 Register</a></b><br> 3264 Address Offset = 32'h0000_1703<br> 3265 Physical Address = 32'h0000_1703<br> 3266 Reset Value = 16'h7a00<br> 3267 Access = RW (16-bit only)<br> 3268 <table border=1 align=center width=100% cellpadding=0> 3269 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3270 <tr bgcolor=WHITE> 3271 <td bgcolor=WHITE align=center valign=top>15:00</td> 3272 <td align=left valign=top>RW</td> 3273 <td align=left valign=top>rx_clk_repeater_1</td> 3274 <td align=left> 3275 Rx clk repeater ctrl type_1 at rx_ctrl[95:80]<br> 3276 Reset value is 0x7a00.</td></tr> 3277 </table><p> 3278 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3279 <hr> 3280 <b><a NAME="PCIE_BLK7_EXT_RX_CLK_REPEATER_2">PCIE_BLK7_EXT_RX_CLK_REPEATER_2 - rx_clk_repeater_2 Register</a></b><br> 3281 Address Offset = 32'h0000_1704<br> 3282 Physical Address = 32'h0000_1704<br> 3283 Reset Value = 16'h1df7<br> 3284 Access = RW (16-bit only)<br> 3285 <table border=1 align=center width=100% cellpadding=0> 3286 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3287 <tr bgcolor=WHITE> 3288 <td bgcolor=WHITE align=center valign=top>15:00</td> 3289 <td align=left valign=top>RW</td> 3290 <td align=left valign=top>rx_clk_repeater_2</td> 3291 <td align=left> 3292 Rx clk repeater ctrl type_2 at rx_ctrl[95:80]<br> 3293 Reset value is 0x1df7.</td></tr> 3294 </table><p> 3295 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3296 <hr> 3297 <b><a NAME="PCIE_BLK7_EXT_RX_CLK_REPEATER_3">PCIE_BLK7_EXT_RX_CLK_REPEATER_3 - rx_clk_repeater_3 Register</a></b><br> 3298 Address Offset = 32'h0000_1705<br> 3299 Physical Address = 32'h0000_1705<br> 3300 Reset Value = 16'h7000<br> 3301 Access = RW (16-bit only)<br> 3302 <table border=1 align=center width=100% cellpadding=0> 3303 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3304 <tr bgcolor=WHITE> 3305 <td bgcolor=WHITE align=center valign=top>15:00</td> 3306 <td align=left valign=top>RW</td> 3307 <td align=left valign=top>rx_clk_repeater_3</td> 3308 <td align=left> 3309 Rx clk repeater ctrl type_3 at rx_ctrl[95:80]<br> 3310 Reset value is 0x7000.</td></tr> 3311 </table><p> 3312 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3313 <hr> 3314 <b><a NAME="PCIE_BLK7_EXT_RX_CLK_REPEATER_BW">PCIE_BLK7_EXT_RX_CLK_REPEATER_BW - PCIE7 rx_clk_repeater_BW Register</a></b><br> 3315 Address Offset = 32'h0000_1706<br> 3316 Physical Address = 32'h0000_1706<br> 3317 Reset Value = 16'h0003<br> 3318 Access = RW (16-bit only)<br> 3319 <table border=1 align=center width=100% cellpadding=0> 3320 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3321 <tr bgcolor=WHITE> 3322 <td bgcolor=WHITE align=center valign=top>15:04</td> 3323 <td align=left valign=top>RW</td> 3324 <td align=left valign=top>spare_bits</td> 3325 <td align=left> 3326 spares<br> 3327 Reset value is 0x0.</td></tr> 3328 <tr bgcolor=WHITE> 3329 <td bgcolor=WHITE align=center valign=top>03:02</td> 3330 <td align=left valign=top>RW</td> 3331 <td align=left valign=top>rx_clk_repeater_BW_gen3</td> 3332 <td align=left> 3333 Rx clk repeater BW(gen3 at rx5/9/13_ctrl[95:94]<br> 3334 Reset value is 0x0.</td></tr> 3335 <tr bgcolor=WHITE> 3336 <td bgcolor=WHITE align=center valign=top>01:00</td> 3337 <td align=left valign=top>RW</td> 3338 <td align=left valign=top>rx_clk_repeater_BW_gen12</td> 3339 <td align=left> 3340 Rx clk repeater BW(gen1/gen2 at rx5/9/13_ctrl[95:94]<br> 3341 Reset value is 0x3.</td></tr> 3342 </table><p> 3343 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3344 <hr> 3345 <b><a NAME="PCIE_BLK7_EXT_SPARE_CTRL0">PCIE_BLK7_EXT_SPARE_CTRL0 - PCIE7 spare_ctrl0 Register</a></b><br> 3346 Address Offset = 32'h0000_1707<br> 3347 Physical Address = 32'h0000_1707<br> 3348 Reset Value = 16'h0000<br> 3349 Access = RW (16-bit only)<br> 3350 <table border=1 align=center width=100% cellpadding=0> 3351 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3352 <tr bgcolor=WHITE> 3353 <td bgcolor=WHITE align=center valign=top>15:00</td> 3354 <td align=left valign=top>RW</td> 3355 <td align=left valign=top>spare_ctrl0</td> 3356 <td align=left> 3357 spare_ctrl0<br> 3358 Reset value is 0x0.</td></tr> 3359 </table><p> 3360 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3361 <hr> 3362 <b><a NAME="PCIE_BLK7_EXT_SPARE_CTRL1">PCIE_BLK7_EXT_SPARE_CTRL1 - PCIE7 spare_ctrl1 Register</a></b><br> 3363 Address Offset = 32'h0000_1708<br> 3364 Physical Address = 32'h0000_1708<br> 3365 Reset Value = 16'h0000<br> 3366 Access = RW (16-bit only)<br> 3367 <table border=1 align=center width=100% cellpadding=0> 3368 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3369 <tr bgcolor=WHITE> 3370 <td bgcolor=WHITE align=center valign=top>15:00</td> 3371 <td align=left valign=top>RW</td> 3372 <td align=left valign=top>spare_ctrl1</td> 3373 <td align=left> 3374 spare_ctrl1<br> 3375 Reset value is 0x0.</td></tr> 3376 </table><p> 3377 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3378 <hr> 3379 <b><a NAME="PCIE_BLK7_EXT_SPARE_CTRL2">PCIE_BLK7_EXT_SPARE_CTRL2 - PCIE7 spare_ctrl2 Register</a></b><br> 3380 Address Offset = 32'h0000_1709<br> 3381 Physical Address = 32'h0000_1709<br> 3382 Reset Value = 16'h0000<br> 3383 Access = RW (16-bit only)<br> 3384 <table border=1 align=center width=100% cellpadding=0> 3385 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3386 <tr bgcolor=WHITE> 3387 <td bgcolor=WHITE align=center valign=top>15:00</td> 3388 <td align=left valign=top>RW</td> 3389 <td align=left valign=top>spare_ctrl2</td> 3390 <td align=left> 3391 spare_ctrl2<br> 3392 Reset value is 0x0.</td></tr> 3393 </table><p> 3394 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3395 <hr> 3396 <b><a NAME="PCIE_BLK7_EXT_SPARE_CTRL3">PCIE_BLK7_EXT_SPARE_CTRL3 - PCIE7 spare_ctrl3 Register</a></b><br> 3397 Address Offset = 32'h0000_170a<br> 3398 Physical Address = 32'h0000_170a<br> 3399 Reset Value = 16'h0000<br> 3400 Access = RW (16-bit only)<br> 3401 <table border=1 align=center width=100% cellpadding=0> 3402 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3403 <tr bgcolor=WHITE> 3404 <td bgcolor=WHITE align=center valign=top>15:00</td> 3405 <td align=left valign=top>RW</td> 3406 <td align=left valign=top>spare_ctrl3</td> 3407 <td align=left> 3408 spare_ctrl3<br> 3409 Reset value is 0x0.</td></tr> 3410 </table><p> 3411 <A HREF="#PCIE_BLK7_EXT Registers">Return to PCIE_BLK7_EXT Table</A><p> 3412 <hr> 3413 <H1><a NAME="TX_DFE0_EXT Registers">TX_DFE0_EXT Registers</a></H1> 3414 <table border=1 align=center width=100% cellpadding=0> 3415 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 3416 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 3417 <tr> 3418 <td align=center>0x5000</td><td><A HREF="#TX_DFE0_EXT_TXSTATUS0">TX_DFE0_EXT_TXSTATUS0</A><br>Status 0 Register</td><td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">gloopback</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig2ana_tx_ElecIdle</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">setTxCnxTest</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig2ana_tx_setTxCnxTest</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rxCnxDetect</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ana2dig_tx_rxCnxDetect</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rltxferr_stky</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txpll_lock</div> </td> <td align=center>16'h0000</td></tr> 3419 <tr> 3420 <td align=center>0x5001</td><td><A HREF="#TX_DFE0_EXT_TXCONTROL0">TX_DFE0_EXT_TXCONTROL0</A><br>Control 0 Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_force_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">L0s_test_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">setTxCnxTest_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_tx_ElecIdle</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">fts_en_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">gloopOutDis_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_enb_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pkt_en_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pkt_strt_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txpol_flip</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">force_disError_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eden_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eden_force_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txpat_seq_en_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_mdata_en_SM</div> </td> <td align=center>16'h0000</td></tr> 3421 <tr> 3422 <td align=center>0x5002</td><td><A HREF="#TX_DFE0_EXT_MDATA0">TX_DFE0_EXT_MDATA0</A><br>MData 0 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdata0</div> </td> <td align=center>16'h0005</td></tr> 3423 <tr> 3424 <td align=center>0x5003</td><td><A HREF="#TX_DFE0_EXT_MDATA1">TX_DFE0_EXT_MDATA1</A><br>MData 1 Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdata1</div> </td> <td align=center>16'h00ff</td></tr> 3425 <tr> 3426 <td align=center>0x5005</td><td><A HREF="#TX_DFE0_EXT_EQ_COEFFICIENT">TX_DFE0_EXT_EQ_COEFFICIENT</A><br>EQ Coefficient Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">eq_coeff</div> </td> <td align=center>16'h0000</td></tr> 3427 <tr> 3428 <td align=center>0x5006</td><td><A HREF="#TX_DFE0_EXT_TXCONTROL1">TX_DFE0_EXT_TXCONTROL1</A><br>Control 1 Register</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">txTestMuxSelect</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rlfifo_tstsel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_seed_ld</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">L0s_timer_ld</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pktBurst_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pktRndm_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ipgLngth</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rxCnxDetect_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rxCnxDetect_force_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pre_emph_stair_rev_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_txmargin_SM</div> </td> <td align=center>16'h0000</td></tr> 3429 <tr> 3430 <td align=center>0x5007</td><td><A HREF="#TX_DFE0_EXT_TXCTRL0">TX_DFE0_EXT_TXCTRL0</A><br>Gen 1 ElecIdle Control Register</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_delay_fall_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rloop_delay_fall_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_delay_rise_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rloop_delay_rise_G1</div> </td> <td align=center>16'h9090</td></tr> 3431 <tr> 3432 <td align=center>0x5008</td><td><A HREF="#TX_DFE0_EXT_TXCTRL1">TX_DFE0_EXT_TXCTRL1</A><br>Gen 2 ElecIdle Control Register</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_delay_fall_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rloop_delay_fall_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_delay_rise_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rloop_delay_rise_G2</div> </td> <td align=center>16'h3090</td></tr> 3433 <tr> 3434 <td align=center>0x5009</td><td><A HREF="#TX_DFE0_EXT_TXCTRL2">TX_DFE0_EXT_TXCTRL2</A><br>Gen 3 ElecIdle Control Register</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_delay_fall_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rloop_delay_fall_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_delay_rise_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rloop_delay_rise_G3</div> </td> <td align=center>16'h5090</td></tr> 3435 <tr> 3436 <td align=center>0x500A</td><td><A HREF="#TX_DFE0_EXT_TXCTRL3">TX_DFE0_EXT_TXCTRL3</A><br>Polarity Control Register</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rising_half_G3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">falling_half_G3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rising_half_G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">falling_half_G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rising_half_G1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">falling_half_G1</div> </td> <td align=center>16'h0000</td></tr> 3437 <tr> 3438 <td align=center>0x500B</td><td><A HREF="#TX_DFE0_EXT_TXCONTROL2">TX_DFE0_EXT_TXCONTROL2</A><br>G3 control 2 register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_g3_ei_fifo_rst_cya</div> </td> <td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_g3f_tm_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_g3f_sw_rst</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_g3f_afrst_en</div> </td> <td align=center>16'h0001</td></tr> 3439 <tr> 3440 <td align=center>0x500C</td><td><A HREF="#TX_DFE0_EXT_TXSTATUS2">TX_DFE0_EXT_TXSTATUS2</A><br>G3 status register</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_g3f_afrst</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_g3f_unflow</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_g3f_ovflow</div> </td> <td align=center>16'h0000</td></tr> 3441 </table><p> 3442 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 3443 <hr> 3444 <b><a NAME="TX_DFE0_EXT_TXSTATUS0">TX_DFE0_EXT_TXSTATUS0 - Status 0 Register</a></b><br> 3445 Address Offset = 32'h0000_5000<br> 3446 Physical Address = 32'h0000_5000<br> 3447 Reset Value = 16'h0000<br> 3448 Access = RO (16-bit only)<br> 3449 <table border=1 align=center width=100% cellpadding=0> 3450 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3451 <tr bgcolor=WHITE> 3452 <td bgcolor=WHITE align=center valign=top>15:09</td> 3453 <td align=left valign=top>RSVD</td> 3454 <td align=left valign=top>Reserved</td> 3455 <td align=left> 3456 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 3457 <tr bgcolor=WHITE> 3458 <td bgcolor=WHITE align=center valign=top>08</td> 3459 <td align=left valign=top>RO</td> 3460 <td align=left valign=top>gloopback</td> 3461 <td align=left> 3462 tbd<br> 3463 Reset value is 0x0.</td></tr> 3464 <tr bgcolor=WHITE> 3465 <td bgcolor=WHITE align=center valign=top>07</td> 3466 <td align=left valign=top>RSVD</td> 3467 <td align=left valign=top>Reserved</td> 3468 <td align=left> 3469 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 3470 <tr bgcolor=WHITE> 3471 <td bgcolor=WHITE align=center valign=top>06</td> 3472 <td align=left valign=top>RO</td> 3473 <td align=left valign=top>dig2ana_tx_ElecIdle</td> 3474 <td align=left> 3475 tbd<br> 3476 Reset value is 0x0.</td></tr> 3477 <tr bgcolor=WHITE> 3478 <td bgcolor=WHITE align=center valign=top>05</td> 3479 <td align=left valign=top>RO</td> 3480 <td align=left valign=top>setTxCnxTest</td> 3481 <td align=left> 3482 tbd<br> 3483 Reset value is 0x0.</td></tr> 3484 <tr bgcolor=WHITE> 3485 <td bgcolor=WHITE align=center valign=top>04</td> 3486 <td align=left valign=top>RO</td> 3487 <td align=left valign=top>dig2ana_tx_setTxCnxTest</td> 3488 <td align=left> 3489 tbd<br> 3490 Reset value is 0x0.</td></tr> 3491 <tr bgcolor=WHITE> 3492 <td bgcolor=WHITE align=center valign=top>03</td> 3493 <td align=left valign=top>RO</td> 3494 <td align=left valign=top>rxCnxDetect</td> 3495 <td align=left> 3496 tbd<br> 3497 Reset value is 0x0.</td></tr> 3498 <tr bgcolor=WHITE> 3499 <td bgcolor=WHITE align=center valign=top>02</td> 3500 <td align=left valign=top>RO</td> 3501 <td align=left valign=top>ana2dig_tx_rxCnxDetect</td> 3502 <td align=left> 3503 tbd<br> 3504 Reset value is 0x0.</td></tr> 3505 <tr bgcolor=WHITE> 3506 <td bgcolor=WHITE align=center valign=top>01</td> 3507 <td align=left valign=top>RO</td> 3508 <td align=left valign=top>rltxferr_stky</td> 3509 <td align=left> 3510 tbd<br> 3511 Reset value is 0x0.</td></tr> 3512 <tr bgcolor=WHITE> 3513 <td bgcolor=WHITE align=center valign=top>00</td> 3514 <td align=left valign=top>RO</td> 3515 <td align=left valign=top>txpll_lock</td> 3516 <td align=left> 3517 tbd<br> 3518 Reset value is 0x0.</td></tr> 3519 </table><p> 3520 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3521 <hr> 3522 <b><a NAME="TX_DFE0_EXT_TXCONTROL0">TX_DFE0_EXT_TXCONTROL0 - Control 0 Register</a></b><br> 3523 Address Offset = 32'h0000_5001<br> 3524 Physical Address = 32'h0000_5001<br> 3525 Reset Value = 16'h0000<br> 3526 Access = RW (16-bit only)<br> 3527 <table border=1 align=center width=100% cellpadding=0> 3528 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3529 <tr bgcolor=WHITE> 3530 <td bgcolor=WHITE align=center valign=top>15</td> 3531 <td align=left valign=top>RW</td> 3532 <td align=left valign=top>mdio_force_SM</td> 3533 <td align=left> 3534 tbd<br> 3535 Reset value is 0x0.</td></tr> 3536 <tr bgcolor=WHITE> 3537 <td bgcolor=WHITE align=center valign=top>14</td> 3538 <td align=left valign=top>RW</td> 3539 <td align=left valign=top>L0s_test_SM</td> 3540 <td align=left> 3541 tbd<br> 3542 Reset value is 0x0.</td></tr> 3543 <tr bgcolor=WHITE> 3544 <td bgcolor=WHITE align=center valign=top>13</td> 3545 <td align=left valign=top>RW</td> 3546 <td align=left valign=top>setTxCnxTest_SM</td> 3547 <td align=left> 3548 tbd<br> 3549 Reset value is 0x0.</td></tr> 3550 <tr bgcolor=WHITE> 3551 <td bgcolor=WHITE align=center valign=top>12</td> 3552 <td align=left valign=top>RW</td> 3553 <td align=left valign=top>mdio_tx_ElecIdle</td> 3554 <td align=left> 3555 tbd<br> 3556 Reset value is 0x0.</td></tr> 3557 <tr bgcolor=WHITE> 3558 <td bgcolor=WHITE align=center valign=top>11</td> 3559 <td align=left valign=top>RSVD</td> 3560 <td align=left valign=top>Reserved</td> 3561 <td align=left> 3562 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 3563 <tr bgcolor=WHITE> 3564 <td bgcolor=WHITE align=center valign=top>10</td> 3565 <td align=left valign=top>RW</td> 3566 <td align=left valign=top>fts_en_SM</td> 3567 <td align=left> 3568 tbd<br> 3569 Reset value is 0x0.</td></tr> 3570 <tr bgcolor=WHITE> 3571 <td bgcolor=WHITE align=center valign=top>09</td> 3572 <td align=left valign=top>RW</td> 3573 <td align=left valign=top>gloopOutDis_r</td> 3574 <td align=left> 3575 tbd<br> 3576 Reset value is 0x0.</td></tr> 3577 <tr bgcolor=WHITE> 3578 <td bgcolor=WHITE align=center valign=top>08</td> 3579 <td align=left valign=top>RW</td> 3580 <td align=left valign=top>prbs_enb_r</td> 3581 <td align=left> 3582 tbd<br> 3583 Reset value is 0x0.</td></tr> 3584 <tr bgcolor=WHITE> 3585 <td bgcolor=WHITE align=center valign=top>07</td> 3586 <td align=left valign=top>RW</td> 3587 <td align=left valign=top>pkt_en_r</td> 3588 <td align=left> 3589 tbd<br> 3590 Reset value is 0x0.</td></tr> 3591 <tr bgcolor=WHITE> 3592 <td bgcolor=WHITE align=center valign=top>06</td> 3593 <td align=left valign=top>RW</td> 3594 <td align=left valign=top>pkt_strt_r</td> 3595 <td align=left> 3596 tbd<br> 3597 Reset value is 0x0.</td></tr> 3598 <tr bgcolor=WHITE> 3599 <td bgcolor=WHITE align=center valign=top>05</td> 3600 <td align=left valign=top>RW</td> 3601 <td align=left valign=top>txpol_flip</td> 3602 <td align=left> 3603 tbd<br> 3604 Reset value is 0x0.</td></tr> 3605 <tr bgcolor=WHITE> 3606 <td bgcolor=WHITE align=center valign=top>04</td> 3607 <td align=left valign=top>RW</td> 3608 <td align=left valign=top>force_disError_SM</td> 3609 <td align=left> 3610 tbd<br> 3611 Reset value is 0x0.</td></tr> 3612 <tr bgcolor=WHITE> 3613 <td bgcolor=WHITE align=center valign=top>03</td> 3614 <td align=left valign=top>RW</td> 3615 <td align=left valign=top>eden_r</td> 3616 <td align=left> 3617 tbd<br> 3618 Reset value is 0x0.</td></tr> 3619 <tr bgcolor=WHITE> 3620 <td bgcolor=WHITE align=center valign=top>02</td> 3621 <td align=left valign=top>RW</td> 3622 <td align=left valign=top>eden_force_r</td> 3623 <td align=left> 3624 tbd<br> 3625 Reset value is 0x0.</td></tr> 3626 <tr bgcolor=WHITE> 3627 <td bgcolor=WHITE align=center valign=top>01</td> 3628 <td align=left valign=top>RW</td> 3629 <td align=left valign=top>txpat_seq_en_SM</td> 3630 <td align=left> 3631 tbd<br> 3632 Reset value is 0x0.</td></tr> 3633 <tr bgcolor=WHITE> 3634 <td bgcolor=WHITE align=center valign=top>00</td> 3635 <td align=left valign=top>RW</td> 3636 <td align=left valign=top>tx_mdata_en_SM</td> 3637 <td align=left> 3638 tbd<br> 3639 Reset value is 0x0.</td></tr> 3640 </table><p> 3641 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3642 <hr> 3643 <b><a NAME="TX_DFE0_EXT_MDATA0">TX_DFE0_EXT_MDATA0 - MData 0 Register</a></b><br> 3644 Address Offset = 32'h0000_5002<br> 3645 Physical Address = 32'h0000_5002<br> 3646 Reset Value = 16'h0005<br> 3647 Access = RW (16-bit only)<br> 3648 <table border=1 align=center width=100% cellpadding=0> 3649 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3650 <tr bgcolor=WHITE> 3651 <td bgcolor=WHITE align=center valign=top>15:00</td> 3652 <td align=left valign=top>RW</td> 3653 <td align=left valign=top>mdata0</td> 3654 <td align=left> 3655 tbd<br> 3656 Reset value is 0x5.</td></tr> 3657 </table><p> 3658 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3659 <hr> 3660 <b><a NAME="TX_DFE0_EXT_MDATA1">TX_DFE0_EXT_MDATA1 - MData 1 Register</a></b><br> 3661 Address Offset = 32'h0000_5003<br> 3662 Physical Address = 32'h0000_5003<br> 3663 Reset Value = 16'h00ff<br> 3664 Access = RW (16-bit only)<br> 3665 <table border=1 align=center width=100% cellpadding=0> 3666 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3667 <tr bgcolor=WHITE> 3668 <td bgcolor=WHITE align=center valign=top>15:00</td> 3669 <td align=left valign=top>RW</td> 3670 <td align=left valign=top>mdata1</td> 3671 <td align=left> 3672 tbd<br> 3673 Reset value is 0xff.</td></tr> 3674 </table><p> 3675 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3676 <hr> 3677 <b><a NAME="TX_DFE0_EXT_EQ_COEFFICIENT">TX_DFE0_EXT_EQ_COEFFICIENT - EQ Coefficient Register</a></b><br> 3678 Address Offset = 32'h0000_5005<br> 3679 Physical Address = 32'h0000_5005<br> 3680 Reset Value = 16'h0000<br> 3681 Access = RO (16-bit only)<br> 3682 <table border=1 align=center width=100% cellpadding=0> 3683 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3684 <tr bgcolor=WHITE> 3685 <td bgcolor=WHITE align=center valign=top>15:00</td> 3686 <td align=left valign=top>RO</td> 3687 <td align=left valign=top>eq_coeff</td> 3688 <td align=left> 3689 no default in ana_defines.inc<br> 3690 Reset value is 0x0.</td></tr> 3691 </table><p> 3692 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3693 <hr> 3694 <b><a NAME="TX_DFE0_EXT_TXCONTROL1">TX_DFE0_EXT_TXCONTROL1 - Control 1 Register</a></b><br> 3695 Address Offset = 32'h0000_5006<br> 3696 Physical Address = 32'h0000_5006<br> 3697 Reset Value = 16'h0000<br> 3698 Access = RW (16-bit only)<br> 3699 <table border=1 align=center width=100% cellpadding=0> 3700 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3701 <tr bgcolor=WHITE> 3702 <td bgcolor=WHITE align=center valign=top>15:13</td> 3703 <td align=left valign=top>RW</td> 3704 <td align=left valign=top>txTestMuxSelect</td> 3705 <td align=left> 3706 tbd<br> 3707 Reset value is 0x0.</td></tr> 3708 <tr bgcolor=WHITE> 3709 <td bgcolor=WHITE align=center valign=top>12:10</td> 3710 <td align=left valign=top>RW</td> 3711 <td align=left valign=top>rlfifo_tstsel</td> 3712 <td align=left> 3713 tbd<br> 3714 Reset value is 0x0.</td></tr> 3715 <tr bgcolor=WHITE> 3716 <td bgcolor=WHITE align=center valign=top>09</td> 3717 <td align=left valign=top>RW</td> 3718 <td align=left valign=top>prbs_seed_ld</td> 3719 <td align=left> 3720 tbd<br> 3721 Reset value is 0x0.</td></tr> 3722 <tr bgcolor=WHITE> 3723 <td bgcolor=WHITE align=center valign=top>08</td> 3724 <td align=left valign=top>RW</td> 3725 <td align=left valign=top>L0s_timer_ld</td> 3726 <td align=left> 3727 tbd<br> 3728 Reset value is 0x0.</td></tr> 3729 <tr bgcolor=WHITE> 3730 <td bgcolor=WHITE align=center valign=top>07</td> 3731 <td align=left valign=top>RW</td> 3732 <td align=left valign=top>pktBurst_en</td> 3733 <td align=left> 3734 tbd<br> 3735 Reset value is 0x0.</td></tr> 3736 <tr bgcolor=WHITE> 3737 <td bgcolor=WHITE align=center valign=top>06</td> 3738 <td align=left valign=top>RW</td> 3739 <td align=left valign=top>pktRndm_en</td> 3740 <td align=left> 3741 tbd<br> 3742 Reset value is 0x0.</td></tr> 3743 <tr bgcolor=WHITE> 3744 <td bgcolor=WHITE align=center valign=top>05:04</td> 3745 <td align=left valign=top>RW</td> 3746 <td align=left valign=top>ipgLngth</td> 3747 <td align=left> 3748 tbd<br> 3749 Reset value is 0x0.</td></tr> 3750 <tr bgcolor=WHITE> 3751 <td bgcolor=WHITE align=center valign=top>03</td> 3752 <td align=left valign=top>RW</td> 3753 <td align=left valign=top>rxCnxDetect_r</td> 3754 <td align=left> 3755 tbd<br> 3756 Reset value is 0x0.</td></tr> 3757 <tr bgcolor=WHITE> 3758 <td bgcolor=WHITE align=center valign=top>02</td> 3759 <td align=left valign=top>RW</td> 3760 <td align=left valign=top>rxCnxDetect_force_r</td> 3761 <td align=left> 3762 tbd<br> 3763 Reset value is 0x0.</td></tr> 3764 <tr bgcolor=WHITE> 3765 <td bgcolor=WHITE align=center valign=top>01</td> 3766 <td align=left valign=top>RW</td> 3767 <td align=left valign=top>pre_emph_stair_rev_en</td> 3768 <td align=left> 3769 tbd<br> 3770 Reset value is 0x0.</td></tr> 3771 <tr bgcolor=WHITE> 3772 <td bgcolor=WHITE align=center valign=top>00</td> 3773 <td align=left valign=top>RW</td> 3774 <td align=left valign=top>mdio_txmargin_SM</td> 3775 <td align=left> 3776 tbd<br> 3777 Reset value is 0x0.</td></tr> 3778 </table><p> 3779 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3780 <hr> 3781 <b><a NAME="TX_DFE0_EXT_TXCTRL0">TX_DFE0_EXT_TXCTRL0 - Gen 1 ElecIdle Control Register</a></b><br> 3782 Address Offset = 32'h0000_5007<br> 3783 Physical Address = 32'h0000_5007<br> 3784 Reset Value = 16'h9090<br> 3785 Access = RW (16-bit only)<br> 3786 <table border=1 align=center width=100% cellpadding=0> 3787 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3788 <tr bgcolor=WHITE> 3789 <td bgcolor=WHITE align=center valign=top>15:13</td> 3790 <td align=left valign=top>RW</td> 3791 <td align=left valign=top>tx_delay_fall_G1</td> 3792 <td align=left> 3793 tbd<br> 3794 Reset value is 0x4.</td></tr> 3795 <tr bgcolor=WHITE> 3796 <td bgcolor=WHITE align=center valign=top>12:08</td> 3797 <td align=left valign=top>RW</td> 3798 <td align=left valign=top>rloop_delay_fall_G1</td> 3799 <td align=left> 3800 tbd<br> 3801 Reset value is 0x10.</td></tr> 3802 <tr bgcolor=WHITE> 3803 <td bgcolor=WHITE align=center valign=top>07:05</td> 3804 <td align=left valign=top>RW</td> 3805 <td align=left valign=top>tx_delay_rise_G1</td> 3806 <td align=left> 3807 tbd<br> 3808 Reset value is 0x4.</td></tr> 3809 <tr bgcolor=WHITE> 3810 <td bgcolor=WHITE align=center valign=top>04:00</td> 3811 <td align=left valign=top>RW</td> 3812 <td align=left valign=top>rloop_delay_rise_G1</td> 3813 <td align=left> 3814 tbd<br> 3815 Reset value is 0x10.</td></tr> 3816 </table><p> 3817 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3818 <hr> 3819 <b><a NAME="TX_DFE0_EXT_TXCTRL1">TX_DFE0_EXT_TXCTRL1 - Gen 2 ElecIdle Control Register</a></b><br> 3820 Address Offset = 32'h0000_5008<br> 3821 Physical Address = 32'h0000_5008<br> 3822 Reset Value = 16'h3090<br> 3823 Access = RW (16-bit only)<br> 3824 <table border=1 align=center width=100% cellpadding=0> 3825 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3826 <tr bgcolor=WHITE> 3827 <td bgcolor=WHITE align=center valign=top>15:13</td> 3828 <td align=left valign=top>RW</td> 3829 <td align=left valign=top>tx_delay_fall_G2</td> 3830 <td align=left> 3831 tbd<br> 3832 Reset value is 0x1.</td></tr> 3833 <tr bgcolor=WHITE> 3834 <td bgcolor=WHITE align=center valign=top>12:08</td> 3835 <td align=left valign=top>RW</td> 3836 <td align=left valign=top>rloop_delay_fall_G2</td> 3837 <td align=left> 3838 tbd<br> 3839 Reset value is 0x10.</td></tr> 3840 <tr bgcolor=WHITE> 3841 <td bgcolor=WHITE align=center valign=top>07:05</td> 3842 <td align=left valign=top>RW</td> 3843 <td align=left valign=top>tx_delay_rise_G2</td> 3844 <td align=left> 3845 tbd<br> 3846 Reset value is 0x4.</td></tr> 3847 <tr bgcolor=WHITE> 3848 <td bgcolor=WHITE align=center valign=top>04:00</td> 3849 <td align=left valign=top>RW</td> 3850 <td align=left valign=top>rloop_delay_rise_G2</td> 3851 <td align=left> 3852 tbd<br> 3853 Reset value is 0x10.</td></tr> 3854 </table><p> 3855 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3856 <hr> 3857 <b><a NAME="TX_DFE0_EXT_TXCTRL2">TX_DFE0_EXT_TXCTRL2 - Gen 3 ElecIdle Control Register</a></b><br> 3858 Address Offset = 32'h0000_5009<br> 3859 Physical Address = 32'h0000_5009<br> 3860 Reset Value = 16'h5090<br> 3861 Access = RW (16-bit only)<br> 3862 <table border=1 align=center width=100% cellpadding=0> 3863 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3864 <tr bgcolor=WHITE> 3865 <td bgcolor=WHITE align=center valign=top>15:13</td> 3866 <td align=left valign=top>RW</td> 3867 <td align=left valign=top>tx_delay_fall_G3</td> 3868 <td align=left> 3869 tbd<br> 3870 Reset value is 0x2.</td></tr> 3871 <tr bgcolor=WHITE> 3872 <td bgcolor=WHITE align=center valign=top>12:08</td> 3873 <td align=left valign=top>RW</td> 3874 <td align=left valign=top>rloop_delay_fall_G3</td> 3875 <td align=left> 3876 tbd<br> 3877 Reset value is 0x10.</td></tr> 3878 <tr bgcolor=WHITE> 3879 <td bgcolor=WHITE align=center valign=top>07:05</td> 3880 <td align=left valign=top>RW</td> 3881 <td align=left valign=top>tx_delay_rise_G3</td> 3882 <td align=left> 3883 tbd<br> 3884 Reset value is 0x4.</td></tr> 3885 <tr bgcolor=WHITE> 3886 <td bgcolor=WHITE align=center valign=top>04:00</td> 3887 <td align=left valign=top>RW</td> 3888 <td align=left valign=top>rloop_delay_rise_G3</td> 3889 <td align=left> 3890 tbd<br> 3891 Reset value is 0x10.</td></tr> 3892 </table><p> 3893 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3894 <hr> 3895 <b><a NAME="TX_DFE0_EXT_TXCTRL3">TX_DFE0_EXT_TXCTRL3 - Polarity Control Register</a></b><br> 3896 Address Offset = 32'h0000_500a<br> 3897 Physical Address = 32'h0000_500a<br> 3898 Reset Value = 16'h0000<br> 3899 Access = RW (16-bit only)<br> 3900 <table border=1 align=center width=100% cellpadding=0> 3901 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3902 <tr bgcolor=WHITE> 3903 <td bgcolor=WHITE align=center valign=top>15:06</td> 3904 <td align=left valign=top>RSVD</td> 3905 <td align=left valign=top>Reserved</td> 3906 <td align=left> 3907 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 3908 <tr bgcolor=WHITE> 3909 <td bgcolor=WHITE align=center valign=top>05</td> 3910 <td align=left valign=top>RW</td> 3911 <td align=left valign=top>rising_half_G3</td> 3912 <td align=left> 3913 tbd<br> 3914 Reset value is 0x0.</td></tr> 3915 <tr bgcolor=WHITE> 3916 <td bgcolor=WHITE align=center valign=top>04</td> 3917 <td align=left valign=top>RW</td> 3918 <td align=left valign=top>falling_half_G3</td> 3919 <td align=left> 3920 tbd<br> 3921 Reset value is 0x0.</td></tr> 3922 <tr bgcolor=WHITE> 3923 <td bgcolor=WHITE align=center valign=top>03</td> 3924 <td align=left valign=top>RW</td> 3925 <td align=left valign=top>rising_half_G2</td> 3926 <td align=left> 3927 tbd<br> 3928 Reset value is 0x0.</td></tr> 3929 <tr bgcolor=WHITE> 3930 <td bgcolor=WHITE align=center valign=top>02</td> 3931 <td align=left valign=top>RW</td> 3932 <td align=left valign=top>falling_half_G2</td> 3933 <td align=left> 3934 tbd<br> 3935 Reset value is 0x0.</td></tr> 3936 <tr bgcolor=WHITE> 3937 <td bgcolor=WHITE align=center valign=top>01</td> 3938 <td align=left valign=top>RW</td> 3939 <td align=left valign=top>rising_half_G1</td> 3940 <td align=left> 3941 tbd<br> 3942 Reset value is 0x0.</td></tr> 3943 <tr bgcolor=WHITE> 3944 <td bgcolor=WHITE align=center valign=top>00</td> 3945 <td align=left valign=top>RW</td> 3946 <td align=left valign=top>falling_half_G1</td> 3947 <td align=left> 3948 tbd<br> 3949 Reset value is 0x0.</td></tr> 3950 </table><p> 3951 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 3952 <hr> 3953 <b><a NAME="TX_DFE0_EXT_TXCONTROL2">TX_DFE0_EXT_TXCONTROL2 - G3 control 2 register</a></b><br> 3954 Address Offset = 32'h0000_500b<br> 3955 Physical Address = 32'h0000_500b<br> 3956 Reset Value = 16'h0001<br> 3957 Access = RW (16-bit only)<br> 3958 <table border=1 align=center width=100% cellpadding=0> 3959 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 3960 <tr bgcolor=WHITE> 3961 <td bgcolor=WHITE align=center valign=top>15</td> 3962 <td align=left valign=top>RW</td> 3963 <td align=left valign=top>tx_g3_ei_fifo_rst_cya</td> 3964 <td align=left> 3965 Reset EI FIFO<br> 3966 Reset value is 0x0.</td></tr> 3967 <tr bgcolor=WHITE> 3968 <td bgcolor=WHITE align=center valign=top>14:05</td> 3969 <td align=left valign=top>RSVD</td> 3970 <td align=left valign=top>Reserved</td> 3971 <td align=left> 3972 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 3973 <tr bgcolor=WHITE> 3974 <td bgcolor=WHITE align=center valign=top>04:02</td> 3975 <td align=left valign=top>RW</td> 3976 <td align=left valign=top>tx_g3f_tm_sel</td> 3977 <td align=left> 3978 lsm test mux field select <br> 3979 Reset value is 0.</td></tr> 3980 <tr bgcolor=WHITE> 3981 <td bgcolor=WHITE align=center valign=top>01</td> 3982 <td align=left valign=top>RW</td> 3983 <td align=left valign=top>tx_g3f_sw_rst</td> 3984 <td align=left> 3985 tx G3 framer - fifo pointer software reset<br> 3986 0 = de-asserted<br> 3987 1 = asserted<br> 3988 Reset value is 0.</td></tr> 3989 <tr bgcolor=WHITE> 3990 <td bgcolor=WHITE align=center valign=top>00</td> 3991 <td align=left valign=top>RW</td> 3992 <td align=left valign=top>tx_g3f_afrst_en</td> 3993 <td align=left> 3994 tx G3 framer - Auto fifo pointer reset enable<br> 3995 0 = disabled<br> 3996 1 = enabled<br> 3997 Reset value is 1.</td></tr> 3998 </table><p> 3999 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 4000 <hr> 4001 <b><a NAME="TX_DFE0_EXT_TXSTATUS2">TX_DFE0_EXT_TXSTATUS2 - G3 status register</a></b><br> 4002 Address Offset = 32'h0000_500c<br> 4003 Physical Address = 32'h0000_500c<br> 4004 Reset Value = 16'h0000<br> 4005 Access = RO (16-bit only)<br> 4006 <table border=1 align=center width=100% cellpadding=0> 4007 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4008 <tr bgcolor=WHITE> 4009 <td bgcolor=WHITE align=center valign=top>15:03</td> 4010 <td align=left valign=top>RSVD</td> 4011 <td align=left valign=top>Reserved</td> 4012 <td align=left> 4013 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4014 <tr bgcolor=WHITE> 4015 <td bgcolor=WHITE align=center valign=top>02</td> 4016 <td align=left valign=top>RO</td> 4017 <td align=left valign=top>tx_g3f_afrst</td> 4018 <td align=left> 4019 rx G3 framer fifo autofifo reset has occured<br> 4020 0 = normal<br> 4021 1 = afrst<br> 4022 Reset value is 0.</td></tr> 4023 <tr bgcolor=WHITE> 4024 <td bgcolor=WHITE align=center valign=top>01</td> 4025 <td align=left valign=top>RO</td> 4026 <td align=left valign=top>tx_g3f_unflow</td> 4027 <td align=left> 4028 rx G3 framer fifo underflow has occured<br> 4029 0 = normal<br> 4030 1 = underflow<br> 4031 Reset value is 0.</td></tr> 4032 <tr bgcolor=WHITE> 4033 <td bgcolor=WHITE align=center valign=top>00</td> 4034 <td align=left valign=top>RO</td> 4035 <td align=left valign=top>tx_g3f_ovflow</td> 4036 <td align=left> 4037 rx G3 framer fifo overflow has occured<br> 4038 0 = normal<br> 4039 1 = overflow<br> 4040 Reset value is 0.</td></tr> 4041 </table><p> 4042 <A HREF="#TX_DFE0_EXT Registers">Return to TX_DFE0_EXT Table</A><p> 4043 <hr> 4044 <H1><a NAME="RX_DFE0_EXT Registers">RX_DFE0_EXT Registers</a></H1> 4045 <table border=1 align=center width=100% cellpadding=0> 4046 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 4047 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 4048 <tr> 4049 <td align=center>0x7000</td><td><A HREF="#RX_DFE0_EXT_RXSTATUS1">RX_DFE0_EXT_RXSTATUS1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">status1</div> </td> <td align=center>16'h0000</td></tr> 4050 <tr> 4051 <td align=center>0x7001</td><td><A HREF="#RX_DFE0_EXT_RXSTATUS2">RX_DFE0_EXT_RXSTATUS2</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">status_2</div> </td> <td align=center>16'h0000</td></tr> 4052 <tr> 4053 <td align=center>0x7002</td><td><A HREF="#RX_DFE0_EXT_RXSTATUS3">RX_DFE0_EXT_RXSTATUS3</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">status3</div> </td> <td align=center>16'h0000</td></tr> 4054 <tr> 4055 <td align=center>0x7003</td><td><A HREF="#RX_DFE0_EXT_RXCONTROL1">RX_DFE0_EXT_RXCONTROL1</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">Status1Sel_SM</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">testMuxSelect_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tpctrl_SM0</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tpctrl_SM1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_rx_G3_RxDataValidRealign</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">Status2Sel_SM</div> </td> <td align=center>16'h0022</td></tr> 4056 <tr> 4057 <td align=center>0x7004</td><td><A HREF="#RX_DFE0_EXT_RXCONTROL2">RX_DFE0_EXT_RXCONTROL2</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">forceDecodeOn_SM</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">err_max_cnt_sel_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">clear_err_cnt_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">auto_clear_err_cnt_SM</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ckcmp_mdio_rst</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ckcmp_afrst_ptr_err_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ckcmp_afrst_phaseptr_err_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_ckcmp_phase_only_en_SM</div> </td> <td align=center>16'h0000</td></tr> 4058 <tr> 4059 <td align=center>0x7005</td><td><A HREF="#RX_DFE0_EXT_RXCONTROL3">RX_DFE0_EXT_RXCONTROL3</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_seed_ld_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">packet_count_en_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxErrDisparity_dis_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_clr_dis_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rxd_dec_sel_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cgbad_tst_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">Emon_en_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_en_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cgbad_en_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">fpat_md_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">useRxSeqDone_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">useSigdet_SM</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">commonClockMode_force_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">commonClockMode_force_value</div> </td> <td align=center>16'h0080</td></tr> 4060 <tr> 4061 <td align=center>0x7006</td><td><A HREF="#RX_DFE0_EXT_RXCONTROL4">RX_DFE0_EXT_RXCONTROL4</A><br>Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_L0s_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comma_mask_force_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comma_mask_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">statMuxRegDis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sync_status_force_r_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sync_status_force_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comma_adj_en_force_ext_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comma_adj_en_force_sync_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comma_adj_en_force_r_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">comma_adj_en_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">link_en_force_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">link_en_r</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_polarity_force_SM</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_polarity_r</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rxd1g_dec_dis_SM</div> </td> <td align=center>16'h0110</td></tr> 4062 <tr> 4063 <td align=center>0x7007</td><td><A HREF="#RX_DFE0_EXT_RXCONTROL5">RX_DFE0_EXT_RXCONTROL5</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">mdio_tcSelect</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ana_rx_mdio_sel_fts_L0S</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_DisableOvUnFlow</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_rx_G3_BlockStatusDis</div> </td> <td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved_for_eco</div> </td> <td align=center>16'hf000</td></tr> 4064 <tr> 4065 <td align=center>0x7008</td><td><A HREF="#RX_DFE0_EXT_RXCONTROL6">RX_DFE0_EXT_RXCONTROL6</A><br>Register</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ana_rx_mdio_sel_com_num</div> </td> <td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ckcmp_event_clr_dis</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ckcmp_wr_event_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ckcmp_rd_event_sel</div> </td> <td align=center>16'h0000</td></tr> 4066 </table><p> 4067 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 4068 <hr> 4069 <b><a NAME="RX_DFE0_EXT_RXSTATUS1">RX_DFE0_EXT_RXSTATUS1 - Register</a></b><br> 4070 Address Offset = 32'h0000_7000<br> 4071 Physical Address = 32'h0000_7000<br> 4072 Reset Value = 16'h0000<br> 4073 Access = RO (16-bit only)<br> 4074 <table border=1 align=center width=100% cellpadding=0> 4075 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4076 <tr bgcolor=WHITE> 4077 <td bgcolor=WHITE align=center valign=top>15:00</td> 4078 <td align=left valign=top>RO</td> 4079 <td align=left valign=top>status1</td> 4080 <td align=left> 4081 tbd<br> 4082 Reset value is 0x0.</td></tr> 4083 </table><p> 4084 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4085 <hr> 4086 <b><a NAME="RX_DFE0_EXT_RXSTATUS2">RX_DFE0_EXT_RXSTATUS2 - Register</a></b><br> 4087 Address Offset = 32'h0000_7001<br> 4088 Physical Address = 32'h0000_7001<br> 4089 Reset Value = 16'h0000<br> 4090 Access = RO (16-bit only)<br> 4091 <table border=1 align=center width=100% cellpadding=0> 4092 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4093 <tr bgcolor=WHITE> 4094 <td bgcolor=WHITE align=center valign=top>15:00</td> 4095 <td align=left valign=top>RO</td> 4096 <td align=left valign=top>status_2</td> 4097 <td align=left> 4098 tbd<br> 4099 Reset value is 0x0.</td></tr> 4100 </table><p> 4101 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4102 <hr> 4103 <b><a NAME="RX_DFE0_EXT_RXSTATUS3">RX_DFE0_EXT_RXSTATUS3 - Register</a></b><br> 4104 Address Offset = 32'h0000_7002<br> 4105 Physical Address = 32'h0000_7002<br> 4106 Reset Value = 16'h0000<br> 4107 Access = RO (16-bit only)<br> 4108 <table border=1 align=center width=100% cellpadding=0> 4109 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4110 <tr bgcolor=WHITE> 4111 <td bgcolor=WHITE align=center valign=top>15:00</td> 4112 <td align=left valign=top>RO</td> 4113 <td align=left valign=top>status3</td> 4114 <td align=left> 4115 tbd<br> 4116 Reset value is 0x0.</td></tr> 4117 </table><p> 4118 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4119 <hr> 4120 <b><a NAME="RX_DFE0_EXT_RXCONTROL1">RX_DFE0_EXT_RXCONTROL1 - Register</a></b><br> 4121 Address Offset = 32'h0000_7003<br> 4122 Physical Address = 32'h0000_7003<br> 4123 Reset Value = 16'h0022<br> 4124 Access = RW (16-bit only)<br> 4125 <table border=1 align=center width=100% cellpadding=0> 4126 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4127 <tr bgcolor=WHITE> 4128 <td bgcolor=WHITE align=center valign=top>15:13</td> 4129 <td align=left valign=top>RW</td> 4130 <td align=left valign=top>Status1Sel_SM</td> 4131 <td align=left> 4132 tbd<br> 4133 Reset value is 0x0.</td></tr> 4134 <tr bgcolor=WHITE> 4135 <td bgcolor=WHITE align=center valign=top>12</td> 4136 <td align=left valign=top>RSVD</td> 4137 <td align=left valign=top>Reserved</td> 4138 <td align=left> 4139 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 4140 <tr bgcolor=WHITE> 4141 <td bgcolor=WHITE align=center valign=top>11:08</td> 4142 <td align=left valign=top>RW</td> 4143 <td align=left valign=top>testMuxSelect_SM</td> 4144 <td align=left> 4145 tbd<br> 4146 Reset value is 0x0.</td></tr> 4147 <tr bgcolor=WHITE> 4148 <td bgcolor=WHITE align=center valign=top>07</td> 4149 <td align=left valign=top>RW</td> 4150 <td align=left valign=top>tpctrl_SM0</td> 4151 <td align=left> 4152 gets assigned to bit [3]<br> 4153 Reset value is 0x0.</td></tr> 4154 <tr bgcolor=WHITE> 4155 <td bgcolor=WHITE align=center valign=top>06:04</td> 4156 <td align=left valign=top>RW</td> 4157 <td align=left valign=top>tpctrl_SM1</td> 4158 <td align=left> 4159 gets assigned to bits [2:0]<br> 4160 Reset value is 0x2.</td></tr> 4161 <tr bgcolor=WHITE> 4162 <td bgcolor=WHITE align=center valign=top>03</td> 4163 <td align=left valign=top>RW</td> 4164 <td align=left valign=top>mdio_rx_G3_RxDataValidRealign</td> 4165 <td align=left> 4166 RxDataValidRealign<br> 4167 Reset value is 0x0.</td></tr> 4168 <tr bgcolor=WHITE> 4169 <td bgcolor=WHITE align=center valign=top>02:00</td> 4170 <td align=left valign=top>RW</td> 4171 <td align=left valign=top>Status2Sel_SM</td> 4172 <td align=left> 4173 tbd<br> 4174 Reset value is 0x2.</td></tr> 4175 </table><p> 4176 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4177 <hr> 4178 <b><a NAME="RX_DFE0_EXT_RXCONTROL2">RX_DFE0_EXT_RXCONTROL2 - Register</a></b><br> 4179 Address Offset = 32'h0000_7004<br> 4180 Physical Address = 32'h0000_7004<br> 4181 Reset Value = 16'h0000<br> 4182 Access = RW (16-bit only)<br> 4183 <table border=1 align=center width=100% cellpadding=0> 4184 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4185 <tr bgcolor=WHITE> 4186 <td bgcolor=WHITE align=center valign=top>15</td> 4187 <td align=left valign=top>RW</td> 4188 <td align=left valign=top>forceDecodeOn_SM</td> 4189 <td align=left> 4190 tbd<br> 4191 Reset value is 0x0.</td></tr> 4192 <tr bgcolor=WHITE> 4193 <td bgcolor=WHITE align=center valign=top>14:11</td> 4194 <td align=left valign=top>RSVD</td> 4195 <td align=left valign=top>Reserved</td> 4196 <td align=left> 4197 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4198 <tr bgcolor=WHITE> 4199 <td bgcolor=WHITE align=center valign=top>10:08</td> 4200 <td align=left valign=top>RW</td> 4201 <td align=left valign=top>err_max_cnt_sel_SM</td> 4202 <td align=left> 4203 tbd<br> 4204 Reset value is 0x0.</td></tr> 4205 <tr bgcolor=WHITE> 4206 <td bgcolor=WHITE align=center valign=top>07</td> 4207 <td align=left valign=top>RW</td> 4208 <td align=left valign=top>clear_err_cnt_SM</td> 4209 <td align=left> 4210 tbd<br> 4211 Reset value is 0x0.</td></tr> 4212 <tr bgcolor=WHITE> 4213 <td bgcolor=WHITE align=center valign=top>06</td> 4214 <td align=left valign=top>RW</td> 4215 <td align=left valign=top>auto_clear_err_cnt_SM</td> 4216 <td align=left> 4217 tbd<br> 4218 Reset value is 0x0.</td></tr> 4219 <tr bgcolor=WHITE> 4220 <td bgcolor=WHITE align=center valign=top>05:04</td> 4221 <td align=left valign=top>RSVD</td> 4222 <td align=left valign=top>Reserved</td> 4223 <td align=left> 4224 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4225 <tr bgcolor=WHITE> 4226 <td bgcolor=WHITE align=center valign=top>03</td> 4227 <td align=left valign=top>RW</td> 4228 <td align=left valign=top>mdio_ckcmp_mdio_rst</td> 4229 <td align=left> 4230 tbd<br> 4231 Reset value is 0x0.</td></tr> 4232 <tr bgcolor=WHITE> 4233 <td bgcolor=WHITE align=center valign=top>02</td> 4234 <td align=left valign=top>RW</td> 4235 <td align=left valign=top>mdio_ckcmp_afrst_ptr_err_en</td> 4236 <td align=left> 4237 tbd<br> 4238 Reset value is 0x0.</td></tr> 4239 <tr bgcolor=WHITE> 4240 <td bgcolor=WHITE align=center valign=top>01</td> 4241 <td align=left valign=top>RW</td> 4242 <td align=left valign=top>mdio_ckcmp_afrst_phaseptr_err_en</td> 4243 <td align=left> 4244 tbd<br> 4245 Reset value is 0x0.</td></tr> 4246 <tr bgcolor=WHITE> 4247 <td bgcolor=WHITE align=center valign=top>00</td> 4248 <td align=left valign=top>RW</td> 4249 <td align=left valign=top>mdio_ckcmp_phase_only_en_SM</td> 4250 <td align=left> 4251 tbd<br> 4252 Reset value is 0x0.</td></tr> 4253 </table><p> 4254 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4255 <hr> 4256 <b><a NAME="RX_DFE0_EXT_RXCONTROL3">RX_DFE0_EXT_RXCONTROL3 - Register</a></b><br> 4257 Address Offset = 32'h0000_7005<br> 4258 Physical Address = 32'h0000_7005<br> 4259 Reset Value = 16'h0080<br> 4260 Access = RW (16-bit only)<br> 4261 <table border=1 align=center width=100% cellpadding=0> 4262 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4263 <tr bgcolor=WHITE> 4264 <td bgcolor=WHITE align=center valign=top>15</td> 4265 <td align=left valign=top>RW</td> 4266 <td align=left valign=top>prbs_seed_ld_SM</td> 4267 <td align=left> 4268 tbd<br> 4269 Reset value is 0x0.</td></tr> 4270 <tr bgcolor=WHITE> 4271 <td bgcolor=WHITE align=center valign=top>14</td> 4272 <td align=left valign=top>RW</td> 4273 <td align=left valign=top>packet_count_en_SM</td> 4274 <td align=left> 4275 tbd<br> 4276 Reset value is 0x0.</td></tr> 4277 <tr bgcolor=WHITE> 4278 <td bgcolor=WHITE align=center valign=top>13</td> 4279 <td align=left valign=top>RW</td> 4280 <td align=left valign=top>RxErrDisparity_dis_SM</td> 4281 <td align=left> 4282 tbd<br> 4283 Reset value is 0x0.</td></tr> 4284 <tr bgcolor=WHITE> 4285 <td bgcolor=WHITE align=center valign=top>12</td> 4286 <td align=left valign=top>RW</td> 4287 <td align=left valign=top>prbs_clr_dis_r</td> 4288 <td align=left> 4289 tbd<br> 4290 Reset value is 0x0.</td></tr> 4291 <tr bgcolor=WHITE> 4292 <td bgcolor=WHITE align=center valign=top>11</td> 4293 <td align=left valign=top>RW</td> 4294 <td align=left valign=top>rxd_dec_sel_r</td> 4295 <td align=left> 4296 tbd<br> 4297 Reset value is 0x0.</td></tr> 4298 <tr bgcolor=WHITE> 4299 <td bgcolor=WHITE align=center valign=top>10</td> 4300 <td align=left valign=top>RW</td> 4301 <td align=left valign=top>cgbad_tst_SM</td> 4302 <td align=left> 4303 tbd<br> 4304 Reset value is 0x0.</td></tr> 4305 <tr bgcolor=WHITE> 4306 <td bgcolor=WHITE align=center valign=top>09</td> 4307 <td align=left valign=top>RW</td> 4308 <td align=left valign=top>Emon_en_r</td> 4309 <td align=left> 4310 tbd<br> 4311 Reset value is 0x0.</td></tr> 4312 <tr bgcolor=WHITE> 4313 <td bgcolor=WHITE align=center valign=top>08</td> 4314 <td align=left valign=top>RW</td> 4315 <td align=left valign=top>prbs_en_r</td> 4316 <td align=left> 4317 tbd<br> 4318 Reset value is 0x0.</td></tr> 4319 <tr bgcolor=WHITE> 4320 <td bgcolor=WHITE align=center valign=top>07</td> 4321 <td align=left valign=top>RW</td> 4322 <td align=left valign=top>cgbad_en_SM</td> 4323 <td align=left> 4324 tbd<br> 4325 Reset value is 0x1.</td></tr> 4326 <tr bgcolor=WHITE> 4327 <td bgcolor=WHITE align=center valign=top>06</td> 4328 <td align=left valign=top>RW</td> 4329 <td align=left valign=top>fpat_md_SM</td> 4330 <td align=left> 4331 tbd<br> 4332 Reset value is 0x0.</td></tr> 4333 <tr bgcolor=WHITE> 4334 <td bgcolor=WHITE align=center valign=top>05</td> 4335 <td align=left valign=top>RW</td> 4336 <td align=left valign=top>useRxSeqDone_SM</td> 4337 <td align=left> 4338 tbd<br> 4339 Reset value is 0x0.</td></tr> 4340 <tr bgcolor=WHITE> 4341 <td bgcolor=WHITE align=center valign=top>04</td> 4342 <td align=left valign=top>RW</td> 4343 <td align=left valign=top>useSigdet_SM</td> 4344 <td align=left> 4345 tbd<br> 4346 Reset value is 0x0.</td></tr> 4347 <tr bgcolor=WHITE> 4348 <td bgcolor=WHITE align=center valign=top>03:02</td> 4349 <td align=left valign=top>RSVD</td> 4350 <td align=left valign=top>Reserved</td> 4351 <td align=left> 4352 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4353 <tr bgcolor=WHITE> 4354 <td bgcolor=WHITE align=center valign=top>01</td> 4355 <td align=left valign=top>RW</td> 4356 <td align=left valign=top>commonClockMode_force_SM</td> 4357 <td align=left> 4358 tbd<br> 4359 Reset value is 0x0.</td></tr> 4360 <tr bgcolor=WHITE> 4361 <td bgcolor=WHITE align=center valign=top>00</td> 4362 <td align=left valign=top>RW</td> 4363 <td align=left valign=top>commonClockMode_force_value</td> 4364 <td align=left> 4365 tbd<br> 4366 Reset value is 0x0.</td></tr> 4367 </table><p> 4368 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4369 <hr> 4370 <b><a NAME="RX_DFE0_EXT_RXCONTROL4">RX_DFE0_EXT_RXCONTROL4 - Register</a></b><br> 4371 Address Offset = 32'h0000_7006<br> 4372 Physical Address = 32'h0000_7006<br> 4373 Reset Value = 16'h0110<br> 4374 Access = RW (16-bit only)<br> 4375 <table border=1 align=center width=100% cellpadding=0> 4376 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4377 <tr bgcolor=WHITE> 4378 <td bgcolor=WHITE align=center valign=top>15</td> 4379 <td align=left valign=top>RW</td> 4380 <td align=left valign=top>prbs_L0s_SM</td> 4381 <td align=left> 4382 tbd<br> 4383 Reset value is 0x0.</td></tr> 4384 <tr bgcolor=WHITE> 4385 <td bgcolor=WHITE align=center valign=top>14</td> 4386 <td align=left valign=top>RW</td> 4387 <td align=left valign=top>comma_mask_force_r</td> 4388 <td align=left> 4389 tbd<br> 4390 Reset value is 0x0.</td></tr> 4391 <tr bgcolor=WHITE> 4392 <td bgcolor=WHITE align=center valign=top>13</td> 4393 <td align=left valign=top>RW</td> 4394 <td align=left valign=top>comma_mask_r</td> 4395 <td align=left> 4396 tbd<br> 4397 Reset value is 0x0.</td></tr> 4398 <tr bgcolor=WHITE> 4399 <td bgcolor=WHITE align=center valign=top>12</td> 4400 <td align=left valign=top>RW</td> 4401 <td align=left valign=top>statMuxRegDis</td> 4402 <td align=left> 4403 tbd<br> 4404 Reset value is 0x0.</td></tr> 4405 <tr bgcolor=WHITE> 4406 <td bgcolor=WHITE align=center valign=top>11</td> 4407 <td align=left valign=top>RW</td> 4408 <td align=left valign=top>sync_status_force_r_SM</td> 4409 <td align=left> 4410 tbd<br> 4411 Reset value is 0x0.</td></tr> 4412 <tr bgcolor=WHITE> 4413 <td bgcolor=WHITE align=center valign=top>10</td> 4414 <td align=left valign=top>RW</td> 4415 <td align=left valign=top>sync_status_force_r</td> 4416 <td align=left> 4417 tbd<br> 4418 Reset value is 0x0.</td></tr> 4419 <tr bgcolor=WHITE> 4420 <td bgcolor=WHITE align=center valign=top>09</td> 4421 <td align=left valign=top>RW</td> 4422 <td align=left valign=top>comma_adj_en_force_ext_SM</td> 4423 <td align=left> 4424 tbd<br> 4425 Reset value is 0x0.</td></tr> 4426 <tr bgcolor=WHITE> 4427 <td bgcolor=WHITE align=center valign=top>08</td> 4428 <td align=left valign=top>RW</td> 4429 <td align=left valign=top>comma_adj_en_force_sync_SM</td> 4430 <td align=left> 4431 tbd<br> 4432 Reset value is 0x1.</td></tr> 4433 <tr bgcolor=WHITE> 4434 <td bgcolor=WHITE align=center valign=top>07</td> 4435 <td align=left valign=top>RW</td> 4436 <td align=left valign=top>comma_adj_en_force_r_SM</td> 4437 <td align=left> 4438 tbd<br> 4439 Reset value is 0x0.</td></tr> 4440 <tr bgcolor=WHITE> 4441 <td bgcolor=WHITE align=center valign=top>06</td> 4442 <td align=left valign=top>RW</td> 4443 <td align=left valign=top>comma_adj_en_r</td> 4444 <td align=left> 4445 tbd<br> 4446 Reset value is 0x0.</td></tr> 4447 <tr bgcolor=WHITE> 4448 <td bgcolor=WHITE align=center valign=top>05</td> 4449 <td align=left valign=top>RW</td> 4450 <td align=left valign=top>link_en_force_SM</td> 4451 <td align=left> 4452 tbd<br> 4453 Reset value is 0x0.</td></tr> 4454 <tr bgcolor=WHITE> 4455 <td bgcolor=WHITE align=center valign=top>04</td> 4456 <td align=left valign=top>RW</td> 4457 <td align=left valign=top>link_en_r</td> 4458 <td align=left> 4459 tbd<br> 4460 Reset value is 0x1.</td></tr> 4461 <tr bgcolor=WHITE> 4462 <td bgcolor=WHITE align=center valign=top>03</td> 4463 <td align=left valign=top>RW</td> 4464 <td align=left valign=top>rx_polarity_force_SM</td> 4465 <td align=left> 4466 tbd<br> 4467 Reset value is 0x0.</td></tr> 4468 <tr bgcolor=WHITE> 4469 <td bgcolor=WHITE align=center valign=top>02</td> 4470 <td align=left valign=top>RW</td> 4471 <td align=left valign=top>rx_polarity_r</td> 4472 <td align=left> 4473 tbd<br> 4474 Reset value is 0x0.</td></tr> 4475 <tr bgcolor=WHITE> 4476 <td bgcolor=WHITE align=center valign=top>01</td> 4477 <td align=left valign=top>RSVD</td> 4478 <td align=left valign=top>Reserved</td> 4479 <td align=left> 4480 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 4481 <tr bgcolor=WHITE> 4482 <td bgcolor=WHITE align=center valign=top>00</td> 4483 <td align=left valign=top>RW</td> 4484 <td align=left valign=top>rxd1g_dec_dis_SM</td> 4485 <td align=left> 4486 tbd<br> 4487 Reset value is 0x0.</td></tr> 4488 </table><p> 4489 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4490 <hr> 4491 <b><a NAME="RX_DFE0_EXT_RXCONTROL5">RX_DFE0_EXT_RXCONTROL5 - Register</a></b><br> 4492 Address Offset = 32'h0000_7007<br> 4493 Physical Address = 32'h0000_7007<br> 4494 Reset Value = 16'hf000<br> 4495 Access = RW (16-bit only)<br> 4496 <table border=1 align=center width=100% cellpadding=0> 4497 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4498 <tr bgcolor=WHITE> 4499 <td bgcolor=WHITE align=center valign=top>15:08</td> 4500 <td align=left valign=top>RW</td> 4501 <td align=left valign=top>mdio_tcSelect</td> 4502 <td align=left> 4503 sigdet_filter<br> 4504 Reset value is 0xf0.</td></tr> 4505 <tr bgcolor=WHITE> 4506 <td bgcolor=WHITE align=center valign=top>07</td> 4507 <td align=left valign=top>RW</td> 4508 <td align=left valign=top>ana_rx_mdio_sel_fts_L0S</td> 4509 <td align=left> 4510 ana_rx_mdio_sel_fts_L0S<br> 4511 Reset value is 0x0.</td></tr> 4512 <tr bgcolor=WHITE> 4513 <td bgcolor=WHITE align=center valign=top>06</td> 4514 <td align=left valign=top>RW</td> 4515 <td align=left valign=top>mdio_DisableOvUnFlow</td> 4516 <td align=left> 4517 tbd<br> 4518 Reset value is 0x0.</td></tr> 4519 <tr bgcolor=WHITE> 4520 <td bgcolor=WHITE align=center valign=top>05</td> 4521 <td align=left valign=top>RW</td> 4522 <td align=left valign=top>mdio_rx_G3_BlockStatusDis</td> 4523 <td align=left> 4524 mdio_rx_G3_BlockStatusDis<br> 4525 Reset value is 0x0.</td></tr> 4526 <tr bgcolor=WHITE> 4527 <td bgcolor=WHITE align=center valign=top>04:00</td> 4528 <td align=left valign=top>RSVD</td> 4529 <td align=left valign=top>Reserved</td> 4530 <td align=left> 4531 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4532 </table><p> 4533 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4534 <hr> 4535 <b><a NAME="RX_DFE0_EXT_RXCONTROL6">RX_DFE0_EXT_RXCONTROL6 - Register</a></b><br> 4536 Address Offset = 32'h0000_7008<br> 4537 Physical Address = 32'h0000_7008<br> 4538 Reset Value = 16'h0000<br> 4539 Access = RW (16-bit only)<br> 4540 <table border=1 align=center width=100% cellpadding=0> 4541 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4542 <tr bgcolor=WHITE> 4543 <td bgcolor=WHITE align=center valign=top>15:14</td> 4544 <td align=left valign=top>RW</td> 4545 <td align=left valign=top>ana_rx_mdio_sel_com_num</td> 4546 <td align=left> 4547 rx_sel_com_num<br> 4548 Reset value is 0x0.</td></tr> 4549 <tr bgcolor=WHITE> 4550 <td bgcolor=WHITE align=center valign=top>13:09</td> 4551 <td align=left valign=top>RSVD</td> 4552 <td align=left valign=top>Reserved</td> 4553 <td align=left> 4554 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4555 <tr bgcolor=WHITE> 4556 <td bgcolor=WHITE align=center valign=top>08</td> 4557 <td align=left valign=top>RW</td> 4558 <td align=left valign=top>ckcmp_event_clr_dis</td> 4559 <td align=left> 4560 tbd<br> 4561 Reset value is 0x0.</td></tr> 4562 <tr bgcolor=WHITE> 4563 <td bgcolor=WHITE align=center valign=top>07:04</td> 4564 <td align=left valign=top>RW</td> 4565 <td align=left valign=top>ckcmp_wr_event_sel</td> 4566 <td align=left> 4567 tbd<br> 4568 Reset value is 0x0.</td></tr> 4569 <tr bgcolor=WHITE> 4570 <td bgcolor=WHITE align=center valign=top>03:00</td> 4571 <td align=left valign=top>RW</td> 4572 <td align=left valign=top>ckcmp_rd_event_sel</td> 4573 <td align=left> 4574 tbd<br> 4575 Reset value is 0x0.</td></tr> 4576 </table><p> 4577 <A HREF="#RX_DFE0_EXT Registers">Return to RX_DFE0_EXT Table</A><p> 4578 <hr> 4579 <H1><a NAME="RX_DFE2_EXT Registers">RX_DFE2_EXT Registers</a></H1> 4580 <table border=1 align=center width=100% cellpadding=0> 4581 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 4582 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 4583 <tr> 4584 <td align=center>0x7200</td><td><A HREF="#RX_DFE2_EXT_CONTROL1">RX_DFE2_EXT_CONTROL1</A><br>G3 control 1 register</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_gbox_sw_rst</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_gbox_afrst_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">lsm_sh_invalid_cnt</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lsm_tm_clk_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">lsm_tm_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">lsm_sreg_field_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lsm_afrst_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lsm_sw_frst</div> </td> <td align=center>16'h1002</td></tr> 4585 <tr> 4586 <td align=center>0x7201</td><td><A HREF="#RX_DFE2_EXT_STATUS1">RX_DFE2_EXT_STATUS1</A><br>G3 status 1 register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lsm_status</div> </td> <td align=center>16'h0000</td></tr> 4587 <tr> 4588 <td align=center>0x7202</td><td><A HREF="#RX_DFE2_EXT_STATUS2">RX_DFE2_EXT_STATUS2</A><br>G3 status 2 register</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_gbox_afrst</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_gbox_unflow</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_gbox_ovflow</div> </td> <td align=center>16'h0000</td></tr> 4589 </table><p> 4590 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 4591 <hr> 4592 <b><a NAME="RX_DFE2_EXT_CONTROL1">RX_DFE2_EXT_CONTROL1 - G3 control 1 register</a></b><br> 4593 Address Offset = 32'h0000_7200<br> 4594 Physical Address = 32'h0000_7200<br> 4595 Reset Value = 16'h1002<br> 4596 Access = RW (16-bit only)<br> 4597 <table border=1 align=center width=100% cellpadding=0> 4598 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4599 <tr bgcolor=WHITE> 4600 <td bgcolor=WHITE align=center valign=top>15:14</td> 4601 <td align=left valign=top>RSVD</td> 4602 <td align=left valign=top>Reserved</td> 4603 <td align=left> 4604 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4605 <tr bgcolor=WHITE> 4606 <td bgcolor=WHITE align=center valign=top>13</td> 4607 <td align=left valign=top>RW</td> 4608 <td align=left valign=top>rg_gbox_sw_rst</td> 4609 <td align=left> 4610 rx Gbox - fifo pointer software reset<br> 4611 0 = de-asserted<br> 4612 1 = asserted<br> 4613 Reset value is 0.</td></tr> 4614 <tr bgcolor=WHITE> 4615 <td bgcolor=WHITE align=center valign=top>12</td> 4616 <td align=left valign=top>RW</td> 4617 <td align=left valign=top>rx_gbox_afrst_en</td> 4618 <td align=left> 4619 rx Gbox - Auto fifo pointer reset enable<br> 4620 0 = disabled<br> 4621 1 = enabled<br> 4622 Reset value is 1.</td></tr> 4623 <tr bgcolor=WHITE> 4624 <td bgcolor=WHITE align=center valign=top>11:09</td> 4625 <td align=left valign=top>RW</td> 4626 <td align=left valign=top>lsm_sh_invalid_cnt</td> 4627 <td align=left> 4628 lsm  - invalid sync header hysterisis count<br> 4629 Reset value is 0.</td></tr> 4630 <tr bgcolor=WHITE> 4631 <td bgcolor=WHITE align=center valign=top>08</td> 4632 <td align=left valign=top>RW</td> 4633 <td align=left valign=top>lsm_tm_clk_en</td> 4634 <td align=left> 4635 lsm test mux clock enable<br> 4636 0 = disabled<br> 4637 1 = enabled<br> 4638 Reset value is 0.</td></tr> 4639 <tr bgcolor=WHITE> 4640 <td bgcolor=WHITE align=center valign=top>07:04</td> 4641 <td align=left valign=top>RW</td> 4642 <td align=left valign=top>lsm_tm_sel</td> 4643 <td align=left> 4644 lsm test mux field select <br> 4645 Reset value is 0.</td></tr> 4646 <tr bgcolor=WHITE> 4647 <td bgcolor=WHITE align=center valign=top>03:02</td> 4648 <td align=left valign=top>RW</td> 4649 <td align=left valign=top>lsm_sreg_field_sel</td> 4650 <td align=left> 4651 lsm status register select <br> 4652 Reset value is 0.</td></tr> 4653 <tr bgcolor=WHITE> 4654 <td bgcolor=WHITE align=center valign=top>01</td> 4655 <td align=left valign=top>RW</td> 4656 <td align=left valign=top>lsm_afrst_en</td> 4657 <td align=left> 4658 lsm - Auto fifo reset enable<br> 4659 0 = disabled<br> 4660 1 = enabled<br> 4661 Reset value is 1.</td></tr> 4662 <tr bgcolor=WHITE> 4663 <td bgcolor=WHITE align=center valign=top>00</td> 4664 <td align=left valign=top>RW</td> 4665 <td align=left valign=top>lsm_sw_frst</td> 4666 <td align=left> 4667 lsm - Software fifo pointer reset<br> 4668 0 = de-asserted<br> 4669 1 = asserted<br> 4670 Reset value is 0.</td></tr> 4671 </table><p> 4672 <A HREF="#RX_DFE2_EXT Registers">Return to RX_DFE2_EXT Table</A><p> 4673 <hr> 4674 <b><a NAME="RX_DFE2_EXT_STATUS1">RX_DFE2_EXT_STATUS1 - G3 status 1 register</a></b><br> 4675 Address Offset = 32'h0000_7201<br> 4676 Physical Address = 32'h0000_7201<br> 4677 Reset Value = 16'h0000<br> 4678 Access = RO (16-bit only)<br> 4679 <table border=1 align=center width=100% cellpadding=0> 4680 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4681 <tr bgcolor=WHITE> 4682 <td bgcolor=WHITE align=center valign=top>15:00</td> 4683 <td align=left valign=top>RO</td> 4684 <td align=left valign=top>lsm_status</td> 4685 <td align=left> 4686 The value dependend on the bits selected by lsm_sreg_field_sel<br> 4687 lsm_sreg_field_sel = 2'b00<br> 4688    {1'b0, latched_SKIP66_det, latched_SKIP98_det,<br> 4689     latched_SKIP130_det, latched_SKIP162_det,<br> 4690     latched_SKIP194_det, latched_SDS_det,<br> 4691     latched_EIEOS_det, latched_sh_valid,<br> 4692     latched_EIOS_det, latched_FTS_det,<br> 4693     latched_TS1_det, latched_TS2_det,<br> 4694     latched_lsm_state[2:0]};<br> 4695 lsm_sreg_field_sel = 2'b01<br> 4696    { {10{1'b0}},<br> 4697      lferr_spacing, lferr_radr, lferr_wadr, lsm_state[2:0]}<br> 4698 Reset value is 0.</td></tr> 4699 </table><p> 4700 <A HREF="#RX_DFE2_EXT Registers">Return to RX_DFE2_EXT Table</A><p> 4701 <hr> 4702 <b><a NAME="RX_DFE2_EXT_STATUS2">RX_DFE2_EXT_STATUS2 - G3 status 2 register</a></b><br> 4703 Address Offset = 32'h0000_7202<br> 4704 Physical Address = 32'h0000_7202<br> 4705 Reset Value = 16'h0000<br> 4706 Access = RO (16-bit only)<br> 4707 <table border=1 align=center width=100% cellpadding=0> 4708 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4709 <tr bgcolor=WHITE> 4710 <td bgcolor=WHITE align=center valign=top>15:03</td> 4711 <td align=left valign=top>RSVD</td> 4712 <td align=left valign=top>Reserved</td> 4713 <td align=left> 4714 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4715 <tr bgcolor=WHITE> 4716 <td bgcolor=WHITE align=center valign=top>02</td> 4717 <td align=left valign=top>RO</td> 4718 <td align=left valign=top>rx_gbox_afrst</td> 4719 <td align=left> 4720 rx G3 gbox fifo autofifo reset has occured<br> 4721 0 = normal<br> 4722 1 = afrst<br> 4723 Reset value is 0.</td></tr> 4724 <tr bgcolor=WHITE> 4725 <td bgcolor=WHITE align=center valign=top>01</td> 4726 <td align=left valign=top>RO</td> 4727 <td align=left valign=top>rx_gbox_unflow</td> 4728 <td align=left> 4729 rx G3 gbox fifo underflow has occured<br> 4730 0 = normal<br> 4731 1 = underflow<br> 4732 Reset value is 0.</td></tr> 4733 <tr bgcolor=WHITE> 4734 <td bgcolor=WHITE align=center valign=top>00</td> 4735 <td align=left valign=top>RO</td> 4736 <td align=left valign=top>rx_gbox_ovflow</td> 4737 <td align=left> 4738 rx G3 gbox fifo overflow has occured<br> 4739 0 = normal<br> 4740 1 = overflow<br> 4741 Reset value is 0.</td></tr> 4742 </table><p> 4743 <A HREF="#RX_DFE2_EXT Registers">Return to RX_DFE2_EXT Table</A><p> 4744 <hr> 4745 <H1><a NAME="DSC_A Registers">DSC_A: per lane register block [One Copy Per Lane] Registers</a></H1> 4746 <table border=1 align=center width=100% cellpadding=0> 4747 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 4748 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 4749 <tr> 4750 <td align=center>0xD001</td><td><A HREF="#DSC_A_CDR_CONTROL_0">DSC_A_CDR_CONTROL_0</A><br>CDR Control 0</td><td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">cdr_lm_thr_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_freq_override_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_integ_sat_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_phase_err_frz</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_integ_reg_clr</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_freq_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">br_pd_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_phase_sat_ctrl</div> </td> <td align=center>16'h0004</td></tr> 4751 <tr> 4752 <td align=center>0xD002</td><td><A HREF="#DSC_A_CDR_CONTROL_1">DSC_A_CDR_CONTROL_1</A><br>CDR Control 1</td><td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">cdr_freq_override_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_vga_unfreeze</div> </td> <td align=center>16'h0690</td></tr> 4753 <tr> 4754 <td align=center>0xD003</td><td><A HREF="#DSC_A_CDR_CONTROL_2">DSC_A_CDR_CONTROL_2</A><br>CDR Control 2</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">osx2p_pherr_gain</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pattern_sel</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">phase_err_offset_mult_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_zero_polarity</div> </td> <td align=center>16'h00f0</td></tr> 4755 <tr> 4756 <td align=center>0xD004</td><td><A HREF="#DSC_A_RX_PI_CONTROL">DSC_A_RX_PI_CONTROL</A><br>RX PI control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pi_manual_reset</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rx_pi_slicers_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pi_manual_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pi_phase_step_dir</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pi_manual_strobe</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">rx_pi_phase_step_cnt</div> </td> <td align=center>16'h0000</td></tr> 4757 <tr> 4758 <td align=center>0xD005</td><td><A HREF="#DSC_A_CDR_STATUS_INTEG_REG">DSC_A_CDR_STATUS_INTEG_REG</A><br>CDR Status Integ Reg</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">cdr_integ_reg</div> </td> <td align=center>16'h0000</td></tr> 4759 <tr> 4760 <td align=center>0xD006</td><td><A HREF="#DSC_A_CDR_STATUS_PHASE_ERROR">DSC_A_CDR_STATUS_PHASE_ERROR</A><br>CDR Status phase err</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">cdr_phase_err</div> </td> <td align=center>16'h0000</td></tr> 4761 <tr> 4762 <td align=center>0xD007</td><td><A HREF="#DSC_A_RX_PI_CNT_BIN_D">DSC_A_RX_PI_CNT_BIN_D</A><br>Rx PI {P1, D}</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">cnt_bin_p1_dreg</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">cnt_bin_d_dreg</div> </td> <td align=center>16'h0000</td></tr> 4763 <tr> 4764 <td align=center>0xD008</td><td><A HREF="#DSC_A_RX_PI_CNT_BIN_P">DSC_A_RX_PI_CNT_BIN_P</A><br>Rx PI {M1, P1}</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">cnt_bin_m1_preg</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">cnt_bin_p1_preg</div> </td> <td align=center>16'h2000</td></tr> 4765 <tr> 4766 <td align=center>0xD009</td><td><A HREF="#DSC_A_RX_PI_CNT_BIN_M">DSC_A_RX_PI_CNT_BIN_M</A><br>Rx PI {D, M1}</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">cnt_bin_d_mreg</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">cnt_bin_m1_mreg</div> </td> <td align=center>16'h0020</td></tr> 4767 <tr> 4768 <td align=center>0xD00A</td><td><A HREF="#DSC_A_RX_PI_DIFF_BIN">DSC_A_RX_PI_DIFF_BIN</A><br>Rx PI {D-P1, D-M1}</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">cnt_d_minus_p1</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">cnt_d_minus_m1</div> </td> <td align=center>16'h0000</td></tr> 4769 <tr> 4770 <td align=center>0xD00B</td><td><A HREF="#DSC_A_TRNSUM_CNTL_5">DSC_A_TRNSUM_CNTL_5</A><br>training sum control 5</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">edge_count_refless_en</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">trnsum_eye_closure_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">swap_lms_data</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">swap_lms_m1</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">trnsum_prbs_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_eye_close_prev_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">trnsum_pattern_match_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_disable_sm_clear</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_clr_sc</div> </td> <td align=center>16'h0060</td></tr> 4771 <tr> 4772 <td align=center>0xD00D</td><td><A HREF="#DSC_A_DSC_UC_CTRL">DSC_A_DSC_UC_CTRL</A><br>DSC uC Control</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">uc_dsc_supp_info</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_dsc_ready_for_cmd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_dsc_error_found</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">uc_dsc_gp_uc_req</div> </td> <td align=center>16'h0000</td></tr> 4773 <tr> 4774 <td align=center>0xD00E</td><td><A HREF="#DSC_A_DSC_SCRATCH">DSC_A_DSC_SCRATCH</A><br>DSC uC Control</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">uc_dsc_data</div> </td> <td align=center>16'h0000</td></tr> 4775 </table><p> 4776 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 4777 <hr> 4778 <b><a NAME="DSC_A_CDR_CONTROL_0">DSC_A_CDR_CONTROL_0 - CDR Control 0</a></b><br> 4779 Address Offset = 32'h0000_d001<br> 4780 Physical Address = 32'h0000_d001<br> 4781 Reset Value = 16'h0004<br> 4782 Access = RW (16-bit only)<br> 4783 <table border=1 align=center width=100% cellpadding=0> 4784 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4785 <tr bgcolor=WHITE> 4786 <td bgcolor=WHITE align=center valign=top>15:11</td> 4787 <td align=left valign=top>RSVD</td> 4788 <td align=left valign=top>Reserved</td> 4789 <td align=left> 4790 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4791 <tr bgcolor=WHITE> 4792 <td bgcolor=WHITE align=center valign=top>10:08</td> 4793 <td align=left valign=top>RW</td> 4794 <td align=left valign=top>cdr_lm_thr_sel</td> 4795 <td align=left> 4796 cdr lock monitor looks for integ reg[15:6] to be within sat - (cdr_lm_thr_sel +1)*512 in magnitude <br> 4797 Reset value is 0x0.</td></tr> 4798 <tr bgcolor=WHITE> 4799 <td bgcolor=WHITE align=center valign=top>07</td> 4800 <td align=left valign=top>RW</td> 4801 <td align=left valign=top>cdr_freq_override_en</td> 4802 <td align=left> 4803 1:override integ register with cdr_freq_override_val  <br> 4804 Reset value is 0x0.</td></tr> 4805 <tr bgcolor=WHITE> 4806 <td bgcolor=WHITE align=center valign=top>06</td> 4807 <td align=left valign=top>RW</td> 4808 <td align=left valign=top>cdr_integ_sat_sel</td> 4809 <td align=left> 4810 0:(-24576, 24575), 1:(-16384, 16383)  <br> 4811 Reset value is 0x0.</td></tr> 4812 <tr bgcolor=WHITE> 4813 <td bgcolor=WHITE align=center valign=top>05</td> 4814 <td align=left valign=top>RW</td> 4815 <td align=left valign=top>cdr_phase_err_frz</td> 4816 <td align=left> 4817 1: override phase error to be 0  <br> 4818 Reset value is 0x0.</td></tr> 4819 <tr bgcolor=WHITE> 4820 <td bgcolor=WHITE align=center valign=top>04</td> 4821 <td align=left valign=top>RW</td> 4822 <td align=left valign=top>cdr_integ_reg_clr</td> 4823 <td align=left> 4824 clear integ register  <br> 4825 Reset value is 0x0.</td></tr> 4826 <tr bgcolor=WHITE> 4827 <td bgcolor=WHITE align=center valign=top>03</td> 4828 <td align=left valign=top>RSVD</td> 4829 <td align=left valign=top>Reserved</td> 4830 <td align=left> 4831 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 4832 <tr bgcolor=WHITE> 4833 <td bgcolor=WHITE align=center valign=top>02</td> 4834 <td align=left valign=top>RW</td> 4835 <td align=left valign=top>cdr_freq_en</td> 4836 <td align=left> 4837 1: 2nd order loop output to contribute  <br> 4838 Reset value is 0x1.</td></tr> 4839 <tr bgcolor=WHITE> 4840 <td bgcolor=WHITE align=center valign=top>01</td> 4841 <td align=left valign=top>RW</td> 4842 <td align=left valign=top>br_pd_en</td> 4843 <td align=left> 4844 Enables BR phase detector  <br> 4845 Reset value is 0x0.</td></tr> 4846 <tr bgcolor=WHITE> 4847 <td bgcolor=WHITE align=center valign=top>00</td> 4848 <td align=left valign=top>RW</td> 4849 <td align=left valign=top>cdr_phase_sat_ctrl</td> 4850 <td align=left> 4851 0:(+-12), 1:(+-10)  <br> 4852 Reset value is 0x0.</td></tr> 4853 </table><p> 4854 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 4855 <hr> 4856 <b><a NAME="DSC_A_CDR_CONTROL_1">DSC_A_CDR_CONTROL_1 - CDR Control 1</a></b><br> 4857 Address Offset = 32'h0000_d002<br> 4858 Physical Address = 32'h0000_d002<br> 4859 Reset Value = 16'h0690<br> 4860 Access = RW (16-bit only)<br> 4861 <table border=1 align=center width=100% cellpadding=0> 4862 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4863 <tr bgcolor=WHITE> 4864 <td bgcolor=WHITE align=center valign=top>15:01</td> 4865 <td align=left valign=top>RW</td> 4866 <td align=left valign=top>cdr_freq_override_val</td> 4867 <td align=left> 4868 Override value for the second order integrator. Initial value is +20ppm which gets loaded on reset <br> 4869 This value gets loaded into [15:1] indexes of the integ reg in the CDRs second order loop on reset. Value/42 is the approximate ppm forced. <br> 4870 Reset value is 0x348.</td></tr> 4871 <tr bgcolor=WHITE> 4872 <td bgcolor=WHITE align=center valign=top>00</td> 4873 <td align=left valign=top>RW</td> 4874 <td align=left valign=top>dfe_vga_unfreeze</td> 4875 <td align=left> 4876 When 1, the dfe and vga adaptive loops are unfrozen.  <br> 4877 Reset value is 0x0.</td></tr> 4878 </table><p> 4879 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 4880 <hr> 4881 <b><a NAME="DSC_A_CDR_CONTROL_2">DSC_A_CDR_CONTROL_2 - CDR Control 2</a></b><br> 4882 Address Offset = 32'h0000_d003<br> 4883 Physical Address = 32'h0000_d003<br> 4884 Reset Value = 16'h00f0<br> 4885 Access = RW (16-bit only)<br> 4886 <table border=1 align=center width=100% cellpadding=0> 4887 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4888 <tr bgcolor=WHITE> 4889 <td bgcolor=WHITE align=center valign=top>15:10</td> 4890 <td align=left valign=top>RSVD</td> 4891 <td align=left valign=top>Reserved</td> 4892 <td align=left> 4893 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4894 <tr bgcolor=WHITE> 4895 <td bgcolor=WHITE align=center valign=top>09:08</td> 4896 <td align=left valign=top>RW</td> 4897 <td align=left valign=top>osx2p_pherr_gain</td> 4898 <td align=left> 4899 in > osx2 modes, the phase error is multiplied by 2^{0,1,2,3} <br> 4900 Reset value is 0x0.</td></tr> 4901 <tr bgcolor=WHITE> 4902 <td bgcolor=WHITE align=center valign=top>07:04</td> 4903 <td align=left valign=top>RW</td> 4904 <td align=left valign=top>pattern_sel</td> 4905 <td align=left> 4906 CDR can be conditioned to operate on selected 3-bit data patterns.<br> 4907 Each bit of this register field enables a specified pattern.<br> 4908 In OS phase detector mode, pattern is specified by {2nd previous, previous, current bit}.<br> 4909 In  BR phase detector mode, pattern is specified by {previous, current, future bit}<br> 4910 Bit 0: 001<br> 4911 Bit 1: 110<br> 4912 Bit 2: 010 for OS modes, 011 for BR mode<br> 4913 Bit 3: 101 for OS modes, 100 for BR mode<br> 4914 For OSx3 and higher oversampling ratios, this feature is not supported, please leave it at reset value of 0xF. <br> 4915 Reset value is 0xf.</td></tr> 4916 <tr bgcolor=WHITE> 4917 <td bgcolor=WHITE align=center valign=top>03:02</td> 4918 <td align=left valign=top>RSVD</td> 4919 <td align=left valign=top>Reserved</td> 4920 <td align=left> 4921 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4922 <tr bgcolor=WHITE> 4923 <td bgcolor=WHITE align=center valign=top>01</td> 4924 <td align=left valign=top>RW</td> 4925 <td align=left valign=top>phase_err_offset_mult_2</td> 4926 <td align=left> 4927 Multiplies the phase error offset by 2  <br> 4928 Reset value is 0x0.</td></tr> 4929 <tr bgcolor=WHITE> 4930 <td bgcolor=WHITE align=center valign=top>00</td> 4931 <td align=left valign=top>RW</td> 4932 <td align=left valign=top>cdr_zero_polarity</td> 4933 <td align=left> 4934 inverts the edge sample (zero) information before the phase detector  <br> 4935 Reset value is 0x0.</td></tr> 4936 </table><p> 4937 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 4938 <hr> 4939 <b><a NAME="DSC_A_RX_PI_CONTROL">DSC_A_RX_PI_CONTROL - RX PI control</a></b><br> 4940 Address Offset = 32'h0000_d004<br> 4941 Physical Address = 32'h0000_d004<br> 4942 Reset Value = 16'h0000<br> 4943 Access = RW (16-bit only)<br> 4944 <table border=1 align=center width=100% cellpadding=0> 4945 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 4946 <tr bgcolor=WHITE> 4947 <td bgcolor=WHITE align=center valign=top>15</td> 4948 <td align=left valign=top>RW</td> 4949 <td align=left valign=top>rx_pi_manual_reset</td> 4950 <td align=left> 4951 active high reset signal which initializes the pi <br> 4952 Reset value is 0x0.</td></tr> 4953 <tr bgcolor=WHITE> 4954 <td bgcolor=WHITE align=center valign=top>14:12</td> 4955 <td align=left valign=top>RW</td> 4956 <td align=left valign=top>rx_pi_slicers_en</td> 4957 <td align=left> 4958 bit-vector representing which PI's to adjust: [0] d, [1] p1, [2] m1, <br> 4959 where [0][1][2] are index locations.  <br> 4960 Eg: if data and m1 slicers need to be moved set pi_slicers_en[2:0] to 3'b101 <br> 4961 Encoding: each index is an independent enable for the corresponding slicer. <br> 4962 Reset value is 0x0.</td></tr> 4963 <tr bgcolor=WHITE> 4964 <td bgcolor=WHITE align=center valign=top>11</td> 4965 <td align=left valign=top>RW</td> 4966 <td align=left valign=top>rx_pi_manual_mode</td> 4967 <td align=left> 4968 0: normal, 1:disconnect all PI's from CDR when enabled  <br> 4969 Reset value is 0x0.</td></tr> 4970 <tr bgcolor=WHITE> 4971 <td bgcolor=WHITE align=center valign=top>10</td> 4972 <td align=left valign=top>RW</td> 4973 <td align=left valign=top>rx_pi_phase_step_dir</td> 4974 <td align=left> 4975 0: left shift, 1: right shift  <br> 4976 Reset value is 0x0.</td></tr> 4977 <tr bgcolor=WHITE> 4978 <td bgcolor=WHITE align=center valign=top>09</td> 4979 <td align=left valign=top>SC</td> 4980 <td align=left valign=top>rx_pi_manual_strobe</td> 4981 <td align=left> 4982 strobe performs a manual override for a specified # of cycles (self clearing) <br> 4983 Reset value is 0x0.</td></tr> 4984 <tr bgcolor=WHITE> 4985 <td bgcolor=WHITE align=center valign=top>08:07</td> 4986 <td align=left valign=top>RSVD</td> 4987 <td align=left valign=top>Reserved</td> 4988 <td align=left> 4989 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 4990 <tr bgcolor=WHITE> 4991 <td bgcolor=WHITE align=center valign=top>06:00</td> 4992 <td align=left valign=top>RW</td> 4993 <td align=left valign=top>rx_pi_phase_step_cnt</td> 4994 <td align=left> 4995 # of steps to adjust  <br> 4996 Reset value is 0x0.</td></tr> 4997 </table><p> 4998 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 4999 <hr> 5000 <b><a NAME="DSC_A_CDR_STATUS_INTEG_REG">DSC_A_CDR_STATUS_INTEG_REG - CDR Status Integ Reg</a></b><br> 5001 Address Offset = 32'h0000_d005<br> 5002 Physical Address = 32'h0000_d005<br> 5003 Reset Value = 16'h0000<br> 5004 Access = RO (16-bit only)<br> 5005 <table border=1 align=center width=100% cellpadding=0> 5006 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5007 <tr bgcolor=WHITE> 5008 <td bgcolor=WHITE align=center valign=top>15:00</td> 5009 <td align=left valign=top>RO</td> 5010 <td align=left valign=top>cdr_integ_reg</td> 5011 <td align=left> 5012 CDR Integ register value. <br> 5013 The frequency offset in ppm can be derived from the cdr_integ_reg as follows: <br> 5014 cdr_integ_reg /83.886 in ppm <br> 5015 Reset value is 0x0.</td></tr> 5016 </table><p> 5017 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5018 <hr> 5019 <b><a NAME="DSC_A_CDR_STATUS_PHASE_ERROR">DSC_A_CDR_STATUS_PHASE_ERROR - CDR Status phase err</a></b><br> 5020 Address Offset = 32'h0000_d006<br> 5021 Physical Address = 32'h0000_d006<br> 5022 Reset Value = 16'h0000<br> 5023 Access = RO (16-bit only)<br> 5024 <table border=1 align=center width=100% cellpadding=0> 5025 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5026 <tr bgcolor=WHITE> 5027 <td bgcolor=WHITE align=center valign=top>15:06</td> 5028 <td align=left valign=top>RSVD</td> 5029 <td align=left valign=top>Reserved</td> 5030 <td align=left> 5031 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5032 <tr bgcolor=WHITE> 5033 <td bgcolor=WHITE align=center valign=top>05:00</td> 5034 <td align=left valign=top>RO</td> 5035 <td align=left valign=top>cdr_phase_err</td> 5036 <td align=left> 5037 CDR Phase Error value (post gain, saturation , freeze logic)  <br> 5038 Reset value is 0x0.</td></tr> 5039 </table><p> 5040 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5041 <hr> 5042 <b><a NAME="DSC_A_RX_PI_CNT_BIN_D">DSC_A_RX_PI_CNT_BIN_D - Rx PI {P1, D}</a></b><br> 5043 Address Offset = 32'h0000_d007<br> 5044 Physical Address = 32'h0000_d007<br> 5045 Reset Value = 16'h0000<br> 5046 Access = RO (16-bit only)<br> 5047 <table border=1 align=center width=100% cellpadding=0> 5048 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5049 <tr bgcolor=WHITE> 5050 <td bgcolor=WHITE align=center valign=top>15</td> 5051 <td align=left valign=top>RSVD</td> 5052 <td align=left valign=top>Reserved</td> 5053 <td align=left> 5054 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5055 <tr bgcolor=WHITE> 5056 <td bgcolor=WHITE align=center valign=top>14:08</td> 5057 <td align=left valign=top>RO</td> 5058 <td align=left valign=top>cnt_bin_p1_dreg</td> 5059 <td align=left> 5060 Slicer P1 location  <br> 5061 This read is duplicated here, so that the entire 15 bits if read at a time,  <br> 5062 the difference between d and p1 can be calculated, which is not possible with single reads without freezing the CDR  <br> 5063 Reset value is 0x0.</td></tr> 5064 <tr bgcolor=WHITE> 5065 <td bgcolor=WHITE align=center valign=top>07</td> 5066 <td align=left valign=top>RSVD</td> 5067 <td align=left valign=top>Reserved</td> 5068 <td align=left> 5069 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5070 <tr bgcolor=WHITE> 5071 <td bgcolor=WHITE align=center valign=top>06:00</td> 5072 <td align=left valign=top>RO</td> 5073 <td align=left valign=top>cnt_bin_d_dreg</td> 5074 <td align=left> 5075 Slicer D location  <br> 5076 Reset value is 0x0.</td></tr> 5077 </table><p> 5078 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5079 <hr> 5080 <b><a NAME="DSC_A_RX_PI_CNT_BIN_P">DSC_A_RX_PI_CNT_BIN_P - Rx PI {M1, P1}</a></b><br> 5081 Address Offset = 32'h0000_d008<br> 5082 Physical Address = 32'h0000_d008<br> 5083 Reset Value = 16'h2000<br> 5084 Access = RO (16-bit only)<br> 5085 <table border=1 align=center width=100% cellpadding=0> 5086 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5087 <tr bgcolor=WHITE> 5088 <td bgcolor=WHITE align=center valign=top>15</td> 5089 <td align=left valign=top>RSVD</td> 5090 <td align=left valign=top>Reserved</td> 5091 <td align=left> 5092 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5093 <tr bgcolor=WHITE> 5094 <td bgcolor=WHITE align=center valign=top>14:08</td> 5095 <td align=left valign=top>RO</td> 5096 <td align=left valign=top>cnt_bin_m1_preg</td> 5097 <td align=left> 5098 Slicer M1 location  <br> 5099 See note for cnt_bin_p1_dreg in rx_pi_cnt_bin_d  <br> 5100 Reset value is 0x20.</td></tr> 5101 <tr bgcolor=WHITE> 5102 <td bgcolor=WHITE align=center valign=top>07</td> 5103 <td align=left valign=top>RSVD</td> 5104 <td align=left valign=top>Reserved</td> 5105 <td align=left> 5106 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5107 <tr bgcolor=WHITE> 5108 <td bgcolor=WHITE align=center valign=top>06:00</td> 5109 <td align=left valign=top>RO</td> 5110 <td align=left valign=top>cnt_bin_p1_preg</td> 5111 <td align=left> 5112 Slicer P1 location  <br> 5113 Reset value is 0x0.</td></tr> 5114 </table><p> 5115 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5116 <hr> 5117 <b><a NAME="DSC_A_RX_PI_CNT_BIN_M">DSC_A_RX_PI_CNT_BIN_M - Rx PI {D, M1}</a></b><br> 5118 Address Offset = 32'h0000_d009<br> 5119 Physical Address = 32'h0000_d009<br> 5120 Reset Value = 16'h0020<br> 5121 Access = RO (16-bit only)<br> 5122 <table border=1 align=center width=100% cellpadding=0> 5123 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5124 <tr bgcolor=WHITE> 5125 <td bgcolor=WHITE align=center valign=top>15</td> 5126 <td align=left valign=top>RSVD</td> 5127 <td align=left valign=top>Reserved</td> 5128 <td align=left> 5129 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5130 <tr bgcolor=WHITE> 5131 <td bgcolor=WHITE align=center valign=top>14:08</td> 5132 <td align=left valign=top>RO</td> 5133 <td align=left valign=top>cnt_bin_d_mreg</td> 5134 <td align=left> 5135 Slicer D location  <br> 5136 See note for cnt_bin_p1_dreg in rx_pi_cnt_bin_d  <br> 5137 Reset value is 0x0.</td></tr> 5138 <tr bgcolor=WHITE> 5139 <td bgcolor=WHITE align=center valign=top>07</td> 5140 <td align=left valign=top>RSVD</td> 5141 <td align=left valign=top>Reserved</td> 5142 <td align=left> 5143 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5144 <tr bgcolor=WHITE> 5145 <td bgcolor=WHITE align=center valign=top>06:00</td> 5146 <td align=left valign=top>RO</td> 5147 <td align=left valign=top>cnt_bin_m1_mreg</td> 5148 <td align=left> 5149 Slicer M1 location  <br> 5150 Reset value is 0x20.</td></tr> 5151 </table><p> 5152 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5153 <hr> 5154 <b><a NAME="DSC_A_RX_PI_DIFF_BIN">DSC_A_RX_PI_DIFF_BIN - Rx PI {D-P1, D-M1}</a></b><br> 5155 Address Offset = 32'h0000_d00a<br> 5156 Physical Address = 32'h0000_d00a<br> 5157 Reset Value = 16'h0000<br> 5158 Access = RO (16-bit only)<br> 5159 <table border=1 align=center width=100% cellpadding=0> 5160 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5161 <tr bgcolor=WHITE> 5162 <td bgcolor=WHITE align=center valign=top>15:08</td> 5163 <td align=left valign=top>RO</td> 5164 <td align=left valign=top>cnt_d_minus_p1</td> 5165 <td align=left> 5166 Slicer D minus P1  <br> 5167 Reset value is 0x0.</td></tr> 5168 <tr bgcolor=WHITE> 5169 <td bgcolor=WHITE align=center valign=top>07:00</td> 5170 <td align=left valign=top>RO</td> 5171 <td align=left valign=top>cnt_d_minus_m1</td> 5172 <td align=left> 5173 Slicer D minus M1  <br> 5174 Reset value is 0x0.</td></tr> 5175 </table><p> 5176 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5177 <hr> 5178 <b><a NAME="DSC_A_TRNSUM_CNTL_5">DSC_A_TRNSUM_CNTL_5 - training sum control 5</a></b><br> 5179 Address Offset = 32'h0000_d00b<br> 5180 Physical Address = 32'h0000_d00b<br> 5181 Reset Value = 16'h0060<br> 5182 Access = RW (16-bit only)<br> 5183 <table border=1 align=center width=100% cellpadding=0> 5184 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5185 <tr bgcolor=WHITE> 5186 <td bgcolor=WHITE align=center valign=top>15</td> 5187 <td align=left valign=top>RW</td> 5188 <td align=left valign=top>edge_count_refless_en</td> 5189 <td align=left> 5190 When 1 this enables the edge counter. The edge counter assumes that the slicers are spaced 1/3rd UI apart. The trnsum accumulators accumulate the edge 5191 information. The even tap accumulates edges counted by 30 samples and odd accumulates the other 30. Math: 60 samples from 3 slicers in a rclk20 cycle. 5192 Max possible edges in 30 samples is <=11 <br> 5193 Reset value is 0x0.</td></tr> 5194 <tr bgcolor=WHITE> 5195 <td bgcolor=WHITE align=center valign=top>14</td> 5196 <td align=left valign=top>RSVD</td> 5197 <td align=left valign=top>Reserved</td> 5198 <td align=left> 5199 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5200 <tr bgcolor=WHITE> 5201 <td bgcolor=WHITE align=center valign=top>13:12</td> 5202 <td align=left valign=top>RW</td> 5203 <td align=left valign=top>trnsum_eye_closure_err_sel</td> 5204 <td align=left> 5205 When trnsum_eye_closure_en is set, this field determines what is compared against d slicer. d!=error_selected , where error_selected is:<br> 5206 2'b00: emux<br> 5207 2'b01: m1<br> 5208 2'b10: p1<br> 5209 2'b11: expected prbs. The expected prbs needs the CDR to slip by pipeline_diff-2 bits. The pipeline_diff is the difference in the data coming to the trnsum 5210 vs the expected prbs bits coming from the prbs checker logic. The (-2) comes from the fact that the trnsum operates on a 2 bit shifted data per cycle to 5211 be able to 'look into the future'.  <br> 5212 Reset value is 0x0.</td></tr> 5213 <tr bgcolor=WHITE> 5214 <td bgcolor=WHITE align=center valign=top>11</td> 5215 <td align=left valign=top>RW</td> 5216 <td align=left valign=top>swap_lms_data</td> 5217 <td align=left> 5218 When set the d and p1 slicers from the AFE, get swapped for all down-stream logic.<br> 5219 Reset value is 0x0.</td></tr> 5220 <tr bgcolor=WHITE> 5221 <td bgcolor=WHITE align=center valign=top>10</td> 5222 <td align=left valign=top>RW</td> 5223 <td align=left valign=top>swap_lms_m1</td> 5224 <td align=left> 5225 When set the m1 and p1 slicers from the AFE, get swapped for all down-stream logic. Lower priority than swap_lms_data.<br> 5226 Reset value is 0x0.</td></tr> 5227 <tr bgcolor=WHITE> 5228 <td bgcolor=WHITE align=center valign=top>09:07</td> 5229 <td align=left valign=top>RSVD</td> 5230 <td align=left valign=top>Reserved</td> 5231 <td align=left> 5232 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5233 <tr bgcolor=WHITE> 5234 <td bgcolor=WHITE align=center valign=top>06:05</td> 5235 <td align=left valign=top>RW</td> 5236 <td align=left valign=top>trnsum_prbs_sel</td> 5237 <td align=left> 5238 0: 2'b00, 0 is sent to the prbs accumulator <br> 5239 1: 2'b01, odd trnsum is sent to the prbs acc <br> 5240 2: 2'b10, even trnsum is sent to the prbs acc <br> 5241 3: 2'b11, both are summed and sent to the prbs acc<br> 5242 Reset value is 0x3.</td></tr> 5243 <tr bgcolor=WHITE> 5244 <td bgcolor=WHITE align=center valign=top>04</td> 5245 <td align=left valign=top>RW</td> 5246 <td align=left valign=top>trnsum_eye_close_prev_en</td> 5247 <td align=left> 5248 When 1, the first eye close event after previous 6 non-eye closure events is picked. The eye close condition settings need to be turned on for this setting 5249 to work.<br> 5250 Reset value is 0x0.</td></tr> 5251 <tr bgcolor=WHITE> 5252 <td bgcolor=WHITE align=center valign=top>03:02</td> 5253 <td align=left valign=top>RW</td> 5254 <td align=left valign=top>trnsum_pattern_match_sel</td> 5255 <td align=left> 5256 0, 3: pattern matching on rx_data<br> 5257     1: pattern matching on m1err<br> 5258     2: pattern matching on expected prbs data<br> 5259 Reset value is 0x0.</td></tr> 5260 <tr bgcolor=WHITE> 5261 <td bgcolor=WHITE align=center valign=top>01</td> 5262 <td align=left valign=top>RW</td> 5263 <td align=left valign=top>trnsum_disable_sm_clear</td> 5264 <td align=left> 5265 When asserted,a pulse on uc_trnsum_en no longer clears the accumulator. <br> 5266 Reset value is 0x0.</td></tr> 5267 <tr bgcolor=WHITE> 5268 <td bgcolor=WHITE align=center valign=top>00</td> 5269 <td align=left valign=top>SC</td> 5270 <td align=left valign=top>trnsum_clr_sc</td> 5271 <td align=left> 5272 Self Clearing bit <br> 5273 When asserted, the trnsum accumulator clears. <br> 5274 Reset value is 0x0.</td></tr> 5275 </table><p> 5276 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5277 <hr> 5278 <b><a NAME="DSC_A_DSC_UC_CTRL">DSC_A_DSC_UC_CTRL - DSC uC Control</a></b><br> 5279 Address Offset = 32'h0000_d00d<br> 5280 Physical Address = 32'h0000_d00d<br> 5281 Reset Value = 16'h0000<br> 5282 Access = RW (16-bit only)<br> 5283 <table border=1 align=center width=100% cellpadding=0> 5284 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5285 <tr bgcolor=WHITE> 5286 <td bgcolor=WHITE align=center valign=top>15:08</td> 5287 <td align=left valign=top>RW</td> 5288 <td align=left valign=top>uc_dsc_supp_info</td> 5289 <td align=left> 5290 Supplemental information. <br> 5291 Reset value is 0x0.</td></tr> 5292 <tr bgcolor=WHITE> 5293 <td bgcolor=WHITE align=center valign=top>07</td> 5294 <td align=left valign=top>RW</td> 5295 <td align=left valign=top>uc_dsc_ready_for_cmd</td> 5296 <td align=left> 5297 Ready for command. <br> 5298 Reset value is 0x0.</td></tr> 5299 <tr bgcolor=WHITE> 5300 <td bgcolor=WHITE align=center valign=top>06</td> 5301 <td align=left valign=top>RW</td> 5302 <td align=left valign=top>uc_dsc_error_found</td> 5303 <td align=left> 5304 Error Found. <br> 5305 Reset value is 0x0.</td></tr> 5306 <tr bgcolor=WHITE> 5307 <td bgcolor=WHITE align=center valign=top>05:00</td> 5308 <td align=left valign=top>RW</td> 5309 <td align=left valign=top>uc_dsc_gp_uc_req</td> 5310 <td align=left> 5311 gp_uc request <br> 5312 Reset value is 0x0.</td></tr> 5313 </table><p> 5314 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5315 <hr> 5316 <b><a NAME="DSC_A_DSC_SCRATCH">DSC_A_DSC_SCRATCH - DSC uC Control</a></b><br> 5317 Address Offset = 32'h0000_d00e<br> 5318 Physical Address = 32'h0000_d00e<br> 5319 Reset Value = 16'h0000<br> 5320 Access = RW (16-bit only)<br> 5321 <table border=1 align=center width=100% cellpadding=0> 5322 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5323 <tr bgcolor=WHITE> 5324 <td bgcolor=WHITE align=center valign=top>15:00</td> 5325 <td align=left valign=top>RW</td> 5326 <td align=left valign=top>uc_dsc_data</td> 5327 <td align=left> 5328 Generic data word to exchange info with micro controller.<br> 5329 Reset value is 0x0.</td></tr> 5330 </table><p> 5331 <A HREF="#DSC_A Registers">Return to DSC_A: per lane register block [One Copy Per Lane] Table</A><p> 5332 <hr> 5333 <H1><a NAME="DSC_B Registers">DSC_B: per lane register block [One Copy Per Lane] Registers</a></H1> 5334 <table border=1 align=center width=100% cellpadding=0> 5335 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 5336 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 5337 <tr> 5338 <td align=center>0xD010</td><td><A HREF="#DSC_B_DSC_SM_CTRL_0">DSC_B_DSC_SM_CTRL_0</A><br>DSC STATE MACHINE CONTROL 0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">set_meas_incomplete</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_dsc_config</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_dsc_restart</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_dsc_eee_done</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">slicer_cal_bypass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">slicer_cal_done_clear</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eee_measure_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_trnsum_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_tune_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_tune_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cl72_timer_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ignore_rx_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eee_quiet_rx_afe_pwrdwn_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eee_mode_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_facq_ack</div> </td> <td align=center>16'h0008</td></tr> 5339 <tr> 5340 <td align=center>0xD011</td><td><A HREF="#DSC_B_DSC_SM_CTRL_1">DSC_B_DSC_SM_CTRL_1</A><br>DSC STATE MACHINE CONTROL 1</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_clr_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_clr_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_frz_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_frz_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">freq_upd_en_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">freq_upd_en_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">timer_done_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">timer_done_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_frz_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_frz_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_clr_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_clr_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_dsc_lock_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_dsc_lock_frc</div> </td> <td align=center>16'h0200</td></tr> 5341 <tr> 5342 <td align=center>0xD012</td><td><A HREF="#DSC_B_DSC_SM_CTRL_2">DSC_B_DSC_SM_CTRL_2</A><br>DSC STATE MACHINE CONTROL 2</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">eee_lfsr_cnt</div> </td> <td align=center>16'h0087</td></tr> 5343 <tr> 5344 <td align=center>0xD013</td><td><A HREF="#DSC_B_DSC_SM_CTRL_3">DSC_B_DSC_SM_CTRL_3</A><br>DSC STATE MACHINE CONTROL 3</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">measure_lfsr_cnt</div> </td> <td align=center>16'h1c1e</td></tr> 5345 <tr> 5346 <td align=center>0xD014</td><td><A HREF="#DSC_B_DSC_SM_CTRL_4">DSC_B_DSC_SM_CTRL_4</A><br>DSC STATE MACHINE CONTROL 4</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">hw_tune_timeout</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">cdr_settle_timeout</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">acq_cdr_timeout</div> </td> <td align=center>16'h35ad</td></tr> 5347 <tr> 5348 <td align=center>0xD015</td><td><A HREF="#DSC_B_DSC_SM_CTRL_5">DSC_B_DSC_SM_CTRL_5</A><br>DSC STATE MACHINE CONTROL 5</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">eee_cdr_settle_timeout</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">eee_acq_cdr_timeout</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">measure_timeout</div> </td> <td align=center>16'h35ad</td></tr> 5349 <tr> 5350 <td align=center>0xD016</td><td><A HREF="#DSC_B_DSC_SM_CTRL_6">DSC_B_DSC_SM_CTRL_6</A><br>DSC STATE MACHINE CONTROL 6</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">eee_ana_pwr_timeout</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">slicer_cal_timeout</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">eee_hw_tune_timeout</div> </td> <td align=center>16'h340d</td></tr> 5351 <tr> 5352 <td align=center>0xD017</td><td><A HREF="#DSC_B_DSC_SM_CTRL_7">DSC_B_DSC_SM_CTRL_7</A><br>DSC STATE MACHINE CONTROL 7</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_norm</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_acqcdr</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_norm</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_eee_acqcdr</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_acqcdr</div> </td> <td align=center>16'h0000</td></tr> 5353 <tr> 5354 <td align=center>0xD018</td><td><A HREF="#DSC_B_DSC_SM_CTRL_8">DSC_B_DSC_SM_CTRL_8</A><br>DSC STATE MACHINE CONTROL 8</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_eee_acqcdr</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">eee_phase_err_offset_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">phase_err_offset_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">eee_phase_err_offset</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">phase_err_offset</div> </td> <td align=center>16'h0011</td></tr> 5355 <tr> 5356 <td align=center>0xD019</td><td><A HREF="#DSC_B_DSC_SM_CTRL_9">DSC_B_DSC_SM_CTRL_9</A><br>DSC STATE MACHINE CONTROL 9</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dcoff_cal_timeout</div> </td> <td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_restart_pmd_hold</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_restart_pmd</div> </td> <td align=center>16'h0000</td></tr> 5357 <tr> 5358 <td align=center>0xD01A</td><td><A HREF="#DSC_B_DSC_SM_STATUS_DSC_LOCK">DSC_B_DSC_SM_STATUS_DSC_LOCK</A><br>DSC STATE MACHINE DSC_LOCK STATUS</td><td bgcolor=#FFFFFF align=center colspan="9"><div class="HT">eee_measure_cnt</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">slicer_cal_done</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">meas_incomplete</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_dsc_lock</div> </td> <td align=center>16'h0000</td></tr> 5359 <tr> 5360 <td align=center>0xD01B</td><td><A HREF="#DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0">DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0</A><br>DSC STATE MACHINE STATUS ONE HOT</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">dsc_state_one_hot_0</div> </td> <td align=center>16'h0000</td></tr> 5361 <tr> 5362 <td align=center>0xD01C</td><td><A HREF="#DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1">DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1</A><br>DSC STATE MACHINE STATUS ONE HOT</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dsc_state_one_hot_1</div> </td> <td align=center>16'h0000</td></tr> 5363 <tr> 5364 <td align=center>0xD01D</td><td><A HREF="#DSC_B_DSC_SM_STATUS_RESTART">DSC_B_DSC_SM_STATUS_RESTART</A><br>DSC STATE MACHINE STATUS RESTART</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eee_quiet_from_eee_states</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">restart_pmd_restart</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">restart_sigdet</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">restart_pi_ext_mode</div> </td> <td align=center>16'h0000</td></tr> 5365 <tr> 5366 <td align=center>0xD01E</td><td><A HREF="#DSC_B_DSC_SM_STATUS_DSC_STATE">DSC_B_DSC_SM_STATUS_DSC_STATE</A><br>DSC STATE MACHINE STATUS</td><td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dsc_state</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dsc_sm_scratch</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_sm_ready_for_cmd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_lm_outoflock</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">dsc_sm_gp_uc_req</div> </td> <td align=center>16'h0040</td></tr> 5367 </table><p> 5368 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 5369 <hr> 5370 <b><a NAME="DSC_B_DSC_SM_CTRL_0">DSC_B_DSC_SM_CTRL_0 - DSC STATE MACHINE CONTROL 0</a></b><br> 5371 Address Offset = 32'h0000_d010<br> 5372 Physical Address = 32'h0000_d010<br> 5373 Reset Value = 16'h0008<br> 5374 Access = RW (16-bit only)<br> 5375 <table border=1 align=center width=100% cellpadding=0> 5376 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5377 <tr bgcolor=WHITE> 5378 <td bgcolor=WHITE align=center valign=top>15</td> 5379 <td align=left valign=top>SC</td> 5380 <td align=left valign=top>set_meas_incomplete</td> 5381 <td align=left> 5382 1'b1 will force meas_incomplete to be 1'b1 to start a new measurement in EEE mode. This is a self-clear bit. <br> 5383 Reset value is 0x0.</td></tr> 5384 <tr bgcolor=WHITE> 5385 <td bgcolor=WHITE align=center valign=top>14</td> 5386 <td align=left valign=top>SC</td> 5387 <td align=left valign=top>uc_ack_dsc_config</td> 5388 <td align=left> 5389 1'b1 will enable the CONFIG to WAIT_FOR_SIG transition. This is a self-clear bit. <br> 5390 Reset value is 0x0.</td></tr> 5391 <tr bgcolor=WHITE> 5392 <td bgcolor=WHITE align=center valign=top>13</td> 5393 <td align=left valign=top>SC</td> 5394 <td align=left valign=top>uc_ack_dsc_restart</td> 5395 <td align=left> 5396 1'b1 will enable the RESTART to CONFIG transition. This is a self-clear bit. <br> 5397 Reset value is 0x0.</td></tr> 5398 <tr bgcolor=WHITE> 5399 <td bgcolor=WHITE align=center valign=top>12</td> 5400 <td align=left valign=top>RSVD</td> 5401 <td align=left valign=top>Reserved</td> 5402 <td align=left> 5403 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5404 <tr bgcolor=WHITE> 5405 <td bgcolor=WHITE align=center valign=top>11</td> 5406 <td align=left valign=top>SC</td> 5407 <td align=left valign=top>uc_ack_dsc_eee_done</td> 5408 <td align=left> 5409 1'b1 will enable the EEE_DONE to DONE transition. This is a self-clear bit. <br> 5410 Reset value is 0x0.</td></tr> 5411 <tr bgcolor=WHITE> 5412 <td bgcolor=WHITE align=center valign=top>10</td> 5413 <td align=left valign=top>RW</td> 5414 <td align=left valign=top>slicer_cal_bypass</td> 5415 <td align=left> 5416 1'b1 will bypass the SLICER_CAL state. <br> 5417 Reset value is 0x0.</td></tr> 5418 <tr bgcolor=WHITE> 5419 <td bgcolor=WHITE align=center valign=top>09</td> 5420 <td align=left valign=top>SC</td> 5421 <td align=left valign=top>slicer_cal_done_clear</td> 5422 <td align=left> 5423 1'b1 will clear the slicer_cal_done status register to 1'b0. This is a self-clear bit. <br> 5424 Reset value is 0x0.</td></tr> 5425 <tr bgcolor=WHITE> 5426 <td bgcolor=WHITE align=center valign=top>08</td> 5427 <td align=left valign=top>RW</td> 5428 <td align=left valign=top>eee_measure_en</td> 5429 <td align=left> 5430 1'b1 Enables the measurement during EEE_MEASURE.  <br> 5431 Reset value is 0x0.</td></tr> 5432 <tr bgcolor=WHITE> 5433 <td bgcolor=WHITE align=center valign=top>07</td> 5434 <td align=left valign=top>SC</td> 5435 <td align=left valign=top>uc_trnsum_en</td> 5436 <td align=left> 5437 1'b1 will move the state from UC_TUNE to MEASURE. This is a self-clear register bit. <br> 5438 Reset value is 0x0.</td></tr> 5439 <tr bgcolor=WHITE> 5440 <td bgcolor=WHITE align=center valign=top>06</td> 5441 <td align=left valign=top>SC</td> 5442 <td align=left valign=top>hw_tune_en</td> 5443 <td align=left> 5444 Should be 1'b1 along with uc_tune_en==1'b1 to move from UC_TUNE to HW_TUNE state.  This is a self-clear register bit. <br> 5445 Reset value is 0x0.</td></tr> 5446 <tr bgcolor=WHITE> 5447 <td bgcolor=WHITE align=center valign=top>05</td> 5448 <td align=left valign=top>RW</td> 5449 <td align=left valign=top>uc_tune_en</td> 5450 <td align=left> 5451 uc_tune_en is used to move in and out of UC_TUNE state. Look for DSC SM state diagram for more details.<br> 5452 Reset value is 0x0.</td></tr> 5453 <tr bgcolor=WHITE> 5454 <td bgcolor=WHITE align=center valign=top>04</td> 5455 <td align=left valign=top>RW</td> 5456 <td align=left valign=top>cl72_timer_en</td> 5457 <td align=left> 5458 If enabled to 1'b1 then LFSR is loaded with 0x01CD else it is loaded with 0x1C1E for all non-EEE and non-MEASURE states.<br> 5459 Reset value is 0x0.</td></tr> 5460 <tr bgcolor=WHITE> 5461 <td bgcolor=WHITE align=center valign=top>03</td> 5462 <td align=left valign=top>RW</td> 5463 <td align=left valign=top>ignore_rx_mode</td> 5464 <td align=left> 5465 If set to 1'b1 then pmd_rx_mode input will be ignored in DSC SM. <br> 5466 Reset value is 0x1.</td></tr> 5467 <tr bgcolor=WHITE> 5468 <td bgcolor=WHITE align=center valign=top>02</td> 5469 <td align=left valign=top>RW</td> 5470 <td align=left valign=top>eee_quiet_rx_afe_pwrdwn_val</td> 5471 <td align=left> 5472 1'b1 will enable the RX AFE powerdown in EEE_QUIET mode. <br> 5473 Reset value is 0x0.</td></tr> 5474 <tr bgcolor=WHITE> 5475 <td bgcolor=WHITE align=center valign=top>01</td> 5476 <td align=left valign=top>RW</td> 5477 <td align=left valign=top>eee_mode_en</td> 5478 <td align=left> 5479 1'b1 will enable the EEE mode. <br> 5480 Reset value is 0x0.</td></tr> 5481 <tr bgcolor=WHITE> 5482 <td bgcolor=WHITE align=center valign=top>00</td> 5483 <td align=left valign=top>SC</td> 5484 <td align=left valign=top>uc_facq_ack</td> 5485 <td align=left> 5486 uc_facq_ack is used to move out of FACQ_DONE state. Look for DSC SM state diagram for more details. <br> 5487 Reset value is 0x0.</td></tr> 5488 </table><p> 5489 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5490 <hr> 5491 <b><a NAME="DSC_B_DSC_SM_CTRL_1">DSC_B_DSC_SM_CTRL_1 - DSC STATE MACHINE CONTROL 1</a></b><br> 5492 Address Offset = 32'h0000_d011<br> 5493 Physical Address = 32'h0000_d011<br> 5494 Reset Value = 16'h0200<br> 5495 Access = RW (16-bit only)<br> 5496 <table border=1 align=center width=100% cellpadding=0> 5497 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5498 <tr bgcolor=WHITE> 5499 <td bgcolor=WHITE align=center valign=top>15:14</td> 5500 <td align=left valign=top>RSVD</td> 5501 <td align=left valign=top>Reserved</td> 5502 <td align=left> 5503 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5504 <tr bgcolor=WHITE> 5505 <td bgcolor=WHITE align=center valign=top>13</td> 5506 <td align=left valign=top>RW</td> 5507 <td align=left valign=top>trnsum_clr_frc_val</td> 5508 <td align=left> 5509 raining Sum freeze force value. <br> 5510 Reset value is 0x0.</td></tr> 5511 <tr bgcolor=WHITE> 5512 <td bgcolor=WHITE align=center valign=top>12</td> 5513 <td align=left valign=top>RW</td> 5514 <td align=left valign=top>trnsum_clr_frc</td> 5515 <td align=left> 5516 Training Sum freeze force. <br> 5517 Reset value is 0x0.</td></tr> 5518 <tr bgcolor=WHITE> 5519 <td bgcolor=WHITE align=center valign=top>11</td> 5520 <td align=left valign=top>RW</td> 5521 <td align=left valign=top>cdr_frz_frc_val</td> 5522 <td align=left> 5523 CDR Freeze force value. <br> 5524 Reset value is 0x0.</td></tr> 5525 <tr bgcolor=WHITE> 5526 <td bgcolor=WHITE align=center valign=top>10</td> 5527 <td align=left valign=top>RW</td> 5528 <td align=left valign=top>cdr_frz_frc</td> 5529 <td align=left> 5530 CDR Freeze force. <br> 5531 Reset value is 0x0.</td></tr> 5532 <tr bgcolor=WHITE> 5533 <td bgcolor=WHITE align=center valign=top>09</td> 5534 <td align=left valign=top>RW</td> 5535 <td align=left valign=top>freq_upd_en_frc_val</td> 5536 <td align=left> 5537 Frequency update force value. <br> 5538 Reset value is 0x1.</td></tr> 5539 <tr bgcolor=WHITE> 5540 <td bgcolor=WHITE align=center valign=top>08</td> 5541 <td align=left valign=top>RW</td> 5542 <td align=left valign=top>freq_upd_en_frc</td> 5543 <td align=left> 5544 Frequency update force. <br> 5545 Reset value is 0x0.</td></tr> 5546 <tr bgcolor=WHITE> 5547 <td bgcolor=WHITE align=center valign=top>07</td> 5548 <td align=left valign=top>RW</td> 5549 <td align=left valign=top>timer_done_frc_val</td> 5550 <td align=left> 5551 If timer_done_frc is set to 1'b1 and DSC SM is in HW_TUNE or MEASURE states then setting this bit to 1 will move the state to next state. <br> 5552 Reset value is 0x0.</td></tr> 5553 <tr bgcolor=WHITE> 5554 <td bgcolor=WHITE align=center valign=top>06</td> 5555 <td align=left valign=top>RW</td> 5556 <td align=left valign=top>timer_done_frc</td> 5557 <td align=left> 5558 Can be forced to 1'b1 which will disable the H/W timer in HW_TUNE and MEASURE states.<br> 5559 Reset value is 0x0.</td></tr> 5560 <tr bgcolor=WHITE> 5561 <td bgcolor=WHITE align=center valign=top>05</td> 5562 <td align=left valign=top>RW</td> 5563 <td align=left valign=top>trnsum_frz_frc_val</td> 5564 <td align=left> 5565 Training Sum freeze force value. <br> 5566 Reset value is 0x0.</td></tr> 5567 <tr bgcolor=WHITE> 5568 <td bgcolor=WHITE align=center valign=top>04</td> 5569 <td align=left valign=top>RW</td> 5570 <td align=left valign=top>trnsum_frz_frc</td> 5571 <td align=left> 5572 Training Sum freeze force. <br> 5573 Reset value is 0x0.</td></tr> 5574 <tr bgcolor=WHITE> 5575 <td bgcolor=WHITE align=center valign=top>03</td> 5576 <td align=left valign=top>RW</td> 5577 <td align=left valign=top>dsc_clr_frc_val</td> 5578 <td align=left> 5579 DSC clear force value. <br> 5580 Reset value is 0x0.</td></tr> 5581 <tr bgcolor=WHITE> 5582 <td bgcolor=WHITE align=center valign=top>02</td> 5583 <td align=left valign=top>RW</td> 5584 <td align=left valign=top>dsc_clr_frc</td> 5585 <td align=left> 5586 DSC clear force. <br> 5587 Reset value is 0x0.</td></tr> 5588 <tr bgcolor=WHITE> 5589 <td bgcolor=WHITE align=center valign=top>01</td> 5590 <td align=left valign=top>RW</td> 5591 <td align=left valign=top>rx_dsc_lock_frc_val</td> 5592 <td align=left> 5593 rx_dsc_lock force value. <br> 5594 Reset value is 0x0.</td></tr> 5595 <tr bgcolor=WHITE> 5596 <td bgcolor=WHITE align=center valign=top>00</td> 5597 <td align=left valign=top>RW</td> 5598 <td align=left valign=top>rx_dsc_lock_frc</td> 5599 <td align=left> 5600 rx_dsc_lock force. <br> 5601 Reset value is 0x0.</td></tr> 5602 </table><p> 5603 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5604 <hr> 5605 <b><a NAME="DSC_B_DSC_SM_CTRL_2">DSC_B_DSC_SM_CTRL_2 - DSC STATE MACHINE CONTROL 2</a></b><br> 5606 Address Offset = 32'h0000_d012<br> 5607 Physical Address = 32'h0000_d012<br> 5608 Reset Value = 16'h0087<br> 5609 Access = RW (16-bit only)<br> 5610 <table border=1 align=center width=100% cellpadding=0> 5611 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5612 <tr bgcolor=WHITE> 5613 <td bgcolor=WHITE align=center valign=top>15:13</td> 5614 <td align=left valign=top>RSVD</td> 5615 <td align=left valign=top>Reserved</td> 5616 <td align=left> 5617 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5618 <tr bgcolor=WHITE> 5619 <td bgcolor=WHITE align=center valign=top>12:00</td> 5620 <td align=left valign=top>RW</td> 5621 <td align=left valign=top>eee_lfsr_cnt</td> 5622 <td align=left> 5623 LFSR timer start value for all EEE timers except EEE_MEASURE. LFSR wraps after every 42 rclk20 clock cycles with this default value. <br> 5624 For all non-EEE and non-MEASURE states, LFSR is loaded with 13'h1c1e when cl72_timer_en = 0 resulting into 2048 rclk20 clock cycles for LFSR wrap interval. 5625 <br> 5626 For all non-EEE and non-MEASURE states, LFSR is loaded with 13'h01cd when cl72_timer_en = 1 resulting into 2192 rclk20 clock cycles for LFSR wrap interval. 5627 <br> 5628 Reset value is 0x87.</td></tr> 5629 </table><p> 5630 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5631 <hr> 5632 <b><a NAME="DSC_B_DSC_SM_CTRL_3">DSC_B_DSC_SM_CTRL_3 - DSC STATE MACHINE CONTROL 3</a></b><br> 5633 Address Offset = 32'h0000_d013<br> 5634 Physical Address = 32'h0000_d013<br> 5635 Reset Value = 16'h1c1e<br> 5636 Access = RW (16-bit only)<br> 5637 <table border=1 align=center width=100% cellpadding=0> 5638 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5639 <tr bgcolor=WHITE> 5640 <td bgcolor=WHITE align=center valign=top>15:13</td> 5641 <td align=left valign=top>RSVD</td> 5642 <td align=left valign=top>Reserved</td> 5643 <td align=left> 5644 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5645 <tr bgcolor=WHITE> 5646 <td bgcolor=WHITE align=center valign=top>12:00</td> 5647 <td align=left valign=top>RW</td> 5648 <td align=left valign=top>measure_lfsr_cnt</td> 5649 <td align=left> 5650 LFSR timer start value for MEASURE and EEE_MEASURE state timers. LFSR wraps after every 2048 rclk20 clock cycles with this default value. <br> 5651 For all non-EEE and non-MEASURE states, LFSR is loaded with 13'h1c1e when cl72_timer_en = 0 resulting into 2048 rclk20 clock cycles for LFSR wrap interval. 5652 <br> 5653 For all non-EEE and non-MEASURE states, LFSR is loaded with 13'h01cd when cl72_timer_en = 1 resulting into 2192 rclk20 clock cycles for LFSR wrap interval. 5654 <br> 5655 Reset value is 0x1c1e.</td></tr> 5656 </table><p> 5657 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5658 <hr> 5659 <b><a NAME="DSC_B_DSC_SM_CTRL_4">DSC_B_DSC_SM_CTRL_4 - DSC STATE MACHINE CONTROL 4</a></b><br> 5660 Address Offset = 32'h0000_d014<br> 5661 Physical Address = 32'h0000_d014<br> 5662 Reset Value = 16'h35ad<br> 5663 Access = RW (16-bit only)<br> 5664 <table border=1 align=center width=100% cellpadding=0> 5665 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5666 <tr bgcolor=WHITE> 5667 <td bgcolor=WHITE align=center valign=top>15</td> 5668 <td align=left valign=top>RSVD</td> 5669 <td align=left valign=top>Reserved</td> 5670 <td align=left> 5671 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5672 <tr bgcolor=WHITE> 5673 <td bgcolor=WHITE align=center valign=top>14:10</td> 5674 <td align=left valign=top>RW</td> 5675 <td align=left valign=top>hw_tune_timeout</td> 5676 <td align=left> 5677 Defines timeout value for the HW_TUNE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5678 Reset value is 0xd.</td></tr> 5679 <tr bgcolor=WHITE> 5680 <td bgcolor=WHITE align=center valign=top>09:05</td> 5681 <td align=left valign=top>RW</td> 5682 <td align=left valign=top>cdr_settle_timeout</td> 5683 <td align=left> 5684 Defines timeout value for the CDR_SETTLE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5685 Reset value is 0xd.</td></tr> 5686 <tr bgcolor=WHITE> 5687 <td bgcolor=WHITE align=center valign=top>04:00</td> 5688 <td align=left valign=top>RW</td> 5689 <td align=left valign=top>acq_cdr_timeout</td> 5690 <td align=left> 5691 Defines timeout value for the ACQ_CDR state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5692 Following is the mapping table for the 5 bit timeout register values to 0-448 count. This mapping is applicable to all the DSC_SM timeout registers. <br> 5693     0      =>           0        <br> 5694     1      =>           1        <br> 5695     2      =>           2        <br> 5696     3      =>           3        <br> 5697     4      =>           4        <br> 5698     5      =>           5        <br> 5699     6      =>           6        <br> 5700     7      =>           7        <br> 5701     8      =>           8        <br> 5702     9      =>          10        <br> 5703    10      =>          12        <br> 5704    11      =>          14        <br> 5705    12      =>          16        <br> 5706    13      =>          20        <br> 5707    14      =>          24        <br> 5708    15      =>          28        <br> 5709    16      =>          32        <br> 5710    17      =>          40        <br> 5711    18      =>          48        <br> 5712    19      =>          56        <br> 5713    20      =>          64        <br> 5714    21      =>          80        <br> 5715    22      =>          96        <br> 5716    23      =>         112        <br> 5717    24      =>         128        <br> 5718    25      =>         160        <br> 5719    26      =>         192        <br> 5720    27      =>         224        <br> 5721    28      =>         256        <br> 5722    29      =>         320        <br> 5723    30      =>         384        <br> 5724    31      =>         448        <br> 5725 Reset value is 0xd.</td></tr> 5726 </table><p> 5727 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5728 <hr> 5729 <b><a NAME="DSC_B_DSC_SM_CTRL_5">DSC_B_DSC_SM_CTRL_5 - DSC STATE MACHINE CONTROL 5</a></b><br> 5730 Address Offset = 32'h0000_d015<br> 5731 Physical Address = 32'h0000_d015<br> 5732 Reset Value = 16'h35ad<br> 5733 Access = RW (16-bit only)<br> 5734 <table border=1 align=center width=100% cellpadding=0> 5735 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5736 <tr bgcolor=WHITE> 5737 <td bgcolor=WHITE align=center valign=top>15</td> 5738 <td align=left valign=top>RSVD</td> 5739 <td align=left valign=top>Reserved</td> 5740 <td align=left> 5741 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5742 <tr bgcolor=WHITE> 5743 <td bgcolor=WHITE align=center valign=top>14:10</td> 5744 <td align=left valign=top>RW</td> 5745 <td align=left valign=top>eee_cdr_settle_timeout</td> 5746 <td align=left> 5747 Defines timeout value for the EEE_CDR_SETTLE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5748 Reset value is 0xd.</td></tr> 5749 <tr bgcolor=WHITE> 5750 <td bgcolor=WHITE align=center valign=top>09:05</td> 5751 <td align=left valign=top>RW</td> 5752 <td align=left valign=top>eee_acq_cdr_timeout</td> 5753 <td align=left> 5754 Defines timeout value for the EEE_ACQ_CDR state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5755 Reset value is 0xd.</td></tr> 5756 <tr bgcolor=WHITE> 5757 <td bgcolor=WHITE align=center valign=top>04:00</td> 5758 <td align=left valign=top>RW</td> 5759 <td align=left valign=top>measure_timeout</td> 5760 <td align=left> 5761 Defines timeout value for the MEASURE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5762 Reset value is 0xd.</td></tr> 5763 </table><p> 5764 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5765 <hr> 5766 <b><a NAME="DSC_B_DSC_SM_CTRL_6">DSC_B_DSC_SM_CTRL_6 - DSC STATE MACHINE CONTROL 6</a></b><br> 5767 Address Offset = 32'h0000_d016<br> 5768 Physical Address = 32'h0000_d016<br> 5769 Reset Value = 16'h340d<br> 5770 Access = RW (16-bit only)<br> 5771 <table border=1 align=center width=100% cellpadding=0> 5772 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5773 <tr bgcolor=WHITE> 5774 <td bgcolor=WHITE align=center valign=top>15</td> 5775 <td align=left valign=top>RSVD</td> 5776 <td align=left valign=top>Reserved</td> 5777 <td align=left> 5778 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5779 <tr bgcolor=WHITE> 5780 <td bgcolor=WHITE align=center valign=top>14:10</td> 5781 <td align=left valign=top>RW</td> 5782 <td align=left valign=top>eee_ana_pwr_timeout</td> 5783 <td align=left> 5784 Defines timeout value for the EEE_ANA_PWR state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5785 Reset value is 0xd.</td></tr> 5786 <tr bgcolor=WHITE> 5787 <td bgcolor=WHITE align=center valign=top>09:05</td> 5788 <td align=left valign=top>RW</td> 5789 <td align=left valign=top>slicer_cal_timeout</td> 5790 <td align=left> 5791 Defines timeout value for the SLICER_CAL state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps. Total time spent in SLICER_CAL 5792 is 8*(slicer_cal_timeout timer) . <br> 5793 Reset value is 0x0.</td></tr> 5794 <tr bgcolor=WHITE> 5795 <td bgcolor=WHITE align=center valign=top>04:00</td> 5796 <td align=left valign=top>RW</td> 5797 <td align=left valign=top>eee_hw_tune_timeout</td> 5798 <td align=left> 5799 Defines timeout value for the EEE_HW_TUNE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5800 Reset value is 0xd.</td></tr> 5801 </table><p> 5802 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5803 <hr> 5804 <b><a NAME="DSC_B_DSC_SM_CTRL_7">DSC_B_DSC_SM_CTRL_7 - DSC STATE MACHINE CONTROL 7</a></b><br> 5805 Address Offset = 32'h0000_d017<br> 5806 Physical Address = 32'h0000_d017<br> 5807 Reset Value = 16'h0000<br> 5808 Access = RW (16-bit only)<br> 5809 <table border=1 align=center width=100% cellpadding=0> 5810 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5811 <tr bgcolor=WHITE> 5812 <td bgcolor=WHITE align=center valign=top>15:14</td> 5813 <td align=left valign=top>RW</td> 5814 <td align=left valign=top>cdr_bwsel_prop_norm</td> 5815 <td align=left> 5816 CDR Proportional Bandwidth select for non ACQ_CDR and EEE_ACQ_CDR states. <br> 5817   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 5818   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 5819 Reset value is 0x0.</td></tr> 5820 <tr bgcolor=WHITE> 5821 <td bgcolor=WHITE align=center valign=top>13:12</td> 5822 <td align=left valign=top>RW</td> 5823 <td align=left valign=top>cdr_bwsel_prop_acqcdr</td> 5824 <td align=left> 5825   CDR Proportional Bandwidth select for ACQ_CDR state. <br> 5826   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 5827   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 5828 Reset value is 0x0.</td></tr> 5829 <tr bgcolor=WHITE> 5830 <td bgcolor=WHITE align=center valign=top>11:08</td> 5831 <td align=left valign=top>RW</td> 5832 <td align=left valign=top>cdr_bwsel_integ_norm</td> 5833 <td align=left> 5834 CDR Integ Bandwidth select for non ACQ_CDR and EEE_ACQ_CDR states. <br> 5835 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 5836 Reset value is 0x0.</td></tr> 5837 <tr bgcolor=WHITE> 5838 <td bgcolor=WHITE align=center valign=top>07:04</td> 5839 <td align=left valign=top>RW</td> 5840 <td align=left valign=top>cdr_bwsel_integ_eee_acqcdr</td> 5841 <td align=left> 5842 CDR Integ Bandwidth select for EEE_ACQ_CDR state. <br> 5843 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 5844 Reset value is 0x0.</td></tr> 5845 <tr bgcolor=WHITE> 5846 <td bgcolor=WHITE align=center valign=top>03:00</td> 5847 <td align=left valign=top>RW</td> 5848 <td align=left valign=top>cdr_bwsel_integ_acqcdr</td> 5849 <td align=left> 5850 CDR Integ Bandwidth select for ACQ_CDR state. <br> 5851 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 5852 Reset value is 0x0.</td></tr> 5853 </table><p> 5854 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5855 <hr> 5856 <b><a NAME="DSC_B_DSC_SM_CTRL_8">DSC_B_DSC_SM_CTRL_8 - DSC STATE MACHINE CONTROL 8</a></b><br> 5857 Address Offset = 32'h0000_d018<br> 5858 Physical Address = 32'h0000_d018<br> 5859 Reset Value = 16'h0011<br> 5860 Access = RW (16-bit only)<br> 5861 <table border=1 align=center width=100% cellpadding=0> 5862 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5863 <tr bgcolor=WHITE> 5864 <td bgcolor=WHITE align=center valign=top>15:14</td> 5865 <td align=left valign=top>RW</td> 5866 <td align=left valign=top>cdr_bwsel_prop_eee_acqcdr</td> 5867 <td align=left> 5868 CDR Proportional Bandwidth select for EEE_ACQ_CDR state. <br> 5869   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 5870   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 5871 Reset value is 0x0.</td></tr> 5872 <tr bgcolor=WHITE> 5873 <td bgcolor=WHITE align=center valign=top>13:12</td> 5874 <td align=left valign=top>RSVD</td> 5875 <td align=left valign=top>Reserved</td> 5876 <td align=left> 5877 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5878 <tr bgcolor=WHITE> 5879 <td bgcolor=WHITE align=center valign=top>11:10</td> 5880 <td align=left valign=top>RW</td> 5881 <td align=left valign=top>eee_phase_err_offset_en</td> 5882 <td align=left> 5883 Phase Error Offset Enable for EEE_ACQ_CDR state. <br> 5884 Reset value is 0x0.</td></tr> 5885 <tr bgcolor=WHITE> 5886 <td bgcolor=WHITE align=center valign=top>09:08</td> 5887 <td align=left valign=top>RW</td> 5888 <td align=left valign=top>phase_err_offset_en</td> 5889 <td align=left> 5890 Phase Error Offset Enable for non-EEE_ACQ_CDR states. <br> 5891 Reset value is 0x0.</td></tr> 5892 <tr bgcolor=WHITE> 5893 <td bgcolor=WHITE align=center valign=top>07:04</td> 5894 <td align=left valign=top>RW</td> 5895 <td align=left valign=top>eee_phase_err_offset</td> 5896 <td align=left> 5897 Phase Error Offset for EEE_ACQ_CDR state. Signed value. Valid range is -8 to 7.  <br> 5898 Reset value is 0x1.</td></tr> 5899 <tr bgcolor=WHITE> 5900 <td bgcolor=WHITE align=center valign=top>03:00</td> 5901 <td align=left valign=top>RW</td> 5902 <td align=left valign=top>phase_err_offset</td> 5903 <td align=left> 5904 Phase Error Offset for non-EEE_ACQ_CDR states. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, depending on 5905 how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 5906 Reset value is 0x1.</td></tr> 5907 </table><p> 5908 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5909 <hr> 5910 <b><a NAME="DSC_B_DSC_SM_CTRL_9">DSC_B_DSC_SM_CTRL_9 - DSC STATE MACHINE CONTROL 9</a></b><br> 5911 Address Offset = 32'h0000_d019<br> 5912 Physical Address = 32'h0000_d019<br> 5913 Reset Value = 16'h0000<br> 5914 Access = RW (16-bit only)<br> 5915 <table border=1 align=center width=100% cellpadding=0> 5916 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5917 <tr bgcolor=WHITE> 5918 <td bgcolor=WHITE align=center valign=top>15</td> 5919 <td align=left valign=top>RSVD</td> 5920 <td align=left valign=top>Reserved</td> 5921 <td align=left> 5922 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 5923 <tr bgcolor=WHITE> 5924 <td bgcolor=WHITE align=center valign=top>14:10</td> 5925 <td align=left valign=top>RW</td> 5926 <td align=left valign=top>dcoff_cal_timeout</td> 5927 <td align=left> 5928 Defines timeout value for the DCOFF_CAL state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 5929 Reset value is 0x0.</td></tr> 5930 <tr bgcolor=WHITE> 5931 <td bgcolor=WHITE align=center valign=top>09:02</td> 5932 <td align=left valign=top>RSVD</td> 5933 <td align=left valign=top>Reserved</td> 5934 <td align=left> 5935 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5936 <tr bgcolor=WHITE> 5937 <td bgcolor=WHITE align=center valign=top>01</td> 5938 <td align=left valign=top>RW</td> 5939 <td align=left valign=top>rx_restart_pmd_hold</td> 5940 <td align=left> 5941 1'b1 will reset the DSC SM into RESTART state and HOLD it there until set to 1'b0. <br> 5942 Reset value is 0x0.</td></tr> 5943 <tr bgcolor=WHITE> 5944 <td bgcolor=WHITE align=center valign=top>00</td> 5945 <td align=left valign=top>SC</td> 5946 <td align=left valign=top>rx_restart_pmd</td> 5947 <td align=left> 5948 1'b1 will reset the DSC SM into RESTART state. This is a self-clear register bit. <br> 5949 Reset value is 0x0.</td></tr> 5950 </table><p> 5951 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5952 <hr> 5953 <b><a NAME="DSC_B_DSC_SM_STATUS_DSC_LOCK">DSC_B_DSC_SM_STATUS_DSC_LOCK - DSC STATE MACHINE DSC_LOCK STATUS</a></b><br> 5954 Address Offset = 32'h0000_d01a<br> 5955 Physical Address = 32'h0000_d01a<br> 5956 Reset Value = 16'h0000<br> 5957 Access = RO (16-bit only)<br> 5958 <table border=1 align=center width=100% cellpadding=0> 5959 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 5960 <tr bgcolor=WHITE> 5961 <td bgcolor=WHITE align=center valign=top>15:07</td> 5962 <td align=left valign=top>RO</td> 5963 <td align=left valign=top>eee_measure_cnt</td> 5964 <td align=left> 5965 Indicates the eee_measure_cnt status. This is a debug register. <br> 5966 Reset value is 0x0.</td></tr> 5967 <tr bgcolor=WHITE> 5968 <td bgcolor=WHITE align=center valign=top>06:03</td> 5969 <td align=left valign=top>RSVD</td> 5970 <td align=left valign=top>Reserved</td> 5971 <td align=left> 5972 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 5973 <tr bgcolor=WHITE> 5974 <td bgcolor=WHITE align=center valign=top>02</td> 5975 <td align=left valign=top>RO</td> 5976 <td align=left valign=top>slicer_cal_done</td> 5977 <td align=left> 5978 Status register which is set to 1'b1 upon successful completion of SLICER_CAL state and transition from SLICER_CAL state to WAIT_FOR_SIG state. <br> 5979 This also gets cleared upon DSC_SM block reset (i.e. datapath reset). <br> 5980 Reset value is 0x0.</td></tr> 5981 <tr bgcolor=WHITE> 5982 <td bgcolor=WHITE align=center valign=top>01</td> 5983 <td align=left valign=top>RO</td> 5984 <td align=left valign=top>meas_incomplete</td> 5985 <td align=left> 5986 1 indicates that measurement is incomplete. 0 indicates that measurement is complete. <br> 5987 Reset value is 0x0.</td></tr> 5988 <tr bgcolor=WHITE> 5989 <td bgcolor=WHITE align=center valign=top>00</td> 5990 <td align=left valign=top>RO</td> 5991 <td align=left valign=top>rx_dsc_lock</td> 5992 <td align=left> 5993 1 indicates that DSC is locked. <br> 5994 Reset value is 0x0.</td></tr> 5995 </table><p> 5996 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 5997 <hr> 5998 <b><a NAME="DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0">DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_0 - DSC STATE MACHINE STATUS ONE HOT</a></b><br> 5999 Address Offset = 32'h0000_d01b<br> 6000 Physical Address = 32'h0000_d01b<br> 6001 Reset Value = 16'h0000<br> 6002 Access = RO (16-bit only)<br> 6003 <table border=1 align=center width=100% cellpadding=0> 6004 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6005 <tr bgcolor=WHITE> 6006 <td bgcolor=WHITE align=center valign=top>15:00</td> 6007 <td align=left valign=top>RO</td> 6008 <td align=left valign=top>dsc_state_one_hot_0</td> 6009 <td align=left> 6010 Sticky one-hot coded states. These registers are cleared on read. <br> 6011    INIT            =  0   <br> 6012    ADJ_PI          =  1   <br> 6013    PAUSE           =  2   <br> 6014    SLICER_OFFSET   =  3   <br> 6015    ACQ_CDR         =  4   <br> 6016    CDR_SETTLE      =  5   <br> 6017    DC_OFFSET       =  6   <br> 6018    HW_TUNE         =  7   <br> 6019    UC_TUNE         =  8   <br> 6020    MEASURE         =  9   <br> 6021    DONE            =  10   <br> 6022    FREEZE          =  11   <br> 6023    FACQ_WAIT       =  12  <br> 6024    L0s_ACQ_CDR     =  13  <br> 6025    L1_ACQ_CDR      =  14  <br> 6026    L0sL1_CDR_STTL  =  15  <br> 6027 Reset value is 0x0.</td></tr> 6028 </table><p> 6029 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 6030 <hr> 6031 <b><a NAME="DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1">DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT_1 - DSC STATE MACHINE STATUS ONE HOT</a></b><br> 6032 Address Offset = 32'h0000_d01c<br> 6033 Physical Address = 32'h0000_d01c<br> 6034 Reset Value = 16'h0000<br> 6035 Access = RO (16-bit only)<br> 6036 <table border=1 align=center width=100% cellpadding=0> 6037 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6038 <tr bgcolor=WHITE> 6039 <td bgcolor=WHITE align=center valign=top>15:02</td> 6040 <td align=left valign=top>RSVD</td> 6041 <td align=left valign=top>Reserved</td> 6042 <td align=left> 6043 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6044 <tr bgcolor=WHITE> 6045 <td bgcolor=WHITE align=center valign=top>01:00</td> 6046 <td align=left valign=top>RO</td> 6047 <td align=left valign=top>dsc_state_one_hot_1</td> 6048 <td align=left> 6049    L0sL1_HW_TUNE   =  0  <br> 6050    FACQ_DONE       =  1  <br> 6051 Reset value is 0x0.</td></tr> 6052 </table><p> 6053 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 6054 <hr> 6055 <b><a NAME="DSC_B_DSC_SM_STATUS_RESTART">DSC_B_DSC_SM_STATUS_RESTART - DSC STATE MACHINE STATUS RESTART</a></b><br> 6056 Address Offset = 32'h0000_d01d<br> 6057 Physical Address = 32'h0000_d01d<br> 6058 Reset Value = 16'h0000<br> 6059 Access = RO (16-bit only)<br> 6060 <table border=1 align=center width=100% cellpadding=0> 6061 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6062 <tr bgcolor=WHITE> 6063 <td bgcolor=WHITE align=center valign=top>15:04</td> 6064 <td align=left valign=top>RSVD</td> 6065 <td align=left valign=top>Reserved</td> 6066 <td align=left> 6067 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6068 <tr bgcolor=WHITE> 6069 <td bgcolor=WHITE align=center valign=top>03</td> 6070 <td align=left valign=top>RO</td> 6071 <td align=left valign=top>eee_quiet_from_eee_states</td> 6072 <td align=left> 6073 Indicates when SM moves from any EEE states to EEE_QUIET state. This is clear on read. <br> 6074 Reset value is 0x0.</td></tr> 6075 <tr bgcolor=WHITE> 6076 <td bgcolor=WHITE align=center valign=top>02</td> 6077 <td align=left valign=top>RO</td> 6078 <td align=left valign=top>restart_pmd_restart</td> 6079 <td align=left> 6080 Indicates when SM moves to RESTART state due to assertion of pmd_restart to 1'b1. This is clear on read. <br> 6081 Reset value is 0x0.</td></tr> 6082 <tr bgcolor=WHITE> 6083 <td bgcolor=WHITE align=center valign=top>01</td> 6084 <td align=left valign=top>RO</td> 6085 <td align=left valign=top>restart_sigdet</td> 6086 <td align=left> 6087   Indicates when SM moves to RESTART state due to sigdet==0 and eee_mode_en register is 1'b0. This is clear on read. <br> 6088 Reset value is 0x0.</td></tr> 6089 <tr bgcolor=WHITE> 6090 <td bgcolor=WHITE align=center valign=top>00</td> 6091 <td align=left valign=top>RO</td> 6092 <td align=left valign=top>restart_pi_ext_mode</td> 6093 <td align=left> 6094 Indicates when SM moves to RESTART state due to enabling of RX_PI external control (i.e. digital loopback enable). This is clear on read. <br> 6095 Reset value is 0x0.</td></tr> 6096 </table><p> 6097 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 6098 <hr> 6099 <b><a NAME="DSC_B_DSC_SM_STATUS_DSC_STATE">DSC_B_DSC_SM_STATUS_DSC_STATE - DSC STATE MACHINE STATUS</a></b><br> 6100 Address Offset = 32'h0000_d01e<br> 6101 Physical Address = 32'h0000_d01e<br> 6102 Reset Value = 16'h0040<br> 6103 Access = RO (16-bit only)<br> 6104 <table border=1 align=center width=100% cellpadding=0> 6105 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6106 <tr bgcolor=WHITE> 6107 <td bgcolor=WHITE align=center valign=top>15:11</td> 6108 <td align=left valign=top>RO</td> 6109 <td align=left valign=top>dsc_state</td> 6110 <td align=left> 6111    INIT            =  0   <br> 6112    PAUSE           =  1   <br> 6113    SLICER_OFFSET   =  2   <br> 6114    ACQ_CDR         =  3   <br> 6115    CDR_SETTLE      =  4   <br> 6116    HW_TUNE         =  5   <br> 6117    UC_TUNE         =  6   <br> 6118    MEASURE         =  7   <br> 6119    DONE            =  8   <br> 6120    FREEZE          =  9   <br> 6121    FACQ_WAIT       =  10  <br> 6122    L0sL1_ACQ_CDR   =  11  <br> 6123    L0sL1_CDR_STTL  =  12  <br> 6124    L0sL1_HW_TUNE   =  13  <br> 6125    FACQ_DONE       =  14  <br> 6126    DC_OFFSET       =  15  <br> 6127    ADJ_PI          =  16  <br> 6128 Reset value is 0x0.</td></tr> 6129 <tr bgcolor=WHITE> 6130 <td bgcolor=WHITE align=center valign=top>10:08</td> 6131 <td align=left valign=top>RO</td> 6132 <td align=left valign=top>dsc_sm_scratch</td> 6133 <td align=left> 6134   3 LSB bits of dsc_scratch <br> 6135 Reset value is 0x0.</td></tr> 6136 <tr bgcolor=WHITE> 6137 <td bgcolor=WHITE align=center valign=top>07</td> 6138 <td align=left valign=top>RO</td> 6139 <td align=left valign=top>dsc_sm_ready_for_cmd</td> 6140 <td align=left> 6141 Ready for Command. <br> 6142 Reset value is 0x0.</td></tr> 6143 <tr bgcolor=WHITE> 6144 <td bgcolor=WHITE align=center valign=top>06</td> 6145 <td align=left valign=top>RO</td> 6146 <td align=left valign=top>cdr_lm_outoflock</td> 6147 <td align=left> 6148 CDR Lock Monitor loss of lock (1 implies a potential loss of lock). This bit sets itself on register read. <br> 6149 And if the cdr_integ_reg is within bounds it clears itself in the next cycle from which it detects within bounds. Note: Set on read <br> 6150 The valid bounds on the cdr_integ_reg are programmed using cdr_lm_thr_sel <br> 6151 Has more meaning after rx_dsc_lock is asserted.<br> 6152 Reset value is 0x1.</td></tr> 6153 <tr bgcolor=WHITE> 6154 <td bgcolor=WHITE align=center valign=top>05:00</td> 6155 <td align=left valign=top>RO</td> 6156 <td align=left valign=top>dsc_sm_gp_uc_req</td> 6157 <td align=left> 6158 gp_uc_req. <br> 6159 Reset value is 0x0.</td></tr> 6160 </table><p> 6161 <A HREF="#DSC_B Registers">Return to DSC_B: per lane register block [One Copy Per Lane] Table</A><p> 6162 <hr> 6163 <H1><a NAME="DSC_C Registers">DSC_C: per lane register block [One Copy Per Lane] Registers</a></H1> 6164 <table border=1 align=center width=100% cellpadding=0> 6165 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 6166 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 6167 <tr> 6168 <td align=center>0xD020</td><td><A HREF="#DSC_C_DFE_COMMON_CTL">DSC_C_DFE_COMMON_CTL</A><br>DFE Common Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_acc_hys_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_allow_simult</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_update_gain</div> </td> <td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_eye_closure_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_hw_eye_closure_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dfe_leaky_lms_upd_dur</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_leaky_lms_en</div> </td> <td align=center>16'h0000</td></tr> 6169 <tr> 6170 <td align=center>0xD021</td><td><A HREF="#DSC_C_DFE_1_CTL">DSC_C_DFE_1_CTL</A><br>DFE 1 Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_1_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_gradient_invert</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_1_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_inv_p1</div> </td> <td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_cmn_only</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_acc_clr</div> </td> <td align=center>16'h0000</td></tr> 6171 <tr> 6172 <td align=center>0xD022</td><td><A HREF="#DSC_C_DFE_2_CTL">DSC_C_DFE_2_CTL</A><br>DFE 2 Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_2_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_gradient_invert</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_2_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_inv_p1</div> </td> <td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_cmn_only</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_acc_clr</div> </td> <td align=center>16'h0000</td></tr> 6173 <tr> 6174 <td align=center>0xD023</td><td><A HREF="#DSC_C_DFE_3_CTL">DSC_C_DFE_3_CTL</A><br>DFE 3 Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_3_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_3_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_3_gradient_invert</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_3_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_3_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_3_inv_p1</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_3_acc_clr</div> </td> <td align=center>16'h0000</td></tr> 6175 <tr> 6176 <td align=center>0xD024</td><td><A HREF="#DSC_C_DFE_4_CTL">DSC_C_DFE_4_CTL</A><br>DFE 4 Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_4_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_4_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_4_gradient_invert</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_4_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_4_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_4_inv_p1</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_4_acc_clr</div> </td> <td align=center>16'h0000</td></tr> 6177 <tr> 6178 <td align=center>0xD025</td><td><A HREF="#DSC_C_DFE_5_CTL">DSC_C_DFE_5_CTL</A><br>DFE 5 Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_5_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_5_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_5_gradient_invert</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">dfe_5_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_5_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_5_inv_p1</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_5_acc_clr</div> </td> <td align=center>16'h0000</td></tr> 6179 <tr> 6180 <td align=center>0xD026</td><td><A HREF="#DSC_C_DFE_PAT_CTL">DSC_C_DFE_PAT_CTL</A><br>DFE Pattern Control</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">dfe_pattern_bit_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">dfe_pattern</div> </td> <td align=center>16'h0000</td></tr> 6181 <tr> 6182 <td align=center>0xD027</td><td><A HREF="#DSC_C_VGA_P1_MISC_CONTROL">DSC_C_VGA_P1_MISC_CONTROL</A><br>VGA P1 Misc Control</td><td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">p1_hwtune_min</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_op_short_norm</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_op_short_offcal</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">vga_hwtune_min</div> </td> <td align=center>16'h8440</td></tr> 6183 <tr> 6184 <td align=center>0xD029</td><td><A HREF="#DSC_C_DC_SLICER_OFFSET_CTL">DSC_C_DC_SLICER_OFFSET_CTL</A><br>DC & Slicer Offset Hw-tune CTL</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dc_offset_pattern_bit_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">dc_offset_pattern</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_dc_offset_grad_inv</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_pattern_inv_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_inv</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">hw_dc_offset_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_dc_offset_hys_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_en</div> </td> <td align=center>16'h0001</td></tr> 6185 <tr> 6186 <td align=center>0xD02A</td><td><A HREF="#DSC_C_SLICER_OFFSET_CONTROL">DSC_C_SLICER_OFFSET_CONTROL</A><br>Slicer Offset Hw-tune CTL</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_slicer_offset_grad_inv</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_slicer_offset_inv_p1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_slicer_offset_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_slicer_offset_inv_data</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">hw_slicer_offset_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_slicer_offset_hys_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hw_slicer_offset_en</div> </td> <td align=center>16'h0001</td></tr> 6187 <tr> 6188 <td align=center>0xD02B</td><td><A HREF="#DSC_C_HWTUNE_OVR_OVERRIDE">DSC_C_HWTUNE_OVR_OVERRIDE</A><br>DFE Overrude</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hwtune_ovr_write_en</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">hwtune_ovr_write_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="9"><div class="HT">hwtune_ovr_write_val</div> </td> <td align=center>16'h0000</td></tr> 6189 <tr> 6190 <td align=center>0xD02C</td><td><A HREF="#DSC_C_VGA_CTL">DSC_C_VGA_CTL</A><br>VGA Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">vga_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_p1_gradient_invert</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">vga_err_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_inv_m1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_inv_p1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">vga_update_gain</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_affected_by_dfe1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">vga_update_style</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_acc_hys_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_p1_acc_clr</div> </td> <td align=center>16'h0000</td></tr> 6191 <tr> 6192 <td align=center>0xD02D</td><td><A HREF="#DSC_C_VGA_PAT_EYEDIAG_CTL">DSC_C_VGA_PAT_EYEDIAG_CTL</A><br>VGA Pat and P1 Eye Diag Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">p1_eyediag_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vga_pattern_bit_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vga_pattern</div> </td> <td align=center>16'h0000</td></tr> 6193 <tr> 6194 <td align=center>0xD02E</td><td><A HREF="#DSC_C_P1_FRAC_OFFS_CTL">DSC_C_P1_FRAC_OFFS_CTL</A><br>P1 Fractional Offset Control</td><td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">p1_hwtune_max</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">p1_off_3levelq_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">p1_offset_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">p1_offset</div> </td> <td align=center>16'hc400</td></tr> 6195 </table><p> 6196 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 6197 <hr> 6198 <b><a NAME="DSC_C_DFE_COMMON_CTL">DSC_C_DFE_COMMON_CTL - DFE Common Control</a></b><br> 6199 Address Offset = 32'h0000_d020<br> 6200 Physical Address = 32'h0000_d020<br> 6201 Reset Value = 16'h0000<br> 6202 Access = RW (16-bit only)<br> 6203 <table border=1 align=center width=100% cellpadding=0> 6204 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6205 <tr bgcolor=WHITE> 6206 <td bgcolor=WHITE align=center valign=top>15</td> 6207 <td align=left valign=top>RW</td> 6208 <td align=left valign=top>dfe_acc_hys_en</td> 6209 <td align=left> 6210 Enables hysteresis behavior in the accumulator  <br> 6211 Reset value is 0x0.</td></tr> 6212 <tr bgcolor=WHITE> 6213 <td bgcolor=WHITE align=center valign=top>14</td> 6214 <td align=left valign=top>RW</td> 6215 <td align=left valign=top>dfe_allow_simult</td> 6216 <td align=left> 6217 Allow simulatenous change for the cmn tap as well as either odd/even tap controls  <br> 6218 Reset value is 0x0.</td></tr> 6219 <tr bgcolor=WHITE> 6220 <td bgcolor=WHITE align=center valign=top>13</td> 6221 <td align=left valign=top>RW</td> 6222 <td align=left valign=top>dfe_update_gain</td> 6223 <td align=left> 6224 *1 or *2 on the updates to the tap  <br> 6225 Reset value is 0x0.</td></tr> 6226 <tr bgcolor=WHITE> 6227 <td bgcolor=WHITE align=center valign=top>12:08</td> 6228 <td align=left valign=top>RSVD</td> 6229 <td align=left valign=top>Reserved</td> 6230 <td align=left> 6231 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6232 <tr bgcolor=WHITE> 6233 <td bgcolor=WHITE align=center valign=top>07:06</td> 6234 <td align=left valign=top>RW</td> 6235 <td align=left valign=top>dfe_eye_closure_err_sel</td> 6236 <td align=left> 6237 When dfe_eye_closure_en is set, this field determines what is compared against d slicer. d!=error_selected , where error_selected is:<br> 6238 2'b00: emux ; emux = d? p1:m1<br> 6239 2'b01: m1<br> 6240 2'b10: p1<br> 6241 2'b11: not supported <br> 6242 Reset value is 0x0.</td></tr> 6243 <tr bgcolor=WHITE> 6244 <td bgcolor=WHITE align=center valign=top>05</td> 6245 <td align=left valign=top>RW</td> 6246 <td align=left valign=top>dfe_hw_eye_closure_en</td> 6247 <td align=left> 6248 When 1, this enables the DFE adaptive loop to only react to eye closure conditions.  <br> 6249 An eye closure condition is defined as d!={emux or p1 or m1} <br> 6250 This selectability is provided by the dfe_eye_closure_err_sel[1:0] <br> 6251 emux is defined as d?p1:m1 <br> 6252 Reset value is 0x0.</td></tr> 6253 <tr bgcolor=WHITE> 6254 <td bgcolor=WHITE align=center valign=top>04:01</td> 6255 <td align=left valign=top>RW</td> 6256 <td align=left valign=top>dfe_leaky_lms_upd_dur</td> 6257 <td align=left> 6258 0: dfe accumulator leaks every cycle <br> 6259 1-7: dfe accumulator leaks every 2^{1-7} cycles <br> 6260 Reset value is 0x0.</td></tr> 6261 <tr bgcolor=WHITE> 6262 <td bgcolor=WHITE align=center valign=top>00</td> 6263 <td align=left valign=top>RW</td> 6264 <td align=left valign=top>dfe_leaky_lms_en</td> 6265 <td align=left> 6266 When 1, the leaky lms feature is enabled in the DFE adaptive loops.<br> 6267 The rate of leakiness = amount/time is adjustable by changing the time interval <br> 6268 The amount of leakiness is fixed to +2 or -2. The interval between leaks is programmable.<br> 6269 +2 when sign of the tap is negative and -2 when sign of the tap is positive.<br> 6270 Reset value is 0x0.</td></tr> 6271 </table><p> 6272 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6273 <hr> 6274 <b><a NAME="DSC_C_DFE_1_CTL">DSC_C_DFE_1_CTL - DFE 1 Control</a></b><br> 6275 Address Offset = 32'h0000_d021<br> 6276 Physical Address = 32'h0000_d021<br> 6277 Reset Value = 16'h0000<br> 6278 Access = RW (16-bit only)<br> 6279 <table border=1 align=center width=100% cellpadding=0> 6280 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6281 <tr bgcolor=WHITE> 6282 <td bgcolor=WHITE align=center valign=top>15</td> 6283 <td align=left valign=top>RW</td> 6284 <td align=left valign=top>dfe_1_en</td> 6285 <td align=left> 6286 Enables the tap for adaptive eq  <br> 6287 Reset value is 0x0.</td></tr> 6288 <tr bgcolor=WHITE> 6289 <td bgcolor=WHITE align=center valign=top>14:13</td> 6290 <td align=left valign=top>RW</td> 6291 <td align=left valign=top>dfe_1_err_sel</td> 6292 <td align=left> 6293 00: emux, 01: p1, 02: m1, 03: nemux  <br> 6294 emux = d? p1:m1; nemux = ~d? p1: m1<br> 6295 Reset value is 0x0.</td></tr> 6296 <tr bgcolor=WHITE> 6297 <td bgcolor=WHITE align=center valign=top>12</td> 6298 <td align=left valign=top>RW</td> 6299 <td align=left valign=top>dfe_1_gradient_invert</td> 6300 <td align=left> 6301 invert the gradient  <br> 6302 Reset value is 0x0.</td></tr> 6303 <tr bgcolor=WHITE> 6304 <td bgcolor=WHITE align=center valign=top>11:10</td> 6305 <td align=left valign=top>RW</td> 6306 <td align=left valign=top>dfe_1_err_gain</td> 6307 <td align=left> 6308 error scaled by 2^dfe_1_err_gain <br> 6309 Reset value is 0x0.</td></tr> 6310 <tr bgcolor=WHITE> 6311 <td bgcolor=WHITE align=center valign=top>09</td> 6312 <td align=left valign=top>RW</td> 6313 <td align=left valign=top>dfe_1_inv_m1</td> 6314 <td align=left> 6315 invert m1 <br> 6316 Reset value is 0x0.</td></tr> 6317 <tr bgcolor=WHITE> 6318 <td bgcolor=WHITE align=center valign=top>08</td> 6319 <td align=left valign=top>RW</td> 6320 <td align=left valign=top>dfe_1_inv_p1</td> 6321 <td align=left> 6322 invert p1 <br> 6323 Reset value is 0x0.</td></tr> 6324 <tr bgcolor=WHITE> 6325 <td bgcolor=WHITE align=center valign=top>07:02</td> 6326 <td align=left valign=top>RSVD</td> 6327 <td align=left valign=top>Reserved</td> 6328 <td align=left> 6329 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6330 <tr bgcolor=WHITE> 6331 <td bgcolor=WHITE align=center valign=top>01</td> 6332 <td align=left valign=top>RW</td> 6333 <td align=left valign=top>dfe_1_cmn_only</td> 6334 <td align=left> 6335 both even and odd errors are summed and apply only to cmn tap - not to the evn and odd taps<br> 6336 Reset value is 0x0.</td></tr> 6337 <tr bgcolor=WHITE> 6338 <td bgcolor=WHITE align=center valign=top>00</td> 6339 <td align=left valign=top>RW</td> 6340 <td align=left valign=top>dfe_1_acc_clr</td> 6341 <td align=left> 6342 clears the dfe_1_tap related accumulator, and intermediate pipeline stages, but not the taps which interface to the analog.<br> 6343 Reset value is 0x0.</td></tr> 6344 </table><p> 6345 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6346 <hr> 6347 <b><a NAME="DSC_C_DFE_2_CTL">DSC_C_DFE_2_CTL - DFE 2 Control</a></b><br> 6348 Address Offset = 32'h0000_d022<br> 6349 Physical Address = 32'h0000_d022<br> 6350 Reset Value = 16'h0000<br> 6351 Access = RW (16-bit only)<br> 6352 <table border=1 align=center width=100% cellpadding=0> 6353 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6354 <tr bgcolor=WHITE> 6355 <td bgcolor=WHITE align=center valign=top>15</td> 6356 <td align=left valign=top>RW</td> 6357 <td align=left valign=top>dfe_2_en</td> 6358 <td align=left> 6359 Enables the tap for adaptive eq  <br> 6360 Reset value is 0x0.</td></tr> 6361 <tr bgcolor=WHITE> 6362 <td bgcolor=WHITE align=center valign=top>14:13</td> 6363 <td align=left valign=top>RW</td> 6364 <td align=left valign=top>dfe_2_err_sel</td> 6365 <td align=left> 6366 00: emux, 01: p1, 02: m1, 03: nemux  <br> 6367 emux = d? p1:m1; nemux = ~d? p1: m1<br> 6368 Reset value is 0x0.</td></tr> 6369 <tr bgcolor=WHITE> 6370 <td bgcolor=WHITE align=center valign=top>12</td> 6371 <td align=left valign=top>RW</td> 6372 <td align=left valign=top>dfe_2_gradient_invert</td> 6373 <td align=left> 6374 invert the gradient  <br> 6375 Reset value is 0x0.</td></tr> 6376 <tr bgcolor=WHITE> 6377 <td bgcolor=WHITE align=center valign=top>11:10</td> 6378 <td align=left valign=top>RW</td> 6379 <td align=left valign=top>dfe_2_err_gain</td> 6380 <td align=left> 6381 error scaled by 2^dfe_2_err_gain <br> 6382 Reset value is 0x0.</td></tr> 6383 <tr bgcolor=WHITE> 6384 <td bgcolor=WHITE align=center valign=top>09</td> 6385 <td align=left valign=top>RW</td> 6386 <td align=left valign=top>dfe_2_inv_m1</td> 6387 <td align=left> 6388 invert m1 <br> 6389 Reset value is 0x0.</td></tr> 6390 <tr bgcolor=WHITE> 6391 <td bgcolor=WHITE align=center valign=top>08</td> 6392 <td align=left valign=top>RW</td> 6393 <td align=left valign=top>dfe_2_inv_p1</td> 6394 <td align=left> 6395 invert p1 <br> 6396 Reset value is 0x0.</td></tr> 6397 <tr bgcolor=WHITE> 6398 <td bgcolor=WHITE align=center valign=top>07:02</td> 6399 <td align=left valign=top>RSVD</td> 6400 <td align=left valign=top>Reserved</td> 6401 <td align=left> 6402 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6403 <tr bgcolor=WHITE> 6404 <td bgcolor=WHITE align=center valign=top>01</td> 6405 <td align=left valign=top>RW</td> 6406 <td align=left valign=top>dfe_2_cmn_only</td> 6407 <td align=left> 6408 both even and odd errors are summed and apply only to cmn tap - not to the evn and odd taps<br> 6409 Reset value is 0x0.</td></tr> 6410 <tr bgcolor=WHITE> 6411 <td bgcolor=WHITE align=center valign=top>00</td> 6412 <td align=left valign=top>RW</td> 6413 <td align=left valign=top>dfe_2_acc_clr</td> 6414 <td align=left> 6415 clears the dfe_2_tap related accumulator, and intermediate pipeline stages, but not the taps which interface to the analog.<br> 6416 Reset value is 0x0.</td></tr> 6417 </table><p> 6418 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6419 <hr> 6420 <b><a NAME="DSC_C_DFE_3_CTL">DSC_C_DFE_3_CTL - DFE 3 Control</a></b><br> 6421 Address Offset = 32'h0000_d023<br> 6422 Physical Address = 32'h0000_d023<br> 6423 Reset Value = 16'h0000<br> 6424 Access = RW (16-bit only)<br> 6425 <table border=1 align=center width=100% cellpadding=0> 6426 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6427 <tr bgcolor=WHITE> 6428 <td bgcolor=WHITE align=center valign=top>15</td> 6429 <td align=left valign=top>RW</td> 6430 <td align=left valign=top>dfe_3_en</td> 6431 <td align=left> 6432 Enables the tap for adaptive eq  <br> 6433 Reset value is 0x0.</td></tr> 6434 <tr bgcolor=WHITE> 6435 <td bgcolor=WHITE align=center valign=top>14:13</td> 6436 <td align=left valign=top>RW</td> 6437 <td align=left valign=top>dfe_3_err_sel</td> 6438 <td align=left> 6439 00: emux, 01: p1, 02: m1, 03: nemux  <br> 6440 emux = d? p1:m1; nemux = ~d? p1: m1<br> 6441 Reset value is 0x0.</td></tr> 6442 <tr bgcolor=WHITE> 6443 <td bgcolor=WHITE align=center valign=top>12</td> 6444 <td align=left valign=top>RW</td> 6445 <td align=left valign=top>dfe_3_gradient_invert</td> 6446 <td align=left> 6447 invert the gradient  <br> 6448 Reset value is 0x0.</td></tr> 6449 <tr bgcolor=WHITE> 6450 <td bgcolor=WHITE align=center valign=top>11:10</td> 6451 <td align=left valign=top>RW</td> 6452 <td align=left valign=top>dfe_3_err_gain</td> 6453 <td align=left> 6454 error scaled by 2^dfe_3_err_gain <br> 6455 Reset value is 0x0.</td></tr> 6456 <tr bgcolor=WHITE> 6457 <td bgcolor=WHITE align=center valign=top>09</td> 6458 <td align=left valign=top>RW</td> 6459 <td align=left valign=top>dfe_3_inv_m1</td> 6460 <td align=left> 6461 invert m1 <br> 6462 Reset value is 0x0.</td></tr> 6463 <tr bgcolor=WHITE> 6464 <td bgcolor=WHITE align=center valign=top>08</td> 6465 <td align=left valign=top>RW</td> 6466 <td align=left valign=top>dfe_3_inv_p1</td> 6467 <td align=left> 6468 invert p1 <br> 6469 Reset value is 0x0.</td></tr> 6470 <tr bgcolor=WHITE> 6471 <td bgcolor=WHITE align=center valign=top>07:01</td> 6472 <td align=left valign=top>RSVD</td> 6473 <td align=left valign=top>Reserved</td> 6474 <td align=left> 6475 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6476 <tr bgcolor=WHITE> 6477 <td bgcolor=WHITE align=center valign=top>00</td> 6478 <td align=left valign=top>RW</td> 6479 <td align=left valign=top>dfe_3_acc_clr</td> 6480 <td align=left> 6481 clears the dfe_3_tap related accumulator, and intermediate pipeline stages, but not the taps which interface to the analog.<br> 6482 Reset value is 0x0.</td></tr> 6483 </table><p> 6484 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6485 <hr> 6486 <b><a NAME="DSC_C_DFE_4_CTL">DSC_C_DFE_4_CTL - DFE 4 Control</a></b><br> 6487 Address Offset = 32'h0000_d024<br> 6488 Physical Address = 32'h0000_d024<br> 6489 Reset Value = 16'h0000<br> 6490 Access = RW (16-bit only)<br> 6491 <table border=1 align=center width=100% cellpadding=0> 6492 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6493 <tr bgcolor=WHITE> 6494 <td bgcolor=WHITE align=center valign=top>15</td> 6495 <td align=left valign=top>RW</td> 6496 <td align=left valign=top>dfe_4_en</td> 6497 <td align=left> 6498 Enables the tap for adaptive eq  <br> 6499 Reset value is 0x0.</td></tr> 6500 <tr bgcolor=WHITE> 6501 <td bgcolor=WHITE align=center valign=top>14:13</td> 6502 <td align=left valign=top>RW</td> 6503 <td align=left valign=top>dfe_4_err_sel</td> 6504 <td align=left> 6505 00: emux, 01: p1, 02: m1, 03: nemux  <br> 6506 emux = d? p1:m1; nemux = ~d? p1: m1<br> 6507 Reset value is 0x0.</td></tr> 6508 <tr bgcolor=WHITE> 6509 <td bgcolor=WHITE align=center valign=top>12</td> 6510 <td align=left valign=top>RW</td> 6511 <td align=left valign=top>dfe_4_gradient_invert</td> 6512 <td align=left> 6513 invert the gradient  <br> 6514 Reset value is 0x0.</td></tr> 6515 <tr bgcolor=WHITE> 6516 <td bgcolor=WHITE align=center valign=top>11:10</td> 6517 <td align=left valign=top>RW</td> 6518 <td align=left valign=top>dfe_4_err_gain</td> 6519 <td align=left> 6520 error scaled by 2^dfe_4_err_gain <br> 6521 Reset value is 0x0.</td></tr> 6522 <tr bgcolor=WHITE> 6523 <td bgcolor=WHITE align=center valign=top>09</td> 6524 <td align=left valign=top>RW</td> 6525 <td align=left valign=top>dfe_4_inv_m1</td> 6526 <td align=left> 6527 invert m1 <br> 6528 Reset value is 0x0.</td></tr> 6529 <tr bgcolor=WHITE> 6530 <td bgcolor=WHITE align=center valign=top>08</td> 6531 <td align=left valign=top>RW</td> 6532 <td align=left valign=top>dfe_4_inv_p1</td> 6533 <td align=left> 6534 invert p1 <br> 6535 Reset value is 0x0.</td></tr> 6536 <tr bgcolor=WHITE> 6537 <td bgcolor=WHITE align=center valign=top>07:01</td> 6538 <td align=left valign=top>RSVD</td> 6539 <td align=left valign=top>Reserved</td> 6540 <td align=left> 6541 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6542 <tr bgcolor=WHITE> 6543 <td bgcolor=WHITE align=center valign=top>00</td> 6544 <td align=left valign=top>RW</td> 6545 <td align=left valign=top>dfe_4_acc_clr</td> 6546 <td align=left> 6547 clears the dfe_4_tap related accumulator, and intermediate pipeline stages, but not the taps which interface to the analog.<br> 6548 Reset value is 0x0.</td></tr> 6549 </table><p> 6550 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6551 <hr> 6552 <b><a NAME="DSC_C_DFE_5_CTL">DSC_C_DFE_5_CTL - DFE 5 Control</a></b><br> 6553 Address Offset = 32'h0000_d025<br> 6554 Physical Address = 32'h0000_d025<br> 6555 Reset Value = 16'h0000<br> 6556 Access = RW (16-bit only)<br> 6557 <table border=1 align=center width=100% cellpadding=0> 6558 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6559 <tr bgcolor=WHITE> 6560 <td bgcolor=WHITE align=center valign=top>15</td> 6561 <td align=left valign=top>RW</td> 6562 <td align=left valign=top>dfe_5_en</td> 6563 <td align=left> 6564 Enables the tap for adaptive eq  <br> 6565 Reset value is 0x0.</td></tr> 6566 <tr bgcolor=WHITE> 6567 <td bgcolor=WHITE align=center valign=top>14:13</td> 6568 <td align=left valign=top>RW</td> 6569 <td align=left valign=top>dfe_5_err_sel</td> 6570 <td align=left> 6571 00: emux, 01: p1, 02: m1, 03: nemux  <br> 6572 emux = d? p1:m1; nemux = ~d? p1: m1<br> 6573 Reset value is 0x0.</td></tr> 6574 <tr bgcolor=WHITE> 6575 <td bgcolor=WHITE align=center valign=top>12</td> 6576 <td align=left valign=top>RW</td> 6577 <td align=left valign=top>dfe_5_gradient_invert</td> 6578 <td align=left> 6579 invert the gradient  <br> 6580 Reset value is 0x0.</td></tr> 6581 <tr bgcolor=WHITE> 6582 <td bgcolor=WHITE align=center valign=top>11:10</td> 6583 <td align=left valign=top>RW</td> 6584 <td align=left valign=top>dfe_5_err_gain</td> 6585 <td align=left> 6586 error scaled by 2^dfe_5_err_gain <br> 6587 Reset value is 0x0.</td></tr> 6588 <tr bgcolor=WHITE> 6589 <td bgcolor=WHITE align=center valign=top>09</td> 6590 <td align=left valign=top>RW</td> 6591 <td align=left valign=top>dfe_5_inv_m1</td> 6592 <td align=left> 6593 invert m1 <br> 6594 Reset value is 0x0.</td></tr> 6595 <tr bgcolor=WHITE> 6596 <td bgcolor=WHITE align=center valign=top>08</td> 6597 <td align=left valign=top>RW</td> 6598 <td align=left valign=top>dfe_5_inv_p1</td> 6599 <td align=left> 6600 invert p1 <br> 6601 Reset value is 0x0.</td></tr> 6602 <tr bgcolor=WHITE> 6603 <td bgcolor=WHITE align=center valign=top>07:01</td> 6604 <td align=left valign=top>RSVD</td> 6605 <td align=left valign=top>Reserved</td> 6606 <td align=left> 6607 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6608 <tr bgcolor=WHITE> 6609 <td bgcolor=WHITE align=center valign=top>00</td> 6610 <td align=left valign=top>RW</td> 6611 <td align=left valign=top>dfe_5_acc_clr</td> 6612 <td align=left> 6613 clears the dfe_5_tap related accumulator, and intermediate pipeline stages, but not the taps which interface to the analog.<br> 6614 Reset value is 0x0.</td></tr> 6615 </table><p> 6616 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6617 <hr> 6618 <b><a NAME="DSC_C_DFE_PAT_CTL">DSC_C_DFE_PAT_CTL - DFE Pattern Control</a></b><br> 6619 Address Offset = 32'h0000_d026<br> 6620 Physical Address = 32'h0000_d026<br> 6621 Reset Value = 16'h0000<br> 6622 Access = RW (16-bit only)<br> 6623 <table border=1 align=center width=100% cellpadding=0> 6624 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6625 <tr bgcolor=WHITE> 6626 <td bgcolor=WHITE align=center valign=top>15:14</td> 6627 <td align=left valign=top>RSVD</td> 6628 <td align=left valign=top>Reserved</td> 6629 <td align=left> 6630 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6631 <tr bgcolor=WHITE> 6632 <td bgcolor=WHITE align=center valign=top>13:08</td> 6633 <td align=left valign=top>RW</td> 6634 <td align=left valign=top>dfe_pattern_bit_en</td> 6635 <td align=left> 6636 pattern bit mask <br> 6637 pattern bits [5:0] msb to lsb <=> locations 0 to -5 (current bit to 5 bits in past)<br> 6638 pattern_bit_en[5:0] serves as a bitwise mask which enables the corresponding bits in the pattern[5:0] to be enabled for matching<br> 6639 Reset value is 0x0.</td></tr> 6640 <tr bgcolor=WHITE> 6641 <td bgcolor=WHITE align=center valign=top>07:06</td> 6642 <td align=left valign=top>RSVD</td> 6643 <td align=left valign=top>Reserved</td> 6644 <td align=left> 6645 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6646 <tr bgcolor=WHITE> 6647 <td bgcolor=WHITE align=center valign=top>05:00</td> 6648 <td align=left valign=top>RW</td> 6649 <td align=left valign=top>dfe_pattern</td> 6650 <td align=left> 6651 pattern based conditioning of error accumulation (accumulate if pattern matches) <br> 6652 pattern bits [5:0] msb to lsb <=> locations 0 to -5 (current bit to 5 bits in past)<br> 6653 Reset value is 0x0.</td></tr> 6654 </table><p> 6655 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6656 <hr> 6657 <b><a NAME="DSC_C_VGA_P1_MISC_CONTROL">DSC_C_VGA_P1_MISC_CONTROL - VGA P1 Misc Control</a></b><br> 6658 Address Offset = 32'h0000_d027<br> 6659 Physical Address = 32'h0000_d027<br> 6660 Reset Value = 16'h8440<br> 6661 Access = RW (16-bit only)<br> 6662 <table border=1 align=center width=100% cellpadding=0> 6663 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6664 <tr bgcolor=WHITE> 6665 <td bgcolor=WHITE align=center valign=top>15:10</td> 6666 <td align=left valign=top>RW</td> 6667 <td align=left valign=top>p1_hwtune_min</td> 6668 <td align=left> 6669 A signed minimum limit which the hardware loop respects during adaptation.<br> 6670 Must be lesser than the p1_hwtune_max.<br> 6671 Default is 21h, which is -31.<br> 6672 Reset value is 0x21.</td></tr> 6673 <tr bgcolor=WHITE> 6674 <td bgcolor=WHITE align=center valign=top>09:08</td> 6675 <td align=left valign=top>RSVD</td> 6676 <td align=left valign=top>Reserved</td> 6677 <td align=left> 6678 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6679 <tr bgcolor=WHITE> 6680 <td bgcolor=WHITE align=center valign=top>07</td> 6681 <td align=left valign=top>RW</td> 6682 <td align=left valign=top>vga_op_short_norm</td> 6683 <td align=left> 6684 This is the normal mode control for the AFE VGA output short function.<br> 6685 This control bit is used in all situations except when DSC_SM is in slicer offset cal states.<br> 6686 In order to force the 'vga output idle' control, i.e. rx_ctrl[16], write the same value to both <br> 6687   vga_op_short_norm and vga_op_short_offcal<br> 6688 Reset value is 0x0.</td></tr> 6689 <tr bgcolor=WHITE> 6690 <td bgcolor=WHITE align=center valign=top>06</td> 6691 <td align=left valign=top>RW</td> 6692 <td align=left valign=top>vga_op_short_offcal</td> 6693 <td align=left> 6694 This is the control for the AFE VGA output short function in a specific situation.<br> 6695 This control bit is used only when the DSC_SM is in slicer offset cal states.<br> 6696 In order to force the 'vga output idle' control, i.e. rx_ctrl[16], write the same value to both <br> 6697   vga_op_short_norm and vga_op_short_offcal<br> 6698 Reset value is 0x1.</td></tr> 6699 <tr bgcolor=WHITE> 6700 <td bgcolor=WHITE align=center valign=top>05:00</td> 6701 <td align=left valign=top>RW</td> 6702 <td align=left valign=top>vga_hwtune_min</td> 6703 <td align=left> 6704 This minimum limit is respected by the VGA harware adaptive loop. <br> 6705 Also used by the status logic for vga_wants_to_go_low.<br> 6706 Reset value is 0x0.</td></tr> 6707 </table><p> 6708 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6709 <hr> 6710 <b><a NAME="DSC_C_DC_SLICER_OFFSET_CTL">DSC_C_DC_SLICER_OFFSET_CTL - DC & Slicer Offset Hw-tune CTL</a></b><br> 6711 Address Offset = 32'h0000_d029<br> 6712 Physical Address = 32'h0000_d029<br> 6713 Reset Value = 16'h0001<br> 6714 Access = RW (16-bit only)<br> 6715 <table border=1 align=center width=100% cellpadding=0> 6716 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6717 <tr bgcolor=WHITE> 6718 <td bgcolor=WHITE align=center valign=top>15:12</td> 6719 <td align=left valign=top>RW</td> 6720 <td align=left valign=top>dc_offset_pattern_bit_en</td> 6721 <td align=left> 6722 pattern bit mask,   range [2:0] corresponds to indexes [2:-1] , where lower indexes are earlier in time samples<br> 6723 Reset value is 0x0.</td></tr> 6724 <tr bgcolor=WHITE> 6725 <td bgcolor=WHITE align=center valign=top>11:08</td> 6726 <td align=left valign=top>RW</td> 6727 <td align=left valign=top>dc_offset_pattern</td> 6728 <td align=left> 6729 pattern,  range [2:0] corresponds to indexes [2:-1] , where lower indexes are earlier in time samples<br> 6730 Reset value is 0x0.</td></tr> 6731 <tr bgcolor=WHITE> 6732 <td bgcolor=WHITE align=center valign=top>07</td> 6733 <td align=left valign=top>RSVD</td> 6734 <td align=left valign=top>Reserved</td> 6735 <td align=left> 6736 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 6737 <tr bgcolor=WHITE> 6738 <td bgcolor=WHITE align=center valign=top>06</td> 6739 <td align=left valign=top>RW</td> 6740 <td align=left valign=top>hw_dc_offset_grad_inv</td> 6741 <td align=left> 6742 inverts the gradient of the adaptation when 1. <br> 6743 Reset value is 0x0.</td></tr> 6744 <tr bgcolor=WHITE> 6745 <td bgcolor=WHITE align=center valign=top>05</td> 6746 <td align=left valign=top>RW</td> 6747 <td align=left valign=top>dc_offset_pattern_inv_en</td> 6748 <td align=left> 6749 When 1, the pattern is matched or the inverse of the pattern is matched. {1,0,X} <=> {0,1,X}<br> 6750 Reset value is 0x0.</td></tr> 6751 <tr bgcolor=WHITE> 6752 <td bgcolor=WHITE align=center valign=top>04</td> 6753 <td align=left valign=top>RW</td> 6754 <td align=left valign=top>dc_offset_inv</td> 6755 <td align=left> 6756 When 1, the m1 slicer is inverted. <br> 6757 Reset value is 0x0.</td></tr> 6758 <tr bgcolor=WHITE> 6759 <td bgcolor=WHITE align=center valign=top>03:02</td> 6760 <td align=left valign=top>RW</td> 6761 <td align=left valign=top>hw_dc_offset_err_gain</td> 6762 <td align=left> 6763 multiplies the error by 2^{0,1,2,3} <br> 6764 Reset value is 0x0.</td></tr> 6765 <tr bgcolor=WHITE> 6766 <td bgcolor=WHITE align=center valign=top>01</td> 6767 <td align=left valign=top>RW</td> 6768 <td align=left valign=top>hw_dc_offset_hys_en</td> 6769 <td align=left> 6770 When 1, hysteresis is enabled on the error accumulator. An underflow/overflow resets the accumulator to 0. <br> 6771 Reset value is 0x0.</td></tr> 6772 <tr bgcolor=WHITE> 6773 <td bgcolor=WHITE align=center valign=top>00</td> 6774 <td align=left valign=top>RW</td> 6775 <td align=left valign=top>dc_offset_en</td> 6776 <td align=left> 6777 Enable the DC Offset Hardware.<br> 6778 Reset value is 0x1.</td></tr> 6779 </table><p> 6780 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6781 <hr> 6782 <b><a NAME="DSC_C_SLICER_OFFSET_CONTROL">DSC_C_SLICER_OFFSET_CONTROL - Slicer Offset Hw-tune CTL</a></b><br> 6783 Address Offset = 32'h0000_d02a<br> 6784 Physical Address = 32'h0000_d02a<br> 6785 Reset Value = 16'h0001<br> 6786 Access = RW (16-bit only)<br> 6787 <table border=1 align=center width=100% cellpadding=0> 6788 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6789 <tr bgcolor=WHITE> 6790 <td bgcolor=WHITE align=center valign=top>15:08</td> 6791 <td align=left valign=top>RSVD</td> 6792 <td align=left valign=top>Reserved</td> 6793 <td align=left> 6794 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 6795 <tr bgcolor=WHITE> 6796 <td bgcolor=WHITE align=center valign=top>07</td> 6797 <td align=left valign=top>RW</td> 6798 <td align=left valign=top>hw_slicer_offset_grad_inv</td> 6799 <td align=left> 6800 When 1, this inverts the gradient of the adaptation<br> 6801 Reset value is 0x0.</td></tr> 6802 <tr bgcolor=WHITE> 6803 <td bgcolor=WHITE align=center valign=top>06</td> 6804 <td align=left valign=top>RW</td> 6805 <td align=left valign=top>hw_slicer_offset_inv_p1</td> 6806 <td align=left> 6807 When 1, this inverts the p1 being used by the slicer offset hardware<br> 6808 Reset value is 0x0.</td></tr> 6809 <tr bgcolor=WHITE> 6810 <td bgcolor=WHITE align=center valign=top>05</td> 6811 <td align=left valign=top>RW</td> 6812 <td align=left valign=top>hw_slicer_offset_inv_m1</td> 6813 <td align=left> 6814 When 1, this inverts the m1 being used by the slicer offset hardware<br> 6815 Reset value is 0x0.</td></tr> 6816 <tr bgcolor=WHITE> 6817 <td bgcolor=WHITE align=center valign=top>04</td> 6818 <td align=left valign=top>RW</td> 6819 <td align=left valign=top>hw_slicer_offset_inv_data</td> 6820 <td align=left> 6821 When 1, this inverts the data being used by the slicer offset hardware<br> 6822 Reset value is 0x0.</td></tr> 6823 <tr bgcolor=WHITE> 6824 <td bgcolor=WHITE align=center valign=top>03:02</td> 6825 <td align=left valign=top>RW</td> 6826 <td align=left valign=top>hw_slicer_offset_err_gain</td> 6827 <td align=left> 6828 Multiplies the error calculated by 2^{gain = 0,1,2,3}<br> 6829 Reset value is 0x0.</td></tr> 6830 <tr bgcolor=WHITE> 6831 <td bgcolor=WHITE align=center valign=top>01</td> 6832 <td align=left valign=top>RW</td> 6833 <td align=left valign=top>hw_slicer_offset_hys_en</td> 6834 <td align=left> 6835 When 1, hysteresis is enabled<br> 6836 Whenever the penultimate error accumulator over/under flows, it returns to 0.<br> 6837 Reset value is 0x0.</td></tr> 6838 <tr bgcolor=WHITE> 6839 <td bgcolor=WHITE align=center valign=top>00</td> 6840 <td align=left valign=top>RW</td> 6841 <td align=left valign=top>hw_slicer_offset_en</td> 6842 <td align=left> 6843 When 1, the slicer_offset hardware is enabled.<br> 6844 Reset value is 0x1.</td></tr> 6845 </table><p> 6846 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6847 <hr> 6848 <b><a NAME="DSC_C_HWTUNE_OVR_OVERRIDE">DSC_C_HWTUNE_OVR_OVERRIDE - DFE Overrude</a></b><br> 6849 Address Offset = 32'h0000_d02b<br> 6850 Physical Address = 32'h0000_d02b<br> 6851 Reset Value = 16'h0000<br> 6852 Access = RW (16-bit only)<br> 6853 <table border=1 align=center width=100% cellpadding=0> 6854 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6855 <tr bgcolor=WHITE> 6856 <td bgcolor=WHITE align=center valign=top>15</td> 6857 <td align=left valign=top>SC</td> 6858 <td align=left valign=top>hwtune_ovr_write_en</td> 6859 <td align=left> 6860 a 1 on this enables the firmware to write the tap values  <br> 6861 First set valid values on hwtune_ovr_write_tapsel and hwtune_ovr_write_val and then set this self clear bit to 1 <br> 6862 Self Clearing<br> 6863 Reset value is 0x0.</td></tr> 6864 <tr bgcolor=WHITE> 6865 <td bgcolor=WHITE align=center valign=top>14</td> 6866 <td align=left valign=top>RSVD</td> 6867 <td align=left valign=top>Reserved</td> 6868 <td align=left> 6869 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 6870 <tr bgcolor=WHITE> 6871 <td bgcolor=WHITE align=center valign=top>13:09</td> 6872 <td align=left valign=top>RW</td> 6873 <td align=left valign=top>hwtune_ovr_write_sel</td> 6874 <td align=left> 6875 'h0 = vga(see vga_update_style for translation information"<br> 6876 'h{1,2,3} = {tap 1 cmn, odd, evn}; {4,5,6,a,b} = {tap 2 cmn, odd, evn, sign even, sign odd}  <br> 6877 'h{7,8,9} = dfe tap 3 ,4, 5 <br> 6878 'hd = p1_eyediag <br> 6879 'he = vga1 ctrl, write vga_update_style to 3 <br> 6880 'hf = vga2 ctrl, write vga_update_style to 3 <br> 6881 'h10 = vga3 ctrl, write vga_update_style to 3 <br> 6882 'h11 = Data Odd  ctrl <br> 6883 'h12 = Data Even ctrl <br> 6884 'h13 = P1 Odd ctrl <br> 6885 'h14 = P1 Even ctrl <br> 6886 'h15 = M1 Odd ctrl <br> 6887 'h16 = M1 Even ctrl <br> 6888 'h17 = DC Offset ctrl <br> 6889 Reset value is 0x0.</td></tr> 6890 <tr bgcolor=WHITE> 6891 <td bgcolor=WHITE align=center valign=top>08:00</td> 6892 <td align=left valign=top>RW</td> 6893 <td align=left valign=top>hwtune_ovr_write_val</td> 6894 <td align=left> 6895 override value   <br> 6896 Please refer to AMS document for working ranges of the signals. <br> 6897 Please note that AMS document describes special encoded formats at the Analog IP boundary. <br> 6898 However, the register interface uses standard 2's complement binary notation matching the interpretation and listed below. <br> 6899 Select: Analog Control    Bits Used           Format and ranges <br> 6900 ================================================================== <br> 6901 0: VGA                         [8:3]          (0..45)  (see vga_update_style 6902 for translation)  <br> 6903 1: Dfe1 cmn                    [5:0]          (0..63)   <br> 6904 2: Dfe1 odd                    [2:0]          (0..7)    <br> 6905 3: Dfe1 even                   [2:0]          (0..7)    <br> 6906 4: Dfe2 cmn                    [4:0]          (0..31)   <br> 6907 5: Dfe2 odd                    [2:0]          (0..4)    <br> 6908 6: Dfe2 even                   [2:0]          (0..4)    <br> 6909 7: Dfe3                        [5:0]          (-31..31) signed 2s complement <br> 6910 8: Dfe4                        [4:0]          (-15..15) signed 2s complement <br> 6911 9: Dfe5                        [4:0]          (-15..15) signed 2s complement <br> 6912 A: Dfe2 sign evn               [0:0]          0: positive; 1: negative <br> 6913 B: Dfe2 sign odd               [0:0]          0: positive; 1: negative <br> 6914 D: rx_p1_eyediag               [8:3]          (-31..31) since analog treat sign = 1 as positive for 6915 this parameter; *-1 before writing.  <br> 6916 E: VGA1                        [3:0]          (0..15) unsigned  <br> 6917 F: VGA2                        [3:0]          (0..15) unsigned  <br> 6918 10:VGA3                        [3:0]          (0..31) unsigned  <br> 6919 11:Data Odd  Offset Control    [5:0]          (-31..31) signed  <br> 6920 12:Data Even Offset Control    [5:0]          (-31..31) signed  <br> 6921 13:P1 Odd  Offset Control      [5:0]          (-31..31) signed  <br> 6922 14:P1 Even Offset Control      [5:0]          (-31..31) signed  <br> 6923 15:M1 Odd  Offset Control      [5:0]          (-31..31) signed  <br> 6924 16:M1 Even Offset Control      [5:0]          (-31..31) signed  <br> 6925 17:DC Offset Control           [6:0]          (-63..63) signed  <br> 6926 Reset value is 0x0.</td></tr> 6927 </table><p> 6928 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 6929 <hr> 6930 <b><a NAME="DSC_C_VGA_CTL">DSC_C_VGA_CTL - VGA Control</a></b><br> 6931 Address Offset = 32'h0000_d02c<br> 6932 Physical Address = 32'h0000_d02c<br> 6933 Reset Value = 16'h0000<br> 6934 Access = RW (16-bit only)<br> 6935 <table border=1 align=center width=100% cellpadding=0> 6936 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 6937 <tr bgcolor=WHITE> 6938 <td bgcolor=WHITE align=center valign=top>15</td> 6939 <td align=left valign=top>RW</td> 6940 <td align=left valign=top>vga_en</td> 6941 <td align=left> 6942 Enables the tap for adaptive eq  <br> 6943 Reset value is 0x0.</td></tr> 6944 <tr bgcolor=WHITE> 6945 <td bgcolor=WHITE align=center valign=top>14:13</td> 6946 <td align=left valign=top>RW</td> 6947 <td align=left valign=top>vga_err_sel</td> 6948 <td align=left> 6949 00: emux, 01: p1, 02: m1, 03: nemux  <br> 6950 emux = d? p1:m1; nemux = ~d? p1: m1<br> 6951 Reset value is 0x0.</td></tr> 6952 <tr bgcolor=WHITE> 6953 <td bgcolor=WHITE align=center valign=top>12</td> 6954 <td align=left valign=top>RW</td> 6955 <td align=left valign=top>vga_p1_gradient_invert</td> 6956 <td align=left> 6957 invert the gradient of the inc/dec going into the vga accumulators <br> 6958 Reset value is 0x0.</td></tr> 6959 <tr bgcolor=WHITE> 6960 <td bgcolor=WHITE align=center valign=top>11:10</td> 6961 <td align=left valign=top>RW</td> 6962 <td align=left valign=top>vga_err_gain</td> 6963 <td align=left> 6964 error scaled by 2^vga_err_gain <br> 6965 Reset value is 0x0.</td></tr> 6966 <tr bgcolor=WHITE> 6967 <td bgcolor=WHITE align=center valign=top>09</td> 6968 <td align=left valign=top>RW</td> 6969 <td align=left valign=top>vga_inv_m1</td> 6970 <td align=left> 6971 invert m1 <br> 6972 Reset value is 0x0.</td></tr> 6973 <tr bgcolor=WHITE> 6974 <td bgcolor=WHITE align=center valign=top>08</td> 6975 <td align=left valign=top>RW</td> 6976 <td align=left valign=top>vga_inv_p1</td> 6977 <td align=left> 6978 invert p1 <br> 6979 Reset value is 0x0.</td></tr> 6980 <tr bgcolor=WHITE> 6981 <td bgcolor=WHITE align=center valign=top>07:06</td> 6982 <td align=left valign=top>RW</td> 6983 <td align=left valign=top>vga_update_gain</td> 6984 <td align=left> 6985 vga update gain *1,2,4,8 <br> 6986 Reset value is 0x0.</td></tr> 6987 <tr bgcolor=WHITE> 6988 <td bgcolor=WHITE align=center valign=top>05</td> 6989 <td align=left valign=top>RSVD</td> 6990 <td align=left valign=top>Reserved</td> 6991 <td align=left> 6992 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 6993 <tr bgcolor=WHITE> 6994 <td bgcolor=WHITE align=center valign=top>04</td> 6995 <td align=left valign=top>RW</td> 6996 <td align=left valign=top>vga_affected_by_dfe1</td> 6997 <td align=left> 6998 0: DFE 1 tap values cannot affect VGA adaptation <br> 6999 1: VGA lowering is not allowed if DFE tap1 wants to go negative <br> 7000 Reset value is 0x0.</td></tr> 7001 <tr bgcolor=WHITE> 7002 <td bgcolor=WHITE align=center valign=top>03:02</td> 7003 <td align=left valign=top>RW</td> 7004 <td align=left valign=top>vga_update_style</td> 7005 <td align=left> 7006 0: populate vga1 first till it is at max and then vga2 and then vga3 <br> 7007 1: populate vga3 first till it is at max and then vga2 and then vga1 <br> 7008 2: populate vga1 first by 1 and then vga2 and then vga3 (so all the vgas are balanced) <br> 7009 3: write to 3 when manually overriding to vga1, 2, or 3 independently - this disables the vga_sum from being translated into vga1,2,3 <br> 7010 Reset value is 0x0.</td></tr> 7011 <tr bgcolor=WHITE> 7012 <td bgcolor=WHITE align=center valign=top>01</td> 7013 <td align=left valign=top>RW</td> 7014 <td align=left valign=top>vga_acc_hys_en</td> 7015 <td align=left> 7016 enables hysteresis on vga accumulators  <br> 7017 Reset value is 0x0.</td></tr> 7018 <tr bgcolor=WHITE> 7019 <td bgcolor=WHITE align=center valign=top>00</td> 7020 <td align=left valign=top>RW</td> 7021 <td align=left valign=top>vga_p1_acc_clr</td> 7022 <td align=left> 7023 clears the vga and p1 related accumulators and intermediate stages <br> 7024 but not the final tap values which interface to the analog.<br> 7025 Reset value is 0x0.</td></tr> 7026 </table><p> 7027 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 7028 <hr> 7029 <b><a NAME="DSC_C_VGA_PAT_EYEDIAG_CTL">DSC_C_VGA_PAT_EYEDIAG_CTL - VGA Pat and P1 Eye Diag Control</a></b><br> 7030 Address Offset = 32'h0000_d02d<br> 7031 Physical Address = 32'h0000_d02d<br> 7032 Reset Value = 16'h0000<br> 7033 Access = RW (16-bit only)<br> 7034 <table border=1 align=center width=100% cellpadding=0> 7035 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7036 <tr bgcolor=WHITE> 7037 <td bgcolor=WHITE align=center valign=top>15</td> 7038 <td align=left valign=top>RW</td> 7039 <td align=left valign=top>p1_eyediag_en</td> 7040 <td align=left> 7041 enable p1 eye diag  <br> 7042 Reset value is 0x0.</td></tr> 7043 <tr bgcolor=WHITE> 7044 <td bgcolor=WHITE align=center valign=top>14:08</td> 7045 <td align=left valign=top>RSVD</td> 7046 <td align=left valign=top>Reserved</td> 7047 <td align=left> 7048 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7049 <tr bgcolor=WHITE> 7050 <td bgcolor=WHITE align=center valign=top>07:04</td> 7051 <td align=left valign=top>RW</td> 7052 <td align=left valign=top>vga_pattern_bit_en</td> 7053 <td align=left> 7054 pattern bit mask; range [2:0] corresponds to indexes [2:-1] , where lower indexes are earlier in time samples<br> 7055 Reset value is 0x0.</td></tr> 7056 <tr bgcolor=WHITE> 7057 <td bgcolor=WHITE align=center valign=top>03:00</td> 7058 <td align=left valign=top>RW</td> 7059 <td align=left valign=top>vga_pattern</td> 7060 <td align=left> 7061 pattern, range [2:0] corresponds to indexes [2:-1] , where lower indexes are earlier in time samples<br> 7062 Reset value is 0x0.</td></tr> 7063 </table><p> 7064 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 7065 <hr> 7066 <b><a NAME="DSC_C_P1_FRAC_OFFS_CTL">DSC_C_P1_FRAC_OFFS_CTL - P1 Fractional Offset Control</a></b><br> 7067 Address Offset = 32'h0000_d02e<br> 7068 Physical Address = 32'h0000_d02e<br> 7069 Reset Value = 16'hc400<br> 7070 Access = RW (16-bit only)<br> 7071 <table border=1 align=center width=100% cellpadding=0> 7072 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7073 <tr bgcolor=WHITE> 7074 <td bgcolor=WHITE align=center valign=top>15:10</td> 7075 <td align=left valign=top>RW</td> 7076 <td align=left valign=top>p1_hwtune_max</td> 7077 <td align=left> 7078 A signed maximum limit which the hardware loop respects during adaptation.<br> 7079 Must be greater than the p1_hwtune_min.<br> 7080 Reset value is 0x31.</td></tr> 7081 <tr bgcolor=WHITE> 7082 <td bgcolor=WHITE align=center valign=top>09</td> 7083 <td align=left valign=top>RSVD</td> 7084 <td align=left valign=top>Reserved</td> 7085 <td align=left> 7086 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7087 <tr bgcolor=WHITE> 7088 <td bgcolor=WHITE align=center valign=top>08</td> 7089 <td align=left valign=top>RW</td> 7090 <td align=left valign=top>p1_off_3levelq_en</td> 7091 <td align=left> 7092 This enables the 3 level quantizer when set +1/-1/0. Else the quantizer is 2 level +1/-1 <br> 7093 Reset value is 0x0.</td></tr> 7094 <tr bgcolor=WHITE> 7095 <td bgcolor=WHITE align=center valign=top>07</td> 7096 <td align=left valign=top>RW</td> 7097 <td align=left valign=top>p1_offset_en</td> 7098 <td align=left> 7099 Enables the Delta Sigma Fractional Offset hardware <br> 7100 Reset value is 0x0.</td></tr> 7101 <tr bgcolor=WHITE> 7102 <td bgcolor=WHITE align=center valign=top>06:00</td> 7103 <td align=left valign=top>RW</td> 7104 <td align=left valign=top>p1_offset</td> 7105 <td align=left> 7106 range is from -64 to +63. It is mapped to -64/64 to 63/64 error which gets added into the accumulator path. This adds into the +20 to -20 range error 7107 signal. <br> 7108 Reset value is 0x0.</td></tr> 7109 </table><p> 7110 <A HREF="#DSC_C Registers">Return to DSC_C: per lane register block [One Copy Per Lane] Table</A><p> 7111 <hr> 7112 <H1><a NAME="DSC_D Registers">DSC_D: per lane register block [One Copy Per Lane] Registers</a></H1> 7113 <table border=1 align=center width=100% cellpadding=0> 7114 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 7115 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 7116 <tr> 7117 <td align=center>0xD030</td><td><A HREF="#DSC_D_TRNSUM_CTL_1">DSC_D_TRNSUM_CTL_1</A><br>Trnsum Ctl 1</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">trnsum_err_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_random_tapsel_disable</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_inv_pattern_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_pattern_full_check_off</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_edge_pattern_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">trnsum_gain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_eye_closure_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_qphase_mult_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">trnsum_tap_range_sel</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td align=center>16'h0000</td></tr> 7118 <tr> 7119 <td align=center>0xD031</td><td><A HREF="#DSC_D_TRNSUM_CTL_2">DSC_D_TRNSUM_CTL_2</A><br>Trnsum Ctl 2</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">trnsum_pattern</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">trnsum_pattern_bit_en</div> </td> <td align=center>16'h0000</td></tr> 7120 <tr> 7121 <td align=center>0xD032</td><td><A HREF="#DSC_D_TRNSUM_CTL_3">DSC_D_TRNSUM_CTL_3</A><br>Trnsum Ctl 3</td><td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">trnsum_tap_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">trnsum_tap_sign</div> </td> <td align=center>16'h0000</td></tr> 7122 <tr> 7123 <td align=center>0xD033</td><td><A HREF="#DSC_D_TRNSUM_CTL_4">DSC_D_TRNSUM_CTL_4</A><br>Trnsum Ctl 4</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tdr_cycle_bin</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tdr_cycle_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tdr_trnsum_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">tdr_bit_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_unsigned_flip</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_unsigned_corr</div> </td> <td align=center>16'h0000</td></tr> 7124 <tr> 7125 <td align=center>0xD034</td><td><A HREF="#DSC_D_TRNSUM_STS_1">DSC_D_TRNSUM_STS_1</A><br>Trnsum Status 1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">trnsum_e_high</div> </td> <td align=center>16'h0000</td></tr> 7126 <tr> 7127 <td align=center>0xD035</td><td><A HREF="#DSC_D_TRNSUM_STS_2">DSC_D_TRNSUM_STS_2</A><br>Trnsum Status 2</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">trnsum_e_low</div> </td> <td align=center>16'h0000</td></tr> 7128 <tr> 7129 <td align=center>0xD036</td><td><A HREF="#DSC_D_TRNSUM_STS_3">DSC_D_TRNSUM_STS_3</A><br>Trnsum Status 3</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">trnsum_o_high</div> </td> <td align=center>16'h0000</td></tr> 7130 <tr> 7131 <td align=center>0xD037</td><td><A HREF="#DSC_D_TRNSUM_STS_4">DSC_D_TRNSUM_STS_4</A><br>Trnsum Status 4</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">trnsum_o_low</div> </td> <td align=center>16'h0000</td></tr> 7132 <tr> 7133 <td align=center>0xD038</td><td><A HREF="#DSC_D_TRNSUM_STS_5">DSC_D_TRNSUM_STS_5</A><br>Trnsum Status 5</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">trnsum_high</div> </td> <td align=center>16'h0000</td></tr> 7134 <tr> 7135 <td align=center>0xD039</td><td><A HREF="#DSC_D_TRNSUM_STS_6">DSC_D_TRNSUM_STS_6</A><br>Trnsum Status 6</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">trnsum_low</div> </td> <td align=center>16'h0000</td></tr> 7136 <tr> 7137 <td align=center>0xD03A</td><td><A HREF="#DSC_D_VGA_P1EYEDIAG_STS">DSC_D_VGA_P1EYEDIAG_STS</A><br>VGA status</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">p1_wants_to_go_high</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">p1_wants_to_go_low</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">p1_eyediag_bin</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_wants_to_go_low</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">vga_bin</div> </td> <td align=center>16'h0000</td></tr> 7138 <tr> 7139 <td align=center>0xD03B</td><td><A HREF="#DSC_D_DFE_1_STS">DSC_D_DFE_1_STS</A><br>DFE 1 status</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_1_wants_negative</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dfe_1_e</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dfe_1_o</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">dfe_1_cmn</div> </td> <td align=center>16'h0000</td></tr> 7140 <tr> 7141 <td align=center>0xD03C</td><td><A HREF="#DSC_D_DFE_2_STS">DSC_D_DFE_2_STS</A><br>DFE 2 status</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dfe_2_e</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dfe_2_o</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_se</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_2_so</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dfe_2_cmn</div> </td> <td align=center>16'h0000</td></tr> 7142 <tr> 7143 <td align=center>0xD03D</td><td><A HREF="#DSC_D_DFE_3_4_5_STS">DSC_D_DFE_3_4_5_STS</A><br>DFE 3,4,5 status</td><td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dfe_5_cmn</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dfe_4_cmn</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">dfe_3_cmn</div> </td> <td align=center>16'h0000</td></tr> 7144 <tr> 7145 <td align=center>0xD03E</td><td><A HREF="#DSC_D_VGA_TAP_BIN">DSC_D_VGA_TAP_BIN</A><br>VGA binary tap values</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vga3_ctrl_bin</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vga2_ctrl_bin</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vga1_ctrl_bin</div> </td> <td align=center>16'h0000</td></tr> 7146 </table><p> 7147 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 7148 <hr> 7149 <b><a NAME="DSC_D_TRNSUM_CTL_1">DSC_D_TRNSUM_CTL_1 - Trnsum Ctl 1</a></b><br> 7150 Address Offset = 32'h0000_d030<br> 7151 Physical Address = 32'h0000_d030<br> 7152 Reset Value = 16'h0000<br> 7153 Access = RW (16-bit only)<br> 7154 <table border=1 align=center width=100% cellpadding=0> 7155 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7156 <tr bgcolor=WHITE> 7157 <td bgcolor=WHITE align=center valign=top>15</td> 7158 <td align=left valign=top>RW</td> 7159 <td align=left valign=top>trnsum_en</td> 7160 <td align=left> 7161 enable training sum. <br> 7162 A rising edge on this signal will clear the trnsum accumulator (status) registers. <br> 7163 A probable use case would be to set it at the beginning of all measurements and clear it at the end. Clearing it should still retain the status register 7164 values. <br> 7165 Reset value is 0x0.</td></tr> 7166 <tr bgcolor=WHITE> 7167 <td bgcolor=WHITE align=center valign=top>14:12</td> 7168 <td align=left valign=top>RW</td> 7169 <td align=left valign=top>trnsum_err_sel</td> 7170 <td align=left> 7171 0: emux = d?p1:m1, 1: 1'b1, 2:m1, 3:p1, 4: d1=d?p1:~m1 <br> 7172 Trnsum sums {err*data} over certain {conditions}. This is the {err} part. <br> 7173 Reset value is 0x0.</td></tr> 7174 <tr bgcolor=WHITE> 7175 <td bgcolor=WHITE align=center valign=top>11</td> 7176 <td align=left valign=top>RW</td> 7177 <td align=left valign=top>trnsum_random_tapsel_disable</td> 7178 <td align=left> 7179 disables random data tap selection  <br> 7180 Reset value is 0x0.</td></tr> 7181 <tr bgcolor=WHITE> 7182 <td bgcolor=WHITE align=center valign=top>10</td> 7183 <td align=left valign=top>RW</td> 7184 <td align=left valign=top>trnsum_inv_pattern_en</td> 7185 <td align=left> 7186 when 1'b1, the pattern is randomly inverted for pattern match  <br> 7187 Reset value is 0x0.</td></tr> 7188 <tr bgcolor=WHITE> 7189 <td bgcolor=WHITE align=center valign=top>09</td> 7190 <td align=left valign=top>RW</td> 7191 <td align=left valign=top>trnsum_pattern_full_check_off</td> 7192 <td align=left> 7193 training only enabled for bits 2 and 13 <br> 7194 Reset value is 0x0.</td></tr> 7195 <tr bgcolor=WHITE> 7196 <td bgcolor=WHITE align=center valign=top>08</td> 7197 <td align=left valign=top>RW</td> 7198 <td align=left valign=top>trnsum_edge_pattern_en</td> 7199 <td align=left> 7200 enables pattern matching on edges {-6,-5,-4,-3,-2,-1,data,0,1,2} where a number (eg: -4) represents an edge between d[-4] and d[-3]<br> 7201 Reset value is 0x0.</td></tr> 7202 <tr bgcolor=WHITE> 7203 <td bgcolor=WHITE align=center valign=top>07:06</td> 7204 <td align=left valign=top>RW</td> 7205 <td align=left valign=top>trnsum_gain</td> 7206 <td align=left> 7207 training sum error values get *1,2,4,8 or 2^{trnsum_gain}  <br> 7208 Reset value is 0x0.</td></tr> 7209 <tr bgcolor=WHITE> 7210 <td bgcolor=WHITE align=center valign=top>05</td> 7211 <td align=left valign=top>RW</td> 7212 <td align=left valign=top>trnsum_eye_closure_en</td> 7213 <td align=left> 7214 when 1'b1, condition is anded with data!=emux <br> 7215 Trnsum sums {err*data} over certain {conditions}. This is part of the {conditions} . <br> 7216 Reset value is 0x0.</td></tr> 7217 <tr bgcolor=WHITE> 7218 <td bgcolor=WHITE align=center valign=top>04</td> 7219 <td align=left valign=top>RW</td> 7220 <td align=left valign=top>cdr_qphase_mult_en</td> 7221 <td align=left> 7222 enables qphase weighting  <br> 7223 Reset value is 0x0.</td></tr> 7224 <tr bgcolor=WHITE> 7225 <td bgcolor=WHITE align=center valign=top>03:02</td> 7226 <td align=left valign=top>RW</td> 7227 <td align=left valign=top>trnsum_tap_range_sel</td> 7228 <td align=left> 7229 0: -2 to 5; 1: 6 to 13; 2: 14 to 21; 3: all 1s are selected as data  <br> 7230 Reset value is 0x0.</td></tr> 7231 <tr bgcolor=WHITE> 7232 <td bgcolor=WHITE align=center valign=top>01:00</td> 7233 <td align=left valign=top>RSVD</td> 7234 <td align=left valign=top>Reserved</td> 7235 <td align=left> 7236 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7237 </table><p> 7238 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7239 <hr> 7240 <b><a NAME="DSC_D_TRNSUM_CTL_2">DSC_D_TRNSUM_CTL_2 - Trnsum Ctl 2</a></b><br> 7241 Address Offset = 32'h0000_d031<br> 7242 Physical Address = 32'h0000_d031<br> 7243 Reset Value = 16'h0000<br> 7244 Access = RW (16-bit only)<br> 7245 <table border=1 align=center width=100% cellpadding=0> 7246 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7247 <tr bgcolor=WHITE> 7248 <td bgcolor=WHITE align=center valign=top>15:08</td> 7249 <td align=left valign=top>RW</td> 7250 <td align=left valign=top>trnsum_pattern</td> 7251 <td align=left> 7252 trnsum pattern.  <br> 7253 Trnsum sums {err*data} over certain {conditions}. This is part of the {conditions} . <br> 7254 The data around the current bit is compared to this pattern, and if it matches, condition is 1; else 0.<br> 7255 {MSB->LSB} corresponds to {newer -> older} bits in time. <br> 7256 {7:0] correspond to {2:-5} wrt current data bit. <br> 7257 Reset value is 0x0.</td></tr> 7258 <tr bgcolor=WHITE> 7259 <td bgcolor=WHITE align=center valign=top>07:00</td> 7260 <td align=left valign=top>RW</td> 7261 <td align=left valign=top>trnsum_pattern_bit_en</td> 7262 <td align=left> 7263 trnsum pattern mask <br> 7264 When a particular location is 0; it is ignored for pattern match. <br> 7265 The bit association is the same as trnsum_pattern. <br> 7266 Reset value is 0x0.</td></tr> 7267 </table><p> 7268 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7269 <hr> 7270 <b><a NAME="DSC_D_TRNSUM_CTL_3">DSC_D_TRNSUM_CTL_3 - Trnsum Ctl 3</a></b><br> 7271 Address Offset = 32'h0000_d032<br> 7272 Physical Address = 32'h0000_d032<br> 7273 Reset Value = 16'h0000<br> 7274 Access = RW (16-bit only)<br> 7275 <table border=1 align=center width=100% cellpadding=0> 7276 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7277 <tr bgcolor=WHITE> 7278 <td bgcolor=WHITE align=center valign=top>15:08</td> 7279 <td align=left valign=top>RW</td> 7280 <td align=left valign=top>trnsum_tap_en</td> 7281 <td align=left> 7282 trnsum tap enable<br> 7283 For trnsum_tap_range_sel ==0; {15:8} correspond to {tap5, tap4, tap3, tap2, tap1, tap0, tapn1, tapn2}. <br> 7284 Multiple taps can be enabled - this means that the training will randomly switch between different paths. (the random movement across enabled taps can 7285 be disabled)<br> 7286 Reset value is 0x0.</td></tr> 7287 <tr bgcolor=WHITE> 7288 <td bgcolor=WHITE align=center valign=top>07:00</td> 7289 <td align=left valign=top>RW</td> 7290 <td align=left valign=top>trnsum_tap_sign</td> 7291 <td align=left> 7292 trnsum tap sign <br> 7293 A 1'b1 at any location, indicates that the trnsum error for that tap will be negated (*-1) before accumulation. <br> 7294 This one hot signal has similar associations as trnsum_tap_en.  <br> 7295 Reset value is 0x0.</td></tr> 7296 </table><p> 7297 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7298 <hr> 7299 <b><a NAME="DSC_D_TRNSUM_CTL_4">DSC_D_TRNSUM_CTL_4 - Trnsum Ctl 4</a></b><br> 7300 Address Offset = 32'h0000_d033<br> 7301 Physical Address = 32'h0000_d033<br> 7302 Reset Value = 16'h0000<br> 7303 Access = RW (16-bit only)<br> 7304 <table border=1 align=center width=100% cellpadding=0> 7305 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7306 <tr bgcolor=WHITE> 7307 <td bgcolor=WHITE align=center valign=top>15:12</td> 7308 <td align=left valign=top>RW</td> 7309 <td align=left valign=top>tdr_cycle_bin</td> 7310 <td align=left> 7311 valid range: from 0 to tdr_cycle_sel; this cycle the tdr is enabled on bit indicated by tdr_bit_sel  <br> 7312 Reset value is 0x0.</td></tr> 7313 <tr bgcolor=WHITE> 7314 <td bgcolor=WHITE align=center valign=top>11:08</td> 7315 <td align=left valign=top>RW</td> 7316 <td align=left valign=top>tdr_cycle_sel</td> 7317 <td align=left> 7318 the cycle counter wraps at this number  <br> 7319 Reset value is 0x0.</td></tr> 7320 <tr bgcolor=WHITE> 7321 <td bgcolor=WHITE align=center valign=top>07</td> 7322 <td align=left valign=top>RW</td> 7323 <td align=left valign=top>tdr_trnsum_en</td> 7324 <td align=left> 7325 enables the tdr feature  <br> 7326 Reset value is 0x0.</td></tr> 7327 <tr bgcolor=WHITE> 7328 <td bgcolor=WHITE align=center valign=top>06:02</td> 7329 <td align=left valign=top>RW</td> 7330 <td align=left valign=top>tdr_bit_sel</td> 7331 <td align=left> 7332 tdr bit select: range is 0 to 19  <br> 7333 Reset value is 0x0.</td></tr> 7334 <tr bgcolor=WHITE> 7335 <td bgcolor=WHITE align=center valign=top>01</td> 7336 <td align=left valign=top>RW</td> 7337 <td align=left valign=top>trnsum_unsigned_flip</td> 7338 <td align=left> 7339 when 1 along with trnsum_unsigned_corr, {0,1} - {2'b01, 2'b00}  <br> 7340 Reset value is 0x0.</td></tr> 7341 <tr bgcolor=WHITE> 7342 <td bgcolor=WHITE align=center valign=top>00</td> 7343 <td align=left valign=top>RW</td> 7344 <td align=left valign=top>trnsum_unsigned_corr</td> 7345 <td align=left> 7346 when 1; and !trnsum_unsigned_flip, correlated error after XOR {0,1} becomes signed {2'b00,2'b01}  <br> 7347 Reset value is 0x0.</td></tr> 7348 </table><p> 7349 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7350 <hr> 7351 <b><a NAME="DSC_D_TRNSUM_STS_1">DSC_D_TRNSUM_STS_1 - Trnsum Status 1</a></b><br> 7352 Address Offset = 32'h0000_d034<br> 7353 Physical Address = 32'h0000_d034<br> 7354 Reset Value = 16'h0000<br> 7355 Access = RO (16-bit only)<br> 7356 <table border=1 align=center width=100% cellpadding=0> 7357 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7358 <tr bgcolor=WHITE> 7359 <td bgcolor=WHITE align=center valign=top>15:00</td> 7360 <td align=left valign=top>RO</td> 7361 <td align=left valign=top>trnsum_e_high</td> 7362 <td align=left> 7363 trnsum accumulator for even bit locations; bits [23:8] <br> 7364 Reset value is 0x0.</td></tr> 7365 </table><p> 7366 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7367 <hr> 7368 <b><a NAME="DSC_D_TRNSUM_STS_2">DSC_D_TRNSUM_STS_2 - Trnsum Status 2</a></b><br> 7369 Address Offset = 32'h0000_d035<br> 7370 Physical Address = 32'h0000_d035<br> 7371 Reset Value = 16'h0000<br> 7372 Access = RO (16-bit only)<br> 7373 <table border=1 align=center width=100% cellpadding=0> 7374 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7375 <tr bgcolor=WHITE> 7376 <td bgcolor=WHITE align=center valign=top>15:08</td> 7377 <td align=left valign=top>RSVD</td> 7378 <td align=left valign=top>Reserved</td> 7379 <td align=left> 7380 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7381 <tr bgcolor=WHITE> 7382 <td bgcolor=WHITE align=center valign=top>07:00</td> 7383 <td align=left valign=top>RO</td> 7384 <td align=left valign=top>trnsum_e_low</td> 7385 <td align=left> 7386 trnsum accumulator for even bit locations; bits [7:0] <br> 7387 Reset value is 0x0.</td></tr> 7388 </table><p> 7389 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7390 <hr> 7391 <b><a NAME="DSC_D_TRNSUM_STS_3">DSC_D_TRNSUM_STS_3 - Trnsum Status 3</a></b><br> 7392 Address Offset = 32'h0000_d036<br> 7393 Physical Address = 32'h0000_d036<br> 7394 Reset Value = 16'h0000<br> 7395 Access = RO (16-bit only)<br> 7396 <table border=1 align=center width=100% cellpadding=0> 7397 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7398 <tr bgcolor=WHITE> 7399 <td bgcolor=WHITE align=center valign=top>15:00</td> 7400 <td align=left valign=top>RO</td> 7401 <td align=left valign=top>trnsum_o_high</td> 7402 <td align=left> 7403 trnsum accumulator for odd bit locations; bits [23:8] <br> 7404 Reset value is 0x0.</td></tr> 7405 </table><p> 7406 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7407 <hr> 7408 <b><a NAME="DSC_D_TRNSUM_STS_4">DSC_D_TRNSUM_STS_4 - Trnsum Status 4</a></b><br> 7409 Address Offset = 32'h0000_d037<br> 7410 Physical Address = 32'h0000_d037<br> 7411 Reset Value = 16'h0000<br> 7412 Access = RO (16-bit only)<br> 7413 <table border=1 align=center width=100% cellpadding=0> 7414 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7415 <tr bgcolor=WHITE> 7416 <td bgcolor=WHITE align=center valign=top>15:08</td> 7417 <td align=left valign=top>RSVD</td> 7418 <td align=left valign=top>Reserved</td> 7419 <td align=left> 7420 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7421 <tr bgcolor=WHITE> 7422 <td bgcolor=WHITE align=center valign=top>07:00</td> 7423 <td align=left valign=top>RO</td> 7424 <td align=left valign=top>trnsum_o_low</td> 7425 <td align=left> 7426 trnsum accumulator for odd bit locations; bits [7:0] <br> 7427 Reset value is 0x0.</td></tr> 7428 </table><p> 7429 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7430 <hr> 7431 <b><a NAME="DSC_D_TRNSUM_STS_5">DSC_D_TRNSUM_STS_5 - Trnsum Status 5</a></b><br> 7432 Address Offset = 32'h0000_d038<br> 7433 Physical Address = 32'h0000_d038<br> 7434 Reset Value = 16'h0000<br> 7435 Access = RO (16-bit only)<br> 7436 <table border=1 align=center width=100% cellpadding=0> 7437 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7438 <tr bgcolor=WHITE> 7439 <td bgcolor=WHITE align=center valign=top>15:00</td> 7440 <td align=left valign=top>RO</td> 7441 <td align=left valign=top>trnsum_high</td> 7442 <td align=left> 7443 trnsum accumulator (even + odd); bits [25:10] <br> 7444 Reset value is 0x0.</td></tr> 7445 </table><p> 7446 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7447 <hr> 7448 <b><a NAME="DSC_D_TRNSUM_STS_6">DSC_D_TRNSUM_STS_6 - Trnsum Status 6</a></b><br> 7449 Address Offset = 32'h0000_d039<br> 7450 Physical Address = 32'h0000_d039<br> 7451 Reset Value = 16'h0000<br> 7452 Access = RO (16-bit only)<br> 7453 <table border=1 align=center width=100% cellpadding=0> 7454 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7455 <tr bgcolor=WHITE> 7456 <td bgcolor=WHITE align=center valign=top>15:10</td> 7457 <td align=left valign=top>RSVD</td> 7458 <td align=left valign=top>Reserved</td> 7459 <td align=left> 7460 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7461 <tr bgcolor=WHITE> 7462 <td bgcolor=WHITE align=center valign=top>09:00</td> 7463 <td align=left valign=top>RO</td> 7464 <td align=left valign=top>trnsum_low</td> 7465 <td align=left> 7466 trnsum accumulator (even + odd); bits [9:0] <br> 7467 Reset value is 0x0.</td></tr> 7468 </table><p> 7469 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7470 <hr> 7471 <b><a NAME="DSC_D_VGA_P1EYEDIAG_STS">DSC_D_VGA_P1EYEDIAG_STS - VGA status</a></b><br> 7472 Address Offset = 32'h0000_d03a<br> 7473 Physical Address = 32'h0000_d03a<br> 7474 Reset Value = 16'h0000<br> 7475 Access = RO (16-bit only)<br> 7476 <table border=1 align=center width=100% cellpadding=0> 7477 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7478 <tr bgcolor=WHITE> 7479 <td bgcolor=WHITE align=center valign=top>15</td> 7480 <td align=left valign=top>RO</td> 7481 <td align=left valign=top>p1_wants_to_go_high</td> 7482 <td align=left> 7483 p1 wants to go higher than the upper limit. <br> 7484 Reset value is 0x0.</td></tr> 7485 <tr bgcolor=WHITE> 7486 <td bgcolor=WHITE align=center valign=top>14</td> 7487 <td align=left valign=top>RO</td> 7488 <td align=left valign=top>p1_wants_to_go_low</td> 7489 <td align=left> 7490 p1 wants to go lower than the lower limit. <br> 7491 Reset value is 0x0.</td></tr> 7492 <tr bgcolor=WHITE> 7493 <td bgcolor=WHITE align=center valign=top>13:08</td> 7494 <td align=left valign=top>RO</td> 7495 <td align=left valign=top>p1_eyediag_bin</td> 7496 <td align=left> 7497 p1 eyediag status <br> 7498 Reset value is 0x0.</td></tr> 7499 <tr bgcolor=WHITE> 7500 <td bgcolor=WHITE align=center valign=top>07</td> 7501 <td align=left valign=top>RSVD</td> 7502 <td align=left valign=top>Reserved</td> 7503 <td align=left> 7504 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7505 <tr bgcolor=WHITE> 7506 <td bgcolor=WHITE align=center valign=top>06</td> 7507 <td align=left valign=top>RO</td> 7508 <td align=left valign=top>vga_wants_to_go_low</td> 7509 <td align=left> 7510 vga wants to go lower than the lower limit. <br> 7511 Reset value is 0x0.</td></tr> 7512 <tr bgcolor=WHITE> 7513 <td bgcolor=WHITE align=center valign=top>05:00</td> 7514 <td align=left valign=top>RO</td> 7515 <td align=left valign=top>vga_bin</td> 7516 <td align=left> 7517 vga status <br> 7518 Reset value is 0x0.</td></tr> 7519 </table><p> 7520 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7521 <hr> 7522 <b><a NAME="DSC_D_DFE_1_STS">DSC_D_DFE_1_STS - DFE 1 status</a></b><br> 7523 Address Offset = 32'h0000_d03b<br> 7524 Physical Address = 32'h0000_d03b<br> 7525 Reset Value = 16'h0000<br> 7526 Access = RO (16-bit only)<br> 7527 <table border=1 align=center width=100% cellpadding=0> 7528 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7529 <tr bgcolor=WHITE> 7530 <td bgcolor=WHITE align=center valign=top>15</td> 7531 <td align=left valign=top>RO</td> 7532 <td align=left valign=top>dfe_1_wants_negative</td> 7533 <td align=left> 7534 dfe1 wants negative<br> 7535 Reset value is 0x0.</td></tr> 7536 <tr bgcolor=WHITE> 7537 <td bgcolor=WHITE align=center valign=top>14</td> 7538 <td align=left valign=top>RSVD</td> 7539 <td align=left valign=top>Reserved</td> 7540 <td align=left> 7541 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7542 <tr bgcolor=WHITE> 7543 <td bgcolor=WHITE align=center valign=top>13:11</td> 7544 <td align=left valign=top>RO</td> 7545 <td align=left valign=top>dfe_1_e</td> 7546 <td align=left> 7547 dfe1 even tap<br> 7548 Reset value is 0x0.</td></tr> 7549 <tr bgcolor=WHITE> 7550 <td bgcolor=WHITE align=center valign=top>10:08</td> 7551 <td align=left valign=top>RO</td> 7552 <td align=left valign=top>dfe_1_o</td> 7553 <td align=left> 7554 dfe1 odd tap <br> 7555 Reset value is 0x0.</td></tr> 7556 <tr bgcolor=WHITE> 7557 <td bgcolor=WHITE align=center valign=top>07:06</td> 7558 <td align=left valign=top>RSVD</td> 7559 <td align=left valign=top>Reserved</td> 7560 <td align=left> 7561 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7562 <tr bgcolor=WHITE> 7563 <td bgcolor=WHITE align=center valign=top>05:00</td> 7564 <td align=left valign=top>RO</td> 7565 <td align=left valign=top>dfe_1_cmn</td> 7566 <td align=left> 7567 dfe 1 cmn tap <br> 7568 Reset value is 0x0.</td></tr> 7569 </table><p> 7570 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7571 <hr> 7572 <b><a NAME="DSC_D_DFE_2_STS">DSC_D_DFE_2_STS - DFE 2 status</a></b><br> 7573 Address Offset = 32'h0000_d03c<br> 7574 Physical Address = 32'h0000_d03c<br> 7575 Reset Value = 16'h0000<br> 7576 Access = RO (16-bit only)<br> 7577 <table border=1 align=center width=100% cellpadding=0> 7578 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7579 <tr bgcolor=WHITE> 7580 <td bgcolor=WHITE align=center valign=top>15:14</td> 7581 <td align=left valign=top>RSVD</td> 7582 <td align=left valign=top>Reserved</td> 7583 <td align=left> 7584 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7585 <tr bgcolor=WHITE> 7586 <td bgcolor=WHITE align=center valign=top>13:11</td> 7587 <td align=left valign=top>RO</td> 7588 <td align=left valign=top>dfe_2_e</td> 7589 <td align=left> 7590 dfe2 even tap <br> 7591 Reset value is 0x0.</td></tr> 7592 <tr bgcolor=WHITE> 7593 <td bgcolor=WHITE align=center valign=top>10:08</td> 7594 <td align=left valign=top>RO</td> 7595 <td align=left valign=top>dfe_2_o</td> 7596 <td align=left> 7597 dfe2 odd tap <br> 7598 Reset value is 0x0.</td></tr> 7599 <tr bgcolor=WHITE> 7600 <td bgcolor=WHITE align=center valign=top>07</td> 7601 <td align=left valign=top>RSVD</td> 7602 <td align=left valign=top>Reserved</td> 7603 <td align=left> 7604 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7605 <tr bgcolor=WHITE> 7606 <td bgcolor=WHITE align=center valign=top>06</td> 7607 <td align=left valign=top>RO</td> 7608 <td align=left valign=top>dfe_2_se</td> 7609 <td align=left> 7610 dfe 2 tap sign even<br> 7611 Reset value is 0x0.</td></tr> 7612 <tr bgcolor=WHITE> 7613 <td bgcolor=WHITE align=center valign=top>05</td> 7614 <td align=left valign=top>RO</td> 7615 <td align=left valign=top>dfe_2_so</td> 7616 <td align=left> 7617 dfe 2 tap sign odd<br> 7618 Reset value is 0x0.</td></tr> 7619 <tr bgcolor=WHITE> 7620 <td bgcolor=WHITE align=center valign=top>04:00</td> 7621 <td align=left valign=top>RO</td> 7622 <td align=left valign=top>dfe_2_cmn</td> 7623 <td align=left> 7624 dfe2 cmn tap <br> 7625 Reset value is 0x0.</td></tr> 7626 </table><p> 7627 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7628 <hr> 7629 <b><a NAME="DSC_D_DFE_3_4_5_STS">DSC_D_DFE_3_4_5_STS - DFE 3,4,5 status</a></b><br> 7630 Address Offset = 32'h0000_d03d<br> 7631 Physical Address = 32'h0000_d03d<br> 7632 Reset Value = 16'h0000<br> 7633 Access = RO (16-bit only)<br> 7634 <table border=1 align=center width=100% cellpadding=0> 7635 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7636 <tr bgcolor=WHITE> 7637 <td bgcolor=WHITE align=center valign=top>15:11</td> 7638 <td align=left valign=top>RO</td> 7639 <td align=left valign=top>dfe_5_cmn</td> 7640 <td align=left> 7641 dfe 5 tap value <br> 7642 Reset value is 0x0.</td></tr> 7643 <tr bgcolor=WHITE> 7644 <td bgcolor=WHITE align=center valign=top>10:06</td> 7645 <td align=left valign=top>RO</td> 7646 <td align=left valign=top>dfe_4_cmn</td> 7647 <td align=left> 7648 dfe 4 tap value <br> 7649 Reset value is 0x0.</td></tr> 7650 <tr bgcolor=WHITE> 7651 <td bgcolor=WHITE align=center valign=top>05:00</td> 7652 <td align=left valign=top>RO</td> 7653 <td align=left valign=top>dfe_3_cmn</td> 7654 <td align=left> 7655 dfe 3 tap value <br> 7656 Reset value is 0x0.</td></tr> 7657 </table><p> 7658 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7659 <hr> 7660 <b><a NAME="DSC_D_VGA_TAP_BIN">DSC_D_VGA_TAP_BIN - VGA binary tap values</a></b><br> 7661 Address Offset = 32'h0000_d03e<br> 7662 Physical Address = 32'h0000_d03e<br> 7663 Reset Value = 16'h0000<br> 7664 Access = RO (16-bit only)<br> 7665 <table border=1 align=center width=100% cellpadding=0> 7666 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7667 <tr bgcolor=WHITE> 7668 <td bgcolor=WHITE align=center valign=top>15:12</td> 7669 <td align=left valign=top>RSVD</td> 7670 <td align=left valign=top>Reserved</td> 7671 <td align=left> 7672 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7673 <tr bgcolor=WHITE> 7674 <td bgcolor=WHITE align=center valign=top>11:08</td> 7675 <td align=left valign=top>RO</td> 7676 <td align=left valign=top>vga3_ctrl_bin</td> 7677 <td align=left> 7678 VGA 3 ctrl value. <br> 7679 Reset value is 0x0.</td></tr> 7680 <tr bgcolor=WHITE> 7681 <td bgcolor=WHITE align=center valign=top>07:04</td> 7682 <td align=left valign=top>RO</td> 7683 <td align=left valign=top>vga2_ctrl_bin</td> 7684 <td align=left> 7685 VGA 2 ctrl value. <br> 7686 Reset value is 0x0.</td></tr> 7687 <tr bgcolor=WHITE> 7688 <td bgcolor=WHITE align=center valign=top>03:00</td> 7689 <td align=left valign=top>RO</td> 7690 <td align=left valign=top>vga1_ctrl_bin</td> 7691 <td align=left> 7692 VGA 1 ctrl value. <br> 7693 Reset value is 0x0.</td></tr> 7694 </table><p> 7695 <A HREF="#DSC_D Registers">Return to DSC_D: per lane register block [One Copy Per Lane] Table</A><p> 7696 <hr> 7697 <H1><a NAME="DSC_E Registers">DSC_E: per lane register block [One Copy Per Lane] Registers</a></H1> 7698 <table border=1 align=center width=100% cellpadding=0> 7699 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 7700 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 7701 <tr> 7702 <td align=center>0xD040</td><td><A HREF="#DSC_E_CTRL">DSC_E_CTRL</A><br>dsc_e_ctrl</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pf_hiz</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">m1_thresh_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">m1_thresh_zero</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">p1_thresh_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">en_hgain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">offset_pd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pd_ch_p1</div> </td> <td align=center>16'h0030</td></tr> 7703 <tr> 7704 <td align=center>0xD041</td><td><A HREF="#DSC_E_PF_CTRL">DSC_E_PF_CTRL</A><br>dsc_e_pf_ctrl</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pf_ctrl</div> </td> <td align=center>16'h0000</td></tr> 7705 <tr> 7706 <td align=center>0xD042</td><td><A HREF="#DSC_E_PF2_LOWP_CTRL">DSC_E_PF2_LOWP_CTRL</A><br>dsc_e_pf2_lowp_ctrl</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">pf2_lowp_ctrl</div> </td> <td align=center>16'h0000</td></tr> 7707 </table><p> 7708 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 7709 <hr> 7710 <b><a NAME="DSC_E_CTRL">DSC_E_CTRL - dsc_e_ctrl</a></b><br> 7711 Address Offset = 32'h0000_d040<br> 7712 Physical Address = 32'h0000_d040<br> 7713 Reset Value = 16'h0030<br> 7714 Access = RW (16-bit only)<br> 7715 <table border=1 align=center width=100% cellpadding=0> 7716 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7717 <tr bgcolor=WHITE> 7718 <td bgcolor=WHITE align=center valign=top>15:08</td> 7719 <td align=left valign=top>RSVD</td> 7720 <td align=left valign=top>Reserved</td> 7721 <td align=left> 7722 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7723 <tr bgcolor=WHITE> 7724 <td bgcolor=WHITE align=center valign=top>07</td> 7725 <td align=left valign=top>RW</td> 7726 <td align=left valign=top>pf_hiz</td> 7727 <td align=left> 7728   When this bit=1, the zero in peaking filter<br> 7729   is shifted to higher frequency <br> 7730 Reset value is 0x0.</td></tr> 7731 <tr bgcolor=WHITE> 7732 <td bgcolor=WHITE align=center valign=top>06:05</td> 7733 <td align=left valign=top>RW</td> 7734 <td align=left valign=top>m1_thresh_sel</td> 7735 <td align=left> 7736 00, 125mV; 01, 150mV (default) <br> 7737 10, 175mV; 11, 200mV <br> 7738 Reset value is 0x1.</td></tr> 7739 <tr bgcolor=WHITE> 7740 <td bgcolor=WHITE align=center valign=top>04</td> 7741 <td align=left valign=top>RW</td> 7742 <td align=left valign=top>m1_thresh_zero</td> 7743 <td align=left> 7744 sets m1 target to 0mV for OS TR <br> 7745 Reset value is 0x1.</td></tr> 7746 <tr bgcolor=WHITE> 7747 <td bgcolor=WHITE align=center valign=top>03</td> 7748 <td align=left valign=top>RW</td> 7749 <td align=left valign=top>p1_thresh_sel</td> 7750 <td align=left> 7751 P1 slicer target level <br> 7752 Reset value is 0x0.</td></tr> 7753 <tr bgcolor=WHITE> 7754 <td bgcolor=WHITE align=center valign=top>02</td> 7755 <td align=left valign=top>RW</td> 7756 <td align=left valign=top>en_hgain</td> 7757 <td align=left> 7758 Enable high gain in DFE sum path for non-DFE mode <br> 7759 Reset value is 0x0.</td></tr> 7760 <tr bgcolor=WHITE> 7761 <td bgcolor=WHITE align=center valign=top>01</td> 7762 <td align=left valign=top>RW</td> 7763 <td align=left valign=top>offset_pd</td> 7764 <td align=left> 7765 Power down analog offset cancellation loop <br> 7766 Reset value is 0x0.</td></tr> 7767 <tr bgcolor=WHITE> 7768 <td bgcolor=WHITE align=center valign=top>00</td> 7769 <td align=left valign=top>RW</td> 7770 <td align=left valign=top>pd_ch_p1</td> 7771 <td align=left> 7772 Power down +1 channel <br> 7773 Reset value is 0x0.</td></tr> 7774 </table><p> 7775 <A HREF="#DSC_E Registers">Return to DSC_E: per lane register block [One Copy Per Lane] Table</A><p> 7776 <hr> 7777 <b><a NAME="DSC_E_PF_CTRL">DSC_E_PF_CTRL - dsc_e_pf_ctrl</a></b><br> 7778 Address Offset = 32'h0000_d041<br> 7779 Physical Address = 32'h0000_d041<br> 7780 Reset Value = 16'h0000<br> 7781 Access = RW (16-bit only)<br> 7782 <table border=1 align=center width=100% cellpadding=0> 7783 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7784 <tr bgcolor=WHITE> 7785 <td bgcolor=WHITE align=center valign=top>15:04</td> 7786 <td align=left valign=top>RSVD</td> 7787 <td align=left valign=top>Reserved</td> 7788 <td align=left> 7789 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7790 <tr bgcolor=WHITE> 7791 <td bgcolor=WHITE align=center valign=top>03:00</td> 7792 <td align=left valign=top>RW</td> 7793 <td align=left valign=top>pf_ctrl</td> 7794 <td align=left> 7795 Peaking filter control, approx 0-8 dB boost in <br> 7796 ~0.5 dB steps. Gray code<br> 7797 Reset value is 0x0.</td></tr> 7798 </table><p> 7799 <A HREF="#DSC_E Registers">Return to DSC_E: per lane register block [One Copy Per Lane] Table</A><p> 7800 <hr> 7801 <b><a NAME="DSC_E_PF2_LOWP_CTRL">DSC_E_PF2_LOWP_CTRL - dsc_e_pf2_lowp_ctrl</a></b><br> 7802 Address Offset = 32'h0000_d042<br> 7803 Physical Address = 32'h0000_d042<br> 7804 Reset Value = 16'h0000<br> 7805 Access = RW (16-bit only)<br> 7806 <table border=1 align=center width=100% cellpadding=0> 7807 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7808 <tr bgcolor=WHITE> 7809 <td bgcolor=WHITE align=center valign=top>15:03</td> 7810 <td align=left valign=top>RSVD</td> 7811 <td align=left valign=top>Reserved</td> 7812 <td align=left> 7813 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 7814 <tr bgcolor=WHITE> 7815 <td bgcolor=WHITE align=center valign=top>02:00</td> 7816 <td align=left valign=top>RW</td> 7817 <td align=left valign=top>pf2_lowp_ctrl</td> 7818 <td align=left> 7819 Low frequency peaking filter, low pass <br> 7820 000 (Gray) - min peaking<br> 7821 100 (Gray) - max peaking<br> 7822 Reset value is 0x0.</td></tr> 7823 </table><p> 7824 <A HREF="#DSC_E Registers">Return to DSC_E: per lane register block [One Copy Per Lane] Table</A><p> 7825 <hr> 7826 <H1><a NAME="TX_PI Registers">TX_PI: per lane register block [One Copy Per Lane] Registers</a></H1> 7827 <table border=1 align=center width=100% cellpadding=0> 7828 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 7829 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 7830 <tr> 7831 <td align=center>0xD070</td><td><A HREF="#TX_PI_CONTROL_0">TX_PI_CONTROL_0</A><br>TX Phase Interpolator Control 0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_frc_phase_step_mux_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">tx_pi_second_order_bwsel_integ</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">tx_pi_first_order_bwsel_integ</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_second_order_loop_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_reset_code_dbg</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_jit_ssc_freq_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_ssc_gen_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_sj_gen_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_freq_override_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_ext_ctrl_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_jitter_filter_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_en</div> </td> <td align=center>16'h0000</td></tr> 7832 <tr> 7833 <td align=center>0xD071</td><td><A HREF="#TX_PI_CONTROL_1">TX_PI_CONTROL_1</A><br>TX Phase Interpolator Control 1</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">tx_pi_freq_override_val</div> </td> <td align=center>16'h0000</td></tr> 7834 <tr> 7835 <td align=center>0xD072</td><td><A HREF="#TX_PI_CONTROL_2">TX_PI_CONTROL_2</A><br>TX Phase Interpolator Control 2</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tx_pi_jit_amp</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tx_pi_jit_freq_idx</div> </td> <td align=center>16'h0000</td></tr> 7836 <tr> 7837 <td align=center>0xD073</td><td><A HREF="#TX_PI_CONTROL_3">TX_PI_CONTROL_3</A><br>TX Phase Interpolator Control 3</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_pi_ext_phase_bwsel_integ</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tx_pi_phase_step_num</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_phase_invert</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_phase_step_dir</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_phase_strobe</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_phase_override</div> </td> <td align=center>16'h3100</td></tr> 7838 <tr> 7839 <td align=center>0xD074</td><td><A HREF="#TX_PI_CONTROL_4">TX_PI_CONTROL_4</A><br>TX Phase Interpolator Control 4</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_frz_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_frz_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_frz_frc</div> </td> <td align=center>16'h0004</td></tr> 7840 <tr> 7841 <td align=center>0xD075</td><td><A HREF="#TX_PI_CONTROL_5">TX_PI_CONTROL_5</A><br>TX Phase Interpolator Control 5</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_pd_bypass_vco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_pd_bypass_flt</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_fifo_resetb_frc_on</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_fifo_resetb</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_ext_pd_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_repeater_mode_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_hs_fifo_phserr_invert</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td align=center>16'h0004</td></tr> 7842 <tr> 7843 <td align=center>0xD078</td><td><A HREF="#TX_PI_STATUS_0">TX_PI_STATUS_0</A><br>TX Phase Interpolator Status 0</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">tx_pi_phase_cntr</div> </td> <td align=center>16'h0000</td></tr> 7844 <tr> 7845 <td align=center>0xD079</td><td><A HREF="#TX_PI_STATUS_1">TX_PI_STATUS_1</A><br>TX Phase Interpolator Status 1</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="14"><div class="HT">tx_pi_integ1_reg</div> </td> <td align=center>16'h0000</td></tr> 7846 <tr> 7847 <td align=center>0xD07A</td><td><A HREF="#TX_PI_STATUS_2">TX_PI_STATUS_2</A><br>TX Phase Interpolator Status 2</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">tx_pi_integ2_reg</div> </td> <td align=center>16'h0000</td></tr> 7848 <tr> 7849 <td align=center>0xD07B</td><td><A HREF="#TX_PI_STATUS_3">TX_PI_STATUS_3</A><br>TX Phase Interpolator Status 3</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tx_pi_phase_err</div> </td> <td align=center>16'h0000</td></tr> 7850 <tr> 7851 <td align=center>0xD07C</td><td><A HREF="#TX_PI_STATUS_4">TX_PI_STATUS_4</A><br>TX Phase Interpolator Status 4</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">st_afe_tx_fifo_resetb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_hs_fifo_phserr</div> </td> <td align=center>16'h0000</td></tr> 7852 <tr> 7853 <td align=center>0xD07D</td><td><A HREF="#TX_PI_TX_FIFO_OVFB_STATUS">TX_PI_TX_FIFO_OVFB_STATUS</A><br>TX FIFO Overflow Status</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_fifo_ovfb_fall_edge_lh</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_fifo_ovfb</div> </td> <td align=center>16'h0000</td></tr> 7854 </table><p> 7855 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 7856 <hr> 7857 <b><a NAME="TX_PI_CONTROL_0">TX_PI_CONTROL_0 - TX Phase Interpolator Control 0</a></b><br> 7858 Address Offset = 32'h0000_d070<br> 7859 Physical Address = 32'h0000_d070<br> 7860 Reset Value = 16'h0000<br> 7861 Access = RW (16-bit only)<br> 7862 <table border=1 align=center width=100% cellpadding=0> 7863 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7864 <tr bgcolor=WHITE> 7865 <td bgcolor=WHITE align=center valign=top>15</td> 7866 <td align=left valign=top>RW</td> 7867 <td align=left valign=top>tx_pi_frc_phase_step_mux_sel</td> 7868 <td align=left> 7869 Force tx_phase_step mux select to 1'b1.  <br> 7870 1'b1 - will force the dsm2_rs_3 to be selected by the tx_phase_step mux.  <br> 7871 1'b0 - back to back inc and dec from the filter will be cancelled out.  <br> 7872 Reset value is 0x0.</td></tr> 7873 <tr bgcolor=WHITE> 7874 <td bgcolor=WHITE align=center valign=top>14</td> 7875 <td align=left valign=top>RSVD</td> 7876 <td align=left valign=top>Reserved</td> 7877 <td align=left> 7878 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7879 <tr bgcolor=WHITE> 7880 <td bgcolor=WHITE align=center valign=top>13:12</td> 7881 <td align=left valign=top>RW</td> 7882 <td align=left valign=top>tx_pi_second_order_bwsel_integ</td> 7883 <td align=left> 7884 Second order bandwidth control. Valid values are 0, 1, 2 and 3. <br> 7885 Reset value is 0x0.</td></tr> 7886 <tr bgcolor=WHITE> 7887 <td bgcolor=WHITE align=center valign=top>11:10</td> 7888 <td align=left valign=top>RW</td> 7889 <td align=left valign=top>tx_pi_first_order_bwsel_integ</td> 7890 <td align=left> 7891 First order bandwidth control. <br> 7892 2'd0 -  80 KHz <br> 7893 2'd1 - 160 KHz <br> 7894 2'd2 - 321 KHz <br> 7895 2'd3 - 642 KHz <br> 7896 Reset value is 0x0.</td></tr> 7897 <tr bgcolor=WHITE> 7898 <td bgcolor=WHITE align=center valign=top>09</td> 7899 <td align=left valign=top>RSVD</td> 7900 <td align=left valign=top>Reserved</td> 7901 <td align=left> 7902 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7903 <tr bgcolor=WHITE> 7904 <td bgcolor=WHITE align=center valign=top>08</td> 7905 <td align=left valign=top>RW</td> 7906 <td align=left valign=top>tx_pi_second_order_loop_en</td> 7907 <td align=left> 7908 2nd Order Loop Enable. 1'b1 will enable the 2nd order loop of the IIR filter. 1'b0 will reset the all the flops related to the 2nd order loop. <br> 7909 This bit is only valid when tx_pi_jitter_filter_en is set to 1'b1. <br> 7910 Reset value is 0x0.</td></tr> 7911 <tr bgcolor=WHITE> 7912 <td bgcolor=WHITE align=center valign=top>07</td> 7913 <td align=left valign=top>RW</td> 7914 <td align=left valign=top>tx_pi_reset_code_dbg</td> 7915 <td align=left> 7916 Debug register.  <br> 7917 Resets the TX PI code going to AFE. This is just a debug register and is not recommended to be used during normal operation of TX PI. <br> 7918 Reset value is 0x0.</td></tr> 7919 <tr bgcolor=WHITE> 7920 <td bgcolor=WHITE align=center valign=top>06</td> 7921 <td align=left valign=top>RW</td> 7922 <td align=left valign=top>tx_pi_jit_ssc_freq_mode</td> 7923 <td align=left> 7924 SSJ Mode Select:  <br> 7925 1'b1 : 10G SSC mode and 1'b0: 6G SSC mode <br> 7926 Reset value is 0x0.</td></tr> 7927 <tr bgcolor=WHITE> 7928 <td bgcolor=WHITE align=center valign=top>05</td> 7929 <td align=left valign=top>RW</td> 7930 <td align=left valign=top>tx_pi_ssc_gen_en</td> 7931 <td align=left> 7932 Spread Spectrum Jitter (SSC) Enable. This has priority over tx_pi_ssc_gen_en if both are enabled simultaneously. <br> 7933 Reset value is 0x0.</td></tr> 7934 <tr bgcolor=WHITE> 7935 <td bgcolor=WHITE align=center valign=top>04</td> 7936 <td align=left valign=top>RW</td> 7937 <td align=left valign=top>tx_pi_sj_gen_en</td> 7938 <td align=left> 7939 Sinusoidal Jitter (SJ) Enable. This has priority over tx_pi_ssc_gen_en if both are enabled simultaneously. <br> 7940 Reset value is 0x0.</td></tr> 7941 <tr bgcolor=WHITE> 7942 <td bgcolor=WHITE align=center valign=top>03</td> 7943 <td align=left valign=top>RW</td> 7944 <td align=left valign=top>tx_pi_freq_override_en</td> 7945 <td align=left> 7946 Enable for the frequency override mode. It should be 1'b1 for fixed frequency and jitter generation modes.  <br> 7947 Reset value is 0x0.</td></tr> 7948 <tr bgcolor=WHITE> 7949 <td bgcolor=WHITE align=center valign=top>02</td> 7950 <td align=left valign=top>RW</td> 7951 <td align=left valign=top>tx_pi_ext_ctrl_en</td> 7952 <td align=left> 7953 Enable for the phase error (inc/dec) from the remote loopback ( or HS Phase FIFO in case of Repeater ) <br> 7954 Reset value is 0x0.</td></tr> 7955 <tr bgcolor=WHITE> 7956 <td bgcolor=WHITE align=center valign=top>01</td> 7957 <td align=left valign=top>RW</td> 7958 <td align=left valign=top>tx_pi_jitter_filter_en</td> 7959 <td align=left> 7960 This enables the IIR filter for the phase_sum_val logic from the CDR ( or external CDR in case of Repeater ) . <br> 7961 Reset value is 0x0.</td></tr> 7962 <tr bgcolor=WHITE> 7963 <td bgcolor=WHITE align=center valign=top>00</td> 7964 <td align=left valign=top>RW</td> 7965 <td align=left valign=top>tx_pi_en</td> 7966 <td align=left> 7967 Transmit Phase Interpolator Enable. If 1'b0 will gate off the TX PI clock and also freeze the PI code. <br> 7968 Reset value is 0x0.</td></tr> 7969 </table><p> 7970 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 7971 <hr> 7972 <b><a NAME="TX_PI_CONTROL_1">TX_PI_CONTROL_1 - TX Phase Interpolator Control 1</a></b><br> 7973 Address Offset = 32'h0000_d071<br> 7974 Physical Address = 32'h0000_d071<br> 7975 Reset Value = 16'h0000<br> 7976 Access = RW (16-bit only)<br> 7977 <table border=1 align=center width=100% cellpadding=0> 7978 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 7979 <tr bgcolor=WHITE> 7980 <td bgcolor=WHITE align=center valign=top>15</td> 7981 <td align=left valign=top>RSVD</td> 7982 <td align=left valign=top>Reserved</td> 7983 <td align=left> 7984 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 7985 <tr bgcolor=WHITE> 7986 <td bgcolor=WHITE align=center valign=top>14:00</td> 7987 <td align=left valign=top>RW</td> 7988 <td align=left valign=top>tx_pi_freq_override_val</td> 7989 <td align=left> 7990 Fixed Frequncy Override Value: Valid values are -8192 to +8192. Register tx_pi_freq_override_en should be 1'b1 to enable the Fixed Frequncy Override mode. 7991 <br> 7992 +8192 (-8192) value in this register will result into 1 TX PI phase inc (dec) every 20T tclk. This results into (1/64 * 1/20)UI phase inc (or dec) per 7993 UI = 781.25 <br> 7994 (-781.25) ppm. So 1 ppm = 10.486 value. <br> 7995 If tx_pi_jit_gen_en is set to 1'b1 then this register provides initilization value for Jitter Gen Integ Reg. Valid values in jitter generation mode are 7996 -8192 to +8191<br> 7997 Reset value is 0x0.</td></tr> 7998 </table><p> 7999 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8000 <hr> 8001 <b><a NAME="TX_PI_CONTROL_2">TX_PI_CONTROL_2 - TX Phase Interpolator Control 2</a></b><br> 8002 Address Offset = 32'h0000_d072<br> 8003 Physical Address = 32'h0000_d072<br> 8004 Reset Value = 16'h0000<br> 8005 Access = RW (16-bit only)<br> 8006 <table border=1 align=center width=100% cellpadding=0> 8007 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8008 <tr bgcolor=WHITE> 8009 <td bgcolor=WHITE align=center valign=top>15:14</td> 8010 <td align=left valign=top>RSVD</td> 8011 <td align=left valign=top>Reserved</td> 8012 <td align=left> 8013 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8014 <tr bgcolor=WHITE> 8015 <td bgcolor=WHITE align=center valign=top>13:08</td> 8016 <td align=left valign=top>RW</td> 8017 <td align=left valign=top>tx_pi_jit_amp</td> 8018 <td align=left> 8019 Jitter Generator Amplification Factor. Valid values are 0 to 63. <br> 8020 Reset value is 0x0.</td></tr> 8021 <tr bgcolor=WHITE> 8022 <td bgcolor=WHITE align=center valign=top>07:06</td> 8023 <td align=left valign=top>RSVD</td> 8024 <td align=left valign=top>Reserved</td> 8025 <td align=left> 8026 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8027 <tr bgcolor=WHITE> 8028 <td bgcolor=WHITE align=center valign=top>05:00</td> 8029 <td align=left valign=top>RW</td> 8030 <td align=left valign=top>tx_pi_jit_freq_idx</td> 8031 <td align=left> 8032 Jitter Generator Frequency Index. Valid values are from 0 to 63. Each value maps to a table into the spec which then provides various Jitter generator 8033 parameters. <br> 8034 In SJ  mode: It provides ndiv, Nsj (or Nsj_div_ndiv), sj_gain1 and sj_gain2. Refer Jitter Generator spec for the table details. <br> 8035 In SSC mode: It provides Nssc.                                        8036        Refer Jitter Generator spec for the table details. <br> 8037 Reset value is 0x0.</td></tr> 8038 </table><p> 8039 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8040 <hr> 8041 <b><a NAME="TX_PI_CONTROL_3">TX_PI_CONTROL_3 - TX Phase Interpolator Control 3</a></b><br> 8042 Address Offset = 32'h0000_d073<br> 8043 Physical Address = 32'h0000_d073<br> 8044 Reset Value = 16'h3100<br> 8045 Access = RW (16-bit only)<br> 8046 <table border=1 align=center width=100% cellpadding=0> 8047 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8048 <tr bgcolor=WHITE> 8049 <td bgcolor=WHITE align=center valign=top>15</td> 8050 <td align=left valign=top>RSVD</td> 8051 <td align=left valign=top>Reserved</td> 8052 <td align=left> 8053 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 8054 <tr bgcolor=WHITE> 8055 <td bgcolor=WHITE align=center valign=top>14:12</td> 8056 <td align=left valign=top>RW</td> 8057 <td align=left valign=top>tx_pi_ext_phase_bwsel_integ</td> 8058 <td align=left> 8059 External Phase bandwidth control. Valid values are 0 to 7. <br> 8060 Reset value is 0x3.</td></tr> 8061 <tr bgcolor=WHITE> 8062 <td bgcolor=WHITE align=center valign=top>11:08</td> 8063 <td align=left valign=top>RW</td> 8064 <td align=left valign=top>tx_pi_phase_step_num</td> 8065 <td align=left> 8066 Defines the number of phase steps movement for every manual strobe. Valid values are 1 to 15. <br> 8067 Reset value is 0x1.</td></tr> 8068 <tr bgcolor=WHITE> 8069 <td bgcolor=WHITE align=center valign=top>07:05</td> 8070 <td align=left valign=top>RSVD</td> 8071 <td align=left valign=top>Reserved</td> 8072 <td align=left> 8073 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8074 <tr bgcolor=WHITE> 8075 <td bgcolor=WHITE align=center valign=top>04</td> 8076 <td align=left valign=top>RW</td> 8077 <td align=left valign=top>tx_pi_phase_invert</td> 8078 <td align=left> 8079 1'b1 : will invert (i.e. swap) the final inc and dec before the PI code shifter logic. <br> 8080 Reset value is 0x0.</td></tr> 8081 <tr bgcolor=WHITE> 8082 <td bgcolor=WHITE align=center valign=top>03</td> 8083 <td align=left valign=top>RSVD</td> 8084 <td align=left valign=top>Reserved</td> 8085 <td align=left> 8086 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 8087 <tr bgcolor=WHITE> 8088 <td bgcolor=WHITE align=center valign=top>02</td> 8089 <td align=left valign=top>RW</td> 8090 <td align=left valign=top>tx_pi_phase_step_dir</td> 8091 <td align=left> 8092 Manual Phase Step direction. <br> 8093 1'b0: Increment <br> 8094 1'b1: Decrement <br> 8095 Reset value is 0x0.</td></tr> 8096 <tr bgcolor=WHITE> 8097 <td bgcolor=WHITE align=center valign=top>01</td> 8098 <td align=left valign=top>SC</td> 8099 <td align=left valign=top>tx_pi_phase_strobe</td> 8100 <td align=left> 8101 Manual Phase strobe. When set to 1'b1 then it will generate 1 phase step (inc/dec depending on tx_pi_phase_step_dir) or multiple phase steps if tx_pi_phase_step_osr 8102 is 1'b1. <br> 8103 If tx_pi_phase_override is 1'b0 then manual phase steps will be added with the output of the IIR filter phase steps during the time when there is no phase 8104 steps from the IIR filter. <br> 8105 Self Clearing Register. Must be polled for 1'b0 before writing it to 1'b1 again for correct Manual Phase Step Shift. <br> 8106 Reset value is 0x0.</td></tr> 8107 <tr bgcolor=WHITE> 8108 <td bgcolor=WHITE align=center valign=top>00</td> 8109 <td align=left valign=top>RW</td> 8110 <td align=left valign=top>tx_pi_phase_override</td> 8111 <td align=left> 8112 Manual Phase Override Mode. When 1'b1 the PI phase can be moved manually using registers. All the filter logic is bypassed during manual mode. <br> 8113 Reset value is 0x0.</td></tr> 8114 </table><p> 8115 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8116 <hr> 8117 <b><a NAME="TX_PI_CONTROL_4">TX_PI_CONTROL_4 - TX Phase Interpolator Control 4</a></b><br> 8118 Address Offset = 32'h0000_d074<br> 8119 Physical Address = 32'h0000_d074<br> 8120 Reset Value = 16'h0004<br> 8121 Access = RW (16-bit only)<br> 8122 <table border=1 align=center width=100% cellpadding=0> 8123 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8124 <tr bgcolor=WHITE> 8125 <td bgcolor=WHITE align=center valign=top>15:03</td> 8126 <td align=left valign=top>RSVD</td> 8127 <td align=left valign=top>Reserved</td> 8128 <td align=left> 8129 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8130 <tr bgcolor=WHITE> 8131 <td bgcolor=WHITE align=center valign=top>02</td> 8132 <td align=left valign=top>RW</td> 8133 <td align=left valign=top>tx_pi_frz_mode</td> 8134 <td align=left> 8135 Freeze Mode. 1'b1 will freeze the integ2 reg so that during the freeze, TX PI will generate the phase steps based on the integ2 freeze value. <br> 8136 1'b1 will freeze the integ2 reg so that during the freeze, TX PI will generate the phase steps based on the integ2 freeze value. <br> 8137 1'b0 will force the phase_sum_val input from the CDR loop timing path of the IIR filter to 0s which will result in slowly bringing the TX clock to 0 ppm 8138 from PLL/VCO clock. <br> 8139 Reset value is 0x1.</td></tr> 8140 <tr bgcolor=WHITE> 8141 <td bgcolor=WHITE align=center valign=top>01</td> 8142 <td align=left valign=top>RW</td> 8143 <td align=left valign=top>tx_pi_frz_frc_val</td> 8144 <td align=left> 8145 Force value for the IIR filter freeze. 1'b1 is freeze, 1'b0 is normal IIR operation. <br> 8146 Reset value is 0x0.</td></tr> 8147 <tr bgcolor=WHITE> 8148 <td bgcolor=WHITE align=center valign=top>00</td> 8149 <td align=left valign=top>RW</td> 8150 <td align=left valign=top>tx_pi_frz_frc</td> 8151 <td align=left> 8152 IIR filter freeze control by force. 1'b1 will force the freeze value indicated by tx_pi_frz_frc_val otherwise Normal IIR operation. <br> 8153 Reset value is 0x0.</td></tr> 8154 </table><p> 8155 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8156 <hr> 8157 <b><a NAME="TX_PI_CONTROL_5">TX_PI_CONTROL_5 - TX Phase Interpolator Control 5</a></b><br> 8158 Address Offset = 32'h0000_d075<br> 8159 Physical Address = 32'h0000_d075<br> 8160 Reset Value = 16'h0004<br> 8161 Access = RW (16-bit only)<br> 8162 <table border=1 align=center width=100% cellpadding=0> 8163 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8164 <tr bgcolor=WHITE> 8165 <td bgcolor=WHITE align=center valign=top>15:12</td> 8166 <td align=left valign=top>RSVD</td> 8167 <td align=left valign=top>Reserved</td> 8168 <td align=left> 8169 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8170 <tr bgcolor=WHITE> 8171 <td bgcolor=WHITE align=center valign=top>11</td> 8172 <td align=left valign=top>RW</td> 8173 <td align=left valign=top>tx_pi_pd_bypass_vco</td> 8174 <td align=left> 8175 1'b1 will enable filter and vco bypass for inc/dec indication from all sources to get a quicker phase locking time. <br> 8176 Reset value is 0x0.</td></tr> 8177 <tr bgcolor=WHITE> 8178 <td bgcolor=WHITE align=center valign=top>10</td> 8179 <td align=left valign=top>RW</td> 8180 <td align=left valign=top>tx_pi_pd_bypass_flt</td> 8181 <td align=left> 8182 1'b1 will enable filter bypass for inc/dec indication from all sources to get a quicker phase locking time. <br> 8183 Reset value is 0x0.</td></tr> 8184 <tr bgcolor=WHITE> 8185 <td bgcolor=WHITE align=center valign=top>09</td> 8186 <td align=left valign=top>RW</td> 8187 <td align=left valign=top>afe_tx_fifo_resetb_frc_on</td> 8188 <td align=left> 8189 1'b0: Normal mode where reset pin tx_fifo_resetb is controlled as per the description of the register afe_tx_fifo_resetb. <br> 8190 1'b1: force the reset pin tx_fifo_resetb to value indicated in the register afe_tx_fifo_resetb. <br> 8191 Reset value is 0x0.</td></tr> 8192 <tr bgcolor=WHITE> 8193 <td bgcolor=WHITE align=center valign=top>08</td> 8194 <td align=left valign=top>RW</td> 8195 <td align=left valign=top>afe_tx_fifo_resetb</td> 8196 <td align=left> 8197 1'b0: will assert the reset pin tx_fifo_resetb to 1'b0. <br> 8198 1'b1: Once this bit is written to 1'b1 then phase error (bit 4) from FIFO is looked for 2 transitions and then reset is de-asserted to the Phase FIFO. 8199 <br> 8200 Reset value is 0x0.</td></tr> 8201 <tr bgcolor=WHITE> 8202 <td bgcolor=WHITE align=center valign=top>07:04</td> 8203 <td align=left valign=top>RSVD</td> 8204 <td align=left valign=top>Reserved</td> 8205 <td align=left> 8206 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8207 <tr bgcolor=WHITE> 8208 <td bgcolor=WHITE align=center valign=top>03</td> 8209 <td align=left valign=top>RW</td> 8210 <td align=left valign=top>tx_pi_ext_pd_sel</td> 8211 <td align=left> 8212 Selects the source of the Phase Detector inc/dec information. <br> 8213 1'b1: Select external PD path irrespective of rg_tx_pi_repeater_mode_en <br> 8214 1'b0: Select PD path based on rg_tx_pi_repeater_mode_en <br> 8215 Reset value is 0x0.</td></tr> 8216 <tr bgcolor=WHITE> 8217 <td bgcolor=WHITE align=center valign=top>02</td> 8218 <td align=left valign=top>RW</td> 8219 <td align=left valign=top>tx_pi_repeater_mode_en</td> 8220 <td align=left> 8221 Selects the source of the Loop Timing CDR and Phase Detector inc/dec information. <br> 8222 1'b1: Select external CDR and hs_fifo_phserr[4:0] from the high speed Phase FIFO PD inside AFE for ultra-low latency path. <br> 8223 1'b0: selects the internal CDR and inc/dec from the Remote Loopback Phase Detector. <br> 8224 Reset value is 0x1.</td></tr> 8225 <tr bgcolor=WHITE> 8226 <td bgcolor=WHITE align=center valign=top>01</td> 8227 <td align=left valign=top>RW</td> 8228 <td align=left valign=top>tx_pi_hs_fifo_phserr_invert</td> 8229 <td align=left> 8230 1'b1: Inverts the hs_fifo_phserr[4:0] to invert the meaning of inc/dec from hs_fifo_phserr[4:0]. When this bit is 1'b0, 1'b1 is increment and 1'b0 is decrement. 8231 <br> 8232 Reset value is 0x0.</td></tr> 8233 <tr bgcolor=WHITE> 8234 <td bgcolor=WHITE align=center valign=top>00</td> 8235 <td align=left valign=top>RSVD</td> 8236 <td align=left valign=top>Reserved</td> 8237 <td align=left> 8238 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 8239 </table><p> 8240 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8241 <hr> 8242 <b><a NAME="TX_PI_STATUS_0">TX_PI_STATUS_0 - TX Phase Interpolator Status 0</a></b><br> 8243 Address Offset = 32'h0000_d078<br> 8244 Physical Address = 32'h0000_d078<br> 8245 Reset Value = 16'h0000<br> 8246 Access = RO (16-bit only)<br> 8247 <table border=1 align=center width=100% cellpadding=0> 8248 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8249 <tr bgcolor=WHITE> 8250 <td bgcolor=WHITE align=center valign=top>15:07</td> 8251 <td align=left valign=top>RSVD</td> 8252 <td align=left valign=top>Reserved</td> 8253 <td align=left> 8254 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8255 <tr bgcolor=WHITE> 8256 <td bgcolor=WHITE align=center valign=top>06:00</td> 8257 <td align=left valign=top>RO</td> 8258 <td align=left valign=top>tx_pi_phase_cntr</td> 8259 <td align=left> 8260 TX PI Phase Counter. Signed Value. <br> 8261 Reset value is 0x0.</td></tr> 8262 </table><p> 8263 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8264 <hr> 8265 <b><a NAME="TX_PI_STATUS_1">TX_PI_STATUS_1 - TX Phase Interpolator Status 1</a></b><br> 8266 Address Offset = 32'h0000_d079<br> 8267 Physical Address = 32'h0000_d079<br> 8268 Reset Value = 16'h0000<br> 8269 Access = RO (16-bit only)<br> 8270 <table border=1 align=center width=100% cellpadding=0> 8271 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8272 <tr bgcolor=WHITE> 8273 <td bgcolor=WHITE align=center valign=top>15:14</td> 8274 <td align=left valign=top>RSVD</td> 8275 <td align=left valign=top>Reserved</td> 8276 <td align=left> 8277 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8278 <tr bgcolor=WHITE> 8279 <td bgcolor=WHITE align=center valign=top>13:00</td> 8280 <td align=left valign=top>RO</td> 8281 <td align=left valign=top>tx_pi_integ1_reg</td> 8282 <td align=left> 8283 TX PI integ1 register. Signed Value. <br> 8284 This field is meant for internal debug only. <br> 8285 Reset value is 0x0.</td></tr> 8286 </table><p> 8287 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8288 <hr> 8289 <b><a NAME="TX_PI_STATUS_2">TX_PI_STATUS_2 - TX Phase Interpolator Status 2</a></b><br> 8290 Address Offset = 32'h0000_d07a<br> 8291 Physical Address = 32'h0000_d07a<br> 8292 Reset Value = 16'h0000<br> 8293 Access = RO (16-bit only)<br> 8294 <table border=1 align=center width=100% cellpadding=0> 8295 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8296 <tr bgcolor=WHITE> 8297 <td bgcolor=WHITE align=center valign=top>15</td> 8298 <td align=left valign=top>RSVD</td> 8299 <td align=left valign=top>Reserved</td> 8300 <td align=left> 8301 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 8302 <tr bgcolor=WHITE> 8303 <td bgcolor=WHITE align=center valign=top>14:00</td> 8304 <td align=left valign=top>RO</td> 8305 <td align=left valign=top>tx_pi_integ2_reg</td> 8306 <td align=left> 8307 TX PI integ2 register. Signed Value. Once settled, it can provide the information of the ppm on the TX clock w.r.t. PLL/VCO clock. <br> 8308 +8192 (-8192) is equal to +781.25 (-781.25) ppm which means tclk is slower (faster) w.r.t. PLL/VCO clock. <br> 8309 Divide this register value by 10.485 to get the tclk ppm. <br> 8310 Reset value is 0x0.</td></tr> 8311 </table><p> 8312 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8313 <hr> 8314 <b><a NAME="TX_PI_STATUS_3">TX_PI_STATUS_3 - TX Phase Interpolator Status 3</a></b><br> 8315 Address Offset = 32'h0000_d07b<br> 8316 Physical Address = 32'h0000_d07b<br> 8317 Reset Value = 16'h0000<br> 8318 Access = RO (16-bit only)<br> 8319 <table border=1 align=center width=100% cellpadding=0> 8320 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8321 <tr bgcolor=WHITE> 8322 <td bgcolor=WHITE align=center valign=top>15:06</td> 8323 <td align=left valign=top>RSVD</td> 8324 <td align=left valign=top>Reserved</td> 8325 <td align=left> 8326 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8327 <tr bgcolor=WHITE> 8328 <td bgcolor=WHITE align=center valign=top>05:00</td> 8329 <td align=left valign=top>RO</td> 8330 <td align=left valign=top>tx_pi_phase_err</td> 8331 <td align=left> 8332 TX PI Phase Error. Signed Value. Valid values are -8 to +8. <br> 8333 Reset value is 0x0.</td></tr> 8334 </table><p> 8335 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8336 <hr> 8337 <b><a NAME="TX_PI_STATUS_4">TX_PI_STATUS_4 - TX Phase Interpolator Status 4</a></b><br> 8338 Address Offset = 32'h0000_d07c<br> 8339 Physical Address = 32'h0000_d07c<br> 8340 Reset Value = 16'h0000<br> 8341 Access = RO (16-bit only)<br> 8342 <table border=1 align=center width=100% cellpadding=0> 8343 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8344 <tr bgcolor=WHITE> 8345 <td bgcolor=WHITE align=center valign=top>15:02</td> 8346 <td align=left valign=top>RSVD</td> 8347 <td align=left valign=top>Reserved</td> 8348 <td align=left> 8349 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8350 <tr bgcolor=WHITE> 8351 <td bgcolor=WHITE align=center valign=top>01</td> 8352 <td align=left valign=top>RO</td> 8353 <td align=left valign=top>st_afe_tx_fifo_resetb</td> 8354 <td align=left> 8355 Status of the final afe_tx_fifo_resetb signal connected to the AFE pin. <br> 8356 Reset value is 0x0.</td></tr> 8357 <tr bgcolor=WHITE> 8358 <td bgcolor=WHITE align=center valign=top>00</td> 8359 <td align=left valign=top>RO</td> 8360 <td align=left valign=top>tx_pi_hs_fifo_phserr</td> 8361 <td align=left> 8362 Bit 4 of hs_fifo_pherr. <br> 8363 Reset value is 0x0.</td></tr> 8364 </table><p> 8365 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8366 <hr> 8367 <b><a NAME="TX_PI_TX_FIFO_OVFB_STATUS">TX_PI_TX_FIFO_OVFB_STATUS - TX FIFO Overflow Status</a></b><br> 8368 Address Offset = 32'h0000_d07d<br> 8369 Physical Address = 32'h0000_d07d<br> 8370 Reset Value = 16'h0000<br> 8371 Access = RO (16-bit only)<br> 8372 <table border=1 align=center width=100% cellpadding=0> 8373 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8374 <tr bgcolor=WHITE> 8375 <td bgcolor=WHITE align=center valign=top>15:02</td> 8376 <td align=left valign=top>RSVD</td> 8377 <td align=left valign=top>Reserved</td> 8378 <td align=left> 8379 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8380 <tr bgcolor=WHITE> 8381 <td bgcolor=WHITE align=center valign=top>01</td> 8382 <td align=left valign=top>RO</td> 8383 <td align=left valign=top>tx_fifo_ovfb_fall_edge_lh</td> 8384 <td align=left> 8385 lathc high indication for 1 -> 0 transition on tx_fifo_ovfb signal from AFE/High Speed Phase FIFO. This is clear on read status.<br> 8386 Reset value is 0x0.</td></tr> 8387 <tr bgcolor=WHITE> 8388 <td bgcolor=WHITE align=center valign=top>00</td> 8389 <td align=left valign=top>RO</td> 8390 <td align=left valign=top>tx_fifo_ovfb</td> 8391 <td align=left> 8392 Indiactes live status of the tx_fifo_ovfb signal from AFE/High Speed Phase FIFO. <br> 8393 Reset value is 0x0.</td></tr> 8394 </table><p> 8395 <A HREF="#TX_PI Registers">Return to TX_PI: per lane register block [One Copy Per Lane] Table</A><p> 8396 <hr> 8397 <H1><a NAME="RXTXCOM_CKRST_CTRL Registers">RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Registers</a></H1> 8398 <table border=1 align=center width=100% cellpadding=0> 8399 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 8400 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 8401 <tr> 8402 <td align=center>0xD080</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL</A><br>RXTXCOM_OSR_MODE_CONTROL</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">osr_mode_frc</div> </td> <td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">osr_mode_frc_val</div> </td> <td align=center>16'h0000</td></tr> 8403 <tr> 8404 <td align=center>0xD081</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</A><br>RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_dp_s_rstb</div> </td> <td align=center>16'h0000</td></tr> 8405 <tr> 8406 <td align=center>0xD083</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</A><br>RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_dp_h_rstb_pkill</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_h_rstb_pkill</div> </td> <td align=center>16'h0000</td></tr> 8407 <tr> 8408 <td align=center>0xD085</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL</A><br>RXTXCOM_UC_ACK_LANE_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_lane_dp_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_lane_cfg_done</div> </td> <td align=center>16'h0000</td></tr> 8409 <tr> 8410 <td align=center>0xD086</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL</A><br>RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lane_reg_reset_occurred</div> </td> <td align=center>16'h0001</td></tr> 8411 <tr> 8412 <td align=center>0xD089</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS</A><br>RXTXCOM_LANE_DP_RESET_STATE_STATUS</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">lane_dp_reset_state</div> </td> <td align=center>16'h0007</td></tr> 8413 <tr> 8414 <td align=center>0xD08A</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL</A><br>RXTXCOM_MULTICAST_MASK_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">multicast_mask_control</div> </td> <td align=center>16'h0000</td></tr> 8415 <tr> 8416 <td align=center>0xD08B</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK">RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK</A><br>RXTXCOM_OSR_MODE_STATUS_MC_MASK</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">multicast_mask_control_status</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">osr_mode</div> </td> <td align=center>16'h0000</td></tr> 8417 <tr> 8418 <td align=center>0xD08C</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</A><br>RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">osr_mode_pin</div> </td> <td align=center>16'h0000</td></tr> 8419 <tr> 8420 <td align=center>0xD08E</td><td><A HREF="#RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL</A><br>RXTXCOM_LN_S_RSTB_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_s_rstb</div> </td> <td align=center>16'h0001</td></tr> 8421 </table><p> 8422 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 8423 <hr> 8424 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL - RXTXCOM_OSR_MODE_CONTROL</a></b><br> 8425 Address Offset = 32'h0000_d080<br> 8426 Physical Address = 32'h0000_d080<br> 8427 Reset Value = 16'h0000<br> 8428 Access = RW (16-bit only)<br> 8429 <table border=1 align=center width=100% cellpadding=0> 8430 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8431 <tr bgcolor=WHITE> 8432 <td bgcolor=WHITE align=center valign=top>15</td> 8433 <td align=left valign=top>RW</td> 8434 <td align=left valign=top>osr_mode_frc</td> 8435 <td align=left> 8436 oversample (OS) mode force. Setting this bit will allow the register value to be used for OS mode. <br> 8437 Othersise, the pin input values are used for OS mode<br> 8438 Reset value is 0x0.</td></tr> 8439 <tr bgcolor=WHITE> 8440 <td bgcolor=WHITE align=center valign=top>14:04</td> 8441 <td align=left valign=top>RSVD</td> 8442 <td align=left valign=top>Reserved</td> 8443 <td align=left> 8444 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8445 <tr bgcolor=WHITE> 8446 <td bgcolor=WHITE align=center valign=top>03:00</td> 8447 <td align=left valign=top>RW</td> 8448 <td align=left valign=top>osr_mode_frc_val</td> 8449 <td align=left> 8450 oversample (OS) mode Decoding of this register is as follows. <br> 8451     OSX1          4'd0        <br> 8452     OSX2          4'd1        <br> 8453     OSX3          4'd2        <br> 8454     OSX3P3        4'd3        <br> 8455     OSX4          4'd4        <br> 8456     OSX5          4'd5        <br> 8457     OSX7P5        4'd6        <br> 8458     OSX8          4'd7        <br> 8459     OSX8P25       4'd8        <br> 8460     OSX10         4'd9        <br> 8461 Reset value is 0x0.</td></tr> 8462 </table><p> 8463 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8464 <hr> 8465 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL - RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</a></b><br> 8466 Address Offset = 32'h0000_d081<br> 8467 Physical Address = 32'h0000_d081<br> 8468 Reset Value = 16'h0000<br> 8469 Access = RW (16-bit only)<br> 8470 <table border=1 align=center width=100% cellpadding=0> 8471 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8472 <tr bgcolor=WHITE> 8473 <td bgcolor=WHITE align=center valign=top>15:01</td> 8474 <td align=left valign=top>RSVD</td> 8475 <td align=left valign=top>Reserved</td> 8476 <td align=left> 8477 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8478 <tr bgcolor=WHITE> 8479 <td bgcolor=WHITE align=center valign=top>00</td> 8480 <td align=left valign=top>RW</td> 8481 <td align=left valign=top>ln_dp_s_rstb</td> 8482 <td align=left> 8483 Active Low Lane Soft Reset for datapath. If asserted by writing to 1'b0 will reset the datapath for a lane. <br> 8484 This soft reset is equivalent to the hard reset input pin pmd_ln_dp_h_rstb_i. <br> 8485 Reset value is 0x0.</td></tr> 8486 </table><p> 8487 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8488 <hr> 8489 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL - RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</a></b><br> 8490 Address Offset = 32'h0000_d083<br> 8491 Physical Address = 32'h0000_d083<br> 8492 Reset Value = 16'h0000<br> 8493 Access = RW (16-bit only)<br> 8494 <table border=1 align=center width=100% cellpadding=0> 8495 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8496 <tr bgcolor=WHITE> 8497 <td bgcolor=WHITE align=center valign=top>15:02</td> 8498 <td align=left valign=top>RSVD</td> 8499 <td align=left valign=top>Reserved</td> 8500 <td align=left> 8501 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8502 <tr bgcolor=WHITE> 8503 <td bgcolor=WHITE align=center valign=top>01</td> 8504 <td align=left valign=top>RW</td> 8505 <td align=left valign=top>pmd_ln_dp_h_rstb_pkill</td> 8506 <td align=left> 8507 1'b1 will disable the pmd_ln_dp_h_rstb input pin. <br> 8508 Reset value is 0x0.</td></tr> 8509 <tr bgcolor=WHITE> 8510 <td bgcolor=WHITE align=center valign=top>00</td> 8511 <td align=left valign=top>RW</td> 8512 <td align=left valign=top>pmd_ln_h_rstb_pkill</td> 8513 <td align=left> 8514 1'b1 will disable the pmd_ln_h_rstb input pin. <br> 8515 Reset value is 0x0.</td></tr> 8516 </table><p> 8517 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8518 <hr> 8519 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL - RXTXCOM_UC_ACK_LANE_CONTROL</a></b><br> 8520 Address Offset = 32'h0000_d085<br> 8521 Physical Address = 32'h0000_d085<br> 8522 Reset Value = 16'h0000<br> 8523 Access = RW (16-bit only)<br> 8524 <table border=1 align=center width=100% cellpadding=0> 8525 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8526 <tr bgcolor=WHITE> 8527 <td bgcolor=WHITE align=center valign=top>15:02</td> 8528 <td align=left valign=top>RSVD</td> 8529 <td align=left valign=top>Reserved</td> 8530 <td align=left> 8531 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8532 <tr bgcolor=WHITE> 8533 <td bgcolor=WHITE align=center valign=top>01</td> 8534 <td align=left valign=top>SC</td> 8535 <td align=left valign=top>uc_ack_lane_dp_reset</td> 8536 <td align=left> 8537 uC will write this to 1 to acknowledge a reset event after seeing "lane_dp_reset_coccured". <br> 8538 Reset value is 0x0.</td></tr> 8539 <tr bgcolor=WHITE> 8540 <td bgcolor=WHITE align=center valign=top>00</td> 8541 <td align=left valign=top>SC</td> 8542 <td align=left valign=top>uc_ack_lane_cfg_done</td> 8543 <td align=left> 8544 uC will write this to 1 to indicate it's configuration of the lane is complete. Writing to 1'b1 will  <br> 8545 should release internal hold on lane_dp_reset, only if lane_dp_reset_state is 3'b001. <br> 8546 Reset value is 0x0.</td></tr> 8547 </table><p> 8548 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8549 <hr> 8550 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL - RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL</a></b><br> 8551 Address Offset = 32'h0000_d086<br> 8552 Physical Address = 32'h0000_d086<br> 8553 Reset Value = 16'h0001<br> 8554 Access = RW (16-bit only)<br> 8555 <table border=1 align=center width=100% cellpadding=0> 8556 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8557 <tr bgcolor=WHITE> 8558 <td bgcolor=WHITE align=center valign=top>15:01</td> 8559 <td align=left valign=top>RSVD</td> 8560 <td align=left valign=top>Reserved</td> 8561 <td align=left> 8562 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8563 <tr bgcolor=WHITE> 8564 <td bgcolor=WHITE align=center valign=top>00</td> 8565 <td align=left valign=top>RW</td> 8566 <td align=left valign=top>lane_reg_reset_occurred</td> 8567 <td align=left> 8568 Set to 1'b1 upon lane level register reset and remains so until cleared by register write from uC. <br> 8569 Reset value is 0x1.</td></tr> 8570 </table><p> 8571 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8572 <hr> 8573 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS">RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS - RXTXCOM_LANE_DP_RESET_STATE_STATUS</a></b><br> 8574 Address Offset = 32'h0000_d089<br> 8575 Physical Address = 32'h0000_d089<br> 8576 Reset Value = 16'h0007<br> 8577 Access = RO (16-bit only)<br> 8578 <table border=1 align=center width=100% cellpadding=0> 8579 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8580 <tr bgcolor=WHITE> 8581 <td bgcolor=WHITE align=center valign=top>15:03</td> 8582 <td align=left valign=top>RSVD</td> 8583 <td align=left valign=top>Reserved</td> 8584 <td align=left> 8585 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8586 <tr bgcolor=WHITE> 8587 <td bgcolor=WHITE align=center valign=top>02:00</td> 8588 <td align=left valign=top>RO</td> 8589 <td align=left valign=top>lane_dp_reset_state</td> 8590 <td align=left> 8591 Bit 2: lane_dp_reset_active   : Set to 1'b1 whenenver lane_dp_reset is currently requested through any register or pin controls.  <br> 8592 Bit 1: lane_dp_reset_occurred : Set to 1'b1 whenenver lane_dp_reset is currently requested through any register or pin controls and is latched high.  8593 <br> 8594 Bit 0: lane_dp_reset_held     : Set to 1'b1 whenenver lane_dp_reset is internally held. Cleared to 1'b0, only if lane_dp_reset_state==001 8595 and uc_ack_lane_cfg_done == 1. <br> 8596 Reset value is 0x7.</td></tr> 8597 </table><p> 8598 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8599 <hr> 8600 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_MULTICAST_MASK_CONTROL - RXTXCOM_MULTICAST_MASK_CONTROL</a></b><br> 8601 Address Offset = 32'h0000_d08a<br> 8602 Physical Address = 32'h0000_d08a<br> 8603 Reset Value = 16'h0000<br> 8604 Access = RW (16-bit only)<br> 8605 <table border=1 align=center width=100% cellpadding=0> 8606 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8607 <tr bgcolor=WHITE> 8608 <td bgcolor=WHITE align=center valign=top>15:01</td> 8609 <td align=left valign=top>RSVD</td> 8610 <td align=left valign=top>Reserved</td> 8611 <td align=left> 8612 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8613 <tr bgcolor=WHITE> 8614 <td bgcolor=WHITE align=center valign=top>00</td> 8615 <td align=left valign=top>WO</td> 8616 <td align=left valign=top>multicast_mask_control</td> 8617 <td align=left> 8618 This masks the lane from a broadcast or multicast write operation. <br> 8619 Reset value is 0x0.</td></tr> 8620 </table><p> 8621 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8622 <hr> 8623 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK">RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK - RXTXCOM_OSR_MODE_STATUS_MC_MASK</a></b><br> 8624 Address Offset = 32'h0000_d08b<br> 8625 Physical Address = 32'h0000_d08b<br> 8626 Reset Value = 16'h0000<br> 8627 Access = RO (16-bit only)<br> 8628 <table border=1 align=center width=100% cellpadding=0> 8629 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8630 <tr bgcolor=WHITE> 8631 <td bgcolor=WHITE align=center valign=top>15:05</td> 8632 <td align=left valign=top>RSVD</td> 8633 <td align=left valign=top>Reserved</td> 8634 <td align=left> 8635 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8636 <tr bgcolor=WHITE> 8637 <td bgcolor=WHITE align=center valign=top>04</td> 8638 <td align=left valign=top>RO</td> 8639 <td align=left valign=top>multicast_mask_control_status</td> 8640 <td align=left> 8641 Status of multicast mask control for masking lane from multicast write operation. <br> 8642 Reset value is 0x0.</td></tr> 8643 <tr bgcolor=WHITE> 8644 <td bgcolor=WHITE align=center valign=top>03:00</td> 8645 <td align=left valign=top>RO</td> 8646 <td align=left valign=top>osr_mode</td> 8647 <td align=left> 8648 OSR Mode status after the mux. <br> 8649 OSR Mode status after the osr_mode_frc/frc_val mux. <br> 8650 Decoding of this register is as follows. <br> 8651     OSX1          4'd0        <br> 8652     OSX2          4'd1        <br> 8653     OSX3          4'd2        <br> 8654     OSX3P3        4'd3        <br> 8655     OSX4          4'd4        <br> 8656     OSX5          4'd5        <br> 8657     OSX7P5        4'd6        <br> 8658     OSX8          4'd7        <br> 8659     OSX8P25       4'd8        <br> 8660     OSX10         4'd9        <br> 8661 Reset value is 0x0.</td></tr> 8662 </table><p> 8663 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8664 <hr> 8665 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS - RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</a></b><br> 8666 Address Offset = 32'h0000_d08c<br> 8667 Physical Address = 32'h0000_d08c<br> 8668 Reset Value = 16'h0000<br> 8669 Access = RO (16-bit only)<br> 8670 <table border=1 align=center width=100% cellpadding=0> 8671 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8672 <tr bgcolor=WHITE> 8673 <td bgcolor=WHITE align=center valign=top>15:04</td> 8674 <td align=left valign=top>RSVD</td> 8675 <td align=left valign=top>Reserved</td> 8676 <td align=left> 8677 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8678 <tr bgcolor=WHITE> 8679 <td bgcolor=WHITE align=center valign=top>03:00</td> 8680 <td align=left valign=top>RO</td> 8681 <td align=left valign=top>osr_mode_pin</td> 8682 <td align=left> 8683 Indicates the status of the pmd_osr_mode input pin. <br> 8684 Decoding of pmd_osr_mode[3:0] pin and osr_mode registers are as follows. <br> 8685     OSX1          4'd0        <br> 8686     OSX2          4'd1        <br> 8687     OSX3          4'd2        <br> 8688     OSX3P3        4'd3        <br> 8689     OSX4          4'd4        <br> 8690     OSX5          4'd5        <br> 8691     OSX7P5        4'd6        <br> 8692     OSX8          4'd7        <br> 8693     OSX8P25       4'd8        <br> 8694     OSX10         4'd9        <br> 8695 Reset value is 0x0.</td></tr> 8696 </table><p> 8697 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8698 <hr> 8699 <b><a NAME="RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL">RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL - RXTXCOM_LN_S_RSTB_CONTROL</a></b><br> 8700 Address Offset = 32'h0000_d08e<br> 8701 Physical Address = 32'h0000_d08e<br> 8702 Reset Value = 16'h0001<br> 8703 Access = RW (16-bit only)<br> 8704 <table border=1 align=center width=100% cellpadding=0> 8705 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8706 <tr bgcolor=WHITE> 8707 <td bgcolor=WHITE align=center valign=top>15:01</td> 8708 <td align=left valign=top>RSVD</td> 8709 <td align=left valign=top>Reserved</td> 8710 <td align=left> 8711 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8712 <tr bgcolor=WHITE> 8713 <td bgcolor=WHITE align=center valign=top>00</td> 8714 <td align=left valign=top>RW</td> 8715 <td align=left valign=top>ln_s_rstb</td> 8716 <td align=left> 8717 Active Low Lane Soft Reset. If asserted by writing to 1'b0 will reset the registers and datapath for a lane. <br> 8718 This soft reset is equivalent to the hard reset input pin pmd_ln_h_rstb_i. <br> 8719 Reset value is 0x1.</td></tr> 8720 </table><p> 8721 <A HREF="#RXTXCOM_CKRST_CTRL Registers">Return to RXTXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane]. This is a virtual register block that broadcasts writes and reads to rxcom_ckrst_ctrl and txcom_ckrst_ctrl blocks. Table</A><p> 8722 <hr> 8723 <H1><a NAME="AMS_RX Registers">AMS_RX: per lane register block [One Copy Per Lane] Registers</a></H1> 8724 <table border=1 align=center width=100% cellpadding=0> 8725 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 8726 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 8727 <tr> 8728 <td align=center>0xD090</td><td><A HREF="#AMS_RX_RX_CTRL_0">AMS_RX_RX_CTRL_0</A><br>RX_CTRL_0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_term_lowzvdd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_term_lowzgnd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_term_cmult_ena</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_term_cm_ena</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_rx_en_rxck_test</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_rxck_testport</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_spare_0_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_rcm_sum</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_sigdet_bypass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_sigdet_pwrdn</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_cm_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_sum_pseudo_diff</div> </td> <td align=center>16'h1c00</td></tr> 8729 <tr> 8730 <td align=center>0xD091</td><td><A HREF="#AMS_RX_RX_CTRL_1">AMS_RX_RX_CTRL_1</A><br>RX_CTRL_1</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_dfe_2</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_spare_1_0</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_pi</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_ctle</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_vga_en_hgain</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_vga_out_idle</div> </td> <td align=center>16'h1048</td></tr> 8731 <tr> 8732 <td align=center>0xD092</td><td><A HREF="#AMS_RX_RX_CTRL_2">AMS_RX_RX_CTRL_2</A><br>RX_CTRL_2</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_rx_spare_2_0</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_rx_en_dfe_tap_fb</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_vga</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_dfe_summer</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_dfe_1</div> </td> <td align=center>16'h7e92</td></tr> 8733 <tr> 8734 <td align=center>0xD093</td><td><A HREF="#AMS_RX_RX_CTRL_3">AMS_RX_RX_CTRL_3</A><br>RX_CTRL_3</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_ll_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_seli1p25dfe</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_i4deadzone</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_sigdet</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_vddr_afe</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_os2x_mode_even_odd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_dfe_os2x_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_20b_demux</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_clk16</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_clk33</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_vcctrl</div> </td> <td align=center>16'h288f</td></tr> 8735 <tr> 8736 <td align=center>0xD094</td><td><A HREF="#AMS_RX_RX_CTRL_4">AMS_RX_RX_CTRL_4</A><br>RX_CTRL_4</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_vga_pon</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_oc_2x</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_spare_4_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_recclkdiv</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_rx_div3o4o5</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_rx_recclkdiv</div> </td> <td align=center>16'h0020</td></tr> 8737 <tr> 8738 <td align=center>0xD095</td><td><A HREF="#AMS_RX_RX_CTRL_5">AMS_RX_RX_CTRL_5</A><br>RX_CTRL_5</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_dcc2_phase_flip</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_slcr_calib_range_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_pi_pd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_dcc1_phase_flip</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_dfeclk</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_ctle_gain_ctrl</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_rx_curr_in_offset</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_pon</div> </td> <td align=center>16'h0fa0</td></tr> 8739 <tr> 8740 <td align=center>0xD096</td><td><A HREF="#AMS_RX_RX_CTRL_6">AMS_RX_RX_CTRL_6</A><br>RX_CTRL_6</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_rx_sigdet_offset_correction_pos</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_sigdet_calibration_select</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_sum_gain_ctrl</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_en_sigdet_calib</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_hiz_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_m1_sign</div> </td> <td align=center>16'h1078</td></tr> 8741 <tr> 8742 <td align=center>0xD097</td><td><A HREF="#AMS_RX_RX_CTRL_7">AMS_RX_RX_CTRL_7</A><br>RX_CTRL_7</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_spare_7_0</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_rx_sigdet_threshold</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_rx_sigdet_offset_correction_neg</div> </td> <td align=center>16'h0130</td></tr> 8743 <tr> 8744 <td align=center>0xD098</td><td><A HREF="#AMS_RX_RX_INT">AMS_RX_RX_INT</A><br>RX_CTRL_INT</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_rxpon_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_rx_vgapon_sel</div> </td> <td align=center>16'h0000</td></tr> 8745 <tr> 8746 <td align=center>0xD099</td><td><A HREF="#AMS_RX_RX_STS">AMS_RX_RX_STS</A><br>RX_STS</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_vgapon_mux</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_rx_rxpon_mux</div> </td> <td align=center>16'h0000</td></tr> 8747 </table><p> 8748 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 8749 <hr> 8750 <b><a NAME="AMS_RX_RX_CTRL_0">AMS_RX_RX_CTRL_0 - RX_CTRL_0</a></b><br> 8751 Address Offset = 32'h0000_d090<br> 8752 Physical Address = 32'h0000_d090<br> 8753 Reset Value = 16'h1c00<br> 8754 Access = RW (16-bit only)<br> 8755 <table border=1 align=center width=100% cellpadding=0> 8756 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8757 <tr bgcolor=WHITE> 8758 <td bgcolor=WHITE align=center valign=top>15</td> 8759 <td align=left valign=top>RW</td> 8760 <td align=left valign=top>ams_rx_term_lowzvdd</td> 8761 <td align=left> 8762 1: Input common mode DC value VDD, Term_lowZvdd in AMS amsbus ctrl_out  15:15 <br> 8763 Reset value is 0x0.</td></tr> 8764 <tr bgcolor=WHITE> 8765 <td bgcolor=WHITE align=center valign=top>14</td> 8766 <td align=left valign=top>RW</td> 8767 <td align=left valign=top>ams_rx_term_lowzgnd</td> 8768 <td align=left> 8769   1: Input common mode DC value 0, Term_lowZgnd in AMS amsbus ctrl_out  14:14 <br> 8770 Reset value is 0x0.</td></tr> 8771 <tr bgcolor=WHITE> 8772 <td bgcolor=WHITE align=center valign=top>13</td> 8773 <td align=left valign=top>RW</td> 8774 <td align=left valign=top>ams_rx_term_cmult_ena</td> 8775 <td align=left> 8776   1: Common mode capacitor multiplier active ON, Term_CMULT_ena in AMS amsbus ctrl_out  13:13 <br> 8777 Reset value is 0x0.</td></tr> 8778 <tr bgcolor=WHITE> 8779 <td bgcolor=WHITE align=center valign=top>12</td> 8780 <td align=left valign=top>RW</td> 8781 <td align=left valign=top>ams_rx_term_cm_ena</td> 8782 <td align=left> 8783   0: Common mode DC floating, 1: Common mode connected to DC voltage, Term_CM_ena in AMS amsbus ctrl_out  12:12 <br> 8784 Reset value is 0x1.</td></tr> 8785 <tr bgcolor=WHITE> 8786 <td bgcolor=WHITE align=center valign=top>11:10</td> 8787 <td align=left valign=top>RW</td> 8788 <td align=left valign=top>ams_rx_en_rxck_test</td> 8789 <td align=left> 8790   RX Test Port Output Rate Selection, En_rxck_test in AMS amsbus ctrl_out  11:10 <br> 8791 Reset value is 0x3.</td></tr> 8792 <tr bgcolor=WHITE> 8793 <td bgcolor=WHITE align=center valign=top>09</td> 8794 <td align=left valign=top>RW</td> 8795 <td align=left valign=top>ams_rx_en_rxck_testport</td> 8796 <td align=left> 8797   test port enable.1: enables the test clock outp/n sent to PLL, En_rxck_testport in AMS amsbus ctrl_out  9:9 <br> 8798 Reset value is 0x0.</td></tr> 8799 <tr bgcolor=WHITE> 8800 <td bgcolor=WHITE align=center valign=top>08:05</td> 8801 <td align=left valign=top>RW</td> 8802 <td align=left valign=top>ams_rx_spare_0_2</td> 8803 <td align=left> 8804   ams reserved[8:5] amsbus ctrl_out  8:5 <br> 8805 Reset value is 0x0.</td></tr> 8806 <tr bgcolor=WHITE> 8807 <td bgcolor=WHITE align=center valign=top>04</td> 8808 <td align=left valign=top>RW</td> 8809 <td align=left valign=top>ams_rx_rcm_sum</td> 8810 <td align=left> 8811   0: (Default) All the fixed summer load is connected to Vcm, 1: 500-Ohms of the fixed Summer load is connected to Vdd amsbus ctrl_out  4:4 <br> 8812 Reset value is 0x0.</td></tr> 8813 <tr bgcolor=WHITE> 8814 <td bgcolor=WHITE align=center valign=top>03</td> 8815 <td align=left valign=top>RW</td> 8816 <td align=left valign=top>ams_rx_sigdet_bypass</td> 8817 <td align=left> 8818   1: Bypass SigDetect output and send 1 at SigDetect output, Rx_sigdet_bypass in AMS amsbus ctrl_out  3:3 <br> 8819 Reset value is 0x0.</td></tr> 8820 <tr bgcolor=WHITE> 8821 <td bgcolor=WHITE align=center valign=top>02</td> 8822 <td align=left valign=top>RW</td> 8823 <td align=left valign=top>ams_rx_sigdet_pwrdn</td> 8824 <td align=left> 8825   Signal Detect Power Down, Rx_sigdet_pwrdn in AMS amsbus ctrl_out  2:2 <br> 8826 Reset value is 0x0.</td></tr> 8827 <tr bgcolor=WHITE> 8828 <td bgcolor=WHITE align=center valign=top>01</td> 8829 <td align=left valign=top>RW</td> 8830 <td align=left valign=top>ams_rx_cm_sel</td> 8831 <td align=left> 8832   0: Input CM of the CTLE is coming from the Const Gm bias, 1: Input CM of the CTLE is coming from a resistor ladder equal to 5/7*Vdd amsbus ctrl_out  8833 1:1 <br> 8834 Reset value is 0x0.</td></tr> 8835 <tr bgcolor=WHITE> 8836 <td bgcolor=WHITE align=center valign=top>00</td> 8837 <td align=left valign=top>RW</td> 8838 <td align=left valign=top>ams_rx_sum_pseudo_diff</td> 8839 <td align=left> 8840   0: Tail device in the summer is biased by constant-gm bias, 1: Tail device in the summer is pulled up to Vdd amsbus ctrl_out  0:0 <br> 8841 Reset value is 0x0.</td></tr> 8842 </table><p> 8843 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 8844 <hr> 8845 <b><a NAME="AMS_RX_RX_CTRL_1">AMS_RX_RX_CTRL_1 - RX_CTRL_1</a></b><br> 8846 Address Offset = 32'h0000_d091<br> 8847 Physical Address = 32'h0000_d091<br> 8848 Reset Value = 16'h1048<br> 8849 Access = RW (16-bit only)<br> 8850 <table border=1 align=center width=100% cellpadding=0> 8851 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8852 <tr bgcolor=WHITE> 8853 <td bgcolor=WHITE align=center valign=top>15:14</td> 8854 <td align=left valign=top>RSVD</td> 8855 <td align=left valign=top>Reserved</td> 8856 <td align=left> 8857 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 8858 <tr bgcolor=WHITE> 8859 <td bgcolor=WHITE align=center valign=top>13:11</td> 8860 <td align=left valign=top>RW</td> 8861 <td align=left valign=top>ams_rx_curr_dfe_2</td> 8862 <td align=left> 8863   Controls the current biasing for DFE TAPS amsbus ctrl_out  29:27 <br> 8864 Reset value is 0x2.</td></tr> 8865 <tr bgcolor=WHITE> 8866 <td bgcolor=WHITE align=center valign=top>10:08</td> 8867 <td align=left valign=top>RW</td> 8868 <td align=left valign=top>ams_rx_spare_1_0</td> 8869 <td align=left> 8870   ams reserved[26:24] amsbus ctrl_out  26:24 <br> 8871 Reset value is 0x0.</td></tr> 8872 <tr bgcolor=WHITE> 8873 <td bgcolor=WHITE align=center valign=top>07:05</td> 8874 <td align=left valign=top>RW</td> 8875 <td align=left valign=top>ams_rx_curr_pi</td> 8876 <td align=left> 8877   Controls the current biasing for the RX Phase Interpolators (Peak, Zero, Eyemon), Curr_pi in AMS amsbus ctrl_out  23:21 <br> 8878 Reset value is 0x2.</td></tr> 8879 <tr bgcolor=WHITE> 8880 <td bgcolor=WHITE align=center valign=top>04:02</td> 8881 <td align=left valign=top>RW</td> 8882 <td align=left valign=top>ams_rx_curr_ctle</td> 8883 <td align=left> 8884   Controls the current biasing for the RX CTLE amsbus ctrl_out  20:18 <br> 8885 Reset value is 0x2.</td></tr> 8886 <tr bgcolor=WHITE> 8887 <td bgcolor=WHITE align=center valign=top>01</td> 8888 <td align=left valign=top>RW</td> 8889 <td align=left valign=top>ams_rx_vga_en_hgain</td> 8890 <td align=left> 8891   Increases the gain of the VGA amsbus ctrl_out  17:17 <br> 8892 Reset value is 0x0.</td></tr> 8893 <tr bgcolor=WHITE> 8894 <td bgcolor=WHITE align=center valign=top>00</td> 8895 <td align=left valign=top>RW</td> 8896 <td align=left valign=top>ams_rx_vga_out_idle</td> 8897 <td align=left> 8898   Not use. Please use vga_op_short from dsc register amsbus ctrl_out  16:16 <br> 8899 Reset value is 0x0.</td></tr> 8900 </table><p> 8901 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 8902 <hr> 8903 <b><a NAME="AMS_RX_RX_CTRL_2">AMS_RX_RX_CTRL_2 - RX_CTRL_2</a></b><br> 8904 Address Offset = 32'h0000_d092<br> 8905 Physical Address = 32'h0000_d092<br> 8906 Reset Value = 16'h7e92<br> 8907 Access = RW (16-bit only)<br> 8908 <table border=1 align=center width=100% cellpadding=0> 8909 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8910 <tr bgcolor=WHITE> 8911 <td bgcolor=WHITE align=center valign=top>15:14</td> 8912 <td align=left valign=top>RW</td> 8913 <td align=left valign=top>ams_rx_spare_2_0</td> 8914 <td align=left> 8915   ams reserved[45:44] amsbus ctrl_out  45:44 <br> 8916 Reset value is 0x1.</td></tr> 8917 <tr bgcolor=WHITE> 8918 <td bgcolor=WHITE align=center valign=top>13:09</td> 8919 <td align=left valign=top>RW</td> 8920 <td align=left valign=top>ams_rx_en_dfe_tap_fb</td> 8921 <td align=left> 8922   Enable the Feedback to control each tap of dfe amsbus ctrl_out  43:39 <br> 8923 Reset value is 0x1f.</td></tr> 8924 <tr bgcolor=WHITE> 8925 <td bgcolor=WHITE align=center valign=top>08:06</td> 8926 <td align=left valign=top>RW</td> 8927 <td align=left valign=top>ams_rx_curr_vga</td> 8928 <td align=left> 8929   Controls the current biasing for VGA amsbus ctrl_out  38:36 <br> 8930 Reset value is 0x2.</td></tr> 8931 <tr bgcolor=WHITE> 8932 <td bgcolor=WHITE align=center valign=top>05:03</td> 8933 <td align=left valign=top>RW</td> 8934 <td align=left valign=top>ams_rx_curr_dfe_summer</td> 8935 <td align=left> 8936   Controls the current biasing for DFE Summer amsbus ctrl_out  35:33 <br> 8937 Reset value is 0x2.</td></tr> 8938 <tr bgcolor=WHITE> 8939 <td bgcolor=WHITE align=center valign=top>02:00</td> 8940 <td align=left valign=top>RW</td> 8941 <td align=left valign=top>ams_rx_curr_dfe_1</td> 8942 <td align=left> 8943   Controls the current biasing for DFE TAPS amsbus ctrl_out  32:30 <br> 8944 Reset value is 0x2.</td></tr> 8945 </table><p> 8946 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 8947 <hr> 8948 <b><a NAME="AMS_RX_RX_CTRL_3">AMS_RX_RX_CTRL_3 - RX_CTRL_3</a></b><br> 8949 Address Offset = 32'h0000_d093<br> 8950 Physical Address = 32'h0000_d093<br> 8951 Reset Value = 16'h288f<br> 8952 Access = RW (16-bit only)<br> 8953 <table border=1 align=center width=100% cellpadding=0> 8954 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 8955 <tr bgcolor=WHITE> 8956 <td bgcolor=WHITE align=center valign=top>15</td> 8957 <td align=left valign=top>RSVD</td> 8958 <td align=left valign=top>Reserved</td> 8959 <td align=left> 8960 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 8961 <tr bgcolor=WHITE> 8962 <td bgcolor=WHITE align=center valign=top>14</td> 8963 <td align=left valign=top>RW</td> 8964 <td align=left valign=top>ams_rx_ll_en</td> 8965 <td align=left> 8966   1: Low latency mode enabled in RX, LowLatency_ena in AMS amsbus ctrl_out  60:60 <br> 8967 Reset value is 0x0.</td></tr> 8968 <tr bgcolor=WHITE> 8969 <td bgcolor=WHITE align=center valign=top>13</td> 8970 <td align=left valign=top>RW</td> 8971 <td align=left valign=top>ams_rx_seli1p25dfe</td> 8972 <td align=left> 8973   1: increase all DFE tap current 1.25x, sel_i1p25dfe in AMS amsbus ctrl_out  59:59 <br> 8974 Reset value is 0x1.</td></tr> 8975 <tr bgcolor=WHITE> 8976 <td bgcolor=WHITE align=center valign=top>12</td> 8977 <td align=left valign=top>RW</td> 8978 <td align=left valign=top>ams_rx_i4deadzone</td> 8979 <td align=left> 8980   1 = adds additional half LSB current to each DFE tap 1-5 amsbus ctrl_out  58:58 <br> 8981 Reset value is 0x0.</td></tr> 8982 <tr bgcolor=WHITE> 8983 <td bgcolor=WHITE align=center valign=top>11:09</td> 8984 <td align=left valign=top>RW</td> 8985 <td align=left valign=top>ams_rx_curr_sigdet</td> 8986 <td align=left> 8987   Current control for the Signal detect, Curr_sigdet in AMS amsbus ctrl_out  57:55 <br> 8988 Reset value is 0x4.</td></tr> 8989 <tr bgcolor=WHITE> 8990 <td bgcolor=WHITE align=center valign=top>08:06</td> 8991 <td align=left valign=top>RW</td> 8992 <td align=left valign=top>ams_rx_curr_vddr_afe</td> 8993 <td align=left> 8994   Controls the current biasing for the RX afe amsbus ctrl_out  54:52 <br> 8995 Reset value is 0x2.</td></tr> 8996 <tr bgcolor=WHITE> 8997 <td bgcolor=WHITE align=center valign=top>05</td> 8998 <td align=left valign=top>RW</td> 8999 <td align=left valign=top>ams_rx_os2x_mode_even_odd</td> 9000 <td align=left> 9001   Allow even or odd path to be selected for OSR2X mode amsbus ctrl_out  51:51 <br> 9002 Reset value is 0x0.</td></tr> 9003 <tr bgcolor=WHITE> 9004 <td bgcolor=WHITE align=center valign=top>04</td> 9005 <td align=left valign=top>RW</td> 9006 <td align=left valign=top>ams_rx_dfe_os2x_mode</td> 9007 <td align=left> 9008   Enables OS2X mode for DFE amsbus ctrl_out  50:50 <br> 9009 Reset value is 0x0.</td></tr> 9010 <tr bgcolor=WHITE> 9011 <td bgcolor=WHITE align=center valign=top>03</td> 9012 <td align=left valign=top>RW</td> 9013 <td align=left valign=top>ams_rx_en_20b_demux</td> 9014 <td align=left> 9015   1: Endable 2 to 20 Demux; 0: Enables 2 to 10 Demux amsbus ctrl_out  49:49 <br> 9016 Reset value is 0x1.</td></tr> 9017 <tr bgcolor=WHITE> 9018 <td bgcolor=WHITE align=center valign=top>02</td> 9019 <td align=left valign=top>RW</td> 9020 <td align=left valign=top>ams_rx_en_clk16</td> 9021 <td align=left> 9022   1: enables the divide by 16 output clock amsbus ctrl_out  48:48 <br> 9023 Reset value is 0x1.</td></tr> 9024 <tr bgcolor=WHITE> 9025 <td bgcolor=WHITE align=center valign=top>01</td> 9026 <td align=left valign=top>RW</td> 9027 <td align=left valign=top>ams_rx_en_clk33</td> 9028 <td align=left> 9029   1: enables the divide by 33 output clock amsbus ctrl_out  47:47 <br> 9030 Reset value is 0x1.</td></tr> 9031 <tr bgcolor=WHITE> 9032 <td bgcolor=WHITE align=center valign=top>00</td> 9033 <td align=left valign=top>RW</td> 9034 <td align=left valign=top>ams_rx_en_vcctrl</td> 9035 <td align=left> 9036   1: enables common mode control for DFE signal path amsbus ctrl_out  46:46 <br> 9037 Reset value is 0x1.</td></tr> 9038 </table><p> 9039 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9040 <hr> 9041 <b><a NAME="AMS_RX_RX_CTRL_4">AMS_RX_RX_CTRL_4 - RX_CTRL_4</a></b><br> 9042 Address Offset = 32'h0000_d094<br> 9043 Physical Address = 32'h0000_d094<br> 9044 Reset Value = 16'h0020<br> 9045 Access = RW (16-bit only)<br> 9046 <table border=1 align=center width=100% cellpadding=0> 9047 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9048 <tr bgcolor=WHITE> 9049 <td bgcolor=WHITE align=center valign=top>15:12</td> 9050 <td align=left valign=top>RW</td> 9051 <td align=left valign=top>ams_rx_vga_pon</td> 9052 <td align=left> 9053   vga rescal bits, dfs changed to 0 for vgapon rescal offset amsbus ctrl_out  76:73 <br> 9054 Reset value is 0x0.</td></tr> 9055 <tr bgcolor=WHITE> 9056 <td bgcolor=WHITE align=center valign=top>11</td> 9057 <td align=left valign=top>RW</td> 9058 <td align=left valign=top>ams_rx_oc_2x</td> 9059 <td align=left> 9060   1: doubles the DC offset range amsbus ctrl_out  72:72 <br> 9061 Reset value is 0x0.</td></tr> 9062 <tr bgcolor=WHITE> 9063 <td bgcolor=WHITE align=center valign=top>10:08</td> 9064 <td align=left valign=top>RW</td> 9065 <td align=left valign=top>ams_rx_spare_4_0</td> 9066 <td align=left> 9067   AMS reserved[71:69] amsbus ctrl_out  71:69 <br> 9068 Reset value is 0x0.</td></tr> 9069 <tr bgcolor=WHITE> 9070 <td bgcolor=WHITE align=center valign=top>07</td> 9071 <td align=left valign=top>RW</td> 9072 <td align=left valign=top>ams_rx_en_recclkdiv</td> 9073 <td align=left> 9074   enables the additional recovered clock dividers amsbus ctrl_out  68:68 <br> 9075 Reset value is 0x0.</td></tr> 9076 <tr bgcolor=WHITE> 9077 <td bgcolor=WHITE align=center valign=top>06:05</td> 9078 <td align=left valign=top>RW</td> 9079 <td align=left valign=top>ams_rx_div3o4o5</td> 9080 <td align=left> 9081   {00, 01, 10, 11} = {N/A, /3, /4, /5} amsbus ctrl_out  67:66 <br> 9082 Reset value is 0x1.</td></tr> 9083 <tr bgcolor=WHITE> 9084 <td bgcolor=WHITE align=center valign=top>04:00</td> 9085 <td align=left valign=top>RW</td> 9086 <td align=left valign=top>ams_rx_recclkdiv</td> 9087 <td align=left> 9088   Recovered clock divider = 1/(div3o4o5 * (recclkdiv<5:1> + 1)) amsbus ctrl_out  65:61 <br> 9089 Reset value is 0x0.</td></tr> 9090 </table><p> 9091 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9092 <hr> 9093 <b><a NAME="AMS_RX_RX_CTRL_5">AMS_RX_RX_CTRL_5 - RX_CTRL_5</a></b><br> 9094 Address Offset = 32'h0000_d095<br> 9095 Physical Address = 32'h0000_d095<br> 9096 Reset Value = 16'h0fa0<br> 9097 Access = RW (16-bit only)<br> 9098 <table border=1 align=center width=100% cellpadding=0> 9099 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9100 <tr bgcolor=WHITE> 9101 <td bgcolor=WHITE align=center valign=top>15</td> 9102 <td align=left valign=top>RW</td> 9103 <td align=left valign=top>ams_rx_dcc2_phase_flip</td> 9104 <td align=left> 9105   1: Flips the clock phase from slicer to dfe tap dcc2 for debug purpose. 0 : normal operation amsbus ctrl_out  92:92 <br> 9106 Reset value is 0x0.</td></tr> 9107 <tr bgcolor=WHITE> 9108 <td bgcolor=WHITE align=center valign=top>14</td> 9109 <td align=left valign=top>RW</td> 9110 <td align=left valign=top>ams_rx_slcr_calib_range_sel</td> 9111 <td align=left> 9112   To select the slicer calibration range amsbus ctrl_out  91:91 <br> 9113 Reset value is 0x0.</td></tr> 9114 <tr bgcolor=WHITE> 9115 <td bgcolor=WHITE align=center valign=top>13</td> 9116 <td align=left valign=top>RW</td> 9117 <td align=left valign=top>ams_rx_pi_pd</td> 9118 <td align=left> 9119   1: powers down the the phase interpolator amsbus ctrl_out  90:90 <br> 9120 Reset value is 0x0.</td></tr> 9121 <tr bgcolor=WHITE> 9122 <td bgcolor=WHITE align=center valign=top>12</td> 9123 <td align=left valign=top>RW</td> 9124 <td align=left valign=top>ams_rx_dcc1_phase_flip</td> 9125 <td align=left> 9126   1: Flips the clock phase from slicer to dfe tap dcc1 for debug purpose. 0 : normal operation amsbus ctrl_out  89:89 <br> 9127 Reset value is 0x0.</td></tr> 9128 <tr bgcolor=WHITE> 9129 <td bgcolor=WHITE align=center valign=top>11</td> 9130 <td align=left valign=top>RW</td> 9131 <td align=left valign=top>ams_rx_en_dfeclk</td> 9132 <td align=left> 9133   1:normal mode, 0=non-dfe mode amsbus ctrl_out  88:88 <br> 9134 Reset value is 0x1.</td></tr> 9135 <tr bgcolor=WHITE> 9136 <td bgcolor=WHITE align=center valign=top>10:07</td> 9137 <td align=left valign=top>RW</td> 9138 <td align=left valign=top>ams_rx_ctle_gain_ctrl</td> 9139 <td align=left> 9140   Controls for DC gain adjustment for CTLE amsbus ctrl_out  87:84 <br> 9141 Reset value is 0xf.</td></tr> 9142 <tr bgcolor=WHITE> 9143 <td bgcolor=WHITE align=center valign=top>06:04</td> 9144 <td align=left valign=top>RW</td> 9145 <td align=left valign=top>ams_rx_curr_in_offset</td> 9146 <td align=left> 9147   controls current biasing for input offset correction, Curr_in_offset in AMS amsbus ctrl_out  83:81 <br> 9148 Reset value is 0x2.</td></tr> 9149 <tr bgcolor=WHITE> 9150 <td bgcolor=WHITE align=center valign=top>03:00</td> 9151 <td align=left valign=top>RW</td> 9152 <td align=left valign=top>ams_rx_pon</td> 9153 <td align=left> 9154   reciever rescal bits, dfs changed to 0 for rxpon rescal offset amsbus ctrl_out  80:77 <br> 9155 Reset value is 0x0.</td></tr> 9156 </table><p> 9157 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9158 <hr> 9159 <b><a NAME="AMS_RX_RX_CTRL_6">AMS_RX_RX_CTRL_6 - RX_CTRL_6</a></b><br> 9160 Address Offset = 32'h0000_d096<br> 9161 Physical Address = 32'h0000_d096<br> 9162 Reset Value = 16'h1078<br> 9163 Access = RW (16-bit only)<br> 9164 <table border=1 align=center width=100% cellpadding=0> 9165 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9166 <tr bgcolor=WHITE> 9167 <td bgcolor=WHITE align=center valign=top>15:13</td> 9168 <td align=left valign=top>RSVD</td> 9169 <td align=left valign=top>Reserved</td> 9170 <td align=left> 9171 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9172 <tr bgcolor=WHITE> 9173 <td bgcolor=WHITE align=center valign=top>12:08</td> 9174 <td align=left valign=top>RW</td> 9175 <td align=left valign=top>ams_rx_sigdet_offset_correction_pos</td> 9176 <td align=left> 9177   Adjust the offset of the positive level detection. (Default: XFI 10.3125Gbps) amsbus ctrl_out  105:101 <br> 9178 Reset value is 0x10.</td></tr> 9179 <tr bgcolor=WHITE> 9180 <td bgcolor=WHITE align=center valign=top>07</td> 9181 <td align=left valign=top>RW</td> 9182 <td align=left valign=top>ams_rx_sigdet_calibration_select</td> 9183 <td align=left> 9184   During signal detect calibration, the output of D2C is delivered to the output pin "o_rx_sigdet." amsbus ctrl_out  100:100 <br> 9185 Reset value is 0x0.</td></tr> 9186 <tr bgcolor=WHITE> 9187 <td bgcolor=WHITE align=center valign=top>06:03</td> 9188 <td align=left valign=top>RW</td> 9189 <td align=left valign=top>ams_rx_sum_gain_ctrl</td> 9190 <td align=left> 9191   amsbus ctrl_out  99:96 <br> 9192 Reset value is 0xf.</td></tr> 9193 <tr bgcolor=WHITE> 9194 <td bgcolor=WHITE align=center valign=top>02</td> 9195 <td align=left valign=top>RW</td> 9196 <td align=left valign=top>ams_rx_en_sigdet_calib</td> 9197 <td align=left> 9198   1: Enable signal detect calibration amsbus ctrl_out  95:95 <br> 9199 Reset value is 0x0.</td></tr> 9200 <tr bgcolor=WHITE> 9201 <td bgcolor=WHITE align=center valign=top>01</td> 9202 <td align=left valign=top>RW</td> 9203 <td align=left valign=top>ams_rx_hiz_1</td> 9204 <td align=left> 9205   amsbus ctrl_out  94:94 <br> 9206 Reset value is 0x0.</td></tr> 9207 <tr bgcolor=WHITE> 9208 <td bgcolor=WHITE align=center valign=top>00</td> 9209 <td align=left valign=top>RW</td> 9210 <td align=left valign=top>ams_rx_m1_sign</td> 9211 <td align=left> 9212   To control the polarity of m1 threshold adjust amsbus ctrl_out  93:93 <br> 9213 Reset value is 0x0.</td></tr> 9214 </table><p> 9215 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9216 <hr> 9217 <b><a NAME="AMS_RX_RX_CTRL_7">AMS_RX_RX_CTRL_7 - RX_CTRL_7</a></b><br> 9218 Address Offset = 32'h0000_d097<br> 9219 Physical Address = 32'h0000_d097<br> 9220 Reset Value = 16'h0130<br> 9221 Access = RW (16-bit only)<br> 9222 <table border=1 align=center width=100% cellpadding=0> 9223 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9224 <tr bgcolor=WHITE> 9225 <td bgcolor=WHITE align=center valign=top>15:14</td> 9226 <td align=left valign=top>RSVD</td> 9227 <td align=left valign=top>Reserved</td> 9228 <td align=left> 9229 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9230 <tr bgcolor=WHITE> 9231 <td bgcolor=WHITE align=center valign=top>13:10</td> 9232 <td align=left valign=top>RW</td> 9233 <td align=left valign=top>ams_rx_spare_7_0</td> 9234 <td align=left> 9235   ams_reserved[119:116] amsbus ctrl_out  119:116 <br> 9236 Reset value is 0x0.</td></tr> 9237 <tr bgcolor=WHITE> 9238 <td bgcolor=WHITE align=center valign=top>09:05</td> 9239 <td align=left valign=top>RW</td> 9240 <td align=left valign=top>ams_rx_sigdet_threshold</td> 9241 <td align=left> 9242   Not used. Please use sigdet_threshold from sigdet module, Rx_sigdet_threshold in AMS amsbus ctrl_out  115:111 <br> 9243 Reset value is 0x9.</td></tr> 9244 <tr bgcolor=WHITE> 9245 <td bgcolor=WHITE align=center valign=top>04:00</td> 9246 <td align=left valign=top>RW</td> 9247 <td align=left valign=top>ams_rx_sigdet_offset_correction_neg</td> 9248 <td align=left> 9249   Adjust the offset of the negative level detection. (Default: XFI 10.3125Gbps) amsbus ctrl_out  110:106 <br> 9250 Reset value is 0x10.</td></tr> 9251 </table><p> 9252 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9253 <hr> 9254 <b><a NAME="AMS_RX_RX_INT">AMS_RX_RX_INT - RX_CTRL_INT</a></b><br> 9255 Address Offset = 32'h0000_d098<br> 9256 Physical Address = 32'h0000_d098<br> 9257 Reset Value = 16'h0000<br> 9258 Access = RW (16-bit only)<br> 9259 <table border=1 align=center width=100% cellpadding=0> 9260 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9261 <tr bgcolor=WHITE> 9262 <td bgcolor=WHITE align=center valign=top>15:02</td> 9263 <td align=left valign=top>RSVD</td> 9264 <td align=left valign=top>Reserved</td> 9265 <td align=left> 9266 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9267 <tr bgcolor=WHITE> 9268 <td bgcolor=WHITE align=center valign=top>01</td> 9269 <td align=left valign=top>RW</td> 9270 <td align=left valign=top>ams_rx_rxpon_sel</td> 9271 <td align=left> 9272   Force select AMS rxpon else select rxpon_int (sum of external rescal and AMS rxpon )<br> 9273 Reset value is 0x0.</td></tr> 9274 <tr bgcolor=WHITE> 9275 <td bgcolor=WHITE align=center valign=top>00</td> 9276 <td align=left valign=top>RW</td> 9277 <td align=left valign=top>ams_rx_vgapon_sel</td> 9278 <td align=left> 9279   Force select AMS vgapon else select vgapon_int(sum of external rescal and AMS vgapon)<br> 9280 Reset value is 0x0.</td></tr> 9281 </table><p> 9282 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9283 <hr> 9284 <b><a NAME="AMS_RX_RX_STS">AMS_RX_RX_STS - RX_STS</a></b><br> 9285 Address Offset = 32'h0000_d099<br> 9286 Physical Address = 32'h0000_d099<br> 9287 Reset Value = 16'h0000<br> 9288 Access = RO (16-bit only)<br> 9289 <table border=1 align=center width=100% cellpadding=0> 9290 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9291 <tr bgcolor=WHITE> 9292 <td bgcolor=WHITE align=center valign=top>15:08</td> 9293 <td align=left valign=top>RSVD</td> 9294 <td align=left valign=top>Reserved</td> 9295 <td align=left> 9296 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9297 <tr bgcolor=WHITE> 9298 <td bgcolor=WHITE align=center valign=top>07:04</td> 9299 <td align=left valign=top>RO</td> 9300 <td align=left valign=top>ams_rx_vgapon_mux</td> 9301 <td align=left> 9302   vgapon at AFE interface<br> 9303 Reset value is 0x0.</td></tr> 9304 <tr bgcolor=WHITE> 9305 <td bgcolor=WHITE align=center valign=top>03:00</td> 9306 <td align=left valign=top>RO</td> 9307 <td align=left valign=top>ams_rx_rxpon_mux</td> 9308 <td align=left> 9309   rxpon at AFE interface<br> 9310 Reset value is 0x0.</td></tr> 9311 </table><p> 9312 <A HREF="#AMS_RX Registers">Return to AMS_RX: per lane register block [One Copy Per Lane] Table</A><p> 9313 <hr> 9314 <H1><a NAME="AMS_TX Registers">AMS_TX: per lane register block [One Copy Per Lane] Registers</a></H1> 9315 <table border=1 align=center width=100% cellpadding=0> 9316 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 9317 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 9318 <tr> 9319 <td align=center>0xD0A0</td><td><A HREF="#AMS_TX_TX_CTRL_0">AMS_TX_TX_CTRL_0</A><br>TX_CTRL_0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_lowlatency_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_fifo_resetb</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_tx_ll_fifo_ctrl</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_ll_fifo_zero_out</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_ll_polarity_flip</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_ll_selpath_tx</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_enable_os_2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_pon</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_tx_ticksel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_pwrdn</div> </td> <td align=center>16'h2800</td></tr> 9320 <tr> 9321 <td align=center>0xD0A1</td><td><A HREF="#AMS_TX_TX_CTRL_1">AMS_TX_TX_CTRL_1</A><br>TX_CTRL_1</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_en_slow</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_wclk33</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_wclk20</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_wclk16</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_testclk_ena</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_tx_testsel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_cntrl_rxdetect_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_tx_rxdtct_th_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_high_current</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_enable_os_4</div> </td> <td align=center>16'h0744</td></tr> 9322 <tr> 9323 <td align=center>0xD0A2</td><td><A HREF="#AMS_TX_TX_CTRL_2">AMS_TX_TX_CTRL_2</A><br>TX_CTRL_2</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_fifo_phsdetect_mode</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_tx_ibias_pibuf_cntl</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_tx_ibias_pi_cntl</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_tx_ibias_opamp_cntl</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_dcc_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_en_hpf</div> </td> <td align=center>16'h5250</td></tr> 9324 <tr> 9325 <td align=center>0xD0A3</td><td><A HREF="#AMS_TX_TX_CTRL_3">AMS_TX_TX_CTRL_3</A><br>TX_CTRL_3</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_refcalm</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_refcalp</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_refcalshunt</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_tx_spare_3_0</div> </td> <td align=center>16'h1556</td></tr> 9326 <tr> 9327 <td align=center>0xD0A4</td><td><A HREF="#AMS_TX_TX_CTRL_4">AMS_TX_TX_CTRL_4</A><br>TX_CTRL_4</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_shntpost2_post2</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">ams_tx_shntpost1_post1pre</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">ams_tx_shntpre_post1pre</div> </td> <td align=center>16'h0000</td></tr> 9328 <tr> 9329 <td align=center>0xD0A5</td><td><A HREF="#AMS_TX_TX_CTRL_5">AMS_TX_TX_CTRL_5</A><br>TX_CTRL_5</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_post2to1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_pre</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_post1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_post2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_shntmain_post2</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">ams_tx_shntmain_post1pre</div> </td> <td align=center>16'h0000</td></tr> 9330 <tr> 9331 <td align=center>0xD0A6</td><td><A HREF="#AMS_TX_TX_CTRL_6">AMS_TX_TX_CTRL_6</A><br>TX_CTRL_6</td><td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_tx_shntpost1_post1</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_tx_dis_cal</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_spare_6_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_pd_phasedet</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_en_shuntmode</div> </td> <td align=center>16'h0001</td></tr> 9332 <tr> 9333 <td align=center>0xD0A7</td><td><A HREF="#AMS_TX_TX_CTRL_7">AMS_TX_TX_CTRL_7</A><br>TX_CTRL_7</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_refcalpcs</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_refcalmcs</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">ams_tx_shntmain_post1</div> </td> <td align=center>16'h0aa0</td></tr> 9334 <tr> 9335 <td align=center>0xD0A8</td><td><A HREF="#AMS_TX_TX_CTRL_8">AMS_TX_TX_CTRL_8</A><br>TX_CTRL_8</td><td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">ams_tx_spare_8_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_shnten_main</div> </td> <td align=center>16'h0000</td></tr> 9336 <tr> 9337 <td align=center>0xD0A9</td><td><A HREF="#AMS_TX_TX_INT">AMS_TX_TX_INT</A><br>TX_CTRL_INT</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_sel_txmaster</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_auto_ll_selpath_tx_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_tx_txpon_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td align=center>16'h0000</td></tr> 9338 <tr> 9339 <td align=center>0xD0AA</td><td><A HREF="#AMS_TX_TX_STS">AMS_TX_TX_STS</A><br>TX_STS</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_rescal</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_tx_txpon_mux</div> </td> <td align=center>16'h0000</td></tr> 9340 </table><p> 9341 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 9342 <hr> 9343 <b><a NAME="AMS_TX_TX_CTRL_0">AMS_TX_TX_CTRL_0 - TX_CTRL_0</a></b><br> 9344 Address Offset = 32'h0000_d0a0<br> 9345 Physical Address = 32'h0000_d0a0<br> 9346 Reset Value = 16'h2800<br> 9347 Access = RW (16-bit only)<br> 9348 <table border=1 align=center width=100% cellpadding=0> 9349 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9350 <tr bgcolor=WHITE> 9351 <td bgcolor=WHITE align=center valign=top>15</td> 9352 <td align=left valign=top>RW</td> 9353 <td align=left valign=top>ams_tx_lowlatency_en</td> 9354 <td align=left> 9355 FIFO and phase detector is enabled. amsbus ctrl_out  15:15 <br> 9356 Reset value is 0x0.</td></tr> 9357 <tr bgcolor=WHITE> 9358 <td bgcolor=WHITE align=center valign=top>14</td> 9359 <td align=left valign=top>RW</td> 9360 <td align=left valign=top>ams_tx_fifo_resetb</td> 9361 <td align=left> 9362   Not use, please use afe_tx_fifo_rstb from TXPI module amsbus ctrl_out  14:14 <br> 9363 Reset value is 0x0.</td></tr> 9364 <tr bgcolor=WHITE> 9365 <td bgcolor=WHITE align=center valign=top>13:11</td> 9366 <td align=left valign=top>RW</td> 9367 <td align=left valign=top>ams_tx_ll_fifo_ctrl</td> 9368 <td align=left> 9369   fifo depth control. see AMS. lowlatency_fifo_ctrl in AMS amsbus ctrl_out  13:11 <br> 9370 Reset value is 0x5.</td></tr> 9371 <tr bgcolor=WHITE> 9372 <td bgcolor=WHITE align=center valign=top>10</td> 9373 <td align=left valign=top>RW</td> 9374 <td align=left valign=top>ams_tx_ll_fifo_zero_out</td> 9375 <td align=left> 9376   1: in the low latency mode the fifo output is forced to 0. TX output is 0. lowlatency_fifo_ctrl in AMS. amsbus ctrl_out  10:10 <br> 9377 Reset value is 0x0.</td></tr> 9378 <tr bgcolor=WHITE> 9379 <td bgcolor=WHITE align=center valign=top>09</td> 9380 <td align=left valign=top>RW</td> 9381 <td align=left valign=top>ams_tx_ll_polarity_flip</td> 9382 <td align=left> 9383   1: In the low latecy mode, inverts the polarity of the data received. lowlatency_polarity_flip in AMS. amsbus ctrl_out  9:9 <br> 9384 Reset value is 0x0.</td></tr> 9385 <tr bgcolor=WHITE> 9386 <td bgcolor=WHITE align=center valign=top>08</td> 9387 <td align=left valign=top>RW</td> 9388 <td align=left valign=top>ams_tx_ll_selpath_tx</td> 9389 <td align=left> 9390   1: enables low latency path in the TX. Controlled by auto data path select as well. lowlatency_selectpathtx in AMS amsbus ctrl_out  8:8 <br> 9391 Reset value is 0x0.</td></tr> 9392 <tr bgcolor=WHITE> 9393 <td bgcolor=WHITE align=center valign=top>07</td> 9394 <td align=left valign=top>RW</td> 9395 <td align=left valign=top>ams_tx_enable_os_2</td> 9396 <td align=left> 9397   1: Subsamples data from the low speed mux to the FIR in order to have the TX FIR 1-UI apart. [16]&[7] not high at same time amsbus ctrl_out  9398 7:7 <br> 9399 Reset value is 0x0.</td></tr> 9400 <tr bgcolor=WHITE> 9401 <td bgcolor=WHITE align=center valign=top>06:03</td> 9402 <td align=left valign=top>RW</td> 9403 <td align=left valign=top>ams_tx_pon</td> 9404 <td align=left> 9405   Resistive Calibration Bits , can be used as offset. amsbus ctrl_out  6:3 <br> 9406 Reset value is 0x0.</td></tr> 9407 <tr bgcolor=WHITE> 9408 <td bgcolor=WHITE align=center valign=top>02:01</td> 9409 <td align=left valign=top>RW</td> 9410 <td align=left valign=top>ams_tx_ticksel</td> 9411 <td align=left> 9412   Local timing adjustment for loading of buffered 20-bit data into MUX 20:2, step=1/5 of 20T. amsbus ctrl_out  2:1 <br> 9413 Reset value is 0x0.</td></tr> 9414 <tr bgcolor=WHITE> 9415 <td bgcolor=WHITE align=center valign=top>00</td> 9416 <td align=left valign=top>RW</td> 9417 <td align=left valign=top>ams_tx_pwrdn</td> 9418 <td align=left> 9419   power down TX. AC-JTAG should still work even if tx is powered down. amsbus ctrl_out  0:0 <br> 9420 Reset value is 0x0.</td></tr> 9421 </table><p> 9422 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9423 <hr> 9424 <b><a NAME="AMS_TX_TX_CTRL_1">AMS_TX_TX_CTRL_1 - TX_CTRL_1</a></b><br> 9425 Address Offset = 32'h0000_d0a1<br> 9426 Physical Address = 32'h0000_d0a1<br> 9427 Reset Value = 16'h0744<br> 9428 Access = RW (16-bit only)<br> 9429 <table border=1 align=center width=100% cellpadding=0> 9430 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9431 <tr bgcolor=WHITE> 9432 <td bgcolor=WHITE align=center valign=top>15</td> 9433 <td align=left valign=top>RSVD</td> 9434 <td align=left valign=top>Reserved</td> 9435 <td align=left> 9436 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 9437 <tr bgcolor=WHITE> 9438 <td bgcolor=WHITE align=center valign=top>14:11</td> 9439 <td align=left valign=top>RW</td> 9440 <td align=left valign=top>ams_tx_en_slow</td> 9441 <td align=left> 9442   enable slew rate control amsbus ctrl_out  30:27 <br> 9443 Reset value is 0x0.</td></tr> 9444 <tr bgcolor=WHITE> 9445 <td bgcolor=WHITE align=center valign=top>10</td> 9446 <td align=left valign=top>RW</td> 9447 <td align=left valign=top>ams_tx_en_wclk33</td> 9448 <td align=left> 9449   Enable 33T clock amsbus ctrl_out  26:26 <br> 9450 Reset value is 0x1.</td></tr> 9451 <tr bgcolor=WHITE> 9452 <td bgcolor=WHITE align=center valign=top>09</td> 9453 <td align=left valign=top>RW</td> 9454 <td align=left valign=top>ams_tx_en_wclk20</td> 9455 <td align=left> 9456   Enable 20T clock amsbus ctrl_out  25:25 <br> 9457 Reset value is 0x1.</td></tr> 9458 <tr bgcolor=WHITE> 9459 <td bgcolor=WHITE align=center valign=top>08</td> 9460 <td align=left valign=top>RW</td> 9461 <td align=left valign=top>ams_tx_en_wclk16</td> 9462 <td align=left> 9463   Enable 16T clock amsbus ctrl_out  24:24 <br> 9464 Reset value is 0x1.</td></tr> 9465 <tr bgcolor=WHITE> 9466 <td bgcolor=WHITE align=center valign=top>07</td> 9467 <td align=left valign=top>RW</td> 9468 <td align=left valign=top>ams_tx_testclk_ena</td> 9469 <td align=left> 9470   Enables TX test clock output into test port, Testclk_en in AMS amsbus ctrl_out  23:23 <br> 9471 Reset value is 0x0.</td></tr> 9472 <tr bgcolor=WHITE> 9473 <td bgcolor=WHITE align=center valign=top>06:05</td> 9474 <td align=left valign=top>RW</td> 9475 <td align=left valign=top>ams_tx_testsel</td> 9476 <td align=left> 9477   TX Test Clock output Selection amsbus ctrl_out  22:21 <br> 9478 Reset value is 0x2.</td></tr> 9479 <tr bgcolor=WHITE> 9480 <td bgcolor=WHITE align=center valign=top>04</td> 9481 <td align=left valign=top>RW</td> 9482 <td align=left valign=top>ams_tx_cntrl_rxdetect_en</td> 9483 <td align=left> 9484   1:Enables RXDetect. CNTRL bit is ORed with direct control pin. FOR USE IN PCIE-GEN3 MODE amsbus ctrl_out  20:20 <br> 9485 Reset value is 0x0.</td></tr> 9486 <tr bgcolor=WHITE> 9487 <td bgcolor=WHITE align=center valign=top>03:02</td> 9488 <td align=left valign=top>RW</td> 9489 <td align=left valign=top>ams_tx_rxdtct_th_sel</td> 9490 <td align=left> 9491   Controls the threshold for the RXdetect. FOR USE IN PCIE-GEN3 MODE amsbus ctrl_out  19:18 <br> 9492 Reset value is 0x1.</td></tr> 9493 <tr bgcolor=WHITE> 9494 <td bgcolor=WHITE align=center valign=top>01</td> 9495 <td align=left valign=top>RW</td> 9496 <td align=left valign=top>ams_tx_en_high_current</td> 9497 <td align=left> 9498   Enables 2X (high) current for IDLE block. 0 - disabled, 1 - enabled amsbus ctrl_out  17:17 <br> 9499 Reset value is 0x0.</td></tr> 9500 <tr bgcolor=WHITE> 9501 <td bgcolor=WHITE align=center valign=top>00</td> 9502 <td align=left valign=top>RW</td> 9503 <td align=left valign=top>ams_tx_enable_os_4</td> 9504 <td align=left> 9505   1: Subsamples data from the low speed mux to the FIR in order to have the TX FIR 1-UI apart. [16]&[7] not high at same time amsbus ctrl_out  9506 16:16 <br> 9507 Reset value is 0x0.</td></tr> 9508 </table><p> 9509 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9510 <hr> 9511 <b><a NAME="AMS_TX_TX_CTRL_2">AMS_TX_TX_CTRL_2 - TX_CTRL_2</a></b><br> 9512 Address Offset = 32'h0000_d0a2<br> 9513 Physical Address = 32'h0000_d0a2<br> 9514 Reset Value = 16'h5250<br> 9515 Access = RW (16-bit only)<br> 9516 <table border=1 align=center width=100% cellpadding=0> 9517 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9518 <tr bgcolor=WHITE> 9519 <td bgcolor=WHITE align=center valign=top>15</td> 9520 <td align=left valign=top>RSVD</td> 9521 <td align=left valign=top>Reserved</td> 9522 <td align=left> 9523 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 9524 <tr bgcolor=WHITE> 9525 <td bgcolor=WHITE align=center valign=top>14</td> 9526 <td align=left valign=top>RW</td> 9527 <td align=left valign=top>ams_tx_fifo_phsdetect_mode</td> 9528 <td align=left> 9529   1: phsdetect at 2.5G, 0: phsdetect at 1.25G amsbus ctrl_out  45:45 <br> 9530 Reset value is 0x1.</td></tr> 9531 <tr bgcolor=WHITE> 9532 <td bgcolor=WHITE align=center valign=top>13:11</td> 9533 <td align=left valign=top>RW</td> 9534 <td align=left valign=top>ams_tx_ibias_pibuf_cntl</td> 9535 <td align=left> 9536   current biasing control for the opamps used in phase interpolator buffer. amsbus ctrl_out  44:42 <br> 9537 Reset value is 0x2.</td></tr> 9538 <tr bgcolor=WHITE> 9539 <td bgcolor=WHITE align=center valign=top>10:08</td> 9540 <td align=left valign=top>RW</td> 9541 <td align=left valign=top>ams_tx_ibias_pi_cntl</td> 9542 <td align=left> 9543   current biasing control for the opamps used in phase interpolator. amsbus ctrl_out  41:39 <br> 9544 Reset value is 0x2.</td></tr> 9545 <tr bgcolor=WHITE> 9546 <td bgcolor=WHITE align=center valign=top>07:05</td> 9547 <td align=left valign=top>RW</td> 9548 <td align=left valign=top>ams_tx_ibias_opamp_cntl</td> 9549 <td align=left> 9550   current biasing control for the opamps used in dcc and calibration amsbus ctrl_out  38:36 <br> 9551 Reset value is 0x2.</td></tr> 9552 <tr bgcolor=WHITE> 9553 <td bgcolor=WHITE align=center valign=top>04</td> 9554 <td align=left valign=top>RW</td> 9555 <td align=left valign=top>ams_tx_dcc_en</td> 9556 <td align=left> 9557   enable duty cycle correction circuit amsbus ctrl_out  35:35 <br> 9558 Reset value is 0x1.</td></tr> 9559 <tr bgcolor=WHITE> 9560 <td bgcolor=WHITE align=center valign=top>03:00</td> 9561 <td align=left valign=top>RW</td> 9562 <td align=left valign=top>ams_tx_en_hpf</td> 9563 <td align=left> 9564   enable a HPF continuous time equalization to the driver. amsbus ctrl_out  34:31 <br> 9565 Reset value is 0x0.</td></tr> 9566 </table><p> 9567 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9568 <hr> 9569 <b><a NAME="AMS_TX_TX_CTRL_3">AMS_TX_TX_CTRL_3 - TX_CTRL_3</a></b><br> 9570 Address Offset = 32'h0000_d0a3<br> 9571 Physical Address = 32'h0000_d0a3<br> 9572 Reset Value = 16'h1556<br> 9573 Access = RW (16-bit only)<br> 9574 <table border=1 align=center width=100% cellpadding=0> 9575 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9576 <tr bgcolor=WHITE> 9577 <td bgcolor=WHITE align=center valign=top>15:14</td> 9578 <td align=left valign=top>RSVD</td> 9579 <td align=left valign=top>Reserved</td> 9580 <td align=left> 9581 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9582 <tr bgcolor=WHITE> 9583 <td bgcolor=WHITE align=center valign=top>13:10</td> 9584 <td align=left valign=top>RW</td> 9585 <td align=left valign=top>ams_tx_refcalm</td> 9586 <td align=left> 9587   Controls the reference value for calibrating the NMOS part of the series slices amsbus ctrl_out  59:56 <br> 9588 Reset value is 0x5.</td></tr> 9589 <tr bgcolor=WHITE> 9590 <td bgcolor=WHITE align=center valign=top>09:06</td> 9591 <td align=left valign=top>RW</td> 9592 <td align=left valign=top>ams_tx_refcalp</td> 9593 <td align=left> 9594   Controls the reference value for calibrating the PMOS part of the series slices amsbus ctrl_out  55:52 <br> 9595 Reset value is 0x5.</td></tr> 9596 <tr bgcolor=WHITE> 9597 <td bgcolor=WHITE align=center valign=top>05:02</td> 9598 <td align=left valign=top>RW</td> 9599 <td align=left valign=top>ams_tx_refcalshunt</td> 9600 <td align=left> 9601   Controls the reference value for calibrating the NMOS part of the shunt slices amsbus ctrl_out  51:48 <br> 9602 Reset value is 0x5.</td></tr> 9603 <tr bgcolor=WHITE> 9604 <td bgcolor=WHITE align=center valign=top>01:00</td> 9605 <td align=left valign=top>RW</td> 9606 <td align=left valign=top>ams_tx_spare_3_0</td> 9607 <td align=left> 9608   AMS reserved bit[47:46] amsbus ctrl_out  47:46 <br> 9609 Reset value is 0x2.</td></tr> 9610 </table><p> 9611 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9612 <hr> 9613 <b><a NAME="AMS_TX_TX_CTRL_4">AMS_TX_TX_CTRL_4 - TX_CTRL_4</a></b><br> 9614 Address Offset = 32'h0000_d0a4<br> 9615 Physical Address = 32'h0000_d0a4<br> 9616 Reset Value = 16'h0000<br> 9617 Access = RW (16-bit only)<br> 9618 <table border=1 align=center width=100% cellpadding=0> 9619 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9620 <tr bgcolor=WHITE> 9621 <td bgcolor=WHITE align=center valign=top>15:12</td> 9622 <td align=left valign=top>RW</td> 9623 <td align=left valign=top>ams_tx_shntpost2_post2</td> 9624 <td align=left> 9625   Direct Control of Shunt slices for post1 in group post2. BUFFERED CONTROL from VERT Slices amsbus ctrl_out  81:78 <br> 9626 Reset value is 0x0.</td></tr> 9627 <tr bgcolor=WHITE> 9628 <td bgcolor=WHITE align=center valign=top>11:06</td> 9629 <td align=left valign=top>RW</td> 9630 <td align=left valign=top>ams_tx_shntpost1_post1pre</td> 9631 <td align=left> 9632   Direct Control of Shunt slices for post1 in group post1pre. BUFFERED CONTROL from VERT Slices amsbus ctrl_out  71:66 <br> 9633 Reset value is 0x0.</td></tr> 9634 <tr bgcolor=WHITE> 9635 <td bgcolor=WHITE align=center valign=top>05:00</td> 9636 <td align=left valign=top>RW</td> 9637 <td align=left valign=top>ams_tx_shntpre_post1pre</td> 9638 <td align=left> 9639   Direct Control of Shunt slices for pre in group post1pre. BUFFERED CONTROL from VERT Slices amsbus ctrl_out  65:60 <br> 9640 Reset value is 0x0.</td></tr> 9641 </table><p> 9642 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9643 <hr> 9644 <b><a NAME="AMS_TX_TX_CTRL_5">AMS_TX_TX_CTRL_5 - TX_CTRL_5</a></b><br> 9645 Address Offset = 32'h0000_d0a5<br> 9646 Physical Address = 32'h0000_d0a5<br> 9647 Reset Value = 16'h0000<br> 9648 Access = RW (16-bit only)<br> 9649 <table border=1 align=center width=100% cellpadding=0> 9650 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9651 <tr bgcolor=WHITE> 9652 <td bgcolor=WHITE align=center valign=top>15:14</td> 9653 <td align=left valign=top>RSVD</td> 9654 <td align=left valign=top>Reserved</td> 9655 <td align=left> 9656 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9657 <tr bgcolor=WHITE> 9658 <td bgcolor=WHITE align=center valign=top>13</td> 9659 <td align=left valign=top>RW</td> 9660 <td align=left valign=top>ams_tx_post2to1</td> 9661 <td align=left> 9662   Converts post2 taps to post1 taps amsbus ctrl_out  89:89 <br> 9663 Reset value is 0x0.</td></tr> 9664 <tr bgcolor=WHITE> 9665 <td bgcolor=WHITE align=center valign=top>12</td> 9666 <td align=left valign=top>RW</td> 9667 <td align=left valign=top>ams_tx_en_pre</td> 9668 <td align=left> 9669   Enables pre path amsbus ctrl_out  88:88 <br> 9670 Reset value is 0x0.</td></tr> 9671 <tr bgcolor=WHITE> 9672 <td bgcolor=WHITE align=center valign=top>11</td> 9673 <td align=left valign=top>RW</td> 9674 <td align=left valign=top>ams_tx_en_post1</td> 9675 <td align=left> 9676   Enables post1 path amsbus ctrl_out  87:87 <br> 9677 Reset value is 0x0.</td></tr> 9678 <tr bgcolor=WHITE> 9679 <td bgcolor=WHITE align=center valign=top>10</td> 9680 <td align=left valign=top>RW</td> 9681 <td align=left valign=top>ams_tx_en_post2</td> 9682 <td align=left> 9683   Enables post2 path amsbus ctrl_out  86:86 <br> 9684 Reset value is 0x0.</td></tr> 9685 <tr bgcolor=WHITE> 9686 <td bgcolor=WHITE align=center valign=top>09:06</td> 9687 <td align=left valign=top>RW</td> 9688 <td align=left valign=top>ams_tx_shntmain_post2</td> 9689 <td align=left> 9690   Direct Control of Shunt slices for main in group post2. INVERTED CONTROL from VERT Slices amsbus ctrl_out  85:82 <br> 9691 Reset value is 0x0.</td></tr> 9692 <tr bgcolor=WHITE> 9693 <td bgcolor=WHITE align=center valign=top>05:00</td> 9694 <td align=left valign=top>RW</td> 9695 <td align=left valign=top>ams_tx_shntmain_post1pre</td> 9696 <td align=left> 9697   Direct Control of Shunt slices for main in group post1pre. INVERTED CONTROL from VERT Slices amsbus ctrl_out  77:72 <br> 9698 Reset value is 0x0.</td></tr> 9699 </table><p> 9700 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9701 <hr> 9702 <b><a NAME="AMS_TX_TX_CTRL_6">AMS_TX_TX_CTRL_6 - TX_CTRL_6</a></b><br> 9703 Address Offset = 32'h0000_d0a6<br> 9704 Physical Address = 32'h0000_d0a6<br> 9705 Reset Value = 16'h0001<br> 9706 Access = RW (16-bit only)<br> 9707 <table border=1 align=center width=100% cellpadding=0> 9708 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9709 <tr bgcolor=WHITE> 9710 <td bgcolor=WHITE align=center valign=top>15:11</td> 9711 <td align=left valign=top>RW</td> 9712 <td align=left valign=top>ams_tx_shntpost1_post1</td> 9713 <td align=left> 9714   Direct Control of Shunt slices for post1 in group post1. BUFFERED CONTROL from VERT Slices amsbus ctrl_out  105:101 <br> 9715 Reset value is 0x0.</td></tr> 9716 <tr bgcolor=WHITE> 9717 <td bgcolor=WHITE align=center valign=top>10:06</td> 9718 <td align=left valign=top>RW</td> 9719 <td align=left valign=top>ams_tx_dis_cal</td> 9720 <td align=left> 9721   Disables the calibratin amplifiers amsbus ctrl_out  100:96 <br> 9722 Reset value is 0x0.</td></tr> 9723 <tr bgcolor=WHITE> 9724 <td bgcolor=WHITE align=center valign=top>05:02</td> 9725 <td align=left valign=top>RW</td> 9726 <td align=left valign=top>ams_tx_spare_6_0</td> 9727 <td align=left> 9728   Enables the Current Mode Slices of the Driver. amsbus ctrl_out  95:92 <br> 9729 Reset value is 0x0.</td></tr> 9730 <tr bgcolor=WHITE> 9731 <td bgcolor=WHITE align=center valign=top>01</td> 9732 <td align=left valign=top>RW</td> 9733 <td align=left valign=top>ams_tx_pd_phasedet</td> 9734 <td align=left> 9735   1: power down phase detection in TCA loop amsbus ctrl_out  91:91 <br> 9736 Reset value is 0x0.</td></tr> 9737 <tr bgcolor=WHITE> 9738 <td bgcolor=WHITE align=center valign=top>00</td> 9739 <td align=left valign=top>RW</td> 9740 <td align=left valign=top>ams_tx_en_shuntmode</td> 9741 <td align=left> 9742   enable shunt mode, ams[90] amsbus ctrl_out  90:90 <br> 9743 Reset value is 0x1.</td></tr> 9744 </table><p> 9745 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9746 <hr> 9747 <b><a NAME="AMS_TX_TX_CTRL_7">AMS_TX_TX_CTRL_7 - TX_CTRL_7</a></b><br> 9748 Address Offset = 32'h0000_d0a7<br> 9749 Physical Address = 32'h0000_d0a7<br> 9750 Reset Value = 16'h0aa0<br> 9751 Access = RW (16-bit only)<br> 9752 <table border=1 align=center width=100% cellpadding=0> 9753 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9754 <tr bgcolor=WHITE> 9755 <td bgcolor=WHITE align=center valign=top>15:13</td> 9756 <td align=left valign=top>RSVD</td> 9757 <td align=left valign=top>Reserved</td> 9758 <td align=left> 9759 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9760 <tr bgcolor=WHITE> 9761 <td bgcolor=WHITE align=center valign=top>12:09</td> 9762 <td align=left valign=top>RW</td> 9763 <td align=left valign=top>ams_tx_refcalpcs</td> 9764 <td align=left> 9765   Controls the reference value for calibrating the PMOS part of the series Current slices amsbus ctrl_out  118:115 <br> 9766 Reset value is 0x5.</td></tr> 9767 <tr bgcolor=WHITE> 9768 <td bgcolor=WHITE align=center valign=top>08:05</td> 9769 <td align=left valign=top>RW</td> 9770 <td align=left valign=top>ams_tx_refcalmcs</td> 9771 <td align=left> 9772   Controls the reference value for calibrating the NMOS part of the series Current slices amsbus ctrl_out  114:111 <br> 9773 Reset value is 0x5.</td></tr> 9774 <tr bgcolor=WHITE> 9775 <td bgcolor=WHITE align=center valign=top>04:00</td> 9776 <td align=left valign=top>RW</td> 9777 <td align=left valign=top>ams_tx_shntmain_post1</td> 9778 <td align=left> 9779   Direct Control of Shunt slices for main in group post1. INVERTED CONTROL from VERT Slices amsbus ctrl_out  110:106 <br> 9780 Reset value is 0x0.</td></tr> 9781 </table><p> 9782 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9783 <hr> 9784 <b><a NAME="AMS_TX_TX_CTRL_8">AMS_TX_TX_CTRL_8 - TX_CTRL_8</a></b><br> 9785 Address Offset = 32'h0000_d0a8<br> 9786 Physical Address = 32'h0000_d0a8<br> 9787 Reset Value = 16'h0000<br> 9788 Access = RW (16-bit only)<br> 9789 <table border=1 align=center width=100% cellpadding=0> 9790 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9791 <tr bgcolor=WHITE> 9792 <td bgcolor=WHITE align=center valign=top>15:09</td> 9793 <td align=left valign=top>RSVD</td> 9794 <td align=left valign=top>Reserved</td> 9795 <td align=left> 9796 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9797 <tr bgcolor=WHITE> 9798 <td bgcolor=WHITE align=center valign=top>08:01</td> 9799 <td align=left valign=top>RW</td> 9800 <td align=left valign=top>ams_tx_spare_8_0</td> 9801 <td align=left> 9802   AMS reserved bit[127:120] amsbus ctrl_out  127:120 <br> 9803 Reset value is 0x0.</td></tr> 9804 <tr bgcolor=WHITE> 9805 <td bgcolor=WHITE align=center valign=top>00</td> 9806 <td align=left valign=top>RW</td> 9807 <td align=left valign=top>ams_tx_shnten_main</td> 9808 <td align=left> 9809   Direct Control of Shunt slices for main in group main. INVERTED CONTROL from VERT Slices amsbus ctrl_out  119:119 <br> 9810 Reset value is 0x0.</td></tr> 9811 </table><p> 9812 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9813 <hr> 9814 <b><a NAME="AMS_TX_TX_INT">AMS_TX_TX_INT - TX_CTRL_INT</a></b><br> 9815 Address Offset = 32'h0000_d0a9<br> 9816 Physical Address = 32'h0000_d0a9<br> 9817 Reset Value = 16'h0000<br> 9818 Access = RW (16-bit only)<br> 9819 <table border=1 align=center width=100% cellpadding=0> 9820 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9821 <tr bgcolor=WHITE> 9822 <td bgcolor=WHITE align=center valign=top>15:04</td> 9823 <td align=left valign=top>RSVD</td> 9824 <td align=left valign=top>Reserved</td> 9825 <td align=left> 9826 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9827 <tr bgcolor=WHITE> 9828 <td bgcolor=WHITE align=center valign=top>03</td> 9829 <td align=left valign=top>RW</td> 9830 <td align=left valign=top>ams_tx_sel_txmaster</td> 9831 <td align=left> 9832   select TX lane as master, only one TX lane can be set to master<br> 9833 Reset value is 0x0.</td></tr> 9834 <tr bgcolor=WHITE> 9835 <td bgcolor=WHITE align=center valign=top>02</td> 9836 <td align=left valign=top>RW</td> 9837 <td align=left valign=top>ams_tx_auto_ll_selpath_tx_dis</td> 9838 <td align=left> 9839   0= Enable auto switching mode for TX datapath. If ll_selpath_tx is 1 then TX datapath is automtically switched to normal tx_data datapath when CL72/Remote_Loopback/PRBS_Gen/Pattern_Gen/TX_EEE_alert_pattern/TX_disable_1s/0s_pattern 9840 TX data sources are selected or enabled. 1= use AMS register field ll_selpath_tx to select between ULL and normal TX datapath.<br> 9841 Reset value is 0x0.</td></tr> 9842 <tr bgcolor=WHITE> 9843 <td bgcolor=WHITE align=center valign=top>01</td> 9844 <td align=left valign=top>RW</td> 9845 <td align=left valign=top>ams_tx_txpon_sel</td> 9846 <td align=left> 9847   1=select AMS txpon value, 0= select txpon_int (sum or external rescal)<br> 9848 Reset value is 0x0.</td></tr> 9849 <tr bgcolor=WHITE> 9850 <td bgcolor=WHITE align=center valign=top>00</td> 9851 <td align=left valign=top>RSVD</td> 9852 <td align=left valign=top>Reserved</td> 9853 <td align=left> 9854 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 9855 </table><p> 9856 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9857 <hr> 9858 <b><a NAME="AMS_TX_TX_STS">AMS_TX_TX_STS - TX_STS</a></b><br> 9859 Address Offset = 32'h0000_d0aa<br> 9860 Physical Address = 32'h0000_d0aa<br> 9861 Reset Value = 16'h0000<br> 9862 Access = RO (16-bit only)<br> 9863 <table border=1 align=center width=100% cellpadding=0> 9864 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9865 <tr bgcolor=WHITE> 9866 <td bgcolor=WHITE align=center valign=top>15:08</td> 9867 <td align=left valign=top>RSVD</td> 9868 <td align=left valign=top>Reserved</td> 9869 <td align=left> 9870 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 9871 <tr bgcolor=WHITE> 9872 <td bgcolor=WHITE align=center valign=top>07:04</td> 9873 <td align=left valign=top>RO</td> 9874 <td align=left valign=top>ams_tx_rescal</td> 9875 <td align=left> 9876   external rescal input value<br> 9877 Reset value is 0x0.</td></tr> 9878 <tr bgcolor=WHITE> 9879 <td bgcolor=WHITE align=center valign=top>03:00</td> 9880 <td align=left valign=top>RO</td> 9881 <td align=left valign=top>ams_tx_txpon_mux</td> 9882 <td align=left> 9883   txpon at AFE interface<br> 9884 Reset value is 0x0.</td></tr> 9885 </table><p> 9886 <A HREF="#AMS_TX Registers">Return to AMS_TX: per lane register block [One Copy Per Lane] Table</A><p> 9887 <hr> 9888 <H1><a NAME="AMS_COM Registers">AMS_COM: common register block for all lanes Registers</a></H1> 9889 <table border=1 align=center width=100% cellpadding=0> 9890 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 9891 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 9892 <tr> 9893 <td align=center>0xD0B0</td><td><A HREF="#AMS_COM_PLL_CTRL_0">AMS_COM_PLL_CTRL_0</A><br>PLL_CTRL_0</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_cpar</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_term_cm_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_spare_0_1</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_rpar</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_lc_refclk_adj_1_0</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">ams_pll_spare_0_0</div> </td> <td align=center>16'h2480</td></tr> 9894 <tr> 9895 <td align=center>0xD0B1</td><td><A HREF="#AMS_COM_PLL_CTRL_1">AMS_COM_PLL_CTRL_1</A><br>PLL_CTRL_1</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_hcur_vco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_enb_10t</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_enb_8t</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">ams_pll_vco_range</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_8p5g_vco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_spare_1_0</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_curr_sel</div> </td> <td align=center>16'h0007</td></tr> 9896 <tr> 9897 <td align=center>0xD0B2</td><td><A HREF="#AMS_COM_PLL_CTRL_2">AMS_COM_PLL_CTRL_2</A><br>PLL_CTRL_2</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_en_i4iqbuf</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_vcobuf_pon</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_clkvco_cal_invert</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_cmos_refclk_ch_hiz</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_calib_adj</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_8p5g</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_vco_pon</div> </td> <td align=center>16'h0080</td></tr> 9898 <tr> 9899 <td align=center>0xD0B3</td><td><A HREF="#AMS_COM_PLL_CTRL_3">AMS_COM_PLL_CTRL_3</A><br>PLL_CTRL_3</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_mmd_halfrate</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_cp_bias</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_spare_3_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_ref_cmos_hz</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_ref_cml_pd</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_clksel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_rclk_refout</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_cmos_refout_overwr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_cml_refout_overwr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_test_frac_clk</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_enb_16t</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_band_iqbuf_ctr</div> </td> <td align=center>16'h460e</td></tr> 9900 <tr> 9901 <td align=center>0xD0B4</td><td><A HREF="#AMS_COM_PLL_CTRL_4">AMS_COM_PLL_CTRL_4</A><br>PLL_CTRL_4</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_test_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_test_amp</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_vco_test_clk_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_bias_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_spare4_2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_bias_vdd_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_spare4_1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_cp_opamp_bias</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_lc_refclk_adj_3_2</div> </td> <td align=center>16'h1511</td></tr> 9902 <tr> 9903 <td align=center>0xD0B5</td><td><A HREF="#AMS_COM_PLL_CTRL_5">AMS_COM_PLL_CTRL_5</A><br>PLL_CTRL_5</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_refdiv_test_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_pwdb_extr_d2c</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_en_refout_div</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_pwrdn</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_term_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_test_sel_overwrite</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_test_vc</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_refout_div_sel</div> </td> <td align=center>16'h1415</td></tr> 9904 <tr> 9905 <td align=center>0xD0B6</td><td><A HREF="#AMS_COM_PLL_CTRL_6">AMS_COM_PLL_CTRL_6</A><br>PLL_CTRL_6</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_i_ndiv_frac_l</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_pfd_offset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_spare6_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_pfd_offset_enlarge</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_vco_i_boost</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_vco_gm_boost</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_pon</div> </td> <td align=center>16'h0000</td></tr> 9906 <tr> 9907 <td align=center>0xD0B7</td><td><A HREF="#AMS_COM_PLL_CTRL_7">AMS_COM_PLL_CTRL_7</A><br>PLL_CTRL_7</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="14"><div class="HT">ams_pll_i_ndiv_frac_h</div> </td> <td align=center>16'h0000</td></tr> 9908 <tr> 9909 <td align=center>0xD0B8</td><td><A HREF="#AMS_COM_PLL_CTRL_8">AMS_COM_PLL_CTRL_8</A><br>PLL_CTRL_8</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_i_ndiv_dither_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_i_pll_sdm_pwrdnb</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_vcofb_div</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_cml_refclk_bias</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">ams_pll_i_ndiv_int</div> </td> <td align=center>16'h4442</td></tr> 9910 <tr> 9911 <td align=center>0xD0B9</td><td><A HREF="#AMS_COM_PLL_CTRL_9">AMS_COM_PLL_CTRL_9</A><br>PLL_CTRL_9</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_cml_refclk_adj</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_bias_iq_ctrl</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">ams_pll_bias_div_ctrl</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_vco_supply_adj</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_sel_fp3cap</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_i_pll_frac_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_mmd_resetb</div> </td> <td align=center>16'h5285</td></tr> 9912 <tr> 9913 <td align=center>0xD0BA</td><td><A HREF="#AMS_COM_PLL_CTRL_10">AMS_COM_PLL_CTRL_10</A><br>PLL_CTRL_10</td><td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_tx_clkmaster_ovrd</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_tx_clkmaster_ctrl_a</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">ams_pll_tx_clkmaster_ctrl_b</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">ams_pll_refclk_in_bias</div> </td> <td align=center>16'h0015</td></tr> 9914 <tr> 9915 <td align=center>0xD0BE</td><td><A HREF="#AMS_COM_PLL_INT">AMS_COM_PLL_INT</A><br>PLL_CTRL_INT</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_refclk_term_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_refclk_div_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_refclk_div2_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ams_pll_refclk_div4_frc_val</div> </td> <td align=center>16'h0000</td></tr> 9916 <tr> 9917 <td align=center>0xD0BF</td><td><A HREF="#AMS_COM_PLL_STS">AMS_COM_PLL_STS</A><br>PLL_STS</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ams_pll_afe_rev_id</div> </td> <td align=center>16'h0000</td></tr> 9918 </table><p> 9919 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 9920 <hr> 9921 <b><a NAME="AMS_COM_PLL_CTRL_0">AMS_COM_PLL_CTRL_0 - PLL_CTRL_0</a></b><br> 9922 Address Offset = 32'h0000_d0b0<br> 9923 Physical Address = 32'h0000_d0b0<br> 9924 Reset Value = 16'h2480<br> 9925 Access = RW (16-bit only)<br> 9926 <table border=1 align=center width=100% cellpadding=0> 9927 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9928 <tr bgcolor=WHITE> 9929 <td bgcolor=WHITE align=center valign=top>15:14</td> 9930 <td align=left valign=top>RW</td> 9931 <td align=left valign=top>ams_pll_cpar</td> 9932 <td align=left> 9933 Change filter shunt capacitor amsbus ctrl_out  15:14 <br> 9934 Reset value is 0x0.</td></tr> 9935 <tr bgcolor=WHITE> 9936 <td bgcolor=WHITE align=center valign=top>13</td> 9937 <td align=left valign=top>RW</td> 9938 <td align=left valign=top>ams_pll_term_cm_en</td> 9939 <td align=left> 9940   enable common-mode input termination amsbus ctrl_out  13:13 <br> 9941 Reset value is 0x1.</td></tr> 9942 <tr bgcolor=WHITE> 9943 <td bgcolor=WHITE align=center valign=top>12</td> 9944 <td align=left valign=top>RW</td> 9945 <td align=left valign=top>ams_pll_spare_0_1</td> 9946 <td align=left> 9947   AMS reserved[12:12] amsbus ctrl_out  12:12 <br> 9948 Reset value is 0x0.</td></tr> 9949 <tr bgcolor=WHITE> 9950 <td bgcolor=WHITE align=center valign=top>11:09</td> 9951 <td align=left valign=top>RW</td> 9952 <td align=left valign=top>ams_pll_rpar</td> 9953 <td align=left> 9954   Change filter resistor for PLL bandwidth, these value include interfonnect resistance of 150 ohms. amsbus ctrl_out  11:9 <br> 9955 Reset value is 0x2.</td></tr> 9956 <tr bgcolor=WHITE> 9957 <td bgcolor=WHITE align=center valign=top>08:07</td> 9958 <td align=left valign=top>RW</td> 9959 <td align=left valign=top>ams_pll_lc_refclk_adj_1_0</td> 9960 <td align=left> 9961   Set the refclk input and output bias for LC ref channel amsbus ctrl_out  8:7 <br> 9962 Reset value is 0x1.</td></tr> 9963 <tr bgcolor=WHITE> 9964 <td bgcolor=WHITE align=center valign=top>06:00</td> 9965 <td align=left valign=top>RW</td> 9966 <td align=left valign=top>ams_pll_spare_0_0</td> 9967 <td align=left> 9968   AMS reserved[6:0] amsbus ctrl_out  6:0 <br> 9969 Reset value is 0x0.</td></tr> 9970 </table><p> 9971 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 9972 <hr> 9973 <b><a NAME="AMS_COM_PLL_CTRL_1">AMS_COM_PLL_CTRL_1 - PLL_CTRL_1</a></b><br> 9974 Address Offset = 32'h0000_d0b1<br> 9975 Physical Address = 32'h0000_d0b1<br> 9976 Reset Value = 16'h0007<br> 9977 Access = RW (16-bit only)<br> 9978 <table border=1 align=center width=100% cellpadding=0> 9979 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 9980 <tr bgcolor=WHITE> 9981 <td bgcolor=WHITE align=center valign=top>15</td> 9982 <td align=left valign=top>RW</td> 9983 <td align=left valign=top>ams_pll_en_hcur_vco</td> 9984 <td align=left> 9985   Program the vco current 0:0%(defualt), 1: +20% amsbus ctrl_out  31:31 <br> 9986 Reset value is 0x0.</td></tr> 9987 <tr bgcolor=WHITE> 9988 <td bgcolor=WHITE align=center valign=top>14</td> 9989 <td align=left valign=top>RW</td> 9990 <td align=left valign=top>ams_pll_enb_10t</td> 9991 <td align=left> 9992   0: off; 1: enable RTL clock 10T amsbus ctrl_out  30:30 <br> 9993 Reset value is 0x0.</td></tr> 9994 <tr bgcolor=WHITE> 9995 <td bgcolor=WHITE align=center valign=top>13</td> 9996 <td align=left valign=top>RW</td> 9997 <td align=left valign=top>ams_pll_enb_8t</td> 9998 <td align=left> 9999   0: off; 1: enable RTL clock 8T amsbus ctrl_out  29:29 <br> 10000 Reset value is 0x0.</td></tr> 10001 <tr bgcolor=WHITE> 10002 <td bgcolor=WHITE align=center valign=top>12:06</td> 10003 <td align=left valign=top>RW</td> 10004 <td align=left valign=top>ams_pll_vco_range</td> 10005 <td align=left> 10006   VCO freq control bits. Refer to AMS VCO table for frequency details. amsbus ctrl_out  28:22 <br> 10007 Reset value is 0x0.</td></tr> 10008 <tr bgcolor=WHITE> 10009 <td bgcolor=WHITE align=center valign=top>05</td> 10010 <td align=left valign=top>RW</td> 10011 <td align=left valign=top>ams_pll_en_8p5g_vco</td> 10012 <td align=left> 10013   8.5G mode control. Turn on extra capacitor band. 1'b0 for gen1/2, 1'b1 for gen3  amsbus ctrl_out  21:21 <br> 10014 Reset value is 0x0.</td></tr> 10015 <tr bgcolor=WHITE> 10016 <td bgcolor=WHITE align=center valign=top>04</td> 10017 <td align=left valign=top>RW</td> 10018 <td align=left valign=top>ams_pll_spare_1_0</td> 10019 <td align=left> 10020   AMS reserved[20:20] amsbus ctrl_out  20:20 <br> 10021 Reset value is 0x0.</td></tr> 10022 <tr bgcolor=WHITE> 10023 <td bgcolor=WHITE align=center valign=top>03:00</td> 10024 <td align=left valign=top>RW</td> 10025 <td align=left valign=top>ams_pll_curr_sel</td> 10026 <td align=left> 10027   Change Ipump (diffenrential) current settings, step size of 100uA. amsbus ctrl_out  19:16 <br> 10028 Reset value is 0x7.</td></tr> 10029 </table><p> 10030 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10031 <hr> 10032 <b><a NAME="AMS_COM_PLL_CTRL_2">AMS_COM_PLL_CTRL_2 - PLL_CTRL_2</a></b><br> 10033 Address Offset = 32'h0000_d0b2<br> 10034 Physical Address = 32'h0000_d0b2<br> 10035 Reset Value = 16'h0080<br> 10036 Access = RW (16-bit only)<br> 10037 <table border=1 align=center width=100% cellpadding=0> 10038 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10039 <tr bgcolor=WHITE> 10040 <td bgcolor=WHITE align=center valign=top>15:14</td> 10041 <td align=left valign=top>RW</td> 10042 <td align=left valign=top>ams_pll_en_i4iqbuf</td> 10043 <td align=left> 10044   Control IQ TX/RX buffer current. amsbus ctrl_out  47:46 <br> 10045 Reset value is 0x0.</td></tr> 10046 <tr bgcolor=WHITE> 10047 <td bgcolor=WHITE align=center valign=top>13:10</td> 10048 <td align=left valign=top>RW</td> 10049 <td align=left valign=top>ams_pll_vcobuf_pon</td> 10050 <td align=left> 10051   Resistor Calibration control setting, used to control VCO buffer current as well. Dfs=0 for offset value. amsbus ctrl_out  45:42 <br> 10052 Reset value is 0x0.</td></tr> 10053 <tr bgcolor=WHITE> 10054 <td bgcolor=WHITE align=center valign=top>09</td> 10055 <td align=left valign=top>RW</td> 10056 <td align=left valign=top>ams_pll_clkvco_cal_invert</td> 10057 <td align=left> 10058   Edge selection for VCO calibration (0:rising edge, 1:falling edge) amsbus ctrl_out  41:41 <br> 10059 Reset value is 0x0.</td></tr> 10060 <tr bgcolor=WHITE> 10061 <td bgcolor=WHITE align=center valign=top>08</td> 10062 <td align=left valign=top>RW</td> 10063 <td align=left valign=top>ams_pll_en_cmos_refclk_ch_hiz</td> 10064 <td align=left> 10065   1: Enable o_pll_cmos_refclk when it is used as an input or output channel,0:default amsbus ctrl_out  40:40 <br> 10066 Reset value is 0x0.</td></tr> 10067 <tr bgcolor=WHITE> 10068 <td bgcolor=WHITE align=center valign=top>07:05</td> 10069 <td align=left valign=top>RW</td> 10070 <td align=left valign=top>ams_pll_calib_adj</td> 10071 <td align=left> 10072   Set control voltage for the calibration. amsbus ctrl_out  39:37 <br> 10073 Reset value is 0x4.</td></tr> 10074 <tr bgcolor=WHITE> 10075 <td bgcolor=WHITE align=center valign=top>04</td> 10076 <td align=left valign=top>RW</td> 10077 <td align=left valign=top>ams_pll_en_8p5g</td> 10078 <td align=left> 10079   8.5G mode control, trun on extra capacitor band to lower VCO frequency. 1'b0 for gen1/2, 1'b1 for gen3  amsbus ctrl_out  36:36 <br> 10080 Reset value is 0x0.</td></tr> 10081 <tr bgcolor=WHITE> 10082 <td bgcolor=WHITE align=center valign=top>03:00</td> 10083 <td align=left valign=top>RW</td> 10084 <td align=left valign=top>ams_pll_vco_pon</td> 10085 <td align=left> 10086   Resistor Calibration control setting, used to control VCO current as well. Dfs=0 for offset value amsbus ctrl_out  35:32 <br> 10087 Reset value is 0x0.</td></tr> 10088 </table><p> 10089 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10090 <hr> 10091 <b><a NAME="AMS_COM_PLL_CTRL_3">AMS_COM_PLL_CTRL_3 - PLL_CTRL_3</a></b><br> 10092 Address Offset = 32'h0000_d0b3<br> 10093 Physical Address = 32'h0000_d0b3<br> 10094 Reset Value = 16'h460e<br> 10095 Access = RW (16-bit only)<br> 10096 <table border=1 align=center width=100% cellpadding=0> 10097 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10098 <tr bgcolor=WHITE> 10099 <td bgcolor=WHITE align=center valign=top>15</td> 10100 <td align=left valign=top>RW</td> 10101 <td align=left valign=top>ams_pll_en_mmd_halfrate</td> 10102 <td align=left> 10103   0: Use 1T clock; 1: Use 2T clock amsbus ctrl_out  63:63 <br> 10104 Reset value is 0x0.</td></tr> 10105 <tr bgcolor=WHITE> 10106 <td bgcolor=WHITE align=center valign=top>14:12</td> 10107 <td align=left valign=top>RW</td> 10108 <td align=left valign=top>ams_pll_cp_bias</td> 10109 <td align=left> 10110   CP Bias setting amsbus ctrl_out  62:60 <br> 10111 Reset value is 0x4.</td></tr> 10112 <tr bgcolor=WHITE> 10113 <td bgcolor=WHITE align=center valign=top>11</td> 10114 <td align=left valign=top>RW</td> 10115 <td align=left valign=top>ams_pll_spare_3_0</td> 10116 <td align=left> 10117   AMS reserved[59:59] amsbus ctrl_out  59:59 <br> 10118 Reset value is 0x0.</td></tr> 10119 <tr bgcolor=WHITE> 10120 <td bgcolor=WHITE align=center valign=top>10</td> 10121 <td align=left valign=top>RW</td> 10122 <td align=left valign=top>ams_pll_ref_cmos_hz</td> 10123 <td align=left> 10124   When pll_ctrl<54>=1 0: refcmos is not high Z;when pll_ctrl<54>=0 X: refcmos is high Z amsbus ctrl_out  58:58 <br> 10125 Reset value is 0x1.</td></tr> 10126 <tr bgcolor=WHITE> 10127 <td bgcolor=WHITE align=center valign=top>09</td> 10128 <td align=left valign=top>RW</td> 10129 <td align=left valign=top>ams_pll_ref_cml_pd</td> 10130 <td align=left> 10131   When pll_ctrl<53>=1 0: CML reference is on; When pll_ctrl<53>=0 X: CML reference is off amsbus ctrl_out  57:57 <br> 10132 Reset value is 0x1.</td></tr> 10133 <tr bgcolor=WHITE> 10134 <td bgcolor=WHITE align=center valign=top>08</td> 10135 <td align=left valign=top>RW</td> 10136 <td align=left valign=top>ams_pll_clksel</td> 10137 <td align=left> 10138   Select the clock source for en_cmos_refout. amsbus ctrl_out  56:56 <br> 10139 Reset value is 0x0.</td></tr> 10140 <tr bgcolor=WHITE> 10141 <td bgcolor=WHITE align=center valign=top>07</td> 10142 <td align=left valign=top>RW</td> 10143 <td align=left valign=top>ams_pll_en_rclk_refout</td> 10144 <td align=left> 10145   1:select RX recovered clk as the clock source for en_cmos_refout. amsbus ctrl_out  55:55 <br> 10146 Reset value is 0x0.</td></tr> 10147 <tr bgcolor=WHITE> 10148 <td bgcolor=WHITE align=center valign=top>06</td> 10149 <td align=left valign=top>RW</td> 10150 <td align=left valign=top>ams_pll_en_cmos_refout_overwr</td> 10151 <td align=left> 10152   1:en_cmos_refout thru pll_ctrl[58], 0:thru refsel<2> pin. en_cmos_refout_overwrite in AMS amsbus ctrl_out  54:54 <br> 10153 Reset value is 0x0.</td></tr> 10154 <tr bgcolor=WHITE> 10155 <td bgcolor=WHITE align=center valign=top>05</td> 10156 <td align=left valign=top>RW</td> 10157 <td align=left valign=top>ams_pll_en_cml_refout_overwr</td> 10158 <td align=left> 10159   1:en_cml_refout thru pll_ctrl[57], 0:thru i_pd_CML_refclk_out pin. en_cml_refout_overwrite in AMS amsbus ctrl_out  53:53 <br> 10160 Reset value is 0x0.</td></tr> 10161 <tr bgcolor=WHITE> 10162 <td bgcolor=WHITE align=center valign=top>04</td> 10163 <td align=left valign=top>RW</td> 10164 <td align=left valign=top>ams_pll_en_test_frac_clk</td> 10165 <td align=left> 10166   1:enable frac-N divider (MMD) output as CMOS test clock amsbus ctrl_out  52:52 <br> 10167 Reset value is 0x0.</td></tr> 10168 <tr bgcolor=WHITE> 10169 <td bgcolor=WHITE align=center valign=top>03</td> 10170 <td align=left valign=top>RW</td> 10171 <td align=left valign=top>ams_pll_enb_16t</td> 10172 <td align=left> 10173   1: Enable o_pll_cmos_vco16; 0: Off amsbus ctrl_out  51:51 <br> 10174 Reset value is 0x1.</td></tr> 10175 <tr bgcolor=WHITE> 10176 <td bgcolor=WHITE align=center valign=top>02:00</td> 10177 <td align=left valign=top>RW</td> 10178 <td align=left valign=top>ams_pll_band_iqbuf_ctr</td> 10179 <td align=left> 10180   TX/RX IQ Clock buffer band controls amsbus ctrl_out  50:48 <br> 10181 Reset value is 0x6.</td></tr> 10182 </table><p> 10183 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10184 <hr> 10185 <b><a NAME="AMS_COM_PLL_CTRL_4">AMS_COM_PLL_CTRL_4 - PLL_CTRL_4</a></b><br> 10186 Address Offset = 32'h0000_d0b4<br> 10187 Physical Address = 32'h0000_d0b4<br> 10188 Reset Value = 16'h1511<br> 10189 Access = RW (16-bit only)<br> 10190 <table border=1 align=center width=100% cellpadding=0> 10191 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10192 <tr bgcolor=WHITE> 10193 <td bgcolor=WHITE align=center valign=top>15</td> 10194 <td align=left valign=top>RSVD</td> 10195 <td align=left valign=top>Reserved</td> 10196 <td align=left> 10197 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 10198 <tr bgcolor=WHITE> 10199 <td bgcolor=WHITE align=center valign=top>14:12</td> 10200 <td align=left valign=top>RW</td> 10201 <td align=left valign=top>ams_pll_test_sel</td> 10202 <td align=left> 10203   Selects the signal to be tested  pcie3: RC=3'b001(refclk); EP=3'b000 amsbus ctrl_out  78:76 <br> 10204 Reset value is 0x1.</td></tr> 10205 <tr bgcolor=WHITE> 10206 <td bgcolor=WHITE align=center valign=top>11:10</td> 10207 <td align=left valign=top>RW</td> 10208 <td align=left valign=top>ams_pll_test_amp</td> 10209 <td align=left> 10210   Sets amplitude without changing the output impedence amsbus ctrl_out  75:74 <br> 10211 Reset value is 0x1.</td></tr> 10212 <tr bgcolor=WHITE> 10213 <td bgcolor=WHITE align=center valign=top>09</td> 10214 <td align=left valign=top>RW</td> 10215 <td align=left valign=top>ams_pll_vco_test_clk_en</td> 10216 <td align=left> 10217   VCO Divider Test Enable  pcie3: RC=1'b1; EP=1'b0 amsbus ctrl_out  73:73 <br> 10218 Reset value is 0x0.</td></tr> 10219 <tr bgcolor=WHITE> 10220 <td bgcolor=WHITE align=center valign=top>08</td> 10221 <td align=left valign=top>RW</td> 10222 <td align=left valign=top>ams_pll_bias_en</td> 10223 <td align=left> 10224   0: Bias Block is Off; 1: Normal Operation, Bias Enabled amsbus ctrl_out  72:72 <br> 10225 Reset value is 0x1.</td></tr> 10226 <tr bgcolor=WHITE> 10227 <td bgcolor=WHITE align=center valign=top>07</td> 10228 <td align=left valign=top>RW</td> 10229 <td align=left valign=top>ams_pll_spare4_2</td> 10230 <td align=left> 10231   VCO_HKVCO: 0=lo KVCO, 1=hi KVCO  AMS reserved[71:71] amsbus ctrl_out  71:71 <br> 10232 Reset value is 0x0.</td></tr> 10233 <tr bgcolor=WHITE> 10234 <td bgcolor=WHITE align=center valign=top>06:05</td> 10235 <td align=left valign=top>RW</td> 10236 <td align=left valign=top>ams_pll_bias_vdd_sel</td> 10237 <td align=left> 10238   00: 0.80V; 01: 0.88V; 10: 0.73V; 11: 0.98V amsbus ctrl_out  70:69 <br> 10239 Reset value is 0x0.</td></tr> 10240 <tr bgcolor=WHITE> 10241 <td bgcolor=WHITE align=center valign=top>04</td> 10242 <td align=left valign=top>RW</td> 10243 <td align=left valign=top>ams_pll_spare4_1</td> 10244 <td align=left> 10245   AMS reserved[68:68] amsbus ctrl_out  68:68 <br> 10246 Reset value is 0x1.</td></tr> 10247 <tr bgcolor=WHITE> 10248 <td bgcolor=WHITE align=center valign=top>03:02</td> 10249 <td align=left valign=top>RW</td> 10250 <td align=left valign=top>ams_pll_cp_opamp_bias</td> 10251 <td align=left> 10252   increase ref current for the CP. amsbus ctrl_out  67:66 <br> 10253 Reset value is 0x0.</td></tr> 10254 <tr bgcolor=WHITE> 10255 <td bgcolor=WHITE align=center valign=top>01:00</td> 10256 <td align=left valign=top>RW</td> 10257 <td align=left valign=top>ams_pll_lc_refclk_adj_3_2</td> 10258 <td align=left> 10259   Set the refclk input and output bias for LC ref channel amsbus ctrl_out  65:64 <br> 10260 Reset value is 0x1.</td></tr> 10261 </table><p> 10262 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10263 <hr> 10264 <b><a NAME="AMS_COM_PLL_CTRL_5">AMS_COM_PLL_CTRL_5 - PLL_CTRL_5</a></b><br> 10265 Address Offset = 32'h0000_d0b5<br> 10266 Physical Address = 32'h0000_d0b5<br> 10267 Reset Value = 16'h1415<br> 10268 Access = RW (16-bit only)<br> 10269 <table border=1 align=center width=100% cellpadding=0> 10270 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10271 <tr bgcolor=WHITE> 10272 <td bgcolor=WHITE align=center valign=top>15:13</td> 10273 <td align=left valign=top>RSVD</td> 10274 <td align=left valign=top>Reserved</td> 10275 <td align=left> 10276 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10277 <tr bgcolor=WHITE> 10278 <td bgcolor=WHITE align=center valign=top>12:10</td> 10279 <td align=left valign=top>RW</td> 10280 <td align=left valign=top>ams_pll_refdiv_test_sel</td> 10281 <td align=left> 10282   not used for PCIe3; RC needs glitchless refclk  Reference Divider Test Selection amsbus ctrl_out  91:89 <br> 10283 Reset value is 0x5.</td></tr> 10284 <tr bgcolor=WHITE> 10285 <td bgcolor=WHITE align=center valign=top>09</td> 10286 <td align=left valign=top>RW</td> 10287 <td align=left valign=top>ams_pll_pwdb_extr_d2c</td> 10288 <td align=left> 10289   0: power down the dummy D2C for IQ buffer amsbus ctrl_out  88:88 <br> 10290 Reset value is 0x0.</td></tr> 10291 <tr bgcolor=WHITE> 10292 <td bgcolor=WHITE align=center valign=top>08</td> 10293 <td align=left valign=top>RW</td> 10294 <td align=left valign=top>ams_pll_en_refout_div</td> 10295 <td align=left> 10296   0: Reference Divider Off; 1: Reference Divider On amsbus ctrl_out  87:87 <br> 10297 Reset value is 0x0.</td></tr> 10298 <tr bgcolor=WHITE> 10299 <td bgcolor=WHITE align=center valign=top>07</td> 10300 <td align=left valign=top>RW</td> 10301 <td align=left valign=top>ams_pll_pwrdn</td> 10302 <td align=left> 10303   1= Power down the PLL core (~8mA reduction) amsbus ctrl_out  86:86 <br> 10304 Reset value is 0x0.</td></tr> 10305 <tr bgcolor=WHITE> 10306 <td bgcolor=WHITE align=center valign=top>06:05</td> 10307 <td align=left valign=top>RW</td> 10308 <td align=left valign=top>ams_pll_term_sel</td> 10309 <td align=left> 10310   reference clock pairs input termination. REFCLK input term_sel in AMS amsbus ctrl_out  85:84 <br> 10311 Reset value is 0x0.</td></tr> 10312 <tr bgcolor=WHITE> 10313 <td bgcolor=WHITE align=center valign=top>04</td> 10314 <td align=left valign=top>RW</td> 10315 <td align=left valign=top>ams_pll_test_sel_overwrite</td> 10316 <td align=left> 10317   0: testport sel thr i_testsel[2:0], 1: testport sel thr pll_ctrl[78:76]. amsbus ctrl_out  83:83 <br> 10318 Reset value is 0x1.</td></tr> 10319 <tr bgcolor=WHITE> 10320 <td bgcolor=WHITE align=center valign=top>03</td> 10321 <td align=left valign=top>RW</td> 10322 <td align=left valign=top>ams_pll_test_vc</td> 10323 <td align=left> 10324   Enable VCO control voltage on PTESTP/N; active high amsbus ctrl_out  82:82 <br> 10325 Reset value is 0x0.</td></tr> 10326 <tr bgcolor=WHITE> 10327 <td bgcolor=WHITE align=center valign=top>02:00</td> 10328 <td align=left valign=top>RW</td> 10329 <td align=left valign=top>ams_pll_refout_div_sel</td> 10330 <td align=left> 10331   reference divider selection amsbus ctrl_out  81:79 <br> 10332 Reset value is 0x5.</td></tr> 10333 </table><p> 10334 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10335 <hr> 10336 <b><a NAME="AMS_COM_PLL_CTRL_6">AMS_COM_PLL_CTRL_6 - PLL_CTRL_6</a></b><br> 10337 Address Offset = 32'h0000_d0b6<br> 10338 Physical Address = 32'h0000_d0b6<br> 10339 Reset Value = 16'h0000<br> 10340 Access = RW (16-bit only)<br> 10341 <table border=1 align=center width=100% cellpadding=0> 10342 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10343 <tr bgcolor=WHITE> 10344 <td bgcolor=WHITE align=center valign=top>15:12</td> 10345 <td align=left valign=top>RW</td> 10346 <td align=left valign=top>ams_pll_i_ndiv_frac_l</td> 10347 <td align=left> 10348   Fractional control of feedback divider[3:0] amsbus ctrl_out  107:104 <br> 10349 Reset value is 0x0.</td></tr> 10350 <tr bgcolor=WHITE> 10351 <td bgcolor=WHITE align=center valign=top>11:10</td> 10352 <td align=left valign=top>RW</td> 10353 <td align=left valign=top>ams_pll_pfd_offset</td> 10354 <td align=left> 10355   In frac-N mode, reset pulse can be offset by 664ps(typical)/418ps(min), pfd_offset in AMS. amsbus ctrl_out  103:102 <br> 10356 Reset value is 0x0.</td></tr> 10357 <tr bgcolor=WHITE> 10358 <td bgcolor=WHITE align=center valign=top>09</td> 10359 <td align=left valign=top>RW</td> 10360 <td align=left valign=top>ams_pll_spare6_1</td> 10361 <td align=left> 10362   AMS reserved[101:101] amsbus ctrl_out  101:101 <br> 10363 Reset value is 0x0.</td></tr> 10364 <tr bgcolor=WHITE> 10365 <td bgcolor=WHITE align=center valign=top>08</td> 10366 <td align=left valign=top>RW</td> 10367 <td align=left valign=top>ams_pll_pfd_offset_enlarge</td> 10368 <td align=left> 10369   1: In offset_PFD mode, offset is extended by ~300ps. pfd_offset_enlarge in AMS. amsbus ctrl_out  100:100 <br> 10370 Reset value is 0x0.</td></tr> 10371 <tr bgcolor=WHITE> 10372 <td bgcolor=WHITE align=center valign=top>07:06</td> 10373 <td align=left valign=top>RW</td> 10374 <td align=left valign=top>ams_pll_vco_i_boost</td> 10375 <td align=left> 10376   VCO Current Boost, 00: 100%, 01: 130%, 10: 130%, 11: 160% amsbus ctrl_out  99:98 <br> 10377 Reset value is 0x0.</td></tr> 10378 <tr bgcolor=WHITE> 10379 <td bgcolor=WHITE align=center valign=top>05:04</td> 10380 <td align=left valign=top>RW</td> 10381 <td align=left valign=top>ams_pll_vco_gm_boost</td> 10382 <td align=left> 10383   VCO GM boost, 00: 100%, 01: 116%, 10: 116%, 11: 132% amsbus ctrl_out  97:96 <br> 10384 Reset value is 0x0.</td></tr> 10385 <tr bgcolor=WHITE> 10386 <td bgcolor=WHITE align=center valign=top>03:00</td> 10387 <td align=left valign=top>RW</td> 10388 <td align=left valign=top>ams_pll_pon</td> 10389 <td align=left> 10390   Resistor Calibration Control Setting, dfs=0 for offset value. amsbus ctrl_out  95:92 <br> 10391 Reset value is 0x0.</td></tr> 10392 </table><p> 10393 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10394 <hr> 10395 <b><a NAME="AMS_COM_PLL_CTRL_7">AMS_COM_PLL_CTRL_7 - PLL_CTRL_7</a></b><br> 10396 Address Offset = 32'h0000_d0b7<br> 10397 Physical Address = 32'h0000_d0b7<br> 10398 Reset Value = 16'h0000<br> 10399 Access = RW (16-bit only)<br> 10400 <table border=1 align=center width=100% cellpadding=0> 10401 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10402 <tr bgcolor=WHITE> 10403 <td bgcolor=WHITE align=center valign=top>15:14</td> 10404 <td align=left valign=top>RSVD</td> 10405 <td align=left valign=top>Reserved</td> 10406 <td align=left> 10407 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10408 <tr bgcolor=WHITE> 10409 <td bgcolor=WHITE align=center valign=top>13:00</td> 10410 <td align=left valign=top>RW</td> 10411 <td align=left valign=top>ams_pll_i_ndiv_frac_h</td> 10412 <td align=left> 10413   Fractional control of feedback divider[17:4] amsbus ctrl_out  121:108 <br> 10414 Reset value is 0x0.</td></tr> 10415 </table><p> 10416 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10417 <hr> 10418 <b><a NAME="AMS_COM_PLL_CTRL_8">AMS_COM_PLL_CTRL_8 - PLL_CTRL_8</a></b><br> 10419 Address Offset = 32'h0000_d0b8<br> 10420 Physical Address = 32'h0000_d0b8<br> 10421 Reset Value = 16'h4442<br> 10422 Access = RW (16-bit only)<br> 10423 <table border=1 align=center width=100% cellpadding=0> 10424 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10425 <tr bgcolor=WHITE> 10426 <td bgcolor=WHITE align=center valign=top>15</td> 10427 <td align=left valign=top>RW</td> 10428 <td align=left valign=top>ams_pll_i_ndiv_dither_en</td> 10429 <td align=left> 10430   Enable 1 bit dithering of the fractional input amsbus ctrl_out  137:137 <br> 10431 Reset value is 0x0.</td></tr> 10432 <tr bgcolor=WHITE> 10433 <td bgcolor=WHITE align=center valign=top>14</td> 10434 <td align=left valign=top>RW</td> 10435 <td align=left valign=top>ams_pll_i_pll_sdm_pwrdnb</td> 10436 <td align=left> 10437   Power down sdm rtl only when LOW amsbus ctrl_out  136:136 <br> 10438 Reset value is 0x1.</td></tr> 10439 <tr bgcolor=WHITE> 10440 <td bgcolor=WHITE align=center valign=top>13:12</td> 10441 <td align=left valign=top>RW</td> 10442 <td align=left valign=top>ams_pll_vcofb_div</td> 10443 <td align=left> 10444   VCO feedback divider amsbus ctrl_out  135:134 <br> 10445 Reset value is 0x0.</td></tr> 10446 <tr bgcolor=WHITE> 10447 <td bgcolor=WHITE align=center valign=top>11:10</td> 10448 <td align=left valign=top>RW</td> 10449 <td align=left valign=top>ams_pll_cml_refclk_bias</td> 10450 <td align=left> 10451   Set the refclk input and output bias for CML ref channel amsbus ctrl_out  133:132 <br> 10452 Reset value is 0x1.</td></tr> 10453 <tr bgcolor=WHITE> 10454 <td bgcolor=WHITE align=center valign=top>09:00</td> 10455 <td align=left valign=top>RW</td> 10456 <td align=left valign=top>ams_pll_i_ndiv_int</td> 10457 <td align=left> 10458   Feedback divider integer control (divider ratio=code) amsbus ctrl_out  131:122 <br> 10459 Reset value is 0x42.</td></tr> 10460 </table><p> 10461 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10462 <hr> 10463 <b><a NAME="AMS_COM_PLL_CTRL_9">AMS_COM_PLL_CTRL_9 - PLL_CTRL_9</a></b><br> 10464 Address Offset = 32'h0000_d0b9<br> 10465 Physical Address = 32'h0000_d0b9<br> 10466 Reset Value = 16'h5285<br> 10467 Access = RW (16-bit only)<br> 10468 <table border=1 align=center width=100% cellpadding=0> 10469 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10470 <tr bgcolor=WHITE> 10471 <td bgcolor=WHITE align=center valign=top>15:14</td> 10472 <td align=left valign=top>RW</td> 10473 <td align=left valign=top>ams_pll_cml_refclk_adj</td> 10474 <td align=left> 10475   Set the refclk input and output bias for CML ref channel amsbus ctrl_out  153:152 <br> 10476 Reset value is 0x1.</td></tr> 10477 <tr bgcolor=WHITE> 10478 <td bgcolor=WHITE align=center valign=top>13:11</td> 10479 <td align=left valign=top>RW</td> 10480 <td align=left valign=top>ams_pll_bias_iq_ctrl</td> 10481 <td align=left> 10482   control current biasing for the IQ buffer. bias_IQ_ctrl in AMS amsbus ctrl_out  151:149 <br> 10483 Reset value is 0x2.</td></tr> 10484 <tr bgcolor=WHITE> 10485 <td bgcolor=WHITE align=center valign=top>10:08</td> 10486 <td align=left valign=top>RW</td> 10487 <td align=left valign=top>ams_pll_bias_div_ctrl</td> 10488 <td align=left> 10489   control current biasing for the CML divider. amsbus ctrl_out  148:146 <br> 10490 Reset value is 0x2.</td></tr> 10491 <tr bgcolor=WHITE> 10492 <td bgcolor=WHITE align=center valign=top>07</td> 10493 <td align=left valign=top>RW</td> 10494 <td align=left valign=top>ams_pll_vco_supply_adj</td> 10495 <td align=left> 10496   0: 0.88VDD; 1: 0.80VDD amsbus ctrl_out  145:145 <br> 10497 Reset value is 0x1.</td></tr> 10498 <tr bgcolor=WHITE> 10499 <td bgcolor=WHITE align=center valign=top>06:03</td> 10500 <td align=left valign=top>RW</td> 10501 <td align=left valign=top>ams_pll_sel_fp3cap</td> 10502 <td align=left> 10503   Controls the filter cap for the third loop filter pole in WIS mode amsbus ctrl_out  144:141 <br> 10504 Reset value is 0x0.</td></tr> 10505 <tr bgcolor=WHITE> 10506 <td bgcolor=WHITE align=center valign=top>02:01</td> 10507 <td align=left valign=top>RW</td> 10508 <td align=left valign=top>ams_pll_i_pll_frac_mode</td> 10509 <td align=left> 10510   integer division mapping for MMD amsbus ctrl_out  140:139 <br> 10511 Reset value is 0x2.</td></tr> 10512 <tr bgcolor=WHITE> 10513 <td bgcolor=WHITE align=center valign=top>00</td> 10514 <td align=left valign=top>RW</td> 10515 <td align=left valign=top>ams_pll_mmd_resetb</td> 10516 <td align=left> 10517   Reset Delta Sigma modulator. amsbus ctrl_out  138:138 <br> 10518 Reset value is 0x1.</td></tr> 10519 </table><p> 10520 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10521 <hr> 10522 <b><a NAME="AMS_COM_PLL_CTRL_10">AMS_COM_PLL_CTRL_10 - PLL_CTRL_10</a></b><br> 10523 Address Offset = 32'h0000_d0ba<br> 10524 Physical Address = 32'h0000_d0ba<br> 10525 Reset Value = 16'h0015<br> 10526 Access = RW (16-bit only)<br> 10527 <table border=1 align=center width=100% cellpadding=0> 10528 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10529 <tr bgcolor=WHITE> 10530 <td bgcolor=WHITE align=center valign=top>15:11</td> 10531 <td align=left valign=top>RSVD</td> 10532 <td align=left valign=top>Reserved</td> 10533 <td align=left> 10534 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10535 <tr bgcolor=WHITE> 10536 <td bgcolor=WHITE align=center valign=top>10</td> 10537 <td align=left valign=top>RW</td> 10538 <td align=left valign=top>ams_pll_tx_clkmaster_ovrd</td> 10539 <td align=left> 10540 mdio override for tx_clkmaster ctrls '0'=normal, '1'=overrides pll_ctrl[164:160] below.<br> 10541 Reset value is 0x0.</td></tr> 10542 <tr bgcolor=WHITE> 10543 <td bgcolor=WHITE align=center valign=top>09:08</td> 10544 <td align=left valign=top>RW</td> 10545 <td align=left valign=top>ams_pll_tx_clkmaster_ctrl_a</td> 10546 <td align=left> 10547 mdio override, normally driven by serdes port '00'=tristate, '01'=input enabled, '10'=output enabled. amsbus ctrl_out  163:162 <br> 10548 Reset value is 0x0.</td></tr> 10549 <tr bgcolor=WHITE> 10550 <td bgcolor=WHITE align=center valign=top>07:06</td> 10551 <td align=left valign=top>RW</td> 10552 <td align=left valign=top>ams_pll_tx_clkmaster_ctrl_b</td> 10553 <td align=left> 10554 mdio override, normally driven by serdes port '00'=tristate, '01'=input enabled, '10'=output enabled. amsbus ctrl_out  161:160 <br> 10555 Reset value is 0x0.</td></tr> 10556 <tr bgcolor=WHITE> 10557 <td bgcolor=WHITE align=center valign=top>05:00</td> 10558 <td align=left valign=top>RW</td> 10559 <td align=left valign=top>ams_pll_refclk_in_bias</td> 10560 <td align=left> 10561   set refclk input bias. amsbus ctrl_out  159:154 <br> 10562 Reset value is 0x15.</td></tr> 10563 </table><p> 10564 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10565 <hr> 10566 <b><a NAME="AMS_COM_PLL_INT">AMS_COM_PLL_INT - PLL_CTRL_INT</a></b><br> 10567 Address Offset = 32'h0000_d0be<br> 10568 Physical Address = 32'h0000_d0be<br> 10569 Reset Value = 16'h0000<br> 10570 Access = RW (16-bit only)<br> 10571 <table border=1 align=center width=100% cellpadding=0> 10572 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10573 <tr bgcolor=WHITE> 10574 <td bgcolor=WHITE align=center valign=top>15:04</td> 10575 <td align=left valign=top>RSVD</td> 10576 <td align=left valign=top>Reserved</td> 10577 <td align=left> 10578 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10579 <tr bgcolor=WHITE> 10580 <td bgcolor=WHITE align=center valign=top>03</td> 10581 <td align=left valign=top>RW</td> 10582 <td align=left valign=top>ams_pll_refclk_term_frc</td> 10583 <td align=left> 10584   0: refclk termination control driven from from input pins; 1: driven from term_sel register<br> 10585 Reset value is 0x0.</td></tr> 10586 <tr bgcolor=WHITE> 10587 <td bgcolor=WHITE align=center valign=top>02</td> 10588 <td align=left valign=top>RW</td> 10589 <td align=left valign=top>ams_pll_refclk_div_frc</td> 10590 <td align=left> 10591   force refclk_div value from register bits instead of pins pmd_refclk_div2 and pmd_refclk_div4<br> 10592 Reset value is 0x0.</td></tr> 10593 <tr bgcolor=WHITE> 10594 <td bgcolor=WHITE align=center valign=top>01</td> 10595 <td align=left valign=top>RW</td> 10596 <td align=left valign=top>ams_pll_refclk_div2_frc_val</td> 10597 <td align=left> 10598   force value for refclk_div2 when refclk_div_frc set to 1 in register<br> 10599 Reset value is 0x0.</td></tr> 10600 <tr bgcolor=WHITE> 10601 <td bgcolor=WHITE align=center valign=top>00</td> 10602 <td align=left valign=top>RW</td> 10603 <td align=left valign=top>ams_pll_refclk_div4_frc_val</td> 10604 <td align=left> 10605   force value for refclk_div4 when refclk_div_frc set to 1 in register<br> 10606 Reset value is 0x0.</td></tr> 10607 </table><p> 10608 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10609 <hr> 10610 <b><a NAME="AMS_COM_PLL_STS">AMS_COM_PLL_STS - PLL_STS</a></b><br> 10611 Address Offset = 32'h0000_d0bf<br> 10612 Physical Address = 32'h0000_d0bf<br> 10613 Reset Value = 16'h0000<br> 10614 Access = RO (16-bit only)<br> 10615 <table border=1 align=center width=100% cellpadding=0> 10616 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10617 <tr bgcolor=WHITE> 10618 <td bgcolor=WHITE align=center valign=top>15:04</td> 10619 <td align=left valign=top>RSVD</td> 10620 <td align=left valign=top>Reserved</td> 10621 <td align=left> 10622 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10623 <tr bgcolor=WHITE> 10624 <td bgcolor=WHITE align=center valign=top>03:00</td> 10625 <td align=left valign=top>RO</td> 10626 <td align=left valign=top>ams_pll_afe_rev_id</td> 10627 <td align=left> 10628   AFE o_rev_id[3:0] output<br> 10629 Reset value is 0x0.</td></tr> 10630 </table><p> 10631 <A HREF="#AMS_COM Registers">Return to AMS_COM: common register block for all lanes Table</A><p> 10632 <hr> 10633 <H1><a NAME="SIGDET Registers">SIGDET: per lane register block [One Copy Per Lane] Registers</a></H1> 10634 <table border=1 align=center width=100% cellpadding=0> 10635 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 10636 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 10637 <tr> 10638 <td align=center>0xD0C3</td><td><A HREF="#SIGDET_CTRL_3">SIGDET_CTRL_3</A><br>CTRL_3</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_tsc_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_rxinfeidledis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_rxl0sl1failure_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_rx_afe_pwrdn_bypass</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">rg_rxl0sl1failure_cnt</div> </td> <td align=center>16'h04ff</td></tr> 10639 <tr> 10640 <td align=center>0xD0C4</td><td><A HREF="#SIGDET_CTRL_4">SIGDET_CTRL_4</A><br>CTRL_4</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rg_sigdet_plllock_tmr</div> </td> <td align=center>16'h4e20</td></tr> 10641 <tr> 10642 <td align=center>0xD0C5</td><td><A HREF="#SIGDET_CTRL_5">SIGDET_CTRL_5</A><br>CTRL_5</td><td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">rg_sigdet_eieos_tmr</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">rg_sigdet_wait_tmr</div> </td> <td align=center>16'h34c2</td></tr> 10643 <tr> 10644 <td align=center>0xD0C6</td><td><A HREF="#SIGDET_CTRL_6">SIGDET_CTRL_6</A><br>CTRL_6</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_tggl_cnt_clr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_filter_sel_gen1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_filter_sel_gen2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_filter_sel_gen3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_sm_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_sm_rst</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_eieos_det_bypass</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_eieos_detect_cnt</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_eios_det_bypass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_eios_detect_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rg_eios_detect_cnt</div> </td> <td align=center>16'h0882</td></tr> 10645 <tr> 10646 <td align=center>0xD0C7</td><td><A HREF="#SIGDET_CTRL_7">SIGDET_CTRL_7</A><br>CTRL_7</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rg_sigdet_cnt_src_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rg_sigdet_raw_qlfy_len_refclk</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_sigdet_filter_len_refclk_gen1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_sigdet_filter_len_refclk_gen2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_sigdet_filter_len_refclk_gen3</div> </td> <td align=center>16'h0000</td></tr> 10647 <tr> 10648 <td align=center>0xD0C8</td><td><A HREF="#SIGDET_CTRL_8">SIGDET_CTRL_8</A><br>CTRL_8</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rg_sigdet_raw_qlfy_len_auxclk</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_sigdet_filter_len_auxclk_gen1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_sigdet_filter_len_auxclk_gen2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rg_sigdet_filter_len_auxclk_gen3</div> </td> <td align=center>16'h0000</td></tr> 10649 <tr> 10650 <td align=center>0xD0C9</td><td><A HREF="#SIGDET_CTRL_9">SIGDET_CTRL_9</A><br>CTRL_9</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_rloop_sigdet_sm_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rg_sigdet_thresh_gen2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rg_sigdet_thresh_gen3_hi</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rg_sigdet_thresh_gen3_lo</div> </td> <td align=center>16'h298a</td></tr> 10651 <tr> 10652 <td align=center>0xD0CA</td><td><A HREF="#SIGDET_SIGDET_STAT_0">SIGDET_SIGDET_STAT_0</A><br>SIGDET_STAT_0</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">afe_sigdet_thresh_1</div> </td> <td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_sigdet_mac</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_sigdet_dsc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_sigdet_raw</div> </td> <td align=center>16'h0000</td></tr> 10653 <tr> 10654 <td align=center>0xD0CB</td><td><A HREF="#SIGDET_SIGDET_STAT_1">SIGDET_SIGDET_STAT_1</A><br>SIGDET_STAT_1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rg_sigdet_tggl_cnt</div> </td> <td align=center>16'h0000</td></tr> 10655 <tr> 10656 <td align=center>0xD0CD</td><td><A HREF="#SIGDET_CTRL_10">SIGDET_CTRL_10</A><br>CTRL_10</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">spares_sigdet</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rg_sigdet_thresh_gen1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_sigdet_deassert_tmr_sel</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">rg_sigdet_deassert_tmr</div> </td> <td align=center>16'h050d</td></tr> 10657 </table><p> 10658 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 10659 <hr> 10660 <b><a NAME="SIGDET_CTRL_3">SIGDET_CTRL_3 - CTRL_3</a></b><br> 10661 Address Offset = 32'h0000_d0c3<br> 10662 Physical Address = 32'h0000_d0c3<br> 10663 Reset Value = 16'h04ff<br> 10664 Access = RW (16-bit only)<br> 10665 <table border=1 align=center width=100% cellpadding=0> 10666 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10667 <tr bgcolor=WHITE> 10668 <td bgcolor=WHITE align=center valign=top>15</td> 10669 <td align=left valign=top>RW</td> 10670 <td align=left valign=top>rg_sigdet_tsc_sel</td> 10671 <td align=left> 10672 default = pcie3 sigdet, 1'b1 = tsc_s1gdet <br> 10673 Reset value is 0x0.</td></tr> 10674 <tr bgcolor=WHITE> 10675 <td bgcolor=WHITE align=center valign=top>14</td> 10676 <td align=left valign=top>RW</td> 10677 <td align=left valign=top>rg_sigdet_frc</td> 10678 <td align=left> 10679 Override sigdet output with a programmable value. <br> 10680 Reset value is 0x0.</td></tr> 10681 <tr bgcolor=WHITE> 10682 <td bgcolor=WHITE align=center valign=top>13</td> 10683 <td align=left valign=top>RW</td> 10684 <td align=left valign=top>rg_sigdet_frc_val</td> 10685 <td align=left> 10686 Sigdet output state when overrided by setting sigdet_frc. <br> 10687 Reset value is 0x0.</td></tr> 10688 <tr bgcolor=WHITE> 10689 <td bgcolor=WHITE align=center valign=top>12</td> 10690 <td align=left valign=top>RW</td> 10691 <td align=left valign=top>rg_rxinfeidledis</td> 10692 <td align=left> 10693 Disable Inferred Electrical Idle received from MAC. <br> 10694 Reset value is 0x0.</td></tr> 10695 <tr bgcolor=WHITE> 10696 <td bgcolor=WHITE align=center valign=top>11</td> 10697 <td align=left valign=top>RW</td> 10698 <td align=left valign=top>rg_rxl0sl1failure_dis</td> 10699 <td align=left> 10700 Disable L0s/L1 Failure signal received from MAC. <br> 10701 Reset value is 0x0.</td></tr> 10702 <tr bgcolor=WHITE> 10703 <td bgcolor=WHITE align=center valign=top>10</td> 10704 <td align=left valign=top>RW</td> 10705 <td align=left valign=top>rg_rx_afe_pwrdn_bypass</td> 10706 <td align=left> 10707 Bypass EIEOS detect when AFE rx is powered off. <br> 10708 Reset value is 0x1.</td></tr> 10709 <tr bgcolor=WHITE> 10710 <td bgcolor=WHITE align=center valign=top>09:00</td> 10711 <td align=left valign=top>RW</td> 10712 <td align=left valign=top>rg_rxl0sl1failure_cnt</td> 10713 <td align=left> 10714 The number of cycles that rx_sigdet_dsc is deasserted when MAC pulses L0s/L1 exit failure. <br> 10715 Reset value is 0xff.</td></tr> 10716 </table><p> 10717 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10718 <hr> 10719 <b><a NAME="SIGDET_CTRL_4">SIGDET_CTRL_4 - CTRL_4</a></b><br> 10720 Address Offset = 32'h0000_d0c4<br> 10721 Physical Address = 32'h0000_d0c4<br> 10722 Reset Value = 16'h4e20<br> 10723 Access = RW (16-bit only)<br> 10724 <table border=1 align=center width=100% cellpadding=0> 10725 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10726 <tr bgcolor=WHITE> 10727 <td bgcolor=WHITE align=center valign=top>15:00</td> 10728 <td align=left valign=top>RW</td> 10729 <td align=left valign=top>rg_sigdet_plllock_tmr</td> 10730 <td align=left> 10731 Timeout value for EIEOS detection in number of comclk. <br> 10732 Reset value is 0x4e20.</td></tr> 10733 </table><p> 10734 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10735 <hr> 10736 <b><a NAME="SIGDET_CTRL_5">SIGDET_CTRL_5 - CTRL_5</a></b><br> 10737 Address Offset = 32'h0000_d0c5<br> 10738 Physical Address = 32'h0000_d0c5<br> 10739 Reset Value = 16'h34c2<br> 10740 Access = RW (16-bit only)<br> 10741 <table border=1 align=center width=100% cellpadding=0> 10742 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10743 <tr bgcolor=WHITE> 10744 <td bgcolor=WHITE align=center valign=top>15:06</td> 10745 <td align=left valign=top>RW</td> 10746 <td align=left valign=top>rg_sigdet_eieos_tmr</td> 10747 <td align=left> 10748 Timeout value for EIEOS detection in number of comclk. <br> 10749 Reset value is 0xd3.</td></tr> 10750 <tr bgcolor=WHITE> 10751 <td bgcolor=WHITE align=center valign=top>05:00</td> 10752 <td align=left valign=top>RW</td> 10753 <td align=left valign=top>rg_sigdet_wait_tmr</td> 10754 <td align=left> 10755 Timeout value for WAIT state in number of comclk. <br> 10756 Reset value is 0x2.</td></tr> 10757 </table><p> 10758 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10759 <hr> 10760 <b><a NAME="SIGDET_CTRL_6">SIGDET_CTRL_6 - CTRL_6</a></b><br> 10761 Address Offset = 32'h0000_d0c6<br> 10762 Physical Address = 32'h0000_d0c6<br> 10763 Reset Value = 16'h0882<br> 10764 Access = RW (16-bit only)<br> 10765 <table border=1 align=center width=100% cellpadding=0> 10766 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10767 <tr bgcolor=WHITE> 10768 <td bgcolor=WHITE align=center valign=top>15</td> 10769 <td align=left valign=top>RW</td> 10770 <td align=left valign=top>rg_sigdet_tggl_cnt_clr</td> 10771 <td align=left> 10772 Clear Sigdet toggle counter. The counter is reset when this bit transitions from 0 to 1. <br> 10773 Reset value is 0x0.</td></tr> 10774 <tr bgcolor=WHITE> 10775 <td bgcolor=WHITE align=center valign=top>14</td> 10776 <td align=left valign=top>RW</td> 10777 <td align=left valign=top>rg_sigdet_filter_sel_gen1</td> 10778 <td align=left> 10779 Gen1 sigdet filter select. 0 = raw AFE sigdet, 1= filtered sigdet <br> 10780 Reset value is 0x0.</td></tr> 10781 <tr bgcolor=WHITE> 10782 <td bgcolor=WHITE align=center valign=top>13</td> 10783 <td align=left valign=top>RW</td> 10784 <td align=left valign=top>rg_sigdet_filter_sel_gen2</td> 10785 <td align=left> 10786 Gen2 sigdet filter select. 0 = raw AFE sigdet, 1= filtered sigdet <br> 10787 Reset value is 0x0.</td></tr> 10788 <tr bgcolor=WHITE> 10789 <td bgcolor=WHITE align=center valign=top>12</td> 10790 <td align=left valign=top>RW</td> 10791 <td align=left valign=top>rg_sigdet_filter_sel_gen3</td> 10792 <td align=left> 10793 Gen3 sigdet filter select. See sigdet_sm_sel descriptions. <br> 10794 Reset value is 0x0.</td></tr> 10795 <tr bgcolor=WHITE> 10796 <td bgcolor=WHITE align=center valign=top>11</td> 10797 <td align=left valign=top>RW</td> 10798 <td align=left valign=top>rg_sigdet_sm_sel</td> 10799 <td align=left> 10800 Select the output of the Sigdet state machine in Gen3. <br> 10801 sigdet_sm_sel sigdet_filter_sel_gen3 <br> 10802        1                 x                = select output of the Sigdet 10803 FSM <br> 10804        0                 1                = select output of the Sigdet 10805 filter <br> 10806        0                 0                = select raw Sigdet from 10807 AFE <br> 10808 Reset value is 0x1.</td></tr> 10809 <tr bgcolor=WHITE> 10810 <td bgcolor=WHITE align=center valign=top>10</td> 10811 <td align=left valign=top>RW</td> 10812 <td align=left valign=top>rg_sigdet_sm_rst</td> 10813 <td align=left> 10814 Sigdet state machine reset. <br> 10815 Reset value is 0x0.</td></tr> 10816 <tr bgcolor=WHITE> 10817 <td bgcolor=WHITE align=center valign=top>09</td> 10818 <td align=left valign=top>RW</td> 10819 <td align=left valign=top>rg_eieos_det_bypass</td> 10820 <td align=left> 10821 EIEOS detection bypass. <br> 10822 Reset value is 0x0.</td></tr> 10823 <tr bgcolor=WHITE> 10824 <td bgcolor=WHITE align=center valign=top>08:05</td> 10825 <td align=left valign=top>RW</td> 10826 <td align=left valign=top>rg_eieos_detect_cnt</td> 10827 <td align=left> 10828 Number of consecutive 0xff00 patterns required to declare EIEOS. <br> 10829 Reset value is 0x4.</td></tr> 10830 <tr bgcolor=WHITE> 10831 <td bgcolor=WHITE align=center valign=top>04</td> 10832 <td align=left valign=top>RW</td> 10833 <td align=left valign=top>rg_eios_det_bypass</td> 10834 <td align=left> 10835 EIOS detection bypass. <br> 10836 Reset value is 0x0.</td></tr> 10837 <tr bgcolor=WHITE> 10838 <td bgcolor=WHITE align=center valign=top>03</td> 10839 <td align=left valign=top>RW</td> 10840 <td align=left valign=top>rg_eios_detect_sel</td> 10841 <td align=left> 10842 Selecte EIOS. 0 = early EIOS detection, 1 = aligned EIOS detection. <br> 10843 Reset value is 0x0.</td></tr> 10844 <tr bgcolor=WHITE> 10845 <td bgcolor=WHITE align=center valign=top>02:00</td> 10846 <td align=left valign=top>RW</td> 10847 <td align=left valign=top>rg_eios_detect_cnt</td> 10848 <td align=left> 10849 Number of consecutive 20-bit EIOS pattern required to declare EIOS. <br> 10850 Reset value is 0x2.</td></tr> 10851 </table><p> 10852 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10853 <hr> 10854 <b><a NAME="SIGDET_CTRL_7">SIGDET_CTRL_7 - CTRL_7</a></b><br> 10855 Address Offset = 32'h0000_d0c7<br> 10856 Physical Address = 32'h0000_d0c7<br> 10857 Reset Value = 16'h0000<br> 10858 Access = RW (16-bit only)<br> 10859 <table border=1 align=center width=100% cellpadding=0> 10860 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10861 <tr bgcolor=WHITE> 10862 <td bgcolor=WHITE align=center valign=top>15:14</td> 10863 <td align=left valign=top>RW</td> 10864 <td align=left valign=top>rg_sigdet_cnt_src_sel</td> 10865 <td align=left> 10866 0:sigdet_filt 1:rx_sigdet_dsc 2:rx_sigdet_mac<br> 10867 Reset value is 0x0.</td></tr> 10868 <tr bgcolor=WHITE> 10869 <td bgcolor=WHITE align=center valign=top>13:12</td> 10870 <td align=left valign=top>RW</td> 10871 <td align=left valign=top>rg_sigdet_raw_qlfy_len_refclk</td> 10872 <td align=left> 10873 Raw sigdet high-time qualify length when refclk is selected. 0 = pass through. <br> 10874 Reset value is 0x0.</td></tr> 10875 <tr bgcolor=WHITE> 10876 <td bgcolor=WHITE align=center valign=top>11:08</td> 10877 <td align=left valign=top>RW</td> 10878 <td align=left valign=top>rg_sigdet_filter_len_refclk_gen1</td> 10879 <td align=left> 10880 Gen1 sigdet filter length when refclk is selected. The actual filter length is one more than value in this field. <br> 10881 Reset value is 0x0.</td></tr> 10882 <tr bgcolor=WHITE> 10883 <td bgcolor=WHITE align=center valign=top>07:04</td> 10884 <td align=left valign=top>RW</td> 10885 <td align=left valign=top>rg_sigdet_filter_len_refclk_gen2</td> 10886 <td align=left> 10887 Gen2 sigdet filter length when refclk is selected. The actual filter length is one more than value in this field. <br> 10888 Reset value is 0x0.</td></tr> 10889 <tr bgcolor=WHITE> 10890 <td bgcolor=WHITE align=center valign=top>03:00</td> 10891 <td align=left valign=top>RW</td> 10892 <td align=left valign=top>rg_sigdet_filter_len_refclk_gen3</td> 10893 <td align=left> 10894 Gen3 sigdet filter length when refclk is selected. The actual filter length is one more than value in this field. <br> 10895 Reset value is 0x0.</td></tr> 10896 </table><p> 10897 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10898 <hr> 10899 <b><a NAME="SIGDET_CTRL_8">SIGDET_CTRL_8 - CTRL_8</a></b><br> 10900 Address Offset = 32'h0000_d0c8<br> 10901 Physical Address = 32'h0000_d0c8<br> 10902 Reset Value = 16'h0000<br> 10903 Access = RW (16-bit only)<br> 10904 <table border=1 align=center width=100% cellpadding=0> 10905 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10906 <tr bgcolor=WHITE> 10907 <td bgcolor=WHITE align=center valign=top>15:14</td> 10908 <td align=left valign=top>RSVD</td> 10909 <td align=left valign=top>Reserved</td> 10910 <td align=left> 10911 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10912 <tr bgcolor=WHITE> 10913 <td bgcolor=WHITE align=center valign=top>13:12</td> 10914 <td align=left valign=top>RW</td> 10915 <td align=left valign=top>rg_sigdet_raw_qlfy_len_auxclk</td> 10916 <td align=left> 10917 Raw sigdet high-time qualify length when auxclk is selected. 0 = pass through. <br> 10918 Reset value is 0x0.</td></tr> 10919 <tr bgcolor=WHITE> 10920 <td bgcolor=WHITE align=center valign=top>11:08</td> 10921 <td align=left valign=top>RW</td> 10922 <td align=left valign=top>rg_sigdet_filter_len_auxclk_gen1</td> 10923 <td align=left> 10924 Gen1 sigdet filter length when auxclk is selected. The actual filter length is one more than value in this field. <br> 10925 Reset value is 0x0.</td></tr> 10926 <tr bgcolor=WHITE> 10927 <td bgcolor=WHITE align=center valign=top>07:04</td> 10928 <td align=left valign=top>RW</td> 10929 <td align=left valign=top>rg_sigdet_filter_len_auxclk_gen2</td> 10930 <td align=left> 10931 Gen2 sigdet filter length when auxclk is selected. The actual filter length is one more than value in this field. <br> 10932 Reset value is 0x0.</td></tr> 10933 <tr bgcolor=WHITE> 10934 <td bgcolor=WHITE align=center valign=top>03:00</td> 10935 <td align=left valign=top>RW</td> 10936 <td align=left valign=top>rg_sigdet_filter_len_auxclk_gen3</td> 10937 <td align=left> 10938 Gen3 sigdet filter length when auxclk is selected. The actual filter length is one more than value in this field. <br> 10939 Reset value is 0x0.</td></tr> 10940 </table><p> 10941 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10942 <hr> 10943 <b><a NAME="SIGDET_CTRL_9">SIGDET_CTRL_9 - CTRL_9</a></b><br> 10944 Address Offset = 32'h0000_d0c9<br> 10945 Physical Address = 32'h0000_d0c9<br> 10946 Reset Value = 16'h298a<br> 10947 Access = RW (16-bit only)<br> 10948 <table border=1 align=center width=100% cellpadding=0> 10949 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10950 <tr bgcolor=WHITE> 10951 <td bgcolor=WHITE align=center valign=top>15</td> 10952 <td align=left valign=top>RW</td> 10953 <td align=left valign=top>rg_rloop_sigdet_sm_sel</td> 10954 <td align=left> 10955 Use G3 sigdet state machine in rloop mode <br> 10956 Reset value is 0x0.</td></tr> 10957 <tr bgcolor=WHITE> 10958 <td bgcolor=WHITE align=center valign=top>14:10</td> 10959 <td align=left valign=top>RW</td> 10960 <td align=left valign=top>rg_sigdet_thresh_gen2</td> 10961 <td align=left> 10962 Gen2 AFE sigdet threshold. <br> 10963 Reset value is 0xa.</td></tr> 10964 <tr bgcolor=WHITE> 10965 <td bgcolor=WHITE align=center valign=top>09:05</td> 10966 <td align=left valign=top>RW</td> 10967 <td align=left valign=top>rg_sigdet_thresh_gen3_hi</td> 10968 <td align=left> 10969 Gen3 AFE sigdet high threshold. <br> 10970 Reset value is 0xc.</td></tr> 10971 <tr bgcolor=WHITE> 10972 <td bgcolor=WHITE align=center valign=top>04:00</td> 10973 <td align=left valign=top>RW</td> 10974 <td align=left valign=top>rg_sigdet_thresh_gen3_lo</td> 10975 <td align=left> 10976 Gen3 AFE sigdet low threshold. <br> 10977 Reset value is 0xa.</td></tr> 10978 </table><p> 10979 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 10980 <hr> 10981 <b><a NAME="SIGDET_SIGDET_STAT_0">SIGDET_SIGDET_STAT_0 - SIGDET_STAT_0</a></b><br> 10982 Address Offset = 32'h0000_d0ca<br> 10983 Physical Address = 32'h0000_d0ca<br> 10984 Reset Value = 16'h0000<br> 10985 Access = RO (16-bit only)<br> 10986 <table border=1 align=center width=100% cellpadding=0> 10987 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 10988 <tr bgcolor=WHITE> 10989 <td bgcolor=WHITE align=center valign=top>15:13</td> 10990 <td align=left valign=top>RSVD</td> 10991 <td align=left valign=top>Reserved</td> 10992 <td align=left> 10993 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 10994 <tr bgcolor=WHITE> 10995 <td bgcolor=WHITE align=center valign=top>12:08</td> 10996 <td align=left valign=top>RO</td> 10997 <td align=left valign=top>afe_sigdet_thresh_1</td> 10998 <td align=left> 10999 AFE rx sigdet threshold value. <br> 11000 Reset value is 0x0.</td></tr> 11001 <tr bgcolor=WHITE> 11002 <td bgcolor=WHITE align=center valign=top>07:03</td> 11003 <td align=left valign=top>RSVD</td> 11004 <td align=left valign=top>Reserved</td> 11005 <td align=left> 11006 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11007 <tr bgcolor=WHITE> 11008 <td bgcolor=WHITE align=center valign=top>02</td> 11009 <td align=left valign=top>RO</td> 11010 <td align=left valign=top>rx_sigdet_mac</td> 11011 <td align=left> 11012 rx sigdet sent to MAC. <br> 11013 Reset value is 0x0.</td></tr> 11014 <tr bgcolor=WHITE> 11015 <td bgcolor=WHITE align=center valign=top>01</td> 11016 <td align=left valign=top>RO</td> 11017 <td align=left valign=top>rx_sigdet_dsc</td> 11018 <td align=left> 11019 rx sigdet sent to DSC_SM. <br> 11020 Reset value is 0x0.</td></tr> 11021 <tr bgcolor=WHITE> 11022 <td bgcolor=WHITE align=center valign=top>00</td> 11023 <td align=left valign=top>RO</td> 11024 <td align=left valign=top>afe_sigdet_raw</td> 11025 <td align=left> 11026 Raw analog rx sigdet. <br> 11027 Reset value is 0x0.</td></tr> 11028 </table><p> 11029 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 11030 <hr> 11031 <b><a NAME="SIGDET_SIGDET_STAT_1">SIGDET_SIGDET_STAT_1 - SIGDET_STAT_1</a></b><br> 11032 Address Offset = 32'h0000_d0cb<br> 11033 Physical Address = 32'h0000_d0cb<br> 11034 Reset Value = 16'h0000<br> 11035 Access = RO (16-bit only)<br> 11036 <table border=1 align=center width=100% cellpadding=0> 11037 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11038 <tr bgcolor=WHITE> 11039 <td bgcolor=WHITE align=center valign=top>15:00</td> 11040 <td align=left valign=top>RO</td> 11041 <td align=left valign=top>rg_sigdet_tggl_cnt</td> 11042 <td align=left> 11043 Number of times filtered sigdet has transitioned from low to high. <br> 11044 Reset value is 0x0.</td></tr> 11045 </table><p> 11046 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 11047 <hr> 11048 <b><a NAME="SIGDET_CTRL_10">SIGDET_CTRL_10 - CTRL_10</a></b><br> 11049 Address Offset = 32'h0000_d0cd<br> 11050 Physical Address = 32'h0000_d0cd<br> 11051 Reset Value = 16'h050d<br> 11052 Access = RW (16-bit only)<br> 11053 <table border=1 align=center width=100% cellpadding=0> 11054 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11055 <tr bgcolor=WHITE> 11056 <td bgcolor=WHITE align=center valign=top>15:12</td> 11057 <td align=left valign=top>RW</td> 11058 <td align=left valign=top>spares_sigdet</td> 11059 <td align=left> 11060 spares sigdet . <br> 11061 Reset value is 0x0.</td></tr> 11062 <tr bgcolor=WHITE> 11063 <td bgcolor=WHITE align=center valign=top>11:07</td> 11064 <td align=left valign=top>RW</td> 11065 <td align=left valign=top>rg_sigdet_thresh_gen1</td> 11066 <td align=left> 11067 Gen1 AFE sigdet threshold. <br> 11068 Reset value is 0xa.</td></tr> 11069 <tr bgcolor=WHITE> 11070 <td bgcolor=WHITE align=center valign=top>06</td> 11071 <td align=left valign=top>RW</td> 11072 <td align=left valign=top>rg_sigdet_deassert_tmr_sel</td> 11073 <td align=left> 11074 Rx sigdet timer select on de-assertion. <br> 11075 Reset value is 0x0.</td></tr> 11076 <tr bgcolor=WHITE> 11077 <td bgcolor=WHITE align=center valign=top>05:00</td> 11078 <td align=left valign=top>RW</td> 11079 <td align=left valign=top>rg_sigdet_deassert_tmr</td> 11080 <td align=left> 11081 Rx sigdet timer on de-assertion. <br> 11082 Reset value is 0xd.</td></tr> 11083 </table><p> 11084 <A HREF="#SIGDET Registers">Return to SIGDET: per lane register block [One Copy Per Lane] Table</A><p> 11085 <hr> 11086 <H1><a NAME="TLB_RX Registers">TLB_RX: per lane register block [One Copy Per Lane] Registers</a></H1> 11087 <table border=1 align=center width=100% cellpadding=0> 11088 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 11089 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 11090 <tr> 11091 <td align=center>0xD0D0</td><td><A HREF="#TLB_RX_PRBS_CHK_CNT_CONFIG">TLB_RX_PRBS_CHK_CNT_CONFIG</A><br>PRBS Checker Count Control</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">prbs_chk_ool_cnt</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">prbs_chk_lock_cnt</div> </td> <td align=center>16'h0602</td></tr> 11092 <tr> 11093 <td align=center>0xD0D1</td><td><A HREF="#TLB_RX_PRBS_CHK_CONFIG">TLB_RX_PRBS_CHK_CONFIG</A><br>PRBS Checker Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_burst_err_cnt_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_clk_en_frc_on</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">trnsum_error_count_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_err_cnt_burst_mode</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_en_auto_mode</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_chk_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_inv</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">prbs_chk_mode_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_en</div> </td> <td align=center>16'h002a</td></tr> 11094 <tr> 11095 <td align=center>0xD0D2</td><td><A HREF="#TLB_RX_DIG_LPBK_CONFIG">TLB_RX_DIG_LPBK_CONFIG</A><br>Digital Loopback Control</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig_lpbk_pd_bias_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig_lpbk_pd_flt_bypass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig_lpbk_pd_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig_lpbk_en</div> </td> <td align=center>16'h000e</td></tr> 11096 <tr> 11097 <td align=center>0xD0D3</td><td><A HREF="#TLB_RX_TLB_RX_MISC_CONFIG">TLB_RX_TLB_RX_MISC_CONFIG</A><br>TLB RX Misc. Control</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dbg_mask_dig_lpbk_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_aggregator_bypass_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pmd_dp_invert</div> </td> <td align=center>16'h0000</td></tr> 11098 <tr> 11099 <td align=center>0xD0D4</td><td><A HREF="#TLB_RX_PRBS_CHK_EN_TIMER_CONTROL">TLB_RX_PRBS_CHK_EN_TIMER_CONTROL</A><br>TLB RX PRBS Checker Enable Timer Control</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">prbs_chk_en_timeout</div> </td> <td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">prbs_chk_en_timer_mode</div> </td> <td align=center>16'h0000</td></tr> 11100 <tr> 11101 <td align=center>0xD0D5</td><td><A HREF="#TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS">TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS</A><br>PRBS Checker Burst Error Counter Status</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">prbs_chk_burst_err_cnt</div> </td> <td align=center>16'h0000</td></tr> 11102 <tr> 11103 <td align=center>0xD0D6</td><td><A HREF="#TLB_RX_DBG_PMD_RX_LOCK_STATUS">TLB_RX_DBG_PMD_RX_LOCK_STATUS</A><br>Debug PMD RX LOCK Status</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dbg_pmd_rx_lock_change</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dbg_pmd_rx_lock</div> </td> <td align=center>16'h0000</td></tr> 11104 <tr> 11105 <td align=center>0xD0D7</td><td><A HREF="#TLB_RX_UC_PMD_RX_LOCK_STATUS">TLB_RX_UC_PMD_RX_LOCK_STATUS</A><br>Debug PMD RX LOCK Status</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_pmd_rx_lock_change</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_pmd_rx_lock</div> </td> <td align=center>16'h0000</td></tr> 11106 <tr> 11107 <td align=center>0xD0D8</td><td><A HREF="#TLB_RX_DIG_LPBK_PD_STATUS">TLB_RX_DIG_LPBK_PD_STATUS</A><br>Digital Loopback Status</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig_lpbk_pd_early_ind</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dig_lpbk_pd_late_ind</div> </td> <td align=center>16'h0002</td></tr> 11108 <tr> 11109 <td align=center>0xD0D9</td><td><A HREF="#TLB_RX_PRBS_CHK_LOCK_STATUS">TLB_RX_PRBS_CHK_LOCK_STATUS</A><br>PRBS Checker LOCK Status</td><td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">prbs_chk_err_cnt_no_clr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_lock</div> </td> <td align=center>16'h0000</td></tr> 11110 <tr> 11111 <td align=center>0xD0DA</td><td><A HREF="#TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS">TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS</A><br>PRBS Checker Error Counter MSB Status</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_chk_lock_lost_lh</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">prbs_chk_err_cnt_msb</div> </td> <td align=center>16'h8000</td></tr> 11112 <tr> 11113 <td align=center>0xD0DB</td><td><A HREF="#TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS">TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS</A><br>PRBS Checker Error Counter LSB Status</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">prbs_chk_err_cnt_lsb</div> </td> <td align=center>16'h0000</td></tr> 11114 <tr> 11115 <td align=center>0xD0DC</td><td><A HREF="#TLB_RX_PMD_RX_LOCK_STATUS">TLB_RX_PMD_RX_LOCK_STATUS</A><br>PMD RX LOCK Status</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_rx_lock_change</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_rx_lock</div> </td> <td align=center>16'h0000</td></tr> 11116 </table><p> 11117 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 11118 <hr> 11119 <b><a NAME="TLB_RX_PRBS_CHK_CNT_CONFIG">TLB_RX_PRBS_CHK_CNT_CONFIG - PRBS Checker Count Control</a></b><br> 11120 Address Offset = 32'h0000_d0d0<br> 11121 Physical Address = 32'h0000_d0d0<br> 11122 Reset Value = 16'h0602<br> 11123 Access = RW (16-bit only)<br> 11124 <table border=1 align=center width=100% cellpadding=0> 11125 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11126 <tr bgcolor=WHITE> 11127 <td bgcolor=WHITE align=center valign=top>15:13</td> 11128 <td align=left valign=top>RSVD</td> 11129 <td align=left valign=top>Reserved</td> 11130 <td align=left> 11131 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11132 <tr bgcolor=WHITE> 11133 <td bgcolor=WHITE align=center valign=top>12:08</td> 11134 <td align=left valign=top>RW</td> 11135 <td align=left valign=top>prbs_chk_ool_cnt</td> 11136 <td align=left> 11137 specifies the number of consecutive valid clock cycles with 1 or more bit errors  <br> 11138 for PRBS checker to go out of PRBS lock state. Valid values are 0 to 31 where  <br> 11139 0 indicate that PRBS will go out of lock as soon as it gets the first clock cycle with 1 or more bit errors. <br> 11140 likewise 31 indicates that PRBS will go out of lock as soon as it gets the 32 consecutive clocks with 1 or more errors. <br> 11141 Reset value is 0x6.</td></tr> 11142 <tr bgcolor=WHITE> 11143 <td bgcolor=WHITE align=center valign=top>07:05</td> 11144 <td align=left valign=top>RSVD</td> 11145 <td align=left valign=top>Reserved</td> 11146 <td align=left> 11147 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11148 <tr bgcolor=WHITE> 11149 <td bgcolor=WHITE align=center valign=top>04:00</td> 11150 <td align=left valign=top>RW</td> 11151 <td align=left valign=top>prbs_chk_lock_cnt</td> 11152 <td align=left> 11153 specifies the number of consecutive valid clock cycles without any bit error <br> 11154 for PRBS checker to go into PRBS lock state. Valid values are 0 to 31 where  <br> 11155 0 indicate that PRBS will lock as soon as it gets the first clock cycle with no bit error. <br> 11156 likewise 31 indicates that PRBS will lock as soon as it gets the 32 consecutive clocks with no error. <br> 11157 Reset value is 0x2.</td></tr> 11158 </table><p> 11159 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11160 <hr> 11161 <b><a NAME="TLB_RX_PRBS_CHK_CONFIG">TLB_RX_PRBS_CHK_CONFIG - PRBS Checker Control</a></b><br> 11162 Address Offset = 32'h0000_d0d1<br> 11163 Physical Address = 32'h0000_d0d1<br> 11164 Reset Value = 16'h002a<br> 11165 Access = RW (16-bit only)<br> 11166 <table border=1 align=center width=100% cellpadding=0> 11167 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11168 <tr bgcolor=WHITE> 11169 <td bgcolor=WHITE align=center valign=top>15</td> 11170 <td align=left valign=top>RW</td> 11171 <td align=left valign=top>prbs_chk_burst_err_cnt_en</td> 11172 <td align=left> 11173 PRBS checker clock enable. <br> 11174      1'b1 will enable the PRBS checker clock. Recommended to be enabled before enabling the prbs_chk_en. <br> 11175 Reset value is 0x0.</td></tr> 11176 <tr bgcolor=WHITE> 11177 <td bgcolor=WHITE align=center valign=top>14:12</td> 11178 <td align=left valign=top>RSVD</td> 11179 <td align=left valign=top>Reserved</td> 11180 <td align=left> 11181 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11182 <tr bgcolor=WHITE> 11183 <td bgcolor=WHITE align=center valign=top>11</td> 11184 <td align=left valign=top>RW</td> 11185 <td align=left valign=top>prbs_chk_clk_en_frc_on</td> 11186 <td align=left> 11187 PRBS checker clock enable. <br> 11188      1'b1 will enable the PRBS checker clock. Recommended to be enabled before enabling the prbs_chk_en. <br> 11189 Reset value is 0x0.</td></tr> 11190 <tr bgcolor=WHITE> 11191 <td bgcolor=WHITE align=center valign=top>10</td> 11192 <td align=left valign=top>RW</td> 11193 <td align=left valign=top>trnsum_error_count_en</td> 11194 <td align=left> 11195 Training sum error counter Mode enable. <br> 11196        1 => will make the PRBS error counter used as trnsum_error counter. PRBS checker can not be used during this mode. <br> 11197        0 => PRBS checker mode. <br> 11198 Reset value is 0x0.</td></tr> 11199 <tr bgcolor=WHITE> 11200 <td bgcolor=WHITE align=center valign=top>09</td> 11201 <td align=left valign=top>RW</td> 11202 <td align=left valign=top>prbs_chk_err_cnt_burst_mode</td> 11203 <td align=left> 11204 PRBS Error Counter Mode.  <br> 11205        1 => Each busrt of error will be counted as 1 error in the error counter. Each error busrt must be separated by 1 error-free cycle 11206 of data which in worst case should be 39 bits. <br> 11207        0 => Each bit error will be counted. <br> 11208 Reset value is 0x0.</td></tr> 11209 <tr bgcolor=WHITE> 11210 <td bgcolor=WHITE align=center valign=top>08</td> 11211 <td align=left valign=top>RSVD</td> 11212 <td align=left valign=top>Reserved</td> 11213 <td align=left> 11214 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 11215 <tr bgcolor=WHITE> 11216 <td bgcolor=WHITE align=center valign=top>07</td> 11217 <td align=left valign=top>RW</td> 11218 <td align=left valign=top>prbs_chk_en_auto_mode</td> 11219 <td align=left> 11220 PRBS Checker Enable Mode Control.  <br> 11221        1 => select (rx_dsc_lock & prbs_chk_en) as PRBS checker enable control. <br> 11222        0 => select                prbs_chk_en  as PRBS checker enable control. <br> 11223 Reset value is 0x0.</td></tr> 11224 <tr bgcolor=WHITE> 11225 <td bgcolor=WHITE align=center valign=top>06:05</td> 11226 <td align=left valign=top>RW</td> 11227 <td align=left valign=top>prbs_chk_mode</td> 11228 <td align=left> 11229 PRBS LOCK state machine select.   <br> 11230        2'd0 -> Self-sync mode w/ hysteresis. PRBS seed register is continuously seeded with previous received bits. <br> 11231                This mode results in faster locking, but bit errors are counted multiple times (often by 3x). <br> 11232        2'd1 -> Initial seed mode w/ hysteresis. PRBS seed registers is seeded with previous received bits only till PRBS lock is  <br> 11233                acquired and then they run locally independently from the received data until the checker goes out of PRBS 11234 lock. <br> 11235        2'd2 -> Initial seed mode w/o hysteresis. Similar to mode 1 above except once locked it stays locked until PRBS is disabled.  11236   <br> 11237        2'd3 -> reserved for future use. <br> 11238 Reset value is 0x1.</td></tr> 11239 <tr bgcolor=WHITE> 11240 <td bgcolor=WHITE align=center valign=top>04</td> 11241 <td align=left valign=top>RW</td> 11242 <td align=left valign=top>prbs_chk_inv</td> 11243 <td align=left> 11244 PRBS Invert enable.<br> 11245      1 => will invert all the data bits to the PRBS checker. <br> 11246      0 => will send normal data to the PRBS checker. <br> 11247 Reset value is 0x0.</td></tr> 11248 <tr bgcolor=WHITE> 11249 <td bgcolor=WHITE align=center valign=top>03:01</td> 11250 <td align=left valign=top>RW</td> 11251 <td align=left valign=top>prbs_chk_mode_sel</td> 11252 <td align=left> 11253 PRBS checker mode select. Selects the PRBS polynomial as shown below <br> 11254      3'd0 -> PRBS 7                    <br> 11255      3'd1 -> PRBS 9                    <br> 11256      3'd2 -> PRBS 11                   <br> 11257      3'd3 -> PRBS 15                   <br> 11258      3'd4 -> PRBS 23                   <br> 11259      3'd5 -> PRBS 31                   <br> 11260      3'd6 -> PRBS 58 (1 + x^39 + x^58) <br> 11261      3'd7 -> reserved for future use.  <br> 11262 Reset value is 0x5.</td></tr> 11263 <tr bgcolor=WHITE> 11264 <td bgcolor=WHITE align=center valign=top>00</td> 11265 <td align=left valign=top>RW</td> 11266 <td align=left valign=top>prbs_chk_en</td> 11267 <td align=left> 11268 PRBS checker enable. <br> 11269      1 => enable  the PRBS checker. <br> 11270      0 => disable the PRBS checker. <br> 11271 Reset value is 0x0.</td></tr> 11272 </table><p> 11273 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11274 <hr> 11275 <b><a NAME="TLB_RX_DIG_LPBK_CONFIG">TLB_RX_DIG_LPBK_CONFIG - Digital Loopback Control</a></b><br> 11276 Address Offset = 32'h0000_d0d2<br> 11277 Physical Address = 32'h0000_d0d2<br> 11278 Reset Value = 16'h000e<br> 11279 Access = RW (16-bit only)<br> 11280 <table border=1 align=center width=100% cellpadding=0> 11281 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11282 <tr bgcolor=WHITE> 11283 <td bgcolor=WHITE align=center valign=top>15:04</td> 11284 <td align=left valign=top>RSVD</td> 11285 <td align=left valign=top>Reserved</td> 11286 <td align=left> 11287 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11288 <tr bgcolor=WHITE> 11289 <td bgcolor=WHITE align=center valign=top>03</td> 11290 <td align=left valign=top>RW</td> 11291 <td align=left valign=top>dig_lpbk_pd_bias_en</td> 11292 <td align=left> 11293 1'b1 will enable PD inc bias mode where there will be inc generated every 16th clock cycle.. <br> 11294 1'b0 will disable the PD bias mode so inc/dec will be generated based on the PD output. <br> 11295 Reset value is 0x1.</td></tr> 11296 <tr bgcolor=WHITE> 11297 <td bgcolor=WHITE align=center valign=top>02</td> 11298 <td align=left valign=top>RW</td> 11299 <td align=left valign=top>dig_lpbk_pd_flt_bypass</td> 11300 <td align=left> 11301 Digital Loopback Phase Detector Filter Bypass. For repeater applications, it should be 1'b1. <br> 11302 For other applications filter can be enabled for better jitter tolerance performance for the didgital loopback. <br> 11303 Reset value is 0x1.</td></tr> 11304 <tr bgcolor=WHITE> 11305 <td bgcolor=WHITE align=center valign=top>01</td> 11306 <td align=left valign=top>RW</td> 11307 <td align=left valign=top>dig_lpbk_pd_mode</td> 11308 <td align=left> 11309 Digital Loopback Phase Detector Mode. For normal operating conditions keep it at the default value of 1'b1. <br> 11310 1'b0 - swap inc/dec. 1'b1 - normal mode. <br> 11311 Reset value is 0x1.</td></tr> 11312 <tr bgcolor=WHITE> 11313 <td bgcolor=WHITE align=center valign=top>00</td> 11314 <td align=left valign=top>RW</td> 11315 <td align=left valign=top>dig_lpbk_en</td> 11316 <td align=left> 11317 TX to RX Parallel Loopback (Digital Loopback) Enable. <br> 11318      1 => Loopback is Enabled.  <br> 11319      0 => Loopback is Disabled. <br> 11320 Reset value is 0x0.</td></tr> 11321 </table><p> 11322 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11323 <hr> 11324 <b><a NAME="TLB_RX_TLB_RX_MISC_CONFIG">TLB_RX_TLB_RX_MISC_CONFIG - TLB RX Misc. Control</a></b><br> 11325 Address Offset = 32'h0000_d0d3<br> 11326 Physical Address = 32'h0000_d0d3<br> 11327 Reset Value = 16'h0000<br> 11328 Access = RW (16-bit only)<br> 11329 <table border=1 align=center width=100% cellpadding=0> 11330 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11331 <tr bgcolor=WHITE> 11332 <td bgcolor=WHITE align=center valign=top>15:03</td> 11333 <td align=left valign=top>RSVD</td> 11334 <td align=left valign=top>Reserved</td> 11335 <td align=left> 11336 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11337 <tr bgcolor=WHITE> 11338 <td bgcolor=WHITE align=center valign=top>02</td> 11339 <td align=left valign=top>RW</td> 11340 <td align=left valign=top>dbg_mask_dig_lpbk_en</td> 11341 <td align=left> 11342 Mask bit for dig_lpbk_en in the pmd_rx_lock equation. This is a debug register. <br> 11343      1 => pmd_rx_lock will be forced to 1'b0 during digital loopback. <br> 11344      0 => pmd_rx_lock will be forced to 1'b1 during digital loopback. <br> 11345 Reset value is 0x0.</td></tr> 11346 <tr bgcolor=WHITE> 11347 <td bgcolor=WHITE align=center valign=top>01</td> 11348 <td align=left valign=top>RW</td> 11349 <td align=left valign=top>rx_aggregator_bypass_en</td> 11350 <td align=left> 11351 RX Aggregator Bypass Enable <br> 11352       When Enabled by writing to 1'b1, DSC Data will bypass the RX Data aggregator block and sent directly to PCS along with a sync pulse which 11353 will indicate the (clk_cnt ==0). <br> 11354       Recommended for use if low latency is desired and where data aggregation will be done in the PCS block based on the sync pulse. <br> 11355 Reset value is 0x0.</td></tr> 11356 <tr bgcolor=WHITE> 11357 <td bgcolor=WHITE align=center valign=top>00</td> 11358 <td align=left valign=top>RW</td> 11359 <td align=left valign=top>rx_pmd_dp_invert</td> 11360 <td align=left> 11361 RX PMD Datapath Invert Control. <br> 11362       When Enabled by writing to 1'b1, it will invert all the datapath bits of the logical lane. <br> 11363       Recommended for use in case P and N pads are swapped on the PCB board. <br> 11364 Reset value is 0x0.</td></tr> 11365 </table><p> 11366 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11367 <hr> 11368 <b><a NAME="TLB_RX_PRBS_CHK_EN_TIMER_CONTROL">TLB_RX_PRBS_CHK_EN_TIMER_CONTROL - TLB RX PRBS Checker Enable Timer Control</a></b><br> 11369 Address Offset = 32'h0000_d0d4<br> 11370 Physical Address = 32'h0000_d0d4<br> 11371 Reset Value = 16'h0000<br> 11372 Access = RW (16-bit only)<br> 11373 <table border=1 align=center width=100% cellpadding=0> 11374 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11375 <tr bgcolor=WHITE> 11376 <td bgcolor=WHITE align=center valign=top>15:13</td> 11377 <td align=left valign=top>RSVD</td> 11378 <td align=left valign=top>Reserved</td> 11379 <td align=left> 11380 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11381 <tr bgcolor=WHITE> 11382 <td bgcolor=WHITE align=center valign=top>12:08</td> 11383 <td align=left valign=top>RW</td> 11384 <td align=left valign=top>prbs_chk_en_timeout</td> 11385 <td align=left> 11386 PRBS timer timeout value. <br> 11387 Valid range 0 to 31 which maps to 0 to 448. Should be programmed before enabling the PRBS checker in timer mode. <br> 11388 Reset value is 0x0.</td></tr> 11389 <tr bgcolor=WHITE> 11390 <td bgcolor=WHITE align=center valign=top>07:02</td> 11391 <td align=left valign=top>RSVD</td> 11392 <td align=left valign=top>Reserved</td> 11393 <td align=left> 11394 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11395 <tr bgcolor=WHITE> 11396 <td bgcolor=WHITE align=center valign=top>01:00</td> 11397 <td align=left valign=top>RW</td> 11398 <td align=left valign=top>prbs_chk_en_timer_mode</td> 11399 <td align=left> 11400 prbs_chk_en timer mode. <br> 11401      2'b0x => prbs_chk_en timer is disabled and PRBS checker mode is enabled as per prbs_chk_en register. <br> 11402      2'b10 => use heartbeat_toggle_1us for the timer. <br> 11403      2'b11 => use heartbeat_toggle_1ms for the timer. <br> 11404 Reset value is 0x0.</td></tr> 11405 </table><p> 11406 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11407 <hr> 11408 <b><a NAME="TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS">TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS - PRBS Checker Burst Error Counter Status</a></b><br> 11409 Address Offset = 32'h0000_d0d5<br> 11410 Physical Address = 32'h0000_d0d5<br> 11411 Reset Value = 16'h0000<br> 11412 Access = RO (16-bit only)<br> 11413 <table border=1 align=center width=100% cellpadding=0> 11414 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11415 <tr bgcolor=WHITE> 11416 <td bgcolor=WHITE align=center valign=top>15:10</td> 11417 <td align=left valign=top>RSVD</td> 11418 <td align=left valign=top>Reserved</td> 11419 <td align=left> 11420 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11421 <tr bgcolor=WHITE> 11422 <td bgcolor=WHITE align=center valign=top>09:00</td> 11423 <td align=left valign=top>RO</td> 11424 <td align=left valign=top>prbs_chk_burst_err_cnt</td> 11425 <td align=left> 11426 PRBS Checker Burst Error Counter Status Register. It is a clear on read register. This register counts <br> 11427 the number of Burst in errors separated by atleast 1 clock cycle worth of data without any bit in error. <br> 11428 Reset value is 0x0.</td></tr> 11429 </table><p> 11430 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11431 <hr> 11432 <b><a NAME="TLB_RX_DBG_PMD_RX_LOCK_STATUS">TLB_RX_DBG_PMD_RX_LOCK_STATUS - Debug PMD RX LOCK Status</a></b><br> 11433 Address Offset = 32'h0000_d0d6<br> 11434 Physical Address = 32'h0000_d0d6<br> 11435 Reset Value = 16'h0000<br> 11436 Access = RO (16-bit only)<br> 11437 <table border=1 align=center width=100% cellpadding=0> 11438 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11439 <tr bgcolor=WHITE> 11440 <td bgcolor=WHITE align=center valign=top>15:02</td> 11441 <td align=left valign=top>RSVD</td> 11442 <td align=left valign=top>Reserved</td> 11443 <td align=left> 11444 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11445 <tr bgcolor=WHITE> 11446 <td bgcolor=WHITE align=center valign=top>01</td> 11447 <td align=left valign=top>RO</td> 11448 <td align=left valign=top>dbg_pmd_rx_lock_change</td> 11449 <td align=left> 11450 Set to 1'b1 when change/transition on PMD RX LOCK. This is a sticky bit and cleared upon read. This is a debug register. <br> 11451 Reset value is 0x0.</td></tr> 11452 <tr bgcolor=WHITE> 11453 <td bgcolor=WHITE align=center valign=top>00</td> 11454 <td align=left valign=top>RO</td> 11455 <td align=left valign=top>dbg_pmd_rx_lock</td> 11456 <td align=left> 11457 Debug PMD RX LOCK Indication. This is a live indication of the status of the pmd_rx_lock output port. <br> 11458                1 => PMD is in LOCKED state and RX PCS data should have acceptable BER.          <br> 11459                0 => PMD is not LOCKED yet.         <br> 11460 Reset value is 0x0.</td></tr> 11461 </table><p> 11462 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11463 <hr> 11464 <b><a NAME="TLB_RX_UC_PMD_RX_LOCK_STATUS">TLB_RX_UC_PMD_RX_LOCK_STATUS - Debug PMD RX LOCK Status</a></b><br> 11465 Address Offset = 32'h0000_d0d7<br> 11466 Physical Address = 32'h0000_d0d7<br> 11467 Reset Value = 16'h0000<br> 11468 Access = RO (16-bit only)<br> 11469 <table border=1 align=center width=100% cellpadding=0> 11470 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11471 <tr bgcolor=WHITE> 11472 <td bgcolor=WHITE align=center valign=top>15:02</td> 11473 <td align=left valign=top>RSVD</td> 11474 <td align=left valign=top>Reserved</td> 11475 <td align=left> 11476 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11477 <tr bgcolor=WHITE> 11478 <td bgcolor=WHITE align=center valign=top>01</td> 11479 <td align=left valign=top>RO</td> 11480 <td align=left valign=top>uc_pmd_rx_lock_change</td> 11481 <td align=left> 11482 Set to 1'b1 when change/transition on PMD RX LOCK. This is a sticky bit and cleared upon read. This is a debug register. <br> 11483 Reset value is 0x0.</td></tr> 11484 <tr bgcolor=WHITE> 11485 <td bgcolor=WHITE align=center valign=top>00</td> 11486 <td align=left valign=top>RO</td> 11487 <td align=left valign=top>uc_pmd_rx_lock</td> 11488 <td align=left> 11489 Debug PMD RX LOCK Indication. This is a live indication of the status of the pmd_rx_lock output port. <br> 11490                1 => PMD is in LOCKED state and RX PCS data should have acceptable BER.          <br> 11491                0 => PMD is not LOCKED yet.         <br> 11492 Reset value is 0x0.</td></tr> 11493 </table><p> 11494 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11495 <hr> 11496 <b><a NAME="TLB_RX_DIG_LPBK_PD_STATUS">TLB_RX_DIG_LPBK_PD_STATUS - Digital Loopback Status</a></b><br> 11497 Address Offset = 32'h0000_d0d8<br> 11498 Physical Address = 32'h0000_d0d8<br> 11499 Reset Value = 16'h0002<br> 11500 Access = RO (16-bit only)<br> 11501 <table border=1 align=center width=100% cellpadding=0> 11502 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11503 <tr bgcolor=WHITE> 11504 <td bgcolor=WHITE align=center valign=top>15:02</td> 11505 <td align=left valign=top>RSVD</td> 11506 <td align=left valign=top>Reserved</td> 11507 <td align=left> 11508 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11509 <tr bgcolor=WHITE> 11510 <td bgcolor=WHITE align=center valign=top>01</td> 11511 <td align=left valign=top>RO</td> 11512 <td align=left valign=top>dig_lpbk_pd_early_ind</td> 11513 <td align=left> 11514 1 means dp_rclk20 is sampling data earlier so delay the dp_rclk20 clock phase. This will result in RX PI phase step increment. <br> 11515 Reset value is 0x1.</td></tr> 11516 <tr bgcolor=WHITE> 11517 <td bgcolor=WHITE align=center valign=top>00</td> 11518 <td align=left valign=top>RO</td> 11519 <td align=left valign=top>dig_lpbk_pd_late_ind</td> 11520 <td align=left> 11521 1 means dp_rclk20 is sampling data late so reduce the delay of the dp_rclk20 clock phase. This will result in RX PI phase step decrement. <br> 11522 Reset value is 0x0.</td></tr> 11523 </table><p> 11524 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11525 <hr> 11526 <b><a NAME="TLB_RX_PRBS_CHK_LOCK_STATUS">TLB_RX_PRBS_CHK_LOCK_STATUS - PRBS Checker LOCK Status</a></b><br> 11527 Address Offset = 32'h0000_d0d9<br> 11528 Physical Address = 32'h0000_d0d9<br> 11529 Reset Value = 16'h0000<br> 11530 Access = RO (16-bit only)<br> 11531 <table border=1 align=center width=100% cellpadding=0> 11532 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11533 <tr bgcolor=WHITE> 11534 <td bgcolor=WHITE align=center valign=top>15:01</td> 11535 <td align=left valign=top>RO</td> 11536 <td align=left valign=top>prbs_chk_err_cnt_no_clr</td> 11537 <td align=left> 11538 PRBS Checker Error Counter which does not get cleared upon read.                  <br> 11539   MSB bit 14 is OR of the MSB bits [30:14] of the internal error counter.         <br> 11540   LSB bits [13:0] are assigned to LSB bits [13:0] of the internal error counter.  <br> 11541   It can be cleared by reading the status register prbs_chk_err_cnt_msb.          <br> 11542 Reset value is 0x0.</td></tr> 11543 <tr bgcolor=WHITE> 11544 <td bgcolor=WHITE align=center valign=top>00</td> 11545 <td align=left valign=top>RO</td> 11546 <td align=left valign=top>prbs_chk_lock</td> 11547 <td align=left> 11548 PRBS Checker LOCK Indication. This is a live indication of the status of the PRBS Checker state machine. <br> 11549                1 => PRBS Checker is in LOCKED state.                        11550                              <br> 11551                0 => PRBS Checker is out of LOCK state and state machine is searching for a LOCK.         11552 <br> 11553 Reset value is 0x0.</td></tr> 11554 </table><p> 11555 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11556 <hr> 11557 <b><a NAME="TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS">TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS - PRBS Checker Error Counter MSB Status</a></b><br> 11558 Address Offset = 32'h0000_d0da<br> 11559 Physical Address = 32'h0000_d0da<br> 11560 Reset Value = 16'h8000<br> 11561 Access = RO (16-bit only)<br> 11562 <table border=1 align=center width=100% cellpadding=0> 11563 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11564 <tr bgcolor=WHITE> 11565 <td bgcolor=WHITE align=center valign=top>15</td> 11566 <td align=left valign=top>RO</td> 11567 <td align=left valign=top>prbs_chk_lock_lost_lh</td> 11568 <td align=left> 11569 PRBS Checker LOCK_LOST Latch High Indication. This register captures the 1->0 transition on the <br> 11570 prbs_chk_lock live status register and keep it latched until read. This is a clear on read status registers.<br> 11571 Reset value is 0x1.</td></tr> 11572 <tr bgcolor=WHITE> 11573 <td bgcolor=WHITE align=center valign=top>14:00</td> 11574 <td align=left valign=top>RO</td> 11575 <td align=left valign=top>prbs_chk_err_cnt_msb</td> 11576 <td align=left> 11577 15 bits MSB portion of PRBS Checker Error Counter Status Register. It is a clear on read register.  <br> 11578 Once MSB bits [30:16] of the counter are read then LSB bits [15:0] of the error counter is loaded  <br> 11579 into a holding register and internal PRBS error counter's all bits are cleared to 0s <br> 11580 (or if there are any error in that particular clock cycle then that will be loaded). <br> 11581 MSB portion must be read first before reading the LSB portion of the error counter.  <br> 11582 Reset value is 0x0.</td></tr> 11583 </table><p> 11584 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11585 <hr> 11586 <b><a NAME="TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS">TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS - PRBS Checker Error Counter LSB Status</a></b><br> 11587 Address Offset = 32'h0000_d0db<br> 11588 Physical Address = 32'h0000_d0db<br> 11589 Reset Value = 16'h0000<br> 11590 Access = RO (16-bit only)<br> 11591 <table border=1 align=center width=100% cellpadding=0> 11592 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11593 <tr bgcolor=WHITE> 11594 <td bgcolor=WHITE align=center valign=top>15:00</td> 11595 <td align=left valign=top>RO</td> 11596 <td align=left valign=top>prbs_chk_err_cnt_lsb</td> 11597 <td align=left> 11598 16 bits LSB portion of PRBS Checker Error Counter Status Register. This register indicates<br> 11599 the value in the holding register when MSB portion [30:16] of the error counter are read. <br> 11600 MSB portion must be read first before reading the LSB portion of the error counter.  <br> 11601 Reset value is 0x0.</td></tr> 11602 </table><p> 11603 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11604 <hr> 11605 <b><a NAME="TLB_RX_PMD_RX_LOCK_STATUS">TLB_RX_PMD_RX_LOCK_STATUS - PMD RX LOCK Status</a></b><br> 11606 Address Offset = 32'h0000_d0dc<br> 11607 Physical Address = 32'h0000_d0dc<br> 11608 Reset Value = 16'h0000<br> 11609 Access = RO (16-bit only)<br> 11610 <table border=1 align=center width=100% cellpadding=0> 11611 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11612 <tr bgcolor=WHITE> 11613 <td bgcolor=WHITE align=center valign=top>15:02</td> 11614 <td align=left valign=top>RSVD</td> 11615 <td align=left valign=top>Reserved</td> 11616 <td align=left> 11617 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11618 <tr bgcolor=WHITE> 11619 <td bgcolor=WHITE align=center valign=top>01</td> 11620 <td align=left valign=top>RO</td> 11621 <td align=left valign=top>pmd_rx_lock_change</td> 11622 <td align=left> 11623 Set to 1'b1 when change/transition on PMD RX LOCK. This is a sticky bit and cleared upon read.<br> 11624 Reset value is 0x0.</td></tr> 11625 <tr bgcolor=WHITE> 11626 <td bgcolor=WHITE align=center valign=top>00</td> 11627 <td align=left valign=top>RO</td> 11628 <td align=left valign=top>pmd_rx_lock</td> 11629 <td align=left> 11630 PMD RX LOCK Indication. This is a live indication of the status of the pmd_rx_lock output port. <br> 11631                1 => PMD is in LOCKED state and RX PCS data should have acceptable BER.          <br> 11632                0 => PMD is not LOCKED yet.         <br> 11633 Reset value is 0x0.</td></tr> 11634 </table><p> 11635 <A HREF="#TLB_RX Registers">Return to TLB_RX: per lane register block [One Copy Per Lane] Table</A><p> 11636 <hr> 11637 <H1><a NAME="TLB_TX Registers">TLB_TX: per lane register block [One Copy Per Lane] Registers</a></H1> 11638 <table border=1 align=center width=100% cellpadding=0> 11639 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 11640 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 11641 <tr> 11642 <td align=center>0xD0E0</td><td><A HREF="#TLB_TX_PATT_GEN_CONFIG">TLB_TX_PATT_GEN_CONFIG</A><br>Pattern Generator Control</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">patt_gen_start_pos</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">patt_gen_stop_pos</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">patt_gen_en</div> </td> <td align=center>16'hb000</td></tr> 11643 <tr> 11644 <td align=center>0xD0E1</td><td><A HREF="#TLB_TX_PRBS_GEN_CONFIG">TLB_TX_PRBS_GEN_CONFIG</A><br>PRBS Generator Control</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_gen_err_ins</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_gen_inv</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">prbs_gen_mode_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">prbs_gen_en</div> </td> <td align=center>16'h000a</td></tr> 11645 <tr> 11646 <td align=center>0xD0E2</td><td><A HREF="#TLB_TX_RMT_LPBK_CONFIG">TLB_TX_RMT_LPBK_CONFIG</A><br>Remote Loopback Control</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rmt_lpbk_pd_frc_on</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rmt_lpbk_pd_mode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rmt_lpbk_en</div> </td> <td align=center>16'h0002</td></tr> 11647 <tr> 11648 <td align=center>0xD0E3</td><td><A HREF="#TLB_TX_TLB_TX_MISC_CONFIG">TLB_TX_TLB_TX_MISC_CONFIG</A><br>TLB TX Misc. Control</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_mux_sel_order</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pcs_native_ana_frmt_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pmd_dp_invert</div> </td> <td align=center>16'h0000</td></tr> 11649 <tr> 11650 <td align=center>0xD0E8</td><td><A HREF="#TLB_TX_RMT_LPBK_PD_STATUS">TLB_TX_RMT_LPBK_PD_STATUS</A><br>Remote Loopback Status</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rmt_lpbk_pd_early_ind</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rmt_lpbk_pd_late_ind</div> </td> <td align=center>16'h0002</td></tr> 11651 </table><p> 11652 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 11653 <hr> 11654 <b><a NAME="TLB_TX_PATT_GEN_CONFIG">TLB_TX_PATT_GEN_CONFIG - Pattern Generator Control</a></b><br> 11655 Address Offset = 32'h0000_d0e0<br> 11656 Physical Address = 32'h0000_d0e0<br> 11657 Reset Value = 16'hb000<br> 11658 Access = RW (16-bit only)<br> 11659 <table border=1 align=center width=100% cellpadding=0> 11660 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11661 <tr bgcolor=WHITE> 11662 <td bgcolor=WHITE align=center valign=top>15:12</td> 11663 <td align=left valign=top>RW</td> 11664 <td align=left valign=top>patt_gen_start_pos</td> 11665 <td align=left> 11666 Valid values are 11 to 0. Defines the start position of the pattern in 20 bit chunks.  <br> 11667 11 means start at bit 239,  <br> 11668 10 means start at bit 219, ...,  <br> 11669   0 means start at bit  19  <br> 11670 so start bit is (rg_patt_gen_start_pos*20 + 19).   <br> 11671 Reset value is 0xb.</td></tr> 11672 <tr bgcolor=WHITE> 11673 <td bgcolor=WHITE align=center valign=top>11:08</td> 11674 <td align=left valign=top>RW</td> 11675 <td align=left valign=top>patt_gen_stop_pos</td> 11676 <td align=left> 11677 Valid values are 11 to 0. Defines the stop  position of the pattern in 20 bit chunks.  <br> 11678 This register value should be less than or equal to rg_patt_gen_start_pos. <br> 11679 11 means stop at bit  220,  <br> 11680 10 means stop at bit  200, ...,    <br> 11681   0 means stop at bit    0  <br> 11682 so stop  bit is (rg_patt_gen_stop_pos*20). <br> 11683 Reset value is 0x0.</td></tr> 11684 <tr bgcolor=WHITE> 11685 <td bgcolor=WHITE align=center valign=top>07:01</td> 11686 <td align=left valign=top>RSVD</td> 11687 <td align=left valign=top>Reserved</td> 11688 <td align=left> 11689 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11690 <tr bgcolor=WHITE> 11691 <td bgcolor=WHITE align=center valign=top>00</td> 11692 <td align=left valign=top>RW</td> 11693 <td align=left valign=top>patt_gen_en</td> 11694 <td align=left> 11695 Fixed pattern generator enable. <br> 11696      1 => enable  the fixed pattern generator. <br> 11697      0 => disable the fixed pattern generator. <br> 11698 Reset value is 0x0.</td></tr> 11699 </table><p> 11700 <A HREF="#TLB_TX Registers">Return to TLB_TX: per lane register block [One Copy Per Lane] Table</A><p> 11701 <hr> 11702 <b><a NAME="TLB_TX_PRBS_GEN_CONFIG">TLB_TX_PRBS_GEN_CONFIG - PRBS Generator Control</a></b><br> 11703 Address Offset = 32'h0000_d0e1<br> 11704 Physical Address = 32'h0000_d0e1<br> 11705 Reset Value = 16'h000a<br> 11706 Access = RW (16-bit only)<br> 11707 <table border=1 align=center width=100% cellpadding=0> 11708 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11709 <tr bgcolor=WHITE> 11710 <td bgcolor=WHITE align=center valign=top>15:06</td> 11711 <td align=left valign=top>RSVD</td> 11712 <td align=left valign=top>Reserved</td> 11713 <td align=left> 11714 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11715 <tr bgcolor=WHITE> 11716 <td bgcolor=WHITE align=center valign=top>05</td> 11717 <td align=left valign=top>RW</td> 11718 <td align=left valign=top>prbs_gen_err_ins</td> 11719 <td align=left> 11720 PRBS Error Insert.<br> 11721      0 to 1 transition on this signal will insert single bit error in the MSB bit of the data bus. <br> 11722 Reset value is 0x0.</td></tr> 11723 <tr bgcolor=WHITE> 11724 <td bgcolor=WHITE align=center valign=top>04</td> 11725 <td align=left valign=top>RW</td> 11726 <td align=left valign=top>prbs_gen_inv</td> 11727 <td align=left> 11728 PRBS Invert enable.<br> 11729      1 => will invert all the data bits from the PRBS generator. <br> 11730      0 => will send normal data from the PRBS generator. <br> 11731 Reset value is 0x0.</td></tr> 11732 <tr bgcolor=WHITE> 11733 <td bgcolor=WHITE align=center valign=top>03:01</td> 11734 <td align=left valign=top>RW</td> 11735 <td align=left valign=top>prbs_gen_mode_sel</td> 11736 <td align=left> 11737 PRBS generator mode select. Selects the PRBS polynomial as shown below <br> 11738      3'd0 -> PRBS 7                    <br> 11739      3'd1 -> PRBS 9                    <br> 11740      3'd2 -> PRBS 11                   <br> 11741      3'd3 -> PRBS 15                   <br> 11742      3'd4 -> PRBS 23                   <br> 11743      3'd5 -> PRBS 31                   <br> 11744      3'd6 -> PRBS 58 (1 + x^39 + x^58) <br> 11745      3'd7 -> reserved for future use.  <br> 11746 Reset value is 0x5.</td></tr> 11747 <tr bgcolor=WHITE> 11748 <td bgcolor=WHITE align=center valign=top>00</td> 11749 <td align=left valign=top>RW</td> 11750 <td align=left valign=top>prbs_gen_en</td> 11751 <td align=left> 11752 PRBS generator enable. <br> 11753      1 => enable  the PRBS generator. <br> 11754      0 => disable the PRBS generator. <br> 11755 Reset value is 0x0.</td></tr> 11756 </table><p> 11757 <A HREF="#TLB_TX Registers">Return to TLB_TX: per lane register block [One Copy Per Lane] Table</A><p> 11758 <hr> 11759 <b><a NAME="TLB_TX_RMT_LPBK_CONFIG">TLB_TX_RMT_LPBK_CONFIG - Remote Loopback Control</a></b><br> 11760 Address Offset = 32'h0000_d0e2<br> 11761 Physical Address = 32'h0000_d0e2<br> 11762 Reset Value = 16'h0002<br> 11763 Access = RW (16-bit only)<br> 11764 <table border=1 align=center width=100% cellpadding=0> 11765 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11766 <tr bgcolor=WHITE> 11767 <td bgcolor=WHITE align=center valign=top>15:03</td> 11768 <td align=left valign=top>RSVD</td> 11769 <td align=left valign=top>Reserved</td> 11770 <td align=left> 11771 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11772 <tr bgcolor=WHITE> 11773 <td bgcolor=WHITE align=center valign=top>02</td> 11774 <td align=left valign=top>RW</td> 11775 <td align=left valign=top>rmt_lpbk_pd_frc_on</td> 11776 <td align=left> 11777 Remote loopback PD enable by force irrespective of rg_rmt_lpbk_en. <br> 11778 1'b1 - enable the phase detector without the remote loopback enable. Can be used to lock RX and TX <br> 11779 clock phases when there is a remote loopback outside PMD <br> 11780 Reset value is 0x0.</td></tr> 11781 <tr bgcolor=WHITE> 11782 <td bgcolor=WHITE align=center valign=top>01</td> 11783 <td align=left valign=top>RW</td> 11784 <td align=left valign=top>rmt_lpbk_pd_mode</td> 11785 <td align=left> 11786 Remote Loopback Phase Detector Mode. For normal operating conditions keep it at the default value of 1'b1. <br> 11787 1'b0 - swap inc/dec. 1'b1 - normal mode. <br> 11788 Reset value is 0x1.</td></tr> 11789 <tr bgcolor=WHITE> 11790 <td bgcolor=WHITE align=center valign=top>00</td> 11791 <td align=left valign=top>RW</td> 11792 <td align=left valign=top>rmt_lpbk_en</td> 11793 <td align=left> 11794 RX to TX Parallel Loopback (Remote Loopback) Enable. <br> 11795      1 => Loopback is Enabled.  <br> 11796      0 => Loopback is Disabled. <br> 11797 Reset value is 0x0.</td></tr> 11798 </table><p> 11799 <A HREF="#TLB_TX Registers">Return to TLB_TX: per lane register block [One Copy Per Lane] Table</A><p> 11800 <hr> 11801 <b><a NAME="TLB_TX_TLB_TX_MISC_CONFIG">TLB_TX_TLB_TX_MISC_CONFIG - TLB TX Misc. Control</a></b><br> 11802 Address Offset = 32'h0000_d0e3<br> 11803 Physical Address = 32'h0000_d0e3<br> 11804 Reset Value = 16'h0000<br> 11805 Access = RW (16-bit only)<br> 11806 <table border=1 align=center width=100% cellpadding=0> 11807 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11808 <tr bgcolor=WHITE> 11809 <td bgcolor=WHITE align=center valign=top>15:03</td> 11810 <td align=left valign=top>RSVD</td> 11811 <td align=left valign=top>Reserved</td> 11812 <td align=left> 11813 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11814 <tr bgcolor=WHITE> 11815 <td bgcolor=WHITE align=center valign=top>02</td> 11816 <td align=left valign=top>RW</td> 11817 <td align=left valign=top>tx_mux_sel_order</td> 11818 <td align=left> 11819 TX Data MUX Select Priority Order. When 1'b1 then priority of Pattern and PRBS generators are swapped w.r.t. CL72. <br> 11820       0 => TX Data Mux select order from higher to lower priority is {rmt_lpbk, patt_gen, cl72_tx, prbs_gen, tx_pcs}. <br> 11821       1 => TX Data Mux select order from higher to lower priority is {rmt_lpbk, prbs_gen, cl72_tx, patt_gen, tx_pcs}. <br> 11822 Reset value is 0x0.</td></tr> 11823 <tr bgcolor=WHITE> 11824 <td bgcolor=WHITE align=center valign=top>01</td> 11825 <td align=left valign=top>RW</td> 11826 <td align=left valign=top>tx_pcs_native_ana_frmt_en</td> 11827 <td align=left> 11828 TX PCS Interface Native Analog Format Enable. <br> 11829       1 => TX PCS Interface is enabled in the Native Analog Format mode. TX PCS sends the over-sampled data in this mode which is sent directly 11830 to AFE. <br> 11831       0 => Raw Data Mode where for every data request TX PCS will send 20 bits of valid data. <br> 11832 Reset value is 0x0.</td></tr> 11833 <tr bgcolor=WHITE> 11834 <td bgcolor=WHITE align=center valign=top>00</td> 11835 <td align=left valign=top>RW</td> 11836 <td align=left valign=top>tx_pmd_dp_invert</td> 11837 <td align=left> 11838 TX PMD Datapath Invert Control. <br> 11839       When Enabled by writing to 1'b1, it will invert all the datapath bits of the logical lane. <br> 11840       Recommended for use in case P and N pads are swapped on the PCB board. <br> 11841 Reset value is 0x0.</td></tr> 11842 </table><p> 11843 <A HREF="#TLB_TX Registers">Return to TLB_TX: per lane register block [One Copy Per Lane] Table</A><p> 11844 <hr> 11845 <b><a NAME="TLB_TX_RMT_LPBK_PD_STATUS">TLB_TX_RMT_LPBK_PD_STATUS - Remote Loopback Status</a></b><br> 11846 Address Offset = 32'h0000_d0e8<br> 11847 Physical Address = 32'h0000_d0e8<br> 11848 Reset Value = 16'h0002<br> 11849 Access = RO (16-bit only)<br> 11850 <table border=1 align=center width=100% cellpadding=0> 11851 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11852 <tr bgcolor=WHITE> 11853 <td bgcolor=WHITE align=center valign=top>15:02</td> 11854 <td align=left valign=top>RSVD</td> 11855 <td align=left valign=top>Reserved</td> 11856 <td align=left> 11857 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11858 <tr bgcolor=WHITE> 11859 <td bgcolor=WHITE align=center valign=top>01</td> 11860 <td align=left valign=top>RO</td> 11861 <td align=left valign=top>rmt_lpbk_pd_early_ind</td> 11862 <td align=left> 11863 1 means dp_tclk20 is sampling data earlier so delay the dp_tclk20 clock phase. This will result in TX PI phase step increment. <br> 11864 Reset value is 0x1.</td></tr> 11865 <tr bgcolor=WHITE> 11866 <td bgcolor=WHITE align=center valign=top>00</td> 11867 <td align=left valign=top>RO</td> 11868 <td align=left valign=top>rmt_lpbk_pd_late_ind</td> 11869 <td align=left> 11870 1 means dp_tclk20 is sampling data late so reduce the delay of the dp_tclk20 clock phase. This will result in TX PI phase step decrement.  <br> 11871 Reset value is 0x0.</td></tr> 11872 </table><p> 11873 <A HREF="#TLB_TX Registers">Return to TLB_TX: per lane register block [One Copy Per Lane] Table</A><p> 11874 <hr> 11875 <H1><a NAME="DIG_COM Registers">DIG_COM: common register block for all lanes Registers</a></H1> 11876 <table border=1 align=center width=100% cellpadding=0> 11877 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 11878 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 11879 <tr> 11880 <td align=center>0xD0F0</td><td><A HREF="#DIG_COM_REVID0">DIG_COM_REVID0</A><br>REVID0</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">revid_rev_letter</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">revid_rev_number</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">revid_bonding</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">revid_process</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">revid_model</div> </td> <td align=center>16'h0363</td></tr> 11881 <tr> 11882 <td align=center>0xD0F1</td><td><A HREF="#DIG_COM_RESET_CONTROL_PMD">DIG_COM_RESET_CONTROL_PMD</A><br>RESET_CONTROL_PMD</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ana_txclk_reset_enable</div> </td> <td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">core_s_rstb</div> </td> <td align=center>16'h0001</td></tr> 11883 <tr> 11884 <td align=center>0xD0F2</td><td><A HREF="#DIG_COM_RESET_CONTROL_CORE_DP">DIG_COM_RESET_CONTROL_CORE_DP</A><br>RESET_CONTROL_CORE_DP</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">disable_ack_timeout</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_vcoclk16_vld_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_vcoclk16_vld_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vcoclk16_s_comclk_frc_on</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vcoclk16_s_comclk_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_mdio_trans_pkill</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sup_rst_seq_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sup_rst_seq_frc_val</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_core_dp_h_rstb_pkill</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td align=center>16'h0000</td></tr> 11885 <tr> 11886 <td align=center>0xD0F3</td><td><A HREF="#DIG_COM_MASKDATA_REG">DIG_COM_MASKDATA_REG</A><br>MASKDATA_REG</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">maskdata</div> </td> <td align=center>16'h0000</td></tr> 11887 <tr> 11888 <td align=center>0xD0F4</td><td><A HREF="#DIG_COM_TOP_USER_CONTROL_0">DIG_COM_TOP_USER_CONTROL_0</A><br>TOP_USER_CONTROL_0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_active</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_s_pll_pwrdn</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">core_dp_s_rstb</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">maskdata_bus_assign</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">heartbeat_count_1us</div> </td> <td align=center>16'h0190</td></tr> 11889 <tr> 11890 <td align=center>0xD0F5</td><td><A HREF="#DIG_COM_UC_ACK_CORE_CONTROL">DIG_COM_UC_ACK_CORE_CONTROL</A><br>UC_ACK_CORE_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_core_dp_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_ack_core_cfg_done</div> </td> <td align=center>16'h0000</td></tr> 11891 <tr> 11892 <td align=center>0xD0F6</td><td><A HREF="#DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL">DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL</A><br>CORE_REG_RESET_OCCURRED_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">core_reg_reset_occurred</div> </td> <td align=center>16'h0001</td></tr> 11893 <tr> 11894 <td align=center>0xD0F7</td><td><A HREF="#DIG_COM_RST_SEQ_TIMER_CONTROL">DIG_COM_RST_SEQ_TIMER_CONTROL</A><br>RST_SEQ_TIMER_CONTROL</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rst_seq_dis_flt_mode</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">pwrdn_seq_timer</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dsc_pwrdn_seq_timer</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dsc_rst_seq_timer</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rst_seq_timer</div> </td> <td align=center>16'h86f0</td></tr> 11895 <tr> 11896 <td align=center>0xD0F8</td><td><A HREF="#DIG_COM_CORE_DP_RESET_STATE_STATUS">DIG_COM_CORE_DP_RESET_STATE_STATUS</A><br>CORE_DP_RESET_STATE_STATUS</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_lane_reset_released</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lane_reset_released</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">lane_reset_released_index</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">tx_lane_reset_released_index</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">core_dp_reset_state</div> </td> <td align=center>16'h0007</td></tr> 11897 <tr> 11898 <td align=center>0xD0F9</td><td><A HREF="#DIG_COM_PMD_CORE_MODE_STATUS">DIG_COM_PMD_CORE_MODE_STATUS</A><br>PMD_CORE_MODE_STATUS</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">pmd_core_mode</div> </td> <td align=center>16'h0000</td></tr> 11899 <tr> 11900 <td align=center>0xD0FE</td><td><A HREF="#DIG_COM_REVID2">DIG_COM_REVID2</A><br>REVID2</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">revid2</div> </td> <td align=center>16'h0000</td></tr> 11901 </table><p> 11902 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 11903 <hr> 11904 <b><a NAME="DIG_COM_REVID0">DIG_COM_REVID0 - REVID0</a></b><br> 11905 Address Offset = 32'h0000_d0f0<br> 11906 Physical Address = 32'h0000_d0f0<br> 11907 Reset Value = 16'h0363<br> 11908 Access = RO (16-bit only)<br> 11909 <table border=1 align=center width=100% cellpadding=0> 11910 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11911 <tr bgcolor=WHITE> 11912 <td bgcolor=WHITE align=center valign=top>15:14</td> 11913 <td align=left valign=top>RO</td> 11914 <td align=left valign=top>revid_rev_letter</td> 11915 <td align=left> 11916 All layer revision letter <br> 11917 0 = revA <br> 11918 1 = revB <br> 11919 2 = revC <br> 11920 3 = revD <br> 11921 Reset value is 0.</td></tr> 11922 <tr bgcolor=WHITE> 11923 <td bgcolor=WHITE align=center valign=top>13:11</td> 11924 <td align=left valign=top>RO</td> 11925 <td align=left valign=top>revid_rev_number</td> 11926 <td align=left> 11927 Metal mask revision number<br> 11928 Reset value is 0.</td></tr> 11929 <tr bgcolor=WHITE> 11930 <td bgcolor=WHITE align=center valign=top>10:09</td> 11931 <td align=left valign=top>RO</td> 11932 <td align=left valign=top>revid_bonding</td> 11933 <td align=left> 11934 bonding <br> 11935 0 = wire bond <br> 11936 1 = flip chip <br> 11937 2-3 = reserved<br> 11938 Reset value is 1.</td></tr> 11939 <tr bgcolor=WHITE> 11940 <td bgcolor=WHITE align=center valign=top>08:06</td> 11941 <td align=left valign=top>RO</td> 11942 <td align=left valign=top>revid_process</td> 11943 <td align=left> 11944 technology process <br> 11945 0 = 90nm <br> 11946 1 = 65nm <br> 11947 2 = 40nm <br> 11948 3 = 28nm <br> 11949 4 = 20nm <br> 11950 5 = 16nm <br> 11951 6-7 = reserved <br> 11952 Reset value is 5.</td></tr> 11953 <tr bgcolor=WHITE> 11954 <td bgcolor=WHITE align=center valign=top>05:00</td> 11955 <td align=left valign=top>RO</td> 11956 <td align=left valign=top>revid_model</td> 11957 <td align=left> 11958 model number<br> 11959 Reset value is 0x23.</td></tr> 11960 </table><p> 11961 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 11962 <hr> 11963 <b><a NAME="DIG_COM_RESET_CONTROL_PMD">DIG_COM_RESET_CONTROL_PMD - RESET_CONTROL_PMD</a></b><br> 11964 Address Offset = 32'h0000_d0f1<br> 11965 Physical Address = 32'h0000_d0f1<br> 11966 Reset Value = 16'h0001<br> 11967 Access = RW (16-bit only)<br> 11968 <table border=1 align=center width=100% cellpadding=0> 11969 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 11970 <tr bgcolor=WHITE> 11971 <td bgcolor=WHITE align=center valign=top>15</td> 11972 <td align=left valign=top>RW</td> 11973 <td align=left valign=top>ana_txclk_reset_enable</td> 11974 <td align=left> 11975 Enable ana_txclk_reset.<br> 11976 Reset value is 0x0.</td></tr> 11977 <tr bgcolor=WHITE> 11978 <td bgcolor=WHITE align=center valign=top>14:01</td> 11979 <td align=left valign=top>RSVD</td> 11980 <td align=left valign=top>Reserved</td> 11981 <td align=left> 11982 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 11983 <tr bgcolor=WHITE> 11984 <td bgcolor=WHITE align=center valign=top>00</td> 11985 <td align=left valign=top>RW</td> 11986 <td align=left valign=top>core_s_rstb</td> 11987 <td align=left> 11988 Active Low Core Level Soft Reset. If asserted by writing to 1'b0 will reset the whole core. <br> 11989 This soft reset is equivalent to the hard reset input pin pmd_por_h_rstb. This regiter bit can only be <br> 11990 reset by assertion of the hard reset input pin pmd_por_h_rstb<br> 11991 Reset value is 0x1.</td></tr> 11992 </table><p> 11993 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 11994 <hr> 11995 <b><a NAME="DIG_COM_RESET_CONTROL_CORE_DP">DIG_COM_RESET_CONTROL_CORE_DP - RESET_CONTROL_CORE_DP</a></b><br> 11996 Address Offset = 32'h0000_d0f2<br> 11997 Physical Address = 32'h0000_d0f2<br> 11998 Reset Value = 16'h0000<br> 11999 Access = RW (16-bit only)<br> 12000 <table border=1 align=center width=100% cellpadding=0> 12001 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12002 <tr bgcolor=WHITE> 12003 <td bgcolor=WHITE align=center valign=top>15</td> 12004 <td align=left valign=top>RW</td> 12005 <td align=left valign=top>disable_ack_timeout</td> 12006 <td align=left> 12007 Setting this bit to 1 disables the ack timeout for all ports. <br> 12008 Reset value is 0x0.</td></tr> 12009 <tr bgcolor=WHITE> 12010 <td bgcolor=WHITE align=center valign=top>14:11</td> 12011 <td align=left valign=top>RSVD</td> 12012 <td align=left valign=top>Reserved</td> 12013 <td align=left> 12014 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12015 <tr bgcolor=WHITE> 12016 <td bgcolor=WHITE align=center valign=top>10</td> 12017 <td align=left valign=top>RW</td> 12018 <td align=left valign=top>pmd_vcoclk16_vld_frc_val</td> 12019 <td align=left> 12020 pmd_vcoclk16_vld pin force value. <br> 12021 Reset value is 0x0.</td></tr> 12022 <tr bgcolor=WHITE> 12023 <td bgcolor=WHITE align=center valign=top>09</td> 12024 <td align=left valign=top>RW</td> 12025 <td align=left valign=top>pmd_vcoclk16_vld_frc</td> 12026 <td align=left> 12027 pmd_vcoclk16_vld pin force. <br> 12028 Reset value is 0x0.</td></tr> 12029 <tr bgcolor=WHITE> 12030 <td bgcolor=WHITE align=center valign=top>08</td> 12031 <td align=left valign=top>RW</td> 12032 <td align=left valign=top>vcoclk16_s_comclk_frc_on</td> 12033 <td align=left> 12034 Mux control for selection of comclk for pmd_vcoclk16 by force. <br> 12035 If asserted by writing to 1'b1 will select the comclk for the pmd_vcoclk16 clock. This is a debug bit and should be used only for recovery from a dead 12036 AFE lane clock. Use of this bit with an active AFE clock can cause clock glitches.<br> 12037 " It is recommended for user to force pmd_vcoclk16_vld to 1'b0 while vcoclk16_s_comclk_frc_on is asserted to 1'b1<br> 12038 by using pmd_vcoclk16_vld_frc/frc_val registers. <br> 12039 Reset value is 0x0.</td></tr> 12040 <tr bgcolor=WHITE> 12041 <td bgcolor=WHITE align=center valign=top>07</td> 12042 <td align=left valign=top>RW</td> 12043 <td align=left valign=top>vcoclk16_s_comclk_sel</td> 12044 <td align=left> 12045 Mux control for selection of comclk for pmd_vcoclk16 clock. <br> 12046 If asserted by writing to 1'b1 will select the comclk for the pmd_vcoclk16 clock. <br> 12047 " It is recommended for user to force pmd_vcoclk16_vld to 1'b0 while vcoclk16_s_comclk_sel is asserted to 1'b1<br> 12048 by using pmd_vcoclk16_vld_frc/frc_val registers. <br> 12049 Reset value is 0x0.</td></tr> 12050 <tr bgcolor=WHITE> 12051 <td bgcolor=WHITE align=center valign=top>06</td> 12052 <td align=left valign=top>RSVD</td> 12053 <td align=left valign=top>Reserved</td> 12054 <td align=left> 12055 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 12056 <tr bgcolor=WHITE> 12057 <td bgcolor=WHITE align=center valign=top>05</td> 12058 <td align=left valign=top>RW</td> 12059 <td align=left valign=top>pmd_mdio_trans_pkill</td> 12060 <td align=left> 12061 1'b1 will disable the pmd_mdio_trans pin. <br> 12062 Reset value is 0x0.</td></tr> 12063 <tr bgcolor=WHITE> 12064 <td bgcolor=WHITE align=center valign=top>04</td> 12065 <td align=left valign=top>RW</td> 12066 <td align=left valign=top>sup_rst_seq_frc</td> 12067 <td align=left> 12068 Suppress reset sequence force. <br> 12069 Reset value is 0x0.</td></tr> 12070 <tr bgcolor=WHITE> 12071 <td bgcolor=WHITE align=center valign=top>03</td> 12072 <td align=left valign=top>RW</td> 12073 <td align=left valign=top>sup_rst_seq_frc_val</td> 12074 <td align=left> 12075 Suppress reset sequence. <br> 12076 Reset value is 0x0.</td></tr> 12077 <tr bgcolor=WHITE> 12078 <td bgcolor=WHITE align=center valign=top>02</td> 12079 <td align=left valign=top>RSVD</td> 12080 <td align=left valign=top>Reserved</td> 12081 <td align=left> 12082 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 12083 <tr bgcolor=WHITE> 12084 <td bgcolor=WHITE align=center valign=top>01</td> 12085 <td align=left valign=top>RW</td> 12086 <td align=left valign=top>pmd_core_dp_h_rstb_pkill</td> 12087 <td align=left> 12088 1'b1 will disable the pmd_core_dp_h_rstb pin. <br> 12089 <br> 12090 Reset value is 0x0.</td></tr> 12091 <tr bgcolor=WHITE> 12092 <td bgcolor=WHITE align=center valign=top>00</td> 12093 <td align=left valign=top>RSVD</td> 12094 <td align=left valign=top>Reserved</td> 12095 <td align=left> 12096 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 12097 </table><p> 12098 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12099 <hr> 12100 <b><a NAME="DIG_COM_MASKDATA_REG">DIG_COM_MASKDATA_REG - MASKDATA_REG</a></b><br> 12101 Address Offset = 32'h0000_d0f3<br> 12102 Physical Address = 32'h0000_d0f3<br> 12103 Reset Value = 16'h0000<br> 12104 Access = RW (16-bit only)<br> 12105 <table border=1 align=center width=100% cellpadding=0> 12106 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12107 <tr bgcolor=WHITE> 12108 <td bgcolor=WHITE align=center valign=top>15:00</td> 12109 <td align=left valign=top>RW</td> 12110 <td align=left valign=top>maskdata</td> 12111 <td align=left> 12112 maskdata for writes that can be used with any PMI port (PMI_HP, PMI_LP or PMI_MDIO). This register will get reset to 0 after each transaction. <br> 12113 Reset value is 0x0.</td></tr> 12114 </table><p> 12115 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12116 <hr> 12117 <b><a NAME="DIG_COM_TOP_USER_CONTROL_0">DIG_COM_TOP_USER_CONTROL_0 - TOP_USER_CONTROL_0</a></b><br> 12118 Address Offset = 32'h0000_d0f4<br> 12119 Physical Address = 32'h0000_d0f4<br> 12120 Reset Value = 16'h0190<br> 12121 Access = RW (16-bit only)<br> 12122 <table border=1 align=center width=100% cellpadding=0> 12123 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12124 <tr bgcolor=WHITE> 12125 <td bgcolor=WHITE align=center valign=top>15</td> 12126 <td align=left valign=top>RW</td> 12127 <td align=left valign=top>uc_active</td> 12128 <td align=left> 12129 When set to 1'b1 then Hardware should wait for uC handshakes to wake up from datapath reset<br> 12130 When set to 1'b0 then Hardware can internally assume that uc_ack_* = 1. <br> 12131 Reset value is 0x0.</td></tr> 12132 <tr bgcolor=WHITE> 12133 <td bgcolor=WHITE align=center valign=top>14</td> 12134 <td align=left valign=top>RW</td> 12135 <td align=left valign=top>afe_s_pll_pwrdn</td> 12136 <td align=left> 12137 Active High PLL Power Down control. <br> 12138 Reset value is 0x0.</td></tr> 12139 <tr bgcolor=WHITE> 12140 <td bgcolor=WHITE align=center valign=top>13</td> 12141 <td align=left valign=top>RW</td> 12142 <td align=left valign=top>core_dp_s_rstb</td> 12143 <td align=left> 12144 Active Low Core Level Datapath Soft Reset. If asserted by writing <br> 12145 to 1'b0 will reset datapath logic of all the lanes. This soft reset <br> 12146 is equivalent to the hard reset input pin core_dp_h_rstb. <br> 12147 Reset value is 0x0.</td></tr> 12148 <tr bgcolor=WHITE> 12149 <td bgcolor=WHITE align=center valign=top>12</td> 12150 <td align=left valign=top>RSVD</td> 12151 <td align=left valign=top>Reserved</td> 12152 <td align=left> 12153 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 12154 <tr bgcolor=WHITE> 12155 <td bgcolor=WHITE align=center valign=top>11:10</td> 12156 <td align=left valign=top>RW</td> 12157 <td align=left valign=top>maskdata_bus_assign</td> 12158 <td align=left> 12159 This 2-bit register is used to assign the maskdata bus to any port . <br> 12160 00: maskdata register is assigned to MDIO port  <br> 12161 01: maskdata register is assigned to PMI_HP port  <br> 12162 10: maskdata register is assigned to PMI_LP port  <br> 12163 11: maskdata register is not assigned to any port  <br> 12164 Reset value is 0x0.</td></tr> 12165 <tr bgcolor=WHITE> 12166 <td bgcolor=WHITE align=center valign=top>09:00</td> 12167 <td align=left valign=top>RW</td> 12168 <td align=left valign=top>heartbeat_count_1us</td> 12169 <td align=left> 12170 Heartbeat timer count in comclk cycles to create 1us heartbeat_1us period. It should be programmed to the nearest increment of 0.25Mhz value of the comclk 12171 frequency in Mhz. <br> 12172 For example, for comclk of 125 Mhz, it should be programmed to 10'd500. For 156.25 Mhz comclk, it should be programmed to 10'd625 and similarly for any 12173 other comclk frequency.  <br> 12174 Reset value is 0x190.</td></tr> 12175 </table><p> 12176 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12177 <hr> 12178 <b><a NAME="DIG_COM_UC_ACK_CORE_CONTROL">DIG_COM_UC_ACK_CORE_CONTROL - UC_ACK_CORE_CONTROL</a></b><br> 12179 Address Offset = 32'h0000_d0f5<br> 12180 Physical Address = 32'h0000_d0f5<br> 12181 Reset Value = 16'h0000<br> 12182 Access = RW (16-bit only)<br> 12183 <table border=1 align=center width=100% cellpadding=0> 12184 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12185 <tr bgcolor=WHITE> 12186 <td bgcolor=WHITE align=center valign=top>15:02</td> 12187 <td align=left valign=top>RSVD</td> 12188 <td align=left valign=top>Reserved</td> 12189 <td align=left> 12190 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12191 <tr bgcolor=WHITE> 12192 <td bgcolor=WHITE align=center valign=top>01</td> 12193 <td align=left valign=top>SC</td> 12194 <td align=left valign=top>uc_ack_core_dp_reset</td> 12195 <td align=left> 12196 uC will write this to 1 to acknowledge a reset event after seeing "core_dp_reset_coccured". <br> 12197 Reset value is 0x0.</td></tr> 12198 <tr bgcolor=WHITE> 12199 <td bgcolor=WHITE align=center valign=top>00</td> 12200 <td align=left valign=top>SC</td> 12201 <td align=left valign=top>uc_ack_core_cfg_done</td> 12202 <td align=left> 12203 uC will write this to 1 to indicate it's configuration of the core is complete. Writing to 1'b1 will  <br> 12204 should release internal hold on core_dp_reset, only if core_dp_reset_state is 3'b001. <br> 12205 Reset value is 0x0.</td></tr> 12206 </table><p> 12207 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12208 <hr> 12209 <b><a NAME="DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL">DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL - CORE_REG_RESET_OCCURRED_CONTROL</a></b><br> 12210 Address Offset = 32'h0000_d0f6<br> 12211 Physical Address = 32'h0000_d0f6<br> 12212 Reset Value = 16'h0001<br> 12213 Access = RW (16-bit only)<br> 12214 <table border=1 align=center width=100% cellpadding=0> 12215 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12216 <tr bgcolor=WHITE> 12217 <td bgcolor=WHITE align=center valign=top>15:01</td> 12218 <td align=left valign=top>RSVD</td> 12219 <td align=left valign=top>Reserved</td> 12220 <td align=left> 12221 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12222 <tr bgcolor=WHITE> 12223 <td bgcolor=WHITE align=center valign=top>00</td> 12224 <td align=left valign=top>RW</td> 12225 <td align=left valign=top>core_reg_reset_occurred</td> 12226 <td align=left> 12227 Set to 1'b1 upon core level register reset and remains so until cleared by register write from uC. <br> 12228 Reset value is 0x1.</td></tr> 12229 </table><p> 12230 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12231 <hr> 12232 <b><a NAME="DIG_COM_RST_SEQ_TIMER_CONTROL">DIG_COM_RST_SEQ_TIMER_CONTROL - RST_SEQ_TIMER_CONTROL</a></b><br> 12233 Address Offset = 32'h0000_d0f7<br> 12234 Physical Address = 32'h0000_d0f7<br> 12235 Reset Value = 16'h86f0<br> 12236 Access = RW (16-bit only)<br> 12237 <table border=1 align=center width=100% cellpadding=0> 12238 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12239 <tr bgcolor=WHITE> 12240 <td bgcolor=WHITE align=center valign=top>15:14</td> 12241 <td align=left valign=top>RW</td> 12242 <td align=left valign=top>rst_seq_dis_flt_mode</td> 12243 <td align=left> 12244 Defines the filter mode for rst_seq_dis/pmd_mdio_trans pin.   <br> 12245   2'd0 - filter is bypassed where input is passed to output untouched. <br> 12246   2'd1 - filter output is 16 comclk cycles if input is > 16 comclk cycles else output is same as input signal.  <br> 12247   2'd2 - filter output is 20 comclk cycles if input is > 20 comclk cycles else output is same as input signal.  <br> 12248   2'd3 - filter output is 24 comclk cycles if input is > 24 comclk cycles else output is same as input signal.  <br> 12249 Reset value is 0x2.</td></tr> 12250 <tr bgcolor=WHITE> 12251 <td bgcolor=WHITE align=center valign=top>13:12</td> 12252 <td align=left valign=top>RSVD</td> 12253 <td align=left valign=top>Reserved</td> 12254 <td align=left> 12255 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12256 <tr bgcolor=WHITE> 12257 <td bgcolor=WHITE align=center valign=top>11:09</td> 12258 <td align=left valign=top>RW</td> 12259 <td align=left valign=top>pwrdn_seq_timer</td> 12260 <td align=left> 12261 Defines the number of comclk cycles between de-assertion of AFE RX/TX lane pwrdn and clock muxing from comclk to lane clock.  <br> 12262 Valid value range is from 0 to 7 which will provide from 8 to 64 clock cycles between de-assertion of AFE RX/TX lane pwrdn <br> 12263 and clock muxing from comclk to lane clock. Wait_time = 8 * (pwrdn_seq_timer + 1). <br> 12264 Reset value is 0x3.</td></tr> 12265 <tr bgcolor=WHITE> 12266 <td bgcolor=WHITE align=center valign=top>08:06</td> 12267 <td align=left valign=top>RW</td> 12268 <td align=left valign=top>dsc_pwrdn_seq_timer</td> 12269 <td align=left> 12270 Defines the number of comclk cycles between de-assertion of AFE RX/TX lane pwrdn and clock muxing from comclk to lane clock.  <br> 12271 Valid value range is from 0 to 7 which will provide from 8 to 64 clock cycles between de-assertion of AFE RX/TX lane pwrdn <br> 12272 and clock muxing from comclk to lane clock. Wait_time = 8 * (pwrdn_seq_timer + 1). <br> 12273 Reset value is 0x3.</td></tr> 12274 <tr bgcolor=WHITE> 12275 <td bgcolor=WHITE align=center valign=top>05:03</td> 12276 <td align=left valign=top>RW</td> 12277 <td align=left valign=top>dsc_rst_seq_timer</td> 12278 <td align=left> 12279 Defines the number of comclk cycles between de-assertion of AFE RX/TX lane reset and clock muxing from comclk to lane clock.  <br> 12280 Valid value range is from 0 to 7 which will provide from 1 to 15 clock cycles between de-assertion of AFE RX/TX lane reset <br> 12281 and clock muxing from comclk to lane clock. Wait_time = 2 * rst_seq_timer + 1. <br> 12282 Reset value is 0x6.</td></tr> 12283 <tr bgcolor=WHITE> 12284 <td bgcolor=WHITE align=center valign=top>02:00</td> 12285 <td align=left valign=top>RW</td> 12286 <td align=left valign=top>rst_seq_timer</td> 12287 <td align=left> 12288 Defines the number of comclk cycles between de-assertion of AFE RX/TX lane reset and clock muxing from comclk to lane clock.  <br> 12289 Valid value range is from 0 to 7 which will provide from 1 to 15 clock cycles between de-assertion of AFE RX/TX lane reset <br> 12290 and clock muxing from comclk to lane clock. Wait_time = 2 * rst_seq_timer + 1. <br> 12291 Reset value is 0x0.</td></tr> 12292 </table><p> 12293 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12294 <hr> 12295 <b><a NAME="DIG_COM_CORE_DP_RESET_STATE_STATUS">DIG_COM_CORE_DP_RESET_STATE_STATUS - CORE_DP_RESET_STATE_STATUS</a></b><br> 12296 Address Offset = 32'h0000_d0f8<br> 12297 Physical Address = 32'h0000_d0f8<br> 12298 Reset Value = 16'h0007<br> 12299 Access = RO (16-bit only)<br> 12300 <table border=1 align=center width=100% cellpadding=0> 12301 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12302 <tr bgcolor=WHITE> 12303 <td bgcolor=WHITE align=center valign=top>15</td> 12304 <td align=left valign=top>RO</td> 12305 <td align=left valign=top>tx_lane_reset_released</td> 12306 <td align=left> 12307 indicates if a lane is currently at {tx_lane_dp_reset_active, tx_lane_dp_reset_occurred} = 01. <br> 12308 Reset value is 0x0.</td></tr> 12309 <tr bgcolor=WHITE> 12310 <td bgcolor=WHITE align=center valign=top>14</td> 12311 <td align=left valign=top>RO</td> 12312 <td align=left valign=top>lane_reset_released</td> 12313 <td align=left> 12314 indicates if a lane is currently at {rx_lane_dp_reset_active, rx_lane_dp_reset_occurred} = 01. <br> 12315 Reset value is 0x0.</td></tr> 12316 <tr bgcolor=WHITE> 12317 <td bgcolor=WHITE align=center valign=top>13</td> 12318 <td align=left valign=top>RSVD</td> 12319 <td align=left valign=top>Reserved</td> 12320 <td align=left> 12321 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 12322 <tr bgcolor=WHITE> 12323 <td bgcolor=WHITE align=center valign=top>12:08</td> 12324 <td align=left valign=top>RO</td> 12325 <td align=left valign=top>lane_reset_released_index</td> 12326 <td align=left> 12327 Index of the lane number of the first RX lane in lane_reset_released state. <br> 12328 Reset value is 0x0.</td></tr> 12329 <tr bgcolor=WHITE> 12330 <td bgcolor=WHITE align=center valign=top>07:03</td> 12331 <td align=left valign=top>RO</td> 12332 <td align=left valign=top>tx_lane_reset_released_index</td> 12333 <td align=left> 12334 Index of the lane number of the first TX lane in lane_reset_released state. <br> 12335 Reset value is 0x0.</td></tr> 12336 <tr bgcolor=WHITE> 12337 <td bgcolor=WHITE align=center valign=top>02:00</td> 12338 <td align=left valign=top>RO</td> 12339 <td align=left valign=top>core_dp_reset_state</td> 12340 <td align=left> 12341 Bit 2: core_dp_reset_active   : Set to 1'b1 whenenver core_dp_reset is currently requested through any register or pin controls.  <br> 12342 Bit 1: core_dp_reset_occurred : Set to 1'b1 whenenver core_dp_reset is currently requested through any register or pin controls and is latched high.  12343 <br> 12344 Bit 0: core_dp_reset_held     : Set to 1'b1 whenenver core_dp_reset is internally held. Cleared to 1'b0, only if core_dp_reset_state==001 12345 and uc_ack_core_cfg_done == 1. <br> 12346 Reset value is 0x7.</td></tr> 12347 </table><p> 12348 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12349 <hr> 12350 <b><a NAME="DIG_COM_PMD_CORE_MODE_STATUS">DIG_COM_PMD_CORE_MODE_STATUS - PMD_CORE_MODE_STATUS</a></b><br> 12351 Address Offset = 32'h0000_d0f9<br> 12352 Physical Address = 32'h0000_d0f9<br> 12353 Reset Value = 16'h0000<br> 12354 Access = RO (16-bit only)<br> 12355 <table border=1 align=center width=100% cellpadding=0> 12356 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12357 <tr bgcolor=WHITE> 12358 <td bgcolor=WHITE align=center valign=top>15:00</td> 12359 <td align=left valign=top>RO</td> 12360 <td align=left valign=top>pmd_core_mode</td> 12361 <td align=left> 12362 This indicates the status of the core input pin pmd_core_mode.  <br> 12363 This is driven from PCS and used for communication between PCS and PMD Micro code. <br> 12364 Reset value is 0x0.</td></tr> 12365 </table><p> 12366 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12367 <hr> 12368 <b><a NAME="DIG_COM_REVID2">DIG_COM_REVID2 - REVID2</a></b><br> 12369 Address Offset = 32'h0000_d0fe<br> 12370 Physical Address = 32'h0000_d0fe<br> 12371 Reset Value = 16'h0000<br> 12372 Access = RO (16-bit only)<br> 12373 <table border=1 align=center width=100% cellpadding=0> 12374 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12375 <tr bgcolor=WHITE> 12376 <td bgcolor=WHITE align=center valign=top>15:04</td> 12377 <td align=left valign=top>RSVD</td> 12378 <td align=left valign=top>Reserved</td> 12379 <td align=left> 12380 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12381 <tr bgcolor=WHITE> 12382 <td bgcolor=WHITE align=center valign=top>03:00</td> 12383 <td align=left valign=top>RO</td> 12384 <td align=left valign=top>revid2</td> 12385 <td align=left> 12386 Revision ID2 code<br> 12387 Reset value is 0x0.</td></tr> 12388 </table><p> 12389 <A HREF="#DIG_COM Registers">Return to DIG_COM: common register block for all lanes Table</A><p> 12390 <hr> 12391 <H1><a NAME="PATT_GEN_COM Registers">PATT_GEN_COM: common register block for all lanes Registers</a></H1> 12392 <table border=1 align=center width=100% cellpadding=0> 12393 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 12394 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 12395 <tr> 12396 <td align=center>0xD100</td><td><A HREF="#PATT_GEN_COM_SEQ_0">PATT_GEN_COM_SEQ_0</A><br>Pattern Generator Sequence Word 0</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_0</div> </td> <td align=center>16'hff00</td></tr> 12397 <tr> 12398 <td align=center>0xD101</td><td><A HREF="#PATT_GEN_COM_SEQ_1">PATT_GEN_COM_SEQ_1</A><br>Pattern Generator Sequence Word 1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_1</div> </td> <td align=center>16'hff00</td></tr> 12399 <tr> 12400 <td align=center>0xD102</td><td><A HREF="#PATT_GEN_COM_SEQ_2">PATT_GEN_COM_SEQ_2</A><br>Pattern Generator Sequence Word 2</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_2</div> </td> <td align=center>16'hff00</td></tr> 12401 <tr> 12402 <td align=center>0xD103</td><td><A HREF="#PATT_GEN_COM_SEQ_3">PATT_GEN_COM_SEQ_3</A><br>Pattern Generator Sequence Word 3</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_3</div> </td> <td align=center>16'hff00</td></tr> 12403 <tr> 12404 <td align=center>0xD104</td><td><A HREF="#PATT_GEN_COM_SEQ_4">PATT_GEN_COM_SEQ_4</A><br>Pattern Generator Sequence Word 4</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_4</div> </td> <td align=center>16'hff00</td></tr> 12405 <tr> 12406 <td align=center>0xD105</td><td><A HREF="#PATT_GEN_COM_SEQ_5">PATT_GEN_COM_SEQ_5</A><br>Pattern Generator Sequence Word 5</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_5</div> </td> <td align=center>16'hff00</td></tr> 12407 <tr> 12408 <td align=center>0xD106</td><td><A HREF="#PATT_GEN_COM_SEQ_6">PATT_GEN_COM_SEQ_6</A><br>Pattern Generator Sequence Word 6</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_6</div> </td> <td align=center>16'hff00</td></tr> 12409 <tr> 12410 <td align=center>0xD107</td><td><A HREF="#PATT_GEN_COM_SEQ_7">PATT_GEN_COM_SEQ_7</A><br>Pattern Generator Sequence Word 7</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_7</div> </td> <td align=center>16'hff00</td></tr> 12411 <tr> 12412 <td align=center>0xD108</td><td><A HREF="#PATT_GEN_COM_SEQ_8">PATT_GEN_COM_SEQ_8</A><br>Pattern Generator Sequence Word 8</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_8</div> </td> <td align=center>16'hff00</td></tr> 12413 <tr> 12414 <td align=center>0xD109</td><td><A HREF="#PATT_GEN_COM_SEQ_9">PATT_GEN_COM_SEQ_9</A><br>Pattern Generator Sequence Word 9</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_9</div> </td> <td align=center>16'hff00</td></tr> 12415 <tr> 12416 <td align=center>0xD10A</td><td><A HREF="#PATT_GEN_COM_SEQ_10">PATT_GEN_COM_SEQ_10</A><br>Pattern Generator Sequence Word 10</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_10</div> </td> <td align=center>16'hff00</td></tr> 12417 <tr> 12418 <td align=center>0xD10B</td><td><A HREF="#PATT_GEN_COM_SEQ_11">PATT_GEN_COM_SEQ_11</A><br>Pattern Generator Sequence Word 11</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_11</div> </td> <td align=center>16'hff00</td></tr> 12419 <tr> 12420 <td align=center>0xD10C</td><td><A HREF="#PATT_GEN_COM_SEQ_12">PATT_GEN_COM_SEQ_12</A><br>Pattern Generator Sequence Word 12</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_12</div> </td> <td align=center>16'hff00</td></tr> 12421 <tr> 12422 <td align=center>0xD10D</td><td><A HREF="#PATT_GEN_COM_SEQ_13">PATT_GEN_COM_SEQ_13</A><br>Pattern Generator Sequence Word 13</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_13</div> </td> <td align=center>16'hff00</td></tr> 12423 <tr> 12424 <td align=center>0xD10E</td><td><A HREF="#PATT_GEN_COM_SEQ_14">PATT_GEN_COM_SEQ_14</A><br>Pattern Generator Sequence Word 14</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">patt_gen_seq_14</div> </td> <td align=center>16'hff00</td></tr> 12425 </table><p> 12426 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 12427 <hr> 12428 <b><a NAME="PATT_GEN_COM_SEQ_0">PATT_GEN_COM_SEQ_0 - Pattern Generator Sequence Word 0</a></b><br> 12429 Address Offset = 32'h0000_d100<br> 12430 Physical Address = 32'h0000_d100<br> 12431 Reset Value = 16'hff00<br> 12432 Access = RW (16-bit only)<br> 12433 <table border=1 align=center width=100% cellpadding=0> 12434 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12435 <tr bgcolor=WHITE> 12436 <td bgcolor=WHITE align=center valign=top>15:00</td> 12437 <td align=left valign=top>RW</td> 12438 <td align=left valign=top>patt_gen_seq_0</td> 12439 <td align=left> 12440 Fixed Pattern Generator Sequence Word 0. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. This word will be transmitted 12441 last. <br> 12442 Reset value is 0xff00.</td></tr> 12443 </table><p> 12444 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12445 <hr> 12446 <b><a NAME="PATT_GEN_COM_SEQ_1">PATT_GEN_COM_SEQ_1 - Pattern Generator Sequence Word 1</a></b><br> 12447 Address Offset = 32'h0000_d101<br> 12448 Physical Address = 32'h0000_d101<br> 12449 Reset Value = 16'hff00<br> 12450 Access = RW (16-bit only)<br> 12451 <table border=1 align=center width=100% cellpadding=0> 12452 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12453 <tr bgcolor=WHITE> 12454 <td bgcolor=WHITE align=center valign=top>15:00</td> 12455 <td align=left valign=top>RW</td> 12456 <td align=left valign=top>patt_gen_seq_1</td> 12457 <td align=left> 12458 Fixed Pattern Generator Sequence Word 1. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12459 Reset value is 0xff00.</td></tr> 12460 </table><p> 12461 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12462 <hr> 12463 <b><a NAME="PATT_GEN_COM_SEQ_2">PATT_GEN_COM_SEQ_2 - Pattern Generator Sequence Word 2</a></b><br> 12464 Address Offset = 32'h0000_d102<br> 12465 Physical Address = 32'h0000_d102<br> 12466 Reset Value = 16'hff00<br> 12467 Access = RW (16-bit only)<br> 12468 <table border=1 align=center width=100% cellpadding=0> 12469 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12470 <tr bgcolor=WHITE> 12471 <td bgcolor=WHITE align=center valign=top>15:00</td> 12472 <td align=left valign=top>RW</td> 12473 <td align=left valign=top>patt_gen_seq_2</td> 12474 <td align=left> 12475 Fixed Pattern Generator Sequence Word 2. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12476 Reset value is 0xff00.</td></tr> 12477 </table><p> 12478 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12479 <hr> 12480 <b><a NAME="PATT_GEN_COM_SEQ_3">PATT_GEN_COM_SEQ_3 - Pattern Generator Sequence Word 3</a></b><br> 12481 Address Offset = 32'h0000_d103<br> 12482 Physical Address = 32'h0000_d103<br> 12483 Reset Value = 16'hff00<br> 12484 Access = RW (16-bit only)<br> 12485 <table border=1 align=center width=100% cellpadding=0> 12486 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12487 <tr bgcolor=WHITE> 12488 <td bgcolor=WHITE align=center valign=top>15:00</td> 12489 <td align=left valign=top>RW</td> 12490 <td align=left valign=top>patt_gen_seq_3</td> 12491 <td align=left> 12492 Fixed Pattern Generator Sequence Word 3. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12493 Reset value is 0xff00.</td></tr> 12494 </table><p> 12495 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12496 <hr> 12497 <b><a NAME="PATT_GEN_COM_SEQ_4">PATT_GEN_COM_SEQ_4 - Pattern Generator Sequence Word 4</a></b><br> 12498 Address Offset = 32'h0000_d104<br> 12499 Physical Address = 32'h0000_d104<br> 12500 Reset Value = 16'hff00<br> 12501 Access = RW (16-bit only)<br> 12502 <table border=1 align=center width=100% cellpadding=0> 12503 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12504 <tr bgcolor=WHITE> 12505 <td bgcolor=WHITE align=center valign=top>15:00</td> 12506 <td align=left valign=top>RW</td> 12507 <td align=left valign=top>patt_gen_seq_4</td> 12508 <td align=left> 12509 Fixed Pattern Generator Sequence Word 4. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12510 Reset value is 0xff00.</td></tr> 12511 </table><p> 12512 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12513 <hr> 12514 <b><a NAME="PATT_GEN_COM_SEQ_5">PATT_GEN_COM_SEQ_5 - Pattern Generator Sequence Word 5</a></b><br> 12515 Address Offset = 32'h0000_d105<br> 12516 Physical Address = 32'h0000_d105<br> 12517 Reset Value = 16'hff00<br> 12518 Access = RW (16-bit only)<br> 12519 <table border=1 align=center width=100% cellpadding=0> 12520 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12521 <tr bgcolor=WHITE> 12522 <td bgcolor=WHITE align=center valign=top>15:00</td> 12523 <td align=left valign=top>RW</td> 12524 <td align=left valign=top>patt_gen_seq_5</td> 12525 <td align=left> 12526 Fixed Pattern Generator Sequence Word 5. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12527 Reset value is 0xff00.</td></tr> 12528 </table><p> 12529 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12530 <hr> 12531 <b><a NAME="PATT_GEN_COM_SEQ_6">PATT_GEN_COM_SEQ_6 - Pattern Generator Sequence Word 6</a></b><br> 12532 Address Offset = 32'h0000_d106<br> 12533 Physical Address = 32'h0000_d106<br> 12534 Reset Value = 16'hff00<br> 12535 Access = RW (16-bit only)<br> 12536 <table border=1 align=center width=100% cellpadding=0> 12537 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12538 <tr bgcolor=WHITE> 12539 <td bgcolor=WHITE align=center valign=top>15:00</td> 12540 <td align=left valign=top>RW</td> 12541 <td align=left valign=top>patt_gen_seq_6</td> 12542 <td align=left> 12543 Fixed Pattern Generator Sequence Word 6. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12544 Reset value is 0xff00.</td></tr> 12545 </table><p> 12546 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12547 <hr> 12548 <b><a NAME="PATT_GEN_COM_SEQ_7">PATT_GEN_COM_SEQ_7 - Pattern Generator Sequence Word 7</a></b><br> 12549 Address Offset = 32'h0000_d107<br> 12550 Physical Address = 32'h0000_d107<br> 12551 Reset Value = 16'hff00<br> 12552 Access = RW (16-bit only)<br> 12553 <table border=1 align=center width=100% cellpadding=0> 12554 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12555 <tr bgcolor=WHITE> 12556 <td bgcolor=WHITE align=center valign=top>15:00</td> 12557 <td align=left valign=top>RW</td> 12558 <td align=left valign=top>patt_gen_seq_7</td> 12559 <td align=left> 12560 Fixed Pattern Generator Sequence Word 7. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12561 Reset value is 0xff00.</td></tr> 12562 </table><p> 12563 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12564 <hr> 12565 <b><a NAME="PATT_GEN_COM_SEQ_8">PATT_GEN_COM_SEQ_8 - Pattern Generator Sequence Word 8</a></b><br> 12566 Address Offset = 32'h0000_d108<br> 12567 Physical Address = 32'h0000_d108<br> 12568 Reset Value = 16'hff00<br> 12569 Access = RW (16-bit only)<br> 12570 <table border=1 align=center width=100% cellpadding=0> 12571 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12572 <tr bgcolor=WHITE> 12573 <td bgcolor=WHITE align=center valign=top>15:00</td> 12574 <td align=left valign=top>RW</td> 12575 <td align=left valign=top>patt_gen_seq_8</td> 12576 <td align=left> 12577 Fixed Pattern Generator Sequence Word 8. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12578 Reset value is 0xff00.</td></tr> 12579 </table><p> 12580 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12581 <hr> 12582 <b><a NAME="PATT_GEN_COM_SEQ_9">PATT_GEN_COM_SEQ_9 - Pattern Generator Sequence Word 9</a></b><br> 12583 Address Offset = 32'h0000_d109<br> 12584 Physical Address = 32'h0000_d109<br> 12585 Reset Value = 16'hff00<br> 12586 Access = RW (16-bit only)<br> 12587 <table border=1 align=center width=100% cellpadding=0> 12588 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12589 <tr bgcolor=WHITE> 12590 <td bgcolor=WHITE align=center valign=top>15:00</td> 12591 <td align=left valign=top>RW</td> 12592 <td align=left valign=top>patt_gen_seq_9</td> 12593 <td align=left> 12594 Fixed Pattern Generator Sequence Word 9. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12595 Reset value is 0xff00.</td></tr> 12596 </table><p> 12597 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12598 <hr> 12599 <b><a NAME="PATT_GEN_COM_SEQ_10">PATT_GEN_COM_SEQ_10 - Pattern Generator Sequence Word 10</a></b><br> 12600 Address Offset = 32'h0000_d10a<br> 12601 Physical Address = 32'h0000_d10a<br> 12602 Reset Value = 16'hff00<br> 12603 Access = RW (16-bit only)<br> 12604 <table border=1 align=center width=100% cellpadding=0> 12605 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12606 <tr bgcolor=WHITE> 12607 <td bgcolor=WHITE align=center valign=top>15:00</td> 12608 <td align=left valign=top>RW</td> 12609 <td align=left valign=top>patt_gen_seq_10</td> 12610 <td align=left> 12611 Fixed Pattern Generator Sequence Word 10. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12612 Reset value is 0xff00.</td></tr> 12613 </table><p> 12614 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12615 <hr> 12616 <b><a NAME="PATT_GEN_COM_SEQ_11">PATT_GEN_COM_SEQ_11 - Pattern Generator Sequence Word 11</a></b><br> 12617 Address Offset = 32'h0000_d10b<br> 12618 Physical Address = 32'h0000_d10b<br> 12619 Reset Value = 16'hff00<br> 12620 Access = RW (16-bit only)<br> 12621 <table border=1 align=center width=100% cellpadding=0> 12622 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12623 <tr bgcolor=WHITE> 12624 <td bgcolor=WHITE align=center valign=top>15:00</td> 12625 <td align=left valign=top>RW</td> 12626 <td align=left valign=top>patt_gen_seq_11</td> 12627 <td align=left> 12628 Fixed Pattern Generator Sequence Word 11. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12629 Reset value is 0xff00.</td></tr> 12630 </table><p> 12631 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12632 <hr> 12633 <b><a NAME="PATT_GEN_COM_SEQ_12">PATT_GEN_COM_SEQ_12 - Pattern Generator Sequence Word 12</a></b><br> 12634 Address Offset = 32'h0000_d10c<br> 12635 Physical Address = 32'h0000_d10c<br> 12636 Reset Value = 16'hff00<br> 12637 Access = RW (16-bit only)<br> 12638 <table border=1 align=center width=100% cellpadding=0> 12639 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12640 <tr bgcolor=WHITE> 12641 <td bgcolor=WHITE align=center valign=top>15:00</td> 12642 <td align=left valign=top>RW</td> 12643 <td align=left valign=top>patt_gen_seq_12</td> 12644 <td align=left> 12645 Fixed Pattern Generator Sequence Word 12. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12646 Reset value is 0xff00.</td></tr> 12647 </table><p> 12648 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12649 <hr> 12650 <b><a NAME="PATT_GEN_COM_SEQ_13">PATT_GEN_COM_SEQ_13 - Pattern Generator Sequence Word 13</a></b><br> 12651 Address Offset = 32'h0000_d10d<br> 12652 Physical Address = 32'h0000_d10d<br> 12653 Reset Value = 16'hff00<br> 12654 Access = RW (16-bit only)<br> 12655 <table border=1 align=center width=100% cellpadding=0> 12656 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12657 <tr bgcolor=WHITE> 12658 <td bgcolor=WHITE align=center valign=top>15:00</td> 12659 <td align=left valign=top>RW</td> 12660 <td align=left valign=top>patt_gen_seq_13</td> 12661 <td align=left> 12662 Fixed Pattern Generator Sequence Word 13. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. <br> 12663 Reset value is 0xff00.</td></tr> 12664 </table><p> 12665 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12666 <hr> 12667 <b><a NAME="PATT_GEN_COM_SEQ_14">PATT_GEN_COM_SEQ_14 - Pattern Generator Sequence Word 14</a></b><br> 12668 Address Offset = 32'h0000_d10e<br> 12669 Physical Address = 32'h0000_d10e<br> 12670 Reset Value = 16'hff00<br> 12671 Access = RW (16-bit only)<br> 12672 <table border=1 align=center width=100% cellpadding=0> 12673 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12674 <tr bgcolor=WHITE> 12675 <td bgcolor=WHITE align=center valign=top>15:00</td> 12676 <td align=left valign=top>RW</td> 12677 <td align=left valign=top>patt_gen_seq_14</td> 12678 <td align=left> 12679 Fixed Pattern Generator Sequence Word 14. MSB bits will be transmitted first on serial transmit lane in both shared and slice mode. This word will be transmitted 12680 first. <br> 12681 Reset value is 0xff00.</td></tr> 12682 </table><p> 12683 <A HREF="#PATT_GEN_COM Registers">Return to PATT_GEN_COM: common register block for all lanes Table</A><p> 12684 <hr> 12685 <H1><a NAME="TX_FED Registers">TX_FED: per lane register block [One Copy Per Lane] Registers</a></H1> 12686 <table border=1 align=center width=100% cellpadding=0> 12687 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 12688 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 12689 <tr> 12690 <td align=center>0xD110</td><td><A HREF="#TX_FED_TXFIR_TAP_CONTROL0">TX_FED_TXFIR_TAP_CONTROL0</A><br>TX FIR TAP Control0 Register</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">txfir_post2</div> </td> <td align=center>16'h0000</td></tr> 12691 <tr> 12692 <td align=center>0xD111</td><td><A HREF="#TX_FED_MISC_CONTROL0">TX_FED_MISC_CONTROL0</A><br>Misc Control0 Register</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">convert_taps_to_afe_error</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">convert_taps_to_afe_int_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">convert_taps_to_afe</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">tx_disable_output_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sdk_tx_disable</div> </td> <td align=center>16'h0020</td></tr> 12693 <tr> 12694 <td align=center>0xD112</td><td><A HREF="#TX_FED_MISC_STATUS0">TX_FED_MISC_STATUS0</A><br>Misc Status 0 Register</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_elec_idle_status</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_disable_status</div> </td> <td align=center>16'h0003</td></tr> 12695 <tr> 12696 <td align=center>0xD113</td><td><A HREF="#TX_FED_MICRO_CONTROL0">TX_FED_MICRO_CONTROL0</A><br>Micro Control0 Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_eee_alert_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_eee_quiet_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tx_disable_timer_ctrl</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_tx_disable_pkill</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dp_reset_tx_disable_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_disable_trigger</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_tx_disable</div> </td> <td align=center>16'hc160</td></tr> 12697 <tr> 12698 <td align=center>0xD11B</td><td><A HREF="#TX_FED_POST2_AFE_CONTROL0">TX_FED_POST2_AFE_CONTROL0</A><br>post2 slice select control register</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post2_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post2_post2_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post2_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post2_post2_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post2_1x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post2_post2_1x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post2_1x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post2_post2_1x_0</div> </td> <td align=center>16'h00a0</td></tr> 12699 <tr> 12700 <td align=center>0xD11C</td><td><A HREF="#TX_FED_POST1_AFE_CONTROL0">TX_FED_POST1_AFE_CONTROL0</A><br>post1 slice select control register</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1pre_1x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1pre_1x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_pre_post1pre_1x_0</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1_2x_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1_2x_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1_1x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1_1x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1_1x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1_1x_0</div> </td> <td align=center>16'h02a0</td></tr> 12701 <tr> 12702 <td align=center>0xD11D</td><td><A HREF="#TX_FED_POST1PRE_AFE_CONTROL0">TX_FED_POST1PRE_AFE_CONTROL0</A><br>post1pre slice select control register</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1pre_2x_3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1pre_2x_3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_pre_post1pre_2x_3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1pre_2x_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1pre_2x_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_pre_post1pre_2x_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1pre_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1pre_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_pre_post1pre_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1pre_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1pre_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_pre_post1pre_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_post1pre_1x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_post1_post1pre_1x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_pre_post1pre_1x_1</div> </td> <td align=center>16'h4000</td></tr> 12703 <tr> 12704 <td align=center>0xD11E</td><td><A HREF="#TX_FED_DC_LEVEL_AFE_CONTROL0">TX_FED_DC_LEVEL_AFE_CONTROL0</A><br>dc_level slice select control register</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_2x_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_2x_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_1x</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">txfir_dc_level_0p5x</div> </td> <td align=center>16'h000f</td></tr> 12705 </table><p> 12706 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 12707 <hr> 12708 <b><a NAME="TX_FED_TXFIR_TAP_CONTROL0">TX_FED_TXFIR_TAP_CONTROL0 - TX FIR TAP Control0 Register</a></b><br> 12709 Address Offset = 32'h0000_d110<br> 12710 Physical Address = 32'h0000_d110<br> 12711 Reset Value = 16'h0000<br> 12712 Access = RW (16-bit only)<br> 12713 <table border=1 align=center width=100% cellpadding=0> 12714 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12715 <tr bgcolor=WHITE> 12716 <td bgcolor=WHITE align=center valign=top>15:04</td> 12717 <td align=left valign=top>RSVD</td> 12718 <td align=left valign=top>Reserved</td> 12719 <td align=left> 12720 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12721 <tr bgcolor=WHITE> 12722 <td bgcolor=WHITE align=center valign=top>03:00</td> 12723 <td align=left valign=top>RW</td> 12724 <td align=left valign=top>txfir_post2</td> 12725 <td align=left> 12726 tx fir post2 tap override value (binary) <br> 12727 Reset value is 0x0.</td></tr> 12728 </table><p> 12729 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 12730 <hr> 12731 <b><a NAME="TX_FED_MISC_CONTROL0">TX_FED_MISC_CONTROL0 - Misc Control0 Register</a></b><br> 12732 Address Offset = 32'h0000_d111<br> 12733 Physical Address = 32'h0000_d111<br> 12734 Reset Value = 16'h0020<br> 12735 Access = RW (16-bit only)<br> 12736 <table border=1 align=center width=100% cellpadding=0> 12737 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12738 <tr bgcolor=WHITE> 12739 <td bgcolor=WHITE align=center valign=top>15:07</td> 12740 <td align=left valign=top>RSVD</td> 12741 <td align=left valign=top>Reserved</td> 12742 <td align=left> 12743 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12744 <tr bgcolor=WHITE> 12745 <td bgcolor=WHITE align=center valign=top>06</td> 12746 <td align=left valign=top>RW</td> 12747 <td align=left valign=top>convert_taps_to_afe_error</td> 12748 <td align=left> 12749 Conversion Error<br> 12750 Micro sets this field to 1'b1 to indicates that the conversion is not  <br> 12751 performed because the binary taps values do not meet the constraints <br> 12752 It is the responsibility of the API code to ensure taps meet the   <br> 12753 constraints <br> 12754 Reset value is 0.</td></tr> 12755 <tr bgcolor=WHITE> 12756 <td bgcolor=WHITE align=center valign=top>05</td> 12757 <td align=left valign=top>RW</td> 12758 <td align=left valign=top>convert_taps_to_afe_int_en</td> 12759 <td align=left> 12760 Conversion Interrupt Enable <br> 12761 When this field is set to 1'b1, then settin the  <br> 12762 convert_txfir_taps_to_afe field  to 1'b1 generates an<br> 12763 interrupt to the micro <br> 12764 1 - enabled,  0 - disabled <br> 12765 Reset value is 1.</td></tr> 12766 <tr bgcolor=WHITE> 12767 <td bgcolor=WHITE align=center valign=top>04</td> 12768 <td align=left valign=top>RW</td> 12769 <td align=left valign=top>convert_taps_to_afe</td> 12770 <td align=left> 12771 Convert txfir binary tap values to afe interface signals <br> 12772 API codes writes a value of 1'b1 to start the conversion <br> 12773 Micro writes a value of 1'b0 to indicate that the conversion is done <br> 12774 It is the responsibilty of the API code to set the correct <br> 12775 pre/main/post1 (in cl72 register block) and post2 values before  <br> 12776 setting this field  <br> 12777 Reset value is 0.</td></tr> 12778 <tr bgcolor=WHITE> 12779 <td bgcolor=WHITE align=center valign=top>03:02</td> 12780 <td align=left valign=top>RW</td> 12781 <td align=left valign=top>tx_disable_output_sel</td> 12782 <td align=left> 12783 These bits select tx disable output function <br> 12784 2'b00 - send electrical idles <br> 12785 2'b01 - send power down <br> 12786 2'b10 - send ones <br> 12787 2'b11 - send zeroes <br> 12788 Reset value is 0.</td></tr> 12789 <tr bgcolor=WHITE> 12790 <td bgcolor=WHITE align=center valign=top>01</td> 12791 <td align=left valign=top>RSVD</td> 12792 <td align=left valign=top>Reserved</td> 12793 <td align=left> 12794 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 12795 <tr bgcolor=WHITE> 12796 <td bgcolor=WHITE align=center valign=top>00</td> 12797 <td align=left valign=top>RW</td> 12798 <td align=left valign=top>sdk_tx_disable</td> 12799 <td align=left> 12800 sdk tx disable <br> 12801 This tx disable control field is for SDK use during TX programming <br> 12802 Please see Eagle & Merlin PMD Internal Functional Specification for details <br> 12803 Reset value is 0.</td></tr> 12804 </table><p> 12805 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 12806 <hr> 12807 <b><a NAME="TX_FED_MISC_STATUS0">TX_FED_MISC_STATUS0 - Misc Status 0 Register</a></b><br> 12808 Address Offset = 32'h0000_d112<br> 12809 Physical Address = 32'h0000_d112<br> 12810 Reset Value = 16'h0003<br> 12811 Access = RO (16-bit only)<br> 12812 <table border=1 align=center width=100% cellpadding=0> 12813 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12814 <tr bgcolor=WHITE> 12815 <td bgcolor=WHITE align=center valign=top>15:02</td> 12816 <td align=left valign=top>RSVD</td> 12817 <td align=left valign=top>Reserved</td> 12818 <td align=left> 12819 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12820 <tr bgcolor=WHITE> 12821 <td bgcolor=WHITE align=center valign=top>01</td> 12822 <td align=left valign=top>RO</td> 12823 <td align=left valign=top>tx_elec_idle_status</td> 12824 <td align=left> 12825 tx electrical idle status <br> 12826 When this bit is set it indicates the tx elecrticl idle active due to:<br> 12827 1) tx disable being programmed to send electrical idles or <br> 12828 2) An internal logic signal derived from PMD interface pins for EEE TX MODE <br> 12829 Reset value is 1.</td></tr> 12830 <tr bgcolor=WHITE> 12831 <td bgcolor=WHITE align=center valign=top>00</td> 12832 <td align=left valign=top>RO</td> 12833 <td align=left valign=top>tx_disable_status</td> 12834 <td align=left> 12835 tx disable status <br> 12836 When this bit is set it indicates the tx_disable is active due to:<br> 12837 1) pin at AN/PCS to PMD Interface OR <br> 12838 2) dp_reset being asserted <br> 12839 3) register bit dedicated to micro use <br> 12840 4) register bit dedicated to SDK use <br> 12841 5) tx disable timer that guarntees minimum assertion time has not expired <br> 12842 Reset value is 1.</td></tr> 12843 </table><p> 12844 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 12845 <hr> 12846 <b><a NAME="TX_FED_MICRO_CONTROL0">TX_FED_MICRO_CONTROL0 - Micro Control0 Register</a></b><br> 12847 Address Offset = 32'h0000_d113<br> 12848 Physical Address = 32'h0000_d113<br> 12849 Reset Value = 16'hc160<br> 12850 Access = RW (16-bit only)<br> 12851 <table border=1 align=center width=100% cellpadding=0> 12852 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12853 <tr bgcolor=WHITE> 12854 <td bgcolor=WHITE align=center valign=top>15</td> 12855 <td align=left valign=top>RW</td> 12856 <td align=left valign=top>tx_eee_alert_en</td> 12857 <td align=left> 12858 Tx eee alert mode control <br> 12859 1 - Enable eee alert mode when pmd_tx_mode (input pins) == 2'b10 <br> 12860 0 - Disable eee alert mode <br> 12861 Reset value is 1.</td></tr> 12862 <tr bgcolor=WHITE> 12863 <td bgcolor=WHITE align=center valign=top>14</td> 12864 <td align=left valign=top>RW</td> 12865 <td align=left valign=top>tx_eee_quiet_en</td> 12866 <td align=left> 12867 Tx eee quiet mode control <br> 12868 1 - Enable eee quiet mode when pmd_tx_mode (input pins) == 2'b01 <br> 12869 0 - Disable eee quiet mode <br> 12870 Reset value is 1.</td></tr> 12871 <tr bgcolor=WHITE> 12872 <td bgcolor=WHITE align=center valign=top>13:10</td> 12873 <td align=left valign=top>RSVD</td> 12874 <td align=left valign=top>Reserved</td> 12875 <td align=left> 12876 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12877 <tr bgcolor=WHITE> 12878 <td bgcolor=WHITE align=center valign=top>09:04</td> 12879 <td align=left valign=top>RW</td> 12880 <td align=left valign=top>tx_disable_timer_ctrl</td> 12881 <td align=left> 12882 tx_disable timer value controls <br> 12883 tx_disable_timer_ctrl[5] (MSB) selects the timer units <br> 12884 0 - 2us units <br> 12885 1 - 1ms units <br> 12886 <br> 12887 tx_disable_timer_ctrl[4:0] (LSB[4:0]) = controls the number of units per <br> 12888 the list below <br> 12889 0                 0 units  <br> 12890 1                 1 units  <br> 12891 2                 2 units  <br> 12892 3                 3 units  <br> 12893 4                 4 units  <br> 12894 5                 5 units  <br> 12895 6                 6 units  <br> 12896 7                 7 units  <br> 12897 8                 8 units  <br> 12898 9                10 units  <br> 12899 10               12 units  <br> 12900 11               14 units  <br> 12901 12               16 units  <br> 12902 13               20 units  <br> 12903 14               24 units  <br> 12904 15               28 units  <br> 12905 16               32 units  <br> 12906 17               40 units  <br> 12907 18               48 units  <br> 12908 19               56 units  <br> 12909 20               64 units  <br> 12910 21               80 units  <br> 12911 22               96 units  <br> 12912 23              112 units  <br> 12913 24              128 units  <br> 12914 25              160 units  <br> 12915 26              192 units  <br> 12916 27              224 units  <br> 12917 28              256 units  <br> 12918 29              320 units  <br> 12919 30              384 units  <br> 12920 31              448 units  <br> 12921 Reset value is 0x16.</td></tr> 12922 <tr bgcolor=WHITE> 12923 <td bgcolor=WHITE align=center valign=top>03</td> 12924 <td align=left valign=top>RW</td> 12925 <td align=left valign=top>pmd_tx_disable_pkill</td> 12926 <td align=left> 12927 Tx disable using the pmd_tx_disable pin disable control <br> 12928 0 - enable tx disable from pmd_tx_disable pin <br> 12929 1 - disable tx disable from pmd_tx_disable pin <br> 12930 Reset value is 0.</td></tr> 12931 <tr bgcolor=WHITE> 12932 <td bgcolor=WHITE align=center valign=top>02</td> 12933 <td align=left valign=top>RW</td> 12934 <td align=left valign=top>dp_reset_tx_disable_dis</td> 12935 <td align=left> 12936 Tx disable based on data path reset<br> 12937 0 - Enable tx disable based on data path reset<br> 12938 1 - Disable tx disable based on data path reset<br> 12939      Need to set this bit to 1 if tx_disable_output_sel = 2'b01 (send TX power down).<br> 12940 Reset value is 0.</td></tr> 12941 <tr bgcolor=WHITE> 12942 <td bgcolor=WHITE align=center valign=top>01</td> 12943 <td align=left valign=top>SC</td> 12944 <td align=left valign=top>tx_disable_trigger</td> 12945 <td align=left> 12946 Tx disable trigger <br> 12947 When this bit is set to 1, it triggers a TX disable with timer starting at 0. <br> 12948 No matter where the TX disable state is, it start a new timer and apply TX disable. <br> 12949 This bit is self clearing <br> 12950 Reset value is 0.</td></tr> 12951 <tr bgcolor=WHITE> 12952 <td bgcolor=WHITE align=center valign=top>00</td> 12953 <td align=left valign=top>RW</td> 12954 <td align=left valign=top>micro_tx_disable</td> 12955 <td align=left> 12956 micro tx disable <br> 12957 This field is used by the Microcontroller for tx disable control during CL72 forced mode <br> 12958 Please see Eagle & Merlin PMD Internal Functional Specification for details <br> 12959 Reset value is 0.</td></tr> 12960 </table><p> 12961 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 12962 <hr> 12963 <b><a NAME="TX_FED_POST2_AFE_CONTROL0">TX_FED_POST2_AFE_CONTROL0 - post2 slice select control register</a></b><br> 12964 Address Offset = 32'h0000_d11b<br> 12965 Physical Address = 32'h0000_d11b<br> 12966 Reset Value = 16'h00a0<br> 12967 Access = RW (16-bit only)<br> 12968 <table border=1 align=center width=100% cellpadding=0> 12969 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 12970 <tr bgcolor=WHITE> 12971 <td bgcolor=WHITE align=center valign=top>15:08</td> 12972 <td align=left valign=top>RSVD</td> 12973 <td align=left valign=top>Reserved</td> 12974 <td align=left> 12975 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 12976 <tr bgcolor=WHITE> 12977 <td bgcolor=WHITE align=center valign=top>07</td> 12978 <td align=left valign=top>RW</td> 12979 <td align=left valign=top>txfir_dc_level_post2_2x_1</td> 12980 <td align=left> 12981 post2_2x[1] slice select - dc_level <br> 12982 maps to i_txk_fir_main_post2[3] pin on m16 afe <br> 12983 Reset value is 1.</td></tr> 12984 <tr bgcolor=WHITE> 12985 <td bgcolor=WHITE align=center valign=top>06</td> 12986 <td align=left valign=top>RW</td> 12987 <td align=left valign=top>txfir_post2_post2_2x_1</td> 12988 <td align=left> 12989 post2_2x[1] slice select - post2 <br> 12990 maps to i_txk_fir_post2_post2[3] pin on m16 afe <br> 12991 Reset value is 0.</td></tr> 12992 <tr bgcolor=WHITE> 12993 <td bgcolor=WHITE align=center valign=top>05</td> 12994 <td align=left valign=top>RW</td> 12995 <td align=left valign=top>txfir_dc_level_post2_2x_0</td> 12996 <td align=left> 12997 post2_2x[0] slice select - dc_level <br> 12998 maps to i_txk_fir_main_post2[2] pin on m16 afe <br> 12999 Reset value is 1.</td></tr> 13000 <tr bgcolor=WHITE> 13001 <td bgcolor=WHITE align=center valign=top>04</td> 13002 <td align=left valign=top>RW</td> 13003 <td align=left valign=top>txfir_post2_post2_2x_0</td> 13004 <td align=left> 13005 post2_2x[0] slice select - post2 <br> 13006 maps to i_txk_fir_post2_post2[2] pin on m16 afe <br> 13007 Reset value is 0.</td></tr> 13008 <tr bgcolor=WHITE> 13009 <td bgcolor=WHITE align=center valign=top>03</td> 13010 <td align=left valign=top>RW</td> 13011 <td align=left valign=top>txfir_dc_level_post2_1x_1</td> 13012 <td align=left> 13013 post2_1x[1] slice select - dc_level <br> 13014 maps to i_txk_fir_main_post2[1] pin on m16 afe <br> 13015 Reset value is 0.</td></tr> 13016 <tr bgcolor=WHITE> 13017 <td bgcolor=WHITE align=center valign=top>02</td> 13018 <td align=left valign=top>RW</td> 13019 <td align=left valign=top>txfir_post2_post2_1x_1</td> 13020 <td align=left> 13021 post2_1x[1] slice select - post2 <br> 13022 maps to i_txk_fir_post2_post2[1] pin on m16 afe <br> 13023 Reset value is 0.</td></tr> 13024 <tr bgcolor=WHITE> 13025 <td bgcolor=WHITE align=center valign=top>01</td> 13026 <td align=left valign=top>RW</td> 13027 <td align=left valign=top>txfir_dc_level_post2_1x_0</td> 13028 <td align=left> 13029 post2_1x[0] slice select - dc_level <br> 13030 maps to i_txk_fir_main_post2[0] pin on m16 afe <br> 13031 Reset value is 0.</td></tr> 13032 <tr bgcolor=WHITE> 13033 <td bgcolor=WHITE align=center valign=top>00</td> 13034 <td align=left valign=top>RW</td> 13035 <td align=left valign=top>txfir_post2_post2_1x_0</td> 13036 <td align=left> 13037 post2_1x[0] slice select - post2 <br> 13038 maps to i_txk_fir_post2_post2[0] pin on m16 afe <br> 13039 Reset value is 0.</td></tr> 13040 </table><p> 13041 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 13042 <hr> 13043 <b><a NAME="TX_FED_POST1_AFE_CONTROL0">TX_FED_POST1_AFE_CONTROL0 - post1 slice select control register</a></b><br> 13044 Address Offset = 32'h0000_d11c<br> 13045 Physical Address = 32'h0000_d11c<br> 13046 Reset Value = 16'h02a0<br> 13047 Access = RW (16-bit only)<br> 13048 <table border=1 align=center width=100% cellpadding=0> 13049 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13050 <tr bgcolor=WHITE> 13051 <td bgcolor=WHITE align=center valign=top>15</td> 13052 <td align=left valign=top>RSVD</td> 13053 <td align=left valign=top>Reserved</td> 13054 <td align=left> 13055 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13056 <tr bgcolor=WHITE> 13057 <td bgcolor=WHITE align=center valign=top>14</td> 13058 <td align=left valign=top>RW</td> 13059 <td align=left valign=top>txfir_dc_level_post1pre_1x_0</td> 13060 <td align=left> 13061 post1pre_1x[0] slice select - dc_level <br> 13062 maps to i_txk_fir_main_post1pre[0] pin on m16 afe <br> 13063 Reset value is 0.</td></tr> 13064 <tr bgcolor=WHITE> 13065 <td bgcolor=WHITE align=center valign=top>13</td> 13066 <td align=left valign=top>RW</td> 13067 <td align=left valign=top>txfir_post1_post1pre_1x_0</td> 13068 <td align=left> 13069 post1pre_1x[0] slice select - post1 <br> 13070 maps to i_txk_fir_post1_post1pre[0] pin on m16 afe <br> 13071 Reset value is 0.</td></tr> 13072 <tr bgcolor=WHITE> 13073 <td bgcolor=WHITE align=center valign=top>12</td> 13074 <td align=left valign=top>RW</td> 13075 <td align=left valign=top>txfir_pre_post1pre_1x_0</td> 13076 <td align=left> 13077 post1pre_1x[0] slice select - pre <br> 13078 maps to i_txk_fir_pre_post1pre[0] pin on m16 afe <br> 13079 Reset value is 0.</td></tr> 13080 <tr bgcolor=WHITE> 13081 <td bgcolor=WHITE align=center valign=top>11:10</td> 13082 <td align=left valign=top>RSVD</td> 13083 <td align=left valign=top>Reserved</td> 13084 <td align=left> 13085 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 13086 <tr bgcolor=WHITE> 13087 <td bgcolor=WHITE align=center valign=top>09</td> 13088 <td align=left valign=top>RW</td> 13089 <td align=left valign=top>txfir_dc_level_post1_2x_2</td> 13090 <td align=left> 13091 post1_2x[2] slice select - dc_level <br> 13092 maps to i_txk_fir_main_post1[4] pin on m16 afe <br> 13093 Reset value is 1.</td></tr> 13094 <tr bgcolor=WHITE> 13095 <td bgcolor=WHITE align=center valign=top>08</td> 13096 <td align=left valign=top>RW</td> 13097 <td align=left valign=top>txfir_post1_post1_2x_2</td> 13098 <td align=left> 13099 pos1_2x[2] slice select - post1 <br> 13100 maps to i_txk_fir_post1_post1[4] pin on m16 afe <br> 13101 Reset value is 0.</td></tr> 13102 <tr bgcolor=WHITE> 13103 <td bgcolor=WHITE align=center valign=top>07</td> 13104 <td align=left valign=top>RW</td> 13105 <td align=left valign=top>txfir_dc_level_post1_2x_1</td> 13106 <td align=left> 13107 post1_2x[1] slice select - dc_level <br> 13108 maps to i_txk_fir_main_post1[3] pin on m16 afe <br> 13109 Reset value is 1.</td></tr> 13110 <tr bgcolor=WHITE> 13111 <td bgcolor=WHITE align=center valign=top>06</td> 13112 <td align=left valign=top>RW</td> 13113 <td align=left valign=top>txfir_post1_post1_2x_1</td> 13114 <td align=left> 13115 pos1_2x[1] slice select - post1 <br> 13116 maps to i_txk_fir_post1_post1[3] pin on m16 afe <br> 13117 Reset value is 0.</td></tr> 13118 <tr bgcolor=WHITE> 13119 <td bgcolor=WHITE align=center valign=top>05</td> 13120 <td align=left valign=top>RW</td> 13121 <td align=left valign=top>txfir_dc_level_post1_2x_0</td> 13122 <td align=left> 13123 post1_2x[0] slice select - dc_level <br> 13124 maps to i_txk_fir_main_post1[2] pin on m16 afe <br> 13125 Reset value is 1.</td></tr> 13126 <tr bgcolor=WHITE> 13127 <td bgcolor=WHITE align=center valign=top>04</td> 13128 <td align=left valign=top>RW</td> 13129 <td align=left valign=top>txfir_post1_post1_2x_0</td> 13130 <td align=left> 13131 pos1_2x[0] slice select - post1 <br> 13132 maps to i_txk_fir_post1_post1[2] pin on m16 afe <br> 13133 Reset value is 0.</td></tr> 13134 <tr bgcolor=WHITE> 13135 <td bgcolor=WHITE align=center valign=top>03</td> 13136 <td align=left valign=top>RW</td> 13137 <td align=left valign=top>txfir_dc_level_post1_1x_1</td> 13138 <td align=left> 13139 post1_1x[1] slice select - dc_level <br> 13140 maps to i_txk_fir_main_post1[1] pin on m16 afe <br> 13141 Reset value is 0.</td></tr> 13142 <tr bgcolor=WHITE> 13143 <td bgcolor=WHITE align=center valign=top>02</td> 13144 <td align=left valign=top>RW</td> 13145 <td align=left valign=top>txfir_post1_post1_1x_1</td> 13146 <td align=left> 13147 post1_1x[1] slice select - post1 <br> 13148 maps to i_txk_fir_post1_post1[1] pin on m16 afe <br> 13149 Reset value is 0.</td></tr> 13150 <tr bgcolor=WHITE> 13151 <td bgcolor=WHITE align=center valign=top>01</td> 13152 <td align=left valign=top>RW</td> 13153 <td align=left valign=top>txfir_dc_level_post1_1x_0</td> 13154 <td align=left> 13155 post1_1x[0] slice select - dc_level <br> 13156 maps to i_txk_fir_main_post1[0] pin on m16 afe <br> 13157 Reset value is 0.</td></tr> 13158 <tr bgcolor=WHITE> 13159 <td bgcolor=WHITE align=center valign=top>00</td> 13160 <td align=left valign=top>RW</td> 13161 <td align=left valign=top>txfir_post1_post1_1x_0</td> 13162 <td align=left> 13163 post1_1x[0] slice select - post1 <br> 13164 maps to i_txk_fir_post1_post1[0] pin on m16 afe <br> 13165 Reset value is 0.</td></tr> 13166 </table><p> 13167 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 13168 <hr> 13169 <b><a NAME="TX_FED_POST1PRE_AFE_CONTROL0">TX_FED_POST1PRE_AFE_CONTROL0 - post1pre slice select control register</a></b><br> 13170 Address Offset = 32'h0000_d11d<br> 13171 Physical Address = 32'h0000_d11d<br> 13172 Reset Value = 16'h4000<br> 13173 Access = RW (16-bit only)<br> 13174 <table border=1 align=center width=100% cellpadding=0> 13175 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13176 <tr bgcolor=WHITE> 13177 <td bgcolor=WHITE align=center valign=top>15</td> 13178 <td align=left valign=top>RSVD</td> 13179 <td align=left valign=top>Reserved</td> 13180 <td align=left> 13181 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13182 <tr bgcolor=WHITE> 13183 <td bgcolor=WHITE align=center valign=top>14</td> 13184 <td align=left valign=top>RW</td> 13185 <td align=left valign=top>txfir_dc_level_post1pre_2x_3</td> 13186 <td align=left> 13187 post1pre_2x[3] slice select - dc_level <br> 13188 maps to i_txk_fir_main_post1pre[5] pin on m16 afe <br> 13189 Reset value is 1.</td></tr> 13190 <tr bgcolor=WHITE> 13191 <td bgcolor=WHITE align=center valign=top>13</td> 13192 <td align=left valign=top>RW</td> 13193 <td align=left valign=top>txfir_post1_post1pre_2x_3</td> 13194 <td align=left> 13195 post1pre_2x[3] slice select - post1 <br> 13196 maps to i_txk_fir_post1_post1pre[5] pin on m16 afe <br> 13197 Reset value is 0.</td></tr> 13198 <tr bgcolor=WHITE> 13199 <td bgcolor=WHITE align=center valign=top>12</td> 13200 <td align=left valign=top>RW</td> 13201 <td align=left valign=top>txfir_pre_post1pre_2x_3</td> 13202 <td align=left> 13203 post1pre_2x[3] slice select - pre <br> 13204 maps to i_txk_fir_pre_post1pre[5] pin on m16 afe <br> 13205 Reset value is 0.</td></tr> 13206 <tr bgcolor=WHITE> 13207 <td bgcolor=WHITE align=center valign=top>11</td> 13208 <td align=left valign=top>RW</td> 13209 <td align=left valign=top>txfir_dc_level_post1pre_2x_2</td> 13210 <td align=left> 13211 post1pre_2x[2] slice select - dc_level <br> 13212 maps to i_txk_fir_main_post1pre[4] pin on m16 afe <br> 13213 Reset value is 0.</td></tr> 13214 <tr bgcolor=WHITE> 13215 <td bgcolor=WHITE align=center valign=top>10</td> 13216 <td align=left valign=top>RW</td> 13217 <td align=left valign=top>txfir_post1_post1pre_2x_2</td> 13218 <td align=left> 13219 post1pre_2x[2] slice select - post1 <br> 13220 maps to i_txk_fir_post1_post1pre[4] pin on m16 afe <br> 13221 Reset value is 0.</td></tr> 13222 <tr bgcolor=WHITE> 13223 <td bgcolor=WHITE align=center valign=top>09</td> 13224 <td align=left valign=top>RW</td> 13225 <td align=left valign=top>txfir_pre_post1pre_2x_2</td> 13226 <td align=left> 13227 post1pre_2x[2] slice select - pre <br> 13228 maps to i_txk_fir_pre_post1pre[4] pin on m16 afe <br> 13229 Reset value is 0.</td></tr> 13230 <tr bgcolor=WHITE> 13231 <td bgcolor=WHITE align=center valign=top>08</td> 13232 <td align=left valign=top>RW</td> 13233 <td align=left valign=top>txfir_dc_level_post1pre_2x_1</td> 13234 <td align=left> 13235 post1pre_2x[1] slice select - dc_level <br> 13236 maps to i_txk_fir_main_post1pre[3] pin on m16 afe <br> 13237 Reset value is 0.</td></tr> 13238 <tr bgcolor=WHITE> 13239 <td bgcolor=WHITE align=center valign=top>07</td> 13240 <td align=left valign=top>RW</td> 13241 <td align=left valign=top>txfir_post1_post1pre_2x_1</td> 13242 <td align=left> 13243 post1pre_2x[1] slice select - post1 <br> 13244 maps to i_txk_fir_post1_post1pre[3] pin on m16 afe <br> 13245 Reset value is 0.</td></tr> 13246 <tr bgcolor=WHITE> 13247 <td bgcolor=WHITE align=center valign=top>06</td> 13248 <td align=left valign=top>RW</td> 13249 <td align=left valign=top>txfir_pre_post1pre_2x_1</td> 13250 <td align=left> 13251 post1pre_2x[1] slice select - pre <br> 13252 maps to i_txk_fir_pre_post1pre[3] pin on m16 afe <br> 13253 Reset value is 0.</td></tr> 13254 <tr bgcolor=WHITE> 13255 <td bgcolor=WHITE align=center valign=top>05</td> 13256 <td align=left valign=top>RW</td> 13257 <td align=left valign=top>txfir_dc_level_post1pre_2x_0</td> 13258 <td align=left> 13259 post1pre_2x[0] slice select - dc_level <br> 13260 maps to i_txk_fir_main_post1pre[2] pin on m16 afe <br> 13261 Reset value is 0.</td></tr> 13262 <tr bgcolor=WHITE> 13263 <td bgcolor=WHITE align=center valign=top>04</td> 13264 <td align=left valign=top>RW</td> 13265 <td align=left valign=top>txfir_post1_post1pre_2x_0</td> 13266 <td align=left> 13267 post1pre_2x[0] slice select - post1 <br> 13268 maps to i_txk_fir_post1_post1pre[2] pin on m16 afe <br> 13269 Reset value is 0.</td></tr> 13270 <tr bgcolor=WHITE> 13271 <td bgcolor=WHITE align=center valign=top>03</td> 13272 <td align=left valign=top>RW</td> 13273 <td align=left valign=top>txfir_pre_post1pre_2x_0</td> 13274 <td align=left> 13275 post1pre_2x[0] slice select - pre <br> 13276 maps to i_txk_fir_pre_post1pre[2] pin on m16 afe <br> 13277 Reset value is 0.</td></tr> 13278 <tr bgcolor=WHITE> 13279 <td bgcolor=WHITE align=center valign=top>02</td> 13280 <td align=left valign=top>RW</td> 13281 <td align=left valign=top>txfir_dc_level_post1pre_1x_1</td> 13282 <td align=left> 13283 post1pre_1x[1] slice select - dc_level <br> 13284 maps to i_txk_fir_main_post1pre[1] pin on m16 afe <br> 13285 Reset value is 0.</td></tr> 13286 <tr bgcolor=WHITE> 13287 <td bgcolor=WHITE align=center valign=top>01</td> 13288 <td align=left valign=top>RW</td> 13289 <td align=left valign=top>txfir_post1_post1pre_1x_1</td> 13290 <td align=left> 13291 post1pre_1x[1] slice select - post1 <br> 13292 maps to i_txk_fir_post1_post1pre[1] pin on m16 afe <br> 13293 Reset value is 0.</td></tr> 13294 <tr bgcolor=WHITE> 13295 <td bgcolor=WHITE align=center valign=top>00</td> 13296 <td align=left valign=top>RW</td> 13297 <td align=left valign=top>txfir_pre_post1pre_1x_1</td> 13298 <td align=left> 13299 post1pre_1x[1] slice select - pre <br> 13300 maps to i_txk_fir_pre_post1pre[1] pin on m16 afe <br> 13301 Reset value is 0.</td></tr> 13302 </table><p> 13303 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 13304 <hr> 13305 <b><a NAME="TX_FED_DC_LEVEL_AFE_CONTROL0">TX_FED_DC_LEVEL_AFE_CONTROL0 - dc_level slice select control register</a></b><br> 13306 Address Offset = 32'h0000_d11e<br> 13307 Physical Address = 32'h0000_d11e<br> 13308 Reset Value = 16'h000f<br> 13309 Access = RW (16-bit only)<br> 13310 <table border=1 align=center width=100% cellpadding=0> 13311 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13312 <tr bgcolor=WHITE> 13313 <td bgcolor=WHITE align=center valign=top>15:04</td> 13314 <td align=left valign=top>RSVD</td> 13315 <td align=left valign=top>Reserved</td> 13316 <td align=left> 13317 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 13318 <tr bgcolor=WHITE> 13319 <td bgcolor=WHITE align=center valign=top>03</td> 13320 <td align=left valign=top>RW</td> 13321 <td align=left valign=top>txfir_dc_level_2x_1</td> 13322 <td align=left> 13323 dc_level_2x[1] slice enable <br> 13324 maps to i_txk_fir_en_main_cs[2] pin on m16 afe <br> 13325 Reset value is 1.</td></tr> 13326 <tr bgcolor=WHITE> 13327 <td bgcolor=WHITE align=center valign=top>02</td> 13328 <td align=left valign=top>RW</td> 13329 <td align=left valign=top>txfir_dc_level_2x_0</td> 13330 <td align=left> 13331 dc_level_2x[0] slice enable <br> 13332 maps to i_txk_fir_en_main_cs[1] pin on m16 afe <br> 13333 Reset value is 1.</td></tr> 13334 <tr bgcolor=WHITE> 13335 <td bgcolor=WHITE align=center valign=top>01</td> 13336 <td align=left valign=top>RW</td> 13337 <td align=left valign=top>txfir_dc_level_1x</td> 13338 <td align=left> 13339 dc_level_1x slice enable <br> 13340 maps to i_txk_fir_en_main_cs[0] pin on m16 afe <br> 13341 Reset value is 1.</td></tr> 13342 <tr bgcolor=WHITE> 13343 <td bgcolor=WHITE align=center valign=top>00</td> 13344 <td align=left valign=top>RW</td> 13345 <td align=left valign=top>txfir_dc_level_0p5x</td> 13346 <td align=left> 13347 txfir_dc_level_0p5x slice enable <br> 13348 maps to i_txk_fir_en_main pin on m16 afe <br> 13349 Reset value is 1.</td></tr> 13350 </table><p> 13351 <A HREF="#TX_FED Registers">Return to TX_FED: per lane register block [One Copy Per Lane] Table</A><p> 13352 <hr> 13353 <H1><a NAME="PLL_CAL_COM Registers">PLL_CAL_COM: common register block for all lanes Registers</a></H1> 13354 <table border=1 align=center width=100% cellpadding=0> 13355 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 13356 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 13357 <tr> 13358 <td align=center>0xD120</td><td><A HREF="#PLL_CAL_COM_CTL_0">PLL_CAL_COM_CTL_0</A><br>PLL_CAL_CTL_0</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cal_th</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_cal_jump_ena</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">calib_step_time</div> </td> <td align=center>16'h0100</td></tr> 13359 <tr> 13360 <td align=center>0xD121</td><td><A HREF="#PLL_CAL_COM_CTL_1">PLL_CAL_COM_CTL_1</A><br>PLL_CAL_CTL_1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">freqdet_time</div> </td> <td align=center>16'hfff0</td></tr> 13361 <tr> 13362 <td align=center>0xD122</td><td><A HREF="#PLL_CAL_COM_CTL_2">PLL_CAL_COM_CTL_2</A><br>PLL_CAL_CTL_2</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="12"><div class="HT">calib_cap_charge_time</div> </td> <td align=center>16'h01ff</td></tr> 13363 <tr> 13364 <td align=center>0xD123</td><td><A HREF="#PLL_CAL_COM_CTL_3">PLL_CAL_COM_CTL_3</A><br>PLL_CAL_CTL_3</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">ext_state</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">accel_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">debug_clr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">freqdet_time_msb</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">freqdet_win</div> </td> <td align=center>16'h1007</td></tr> 13365 <tr> 13366 <td align=center>0xD124</td><td><A HREF="#PLL_CAL_COM_CTL_4">PLL_CAL_COM_CTL_4</A><br>PLL_CAL_CTL_4</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">halfstep_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_force_cap_pass_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_force_cap_pass</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cal_pause_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cal_pause_rel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cap_delay</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">calib_start</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">en_calib_n</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">ext_range</div> </td> <td align=center>16'h8240</td></tr> 13367 <tr> 13368 <td align=center>0xD125</td><td><A HREF="#PLL_CAL_COM_CTL_5">PLL_CAL_COM_CTL_5</A><br>PLL_CAL_CTL_5</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_seq_start</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lkdt_pause_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lkdt_pause_rel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vco_rst_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">autocal_en</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">autocal_cnt</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lkdt_byp</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_lock_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_lock_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pllforce_fdone</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pllforce_fdone_en</div> </td> <td align=center>16'h8160</td></tr> 13369 <tr> 13370 <td align=center>0xD126</td><td><A HREF="#PLL_CAL_COM_CTL_6">PLL_CAL_COM_CTL_6</A><br>PLL_CAL_CTL_6</td><td bgcolor=#CCCCCC align=center colspan="8"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">band_iqbuf_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vcorange_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vcobufpon_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vcopon_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pllpon_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td align=center>16'h0000</td></tr> 13371 <tr> 13372 <td align=center>0xD128</td><td><A HREF="#PLL_CAL_COM_STS_0">PLL_CAL_COM_STS_0</A><br>PLL_CAL_STS_0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_fail_stky</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cal_state</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cal_valid</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_lock</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_lock_bar_stky</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">pll_range</div> </td> <td align=center>16'h013f</td></tr> 13373 <tr> 13374 <td align=center>0xD129</td><td><A HREF="#PLL_CAL_COM_STS_1">PLL_CAL_COM_STS_1</A><br>PLL_CAL_STS_1</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lkdtref_counter_msb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">lkdtvco_counter_msb</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">calref_counter</div> </td> <td align=center>16'h0000</td></tr> 13375 <tr> 13376 <td align=center>0xD12A</td><td><A HREF="#PLL_CAL_COM_STS_2">PLL_CAL_COM_STS_2</A><br>PLL_CAL_STS_2</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">band_iqbuf_mux</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">calvco_counter</div> </td> <td align=center>16'h6000</td></tr> 13377 <tr> 13378 <td align=center>0xD12B</td><td><A HREF="#PLL_CAL_COM_STS_3">PLL_CAL_COM_STS_3</A><br>PLL_CAL_STS_3</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lkdtref_counter</div> </td> <td align=center>16'h0000</td></tr> 13379 <tr> 13380 <td align=center>0xD12C</td><td><A HREF="#PLL_CAL_COM_STS_4">PLL_CAL_COM_STS_4</A><br>PLL_CAL_STS_4</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">lkdtvco_counter</div> </td> <td align=center>16'h0000</td></tr> 13381 <tr> 13382 <td align=center>0xD12D</td><td><A HREF="#PLL_CAL_COM_STS_5">PLL_CAL_COM_STS_5</A><br>PLL_CAL_STS_5</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vcobufpon_mux</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">calstate_onehot</div> </td> <td align=center>16'h0000</td></tr> 13383 <tr> 13384 <td align=center>0xD12E</td><td><A HREF="#PLL_CAL_COM_STS_6">PLL_CAL_COM_STS_6</A><br>PLL_CAL_STS_6</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pll_pwrdn_or</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">vco_range_mux</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">vcopon_mux</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pllpon_mux</div> </td> <td align=center>16'h3f00</td></tr> 13385 </table><p> 13386 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 13387 <hr> 13388 <b><a NAME="PLL_CAL_COM_CTL_0">PLL_CAL_COM_CTL_0 - PLL_CAL_CTL_0</a></b><br> 13389 Address Offset = 32'h0000_d120<br> 13390 Physical Address = 32'h0000_d120<br> 13391 Reset Value = 16'h0100<br> 13392 Access = RW (16-bit only)<br> 13393 <table border=1 align=center width=100% cellpadding=0> 13394 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13395 <tr bgcolor=WHITE> 13396 <td bgcolor=WHITE align=center valign=top>15:14</td> 13397 <td align=left valign=top>RW</td> 13398 <td align=left valign=top>cal_th</td> 13399 <td align=left> 13400 programmable PLL calibration threshold for best, typical and worst case<br> 13401 Reset value is 0x0.</td></tr> 13402 <tr bgcolor=WHITE> 13403 <td bgcolor=WHITE align=center valign=top>13</td> 13404 <td align=left valign=top>RW</td> 13405 <td align=left valign=top>pll_cal_jump_ena</td> 13406 <td align=left> 13407 when asserted will allow CALIB SM to jump tuning states for faster lock<br> 13408 Reset value is 0x0.</td></tr> 13409 <tr bgcolor=WHITE> 13410 <td bgcolor=WHITE align=center valign=top>12:00</td> 13411 <td align=left valign=top>RW</td> 13412 <td align=left valign=top>calib_step_time</td> 13413 <td align=left> 13414 The number of divided vco/ref calibration clocks to wait after the pll range has been changed<br> 13415 Reset value is 0x100.</td></tr> 13416 </table><p> 13417 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13418 <hr> 13419 <b><a NAME="PLL_CAL_COM_CTL_1">PLL_CAL_COM_CTL_1 - PLL_CAL_CTL_1</a></b><br> 13420 Address Offset = 32'h0000_d121<br> 13421 Physical Address = 32'h0000_d121<br> 13422 Reset Value = 16'hfff0<br> 13423 Access = RW (16-bit only)<br> 13424 <table border=1 align=center width=100% cellpadding=0> 13425 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13426 <tr bgcolor=WHITE> 13427 <td bgcolor=WHITE align=center valign=top>15:00</td> 13428 <td align=left valign=top>RW</td> 13429 <td align=left valign=top>freqdet_time</td> 13430 <td align=left> 13431 ref/vco counter terminal value in lockdet module<br> 13432 Reset value is 0xfff0.</td></tr> 13433 </table><p> 13434 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13435 <hr> 13436 <b><a NAME="PLL_CAL_COM_CTL_2">PLL_CAL_COM_CTL_2 - PLL_CAL_CTL_2</a></b><br> 13437 Address Offset = 32'h0000_d122<br> 13438 Physical Address = 32'h0000_d122<br> 13439 Reset Value = 16'h01ff<br> 13440 Access = RW (16-bit only)<br> 13441 <table border=1 align=center width=100% cellpadding=0> 13442 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13443 <tr bgcolor=WHITE> 13444 <td bgcolor=WHITE align=center valign=top>15:12</td> 13445 <td align=left valign=top>RSVD</td> 13446 <td align=left valign=top>Reserved</td> 13447 <td align=left> 13448 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 13449 <tr bgcolor=WHITE> 13450 <td bgcolor=WHITE align=center valign=top>11:00</td> 13451 <td align=left valign=top>RW</td> 13452 <td align=left valign=top>calib_cap_charge_time</td> 13453 <td align=left> 13454 The number of divided ref calibration clocks to wait for initial cap charge time<br> 13455 Reset value is 0x1ff.</td></tr> 13456 </table><p> 13457 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13458 <hr> 13459 <b><a NAME="PLL_CAL_COM_CTL_3">PLL_CAL_COM_CTL_3 - PLL_CAL_CTL_3</a></b><br> 13460 Address Offset = 32'h0000_d123<br> 13461 Physical Address = 32'h0000_d123<br> 13462 Reset Value = 16'h1007<br> 13463 Access = RW (16-bit only)<br> 13464 <table border=1 align=center width=100% cellpadding=0> 13465 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13466 <tr bgcolor=WHITE> 13467 <td bgcolor=WHITE align=center valign=top>15:12</td> 13468 <td align=left valign=top>RW</td> 13469 <td align=left valign=top>ext_state</td> 13470 <td align=left> 13471 state to be forced into when in accelerated mode, dfs to s0<br> 13472 Reset value is 0x1.</td></tr> 13473 <tr bgcolor=WHITE> 13474 <td bgcolor=WHITE align=center valign=top>11</td> 13475 <td align=left valign=top>RW</td> 13476 <td align=left valign=top>accel_en</td> 13477 <td align=left> 13478 accelerated mode enable<br> 13479 Reset value is 0x0.</td></tr> 13480 <tr bgcolor=WHITE> 13481 <td bgcolor=WHITE align=center valign=top>10</td> 13482 <td align=left valign=top>RW</td> 13483 <td align=left valign=top>debug_clr</td> 13484 <td align=left> 13485 set 1 to clear debug status. cal state one hot<br> 13486 Reset value is 0x0.</td></tr> 13487 <tr bgcolor=WHITE> 13488 <td bgcolor=WHITE align=center valign=top>09</td> 13489 <td align=left valign=top>RW</td> 13490 <td align=left valign=top>freqdet_time_msb</td> 13491 <td align=left> 13492 The MSB for freqdet_time<br> 13493 Reset value is 0x0.</td></tr> 13494 <tr bgcolor=WHITE> 13495 <td bgcolor=WHITE align=center valign=top>08</td> 13496 <td align=left valign=top>RSVD</td> 13497 <td align=left valign=top>Reserved</td> 13498 <td align=left> 13499 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13500 <tr bgcolor=WHITE> 13501 <td bgcolor=WHITE align=center valign=top>07:00</td> 13502 <td align=left valign=top>RW</td> 13503 <td align=left valign=top>freqdet_win</td> 13504 <td align=left> 13505 Frequency detect compare window in lockdet module<br> 13506 Reset value is 0x7.</td></tr> 13507 </table><p> 13508 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13509 <hr> 13510 <b><a NAME="PLL_CAL_COM_CTL_4">PLL_CAL_COM_CTL_4 - PLL_CAL_CTL_4</a></b><br> 13511 Address Offset = 32'h0000_d124<br> 13512 Physical Address = 32'h0000_d124<br> 13513 Reset Value = 16'h8240<br> 13514 Access = RW (16-bit only)<br> 13515 <table border=1 align=center width=100% cellpadding=0> 13516 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13517 <tr bgcolor=WHITE> 13518 <td bgcolor=WHITE align=center valign=top>15</td> 13519 <td align=left valign=top>RW</td> 13520 <td align=left valign=top>halfstep_en</td> 13521 <td align=left> 13522 enable half_step pll calibration<br> 13523 Reset value is 0x1.</td></tr> 13524 <tr bgcolor=WHITE> 13525 <td bgcolor=WHITE align=center valign=top>14</td> 13526 <td align=left valign=top>RW</td> 13527 <td align=left valign=top>pll_force_cap_pass_en</td> 13528 <td align=left> 13529 force cal_valid<br> 13530 Reset value is 0x0.</td></tr> 13531 <tr bgcolor=WHITE> 13532 <td bgcolor=WHITE align=center valign=top>13</td> 13533 <td align=left valign=top>RW</td> 13534 <td align=left valign=top>pll_force_cap_pass</td> 13535 <td align=left> 13536 force cal_valid value<br> 13537 Reset value is 0x0.</td></tr> 13538 <tr bgcolor=WHITE> 13539 <td bgcolor=WHITE align=center valign=top>12</td> 13540 <td align=left valign=top>RW</td> 13541 <td align=left valign=top>cal_pause_en</td> 13542 <td align=left> 13543 enable pausing to calib process, for debug only<br> 13544 Reset value is 0x0.</td></tr> 13545 <tr bgcolor=WHITE> 13546 <td bgcolor=WHITE align=center valign=top>11</td> 13547 <td align=left valign=top>RW</td> 13548 <td align=left valign=top>cal_pause_rel</td> 13549 <td align=left> 13550 release pausing to calib process at posedge, for debug only<br> 13551 Reset value is 0x0.</td></tr> 13552 <tr bgcolor=WHITE> 13553 <td bgcolor=WHITE align=center valign=top>10</td> 13554 <td align=left valign=top>RW</td> 13555 <td align=left valign=top>cap_delay</td> 13556 <td align=left> 13557 additional delay to calibration step time<br> 13558 Reset value is 0x0.</td></tr> 13559 <tr bgcolor=WHITE> 13560 <td bgcolor=WHITE align=center valign=top>09</td> 13561 <td align=left valign=top>RW</td> 13562 <td align=left valign=top>calib_start</td> 13563 <td align=left> 13564 1 to start calib, 0 to disable calibration<br> 13565 Reset value is 0x1.</td></tr> 13566 <tr bgcolor=WHITE> 13567 <td bgcolor=WHITE align=center valign=top>08</td> 13568 <td align=left valign=top>RW</td> 13569 <td align=left valign=top>en_calib_n</td> 13570 <td align=left> 13571 Enable calibration - active low<br> 13572 Reset value is 0x0.</td></tr> 13573 <tr bgcolor=WHITE> 13574 <td bgcolor=WHITE align=center valign=top>07</td> 13575 <td align=left valign=top>RSVD</td> 13576 <td align=left valign=top>Reserved</td> 13577 <td align=left> 13578 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13579 <tr bgcolor=WHITE> 13580 <td bgcolor=WHITE align=center valign=top>06:00</td> 13581 <td align=left valign=top>RW</td> 13582 <td align=left valign=top>ext_range</td> 13583 <td align=left> 13584 Externally programmable value for PLL_RANGE<br> 13585 Reset value is 0x40.</td></tr> 13586 </table><p> 13587 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13588 <hr> 13589 <b><a NAME="PLL_CAL_COM_CTL_5">PLL_CAL_COM_CTL_5 - PLL_CAL_CTL_5</a></b><br> 13590 Address Offset = 32'h0000_d125<br> 13591 Physical Address = 32'h0000_d125<br> 13592 Reset Value = 16'h8160<br> 13593 Access = RW (16-bit only)<br> 13594 <table border=1 align=center width=100% cellpadding=0> 13595 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13596 <tr bgcolor=WHITE> 13597 <td bgcolor=WHITE align=center valign=top>15</td> 13598 <td align=left valign=top>RW</td> 13599 <td align=left valign=top>pll_seq_start</td> 13600 <td align=left> 13601 To start the pll sequence. For debug only, use core_dp_s/h_rstb to re-start PLL calibration<br> 13602 Reset value is 0x1.</td></tr> 13603 <tr bgcolor=WHITE> 13604 <td bgcolor=WHITE align=center valign=top>14</td> 13605 <td align=left valign=top>RW</td> 13606 <td align=left valign=top>lkdt_pause_en</td> 13607 <td align=left> 13608 Enable pausing for Frequency detect, for debug only<br> 13609 Reset value is 0x0.</td></tr> 13610 <tr bgcolor=WHITE> 13611 <td bgcolor=WHITE align=center valign=top>13</td> 13612 <td align=left valign=top>RW</td> 13613 <td align=left valign=top>lkdt_pause_rel</td> 13614 <td align=left> 13615 Release pausing for Frequency detect, for debug only<br> 13616 Reset value is 0x0.</td></tr> 13617 <tr bgcolor=WHITE> 13618 <td bgcolor=WHITE align=center valign=top>12</td> 13619 <td align=left valign=top>RW</td> 13620 <td align=left valign=top>vco_rst_en</td> 13621 <td align=left> 13622 Enable PLL reset when PLL is in start state. For debug only, use core_dp_s/h_rstb to re-start PLL calibration<br> 13623 Reset value is 0x0.</td></tr> 13624 <tr bgcolor=WHITE> 13625 <td bgcolor=WHITE align=center valign=top>11:09</td> 13626 <td align=left valign=top>RSVD</td> 13627 <td align=left valign=top>Reserved</td> 13628 <td align=left> 13629 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 13630 <tr bgcolor=WHITE> 13631 <td bgcolor=WHITE align=center valign=top>08</td> 13632 <td align=left valign=top>RW</td> 13633 <td align=left valign=top>autocal_en</td> 13634 <td align=left> 13635 auto calibration enable when no pll_lock after numbers of trials in autocal_cnt<br> 13636 Reset value is 0x1.</td></tr> 13637 <tr bgcolor=WHITE> 13638 <td bgcolor=WHITE align=center valign=top>07:05</td> 13639 <td align=left valign=top>RW</td> 13640 <td align=left valign=top>autocal_cnt</td> 13641 <td align=left> 13642 auto calibration count<br> 13643 Reset value is 0x3.</td></tr> 13644 <tr bgcolor=WHITE> 13645 <td bgcolor=WHITE align=center valign=top>04</td> 13646 <td align=left valign=top>RW</td> 13647 <td align=left valign=top>lkdt_byp</td> 13648 <td align=left> 13649 Bypass lock detect process and force Lock<br> 13650 Reset value is 0x0.</td></tr> 13651 <tr bgcolor=WHITE> 13652 <td bgcolor=WHITE align=center valign=top>03</td> 13653 <td align=left valign=top>RW</td> 13654 <td align=left valign=top>pll_lock_frc_val</td> 13655 <td align=left> 13656 Force Pll Lock value<br> 13657 Reset value is 0x0.</td></tr> 13658 <tr bgcolor=WHITE> 13659 <td bgcolor=WHITE align=center valign=top>02</td> 13660 <td align=left valign=top>RW</td> 13661 <td align=left valign=top>pll_lock_frc</td> 13662 <td align=left> 13663 Force PLL Lock<br> 13664 Reset value is 0x0.</td></tr> 13665 <tr bgcolor=WHITE> 13666 <td bgcolor=WHITE align=center valign=top>01</td> 13667 <td align=left valign=top>RW</td> 13668 <td align=left valign=top>pllforce_fdone</td> 13669 <td align=left> 13670 Force Frequency detect value value<br> 13671 Reset value is 0x0.</td></tr> 13672 <tr bgcolor=WHITE> 13673 <td bgcolor=WHITE align=center valign=top>00</td> 13674 <td align=left valign=top>RW</td> 13675 <td align=left valign=top>pllforce_fdone_en</td> 13676 <td align=left> 13677 Force Frequency detect<br> 13678 Reset value is 0x0.</td></tr> 13679 </table><p> 13680 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13681 <hr> 13682 <b><a NAME="PLL_CAL_COM_CTL_6">PLL_CAL_COM_CTL_6 - PLL_CAL_CTL_6</a></b><br> 13683 Address Offset = 32'h0000_d126<br> 13684 Physical Address = 32'h0000_d126<br> 13685 Reset Value = 16'h0000<br> 13686 Access = RW (16-bit only)<br> 13687 <table border=1 align=center width=100% cellpadding=0> 13688 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13689 <tr bgcolor=WHITE> 13690 <td bgcolor=WHITE align=center valign=top>15:08</td> 13691 <td align=left valign=top>RSVD</td> 13692 <td align=left valign=top>Reserved</td> 13693 <td align=left> 13694 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 13695 <tr bgcolor=WHITE> 13696 <td bgcolor=WHITE align=center valign=top>07</td> 13697 <td align=left valign=top>RW</td> 13698 <td align=left valign=top>band_iqbuf_sel</td> 13699 <td align=left> 13700 Force select AMS band_iqbuf value else select pll_range[6:4] from pll calibration<br> 13701 Reset value is 0x0.</td></tr> 13702 <tr bgcolor=WHITE> 13703 <td bgcolor=WHITE align=center valign=top>06</td> 13704 <td align=left valign=top>RW</td> 13705 <td align=left valign=top>vcorange_sel</td> 13706 <td align=left> 13707 Force select AMS vcorange value else select pll_range from pll calibration<br> 13708 Reset value is 0x0.</td></tr> 13709 <tr bgcolor=WHITE> 13710 <td bgcolor=WHITE align=center valign=top>05</td> 13711 <td align=left valign=top>RW</td> 13712 <td align=left valign=top>vcobufpon_sel</td> 13713 <td align=left> 13714 1= select AMS vcobufpon value, 0= select vcobufpon_int (sum or external rescal)<br> 13715 Reset value is 0x0.</td></tr> 13716 <tr bgcolor=WHITE> 13717 <td bgcolor=WHITE align=center valign=top>04</td> 13718 <td align=left valign=top>RSVD</td> 13719 <td align=left valign=top>Reserved</td> 13720 <td align=left> 13721 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13722 <tr bgcolor=WHITE> 13723 <td bgcolor=WHITE align=center valign=top>03</td> 13724 <td align=left valign=top>RW</td> 13725 <td align=left valign=top>vcopon_sel</td> 13726 <td align=left> 13727 1= select AMS vcopon value, 0= select vcopon_int (sum or external rescal)<br> 13728 Reset value is 0x0.</td></tr> 13729 <tr bgcolor=WHITE> 13730 <td bgcolor=WHITE align=center valign=top>02</td> 13731 <td align=left valign=top>RSVD</td> 13732 <td align=left valign=top>Reserved</td> 13733 <td align=left> 13734 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13735 <tr bgcolor=WHITE> 13736 <td bgcolor=WHITE align=center valign=top>01</td> 13737 <td align=left valign=top>RW</td> 13738 <td align=left valign=top>pllpon_sel</td> 13739 <td align=left> 13740 1= select AMS pllpon value, 0= select pllpon_int (sum or external rescal)<br> 13741 Reset value is 0x0.</td></tr> 13742 <tr bgcolor=WHITE> 13743 <td bgcolor=WHITE align=center valign=top>00</td> 13744 <td align=left valign=top>RSVD</td> 13745 <td align=left valign=top>Reserved</td> 13746 <td align=left> 13747 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13748 </table><p> 13749 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13750 <hr> 13751 <b><a NAME="PLL_CAL_COM_STS_0">PLL_CAL_COM_STS_0 - PLL_CAL_STS_0</a></b><br> 13752 Address Offset = 32'h0000_d128<br> 13753 Physical Address = 32'h0000_d128<br> 13754 Reset Value = 16'h013f<br> 13755 Access = RO (16-bit only)<br> 13756 <table border=1 align=center width=100% cellpadding=0> 13757 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13758 <tr bgcolor=WHITE> 13759 <td bgcolor=WHITE align=center valign=top>15</td> 13760 <td align=left valign=top>RO</td> 13761 <td align=left valign=top>pll_fail_stky</td> 13762 <td align=left> 13763 Pll lock drop due to frequency comparison failure sticky status, clear upon read.<br> 13764 Reset value is 0x0.</td></tr> 13765 <tr bgcolor=WHITE> 13766 <td bgcolor=WHITE align=center valign=top>14:11</td> 13767 <td align=left valign=top>RO</td> 13768 <td align=left valign=top>cal_state</td> 13769 <td align=left> 13770 Calibratin State status, default to Idle state<br> 13771 Reset value is 0x0.</td></tr> 13772 <tr bgcolor=WHITE> 13773 <td bgcolor=WHITE align=center valign=top>10</td> 13774 <td align=left valign=top>RO</td> 13775 <td align=left valign=top>cal_valid</td> 13776 <td align=left> 13777 Cal valid status<br> 13778 Reset value is 0x0.</td></tr> 13779 <tr bgcolor=WHITE> 13780 <td bgcolor=WHITE align=center valign=top>09</td> 13781 <td align=left valign=top>RO</td> 13782 <td align=left valign=top>pll_lock</td> 13783 <td align=left> 13784 Pll lock status<br> 13785 Reset value is 0x0.</td></tr> 13786 <tr bgcolor=WHITE> 13787 <td bgcolor=WHITE align=center valign=top>08</td> 13788 <td align=left valign=top>RO</td> 13789 <td align=left valign=top>pll_lock_bar_stky</td> 13790 <td align=left> 13791 Pll lock drop sticky status, clear upon read.<br> 13792 Reset value is 0x1.</td></tr> 13793 <tr bgcolor=WHITE> 13794 <td bgcolor=WHITE align=center valign=top>07</td> 13795 <td align=left valign=top>RSVD</td> 13796 <td align=left valign=top>Reserved</td> 13797 <td align=left> 13798 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13799 <tr bgcolor=WHITE> 13800 <td bgcolor=WHITE align=center valign=top>06:00</td> 13801 <td align=left valign=top>RO</td> 13802 <td align=left valign=top>pll_range</td> 13803 <td align=left> 13804 Pll range value<br> 13805 Reset value is 0x3f.</td></tr> 13806 </table><p> 13807 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13808 <hr> 13809 <b><a NAME="PLL_CAL_COM_STS_1">PLL_CAL_COM_STS_1 - PLL_CAL_STS_1</a></b><br> 13810 Address Offset = 32'h0000_d129<br> 13811 Physical Address = 32'h0000_d129<br> 13812 Reset Value = 16'h0000<br> 13813 Access = RO (16-bit only)<br> 13814 <table border=1 align=center width=100% cellpadding=0> 13815 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13816 <tr bgcolor=WHITE> 13817 <td bgcolor=WHITE align=center valign=top>15</td> 13818 <td align=left valign=top>RO</td> 13819 <td align=left valign=top>lkdtref_counter_msb</td> 13820 <td align=left> 13821 LKDT refclk counter bit16, for debug only<br> 13822 Reset value is 0x0.</td></tr> 13823 <tr bgcolor=WHITE> 13824 <td bgcolor=WHITE align=center valign=top>14</td> 13825 <td align=left valign=top>RO</td> 13826 <td align=left valign=top>lkdtvco_counter_msb</td> 13827 <td align=left> 13828 LKDT vcoclk counter bit16, for debug only<br> 13829 Reset value is 0x0.</td></tr> 13830 <tr bgcolor=WHITE> 13831 <td bgcolor=WHITE align=center valign=top>13</td> 13832 <td align=left valign=top>RSVD</td> 13833 <td align=left valign=top>Reserved</td> 13834 <td align=left> 13835 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 13836 <tr bgcolor=WHITE> 13837 <td bgcolor=WHITE align=center valign=top>12:00</td> 13838 <td align=left valign=top>RO</td> 13839 <td align=left valign=top>calref_counter</td> 13840 <td align=left> 13841 Calibration refclk counter, for debug only<br> 13842 Reset value is 0x0.</td></tr> 13843 </table><p> 13844 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13845 <hr> 13846 <b><a NAME="PLL_CAL_COM_STS_2">PLL_CAL_COM_STS_2 - PLL_CAL_STS_2</a></b><br> 13847 Address Offset = 32'h0000_d12a<br> 13848 Physical Address = 32'h0000_d12a<br> 13849 Reset Value = 16'h6000<br> 13850 Access = RO (16-bit only)<br> 13851 <table border=1 align=center width=100% cellpadding=0> 13852 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13853 <tr bgcolor=WHITE> 13854 <td bgcolor=WHITE align=center valign=top>15:13</td> 13855 <td align=left valign=top>RO</td> 13856 <td align=left valign=top>band_iqbuf_mux</td> 13857 <td align=left> 13858 band_iqbuf at AFE pll_ctrl interface<br> 13859 Reset value is 0x3.</td></tr> 13860 <tr bgcolor=WHITE> 13861 <td bgcolor=WHITE align=center valign=top>12:00</td> 13862 <td align=left valign=top>RO</td> 13863 <td align=left valign=top>calvco_counter</td> 13864 <td align=left> 13865 Calibration vcoclk counter, for debug only<br> 13866 Reset value is 0x0.</td></tr> 13867 </table><p> 13868 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13869 <hr> 13870 <b><a NAME="PLL_CAL_COM_STS_3">PLL_CAL_COM_STS_3 - PLL_CAL_STS_3</a></b><br> 13871 Address Offset = 32'h0000_d12b<br> 13872 Physical Address = 32'h0000_d12b<br> 13873 Reset Value = 16'h0000<br> 13874 Access = RO (16-bit only)<br> 13875 <table border=1 align=center width=100% cellpadding=0> 13876 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13877 <tr bgcolor=WHITE> 13878 <td bgcolor=WHITE align=center valign=top>15:00</td> 13879 <td align=left valign=top>RO</td> 13880 <td align=left valign=top>lkdtref_counter</td> 13881 <td align=left> 13882 LKDT refclk counter, for debug only<br> 13883 Reset value is 0x0.</td></tr> 13884 </table><p> 13885 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13886 <hr> 13887 <b><a NAME="PLL_CAL_COM_STS_4">PLL_CAL_COM_STS_4 - PLL_CAL_STS_4</a></b><br> 13888 Address Offset = 32'h0000_d12c<br> 13889 Physical Address = 32'h0000_d12c<br> 13890 Reset Value = 16'h0000<br> 13891 Access = RO (16-bit only)<br> 13892 <table border=1 align=center width=100% cellpadding=0> 13893 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13894 <tr bgcolor=WHITE> 13895 <td bgcolor=WHITE align=center valign=top>15:00</td> 13896 <td align=left valign=top>RO</td> 13897 <td align=left valign=top>lkdtvco_counter</td> 13898 <td align=left> 13899 LKDT vcoclk counter, for debug only<br> 13900 Reset value is 0x0.</td></tr> 13901 </table><p> 13902 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13903 <hr> 13904 <b><a NAME="PLL_CAL_COM_STS_5">PLL_CAL_COM_STS_5 - PLL_CAL_STS_5</a></b><br> 13905 Address Offset = 32'h0000_d12d<br> 13906 Physical Address = 32'h0000_d12d<br> 13907 Reset Value = 16'h0000<br> 13908 Access = RO (16-bit only)<br> 13909 <table border=1 align=center width=100% cellpadding=0> 13910 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13911 <tr bgcolor=WHITE> 13912 <td bgcolor=WHITE align=center valign=top>15:14</td> 13913 <td align=left valign=top>RSVD</td> 13914 <td align=left valign=top>Reserved</td> 13915 <td align=left> 13916 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 13917 <tr bgcolor=WHITE> 13918 <td bgcolor=WHITE align=center valign=top>13:10</td> 13919 <td align=left valign=top>RO</td> 13920 <td align=left valign=top>vcobufpon_mux</td> 13921 <td align=left> 13922 vcobufpon at AFE pll_ctrl interface<br> 13923 Reset value is 0x0.</td></tr> 13924 <tr bgcolor=WHITE> 13925 <td bgcolor=WHITE align=center valign=top>09:00</td> 13926 <td align=left valign=top>RO</td> 13927 <td align=left valign=top>calstate_onehot</td> 13928 <td align=left> 13929 Calibration state machine one hot status<br> 13930 Reset value is 0x0.</td></tr> 13931 </table><p> 13932 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13933 <hr> 13934 <b><a NAME="PLL_CAL_COM_STS_6">PLL_CAL_COM_STS_6 - PLL_CAL_STS_6</a></b><br> 13935 Address Offset = 32'h0000_d12e<br> 13936 Physical Address = 32'h0000_d12e<br> 13937 Reset Value = 16'h3f00<br> 13938 Access = RO (16-bit only)<br> 13939 <table border=1 align=center width=100% cellpadding=0> 13940 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13941 <tr bgcolor=WHITE> 13942 <td bgcolor=WHITE align=center valign=top>15</td> 13943 <td align=left valign=top>RO</td> 13944 <td align=left valign=top>pll_pwrdn_or</td> 13945 <td align=left> 13946 pll_pwrdn at AFE pll_ctrl interface<br> 13947 Reset value is 0x0.</td></tr> 13948 <tr bgcolor=WHITE> 13949 <td bgcolor=WHITE align=center valign=top>14:08</td> 13950 <td align=left valign=top>RO</td> 13951 <td align=left valign=top>vco_range_mux</td> 13952 <td align=left> 13953 vco_range at AFE pll_ctrl interface<br> 13954 Reset value is 0x3f.</td></tr> 13955 <tr bgcolor=WHITE> 13956 <td bgcolor=WHITE align=center valign=top>07:04</td> 13957 <td align=left valign=top>RO</td> 13958 <td align=left valign=top>vcopon_mux</td> 13959 <td align=left> 13960 vcopon at AFE interface<br> 13961 Reset value is 0x0.</td></tr> 13962 <tr bgcolor=WHITE> 13963 <td bgcolor=WHITE align=center valign=top>03:00</td> 13964 <td align=left valign=top>RO</td> 13965 <td align=left valign=top>pllpon_mux</td> 13966 <td align=left> 13967 pllpon at AFE interface<br> 13968 Reset value is 0x0.</td></tr> 13969 </table><p> 13970 <A HREF="#PLL_CAL_COM Registers">Return to PLL_CAL_COM: common register block for all lanes Table</A><p> 13971 <hr> 13972 <H1><a NAME="TX_COM Registers">TX_COM: common register block for all lanes Registers</a></H1> 13973 <table border=1 align=center width=100% cellpadding=0> 13974 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 13975 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 13976 <tr> 13977 <td align=center>0xD130</td><td><A HREF="#TX_COM_TXCOM_CONTROL0_REGISTER">TX_COM_TXCOM_CONTROL0_REGISTER</A><br>TX common control 0 register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">txcom_cl72_max_wait_timer_period</div> </td> <td align=center>16'h01f4</td></tr> 13978 <tr> 13979 <td align=center>0xD131</td><td><A HREF="#TX_COM_TXCOM_CONTROL1_REGISTER">TX_COM_TXCOM_CONTROL1_REGISTER</A><br>TX common control 1 register</td><td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="9"><div class="HT">txcom_cl72_wait_cntr_limit</div> </td> <td align=center>16'h00c8</td></tr> 13980 </table><p> 13981 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 13982 <hr> 13983 <b><a NAME="TX_COM_TXCOM_CONTROL0_REGISTER">TX_COM_TXCOM_CONTROL0_REGISTER - TX common control 0 register</a></b><br> 13984 Address Offset = 32'h0000_d130<br> 13985 Physical Address = 32'h0000_d130<br> 13986 Reset Value = 16'h01f4<br> 13987 Access = RW (16-bit only)<br> 13988 <table border=1 align=center width=100% cellpadding=0> 13989 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 13990 <tr bgcolor=WHITE> 13991 <td bgcolor=WHITE align=center valign=top>15:00</td> 13992 <td align=left valign=top>RW</td> 13993 <td align=left valign=top>txcom_cl72_max_wait_timer_period</td> 13994 <td align=left> 13995 Maximum Training Time in ms<br> 13996 Period/range is 500 ms <br> 13997 Reset value is 0x1f4.</td></tr> 13998 </table><p> 13999 <A HREF="#TX_COM Registers">Return to TX_COM: common register block for all lanes Table</A><p> 14000 <hr> 14001 <b><a NAME="TX_COM_TXCOM_CONTROL1_REGISTER">TX_COM_TXCOM_CONTROL1_REGISTER - TX common control 1 register</a></b><br> 14002 Address Offset = 32'h0000_d131<br> 14003 Physical Address = 32'h0000_d131<br> 14004 Reset Value = 16'h00c8<br> 14005 Access = RW (16-bit only)<br> 14006 <table border=1 align=center width=100% cellpadding=0> 14007 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14008 <tr bgcolor=WHITE> 14009 <td bgcolor=WHITE align=center valign=top>15:09</td> 14010 <td align=left valign=top>RSVD</td> 14011 <td align=left valign=top>Reserved</td> 14012 <td align=left> 14013 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14014 <tr bgcolor=WHITE> 14015 <td bgcolor=WHITE align=center valign=top>08:00</td> 14016 <td align=left valign=top>RW</td> 14017 <td align=left valign=top>txcom_cl72_wait_cntr_limit</td> 14018 <td align=left> 14019 Period/range is 100-300 frames <br> 14020 Period to keep transiming frames after the local device has completed training<br> 14021 The units are training pages.<br> 14022 Reset value is 0xc8.</td></tr> 14023 </table><p> 14024 <A HREF="#TX_COM Registers">Return to TX_COM: common register block for all lanes Table</A><p> 14025 <hr> 14026 <H1><a NAME="DSC_F Registers">DSC_F: per lane register block [One Copy Per Lane] Registers</a></H1> 14027 <table border=1 align=center width=100% cellpadding=0> 14028 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 14029 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 14030 <tr> 14031 <td align=center>0xD141</td><td><A HREF="#DSC_F_DSC_F_DATA_ODD_OFFSET">DSC_F_DSC_F_DATA_ODD_OFFSET</A><br>dsc_f_data_odd_offset</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">data_offset_odd_bin</div> </td> <td align=center>16'h0000</td></tr> 14032 <tr> 14033 <td align=center>0xD142</td><td><A HREF="#DSC_F_DSC_F_DATA_EVEN_OFFSET">DSC_F_DSC_F_DATA_EVEN_OFFSET</A><br>dsc_f_data_even_offset</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">data_offset_evn_bin</div> </td> <td align=center>16'h0000</td></tr> 14034 <tr> 14035 <td align=center>0xD143</td><td><A HREF="#DSC_F_DSC_F_P1_ODD_OFFSET">DSC_F_DSC_F_P1_ODD_OFFSET</A><br>dsc_f_p1_odd_offset</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">p1_offset_odd_bin</div> </td> <td align=center>16'h0000</td></tr> 14036 <tr> 14037 <td align=center>0xD144</td><td><A HREF="#DSC_F_DSC_F_P1_EVEN_OFFSET">DSC_F_DSC_F_P1_EVEN_OFFSET</A><br>dsc_f_p1_even_offset</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">p1_offset_evn_bin</div> </td> <td align=center>16'h0000</td></tr> 14038 <tr> 14039 <td align=center>0xD145</td><td><A HREF="#DSC_F_DSC_F_M1_ODD_OFFSET">DSC_F_DSC_F_M1_ODD_OFFSET</A><br>dsc_f_m1_odd_offset</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">m1_offset_odd_bin</div> </td> <td align=center>16'h0000</td></tr> 14040 <tr> 14041 <td align=center>0xD146</td><td><A HREF="#DSC_F_DSC_F_M1_EVEN_OFFSET">DSC_F_DSC_F_M1_EVEN_OFFSET</A><br>dsc_f_m1_even_offset</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">m1_offset_evn_bin</div> </td> <td align=center>16'h0000</td></tr> 14042 <tr> 14043 <td align=center>0xD147</td><td><A HREF="#DSC_F_DSC_F_DC_OFFSET">DSC_F_DSC_F_DC_OFFSET</A><br>dsc_f_dc_offset</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">dc_offset_bin</div> </td> <td align=center>16'h0000</td></tr> 14044 </table><p> 14045 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 14046 <hr> 14047 <b><a NAME="DSC_F_DSC_F_DATA_ODD_OFFSET">DSC_F_DSC_F_DATA_ODD_OFFSET - dsc_f_data_odd_offset</a></b><br> 14048 Address Offset = 32'h0000_d141<br> 14049 Physical Address = 32'h0000_d141<br> 14050 Reset Value = 16'h0000<br> 14051 Access = RO (16-bit only)<br> 14052 <table border=1 align=center width=100% cellpadding=0> 14053 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14054 <tr bgcolor=WHITE> 14055 <td bgcolor=WHITE align=center valign=top>15:06</td> 14056 <td align=left valign=top>RSVD</td> 14057 <td align=left valign=top>Reserved</td> 14058 <td align=left> 14059 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14060 <tr bgcolor=WHITE> 14061 <td bgcolor=WHITE align=center valign=top>05:00</td> 14062 <td align=left valign=top>RO</td> 14063 <td align=left valign=top>data_offset_odd_bin</td> 14064 <td align=left> 14065 Status Reg: Offset for the odd data slicer <br> 14066 Reset value is 0x0.</td></tr> 14067 </table><p> 14068 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14069 <hr> 14070 <b><a NAME="DSC_F_DSC_F_DATA_EVEN_OFFSET">DSC_F_DSC_F_DATA_EVEN_OFFSET - dsc_f_data_even_offset</a></b><br> 14071 Address Offset = 32'h0000_d142<br> 14072 Physical Address = 32'h0000_d142<br> 14073 Reset Value = 16'h0000<br> 14074 Access = RO (16-bit only)<br> 14075 <table border=1 align=center width=100% cellpadding=0> 14076 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14077 <tr bgcolor=WHITE> 14078 <td bgcolor=WHITE align=center valign=top>15:06</td> 14079 <td align=left valign=top>RSVD</td> 14080 <td align=left valign=top>Reserved</td> 14081 <td align=left> 14082 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14083 <tr bgcolor=WHITE> 14084 <td bgcolor=WHITE align=center valign=top>05:00</td> 14085 <td align=left valign=top>RO</td> 14086 <td align=left valign=top>data_offset_evn_bin</td> 14087 <td align=left> 14088 Status Reg: Offset for the even data slicer   <br> 14089 Reset value is 0x0.</td></tr> 14090 </table><p> 14091 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14092 <hr> 14093 <b><a NAME="DSC_F_DSC_F_P1_ODD_OFFSET">DSC_F_DSC_F_P1_ODD_OFFSET - dsc_f_p1_odd_offset</a></b><br> 14094 Address Offset = 32'h0000_d143<br> 14095 Physical Address = 32'h0000_d143<br> 14096 Reset Value = 16'h0000<br> 14097 Access = RO (16-bit only)<br> 14098 <table border=1 align=center width=100% cellpadding=0> 14099 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14100 <tr bgcolor=WHITE> 14101 <td bgcolor=WHITE align=center valign=top>15:06</td> 14102 <td align=left valign=top>RSVD</td> 14103 <td align=left valign=top>Reserved</td> 14104 <td align=left> 14105 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14106 <tr bgcolor=WHITE> 14107 <td bgcolor=WHITE align=center valign=top>05:00</td> 14108 <td align=left valign=top>RO</td> 14109 <td align=left valign=top>p1_offset_odd_bin</td> 14110 <td align=left> 14111 Status Reg: Offset for the odd p1 slicer   <br> 14112 Reset value is 0x0.</td></tr> 14113 </table><p> 14114 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14115 <hr> 14116 <b><a NAME="DSC_F_DSC_F_P1_EVEN_OFFSET">DSC_F_DSC_F_P1_EVEN_OFFSET - dsc_f_p1_even_offset</a></b><br> 14117 Address Offset = 32'h0000_d144<br> 14118 Physical Address = 32'h0000_d144<br> 14119 Reset Value = 16'h0000<br> 14120 Access = RO (16-bit only)<br> 14121 <table border=1 align=center width=100% cellpadding=0> 14122 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14123 <tr bgcolor=WHITE> 14124 <td bgcolor=WHITE align=center valign=top>15:06</td> 14125 <td align=left valign=top>RSVD</td> 14126 <td align=left valign=top>Reserved</td> 14127 <td align=left> 14128 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14129 <tr bgcolor=WHITE> 14130 <td bgcolor=WHITE align=center valign=top>05:00</td> 14131 <td align=left valign=top>RO</td> 14132 <td align=left valign=top>p1_offset_evn_bin</td> 14133 <td align=left> 14134 Status Reg: Offset for the even p1 slicer   <br> 14135 Reset value is 0x0.</td></tr> 14136 </table><p> 14137 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14138 <hr> 14139 <b><a NAME="DSC_F_DSC_F_M1_ODD_OFFSET">DSC_F_DSC_F_M1_ODD_OFFSET - dsc_f_m1_odd_offset</a></b><br> 14140 Address Offset = 32'h0000_d145<br> 14141 Physical Address = 32'h0000_d145<br> 14142 Reset Value = 16'h0000<br> 14143 Access = RO (16-bit only)<br> 14144 <table border=1 align=center width=100% cellpadding=0> 14145 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14146 <tr bgcolor=WHITE> 14147 <td bgcolor=WHITE align=center valign=top>15:06</td> 14148 <td align=left valign=top>RSVD</td> 14149 <td align=left valign=top>Reserved</td> 14150 <td align=left> 14151 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14152 <tr bgcolor=WHITE> 14153 <td bgcolor=WHITE align=center valign=top>05:00</td> 14154 <td align=left valign=top>RO</td> 14155 <td align=left valign=top>m1_offset_odd_bin</td> 14156 <td align=left> 14157 Status Reg: Offset for the odd m1 slicer   <br> 14158 Reset value is 0x0.</td></tr> 14159 </table><p> 14160 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14161 <hr> 14162 <b><a NAME="DSC_F_DSC_F_M1_EVEN_OFFSET">DSC_F_DSC_F_M1_EVEN_OFFSET - dsc_f_m1_even_offset</a></b><br> 14163 Address Offset = 32'h0000_d146<br> 14164 Physical Address = 32'h0000_d146<br> 14165 Reset Value = 16'h0000<br> 14166 Access = RO (16-bit only)<br> 14167 <table border=1 align=center width=100% cellpadding=0> 14168 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14169 <tr bgcolor=WHITE> 14170 <td bgcolor=WHITE align=center valign=top>15:06</td> 14171 <td align=left valign=top>RSVD</td> 14172 <td align=left valign=top>Reserved</td> 14173 <td align=left> 14174 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14175 <tr bgcolor=WHITE> 14176 <td bgcolor=WHITE align=center valign=top>05:00</td> 14177 <td align=left valign=top>RO</td> 14178 <td align=left valign=top>m1_offset_evn_bin</td> 14179 <td align=left> 14180 Status Reg: Offset for the even m1 slicer   <br> 14181 Reset value is 0x0.</td></tr> 14182 </table><p> 14183 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14184 <hr> 14185 <b><a NAME="DSC_F_DSC_F_DC_OFFSET">DSC_F_DSC_F_DC_OFFSET - dsc_f_dc_offset</a></b><br> 14186 Address Offset = 32'h0000_d147<br> 14187 Physical Address = 32'h0000_d147<br> 14188 Reset Value = 16'h0000<br> 14189 Access = RO (16-bit only)<br> 14190 <table border=1 align=center width=100% cellpadding=0> 14191 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14192 <tr bgcolor=WHITE> 14193 <td bgcolor=WHITE align=center valign=top>15:07</td> 14194 <td align=left valign=top>RSVD</td> 14195 <td align=left valign=top>Reserved</td> 14196 <td align=left> 14197 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14198 <tr bgcolor=WHITE> 14199 <td bgcolor=WHITE align=center valign=top>06:00</td> 14200 <td align=left valign=top>RO</td> 14201 <td align=left valign=top>dc_offset_bin</td> 14202 <td align=left> 14203   Status Reg: DC Offset provided at the Rx Input<br> 14204 Reset value is 0x0.</td></tr> 14205 </table><p> 14206 <A HREF="#DSC_F Registers">Return to DSC_F: per lane register block [One Copy Per Lane] Table</A><p> 14207 <hr> 14208 <H1><a NAME="DIG_COM_B Registers">DIG_COM_B: common register block for all lanes Registers</a></H1> 14209 <table border=1 align=center width=100% cellpadding=0> 14210 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 14211 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 14212 <tr> 14213 <td align=center>0xD150</td><td><A HREF="#DIG_COM_B_LANE_ADDR_0">DIG_COM_B_LANE_ADDR_0</A><br>LANE_ADDR_0</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">tx_lane_addr_0</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rx_lane_addr_0</div> </td> <td align=center>16'h0000</td></tr> 14214 <tr> 14215 <td align=center>0xD151</td><td><A HREF="#DIG_COM_B_LANE_ADDR_1">DIG_COM_B_LANE_ADDR_1</A><br>LANE_ADDR_1</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">tx_lane_addr_1</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rx_lane_addr_1</div> </td> <td align=center>16'h0101</td></tr> 14216 <tr> 14217 <td align=center>0xD152</td><td><A HREF="#DIG_COM_B_LANE_ADDR_2">DIG_COM_B_LANE_ADDR_2</A><br>LANE_ADDR_2</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">tx_lane_addr_2</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rx_lane_addr_2</div> </td> <td align=center>16'h0202</td></tr> 14218 <tr> 14219 <td align=center>0xD153</td><td><A HREF="#DIG_COM_B_LANE_ADDR_3">DIG_COM_B_LANE_ADDR_3</A><br>LANE_ADDR_3</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">tx_lane_addr_3</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">rx_lane_addr_3</div> </td> <td align=center>16'h0303</td></tr> 14220 </table><p> 14221 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 14222 <hr> 14223 <b><a NAME="DIG_COM_B_LANE_ADDR_0">DIG_COM_B_LANE_ADDR_0 - LANE_ADDR_0</a></b><br> 14224 Address Offset = 32'h0000_d150<br> 14225 Physical Address = 32'h0000_d150<br> 14226 Reset Value = 16'h0000<br> 14227 Access = RW (16-bit only)<br> 14228 <table border=1 align=center width=100% cellpadding=0> 14229 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14230 <tr bgcolor=WHITE> 14231 <td bgcolor=WHITE align=center valign=top>15:13</td> 14232 <td align=left valign=top>RSVD</td> 14233 <td align=left valign=top>Reserved</td> 14234 <td align=left> 14235 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14236 <tr bgcolor=WHITE> 14237 <td bgcolor=WHITE align=center valign=top>12:08</td> 14238 <td align=left valign=top>RW</td> 14239 <td align=left valign=top>tx_lane_addr_0</td> 14240 <td align=left> 14241 Determines the logical address associated with the PMD TX lane with physical index  "_0" at the PCS interface. <br> 14242 tx_lane_addr_0 is the logical address of the TX lane with pins at the PCS interface labeled "_0". <br> 14243 Reset value is 0x0.</td></tr> 14244 <tr bgcolor=WHITE> 14245 <td bgcolor=WHITE align=center valign=top>07:05</td> 14246 <td align=left valign=top>RSVD</td> 14247 <td align=left valign=top>Reserved</td> 14248 <td align=left> 14249 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14250 <tr bgcolor=WHITE> 14251 <td bgcolor=WHITE align=center valign=top>04:00</td> 14252 <td align=left valign=top>RW</td> 14253 <td align=left valign=top>rx_lane_addr_0</td> 14254 <td align=left> 14255 Determines the logical address associated with the PMD RX lane with physical index  "_0" at the PCS interface. <br> 14256 rx_lane_addr_0 is the logical address of the lane with pins at the PCS interface labeled "_0". <br> 14257 Reset value is 0x0.</td></tr> 14258 </table><p> 14259 <A HREF="#DIG_COM_B Registers">Return to DIG_COM_B: common register block for all lanes Table</A><p> 14260 <hr> 14261 <b><a NAME="DIG_COM_B_LANE_ADDR_1">DIG_COM_B_LANE_ADDR_1 - LANE_ADDR_1</a></b><br> 14262 Address Offset = 32'h0000_d151<br> 14263 Physical Address = 32'h0000_d151<br> 14264 Reset Value = 16'h0101<br> 14265 Access = RW (16-bit only)<br> 14266 <table border=1 align=center width=100% cellpadding=0> 14267 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14268 <tr bgcolor=WHITE> 14269 <td bgcolor=WHITE align=center valign=top>15:13</td> 14270 <td align=left valign=top>RSVD</td> 14271 <td align=left valign=top>Reserved</td> 14272 <td align=left> 14273 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14274 <tr bgcolor=WHITE> 14275 <td bgcolor=WHITE align=center valign=top>12:08</td> 14276 <td align=left valign=top>RW</td> 14277 <td align=left valign=top>tx_lane_addr_1</td> 14278 <td align=left> 14279 Determines the logical address associated with the PMD TX lane with physical index  "_1" at the PCS interface. <br> 14280 tx_lane_addr_1 is the logical address of the TX lane with pins at the PCS interface labeled "_1". <br> 14281 Reset value is 0x1.</td></tr> 14282 <tr bgcolor=WHITE> 14283 <td bgcolor=WHITE align=center valign=top>07:05</td> 14284 <td align=left valign=top>RSVD</td> 14285 <td align=left valign=top>Reserved</td> 14286 <td align=left> 14287 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14288 <tr bgcolor=WHITE> 14289 <td bgcolor=WHITE align=center valign=top>04:00</td> 14290 <td align=left valign=top>RW</td> 14291 <td align=left valign=top>rx_lane_addr_1</td> 14292 <td align=left> 14293 Determines the logical address associated with the PMD RX lane with physical index  "_1" at the PCS interface. <br> 14294 rx_lane_addr_1 is the logical address of the lane with pins at the PCS interface labeled "_1". <br> 14295 Reset value is 0x1.</td></tr> 14296 </table><p> 14297 <A HREF="#DIG_COM_B Registers">Return to DIG_COM_B: common register block for all lanes Table</A><p> 14298 <hr> 14299 <b><a NAME="DIG_COM_B_LANE_ADDR_2">DIG_COM_B_LANE_ADDR_2 - LANE_ADDR_2</a></b><br> 14300 Address Offset = 32'h0000_d152<br> 14301 Physical Address = 32'h0000_d152<br> 14302 Reset Value = 16'h0202<br> 14303 Access = RW (16-bit only)<br> 14304 <table border=1 align=center width=100% cellpadding=0> 14305 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14306 <tr bgcolor=WHITE> 14307 <td bgcolor=WHITE align=center valign=top>15:13</td> 14308 <td align=left valign=top>RSVD</td> 14309 <td align=left valign=top>Reserved</td> 14310 <td align=left> 14311 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14312 <tr bgcolor=WHITE> 14313 <td bgcolor=WHITE align=center valign=top>12:08</td> 14314 <td align=left valign=top>RW</td> 14315 <td align=left valign=top>tx_lane_addr_2</td> 14316 <td align=left> 14317 Determines the logical address associated with the PMD TX lane with physical index  "_2" at the PCS interface. <br> 14318 tx_lane_addr_2 is the logical address of the TX lane with pins at the PCS interface labeled "_2". <br> 14319 Reset value is 0x2.</td></tr> 14320 <tr bgcolor=WHITE> 14321 <td bgcolor=WHITE align=center valign=top>07:05</td> 14322 <td align=left valign=top>RSVD</td> 14323 <td align=left valign=top>Reserved</td> 14324 <td align=left> 14325 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14326 <tr bgcolor=WHITE> 14327 <td bgcolor=WHITE align=center valign=top>04:00</td> 14328 <td align=left valign=top>RW</td> 14329 <td align=left valign=top>rx_lane_addr_2</td> 14330 <td align=left> 14331 Determines the logical address associated with the PMD RX lane with physical index  "_2" at the PCS interface. <br> 14332 rx_lane_addr_2 is the logical address of the lane with pins at the PCS interface labeled "_2". <br> 14333 Reset value is 0x2.</td></tr> 14334 </table><p> 14335 <A HREF="#DIG_COM_B Registers">Return to DIG_COM_B: common register block for all lanes Table</A><p> 14336 <hr> 14337 <b><a NAME="DIG_COM_B_LANE_ADDR_3">DIG_COM_B_LANE_ADDR_3 - LANE_ADDR_3</a></b><br> 14338 Address Offset = 32'h0000_d153<br> 14339 Physical Address = 32'h0000_d153<br> 14340 Reset Value = 16'h0303<br> 14341 Access = RW (16-bit only)<br> 14342 <table border=1 align=center width=100% cellpadding=0> 14343 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14344 <tr bgcolor=WHITE> 14345 <td bgcolor=WHITE align=center valign=top>15:13</td> 14346 <td align=left valign=top>RSVD</td> 14347 <td align=left valign=top>Reserved</td> 14348 <td align=left> 14349 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14350 <tr bgcolor=WHITE> 14351 <td bgcolor=WHITE align=center valign=top>12:08</td> 14352 <td align=left valign=top>RW</td> 14353 <td align=left valign=top>tx_lane_addr_3</td> 14354 <td align=left> 14355 Determines the logical address associated with the PMD TX lane with physical index  "_3" at the PCS interface. <br> 14356 tx_lane_addr_3 is the logical address of the TX lane with pins at the PCS interface labeled "_3". <br> 14357 Reset value is 0x3.</td></tr> 14358 <tr bgcolor=WHITE> 14359 <td bgcolor=WHITE align=center valign=top>07:05</td> 14360 <td align=left valign=top>RSVD</td> 14361 <td align=left valign=top>Reserved</td> 14362 <td align=left> 14363 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14364 <tr bgcolor=WHITE> 14365 <td bgcolor=WHITE align=center valign=top>04:00</td> 14366 <td align=left valign=top>RW</td> 14367 <td align=left valign=top>rx_lane_addr_3</td> 14368 <td align=left> 14369 Determines the logical address associated with the PMD RX lane with physical index  "_3" at the PCS interface. <br> 14370 rx_lane_addr_3 is the logical address of the lane with pins at the PCS interface labeled "_3". <br> 14371 Reset value is 0x3.</td></tr> 14372 </table><p> 14373 <A HREF="#DIG_COM_B Registers">Return to DIG_COM_B: common register block for all lanes Table</A><p> 14374 <hr> 14375 <H1><a NAME="RX_CKRST_CTRL Registers">RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Registers</a></H1> 14376 <table border=1 align=center width=100% cellpadding=0> 14377 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 14378 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 14379 <tr> 14380 <td align=center>0xD161</td><td><A HREF="#RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL">RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL</A><br>RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_sigdet_pwrdn</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_rx_s_pwrdn</div> </td> <td align=center>16'h0000</td></tr> 14381 <tr> 14382 <td align=center>0xD162</td><td><A HREF="#RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL">RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL</A><br>RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_rx_reset_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_rx_reset_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_rx_pwrdn_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_rx_pwrdn_frc</div> </td> <td align=center>16'h0000</td></tr> 14383 <tr> 14384 <td align=center>0xD163</td><td><A HREF="#RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</A><br>RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_rx_h_pwrdn_pkill</div> </td> <td align=center>16'h0000</td></tr> 14385 <tr> 14386 <td align=center>0xD164</td><td><A HREF="#RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL">RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL</A><br>RX_LANE_DEBUG_RESET_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sigdet_dp_rstb_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_rx_dp_s_rstb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_rx_s_rstb</div> </td> <td align=center>16'h0003</td></tr> 14387 <tr> 14388 <td align=center>0xD167</td><td><A HREF="#RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL">RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL</A><br>RX_CLOCK_N_RESET_DEBUG_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_rx_clk_vld_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_rx_clk_vld_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_rx_s_comclk_frc_on</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_rx_s_comclk_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_rx_s_clkgate_frc_on</div> </td> <td align=center>16'h0000</td></tr> 14389 <tr> 14390 <td align=center>0xD168</td><td><A HREF="#RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS">RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS</A><br>RX_PMD_LANE_MODE_STATUS</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">pmd_lane_mode</div> </td> <td align=center>16'h0000</td></tr> 14391 <tr> 14392 <td align=center>0xD16C</td><td><A HREF="#RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</A><br>RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_rx_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_rx_pwrdn</div> </td> <td align=center>16'h0002</td></tr> 14393 </table><p> 14394 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 14395 <hr> 14396 <b><a NAME="RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL">RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL - RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL</a></b><br> 14397 Address Offset = 32'h0000_d161<br> 14398 Physical Address = 32'h0000_d161<br> 14399 Reset Value = 16'h0000<br> 14400 Access = RW (16-bit only)<br> 14401 <table border=1 align=center width=100% cellpadding=0> 14402 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14403 <tr bgcolor=WHITE> 14404 <td bgcolor=WHITE align=center valign=top>15:02</td> 14405 <td align=left valign=top>RSVD</td> 14406 <td align=left valign=top>Reserved</td> 14407 <td align=left> 14408 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14409 <tr bgcolor=WHITE> 14410 <td bgcolor=WHITE align=center valign=top>01</td> 14411 <td align=left valign=top>RW</td> 14412 <td align=left valign=top>afe_sigdet_pwrdn</td> 14413 <td align=left> 14414 Power Down for Signal Detect. 1=power down <br> 14415 Reset value is 0x0.</td></tr> 14416 <tr bgcolor=WHITE> 14417 <td bgcolor=WHITE align=center valign=top>00</td> 14418 <td align=left valign=top>RW</td> 14419 <td align=left valign=top>ln_rx_s_pwrdn</td> 14420 <td align=left> 14421 Active High Power Down control for RX Lane. <br> 14422 If asserted by writing to 1'b1 will power down the RX Lane. <br> 14423 Reset value is 0x0.</td></tr> 14424 </table><p> 14425 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14426 <hr> 14427 <b><a NAME="RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL">RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL - RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL</a></b><br> 14428 Address Offset = 32'h0000_d162<br> 14429 Physical Address = 32'h0000_d162<br> 14430 Reset Value = 16'h0000<br> 14431 Access = RW (16-bit only)<br> 14432 <table border=1 align=center width=100% cellpadding=0> 14433 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14434 <tr bgcolor=WHITE> 14435 <td bgcolor=WHITE align=center valign=top>15:04</td> 14436 <td align=left valign=top>RSVD</td> 14437 <td align=left valign=top>Reserved</td> 14438 <td align=left> 14439 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14440 <tr bgcolor=WHITE> 14441 <td bgcolor=WHITE align=center valign=top>03</td> 14442 <td align=left valign=top>RW</td> 14443 <td align=left valign=top>afe_rx_reset_frc_val</td> 14444 <td align=left> 14445 AFE RX Lane reset force value. <br> 14446 Reset value is 0x0.</td></tr> 14447 <tr bgcolor=WHITE> 14448 <td bgcolor=WHITE align=center valign=top>02</td> 14449 <td align=left valign=top>RW</td> 14450 <td align=left valign=top>afe_rx_reset_frc</td> 14451 <td align=left> 14452 AFE RX Lane reset force. <br> 14453 Reset value is 0x0.</td></tr> 14454 <tr bgcolor=WHITE> 14455 <td bgcolor=WHITE align=center valign=top>01</td> 14456 <td align=left valign=top>RW</td> 14457 <td align=left valign=top>afe_rx_pwrdn_frc_val</td> 14458 <td align=left> 14459 AFE RX Lane powerdown force value. <br> 14460 Reset value is 0x0.</td></tr> 14461 <tr bgcolor=WHITE> 14462 <td bgcolor=WHITE align=center valign=top>00</td> 14463 <td align=left valign=top>RW</td> 14464 <td align=left valign=top>afe_rx_pwrdn_frc</td> 14465 <td align=left> 14466 AFE RX Lane powerdown force. <br> 14467 Reset value is 0x0.</td></tr> 14468 </table><p> 14469 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14470 <hr> 14471 <b><a NAME="RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL - RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</a></b><br> 14472 Address Offset = 32'h0000_d163<br> 14473 Physical Address = 32'h0000_d163<br> 14474 Reset Value = 16'h0000<br> 14475 Access = RW (16-bit only)<br> 14476 <table border=1 align=center width=100% cellpadding=0> 14477 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14478 <tr bgcolor=WHITE> 14479 <td bgcolor=WHITE align=center valign=top>15:01</td> 14480 <td align=left valign=top>RSVD</td> 14481 <td align=left valign=top>Reserved</td> 14482 <td align=left> 14483 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14484 <tr bgcolor=WHITE> 14485 <td bgcolor=WHITE align=center valign=top>00</td> 14486 <td align=left valign=top>RW</td> 14487 <td align=left valign=top>pmd_ln_rx_h_pwrdn_pkill</td> 14488 <td align=left> 14489 1'b1 will disable the pmd_ln_rx_h_pwrdn input pin. <br> 14490 Reset value is 0x0.</td></tr> 14491 </table><p> 14492 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14493 <hr> 14494 <b><a NAME="RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL">RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL - RX_LANE_DEBUG_RESET_CONTROL</a></b><br> 14495 Address Offset = 32'h0000_d164<br> 14496 Physical Address = 32'h0000_d164<br> 14497 Reset Value = 16'h0003<br> 14498 Access = RW (16-bit only)<br> 14499 <table border=1 align=center width=100% cellpadding=0> 14500 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14501 <tr bgcolor=WHITE> 14502 <td bgcolor=WHITE align=center valign=top>15:03</td> 14503 <td align=left valign=top>RSVD</td> 14504 <td align=left valign=top>Reserved</td> 14505 <td align=left> 14506 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14507 <tr bgcolor=WHITE> 14508 <td bgcolor=WHITE align=center valign=top>02</td> 14509 <td align=left valign=top>RW</td> 14510 <td align=left valign=top>sigdet_dp_rstb_en</td> 14511 <td align=left> 14512 If asserted by writing to 1'b1 then lane datapath reset will also reset the sigdet filetr logic alomg with lane register reset. <br> 14513 Reset value is 0x0.</td></tr> 14514 <tr bgcolor=WHITE> 14515 <td bgcolor=WHITE align=center valign=top>01</td> 14516 <td align=left valign=top>RW</td> 14517 <td align=left valign=top>ln_rx_dp_s_rstb</td> 14518 <td align=left> 14519 Active Low Lane Soft Reset for RX datapath. If asserted by writing to 1'b0 will reset the RX datapath for a lane. <br> 14520 This is a debug only register and it is not handled by FW-HW handshake <br> 14521 Reset value is 0x1.</td></tr> 14522 <tr bgcolor=WHITE> 14523 <td bgcolor=WHITE align=center valign=top>00</td> 14524 <td align=left valign=top>RW</td> 14525 <td align=left valign=top>ln_rx_s_rstb</td> 14526 <td align=left> 14527 Active Low Lane Soft Reset for RX datapath and registers. If asserted by writing to 1'b0 will reset the RX registers and datapath for a lane. <br> 14528 This is a debug only register and it is not handled by FW-HW handshake <br> 14529 Reset value is 0x1.</td></tr> 14530 </table><p> 14531 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14532 <hr> 14533 <b><a NAME="RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL">RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL - RX_CLOCK_N_RESET_DEBUG_CONTROL</a></b><br> 14534 Address Offset = 32'h0000_d167<br> 14535 Physical Address = 32'h0000_d167<br> 14536 Reset Value = 16'h0000<br> 14537 Access = RW (16-bit only)<br> 14538 <table border=1 align=center width=100% cellpadding=0> 14539 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14540 <tr bgcolor=WHITE> 14541 <td bgcolor=WHITE align=center valign=top>15:05</td> 14542 <td align=left valign=top>RSVD</td> 14543 <td align=left valign=top>Reserved</td> 14544 <td align=left> 14545 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14546 <tr bgcolor=WHITE> 14547 <td bgcolor=WHITE align=center valign=top>04</td> 14548 <td align=left valign=top>RW</td> 14549 <td align=left valign=top>pmd_rx_clk_vld_frc_val</td> 14550 <td align=left> 14551 pmd_rx_clk_vld core output pin force value. <br> 14552 Reset value is 0x0.</td></tr> 14553 <tr bgcolor=WHITE> 14554 <td bgcolor=WHITE align=center valign=top>03</td> 14555 <td align=left valign=top>RW</td> 14556 <td align=left valign=top>pmd_rx_clk_vld_frc</td> 14557 <td align=left> 14558 pmd_rx_clk_vld core output pin force. <br> 14559 Reset value is 0x0.</td></tr> 14560 <tr bgcolor=WHITE> 14561 <td bgcolor=WHITE align=center valign=top>02</td> 14562 <td align=left valign=top>RW</td> 14563 <td align=left valign=top>ln_rx_s_comclk_frc_on</td> 14564 <td align=left> 14565 Mux control for selection of comclk for RX Lane clocks by force. <br> 14566 If asserted by writing to 1'b1 will select the comclk for the RX lane clocks. This is a debug bit and should be used only for recovery from a dead AFE 14567 lane clock. Use of this bit with an active AFE clock can cause clock glitches.<br> 14568 " It is recommended for user to force pmd_rx_clk_vld to 1'b0 while ln_rx_s_comclk_frc_on is asserted to 1'b1<br> 14569 by using pmd_rx_clk_vld_frc/frc_val registers. <br> 14570 Reset value is 0x0.</td></tr> 14571 <tr bgcolor=WHITE> 14572 <td bgcolor=WHITE align=center valign=top>01</td> 14573 <td align=left valign=top>RW</td> 14574 <td align=left valign=top>ln_rx_s_comclk_sel</td> 14575 <td align=left> 14576 Mux control for selection of comclk for RX Lane clocks. <br> 14577 If asserted by writing to 1'b1 will select the comclk for the lane clocks. <br> 14578 " It is recommended for user to force pmd_rx_clk_vld to 1'b0 while ln_rx_s_comclk_sel is asserted to 1'b1<br> 14579 by using pmd_rx_clk_vld_frc/frc_val registers. <br> 14580 Reset value is 0x0.</td></tr> 14581 <tr bgcolor=WHITE> 14582 <td bgcolor=WHITE align=center valign=top>00</td> 14583 <td align=left valign=top>RW</td> 14584 <td align=left valign=top>ln_rx_s_clkgate_frc_on</td> 14585 <td align=left> 14586 RX Active High Lane clock gator enable. If 1'1b1 then rx lane clock will be gated off. It does not affect the rclk going <br> 14587 to RMIC block so rx lane based registers can still be readable but not writable. <br> 14588 " It is recommended for user to force pmd_rx_clk_vld to 1'b0 while rx_s_clkgate_frc_on is asserted to 1'b1<br> 14589 by using pmd_rx_clk_vld_frc/frc_val registers. <br> 14590 Reset value is 0x0.</td></tr> 14591 </table><p> 14592 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14593 <hr> 14594 <b><a NAME="RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS">RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS - RX_PMD_LANE_MODE_STATUS</a></b><br> 14595 Address Offset = 32'h0000_d168<br> 14596 Physical Address = 32'h0000_d168<br> 14597 Reset Value = 16'h0000<br> 14598 Access = RO (16-bit only)<br> 14599 <table border=1 align=center width=100% cellpadding=0> 14600 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14601 <tr bgcolor=WHITE> 14602 <td bgcolor=WHITE align=center valign=top>15:00</td> 14603 <td align=left valign=top>RO</td> 14604 <td align=left valign=top>pmd_lane_mode</td> 14605 <td align=left> 14606 This indicates the status of the core input pin pmd_lane_mode.  <br> 14607 This is driven from PCS and used for communication between PCS and PMD Micro code. <br> 14608 Reset value is 0x0.</td></tr> 14609 </table><p> 14610 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14611 <hr> 14612 <b><a NAME="RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS - RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</a></b><br> 14613 Address Offset = 32'h0000_d16c<br> 14614 Physical Address = 32'h0000_d16c<br> 14615 Reset Value = 16'h0002<br> 14616 Access = RO (16-bit only)<br> 14617 <table border=1 align=center width=100% cellpadding=0> 14618 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14619 <tr bgcolor=WHITE> 14620 <td bgcolor=WHITE align=center valign=top>15:02</td> 14621 <td align=left valign=top>RSVD</td> 14622 <td align=left valign=top>Reserved</td> 14623 <td align=left> 14624 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14625 <tr bgcolor=WHITE> 14626 <td bgcolor=WHITE align=center valign=top>01</td> 14627 <td align=left valign=top>RO</td> 14628 <td align=left valign=top>afe_rx_reset</td> 14629 <td align=left> 14630 Indicates the status of the afe_rx_reset signal to the AFE after frc/frc_val mux. <br> 14631 Reset value is 0x1.</td></tr> 14632 <tr bgcolor=WHITE> 14633 <td bgcolor=WHITE align=center valign=top>00</td> 14634 <td align=left valign=top>RO</td> 14635 <td align=left valign=top>afe_rx_pwrdn</td> 14636 <td align=left> 14637 Indicates the status of the afe_rx_pwrdn signal to the AFE after frc/frc_val mux. <br> 14638 Reset value is 0x0.</td></tr> 14639 </table><p> 14640 <A HREF="#RX_CKRST_CTRL Registers">Return to RX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14641 <hr> 14642 <H1><a NAME="TX_CKRST_CTRL Registers">TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Registers</a></H1> 14643 <table border=1 align=center width=100% cellpadding=0> 14644 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 14645 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 14646 <tr> 14647 <td align=center>0xD171</td><td><A HREF="#TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL">TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL</A><br>TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_reset_deassert</div> </td> <td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_tx_s_pwrdn</div> </td> <td align=center>16'h0000</td></tr> 14648 <tr> 14649 <td align=center>0xD172</td><td><A HREF="#TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL">TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL</A><br>TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_txclk_reset_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_txclk_reset_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_reset_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_reset_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_pwrdn_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_pwrdn_frc</div> </td> <td align=center>16'h0000</td></tr> 14650 <tr> 14651 <td align=center>0xD173</td><td><A HREF="#TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</A><br>TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_tx_h_pwrdn_pkill</div> </td> <td align=center>16'h0000</td></tr> 14652 <tr> 14653 <td align=center>0xD174</td><td><A HREF="#TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL">TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL</A><br>TX_LANE_DEBUG_RESET_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_tx_dp_s_rstb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_tx_s_rstb</div> </td> <td align=center>16'h0003</td></tr> 14654 <tr> 14655 <td align=center>0xD177</td><td><A HREF="#TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL">TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL</A><br>TX_CLOCK_N_RESET_DEBUG_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_tx_clk_vld_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_tx_clk_vld_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_tx_s_comclk_frc_on</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_tx_s_comclk_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ln_tx_s_clkgate_frc_on</div> </td> <td align=center>16'h0000</td></tr> 14656 <tr> 14657 <td align=center>0xD17C</td><td><A HREF="#TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</A><br>TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_txclk_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">afe_tx_pwrdn</div> </td> <td align=center>16'h0006</td></tr> 14658 <tr> 14659 <td align=center>0xD17D</td><td><A HREF="#TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL">TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL</A><br>TX_CLOCK_N_RESET_MISC_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_loop_filter_stable</div> </td> <td align=center>16'h0001</td></tr> 14660 </table><p> 14661 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 14662 <hr> 14663 <b><a NAME="TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL">TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL - TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL</a></b><br> 14664 Address Offset = 32'h0000_d171<br> 14665 Physical Address = 32'h0000_d171<br> 14666 Reset Value = 16'h0000<br> 14667 Access = RW (16-bit only)<br> 14668 <table border=1 align=center width=100% cellpadding=0> 14669 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14670 <tr bgcolor=WHITE> 14671 <td bgcolor=WHITE align=center valign=top>15</td> 14672 <td align=left valign=top>RW</td> 14673 <td align=left valign=top>afe_tx_reset_deassert</td> 14674 <td align=left> 14675 AFE TX Lane reset control. This register will be reset upon POR reg/pin or lane reset reg/pin. Lower priority than the afe_tx_reset_frc/frc_val and  14676 afe_txclk_reset_frc/frc_val option.<br> 14677 1 - AFE TX Lane txclk_reset/tx_reset pins will be forcefully de-asserted irrespective of core/lane datapath pin/reg resets asserted. <br> 14678      This bit must be set to 1'b1 for TX_Disable all 1s/0s mode to allow TX AFE to transmit the all 1s/0s data. <br> 14679 0 - AFE TX Lane txclk_reset/tx_reset pins will be asserted if core/lane pin/reg resets are asserted. <br> 14680 Reset value is 0x0.</td></tr> 14681 <tr bgcolor=WHITE> 14682 <td bgcolor=WHITE align=center valign=top>14:01</td> 14683 <td align=left valign=top>RSVD</td> 14684 <td align=left valign=top>Reserved</td> 14685 <td align=left> 14686 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14687 <tr bgcolor=WHITE> 14688 <td bgcolor=WHITE align=center valign=top>00</td> 14689 <td align=left valign=top>RW</td> 14690 <td align=left valign=top>ln_tx_s_pwrdn</td> 14691 <td align=left> 14692 Active High Power Down control for TX Lane. <br> 14693 If asserted by writing to 1'b1 will power down the TX Lane. <br> 14694 Reset value is 0x0.</td></tr> 14695 </table><p> 14696 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14697 <hr> 14698 <b><a NAME="TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL">TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL - TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL</a></b><br> 14699 Address Offset = 32'h0000_d172<br> 14700 Physical Address = 32'h0000_d172<br> 14701 Reset Value = 16'h0000<br> 14702 Access = RW (16-bit only)<br> 14703 <table border=1 align=center width=100% cellpadding=0> 14704 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14705 <tr bgcolor=WHITE> 14706 <td bgcolor=WHITE align=center valign=top>15:06</td> 14707 <td align=left valign=top>RSVD</td> 14708 <td align=left valign=top>Reserved</td> 14709 <td align=left> 14710 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14711 <tr bgcolor=WHITE> 14712 <td bgcolor=WHITE align=center valign=top>05</td> 14713 <td align=left valign=top>RW</td> 14714 <td align=left valign=top>afe_txclk_reset_frc_val</td> 14715 <td align=left> 14716 AFE TXCLK Lane reset force value. <br> 14717 Reset value is 0x0.</td></tr> 14718 <tr bgcolor=WHITE> 14719 <td bgcolor=WHITE align=center valign=top>04</td> 14720 <td align=left valign=top>RW</td> 14721 <td align=left valign=top>afe_txclk_reset_frc</td> 14722 <td align=left> 14723 AFE TXCLK Lane reset force. <br> 14724 Reset value is 0x0.</td></tr> 14725 <tr bgcolor=WHITE> 14726 <td bgcolor=WHITE align=center valign=top>03</td> 14727 <td align=left valign=top>RW</td> 14728 <td align=left valign=top>afe_tx_reset_frc_val</td> 14729 <td align=left> 14730 AFE TX Lane reset force value. <br> 14731 Reset value is 0x0.</td></tr> 14732 <tr bgcolor=WHITE> 14733 <td bgcolor=WHITE align=center valign=top>02</td> 14734 <td align=left valign=top>RW</td> 14735 <td align=left valign=top>afe_tx_reset_frc</td> 14736 <td align=left> 14737 AFE TX Lane reset force. <br> 14738 Reset value is 0x0.</td></tr> 14739 <tr bgcolor=WHITE> 14740 <td bgcolor=WHITE align=center valign=top>01</td> 14741 <td align=left valign=top>RW</td> 14742 <td align=left valign=top>afe_tx_pwrdn_frc_val</td> 14743 <td align=left> 14744 AFE TX Lane powerdown force value. <br> 14745 Reset value is 0x0.</td></tr> 14746 <tr bgcolor=WHITE> 14747 <td bgcolor=WHITE align=center valign=top>00</td> 14748 <td align=left valign=top>RW</td> 14749 <td align=left valign=top>afe_tx_pwrdn_frc</td> 14750 <td align=left> 14751 AFE TX Lane powerdown force. <br> 14752 Reset value is 0x0.</td></tr> 14753 </table><p> 14754 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14755 <hr> 14756 <b><a NAME="TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL - TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</a></b><br> 14757 Address Offset = 32'h0000_d173<br> 14758 Physical Address = 32'h0000_d173<br> 14759 Reset Value = 16'h0000<br> 14760 Access = RW (16-bit only)<br> 14761 <table border=1 align=center width=100% cellpadding=0> 14762 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14763 <tr bgcolor=WHITE> 14764 <td bgcolor=WHITE align=center valign=top>15:01</td> 14765 <td align=left valign=top>RSVD</td> 14766 <td align=left valign=top>Reserved</td> 14767 <td align=left> 14768 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14769 <tr bgcolor=WHITE> 14770 <td bgcolor=WHITE align=center valign=top>00</td> 14771 <td align=left valign=top>RW</td> 14772 <td align=left valign=top>pmd_ln_tx_h_pwrdn_pkill</td> 14773 <td align=left> 14774 1'b1 will disable the pmd_ln_tx_h_pwrdn input pin. <br> 14775 Reset value is 0x0.</td></tr> 14776 </table><p> 14777 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14778 <hr> 14779 <b><a NAME="TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL">TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL - TX_LANE_DEBUG_RESET_CONTROL</a></b><br> 14780 Address Offset = 32'h0000_d174<br> 14781 Physical Address = 32'h0000_d174<br> 14782 Reset Value = 16'h0003<br> 14783 Access = RW (16-bit only)<br> 14784 <table border=1 align=center width=100% cellpadding=0> 14785 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14786 <tr bgcolor=WHITE> 14787 <td bgcolor=WHITE align=center valign=top>15:02</td> 14788 <td align=left valign=top>RSVD</td> 14789 <td align=left valign=top>Reserved</td> 14790 <td align=left> 14791 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14792 <tr bgcolor=WHITE> 14793 <td bgcolor=WHITE align=center valign=top>01</td> 14794 <td align=left valign=top>RW</td> 14795 <td align=left valign=top>ln_tx_dp_s_rstb</td> 14796 <td align=left> 14797 Active Low Lane Soft Reset for TX datapath. If asserted by writing to 1'b0 will reset the TX datapath for a lane. <br> 14798 This is a debug only register and it is not handled by FW-HW handshake <br> 14799 Reset value is 0x1.</td></tr> 14800 <tr bgcolor=WHITE> 14801 <td bgcolor=WHITE align=center valign=top>00</td> 14802 <td align=left valign=top>RW</td> 14803 <td align=left valign=top>ln_tx_s_rstb</td> 14804 <td align=left> 14805 Active Low Lane Soft Reset for TX datapath and registers. If asserted by writing to 1'b0 will reset the TX registers and datapath for a lane. <br> 14806 This is a debug only register and it is not handled by FW-HW handshake <br> 14807 Reset value is 0x1.</td></tr> 14808 </table><p> 14809 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14810 <hr> 14811 <b><a NAME="TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL">TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL - TX_CLOCK_N_RESET_DEBUG_CONTROL</a></b><br> 14812 Address Offset = 32'h0000_d177<br> 14813 Physical Address = 32'h0000_d177<br> 14814 Reset Value = 16'h0000<br> 14815 Access = RW (16-bit only)<br> 14816 <table border=1 align=center width=100% cellpadding=0> 14817 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14818 <tr bgcolor=WHITE> 14819 <td bgcolor=WHITE align=center valign=top>15:05</td> 14820 <td align=left valign=top>RSVD</td> 14821 <td align=left valign=top>Reserved</td> 14822 <td align=left> 14823 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14824 <tr bgcolor=WHITE> 14825 <td bgcolor=WHITE align=center valign=top>04</td> 14826 <td align=left valign=top>RW</td> 14827 <td align=left valign=top>pmd_tx_clk_vld_frc_val</td> 14828 <td align=left> 14829 pmd_tx_clk_vld core output pin force value. <br> 14830 Reset value is 0x0.</td></tr> 14831 <tr bgcolor=WHITE> 14832 <td bgcolor=WHITE align=center valign=top>03</td> 14833 <td align=left valign=top>RW</td> 14834 <td align=left valign=top>pmd_tx_clk_vld_frc</td> 14835 <td align=left> 14836 pmd_tx_clk_vld core output pin force. <br> 14837 Reset value is 0x0.</td></tr> 14838 <tr bgcolor=WHITE> 14839 <td bgcolor=WHITE align=center valign=top>02</td> 14840 <td align=left valign=top>RW</td> 14841 <td align=left valign=top>ln_tx_s_comclk_frc_on</td> 14842 <td align=left> 14843 Mux control for selection of comclk for TX Lane clocks by force. <br> 14844 If asserted by writing to 1'b1 will select the comclk for the TX lane clocks. This is a debug bit and should be used only for recovery from a dead AFE 14845 lane clock. Use of this bit with an active AFE clock can cause clock glitches.<br> 14846 " It is recommended for user to force pmd_tx_clk_vld to 1'b0 while tx_s_comclk_frc_on is asserted to 1'b1<br> 14847 by using pmd_tx_clk_vld_frc/frc_val registers. <br> 14848 Reset value is 0x0.</td></tr> 14849 <tr bgcolor=WHITE> 14850 <td bgcolor=WHITE align=center valign=top>01</td> 14851 <td align=left valign=top>RW</td> 14852 <td align=left valign=top>ln_tx_s_comclk_sel</td> 14853 <td align=left> 14854 Mux control for selection of comclk for TX Lane clocks. <br> 14855 If asserted by writing to 1'b1 will select the comclk for the lane clocks. <br> 14856 " It is recommended for user to force pmd_tx_clk_vld to 1'b0 while tx_s_comclk_sel is asserted to 1'b1<br> 14857 by using pmd_tx_clk_vld_frc/frc_val registers. <br> 14858 Reset value is 0x0.</td></tr> 14859 <tr bgcolor=WHITE> 14860 <td bgcolor=WHITE align=center valign=top>00</td> 14861 <td align=left valign=top>RW</td> 14862 <td align=left valign=top>ln_tx_s_clkgate_frc_on</td> 14863 <td align=left> 14864 TX Active High Lane clock gator enable. If 1'1b1 then tx lane clock will be gated off. It does not affect the tclk going <br> 14865 to RMIC block so tx lane based registers can still be readable but not writable. <br> 14866 " It is recommended for user to force pmd_tx_clk_vld to 1'b0 while tx_s_clkgate_frc_on is asserted to 1'b1<br> 14867 by using pmd_tx_clk_vld_frc/frc_val registers. <br> 14868 Reset value is 0x0.</td></tr> 14869 </table><p> 14870 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14871 <hr> 14872 <b><a NAME="TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS - TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</a></b><br> 14873 Address Offset = 32'h0000_d17c<br> 14874 Physical Address = 32'h0000_d17c<br> 14875 Reset Value = 16'h0006<br> 14876 Access = RO (16-bit only)<br> 14877 <table border=1 align=center width=100% cellpadding=0> 14878 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14879 <tr bgcolor=WHITE> 14880 <td bgcolor=WHITE align=center valign=top>15:03</td> 14881 <td align=left valign=top>RSVD</td> 14882 <td align=left valign=top>Reserved</td> 14883 <td align=left> 14884 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14885 <tr bgcolor=WHITE> 14886 <td bgcolor=WHITE align=center valign=top>02</td> 14887 <td align=left valign=top>RO</td> 14888 <td align=left valign=top>afe_txclk_reset</td> 14889 <td align=left> 14890 Indicates the status of the afe_txclk_reset signal to the AFE after frc/frc_val mux. <br> 14891 Reset value is 0x1.</td></tr> 14892 <tr bgcolor=WHITE> 14893 <td bgcolor=WHITE align=center valign=top>01</td> 14894 <td align=left valign=top>RO</td> 14895 <td align=left valign=top>afe_tx_reset</td> 14896 <td align=left> 14897 Indicates the status of the afe_tx_reset signal to the AFE after frc/frc_val mux. <br> 14898 Reset value is 0x1.</td></tr> 14899 <tr bgcolor=WHITE> 14900 <td bgcolor=WHITE align=center valign=top>00</td> 14901 <td align=left valign=top>RO</td> 14902 <td align=left valign=top>afe_tx_pwrdn</td> 14903 <td align=left> 14904 Indicates the status of the afe_tx_pwrdn signal to the AFE after frc/frc_val mux. <br> 14905 Reset value is 0x0.</td></tr> 14906 </table><p> 14907 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14908 <hr> 14909 <b><a NAME="TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL">TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL - TX_CLOCK_N_RESET_MISC_CONTROL</a></b><br> 14910 Address Offset = 32'h0000_d17d<br> 14911 Physical Address = 32'h0000_d17d<br> 14912 Reset Value = 16'h0001<br> 14913 Access = RW (16-bit only)<br> 14914 <table border=1 align=center width=100% cellpadding=0> 14915 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14916 <tr bgcolor=WHITE> 14917 <td bgcolor=WHITE align=center valign=top>15:01</td> 14918 <td align=left valign=top>RSVD</td> 14919 <td align=left valign=top>Reserved</td> 14920 <td align=left> 14921 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14922 <tr bgcolor=WHITE> 14923 <td bgcolor=WHITE align=center valign=top>00</td> 14924 <td align=left valign=top>RW</td> 14925 <td align=left valign=top>tx_pi_loop_filter_stable</td> 14926 <td align=left> 14927 This register bit is ANDed with pmd_tx_clk_vld before frc/frc_val mux. This register will be controlled by the firmware when TX_PI is enabled. <br> 14928 When TX_PI is enabled then this register will be written to 1'b0 while TX_PI is acquiring the lock with the source clock and will be written to 1'b1 by 14929 firmware <br> 14930 to indicate that clocks are locked. It indicates to chip level via pmd_tx_clk_vld to reset any datapath FIFOs and come out of reset when TX clock is stable. 14931 <br> 14932 Reset value is 0x1.</td></tr> 14933 </table><p> 14934 <A HREF="#TX_CKRST_CTRL Registers">Return to TX_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 14935 <hr> 14936 <H1><a NAME="RXCOM_CKRST_CTRL Registers">RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Registers</a></H1> 14937 <table border=1 align=center width=100% cellpadding=0> 14938 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 14939 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 14940 <tr> 14941 <td align=center>0xD180</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL">RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL</A><br>RXCOM_OSR_MODE_CONTROL</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_osr_mode_frc</div> </td> <td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rx_osr_mode_frc_val</div> </td> <td align=center>16'h0000</td></tr> 14942 <tr> 14943 <td align=center>0xD181</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</A><br>RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_ln_dp_s_rstb</div> </td> <td align=center>16'h0000</td></tr> 14944 <tr> 14945 <td align=center>0xD183</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</A><br>RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_rx_dp_h_rstb_pkill</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_rx_h_rstb_pkill</div> </td> <td align=center>16'h0000</td></tr> 14946 <tr> 14947 <td align=center>0xD185</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL">RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL</A><br>RXCOM_UC_ACK_LANE_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_uc_ack_lane_dp_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_uc_ack_lane_cfg_done</div> </td> <td align=center>16'h0000</td></tr> 14948 <tr> 14949 <td align=center>0xD186</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL</A><br>RXCOM_LANE_REG_RESET_OCCURRED_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_lane_reg_reset_occurred</div> </td> <td align=center>16'h0001</td></tr> 14950 <tr> 14951 <td align=center>0xD189</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS">RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS</A><br>RXCOM_LANE_DP_RESET_STATE_STATUS</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rx_lane_dp_reset_state</div> </td> <td align=center>16'h0007</td></tr> 14952 <tr> 14953 <td align=center>0xD18A</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL">RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL</A><br>RXCOM_MULTICAST_MASK_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_multicast_mask_control</div> </td> <td align=center>16'h0000</td></tr> 14954 <tr> 14955 <td align=center>0xD18B</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK">RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK</A><br>RXCOM_OSR_MODE_STATUS_MC_MASK</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_multicast_mask_control_status</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rx_osr_mode</div> </td> <td align=center>16'h0000</td></tr> 14956 <tr> 14957 <td align=center>0xD18C</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</A><br>RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rx_osr_mode_pin</div> </td> <td align=center>16'h0000</td></tr> 14958 <tr> 14959 <td align=center>0xD18E</td><td><A HREF="#RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL</A><br>RXCOM_LN_S_RSTB_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_ln_s_rstb</div> </td> <td align=center>16'h0001</td></tr> 14960 </table><p> 14961 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 14962 <hr> 14963 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL">RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL - RXCOM_OSR_MODE_CONTROL</a></b><br> 14964 Address Offset = 32'h0000_d180<br> 14965 Physical Address = 32'h0000_d180<br> 14966 Reset Value = 16'h0000<br> 14967 Access = RW (16-bit only)<br> 14968 <table border=1 align=center width=100% cellpadding=0> 14969 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 14970 <tr bgcolor=WHITE> 14971 <td bgcolor=WHITE align=center valign=top>15</td> 14972 <td align=left valign=top>RW</td> 14973 <td align=left valign=top>rx_osr_mode_frc</td> 14974 <td align=left> 14975 oversample (OS) mode force. Setting this bit will allow the register value to be used for OS mode. <br> 14976 Othersise, the pin input values are used for OS mode<br> 14977 Reset value is 0x0.</td></tr> 14978 <tr bgcolor=WHITE> 14979 <td bgcolor=WHITE align=center valign=top>14:04</td> 14980 <td align=left valign=top>RSVD</td> 14981 <td align=left valign=top>Reserved</td> 14982 <td align=left> 14983 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 14984 <tr bgcolor=WHITE> 14985 <td bgcolor=WHITE align=center valign=top>03:00</td> 14986 <td align=left valign=top>RW</td> 14987 <td align=left valign=top>rx_osr_mode_frc_val</td> 14988 <td align=left> 14989 oversample (OS) mode Decoding of this register is as follows. <br> 14990     OSX1          4'd0        <br> 14991     OSX2          4'd1        <br> 14992     OSX3          4'd2        <br> 14993     OSX3P3        4'd3        <br> 14994     OSX4          4'd4        <br> 14995     OSX5          4'd5        <br> 14996     OSX7P5        4'd6        <br> 14997     OSX8          4'd7        <br> 14998     OSX8P25       4'd8        <br> 14999     OSX10         4'd9        <br> 15000 Reset value is 0x0.</td></tr> 15001 </table><p> 15002 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15003 <hr> 15004 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL - RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</a></b><br> 15005 Address Offset = 32'h0000_d181<br> 15006 Physical Address = 32'h0000_d181<br> 15007 Reset Value = 16'h0000<br> 15008 Access = RW (16-bit only)<br> 15009 <table border=1 align=center width=100% cellpadding=0> 15010 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15011 <tr bgcolor=WHITE> 15012 <td bgcolor=WHITE align=center valign=top>15:01</td> 15013 <td align=left valign=top>RSVD</td> 15014 <td align=left valign=top>Reserved</td> 15015 <td align=left> 15016 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15017 <tr bgcolor=WHITE> 15018 <td bgcolor=WHITE align=center valign=top>00</td> 15019 <td align=left valign=top>RW</td> 15020 <td align=left valign=top>rx_ln_dp_s_rstb</td> 15021 <td align=left> 15022 Active Low Lane Soft Reset for datapath. If asserted by writing to 1'b0 will reset the datapath for a lane. <br> 15023 This soft reset is equivalent to the hard reset input pin pmd_ln_dp_h_rstb_i. <br> 15024 Reset value is 0x0.</td></tr> 15025 </table><p> 15026 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15027 <hr> 15028 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL - RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</a></b><br> 15029 Address Offset = 32'h0000_d183<br> 15030 Physical Address = 32'h0000_d183<br> 15031 Reset Value = 16'h0000<br> 15032 Access = RW (16-bit only)<br> 15033 <table border=1 align=center width=100% cellpadding=0> 15034 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15035 <tr bgcolor=WHITE> 15036 <td bgcolor=WHITE align=center valign=top>15:02</td> 15037 <td align=left valign=top>RSVD</td> 15038 <td align=left valign=top>Reserved</td> 15039 <td align=left> 15040 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15041 <tr bgcolor=WHITE> 15042 <td bgcolor=WHITE align=center valign=top>01</td> 15043 <td align=left valign=top>RW</td> 15044 <td align=left valign=top>pmd_ln_rx_dp_h_rstb_pkill</td> 15045 <td align=left> 15046 1'b1 will disable the pmd_ln_dp_h_rstb input pin. <br> 15047 Reset value is 0x0.</td></tr> 15048 <tr bgcolor=WHITE> 15049 <td bgcolor=WHITE align=center valign=top>00</td> 15050 <td align=left valign=top>RW</td> 15051 <td align=left valign=top>pmd_ln_rx_h_rstb_pkill</td> 15052 <td align=left> 15053 1'b1 will disable the pmd_ln_h_rstb input pin. <br> 15054 Reset value is 0x0.</td></tr> 15055 </table><p> 15056 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15057 <hr> 15058 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL">RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL - RXCOM_UC_ACK_LANE_CONTROL</a></b><br> 15059 Address Offset = 32'h0000_d185<br> 15060 Physical Address = 32'h0000_d185<br> 15061 Reset Value = 16'h0000<br> 15062 Access = RW (16-bit only)<br> 15063 <table border=1 align=center width=100% cellpadding=0> 15064 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15065 <tr bgcolor=WHITE> 15066 <td bgcolor=WHITE align=center valign=top>15:02</td> 15067 <td align=left valign=top>RSVD</td> 15068 <td align=left valign=top>Reserved</td> 15069 <td align=left> 15070 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15071 <tr bgcolor=WHITE> 15072 <td bgcolor=WHITE align=center valign=top>01</td> 15073 <td align=left valign=top>SC</td> 15074 <td align=left valign=top>rx_uc_ack_lane_dp_reset</td> 15075 <td align=left> 15076 uC will write this to 1 to acknowledge a reset event after seeing "lane_dp_reset_coccured". <br> 15077 Reset value is 0x0.</td></tr> 15078 <tr bgcolor=WHITE> 15079 <td bgcolor=WHITE align=center valign=top>00</td> 15080 <td align=left valign=top>SC</td> 15081 <td align=left valign=top>rx_uc_ack_lane_cfg_done</td> 15082 <td align=left> 15083 uC will write this to 1 to indicate it's configuration of the lane is complete. Writing to 1'b1 will  <br> 15084 should release internal hold on lane_dp_reset, only if lane_dp_reset_state is 3'b001. <br> 15085 Reset value is 0x0.</td></tr> 15086 </table><p> 15087 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15088 <hr> 15089 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL - RXCOM_LANE_REG_RESET_OCCURRED_CONTROL</a></b><br> 15090 Address Offset = 32'h0000_d186<br> 15091 Physical Address = 32'h0000_d186<br> 15092 Reset Value = 16'h0001<br> 15093 Access = RW (16-bit only)<br> 15094 <table border=1 align=center width=100% cellpadding=0> 15095 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15096 <tr bgcolor=WHITE> 15097 <td bgcolor=WHITE align=center valign=top>15:01</td> 15098 <td align=left valign=top>RSVD</td> 15099 <td align=left valign=top>Reserved</td> 15100 <td align=left> 15101 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15102 <tr bgcolor=WHITE> 15103 <td bgcolor=WHITE align=center valign=top>00</td> 15104 <td align=left valign=top>RW</td> 15105 <td align=left valign=top>rx_lane_reg_reset_occurred</td> 15106 <td align=left> 15107 Set to 1'b1 upon lane level register reset and remains so until cleared by register write from uC. <br> 15108 Reset value is 0x1.</td></tr> 15109 </table><p> 15110 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15111 <hr> 15112 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS">RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS - RXCOM_LANE_DP_RESET_STATE_STATUS</a></b><br> 15113 Address Offset = 32'h0000_d189<br> 15114 Physical Address = 32'h0000_d189<br> 15115 Reset Value = 16'h0007<br> 15116 Access = RO (16-bit only)<br> 15117 <table border=1 align=center width=100% cellpadding=0> 15118 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15119 <tr bgcolor=WHITE> 15120 <td bgcolor=WHITE align=center valign=top>15:03</td> 15121 <td align=left valign=top>RSVD</td> 15122 <td align=left valign=top>Reserved</td> 15123 <td align=left> 15124 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15125 <tr bgcolor=WHITE> 15126 <td bgcolor=WHITE align=center valign=top>02:00</td> 15127 <td align=left valign=top>RO</td> 15128 <td align=left valign=top>rx_lane_dp_reset_state</td> 15129 <td align=left> 15130 Bit 2: lane_dp_reset_active   : Set to 1'b1 whenenver lane_dp_reset is currently requested through any register or pin controls.  <br> 15131 Bit 1: lane_dp_reset_occurred : Set to 1'b1 whenenver lane_dp_reset is currently requested through any register or pin controls and is latched high.  15132 <br> 15133 Bit 0: lane_dp_reset_held     : Set to 1'b1 whenenver lane_dp_reset is internally held. Cleared to 1'b0, only if lane_dp_reset_state==001 15134 and uc_ack_lane_cfg_done == 1. <br> 15135 Reset value is 0x7.</td></tr> 15136 </table><p> 15137 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15138 <hr> 15139 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL">RXCOM_CKRST_CTRL_RXCOM_MULTICAST_MASK_CONTROL - RXCOM_MULTICAST_MASK_CONTROL</a></b><br> 15140 Address Offset = 32'h0000_d18a<br> 15141 Physical Address = 32'h0000_d18a<br> 15142 Reset Value = 16'h0000<br> 15143 Access = RW (16-bit only)<br> 15144 <table border=1 align=center width=100% cellpadding=0> 15145 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15146 <tr bgcolor=WHITE> 15147 <td bgcolor=WHITE align=center valign=top>15:01</td> 15148 <td align=left valign=top>RSVD</td> 15149 <td align=left valign=top>Reserved</td> 15150 <td align=left> 15151 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15152 <tr bgcolor=WHITE> 15153 <td bgcolor=WHITE align=center valign=top>00</td> 15154 <td align=left valign=top>WO</td> 15155 <td align=left valign=top>rx_multicast_mask_control</td> 15156 <td align=left> 15157 This masks the lane from a broadcast or multicast write operation. <br> 15158 Reset value is 0x0.</td></tr> 15159 </table><p> 15160 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15161 <hr> 15162 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK">RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK - RXCOM_OSR_MODE_STATUS_MC_MASK</a></b><br> 15163 Address Offset = 32'h0000_d18b<br> 15164 Physical Address = 32'h0000_d18b<br> 15165 Reset Value = 16'h0000<br> 15166 Access = RO (16-bit only)<br> 15167 <table border=1 align=center width=100% cellpadding=0> 15168 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15169 <tr bgcolor=WHITE> 15170 <td bgcolor=WHITE align=center valign=top>15:05</td> 15171 <td align=left valign=top>RSVD</td> 15172 <td align=left valign=top>Reserved</td> 15173 <td align=left> 15174 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15175 <tr bgcolor=WHITE> 15176 <td bgcolor=WHITE align=center valign=top>04</td> 15177 <td align=left valign=top>RO</td> 15178 <td align=left valign=top>rx_multicast_mask_control_status</td> 15179 <td align=left> 15180 Status of multicast mask control for masking lane from multicast write operation. <br> 15181 Reset value is 0x0.</td></tr> 15182 <tr bgcolor=WHITE> 15183 <td bgcolor=WHITE align=center valign=top>03:00</td> 15184 <td align=left valign=top>RO</td> 15185 <td align=left valign=top>rx_osr_mode</td> 15186 <td align=left> 15187 OSR Mode status after the mux. <br> 15188 OSR Mode status after the osr_mode_frc/frc_val mux. <br> 15189 Decoding of this register is as follows. <br> 15190     OSX1          4'd0        <br> 15191     OSX2          4'd1        <br> 15192     OSX3          4'd2        <br> 15193     OSX3P3        4'd3        <br> 15194     OSX4          4'd4        <br> 15195     OSX5          4'd5        <br> 15196     OSX7P5        4'd6        <br> 15197     OSX8          4'd7        <br> 15198     OSX8P25       4'd8        <br> 15199     OSX10         4'd9        <br> 15200 Reset value is 0x0.</td></tr> 15201 </table><p> 15202 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15203 <hr> 15204 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS - RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</a></b><br> 15205 Address Offset = 32'h0000_d18c<br> 15206 Physical Address = 32'h0000_d18c<br> 15207 Reset Value = 16'h0000<br> 15208 Access = RO (16-bit only)<br> 15209 <table border=1 align=center width=100% cellpadding=0> 15210 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15211 <tr bgcolor=WHITE> 15212 <td bgcolor=WHITE align=center valign=top>15:04</td> 15213 <td align=left valign=top>RSVD</td> 15214 <td align=left valign=top>Reserved</td> 15215 <td align=left> 15216 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15217 <tr bgcolor=WHITE> 15218 <td bgcolor=WHITE align=center valign=top>03:00</td> 15219 <td align=left valign=top>RO</td> 15220 <td align=left valign=top>rx_osr_mode_pin</td> 15221 <td align=left> 15222 Indicates the status of the pmd_osr_mode input pin. <br> 15223 Decoding of pmd_osr_mode[3:0] pin and osr_mode registers are as follows. <br> 15224     OSX1          4'd0        <br> 15225     OSX2          4'd1        <br> 15226     OSX3          4'd2        <br> 15227     OSX3P3        4'd3        <br> 15228     OSX4          4'd4        <br> 15229     OSX5          4'd5        <br> 15230     OSX7P5        4'd6        <br> 15231     OSX8          4'd7        <br> 15232     OSX8P25       4'd8        <br> 15233     OSX10         4'd9        <br> 15234 Reset value is 0x0.</td></tr> 15235 </table><p> 15236 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15237 <hr> 15238 <b><a NAME="RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL">RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL - RXCOM_LN_S_RSTB_CONTROL</a></b><br> 15239 Address Offset = 32'h0000_d18e<br> 15240 Physical Address = 32'h0000_d18e<br> 15241 Reset Value = 16'h0001<br> 15242 Access = RW (16-bit only)<br> 15243 <table border=1 align=center width=100% cellpadding=0> 15244 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15245 <tr bgcolor=WHITE> 15246 <td bgcolor=WHITE align=center valign=top>15:01</td> 15247 <td align=left valign=top>RSVD</td> 15248 <td align=left valign=top>Reserved</td> 15249 <td align=left> 15250 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15251 <tr bgcolor=WHITE> 15252 <td bgcolor=WHITE align=center valign=top>00</td> 15253 <td align=left valign=top>RW</td> 15254 <td align=left valign=top>rx_ln_s_rstb</td> 15255 <td align=left> 15256 Active Low Lane Soft Reset. If asserted by writing to 1'b0 will reset the registers and datapath for a lane. <br> 15257 This soft reset is equivalent to the hard reset input pin pmd_ln_h_rstb_i. <br> 15258 Reset value is 0x1.</td></tr> 15259 </table><p> 15260 <A HREF="#RXCOM_CKRST_CTRL Registers">Return to RXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15261 <hr> 15262 <H1><a NAME="TXCOM_CKRST_CTRL Registers">TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Registers</a></H1> 15263 <table border=1 align=center width=100% cellpadding=0> 15264 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 15265 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 15266 <tr> 15267 <td align=center>0xD190</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL">TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL</A><br>TXCOM_OSR_MODE_CONTROL</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_osr_mode_frc</div> </td> <td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tx_osr_mode_frc_val</div> </td> <td align=center>16'h0000</td></tr> 15268 <tr> 15269 <td align=center>0xD191</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</A><br>TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_ln_dp_s_rstb</div> </td> <td align=center>16'h0000</td></tr> 15270 <tr> 15271 <td align=center>0xD193</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</A><br>TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_tx_dp_h_rstb_pkill</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">pmd_ln_tx_h_rstb_pkill</div> </td> <td align=center>16'h0000</td></tr> 15272 <tr> 15273 <td align=center>0xD195</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL">TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL</A><br>TXCOM_UC_ACK_LANE_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_uc_ack_lane_dp_reset</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_uc_ack_lane_cfg_done</div> </td> <td align=center>16'h0000</td></tr> 15274 <tr> 15275 <td align=center>0xD196</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL</A><br>TXCOM_LANE_REG_RESET_OCCURRED_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_lane_reg_reset_occurred</div> </td> <td align=center>16'h0001</td></tr> 15276 <tr> 15277 <td align=center>0xD199</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS">TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS</A><br>TXCOM_LANE_DP_RESET_STATE_STATUS</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tx_lane_dp_reset_state</div> </td> <td align=center>16'h0007</td></tr> 15278 <tr> 15279 <td align=center>0xD19A</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL">TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL</A><br>TXCOM_MULTICAST_MASK_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_multicast_mask_control</div> </td> <td align=center>16'h0000</td></tr> 15280 <tr> 15281 <td align=center>0xD19B</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK">TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK</A><br>TXCOM_OSR_MODE_STATUS_MC_MASK</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_multicast_mask_control_status</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tx_osr_mode</div> </td> <td align=center>16'h0000</td></tr> 15282 <tr> 15283 <td align=center>0xD19C</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</A><br>TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tx_osr_mode_pin</div> </td> <td align=center>16'h0000</td></tr> 15284 <tr> 15285 <td align=center>0xD19E</td><td><A HREF="#TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL</A><br>TXCOM_LN_S_RSTB_CONTROL</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_ln_s_rstb</div> </td> <td align=center>16'h0001</td></tr> 15286 </table><p> 15287 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 15288 <hr> 15289 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL">TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL - TXCOM_OSR_MODE_CONTROL</a></b><br> 15290 Address Offset = 32'h0000_d190<br> 15291 Physical Address = 32'h0000_d190<br> 15292 Reset Value = 16'h0000<br> 15293 Access = RW (16-bit only)<br> 15294 <table border=1 align=center width=100% cellpadding=0> 15295 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15296 <tr bgcolor=WHITE> 15297 <td bgcolor=WHITE align=center valign=top>15</td> 15298 <td align=left valign=top>RW</td> 15299 <td align=left valign=top>tx_osr_mode_frc</td> 15300 <td align=left> 15301 oversample (OS) mode force. Setting this bit will allow the register value to be used for OS mode. <br> 15302 Othersise, the pin input values are used for OS mode<br> 15303 Reset value is 0x0.</td></tr> 15304 <tr bgcolor=WHITE> 15305 <td bgcolor=WHITE align=center valign=top>14:04</td> 15306 <td align=left valign=top>RSVD</td> 15307 <td align=left valign=top>Reserved</td> 15308 <td align=left> 15309 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15310 <tr bgcolor=WHITE> 15311 <td bgcolor=WHITE align=center valign=top>03:00</td> 15312 <td align=left valign=top>RW</td> 15313 <td align=left valign=top>tx_osr_mode_frc_val</td> 15314 <td align=left> 15315 oversample (OS) mode Decoding of this register is as follows. <br> 15316     OSX1          4'd0        <br> 15317     OSX2          4'd1        <br> 15318     OSX3          4'd2        <br> 15319     OSX3P3        4'd3        <br> 15320     OSX4          4'd4        <br> 15321     OSX5          4'd5        <br> 15322     OSX7P5        4'd6        <br> 15323     OSX8          4'd7        <br> 15324     OSX8P25       4'd8        <br> 15325     OSX10         4'd9        <br> 15326 Reset value is 0x0.</td></tr> 15327 </table><p> 15328 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15329 <hr> 15330 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL - TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL</a></b><br> 15331 Address Offset = 32'h0000_d191<br> 15332 Physical Address = 32'h0000_d191<br> 15333 Reset Value = 16'h0000<br> 15334 Access = RW (16-bit only)<br> 15335 <table border=1 align=center width=100% cellpadding=0> 15336 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15337 <tr bgcolor=WHITE> 15338 <td bgcolor=WHITE align=center valign=top>15:01</td> 15339 <td align=left valign=top>RSVD</td> 15340 <td align=left valign=top>Reserved</td> 15341 <td align=left> 15342 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15343 <tr bgcolor=WHITE> 15344 <td bgcolor=WHITE align=center valign=top>00</td> 15345 <td align=left valign=top>RW</td> 15346 <td align=left valign=top>tx_ln_dp_s_rstb</td> 15347 <td align=left> 15348 Active Low Lane Soft Reset for datapath. If asserted by writing to 1'b0 will reset the datapath for a lane. <br> 15349 This soft reset is equivalent to the hard reset input pin pmd_ln_dp_h_rstb_i. <br> 15350 Reset value is 0x0.</td></tr> 15351 </table><p> 15352 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15353 <hr> 15354 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL - TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL</a></b><br> 15355 Address Offset = 32'h0000_d193<br> 15356 Physical Address = 32'h0000_d193<br> 15357 Reset Value = 16'h0000<br> 15358 Access = RW (16-bit only)<br> 15359 <table border=1 align=center width=100% cellpadding=0> 15360 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15361 <tr bgcolor=WHITE> 15362 <td bgcolor=WHITE align=center valign=top>15:02</td> 15363 <td align=left valign=top>RSVD</td> 15364 <td align=left valign=top>Reserved</td> 15365 <td align=left> 15366 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15367 <tr bgcolor=WHITE> 15368 <td bgcolor=WHITE align=center valign=top>01</td> 15369 <td align=left valign=top>RW</td> 15370 <td align=left valign=top>pmd_ln_tx_dp_h_rstb_pkill</td> 15371 <td align=left> 15372 1'b1 will disable the pmd_ln_dp_h_rstb input pin. <br> 15373 Reset value is 0x0.</td></tr> 15374 <tr bgcolor=WHITE> 15375 <td bgcolor=WHITE align=center valign=top>00</td> 15376 <td align=left valign=top>RW</td> 15377 <td align=left valign=top>pmd_ln_tx_h_rstb_pkill</td> 15378 <td align=left> 15379 1'b1 will disable the pmd_ln_h_rstb input pin. <br> 15380 Reset value is 0x0.</td></tr> 15381 </table><p> 15382 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15383 <hr> 15384 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL">TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL - TXCOM_UC_ACK_LANE_CONTROL</a></b><br> 15385 Address Offset = 32'h0000_d195<br> 15386 Physical Address = 32'h0000_d195<br> 15387 Reset Value = 16'h0000<br> 15388 Access = RW (16-bit only)<br> 15389 <table border=1 align=center width=100% cellpadding=0> 15390 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15391 <tr bgcolor=WHITE> 15392 <td bgcolor=WHITE align=center valign=top>15:02</td> 15393 <td align=left valign=top>RSVD</td> 15394 <td align=left valign=top>Reserved</td> 15395 <td align=left> 15396 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15397 <tr bgcolor=WHITE> 15398 <td bgcolor=WHITE align=center valign=top>01</td> 15399 <td align=left valign=top>SC</td> 15400 <td align=left valign=top>tx_uc_ack_lane_dp_reset</td> 15401 <td align=left> 15402 uC will write this to 1 to acknowledge a reset event after seeing "lane_dp_reset_coccured". <br> 15403 Reset value is 0x0.</td></tr> 15404 <tr bgcolor=WHITE> 15405 <td bgcolor=WHITE align=center valign=top>00</td> 15406 <td align=left valign=top>SC</td> 15407 <td align=left valign=top>tx_uc_ack_lane_cfg_done</td> 15408 <td align=left> 15409 uC will write this to 1 to indicate it's configuration of the lane is complete. Writing to 1'b1 will  <br> 15410 should release internal hold on lane_dp_reset, only if lane_dp_reset_state is 3'b001. <br> 15411 Reset value is 0x0.</td></tr> 15412 </table><p> 15413 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15414 <hr> 15415 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL - TXCOM_LANE_REG_RESET_OCCURRED_CONTROL</a></b><br> 15416 Address Offset = 32'h0000_d196<br> 15417 Physical Address = 32'h0000_d196<br> 15418 Reset Value = 16'h0001<br> 15419 Access = RW (16-bit only)<br> 15420 <table border=1 align=center width=100% cellpadding=0> 15421 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15422 <tr bgcolor=WHITE> 15423 <td bgcolor=WHITE align=center valign=top>15:01</td> 15424 <td align=left valign=top>RSVD</td> 15425 <td align=left valign=top>Reserved</td> 15426 <td align=left> 15427 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15428 <tr bgcolor=WHITE> 15429 <td bgcolor=WHITE align=center valign=top>00</td> 15430 <td align=left valign=top>RW</td> 15431 <td align=left valign=top>tx_lane_reg_reset_occurred</td> 15432 <td align=left> 15433 Set to 1'b1 upon lane level register reset and remains so until cleared by register write from uC. <br> 15434 Reset value is 0x1.</td></tr> 15435 </table><p> 15436 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15437 <hr> 15438 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS">TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS - TXCOM_LANE_DP_RESET_STATE_STATUS</a></b><br> 15439 Address Offset = 32'h0000_d199<br> 15440 Physical Address = 32'h0000_d199<br> 15441 Reset Value = 16'h0007<br> 15442 Access = RO (16-bit only)<br> 15443 <table border=1 align=center width=100% cellpadding=0> 15444 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15445 <tr bgcolor=WHITE> 15446 <td bgcolor=WHITE align=center valign=top>15:03</td> 15447 <td align=left valign=top>RSVD</td> 15448 <td align=left valign=top>Reserved</td> 15449 <td align=left> 15450 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15451 <tr bgcolor=WHITE> 15452 <td bgcolor=WHITE align=center valign=top>02:00</td> 15453 <td align=left valign=top>RO</td> 15454 <td align=left valign=top>tx_lane_dp_reset_state</td> 15455 <td align=left> 15456 Bit 2: lane_dp_reset_active   : Set to 1'b1 whenenver lane_dp_reset is currently requested through any register or pin controls.  <br> 15457 Bit 1: lane_dp_reset_occurred : Set to 1'b1 whenenver lane_dp_reset is currently requested through any register or pin controls and is latched high.  15458 <br> 15459 Bit 0: lane_dp_reset_held     : Set to 1'b1 whenenver lane_dp_reset is internally held. Cleared to 1'b0, only if lane_dp_reset_state==001 15460 and uc_ack_lane_cfg_done == 1. <br> 15461 Reset value is 0x7.</td></tr> 15462 </table><p> 15463 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15464 <hr> 15465 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL">TXCOM_CKRST_CTRL_TXCOM_MULTICAST_MASK_CONTROL - TXCOM_MULTICAST_MASK_CONTROL</a></b><br> 15466 Address Offset = 32'h0000_d19a<br> 15467 Physical Address = 32'h0000_d19a<br> 15468 Reset Value = 16'h0000<br> 15469 Access = RW (16-bit only)<br> 15470 <table border=1 align=center width=100% cellpadding=0> 15471 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15472 <tr bgcolor=WHITE> 15473 <td bgcolor=WHITE align=center valign=top>15:01</td> 15474 <td align=left valign=top>RSVD</td> 15475 <td align=left valign=top>Reserved</td> 15476 <td align=left> 15477 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15478 <tr bgcolor=WHITE> 15479 <td bgcolor=WHITE align=center valign=top>00</td> 15480 <td align=left valign=top>WO</td> 15481 <td align=left valign=top>tx_multicast_mask_control</td> 15482 <td align=left> 15483 This masks the lane from a broadcast or multicast write operation. <br> 15484 Reset value is 0x0.</td></tr> 15485 </table><p> 15486 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15487 <hr> 15488 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK">TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK - TXCOM_OSR_MODE_STATUS_MC_MASK</a></b><br> 15489 Address Offset = 32'h0000_d19b<br> 15490 Physical Address = 32'h0000_d19b<br> 15491 Reset Value = 16'h0000<br> 15492 Access = RO (16-bit only)<br> 15493 <table border=1 align=center width=100% cellpadding=0> 15494 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15495 <tr bgcolor=WHITE> 15496 <td bgcolor=WHITE align=center valign=top>15:05</td> 15497 <td align=left valign=top>RSVD</td> 15498 <td align=left valign=top>Reserved</td> 15499 <td align=left> 15500 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15501 <tr bgcolor=WHITE> 15502 <td bgcolor=WHITE align=center valign=top>04</td> 15503 <td align=left valign=top>RO</td> 15504 <td align=left valign=top>tx_multicast_mask_control_status</td> 15505 <td align=left> 15506 Status of multicast mask control for masking lane from multicast write operation. <br> 15507 Reset value is 0x0.</td></tr> 15508 <tr bgcolor=WHITE> 15509 <td bgcolor=WHITE align=center valign=top>03:00</td> 15510 <td align=left valign=top>RO</td> 15511 <td align=left valign=top>tx_osr_mode</td> 15512 <td align=left> 15513 OSR Mode status after the mux. <br> 15514 OSR Mode status after the osr_mode_frc/frc_val mux. <br> 15515 Decoding of this register is as follows. <br> 15516     OSX1          4'd0        <br> 15517     OSX2          4'd1        <br> 15518     OSX3          4'd2        <br> 15519     OSX3P3        4'd3        <br> 15520     OSX4          4'd4        <br> 15521     OSX5          4'd5        <br> 15522     OSX7P5        4'd6        <br> 15523     OSX8          4'd7        <br> 15524     OSX8P25       4'd8        <br> 15525     OSX10         4'd9        <br> 15526 Reset value is 0x0.</td></tr> 15527 </table><p> 15528 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15529 <hr> 15530 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS">TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS - TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS</a></b><br> 15531 Address Offset = 32'h0000_d19c<br> 15532 Physical Address = 32'h0000_d19c<br> 15533 Reset Value = 16'h0000<br> 15534 Access = RO (16-bit only)<br> 15535 <table border=1 align=center width=100% cellpadding=0> 15536 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15537 <tr bgcolor=WHITE> 15538 <td bgcolor=WHITE align=center valign=top>15:04</td> 15539 <td align=left valign=top>RSVD</td> 15540 <td align=left valign=top>Reserved</td> 15541 <td align=left> 15542 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15543 <tr bgcolor=WHITE> 15544 <td bgcolor=WHITE align=center valign=top>03:00</td> 15545 <td align=left valign=top>RO</td> 15546 <td align=left valign=top>tx_osr_mode_pin</td> 15547 <td align=left> 15548 Indicates the status of the pmd_osr_mode input pin. <br> 15549 Decoding of pmd_osr_mode[3:0] pin and osr_mode registers are as follows. <br> 15550     OSX1          4'd0        <br> 15551     OSX2          4'd1        <br> 15552     OSX3          4'd2        <br> 15553     OSX3P3        4'd3        <br> 15554     OSX4          4'd4        <br> 15555     OSX5          4'd5        <br> 15556     OSX7P5        4'd6        <br> 15557     OSX8          4'd7        <br> 15558     OSX8P25       4'd8        <br> 15559     OSX10         4'd9        <br> 15560 Reset value is 0x0.</td></tr> 15561 </table><p> 15562 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15563 <hr> 15564 <b><a NAME="TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL">TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL - TXCOM_LN_S_RSTB_CONTROL</a></b><br> 15565 Address Offset = 32'h0000_d19e<br> 15566 Physical Address = 32'h0000_d19e<br> 15567 Reset Value = 16'h0001<br> 15568 Access = RW (16-bit only)<br> 15569 <table border=1 align=center width=100% cellpadding=0> 15570 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15571 <tr bgcolor=WHITE> 15572 <td bgcolor=WHITE align=center valign=top>15:01</td> 15573 <td align=left valign=top>RSVD</td> 15574 <td align=left valign=top>Reserved</td> 15575 <td align=left> 15576 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15577 <tr bgcolor=WHITE> 15578 <td bgcolor=WHITE align=center valign=top>00</td> 15579 <td align=left valign=top>RW</td> 15580 <td align=left valign=top>tx_ln_s_rstb</td> 15581 <td align=left> 15582 Active Low Lane Soft Reset. If asserted by writing to 1'b0 will reset the registers and datapath for a lane. <br> 15583 This soft reset is equivalent to the hard reset input pin pmd_ln_h_rstb_i. <br> 15584 Reset value is 0x1.</td></tr> 15585 </table><p> 15586 <A HREF="#TXCOM_CKRST_CTRL Registers">Return to TXCOM_CKRST_CTRL: per lane register block [One Copy Per Lane] Table</A><p> 15587 <hr> 15588 <H1><a NAME="TX_TCA Registers">TX_TCA: per lane register block [One Copy Per Lane] Registers</a></H1> 15589 <table border=1 align=center width=100% cellpadding=0> 15590 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 15591 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 15592 <tr> 15593 <td align=center>0xD1A0</td><td><A HREF="#TX_TCA_TX_TCA_CONTROL_0">TX_TCA_TX_TCA_CONTROL_0</A><br>TX TCA Control 0</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ana_tca_power_on_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tca_done_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tca_done_frc</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">tca_timer_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tca_restart</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tca_disable</div> </td> <td align=center>16'h0000</td></tr> 15594 <tr> 15595 <td align=center>0xD1A1</td><td><A HREF="#TX_TCA_TX_TCA_CONTROL_1">TX_TCA_TX_TCA_CONTROL_1</A><br>TX TCA Control 1</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="14"><div class="HT">tca_wait_timer</div> </td> <td align=center>16'h000a</td></tr> 15596 <tr> 15597 <td align=center>0xD1A2</td><td><A HREF="#TX_TCA_TX_TCA_CONTROL_2">TX_TCA_TX_TCA_CONTROL_2</A><br>TX TCA Control 2</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="14"><div class="HT">tca_coarse_timer</div> </td> <td align=center>16'h0d80</td></tr> 15598 <tr> 15599 <td align=center>0xD1A3</td><td><A HREF="#TX_TCA_TX_TCA_CONTROL_3">TX_TCA_TX_TCA_CONTROL_3</A><br>TX TCA Control 3</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="14"><div class="HT">tca_fine_timer</div> </td> <td align=center>16'h0400</td></tr> 15600 <tr> 15601 <td align=center>0xD1A4</td><td><A HREF="#TX_TCA_TX_TCA_CONTROL_4">TX_TCA_TX_TCA_CONTROL_4</A><br>TX TCA Control 4</td><td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">phserr_win_coarse</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">phserr_win_fine</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">fine_done_by_timer</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">coarse_done_by_timer</div> </td> <td align=center>16'h5028</td></tr> 15602 <tr> 15603 <td align=center>0xD1A5</td><td><A HREF="#TX_TCA_TX_PI_OFFSET_CONTROL">TX_TCA_TX_PI_OFFSET_CONTROL</A><br>TX PI Offset Control</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_offset_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">tx_pi_offset_dir</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">tx_pi_shift_num</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">tx_pi_offset_num</div> </td> <td align=center>16'h1801</td></tr> 15604 <tr> 15605 <td align=center>0xD1A6</td><td><A HREF="#TX_TCA_TX_TCA_STATUS">TX_TCA_TX_TCA_STATUS</A><br>TX TCA Status</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">tca_state</div> </td> <td align=center>16'h0000</td></tr> 15606 </table><p> 15607 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 15608 <hr> 15609 <b><a NAME="TX_TCA_TX_TCA_CONTROL_0">TX_TCA_TX_TCA_CONTROL_0 - TX TCA Control 0</a></b><br> 15610 Address Offset = 32'h0000_d1a0<br> 15611 Physical Address = 32'h0000_d1a0<br> 15612 Reset Value = 16'h0000<br> 15613 Access = RW (16-bit only)<br> 15614 <table border=1 align=center width=100% cellpadding=0> 15615 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15616 <tr bgcolor=WHITE> 15617 <td bgcolor=WHITE align=center valign=top>15:07</td> 15618 <td align=left valign=top>RSVD</td> 15619 <td align=left valign=top>Reserved</td> 15620 <td align=left> 15621 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15622 <tr bgcolor=WHITE> 15623 <td bgcolor=WHITE align=center valign=top>06</td> 15624 <td align=left valign=top>RW</td> 15625 <td align=left valign=top>ana_tca_power_on_frc</td> 15626 <td align=left> 15627 Always keep AMS TCA master clock and TX PD power on <br> 15628 Reset value is 0x0.</td></tr> 15629 <tr bgcolor=WHITE> 15630 <td bgcolor=WHITE align=center valign=top>05</td> 15631 <td align=left valign=top>RW</td> 15632 <td align=left valign=top>tca_done_frc_val</td> 15633 <td align=left> 15634 TCA done force value <br> 15635 Reset value is 0x0.</td></tr> 15636 <tr bgcolor=WHITE> 15637 <td bgcolor=WHITE align=center valign=top>04</td> 15638 <td align=left valign=top>RW</td> 15639 <td align=left valign=top>tca_done_frc</td> 15640 <td align=left> 15641 TCA done force<br> 15642 Reset value is 0x0.</td></tr> 15643 <tr bgcolor=WHITE> 15644 <td bgcolor=WHITE align=center valign=top>03:02</td> 15645 <td align=left valign=top>RW</td> 15646 <td align=left valign=top>tca_timer_sel</td> 15647 <td align=left> 15648 Select TCA coarse state timer. <br> 15649 Reset value is 0x0.</td></tr> 15650 <tr bgcolor=WHITE> 15651 <td bgcolor=WHITE align=center valign=top>01</td> 15652 <td align=left valign=top>RW</td> 15653 <td align=left valign=top>tca_restart</td> 15654 <td align=left> 15655 Restart TCA SM. <br> 15656 Reset value is 0x0.</td></tr> 15657 <tr bgcolor=WHITE> 15658 <td bgcolor=WHITE align=center valign=top>00</td> 15659 <td align=left valign=top>RW</td> 15660 <td align=left valign=top>tca_disable</td> 15661 <td align=left> 15662 Disable TCA. <br> 15663 Reset value is 0x0.</td></tr> 15664 </table><p> 15665 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15666 <hr> 15667 <b><a NAME="TX_TCA_TX_TCA_CONTROL_1">TX_TCA_TX_TCA_CONTROL_1 - TX TCA Control 1</a></b><br> 15668 Address Offset = 32'h0000_d1a1<br> 15669 Physical Address = 32'h0000_d1a1<br> 15670 Reset Value = 16'h000a<br> 15671 Access = RW (16-bit only)<br> 15672 <table border=1 align=center width=100% cellpadding=0> 15673 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15674 <tr bgcolor=WHITE> 15675 <td bgcolor=WHITE align=center valign=top>15:14</td> 15676 <td align=left valign=top>RSVD</td> 15677 <td align=left valign=top>Reserved</td> 15678 <td align=left> 15679 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15680 <tr bgcolor=WHITE> 15681 <td bgcolor=WHITE align=center valign=top>13:00</td> 15682 <td align=left valign=top>RW</td> 15683 <td align=left valign=top>tca_wait_timer</td> 15684 <td align=left> 15685 TCA WAIT state timer. Must be greater than 0 <br> 15686 Reset value is 0xa.</td></tr> 15687 </table><p> 15688 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15689 <hr> 15690 <b><a NAME="TX_TCA_TX_TCA_CONTROL_2">TX_TCA_TX_TCA_CONTROL_2 - TX TCA Control 2</a></b><br> 15691 Address Offset = 32'h0000_d1a2<br> 15692 Physical Address = 32'h0000_d1a2<br> 15693 Reset Value = 16'h0d80<br> 15694 Access = RW (16-bit only)<br> 15695 <table border=1 align=center width=100% cellpadding=0> 15696 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15697 <tr bgcolor=WHITE> 15698 <td bgcolor=WHITE align=center valign=top>15:14</td> 15699 <td align=left valign=top>RSVD</td> 15700 <td align=left valign=top>Reserved</td> 15701 <td align=left> 15702 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15703 <tr bgcolor=WHITE> 15704 <td bgcolor=WHITE align=center valign=top>13:00</td> 15705 <td align=left valign=top>RW</td> 15706 <td align=left valign=top>tca_coarse_timer</td> 15707 <td align=left> 15708 TCA COARSE state timer. <br> 15709 Reset value is 0xd80.</td></tr> 15710 </table><p> 15711 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15712 <hr> 15713 <b><a NAME="TX_TCA_TX_TCA_CONTROL_3">TX_TCA_TX_TCA_CONTROL_3 - TX TCA Control 3</a></b><br> 15714 Address Offset = 32'h0000_d1a3<br> 15715 Physical Address = 32'h0000_d1a3<br> 15716 Reset Value = 16'h0400<br> 15717 Access = RW (16-bit only)<br> 15718 <table border=1 align=center width=100% cellpadding=0> 15719 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15720 <tr bgcolor=WHITE> 15721 <td bgcolor=WHITE align=center valign=top>15:14</td> 15722 <td align=left valign=top>RSVD</td> 15723 <td align=left valign=top>Reserved</td> 15724 <td align=left> 15725 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15726 <tr bgcolor=WHITE> 15727 <td bgcolor=WHITE align=center valign=top>13:00</td> 15728 <td align=left valign=top>RW</td> 15729 <td align=left valign=top>tca_fine_timer</td> 15730 <td align=left> 15731 TCA FINE state timer. <br> 15732 Reset value is 0x400.</td></tr> 15733 </table><p> 15734 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15735 <hr> 15736 <b><a NAME="TX_TCA_TX_TCA_CONTROL_4">TX_TCA_TX_TCA_CONTROL_4 - TX TCA Control 4</a></b><br> 15737 Address Offset = 32'h0000_d1a4<br> 15738 Physical Address = 32'h0000_d1a4<br> 15739 Reset Value = 16'h5028<br> 15740 Access = RW (16-bit only)<br> 15741 <table border=1 align=center width=100% cellpadding=0> 15742 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15743 <tr bgcolor=WHITE> 15744 <td bgcolor=WHITE align=center valign=top>15:09</td> 15745 <td align=left valign=top>RW</td> 15746 <td align=left valign=top>phserr_win_coarse</td> 15747 <td align=left> 15748 tx_data_phdet edge detection number in coarse state  . <br> 15749 Reset value is 0x28.</td></tr> 15750 <tr bgcolor=WHITE> 15751 <td bgcolor=WHITE align=center valign=top>08:02</td> 15752 <td align=left valign=top>RW</td> 15753 <td align=left valign=top>phserr_win_fine</td> 15754 <td align=left> 15755 tx_data_phdet edge detection number in fine state  . <br> 15756 Reset value is 0xa.</td></tr> 15757 <tr bgcolor=WHITE> 15758 <td bgcolor=WHITE align=center valign=top>01</td> 15759 <td align=left valign=top>RW</td> 15760 <td align=left valign=top>fine_done_by_timer</td> 15761 <td align=left> 15762 Fine done by timer. <br> 15763 Reset value is 0x0.</td></tr> 15764 <tr bgcolor=WHITE> 15765 <td bgcolor=WHITE align=center valign=top>00</td> 15766 <td align=left valign=top>RW</td> 15767 <td align=left valign=top>coarse_done_by_timer</td> 15768 <td align=left> 15769 Coarse done by timer. <br> 15770 Reset value is 0x0.</td></tr> 15771 </table><p> 15772 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15773 <hr> 15774 <b><a NAME="TX_TCA_TX_PI_OFFSET_CONTROL">TX_TCA_TX_PI_OFFSET_CONTROL - TX PI Offset Control</a></b><br> 15775 Address Offset = 32'h0000_d1a5<br> 15776 Physical Address = 32'h0000_d1a5<br> 15777 Reset Value = 16'h1801<br> 15778 Access = RW (16-bit only)<br> 15779 <table border=1 align=center width=100% cellpadding=0> 15780 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15781 <tr bgcolor=WHITE> 15782 <td bgcolor=WHITE align=center valign=top>15</td> 15783 <td align=left valign=top>RW</td> 15784 <td align=left valign=top>tx_pi_offset_en</td> 15785 <td align=left> 15786 Enable TCA automatically generate TX PI offset to account for the 20T port buffers between quad. <br> 15787 Reset value is 0x0.</td></tr> 15788 <tr bgcolor=WHITE> 15789 <td bgcolor=WHITE align=center valign=top>14</td> 15790 <td align=left valign=top>RW</td> 15791 <td align=left valign=top>tx_pi_offset_dir</td> 15792 <td align=left> 15793 0: Increment. <br> 15794 1: Decrement. <br> 15795 Reset value is 0x0.</td></tr> 15796 <tr bgcolor=WHITE> 15797 <td bgcolor=WHITE align=center valign=top>13:10</td> 15798 <td align=left valign=top>RW</td> 15799 <td align=left valign=top>tx_pi_shift_num</td> 15800 <td align=left> 15801 TX PI shift step number. Minimum = 1.<br> 15802 Reset value is 0x6.</td></tr> 15803 <tr bgcolor=WHITE> 15804 <td bgcolor=WHITE align=center valign=top>09:00</td> 15805 <td align=left valign=top>RW</td> 15806 <td align=left valign=top>tx_pi_offset_num</td> 15807 <td align=left> 15808 TX PI offset step number. Minimum = 1.<br> 15809 Reset value is 0x1.</td></tr> 15810 </table><p> 15811 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15812 <hr> 15813 <b><a NAME="TX_TCA_TX_TCA_STATUS">TX_TCA_TX_TCA_STATUS - TX TCA Status</a></b><br> 15814 Address Offset = 32'h0000_d1a6<br> 15815 Physical Address = 32'h0000_d1a6<br> 15816 Reset Value = 16'h0000<br> 15817 Access = RO (16-bit only)<br> 15818 <table border=1 align=center width=100% cellpadding=0> 15819 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15820 <tr bgcolor=WHITE> 15821 <td bgcolor=WHITE align=center valign=top>15:03</td> 15822 <td align=left valign=top>RSVD</td> 15823 <td align=left valign=top>Reserved</td> 15824 <td align=left> 15825 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15826 <tr bgcolor=WHITE> 15827 <td bgcolor=WHITE align=center valign=top>02:00</td> 15828 <td align=left valign=top>RO</td> 15829 <td align=left valign=top>tca_state</td> 15830 <td align=left> 15831 TCA SM. <br> 15832 Reset value is 0x0.</td></tr> 15833 </table><p> 15834 <A HREF="#TX_TCA Registers">Return to TX_TCA: per lane register block [One Copy Per Lane] Table</A><p> 15835 <hr> 15836 <H1><a NAME="MICRO_A_COM Registers">MICRO_A_COM: common register block for all lanes within each Micro Top Registers</a></H1> 15837 <table border=1 align=center width=100% cellpadding=0> 15838 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 15839 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 15840 <tr> 15841 <td align=center>0xD200</td><td><A HREF="#MICRO_A_COM_CLOCK_CONTROL0">MICRO_A_COM_CLOCK_CONTROL0</A><br>Clock control registers 0</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_core_clk_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_master_clk_en</div> </td> <td align=center>16'h0000</td></tr> 15842 <tr> 15843 <td align=center>0xD201</td><td><A HREF="#MICRO_A_COM_RESET_CONTROL0">MICRO_A_COM_RESET_CONTROL0</A><br>Reset control registers 0</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pram_if_rstb</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_core_rstb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_master_rstb</div> </td> <td align=center>16'h0000</td></tr> 15844 <tr> 15845 <td align=center>0xD202</td><td><A HREF="#MICRO_A_COM_AHB_CONTROL0">MICRO_A_COM_AHB_CONTROL0</A><br>rmi to ahb control registers 0</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_autoinc_rdaddr_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_autoinc_wraddr_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">micro_ra_init</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">micro_ra_rddatasize</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">micro_ra_wrdatasize</div> </td> <td align=center>16'h0000</td></tr> 15846 <tr> 15847 <td align=center>0xD203</td><td><A HREF="#MICRO_A_COM_AHB_STATUS0">MICRO_A_COM_AHB_STATUS0</A><br>rmi to ahb status registers 0</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_ra_initdone</div> </td> <td align=center>16'h0000</td></tr> 15848 <tr> 15849 <td align=center>0xD204</td><td><A HREF="#MICRO_A_COM_AHB_WRADDR_LSW">MICRO_A_COM_AHB_WRADDR_LSW</A><br>rmi to ahb write address LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_wraddr_lsw</div> </td> <td align=center>16'h0000</td></tr> 15850 <tr> 15851 <td align=center>0xD205</td><td><A HREF="#MICRO_A_COM_AHB_WRADDR_MSW">MICRO_A_COM_AHB_WRADDR_MSW</A><br>rmi to ahb write address MSW (bits 31:16) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_wraddr_msw</div> </td> <td align=center>16'h0000</td></tr> 15852 <tr> 15853 <td align=center>0xD206</td><td><A HREF="#MICRO_A_COM_AHB_WRDATA_LSW">MICRO_A_COM_AHB_WRDATA_LSW</A><br>rmi to ahb write data LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_wrdata_lsw</div> </td> <td align=center>16'h0000</td></tr> 15854 <tr> 15855 <td align=center>0xD207</td><td><A HREF="#MICRO_A_COM_AHB_WRDATA_MSW">MICRO_A_COM_AHB_WRDATA_MSW</A><br>rmi to ahb write data MSW (bits 31:16) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_wrdata_msw</div> </td> <td align=center>16'h0000</td></tr> 15856 <tr> 15857 <td align=center>0xD208</td><td><A HREF="#MICRO_A_COM_AHB_RDADDR_LSW">MICRO_A_COM_AHB_RDADDR_LSW</A><br>rmi to ahb read address LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_rdaddr_lsw</div> </td> <td align=center>16'h0000</td></tr> 15858 <tr> 15859 <td align=center>0xD209</td><td><A HREF="#MICRO_A_COM_AHB_RDADDR_MSW">MICRO_A_COM_AHB_RDADDR_MSW</A><br>rmi to ahb read address MSW (bits 31:16) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_rdaddr_msw</div> </td> <td align=center>16'h0000</td></tr> 15860 <tr> 15861 <td align=center>0xD20A</td><td><A HREF="#MICRO_A_COM_AHB_RDDATA_LSW">MICRO_A_COM_AHB_RDDATA_LSW</A><br>rmi to ahb read data LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_rddata_lsw</div> </td> <td align=center>16'h0000</td></tr> 15862 <tr> 15863 <td align=center>0xD20B</td><td><A HREF="#MICRO_A_COM_AHB_RDDATA_MSW">MICRO_A_COM_AHB_RDDATA_MSW</A><br>rmi to ahb read data MSW (bits 31:16) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_rddata_msw</div> </td> <td align=center>16'h0000</td></tr> 15864 <tr> 15865 <td align=center>0xD20C</td><td><A HREF="#MICRO_A_COM_PRAMIF_CONTROL0">MICRO_A_COM_PRAMIF_CONTROL0</A><br>pram i/f to ahb control registers 0</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pramif_en</div> </td> <td align=center>16'h0000</td></tr> 15866 <tr> 15867 <td align=center>0xD20D</td><td><A HREF="#MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW">MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW</A><br>pram i/f to ahb write address LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="14"><div class="HT">micro_pramif_ahb_wraddr_lsw</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td align=center>16'h0000</td></tr> 15868 <tr> 15869 <td align=center>0xD20E</td><td><A HREF="#MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW">MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW</A><br>pram i/f to ahb write address MSW (bits 31:16) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_pramif_ahb_wraddr_msw</div> </td> <td align=center>16'h0000</td></tr> 15870 </table><p> 15871 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 15872 <hr> 15873 <b><a NAME="MICRO_A_COM_CLOCK_CONTROL0">MICRO_A_COM_CLOCK_CONTROL0 - Clock control registers 0</a></b><br> 15874 Address Offset = 32'h0000_d200<br> 15875 Physical Address = 32'h0000_d200<br> 15876 Reset Value = 16'h0000<br> 15877 Access = RW (16-bit only)<br> 15878 <table border=1 align=center width=100% cellpadding=0> 15879 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15880 <tr bgcolor=WHITE> 15881 <td bgcolor=WHITE align=center valign=top>15:02</td> 15882 <td align=left valign=top>RSVD</td> 15883 <td align=left valign=top>Reserved</td> 15884 <td align=left> 15885 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15886 <tr bgcolor=WHITE> 15887 <td bgcolor=WHITE align=center valign=top>01</td> 15888 <td align=left valign=top>RW</td> 15889 <td align=left valign=top>micro_core_clk_en</td> 15890 <td align=left> 15891 micro core clock enable (m0):<br> 15892 While the micro-code is being loaded into the code RAM, the clock to <br> 15893 micro_core (m0) is normally disabled and a reset is asserted<br> 15894 0 - disabled <br> 15895 1 - enables <br> 15896 Reset value is 0.</td></tr> 15897 <tr bgcolor=WHITE> 15898 <td bgcolor=WHITE align=center valign=top>00</td> 15899 <td align=left valign=top>RW</td> 15900 <td align=left valign=top>micro_master_clk_en</td> 15901 <td align=left> 15902 master clock enable:<br> 15903 By default the clock to micro sub-system is disabled and <br> 15904 only the micro control and status registers can be accessed through<br> 15905 the RMIC interface. Setting this field to 1'b1 enable the master clock<br> 15906 <br> 15907 0 - disabled <br> 15908 1 - enables <br> 15909 Reset value is 0.</td></tr> 15910 </table><p> 15911 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 15912 <hr> 15913 <b><a NAME="MICRO_A_COM_RESET_CONTROL0">MICRO_A_COM_RESET_CONTROL0 - Reset control registers 0</a></b><br> 15914 Address Offset = 32'h0000_d201<br> 15915 Physical Address = 32'h0000_d201<br> 15916 Reset Value = 16'h0000<br> 15917 Access = RW (16-bit only)<br> 15918 <table border=1 align=center width=100% cellpadding=0> 15919 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15920 <tr bgcolor=WHITE> 15921 <td bgcolor=WHITE align=center valign=top>15:04</td> 15922 <td align=left valign=top>RSVD</td> 15923 <td align=left valign=top>Reserved</td> 15924 <td align=left> 15925 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15926 <tr bgcolor=WHITE> 15927 <td bgcolor=WHITE align=center valign=top>03</td> 15928 <td align=left valign=top>RW</td> 15929 <td align=left valign=top>micro_pram_if_rstb</td> 15930 <td align=left> 15931 PRAM interface reset :<br> 15932 By default a reset to the PRAM interface is asserted, and  <br> 15933 only the micro control and status registers can be accessed through<br> 15934 the RMIC interface. Setting this field to 1'b1 de-assert a reset to the PRAM interface <br> 15935 0 - asserted <br> 15936 1 - de-asserted <br> 15937 Reset value is 0.</td></tr> 15938 <tr bgcolor=WHITE> 15939 <td bgcolor=WHITE align=center valign=top>02</td> 15940 <td align=left valign=top>RSVD</td> 15941 <td align=left valign=top>Reserved</td> 15942 <td align=left> 15943 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 15944 <tr bgcolor=WHITE> 15945 <td bgcolor=WHITE align=center valign=top>01</td> 15946 <td align=left valign=top>RW</td> 15947 <td align=left valign=top>micro_core_rstb</td> 15948 <td align=left> 15949 micro core reset (m0):<br> 15950 While the micro-code is being loaded into the code RAM, the clock to <br> 15951 micro_core (m0) is normally disabled and a reset is asserted.<br> 15952 Setting this field to 1'b1 de-asserts a reset to the micro.<br> 15953 0 - disabled <br> 15954 1 - enables <br> 15955 Reset value is 0.</td></tr> 15956 <tr bgcolor=WHITE> 15957 <td bgcolor=WHITE align=center valign=top>00</td> 15958 <td align=left valign=top>RW</td> 15959 <td align=left valign=top>micro_master_rstb</td> 15960 <td align=left> 15961 master reset :<br> 15962 By default a reset to micro controller sub-system is asserted, and  <br> 15963 only the micro control and status registers can be accessed through<br> 15964 the RMIC interface. Setting this field to 1'b1 de-assert a reset to the micro-subsystem<br> 15965 <br> 15966 0 - asserted <br> 15967 1 - de-asserted <br> 15968 Reset value is 0.</td></tr> 15969 </table><p> 15970 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 15971 <hr> 15972 <b><a NAME="MICRO_A_COM_AHB_CONTROL0">MICRO_A_COM_AHB_CONTROL0 - rmi to ahb control registers 0</a></b><br> 15973 Address Offset = 32'h0000_d202<br> 15974 Physical Address = 32'h0000_d202<br> 15975 Reset Value = 16'h0000<br> 15976 Access = RW (16-bit only)<br> 15977 <table border=1 align=center width=100% cellpadding=0> 15978 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 15979 <tr bgcolor=WHITE> 15980 <td bgcolor=WHITE align=center valign=top>15:14</td> 15981 <td align=left valign=top>RSVD</td> 15982 <td align=left valign=top>Reserved</td> 15983 <td align=left> 15984 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 15985 <tr bgcolor=WHITE> 15986 <td bgcolor=WHITE align=center valign=top>13</td> 15987 <td align=left valign=top>RW</td> 15988 <td align=left valign=top>micro_autoinc_rdaddr_en</td> 15989 <td align=left> 15990 Automatic increment read address enable <br> 15991 0 - disabled, micro_ra_rdaddr_lsw and micro_ra_rdaddr_msw field specify the constant address <br> 15992     where the data is read via the micro_ra_rddata_msw and micro_ra_rddata_lsw fileds<br> 15993     <br> 15994 1 - enabled, micro_ra_rdaddr_lsw and micro_ra_rdaddr_msw field specify the start address <br> 15995     where the data is read via the micro_ra_rddata_msw and micro_ra_rddata_lsw fileds<br> 15996     the address automatically increments based on the micro_ra_rddatasize field after <br> 15997     the read has been performed <br> 15998 Reset value is 0.</td></tr> 15999 <tr bgcolor=WHITE> 16000 <td bgcolor=WHITE align=center valign=top>12</td> 16001 <td align=left valign=top>RW</td> 16002 <td align=left valign=top>micro_autoinc_wraddr_en</td> 16003 <td align=left> 16004 Automatic increment write address enable <br> 16005 0 - disabled, micro_ra_wraddr_lsw and micro_ra_wraddr_msw field specify the constant address <br> 16006     where the data from the micro_ra_wrdata_msw and micro_ra_wrdata_lsw is written.<br> 16007     <br> 16008 1 - enabled, micro_ra_wraddr_lsw and micro_ra_wraddr_msw field specify the start address <br> 16009     where the data from the micro_ra_wrdata_msw and micro_ra_wrdata_lsw is written.<br> 16010     the address automatically increments based on the micro_ra_wrdatasize field after <br> 16011     the write has been performed <br> 16012 Reset value is 0.</td></tr> 16013 <tr bgcolor=WHITE> 16014 <td bgcolor=WHITE align=center valign=top>11:10</td> 16015 <td align=left valign=top>RSVD</td> 16016 <td align=left valign=top>Reserved</td> 16017 <td align=left> 16018 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16019 <tr bgcolor=WHITE> 16020 <td bgcolor=WHITE align=center valign=top>09:08</td> 16021 <td align=left valign=top>RW</td> 16022 <td align=left valign=top>micro_ra_init</td> 16023 <td align=left> 16024 Intialize code/data RAM<br> 16025 2'b01: initailize code RAM - write zeroes to all locations<br> 16026 2'b10: initialize data RAM - write zeroes to all loactions<br> 16027 2'b00, 2'b11: ignored<br> 16028 Reset value is 0.</td></tr> 16029 <tr bgcolor=WHITE> 16030 <td bgcolor=WHITE align=center valign=top>07:06</td> 16031 <td align=left valign=top>RSVD</td> 16032 <td align=left valign=top>Reserved</td> 16033 <td align=left> 16034 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16035 <tr bgcolor=WHITE> 16036 <td bgcolor=WHITE align=center valign=top>05:04</td> 16037 <td align=left valign=top>RW</td> 16038 <td align=left valign=top>micro_ra_rddatasize</td> 16039 <td align=left> 16040 read data size select <br> 16041 'd0 : 8-bit    <br> 16042 'd1 : 16-bit   <br> 16043 'd2 : 32-bit   <br> 16044 'd3 : reserved <br> 16045 Reset value is 0.</td></tr> 16046 <tr bgcolor=WHITE> 16047 <td bgcolor=WHITE align=center valign=top>03:02</td> 16048 <td align=left valign=top>RSVD</td> 16049 <td align=left valign=top>Reserved</td> 16050 <td align=left> 16051 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16052 <tr bgcolor=WHITE> 16053 <td bgcolor=WHITE align=center valign=top>01:00</td> 16054 <td align=left valign=top>RW</td> 16055 <td align=left valign=top>micro_ra_wrdatasize</td> 16056 <td align=left> 16057 write data size select <br> 16058 'd0 : 8-bit    <br> 16059 'd1 : 16-bit   <br> 16060 'd2 : 32-bit   <br> 16061 'd3 : reserved <br> 16062 Reset value is 0.</td></tr> 16063 </table><p> 16064 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16065 <hr> 16066 <b><a NAME="MICRO_A_COM_AHB_STATUS0">MICRO_A_COM_AHB_STATUS0 - rmi to ahb status registers 0</a></b><br> 16067 Address Offset = 32'h0000_d203<br> 16068 Physical Address = 32'h0000_d203<br> 16069 Reset Value = 16'h0000<br> 16070 Access = RO (16-bit only)<br> 16071 <table border=1 align=center width=100% cellpadding=0> 16072 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16073 <tr bgcolor=WHITE> 16074 <td bgcolor=WHITE align=center valign=top>15:01</td> 16075 <td align=left valign=top>RSVD</td> 16076 <td align=left valign=top>Reserved</td> 16077 <td align=left> 16078 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16079 <tr bgcolor=WHITE> 16080 <td bgcolor=WHITE align=center valign=top>00</td> 16081 <td align=left valign=top>RO</td> 16082 <td align=left valign=top>micro_ra_initdone</td> 16083 <td align=left> 16084 When this bit is set, it indicate that code/data RAM initialization process is complete<br> 16085 This reamins set until <br> 16086 Reset value is 0.</td></tr> 16087 </table><p> 16088 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16089 <hr> 16090 <b><a NAME="MICRO_A_COM_AHB_WRADDR_LSW">MICRO_A_COM_AHB_WRADDR_LSW - rmi to ahb write address LSW (bits 15:0) register</a></b><br> 16091 Address Offset = 32'h0000_d204<br> 16092 Physical Address = 32'h0000_d204<br> 16093 Reset Value = 16'h0000<br> 16094 Access = RW (16-bit only)<br> 16095 <table border=1 align=center width=100% cellpadding=0> 16096 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16097 <tr bgcolor=WHITE> 16098 <td bgcolor=WHITE align=center valign=top>15:00</td> 16099 <td align=left valign=top>RW</td> 16100 <td align=left valign=top>micro_ra_wraddr_lsw</td> 16101 <td align=left> 16102 These bits are used to generate the lower 16-bits of the address on the AHB-Lite bus during write transactions<br> 16103 bit 0 is not used during 16-bit transactions and <br> 16104 bits[1:0] are not used during 32-bit transactions <br> 16105 Reset value is 0.</td></tr> 16106 </table><p> 16107 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16108 <hr> 16109 <b><a NAME="MICRO_A_COM_AHB_WRADDR_MSW">MICRO_A_COM_AHB_WRADDR_MSW - rmi to ahb write address MSW (bits 31:16) register</a></b><br> 16110 Address Offset = 32'h0000_d205<br> 16111 Physical Address = 32'h0000_d205<br> 16112 Reset Value = 16'h0000<br> 16113 Access = RW (16-bit only)<br> 16114 <table border=1 align=center width=100% cellpadding=0> 16115 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16116 <tr bgcolor=WHITE> 16117 <td bgcolor=WHITE align=center valign=top>15:00</td> 16118 <td align=left valign=top>RW</td> 16119 <td align=left valign=top>micro_ra_wraddr_msw</td> 16120 <td align=left> 16121 These bits are used to generate the upper 16-bits of the address on the AHB-Lite bus during write transactions<br> 16122 Reset value is 0.</td></tr> 16123 </table><p> 16124 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16125 <hr> 16126 <b><a NAME="MICRO_A_COM_AHB_WRDATA_LSW">MICRO_A_COM_AHB_WRDATA_LSW - rmi to ahb write data LSW (bits 15:0) register</a></b><br> 16127 Address Offset = 32'h0000_d206<br> 16128 Physical Address = 32'h0000_d206<br> 16129 Reset Value = 16'h0000<br> 16130 Access = RW (16-bit only)<br> 16131 <table border=1 align=center width=100% cellpadding=0> 16132 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16133 <tr bgcolor=WHITE> 16134 <td bgcolor=WHITE align=center valign=top>15:00</td> 16135 <td align=left valign=top>RW</td> 16136 <td align=left valign=top>micro_ra_wrdata_lsw</td> 16137 <td align=left> 16138 These bits are used to generate the lower 16-bits of the data on the AHB-Lite bus during write transactions<br> 16139 Write transaction on the AHB-Lite is initiated when this register is written <br> 16140 Reset value is 0.</td></tr> 16141 </table><p> 16142 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16143 <hr> 16144 <b><a NAME="MICRO_A_COM_AHB_WRDATA_MSW">MICRO_A_COM_AHB_WRDATA_MSW - rmi to ahb write data MSW (bits 31:16) register</a></b><br> 16145 Address Offset = 32'h0000_d207<br> 16146 Physical Address = 32'h0000_d207<br> 16147 Reset Value = 16'h0000<br> 16148 Access = RW (16-bit only)<br> 16149 <table border=1 align=center width=100% cellpadding=0> 16150 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16151 <tr bgcolor=WHITE> 16152 <td bgcolor=WHITE align=center valign=top>15:00</td> 16153 <td align=left valign=top>RW</td> 16154 <td align=left valign=top>micro_ra_wrdata_msw</td> 16155 <td align=left> 16156 These bits are used  to generate the upper 16-bits of the data on the AHB-Lite bus during write transactions<br> 16157 Reset value is 0.</td></tr> 16158 </table><p> 16159 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16160 <hr> 16161 <b><a NAME="MICRO_A_COM_AHB_RDADDR_LSW">MICRO_A_COM_AHB_RDADDR_LSW - rmi to ahb read address LSW (bits 15:0) register</a></b><br> 16162 Address Offset = 32'h0000_d208<br> 16163 Physical Address = 32'h0000_d208<br> 16164 Reset Value = 16'h0000<br> 16165 Access = RW (16-bit only)<br> 16166 <table border=1 align=center width=100% cellpadding=0> 16167 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16168 <tr bgcolor=WHITE> 16169 <td bgcolor=WHITE align=center valign=top>15:00</td> 16170 <td align=left valign=top>RW</td> 16171 <td align=left valign=top>micro_ra_rdaddr_lsw</td> 16172 <td align=left> 16173 These bits are used to generate the lower 16-bits of the address on the AHB-Lite bus during read transactions<br> 16174 bit 0 is not used during 16-bit transactions and <br> 16175 bits[1:0] are not used during 32-bit transactions <br> 16176 Read transaction is initiated on the AHB-Lite when this register is written <br> 16177 Reset value is 0.</td></tr> 16178 </table><p> 16179 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16180 <hr> 16181 <b><a NAME="MICRO_A_COM_AHB_RDADDR_MSW">MICRO_A_COM_AHB_RDADDR_MSW - rmi to ahb read address MSW (bits 31:16) register</a></b><br> 16182 Address Offset = 32'h0000_d209<br> 16183 Physical Address = 32'h0000_d209<br> 16184 Reset Value = 16'h0000<br> 16185 Access = RW (16-bit only)<br> 16186 <table border=1 align=center width=100% cellpadding=0> 16187 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16188 <tr bgcolor=WHITE> 16189 <td bgcolor=WHITE align=center valign=top>15:00</td> 16190 <td align=left valign=top>RW</td> 16191 <td align=left valign=top>micro_ra_rdaddr_msw</td> 16192 <td align=left> 16193 These bits are used by to generate the upper 16-bits of the address on the AHB-Lite bus during read transactions<br> 16194 Reset value is 0.</td></tr> 16195 </table><p> 16196 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16197 <hr> 16198 <b><a NAME="MICRO_A_COM_AHB_RDDATA_LSW">MICRO_A_COM_AHB_RDDATA_LSW - rmi to ahb read data LSW (bits 15:0) register</a></b><br> 16199 Address Offset = 32'h0000_d20a<br> 16200 Physical Address = 32'h0000_d20a<br> 16201 Reset Value = 16'h0000<br> 16202 Access = RO (16-bit only)<br> 16203 <table border=1 align=center width=100% cellpadding=0> 16204 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16205 <tr bgcolor=WHITE> 16206 <td bgcolor=WHITE align=center valign=top>15:00</td> 16207 <td align=left valign=top>RO</td> 16208 <td align=left valign=top>micro_ra_rddata_lsw</td> 16209 <td align=left> 16210 These are the lower 16-bits of the read data from the AHB-Lite slave device <br> 16211 Read transaction is initiated on the AHB-Lite when this register is read <br> 16212 Reset value is 0.</td></tr> 16213 </table><p> 16214 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16215 <hr> 16216 <b><a NAME="MICRO_A_COM_AHB_RDDATA_MSW">MICRO_A_COM_AHB_RDDATA_MSW - rmi to ahb read data MSW (bits 31:16) register</a></b><br> 16217 Address Offset = 32'h0000_d20b<br> 16218 Physical Address = 32'h0000_d20b<br> 16219 Reset Value = 16'h0000<br> 16220 Access = RO (16-bit only)<br> 16221 <table border=1 align=center width=100% cellpadding=0> 16222 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16223 <tr bgcolor=WHITE> 16224 <td bgcolor=WHITE align=center valign=top>15:00</td> 16225 <td align=left valign=top>RO</td> 16226 <td align=left valign=top>micro_ra_rddata_msw</td> 16227 <td align=left> 16228 These are the upper 16-bits of the read data from the AHB-Lite slave device <br> 16229 Reset value is 0.</td></tr> 16230 </table><p> 16231 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16232 <hr> 16233 <b><a NAME="MICRO_A_COM_PRAMIF_CONTROL0">MICRO_A_COM_PRAMIF_CONTROL0 - pram i/f to ahb control registers 0</a></b><br> 16234 Address Offset = 32'h0000_d20c<br> 16235 Physical Address = 32'h0000_d20c<br> 16236 Reset Value = 16'h0000<br> 16237 Access = RW (16-bit only)<br> 16238 <table border=1 align=center width=100% cellpadding=0> 16239 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16240 <tr bgcolor=WHITE> 16241 <td bgcolor=WHITE align=center valign=top>15:01</td> 16242 <td align=left valign=top>RSVD</td> 16243 <td align=left valign=top>Reserved</td> 16244 <td align=left> 16245 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16246 <tr bgcolor=WHITE> 16247 <td bgcolor=WHITE align=center valign=top>00</td> 16248 <td align=left valign=top>RW</td> 16249 <td align=left valign=top>micro_pramif_en</td> 16250 <td align=left> 16251 When this bit is set, pram if interface can generate write transactions on the  <br> 16252 AHB-Lite bus, the start address of the transaction is specifield <br> 16253 in the pramif_ahb_wraddr_lsw and pramif_ahb_wraddr_msw fields <br> 16254 Reset value is 0.</td></tr> 16255 </table><p> 16256 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16257 <hr> 16258 <b><a NAME="MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW">MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW - pram i/f to ahb write address LSW (bits 15:0) register</a></b><br> 16259 Address Offset = 32'h0000_d20d<br> 16260 Physical Address = 32'h0000_d20d<br> 16261 Reset Value = 16'h0000<br> 16262 Access = RW (16-bit only)<br> 16263 <table border=1 align=center width=100% cellpadding=0> 16264 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16265 <tr bgcolor=WHITE> 16266 <td bgcolor=WHITE align=center valign=top>15:02</td> 16267 <td align=left valign=top>RW</td> 16268 <td align=left valign=top>micro_pramif_ahb_wraddr_lsw</td> 16269 <td align=left> 16270 These bits are used to generate the lower 14-bits of the address on the AHB-Lite bus during pram interface write transactions<br> 16271 bits[1:0] are not used for 32 transactions <br> 16272 Reset value is 0.</td></tr> 16273 <tr bgcolor=WHITE> 16274 <td bgcolor=WHITE align=center valign=top>01:00</td> 16275 <td align=left valign=top>RSVD</td> 16276 <td align=left valign=top>Reserved</td> 16277 <td align=left> 16278 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16279 </table><p> 16280 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16281 <hr> 16282 <b><a NAME="MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW">MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW - pram i/f to ahb write address MSW (bits 31:16) register</a></b><br> 16283 Address Offset = 32'h0000_d20e<br> 16284 Physical Address = 32'h0000_d20e<br> 16285 Reset Value = 16'h0000<br> 16286 Access = RW (16-bit only)<br> 16287 <table border=1 align=center width=100% cellpadding=0> 16288 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16289 <tr bgcolor=WHITE> 16290 <td bgcolor=WHITE align=center valign=top>15:00</td> 16291 <td align=left valign=top>RW</td> 16292 <td align=left valign=top>micro_pramif_ahb_wraddr_msw</td> 16293 <td align=left> 16294 These bits are used to generate the upper 16-bits of the address on the AHB-Lite bus during pram interface write transactions<br> 16295 Reset value is 0.</td></tr> 16296 </table><p> 16297 <A HREF="#MICRO_A_COM Registers">Return to MICRO_A_COM: common register block for all lanes within each Micro Top Table</A><p> 16298 <hr> 16299 <H1><a NAME="MICRO_B_COM Registers">MICRO_B_COM: common register block for all lanes within each Micro Top Registers</a></H1> 16300 <table border=1 align=center width=100% cellpadding=0> 16301 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 16302 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 16303 <tr> 16304 <td align=center>0xD210</td><td><A HREF="#MICRO_B_COM_PVT_STATUS0">MICRO_B_COM_PVT_STATUS0</A><br>pvt temperature status register 0</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">micro_pvt_tempdata_rmi</div> </td> <td align=center>16'h0000</td></tr> 16305 <tr> 16306 <td align=center>0xD211</td><td><A HREF="#MICRO_B_COM_RMI_TO_MICRO_MBOX0">MICRO_B_COM_RMI_TO_MICRO_MBOX0</A><br>rmi to micro mailbox register 0</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_rmi_to_micro_mbox0</div> </td> <td align=center>16'h0000</td></tr> 16307 <tr> 16308 <td align=center>0xD212</td><td><A HREF="#MICRO_B_COM_RMI_TO_MICRO_MBOX1">MICRO_B_COM_RMI_TO_MICRO_MBOX1</A><br>rmi to micro mailbox register 1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_rmi_to_micro_mbox1</div> </td> <td align=center>16'h0000</td></tr> 16309 <tr> 16310 <td align=center>0xD213</td><td><A HREF="#MICRO_B_COM_MICRO_TO_RMI_MBOX0">MICRO_B_COM_MICRO_TO_RMI_MBOX0</A><br>micro to rmi mailbox register 0</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_to_rmi_mbox0</div> </td> <td align=center>16'h0000</td></tr> 16311 <tr> 16312 <td align=center>0xD214</td><td><A HREF="#MICRO_B_COM_MICRO_TO_RMI_MBOX1">MICRO_B_COM_MICRO_TO_RMI_MBOX1</A><br>micro to rmi mailbox register 1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_to_rmi_mbox1</div> </td> <td align=center>16'h0000</td></tr> 16313 <tr> 16314 <td align=center>0xD215</td><td><A HREF="#MICRO_B_COM_RMI_MBOX_CONTROL0">MICRO_B_COM_RMI_MBOX_CONTROL0</A><br>rmi mailbox control register 0</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_gen_intr_rmi_mbox1wr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_gen_intr_rmi_mbox0wr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_mbox_send_msgin</div> </td> <td align=center>16'h0000</td></tr> 16315 <tr> 16316 <td align=center>0xD216</td><td><A HREF="#MICRO_B_COM_RMI_AHB_CONTROL1">MICRO_B_COM_RMI_AHB_CONTROL1</A><br>ahb control register 1</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_ext_ack_timeout_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_ack_timeout_dis</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_sw_pmi_hp_ext_rstb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_sw_pmi_hp_rstb</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_m0_hresp_en</div> </td> <td align=center>16'h0007</td></tr> 16317 <tr> 16318 <td align=center>0xD217</td><td><A HREF="#MICRO_B_COM_RMI_AHB_STATUS1">MICRO_B_COM_RMI_AHB_STATUS1</A><br>ahb status register 1</td><td bgcolor=#CCCCCC align=center colspan="13"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pr_default_slave_error</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_default_slave_error</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_m0_default_slave_error</div> </td> <td align=center>16'h0000</td></tr> 16319 <tr> 16320 <td align=center>0xD218</td><td><A HREF="#MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW">MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW</A><br>rmi to ahb auto-incremented write address LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_autoinc_nxt_wraddr_lsw</div> </td> <td align=center>16'h0000</td></tr> 16321 <tr> 16322 <td align=center>0xD219</td><td><A HREF="#MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW">MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW</A><br>rmi to ahb auto-incremented read address LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_ra_autoinc_nxt_rdaddr_lsw</div> </td> <td align=center>16'h0000</td></tr> 16323 <tr> 16324 <td align=center>0xD21A</td><td><A HREF="#MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW">MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW</A><br>pram i/f to ahb auto-incremented write address LSW (bits 15:0) register</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_pr_autoinc_nxt_wraddr_lsw</div> </td> <td align=center>16'h0000</td></tr> 16325 <tr> 16326 <td align=center>0xD21B</td><td><A HREF="#MICRO_B_COM_RMI_PVT_CONTROL0">MICRO_B_COM_RMI_PVT_CONTROL0</A><br>rmi pvt temperature control register 0</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pvt_tempdata_frc</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">micro_pvt_tempdata_frcval</div> </td> <td align=center>16'h0000</td></tr> 16327 </table><p> 16328 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 16329 <hr> 16330 <b><a NAME="MICRO_B_COM_PVT_STATUS0">MICRO_B_COM_PVT_STATUS0 - pvt temperature status register 0</a></b><br> 16331 Address Offset = 32'h0000_d210<br> 16332 Physical Address = 32'h0000_d210<br> 16333 Reset Value = 16'h0000<br> 16334 Access = RO (16-bit only)<br> 16335 <table border=1 align=center width=100% cellpadding=0> 16336 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16337 <tr bgcolor=WHITE> 16338 <td bgcolor=WHITE align=center valign=top>15:10</td> 16339 <td align=left valign=top>RSVD</td> 16340 <td align=left valign=top>Reserved</td> 16341 <td align=left> 16342 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16343 <tr bgcolor=WHITE> 16344 <td bgcolor=WHITE align=center valign=top>09:00</td> 16345 <td align=left valign=top>RO</td> 16346 <td align=left valign=top>micro_pvt_tempdata_rmi</td> 16347 <td align=left> 16348    temperature data <br> 16349    {6'd0,tempearture_data[9:0]} <br> 16350    reads the current value of the temperature data capatured <br> 16351 Reset value is 0.</td></tr> 16352 </table><p> 16353 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16354 <hr> 16355 <b><a NAME="MICRO_B_COM_RMI_TO_MICRO_MBOX0">MICRO_B_COM_RMI_TO_MICRO_MBOX0 - rmi to micro mailbox register 0</a></b><br> 16356 Address Offset = 32'h0000_d211<br> 16357 Physical Address = 32'h0000_d211<br> 16358 Reset Value = 16'h0000<br> 16359 Access = RW (16-bit only)<br> 16360 <table border=1 align=center width=100% cellpadding=0> 16361 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16362 <tr bgcolor=WHITE> 16363 <td bgcolor=WHITE align=center valign=top>15:00</td> 16364 <td align=left valign=top>RW</td> 16365 <td align=left valign=top>micro_rmi_to_micro_mbox0</td> 16366 <td align=left> 16367 There bits represents bits [15:0] of the message from rmi to micro <br> 16368 Write to this registers can optionaly generate an interrupt to the micro <br> 16369 Reset value is 0.</td></tr> 16370 </table><p> 16371 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16372 <hr> 16373 <b><a NAME="MICRO_B_COM_RMI_TO_MICRO_MBOX1">MICRO_B_COM_RMI_TO_MICRO_MBOX1 - rmi to micro mailbox register 1</a></b><br> 16374 Address Offset = 32'h0000_d212<br> 16375 Physical Address = 32'h0000_d212<br> 16376 Reset Value = 16'h0000<br> 16377 Access = RW (16-bit only)<br> 16378 <table border=1 align=center width=100% cellpadding=0> 16379 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16380 <tr bgcolor=WHITE> 16381 <td bgcolor=WHITE align=center valign=top>15:00</td> 16382 <td align=left valign=top>RW</td> 16383 <td align=left valign=top>micro_rmi_to_micro_mbox1</td> 16384 <td align=left> 16385 There bits represents bits [31:16] of the message from rmi to micro <br> 16386 Reset value is 0.</td></tr> 16387 </table><p> 16388 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16389 <hr> 16390 <b><a NAME="MICRO_B_COM_MICRO_TO_RMI_MBOX0">MICRO_B_COM_MICRO_TO_RMI_MBOX0 - micro to rmi mailbox register 0</a></b><br> 16391 Address Offset = 32'h0000_d213<br> 16392 Physical Address = 32'h0000_d213<br> 16393 Reset Value = 16'h0000<br> 16394 Access = RO (16-bit only)<br> 16395 <table border=1 align=center width=100% cellpadding=0> 16396 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16397 <tr bgcolor=WHITE> 16398 <td bgcolor=WHITE align=center valign=top>15:00</td> 16399 <td align=left valign=top>RO</td> 16400 <td align=left valign=top>micro_to_rmi_mbox0</td> 16401 <td align=left> 16402 There bits represents bits [15:0] of the message from rmi to micro <br> 16403 Reset value is 0.</td></tr> 16404 </table><p> 16405 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16406 <hr> 16407 <b><a NAME="MICRO_B_COM_MICRO_TO_RMI_MBOX1">MICRO_B_COM_MICRO_TO_RMI_MBOX1 - micro to rmi mailbox register 1</a></b><br> 16408 Address Offset = 32'h0000_d214<br> 16409 Physical Address = 32'h0000_d214<br> 16410 Reset Value = 16'h0000<br> 16411 Access = RO (16-bit only)<br> 16412 <table border=1 align=center width=100% cellpadding=0> 16413 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16414 <tr bgcolor=WHITE> 16415 <td bgcolor=WHITE align=center valign=top>15:00</td> 16416 <td align=left valign=top>RO</td> 16417 <td align=left valign=top>micro_to_rmi_mbox1</td> 16418 <td align=left> 16419 There bits represents bits [31:16] of the message from rmi to micro <br> 16420 Reset value is 0.</td></tr> 16421 </table><p> 16422 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16423 <hr> 16424 <b><a NAME="MICRO_B_COM_RMI_MBOX_CONTROL0">MICRO_B_COM_RMI_MBOX_CONTROL0 - rmi mailbox control register 0</a></b><br> 16425 Address Offset = 32'h0000_d215<br> 16426 Physical Address = 32'h0000_d215<br> 16427 Reset Value = 16'h0000<br> 16428 Access = RW (16-bit only)<br> 16429 <table border=1 align=center width=100% cellpadding=0> 16430 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16431 <tr bgcolor=WHITE> 16432 <td bgcolor=WHITE align=center valign=top>15:03</td> 16433 <td align=left valign=top>RSVD</td> 16434 <td align=left valign=top>Reserved</td> 16435 <td align=left> 16436 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16437 <tr bgcolor=WHITE> 16438 <td bgcolor=WHITE align=center valign=top>02</td> 16439 <td align=left valign=top>RW</td> 16440 <td align=left valign=top>micro_gen_intr_rmi_mbox1wr</td> 16441 <td align=left> 16442 Generate interrupt when micro_rmi_to_micro_mbox1 field is written <br> 16443 0 - disabled <br> 16444 1 - enbled <br> 16445 Reset value is 0.</td></tr> 16446 <tr bgcolor=WHITE> 16447 <td bgcolor=WHITE align=center valign=top>01</td> 16448 <td align=left valign=top>RW</td> 16449 <td align=left valign=top>micro_gen_intr_rmi_mbox0wr</td> 16450 <td align=left> 16451 Generate interrupt when micro_rmi_to_micro_mbox0 field is written <br> 16452 0 - disabled <br> 16453 1 - enbled <br> 16454 Reset value is 0.</td></tr> 16455 <tr bgcolor=WHITE> 16456 <td bgcolor=WHITE align=center valign=top>00</td> 16457 <td align=left valign=top>SC</td> 16458 <td align=left valign=top>micro_rmi_mbox_send_msgin</td> 16459 <td align=left> 16460 Send message in (to the micro)<br> 16461 This field is set by the RMIC to indicate to the Micro that the message in the <br> 16462 rmi_to_micro_mbox1, and rmi_to_micro_mbox0 regiters is valid. <br> 16463 Reset value is 0.</td></tr> 16464 </table><p> 16465 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16466 <hr> 16467 <b><a NAME="MICRO_B_COM_RMI_AHB_CONTROL1">MICRO_B_COM_RMI_AHB_CONTROL1 - ahb control register 1</a></b><br> 16468 Address Offset = 32'h0000_d216<br> 16469 Physical Address = 32'h0000_d216<br> 16470 Reset Value = 16'h0007<br> 16471 Access = RW (16-bit only)<br> 16472 <table border=1 align=center width=100% cellpadding=0> 16473 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16474 <tr bgcolor=WHITE> 16475 <td bgcolor=WHITE align=center valign=top>15:05</td> 16476 <td align=left valign=top>RSVD</td> 16477 <td align=left valign=top>Reserved</td> 16478 <td align=left> 16479 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16480 <tr bgcolor=WHITE> 16481 <td bgcolor=WHITE align=center valign=top>04</td> 16482 <td align=left valign=top>RW</td> 16483 <td align=left valign=top>micro_pmi_hp_ext_ack_timeout_dis</td> 16484 <td align=left> 16485 pmi_hp_ext_ack_* timeout disable<br> 16486 When micro initates a read/write transctions on the pmi_hp_ext bus <br> 16487 it allows upto 256 clock cycles for pmi_hp_ext_ack_mc/pmi_hp_ext_ack_uc to be asserted <br> 16488 If pmi_hp_ext_ack_* is not received within this time, then it  <br> 16489 1. terminates the current transactions on the pmi_hp_ext bus <br> 16490 2. set the pmi_hp_ext_ack_timeout_status field of the ahbcommon_pmi_hp_status0 register.<br> 16491 3. performs the response error signaling on the micro AHB bus if micro_m0_hresp_en field is set to 1'b1 <br> 16492 This timeout period/error reporting/reponse error signaling can be disabled by setting this field i.e.<br> 16493 0: enabled  <br> 16494 1: disabled <br> 16495 Reset value is 0.</td></tr> 16496 <tr bgcolor=WHITE> 16497 <td bgcolor=WHITE align=center valign=top>03</td> 16498 <td align=left valign=top>RW</td> 16499 <td align=left valign=top>micro_pmi_hp_ack_timeout_dis</td> 16500 <td align=left> 16501 pmi_hp_ack_* timeout disable<br> 16502 When micro initates a read/write transctions on the pmi_hp bus <br> 16503 it allows upto 256 clock cycles for pmi_hp_ack_mc/pmi_hp_ack_uc to be asserted <br> 16504 If pmi_hp_ack_* is not received within this time, then it  <br> 16505 1. terminates the current transactions on the pmi_hp bus <br> 16506 2. set the pmi_hp_ack_timeout_status field of the ahbcommon_pmi_hp_status0 register.<br> 16507 3. performs the response error signaling on the micro AHB bus when micro_m0_hresp_en field is set to 1'b1 <br> 16508 This timeout period/error reporting/reponse error signaling can be disabled by setting this field i.e.<br> 16509 0: enabled  <br> 16510 1: disabled <br> 16511 Reset value is 0.</td></tr> 16512 <tr bgcolor=WHITE> 16513 <td bgcolor=WHITE align=center valign=top>02</td> 16514 <td align=left valign=top>RW</td> 16515 <td align=left valign=top>micro_sw_pmi_hp_ext_rstb</td> 16516 <td align=left> 16517 Software reset pmi_hp_ext interface logic <br> 16518 This bit is to initialize the pmi_hp_ext block <br> 16519 0 - reset asserted <br> 16520 1 - reset de-asserted <br> 16521 Reset value is 1.</td></tr> 16522 <tr bgcolor=WHITE> 16523 <td bgcolor=WHITE align=center valign=top>01</td> 16524 <td align=left valign=top>RW</td> 16525 <td align=left valign=top>micro_sw_pmi_hp_rstb</td> 16526 <td align=left> 16527 Software reset pmi_hp interface logic <br> 16528 This bit is to initialize the pmi_hp block <br> 16529 0 - reset asserted <br> 16530 1 - reset de-asserted <br> 16531 Reset value is 1.</td></tr> 16532 <tr bgcolor=WHITE> 16533 <td bgcolor=WHITE align=center valign=top>00</td> 16534 <td align=left valign=top>RW</td> 16535 <td align=left valign=top>micro_m0_hresp_en</td> 16536 <td align=left> 16537 m0 response error signaling enable<br> 16538 0 - disabled <br> 16539 1 - enabled <br> 16540 Reset value is 1.</td></tr> 16541 </table><p> 16542 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16543 <hr> 16544 <b><a NAME="MICRO_B_COM_RMI_AHB_STATUS1">MICRO_B_COM_RMI_AHB_STATUS1 - ahb status register 1</a></b><br> 16545 Address Offset = 32'h0000_d217<br> 16546 Physical Address = 32'h0000_d217<br> 16547 Reset Value = 16'h0000<br> 16548 Access = RO (16-bit only)<br> 16549 <table border=1 align=center width=100% cellpadding=0> 16550 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16551 <tr bgcolor=WHITE> 16552 <td bgcolor=WHITE align=center valign=top>15:03</td> 16553 <td align=left valign=top>RSVD</td> 16554 <td align=left valign=top>Reserved</td> 16555 <td align=left> 16556 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16557 <tr bgcolor=WHITE> 16558 <td bgcolor=WHITE align=center valign=top>02</td> 16559 <td align=left valign=top>RO</td> 16560 <td align=left valign=top>micro_pr_default_slave_error</td> 16561 <td align=left> 16562 PRAM interface default slave error detected. PRAM interface attempted to access un-used address<br> 16563 1 - error detected - latched high clear on read <br> 16564 0 - no error <br> 16565 Reset value is 0.</td></tr> 16566 <tr bgcolor=WHITE> 16567 <td bgcolor=WHITE align=center valign=top>01</td> 16568 <td align=left valign=top>RO</td> 16569 <td align=left valign=top>micro_rmi_default_slave_error</td> 16570 <td align=left> 16571 register interface default slave error detected. Register interface attempted to access un-used address<br> 16572 1 - error detected - latched high clear on read <br> 16573 0 - no error <br> 16574 Reset value is 0.</td></tr> 16575 <tr bgcolor=WHITE> 16576 <td bgcolor=WHITE align=center valign=top>00</td> 16577 <td align=left valign=top>RO</td> 16578 <td align=left valign=top>micro_m0_default_slave_error</td> 16579 <td align=left> 16580 m0 default slave error detected. M0 attempted to access un-used address<br> 16581 1 - error detected - latched high clear on read <br> 16582 0 - no error <br> 16583 Reset value is 0.</td></tr> 16584 </table><p> 16585 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16586 <hr> 16587 <b><a NAME="MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW">MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW - rmi to ahb auto-incremented write address LSW (bits 15:0) register</a></b><br> 16588 Address Offset = 32'h0000_d218<br> 16589 Physical Address = 32'h0000_d218<br> 16590 Reset Value = 16'h0000<br> 16591 Access = RO (16-bit only)<br> 16592 <table border=1 align=center width=100% cellpadding=0> 16593 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16594 <tr bgcolor=WHITE> 16595 <td bgcolor=WHITE align=center valign=top>15:00</td> 16596 <td align=left valign=top>RO</td> 16597 <td align=left valign=top>micro_ra_autoinc_nxt_wraddr_lsw</td> 16598 <td align=left> 16599 When the micro_autoinc_wraddr_en is set, then these bits <br> 16600 indicate the lower 16-bits of the address that will be used <br> 16601 "during the next write transaction.<br> 16602 These bits allow address tracking when rmi interface auto address <br> 16603 increment mode is used<br> 16604 Reset value is 0.</td></tr> 16605 </table><p> 16606 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16607 <hr> 16608 <b><a NAME="MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW">MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW - rmi to ahb auto-incremented read address LSW (bits 15:0) register</a></b><br> 16609 Address Offset = 32'h0000_d219<br> 16610 Physical Address = 32'h0000_d219<br> 16611 Reset Value = 16'h0000<br> 16612 Access = RO (16-bit only)<br> 16613 <table border=1 align=center width=100% cellpadding=0> 16614 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16615 <tr bgcolor=WHITE> 16616 <td bgcolor=WHITE align=center valign=top>15:00</td> 16617 <td align=left valign=top>RO</td> 16618 <td align=left valign=top>micro_ra_autoinc_nxt_rdaddr_lsw</td> 16619 <td align=left> 16620 When the micro_autoinc_rdaddr_en is set, then these bits <br> 16621 indicate the lower 16-bits of the address that will be used <br> 16622 "during the next read transaction.<br> 16623 These bits allow address tracking when rmi interface auto address <br> 16624 increment mode is used<br> 16625 Reset value is 0.</td></tr> 16626 </table><p> 16627 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16628 <hr> 16629 <b><a NAME="MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW">MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW - pram i/f to ahb auto-incremented write address LSW (bits 15:0) register</a></b><br> 16630 Address Offset = 32'h0000_d21a<br> 16631 Physical Address = 32'h0000_d21a<br> 16632 Reset Value = 16'h0000<br> 16633 Access = RO (16-bit only)<br> 16634 <table border=1 align=center width=100% cellpadding=0> 16635 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16636 <tr bgcolor=WHITE> 16637 <td bgcolor=WHITE align=center valign=top>15:00</td> 16638 <td align=left valign=top>RO</td> 16639 <td align=left valign=top>micro_pr_autoinc_nxt_wraddr_lsw</td> 16640 <td align=left> 16641 When pram interface is used to write to the code/data RAM <br> 16642 then these bits indicate the lower 16-bits of the address that will be used <br> 16643 "during the next write transaction.<br> 16644 These bits allow address tracking <br> 16645 Reset value is 0.</td></tr> 16646 </table><p> 16647 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16648 <hr> 16649 <b><a NAME="MICRO_B_COM_RMI_PVT_CONTROL0">MICRO_B_COM_RMI_PVT_CONTROL0 - rmi pvt temperature control register 0</a></b><br> 16650 Address Offset = 32'h0000_d21b<br> 16651 Physical Address = 32'h0000_d21b<br> 16652 Reset Value = 16'h0000<br> 16653 Access = RW (16-bit only)<br> 16654 <table border=1 align=center width=100% cellpadding=0> 16655 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16656 <tr bgcolor=WHITE> 16657 <td bgcolor=WHITE align=center valign=top>15:13</td> 16658 <td align=left valign=top>RSVD</td> 16659 <td align=left valign=top>Reserved</td> 16660 <td align=left> 16661 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16662 <tr bgcolor=WHITE> 16663 <td bgcolor=WHITE align=center valign=top>12</td> 16664 <td align=left valign=top>RW</td> 16665 <td align=left valign=top>micro_pvt_tempdata_frc</td> 16666 <td align=left> 16667 temperature dat force enable <br> 16668 When micro_pvt_tempdata_frc field is set to 1'b1 then micro_pvt_tempdata_frcval<br> 16669 field is used to set the temperature value. The temperature value can be read <br> 16670 via micro_pvt_tempdata_rmi field of the pvt_status0 register or <br> 16671 via ahbcommon_pvt_tempdata filed of the ahbcommon_pvt_tempdata register<br> 16672 Reset value is 0.</td></tr> 16673 <tr bgcolor=WHITE> 16674 <td bgcolor=WHITE align=center valign=top>11:10</td> 16675 <td align=left valign=top>RSVD</td> 16676 <td align=left valign=top>Reserved</td> 16677 <td align=left> 16678 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16679 <tr bgcolor=WHITE> 16680 <td bgcolor=WHITE align=center valign=top>09:00</td> 16681 <td align=left valign=top>RW</td> 16682 <td align=left valign=top>micro_pvt_tempdata_frcval</td> 16683 <td align=left> 16684 temperature data force value<br> 16685 When micro_pvt_tempdata_frc field is set to 1'b1 then micro_pvt_tempdata_frcval<br> 16686 field is used to set the temperature value. The temperature value can be read <br> 16687 via micro_pvt_tempdata_rmi field of the pvt_status0 register or <br> 16688 via ahbcommon_pvt_tempdata filed of the ahbcommon_pvt_tempdata register<br> 16689 Reset value is 0.</td></tr> 16690 </table><p> 16691 <A HREF="#MICRO_B_COM Registers">Return to MICRO_B_COM: common register block for all lanes within each Micro Top Table</A><p> 16692 <hr> 16693 <H1><a NAME="MICRO_C_COM Registers">MICRO_C_COM: common register block for all lanes within each Micro Top Registers</a></H1> 16694 <table border=1 align=center width=100% cellpadding=0> 16695 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 16696 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 16697 <tr> 16698 <td align=center>0xD220</td><td><A HREF="#MICRO_C_COM_CODE_RAM_ECCCONTROL0">MICRO_C_COM_CODE_RAM_ECCCONTROL0</A><br>code ram ecc control 0</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">micro_ecc_corrupt</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_ecc_frc_disable</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_eccg_mode</div> </td> <td align=center>16'h0000</td></tr> 16699 <tr> 16700 <td align=center>0xD221</td><td><A HREF="#MICRO_C_COM_CODE_RAM_ECCCONTRO1">MICRO_C_COM_CODE_RAM_ECCCONTRO1</A><br>code ram ecc control 1</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">micro_ra_ecc_wrdata</div> </td> <td align=center>16'h0000</td></tr> 16701 <tr> 16702 <td align=center>0xD222</td><td><A HREF="#MICRO_C_COM_CODE_RAM_ECCSTATUS0">MICRO_C_COM_CODE_RAM_ECCSTATUS0</A><br>code ram ecc status 0</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">micro_code_ram_ecc_address</div> </td> <td align=center>16'h0000</td></tr> 16703 <tr> 16704 <td align=center>0xD223</td><td><A HREF="#MICRO_C_COM_CODE_RAM_ECCSTATUS1">MICRO_C_COM_CODE_RAM_ECCSTATUS1</A><br>code ram ecc status 1</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">micro_ra_ecc_rddata</div> </td> <td align=center>16'h0000</td></tr> 16705 <tr> 16706 <td align=center>0xD224</td><td><A HREF="#MICRO_C_COM_CODE_RAM_TESTIFCONTROL0">MICRO_C_COM_CODE_RAM_TESTIFCONTROL0</A><br>code ram test interface control 0</td><td bgcolor=#CCCCCC align=center colspan="9"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">micro_code_ram_tm</div> </td> <td align=center>16'h0000</td></tr> 16707 <tr> 16708 <td align=center>0xD225</td><td><A HREF="#MICRO_C_COM_RAM_CONTROL0">MICRO_C_COM_RAM_CONTROL0</A><br>ram configuration register 0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_ignore_m0_code_writes</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_ramclk_noninv</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">micro_dr_size</div> </td> <td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_protect_fwcode</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_dr_looktab_en</div> </td> <td align=center>16'h8401</td></tr> 16709 <tr> 16710 <td align=center>0xD226</td><td><A HREF="#MICRO_C_COM_RMI_EXT_INTR_CONTROL0">MICRO_C_COM_RMI_EXT_INTR_CONTROL0</A><br>rmi external interrupt control register 0</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_m0_systemresetreq_intr_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_m0_lockup_intr_en</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_ecc_multirow_err_intr_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_ecc_uncorr_err_intr_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_ecc_corr_err_intr_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_mbox_msgout_intr_en</div> </td> <td align=center>16'h0000</td></tr> 16711 <tr> 16712 <td align=center>0xD227</td><td><A HREF="#MICRO_C_COM_RMI_EXT_INTR_STATUS0">MICRO_C_COM_RMI_EXT_INTR_STATUS0</A><br>rmi external interrupt status register 0</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_m0_systemresetreq_status</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_m0_lockup_status</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_ecc_multirow_err_status</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_ecc_uncorr_err_status</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_ecc_corr_err_status</div> </td> <td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_rmi_mbox_msgout_status</div> </td> <td align=center>16'h0000</td></tr> 16713 <tr> 16714 <td align=center>0xD228</td><td><A HREF="#MICRO_C_COM_RMI_PMI_IF_CONTROL0">MICRO_C_COM_RMI_PMI_IF_CONTROL0</A><br>pmi interface control register 0</td><td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_ext_fast_bktobk_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_ext_fast_dual_meta_ff_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_ext_fast_read_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="5"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_fast_bktobk_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_fast_dual_meta_ff_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">micro_pmi_hp_fast_read_en</div> </td> <td align=center>16'h0101</td></tr> 16715 <tr> 16716 <td align=center>0xD229</td><td><A HREF="#MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0">MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0</A><br>Silicon debug control register 0</td><td bgcolor=#CCCCCC align=center colspan="14"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">micro_silicon_debug_status_mux_sel</div> </td> <td align=center>16'h0000</td></tr> 16717 <tr> 16718 <td align=center>0xD22A</td><td><A HREF="#MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0">MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0</A><br>Silicon debug status register 0</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_silicon_debug_status_muxed_data</div> </td> <td align=center>16'h0000</td></tr> 16719 </table><p> 16720 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 16721 <hr> 16722 <b><a NAME="MICRO_C_COM_CODE_RAM_ECCCONTROL0">MICRO_C_COM_CODE_RAM_ECCCONTROL0 - code ram ecc control 0</a></b><br> 16723 Address Offset = 32'h0000_d220<br> 16724 Physical Address = 32'h0000_d220<br> 16725 Reset Value = 16'h0000<br> 16726 Access = RW (16-bit only)<br> 16727 <table border=1 align=center width=100% cellpadding=0> 16728 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16729 <tr bgcolor=WHITE> 16730 <td bgcolor=WHITE align=center valign=top>15:06</td> 16731 <td align=left valign=top>RSVD</td> 16732 <td align=left valign=top>Reserved</td> 16733 <td align=left> 16734 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16735 <tr bgcolor=WHITE> 16736 <td bgcolor=WHITE align=center valign=top>05:04</td> 16737 <td align=left valign=top>RW</td> 16738 <td align=left valign=top>micro_ecc_corrupt</td> 16739 <td align=left> 16740 This field allows the ecc codes to be corrupted for testing.<br> 16741 2'b00 - normal mode  <br> 16742 2'b01 - corrupt the ECC code written into the code/data RAM <br> 16743 2'b10 - corrupt data - add 1 bit data error on the RX side <br> 16744 2'b11 - corrupt data - add 2 bit data error on the RA side <br> 16745 Reset value is 0.</td></tr> 16746 <tr bgcolor=WHITE> 16747 <td bgcolor=WHITE align=center valign=top>03:02</td> 16748 <td align=left valign=top>RSVD</td> 16749 <td align=left valign=top>Reserved</td> 16750 <td align=left> 16751 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16752 <tr bgcolor=WHITE> 16753 <td bgcolor=WHITE align=center valign=top>01</td> 16754 <td align=left valign=top>RW</td> 16755 <td align=left valign=top>micro_ecc_frc_disable</td> 16756 <td align=left> 16757 ecc force disable <br> 16758 0: ECC Enabled  - ECC error code generation determine by the micro_eccg_mode field <br> 16759                   ECC error checking enabled in hardware mode only <br> 16760 1: ECC Disabled - ECC error codes values written into the RAM set to zero <br> 16761                   ECC error checking disabled <br> 16762 Reset value is 0.</td></tr> 16763 <tr bgcolor=WHITE> 16764 <td bgcolor=WHITE align=center valign=top>00</td> 16765 <td align=left valign=top>RW</td> 16766 <td align=left valign=top>micro_eccg_mode</td> 16767 <td align=left> 16768 ecc code generation mode <br> 16769 0: Hardware mode - ECC code generated by hardware, ECC error checking enabled<br> 16770 1: Software mode - ECC code from the rg_ra_ecc_wrdata field are written into code/data RAM<br> 16771                    ECC error checking disabled. This mode is only supported <br> 16772                    when register interface is used <br> 16773 Reset value is 0.</td></tr> 16774 </table><p> 16775 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 16776 <hr> 16777 <b><a NAME="MICRO_C_COM_CODE_RAM_ECCCONTRO1">MICRO_C_COM_CODE_RAM_ECCCONTRO1 - code ram ecc control 1</a></b><br> 16778 Address Offset = 32'h0000_d221<br> 16779 Physical Address = 32'h0000_d221<br> 16780 Reset Value = 16'h0000<br> 16781 Access = RW (16-bit only)<br> 16782 <table border=1 align=center width=100% cellpadding=0> 16783 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16784 <tr bgcolor=WHITE> 16785 <td bgcolor=WHITE align=center valign=top>15:07</td> 16786 <td align=left valign=top>RSVD</td> 16787 <td align=left valign=top>Reserved</td> 16788 <td align=left> 16789 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16790 <tr bgcolor=WHITE> 16791 <td bgcolor=WHITE align=center valign=top>06:00</td> 16792 <td align=left valign=top>RW</td> 16793 <td align=left valign=top>micro_ra_ecc_wrdata</td> 16794 <td align=left> 16795 This foield is used to write the ECC codes into the code/data when ECC software modes is enabled <br> 16796 Reset value is 0.</td></tr> 16797 </table><p> 16798 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 16799 <hr> 16800 <b><a NAME="MICRO_C_COM_CODE_RAM_ECCSTATUS0">MICRO_C_COM_CODE_RAM_ECCSTATUS0 - code ram ecc status 0</a></b><br> 16801 Address Offset = 32'h0000_d222<br> 16802 Physical Address = 32'h0000_d222<br> 16803 Reset Value = 16'h0000<br> 16804 Access = RO (16-bit only)<br> 16805 <table border=1 align=center width=100% cellpadding=0> 16806 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16807 <tr bgcolor=WHITE> 16808 <td bgcolor=WHITE align=center valign=top>15</td> 16809 <td align=left valign=top>RSVD</td> 16810 <td align=left valign=top>Reserved</td> 16811 <td align=left> 16812 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 16813 <tr bgcolor=WHITE> 16814 <td bgcolor=WHITE align=center valign=top>14:00</td> 16815 <td align=left valign=top>RO</td> 16816 <td align=left valign=top>micro_code_ram_ecc_address</td> 16817 <td align=left> 16818 First ecc error address <br> 16819 Reset value is 0.</td></tr> 16820 </table><p> 16821 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 16822 <hr> 16823 <b><a NAME="MICRO_C_COM_CODE_RAM_ECCSTATUS1">MICRO_C_COM_CODE_RAM_ECCSTATUS1 - code ram ecc status 1</a></b><br> 16824 Address Offset = 32'h0000_d223<br> 16825 Physical Address = 32'h0000_d223<br> 16826 Reset Value = 16'h0000<br> 16827 Access = RO (16-bit only)<br> 16828 <table border=1 align=center width=100% cellpadding=0> 16829 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16830 <tr bgcolor=WHITE> 16831 <td bgcolor=WHITE align=center valign=top>15:07</td> 16832 <td align=left valign=top>RSVD</td> 16833 <td align=left valign=top>Reserved</td> 16834 <td align=left> 16835 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16836 <tr bgcolor=WHITE> 16837 <td bgcolor=WHITE align=center valign=top>06:00</td> 16838 <td align=left valign=top>RO</td> 16839 <td align=left valign=top>micro_ra_ecc_rddata</td> 16840 <td align=left> 16841 When the register interface is used to read code/data RAM, then this field can be used<br> 16842 read the ECC codes currently stored in the code/data RAM<br> 16843 Reset value is 0.</td></tr> 16844 </table><p> 16845 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 16846 <hr> 16847 <b><a NAME="MICRO_C_COM_CODE_RAM_TESTIFCONTROL0">MICRO_C_COM_CODE_RAM_TESTIFCONTROL0 - code ram test interface control 0</a></b><br> 16848 Address Offset = 32'h0000_d224<br> 16849 Physical Address = 32'h0000_d224<br> 16850 Reset Value = 16'h0000<br> 16851 Access = RW (16-bit only)<br> 16852 <table border=1 align=center width=100% cellpadding=0> 16853 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16854 <tr bgcolor=WHITE> 16855 <td bgcolor=WHITE align=center valign=top>15:07</td> 16856 <td align=left valign=top>RSVD</td> 16857 <td align=left valign=top>Reserved</td> 16858 <td align=left> 16859 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16860 <tr bgcolor=WHITE> 16861 <td bgcolor=WHITE align=center valign=top>06:00</td> 16862 <td align=left valign=top>RW</td> 16863 <td align=left valign=top>micro_code_ram_tm</td> 16864 <td align=left> 16865 Test Mode. <br> 16866   These pins are used to put the instance into various test <br> 16867   modes that can be used for a number of different purposes <br> 16868   including extended screening, yield improvement and debug. <br> 16869   The default mode of the instance is tm<?:0>='d0. It is  <br> 16870   highly recommended that the user has control over all the <br> 16871   tm<?:0> inputs. All tm<?:0> inputs are asynchronous. See  <br> 16872   the Test Modes section of the on line M16SP Web  <br> 16873   Specification for further details. <br> 16874 Reset value is 0.</td></tr> 16875 </table><p> 16876 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 16877 <hr> 16878 <b><a NAME="MICRO_C_COM_RAM_CONTROL0">MICRO_C_COM_RAM_CONTROL0 - ram configuration register 0</a></b><br> 16879 Address Offset = 32'h0000_d225<br> 16880 Physical Address = 32'h0000_d225<br> 16881 Reset Value = 16'h8401<br> 16882 Access = RW (16-bit only)<br> 16883 <table border=1 align=center width=100% cellpadding=0> 16884 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16885 <tr bgcolor=WHITE> 16886 <td bgcolor=WHITE align=center valign=top>15</td> 16887 <td align=left valign=top>RW</td> 16888 <td align=left valign=top>micro_ignore_m0_code_writes</td> 16889 <td align=left> 16890 Ignore Micro writes to the code portion of the RAM <br> 16891 0 - Allow writes <br> 16892 1 - Ignore writes <br> 16893 Reset value is 1.</td></tr> 16894 <tr bgcolor=WHITE> 16895 <td bgcolor=WHITE align=center valign=top>14</td> 16896 <td align=left valign=top>RW</td> 16897 <td align=left valign=top>micro_ramclk_noninv</td> 16898 <td align=left> 16899 Code/Data RAM clock non-inverted <br> 16900 0 - inverted <br> 16901 1 - non-inverted <br> 16902 When non-inverted clock to RAM is used, then a wait state to be inserted during read access.<br> 16903 However, it eliminates the use of both edges of the clock (duty cycle) and makes the timing closer easier <br> 16904 Reset value is 0.</td></tr> 16905 <tr bgcolor=WHITE> 16906 <td bgcolor=WHITE align=center valign=top>13:08</td> 16907 <td align=left valign=top>RW</td> 16908 <td align=left valign=top>micro_dr_size</td> 16909 <td align=left> 16910 Data/Code RAM allocation when the micro_dr_looktab_en field is set to 1'b1 <br> 16911 The RAM is 36KB and this field can be used to allocate data/code RAM on a 1KB granualarity <br> 16912 6'd0  : Data RAM = 0KB,  Code RAM = 36KB <br> 16913 6'd1  : Data RAM = 1KB,  Code RAM = 35KB <br> 16914 6'd2  : Data RAM = 2KB,  Code RAM = 34KB <br> 16915 ...   : Data RAM = .. ,  Code RAM = ..  <br> 16916 ...   : Data RAM = .. ,  Code RAM = ..  <br> 16917 6'd35 : Data RAM = 35KB, Code RAM = 1KB <br> 16918 6'd36 : Data RAM = 36KB, Code RAM = 0KB <br> 16919 PLEASE NOTE: the micro in the PMD core does not have any additional RAM to store Code/Data <br> 16920 therfore a value of 0 and 36 should not be used <br> 16921 Reset value is 4.</td></tr> 16922 <tr bgcolor=WHITE> 16923 <td bgcolor=WHITE align=center valign=top>07:02</td> 16924 <td align=left valign=top>RSVD</td> 16925 <td align=left valign=top>Reserved</td> 16926 <td align=left> 16927 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16928 <tr bgcolor=WHITE> 16929 <td bgcolor=WHITE align=center valign=top>01</td> 16930 <td align=left valign=top>RW</td> 16931 <td align=left valign=top>micro_protect_fwcode</td> 16932 <td align=left> 16933 protect firmware code during micro master reset <br> 16934 1 - RAM address, data, chip select and write enable are set to inactive state <br> 16935     to prevent timing violations from corrupting the contents of the RAM <br> 16936     If this field is used then the software has to clear this filed before re-starting the micro <br> 16937 0 - RAM address, data, chip select and write enable are set to inactive state <br> 16938     by using micro_master_rstb register field to prevent timing violations from corrupting the contents of the RAM <br> 16939 Reset value is 0.</td></tr> 16940 <tr bgcolor=WHITE> 16941 <td bgcolor=WHITE align=center valign=top>00</td> 16942 <td align=left valign=top>RW</td> 16943 <td align=left valign=top>micro_dr_looktab_en</td> 16944 <td align=left> 16945 Data RAM lookup table enable <br> 16946 1 - Data RAM mapped in the data region by hardware <br> 16947     starting at address 0x2000_0000 (for software compatibilty) <br> 16948 0 - Data RAM not mapped by hardware <br> 16949     Firmware defines code/data regiions <br> 16950 Reset value is 1.</td></tr> 16951 </table><p> 16952 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 16953 <hr> 16954 <b><a NAME="MICRO_C_COM_RMI_EXT_INTR_CONTROL0">MICRO_C_COM_RMI_EXT_INTR_CONTROL0 - rmi external interrupt control register 0</a></b><br> 16955 Address Offset = 32'h0000_d226<br> 16956 Physical Address = 32'h0000_d226<br> 16957 Reset Value = 16'h0000<br> 16958 Access = RW (16-bit only)<br> 16959 <table border=1 align=center width=100% cellpadding=0> 16960 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 16961 <tr bgcolor=WHITE> 16962 <td bgcolor=WHITE align=center valign=top>15:10</td> 16963 <td align=left valign=top>RSVD</td> 16964 <td align=left valign=top>Reserved</td> 16965 <td align=left> 16966 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 16967 <tr bgcolor=WHITE> 16968 <td bgcolor=WHITE align=center valign=top>09</td> 16969 <td align=left valign=top>RW</td> 16970 <td align=left valign=top>micro_rmi_m0_systemresetreq_intr_en</td> 16971 <td align=left> 16972 M0 systemresetreq interrupt enable <br> 16973 When this field is set to 1'b1 then the micro_rmi_m0_systemresetreq_status field of the rmi_ext_intr_status0<br> 16974 registers generate an interrupt on the micro_ext_intr pin<br> 16975 Reset value is 0.</td></tr> 16976 <tr bgcolor=WHITE> 16977 <td bgcolor=WHITE align=center valign=top>08</td> 16978 <td align=left valign=top>RW</td> 16979 <td align=left valign=top>micro_rmi_m0_lockup_intr_en</td> 16980 <td align=left> 16981 M0 lockup interrupt enable<br> 16982 When this field is set to 1'b1 then the micro_rmi_m0_lockup_status field of the rmi_ext_intr_status0<br> 16983 registers generate an interrupt on the micro_ext_intr pin<br> 16984 Reset value is 0.</td></tr> 16985 <tr bgcolor=WHITE> 16986 <td bgcolor=WHITE align=center valign=top>07</td> 16987 <td align=left valign=top>RSVD</td> 16988 <td align=left valign=top>Reserved</td> 16989 <td align=left> 16990 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 16991 <tr bgcolor=WHITE> 16992 <td bgcolor=WHITE align=center valign=top>06</td> 16993 <td align=left valign=top>RW</td> 16994 <td align=left valign=top>micro_rmi_ecc_multirow_err_intr_en</td> 16995 <td align=left> 16996 ECC error on multiple row detect interrupt enable <br> 16997 When this field is set to 1'b1 then the micro_rmi_ecc_multirow_err_status field of the rmi_ext_intr_status0<br> 16998 registers generate an interrupt on the micro_ext_intr pin<br> 16999 Reset value is 0.</td></tr> 17000 <tr bgcolor=WHITE> 17001 <td bgcolor=WHITE align=center valign=top>05</td> 17002 <td align=left valign=top>RW</td> 17003 <td align=left valign=top>micro_rmi_ecc_uncorr_err_intr_en</td> 17004 <td align=left> 17005 ECC 2 bit un-correctable error detect interrupt enable <br> 17006 When this field is set to 1'b1 then the micro_rmi_ecc_uncorr_err_status field of the rmi_ext_intr_status0<br> 17007 registers generate an interrupt on the micro_ext_intr pin<br> 17008 Reset value is 0.</td></tr> 17009 <tr bgcolor=WHITE> 17010 <td bgcolor=WHITE align=center valign=top>04</td> 17011 <td align=left valign=top>RW</td> 17012 <td align=left valign=top>micro_rmi_ecc_corr_err_intr_en</td> 17013 <td align=left> 17014 ECC 1 bit correctable error detect interrupt enable <br> 17015 When this field is set to 1'b1 then the micro_rmi_ecc_corr_err_status field of the rmi_ext_intr_status0<br> 17016 registers generate an interrupt on the micro_ext_intr pin<br> 17017 Reset value is 0.</td></tr> 17018 <tr bgcolor=WHITE> 17019 <td bgcolor=WHITE align=center valign=top>03:01</td> 17020 <td align=left valign=top>RSVD</td> 17021 <td align=left valign=top>Reserved</td> 17022 <td align=left> 17023 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17024 <tr bgcolor=WHITE> 17025 <td bgcolor=WHITE align=center valign=top>00</td> 17026 <td align=left valign=top>RW</td> 17027 <td align=left valign=top>micro_rmi_mbox_msgout_intr_en</td> 17028 <td align=left> 17029 Message out (from Micro) interrupt enable <br> 17030 When this field is set to 1'b1 then the micro_rmi_mbox_msgout_status field of the rmi_ext_intr_status0<br> 17031 registers generate an interrupt on the micro_ext_intr pin<br> 17032 Reset value is 0.</td></tr> 17033 </table><p> 17034 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 17035 <hr> 17036 <b><a NAME="MICRO_C_COM_RMI_EXT_INTR_STATUS0">MICRO_C_COM_RMI_EXT_INTR_STATUS0 - rmi external interrupt status register 0</a></b><br> 17037 Address Offset = 32'h0000_d227<br> 17038 Physical Address = 32'h0000_d227<br> 17039 Reset Value = 16'h0000<br> 17040 Access = RO (16-bit only)<br> 17041 <table border=1 align=center width=100% cellpadding=0> 17042 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17043 <tr bgcolor=WHITE> 17044 <td bgcolor=WHITE align=center valign=top>15:10</td> 17045 <td align=left valign=top>RSVD</td> 17046 <td align=left valign=top>Reserved</td> 17047 <td align=left> 17048 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17049 <tr bgcolor=WHITE> 17050 <td bgcolor=WHITE align=center valign=top>09</td> 17051 <td align=left valign=top>RO</td> 17052 <td align=left valign=top>micro_rmi_m0_systemresetreq_status</td> 17053 <td align=left> 17054 M0 systemresetreq status<br> 17055 This field indicates the status of the M0 "systemresetreq" signal <br> 17056 Reset value is 0.</td></tr> 17057 <tr bgcolor=WHITE> 17058 <td bgcolor=WHITE align=center valign=top>08</td> 17059 <td align=left valign=top>RO</td> 17060 <td align=left valign=top>micro_rmi_m0_lockup_status</td> 17061 <td align=left> 17062 M0 lockup status<br> 17063 This field indicates the status of the M0 "lockup" signal <br> 17064 Reset value is 0.</td></tr> 17065 <tr bgcolor=WHITE> 17066 <td bgcolor=WHITE align=center valign=top>07</td> 17067 <td align=left valign=top>RSVD</td> 17068 <td align=left valign=top>Reserved</td> 17069 <td align=left> 17070 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 17071 <tr bgcolor=WHITE> 17072 <td bgcolor=WHITE align=center valign=top>06</td> 17073 <td align=left valign=top>RO</td> 17074 <td align=left valign=top>micro_rmi_ecc_multirow_err_status</td> 17075 <td align=left> 17076 ECC error on multiple row detected  status <br> 17077 This field is set to 1'b1 when the ECC logic detects correctable or uncorrecatble errors on multiple rows. <br> 17078 This bits remain remains set until this register is read<br> 17079 Reset value is 0.</td></tr> 17080 <tr bgcolor=WHITE> 17081 <td bgcolor=WHITE align=center valign=top>05</td> 17082 <td align=left valign=top>RO</td> 17083 <td align=left valign=top>micro_rmi_ecc_uncorr_err_status</td> 17084 <td align=left> 17085 ECC 2 bit un-correctable error detected status <br> 17086 This field is set to 1'b1 when the ECC logic detects one bit un-correctable error. <br> 17087 This bits remain remains set until this register is read<br> 17088 Reset value is 0.</td></tr> 17089 <tr bgcolor=WHITE> 17090 <td bgcolor=WHITE align=center valign=top>04</td> 17091 <td align=left valign=top>RO</td> 17092 <td align=left valign=top>micro_rmi_ecc_corr_err_status</td> 17093 <td align=left> 17094 ECC 1 bit correctable error detected status <br> 17095 This field is set to 1'b1 when the ECC logic detects one bit correctable error. <br> 17096 This bits remain remains set until this register is read<br> 17097 Reset value is 0.</td></tr> 17098 <tr bgcolor=WHITE> 17099 <td bgcolor=WHITE align=center valign=top>03:01</td> 17100 <td align=left valign=top>RSVD</td> 17101 <td align=left valign=top>Reserved</td> 17102 <td align=left> 17103 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17104 <tr bgcolor=WHITE> 17105 <td bgcolor=WHITE align=center valign=top>00</td> 17106 <td align=left valign=top>RO</td> 17107 <td align=left valign=top>micro_rmi_mbox_msgout_status</td> 17108 <td align=left> 17109 Message out (from Micro) status <br> 17110 This field is set to 1'b1 when the RMIC receives a message from the Micro. <br> 17111 It indicates to the RMIC that the message on the micro_to_rmi_mbox3, <br> 17112 micro_to_rmi_mbox2, micro_to_rmi_mbox1 and micro_to_rmi_mbox0 registers is valid <br> 17113 This bits remain remains set until this register is read<br> 17114 Reset value is 0.</td></tr> 17115 </table><p> 17116 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 17117 <hr> 17118 <b><a NAME="MICRO_C_COM_RMI_PMI_IF_CONTROL0">MICRO_C_COM_RMI_PMI_IF_CONTROL0 - pmi interface control register 0</a></b><br> 17119 Address Offset = 32'h0000_d228<br> 17120 Physical Address = 32'h0000_d228<br> 17121 Reset Value = 16'h0101<br> 17122 Access = RW (16-bit only)<br> 17123 <table border=1 align=center width=100% cellpadding=0> 17124 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17125 <tr bgcolor=WHITE> 17126 <td bgcolor=WHITE align=center valign=top>15:11</td> 17127 <td align=left valign=top>RSVD</td> 17128 <td align=left valign=top>Reserved</td> 17129 <td align=left> 17130 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17131 <tr bgcolor=WHITE> 17132 <td bgcolor=WHITE align=center valign=top>10</td> 17133 <td align=left valign=top>RW</td> 17134 <td align=left valign=top>micro_pmi_hp_ext_fast_bktobk_en</td> 17135 <td align=left> 17136 pmi_hp_ext interface fast back to back enable <br> 17137 1 - skip over some of the states in the fsm during back to back transition <br> 17138 0 - state transitions as in f28 <br> 17139 Reset value is 0.</td></tr> 17140 <tr bgcolor=WHITE> 17141 <td bgcolor=WHITE align=center valign=top>09</td> 17142 <td align=left valign=top>RW</td> 17143 <td align=left valign=top>micro_pmi_hp_ext_fast_dual_meta_ff_en</td> 17144 <td align=left> 17145 pmi_hp_ext interface fast dual meta flops enable <br> 17146 1 - use both the rising and falling edges of the clock for dual meta flops <br> 17147 0 - use only the rising edges of the clock for dual meta flops<br> 17148 Reset value is 0.</td></tr> 17149 <tr bgcolor=WHITE> 17150 <td bgcolor=WHITE align=center valign=top>08</td> 17151 <td align=left valign=top>RW</td> 17152 <td align=left valign=top>micro_pmi_hp_ext_fast_read_en</td> 17153 <td align=left> 17154 pmi hp ext interface fast read enable <br> 17155 1 - use pmi_hp_ext_read_vld during read <br> 17156 0 - use pmi_hp_ext_ack during read<br> 17157 Reset value is 1.</td></tr> 17158 <tr bgcolor=WHITE> 17159 <td bgcolor=WHITE align=center valign=top>07:03</td> 17160 <td align=left valign=top>RSVD</td> 17161 <td align=left valign=top>Reserved</td> 17162 <td align=left> 17163 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17164 <tr bgcolor=WHITE> 17165 <td bgcolor=WHITE align=center valign=top>02</td> 17166 <td align=left valign=top>RW</td> 17167 <td align=left valign=top>micro_pmi_hp_fast_bktobk_en</td> 17168 <td align=left> 17169 pmi hp interface fast back to back enable <br> 17170 1 - skip over some of the states in the fsm during back to back transition <br> 17171 0 - state transitions as in f28 <br> 17172 Reset value is 0.</td></tr> 17173 <tr bgcolor=WHITE> 17174 <td bgcolor=WHITE align=center valign=top>01</td> 17175 <td align=left valign=top>RW</td> 17176 <td align=left valign=top>micro_pmi_hp_fast_dual_meta_ff_en</td> 17177 <td align=left> 17178 pmi hp interface fast dual meta flops enable <br> 17179 1 - use both the rising and falling edges of the clock for dual meta flops <br> 17180 0 - use only the rising edges of the clock for dual meta flops<br> 17181 Reset value is 0.</td></tr> 17182 <tr bgcolor=WHITE> 17183 <td bgcolor=WHITE align=center valign=top>00</td> 17184 <td align=left valign=top>RW</td> 17185 <td align=left valign=top>micro_pmi_hp_fast_read_en</td> 17186 <td align=left> 17187 pmi hp interface fast read enable <br> 17188 1 - use pmi_hp_read_vld during read<br> 17189 0 - use pmi_hp_ack during read<br> 17190 Reset value is 1.</td></tr> 17191 </table><p> 17192 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 17193 <hr> 17194 <b><a NAME="MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0">MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0 - Silicon debug control register 0</a></b><br> 17195 Address Offset = 32'h0000_d229<br> 17196 Physical Address = 32'h0000_d229<br> 17197 Reset Value = 16'h0000<br> 17198 Access = RW (16-bit only)<br> 17199 <table border=1 align=center width=100% cellpadding=0> 17200 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17201 <tr bgcolor=WHITE> 17202 <td bgcolor=WHITE align=center valign=top>15:02</td> 17203 <td align=left valign=top>RSVD</td> 17204 <td align=left valign=top>Reserved</td> 17205 <td align=left> 17206 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17207 <tr bgcolor=WHITE> 17208 <td bgcolor=WHITE align=center valign=top>01:00</td> 17209 <td align=left valign=top>RW</td> 17210 <td align=left valign=top>micro_silicon_debug_status_mux_sel</td> 17211 <td align=left> 17212 This field is used to select the data to be muxed to rmi_silicon_debug_status0 registers  <br> 17213 0 - register interface - {5'd0, init_req,  wraddr_changed,  write_req, <br> 17214                           rdaddr_changed, read_req, ra_state[1:0], <br> 17215                           1'b0, ra_his_state[2:0]} <br> 17216 1 - pram interface     - {2'b00, pif_state_status[1:0], pif_his_state_status[3:0], <br> 17217                           pr_hready, pr_cr_chipsel, pr_state[1:0], 1'b0, <br> 17218                           pr_his_state[2:0]};<br> 17219 2 - pmi_hp interface   - {1'b0, pmi_state[2:0], 4'h0, pmi_his_state[7:0]} <br> 17220 3 - pmi_hp_ext interface   - {1'b0, pmi_state[2:0], 4'h0, pmi_his_state[7:0]} <br> 17221 Reset value is 0.</td></tr> 17222 </table><p> 17223 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 17224 <hr> 17225 <b><a NAME="MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0">MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0 - Silicon debug status register 0</a></b><br> 17226 Address Offset = 32'h0000_d22a<br> 17227 Physical Address = 32'h0000_d22a<br> 17228 Reset Value = 16'h0000<br> 17229 Access = RO (16-bit only)<br> 17230 <table border=1 align=center width=100% cellpadding=0> 17231 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17232 <tr bgcolor=WHITE> 17233 <td bgcolor=WHITE align=center valign=top>15:00</td> 17234 <td align=left valign=top>RO</td> 17235 <td align=left valign=top>micro_silicon_debug_status_muxed_data</td> 17236 <td align=left> 17237 Muxed status data is made avaialable on this field.  <br> 17238 micro_silicon_debug_status_mux_sel is used to select the data source <br> 17239 Reset value is 0.</td></tr> 17240 </table><p> 17241 <A HREF="#MICRO_C_COM Registers">Return to MICRO_C_COM: common register block for all lanes within each Micro Top Table</A><p> 17242 <hr> 17243 <H1><a NAME="MICRO_INFO_COM Registers">MICRO_INFO_COM: Status Register for all Lanes within each Micro Top Registers</a></H1> 17244 <table border=1 align=center width=100% cellpadding=0> 17245 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 17246 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 17247 <tr> 17248 <td align=center>0xD230</td><td><A HREF="#MICRO_INFO_COM_CTRL0">MICRO_INFO_COM_CTRL0</A><br>MicroController Version Number</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">uc_version</div> </td> <td align=center>16'h0000</td></tr> 17249 <tr> 17250 <td align=center>0xD231</td><td><A HREF="#MICRO_INFO_COM_EVAL_STAT">MICRO_INFO_COM_EVAL_STAT</A><br>Equalization Status for all lanes</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">err_clr3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">err_clr2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">err_clr1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">err_clr0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_done_3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_done_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_done_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_done_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_err_3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_err_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_err_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_err_0</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_eval_3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_eval_2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_eval_1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_eval_0</div> </td> <td align=center>16'h0000</td></tr> 17251 </table><p> 17252 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 17253 <hr> 17254 <b><a NAME="MICRO_INFO_COM_CTRL0">MICRO_INFO_COM_CTRL0 - MicroController Version Number</a></b><br> 17255 Address Offset = 32'h0000_d230<br> 17256 Physical Address = 32'h0000_d230<br> 17257 Reset Value = 16'h0000<br> 17258 Access = RW (16-bit only)<br> 17259 <table border=1 align=center width=100% cellpadding=0> 17260 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17261 <tr bgcolor=WHITE> 17262 <td bgcolor=WHITE align=center valign=top>15:00</td> 17263 <td align=left valign=top>RW</td> 17264 <td align=left valign=top>uc_version</td> 17265 <td align=left> 17266 MicroController Version Number<br> 17267 Reset value is 0x0.</td></tr> 17268 </table><p> 17269 <A HREF="#MICRO_INFO_COM Registers">Return to MICRO_INFO_COM: Status Register for all Lanes within each Micro Top Table</A><p> 17270 <hr> 17271 <b><a NAME="MICRO_INFO_COM_EVAL_STAT">MICRO_INFO_COM_EVAL_STAT - Equalization Status for all lanes</a></b><br> 17272 Address Offset = 32'h0000_d231<br> 17273 Physical Address = 32'h0000_d231<br> 17274 Reset Value = 16'h0000<br> 17275 Access = RO (16-bit only)<br> 17276 <table border=1 align=center width=100% cellpadding=0> 17277 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17278 <tr bgcolor=WHITE> 17279 <td bgcolor=WHITE align=center valign=top>15</td> 17280 <td align=left valign=top>RO</td> 17281 <td align=left valign=top>err_clr3</td> 17282 <td align=left> 17283 Indicates Invalid Request was processed<br> 17284 Cleared on new equalization request<br> 17285 Reset value is 0x0.</td></tr> 17286 <tr bgcolor=WHITE> 17287 <td bgcolor=WHITE align=center valign=top>14</td> 17288 <td align=left valign=top>RO</td> 17289 <td align=left valign=top>err_clr2</td> 17290 <td align=left> 17291 Indicates Invalid Request was processed<br> 17292 Cleared on new equalization request<br> 17293 Reset value is 0x0.</td></tr> 17294 <tr bgcolor=WHITE> 17295 <td bgcolor=WHITE align=center valign=top>13</td> 17296 <td align=left valign=top>RO</td> 17297 <td align=left valign=top>err_clr1</td> 17298 <td align=left> 17299 Indicates Invalid Request was processed<br> 17300 Cleared on new equalization request<br> 17301 Reset value is 0x0.</td></tr> 17302 <tr bgcolor=WHITE> 17303 <td bgcolor=WHITE align=center valign=top>12</td> 17304 <td align=left valign=top>RO</td> 17305 <td align=left valign=top>err_clr0</td> 17306 <td align=left> 17307 Indicates Invalid Request was processed<br> 17308 Cleared on new equalization request<br> 17309 Reset value is 0x0.</td></tr> 17310 <tr bgcolor=WHITE> 17311 <td bgcolor=WHITE align=center valign=top>11</td> 17312 <td align=left valign=top>RO</td> 17313 <td align=left valign=top>eq_done_3</td> 17314 <td align=left> 17315 Indicates Equalization is complete and assert Phy_Status<br> 17316   Cleared on new equalization request<br> 17317 Reset value is 0x0.</td></tr> 17318 <tr bgcolor=WHITE> 17319 <td bgcolor=WHITE align=center valign=top>10</td> 17320 <td align=left valign=top>RO</td> 17321 <td align=left valign=top>eq_done_2</td> 17322 <td align=left> 17323 Indicates Equalization is complete and assert Phy_Status<br> 17324   Cleared on new equalization request<br> 17325 Reset value is 0x0.</td></tr> 17326 <tr bgcolor=WHITE> 17327 <td bgcolor=WHITE align=center valign=top>09</td> 17328 <td align=left valign=top>RO</td> 17329 <td align=left valign=top>eq_done_1</td> 17330 <td align=left> 17331 Indicates Equalization is complete and assert Phy_Status<br> 17332   Cleared on new equalization request<br> 17333 Reset value is 0x0.</td></tr> 17334 <tr bgcolor=WHITE> 17335 <td bgcolor=WHITE align=center valign=top>08</td> 17336 <td align=left valign=top>RO</td> 17337 <td align=left valign=top>eq_done_0</td> 17338 <td align=left> 17339 Indicates Equalization is complete and assert Phy_Status<br> 17340   Cleared on new equalization request<br> 17341 Reset value is 0x0.</td></tr> 17342 <tr bgcolor=WHITE> 17343 <td bgcolor=WHITE align=center valign=top>07</td> 17344 <td align=left valign=top>RO</td> 17345 <td align=left valign=top>eval_err_3</td> 17346 <td align=left> 17347 Indicates last Equalization was out of range <br> 17348   Cleared when Invalid Request has been processed<br> 17349 Reset value is 0x0.</td></tr> 17350 <tr bgcolor=WHITE> 17351 <td bgcolor=WHITE align=center valign=top>06</td> 17352 <td align=left valign=top>RO</td> 17353 <td align=left valign=top>eval_err_2</td> 17354 <td align=left> 17355 Indicates last Equalization was out of range <br> 17356   Cleared when Invalid Request has been processed<br> 17357 Reset value is 0x0.</td></tr> 17358 <tr bgcolor=WHITE> 17359 <td bgcolor=WHITE align=center valign=top>05</td> 17360 <td align=left valign=top>RO</td> 17361 <td align=left valign=top>eval_err_1</td> 17362 <td align=left> 17363 Indicates last Equalization was out of range <br> 17364   Cleared when Invalid Request has been processed<br> 17365 Reset value is 0x0.</td></tr> 17366 <tr bgcolor=WHITE> 17367 <td bgcolor=WHITE align=center valign=top>04</td> 17368 <td align=left valign=top>RO</td> 17369 <td align=left valign=top>eval_err_0</td> 17370 <td align=left> 17371 Indicates last Equalization was out of range <br> 17372   Cleared when Invalid Request has been processed<br> 17373 Reset value is 0x0.</td></tr> 17374 <tr bgcolor=WHITE> 17375 <td bgcolor=WHITE align=center valign=top>03</td> 17376 <td align=left valign=top>RO</td> 17377 <td align=left valign=top>eq_eval_3</td> 17378 <td align=left> 17379 Indicates request for Equalization <br> 17380   Cleared when Equalization is complete<br> 17381 Reset value is 0x0.</td></tr> 17382 <tr bgcolor=WHITE> 17383 <td bgcolor=WHITE align=center valign=top>02</td> 17384 <td align=left valign=top>RO</td> 17385 <td align=left valign=top>eq_eval_2</td> 17386 <td align=left> 17387 Indicates request for Equalization <br> 17388   Cleared when Equalization is complete<br> 17389 Reset value is 0x0.</td></tr> 17390 <tr bgcolor=WHITE> 17391 <td bgcolor=WHITE align=center valign=top>01</td> 17392 <td align=left valign=top>RO</td> 17393 <td align=left valign=top>eq_eval_1</td> 17394 <td align=left> 17395 Indicates request for Equalization <br> 17396   Cleared when Equalization is complete<br> 17397 Reset value is 0x0.</td></tr> 17398 <tr bgcolor=WHITE> 17399 <td bgcolor=WHITE align=center valign=top>00</td> 17400 <td align=left valign=top>RO</td> 17401 <td align=left valign=top>eq_eval_0</td> 17402 <td align=left> 17403 Indicates request for Equalization <br> 17404   Cleared when Equalization is complete<br> 17405 Reset value is 0x0.</td></tr> 17406 </table><p> 17407 <A HREF="#MICRO_INFO_COM Registers">Return to MICRO_INFO_COM: Status Register for all Lanes within each Micro Top Table</A><p> 17408 <hr> 17409 <H1><a NAME="MICRO_CTRL0 Registers">MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Registers</a></H1> 17410 <table border=1 align=center width=100% cellpadding=0> 17411 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 17412 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 17413 <tr> 17414 <td align=center>0xD240</td><td><A HREF="#MICRO_CTRL0_UC_CTRL0">MICRO_CTRL0_UC_CTRL0</A><br>MicroController Gen3 Ready Bit</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_gen3_rdy</div> </td> <td align=center>16'h0000</td></tr> 17415 <tr> 17416 <td align=center>0xD241</td><td><A HREF="#MICRO_CTRL0_UC_CTRL1">MICRO_CTRL0_UC_CTRL1</A><br>MicroController Feeback Direction Change and Figure of Merit Control Register</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_done</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_err_clr</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fdbk_dir_chg</div> </td> <td bgcolor=#FFFFFF align=center colspan="8"><div class="HT">fig_merit</div> </td> <td align=center>16'h0000</td></tr> 17417 <tr> 17418 <td align=center>0xD242</td><td><A HREF="#MICRO_CTRL0_UC_CTRL2">MICRO_CTRL0_UC_CTRL2</A><br>MicroController Gen1/Gen2 Peaking Filter Control</td><td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">pf2_lowp_ctrl_g2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pf_hiz_g2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pf_ctrl_g2</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">pf2_lowp_ctrl_g1</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_pf_hiz_g1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">pf_ctrl_g1</div> </td> <td align=center>16'h0707</td></tr> 17419 <tr> 17420 <td align=center>0xD243</td><td><A HREF="#MICRO_CTRL0_UC_CTRL3">MICRO_CTRL0_UC_CTRL3</A><br>MicroController Gen1/Gen2 VGA Control</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_en_dfe_clk_G1G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rx_m1_thresh_zero_G1G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rx_vga3_ctrl_G1G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rx_vga2_ctrl_G1G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">rx_vga1_ctrl_G1G2</div> </td> <td align=center>16'h1fff</td></tr> 17421 <tr> 17422 <td align=center>0xD244</td><td><A HREF="#MICRO_CTRL0_LP_INFO0">MICRO_CTRL0_LP_INFO0</A><br>Link Partner's Pre/Main Coeffecient</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">lp_main_coeff</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">lp_pre_coeff</div> </td> <td align=center>16'h0000</td></tr> 17423 <tr> 17424 <td align=center>0xD245</td><td><A HREF="#MICRO_CTRL0_LP_INFO1">MICRO_CTRL0_LP_INFO1</A><br>RX Hint and Link Partner's Post Coeffecient</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rx_hint</div> </td> <td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">lp_post_coeff</div> </td> <td align=center>16'h0000</td></tr> 17425 <tr> 17426 <td align=center>0xD246</td><td><A HREF="#MICRO_CTRL0_LP_INFO2">MICRO_CTRL0_LP_INFO2</A><br>Low Frequency and Full Swing</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">tx_lf</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">lp_fs</div> </td> <td align=center>16'h0000</td></tr> 17427 <tr> 17428 <td align=center>0xD247</td><td><A HREF="#MICRO_CTRL0_UC_EVAL_STAT">MICRO_CTRL0_UC_EVAL_STAT</A><br>Equalization Status</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">err_clr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_done</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eval_err</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">eq_eval</div> </td> <td align=center>16'h0000</td></tr> 17429 </table><p> 17430 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 17431 <hr> 17432 <b><a NAME="MICRO_CTRL0_UC_CTRL0">MICRO_CTRL0_UC_CTRL0 - MicroController Gen3 Ready Bit</a></b><br> 17433 Address Offset = 32'h0000_d240<br> 17434 Physical Address = 32'h0000_d240<br> 17435 Reset Value = 16'h0000<br> 17436 Access = RW (16-bit only)<br> 17437 <table border=1 align=center width=100% cellpadding=0> 17438 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17439 <tr bgcolor=WHITE> 17440 <td bgcolor=WHITE align=center valign=top>15:01</td> 17441 <td align=left valign=top>RSVD</td> 17442 <td align=left valign=top>Reserved</td> 17443 <td align=left> 17444 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17445 <tr bgcolor=WHITE> 17446 <td bgcolor=WHITE align=center valign=top>00</td> 17447 <td align=left valign=top>RW</td> 17448 <td align=left valign=top>uc_gen3_rdy</td> 17449 <td align=left> 17450 Once uC is released from reset, this bit will indicate<br> 17451 ready for Gen3, set by uC<br> 17452 Reset value is 0x0.</td></tr> 17453 </table><p> 17454 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17455 <hr> 17456 <b><a NAME="MICRO_CTRL0_UC_CTRL1">MICRO_CTRL0_UC_CTRL1 - MicroController Feeback Direction Change and Figure of Merit Control Register</a></b><br> 17457 Address Offset = 32'h0000_d241<br> 17458 Physical Address = 32'h0000_d241<br> 17459 Reset Value = 16'h0000<br> 17460 Access = RW (16-bit only)<br> 17461 <table border=1 align=center width=100% cellpadding=0> 17462 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17463 <tr bgcolor=WHITE> 17464 <td bgcolor=WHITE align=center valign=top>15</td> 17465 <td align=left valign=top>SC</td> 17466 <td align=left valign=top>eval_done</td> 17467 <td align=left> 17468 When asserted indicates uC is done calculating <br> 17469 fdbk_dir_chg and/or fig_merit and assert Phy Status<br> 17470 This bit will be cleared when eq_eval is asserted<br> 17471 Reset value is 0x0.</td></tr> 17472 <tr bgcolor=WHITE> 17473 <td bgcolor=WHITE align=center valign=top>14</td> 17474 <td align=left valign=top>SC</td> 17475 <td align=left valign=top>eval_err_clr</td> 17476 <td align=left> 17477 When asserted indicates the uC's last evaluation<br> 17478 was incorrect and this invalid request was <br> 17479 processed and is cleared<br> 17480 Reset value is 0x0.</td></tr> 17481 <tr bgcolor=WHITE> 17482 <td bgcolor=WHITE align=center valign=top>13:08</td> 17483 <td align=left valign=top>RW</td> 17484 <td align=left valign=top>fdbk_dir_chg</td> 17485 <td align=left> 17486 tbd<br> 17487 Reset value is 0x0.</td></tr> 17488 <tr bgcolor=WHITE> 17489 <td bgcolor=WHITE align=center valign=top>07:00</td> 17490 <td align=left valign=top>RW</td> 17491 <td align=left valign=top>fig_merit</td> 17492 <td align=left> 17493 tbd<br> 17494 Reset value is 0x0.</td></tr> 17495 </table><p> 17496 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17497 <hr> 17498 <b><a NAME="MICRO_CTRL0_UC_CTRL2">MICRO_CTRL0_UC_CTRL2 - MicroController Gen1/Gen2 Peaking Filter Control</a></b><br> 17499 Address Offset = 32'h0000_d242<br> 17500 Physical Address = 32'h0000_d242<br> 17501 Reset Value = 16'h0707<br> 17502 Access = RW (16-bit only)<br> 17503 <table border=1 align=center width=100% cellpadding=0> 17504 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17505 <tr bgcolor=WHITE> 17506 <td bgcolor=WHITE align=center valign=top>15:13</td> 17507 <td align=left valign=top>RW</td> 17508 <td align=left valign=top>pf2_lowp_ctrl_g2</td> 17509 <td align=left> 17510 Low Freq PF, low pass. Gray code<br> 17511 Reset value is 0x0.</td></tr> 17512 <tr bgcolor=WHITE> 17513 <td bgcolor=WHITE align=center valign=top>12</td> 17514 <td align=left valign=top>RW</td> 17515 <td align=left valign=top>rx_pf_hiz_g2</td> 17516 <td align=left> 17517 Enable hiz mode for peaking filter, shift the boost peak to a higher freq.<br> 17518 Reset value is 0x0.</td></tr> 17519 <tr bgcolor=WHITE> 17520 <td bgcolor=WHITE align=center valign=top>11:08</td> 17521 <td align=left valign=top>RW</td> 17522 <td align=left valign=top>pf_ctrl_g2</td> 17523 <td align=left> 17524 Init value of OS Gen 2 rate peaking filter. Gray code.<br> 17525 Reset value is 0x7.</td></tr> 17526 <tr bgcolor=WHITE> 17527 <td bgcolor=WHITE align=center valign=top>07:05</td> 17528 <td align=left valign=top>RW</td> 17529 <td align=left valign=top>pf2_lowp_ctrl_g1</td> 17530 <td align=left> 17531 Low Freq PF, low pass. Gray code<br> 17532 Reset value is 0x0.</td></tr> 17533 <tr bgcolor=WHITE> 17534 <td bgcolor=WHITE align=center valign=top>04</td> 17535 <td align=left valign=top>RW</td> 17536 <td align=left valign=top>rx_pf_hiz_g1</td> 17537 <td align=left> 17538 Enable hiz mode for peaking filter, shift the boost peak to a higher freq.<br> 17539 Reset value is 0x0.</td></tr> 17540 <tr bgcolor=WHITE> 17541 <td bgcolor=WHITE align=center valign=top>03:00</td> 17542 <td align=left valign=top>RW</td> 17543 <td align=left valign=top>pf_ctrl_g1</td> 17544 <td align=left> 17545 Init value of OS Gen 2 rate peaking filter. Gray code.<br> 17546 Reset value is 0x7.</td></tr> 17547 </table><p> 17548 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17549 <hr> 17550 <b><a NAME="MICRO_CTRL0_UC_CTRL3">MICRO_CTRL0_UC_CTRL3 - MicroController Gen1/Gen2 VGA Control</a></b><br> 17551 Address Offset = 32'h0000_d243<br> 17552 Physical Address = 32'h0000_d243<br> 17553 Reset Value = 16'h1fff<br> 17554 Access = RW (16-bit only)<br> 17555 <table border=1 align=center width=100% cellpadding=0> 17556 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17557 <tr bgcolor=WHITE> 17558 <td bgcolor=WHITE align=center valign=top>15:14</td> 17559 <td align=left valign=top>RSVD</td> 17560 <td align=left valign=top>Reserved</td> 17561 <td align=left> 17562 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17563 <tr bgcolor=WHITE> 17564 <td bgcolor=WHITE align=center valign=top>13</td> 17565 <td align=left valign=top>RW</td> 17566 <td align=left valign=top>rx_en_dfe_clk_G1G2</td> 17567 <td align=left> 17568 <br> 17569 Reset value is 0x0.</td></tr> 17570 <tr bgcolor=WHITE> 17571 <td bgcolor=WHITE align=center valign=top>12</td> 17572 <td align=left valign=top>RW</td> 17573 <td align=left valign=top>rx_m1_thresh_zero_G1G2</td> 17574 <td align=left> 17575 <br> 17576 Reset value is 0x1.</td></tr> 17577 <tr bgcolor=WHITE> 17578 <td bgcolor=WHITE align=center valign=top>11:08</td> 17579 <td align=left valign=top>RW</td> 17580 <td align=left valign=top>rx_vga3_ctrl_G1G2</td> 17581 <td align=left> 17582 <br> 17583 Reset value is 0xf.</td></tr> 17584 <tr bgcolor=WHITE> 17585 <td bgcolor=WHITE align=center valign=top>07:04</td> 17586 <td align=left valign=top>RW</td> 17587 <td align=left valign=top>rx_vga2_ctrl_G1G2</td> 17588 <td align=left> 17589 <br> 17590 Reset value is 0xf.</td></tr> 17591 <tr bgcolor=WHITE> 17592 <td bgcolor=WHITE align=center valign=top>03:00</td> 17593 <td align=left valign=top>RW</td> 17594 <td align=left valign=top>rx_vga1_ctrl_G1G2</td> 17595 <td align=left> 17596 <br> 17597 Reset value is 0xf.</td></tr> 17598 </table><p> 17599 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17600 <hr> 17601 <b><a NAME="MICRO_CTRL0_LP_INFO0">MICRO_CTRL0_LP_INFO0 - Link Partner's Pre/Main Coeffecient</a></b><br> 17602 Address Offset = 32'h0000_d244<br> 17603 Physical Address = 32'h0000_d244<br> 17604 Reset Value = 16'h0000<br> 17605 Access = RO (16-bit only)<br> 17606 <table border=1 align=center width=100% cellpadding=0> 17607 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17608 <tr bgcolor=WHITE> 17609 <td bgcolor=WHITE align=center valign=top>15:14</td> 17610 <td align=left valign=top>RSVD</td> 17611 <td align=left valign=top>Reserved</td> 17612 <td align=left> 17613 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17614 <tr bgcolor=WHITE> 17615 <td bgcolor=WHITE align=center valign=top>13:08</td> 17616 <td align=left valign=top>RO</td> 17617 <td align=left valign=top>lp_main_coeff</td> 17618 <td align=left> 17619 Link Partner's Main Coeffecient<br> 17620 Reset value is 0x0.</td></tr> 17621 <tr bgcolor=WHITE> 17622 <td bgcolor=WHITE align=center valign=top>07:06</td> 17623 <td align=left valign=top>RSVD</td> 17624 <td align=left valign=top>Reserved</td> 17625 <td align=left> 17626 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17627 <tr bgcolor=WHITE> 17628 <td bgcolor=WHITE align=center valign=top>05:00</td> 17629 <td align=left valign=top>RO</td> 17630 <td align=left valign=top>lp_pre_coeff</td> 17631 <td align=left> 17632 Link Partner's Pre Coeffecient<br> 17633 Reset value is 0x0.</td></tr> 17634 </table><p> 17635 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17636 <hr> 17637 <b><a NAME="MICRO_CTRL0_LP_INFO1">MICRO_CTRL0_LP_INFO1 - RX Hint and Link Partner's Post Coeffecient</a></b><br> 17638 Address Offset = 32'h0000_d245<br> 17639 Physical Address = 32'h0000_d245<br> 17640 Reset Value = 16'h0000<br> 17641 Access = RO (16-bit only)<br> 17642 <table border=1 align=center width=100% cellpadding=0> 17643 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17644 <tr bgcolor=WHITE> 17645 <td bgcolor=WHITE align=center valign=top>15</td> 17646 <td align=left valign=top>RSVD</td> 17647 <td align=left valign=top>Reserved</td> 17648 <td align=left> 17649 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 17650 <tr bgcolor=WHITE> 17651 <td bgcolor=WHITE align=center valign=top>14:12</td> 17652 <td align=left valign=top>RO</td> 17653 <td align=left valign=top>rx_hint</td> 17654 <td align=left> 17655 Link Partner's Main Coeffecient<br> 17656 Reset value is 0x0.</td></tr> 17657 <tr bgcolor=WHITE> 17658 <td bgcolor=WHITE align=center valign=top>11:06</td> 17659 <td align=left valign=top>RSVD</td> 17660 <td align=left valign=top>Reserved</td> 17661 <td align=left> 17662 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17663 <tr bgcolor=WHITE> 17664 <td bgcolor=WHITE align=center valign=top>05:00</td> 17665 <td align=left valign=top>RO</td> 17666 <td align=left valign=top>lp_post_coeff</td> 17667 <td align=left> 17668 Link Partner's Post Coeffecient<br> 17669 Reset value is 0x0.</td></tr> 17670 </table><p> 17671 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17672 <hr> 17673 <b><a NAME="MICRO_CTRL0_LP_INFO2">MICRO_CTRL0_LP_INFO2 - Low Frequency and Full Swing</a></b><br> 17674 Address Offset = 32'h0000_d246<br> 17675 Physical Address = 32'h0000_d246<br> 17676 Reset Value = 16'h0000<br> 17677 Access = RO (16-bit only)<br> 17678 <table border=1 align=center width=100% cellpadding=0> 17679 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17680 <tr bgcolor=WHITE> 17681 <td bgcolor=WHITE align=center valign=top>15:14</td> 17682 <td align=left valign=top>RSVD</td> 17683 <td align=left valign=top>Reserved</td> 17684 <td align=left> 17685 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17686 <tr bgcolor=WHITE> 17687 <td bgcolor=WHITE align=center valign=top>13:08</td> 17688 <td align=left valign=top>RO</td> 17689 <td align=left valign=top>tx_lf</td> 17690 <td align=left> 17691 Low Frequency value<br> 17692 Reset value is 0x0.</td></tr> 17693 <tr bgcolor=WHITE> 17694 <td bgcolor=WHITE align=center valign=top>07:06</td> 17695 <td align=left valign=top>RSVD</td> 17696 <td align=left valign=top>Reserved</td> 17697 <td align=left> 17698 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17699 <tr bgcolor=WHITE> 17700 <td bgcolor=WHITE align=center valign=top>05:00</td> 17701 <td align=left valign=top>RO</td> 17702 <td align=left valign=top>lp_fs</td> 17703 <td align=left> 17704 Full Swing value<br> 17705 Reset value is 0x0.</td></tr> 17706 </table><p> 17707 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17708 <hr> 17709 <b><a NAME="MICRO_CTRL0_UC_EVAL_STAT">MICRO_CTRL0_UC_EVAL_STAT - Equalization Status</a></b><br> 17710 Address Offset = 32'h0000_d247<br> 17711 Physical Address = 32'h0000_d247<br> 17712 Reset Value = 16'h0000<br> 17713 Access = RO (16-bit only)<br> 17714 <table border=1 align=center width=100% cellpadding=0> 17715 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17716 <tr bgcolor=WHITE> 17717 <td bgcolor=WHITE align=center valign=top>15:04</td> 17718 <td align=left valign=top>RSVD</td> 17719 <td align=left valign=top>Reserved</td> 17720 <td align=left> 17721 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17722 <tr bgcolor=WHITE> 17723 <td bgcolor=WHITE align=center valign=top>03</td> 17724 <td align=left valign=top>RO</td> 17725 <td align=left valign=top>err_clr</td> 17726 <td align=left> 17727 Indicates Invalid Request was processed<br> 17728 Cleared on new equalization request<br> 17729 Reset value is 0x0.</td></tr> 17730 <tr bgcolor=WHITE> 17731 <td bgcolor=WHITE align=center valign=top>02</td> 17732 <td align=left valign=top>RO</td> 17733 <td align=left valign=top>eq_done</td> 17734 <td align=left> 17735 Indicates Equalization is complete and assert Phy_Status<br> 17736   Cleared on new equalization request<br> 17737 Reset value is 0x0.</td></tr> 17738 <tr bgcolor=WHITE> 17739 <td bgcolor=WHITE align=center valign=top>01</td> 17740 <td align=left valign=top>RO</td> 17741 <td align=left valign=top>eval_err</td> 17742 <td align=left> 17743 Indicates last Equalization was out of range <br> 17744   Cleared when Invalid Request has been processed<br> 17745 Reset value is 0x0.</td></tr> 17746 <tr bgcolor=WHITE> 17747 <td bgcolor=WHITE align=center valign=top>00</td> 17748 <td align=left valign=top>RO</td> 17749 <td align=left valign=top>eq_eval</td> 17750 <td align=left> 17751 Indicates request for Equalization <br> 17752   Cleared when Equalization is complete<br> 17753 Reset value is 0x0.</td></tr> 17754 </table><p> 17755 <A HREF="#MICRO_CTRL0 Registers">Return to MICRO_CTRL0: Control Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17756 <hr> 17757 <H1><a NAME="MICRO_DBG Registers">MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Registers</a></H1> 17758 <table border=1 align=center width=100% cellpadding=0> 17759 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 17760 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 17761 <tr> 17762 <td align=center>0xD250</td><td><A HREF="#MICRO_DBG_STATUS0">MICRO_DBG_STATUS0</A><br>System Status  0</td><td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rate_sel</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rx_sigdet</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">rx_sigdet_st</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">uc_dbg_dsc_state</div> </td> <td align=center>16'h0000</td></tr> 17763 <tr> 17764 <td align=center>0xD251</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG1">MICRO_DBG_MICRO_DEBUG1</A><br>Micro Debug 1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg1</div> </td> <td align=center>16'h0000</td></tr> 17765 <tr> 17766 <td align=center>0xD252</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG2">MICRO_DBG_MICRO_DEBUG2</A><br>Micro Debug 2</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg2</div> </td> <td align=center>16'h0000</td></tr> 17767 <tr> 17768 <td align=center>0xD253</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG3">MICRO_DBG_MICRO_DEBUG3</A><br>Micro Debug 3</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg3</div> </td> <td align=center>16'h0000</td></tr> 17769 <tr> 17770 <td align=center>0xD254</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG4">MICRO_DBG_MICRO_DEBUG4</A><br>Micro Debug 4</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg4</div> </td> <td align=center>16'h0000</td></tr> 17771 <tr> 17772 <td align=center>0xD255</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG5">MICRO_DBG_MICRO_DEBUG5</A><br>Micro Debug 5</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg5</div> </td> <td align=center>16'h0000</td></tr> 17773 <tr> 17774 <td align=center>0xD256</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG6">MICRO_DBG_MICRO_DEBUG6</A><br>Micro Debug 6</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg6</div> </td> <td align=center>16'h0000</td></tr> 17775 <tr> 17776 <td align=center>0xD257</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG7">MICRO_DBG_MICRO_DEBUG7</A><br>Micro Debug 7</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg7</div> </td> <td align=center>16'h0000</td></tr> 17777 <tr> 17778 <td align=center>0xD258</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG8">MICRO_DBG_MICRO_DEBUG8</A><br>Micro Debug 8</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg8</div> </td> <td align=center>16'h0000</td></tr> 17779 <tr> 17780 <td align=center>0xD259</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG9">MICRO_DBG_MICRO_DEBUG9</A><br>Micro Debug 9</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg9</div> </td> <td align=center>16'h0000</td></tr> 17781 <tr> 17782 <td align=center>0xD25A</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG10">MICRO_DBG_MICRO_DEBUG10</A><br>Micro Debug 10</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg10</div> </td> <td align=center>16'h0000</td></tr> 17783 <tr> 17784 <td align=center>0xD25B</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG11">MICRO_DBG_MICRO_DEBUG11</A><br>Micro Debug 11</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg11</div> </td> <td align=center>16'h0000</td></tr> 17785 <tr> 17786 <td align=center>0xD25C</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG12">MICRO_DBG_MICRO_DEBUG12</A><br>Micro Debug 12</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg12</div> </td> <td align=center>16'h0000</td></tr> 17787 <tr> 17788 <td align=center>0xD25D</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG13">MICRO_DBG_MICRO_DEBUG13</A><br>Micro Debug 13</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg13</div> </td> <td align=center>16'h0000</td></tr> 17789 <tr> 17790 <td align=center>0xD25E</td><td><A HREF="#MICRO_DBG_MICRO_DEBUG14">MICRO_DBG_MICRO_DEBUG14</A><br>Micro Debug 14</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">micro_dbg14</div> </td> <td align=center>16'h0000</td></tr> 17791 </table><p> 17792 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 17793 <hr> 17794 <b><a NAME="MICRO_DBG_STATUS0">MICRO_DBG_STATUS0 - System Status 0</a></b><br> 17795 Address Offset = 32'h0000_d250<br> 17796 Physical Address = 32'h0000_d250<br> 17797 Reset Value = 16'h0000<br> 17798 Access = RO (16-bit only)<br> 17799 <table border=1 align=center width=100% cellpadding=0> 17800 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17801 <tr bgcolor=WHITE> 17802 <td bgcolor=WHITE align=center valign=top>15:14</td> 17803 <td align=left valign=top>RSVD</td> 17804 <td align=left valign=top>Reserved</td> 17805 <td align=left> 17806 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 17807 <tr bgcolor=WHITE> 17808 <td bgcolor=WHITE align=center valign=top>13:12</td> 17809 <td align=left valign=top>RO</td> 17810 <td align=left valign=top>rate_sel</td> 17811 <td align=left> 17812 Rate Select: 00=Gen1, 01=Gen2, 10=Gen3<br> 17813 Reset value is 0x0.</td></tr> 17814 <tr bgcolor=WHITE> 17815 <td bgcolor=WHITE align=center valign=top>11</td> 17816 <td align=left valign=top>RSVD</td> 17817 <td align=left valign=top>Reserved</td> 17818 <td align=left> 17819 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 17820 <tr bgcolor=WHITE> 17821 <td bgcolor=WHITE align=center valign=top>10:08</td> 17822 <td align=left valign=top>RO</td> 17823 <td align=left valign=top>rx_sigdet</td> 17824 <td align=left> 17825 10   9   8<br> 17826 x   x   1 = DSC<br> 17827 x   1   x = MAC<br> 17828 1   x   x = RAW<br> 17829 Reset value is 0x0.</td></tr> 17830 <tr bgcolor=WHITE> 17831 <td bgcolor=WHITE align=center valign=top>07:05</td> 17832 <td align=left valign=top>RO</td> 17833 <td align=left valign=top>rx_sigdet_st</td> 17834 <td align=left> 17835 ARM_ST         = 3'h0<br> 17836 PLL_LOCK_ST    = 3'h1<br> 17837 EIEOS_DET_ST   = 3'h2<br> 17838 SIGNAL_ON_ST   = 3'h3<br> 17839 SIGNAL_DROP_ST = 3'h4<br> 17840 WAIT_ST        = 3'h5<br> 17841 Reset value is 0x0.</td></tr> 17842 <tr bgcolor=WHITE> 17843 <td bgcolor=WHITE align=center valign=top>04:00</td> 17844 <td align=left valign=top>RO</td> 17845 <td align=left valign=top>uc_dbg_dsc_state</td> 17846 <td align=left> 17847 DSC State - refer to register 0xD01E for description<br> 17848 Reset value is 0x0.</td></tr> 17849 </table><p> 17850 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17851 <hr> 17852 <b><a NAME="MICRO_DBG_MICRO_DEBUG1">MICRO_DBG_MICRO_DEBUG1 - Micro Debug 1</a></b><br> 17853 Address Offset = 32'h0000_d251<br> 17854 Physical Address = 32'h0000_d251<br> 17855 Reset Value = 16'h0000<br> 17856 Access = RW (16-bit only)<br> 17857 <table border=1 align=center width=100% cellpadding=0> 17858 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17859 <tr bgcolor=WHITE> 17860 <td bgcolor=WHITE align=center valign=top>15:00</td> 17861 <td align=left valign=top>RW</td> 17862 <td align=left valign=top>micro_dbg1</td> 17863 <td align=left> 17864 Micro Debug 1 Register<br> 17865 Reset value is 0x0.</td></tr> 17866 </table><p> 17867 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17868 <hr> 17869 <b><a NAME="MICRO_DBG_MICRO_DEBUG2">MICRO_DBG_MICRO_DEBUG2 - Micro Debug 2</a></b><br> 17870 Address Offset = 32'h0000_d252<br> 17871 Physical Address = 32'h0000_d252<br> 17872 Reset Value = 16'h0000<br> 17873 Access = RW (16-bit only)<br> 17874 <table border=1 align=center width=100% cellpadding=0> 17875 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17876 <tr bgcolor=WHITE> 17877 <td bgcolor=WHITE align=center valign=top>15:00</td> 17878 <td align=left valign=top>RW</td> 17879 <td align=left valign=top>micro_dbg2</td> 17880 <td align=left> 17881 Micro Debug 2 Register<br> 17882 Reset value is 0x0.</td></tr> 17883 </table><p> 17884 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17885 <hr> 17886 <b><a NAME="MICRO_DBG_MICRO_DEBUG3">MICRO_DBG_MICRO_DEBUG3 - Micro Debug 3</a></b><br> 17887 Address Offset = 32'h0000_d253<br> 17888 Physical Address = 32'h0000_d253<br> 17889 Reset Value = 16'h0000<br> 17890 Access = RW (16-bit only)<br> 17891 <table border=1 align=center width=100% cellpadding=0> 17892 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17893 <tr bgcolor=WHITE> 17894 <td bgcolor=WHITE align=center valign=top>15:00</td> 17895 <td align=left valign=top>RW</td> 17896 <td align=left valign=top>micro_dbg3</td> 17897 <td align=left> 17898 Micro Debug 3 Register<br> 17899 Reset value is 0x0.</td></tr> 17900 </table><p> 17901 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17902 <hr> 17903 <b><a NAME="MICRO_DBG_MICRO_DEBUG4">MICRO_DBG_MICRO_DEBUG4 - Micro Debug 4</a></b><br> 17904 Address Offset = 32'h0000_d254<br> 17905 Physical Address = 32'h0000_d254<br> 17906 Reset Value = 16'h0000<br> 17907 Access = RW (16-bit only)<br> 17908 <table border=1 align=center width=100% cellpadding=0> 17909 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17910 <tr bgcolor=WHITE> 17911 <td bgcolor=WHITE align=center valign=top>15:00</td> 17912 <td align=left valign=top>RW</td> 17913 <td align=left valign=top>micro_dbg4</td> 17914 <td align=left> 17915 Micro Debug 4 Register<br> 17916 Reset value is 0x0.</td></tr> 17917 </table><p> 17918 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17919 <hr> 17920 <b><a NAME="MICRO_DBG_MICRO_DEBUG5">MICRO_DBG_MICRO_DEBUG5 - Micro Debug 5</a></b><br> 17921 Address Offset = 32'h0000_d255<br> 17922 Physical Address = 32'h0000_d255<br> 17923 Reset Value = 16'h0000<br> 17924 Access = RW (16-bit only)<br> 17925 <table border=1 align=center width=100% cellpadding=0> 17926 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17927 <tr bgcolor=WHITE> 17928 <td bgcolor=WHITE align=center valign=top>15:00</td> 17929 <td align=left valign=top>RW</td> 17930 <td align=left valign=top>micro_dbg5</td> 17931 <td align=left> 17932 Micro Debug 5 Register<br> 17933 Reset value is 0x0.</td></tr> 17934 </table><p> 17935 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17936 <hr> 17937 <b><a NAME="MICRO_DBG_MICRO_DEBUG6">MICRO_DBG_MICRO_DEBUG6 - Micro Debug 6</a></b><br> 17938 Address Offset = 32'h0000_d256<br> 17939 Physical Address = 32'h0000_d256<br> 17940 Reset Value = 16'h0000<br> 17941 Access = RW (16-bit only)<br> 17942 <table border=1 align=center width=100% cellpadding=0> 17943 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17944 <tr bgcolor=WHITE> 17945 <td bgcolor=WHITE align=center valign=top>15:00</td> 17946 <td align=left valign=top>RW</td> 17947 <td align=left valign=top>micro_dbg6</td> 17948 <td align=left> 17949 Micro Debug 6 Register<br> 17950 Reset value is 0x0.</td></tr> 17951 </table><p> 17952 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17953 <hr> 17954 <b><a NAME="MICRO_DBG_MICRO_DEBUG7">MICRO_DBG_MICRO_DEBUG7 - Micro Debug 7</a></b><br> 17955 Address Offset = 32'h0000_d257<br> 17956 Physical Address = 32'h0000_d257<br> 17957 Reset Value = 16'h0000<br> 17958 Access = RW (16-bit only)<br> 17959 <table border=1 align=center width=100% cellpadding=0> 17960 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17961 <tr bgcolor=WHITE> 17962 <td bgcolor=WHITE align=center valign=top>15:00</td> 17963 <td align=left valign=top>RW</td> 17964 <td align=left valign=top>micro_dbg7</td> 17965 <td align=left> 17966 Micro Debug 7 Register<br> 17967 Reset value is 0x0.</td></tr> 17968 </table><p> 17969 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17970 <hr> 17971 <b><a NAME="MICRO_DBG_MICRO_DEBUG8">MICRO_DBG_MICRO_DEBUG8 - Micro Debug 8</a></b><br> 17972 Address Offset = 32'h0000_d258<br> 17973 Physical Address = 32'h0000_d258<br> 17974 Reset Value = 16'h0000<br> 17975 Access = RW (16-bit only)<br> 17976 <table border=1 align=center width=100% cellpadding=0> 17977 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17978 <tr bgcolor=WHITE> 17979 <td bgcolor=WHITE align=center valign=top>15:00</td> 17980 <td align=left valign=top>RW</td> 17981 <td align=left valign=top>micro_dbg8</td> 17982 <td align=left> 17983 Micro Debug 8 Register<br> 17984 Reset value is 0x0.</td></tr> 17985 </table><p> 17986 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 17987 <hr> 17988 <b><a NAME="MICRO_DBG_MICRO_DEBUG9">MICRO_DBG_MICRO_DEBUG9 - Micro Debug 9</a></b><br> 17989 Address Offset = 32'h0000_d259<br> 17990 Physical Address = 32'h0000_d259<br> 17991 Reset Value = 16'h0000<br> 17992 Access = RW (16-bit only)<br> 17993 <table border=1 align=center width=100% cellpadding=0> 17994 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 17995 <tr bgcolor=WHITE> 17996 <td bgcolor=WHITE align=center valign=top>15:00</td> 17997 <td align=left valign=top>RW</td> 17998 <td align=left valign=top>micro_dbg9</td> 17999 <td align=left> 18000 Micro Debug 9 Register<br> 18001 Reset value is 0x0.</td></tr> 18002 </table><p> 18003 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 18004 <hr> 18005 <b><a NAME="MICRO_DBG_MICRO_DEBUG10">MICRO_DBG_MICRO_DEBUG10 - Micro Debug 10</a></b><br> 18006 Address Offset = 32'h0000_d25a<br> 18007 Physical Address = 32'h0000_d25a<br> 18008 Reset Value = 16'h0000<br> 18009 Access = RW (16-bit only)<br> 18010 <table border=1 align=center width=100% cellpadding=0> 18011 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18012 <tr bgcolor=WHITE> 18013 <td bgcolor=WHITE align=center valign=top>15:00</td> 18014 <td align=left valign=top>RW</td> 18015 <td align=left valign=top>micro_dbg10</td> 18016 <td align=left> 18017 Micro Debug 10 Register<br> 18018 Reset value is 0x0.</td></tr> 18019 </table><p> 18020 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 18021 <hr> 18022 <b><a NAME="MICRO_DBG_MICRO_DEBUG11">MICRO_DBG_MICRO_DEBUG11 - Micro Debug 11</a></b><br> 18023 Address Offset = 32'h0000_d25b<br> 18024 Physical Address = 32'h0000_d25b<br> 18025 Reset Value = 16'h0000<br> 18026 Access = RW (16-bit only)<br> 18027 <table border=1 align=center width=100% cellpadding=0> 18028 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18029 <tr bgcolor=WHITE> 18030 <td bgcolor=WHITE align=center valign=top>15:00</td> 18031 <td align=left valign=top>RW</td> 18032 <td align=left valign=top>micro_dbg11</td> 18033 <td align=left> 18034 Micro Debug 11 Register<br> 18035 Reset value is 0x0.</td></tr> 18036 </table><p> 18037 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 18038 <hr> 18039 <b><a NAME="MICRO_DBG_MICRO_DEBUG12">MICRO_DBG_MICRO_DEBUG12 - Micro Debug 12</a></b><br> 18040 Address Offset = 32'h0000_d25c<br> 18041 Physical Address = 32'h0000_d25c<br> 18042 Reset Value = 16'h0000<br> 18043 Access = RW (16-bit only)<br> 18044 <table border=1 align=center width=100% cellpadding=0> 18045 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18046 <tr bgcolor=WHITE> 18047 <td bgcolor=WHITE align=center valign=top>15:00</td> 18048 <td align=left valign=top>RW</td> 18049 <td align=left valign=top>micro_dbg12</td> 18050 <td align=left> 18051 Micro Debug 12 Register<br> 18052 Reset value is 0x0.</td></tr> 18053 </table><p> 18054 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 18055 <hr> 18056 <b><a NAME="MICRO_DBG_MICRO_DEBUG13">MICRO_DBG_MICRO_DEBUG13 - Micro Debug 13</a></b><br> 18057 Address Offset = 32'h0000_d25d<br> 18058 Physical Address = 32'h0000_d25d<br> 18059 Reset Value = 16'h0000<br> 18060 Access = RW (16-bit only)<br> 18061 <table border=1 align=center width=100% cellpadding=0> 18062 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18063 <tr bgcolor=WHITE> 18064 <td bgcolor=WHITE align=center valign=top>15:00</td> 18065 <td align=left valign=top>RW</td> 18066 <td align=left valign=top>micro_dbg13</td> 18067 <td align=left> 18068 Micro Debug 13 Register<br> 18069 Reset value is 0x0.</td></tr> 18070 </table><p> 18071 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 18072 <hr> 18073 <b><a NAME="MICRO_DBG_MICRO_DEBUG14">MICRO_DBG_MICRO_DEBUG14 - Micro Debug 14</a></b><br> 18074 Address Offset = 32'h0000_d25e<br> 18075 Physical Address = 32'h0000_d25e<br> 18076 Reset Value = 16'h0000<br> 18077 Access = RW (16-bit only)<br> 18078 <table border=1 align=center width=100% cellpadding=0> 18079 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18080 <tr bgcolor=WHITE> 18081 <td bgcolor=WHITE align=center valign=top>15:00</td> 18082 <td align=left valign=top>RW</td> 18083 <td align=left valign=top>micro_dbg14</td> 18084 <td align=left> 18085 Micro Debug 14 Register<br> 18086 Reset value is 0x0.</td></tr> 18087 </table><p> 18088 <A HREF="#MICRO_DBG Registers">Return to MICRO_DBG: Debug Registers [One Copy Per Lane] within each Micro Top Table</A><p> 18089 <hr> 18090 <H1><a NAME="DSC_G Registers">DSC_G: per lane register block [One Copy Per Lane] Registers</a></H1> 18091 <table border=1 align=center width=100% cellpadding=0> 18092 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 18093 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 18094 <tr> 18095 <td align=center>0xD260</td><td><A HREF="#DSC_G_DSC_SM_CTL_15">DSC_G_DSC_SM_CTL_15</A><br>DSC SM Ctl 15</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">L1_phase_err_offset_en_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">L1_phase_err_offset_en_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">L0s_phase_err_offset_en_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">L0s_phase_err_offset_en_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">L0s_phase_err_offset_en_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">phase_err_offset_en_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">phase_err_offset_en_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">phase_err_offset_en_G1</div> </td> <td align=center>16'hffff</td></tr> 18096 <tr> 18097 <td align=center>0xD261</td><td><A HREF="#DSC_G_DSC_SM_CTL_16">DSC_G_DSC_SM_CTL_16</A><br>DSC SM Ctl 16</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxL1Active_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxL1Active_frc_val</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">phase_err_offset_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">phase_err_offset_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">phase_err_offset_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">L1_phase_err_offset_en_G3</div> </td> <td align=center>16'h0003</td></tr> 18098 <tr> 18099 <td align=center>0xD262</td><td><A HREF="#DSC_G_DSC_SM_CTL_17">DSC_G_DSC_SM_CTL_17</A><br>DSC SM Ctl 17</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">L1_phase_err_offset_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">L0s_phase_err_offset_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">L0s_phase_err_offset_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">L0s_phase_err_offset_G1</div> </td> <td align=center>16'h0224</td></tr> 18100 <tr> 18101 <td align=center>0xD263</td><td><A HREF="#DSC_G_DSC_SM_CTL_18">DSC_G_DSC_SM_CTL_18</A><br>DSC SM Ctl 18</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxL0sL1Failure_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxL0sL1Failure_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_frz_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_frz_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_frz_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_frz_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_frz_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_frz_frc_val</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">L1_phase_err_offset_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">L1_phase_err_offset_G2</div> </td> <td align=center>16'h0022</td></tr> 18102 <tr> 18103 <td align=center>0xD264</td><td><A HREF="#DSC_G_DSC_SM_CTL_19">DSC_G_DSC_SM_CTL_19</A><br>DSC SM Ctl 19</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxL0sActive_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxL0sActive_frc_val</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">L0sL1_lfsr_cnt_G2</div> </td> <td align=center>16'h1df7</td></tr> 18104 <tr> 18105 <td align=center>0xD265</td><td><A HREF="#DSC_G_DSC_SM_CTL_20">DSC_G_DSC_SM_CTL_20</A><br>DSC SM Ctl 20</td><td bgcolor=#CCCCCC align=center colspan="3"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">L0sL1_lfsr_cnt_G3</div> </td> <td align=center>16'h17f1</td></tr> 18106 <tr> 18107 <td align=center>0xD266</td><td><A HREF="#DSC_G_DSC_SM_CTL_21">DSC_G_DSC_SM_CTL_21</A><br>DSC SM Ctl 21</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">hwtune_en_G1G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">ucuse_en_G1G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">use_facq_done_G1G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">norm_lfsr_cnt_G1G2</div> </td> <td align=center>16'h1257</td></tr> 18108 <tr> 18109 <td align=center>0xD267</td><td><A HREF="#DSC_G_DSC_SM_CTL_22">DSC_G_DSC_SM_CTL_22</A><br>DSC SM Ctl 22</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">facq_en_disable_G3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">facq_en_disable_G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">facq_en_disable_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">norm_lfsr_cnt_G3</div> </td> <td align=center>16'h1c1e</td></tr> 18110 <tr> 18111 <td align=center>0xD268</td><td><A HREF="#DSC_G_DSC_SM_CTL_23">DSC_G_DSC_SM_CTL_23</A><br>DSC SM Ctl 23</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_peak_polarity</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_cdr_sttl_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_cdr_sttl_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_cdr_sttl_timeout_G1</div> </td> <td align=center>16'h210c</td></tr> 18112 <tr> 18113 <td align=center>0xD269</td><td><A HREF="#DSC_G_DSC_SM_CTL_24">DSC_G_DSC_SM_CTL_24</A><br>DSC SM Ctl 24</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_acc_reset</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">slicer_offset_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">slicer_offset_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">slicer_offset_timeout_G1</div> </td> <td align=center>16'h2000</td></tr> 18114 <tr> 18115 <td align=center>0xD26A</td><td><A HREF="#DSC_G_DSC_SM_CTL_25">DSC_G_DSC_SM_CTL_25</A><br>DSC SM Ctl 25</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dc_offset_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dc_offset_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">dc_offset_timeout_G1</div> </td> <td align=center>16'h3180</td></tr> 18116 <tr> 18117 <td align=center>0xD26B</td><td><A HREF="#DSC_G_DSC_SM_CTL_26">DSC_G_DSC_SM_CTL_26</A><br>DSC SM Ctl 26</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">adj_pi_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">step_dir</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">m1_minus_d_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">m1_minus_d_G1</div> </td> <td align=center>16'h8000</td></tr> 18118 <tr> 18119 <td align=center>0xD26C</td><td><A HREF="#DSC_G_DSC_SM_CTL_27">DSC_G_DSC_SM_CTL_27</A><br>DSC SM Ctl 27</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_use_odd_G3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_use_even_G3</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_use_odd_G1G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dc_offset_use_even_G1G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_sm_manual_mode</div> </td> <td bgcolor=#FFFFFF align=center colspan="7"><div class="HT">m1_minus_d_G3</div> </td> <td align=center>16'h0ea0</td></tr> 18120 <tr> 18121 <td align=center>0xD26D</td><td><A HREF="#DSC_G_DSC_SM_CTL_28">DSC_G_DSC_SM_CTL_28</A><br>DSC SM Ctl 28</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_sm_tmux_sel</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_zero_from_m1_slicer_g2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">cdr_zero_from_m1_slicer_g1</div> </td> <td bgcolor=#FFFFFF align=center colspan="13"><div class="HT">L0sL1_lfsr_cnt_G1</div> </td> <td align=center>16'h0bd8</td></tr> 18122 <tr> 18123 <td align=center>0xD26E</td><td><A HREF="#DSC_G_DSC_SM_CTL_29">DSC_G_DSC_SM_CTL_29</A><br>DSC SM Ctl 29</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">sigdet_frc_init</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">disable_L0s_exit</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">disable_L1_exit</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_slicer_offset_done_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_slicer_offset_done_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_slicer_offset_cnt_frc</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dsc_slicer_offset_cnt_frc_val</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">redo_slicer_calibration</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">slicer_calibration_mask</div> </td> <td align=center>16'h0040</td></tr> 18124 </table><p> 18125 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 18126 <hr> 18127 <b><a NAME="DSC_G_DSC_SM_CTL_15">DSC_G_DSC_SM_CTL_15 - DSC SM Ctl 15</a></b><br> 18128 Address Offset = 32'h0000_d260<br> 18129 Physical Address = 32'h0000_d260<br> 18130 Reset Value = 16'hffff<br> 18131 Access = RW (16-bit only)<br> 18132 <table border=1 align=center width=100% cellpadding=0> 18133 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18134 <tr bgcolor=WHITE> 18135 <td bgcolor=WHITE align=center valign=top>15:14</td> 18136 <td align=left valign=top>RW</td> 18137 <td align=left valign=top>L1_phase_err_offset_en_G2</td> 18138 <td align=left> 18139 Phase Error Offset Enable for L0sL1_ACQ_CDR states in gen2 speed. <br> 18140 Reset value is 0x3.</td></tr> 18141 <tr bgcolor=WHITE> 18142 <td bgcolor=WHITE align=center valign=top>13:12</td> 18143 <td align=left valign=top>RW</td> 18144 <td align=left valign=top>L1_phase_err_offset_en_G1</td> 18145 <td align=left> 18146 Phase Error Offset Enable for L0sL1_ACQ_CDR states in gen1 speed. <br> 18147 Reset value is 0x3.</td></tr> 18148 <tr bgcolor=WHITE> 18149 <td bgcolor=WHITE align=center valign=top>11:10</td> 18150 <td align=left valign=top>RW</td> 18151 <td align=left valign=top>L0s_phase_err_offset_en_G3</td> 18152 <td align=left> 18153 Phase Error Offset Enable for L0sL1_ACQ_CDR states in gen3 speed. <br> 18154 Reset value is 0x3.</td></tr> 18155 <tr bgcolor=WHITE> 18156 <td bgcolor=WHITE align=center valign=top>09:08</td> 18157 <td align=left valign=top>RW</td> 18158 <td align=left valign=top>L0s_phase_err_offset_en_G2</td> 18159 <td align=left> 18160 Phase Error Offset Enable for L0sL1_ACQ_CDR states in gen2 speed. <br> 18161 Reset value is 0x3.</td></tr> 18162 <tr bgcolor=WHITE> 18163 <td bgcolor=WHITE align=center valign=top>07:06</td> 18164 <td align=left valign=top>RW</td> 18165 <td align=left valign=top>L0s_phase_err_offset_en_G1</td> 18166 <td align=left> 18167 Phase Error Offset Enable for L0sL1_ACQ_CDR states in gen1 speed. <br> 18168 Reset value is 0x3.</td></tr> 18169 <tr bgcolor=WHITE> 18170 <td bgcolor=WHITE align=center valign=top>05:04</td> 18171 <td align=left valign=top>RW</td> 18172 <td align=left valign=top>phase_err_offset_en_G3</td> 18173 <td align=left> 18174 Phase Error Offset Enable for non-L0sL1_ACQ_CDR states in gen3 speed. <br> 18175 Reset value is 0x3.</td></tr> 18176 <tr bgcolor=WHITE> 18177 <td bgcolor=WHITE align=center valign=top>03:02</td> 18178 <td align=left valign=top>RW</td> 18179 <td align=left valign=top>phase_err_offset_en_G2</td> 18180 <td align=left> 18181 Phase Error Offset Enable for non-L0sL1_ACQ_CDR states in gen2 speed. <br> 18182 Reset value is 0x3.</td></tr> 18183 <tr bgcolor=WHITE> 18184 <td bgcolor=WHITE align=center valign=top>01:00</td> 18185 <td align=left valign=top>RW</td> 18186 <td align=left valign=top>phase_err_offset_en_G1</td> 18187 <td align=left> 18188 Phase Error Offset Enable for non-L0sL1_ACQ_CDR states in gen1 speed. <br> 18189 Reset value is 0x3.</td></tr> 18190 </table><p> 18191 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18192 <hr> 18193 <b><a NAME="DSC_G_DSC_SM_CTL_16">DSC_G_DSC_SM_CTL_16 - DSC SM Ctl 16</a></b><br> 18194 Address Offset = 32'h0000_d261<br> 18195 Physical Address = 32'h0000_d261<br> 18196 Reset Value = 16'h0003<br> 18197 Access = RW (16-bit only)<br> 18198 <table border=1 align=center width=100% cellpadding=0> 18199 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18200 <tr bgcolor=WHITE> 18201 <td bgcolor=WHITE align=center valign=top>15</td> 18202 <td align=left valign=top>RW</td> 18203 <td align=left valign=top>RxL1Active_frc</td> 18204 <td align=left> 18205 Force RXL1Active <br> 18206 Reset value is 0x0.</td></tr> 18207 <tr bgcolor=WHITE> 18208 <td bgcolor=WHITE align=center valign=top>14</td> 18209 <td align=left valign=top>RW</td> 18210 <td align=left valign=top>RxL1Active_frc_val</td> 18211 <td align=left> 18212 Force RXL1Active value<br> 18213 Reset value is 0x0.</td></tr> 18214 <tr bgcolor=WHITE> 18215 <td bgcolor=WHITE align=center valign=top>13:10</td> 18216 <td align=left valign=top>RW</td> 18217 <td align=left valign=top>phase_err_offset_G3</td> 18218 <td align=left> 18219 Phase Error Offset for non-L0sL1_ACQ_CDR states in gen3 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 18220 7/4, depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18221 Reset value is 0x0.</td></tr> 18222 <tr bgcolor=WHITE> 18223 <td bgcolor=WHITE align=center valign=top>09:06</td> 18224 <td align=left valign=top>RW</td> 18225 <td align=left valign=top>phase_err_offset_G2</td> 18226 <td align=left> 18227 Phase Error Offset for non-L0sL1_ACQ_CDR states in gen2 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 18228 7/4, depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18229 Reset value is 0x0.</td></tr> 18230 <tr bgcolor=WHITE> 18231 <td bgcolor=WHITE align=center valign=top>05:02</td> 18232 <td align=left valign=top>RW</td> 18233 <td align=left valign=top>phase_err_offset_G1</td> 18234 <td align=left> 18235 Phase Error Offset for non-L0sL1_ACQ_CDR states in gen1 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 18236 7/4, depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18237 Reset value is 0x0.</td></tr> 18238 <tr bgcolor=WHITE> 18239 <td bgcolor=WHITE align=center valign=top>01:00</td> 18240 <td align=left valign=top>RW</td> 18241 <td align=left valign=top>L1_phase_err_offset_en_G3</td> 18242 <td align=left> 18243 Phase Error Offset Enable for L0sL1_ACQ_CDR states in gen3 speed. <br> 18244 Reset value is 0x3.</td></tr> 18245 </table><p> 18246 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18247 <hr> 18248 <b><a NAME="DSC_G_DSC_SM_CTL_17">DSC_G_DSC_SM_CTL_17 - DSC SM Ctl 17</a></b><br> 18249 Address Offset = 32'h0000_d262<br> 18250 Physical Address = 32'h0000_d262<br> 18251 Reset Value = 16'h0224<br> 18252 Access = RW (16-bit only)<br> 18253 <table border=1 align=center width=100% cellpadding=0> 18254 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18255 <tr bgcolor=WHITE> 18256 <td bgcolor=WHITE align=center valign=top>15:12</td> 18257 <td align=left valign=top>RW</td> 18258 <td align=left valign=top>L1_phase_err_offset_G1</td> 18259 <td align=left> 18260 Phase Error Offset for L0sL1_ACQ_CDR states in gen1 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, 18261 depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18262 Reset value is 0x0.</td></tr> 18263 <tr bgcolor=WHITE> 18264 <td bgcolor=WHITE align=center valign=top>11:08</td> 18265 <td align=left valign=top>RW</td> 18266 <td align=left valign=top>L0s_phase_err_offset_G3</td> 18267 <td align=left> 18268 Phase Error Offset for L0sL1_ACQ_CDR states in gen3 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, 18269 depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18270 Reset value is 0x2.</td></tr> 18271 <tr bgcolor=WHITE> 18272 <td bgcolor=WHITE align=center valign=top>07:04</td> 18273 <td align=left valign=top>RW</td> 18274 <td align=left valign=top>L0s_phase_err_offset_G2</td> 18275 <td align=left> 18276 Phase Error Offset for L0sL1_ACQ_CDR states in gen2 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, 18277 depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18278 Reset value is 0x2.</td></tr> 18279 <tr bgcolor=WHITE> 18280 <td bgcolor=WHITE align=center valign=top>03:00</td> 18281 <td align=left valign=top>RW</td> 18282 <td align=left valign=top>L0s_phase_err_offset_G1</td> 18283 <td align=left> 18284 Phase Error Offset for L0sL1_ACQ_CDR states in gen3 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, 18285 depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18286 Reset value is 0x4.</td></tr> 18287 </table><p> 18288 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18289 <hr> 18290 <b><a NAME="DSC_G_DSC_SM_CTL_18">DSC_G_DSC_SM_CTL_18 - DSC SM Ctl 18</a></b><br> 18291 Address Offset = 32'h0000_d263<br> 18292 Physical Address = 32'h0000_d263<br> 18293 Reset Value = 16'h0022<br> 18294 Access = RW (16-bit only)<br> 18295 <table border=1 align=center width=100% cellpadding=0> 18296 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18297 <tr bgcolor=WHITE> 18298 <td bgcolor=WHITE align=center valign=top>15</td> 18299 <td align=left valign=top>RW</td> 18300 <td align=left valign=top>RxL0sL1Failure_frc</td> 18301 <td align=left> 18302 Force RxL0sL1Failure <br> 18303 Reset value is 0x0.</td></tr> 18304 <tr bgcolor=WHITE> 18305 <td bgcolor=WHITE align=center valign=top>14</td> 18306 <td align=left valign=top>RW</td> 18307 <td align=left valign=top>RxL0sL1Failure_frc_val</td> 18308 <td align=left> 18309 Force RxL0sL1Failure value<br> 18310 Reset value is 0x0.</td></tr> 18311 <tr bgcolor=WHITE> 18312 <td bgcolor=WHITE align=center valign=top>13</td> 18313 <td align=left valign=top>RW</td> 18314 <td align=left valign=top>dc_offset_frz_frc</td> 18315 <td align=left> 18316 DC Offset freeze force. <br> 18317 Reset value is 0x0.</td></tr> 18318 <tr bgcolor=WHITE> 18319 <td bgcolor=WHITE align=center valign=top>12</td> 18320 <td align=left valign=top>RW</td> 18321 <td align=left valign=top>dc_offset_frz_frc_val</td> 18322 <td align=left> 18323 DC Offset freeze force value. <br> 18324 Reset value is 0x0.</td></tr> 18325 <tr bgcolor=WHITE> 18326 <td bgcolor=WHITE align=center valign=top>11</td> 18327 <td align=left valign=top>RW</td> 18328 <td align=left valign=top>dfe_frz_frc</td> 18329 <td align=left> 18330 DFE freeze force. <br> 18331 Reset value is 0x0.</td></tr> 18332 <tr bgcolor=WHITE> 18333 <td bgcolor=WHITE align=center valign=top>10</td> 18334 <td align=left valign=top>RW</td> 18335 <td align=left valign=top>dfe_frz_frc_val</td> 18336 <td align=left> 18337 DFE freeze force value. <br> 18338 Reset value is 0x0.</td></tr> 18339 <tr bgcolor=WHITE> 18340 <td bgcolor=WHITE align=center valign=top>09</td> 18341 <td align=left valign=top>RW</td> 18342 <td align=left valign=top>vga_frz_frc</td> 18343 <td align=left> 18344 VGA freeze force. <br> 18345 Reset value is 0x0.</td></tr> 18346 <tr bgcolor=WHITE> 18347 <td bgcolor=WHITE align=center valign=top>08</td> 18348 <td align=left valign=top>RW</td> 18349 <td align=left valign=top>vga_frz_frc_val</td> 18350 <td align=left> 18351 VGA freeze force value. <br> 18352 Reset value is 0x0.</td></tr> 18353 <tr bgcolor=WHITE> 18354 <td bgcolor=WHITE align=center valign=top>07:04</td> 18355 <td align=left valign=top>RW</td> 18356 <td align=left valign=top>L1_phase_err_offset_G3</td> 18357 <td align=left> 18358 Phase Error Offset for L0sL1_ACQ_CDR states in gen3 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, 18359 depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18360 Reset value is 0x2.</td></tr> 18361 <tr bgcolor=WHITE> 18362 <td bgcolor=WHITE align=center valign=top>03:00</td> 18363 <td align=left valign=top>RW</td> 18364 <td align=left valign=top>L1_phase_err_offset_G2</td> 18365 <td align=left> 18366 Phase Error Offset for L0sL1_ACQ_CDR states in gen2 speed. Signed value. Valid range is -8 to 7. This translates to either -8/2 to 7/2 or -8/4 to 7/4, 18367 depending on how rg_phase_err_offset_mult_2 is set. By default is is -8/4 to 7/4 adding into VCO reg. <br> 18368 Reset value is 0x2.</td></tr> 18369 </table><p> 18370 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18371 <hr> 18372 <b><a NAME="DSC_G_DSC_SM_CTL_19">DSC_G_DSC_SM_CTL_19 - DSC SM Ctl 19</a></b><br> 18373 Address Offset = 32'h0000_d264<br> 18374 Physical Address = 32'h0000_d264<br> 18375 Reset Value = 16'h1df7<br> 18376 Access = RW (16-bit only)<br> 18377 <table border=1 align=center width=100% cellpadding=0> 18378 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18379 <tr bgcolor=WHITE> 18380 <td bgcolor=WHITE align=center valign=top>15</td> 18381 <td align=left valign=top>RSVD</td> 18382 <td align=left valign=top>Reserved</td> 18383 <td align=left> 18384 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 18385 <tr bgcolor=WHITE> 18386 <td bgcolor=WHITE align=center valign=top>14</td> 18387 <td align=left valign=top>RW</td> 18388 <td align=left valign=top>RxL0sActive_frc</td> 18389 <td align=left> 18390 Force RXL0sActive <br> 18391 Reset value is 0x0.</td></tr> 18392 <tr bgcolor=WHITE> 18393 <td bgcolor=WHITE align=center valign=top>13</td> 18394 <td align=left valign=top>RW</td> 18395 <td align=left valign=top>RxL0sActive_frc_val</td> 18396 <td align=left> 18397 Force RXL0sActive value<br> 18398 Reset value is 0x0.</td></tr> 18399 <tr bgcolor=WHITE> 18400 <td bgcolor=WHITE align=center valign=top>12:00</td> 18401 <td align=left valign=top>RW</td> 18402 <td align=left valign=top>L0sL1_lfsr_cnt_G2</td> 18403 <td align=left> 18404 LFSR timer start value for L0sL1 timers in gen2 speed. (12ns) <br> 18405 Reset value is 0x1df7.</td></tr> 18406 </table><p> 18407 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18408 <hr> 18409 <b><a NAME="DSC_G_DSC_SM_CTL_20">DSC_G_DSC_SM_CTL_20 - DSC SM Ctl 20</a></b><br> 18410 Address Offset = 32'h0000_d265<br> 18411 Physical Address = 32'h0000_d265<br> 18412 Reset Value = 16'h17f1<br> 18413 Access = RW (16-bit only)<br> 18414 <table border=1 align=center width=100% cellpadding=0> 18415 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18416 <tr bgcolor=WHITE> 18417 <td bgcolor=WHITE align=center valign=top>15:13</td> 18418 <td align=left valign=top>RSVD</td> 18419 <td align=left valign=top>Reserved</td> 18420 <td align=left> 18421 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 18422 <tr bgcolor=WHITE> 18423 <td bgcolor=WHITE align=center valign=top>12:00</td> 18424 <td align=left valign=top>RW</td> 18425 <td align=left valign=top>L0sL1_lfsr_cnt_G3</td> 18426 <td align=left> 18427 LFSR timer start value for L0sL1 timers in gen3 speed. (10 ns) <br> 18428 Reset value is 0x17f1.</td></tr> 18429 </table><p> 18430 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18431 <hr> 18432 <b><a NAME="DSC_G_DSC_SM_CTL_21">DSC_G_DSC_SM_CTL_21 - DSC SM Ctl 21</a></b><br> 18433 Address Offset = 32'h0000_d266<br> 18434 Physical Address = 32'h0000_d266<br> 18435 Reset Value = 16'h1257<br> 18436 Access = RW (16-bit only)<br> 18437 <table border=1 align=center width=100% cellpadding=0> 18438 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18439 <tr bgcolor=WHITE> 18440 <td bgcolor=WHITE align=center valign=top>15</td> 18441 <td align=left valign=top>RW</td> 18442 <td align=left valign=top>hwtune_en_G1G2</td> 18443 <td align=left> 18444 Unfreeze trnsum, DFE and VGA in gen1/gen2 speed. <br> 18445 Reset value is 0x0.</td></tr> 18446 <tr bgcolor=WHITE> 18447 <td bgcolor=WHITE align=center valign=top>14</td> 18448 <td align=left valign=top>RW</td> 18449 <td align=left valign=top>ucuse_en_G1G2</td> 18450 <td align=left> 18451 Disable the gating of uc_active and uc_tune_en in gen1/gen2 speed. <br> 18452 Reset value is 0x0.</td></tr> 18453 <tr bgcolor=WHITE> 18454 <td bgcolor=WHITE align=center valign=top>13</td> 18455 <td align=left valign=top>RW</td> 18456 <td align=left valign=top>use_facq_done_G1G2</td> 18457 <td align=left> 18458 " Enable FACQ_DONE state in gen1/gen2 speed<br> 18459 Reset value is 0x0.</td></tr> 18460 <tr bgcolor=WHITE> 18461 <td bgcolor=WHITE align=center valign=top>12:00</td> 18462 <td align=left valign=top>RW</td> 18463 <td align=left valign=top>norm_lfsr_cnt_G1G2</td> 18464 <td align=left> 18465 LFSR timer start value for non-L0sL1 timers in gen1/gen2 speed. <br> 18466 Reset value is 0x1257.</td></tr> 18467 </table><p> 18468 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18469 <hr> 18470 <b><a NAME="DSC_G_DSC_SM_CTL_22">DSC_G_DSC_SM_CTL_22 - DSC SM Ctl 22</a></b><br> 18471 Address Offset = 32'h0000_d267<br> 18472 Physical Address = 32'h0000_d267<br> 18473 Reset Value = 16'h1c1e<br> 18474 Access = RW (16-bit only)<br> 18475 <table border=1 align=center width=100% cellpadding=0> 18476 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18477 <tr bgcolor=WHITE> 18478 <td bgcolor=WHITE align=center valign=top>15</td> 18479 <td align=left valign=top>RW</td> 18480 <td align=left valign=top>facq_en_disable_G3</td> 18481 <td align=left> 18482 Disable fast acquisition in gen3 speed. <br> 18483 Reset value is 0x0.</td></tr> 18484 <tr bgcolor=WHITE> 18485 <td bgcolor=WHITE align=center valign=top>14</td> 18486 <td align=left valign=top>RW</td> 18487 <td align=left valign=top>facq_en_disable_G2</td> 18488 <td align=left> 18489 Disable fast acquisition in gen3 speed. <br> 18490 Reset value is 0x0.</td></tr> 18491 <tr bgcolor=WHITE> 18492 <td bgcolor=WHITE align=center valign=top>13</td> 18493 <td align=left valign=top>RW</td> 18494 <td align=left valign=top>facq_en_disable_G1</td> 18495 <td align=left> 18496 Disable fast acquisition in gen3 speed. <br> 18497 Reset value is 0x0.</td></tr> 18498 <tr bgcolor=WHITE> 18499 <td bgcolor=WHITE align=center valign=top>12:00</td> 18500 <td align=left valign=top>RW</td> 18501 <td align=left valign=top>norm_lfsr_cnt_G3</td> 18502 <td align=left> 18503 LFSR timer start value for non-L0sL1 timers in gen3 speed. <br> 18504 Reset value is 0x1c1e.</td></tr> 18505 </table><p> 18506 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18507 <hr> 18508 <b><a NAME="DSC_G_DSC_SM_CTL_23">DSC_G_DSC_SM_CTL_23 - DSC SM Ctl 23</a></b><br> 18509 Address Offset = 32'h0000_d268<br> 18510 Physical Address = 32'h0000_d268<br> 18511 Reset Value = 16'h210c<br> 18512 Access = RW (16-bit only)<br> 18513 <table border=1 align=center width=100% cellpadding=0> 18514 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18515 <tr bgcolor=WHITE> 18516 <td bgcolor=WHITE align=center valign=top>15</td> 18517 <td align=left valign=top>RW</td> 18518 <td align=left valign=top>cdr_peak_polarity</td> 18519 <td align=left> 18520 inverts the peak information before the phase detector  <br> 18521 Reset value is 0x0.</td></tr> 18522 <tr bgcolor=WHITE> 18523 <td bgcolor=WHITE align=center valign=top>14:10</td> 18524 <td align=left valign=top>RW</td> 18525 <td align=left valign=top>L1_cdr_sttl_timeout_G3</td> 18526 <td align=left> 18527 Defines timeout value for the L0sL1_CDR_STTL state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18528 Reset value is 0x8.</td></tr> 18529 <tr bgcolor=WHITE> 18530 <td bgcolor=WHITE align=center valign=top>09:05</td> 18531 <td align=left valign=top>RW</td> 18532 <td align=left valign=top>L1_cdr_sttl_timeout_G2</td> 18533 <td align=left> 18534 Defines timeout value for the L0sL1_CDR_STTL state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18535 Reset value is 0x8.</td></tr> 18536 <tr bgcolor=WHITE> 18537 <td bgcolor=WHITE align=center valign=top>04:00</td> 18538 <td align=left valign=top>RW</td> 18539 <td align=left valign=top>L1_cdr_sttl_timeout_G1</td> 18540 <td align=left> 18541 Defines timeout value for the L0sL1_CDR_STTL state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18542 Reset value is 0xc.</td></tr> 18543 </table><p> 18544 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18545 <hr> 18546 <b><a NAME="DSC_G_DSC_SM_CTL_24">DSC_G_DSC_SM_CTL_24 - DSC SM Ctl 24</a></b><br> 18547 Address Offset = 32'h0000_d269<br> 18548 Physical Address = 32'h0000_d269<br> 18549 Reset Value = 16'h2000<br> 18550 Access = RW (16-bit only)<br> 18551 <table border=1 align=center width=100% cellpadding=0> 18552 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18553 <tr bgcolor=WHITE> 18554 <td bgcolor=WHITE align=center valign=top>15</td> 18555 <td align=left valign=top>RW</td> 18556 <td align=left valign=top>dfe_acc_reset</td> 18557 <td align=left> 18558 <br> 18559 Reset value is 0x0.</td></tr> 18560 <tr bgcolor=WHITE> 18561 <td bgcolor=WHITE align=center valign=top>14:10</td> 18562 <td align=left valign=top>RW</td> 18563 <td align=left valign=top>slicer_offset_timeout_G3</td> 18564 <td align=left> 18565 Defines timeout value for the SLICER_OFFSET state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18566 Reset value is 0x8.</td></tr> 18567 <tr bgcolor=WHITE> 18568 <td bgcolor=WHITE align=center valign=top>09:05</td> 18569 <td align=left valign=top>RW</td> 18570 <td align=left valign=top>slicer_offset_timeout_G2</td> 18571 <td align=left> 18572 Defines timeout value for the SLICER_OFFSET state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18573 Reset value is 0x0.</td></tr> 18574 <tr bgcolor=WHITE> 18575 <td bgcolor=WHITE align=center valign=top>04:00</td> 18576 <td align=left valign=top>RW</td> 18577 <td align=left valign=top>slicer_offset_timeout_G1</td> 18578 <td align=left> 18579 Defines timeout value for the SLICER_OFFSET state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18580 Reset value is 0x0.</td></tr> 18581 </table><p> 18582 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18583 <hr> 18584 <b><a NAME="DSC_G_DSC_SM_CTL_25">DSC_G_DSC_SM_CTL_25 - DSC SM Ctl 25</a></b><br> 18585 Address Offset = 32'h0000_d26a<br> 18586 Physical Address = 32'h0000_d26a<br> 18587 Reset Value = 16'h3180<br> 18588 Access = RW (16-bit only)<br> 18589 <table border=1 align=center width=100% cellpadding=0> 18590 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18591 <tr bgcolor=WHITE> 18592 <td bgcolor=WHITE align=center valign=top>15</td> 18593 <td align=left valign=top>RSVD</td> 18594 <td align=left valign=top>Reserved</td> 18595 <td align=left> 18596 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 18597 <tr bgcolor=WHITE> 18598 <td bgcolor=WHITE align=center valign=top>14:10</td> 18599 <td align=left valign=top>RW</td> 18600 <td align=left valign=top>dc_offset_timeout_G3</td> 18601 <td align=left> 18602 Defines timeout value for the DC_OFFSET state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18603 Reset value is 0xc.</td></tr> 18604 <tr bgcolor=WHITE> 18605 <td bgcolor=WHITE align=center valign=top>09:05</td> 18606 <td align=left valign=top>RW</td> 18607 <td align=left valign=top>dc_offset_timeout_G2</td> 18608 <td align=left> 18609 Defines timeout value for the DC_OFFSET state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18610 Reset value is 0xc.</td></tr> 18611 <tr bgcolor=WHITE> 18612 <td bgcolor=WHITE align=center valign=top>04:00</td> 18613 <td align=left valign=top>RW</td> 18614 <td align=left valign=top>dc_offset_timeout_G1</td> 18615 <td align=left> 18616 Defines timeout value for the DC_OFFSET state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 18617 Reset value is 0x0.</td></tr> 18618 </table><p> 18619 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18620 <hr> 18621 <b><a NAME="DSC_G_DSC_SM_CTL_26">DSC_G_DSC_SM_CTL_26 - DSC SM Ctl 26</a></b><br> 18622 Address Offset = 32'h0000_d26b<br> 18623 Physical Address = 32'h0000_d26b<br> 18624 Reset Value = 16'h8000<br> 18625 Access = RW (16-bit only)<br> 18626 <table border=1 align=center width=100% cellpadding=0> 18627 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18628 <tr bgcolor=WHITE> 18629 <td bgcolor=WHITE align=center valign=top>15</td> 18630 <td align=left valign=top>RW</td> 18631 <td align=left valign=top>adj_pi_en</td> 18632 <td align=left> 18633 <br> 18634 Reset value is 0x1.</td></tr> 18635 <tr bgcolor=WHITE> 18636 <td bgcolor=WHITE align=center valign=top>14</td> 18637 <td align=left valign=top>RW</td> 18638 <td align=left valign=top>step_dir</td> 18639 <td align=left> 18640 <br> 18641 Reset value is 0x0.</td></tr> 18642 <tr bgcolor=WHITE> 18643 <td bgcolor=WHITE align=center valign=top>13:07</td> 18644 <td align=left valign=top>RW</td> 18645 <td align=left valign=top>m1_minus_d_G2</td> 18646 <td align=left> 18647 sample clock phase offset for gen2 speed <br> 18648 Reset value is 0x0.</td></tr> 18649 <tr bgcolor=WHITE> 18650 <td bgcolor=WHITE align=center valign=top>06:00</td> 18651 <td align=left valign=top>RW</td> 18652 <td align=left valign=top>m1_minus_d_G1</td> 18653 <td align=left> 18654 sample clock phase offset for gen1 speed <br> 18655 Reset value is 0x0.</td></tr> 18656 </table><p> 18657 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18658 <hr> 18659 <b><a NAME="DSC_G_DSC_SM_CTL_27">DSC_G_DSC_SM_CTL_27 - DSC SM Ctl 27</a></b><br> 18660 Address Offset = 32'h0000_d26c<br> 18661 Physical Address = 32'h0000_d26c<br> 18662 Reset Value = 16'h0ea0<br> 18663 Access = RW (16-bit only)<br> 18664 <table border=1 align=center width=100% cellpadding=0> 18665 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18666 <tr bgcolor=WHITE> 18667 <td bgcolor=WHITE align=center valign=top>15:12</td> 18668 <td align=left valign=top>RSVD</td> 18669 <td align=left valign=top>Reserved</td> 18670 <td align=left> 18671 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 18672 <tr bgcolor=WHITE> 18673 <td bgcolor=WHITE align=center valign=top>11</td> 18674 <td align=left valign=top>RW</td> 18675 <td align=left valign=top>dc_offset_use_odd_G3</td> 18676 <td align=left> 18677 dc offset use odd data <br> 18678 Reset value is 0x1.</td></tr> 18679 <tr bgcolor=WHITE> 18680 <td bgcolor=WHITE align=center valign=top>10</td> 18681 <td align=left valign=top>RW</td> 18682 <td align=left valign=top>dc_offset_use_even_G3</td> 18683 <td align=left> 18684 dc offset use even data <br> 18685 Reset value is 0x1.</td></tr> 18686 <tr bgcolor=WHITE> 18687 <td bgcolor=WHITE align=center valign=top>09</td> 18688 <td align=left valign=top>RW</td> 18689 <td align=left valign=top>dc_offset_use_odd_G1G2</td> 18690 <td align=left> 18691 dc offset use odd data <br> 18692 Reset value is 0x1.</td></tr> 18693 <tr bgcolor=WHITE> 18694 <td bgcolor=WHITE align=center valign=top>08</td> 18695 <td align=left valign=top>RW</td> 18696 <td align=left valign=top>dc_offset_use_even_G1G2</td> 18697 <td align=left> 18698 dc offset use even data <br> 18699 Reset value is 0x0.</td></tr> 18700 <tr bgcolor=WHITE> 18701 <td bgcolor=WHITE align=center valign=top>07</td> 18702 <td align=left valign=top>RW</td> 18703 <td align=left valign=top>dsc_sm_manual_mode</td> 18704 <td align=left> 18705 Manually adjust PI when DSC_SM is in ADJ_PI state<br> 18706 Reset value is 0x1.</td></tr> 18707 <tr bgcolor=WHITE> 18708 <td bgcolor=WHITE align=center valign=top>06:00</td> 18709 <td align=left valign=top>RW</td> 18710 <td align=left valign=top>m1_minus_d_G3</td> 18711 <td align=left> 18712 sample clock phase offset for gen3 speed <br> 18713 Reset value is 0x20.</td></tr> 18714 </table><p> 18715 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18716 <hr> 18717 <b><a NAME="DSC_G_DSC_SM_CTL_28">DSC_G_DSC_SM_CTL_28 - DSC SM Ctl 28</a></b><br> 18718 Address Offset = 32'h0000_d26d<br> 18719 Physical Address = 32'h0000_d26d<br> 18720 Reset Value = 16'h0bd8<br> 18721 Access = RW (16-bit only)<br> 18722 <table border=1 align=center width=100% cellpadding=0> 18723 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18724 <tr bgcolor=WHITE> 18725 <td bgcolor=WHITE align=center valign=top>15</td> 18726 <td align=left valign=top>RW</td> 18727 <td align=left valign=top>dsc_sm_tmux_sel</td> 18728 <td align=left> 18729 Select DSC_SM signals to the test bus<br> 18730 Reset value is 0x0.</td></tr> 18731 <tr bgcolor=WHITE> 18732 <td bgcolor=WHITE align=center valign=top>14</td> 18733 <td align=left valign=top>RW</td> 18734 <td align=left valign=top>cdr_zero_from_m1_slicer_g2</td> 18735 <td align=left> 18736 Take zero crossing from data slicer (odd) in Gen2 mode <br> 18737 Reset value is 0x0.</td></tr> 18738 <tr bgcolor=WHITE> 18739 <td bgcolor=WHITE align=center valign=top>13</td> 18740 <td align=left valign=top>RW</td> 18741 <td align=left valign=top>cdr_zero_from_m1_slicer_g1</td> 18742 <td align=left> 18743 Take zero crossing from data slicer (odd) in Gen1 mode <br> 18744 Reset value is 0x0.</td></tr> 18745 <tr bgcolor=WHITE> 18746 <td bgcolor=WHITE align=center valign=top>12:00</td> 18747 <td align=left valign=top>RW</td> 18748 <td align=left valign=top>L0sL1_lfsr_cnt_G1</td> 18749 <td align=left> 18750 LFSR timer start value for L0sL1 timers in gen1 speed. (20ns) <br> 18751 Reset value is 0xbd8.</td></tr> 18752 </table><p> 18753 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18754 <hr> 18755 <b><a NAME="DSC_G_DSC_SM_CTL_29">DSC_G_DSC_SM_CTL_29 - DSC SM Ctl 29</a></b><br> 18756 Address Offset = 32'h0000_d26e<br> 18757 Physical Address = 32'h0000_d26e<br> 18758 Reset Value = 16'h0040<br> 18759 Access = RW (16-bit only)<br> 18760 <table border=1 align=center width=100% cellpadding=0> 18761 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18762 <tr bgcolor=WHITE> 18763 <td bgcolor=WHITE align=center valign=top>15</td> 18764 <td align=left valign=top>RW</td> 18765 <td align=left valign=top>sigdet_frc_init</td> 18766 <td align=left> 18767 Force DSC_SM state to INIT state when no sigdet <br> 18768 Reset value is 0x0.</td></tr> 18769 <tr bgcolor=WHITE> 18770 <td bgcolor=WHITE align=center valign=top>14</td> 18771 <td align=left valign=top>RW</td> 18772 <td align=left valign=top>disable_L0s_exit</td> 18773 <td align=left> 18774 Disable DSC_SM L0s exit <br> 18775 Reset value is 0x0.</td></tr> 18776 <tr bgcolor=WHITE> 18777 <td bgcolor=WHITE align=center valign=top>13</td> 18778 <td align=left valign=top>RW</td> 18779 <td align=left valign=top>disable_L1_exit</td> 18780 <td align=left> 18781 Disable DSC_SM L1 exit <br> 18782 Reset value is 0x0.</td></tr> 18783 <tr bgcolor=WHITE> 18784 <td bgcolor=WHITE align=center valign=top>12</td> 18785 <td align=left valign=top>RW</td> 18786 <td align=left valign=top>dsc_slicer_offset_done_frc</td> 18787 <td align=left> 18788 force dsc_slicer_offset_done value <br> 18789 Reset value is 0x0.</td></tr> 18790 <tr bgcolor=WHITE> 18791 <td bgcolor=WHITE align=center valign=top>11</td> 18792 <td align=left valign=top>RW</td> 18793 <td align=left valign=top>dsc_slicer_offset_done_frc_val</td> 18794 <td align=left> 18795 force dsc_slicer_offset_done value <br> 18796 Reset value is 0x0.</td></tr> 18797 <tr bgcolor=WHITE> 18798 <td bgcolor=WHITE align=center valign=top>10</td> 18799 <td align=left valign=top>RW</td> 18800 <td align=left valign=top>dsc_slicer_offset_cnt_frc</td> 18801 <td align=left> 18802 force dsc_slicer_offset_cnt <br> 18803 Reset value is 0x0.</td></tr> 18804 <tr bgcolor=WHITE> 18805 <td bgcolor=WHITE align=center valign=top>09:07</td> 18806 <td align=left valign=top>RW</td> 18807 <td align=left valign=top>dsc_slicer_offset_cnt_frc_val</td> 18808 <td align=left> 18809 force dsc_slicer_offset_cnt value<br> 18810 Reset value is 0x0.</td></tr> 18811 <tr bgcolor=WHITE> 18812 <td bgcolor=WHITE align=center valign=top>06</td> 18813 <td align=left valign=top>RW</td> 18814 <td align=left valign=top>redo_slicer_calibration</td> 18815 <td align=left> 18816 When DSC_SM restarts, redo slicer calibration<br> 18817 Reset value is 0x1.</td></tr> 18818 <tr bgcolor=WHITE> 18819 <td bgcolor=WHITE align=center valign=top>05:00</td> 18820 <td align=left valign=top>RW</td> 18821 <td align=left valign=top>slicer_calibration_mask</td> 18822 <td align=left> 18823 Slicer Calibration Mask.  <br> 18824 1 means skip slicer offset calibration.<br> 18825 Reset value is 0x0.</td></tr> 18826 </table><p> 18827 <A HREF="#DSC_G Registers">Return to DSC_G: per lane register block [One Copy Per Lane] Table</A><p> 18828 <hr> 18829 <H1><a NAME="DSC_H Registers">DSC_H: per lane register block [One Copy Per Lane] Registers</a></H1> 18830 <table border=1 align=center width=100% cellpadding=0> 18831 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 18832 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 18833 <tr> 18834 <td align=center>0xD270</td><td><A HREF="#DSC_H_DSC_SM_CTL_30">DSC_H_DSC_SM_CTL_30</A><br>DSC SM Ctl 30</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_pattern_sel_lock_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_pattern_sel_steady_state_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_pattern_sel_steady_state_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_pattern_sel_steady_state_G1</div> </td> <td align=center>16'hffff</td></tr> 18835 <tr> 18836 <td align=center>0xD271</td><td><A HREF="#DSC_H_DSC_SM_CTL_31">DSC_H_DSC_SM_CTL_31</A><br>DSC SM Ctl 31</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_sm_pause_entry</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dsc_sm_pause_exit</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dsc_lock_in_uc_tune</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">dsc_lock_in_hw_tune</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_pattern_sel_lock_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_pattern_sel_lock_G1</div> </td> <td align=center>16'h00ff</td></tr> 18837 <tr> 18838 <td align=center>0xD272</td><td><A HREF="#DSC_H_DSC_SM_CTL_32">DSC_H_DSC_SM_CTL_32</A><br>DSC SM Ctl 32</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_clken_frc</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">dfe_clken_frc_val</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_pi_step_size_norm_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_pi_step_size_norm_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_pi_step_size_norm_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_pi_step_size_facq_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_pi_step_size_facq_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rx_pi_step_size_facq_G1</div> </td> <td bgcolor=#CCCCCC align=center colspan="2"><div class="HT">reserved</div> </td> <td align=center>16'h0514</td></tr> 18839 <tr> 18840 <td align=center>0xD273</td><td><A HREF="#DSC_H_DSC_SM_CTL_33">DSC_H_DSC_SM_CTL_33</A><br>DSC SM Ctl 33</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">pcie_g1_condition_mask_e</div> </td> <td align=center>16'h0155</td></tr> 18841 <tr> 18842 <td align=center>0xD274</td><td><A HREF="#DSC_H_DSC_SM_CTL_34">DSC_H_DSC_SM_CTL_34</A><br>DSC SM Ctl 34</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="10"><div class="HT">pcie_g1_condition_mask_o</div> </td> <td align=center>16'h0155</td></tr> 18843 <tr> 18844 <td align=center>0xD275</td><td><A HREF="#DSC_H_DSC_SM_STATUS_0">DSC_H_DSC_SM_STATUS_0</A><br>DSC SM Status 0</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">vga_op_short</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxFastAcqEnable_mux</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxFastAcqEnable_G1G2</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">RxFastAcqEnable_G3</div> </td> <td align=center>16'h0000</td></tr> 18845 </table><p> 18846 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 18847 <hr> 18848 <b><a NAME="DSC_H_DSC_SM_CTL_30">DSC_H_DSC_SM_CTL_30 - DSC SM Ctl 30</a></b><br> 18849 Address Offset = 32'h0000_d270<br> 18850 Physical Address = 32'h0000_d270<br> 18851 Reset Value = 16'hffff<br> 18852 Access = RW (16-bit only)<br> 18853 <table border=1 align=center width=100% cellpadding=0> 18854 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18855 <tr bgcolor=WHITE> 18856 <td bgcolor=WHITE align=center valign=top>15:12</td> 18857 <td align=left valign=top>RW</td> 18858 <td align=left valign=top>cdr_pattern_sel_lock_G3</td> 18859 <td align=left> 18860 Select which CDR edge to use for locking in Gen3<br> 18861 Reset value is 0xf.</td></tr> 18862 <tr bgcolor=WHITE> 18863 <td bgcolor=WHITE align=center valign=top>11:08</td> 18864 <td align=left valign=top>RW</td> 18865 <td align=left valign=top>cdr_pattern_sel_steady_state_G3</td> 18866 <td align=left> 18867 Select which CDR edge to use for steady state in Gen3<br> 18868 Reset value is 0xf.</td></tr> 18869 <tr bgcolor=WHITE> 18870 <td bgcolor=WHITE align=center valign=top>07:04</td> 18871 <td align=left valign=top>RW</td> 18872 <td align=left valign=top>cdr_pattern_sel_steady_state_G2</td> 18873 <td align=left> 18874 Select which CDR edge to use for steady state in Gen2<br> 18875 Reset value is 0xf.</td></tr> 18876 <tr bgcolor=WHITE> 18877 <td bgcolor=WHITE align=center valign=top>03:00</td> 18878 <td align=left valign=top>RW</td> 18879 <td align=left valign=top>cdr_pattern_sel_steady_state_G1</td> 18880 <td align=left> 18881 Select which CDR edge to use for steady state in Gen1<br> 18882 Reset value is 0xf.</td></tr> 18883 </table><p> 18884 <A HREF="#DSC_H Registers">Return to DSC_H: per lane register block [One Copy Per Lane] Table</A><p> 18885 <hr> 18886 <b><a NAME="DSC_H_DSC_SM_CTL_31">DSC_H_DSC_SM_CTL_31 - DSC SM Ctl 31</a></b><br> 18887 Address Offset = 32'h0000_d271<br> 18888 Physical Address = 32'h0000_d271<br> 18889 Reset Value = 16'h00ff<br> 18890 Access = RW (16-bit only)<br> 18891 <table border=1 align=center width=100% cellpadding=0> 18892 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18893 <tr bgcolor=WHITE> 18894 <td bgcolor=WHITE align=center valign=top>15</td> 18895 <td align=left valign=top>RW</td> 18896 <td align=left valign=top>dsc_sm_pause_entry</td> 18897 <td align=left> 18898 DSC enter PAUSE state from INIT state<br> 18899 Reset value is 0x0.</td></tr> 18900 <tr bgcolor=WHITE> 18901 <td bgcolor=WHITE align=center valign=top>14</td> 18902 <td align=left valign=top>RW</td> 18903 <td align=left valign=top>dsc_sm_pause_exit</td> 18904 <td align=left> 18905 DSC exit PAUSE state<br> 18906 Reset value is 0x0.</td></tr> 18907 <tr bgcolor=WHITE> 18908 <td bgcolor=WHITE align=center valign=top>13:11</td> 18909 <td align=left valign=top>RW</td> 18910 <td align=left valign=top>dsc_lock_in_uc_tune</td> 18911 <td align=left> 18912 dsc lock asserts in UC_TUNE state (bit2:gen2 bit1:gen1 bit0:gen0)<br> 18913 Reset value is 0x0.</td></tr> 18914 <tr bgcolor=WHITE> 18915 <td bgcolor=WHITE align=center valign=top>10:08</td> 18916 <td align=left valign=top>RW</td> 18917 <td align=left valign=top>dsc_lock_in_hw_tune</td> 18918 <td align=left> 18919 dsc lock asserts in HW_TUNE state (bit2:gen2 bit1:gen1 bit0:gen0)<br> 18920 Reset value is 0x0.</td></tr> 18921 <tr bgcolor=WHITE> 18922 <td bgcolor=WHITE align=center valign=top>07:04</td> 18923 <td align=left valign=top>RW</td> 18924 <td align=left valign=top>cdr_pattern_sel_lock_G2</td> 18925 <td align=left> 18926 Select which CDR edge to use for locking in Gen2<br> 18927 Reset value is 0xf.</td></tr> 18928 <tr bgcolor=WHITE> 18929 <td bgcolor=WHITE align=center valign=top>03:00</td> 18930 <td align=left valign=top>RW</td> 18931 <td align=left valign=top>cdr_pattern_sel_lock_G1</td> 18932 <td align=left> 18933 Select which CDR edge to use for locking in Gen1<br> 18934 Reset value is 0xf.</td></tr> 18935 </table><p> 18936 <A HREF="#DSC_H Registers">Return to DSC_H: per lane register block [One Copy Per Lane] Table</A><p> 18937 <hr> 18938 <b><a NAME="DSC_H_DSC_SM_CTL_32">DSC_H_DSC_SM_CTL_32 - DSC SM Ctl 32</a></b><br> 18939 Address Offset = 32'h0000_d272<br> 18940 Physical Address = 32'h0000_d272<br> 18941 Reset Value = 16'h0514<br> 18942 Access = RW (16-bit only)<br> 18943 <table border=1 align=center width=100% cellpadding=0> 18944 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 18945 <tr bgcolor=WHITE> 18946 <td bgcolor=WHITE align=center valign=top>15</td> 18947 <td align=left valign=top>RW</td> 18948 <td align=left valign=top>dfe_clken_frc</td> 18949 <td align=left> 18950 Force dfe_clken<br> 18951 Reset value is 0x0.</td></tr> 18952 <tr bgcolor=WHITE> 18953 <td bgcolor=WHITE align=center valign=top>14</td> 18954 <td align=left valign=top>RW</td> 18955 <td align=left valign=top>dfe_clken_frc_val</td> 18956 <td align=left> 18957 Force value of dfe_clken <br> 18958 Reset value is 0x0.</td></tr> 18959 <tr bgcolor=WHITE> 18960 <td bgcolor=WHITE align=center valign=top>13:12</td> 18961 <td align=left valign=top>RW</td> 18962 <td align=left valign=top>rx_pi_step_size_norm_G3</td> 18963 <td align=left> 18964 RX Phase interperator phase step size for non fast acquisition states in gen3 speed. 2:step size=4 1:step size=2 0:step_size=1<br> 18965 Reset value is 0x0.</td></tr> 18966 <tr bgcolor=WHITE> 18967 <td bgcolor=WHITE align=center valign=top>11:10</td> 18968 <td align=left valign=top>RW</td> 18969 <td align=left valign=top>rx_pi_step_size_norm_G2</td> 18970 <td align=left> 18971 RX Phase interperator phase step size for non fast acquisition states in gen2 speed. 2:step size=4 1:step size=2 0:step_size=1<br> 18972 Reset value is 0x1.</td></tr> 18973 <tr bgcolor=WHITE> 18974 <td bgcolor=WHITE align=center valign=top>09:08</td> 18975 <td align=left valign=top>RW</td> 18976 <td align=left valign=top>rx_pi_step_size_norm_G1</td> 18977 <td align=left> 18978 RX Phase interperator phase step size for non fast acquisition states in gen1 speed. 2:step size=4 1:step size=2 0:step_size=1<br> 18979 Reset value is 0x1.</td></tr> 18980 <tr bgcolor=WHITE> 18981 <td bgcolor=WHITE align=center valign=top>07:06</td> 18982 <td align=left valign=top>RW</td> 18983 <td align=left valign=top>rx_pi_step_size_facq_G3</td> 18984 <td align=left> 18985 RX Phase interperator phase step size for fast acquisition states in gen3 speed. 2:step size=4 1:step size=2 0:step_size=1<br> 18986 Reset value is 0x0.</td></tr> 18987 <tr bgcolor=WHITE> 18988 <td bgcolor=WHITE align=center valign=top>05:04</td> 18989 <td align=left valign=top>RW</td> 18990 <td align=left valign=top>rx_pi_step_size_facq_G2</td> 18991 <td align=left> 18992 RX Phase interperator phase step size for fast acquisition statesin gen2 speed. 2:step size=4 1:step size=2 0:step_size=1<br> 18993 Reset value is 0x1.</td></tr> 18994 <tr bgcolor=WHITE> 18995 <td bgcolor=WHITE align=center valign=top>03:02</td> 18996 <td align=left valign=top>RW</td> 18997 <td align=left valign=top>rx_pi_step_size_facq_G1</td> 18998 <td align=left> 18999 RX Phase interperator phase step size for fast acquisition states in gen1 speed. 2:step size=4 1:step size=2 0:step_size=1<br> 19000 Reset value is 0x1.</td></tr> 19001 <tr bgcolor=WHITE> 19002 <td bgcolor=WHITE align=center valign=top>01:00</td> 19003 <td align=left valign=top>RSVD</td> 19004 <td align=left valign=top>Reserved</td> 19005 <td align=left> 19006 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 19007 </table><p> 19008 <A HREF="#DSC_H Registers">Return to DSC_H: per lane register block [One Copy Per Lane] Table</A><p> 19009 <hr> 19010 <b><a NAME="DSC_H_DSC_SM_CTL_33">DSC_H_DSC_SM_CTL_33 - DSC SM Ctl 33</a></b><br> 19011 Address Offset = 32'h0000_d273<br> 19012 Physical Address = 32'h0000_d273<br> 19013 Reset Value = 16'h0155<br> 19014 Access = RW (16-bit only)<br> 19015 <table border=1 align=center width=100% cellpadding=0> 19016 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19017 <tr bgcolor=WHITE> 19018 <td bgcolor=WHITE align=center valign=top>15:10</td> 19019 <td align=left valign=top>RSVD</td> 19020 <td align=left valign=top>Reserved</td> 19021 <td align=left> 19022 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 19023 <tr bgcolor=WHITE> 19024 <td bgcolor=WHITE align=center valign=top>09:00</td> 19025 <td align=left valign=top>RW</td> 19026 <td align=left valign=top>pcie_g1_condition_mask_e</td> 19027 <td align=left> 19028 Mask out the individual bit metrics in trnsum_cmn_block_e during gen1 eye monitor<br> 19029 Reset value is 0x155.</td></tr> 19030 </table><p> 19031 <A HREF="#DSC_H Registers">Return to DSC_H: per lane register block [One Copy Per Lane] Table</A><p> 19032 <hr> 19033 <b><a NAME="DSC_H_DSC_SM_CTL_34">DSC_H_DSC_SM_CTL_34 - DSC SM Ctl 34</a></b><br> 19034 Address Offset = 32'h0000_d274<br> 19035 Physical Address = 32'h0000_d274<br> 19036 Reset Value = 16'h0155<br> 19037 Access = RW (16-bit only)<br> 19038 <table border=1 align=center width=100% cellpadding=0> 19039 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19040 <tr bgcolor=WHITE> 19041 <td bgcolor=WHITE align=center valign=top>15:10</td> 19042 <td align=left valign=top>RSVD</td> 19043 <td align=left valign=top>Reserved</td> 19044 <td align=left> 19045 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 19046 <tr bgcolor=WHITE> 19047 <td bgcolor=WHITE align=center valign=top>09:00</td> 19048 <td align=left valign=top>RW</td> 19049 <td align=left valign=top>pcie_g1_condition_mask_o</td> 19050 <td align=left> 19051 Mask out the individual bit metrics in trnsum_cmn_block_o during gen1 eye monitor<br> 19052 Reset value is 0x155.</td></tr> 19053 </table><p> 19054 <A HREF="#DSC_H Registers">Return to DSC_H: per lane register block [One Copy Per Lane] Table</A><p> 19055 <hr> 19056 <b><a NAME="DSC_H_DSC_SM_STATUS_0">DSC_H_DSC_SM_STATUS_0 - DSC SM Status 0</a></b><br> 19057 Address Offset = 32'h0000_d275<br> 19058 Physical Address = 32'h0000_d275<br> 19059 Reset Value = 16'h0000<br> 19060 Access = RO (16-bit only)<br> 19061 <table border=1 align=center width=100% cellpadding=0> 19062 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19063 <tr bgcolor=WHITE> 19064 <td bgcolor=WHITE align=center valign=top>15:04</td> 19065 <td align=left valign=top>RSVD</td> 19066 <td align=left valign=top>Reserved</td> 19067 <td align=left> 19068 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 19069 <tr bgcolor=WHITE> 19070 <td bgcolor=WHITE align=center valign=top>03</td> 19071 <td align=left valign=top>RO</td> 19072 <td align=left valign=top>vga_op_short</td> 19073 <td align=left> 19074 <br> 19075 Reset value is 0x0.</td></tr> 19076 <tr bgcolor=WHITE> 19077 <td bgcolor=WHITE align=center valign=top>02</td> 19078 <td align=left valign=top>RO</td> 19079 <td align=left valign=top>RxFastAcqEnable_mux</td> 19080 <td align=left> 19081 <br> 19082 Reset value is 0x0.</td></tr> 19083 <tr bgcolor=WHITE> 19084 <td bgcolor=WHITE align=center valign=top>01</td> 19085 <td align=left valign=top>RO</td> 19086 <td align=left valign=top>RxFastAcqEnable_G1G2</td> 19087 <td align=left> 19088 <br> 19089 Reset value is 0x0.</td></tr> 19090 <tr bgcolor=WHITE> 19091 <td bgcolor=WHITE align=center valign=top>00</td> 19092 <td align=left valign=top>RO</td> 19093 <td align=left valign=top>RxFastAcqEnable_G3</td> 19094 <td align=left> 19095 <br> 19096 Reset value is 0x0.</td></tr> 19097 </table><p> 19098 <A HREF="#DSC_H Registers">Return to DSC_H: per lane register block [One Copy Per Lane] Table</A><p> 19099 <hr> 19100 <H1><a NAME="DSC_I Registers">DSC_I: per lane register block [One Copy Per Lane] Registers</a></H1> 19101 <table border=1 align=center width=100% cellpadding=0> 19102 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 19103 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 19104 <tr> 19105 <td align=center>0xD280</td><td><A HREF="#DSC_I_RX_HIST_STAT_0">DSC_I_RX_HIST_STAT_0</A><br>RX Histogram Status 0</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_00</div> </td> <td align=center>16'h0000</td></tr> 19106 <tr> 19107 <td align=center>0xD281</td><td><A HREF="#DSC_I_RX_HIST_STAT_1">DSC_I_RX_HIST_STAT_1</A><br>RX Histogram Status 1</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_01</div> </td> <td align=center>16'h0000</td></tr> 19108 <tr> 19109 <td align=center>0xD282</td><td><A HREF="#DSC_I_RX_HIST_STAT_2">DSC_I_RX_HIST_STAT_2</A><br>RX Histogram Status 2</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_02</div> </td> <td align=center>16'h0000</td></tr> 19110 <tr> 19111 <td align=center>0xD283</td><td><A HREF="#DSC_I_RX_HIST_STAT_3">DSC_I_RX_HIST_STAT_3</A><br>RX Histogram Status 3</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_03</div> </td> <td align=center>16'h0000</td></tr> 19112 <tr> 19113 <td align=center>0xD284</td><td><A HREF="#DSC_I_RX_HIST_STAT_4">DSC_I_RX_HIST_STAT_4</A><br>RX Histogram Status 4</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_04</div> </td> <td align=center>16'h0000</td></tr> 19114 <tr> 19115 <td align=center>0xD285</td><td><A HREF="#DSC_I_RX_HIST_STAT_5">DSC_I_RX_HIST_STAT_5</A><br>RX Histogram Status 5</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_05</div> </td> <td align=center>16'h0000</td></tr> 19116 <tr> 19117 <td align=center>0xD286</td><td><A HREF="#DSC_I_RX_HIST_STAT_6">DSC_I_RX_HIST_STAT_6</A><br>RX Histogram Status 6</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_06</div> </td> <td align=center>16'h0000</td></tr> 19118 <tr> 19119 <td align=center>0xD287</td><td><A HREF="#DSC_I_RX_HIST_STAT_7">DSC_I_RX_HIST_STAT_7</A><br>RX Histogram Status 7</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_07</div> </td> <td align=center>16'h0000</td></tr> 19120 <tr> 19121 <td align=center>0xD288</td><td><A HREF="#DSC_I_RX_HIST_STAT_8">DSC_I_RX_HIST_STAT_8</A><br>RX Histogram Status 8</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_08</div> </td> <td align=center>16'h0000</td></tr> 19122 <tr> 19123 <td align=center>0xD289</td><td><A HREF="#DSC_I_RX_HIST_STAT_9">DSC_I_RX_HIST_STAT_9</A><br>RX Histogram Status 9</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_09</div> </td> <td align=center>16'h0000</td></tr> 19124 <tr> 19125 <td align=center>0xD28A</td><td><A HREF="#DSC_I_RX_HIST_STAT_10">DSC_I_RX_HIST_STAT_10</A><br>RX Histogram Status 10</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_10</div> </td> <td align=center>16'h0000</td></tr> 19126 <tr> 19127 <td align=center>0xD28B</td><td><A HREF="#DSC_I_RX_HIST_STAT_11">DSC_I_RX_HIST_STAT_11</A><br>RX Histogram Status 11</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_11</div> </td> <td align=center>16'h0000</td></tr> 19128 <tr> 19129 <td align=center>0xD28C</td><td><A HREF="#DSC_I_RX_HIST_STAT_12">DSC_I_RX_HIST_STAT_12</A><br>RX Histogram Status 12</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_12</div> </td> <td align=center>16'h0000</td></tr> 19130 <tr> 19131 <td align=center>0xD28D</td><td><A HREF="#DSC_I_RX_HIST_STAT_13">DSC_I_RX_HIST_STAT_13</A><br>RX Histogram Status 13</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">rx_hist_13</div> </td> <td align=center>16'h0000</td></tr> 19132 <tr> 19133 <td align=center>0xD28E</td><td><A HREF="#DSC_I_RX_HIST_CTRL">DSC_I_RX_HIST_CTRL</A><br>RX Histogram Controls</td><td bgcolor=#CCCCCC align=center colspan="12"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_hist_clr</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">rg_hist_stop</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">rg_hist_rd_mux_sel</div> </td> <td align=center>16'h0000</td></tr> 19134 </table><p> 19135 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 19136 <hr> 19137 <b><a NAME="DSC_I_RX_HIST_STAT_0">DSC_I_RX_HIST_STAT_0 - RX Histogram Status 0</a></b><br> 19138 Address Offset = 32'h0000_d280<br> 19139 Physical Address = 32'h0000_d280<br> 19140 Reset Value = 16'h0000<br> 19141 Access = RO (16-bit only)<br> 19142 <table border=1 align=center width=100% cellpadding=0> 19143 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19144 <tr bgcolor=WHITE> 19145 <td bgcolor=WHITE align=center valign=top>15:00</td> 19146 <td align=left valign=top>RO</td> 19147 <td align=left valign=top>rx_hist_00</td> 19148 <td align=left> 19149 {pll_lock,rate_select,fast_acq_gen3,fast_acq_gen12 <br> 19150 eieos_detect,eios_detect,dsc_lock,dsc_state[4:0] <br> 19151 sigdet_mac,sigdet_dsc,afe_sigdet_filt<br> 19152 Reset value is 0x0.</td></tr> 19153 </table><p> 19154 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19155 <hr> 19156 <b><a NAME="DSC_I_RX_HIST_STAT_1">DSC_I_RX_HIST_STAT_1 - RX Histogram Status 1</a></b><br> 19157 Address Offset = 32'h0000_d281<br> 19158 Physical Address = 32'h0000_d281<br> 19159 Reset Value = 16'h0000<br> 19160 Access = RO (16-bit only)<br> 19161 <table border=1 align=center width=100% cellpadding=0> 19162 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19163 <tr bgcolor=WHITE> 19164 <td bgcolor=WHITE align=center valign=top>15:00</td> 19165 <td align=left valign=top>RO</td> 19166 <td align=left valign=top>rx_hist_01</td> 19167 <td align=left> 19168 refer to rx_hist_stat_0 defn <br> 19169 Reset value is 0x0.</td></tr> 19170 </table><p> 19171 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19172 <hr> 19173 <b><a NAME="DSC_I_RX_HIST_STAT_2">DSC_I_RX_HIST_STAT_2 - RX Histogram Status 2</a></b><br> 19174 Address Offset = 32'h0000_d282<br> 19175 Physical Address = 32'h0000_d282<br> 19176 Reset Value = 16'h0000<br> 19177 Access = RO (16-bit only)<br> 19178 <table border=1 align=center width=100% cellpadding=0> 19179 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19180 <tr bgcolor=WHITE> 19181 <td bgcolor=WHITE align=center valign=top>15:00</td> 19182 <td align=left valign=top>RO</td> 19183 <td align=left valign=top>rx_hist_02</td> 19184 <td align=left> 19185 refer to rx_hist_stat_0 defn <br> 19186 Reset value is 0x0.</td></tr> 19187 </table><p> 19188 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19189 <hr> 19190 <b><a NAME="DSC_I_RX_HIST_STAT_3">DSC_I_RX_HIST_STAT_3 - RX Histogram Status 3</a></b><br> 19191 Address Offset = 32'h0000_d283<br> 19192 Physical Address = 32'h0000_d283<br> 19193 Reset Value = 16'h0000<br> 19194 Access = RO (16-bit only)<br> 19195 <table border=1 align=center width=100% cellpadding=0> 19196 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19197 <tr bgcolor=WHITE> 19198 <td bgcolor=WHITE align=center valign=top>15:00</td> 19199 <td align=left valign=top>RO</td> 19200 <td align=left valign=top>rx_hist_03</td> 19201 <td align=left> 19202 refer to rx_hist_stat_0 defn <br> 19203 Reset value is 0x0.</td></tr> 19204 </table><p> 19205 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19206 <hr> 19207 <b><a NAME="DSC_I_RX_HIST_STAT_4">DSC_I_RX_HIST_STAT_4 - RX Histogram Status 4</a></b><br> 19208 Address Offset = 32'h0000_d284<br> 19209 Physical Address = 32'h0000_d284<br> 19210 Reset Value = 16'h0000<br> 19211 Access = RO (16-bit only)<br> 19212 <table border=1 align=center width=100% cellpadding=0> 19213 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19214 <tr bgcolor=WHITE> 19215 <td bgcolor=WHITE align=center valign=top>15:00</td> 19216 <td align=left valign=top>RO</td> 19217 <td align=left valign=top>rx_hist_04</td> 19218 <td align=left> 19219 refer to rx_hist_stat_0 defn <br> 19220 Reset value is 0x0.</td></tr> 19221 </table><p> 19222 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19223 <hr> 19224 <b><a NAME="DSC_I_RX_HIST_STAT_5">DSC_I_RX_HIST_STAT_5 - RX Histogram Status 5</a></b><br> 19225 Address Offset = 32'h0000_d285<br> 19226 Physical Address = 32'h0000_d285<br> 19227 Reset Value = 16'h0000<br> 19228 Access = RO (16-bit only)<br> 19229 <table border=1 align=center width=100% cellpadding=0> 19230 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19231 <tr bgcolor=WHITE> 19232 <td bgcolor=WHITE align=center valign=top>15:00</td> 19233 <td align=left valign=top>RO</td> 19234 <td align=left valign=top>rx_hist_05</td> 19235 <td align=left> 19236 refer to rx_hist_stat_0 defn <br> 19237 Reset value is 0x0.</td></tr> 19238 </table><p> 19239 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19240 <hr> 19241 <b><a NAME="DSC_I_RX_HIST_STAT_6">DSC_I_RX_HIST_STAT_6 - RX Histogram Status 6</a></b><br> 19242 Address Offset = 32'h0000_d286<br> 19243 Physical Address = 32'h0000_d286<br> 19244 Reset Value = 16'h0000<br> 19245 Access = RO (16-bit only)<br> 19246 <table border=1 align=center width=100% cellpadding=0> 19247 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19248 <tr bgcolor=WHITE> 19249 <td bgcolor=WHITE align=center valign=top>15:00</td> 19250 <td align=left valign=top>RO</td> 19251 <td align=left valign=top>rx_hist_06</td> 19252 <td align=left> 19253 refer to rx_hist_stat_0 defn <br> 19254 Reset value is 0x0.</td></tr> 19255 </table><p> 19256 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19257 <hr> 19258 <b><a NAME="DSC_I_RX_HIST_STAT_7">DSC_I_RX_HIST_STAT_7 - RX Histogram Status 7</a></b><br> 19259 Address Offset = 32'h0000_d287<br> 19260 Physical Address = 32'h0000_d287<br> 19261 Reset Value = 16'h0000<br> 19262 Access = RO (16-bit only)<br> 19263 <table border=1 align=center width=100% cellpadding=0> 19264 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19265 <tr bgcolor=WHITE> 19266 <td bgcolor=WHITE align=center valign=top>15:00</td> 19267 <td align=left valign=top>RO</td> 19268 <td align=left valign=top>rx_hist_07</td> 19269 <td align=left> 19270 refer to rx_hist_stat_0 defn <br> 19271 Reset value is 0x0.</td></tr> 19272 </table><p> 19273 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19274 <hr> 19275 <b><a NAME="DSC_I_RX_HIST_STAT_8">DSC_I_RX_HIST_STAT_8 - RX Histogram Status 8</a></b><br> 19276 Address Offset = 32'h0000_d288<br> 19277 Physical Address = 32'h0000_d288<br> 19278 Reset Value = 16'h0000<br> 19279 Access = RO (16-bit only)<br> 19280 <table border=1 align=center width=100% cellpadding=0> 19281 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19282 <tr bgcolor=WHITE> 19283 <td bgcolor=WHITE align=center valign=top>15:00</td> 19284 <td align=left valign=top>RO</td> 19285 <td align=left valign=top>rx_hist_08</td> 19286 <td align=left> 19287 refer to rx_hist_stat_0 defn <br> 19288 Reset value is 0x0.</td></tr> 19289 </table><p> 19290 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19291 <hr> 19292 <b><a NAME="DSC_I_RX_HIST_STAT_9">DSC_I_RX_HIST_STAT_9 - RX Histogram Status 9</a></b><br> 19293 Address Offset = 32'h0000_d289<br> 19294 Physical Address = 32'h0000_d289<br> 19295 Reset Value = 16'h0000<br> 19296 Access = RO (16-bit only)<br> 19297 <table border=1 align=center width=100% cellpadding=0> 19298 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19299 <tr bgcolor=WHITE> 19300 <td bgcolor=WHITE align=center valign=top>15:00</td> 19301 <td align=left valign=top>RO</td> 19302 <td align=left valign=top>rx_hist_09</td> 19303 <td align=left> 19304 refer to rx_hist_stat_0 defn <br> 19305 Reset value is 0x0.</td></tr> 19306 </table><p> 19307 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19308 <hr> 19309 <b><a NAME="DSC_I_RX_HIST_STAT_10">DSC_I_RX_HIST_STAT_10 - RX Histogram Status 10</a></b><br> 19310 Address Offset = 32'h0000_d28a<br> 19311 Physical Address = 32'h0000_d28a<br> 19312 Reset Value = 16'h0000<br> 19313 Access = RO (16-bit only)<br> 19314 <table border=1 align=center width=100% cellpadding=0> 19315 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19316 <tr bgcolor=WHITE> 19317 <td bgcolor=WHITE align=center valign=top>15:00</td> 19318 <td align=left valign=top>RO</td> 19319 <td align=left valign=top>rx_hist_10</td> 19320 <td align=left> 19321 refer to rx_hist_stat_0 defn <br> 19322 Reset value is 0x0.</td></tr> 19323 </table><p> 19324 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19325 <hr> 19326 <b><a NAME="DSC_I_RX_HIST_STAT_11">DSC_I_RX_HIST_STAT_11 - RX Histogram Status 11</a></b><br> 19327 Address Offset = 32'h0000_d28b<br> 19328 Physical Address = 32'h0000_d28b<br> 19329 Reset Value = 16'h0000<br> 19330 Access = RO (16-bit only)<br> 19331 <table border=1 align=center width=100% cellpadding=0> 19332 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19333 <tr bgcolor=WHITE> 19334 <td bgcolor=WHITE align=center valign=top>15:00</td> 19335 <td align=left valign=top>RO</td> 19336 <td align=left valign=top>rx_hist_11</td> 19337 <td align=left> 19338 refer to rx_hist_stat_0 defn <br> 19339 Reset value is 0x0.</td></tr> 19340 </table><p> 19341 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19342 <hr> 19343 <b><a NAME="DSC_I_RX_HIST_STAT_12">DSC_I_RX_HIST_STAT_12 - RX Histogram Status 12</a></b><br> 19344 Address Offset = 32'h0000_d28c<br> 19345 Physical Address = 32'h0000_d28c<br> 19346 Reset Value = 16'h0000<br> 19347 Access = RO (16-bit only)<br> 19348 <table border=1 align=center width=100% cellpadding=0> 19349 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19350 <tr bgcolor=WHITE> 19351 <td bgcolor=WHITE align=center valign=top>15:00</td> 19352 <td align=left valign=top>RO</td> 19353 <td align=left valign=top>rx_hist_12</td> 19354 <td align=left> 19355 refer to rx_hist_stat_0 defn <br> 19356 Reset value is 0x0.</td></tr> 19357 </table><p> 19358 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19359 <hr> 19360 <b><a NAME="DSC_I_RX_HIST_STAT_13">DSC_I_RX_HIST_STAT_13 - RX Histogram Status 13</a></b><br> 19361 Address Offset = 32'h0000_d28d<br> 19362 Physical Address = 32'h0000_d28d<br> 19363 Reset Value = 16'h0000<br> 19364 Access = RO (16-bit only)<br> 19365 <table border=1 align=center width=100% cellpadding=0> 19366 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19367 <tr bgcolor=WHITE> 19368 <td bgcolor=WHITE align=center valign=top>15:00</td> 19369 <td align=left valign=top>RO</td> 19370 <td align=left valign=top>rx_hist_13</td> 19371 <td align=left> 19372 refer to rx_hist_stat_0 defn <br> 19373 Reset value is 0x0.</td></tr> 19374 </table><p> 19375 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19376 <hr> 19377 <b><a NAME="DSC_I_RX_HIST_CTRL">DSC_I_RX_HIST_CTRL - RX Histogram Controls</a></b><br> 19378 Address Offset = 32'h0000_d28e<br> 19379 Physical Address = 32'h0000_d28e<br> 19380 Reset Value = 16'h0000<br> 19381 Access = RW (16-bit only)<br> 19382 <table border=1 align=center width=100% cellpadding=0> 19383 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19384 <tr bgcolor=WHITE> 19385 <td bgcolor=WHITE align=center valign=top>15:04</td> 19386 <td align=left valign=top>RSVD</td> 19387 <td align=left valign=top>Reserved</td> 19388 <td align=left> 19389 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 19390 <tr bgcolor=WHITE> 19391 <td bgcolor=WHITE align=center valign=top>03</td> 19392 <td align=left valign=top>RW</td> 19393 <td align=left valign=top>rg_hist_clr</td> 19394 <td align=left> 19395 RX Histogram Clear<br> 19396 Reset value is 0x0.</td></tr> 19397 <tr bgcolor=WHITE> 19398 <td bgcolor=WHITE align=center valign=top>02</td> 19399 <td align=left valign=top>RW</td> 19400 <td align=left valign=top>rg_hist_stop</td> 19401 <td align=left> 19402 RX Histogram Stop<br> 19403 Reset value is 0x0.</td></tr> 19404 <tr bgcolor=WHITE> 19405 <td bgcolor=WHITE align=center valign=top>01:00</td> 19406 <td align=left valign=top>RW</td> 19407 <td align=left valign=top>rg_hist_rd_mux_sel</td> 19408 <td align=left> 19409 RX Histogram Read Mux Select<br> 19410 Reset value is 0x0.</td></tr> 19411 </table><p> 19412 <A HREF="#DSC_I Registers">Return to DSC_I: per lane register block [One Copy Per Lane] Table</A><p> 19413 <hr> 19414 <H1><a NAME="DSC_J Registers">DSC_J: per lane register block [One Copy Per Lane] Registers</a></H1> 19415 <table border=1 align=center width=100% cellpadding=0> 19416 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 19417 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 19418 <tr> 19419 <td align=center>0xD290</td><td><A HREF="#DSC_J_DSC_SM_CTL_0">DSC_J_DSC_SM_CTL_0</A><br>DSC SM Ctl 0</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">uc_adj_pi</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">acq_cdr_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">acq_cdr_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">acq_cdr_timeout_G1</div> </td> <td align=center>16'h210c</td></tr> 19420 <tr> 19421 <td align=center>0xD291</td><td><A HREF="#DSC_J_DSC_SM_CTL_1">DSC_J_DSC_SM_CTL_1</A><br>DSC SM Ctl 1</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">cdr_settle_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">cdr_settle_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">cdr_settle_timeout_G1</div> </td> <td align=center>16'h210c</td></tr> 19422 <tr> 19423 <td align=center>0xD292</td><td><A HREF="#DSC_J_DSC_SM_CTL_2">DSC_J_DSC_SM_CTL_2</A><br>DSC SM Ctl 2</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">hw_tune_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">hw_tune_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">hw_tune_timeout_G1</div> </td> <td align=center>16'h6000</td></tr> 19424 <tr> 19425 <td align=center>0xD293</td><td><A HREF="#DSC_J_DSC_SM_CTL_3">DSC_J_DSC_SM_CTL_3</A><br>DSC SM Ctl 3</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">facq_wait_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">facq_wait_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">facq_wait_timeout_G1</div> </td> <td align=center>16'h0000</td></tr> 19426 <tr> 19427 <td align=center>0xD294</td><td><A HREF="#DSC_J_DSC_SM_CTL_4">DSC_J_DSC_SM_CTL_4</A><br>DSC SM Ctl 4</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_acq_cdr_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_acq_cdr_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_acq_cdr_timeout_G1</div> </td> <td align=center>16'h1088</td></tr> 19428 <tr> 19429 <td align=center>0xD295</td><td><A HREF="#DSC_J_DSC_SM_CTL_5">DSC_J_DSC_SM_CTL_5</A><br>DSC SM Ctl 5</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_acq_cdr_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_acq_cdr_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_acq_cdr_timeout_G1</div> </td> <td align=center>16'h210c</td></tr> 19430 <tr> 19431 <td align=center>0xD296</td><td><A HREF="#DSC_J_DSC_SM_CTL_6">DSC_J_DSC_SM_CTL_6</A><br>DSC SM Ctl 6</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_cdr_sttl_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_cdr_sttl_timeout_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_cdr_sttl_timeout_G1</div> </td> <td align=center>16'h1088</td></tr> 19432 <tr> 19433 <td align=center>0xD297</td><td><A HREF="#DSC_J_DSC_SM_CTL_7">DSC_J_DSC_SM_CTL_7</A><br>DSC SM Ctl 7</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L1_hw_tune_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">L0s_hw_tune_timeout_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">measure_timeout_G3</div> </td> <td align=center>16'h0000</td></tr> 19434 <tr> 19435 <td align=center>0xD298</td><td><A HREF="#DSC_J_DSC_SM_CTL_8">DSC_J_DSC_SM_CTL_8</A><br>DSC SM Ctl 8</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L0s_acqcdr_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L0s_acqcdr_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_norm_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_norm_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_norm_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_acqcdr_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_acqcdr_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_acqcdr_G1</div> </td> <td align=center>16'ha56a</td></tr> 19436 <tr> 19437 <td align=center>0xD299</td><td><A HREF="#DSC_J_DSC_SM_CTL_9">DSC_J_DSC_SM_CTL_9</A><br>DSC SM Ctl 9</td><td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L1_cdrsttl_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L0s_cdrsttl_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L0s_cdrsttl_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L0s_cdrsttl_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L1_acqcdr_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L1_acqcdr_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L1_acqcdr_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L0s_acqcdr_G3</div> </td> <td align=center>16'h55aa</td></tr> 19438 <tr> 19439 <td align=center>0xD29A</td><td><A HREF="#DSC_J_DSC_SM_CTL_10">DSC_J_DSC_SM_CTL_10</A><br>DSC SM Ctl 10</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_acqcdr_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_acqcdr_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_acqcdr_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L1_cdrsttl_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="2"><div class="HT">cdr_bwsel_prop_L1_cdrsttl_G2</div> </td> <td align=center>16'h0005</td></tr> 19440 <tr> 19441 <td align=center>0xD29B</td><td><A HREF="#DSC_J_DSC_SM_CTL_11">DSC_J_DSC_SM_CTL_11</A><br>DSC SM Ctl 11</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L0s_acqcdr_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_norm_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_norm_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_norm_G1</div> </td> <td align=center>16'h0000</td></tr> 19442 <tr> 19443 <td align=center>0xD29C</td><td><A HREF="#DSC_J_DSC_SM_CTL_12">DSC_J_DSC_SM_CTL_12</A><br>DSC SM Ctl 12</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L1_acqcdr_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L1_acqcdr_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L0s_acqcdr_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L0s_acqcdr_G2</div> </td> <td align=center>16'h0000</td></tr> 19444 <tr> 19445 <td align=center>0xD29D</td><td><A HREF="#DSC_J_DSC_SM_CTL_13">DSC_J_DSC_SM_CTL_13</A><br>DSC SM Ctl 13</td><td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L0s_cdrsttl_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L0s_cdrsttl_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L0s_cdrsttl_G1</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L1_acqcdr_G3</div> </td> <td align=center>16'h0000</td></tr> 19446 <tr> 19447 <td align=center>0xD29E</td><td><A HREF="#DSC_J_DSC_SM_CTL_14">DSC_J_DSC_SM_CTL_14</A><br>DSC SM Ctl 14</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L1_cdrsttl_G3</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L1_cdrsttl_G2</div> </td> <td bgcolor=#FFFFFF align=center colspan="4"><div class="HT">cdr_bwsel_integ_L1_cdrsttl_G1</div> </td> <td align=center>16'h0000</td></tr> 19448 </table><p> 19449 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 19450 <hr> 19451 <b><a NAME="DSC_J_DSC_SM_CTL_0">DSC_J_DSC_SM_CTL_0 - DSC SM Ctl 0</a></b><br> 19452 Address Offset = 32'h0000_d290<br> 19453 Physical Address = 32'h0000_d290<br> 19454 Reset Value = 16'h210c<br> 19455 Access = RW (16-bit only)<br> 19456 <table border=1 align=center width=100% cellpadding=0> 19457 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19458 <tr bgcolor=WHITE> 19459 <td bgcolor=WHITE align=center valign=top>15</td> 19460 <td align=left valign=top>RW</td> 19461 <td align=left valign=top>uc_adj_pi</td> 19462 <td align=left> 19463 In the PAUSE state of DSC state machine, use firmware to adjust PI. <br> 19464 Reset value is 0x0.</td></tr> 19465 <tr bgcolor=WHITE> 19466 <td bgcolor=WHITE align=center valign=top>14:10</td> 19467 <td align=left valign=top>RW</td> 19468 <td align=left valign=top>acq_cdr_timeout_G3</td> 19469 <td align=left> 19470 Defines timeout value for the ACQ_CDR state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19471 Reset value is 0x8.</td></tr> 19472 <tr bgcolor=WHITE> 19473 <td bgcolor=WHITE align=center valign=top>09:05</td> 19474 <td align=left valign=top>RW</td> 19475 <td align=left valign=top>acq_cdr_timeout_G2</td> 19476 <td align=left> 19477 Defines timeout value for the ACQ_CDR state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19478 Reset value is 0x8.</td></tr> 19479 <tr bgcolor=WHITE> 19480 <td bgcolor=WHITE align=center valign=top>04:00</td> 19481 <td align=left valign=top>RW</td> 19482 <td align=left valign=top>acq_cdr_timeout_G1</td> 19483 <td align=left> 19484 Defines timeout value for the ACQ_CDR state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19485 Reset value is 0xc.</td></tr> 19486 </table><p> 19487 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19488 <hr> 19489 <b><a NAME="DSC_J_DSC_SM_CTL_1">DSC_J_DSC_SM_CTL_1 - DSC SM Ctl 1</a></b><br> 19490 Address Offset = 32'h0000_d291<br> 19491 Physical Address = 32'h0000_d291<br> 19492 Reset Value = 16'h210c<br> 19493 Access = RW (16-bit only)<br> 19494 <table border=1 align=center width=100% cellpadding=0> 19495 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19496 <tr bgcolor=WHITE> 19497 <td bgcolor=WHITE align=center valign=top>15</td> 19498 <td align=left valign=top>RSVD</td> 19499 <td align=left valign=top>Reserved</td> 19500 <td align=left> 19501 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19502 <tr bgcolor=WHITE> 19503 <td bgcolor=WHITE align=center valign=top>14:10</td> 19504 <td align=left valign=top>RW</td> 19505 <td align=left valign=top>cdr_settle_timeout_G3</td> 19506 <td align=left> 19507 Defines timeout value for the CDR_SETTLE state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19508 Reset value is 0x8.</td></tr> 19509 <tr bgcolor=WHITE> 19510 <td bgcolor=WHITE align=center valign=top>09:05</td> 19511 <td align=left valign=top>RW</td> 19512 <td align=left valign=top>cdr_settle_timeout_G2</td> 19513 <td align=left> 19514 Defines timeout value for the CDR_SETTLE state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19515 Reset value is 0x8.</td></tr> 19516 <tr bgcolor=WHITE> 19517 <td bgcolor=WHITE align=center valign=top>04:00</td> 19518 <td align=left valign=top>RW</td> 19519 <td align=left valign=top>cdr_settle_timeout_G1</td> 19520 <td align=left> 19521 Defines timeout value for the CDR_SETTLE state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19522 Reset value is 0xc.</td></tr> 19523 </table><p> 19524 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19525 <hr> 19526 <b><a NAME="DSC_J_DSC_SM_CTL_2">DSC_J_DSC_SM_CTL_2 - DSC SM Ctl 2</a></b><br> 19527 Address Offset = 32'h0000_d292<br> 19528 Physical Address = 32'h0000_d292<br> 19529 Reset Value = 16'h6000<br> 19530 Access = RW (16-bit only)<br> 19531 <table border=1 align=center width=100% cellpadding=0> 19532 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19533 <tr bgcolor=WHITE> 19534 <td bgcolor=WHITE align=center valign=top>15</td> 19535 <td align=left valign=top>RSVD</td> 19536 <td align=left valign=top>Reserved</td> 19537 <td align=left> 19538 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19539 <tr bgcolor=WHITE> 19540 <td bgcolor=WHITE align=center valign=top>14:10</td> 19541 <td align=left valign=top>RW</td> 19542 <td align=left valign=top>hw_tune_timeout_G3</td> 19543 <td align=left> 19544 Defines timeout value for the HW_TUNE state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19545 Reset value is 0x18.</td></tr> 19546 <tr bgcolor=WHITE> 19547 <td bgcolor=WHITE align=center valign=top>09:05</td> 19548 <td align=left valign=top>RW</td> 19549 <td align=left valign=top>hw_tune_timeout_G2</td> 19550 <td align=left> 19551 Defines timeout value for the HW_TUNE state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19552 Reset value is 0x0.</td></tr> 19553 <tr bgcolor=WHITE> 19554 <td bgcolor=WHITE align=center valign=top>04:00</td> 19555 <td align=left valign=top>RW</td> 19556 <td align=left valign=top>hw_tune_timeout_G1</td> 19557 <td align=left> 19558 Defines timeout value for the HW_TUNE state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19559 Reset value is 0x0.</td></tr> 19560 </table><p> 19561 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19562 <hr> 19563 <b><a NAME="DSC_J_DSC_SM_CTL_3">DSC_J_DSC_SM_CTL_3 - DSC SM Ctl 3</a></b><br> 19564 Address Offset = 32'h0000_d293<br> 19565 Physical Address = 32'h0000_d293<br> 19566 Reset Value = 16'h0000<br> 19567 Access = RW (16-bit only)<br> 19568 <table border=1 align=center width=100% cellpadding=0> 19569 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19570 <tr bgcolor=WHITE> 19571 <td bgcolor=WHITE align=center valign=top>15</td> 19572 <td align=left valign=top>RSVD</td> 19573 <td align=left valign=top>Reserved</td> 19574 <td align=left> 19575 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19576 <tr bgcolor=WHITE> 19577 <td bgcolor=WHITE align=center valign=top>14:10</td> 19578 <td align=left valign=top>RW</td> 19579 <td align=left valign=top>facq_wait_timeout_G3</td> 19580 <td align=left> 19581 Defines timeout value for the FACQ_WAIT state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19582 Reset value is 0x0.</td></tr> 19583 <tr bgcolor=WHITE> 19584 <td bgcolor=WHITE align=center valign=top>09:05</td> 19585 <td align=left valign=top>RW</td> 19586 <td align=left valign=top>facq_wait_timeout_G2</td> 19587 <td align=left> 19588 Defines timeout value for the FACQ_WAIT state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19589 Reset value is 0x0.</td></tr> 19590 <tr bgcolor=WHITE> 19591 <td bgcolor=WHITE align=center valign=top>04:00</td> 19592 <td align=left valign=top>RW</td> 19593 <td align=left valign=top>facq_wait_timeout_G1</td> 19594 <td align=left> 19595 Defines timeout value for the FACQ_WAIT state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19596 Reset value is 0x0.</td></tr> 19597 </table><p> 19598 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19599 <hr> 19600 <b><a NAME="DSC_J_DSC_SM_CTL_4">DSC_J_DSC_SM_CTL_4 - DSC SM Ctl 4</a></b><br> 19601 Address Offset = 32'h0000_d294<br> 19602 Physical Address = 32'h0000_d294<br> 19603 Reset Value = 16'h1088<br> 19604 Access = RW (16-bit only)<br> 19605 <table border=1 align=center width=100% cellpadding=0> 19606 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19607 <tr bgcolor=WHITE> 19608 <td bgcolor=WHITE align=center valign=top>15</td> 19609 <td align=left valign=top>RSVD</td> 19610 <td align=left valign=top>Reserved</td> 19611 <td align=left> 19612 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19613 <tr bgcolor=WHITE> 19614 <td bgcolor=WHITE align=center valign=top>14:10</td> 19615 <td align=left valign=top>RW</td> 19616 <td align=left valign=top>L0s_acq_cdr_timeout_G3</td> 19617 <td align=left> 19618 Defines timeout value for the L0sL1_ACQ_CDR state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19619 Reset value is 0x4.</td></tr> 19620 <tr bgcolor=WHITE> 19621 <td bgcolor=WHITE align=center valign=top>09:05</td> 19622 <td align=left valign=top>RW</td> 19623 <td align=left valign=top>L0s_acq_cdr_timeout_G2</td> 19624 <td align=left> 19625 Defines timeout value for the L0sL1_ACQ_CDR state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19626 Reset value is 0x4.</td></tr> 19627 <tr bgcolor=WHITE> 19628 <td bgcolor=WHITE align=center valign=top>04:00</td> 19629 <td align=left valign=top>RW</td> 19630 <td align=left valign=top>L0s_acq_cdr_timeout_G1</td> 19631 <td align=left> 19632 Defines timeout value for the L0sL1_ACQ_CDR state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19633 Reset value is 0x8.</td></tr> 19634 </table><p> 19635 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19636 <hr> 19637 <b><a NAME="DSC_J_DSC_SM_CTL_5">DSC_J_DSC_SM_CTL_5 - DSC SM Ctl 5</a></b><br> 19638 Address Offset = 32'h0000_d295<br> 19639 Physical Address = 32'h0000_d295<br> 19640 Reset Value = 16'h210c<br> 19641 Access = RW (16-bit only)<br> 19642 <table border=1 align=center width=100% cellpadding=0> 19643 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19644 <tr bgcolor=WHITE> 19645 <td bgcolor=WHITE align=center valign=top>15</td> 19646 <td align=left valign=top>RSVD</td> 19647 <td align=left valign=top>Reserved</td> 19648 <td align=left> 19649 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19650 <tr bgcolor=WHITE> 19651 <td bgcolor=WHITE align=center valign=top>14:10</td> 19652 <td align=left valign=top>RW</td> 19653 <td align=left valign=top>L1_acq_cdr_timeout_G3</td> 19654 <td align=left> 19655 Defines timeout value for the L0sL1_ACQ_CDR state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19656 Reset value is 0x8.</td></tr> 19657 <tr bgcolor=WHITE> 19658 <td bgcolor=WHITE align=center valign=top>09:05</td> 19659 <td align=left valign=top>RW</td> 19660 <td align=left valign=top>L1_acq_cdr_timeout_G2</td> 19661 <td align=left> 19662 Defines timeout value for the L0sL1_ACQ_CDR state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19663 Reset value is 0x8.</td></tr> 19664 <tr bgcolor=WHITE> 19665 <td bgcolor=WHITE align=center valign=top>04:00</td> 19666 <td align=left valign=top>RW</td> 19667 <td align=left valign=top>L1_acq_cdr_timeout_G1</td> 19668 <td align=left> 19669 Defines timeout value for the L0sL1_ACQ_CDR state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19670 Reset value is 0xc.</td></tr> 19671 </table><p> 19672 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19673 <hr> 19674 <b><a NAME="DSC_J_DSC_SM_CTL_6">DSC_J_DSC_SM_CTL_6 - DSC SM Ctl 6</a></b><br> 19675 Address Offset = 32'h0000_d296<br> 19676 Physical Address = 32'h0000_d296<br> 19677 Reset Value = 16'h1088<br> 19678 Access = RW (16-bit only)<br> 19679 <table border=1 align=center width=100% cellpadding=0> 19680 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19681 <tr bgcolor=WHITE> 19682 <td bgcolor=WHITE align=center valign=top>15</td> 19683 <td align=left valign=top>RSVD</td> 19684 <td align=left valign=top>Reserved</td> 19685 <td align=left> 19686 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19687 <tr bgcolor=WHITE> 19688 <td bgcolor=WHITE align=center valign=top>14:10</td> 19689 <td align=left valign=top>RW</td> 19690 <td align=left valign=top>L0s_cdr_sttl_timeout_G3</td> 19691 <td align=left> 19692 Defines timeout value for the L0sL1_CDR_STTL state timer in gen3 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19693 Reset value is 0x4.</td></tr> 19694 <tr bgcolor=WHITE> 19695 <td bgcolor=WHITE align=center valign=top>09:05</td> 19696 <td align=left valign=top>RW</td> 19697 <td align=left valign=top>L0s_cdr_sttl_timeout_G2</td> 19698 <td align=left> 19699 Defines timeout value for the L0sL1_CDR_STTL state timer in gen2 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19700 Reset value is 0x4.</td></tr> 19701 <tr bgcolor=WHITE> 19702 <td bgcolor=WHITE align=center valign=top>04:00</td> 19703 <td align=left valign=top>RW</td> 19704 <td align=left valign=top>L0s_cdr_sttl_timeout_G1</td> 19705 <td align=left> 19706 Defines timeout value for the L0sL1_CDR_STTL state timer in gen1 speed.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19707 Reset value is 0x8.</td></tr> 19708 </table><p> 19709 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19710 <hr> 19711 <b><a NAME="DSC_J_DSC_SM_CTL_7">DSC_J_DSC_SM_CTL_7 - DSC SM Ctl 7</a></b><br> 19712 Address Offset = 32'h0000_d297<br> 19713 Physical Address = 32'h0000_d297<br> 19714 Reset Value = 16'h0000<br> 19715 Access = RW (16-bit only)<br> 19716 <table border=1 align=center width=100% cellpadding=0> 19717 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19718 <tr bgcolor=WHITE> 19719 <td bgcolor=WHITE align=center valign=top>15</td> 19720 <td align=left valign=top>RSVD</td> 19721 <td align=left valign=top>Reserved</td> 19722 <td align=left> 19723 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 19724 <tr bgcolor=WHITE> 19725 <td bgcolor=WHITE align=center valign=top>14:10</td> 19726 <td align=left valign=top>RW</td> 19727 <td align=left valign=top>L1_hw_tune_timeout_G3</td> 19728 <td align=left> 19729 Defines timeout value for the L0sL1_HW_TUNE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19730 Reset value is 0x0.</td></tr> 19731 <tr bgcolor=WHITE> 19732 <td bgcolor=WHITE align=center valign=top>09:05</td> 19733 <td align=left valign=top>RW</td> 19734 <td align=left valign=top>L0s_hw_tune_timeout_G3</td> 19735 <td align=left> 19736 Defines timeout value for the L0sL1_HW_TUNE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19737 Reset value is 0x0.</td></tr> 19738 <tr bgcolor=WHITE> 19739 <td bgcolor=WHITE align=center valign=top>04:00</td> 19740 <td align=left valign=top>RW</td> 19741 <td align=left valign=top>measure_timeout_G3</td> 19742 <td align=left> 19743 Defines timeout value for the MEASURE state timer.  Valid range is 0 to 31 which is mapped to 0 to 448 LFSR wraps.<br> 19744 Reset value is 0x0.</td></tr> 19745 </table><p> 19746 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19747 <hr> 19748 <b><a NAME="DSC_J_DSC_SM_CTL_8">DSC_J_DSC_SM_CTL_8 - DSC SM Ctl 8</a></b><br> 19749 Address Offset = 32'h0000_d298<br> 19750 Physical Address = 32'h0000_d298<br> 19751 Reset Value = 16'ha56a<br> 19752 Access = RW (16-bit only)<br> 19753 <table border=1 align=center width=100% cellpadding=0> 19754 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19755 <tr bgcolor=WHITE> 19756 <td bgcolor=WHITE align=center valign=top>15:14</td> 19757 <td align=left valign=top>RW</td> 19758 <td align=left valign=top>cdr_bwsel_prop_L0s_acqcdr_G2</td> 19759 <td align=left> 19760 CDR Proportional Bandwidth select for L0sL1_ACQ_CDR states in gen2 speed. <br> 19761   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19762   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19763 Reset value is 0x2.</td></tr> 19764 <tr bgcolor=WHITE> 19765 <td bgcolor=WHITE align=center valign=top>13:12</td> 19766 <td align=left valign=top>RW</td> 19767 <td align=left valign=top>cdr_bwsel_prop_L0s_acqcdr_G1</td> 19768 <td align=left> 19769 CDR Proportional Bandwidth select for L0sL1_ACQ_CDR states in gen1 speed. <br> 19770   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19771   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19772 Reset value is 0x2.</td></tr> 19773 <tr bgcolor=WHITE> 19774 <td bgcolor=WHITE align=center valign=top>11:10</td> 19775 <td align=left valign=top>RW</td> 19776 <td align=left valign=top>cdr_bwsel_prop_norm_G3</td> 19777 <td align=left> 19778 CDR Proportional Bandwidth select for non ACQ_CDR states in gen3 speed. <br> 19779   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19780   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19781 Reset value is 0x1.</td></tr> 19782 <tr bgcolor=WHITE> 19783 <td bgcolor=WHITE align=center valign=top>09:08</td> 19784 <td align=left valign=top>RW</td> 19785 <td align=left valign=top>cdr_bwsel_prop_norm_G2</td> 19786 <td align=left> 19787 CDR Proportional Bandwidth select for non ACQ_CDR states in gen2 speed. <br> 19788   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19789   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19790 Reset value is 0x1.</td></tr> 19791 <tr bgcolor=WHITE> 19792 <td bgcolor=WHITE align=center valign=top>07:06</td> 19793 <td align=left valign=top>RW</td> 19794 <td align=left valign=top>cdr_bwsel_prop_norm_G1</td> 19795 <td align=left> 19796 CDR Proportional Bandwidth select for non ACQ_CDR states in gen1 speed. <br> 19797   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19798   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19799 Reset value is 0x1.</td></tr> 19800 <tr bgcolor=WHITE> 19801 <td bgcolor=WHITE align=center valign=top>05:04</td> 19802 <td align=left valign=top>RW</td> 19803 <td align=left valign=top>cdr_bwsel_prop_acqcdr_G3</td> 19804 <td align=left> 19805   CDR Proportional Bandwidth select for ACQ_CDR state in gen3 speed. <br> 19806   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19807   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19808 Reset value is 0x2.</td></tr> 19809 <tr bgcolor=WHITE> 19810 <td bgcolor=WHITE align=center valign=top>03:02</td> 19811 <td align=left valign=top>RW</td> 19812 <td align=left valign=top>cdr_bwsel_prop_acqcdr_G2</td> 19813 <td align=left> 19814   CDR Proportional Bandwidth select for ACQ_CDR state in gen2 speed. <br> 19815   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19816   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19817 Reset value is 0x2.</td></tr> 19818 <tr bgcolor=WHITE> 19819 <td bgcolor=WHITE align=center valign=top>01:00</td> 19820 <td align=left valign=top>RW</td> 19821 <td align=left valign=top>cdr_bwsel_prop_acqcdr_G1</td> 19822 <td align=left> 19823   CDR Proportional Bandwidth select for ACQ_CDR state in gen1 speed. <br> 19824   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19825   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19826 Reset value is 0x2.</td></tr> 19827 </table><p> 19828 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19829 <hr> 19830 <b><a NAME="DSC_J_DSC_SM_CTL_9">DSC_J_DSC_SM_CTL_9 - DSC SM Ctl 9</a></b><br> 19831 Address Offset = 32'h0000_d299<br> 19832 Physical Address = 32'h0000_d299<br> 19833 Reset Value = 16'h55aa<br> 19834 Access = RW (16-bit only)<br> 19835 <table border=1 align=center width=100% cellpadding=0> 19836 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19837 <tr bgcolor=WHITE> 19838 <td bgcolor=WHITE align=center valign=top>15:14</td> 19839 <td align=left valign=top>RW</td> 19840 <td align=left valign=top>cdr_bwsel_prop_L1_cdrsttl_G1</td> 19841 <td align=left> 19842 CDR Proportional Bandwidth select for L0sL1_CDR_STTL states in gen1 speed. <br> 19843   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19844   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19845 Reset value is 0x1.</td></tr> 19846 <tr bgcolor=WHITE> 19847 <td bgcolor=WHITE align=center valign=top>13:12</td> 19848 <td align=left valign=top>RW</td> 19849 <td align=left valign=top>cdr_bwsel_prop_L0s_cdrsttl_G3</td> 19850 <td align=left> 19851 CDR Proportional Bandwidth select for L0sL1_CDR_STTL states in gen3 speed. <br> 19852   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19853   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19854 Reset value is 0x1.</td></tr> 19855 <tr bgcolor=WHITE> 19856 <td bgcolor=WHITE align=center valign=top>11:10</td> 19857 <td align=left valign=top>RW</td> 19858 <td align=left valign=top>cdr_bwsel_prop_L0s_cdrsttl_G2</td> 19859 <td align=left> 19860 CDR Proportional Bandwidth select for L0sL1_CDR_STTL states in gen2 speed. <br> 19861   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19862   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19863 Reset value is 0x1.</td></tr> 19864 <tr bgcolor=WHITE> 19865 <td bgcolor=WHITE align=center valign=top>09:08</td> 19866 <td align=left valign=top>RW</td> 19867 <td align=left valign=top>cdr_bwsel_prop_L0s_cdrsttl_G1</td> 19868 <td align=left> 19869 CDR Proportional Bandwidth select for L0sL1_CDR_STTL states in gen1 speed. <br> 19870   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19871   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19872 Reset value is 0x1.</td></tr> 19873 <tr bgcolor=WHITE> 19874 <td bgcolor=WHITE align=center valign=top>07:06</td> 19875 <td align=left valign=top>RW</td> 19876 <td align=left valign=top>cdr_bwsel_prop_L1_acqcdr_G3</td> 19877 <td align=left> 19878 CDR Proportional Bandwidth select for L0sL1_ACQ_CDR states in gen3 speed. <br> 19879   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19880   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19881 Reset value is 0x2.</td></tr> 19882 <tr bgcolor=WHITE> 19883 <td bgcolor=WHITE align=center valign=top>05:04</td> 19884 <td align=left valign=top>RW</td> 19885 <td align=left valign=top>cdr_bwsel_prop_L1_acqcdr_G2</td> 19886 <td align=left> 19887 CDR Proportional Bandwidth select for L0sL1_ACQ_CDR states in gen2 speed. <br> 19888   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19889   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19890 Reset value is 0x2.</td></tr> 19891 <tr bgcolor=WHITE> 19892 <td bgcolor=WHITE align=center valign=top>03:02</td> 19893 <td align=left valign=top>RW</td> 19894 <td align=left valign=top>cdr_bwsel_prop_L1_acqcdr_G1</td> 19895 <td align=left> 19896 CDR Proportional Bandwidth select for L0sL1_ACQ_CDR states in gen1 speed. <br> 19897   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19898   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19899 Reset value is 0x2.</td></tr> 19900 <tr bgcolor=WHITE> 19901 <td bgcolor=WHITE align=center valign=top>01:00</td> 19902 <td align=left valign=top>RW</td> 19903 <td align=left valign=top>cdr_bwsel_prop_L0s_acqcdr_G3</td> 19904 <td align=left> 19905 CDR Proportional Bandwidth select for L0sL1_ACQ_CDR states in gen3 speed. <br> 19906   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19907   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19908 Reset value is 0x2.</td></tr> 19909 </table><p> 19910 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19911 <hr> 19912 <b><a NAME="DSC_J_DSC_SM_CTL_10">DSC_J_DSC_SM_CTL_10 - DSC SM Ctl 10</a></b><br> 19913 Address Offset = 32'h0000_d29a<br> 19914 Physical Address = 32'h0000_d29a<br> 19915 Reset Value = 16'h0005<br> 19916 Access = RW (16-bit only)<br> 19917 <table border=1 align=center width=100% cellpadding=0> 19918 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19919 <tr bgcolor=WHITE> 19920 <td bgcolor=WHITE align=center valign=top>15:12</td> 19921 <td align=left valign=top>RW</td> 19922 <td align=left valign=top>cdr_bwsel_integ_acqcdr_G3</td> 19923 <td align=left> 19924 CDR Integ Bandwidth select for ACQ_CDR state in gen3 speed. <br> 19925 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 19926 Reset value is 0x0.</td></tr> 19927 <tr bgcolor=WHITE> 19928 <td bgcolor=WHITE align=center valign=top>11:08</td> 19929 <td align=left valign=top>RW</td> 19930 <td align=left valign=top>cdr_bwsel_integ_acqcdr_G2</td> 19931 <td align=left> 19932 CDR Integ Bandwidth select for ACQ_CDR state in gen2 speed. <br> 19933 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 19934 Reset value is 0x0.</td></tr> 19935 <tr bgcolor=WHITE> 19936 <td bgcolor=WHITE align=center valign=top>07:04</td> 19937 <td align=left valign=top>RW</td> 19938 <td align=left valign=top>cdr_bwsel_integ_acqcdr_G1</td> 19939 <td align=left> 19940 CDR Integ Bandwidth select for ACQ_CDR state in gen1 speed. <br> 19941 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 19942 Reset value is 0x0.</td></tr> 19943 <tr bgcolor=WHITE> 19944 <td bgcolor=WHITE align=center valign=top>03:02</td> 19945 <td align=left valign=top>RW</td> 19946 <td align=left valign=top>cdr_bwsel_prop_L1_cdrsttl_G3</td> 19947 <td align=left> 19948 CDR Proportional Bandwidth select for L0sL1_CDR_STTL states in gen3 speed. <br> 19949   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19950   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19951 Reset value is 0x1.</td></tr> 19952 <tr bgcolor=WHITE> 19953 <td bgcolor=WHITE align=center valign=top>01:00</td> 19954 <td align=left valign=top>RW</td> 19955 <td align=left valign=top>cdr_bwsel_prop_L1_cdrsttl_G2</td> 19956 <td align=left> 19957 CDR Proportional Bandwidth select for L0sL1_CDR_STTL states in gen2 speed. <br> 19958   {0, 1, 2} map to {2^1, 2^2, 2^0} <br> 19959   2^2 has a user beware attached to it. Use is when max number of edges per rclk20 * osx2p_pherr_gain are guaranteed to be < 15  <br> 19960 Reset value is 0x1.</td></tr> 19961 </table><p> 19962 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 19963 <hr> 19964 <b><a NAME="DSC_J_DSC_SM_CTL_11">DSC_J_DSC_SM_CTL_11 - DSC SM Ctl 11</a></b><br> 19965 Address Offset = 32'h0000_d29b<br> 19966 Physical Address = 32'h0000_d29b<br> 19967 Reset Value = 16'h0000<br> 19968 Access = RW (16-bit only)<br> 19969 <table border=1 align=center width=100% cellpadding=0> 19970 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 19971 <tr bgcolor=WHITE> 19972 <td bgcolor=WHITE align=center valign=top>15:12</td> 19973 <td align=left valign=top>RW</td> 19974 <td align=left valign=top>cdr_bwsel_integ_L0s_acqcdr_G1</td> 19975 <td align=left> 19976 CDR Integ Bandwidth select for L0sL1_ACQ_CDR state in gen1 speed. <br> 19977 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 19978 Reset value is 0x0.</td></tr> 19979 <tr bgcolor=WHITE> 19980 <td bgcolor=WHITE align=center valign=top>11:08</td> 19981 <td align=left valign=top>RW</td> 19982 <td align=left valign=top>cdr_bwsel_integ_norm_G3</td> 19983 <td align=left> 19984 CDR Integ Bandwidth select for non ACQ_CDR and L0sL1_ACQ_CDR states in gen3 speed. <br> 19985 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 19986 Reset value is 0x0.</td></tr> 19987 <tr bgcolor=WHITE> 19988 <td bgcolor=WHITE align=center valign=top>07:04</td> 19989 <td align=left valign=top>RW</td> 19990 <td align=left valign=top>cdr_bwsel_integ_norm_G2</td> 19991 <td align=left> 19992 CDR Integ Bandwidth select for non ACQ_CDR and L0sL1_ACQ_CDR states in gen3 speed. <br> 19993 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 19994 Reset value is 0x0.</td></tr> 19995 <tr bgcolor=WHITE> 19996 <td bgcolor=WHITE align=center valign=top>03:00</td> 19997 <td align=left valign=top>RW</td> 19998 <td align=left valign=top>cdr_bwsel_integ_norm_G1</td> 19999 <td align=left> 20000 CDR Integ Bandwidth select for non ACQ_CDR and L0sL1_ACQ_CDR states in gen3 speed. <br> 20001 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20002 Reset value is 0x0.</td></tr> 20003 </table><p> 20004 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 20005 <hr> 20006 <b><a NAME="DSC_J_DSC_SM_CTL_12">DSC_J_DSC_SM_CTL_12 - DSC SM Ctl 12</a></b><br> 20007 Address Offset = 32'h0000_d29c<br> 20008 Physical Address = 32'h0000_d29c<br> 20009 Reset Value = 16'h0000<br> 20010 Access = RW (16-bit only)<br> 20011 <table border=1 align=center width=100% cellpadding=0> 20012 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20013 <tr bgcolor=WHITE> 20014 <td bgcolor=WHITE align=center valign=top>15:12</td> 20015 <td align=left valign=top>RW</td> 20016 <td align=left valign=top>cdr_bwsel_integ_L1_acqcdr_G2</td> 20017 <td align=left> 20018 CDR Integ Bandwidth select for L0sL1_ACQ_CDR state in gen2 speed. <br> 20019 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20020 Reset value is 0x0.</td></tr> 20021 <tr bgcolor=WHITE> 20022 <td bgcolor=WHITE align=center valign=top>11:08</td> 20023 <td align=left valign=top>RW</td> 20024 <td align=left valign=top>cdr_bwsel_integ_L1_acqcdr_G1</td> 20025 <td align=left> 20026 CDR Integ Bandwidth select for L0sL1_ACQ_CDR state in gen1 speed. <br> 20027 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20028 Reset value is 0x0.</td></tr> 20029 <tr bgcolor=WHITE> 20030 <td bgcolor=WHITE align=center valign=top>07:04</td> 20031 <td align=left valign=top>RW</td> 20032 <td align=left valign=top>cdr_bwsel_integ_L0s_acqcdr_G3</td> 20033 <td align=left> 20034 CDR Integ Bandwidth select for L0sL1_ACQ_CDR state in gen3 speed. <br> 20035 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20036 Reset value is 0x0.</td></tr> 20037 <tr bgcolor=WHITE> 20038 <td bgcolor=WHITE align=center valign=top>03:00</td> 20039 <td align=left valign=top>RW</td> 20040 <td align=left valign=top>cdr_bwsel_integ_L0s_acqcdr_G2</td> 20041 <td align=left> 20042 CDR Integ Bandwidth select for L0sL1_ACQ_CDR state in gen2 speed. <br> 20043 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20044 Reset value is 0x0.</td></tr> 20045 </table><p> 20046 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 20047 <hr> 20048 <b><a NAME="DSC_J_DSC_SM_CTL_13">DSC_J_DSC_SM_CTL_13 - DSC SM Ctl 13</a></b><br> 20049 Address Offset = 32'h0000_d29d<br> 20050 Physical Address = 32'h0000_d29d<br> 20051 Reset Value = 16'h0000<br> 20052 Access = RW (16-bit only)<br> 20053 <table border=1 align=center width=100% cellpadding=0> 20054 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20055 <tr bgcolor=WHITE> 20056 <td bgcolor=WHITE align=center valign=top>15:12</td> 20057 <td align=left valign=top>RW</td> 20058 <td align=left valign=top>cdr_bwsel_integ_L0s_cdrsttl_G3</td> 20059 <td align=left> 20060 CDR Integ Bandwidth select for L0sL1_CDR_STTL state in gen3 speed. <br> 20061 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20062 Reset value is 0x0.</td></tr> 20063 <tr bgcolor=WHITE> 20064 <td bgcolor=WHITE align=center valign=top>11:08</td> 20065 <td align=left valign=top>RW</td> 20066 <td align=left valign=top>cdr_bwsel_integ_L0s_cdrsttl_G2</td> 20067 <td align=left> 20068 CDR Integ Bandwidth select for L0sL1_CDR_STTL state in gen2 speed. <br> 20069 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20070 Reset value is 0x0.</td></tr> 20071 <tr bgcolor=WHITE> 20072 <td bgcolor=WHITE align=center valign=top>07:04</td> 20073 <td align=left valign=top>RW</td> 20074 <td align=left valign=top>cdr_bwsel_integ_L0s_cdrsttl_G1</td> 20075 <td align=left> 20076 CDR Integ Bandwidth select for L0sL1_CDR_STTL state in gen1 speed. <br> 20077 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20078 Reset value is 0x0.</td></tr> 20079 <tr bgcolor=WHITE> 20080 <td bgcolor=WHITE align=center valign=top>03:00</td> 20081 <td align=left valign=top>RW</td> 20082 <td align=left valign=top>cdr_bwsel_integ_L1_acqcdr_G3</td> 20083 <td align=left> 20084 CDR Integ Bandwidth select for L0sL1_ACQ_CDR state in gen3 speed. <br> 20085 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20086 Reset value is 0x0.</td></tr> 20087 </table><p> 20088 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 20089 <hr> 20090 <b><a NAME="DSC_J_DSC_SM_CTL_14">DSC_J_DSC_SM_CTL_14 - DSC SM Ctl 14</a></b><br> 20091 Address Offset = 32'h0000_d29e<br> 20092 Physical Address = 32'h0000_d29e<br> 20093 Reset Value = 16'h0000<br> 20094 Access = RW (16-bit only)<br> 20095 <table border=1 align=center width=100% cellpadding=0> 20096 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20097 <tr bgcolor=WHITE> 20098 <td bgcolor=WHITE align=center valign=top>15:12</td> 20099 <td align=left valign=top>RSVD</td> 20100 <td align=left valign=top>Reserved</td> 20101 <td align=left> 20102 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20103 <tr bgcolor=WHITE> 20104 <td bgcolor=WHITE align=center valign=top>11:08</td> 20105 <td align=left valign=top>RW</td> 20106 <td align=left valign=top>cdr_bwsel_integ_L1_cdrsttl_G3</td> 20107 <td align=left> 20108 CDR Integ Bandwidth select for L0sL1_CDR_STTL state in gen3 speed. <br> 20109 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20110 Reset value is 0x0.</td></tr> 20111 <tr bgcolor=WHITE> 20112 <td bgcolor=WHITE align=center valign=top>07:04</td> 20113 <td align=left valign=top>RW</td> 20114 <td align=left valign=top>cdr_bwsel_integ_L1_cdrsttl_G2</td> 20115 <td align=left> 20116 CDR Integ Bandwidth select for L0sL1_CDR_STTL state in gen2 speed. <br> 20117 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20118 Reset value is 0x0.</td></tr> 20119 <tr bgcolor=WHITE> 20120 <td bgcolor=WHITE align=center valign=top>03:00</td> 20121 <td align=left valign=top>RW</td> 20122 <td align=left valign=top>cdr_bwsel_integ_L1_cdrsttl_G1</td> 20123 <td align=left> 20124 CDR Integ Bandwidth select for L0sL1_CDR_STTL state in gen1 speed. <br> 20125 {0->4} <=> 2^{0->4}. {13,14,15} <=> {2^{-3,-2,-1}}. <br> 20126 Reset value is 0x0.</td></tr> 20127 </table><p> 20128 <A HREF="#DSC_J Registers">Return to DSC_J: per lane register block [One Copy Per Lane] Table</A><p> 20129 <hr> 20130 <H1><a NAME="TX_COEFF_MAIN Registers">TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Registers</a></H1> 20131 <table border=1 align=center width=100% cellpadding=0> 20132 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 20133 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 20134 <tr> 20135 <td align=center>0xD300</td><td><A HREF="#TX_COEFF_MAIN_MAIN_EXTENT_CTRL0">TX_COEFF_MAIN_MAIN_EXTENT_CTRL0</A><br>TX COEFF main_extent_0</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_main_extent_0</div> </td> <td align=center>16'h01ff</td></tr> 20136 <tr> 20137 <td align=center>0xD301</td><td><A HREF="#TX_COEFF_MAIN_MAIN_EXTENT_CTRL1">TX_COEFF_MAIN_MAIN_EXTENT_CTRL1</A><br>TX COEFF main_extent_1</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_main_extent_1</div> </td> <td align=center>16'h01df</td></tr> 20138 <tr> 20139 <td align=center>0xD302</td><td><A HREF="#TX_COEFF_MAIN_MAIN_EXTENT_CTRL2">TX_COEFF_MAIN_MAIN_EXTENT_CTRL2</A><br>TX COEFF main_extent_2</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_main_extent_2</div> </td> <td align=center>16'h013f</td></tr> 20140 <tr> 20141 <td align=center>0xD303</td><td><A HREF="#TX_COEFF_MAIN_MAIN_EXTENT_CTRL3">TX_COEFF_MAIN_MAIN_EXTENT_CTRL3</A><br>TX COEFF main_extent_3</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_main_extent_3</div> </td> <td align=center>16'h003f</td></tr> 20142 <tr> 20143 <td align=center>0xD304</td><td><A HREF="#TX_COEFF_MAIN_MAIN_EXTENT_CTRL4">TX_COEFF_MAIN_MAIN_EXTENT_CTRL4</A><br>TX COEFF main_extent_4</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_main_extent_4</div> </td> <td align=center>16'h000f</td></tr> 20144 <tr> 20145 <td align=center>0xD305</td><td><A HREF="#TX_COEFF_MAIN_MAIN_EXTENT_CTRL5">TX_COEFF_MAIN_MAIN_EXTENT_CTRL5</A><br>TX COEFF main_extent_5</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_main_extent_5</div> </td> <td align=center>16'h000b</td></tr> 20146 </table><p> 20147 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 20148 <hr> 20149 <b><a NAME="TX_COEFF_MAIN_MAIN_EXTENT_CTRL0">TX_COEFF_MAIN_MAIN_EXTENT_CTRL0 - TX COEFF main_extent_0</a></b><br> 20150 Address Offset = 32'h0000_d300<br> 20151 Physical Address = 32'h0000_d300<br> 20152 Reset Value = 16'h01ff<br> 20153 Access = RW (16-bit only)<br> 20154 <table border=1 align=center width=100% cellpadding=0> 20155 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20156 <tr bgcolor=WHITE> 20157 <td bgcolor=WHITE align=center valign=top>15</td> 20158 <td align=left valign=top>RSVD</td> 20159 <td align=left valign=top>Reserved</td> 20160 <td align=left> 20161 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20162 <tr bgcolor=WHITE> 20163 <td bgcolor=WHITE align=center valign=top>14:00</td> 20164 <td align=left valign=top>RW</td> 20165 <td align=left valign=top>fir_main_extent_0</td> 20166 <td align=left> 20167 tx coeff fir_main_extent_0 when pre_coefficient = 11<br> 20168 Reset value is 0x1ff.</td></tr> 20169 </table><p> 20170 <A HREF="#TX_COEFF_MAIN Registers">Return to TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Table</A><p> 20171 <hr> 20172 <b><a NAME="TX_COEFF_MAIN_MAIN_EXTENT_CTRL1">TX_COEFF_MAIN_MAIN_EXTENT_CTRL1 - TX COEFF main_extent_1</a></b><br> 20173 Address Offset = 32'h0000_d301<br> 20174 Physical Address = 32'h0000_d301<br> 20175 Reset Value = 16'h01df<br> 20176 Access = RW (16-bit only)<br> 20177 <table border=1 align=center width=100% cellpadding=0> 20178 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20179 <tr bgcolor=WHITE> 20180 <td bgcolor=WHITE align=center valign=top>15</td> 20181 <td align=left valign=top>RSVD</td> 20182 <td align=left valign=top>Reserved</td> 20183 <td align=left> 20184 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20185 <tr bgcolor=WHITE> 20186 <td bgcolor=WHITE align=center valign=top>14:00</td> 20187 <td align=left valign=top>RW</td> 20188 <td align=left valign=top>fir_main_extent_1</td> 20189 <td align=left> 20190 tx coeff fir_main_extent_1 when pre_coefficient = 11<br> 20191 Reset value is 0x1df.</td></tr> 20192 </table><p> 20193 <A HREF="#TX_COEFF_MAIN Registers">Return to TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Table</A><p> 20194 <hr> 20195 <b><a NAME="TX_COEFF_MAIN_MAIN_EXTENT_CTRL2">TX_COEFF_MAIN_MAIN_EXTENT_CTRL2 - TX COEFF main_extent_2</a></b><br> 20196 Address Offset = 32'h0000_d302<br> 20197 Physical Address = 32'h0000_d302<br> 20198 Reset Value = 16'h013f<br> 20199 Access = RW (16-bit only)<br> 20200 <table border=1 align=center width=100% cellpadding=0> 20201 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20202 <tr bgcolor=WHITE> 20203 <td bgcolor=WHITE align=center valign=top>15</td> 20204 <td align=left valign=top>RSVD</td> 20205 <td align=left valign=top>Reserved</td> 20206 <td align=left> 20207 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20208 <tr bgcolor=WHITE> 20209 <td bgcolor=WHITE align=center valign=top>14:00</td> 20210 <td align=left valign=top>RW</td> 20211 <td align=left valign=top>fir_main_extent_2</td> 20212 <td align=left> 20213 tx coeff fir_main_extent_2 when pre_coefficient = 12<br> 20214 Reset value is 0x13f.</td></tr> 20215 </table><p> 20216 <A HREF="#TX_COEFF_MAIN Registers">Return to TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Table</A><p> 20217 <hr> 20218 <b><a NAME="TX_COEFF_MAIN_MAIN_EXTENT_CTRL3">TX_COEFF_MAIN_MAIN_EXTENT_CTRL3 - TX COEFF main_extent_3</a></b><br> 20219 Address Offset = 32'h0000_d303<br> 20220 Physical Address = 32'h0000_d303<br> 20221 Reset Value = 16'h003f<br> 20222 Access = RW (16-bit only)<br> 20223 <table border=1 align=center width=100% cellpadding=0> 20224 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20225 <tr bgcolor=WHITE> 20226 <td bgcolor=WHITE align=center valign=top>15</td> 20227 <td align=left valign=top>RSVD</td> 20228 <td align=left valign=top>Reserved</td> 20229 <td align=left> 20230 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20231 <tr bgcolor=WHITE> 20232 <td bgcolor=WHITE align=center valign=top>14:00</td> 20233 <td align=left valign=top>RW</td> 20234 <td align=left valign=top>fir_main_extent_3</td> 20235 <td align=left> 20236 tx coeff fir_main_extent_3 when pre_coefficient = 13<br> 20237 Reset value is 0x3f.</td></tr> 20238 </table><p> 20239 <A HREF="#TX_COEFF_MAIN Registers">Return to TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Table</A><p> 20240 <hr> 20241 <b><a NAME="TX_COEFF_MAIN_MAIN_EXTENT_CTRL4">TX_COEFF_MAIN_MAIN_EXTENT_CTRL4 - TX COEFF main_extent_4</a></b><br> 20242 Address Offset = 32'h0000_d304<br> 20243 Physical Address = 32'h0000_d304<br> 20244 Reset Value = 16'h000f<br> 20245 Access = RW (16-bit only)<br> 20246 <table border=1 align=center width=100% cellpadding=0> 20247 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20248 <tr bgcolor=WHITE> 20249 <td bgcolor=WHITE align=center valign=top>15</td> 20250 <td align=left valign=top>RSVD</td> 20251 <td align=left valign=top>Reserved</td> 20252 <td align=left> 20253 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20254 <tr bgcolor=WHITE> 20255 <td bgcolor=WHITE align=center valign=top>14:00</td> 20256 <td align=left valign=top>RW</td> 20257 <td align=left valign=top>fir_main_extent_4</td> 20258 <td align=left> 20259 tx coeff fir_main_extent_4 when pre_coefficient = 14<br> 20260 Reset value is 0xf.</td></tr> 20261 </table><p> 20262 <A HREF="#TX_COEFF_MAIN Registers">Return to TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Table</A><p> 20263 <hr> 20264 <b><a NAME="TX_COEFF_MAIN_MAIN_EXTENT_CTRL5">TX_COEFF_MAIN_MAIN_EXTENT_CTRL5 - TX COEFF main_extent_5</a></b><br> 20265 Address Offset = 32'h0000_d305<br> 20266 Physical Address = 32'h0000_d305<br> 20267 Reset Value = 16'h000b<br> 20268 Access = RW (16-bit only)<br> 20269 <table border=1 align=center width=100% cellpadding=0> 20270 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20271 <tr bgcolor=WHITE> 20272 <td bgcolor=WHITE align=center valign=top>15</td> 20273 <td align=left valign=top>RSVD</td> 20274 <td align=left valign=top>Reserved</td> 20275 <td align=left> 20276 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20277 <tr bgcolor=WHITE> 20278 <td bgcolor=WHITE align=center valign=top>14:00</td> 20279 <td align=left valign=top>RW</td> 20280 <td align=left valign=top>fir_main_extent_5</td> 20281 <td align=left> 20282 tx coeff fir_main_extent_5 when pre_coefficient = 15<br> 20283 Reset value is 0xb.</td></tr> 20284 </table><p> 20285 <A HREF="#TX_COEFF_MAIN Registers">Return to TX_COEFF_MAIN: per lane register block [One Copy Per Lane] Table</A><p> 20286 <hr> 20287 <H1><a NAME="TX_COEFF_PM Registers">TX_COEFF_PM: per lane register block [One Copy Per Lane] Registers</a></H1> 20288 <table border=1 align=center width=100% cellpadding=0> 20289 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 20290 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 20291 <tr> 20292 <td align=center>0xD310</td><td><A HREF="#TX_COEFF_PM_PRE_CTRL0">TX_COEFF_PM_PRE_CTRL0</A><br>TX COEFF FIR_PRE Register: R1R0</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_1</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_0</div> </td> <td align=center>16'h0040</td></tr> 20293 <tr> 20294 <td align=center>0xD311</td><td><A HREF="#TX_COEFF_PM_PRE_CTRL1">TX_COEFF_PM_PRE_CTRL1</A><br>TX COEFF FIR_PRE Register: R3R2</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_3</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_2</div> </td> <td align=center>16'h0144</td></tr> 20295 <tr> 20296 <td align=center>0xD312</td><td><A HREF="#TX_COEFF_PM_PRE_CTRL2">TX_COEFF_PM_PRE_CTRL2</A><br>TX COEFF FIR_PRE Register: R5R4</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_5</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_4</div> </td> <td align=center>16'h034c</td></tr> 20297 <tr> 20298 <td align=center>0xD313</td><td><A HREF="#TX_COEFF_PM_PRE_CTRL3">TX_COEFF_PM_PRE_CTRL3</A><br>TX COEFF FIR_PRE Register: R7R6</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_7</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_6</div> </td> <td align=center>16'h075c</td></tr> 20299 <tr> 20300 <td align=center>0xD314</td><td><A HREF="#TX_COEFF_PM_PRE_CTRL4">TX_COEFF_PM_PRE_CTRL4</A><br>TX COEFF FIR_PRE Register: R9R8</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_9</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_8</div> </td> <td align=center>16'h0f7c</td></tr> 20301 <tr> 20302 <td align=center>0xD315</td><td><A HREF="#TX_COEFF_PM_PRE_CTRL5">TX_COEFF_PM_PRE_CTRL5</A><br>TX COEFF FIR_PRE Register: R11R10</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_10</div> </td> <td align=center>16'h003f</td></tr> 20303 <tr> 20304 <td align=center>0xD316</td><td><A HREF="#TX_COEFF_PM_REGMAIN_CTRL0">TX_COEFF_PM_REGMAIN_CTRL0</A><br>TX COEFF REG_MAINPOST Register: R2R1</td><td bgcolor=#CCCCCC align=center colspan="6"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">reg_en_main</div> </td> <td bgcolor=#FFFFFF align=center colspan="3"><div class="HT">reg_main_cs</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">reg_main_post1pre_default</div> </td> <td align=center>16'h03c0</td></tr> 20305 <tr> 20306 <td align=center>0xD317</td><td><A HREF="#TX_COEFF_PM_REGOVRD_CTRL">TX_COEFF_PM_REGOVRD_CTRL</A><br>TX COEFF REG over_write</td><td bgcolor=#CCCCCC align=center colspan="15"><div class="HT">reserved_for_eco</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">reg_ovrd</div> </td> <td align=center>16'h0000</td></tr> 20307 </table><p> 20308 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 20309 <hr> 20310 <b><a NAME="TX_COEFF_PM_PRE_CTRL0">TX_COEFF_PM_PRE_CTRL0 - TX COEFF FIR_PRE Register: R1R0</a></b><br> 20311 Address Offset = 32'h0000_d310<br> 20312 Physical Address = 32'h0000_d310<br> 20313 Reset Value = 16'h0040<br> 20314 Access = RW (16-bit only)<br> 20315 <table border=1 align=center width=100% cellpadding=0> 20316 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20317 <tr bgcolor=WHITE> 20318 <td bgcolor=WHITE align=center valign=top>15:12</td> 20319 <td align=left valign=top>RSVD</td> 20320 <td align=left valign=top>Reserved</td> 20321 <td align=left> 20322 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20323 <tr bgcolor=WHITE> 20324 <td bgcolor=WHITE align=center valign=top>11:06</td> 20325 <td align=left valign=top>RW</td> 20326 <td align=left valign=top>fir_pre_1</td> 20327 <td align=left> 20328 tx coeff fir_pre_1 <br> 20329 Reset value is 0x1.</td></tr> 20330 <tr bgcolor=WHITE> 20331 <td bgcolor=WHITE align=center valign=top>05:00</td> 20332 <td align=left valign=top>RW</td> 20333 <td align=left valign=top>fir_pre_0</td> 20334 <td align=left> 20335 tx coeff fir_pre_0 <br> 20336 Reset value is 0x0.</td></tr> 20337 </table><p> 20338 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20339 <hr> 20340 <b><a NAME="TX_COEFF_PM_PRE_CTRL1">TX_COEFF_PM_PRE_CTRL1 - TX COEFF FIR_PRE Register: R3R2</a></b><br> 20341 Address Offset = 32'h0000_d311<br> 20342 Physical Address = 32'h0000_d311<br> 20343 Reset Value = 16'h0144<br> 20344 Access = RW (16-bit only)<br> 20345 <table border=1 align=center width=100% cellpadding=0> 20346 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20347 <tr bgcolor=WHITE> 20348 <td bgcolor=WHITE align=center valign=top>15:12</td> 20349 <td align=left valign=top>RSVD</td> 20350 <td align=left valign=top>Reserved</td> 20351 <td align=left> 20352 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20353 <tr bgcolor=WHITE> 20354 <td bgcolor=WHITE align=center valign=top>11:06</td> 20355 <td align=left valign=top>RW</td> 20356 <td align=left valign=top>fir_pre_3</td> 20357 <td align=left> 20358 tx coeff fir_pre_3 <br> 20359 Reset value is 0x5.</td></tr> 20360 <tr bgcolor=WHITE> 20361 <td bgcolor=WHITE align=center valign=top>05:00</td> 20362 <td align=left valign=top>RW</td> 20363 <td align=left valign=top>fir_pre_2</td> 20364 <td align=left> 20365 tx coeff fir_pre_2 <br> 20366 Reset value is 0x4.</td></tr> 20367 </table><p> 20368 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20369 <hr> 20370 <b><a NAME="TX_COEFF_PM_PRE_CTRL2">TX_COEFF_PM_PRE_CTRL2 - TX COEFF FIR_PRE Register: R5R4</a></b><br> 20371 Address Offset = 32'h0000_d312<br> 20372 Physical Address = 32'h0000_d312<br> 20373 Reset Value = 16'h034c<br> 20374 Access = RW (16-bit only)<br> 20375 <table border=1 align=center width=100% cellpadding=0> 20376 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20377 <tr bgcolor=WHITE> 20378 <td bgcolor=WHITE align=center valign=top>15:12</td> 20379 <td align=left valign=top>RSVD</td> 20380 <td align=left valign=top>Reserved</td> 20381 <td align=left> 20382 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20383 <tr bgcolor=WHITE> 20384 <td bgcolor=WHITE align=center valign=top>11:06</td> 20385 <td align=left valign=top>RW</td> 20386 <td align=left valign=top>fir_pre_5</td> 20387 <td align=left> 20388 tx coeff fir_pre_5 <br> 20389 Reset value is 0xd.</td></tr> 20390 <tr bgcolor=WHITE> 20391 <td bgcolor=WHITE align=center valign=top>05:00</td> 20392 <td align=left valign=top>RW</td> 20393 <td align=left valign=top>fir_pre_4</td> 20394 <td align=left> 20395 tx coeff fir_pre_4 <br> 20396 Reset value is 0xc.</td></tr> 20397 </table><p> 20398 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20399 <hr> 20400 <b><a NAME="TX_COEFF_PM_PRE_CTRL3">TX_COEFF_PM_PRE_CTRL3 - TX COEFF FIR_PRE Register: R7R6</a></b><br> 20401 Address Offset = 32'h0000_d313<br> 20402 Physical Address = 32'h0000_d313<br> 20403 Reset Value = 16'h075c<br> 20404 Access = RW (16-bit only)<br> 20405 <table border=1 align=center width=100% cellpadding=0> 20406 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20407 <tr bgcolor=WHITE> 20408 <td bgcolor=WHITE align=center valign=top>15:12</td> 20409 <td align=left valign=top>RSVD</td> 20410 <td align=left valign=top>Reserved</td> 20411 <td align=left> 20412 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20413 <tr bgcolor=WHITE> 20414 <td bgcolor=WHITE align=center valign=top>11:06</td> 20415 <td align=left valign=top>RW</td> 20416 <td align=left valign=top>fir_pre_7</td> 20417 <td align=left> 20418 tx coeff fir_pre_7 <br> 20419 Reset value is 0x1d.</td></tr> 20420 <tr bgcolor=WHITE> 20421 <td bgcolor=WHITE align=center valign=top>05:00</td> 20422 <td align=left valign=top>RW</td> 20423 <td align=left valign=top>fir_pre_6</td> 20424 <td align=left> 20425 tx coeff fir_pre_6 <br> 20426 Reset value is 0x1c.</td></tr> 20427 </table><p> 20428 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20429 <hr> 20430 <b><a NAME="TX_COEFF_PM_PRE_CTRL4">TX_COEFF_PM_PRE_CTRL4 - TX COEFF FIR_PRE Register: R9R8</a></b><br> 20431 Address Offset = 32'h0000_d314<br> 20432 Physical Address = 32'h0000_d314<br> 20433 Reset Value = 16'h0f7c<br> 20434 Access = RW (16-bit only)<br> 20435 <table border=1 align=center width=100% cellpadding=0> 20436 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20437 <tr bgcolor=WHITE> 20438 <td bgcolor=WHITE align=center valign=top>15:12</td> 20439 <td align=left valign=top>RSVD</td> 20440 <td align=left valign=top>Reserved</td> 20441 <td align=left> 20442 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20443 <tr bgcolor=WHITE> 20444 <td bgcolor=WHITE align=center valign=top>11:06</td> 20445 <td align=left valign=top>RW</td> 20446 <td align=left valign=top>fir_pre_9</td> 20447 <td align=left> 20448 tx coeff fir_pre_9 <br> 20449 Reset value is 0x3d.</td></tr> 20450 <tr bgcolor=WHITE> 20451 <td bgcolor=WHITE align=center valign=top>05:00</td> 20452 <td align=left valign=top>RW</td> 20453 <td align=left valign=top>fir_pre_8</td> 20454 <td align=left> 20455 tx coeff fir_pre_8 <br> 20456 Reset value is 0x3c.</td></tr> 20457 </table><p> 20458 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20459 <hr> 20460 <b><a NAME="TX_COEFF_PM_PRE_CTRL5">TX_COEFF_PM_PRE_CTRL5 - TX COEFF FIR_PRE Register: R11R10</a></b><br> 20461 Address Offset = 32'h0000_d315<br> 20462 Physical Address = 32'h0000_d315<br> 20463 Reset Value = 16'h003f<br> 20464 Access = RW (16-bit only)<br> 20465 <table border=1 align=center width=100% cellpadding=0> 20466 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20467 <tr bgcolor=WHITE> 20468 <td bgcolor=WHITE align=center valign=top>15:06</td> 20469 <td align=left valign=top>RSVD</td> 20470 <td align=left valign=top>Reserved</td> 20471 <td align=left> 20472 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20473 <tr bgcolor=WHITE> 20474 <td bgcolor=WHITE align=center valign=top>05:00</td> 20475 <td align=left valign=top>RW</td> 20476 <td align=left valign=top>fir_pre_10</td> 20477 <td align=left> 20478 tx coeff fir_pre_10 <br> 20479 Reset value is 0x3f.</td></tr> 20480 </table><p> 20481 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20482 <hr> 20483 <b><a NAME="TX_COEFF_PM_REGMAIN_CTRL0">TX_COEFF_PM_REGMAIN_CTRL0 - TX COEFF REG_MAINPOST Register: R2R1</a></b><br> 20484 Address Offset = 32'h0000_d316<br> 20485 Physical Address = 32'h0000_d316<br> 20486 Reset Value = 16'h03c0<br> 20487 Access = RW (16-bit only)<br> 20488 <table border=1 align=center width=100% cellpadding=0> 20489 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20490 <tr bgcolor=WHITE> 20491 <td bgcolor=WHITE align=center valign=top>15:10</td> 20492 <td align=left valign=top>RSVD</td> 20493 <td align=left valign=top>Reserved</td> 20494 <td align=left> 20495 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20496 <tr bgcolor=WHITE> 20497 <td bgcolor=WHITE align=center valign=top>09</td> 20498 <td align=left valign=top>RW</td> 20499 <td align=left valign=top>reg_en_main</td> 20500 <td align=left> 20501 tx coeff reg_en_main <br> 20502 Reset value is 0x1.</td></tr> 20503 <tr bgcolor=WHITE> 20504 <td bgcolor=WHITE align=center valign=top>08:06</td> 20505 <td align=left valign=top>RW</td> 20506 <td align=left valign=top>reg_main_cs</td> 20507 <td align=left> 20508 tx coeff reg_main_cs <br> 20509 Reset value is 0x7.</td></tr> 20510 <tr bgcolor=WHITE> 20511 <td bgcolor=WHITE align=center valign=top>05:00</td> 20512 <td align=left valign=top>RW</td> 20513 <td align=left valign=top>reg_main_post1pre_default</td> 20514 <td align=left> 20515 tx coeff reg_main_post1pre default value<br> 20516 Reset value is 0x0.</td></tr> 20517 </table><p> 20518 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20519 <hr> 20520 <b><a NAME="TX_COEFF_PM_REGOVRD_CTRL">TX_COEFF_PM_REGOVRD_CTRL - TX COEFF REG over_write</a></b><br> 20521 Address Offset = 32'h0000_d317<br> 20522 Physical Address = 32'h0000_d317<br> 20523 Reset Value = 16'h0000<br> 20524 Access = RW (16-bit only)<br> 20525 <table border=1 align=center width=100% cellpadding=0> 20526 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20527 <tr bgcolor=WHITE> 20528 <td bgcolor=WHITE align=center valign=top>15:01</td> 20529 <td align=left valign=top>RSVD</td> 20530 <td align=left valign=top>Reserved</td> 20531 <td align=left> 20532 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 20533 <tr bgcolor=WHITE> 20534 <td bgcolor=WHITE align=center valign=top>00</td> 20535 <td align=left valign=top>RW</td> 20536 <td align=left valign=top>reg_ovrd</td> 20537 <td align=left> 20538 tx coeff register over_write <br> 20539 Reset value is 0x0.</td></tr> 20540 </table><p> 20541 <A HREF="#TX_COEFF_PM Registers">Return to TX_COEFF_PM: per lane register block [One Copy Per Lane] Table</A><p> 20542 <hr> 20543 <H1><a NAME="TX_COEFF_POST Registers">TX_COEFF_POST: per lane register block [One Copy Per Lane] Registers</a></H1> 20544 <table border=1 align=center width=100% cellpadding=0> 20545 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 20546 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 20547 <tr> 20548 <td align=center>0xD320</td><td><A HREF="#TX_COEFF_POST_POST_EXTENT_CTRL0">TX_COEFF_POST_POST_EXTENT_CTRL0</A><br>TX COEFF post_extent_0</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_extent_0</div> </td> <td align=center>16'h0000</td></tr> 20549 <tr> 20550 <td align=center>0xD321</td><td><A HREF="#TX_COEFF_POST_POST_EXTENT_CTRL1">TX_COEFF_POST_POST_EXTENT_CTRL1</A><br>TX COEFF post_extent_1</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_extent_1</div> </td> <td align=center>16'h0800</td></tr> 20551 <tr> 20552 <td align=center>0xD322</td><td><A HREF="#TX_COEFF_POST_POST_EXTENT_CTRL2">TX_COEFF_POST_POST_EXTENT_CTRL2</A><br>TX COEFF post_extent_2</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_extent_2</div> </td> <td align=center>16'h3000</td></tr> 20553 <tr> 20554 <td align=center>0xD323</td><td><A HREF="#TX_COEFF_POST_POST_EXTENT_CTRL3">TX_COEFF_POST_POST_EXTENT_CTRL3</A><br>TX COEFF post_extent_3</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_extent_3</div> </td> <td align=center>16'h7000</td></tr> 20555 <tr> 20556 <td align=center>0xD324</td><td><A HREF="#TX_COEFF_POST_POST_EXTENT_CTRL4">TX_COEFF_POST_POST_EXTENT_CTRL4</A><br>TX COEFF post_extent_4</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_extent_4</div> </td> <td align=center>16'h7c00</td></tr> 20557 <tr> 20558 <td align=center>0xD325</td><td><A HREF="#TX_COEFF_POST_POST_EXTENT_CTRL5">TX_COEFF_POST_POST_EXTENT_CTRL5</A><br>TX COEFF post_extent_5</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_extent_5</div> </td> <td align=center>16'h7c04</td></tr> 20559 </table><p> 20560 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 20561 <hr> 20562 <b><a NAME="TX_COEFF_POST_POST_EXTENT_CTRL0">TX_COEFF_POST_POST_EXTENT_CTRL0 - TX COEFF post_extent_0</a></b><br> 20563 Address Offset = 32'h0000_d320<br> 20564 Physical Address = 32'h0000_d320<br> 20565 Reset Value = 16'h0000<br> 20566 Access = RW (16-bit only)<br> 20567 <table border=1 align=center width=100% cellpadding=0> 20568 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20569 <tr bgcolor=WHITE> 20570 <td bgcolor=WHITE align=center valign=top>15</td> 20571 <td align=left valign=top>RSVD</td> 20572 <td align=left valign=top>Reserved</td> 20573 <td align=left> 20574 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20575 <tr bgcolor=WHITE> 20576 <td bgcolor=WHITE align=center valign=top>14:00</td> 20577 <td align=left valign=top>RW</td> 20578 <td align=left valign=top>fir_post_extent_0</td> 20579 <td align=left> 20580 tx coeff fir_post_extent_0 when pre_coefficient = 11<br> 20581 Reset value is 0x0.</td></tr> 20582 </table><p> 20583 <A HREF="#TX_COEFF_POST Registers">Return to TX_COEFF_POST: per lane register block [One Copy Per Lane] Table</A><p> 20584 <hr> 20585 <b><a NAME="TX_COEFF_POST_POST_EXTENT_CTRL1">TX_COEFF_POST_POST_EXTENT_CTRL1 - TX COEFF post_extent_1</a></b><br> 20586 Address Offset = 32'h0000_d321<br> 20587 Physical Address = 32'h0000_d321<br> 20588 Reset Value = 16'h0800<br> 20589 Access = RW (16-bit only)<br> 20590 <table border=1 align=center width=100% cellpadding=0> 20591 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20592 <tr bgcolor=WHITE> 20593 <td bgcolor=WHITE align=center valign=top>15</td> 20594 <td align=left valign=top>RSVD</td> 20595 <td align=left valign=top>Reserved</td> 20596 <td align=left> 20597 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20598 <tr bgcolor=WHITE> 20599 <td bgcolor=WHITE align=center valign=top>14:00</td> 20600 <td align=left valign=top>RW</td> 20601 <td align=left valign=top>fir_post_extent_1</td> 20602 <td align=left> 20603 tx coeff fir_post_extent_1 when pre_coefficient = 11<br> 20604 Reset value is 0x800.</td></tr> 20605 </table><p> 20606 <A HREF="#TX_COEFF_POST Registers">Return to TX_COEFF_POST: per lane register block [One Copy Per Lane] Table</A><p> 20607 <hr> 20608 <b><a NAME="TX_COEFF_POST_POST_EXTENT_CTRL2">TX_COEFF_POST_POST_EXTENT_CTRL2 - TX COEFF post_extent_2</a></b><br> 20609 Address Offset = 32'h0000_d322<br> 20610 Physical Address = 32'h0000_d322<br> 20611 Reset Value = 16'h3000<br> 20612 Access = RW (16-bit only)<br> 20613 <table border=1 align=center width=100% cellpadding=0> 20614 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20615 <tr bgcolor=WHITE> 20616 <td bgcolor=WHITE align=center valign=top>15</td> 20617 <td align=left valign=top>RSVD</td> 20618 <td align=left valign=top>Reserved</td> 20619 <td align=left> 20620 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20621 <tr bgcolor=WHITE> 20622 <td bgcolor=WHITE align=center valign=top>14:00</td> 20623 <td align=left valign=top>RW</td> 20624 <td align=left valign=top>fir_post_extent_2</td> 20625 <td align=left> 20626 tx coeff fir_post_extent_2 when pre_coefficient = 12<br> 20627 Reset value is 0x3000.</td></tr> 20628 </table><p> 20629 <A HREF="#TX_COEFF_POST Registers">Return to TX_COEFF_POST: per lane register block [One Copy Per Lane] Table</A><p> 20630 <hr> 20631 <b><a NAME="TX_COEFF_POST_POST_EXTENT_CTRL3">TX_COEFF_POST_POST_EXTENT_CTRL3 - TX COEFF post_extent_3</a></b><br> 20632 Address Offset = 32'h0000_d323<br> 20633 Physical Address = 32'h0000_d323<br> 20634 Reset Value = 16'h7000<br> 20635 Access = RW (16-bit only)<br> 20636 <table border=1 align=center width=100% cellpadding=0> 20637 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20638 <tr bgcolor=WHITE> 20639 <td bgcolor=WHITE align=center valign=top>15</td> 20640 <td align=left valign=top>RSVD</td> 20641 <td align=left valign=top>Reserved</td> 20642 <td align=left> 20643 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20644 <tr bgcolor=WHITE> 20645 <td bgcolor=WHITE align=center valign=top>14:00</td> 20646 <td align=left valign=top>RW</td> 20647 <td align=left valign=top>fir_post_extent_3</td> 20648 <td align=left> 20649 tx coeff fir_post_extent_3 when pre_coefficient = 13<br> 20650 Reset value is 0x7000.</td></tr> 20651 </table><p> 20652 <A HREF="#TX_COEFF_POST Registers">Return to TX_COEFF_POST: per lane register block [One Copy Per Lane] Table</A><p> 20653 <hr> 20654 <b><a NAME="TX_COEFF_POST_POST_EXTENT_CTRL4">TX_COEFF_POST_POST_EXTENT_CTRL4 - TX COEFF post_extent_4</a></b><br> 20655 Address Offset = 32'h0000_d324<br> 20656 Physical Address = 32'h0000_d324<br> 20657 Reset Value = 16'h7c00<br> 20658 Access = RW (16-bit only)<br> 20659 <table border=1 align=center width=100% cellpadding=0> 20660 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20661 <tr bgcolor=WHITE> 20662 <td bgcolor=WHITE align=center valign=top>15</td> 20663 <td align=left valign=top>RSVD</td> 20664 <td align=left valign=top>Reserved</td> 20665 <td align=left> 20666 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20667 <tr bgcolor=WHITE> 20668 <td bgcolor=WHITE align=center valign=top>14:00</td> 20669 <td align=left valign=top>RW</td> 20670 <td align=left valign=top>fir_post_extent_4</td> 20671 <td align=left> 20672 tx coeff fir_post_extent_4 when pre_coefficient = 14<br> 20673 Reset value is 0x7c00.</td></tr> 20674 </table><p> 20675 <A HREF="#TX_COEFF_POST Registers">Return to TX_COEFF_POST: per lane register block [One Copy Per Lane] Table</A><p> 20676 <hr> 20677 <b><a NAME="TX_COEFF_POST_POST_EXTENT_CTRL5">TX_COEFF_POST_POST_EXTENT_CTRL5 - TX COEFF post_extent_5</a></b><br> 20678 Address Offset = 32'h0000_d325<br> 20679 Physical Address = 32'h0000_d325<br> 20680 Reset Value = 16'h7c04<br> 20681 Access = RW (16-bit only)<br> 20682 <table border=1 align=center width=100% cellpadding=0> 20683 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20684 <tr bgcolor=WHITE> 20685 <td bgcolor=WHITE align=center valign=top>15</td> 20686 <td align=left valign=top>RSVD</td> 20687 <td align=left valign=top>Reserved</td> 20688 <td align=left> 20689 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20690 <tr bgcolor=WHITE> 20691 <td bgcolor=WHITE align=center valign=top>14:00</td> 20692 <td align=left valign=top>RW</td> 20693 <td align=left valign=top>fir_post_extent_5</td> 20694 <td align=left> 20695 tx coeff fir_post_extent_5 when pre_coefficient = 15<br> 20696 Reset value is 0x7c04.</td></tr> 20697 </table><p> 20698 <A HREF="#TX_COEFF_POST Registers">Return to TX_COEFF_POST: per lane register block [One Copy Per Lane] Table</A><p> 20699 <hr> 20700 <H1><a NAME="TX_COEFF_POSTA Registers">TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Registers</a></H1> 20701 <table border=1 align=center width=100% cellpadding=0> 20702 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 20703 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 20704 <tr> 20705 <td align=center>0xD330</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL0">TX_COEFF_POSTA_POST_CTRL0</A><br>TX COEFF FIR_POST Register: R0</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_0</div> </td> <td align=center>16'h0000</td></tr> 20706 <tr> 20707 <td align=center>0xD331</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL1">TX_COEFF_POSTA_POST_CTRL1</A><br>TX COEFF FIR_POST Register: R1</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_1</div> </td> <td align=center>16'h0020</td></tr> 20708 <tr> 20709 <td align=center>0xD332</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL2">TX_COEFF_POSTA_POST_CTRL2</A><br>TX COEFF FIR_POST Register: R2</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_2</div> </td> <td align=center>16'h0030</td></tr> 20710 <tr> 20711 <td align=center>0xD333</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL3">TX_COEFF_POSTA_POST_CTRL3</A><br>TX COEFF FIR_POST Register: R3</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_3</div> </td> <td align=center>16'h0220</td></tr> 20712 <tr> 20713 <td align=center>0xD334</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL4">TX_COEFF_POSTA_POST_CTRL4</A><br>TX COEFF FIR_POST Register: R4</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_4</div> </td> <td align=center>16'h0230</td></tr> 20714 <tr> 20715 <td align=center>0xD335</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL5">TX_COEFF_POSTA_POST_CTRL5</A><br>TX COEFF FIR_POST Register: R5</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_5</div> </td> <td align=center>16'h0320</td></tr> 20716 <tr> 20717 <td align=center>0xD336</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL6">TX_COEFF_POSTA_POST_CTRL6</A><br>TX COEFF FIR_POST Register: R6</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_6</div> </td> <td align=center>16'h0330</td></tr> 20718 <tr> 20719 <td align=center>0xD337</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL7">TX_COEFF_POSTA_POST_CTRL7</A><br>TX COEFF FIR_POST Register: R7</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_7</div> </td> <td align=center>16'h03a0</td></tr> 20720 <tr> 20721 <td align=center>0xD338</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL8">TX_COEFF_POSTA_POST_CTRL8</A><br>TX COEFF FIR_POST Register: R8</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_8</div> </td> <td align=center>16'h03b0</td></tr> 20722 <tr> 20723 <td align=center>0xD339</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL9">TX_COEFF_POSTA_POST_CTRL9</A><br>TX COEFF FIR_POST Register: R9</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_9</div> </td> <td align=center>16'h03e0</td></tr> 20724 <tr> 20725 <td align=center>0xD33A</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL10">TX_COEFF_POSTA_POST_CTRL10</A><br>TX COEFF FIR_POST Register: R10</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_10</div> </td> <td align=center>16'h03f0</td></tr> 20726 <tr> 20727 <td align=center>0xD33B</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL11">TX_COEFF_POSTA_POST_CTRL11</A><br>TX COEFF FIR_POST Register: R11</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_11</div> </td> <td align=center>16'h07f0</td></tr> 20728 <tr> 20729 <td align=center>0xD33C</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL12">TX_COEFF_POSTA_POST_CTRL12</A><br>TX COEFF FIR_POST Register: R12</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_12</div> </td> <td align=center>16'h13f0</td></tr> 20730 <tr> 20731 <td align=center>0xD33D</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL13">TX_COEFF_POSTA_POST_CTRL13</A><br>TX COEFF FIR_POST Register: R13</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_13</div> </td> <td align=center>16'h17f0</td></tr> 20732 <tr> 20733 <td align=center>0xD33E</td><td><A HREF="#TX_COEFF_POSTA_POST_CTRL14">TX_COEFF_POSTA_POST_CTRL14</A><br>TX COEFF FIR_POST Register: R14</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_14</div> </td> <td align=center>16'h33f0</td></tr> 20734 </table><p> 20735 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 20736 <hr> 20737 <b><a NAME="TX_COEFF_POSTA_POST_CTRL0">TX_COEFF_POSTA_POST_CTRL0 - TX COEFF FIR_POST Register: R0</a></b><br> 20738 Address Offset = 32'h0000_d330<br> 20739 Physical Address = 32'h0000_d330<br> 20740 Reset Value = 16'h0000<br> 20741 Access = RW (16-bit only)<br> 20742 <table border=1 align=center width=100% cellpadding=0> 20743 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20744 <tr bgcolor=WHITE> 20745 <td bgcolor=WHITE align=center valign=top>15</td> 20746 <td align=left valign=top>RSVD</td> 20747 <td align=left valign=top>Reserved</td> 20748 <td align=left> 20749 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20750 <tr bgcolor=WHITE> 20751 <td bgcolor=WHITE align=center valign=top>14:00</td> 20752 <td align=left valign=top>RW</td> 20753 <td align=left valign=top>fir_post_0</td> 20754 <td align=left> 20755 tx coeff fir_post_0 <br> 20756 Reset value is 0x0.</td></tr> 20757 </table><p> 20758 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20759 <hr> 20760 <b><a NAME="TX_COEFF_POSTA_POST_CTRL1">TX_COEFF_POSTA_POST_CTRL1 - TX COEFF FIR_POST Register: R1</a></b><br> 20761 Address Offset = 32'h0000_d331<br> 20762 Physical Address = 32'h0000_d331<br> 20763 Reset Value = 16'h0020<br> 20764 Access = RW (16-bit only)<br> 20765 <table border=1 align=center width=100% cellpadding=0> 20766 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20767 <tr bgcolor=WHITE> 20768 <td bgcolor=WHITE align=center valign=top>15</td> 20769 <td align=left valign=top>RSVD</td> 20770 <td align=left valign=top>Reserved</td> 20771 <td align=left> 20772 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20773 <tr bgcolor=WHITE> 20774 <td bgcolor=WHITE align=center valign=top>14:00</td> 20775 <td align=left valign=top>RW</td> 20776 <td align=left valign=top>fir_post_1</td> 20777 <td align=left> 20778 tx coeff fir_post_1 <br> 20779 Reset value is 0x20.</td></tr> 20780 </table><p> 20781 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20782 <hr> 20783 <b><a NAME="TX_COEFF_POSTA_POST_CTRL2">TX_COEFF_POSTA_POST_CTRL2 - TX COEFF FIR_POST Register: R2</a></b><br> 20784 Address Offset = 32'h0000_d332<br> 20785 Physical Address = 32'h0000_d332<br> 20786 Reset Value = 16'h0030<br> 20787 Access = RW (16-bit only)<br> 20788 <table border=1 align=center width=100% cellpadding=0> 20789 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20790 <tr bgcolor=WHITE> 20791 <td bgcolor=WHITE align=center valign=top>15</td> 20792 <td align=left valign=top>RSVD</td> 20793 <td align=left valign=top>Reserved</td> 20794 <td align=left> 20795 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20796 <tr bgcolor=WHITE> 20797 <td bgcolor=WHITE align=center valign=top>14:00</td> 20798 <td align=left valign=top>RW</td> 20799 <td align=left valign=top>fir_post_2</td> 20800 <td align=left> 20801 tx coeff fir_post_2 <br> 20802 Reset value is 0x30.</td></tr> 20803 </table><p> 20804 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20805 <hr> 20806 <b><a NAME="TX_COEFF_POSTA_POST_CTRL3">TX_COEFF_POSTA_POST_CTRL3 - TX COEFF FIR_POST Register: R3</a></b><br> 20807 Address Offset = 32'h0000_d333<br> 20808 Physical Address = 32'h0000_d333<br> 20809 Reset Value = 16'h0220<br> 20810 Access = RW (16-bit only)<br> 20811 <table border=1 align=center width=100% cellpadding=0> 20812 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20813 <tr bgcolor=WHITE> 20814 <td bgcolor=WHITE align=center valign=top>15</td> 20815 <td align=left valign=top>RSVD</td> 20816 <td align=left valign=top>Reserved</td> 20817 <td align=left> 20818 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20819 <tr bgcolor=WHITE> 20820 <td bgcolor=WHITE align=center valign=top>14:00</td> 20821 <td align=left valign=top>RW</td> 20822 <td align=left valign=top>fir_post_3</td> 20823 <td align=left> 20824 tx coeff fir_post_3 <br> 20825 Reset value is 0x220.</td></tr> 20826 </table><p> 20827 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20828 <hr> 20829 <b><a NAME="TX_COEFF_POSTA_POST_CTRL4">TX_COEFF_POSTA_POST_CTRL4 - TX COEFF FIR_POST Register: R4</a></b><br> 20830 Address Offset = 32'h0000_d334<br> 20831 Physical Address = 32'h0000_d334<br> 20832 Reset Value = 16'h0230<br> 20833 Access = RW (16-bit only)<br> 20834 <table border=1 align=center width=100% cellpadding=0> 20835 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20836 <tr bgcolor=WHITE> 20837 <td bgcolor=WHITE align=center valign=top>15</td> 20838 <td align=left valign=top>RSVD</td> 20839 <td align=left valign=top>Reserved</td> 20840 <td align=left> 20841 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20842 <tr bgcolor=WHITE> 20843 <td bgcolor=WHITE align=center valign=top>14:00</td> 20844 <td align=left valign=top>RW</td> 20845 <td align=left valign=top>fir_post_4</td> 20846 <td align=left> 20847 tx coeff fir_post_4 <br> 20848 Reset value is 0x230.</td></tr> 20849 </table><p> 20850 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20851 <hr> 20852 <b><a NAME="TX_COEFF_POSTA_POST_CTRL5">TX_COEFF_POSTA_POST_CTRL5 - TX COEFF FIR_POST Register: R5</a></b><br> 20853 Address Offset = 32'h0000_d335<br> 20854 Physical Address = 32'h0000_d335<br> 20855 Reset Value = 16'h0320<br> 20856 Access = RW (16-bit only)<br> 20857 <table border=1 align=center width=100% cellpadding=0> 20858 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20859 <tr bgcolor=WHITE> 20860 <td bgcolor=WHITE align=center valign=top>15</td> 20861 <td align=left valign=top>RSVD</td> 20862 <td align=left valign=top>Reserved</td> 20863 <td align=left> 20864 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20865 <tr bgcolor=WHITE> 20866 <td bgcolor=WHITE align=center valign=top>14:00</td> 20867 <td align=left valign=top>RW</td> 20868 <td align=left valign=top>fir_post_5</td> 20869 <td align=left> 20870 tx coeff fir_post_5 <br> 20871 Reset value is 0x320.</td></tr> 20872 </table><p> 20873 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20874 <hr> 20875 <b><a NAME="TX_COEFF_POSTA_POST_CTRL6">TX_COEFF_POSTA_POST_CTRL6 - TX COEFF FIR_POST Register: R6</a></b><br> 20876 Address Offset = 32'h0000_d336<br> 20877 Physical Address = 32'h0000_d336<br> 20878 Reset Value = 16'h0330<br> 20879 Access = RW (16-bit only)<br> 20880 <table border=1 align=center width=100% cellpadding=0> 20881 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20882 <tr bgcolor=WHITE> 20883 <td bgcolor=WHITE align=center valign=top>15</td> 20884 <td align=left valign=top>RSVD</td> 20885 <td align=left valign=top>Reserved</td> 20886 <td align=left> 20887 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20888 <tr bgcolor=WHITE> 20889 <td bgcolor=WHITE align=center valign=top>14:00</td> 20890 <td align=left valign=top>RW</td> 20891 <td align=left valign=top>fir_post_6</td> 20892 <td align=left> 20893 tx coeff fir_post_6 <br> 20894 Reset value is 0x330.</td></tr> 20895 </table><p> 20896 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20897 <hr> 20898 <b><a NAME="TX_COEFF_POSTA_POST_CTRL7">TX_COEFF_POSTA_POST_CTRL7 - TX COEFF FIR_POST Register: R7</a></b><br> 20899 Address Offset = 32'h0000_d337<br> 20900 Physical Address = 32'h0000_d337<br> 20901 Reset Value = 16'h03a0<br> 20902 Access = RW (16-bit only)<br> 20903 <table border=1 align=center width=100% cellpadding=0> 20904 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20905 <tr bgcolor=WHITE> 20906 <td bgcolor=WHITE align=center valign=top>15</td> 20907 <td align=left valign=top>RSVD</td> 20908 <td align=left valign=top>Reserved</td> 20909 <td align=left> 20910 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20911 <tr bgcolor=WHITE> 20912 <td bgcolor=WHITE align=center valign=top>14:00</td> 20913 <td align=left valign=top>RW</td> 20914 <td align=left valign=top>fir_post_7</td> 20915 <td align=left> 20916 tx coeff fir_post_7 <br> 20917 Reset value is 0x3a0.</td></tr> 20918 </table><p> 20919 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20920 <hr> 20921 <b><a NAME="TX_COEFF_POSTA_POST_CTRL8">TX_COEFF_POSTA_POST_CTRL8 - TX COEFF FIR_POST Register: R8</a></b><br> 20922 Address Offset = 32'h0000_d338<br> 20923 Physical Address = 32'h0000_d338<br> 20924 Reset Value = 16'h03b0<br> 20925 Access = RW (16-bit only)<br> 20926 <table border=1 align=center width=100% cellpadding=0> 20927 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20928 <tr bgcolor=WHITE> 20929 <td bgcolor=WHITE align=center valign=top>15</td> 20930 <td align=left valign=top>RSVD</td> 20931 <td align=left valign=top>Reserved</td> 20932 <td align=left> 20933 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20934 <tr bgcolor=WHITE> 20935 <td bgcolor=WHITE align=center valign=top>14:00</td> 20936 <td align=left valign=top>RW</td> 20937 <td align=left valign=top>fir_post_8</td> 20938 <td align=left> 20939 tx coeff fir_post_8 <br> 20940 Reset value is 0x3b0.</td></tr> 20941 </table><p> 20942 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20943 <hr> 20944 <b><a NAME="TX_COEFF_POSTA_POST_CTRL9">TX_COEFF_POSTA_POST_CTRL9 - TX COEFF FIR_POST Register: R9</a></b><br> 20945 Address Offset = 32'h0000_d339<br> 20946 Physical Address = 32'h0000_d339<br> 20947 Reset Value = 16'h03e0<br> 20948 Access = RW (16-bit only)<br> 20949 <table border=1 align=center width=100% cellpadding=0> 20950 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20951 <tr bgcolor=WHITE> 20952 <td bgcolor=WHITE align=center valign=top>15</td> 20953 <td align=left valign=top>RSVD</td> 20954 <td align=left valign=top>Reserved</td> 20955 <td align=left> 20956 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20957 <tr bgcolor=WHITE> 20958 <td bgcolor=WHITE align=center valign=top>14:00</td> 20959 <td align=left valign=top>RW</td> 20960 <td align=left valign=top>fir_post_9</td> 20961 <td align=left> 20962 tx coeff fir_post_9 <br> 20963 Reset value is 0x3e0.</td></tr> 20964 </table><p> 20965 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20966 <hr> 20967 <b><a NAME="TX_COEFF_POSTA_POST_CTRL10">TX_COEFF_POSTA_POST_CTRL10 - TX COEFF FIR_POST Register: R10</a></b><br> 20968 Address Offset = 32'h0000_d33a<br> 20969 Physical Address = 32'h0000_d33a<br> 20970 Reset Value = 16'h03f0<br> 20971 Access = RW (16-bit only)<br> 20972 <table border=1 align=center width=100% cellpadding=0> 20973 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20974 <tr bgcolor=WHITE> 20975 <td bgcolor=WHITE align=center valign=top>15</td> 20976 <td align=left valign=top>RSVD</td> 20977 <td align=left valign=top>Reserved</td> 20978 <td align=left> 20979 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 20980 <tr bgcolor=WHITE> 20981 <td bgcolor=WHITE align=center valign=top>14:00</td> 20982 <td align=left valign=top>RW</td> 20983 <td align=left valign=top>fir_post_10</td> 20984 <td align=left> 20985 tx coeff fir_post_10 <br> 20986 Reset value is 0x3f0.</td></tr> 20987 </table><p> 20988 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 20989 <hr> 20990 <b><a NAME="TX_COEFF_POSTA_POST_CTRL11">TX_COEFF_POSTA_POST_CTRL11 - TX COEFF FIR_POST Register: R11</a></b><br> 20991 Address Offset = 32'h0000_d33b<br> 20992 Physical Address = 32'h0000_d33b<br> 20993 Reset Value = 16'h07f0<br> 20994 Access = RW (16-bit only)<br> 20995 <table border=1 align=center width=100% cellpadding=0> 20996 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 20997 <tr bgcolor=WHITE> 20998 <td bgcolor=WHITE align=center valign=top>15</td> 20999 <td align=left valign=top>RSVD</td> 21000 <td align=left valign=top>Reserved</td> 21001 <td align=left> 21002 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21003 <tr bgcolor=WHITE> 21004 <td bgcolor=WHITE align=center valign=top>14:00</td> 21005 <td align=left valign=top>RW</td> 21006 <td align=left valign=top>fir_post_11</td> 21007 <td align=left> 21008 tx coeff fir_post_11 <br> 21009 Reset value is 0x7f0.</td></tr> 21010 </table><p> 21011 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 21012 <hr> 21013 <b><a NAME="TX_COEFF_POSTA_POST_CTRL12">TX_COEFF_POSTA_POST_CTRL12 - TX COEFF FIR_POST Register: R12</a></b><br> 21014 Address Offset = 32'h0000_d33c<br> 21015 Physical Address = 32'h0000_d33c<br> 21016 Reset Value = 16'h13f0<br> 21017 Access = RW (16-bit only)<br> 21018 <table border=1 align=center width=100% cellpadding=0> 21019 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21020 <tr bgcolor=WHITE> 21021 <td bgcolor=WHITE align=center valign=top>15</td> 21022 <td align=left valign=top>RSVD</td> 21023 <td align=left valign=top>Reserved</td> 21024 <td align=left> 21025 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21026 <tr bgcolor=WHITE> 21027 <td bgcolor=WHITE align=center valign=top>14:00</td> 21028 <td align=left valign=top>RW</td> 21029 <td align=left valign=top>fir_post_12</td> 21030 <td align=left> 21031 tx coeff fir_post_12 <br> 21032 Reset value is 0x13f0.</td></tr> 21033 </table><p> 21034 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 21035 <hr> 21036 <b><a NAME="TX_COEFF_POSTA_POST_CTRL13">TX_COEFF_POSTA_POST_CTRL13 - TX COEFF FIR_POST Register: R13</a></b><br> 21037 Address Offset = 32'h0000_d33d<br> 21038 Physical Address = 32'h0000_d33d<br> 21039 Reset Value = 16'h17f0<br> 21040 Access = RW (16-bit only)<br> 21041 <table border=1 align=center width=100% cellpadding=0> 21042 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21043 <tr bgcolor=WHITE> 21044 <td bgcolor=WHITE align=center valign=top>15</td> 21045 <td align=left valign=top>RSVD</td> 21046 <td align=left valign=top>Reserved</td> 21047 <td align=left> 21048 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21049 <tr bgcolor=WHITE> 21050 <td bgcolor=WHITE align=center valign=top>14:00</td> 21051 <td align=left valign=top>RW</td> 21052 <td align=left valign=top>fir_post_13</td> 21053 <td align=left> 21054 tx coeff fir_post_13 <br> 21055 Reset value is 0x17f0.</td></tr> 21056 </table><p> 21057 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 21058 <hr> 21059 <b><a NAME="TX_COEFF_POSTA_POST_CTRL14">TX_COEFF_POSTA_POST_CTRL14 - TX COEFF FIR_POST Register: R14</a></b><br> 21060 Address Offset = 32'h0000_d33e<br> 21061 Physical Address = 32'h0000_d33e<br> 21062 Reset Value = 16'h33f0<br> 21063 Access = RW (16-bit only)<br> 21064 <table border=1 align=center width=100% cellpadding=0> 21065 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21066 <tr bgcolor=WHITE> 21067 <td bgcolor=WHITE align=center valign=top>15</td> 21068 <td align=left valign=top>RSVD</td> 21069 <td align=left valign=top>Reserved</td> 21070 <td align=left> 21071 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21072 <tr bgcolor=WHITE> 21073 <td bgcolor=WHITE align=center valign=top>14:00</td> 21074 <td align=left valign=top>RW</td> 21075 <td align=left valign=top>fir_post_14</td> 21076 <td align=left> 21077 tx coeff fir_post_14 <br> 21078 Reset value is 0x33f0.</td></tr> 21079 </table><p> 21080 <A HREF="#TX_COEFF_POSTA Registers">Return to TX_COEFF_POSTA: per lane register block [One Copy Per Lane] Table</A><p> 21081 <hr> 21082 <H1><a NAME="TX_COEFF_POSTB Registers">TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Registers</a></H1> 21083 <table border=1 align=center width=100% cellpadding=0> 21084 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 21085 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 21086 <tr> 21087 <td align=center>0xD340</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL15">TX_COEFF_POSTB_POST_CTRL15</A><br>TX COEFF FIR_POST Register: R15</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_15</div> </td> <td align=center>16'h37f0</td></tr> 21088 <tr> 21089 <td align=center>0xD341</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL16">TX_COEFF_POSTB_POST_CTRL16</A><br>TX COEFF FIR_POST Register: R16</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_16</div> </td> <td align=center>16'h73f0</td></tr> 21090 <tr> 21091 <td align=center>0xD342</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL17">TX_COEFF_POSTB_POST_CTRL17</A><br>TX COEFF FIR_POST Register: R17</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_17</div> </td> <td align=center>16'h77f0</td></tr> 21092 <tr> 21093 <td align=center>0xD343</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL18">TX_COEFF_POSTB_POST_CTRL18</A><br>TX COEFF FIR_POST Register: R18</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_18</div> </td> <td align=center>16'h7ff0</td></tr> 21094 <tr> 21095 <td align=center>0xD344</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL19">TX_COEFF_POSTB_POST_CTRL19</A><br>TX COEFF FIR_POST Register: R19</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_19</div> </td> <td align=center>16'h7ff1</td></tr> 21096 <tr> 21097 <td align=center>0xD345</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL20">TX_COEFF_POSTB_POST_CTRL20</A><br>TX COEFF FIR_POST Register: R20</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_20</div> </td> <td align=center>16'h7ff4</td></tr> 21098 <tr> 21099 <td align=center>0xD346</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL21">TX_COEFF_POSTB_POST_CTRL21</A><br>TX COEFF FIR_POST Register: R21</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_21</div> </td> <td align=center>16'h7ff5</td></tr> 21100 <tr> 21101 <td align=center>0xD347</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL22">TX_COEFF_POSTB_POST_CTRL22</A><br>TX COEFF FIR_POST Register: R22</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_22</div> </td> <td align=center>16'h7ffc</td></tr> 21102 <tr> 21103 <td align=center>0xD348</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL23">TX_COEFF_POSTB_POST_CTRL23</A><br>TX COEFF FIR_POST Register: R23</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_23</div> </td> <td align=center>16'h7ffd</td></tr> 21104 <tr> 21105 <td align=center>0xD349</td><td><A HREF="#TX_COEFF_POSTB_POST_CTRL24">TX_COEFF_POSTB_POST_CTRL24</A><br>TX COEFF FIR_POST Register: R24</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="15"><div class="HT">fir_post_24</div> </td> <td align=center>16'h7fff</td></tr> 21106 <tr> 21107 <td align=center>0xD34A</td><td><A HREF="#TX_COEFF_POSTB_REG_PRE_POST_CTRL">TX_COEFF_POSTB_REG_PRE_POST_CTRL</A><br>TX FIR REG_PRE_POST1PRE_DEFAULT & REG_POST1_POST1PRE_DEFAULT Register</td><td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">post1_post1pre_default</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">pre_post1pre_default</div> </td> <td align=center>16'h0000</td></tr> 21108 </table><p> 21109 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 21110 <hr> 21111 <b><a NAME="TX_COEFF_POSTB_POST_CTRL15">TX_COEFF_POSTB_POST_CTRL15 - TX COEFF FIR_POST Register: R15</a></b><br> 21112 Address Offset = 32'h0000_d340<br> 21113 Physical Address = 32'h0000_d340<br> 21114 Reset Value = 16'h37f0<br> 21115 Access = RW (16-bit only)<br> 21116 <table border=1 align=center width=100% cellpadding=0> 21117 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21118 <tr bgcolor=WHITE> 21119 <td bgcolor=WHITE align=center valign=top>15</td> 21120 <td align=left valign=top>RSVD</td> 21121 <td align=left valign=top>Reserved</td> 21122 <td align=left> 21123 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21124 <tr bgcolor=WHITE> 21125 <td bgcolor=WHITE align=center valign=top>14:00</td> 21126 <td align=left valign=top>RW</td> 21127 <td align=left valign=top>fir_post_15</td> 21128 <td align=left> 21129 tx coeff fir_post_15 <br> 21130 Reset value is 0x37f0.</td></tr> 21131 </table><p> 21132 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21133 <hr> 21134 <b><a NAME="TX_COEFF_POSTB_POST_CTRL16">TX_COEFF_POSTB_POST_CTRL16 - TX COEFF FIR_POST Register: R16</a></b><br> 21135 Address Offset = 32'h0000_d341<br> 21136 Physical Address = 32'h0000_d341<br> 21137 Reset Value = 16'h73f0<br> 21138 Access = RW (16-bit only)<br> 21139 <table border=1 align=center width=100% cellpadding=0> 21140 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21141 <tr bgcolor=WHITE> 21142 <td bgcolor=WHITE align=center valign=top>15</td> 21143 <td align=left valign=top>RSVD</td> 21144 <td align=left valign=top>Reserved</td> 21145 <td align=left> 21146 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21147 <tr bgcolor=WHITE> 21148 <td bgcolor=WHITE align=center valign=top>14:00</td> 21149 <td align=left valign=top>RW</td> 21150 <td align=left valign=top>fir_post_16</td> 21151 <td align=left> 21152 tx coeff fir_post_16 <br> 21153 Reset value is 0x73f0.</td></tr> 21154 </table><p> 21155 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21156 <hr> 21157 <b><a NAME="TX_COEFF_POSTB_POST_CTRL17">TX_COEFF_POSTB_POST_CTRL17 - TX COEFF FIR_POST Register: R17</a></b><br> 21158 Address Offset = 32'h0000_d342<br> 21159 Physical Address = 32'h0000_d342<br> 21160 Reset Value = 16'h77f0<br> 21161 Access = RW (16-bit only)<br> 21162 <table border=1 align=center width=100% cellpadding=0> 21163 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21164 <tr bgcolor=WHITE> 21165 <td bgcolor=WHITE align=center valign=top>15</td> 21166 <td align=left valign=top>RSVD</td> 21167 <td align=left valign=top>Reserved</td> 21168 <td align=left> 21169 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21170 <tr bgcolor=WHITE> 21171 <td bgcolor=WHITE align=center valign=top>14:00</td> 21172 <td align=left valign=top>RW</td> 21173 <td align=left valign=top>fir_post_17</td> 21174 <td align=left> 21175 tx coeff fir_post_17 <br> 21176 Reset value is 0x77f0.</td></tr> 21177 </table><p> 21178 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21179 <hr> 21180 <b><a NAME="TX_COEFF_POSTB_POST_CTRL18">TX_COEFF_POSTB_POST_CTRL18 - TX COEFF FIR_POST Register: R18</a></b><br> 21181 Address Offset = 32'h0000_d343<br> 21182 Physical Address = 32'h0000_d343<br> 21183 Reset Value = 16'h7ff0<br> 21184 Access = RW (16-bit only)<br> 21185 <table border=1 align=center width=100% cellpadding=0> 21186 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21187 <tr bgcolor=WHITE> 21188 <td bgcolor=WHITE align=center valign=top>15</td> 21189 <td align=left valign=top>RSVD</td> 21190 <td align=left valign=top>Reserved</td> 21191 <td align=left> 21192 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21193 <tr bgcolor=WHITE> 21194 <td bgcolor=WHITE align=center valign=top>14:00</td> 21195 <td align=left valign=top>RW</td> 21196 <td align=left valign=top>fir_post_18</td> 21197 <td align=left> 21198 tx coeff fir_post_18 <br> 21199 Reset value is 0x7ff0.</td></tr> 21200 </table><p> 21201 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21202 <hr> 21203 <b><a NAME="TX_COEFF_POSTB_POST_CTRL19">TX_COEFF_POSTB_POST_CTRL19 - TX COEFF FIR_POST Register: R19</a></b><br> 21204 Address Offset = 32'h0000_d344<br> 21205 Physical Address = 32'h0000_d344<br> 21206 Reset Value = 16'h7ff1<br> 21207 Access = RW (16-bit only)<br> 21208 <table border=1 align=center width=100% cellpadding=0> 21209 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21210 <tr bgcolor=WHITE> 21211 <td bgcolor=WHITE align=center valign=top>15</td> 21212 <td align=left valign=top>RSVD</td> 21213 <td align=left valign=top>Reserved</td> 21214 <td align=left> 21215 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21216 <tr bgcolor=WHITE> 21217 <td bgcolor=WHITE align=center valign=top>14:00</td> 21218 <td align=left valign=top>RW</td> 21219 <td align=left valign=top>fir_post_19</td> 21220 <td align=left> 21221 tx coeff fir_post_19 <br> 21222 Reset value is 0x7ff1.</td></tr> 21223 </table><p> 21224 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21225 <hr> 21226 <b><a NAME="TX_COEFF_POSTB_POST_CTRL20">TX_COEFF_POSTB_POST_CTRL20 - TX COEFF FIR_POST Register: R20</a></b><br> 21227 Address Offset = 32'h0000_d345<br> 21228 Physical Address = 32'h0000_d345<br> 21229 Reset Value = 16'h7ff4<br> 21230 Access = RW (16-bit only)<br> 21231 <table border=1 align=center width=100% cellpadding=0> 21232 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21233 <tr bgcolor=WHITE> 21234 <td bgcolor=WHITE align=center valign=top>15</td> 21235 <td align=left valign=top>RSVD</td> 21236 <td align=left valign=top>Reserved</td> 21237 <td align=left> 21238 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21239 <tr bgcolor=WHITE> 21240 <td bgcolor=WHITE align=center valign=top>14:00</td> 21241 <td align=left valign=top>RW</td> 21242 <td align=left valign=top>fir_post_20</td> 21243 <td align=left> 21244 tx coeff fir_post_20 <br> 21245 Reset value is 0x7ff4.</td></tr> 21246 </table><p> 21247 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21248 <hr> 21249 <b><a NAME="TX_COEFF_POSTB_POST_CTRL21">TX_COEFF_POSTB_POST_CTRL21 - TX COEFF FIR_POST Register: R21</a></b><br> 21250 Address Offset = 32'h0000_d346<br> 21251 Physical Address = 32'h0000_d346<br> 21252 Reset Value = 16'h7ff5<br> 21253 Access = RW (16-bit only)<br> 21254 <table border=1 align=center width=100% cellpadding=0> 21255 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21256 <tr bgcolor=WHITE> 21257 <td bgcolor=WHITE align=center valign=top>15</td> 21258 <td align=left valign=top>RSVD</td> 21259 <td align=left valign=top>Reserved</td> 21260 <td align=left> 21261 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21262 <tr bgcolor=WHITE> 21263 <td bgcolor=WHITE align=center valign=top>14:00</td> 21264 <td align=left valign=top>RW</td> 21265 <td align=left valign=top>fir_post_21</td> 21266 <td align=left> 21267 tx coeff fir_post_21 <br> 21268 Reset value is 0x7ff5.</td></tr> 21269 </table><p> 21270 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21271 <hr> 21272 <b><a NAME="TX_COEFF_POSTB_POST_CTRL22">TX_COEFF_POSTB_POST_CTRL22 - TX COEFF FIR_POST Register: R22</a></b><br> 21273 Address Offset = 32'h0000_d347<br> 21274 Physical Address = 32'h0000_d347<br> 21275 Reset Value = 16'h7ffc<br> 21276 Access = RW (16-bit only)<br> 21277 <table border=1 align=center width=100% cellpadding=0> 21278 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21279 <tr bgcolor=WHITE> 21280 <td bgcolor=WHITE align=center valign=top>15</td> 21281 <td align=left valign=top>RSVD</td> 21282 <td align=left valign=top>Reserved</td> 21283 <td align=left> 21284 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21285 <tr bgcolor=WHITE> 21286 <td bgcolor=WHITE align=center valign=top>14:00</td> 21287 <td align=left valign=top>RW</td> 21288 <td align=left valign=top>fir_post_22</td> 21289 <td align=left> 21290 tx coeff fir_post_22 <br> 21291 Reset value is 0x7ffc.</td></tr> 21292 </table><p> 21293 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21294 <hr> 21295 <b><a NAME="TX_COEFF_POSTB_POST_CTRL23">TX_COEFF_POSTB_POST_CTRL23 - TX COEFF FIR_POST Register: R23</a></b><br> 21296 Address Offset = 32'h0000_d348<br> 21297 Physical Address = 32'h0000_d348<br> 21298 Reset Value = 16'h7ffd<br> 21299 Access = RW (16-bit only)<br> 21300 <table border=1 align=center width=100% cellpadding=0> 21301 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21302 <tr bgcolor=WHITE> 21303 <td bgcolor=WHITE align=center valign=top>15</td> 21304 <td align=left valign=top>RSVD</td> 21305 <td align=left valign=top>Reserved</td> 21306 <td align=left> 21307 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21308 <tr bgcolor=WHITE> 21309 <td bgcolor=WHITE align=center valign=top>14:00</td> 21310 <td align=left valign=top>RW</td> 21311 <td align=left valign=top>fir_post_23</td> 21312 <td align=left> 21313 tx coeff fir_post_23 <br> 21314 Reset value is 0x7ffd.</td></tr> 21315 </table><p> 21316 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21317 <hr> 21318 <b><a NAME="TX_COEFF_POSTB_POST_CTRL24">TX_COEFF_POSTB_POST_CTRL24 - TX COEFF FIR_POST Register: R24</a></b><br> 21319 Address Offset = 32'h0000_d349<br> 21320 Physical Address = 32'h0000_d349<br> 21321 Reset Value = 16'h7fff<br> 21322 Access = RW (16-bit only)<br> 21323 <table border=1 align=center width=100% cellpadding=0> 21324 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21325 <tr bgcolor=WHITE> 21326 <td bgcolor=WHITE align=center valign=top>15</td> 21327 <td align=left valign=top>RSVD</td> 21328 <td align=left valign=top>Reserved</td> 21329 <td align=left> 21330 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21331 <tr bgcolor=WHITE> 21332 <td bgcolor=WHITE align=center valign=top>14:00</td> 21333 <td align=left valign=top>RW</td> 21334 <td align=left valign=top>fir_post_24</td> 21335 <td align=left> 21336 tx coeff fir_post_24 <br> 21337 Reset value is 0x7fff.</td></tr> 21338 </table><p> 21339 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21340 <hr> 21341 <b><a NAME="TX_COEFF_POSTB_REG_PRE_POST_CTRL">TX_COEFF_POSTB_REG_PRE_POST_CTRL - TX FIR REG_PRE_POST1PRE_DEFAULT & REG_POST1_POST1PRE_DEFAULT Register</a></b><br> 21342 Address Offset = 32'h0000_d34a<br> 21343 Physical Address = 32'h0000_d34a<br> 21344 Reset Value = 16'h0000<br> 21345 Access = RW (16-bit only)<br> 21346 <table border=1 align=center width=100% cellpadding=0> 21347 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21348 <tr bgcolor=WHITE> 21349 <td bgcolor=WHITE align=center valign=top>15:12</td> 21350 <td align=left valign=top>RSVD</td> 21351 <td align=left valign=top>Reserved</td> 21352 <td align=left> 21353 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21354 <tr bgcolor=WHITE> 21355 <td bgcolor=WHITE align=center valign=top>11:06</td> 21356 <td align=left valign=top>RW</td> 21357 <td align=left valign=top>post1_post1pre_default</td> 21358 <td align=left> 21359 tx Register post1_post1pre_default <br> 21360 Reset value is 0x0.</td></tr> 21361 <tr bgcolor=WHITE> 21362 <td bgcolor=WHITE align=center valign=top>05:00</td> 21363 <td align=left valign=top>RW</td> 21364 <td align=left valign=top>pre_post1pre_default</td> 21365 <td align=left> 21366 tx Register re_post1pre_default <br> 21367 Reset value is 0x0.</td></tr> 21368 </table><p> 21369 <A HREF="#TX_COEFF_POSTB Registers">Return to TX_COEFF_POSTB: per lane register block [One Copy Per Lane] Table</A><p> 21370 <hr> 21371 <H1><a NAME="TX_COEFF_PRE Registers">TX_COEFF_PRE: per lane register block [One Copy Per Lane] Registers</a></H1> 21372 <table border=1 align=center width=100% cellpadding=0> 21373 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 21374 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 21375 <tr> 21376 <td align=center>0xD350</td><td><A HREF="#TX_COEFF_PRE_PRE_EXTENT_CTRL0">TX_COEFF_PRE_PRE_EXTENT_CTRL0</A><br>TX COEFF pre_extent_0</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_extent_0</div> </td> <td align=center>16'h003f</td></tr> 21377 <tr> 21378 <td align=center>0xD351</td><td><A HREF="#TX_COEFF_PRE_PRE_EXTENT_CTRL1">TX_COEFF_PRE_PRE_EXTENT_CTRL1</A><br>TX COEFF pre_extent_1</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_extent_1</div> </td> <td align=center>16'h003f</td></tr> 21379 <tr> 21380 <td align=center>0xD352</td><td><A HREF="#TX_COEFF_PRE_PRE_EXTENT_CTRL2">TX_COEFF_PRE_PRE_EXTENT_CTRL2</A><br>TX COEFF pre_extent_2</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_extent_2</div> </td> <td align=center>16'h003f</td></tr> 21381 <tr> 21382 <td align=center>0xD353</td><td><A HREF="#TX_COEFF_PRE_PRE_EXTENT_CTRL3">TX_COEFF_PRE_PRE_EXTENT_CTRL3</A><br>TX COEFF pre_extent_3</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_extent_3</div> </td> <td align=center>16'h003f</td></tr> 21383 <tr> 21384 <td align=center>0xD354</td><td><A HREF="#TX_COEFF_PRE_PRE_EXTENT_CTRL4">TX_COEFF_PRE_PRE_EXTENT_CTRL4</A><br>TX COEFF pre_extent_4</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_extent_4</div> </td> <td align=center>16'h003f</td></tr> 21385 <tr> 21386 <td align=center>0xD355</td><td><A HREF="#TX_COEFF_PRE_PRE_EXTENT_CTRL5">TX_COEFF_PRE_PRE_EXTENT_CTRL5</A><br>TX COEFF pre_extent_5</td><td bgcolor=#CCCCCC align=center colspan="10"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="6"><div class="HT">fir_pre_extent_5</div> </td> <td align=center>16'h003f</td></tr> 21387 </table><p> 21388 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 21389 <hr> 21390 <b><a NAME="TX_COEFF_PRE_PRE_EXTENT_CTRL0">TX_COEFF_PRE_PRE_EXTENT_CTRL0 - TX COEFF pre_extent_0</a></b><br> 21391 Address Offset = 32'h0000_d350<br> 21392 Physical Address = 32'h0000_d350<br> 21393 Reset Value = 16'h003f<br> 21394 Access = RW (16-bit only)<br> 21395 <table border=1 align=center width=100% cellpadding=0> 21396 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21397 <tr bgcolor=WHITE> 21398 <td bgcolor=WHITE align=center valign=top>15:06</td> 21399 <td align=left valign=top>RSVD</td> 21400 <td align=left valign=top>Reserved</td> 21401 <td align=left> 21402 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21403 <tr bgcolor=WHITE> 21404 <td bgcolor=WHITE align=center valign=top>05:00</td> 21405 <td align=left valign=top>RW</td> 21406 <td align=left valign=top>fir_pre_extent_0</td> 21407 <td align=left> 21408 tx coeff fir_pre_extent_0 when pre_coefficient > 10<br> 21409 Reset value is 0x3f.</td></tr> 21410 </table><p> 21411 <A HREF="#TX_COEFF_PRE Registers">Return to TX_COEFF_PRE: per lane register block [One Copy Per Lane] Table</A><p> 21412 <hr> 21413 <b><a NAME="TX_COEFF_PRE_PRE_EXTENT_CTRL1">TX_COEFF_PRE_PRE_EXTENT_CTRL1 - TX COEFF pre_extent_1</a></b><br> 21414 Address Offset = 32'h0000_d351<br> 21415 Physical Address = 32'h0000_d351<br> 21416 Reset Value = 16'h003f<br> 21417 Access = RW (16-bit only)<br> 21418 <table border=1 align=center width=100% cellpadding=0> 21419 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21420 <tr bgcolor=WHITE> 21421 <td bgcolor=WHITE align=center valign=top>15:06</td> 21422 <td align=left valign=top>RSVD</td> 21423 <td align=left valign=top>Reserved</td> 21424 <td align=left> 21425 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21426 <tr bgcolor=WHITE> 21427 <td bgcolor=WHITE align=center valign=top>05:00</td> 21428 <td align=left valign=top>RW</td> 21429 <td align=left valign=top>fir_pre_extent_1</td> 21430 <td align=left> 21431 tx coeff fir_pre_extent_1 when pre_coefficient > 10<br> 21432 Reset value is 0x3f.</td></tr> 21433 </table><p> 21434 <A HREF="#TX_COEFF_PRE Registers">Return to TX_COEFF_PRE: per lane register block [One Copy Per Lane] Table</A><p> 21435 <hr> 21436 <b><a NAME="TX_COEFF_PRE_PRE_EXTENT_CTRL2">TX_COEFF_PRE_PRE_EXTENT_CTRL2 - TX COEFF pre_extent_2</a></b><br> 21437 Address Offset = 32'h0000_d352<br> 21438 Physical Address = 32'h0000_d352<br> 21439 Reset Value = 16'h003f<br> 21440 Access = RW (16-bit only)<br> 21441 <table border=1 align=center width=100% cellpadding=0> 21442 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21443 <tr bgcolor=WHITE> 21444 <td bgcolor=WHITE align=center valign=top>15:06</td> 21445 <td align=left valign=top>RSVD</td> 21446 <td align=left valign=top>Reserved</td> 21447 <td align=left> 21448 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21449 <tr bgcolor=WHITE> 21450 <td bgcolor=WHITE align=center valign=top>05:00</td> 21451 <td align=left valign=top>RW</td> 21452 <td align=left valign=top>fir_pre_extent_2</td> 21453 <td align=left> 21454 tx coeff fir_pre_extent_2 when pre_coefficient > 10<br> 21455 Reset value is 0x3f.</td></tr> 21456 </table><p> 21457 <A HREF="#TX_COEFF_PRE Registers">Return to TX_COEFF_PRE: per lane register block [One Copy Per Lane] Table</A><p> 21458 <hr> 21459 <b><a NAME="TX_COEFF_PRE_PRE_EXTENT_CTRL3">TX_COEFF_PRE_PRE_EXTENT_CTRL3 - TX COEFF pre_extent_3</a></b><br> 21460 Address Offset = 32'h0000_d353<br> 21461 Physical Address = 32'h0000_d353<br> 21462 Reset Value = 16'h003f<br> 21463 Access = RW (16-bit only)<br> 21464 <table border=1 align=center width=100% cellpadding=0> 21465 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21466 <tr bgcolor=WHITE> 21467 <td bgcolor=WHITE align=center valign=top>15:06</td> 21468 <td align=left valign=top>RSVD</td> 21469 <td align=left valign=top>Reserved</td> 21470 <td align=left> 21471 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21472 <tr bgcolor=WHITE> 21473 <td bgcolor=WHITE align=center valign=top>05:00</td> 21474 <td align=left valign=top>RW</td> 21475 <td align=left valign=top>fir_pre_extent_3</td> 21476 <td align=left> 21477 tx coeff fir_pre_extent_3 when pre_coefficient > 10<br> 21478 Reset value is 0x3f.</td></tr> 21479 </table><p> 21480 <A HREF="#TX_COEFF_PRE Registers">Return to TX_COEFF_PRE: per lane register block [One Copy Per Lane] Table</A><p> 21481 <hr> 21482 <b><a NAME="TX_COEFF_PRE_PRE_EXTENT_CTRL4">TX_COEFF_PRE_PRE_EXTENT_CTRL4 - TX COEFF pre_extent_4</a></b><br> 21483 Address Offset = 32'h0000_d354<br> 21484 Physical Address = 32'h0000_d354<br> 21485 Reset Value = 16'h003f<br> 21486 Access = RW (16-bit only)<br> 21487 <table border=1 align=center width=100% cellpadding=0> 21488 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21489 <tr bgcolor=WHITE> 21490 <td bgcolor=WHITE align=center valign=top>15:06</td> 21491 <td align=left valign=top>RSVD</td> 21492 <td align=left valign=top>Reserved</td> 21493 <td align=left> 21494 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21495 <tr bgcolor=WHITE> 21496 <td bgcolor=WHITE align=center valign=top>05:00</td> 21497 <td align=left valign=top>RW</td> 21498 <td align=left valign=top>fir_pre_extent_4</td> 21499 <td align=left> 21500 tx coeff fir_pre_extent_4 when pre_coefficient > 10<br> 21501 Reset value is 0x3f.</td></tr> 21502 </table><p> 21503 <A HREF="#TX_COEFF_PRE Registers">Return to TX_COEFF_PRE: per lane register block [One Copy Per Lane] Table</A><p> 21504 <hr> 21505 <b><a NAME="TX_COEFF_PRE_PRE_EXTENT_CTRL5">TX_COEFF_PRE_PRE_EXTENT_CTRL5 - TX COEFF pre_extent_5</a></b><br> 21506 Address Offset = 32'h0000_d355<br> 21507 Physical Address = 32'h0000_d355<br> 21508 Reset Value = 16'h003f<br> 21509 Access = RW (16-bit only)<br> 21510 <table border=1 align=center width=100% cellpadding=0> 21511 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21512 <tr bgcolor=WHITE> 21513 <td bgcolor=WHITE align=center valign=top>15:06</td> 21514 <td align=left valign=top>RSVD</td> 21515 <td align=left valign=top>Reserved</td> 21516 <td align=left> 21517 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21518 <tr bgcolor=WHITE> 21519 <td bgcolor=WHITE align=center valign=top>05:00</td> 21520 <td align=left valign=top>RW</td> 21521 <td align=left valign=top>fir_pre_extent_5</td> 21522 <td align=left> 21523 tx coeff fir_pre_extent_5 when pre_coefficient > 10<br> 21524 Reset value is 0x3f.</td></tr> 21525 </table><p> 21526 <A HREF="#TX_COEFF_PRE Registers">Return to TX_COEFF_PRE: per lane register block [One Copy Per Lane] Table</A><p> 21527 <hr> 21528 <H1><a NAME="MDIO_MMDSEL_AER_COM Registers">MDIO_MMDSEL_AER_COM: common register block for all lanes Registers</a></H1> 21529 <table border=1 align=center width=100% cellpadding=0> 21530 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 21531 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 21532 <tr> 21533 <td align=center>0xFFDC</td><td><A HREF="#MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR">MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR</A><br>Broadcast Port Address</td><td bgcolor=#CCCCCC align=center colspan="11"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="5"><div class="HT">mdio_brcst_port_addr</div> </td> <td align=center>16'h001f</td></tr> 21534 <tr> 21535 <td align=center>0xFFDD</td><td><A HREF="#MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT">MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT</A><br>MMD Select</td><td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_multi_prts_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_multi_mmds_en</div> </td> <td bgcolor=#CCCCCC align=center colspan="7"><div class="HT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_dev_pcs_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_dev_dte_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_dev_phy_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_dev_an_en</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_dev_pmd_en</div> </td> <td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center valign=center width=0><div class="VT">mdio_dev_cl22_en</div> </td> <td align=center>16'h404d</td></tr> 21536 <tr> 21537 <td align=center>0xFFDE</td><td><A HREF="#MDIO_MMDSEL_AER_COM_MDIO_AER">MDIO_MMDSEL_AER_COM_MDIO_AER</A><br>AER</td><td bgcolor=#FFFFFF align=center colspan="16"><div class="HT">mdio_aer</div> </td> <td align=center>16'h0000</td></tr> 21538 </table><p> 21539 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 21540 <hr> 21541 <b><a NAME="MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR">MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR - Broadcast Port Address</a></b><br> 21542 Address Offset = 32'h0000_ffdc<br> 21543 Physical Address = 32'h0000_ffdc<br> 21544 Reset Value = 16'h001f<br> 21545 Access = RW (16-bit only)<br> 21546 <table border=1 align=center width=100% cellpadding=0> 21547 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21548 <tr bgcolor=WHITE> 21549 <td bgcolor=WHITE align=center valign=top>15:05</td> 21550 <td align=left valign=top>RSVD</td> 21551 <td align=left valign=top>Reserved</td> 21552 <td align=left> 21553 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21554 <tr bgcolor=WHITE> 21555 <td bgcolor=WHITE align=center valign=top>04:00</td> 21556 <td align=left valign=top>RW</td> 21557 <td align=left valign=top>mdio_brcst_port_addr</td> 21558 <td align=left> 21559 Braodcast port address that can be used to broadcast mdio commands <br> 21560 to multiple controllers connected to the same mdio station manager <br> 21561 Reset value is 0x1f.</td></tr> 21562 </table><p> 21563 <A HREF="#MDIO_MMDSEL_AER_COM Registers">Return to MDIO_MMDSEL_AER_COM: common register block for all lanes Table</A><p> 21564 <hr> 21565 <b><a NAME="MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT">MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT - MMD Select</a></b><br> 21566 Address Offset = 32'h0000_ffdd<br> 21567 Physical Address = 32'h0000_ffdd<br> 21568 Reset Value = 16'h404d<br> 21569 Access = RW (16-bit only)<br> 21570 <table border=1 align=center width=100% cellpadding=0> 21571 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21572 <tr bgcolor=WHITE> 21573 <td bgcolor=WHITE align=center valign=top>15</td> 21574 <td align=left valign=top>RW</td> 21575 <td align=left valign=top>mdio_multi_prts_en</td> 21576 <td align=left> 21577 When set enables multiple prtad functionality.  Each of the lanes' <br> 21578 mmds can be accessed with consecutive PRTADs.  Lane 0 is accessed <br> 21579 with PRTAD_STRAP, lane 1 with PRTAD_STRAP+1, lane 2 with PRTAD_STRAP+2 <br> 21580 and lane 3 with PRTAD_STRAP+3.<br> 21581 Reset value is 0.</td></tr> 21582 <tr bgcolor=WHITE> 21583 <td bgcolor=WHITE align=center valign=top>14</td> 21584 <td align=left valign=top>RW</td> 21585 <td align=left valign=top>mdio_multi_mmds_en</td> 21586 <td align=left> 21587 When set enables the multiple MMD functionality.  MD_ST is ignored and <br> 21588 each device can be accessed directly with the appropriate CL22 or CL45 <br> 21589 protocol.<br> 21590 Reset value is 1.</td></tr> 21591 <tr bgcolor=WHITE> 21592 <td bgcolor=WHITE align=center valign=top>13:07</td> 21593 <td align=left valign=top>RSVD</td> 21594 <td align=left valign=top>Reserved</td> 21595 <td align=left> 21596 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21597 <tr bgcolor=WHITE> 21598 <td bgcolor=WHITE align=center valign=top>06</td> 21599 <td align=left valign=top>RW</td> 21600 <td align=left valign=top>mdio_dev_pcs_en</td> 21601 <td align=left> 21602 When set and mdio_multi_mmds_en=1 then the PCS device=3 registers can be directly <br> 21603 accessed through the MDIO serial data stream.<br> 21604 Reset value is 1.</td></tr> 21605 <tr bgcolor=WHITE> 21606 <td bgcolor=WHITE align=center valign=top>05</td> 21607 <td align=left valign=top>RW</td> 21608 <td align=left valign=top>mdio_dev_dte_en</td> 21609 <td align=left> 21610 When set and mdio_multi_mmds_en=1 then the DTE device=5 registers can be directly <br> 21611 accessed through the MDIO serial data stream.<br> 21612 Reset value is 0.</td></tr> 21613 <tr bgcolor=WHITE> 21614 <td bgcolor=WHITE align=center valign=top>04</td> 21615 <td align=left valign=top>RW</td> 21616 <td align=left valign=top>mdio_dev_phy_en</td> 21617 <td align=left> 21618 When set and mdio_multi_mmds_en=1 then the PHY device=4 registers can be directly <br> 21619 accessed through the MDIO serial data stream.<br> 21620 Reset value is 0.</td></tr> 21621 <tr bgcolor=WHITE> 21622 <td bgcolor=WHITE align=center valign=top>03</td> 21623 <td align=left valign=top>RW</td> 21624 <td align=left valign=top>mdio_dev_an_en</td> 21625 <td align=left> 21626 When set and mdio_multi_mmds_en=1 then the AN device=7 registers can be directly <br> 21627 accessed through the MDIO serial data stream.<br> 21628 Reset value is 1.</td></tr> 21629 <tr bgcolor=WHITE> 21630 <td bgcolor=WHITE align=center valign=top>02</td> 21631 <td align=left valign=top>RW</td> 21632 <td align=left valign=top>mdio_dev_pmd_en</td> 21633 <td align=left> 21634 When set and mdio_multi_mmds_en=1 then the PMD device=1 registers can be directly <br> 21635 accessed through the MDIO serial data stream.<br> 21636 Reset value is 1.</td></tr> 21637 <tr bgcolor=WHITE> 21638 <td bgcolor=WHITE align=center valign=top>01</td> 21639 <td align=left valign=top>RSVD</td> 21640 <td align=left valign=top>Reserved</td> 21641 <td align=left> 21642 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21643 <tr bgcolor=WHITE> 21644 <td bgcolor=WHITE align=center valign=top>00</td> 21645 <td align=left valign=top>RW</td> 21646 <td align=left valign=top>mdio_dev_cl22_en</td> 21647 <td align=left> 21648 When set and mdio_multi_mmds_en=1 then CL22 registers can be directly <br> 21649 accessed through the MDIO serial data stream.<br> 21650 Reset value is 1.</td></tr> 21651 </table><p> 21652 <A HREF="#MDIO_MMDSEL_AER_COM Registers">Return to MDIO_MMDSEL_AER_COM: common register block for all lanes Table</A><p> 21653 <hr> 21654 <b><a NAME="MDIO_MMDSEL_AER_COM_MDIO_AER">MDIO_MMDSEL_AER_COM_MDIO_AER - AER</a></b><br> 21655 Address Offset = 32'h0000_ffde<br> 21656 Physical Address = 32'h0000_ffde<br> 21657 Reset Value = 16'h0000<br> 21658 Access = RW (16-bit only)<br> 21659 <table border=1 align=center width=100% cellpadding=0> 21660 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21661 <tr bgcolor=WHITE> 21662 <td bgcolor=WHITE align=center valign=top>15:00</td> 21663 <td align=left valign=top>RW</td> 21664 <td align=left valign=top>mdio_aer</td> 21665 <td align=left> 21666 Provides upper 16-bits of 32-bit address for mdio transactions<br> 21667 Reset value is 0x0.</td></tr> 21668 </table><p> 21669 <A HREF="#MDIO_MMDSEL_AER_COM Registers">Return to MDIO_MMDSEL_AER_COM: common register block for all lanes Table</A><p> 21670 <hr> 21671 <H1><a NAME="MDIO_BLK_ADDR_COM Registers">MDIO_BLK_ADDR_COM: common register block for all lanes Registers</a></H1> 21672 <table border=1 align=center width=100% cellpadding=0> 21673 <tr bgcolor="#C0CFF0"><td rowspan="2" align=center width=5%><b>Address</b></td><td rowspan="2" align=center width=25%><b>Register Name/Description </b></td><td colspan="16" align=center width=65%><b>Bit Description</b></td><td rowspan="2" align=center width=5%><b>Default</b></td></tr> 21674 <tr bgcolor="#C0CFF0"><td align=center width=2%><b>15</b></td><td align=center width=2%><b>14</b></td><td align=center width=2%><b>13</b></td><td align=center width=2%><b>12</b></td><td align=center width=2%><b>11</b></td><td align=center width=2%><b>10</b></td><td align=center width=2%><b>9</b></td><td align=center width=2%><b>8</b></td><td align=center width=2%><b>7</b></td><td align=center width=2%><b>6</b></td><td align=center width=2%><b>5</b></td><td align=center width=2%><b>4</b></td><td align=center width=2%><b>3</b></td><td align=center width=2%><b>2</b></td><td align=center width=2%><b>1</b></td><td align=center width=2%><b>0</b></td></tr> 21675 <tr> 21676 <td align=center>0xFFDF</td><td><A HREF="#MDIO_BLK_ADDR_COM_BLK_ADDR">MDIO_BLK_ADDR_COM_BLK_ADDR</A><br>BLK_ADDR</td><td bgcolor=#CCCCCC align=center valign=center width=0><div class="VT">reserved</div> </td> <td bgcolor=#FFFFFF align=center colspan="11"><div class="HT">mdio_blk_addr</div> </td> <td bgcolor=#CCCCCC align=center colspan="4"><div class="HT">reserved</div> </td> <td align=center>16'h0000</td></tr> 21677 </table><p> 21678 <A HREF="#pcie_gen3">Return to pcie_gen3: pcie_gen3 Table</A><p> 21679 <hr> 21680 <b><a NAME="MDIO_BLK_ADDR_COM_BLK_ADDR">MDIO_BLK_ADDR_COM_BLK_ADDR - BLK_ADDR</a></b><br> 21681 Address Offset = 32'h0000_ffdf<br> 21682 Physical Address = 32'h0000_ffdf<br> 21683 Reset Value = 16'h0000<br> 21684 Access = RW (16-bit only)<br> 21685 <table border=1 align=center width=100% cellpadding=0> 21686 <tr bgcolor="#C0CFF0"><th align=center width=5%>Bit Field</th><th align=center width=5%>Bit Access </th><th align=center width=25%>Field Name</th><th align=center width=65%>Description</th></tr> 21687 <tr bgcolor=WHITE> 21688 <td bgcolor=WHITE align=center valign=top>15</td> 21689 <td align=left valign=top>RSVD</td> 21690 <td align=left valign=top>Reserved</td> 21691 <td align=left> 21692 Reserved bit must be written with 0.  A read returns an unknown value.</td></tr> 21693 <tr bgcolor=WHITE> 21694 <td bgcolor=WHITE align=center valign=top>14:04</td> 21695 <td align=left valign=top>RW</td> 21696 <td align=left valign=top>mdio_blk_addr</td> 21697 <td align=left> 21698 Block address (used for clause 22 transactions to get the address bits 14:4)<br> 21699 Reset value is 0x0.</td></tr> 21700 <tr bgcolor=WHITE> 21701 <td bgcolor=WHITE align=center valign=top>03:00</td> 21702 <td align=left valign=top>RSVD</td> 21703 <td align=left valign=top>Reserved</td> 21704 <td align=left> 21705 Reserved bits must be written with 0.  A read returns an unknown value.</td></tr> 21706 </table><p> 21707 <A HREF="#MDIO_BLK_ADDR_COM Registers">Return to MDIO_BLK_ADDR_COM: common register block for all lanes Table</A><p> 21708 <hr> 21709 </html>