openbcm

Git mirror of https://github.com/Broadcom-Network-Switching-Software/OpenBCM
git clone git://git.finwo.net/mirror/broadcom/openbcm
Log | Files | Refs | README

pcie_diag.c (7227B)

      1 /*
      2  * 
      3  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      4  * 
      5  * Copyright 2007-2019 Broadcom Inc. All rights reserved.
      6  */
      7 
      8 #include <merlin16_pcieg3_internal.h>
      9 #include <common/srds_api_err_code.h>
     10 #include <common/srds_api_types.h>
     11 #include <merlin16_pcieg3_diag.h>
     12 #include <merlin16_pcieg3_debug_functions.h>
     13 #include <merlin16_pcieg3_dependencies.h>
     14 #include <merlin16_pcieg3_config.h>
     15 #include <pcig3_phy_acc.h>
     16 
     17 /******************************************************************************
     18  Register read/write
     19  */
     20 int pcie_phy_diag_reg_read(srds_access_t *sa, uint16_t address, uint16_t *pdata)
     21 {
     22     int rv;
     23 
     24     rv = merlin16_pcieg3_pmd_rdt_reg(sa, address, pdata);
     25     return (rv == ERR_CODE_NONE) ? SRDS_E_NONE : SRDS_E_FAIL;
     26 }
     27 
     28 int pcie_phy_diag_reg_write(srds_access_t *sa, uint16_t address, uint16_t data)
     29 {
     30     int rv;
     31 
     32     rv = merlin16_pcieg3_pmd_wr_reg(sa, address, data);
     33     return (rv == ERR_CODE_NONE) ? SRDS_E_NONE : SRDS_E_FAIL;
     34 }
     35 
     36 int pcie_phy_diag_reg_mwr(srds_access_t *sa, uint16_t address, uint16_t mask, uint8_t lsb, uint16_t val)
     37 {
     38     int rv;
     39 
     40     rv = merlin16_pcieg3_pmd_mwr_reg(sa, address, mask, lsb, val);
     41     return (rv == ERR_CODE_NONE) ? SRDS_E_NONE : SRDS_E_FAIL;
     42 }
     43 
     44 int pcie_phy_diag_pram_read(srds_access_t *sa, uint32_t address, uint32_t size)
     45 {
     46     uint16_t addr_l, addr_h;
     47     uint16_t data_l;
     48     int i, rv = SRDS_E_NONE;
     49 
     50     addr_l = (uint16_t) address & 0xffff;
     51     addr_h = (uint16_t) ((address >> 16) & 0xffff);
     52 
     53     /* Enable pram if */
     54     cli_out("\n_pcie_serdes_pram_read: Enable pram if\n");
     55     rv= pcie_phy_diag_reg_mwr(sa, 0xd202, 1 << 13, 13, 1);
     56     if (rv != SRDS_E_NONE) goto done;
     57 
     58     /* Set 16-bit read size */
     59     rv= pcie_phy_diag_reg_mwr(sa, 0xd202, 3 << 4, 4, 1);
     60     if (rv != SRDS_E_NONE) goto done;
     61 
     62     rv = pcie_phy_diag_reg_write(sa, 0xd208, addr_l); /* LSW ADDR */
     63     if (rv != SRDS_E_NONE) goto done;
     64 
     65     rv = pcie_phy_diag_reg_write(sa, 0xd209, addr_h); /* MSW ADDR */
     66     if (rv != SRDS_E_NONE) goto done;
     67 
     68     for (i = 0; i < size; i++) {
     69         rv = pcie_phy_diag_reg_read(sa, 0xd20a, &data_l); /* LSW ADDR */
     70         if (rv != SRDS_E_NONE) goto done;
     71         cli_out("address: 0x%x,  data = 0x%x\n", address, data_l);
     72         address += 2;
     73     }
     74 
     75 done:
     76     if (rv != SRDS_E_NONE) {
     77         cli_out("\npcie_diag_pram_read: phy access failed: Error 0x%x \n", rv);
     78     }
     79 
     80     return rv;
     81 }
     82 
     83 /******************************************************************************
     84 DSC
     85  */
     86 int pcie_phy_diag_dsc(srds_access_t *sa, int array_size)
     87 {
     88     int i, rv = ERR_CODE_NONE;
     89     uint32_t lane, lane_index;
     90 
     91     if (sa == NULL || array_size == 0) {
     92         return SRDS_E_PARAM;
     93     }
     94 
     95     for (i = 0 ; i < array_size ; i++) {
     96         lane = sa[i].lane_mask;
     97         rv = merlin16_pcieg3_display_core_state(&sa[i]);
     98         if (rv != ERR_CODE_NONE) {
     99            cli_out("merlin16_pcieg3_display_core_state() failed: 0x%x\n", rv);
    100            return SRDS_E_FAIL;
    101         }
    102 
    103         rv = merlin16_pcieg3_display_lane_state_hdr();
    104         if (rv != ERR_CODE_NONE) {
    105            cli_out("merlin16_pcieg3_display_lane_state_hdr() failed: 0x%x\n", rv);
    106            return SRDS_E_FAIL;
    107         }
    108 
    109         for (lane_index = 0 ; lane_index < PCIE_MAX_LANES_PER_CORE; lane_index++) {
    110             sa[i].lane_mask = lane & (1<<lane_index);
    111             /*if lane is not selected pass*/
    112             if(sa[i].lane_mask == 0){
    113                 continue;
    114             }
    115             /*collect info*/
    116             rv = merlin16_pcieg3_display_lane_state(&sa[i]);
    117             if (rv != ERR_CODE_NONE) {
    118                 cli_out("merlin16_pcieg3_display_lane_state() failed: 0x%x\n", rv);
    119                 break;
    120             }
    121         }
    122         sa[i].lane_mask = lane;
    123         if (rv != ERR_CODE_NONE) {
    124             break;
    125         }
    126     }
    127 
    128     return (rv == ERR_CODE_NONE) ? SRDS_E_NONE : SRDS_E_FAIL;
    129 }
    130 
    131 /******************************************************************************
    132 State
    133  */
    134 int pcie_phy_diag_state(srds_access_t *sa, int array_size)
    135 {
    136     int i, rv = ERR_CODE_NONE;
    137     uint32_t lane, lane_index;
    138 
    139     if (sa == NULL || array_size == 0) {
    140         return SRDS_E_PARAM;
    141     }
    142 
    143     for (i = 0 ; i < array_size ; i++) {
    144         lane = sa[i].lane_mask;
    145         merlin16_pcieg3_init_merlin16_pcieg3_info(&sa[i]);
    146         rv = merlin16_pcieg3_display_core_state_hdr();
    147         if (rv != ERR_CODE_NONE) {
    148            cli_out("merlin16_pcieg3_display_core_state_hdr() failed: 0x%x\n", rv);
    149            return SRDS_E_FAIL;
    150         }
    151         rv = merlin16_pcieg3_display_core_state_line(&sa[i]);
    152         if (rv != ERR_CODE_NONE) {
    153            cli_out("erlin16_pcieg3_display_core_state_line() failed: 0x%x\n", rv);
    154            return SRDS_E_FAIL;
    155         }
    156         rv = merlin16_pcieg3_display_core_state(&sa[i]);
    157         if (rv != ERR_CODE_NONE) {
    158            cli_out("merlin16_pcieg3_display_core_state() failed: 0x%x\n", rv);
    159            return SRDS_E_FAIL;
    160         }
    161         rv = merlin16_pcieg3_display_lane_state_hdr();
    162         if (rv != ERR_CODE_NONE) {
    163            cli_out("merlin16_pcieg3_display_lane_state_hdr() failed: 0x%x\n", rv);
    164            return SRDS_E_FAIL;
    165         }
    166 
    167         for (lane_index = 0 ; lane_index < PCIE_MAX_LANES_PER_CORE; lane_index++) {
    168             sa[i].lane_mask = lane & (1<<lane_index);
    169             /*if lane is not selected pass*/
    170             if (sa[i].lane_mask == 0) {
    171                 continue;
    172             }
    173             /*collect info*/
    174             rv = merlin16_pcieg3_display_lane_state(&sa[i]);
    175             if (rv != ERR_CODE_NONE) {
    176                 break;
    177             }
    178             rv = merlin16_pcieg3_read_event_log(&sa[i]);
    179             if (rv != ERR_CODE_NONE) {
    180                 break;
    181             }
    182         }
    183         sa[i].lane_mask = lane;
    184         if (rv != ERR_CODE_NONE) {
    185             break;
    186         }
    187     }
    188 
    189     return (rv == ERR_CODE_NONE) ? SRDS_E_NONE : SRDS_E_FAIL;
    190 }
    191 
    192 /******************************************************************************
    193 Eyescan
    194  */
    195 int pcie_phy_diag_eyescan(srds_access_t *sa, int array_size)
    196 {
    197     int i, rv = ERR_CODE_NONE;
    198     uint32_t lane, lane_index;
    199 
    200     if (sa == NULL || array_size == 0) {
    201         return SRDS_E_PARAM;
    202     }
    203 
    204     for (i = 0 ; i < array_size ; i++) {
    205         lane = sa[i].lane_mask;
    206         cli_out("pcie_phy_diag_eyescan: lane_mask: 0x%x\n", lane);
    207         merlin16_pcieg3_init_merlin16_pcieg3_info(&sa[i]);
    208 
    209         for (lane_index = 0 ; lane_index < PCIE_MAX_LANES_PER_CORE; lane_index++) {
    210             sa[i].lane_mask = lane & (1<<lane_index);
    211             sa[i].core = i;
    212             /*if lane is not selected pass*/
    213             if (sa[i].lane_mask == 0) {
    214                 continue;
    215             }
    216             /* Display eyescan */
    217             cli_out("\nEyescan for Core: %d, lane: %d\n", i, lane_index);
    218             cli_out("==============================\n");
    219             rv = merlin16_pcieg3_display_eye_scan(&sa[i]);
    220             if (rv != ERR_CODE_NONE) {
    221                 break;
    222             }
    223         }
    224         sa[i].lane_mask = lane;
    225         if(rv != ERR_CODE_NONE) {
    226             break;
    227         }
    228     }
    229 
    230     return (rv == ERR_CODE_NONE) ? SRDS_E_NONE : SRDS_E_FAIL;
    231 }