zm73xx.h (7057B)
1 /* 2 * 3 * 4 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 5 * 6 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 7 * 8 * zm73xx.h Digital Power Monitor 9 * 10 * Driver Supports PowerOne zm7304, zm7308, zm7316 & zm7332 11 * 12 * <http://www.power-one.com> 13 * 14 * This driver's initial intent is use on the Broadcom MetroCore Chassis boards. 15 */ 16 17 /* 18 * The ZM7300 series chips have several banks of registers, 19 * user memory, Point Of Load settings, and can monitor the state 20 * of the PoLs. 21 * 22 * The command set is laid out below 23 */ 24 #if !defined(_ZM73XX_H_) 25 #define _ZM73XX_H_ 26 27 #define ZM73_CMD_WRP (0x01) /* 6 write 1 read -- BB mode */ 28 #define ZM73_CMD_RRP (0x11) /* 2 write 2 read -- BB mode */ 29 #define ZM73_CMD_WRM (0x02) /* 2 write 1 read -- BB mode */ 30 #define ZM73_CMD_RRM (0x12) /* 1 write 6 read -- Ext Mode */ 31 #define ZM73_CMD_SRM (0x34) /* 2 write 1 read -- BB mode */ 32 #define ZM73_CMD_RPID (0x16) /* 0 write 33 read -- BB mode */ 33 #define ZM73_CMD_LSR (0x32) /* 1 write 1 read -- Ext Mode */ 34 #define ZM73_CMD_WSR (0x05) /* 2 write 1 read -- BB mode */ 35 #define ZM73_CMD_RSR (0x15) /* 3 write 1 read -- BB mode */ 36 #define ZM73_CMD_SSR (0x33) /* 1 write 1 read -- Ext Mode */ 37 #define ZM73_CMD_LUM (0x35) /* 1 write 1 read -- Ext Mode */ 38 #define ZM73_CMD_WUM (0x36) /* 2 write 1 read -- BB mode */ 39 #define ZM73_CMD_RUM (0x38) /* 2 write 2 read -- BB mode */ 40 #define ZM73_CMD_SUM (0x37) /* 1 write 1 read -- Ext Mode */ 41 #define ZM73_CMD_RSM (0x40) /* 0 write 7 read -- BB mode */ 42 #define ZM73_CMD_RPM (0x41) /* 0 write 17 read -- BB mode */ 43 #define ZM73_CMD_RMDP (0x45) /* 1 write 6 read -- Ext Mode */ 44 #define ZM73_CMD_RPSS (0x44) /* 0 write 5 read -- Ext Mode */ 45 #define ZM73_CMD_RRT (0x42) /* 0 write 5 read -- Ext Mode */ 46 #define ZM73_CMD_ONA (0x20) /* Normal BYTE_WRITE_DATA */ 47 #define ZM73_CMD_ONB (0x21) /* Normal BYTE_WRITE_DATA */ 48 #define ZM73_CMD_ONC (0x22) /* Normal BYTE_WRITE_DATA */ 49 #define ZM73_CMD_OND (0x23) /* Normal BYTE_WRITE_DATA */ 50 #define ZM73_CMD_ONS (0x24) /* Normal BYTE_WRITE_DATA */ 51 #define ZM73_CMD_OFA (0x25) /* Normal BYTE_WRITE_DATA */ 52 #define ZM73_CMD_OFB (0x26) /* Normal BYTE_WRITE_DATA */ 53 #define ZM73_CMD_OFC (0x27) /* Normal BYTE_WRITE_DATA */ 54 #define ZM73_CMD_OFD (0x28) /* Normal BYTE_WRITE_DATA */ 55 #define ZM73_CMD_OFS (0x29) /* Normal BYTE_WRITE_DATA */ 56 #define ZM73_CMD_EOFA (0x2A) /* Normal BYTE_WRITE_DATA */ 57 #define ZM73_CMD_EOFB (0x2B) /* Normal BYTE_WRITE_DATA */ 58 #define ZM73_CMD_EOFC (0x2C) /* Normal BYTE_WRITE_DATA */ 59 #define ZM73_CMD_EOFD (0x2D) /* Normal BYTE_WRITE_DATA */ 60 #define ZM73_CMD_EOFS (0x2E) /* Normal BYTE_WRITE_DATA */ 61 #define ZM73_CMD_MAR (0x39) /* 1 write 1 read -- Ext Mode */ 62 #define ZM73_CMD_FON (0x3A) /* Normal BYTE_WRITE_DATA */ 63 #define ZM73_CMD_FOF (0x3B) /* Normal BYTE_WRITE_DATA */ 64 #define ZM73_CMD_CRC (0x2F) /* 4 write 1 read -- BB mode */ 65 #define ZM73_CMD_PRGP (0x31) /* 4 write 1 read -- BB mode */ 66 67 /* 68 * DPM Setup Registers 69 */ 70 71 #define ZM73XX_DPM_REG_GD1 (0x00) 72 #define ZM73XX_DPM_REG_GD2 (0x04) 73 #define ZM73XX_DPM_REG_GAC (0x08) 74 #define ZM73XX_DPM_REG_GBC (0x09) 75 #define ZM73XX_DPM_REG_GCC (0x0A) 76 #define ZM73XX_DPM_REG_GDC (0x0B) 77 #define ZM73XX_DPM_REG_FPC1 (0x0C) 78 #define ZM73XX_DPM_REG_FPC2 (0x0D) 79 #define ZM73XX_DPM_REG_EPC (0x0E) 80 #define ZM73XX_DPM_REG_IC1 (0x0F) 81 #define ZM73XX_DPM_REG_IC2 (0x10) 82 #define ZM73XX_DPM_REG_IBL (0x11) 83 #define ZM73XX_DPM_REG_IBH (0x13) 84 #define ZM73XX_DPM_REG_ID (0x15) 85 #define ZM73XX_DPM_REG_PB1 (0x17) 86 #define ZM73XX_DPM_REG_PB2 (0x1B) 87 #define ZM73XX_DPM_REG_PB3 (0x1F) 88 #define ZM73XX_DPM_REG_PB4 (0x23) 89 #define ZM73XX_DPM_REG_PMC (0x27) 90 #define ZM73XX_DPM_REG_PID (0x28) 91 #define ZM73XX_DPM_REG_RTC (0x80) 92 #define ZM73XX_DPM_REG_PPS (0x84) 93 #define ZM73XX_DPM_REG_EST (0x88) 94 #define ZM73XX_DPM_REG_IBV (0x89) 95 #define ZM73XX_DPM_REG_STA (0x8B) 96 #define ZM73XX_DPM_REG_STB (0x8C) 97 #define ZM73XX_DPM_REG_STC (0x8D) 98 #define ZM73XX_DPM_REG_STD (0x8E) 99 #define ZM73XX_DPM_REG_REL0 (0x8F) 100 #define ZM73XX_DPM_REG_REL1 (0x90) 101 #define ZM73XX_DPM_REG_PSS (0x91) 102 #define ZM73XX_DPM_REG_DPMS (0x95) 103 #define ZM73XX_DPM_REG_WP (0x96) 104 105 #define NUM_DPM_REGS 0x97 106 107 108 /* 109 * Group Status Register Bits 110 */ 111 #define ZM73XX_GRP_ST_PT (0x80) /* Pre-Warning Temperature Warning */ 112 #define ZM73XX_GRP_ST_PG (0x40) /* Power Good Warning */ 113 #define ZM73XX_GRP_ST_TR (0x20) /* Tracking Fault */ 114 #define ZM73XX_GRP_ST_OT (0x10) /* Temperature Fault */ 115 #define ZM73XX_GRP_ST_OC (0x08) /* OverCurrent Fault */ 116 #define ZM73XX_GRP_ST_UV (0x04) /* UnderVoltage Fault */ 117 #define ZM73XX_GRP_ST_OV (0x02) /* Overvoltage Error */ 118 #define ZM73XX_GRP_ST_PV (0x01) /* Phase Voltage Error */ 119 120 121 /* 122 * POL Setup Registers 123 */ 124 #define ZM73XX_POL_REG_PC1 (0x00) 125 #define ZM73XX_POL_REG_PC2 (0x01) 126 #define ZM73XX_POL_REG_PC3 (0x02) 127 #define ZM73XX_POL_REG_TC (0x03) 128 #define ZM73XX_POL_REG_INT (0x04) 129 #define ZM73XX_POL_REG_DON (0x05) 130 #define ZM73XX_POL_REG_DOF (0x06) 131 #define ZM73XX_POL_REG_VOS (0x07) 132 #define ZM73XX_POL_REG_CLS (0x08) 133 #define ZM73XX_POL_REG_DCL (0x09) 134 #define ZM73XX_POL_REG_B1 (0x0A) 135 #define ZM73XX_POL_REG_B2 (0x0B) 136 #define ZM73XX_POL_REG_B3 (0x0C) 137 #define ZM73XX_POL_REG_C0L (0x0D) 138 #define ZM73XX_POL_REG_C0H (0x0E) 139 #define ZM73XX_POL_REG_C1L (0x0F) 140 #define ZM73XX_POL_REG_C1H (0x10) 141 #define ZM73XX_POL_REG_C2L (0x11) 142 #define ZM73XX_POL_REG_C2H (0x12) 143 #define ZM73XX_POL_REG_C3L (0x13) 144 #define ZM73XX_POL_REG_C3H (0x14) 145 #define ZM73XX_POL_REG_RUN (0x15) 146 #define ZM73XX_POL_REG_ST (0x16) 147 #define ZM73XX_POL_REG_VOM (0x17) 148 #define ZM73XX_POL_REG_IOM (0x18) 149 #define ZM73XX_POL_REG_TOM (0x19) 150 #define ZM73XX_POL_REG_VOML (0x1C) 151 #define ZM73XX_POL_REG_VOMH (0x1D) 152 #define ZM73XX_POL_REG_CRC0 (0x1E) 153 #define ZM73XX_POL_REG_CRC1 (0x1F) 154 155 #define NUM_POL_REGS (0x20) 156 157 /* 158 * Auxillary Device Setup Registers 159 */ 160 #define ZM73XX_AUX_REG_EC (0x00) 161 #define ZM73XX_AUX_REG_EON (0x05) 162 #define ZM73XX_AUX_REG_EOF (0x06) 163 #define ZM73XX_AUX_REG_CRC0_x (0x1E) 164 #define ZM73XX_AUX_REG_CRC1_x (0x1F) 165 166 /* 167 * POL/Aux Setup registers and data 168 * Note: Aux does not use all registers 169 */ 170 #define ZM73XX_POL_NONE (0x00) 171 #define ZM73XX_POL_ZY7005 (0x01) 172 #define ZM73XX_POL_ZY7105 (0x02) 173 #define ZM73XX_POL_ZY7007 (0x03) 174 #define ZM73XX_POL_ZY7107 (0x04) 175 #define ZM73XX_POL_ZY7010 (0x05) 176 #define ZM73XX_POL_ZY7210 (0x06) 177 #define ZM73XX_POL_ZY7015 (0x07) 178 #define ZM73XX_POL_ZY7115 (0x08) 179 #define ZM73XX_POL_ZY7020 (0x09) 180 #define ZM73XX_POL_ZY7120 (0x0A) 181 #define ZM73XX_POL_ZY7030 (0x0B) 182 #define ZM73XX_POL_ZY7130 (0x0C) 183 #define ZM73XX_POL_ZY7040 (0x0D) 184 #define ZM73XX_POL_ZY7140 (0x0E) 185 #define ZM73XX_POL_ZY7050 (0x0F) 186 #define ZM73XX_POL_ZY7150 (0x10) 187 #define ZM73XX_POL_AUX0 (0xF8) 188 #define ZM73XX_POL_AUX1 (0xF9) 189 #define ZM73XX_POL_AUX2 (0xFA) 190 #define ZM73XX_POL_AUX3 (0xFB) 191 192 #endif /* _ZM73XX_H_ */ 193