triumph3.h (41809B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: triumph3.h 8 */ 9 10 #ifndef _SOC_TRIUMPH3_H_ 11 #define _SOC_TRIUMPH3_H_ 12 13 #include <soc/drv.h> 14 15 /*#define MMU_RESET_DEBUG_SUPPORT 1*/ 16 #define _SOC_TR3_MAX_NUM_LPORTS 64 17 #define _SOC_TR3_IBOD_INTR_MASK 0x01000 18 #define _SOC_TR3_FLOWTRACKER_INTR_MASK 0x08000 19 #define _SOC_TR3_ISM_INTR_MASK 0x10000 20 #define _SOC_TR3_ESM_INTR_MASK 0x20000 21 #define _SOC_TR3_AXP_INTR_MASK 0x40000 22 #define _SOC_TR3_FUNC_PARITY_INTR_MASK (_SOC_TR3_IBOD_INTR_MASK | \ 23 _SOC_TR3_ISM_INTR_MASK | _SOC_TR3_AXP_INTR_MASK | \ 24 _SOC_TR3_FLOWTRACKER_INTR_MASK) 25 #define _SOC_TR3_FUNC_INTR_MASK _SOC_TR3_FUNC_PARITY_INTR_MASK 26 27 #define _SOC_TR3_L2_BULK_BURST_MIN 0 28 #define _SOC_TR3_L2_BULK_BURST_MAX 7 29 30 #define _SOC_TR3_PHY_PER_PORT_BLOCK 3 31 #define _SOC_TR3_LANES_PER_PHY 4 32 #define _SOC_TR3_MAX_HG_PORT_COUNT 24 33 34 /* sample esm config-related defines */ 35 #define F11_HWTL 7 36 #define F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC 5 37 #define F11_SA_OTAG_DA_ETHTYPE 4 38 #define F11_NSA_OTAG_NDA_ETHTYPE 3 39 #define F11_UDF1 2 40 #define F11_UDF2 1 41 42 #define F10_HWTL 7 43 #define F10_DIPV6 5 44 #define F10_N_DIPV6 4 45 #define F10_SIPV6_U64_DIPV6_U64 3 46 #define F10_UDF1 2 47 #define F10_UDF2 1 48 49 #define F9_HWTL 7 50 #define F9_SIPV6 5 51 #define F9_N_SIPV6 4 52 #define F9_SIPV6_L64_DIPV6_L64 3 53 #define F9_UDF1 2 54 #define F9_UDF2 1 55 56 #define F8_HWTL 31 57 #define F8_SA_3210_DA_3210 13 58 #define F8_SA_DA_3210 13 59 #define F8_OTAG_DA 12 60 #define F8_OTAG_SA 11 61 #define F8_SIPV4_DIPV4 10 62 #define F8_N_SIPV4_N_DIPV4 9 63 #define F8_SIPV6_U64 8 64 #define F8_DIPV6_U64 7 65 #define F8_IP_FLOW_V6_BITS_FLAGS_IPV4 6 66 #define F8_AUX_TAG_1_AUX_TAG_2 5 67 #define F8_UDF1_3210 4 68 #define F8_UDF1_7654 3 69 #define F8_UDF2_3210 2 70 #define F8_UDF2_7654 1 71 72 #define F7_HWTL 31 73 #define F7_INT_RANGE_CHECK_L3_IIF 20 74 #define F7_SA_54_DA_54 19 75 #define F7_SA_54_ETHTYPE 18 76 #define F7_DA_54_ETHTYPE 17 77 #define F7_OTAG_ITAG 16 78 #define F7_OTAG_ETHTYPE 15 79 #define F7_SIPV4 14 80 #define F7_DIPV4 13 81 #define F7_L4_SRC_L4_DST 12 82 #define F7_N_L4_SRC_N_L4_DST 11 83 #define F7_IP_FLOW_FLAGS_IP_2 10 84 #define F7_SVP_DVP 9 85 #define F7_SGLP_DGLP 8 86 #define F7_AUX_TAG_1 7 87 #define F7_AUX_TAG_2 6 88 #define F7_CLASSID_ALL 5 89 #define F7_UDF2_10 4 90 #define F7_UDF2_32 3 91 #define F7_UDF2_54 2 92 #define F7_UDF2_76 1 93 94 #define F6_HWTL 31 95 #define F6_SA_3210 19 96 #define F6_DA_3210 18 97 #define F6_SA_54_DA_54 17 98 #define F6_OTAG_ITAG 16 99 #define F6_OTAG_ETHERTYPE 15 100 #define F6_SIPV4 14 101 #define F6_DIPV4 13 102 #define F6_L4_SRC_L4_DST 12 103 #define F6_N_L4_SRC_N_L4_DST 11 104 #define F6_IP_FLOW_FLAGS_IP_2 10 105 #define F6_SVP_DVP 9 106 #define F6_SGLP_DGLP 8 107 #define F6_AUX_TAG_1 7 108 #define F6_AUX_TAG_2 6 109 #define F6_CLASSID_ALL 5 110 #define F6_UDF1_10 4 111 #define F6_UDF1_32 3 112 #define F6_UDF1_54 2 113 #define F6_UDF1_76 1 114 115 #define F5_HWTL 31 116 #define F5_ETHTYPE 22 117 #define F5_SA_54 21 118 #define F5_OTAG 20 119 #define F5_ITAG 19 120 #define F5_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST 18 121 #define F5_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC 17 122 #define F5_FLAGS_IP_1_VRF 16 123 #define F5_L3_PROTOCOL_TOS 15 124 #define F5_FLAGS_IP_3 14 125 #define F5_TOS_TTL 13 126 #define F5_L4_SRC 12 127 #define F5_L4_DST 11 128 #define F5_L3_IIF 10 129 #define F5_INT_RANGE_CHECK 9 130 #define F5_SVP 8 131 #define F5_DVP 7 132 #define F5_SGLP 6 133 #define F5_DGLP 5 134 #define F5_CLASSID_INTERFACE 4 135 #define F5_CLASSID_SRC 3 136 #define F5_CLASSID_DST 2 137 #define F5_UDF_1_AND_2_VALID 1 138 139 #define F4_HWTL 31 140 #define F4_ETHTYPE 29 141 #define F4_DA_54 28 142 #define F4_OTAG 27 143 #define F4_ITAG 26 144 #define F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST 25 145 #define F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC 24 146 #define F4_FLAGS_IP_1_VRF 23 147 #define F4_L3_PROTOCOL_TOS 22 148 #define F4_FLAGS_IP_3 21 149 #define F4_TOS_TTL 20 150 #define F4_L4_SRC 19 151 #define F4_L4_DST 18 152 #define F4_L3_IIF 17 153 #define F4_INT_RANGE_CHECK 16 154 #define F4_SVP 15 155 #define F4_DVP 14 156 #define F4_SGLP 13 157 #define F4_DGLP 12 158 #define CLASSID_INTERFACE 11 159 #define F4_CLASSID_SRC 10 160 #define F4_CLASSID_DST 9 161 #define F4_UDF2_0 8 162 #define F4_UDF2_1 7 163 #define F4_UDF2_2 6 164 #define F4_UDF2_3 5 165 #define F4_UDF2_4 4 166 #define F4_UDF2_5 3 167 #define F4_UDF2_6 2 168 #define F4_UDF2_7 1 169 170 #define F3_HWTL 31 171 #define F3_ETHTYPE 29 172 #define F3_OTAG 28 173 #define F3_ITAG 27 174 #define F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST 26 175 #define F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC 25 176 #define F3_FLAGS_IP_1_VRF 24 177 #define F3_L3_PROTOCOL_TOS 23 178 #define F3_FLAGS_IP_3 22 179 #define F3_TOS_TTL 21 180 #define F3_L4_SRC 20 181 #define F3_L4_DST 19 182 #define F3_L3_IIF 18 183 #define F3_INT_RANGE_CHECK 17 184 #define F3_SVP 16 185 #define F3_DVP 15 186 #define F3_SGLP 14 187 #define F3_DGLP 13 188 #define F3_CLASSID_INTERFACE 12 189 #define F3_CLASSID_SRC 11 190 #define F3_CLASSID_DST 10 191 #define F3_UDF_1_AND_2_VALID 9 192 #define F3_UDF1_0 8 193 #define F3_UDF1_1 7 194 #define F3_UDF1_2 6 195 #define F3_UDF1_3 5 196 #define F3_UDF1_4 4 197 #define F3_UDF1_5 3 198 #define F3_UDF1_6 2 199 #define F3_UDF1_7 1 200 201 #define F1_HWTL 7 202 #define F1_DIPV6 5 203 #define F1_N_DIPV6 4 204 #define F1_SIPV6_U64_DIPV6_U64 3 205 #define F1_SIPV6_L64_DIPV6_L64 2 206 #define F1_UDF2 1 207 208 #define F2_FLAG_TOS_7 123 209 #define F2_FLAG_TOS_6 122 210 #define F2_FLAG_TOS_5 121 211 #define F2_FLAG_TOS_4 120 212 #define F2_FLAG_TOS_3 119 213 #define F2_FLAG_TOS_2 118 214 #define F2_FLAG_TOS_1 117 215 #define F2_FLAG_TOS_0 116 216 #define F2_FLAG_INCOMING_TAG_STATUS_1 115 217 #define F2_FLAG_INCOMING_TAG_STATUS_0 114 218 #define F2_FLAG_MY_STATION_HIT 95 219 #define F2_FLAG_MH_MIRROR_ONLY 94 220 #define F2_FLAG_HG 93 221 #define F2_FLAG_L3_IIF_VALID 86 222 #define F2_FLAG_L3_PROTOCOL_FN_3 61 223 #define F2_FLAG_L3_PROTOCOL_FN_2 60 224 #define F2_FLAG_L3_PROTOCOL_FN_1 59 225 #define F2_FLAG_L3_PROTOCOL_FN_0 58 226 #define F2_FLAG_L3_TYPE_3 39 227 #define F2_FLAG_L3_TYPE_2 38 228 #define F2_FLAG_L3_TYPE_1 37 229 #define F2_FLAG_L3_TYPE_0 36 230 #define F2_FLAG_FORWARDING_TYPE_2 34 231 #define F2_FLAG_FORWARDING_TYPE_1 33 232 #define F2_FLAG_FORWARDING_TYPE_0 32 233 #define F2_FLAG_LOOKUP_STATUS_VECTOR_17 29 234 #define F2_FLAG_LOOKUP_STATUS_VECTOR_16 28 235 #define F2_FLAG_LOOKUP_STATUS_VECTOR_15 27 236 #define F2_FLAG_LOOKUP_STATUS_VECTOR_14 26 237 #define F2_FLAG_LOOKUP_STATUS_VECTOR_13 25 238 #define F2_FLAG_LOOKUP_STATUS_VECTOR_12 24 239 #define F2_FLAG_LOOKUP_STATUS_VECTOR_11 23 240 #define F2_FLAG_LOOKUP_STATUS_VECTOR_10 22 241 #define F2_FLAG_LOOKUP_STATUS_VECTOR_9 21 242 #define F2_FLAG_LOOKUP_STATUS_VECTOR_8 20 243 #define F2_FLAG_LOOKUP_STATUS_VECTOR_7 19 244 #define F2_FLAG_LOOKUP_STATUS_VECTOR_6 18 245 #define F2_FLAG_LOOKUP_STATUS_VECTOR_5 17 246 #define F2_FLAG_LOOKUP_STATUS_VECTOR_4 16 247 #define F2_FLAG_LOOKUP_STATUS_VECTOR_3 15 248 #define F2_FLAG_LOOKUP_STATUS_VECTOR_2 14 249 #define F2_FLAG_LOOKUP_STATUS_VECTOR_1 13 250 #define F2_FLAG_LOOKUP_STATUS_VECTOR_0 12 251 #define F2_FLAG_TUNNEL_AND_LPBK_TYPE_4 11 252 #define F2_FLAG_TUNNEL_AND_LPBK_TYPE_3 10 253 #define F2_FLAG_TUNNEL_AND_LPBK_TYPE_2 9 254 #define F2_FLAG_TUNNEL_AND_LPBK_TYPE_1 8 255 #define F2_FLAG_TUNNEL_AND_LPBK_TYPE_0 7 256 #define F2_FLAG_ESM_KEY_SUBTYPE_0 0 257 #define F2_FLAG_RESERVED_0 109 258 259 #define FLAGS_FIELD_ABSENT 1 260 261 #define KEY_GEN_RSP_TYPE_L2_SA 1 262 #define KEY_GEN_RSP_TYPE_L2_DA 2 263 #define KEY_GEN_RSP_TYPE_SIP 3 264 #define KEY_GEN_RSP_TYPE_DIP 4 265 #define KEY_GEN_RSP_TYPE_ACL 5 266 #define KEY_GEN_RSP_TYPE_SA_OPT 6 267 268 #define KEY_GEN_OFFSET_L2 1 269 #define KEY_GEN_OFFSET_IPV4_ONLY 2 270 #define KEY_GEN_OFFSET_IPV6_64_ONLY 3 271 #define KEY_GEN_OFFSET_IPV6_128_ONLY 4 272 #define KEY_GEN_OFFSET_IPV4_SA 5 273 #define KEY_GEN_OFFSET_IPV6_128_SA 6 274 #define KEY_GEN_OFFSET_IPV6_64_SA 7 275 #define KEY_GEN_OFFSET_AFLSS0 8 276 #define KEY_GEN_OFFSET_AFLSS1 9 277 #define KEY_GEN_OFFSET_AFLSS2 10 278 #define KEY_GEN_OFFSET_AFLSS3 11 279 #define KEY_GEN_OFFSET_AFLSS0A 12 280 #define KEY_GEN_OFFSET_AFLSS1A 13 281 #define KEY_GEN_OFFSET_AFLSS2A 14 282 #define KEY_GEN_OFFSET_AFLSS1MP 15 283 #define KEY_GEN_OFFSET_FLSS0 16 284 #define KEY_GEN_OFFSET_TR2_ACL_L2C 17 285 #define KEY_GEN_OFFSET_TR2_ACL_L2C_IP4 18 286 #define KEY_GEN_OFFSET_TR2_ACL_L2C_IP6U 19 287 #define KEY_GEN_OFFSET_TR2_ACL_L2C_IP6 20 288 #define KEY_GEN_OFFSET_TR2_ACL_L2C_ONLY 21 289 #define KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SGLP 22 290 #define KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SVP 23 291 #define KEY_GEN_OFFSET_TR2_ACL_L2_7K_SGLP 24 292 #define KEY_GEN_OFFSET_TR2_ACL_L2_7K_SVP 25 293 #define KEY_GEN_OFFSET_TR2_ACL_L2_V6U_NON7K_SGLP 26 294 #define KEY_GEN_OFFSET_TR2_ACL_L2_ONLY 27 295 #define KEY_GEN_OFFSET_TR2_ACL_IP4C 28 296 #define KEY_GEN_OFFSET_TR2_ACL_IP4C_L2 29 297 #define KEY_GEN_OFFSET_TR2_ACL_IP4C_ONLY 30 298 #define KEY_GEN_OFFSET_TR2_ACL_IP4 31 299 #define KEY_GEN_OFFSET_TR2_ACL_IP4_L2 32 300 #define KEY_GEN_OFFSET_TR2_ACL_IP4_ONLY 33 301 #define KEY_GEN_OFFSET_TR2_ACL_L2IP4 34 302 #define KEY_GEN_OFFSET_TR2_ACL_L2IP4_L2 35 303 #define KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY 36 304 #define KEY_GEN_OFFSET_TR2_ACL_IP6C 37 305 #define KEY_GEN_OFFSET_TR2_ACL_IP6C_IP6U_FWD 38 306 #define KEY_GEN_OFFSET_TR2_ACL_IP6C_L2 39 307 #define KEY_GEN_OFFSET_TR2_ACL_IP6C_ONLY 40 308 #define KEY_GEN_OFFSET_TR2_ACL_IP6S 41 309 #define KEY_GEN_OFFSET_TR2_ACL_IP6S_IP6U_FWD 42 310 #define KEY_GEN_OFFSET_TR2_ACL_IP6S_L2 43 311 #define KEY_GEN_OFFSET_TR2_ACL_IP6S_ONLY 44 312 #define KEY_GEN_OFFSET_TR2_ACL_IP6F 45 313 #define KEY_GEN_OFFSET_TR2_ACL_IP6F_IP6U_FWD 46 314 #define KEY_GEN_OFFSET_TR2_ACL_IP6F_L2 47 315 #define KEY_GEN_OFFSET_TR2_ACL_IP6F_ONLY 48 316 #define KEY_GEN_OFFSET_TR2_ACL_L2IP6 49 317 #define KEY_GEN_OFFSET_TR2_ACL_L2IP6_L2 50 318 #define KEY_GEN_OFFSET_TR2_ACL_L2IP6_ONLY 51 319 /* 320 * This macro is introduced for Source Mac address based 321 * ESM lookup through VFP_POLICY_TABLE WAR purpose 322 */ 323 #define KEY_GEN_OFFSET_TR3_WAR_L2SA_ONLY 52 324 #define KEY_GEN_OFFSET_MAX 52 325 326 #define PKT_TYPE_L2 1 327 #define PKT_TYPE_IPV4 2 328 #define PKT_TYPE_IPV6 3 329 330 /* tcam forwarding behaviors */ 331 #define FWD_TYPE_L2_VLAN 1 332 #define FWD_TYPE_L2_VFI 2 333 #define FWD_TYPE_V4_BRIDGE 3 334 #define FWD_TYPE_V6_BRIDGE 4 335 #define FWD_TYPE_V4_ROUTE 5 336 #define FWD_TYPE_V6_ROUTE 6 337 338 #define SRCH_PROFILE_SRC_L3IIF_BASE 0 339 #define SRCH_PROFILE_SRC_SRC_VP_BASE 256 340 #define SRCH_PROFILE_SRC_VLAN_BASE 512 341 #define SRCH_PROFILE_SRC_VFP_BASE 768 342 #define SRCH_PROFILE_SRC_VLAN_XLAT_BASE 1024 343 #define SRCH_PROFILE_SRC_TRUNK_MAP_BASE 1280 344 345 #define SRCH_PROFILE_SRC_TRUNK_MAP_0 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 0) 346 #define SRCH_PROFILE_SRC_TRUNK_MAP_1 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 32) 347 #define SRCH_PROFILE_SRC_TRUNK_MAP_2 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 2*32) 348 #define SRCH_PROFILE_SRC_TRUNK_MAP_3 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 3*32) 349 #define SRCH_PROFILE_SRC_TRUNK_MAP_4 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 4*32) 350 #define SRCH_PROFILE_SRC_TRUNK_MAP_5 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 5*32) 351 #define SRCH_PROFILE_SRC_TRUNK_MAP_6 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 6*32) 352 #define SRCH_PROFILE_SRC_TRUNK_MAP_7 (SRCH_PROFILE_SRC_TRUNK_MAP_BASE + 7*32) 353 354 #define ET_PA_AD_L2_ENTRY 0 355 #define ET_PA_AD_L3_ENTRY_DEFIP 0 356 #define ET_PA_AD_L3_ENTRY_UCAST 1 357 358 #define SOC_MEM_KEY_EXT_L2_ENTRY_1_L2_BRIDGE 0 359 #define SOC_MEM_KEY_EXT_L2_ENTRY_1_L2_VFI 1 360 #define SOC_MEM_KEY_EXT_L2_ENTRY_2_L2_BRIDGE 0 361 #define SOC_MEM_KEY_EXT_L2_ENTRY_2_L2_VFI 1 362 #define SOC_MEM_TR3_EXT_L2_MAX_ENTRIES 1048576 363 364 /* HSP Hierarchy related constants */ 365 #define _SOC_HSP_MAX_L0_NODES 10 366 #define _SOC_HSP_VALID_L0_START 1 367 #define _SOC_HSP_VALID_L0_END 9 368 #define _SOC_HSP_MIN_QUEUE_OFFSET 0 369 #define _SOC_HSP_MAX_QUEUE_OFFSET 3 370 #define _SOC_HSP_LAST_L0_UC_START 8 371 #define _SOC_HSP_LAST_L0_MC_START 18 372 #define _SOC_HSP_LAST_L0_MAX_UC_QUEUE 2 373 #define _SOC_HSP_L0_BASE_HW_INDEX 232 374 #define _SOC_HSP_L0_PER_PORT_OFFSET 12 375 #define _SOC_HSP_NUM_UC_QUEUE 10 376 #define _SOC_HSP_NUM_MC_QUEUE 10 377 #define _SOC_HSP_LAST_L0_NUM_UC_QUEUE 2 378 #define _SOC_HSP_LAST_L0_NUM_MC_QUEUE 2 379 typedef struct _tr3_worst_fme { 380 uint8 cost0; 381 uint8 cost1; 382 uint8 cost2; 383 uint8 idx; 384 } tr3_worst_fme_t; 385 386 typedef struct soc_et_pa_xlat_ { 387 uint32 et_width; 388 uint32 ad_width; 389 uint32 entry_type; 390 uint32 l2_bulk_enable; 391 uint32 hit_bit_enable; 392 uint32 hit_bit_pa_base; 393 uint32 ad_ba; 394 uint32 ad_ra_base; 395 uint32 ad_ca; 396 } soc_et_pa_xlat_t; 397 398 extern int soc_tr3_esm_get_worst_fme(int unit); 399 extern soc_functions_t soc_triumph3_drv_funs; 400 401 #define SOC_TR3_CORE_CLOCK_UNKNOWN 0 402 #define SOC_TR3_CORE_CLOCK_315 315 403 #define SOC_TR3_CORE_CLOCK_415 415 404 #define SOC_TR3_CORE_CLOCK_450 450 405 406 extern int soc_tr3_core_clock_speed(int unit); 407 extern int soc_tr3_mem_config(int unit, int dev_id, int rev_id); 408 extern void soc_tr3_chip_func_ft_intr(void *unit_vp, void *d1, 409 void *d2, void *d3, void *d4); 410 411 extern int _soc_triumph3_mem_parity_control(int unit, soc_mem_t mem, 412 int copyno, int enable); 413 extern void soc_tr3_process_func_intr(void *unit_vp, void *d1, void *d2, 414 void *d3, void *d4); 415 extern int soc_tr3_ser_mem_clear(int unit, soc_mem_t mem); 416 417 extern void soc_tr3_blk_counter_config(int unit); 418 extern int soc_triumph3_get_egr_perq_xmt_counters_size(int unit, 419 int *num_entries); 420 extern int soc_tr3_port_config_init(int unit, uint16 dev_id); 421 extern int soc_tr3_port_lanes_set(int unit, soc_port_t port, int lanes, 422 int *old_lanes, int *mode_change); 423 extern int soc_tr3_port_lanes_get(int unit, soc_port_t port, int *lanes); 424 extern int soc_tr3_port_lanes_gen(int unit, soc_port_t port, int *lanes, 425 soc_block_type_t *pbt); 426 extern int soc_tr3_port_is_flex_port(int unit, soc_port_t port); 427 extern int soc_tr3_phy_addr_get(int unit, soc_port_t port, uint16 *int_addr); 428 extern int soc_triumph3_get_port_mapping(int unit, uint16 dev_id); 429 extern int soc_triumph3_init_port_mapping(int unit); 430 extern int soc_triumph3_init_num_cosq(int unit); 431 432 extern int soc_tr3_l2x_start(int unit, uint32 flags, sal_usecs_t interval); 433 extern int soc_tr3_l2x_stop(int unit); 434 extern int soc_tr3_l2x_running(int unit, uint32 *flags, sal_usecs_t *interval); 435 extern int soc_tr3_l2_entry_dump(void *user_data, shr_avl_datum_t *datum, 436 void *extra_data); 437 extern int soc_tr3_ext_l2_1_entry_dump(void *user_data, shr_avl_datum_t *datum, 438 void *extra_data); 439 extern int soc_tr3_ext_l2_2_entry_dump(void *user_data, shr_avl_datum_t *datum, 440 void *extra_data); 441 extern int soc_tr3_l2_attach(int unit); 442 extern int soc_tr3_l2_detach(int unit); 443 extern int soc_tr3_l2_freeze(int unit); 444 extern int soc_tr3_l2_thaw(int unit); 445 extern int soc_tr3_l2_is_frozen(int unit, int *frozen); 446 extern int soc_tr3_l2_port_age(int unit, soc_reg_t reg0, soc_reg_t reg1); 447 extern int soc_tr3_l2_hw_index(int unit, int qnum, int uc); 448 extern int soc_tr3_l2_bulk_age_start(int unit, int interval); 449 extern int soc_tr3_l2_bulk_age_stop(int unit); 450 extern void soc_tr3_l2mod_fifo_process(int unit, uint32 flags, 451 l2_mod_fifo_entry_t *entry); 452 extern int soc_tr3_l2_entry_limit_count_update(int unit); 453 extern int _soc_triumph3_esm_init_adjust_mem_size(int unit); 454 extern int soc_tr3_l3_defip_index_map(int unit, soc_mem_t mem, int index); 455 extern int soc_tr3_l3_defip_index_remap(int unit, soc_mem_t mem, int index); 456 extern int soc_tr3_l3_defip_mem_index_get(int unit, int pindex, soc_mem_t *mem); 457 extern int _soc_tr3_port_mem_blk_enabled(int unit, int blk); 458 extern int soc_triumph3_chip_reset(int unit); 459 extern int soc_tr3_lls_bmap_alloc(int unit); 460 461 /********************************************************************** 462 * MMU, COSQ related prototypes. 463 */ 464 typedef enum { 465 SOC_TR3_SCHED_MODE_UNKNOWN = 0, 466 SOC_TR3_SCHED_MODE_STRICT, 467 SOC_TR3_SCHED_MODE_WRR, 468 SOC_TR3_SCHED_MODE_WDRR 469 } soc_tr3_sched_mode_e; 470 471 typedef enum { 472 SOC_TR3_NODE_LVL_ROOT = 0, 473 SOC_TR3_NODE_LVL_L0, 474 SOC_TR3_NODE_LVL_L1, 475 SOC_TR3_NODE_LVL_L2, 476 SOC_TR3_NODE_LVL_MAX 477 } soc_tr3_node_lvl_e; 478 479 typedef enum { 480 _SOC_TR3_INDEX_STYLE_BUCKET, 481 _SOC_TR3_INDEX_STYLE_BUCKET_MODE, 482 _SOC_TR3_INDEX_STYLE_WRED, 483 _SOC_TR3_INDEX_STYLE_WRED_DROP_THRESH, 484 _SOC_TR3_INDEX_STYLE_SCHEDULER, 485 _SOC_TR3_INDEX_STYLE_PERQ_XMT, 486 _SOC_TR3_INDEX_STYLE_UCAST_DROP, 487 _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 488 _SOC_TR3_INDEX_STYLE_MCAST_QUEUE, 489 _SOC_TR3_INDEX_STYLE_EXT_UCAST_QUEUE, 490 _SOC_TR3_INDEX_STYLE_EGR_POOL, 491 _SOC_TR3_INDEX_STYLE_COUNT 492 } soc_tr3_index_style_t; 493 494 typedef struct _soc_tr3_axp_lls_config_ 495 { 496 int local_port; 497 /* Index 0 - UC; MC only or AXP3 498 * Index 1 - MC 499 * Index 2 - MC only for AXP3 500 */ 501 int base[3]; 502 int numq[3]; 503 } _soc_tr3_axp_lls_config; 504 505 extern _soc_tr3_axp_lls_config _tr3_axp_lls_config[4]; 506 507 #define _SOC_TR3_NODE_CONFIG_MEM(n) \ 508 (((n)==SOC_TR3_NODE_LVL_ROOT) ? LLS_PORT_CONFIGm : \ 509 (((n) == SOC_TR3_NODE_LVL_L0) ? LLS_L0_CONFIGm : \ 510 ((n) == SOC_TR3_NODE_LVL_L1 ? LLS_L1_CONFIGm : -1 ))) 511 512 #define _SOC_TR3_NODE_PARENT_MEM(n) \ 513 (((n)==SOC_TR3_NODE_LVL_L2) ? LLS_L2_PARENTm : \ 514 (((n) == SOC_TR3_NODE_LVL_L1) ? LLS_L1_PARENTm : \ 515 (((n) == SOC_TR3_NODE_LVL_L0) ? LLS_L0_PARENTm : -1 ))) 516 517 #define _SOC_TR3_NODE_WIEGHT_MEM(n) \ 518 (((n)==SOC_TR3_NODE_LVL_L0) ? LLS_L0_CHILD_WEIGHT_CFGm : \ 519 (((n) == SOC_TR3_NODE_LVL_L1) ? LLS_L1_CHILD_WEIGHT_CFGm : \ 520 (((n) == SOC_TR3_NODE_LVL_L2) ? LLS_L2_CHILD_WEIGHT_CFGm : -1 ))) 521 522 typedef int (*_soc_tr3_bst_hw_cb)(int unit); 523 extern int soc_tr3_set_bst_callback(int unit, _soc_tr3_bst_hw_cb cb); 524 525 typedef int (*soc_tr3_oam_handler_t)(int unit, soc_field_t fault_field); 526 typedef int (*soc_tr3_oam_ser_handler_t)(int unit, soc_mem_t mem, int index); 527 extern void soc_tr3_oam_handler_register(int unit, soc_tr3_oam_handler_t handler); 528 extern void soc_tr3_oam_ser_handler_register(int unit, 529 soc_tr3_oam_ser_handler_t handler); 530 extern int soc_tr3_oam_ser_process(int unit, soc_mem_t mem, int index); 531 532 extern int soc_tr3_temperature_monitor_get(int unit, 533 int temperature_max, 534 soc_switch_temperature_monitor_t *temperature_array, 535 int *temperature_count); 536 537 extern int soc_tr3_lls_init(int unit); 538 extern int soc_tr3_lls_port_uninit(int unit, soc_port_t port); 539 extern int soc_tr3_lls_l2_disable(int unit); 540 extern int soc_tr3_lls_reset(int unit); 541 extern int soc_tr3_lb_lls_init(int unit); 542 extern int soc_tr3_lb_lls_port_uninit(int unit, int port); 543 544 typedef int (*_soc_tr3_lls_traverse_cb)(int unit, int port, int level, 545 int hw_index, void *cookie); 546 extern int soc_tr3_port_lls_traverse(int unit, soc_port_t port, 547 _soc_tr3_lls_traverse_cb cb, void *cookie); 548 extern int _soc_tr3_invalid_parent_index(int unit, int level); 549 extern int soc_tr3_sched_weight_get(int unit, int level, int hw_index, int *weight); 550 extern int soc_tr3_sched_weight_set(int unit, int level, int index, int weight); 551 extern int soc_tr3_cosq_set_sched_parent(int unit, soc_port_t port, 552 int node_type, int hw_index, 553 int parent_hw_idx); 554 extern int 555 soc_tr3_cosq_set_sched_child_config(int unit, soc_port_t port, int level, 556 int index, int num_spri, int first_child, 557 int first_mc_child, uint32 ucmap, uint32 spmap); 558 559 extern int 560 soc_tr3_cosq_set_sched_mode(int unit, soc_port_t port, int level, int index, 561 soc_tr3_sched_mode_e mode, int weight); 562 563 extern int 564 soc_tr3_cosq_set_sched_config(int unit, soc_port_t port, 565 int level, int index, int child_index, 566 int num_spri, int first_child, 567 int first_mc_child, uint32 ucmap, uint32 spmap, 568 soc_tr3_sched_mode_e mode, int weight); 569 570 extern int 571 soc_tr3_cosq_get_sched_child_config(int unit, soc_port_t port, int level, int index, 572 int *pnum_spri, int *pfirst_child, 573 int *pfirst_mc_child, uint32 *pucmap, 574 uint32 *pspmap); 575 576 extern int 577 soc_tr3_cosq_get_sched_mode(int unit, soc_port_t port, int level, int index, 578 soc_tr3_sched_mode_e *pmode, int *weight); 579 580 extern int 581 soc_tr3_cosq_get_sched_config(int unit, soc_port_t port, 582 int level, int index, int child_index, 583 int *pnum_spri, int *pfirst_child, 584 int *pfirst_mc_child, uint32 *pucmap, 585 uint32 *pspmap, soc_tr3_sched_mode_e *pmode, 586 int *weight); 587 588 extern int soc_port_hg_capable(int unit, int port); 589 extern int soc_tr3_get_def_qbase(int unit, soc_port_t inport, int qtype, 590 int *pbase, int *pnumq); 591 extern int soc_tr3_get_mcq_count(int unit); 592 extern int soc_tr3_get_child_type(int unit, soc_port_t port, int level, 593 int *child_type); 594 extern int soc_tr3_sched_hw_index_get(int unit, int port, int lvl, int offset, 595 int *hw_index); 596 extern int soc_tr3_hsp_sched_hw_index_get(int unit, int port, int lvl, int index, 597 int offset, int *hw_index); 598 extern int soc_tr3_mmu_config_init(int unit, int test_only); 599 extern int soc_tr3_dump_port_lls(int unit, int port); 600 extern int soc_tr3_dump_port_hsp(int unit, int port); 601 extern int soc_tr3_hsp_sched_weight_set(int unit, int port, int cosq, int weight, int adjust_cos); 602 extern int soc_tr3_hsp_sched_weight_get(int unit, int port, int cosq, int *weight); 603 extern int soc_tr3_hsp_set_sched_config(int unit, soc_port_t port, int cosq, 604 soc_tr3_sched_mode_e mode, int adjust_cos); 605 extern int soc_tr3_hsp_get_sched_config(int unit, soc_port_t port, int cosq, 606 soc_tr3_sched_mode_e *mode); 607 extern int _soc_tr3_hsp_sched_weight_set(int unit, int port, int index, int cosq, int weight); 608 extern int _soc_tr3_hsp_sched_weight_get(int unit, int port, int index, int cosq, int *weight); 609 extern int _soc_tr3_hsp_set_sched_config(int unit, soc_port_t port, int index, int cosq, 610 soc_tr3_sched_mode_e mode); 611 extern int _soc_tr3_hsp_get_sched_config(int unit, soc_port_t port, int index, int cosq, 612 soc_tr3_sched_mode_e *mode); 613 /********************************************************************** 614 * ESM related prototypes. 615 */ 616 extern int soc_tr3_esm_init_read_config(int unit); 617 extern int soc_triumph3_tcam_access(int unit, int op_type, int num_inst, 618 int num_pre_nop, int num_post_nop, 619 uint32 *dbus, int *ibus, int num_bits, 620 int num_searches); 621 extern void soc_triumph3_esm_init_mem_config(int unit); 622 extern int soc_tr3_esm_get_ism_mem_size(int unit, uint32 mem_type, uint32 *size); 623 extern int soc_triumph3_esm_init(int unit); 624 extern int soc_tr3_search_ext_mem(int unit, soc_mem_t *mem, void *key, 625 int *index_ptr); 626 extern int soc_tr3_get_vbit(int unit, soc_mem_t mem, int index, int *val); 627 extern int soc_tr3_set_vbit(int unit, soc_mem_t mem, int index, int val); 628 extern int soc_tr3_nl11k_init(int unit); 629 extern int soc_tr3_esm_pkt_type_to_slice_map_set(int unit, int pkt_type, 630 int slice); 631 extern int nl_mdio_prbs_chk(int unit, uint16 mdio_portid, uint16 prbs, 632 uint32 seed, uint16 crx, uint32 enable); 633 extern int nl_mdio_prbs_gen(int unit, uint16 mdio_portid, uint16 prbs, 634 uint32 seed, uint16 crx, uint32 enable); 635 extern int nl_mdio_prbs_chk_err(int unit, uint16 mdio_portid, uint16 crx); 636 extern unsigned mdio_portid_get(int unit, unsigned dev_id); 637 extern int hwtl_find_idle_req_rsp_latency(int unit, int ptr_fme_req, 638 int test_runtime_seconds, 639 unsigned *latency_ns); 640 641 #define SET_TCAM_PARTITION_AD_INFO(part, et_w, ad_w, e_type, l2_bulk, hit_bit, \ 642 ad_flags) \ 643 do {\ 644 if (partitions[part].num_entries) {\ 645 partitions[part].ad_info.et_width = (et_w);\ 646 partitions[part].ad_info.ad_width = (ad_w);\ 647 partitions[part].ad_info.entry_type = (e_type);\ 648 partitions[part].ad_info.l2_bulk_enable = (l2_bulk);\ 649 partitions[part].ad_info.hit_bit_enable = (hit_bit);\ 650 partitions[part].flags |= (ad_flags);\ 651 }\ 652 } while (0) 653 654 #define SOC_TR3_INCR_AD_ADDR(cur_row, cur_col, cur_bank, col_decr, err_code) \ 655 do {\ 656 (cur_col) -= (col_decr);\ 657 if ((cur_col) < 0) {\ 658 /* advance to next row */\ 659 (cur_row) += (8 >> partitions[part].ad_info.et_width);\ 660 /* check if end of bank */\ 661 if (((cur_row) << 9) >= ism_bank_size[(cur_bank)]) {\ 662 (cur_bank)++;\ 663 if ((cur_bank) >= ism_bank_count) {\ 664 (err_code) = SOC_E_MEMORY;\ 665 break;\ 666 }\ 667 (cur_row) = 0;\ 668 }\ 669 (cur_col) = 11;\ 670 }\ 671 (err_code) = SOC_E_NONE;\ 672 } while (0) 673 674 #define SOC_TR3_SET_POLICY_TABLE_SIZE(table1, table2, table3, table4, table6, \ 675 policy_width, num_entries)\ 676 do {\ 677 switch ((policy_width)) {\ 678 case 1:\ 679 memState[(table1)].index_max = (num_entries);\ 680 break;\ 681 case 2:\ 682 memState[(table2)].index_max = (num_entries);\ 683 break;\ 684 case 3:\ 685 memState[(table3)].index_max = (num_entries);\ 686 break;\ 687 case 4:\ 688 memState[(table4)].index_max = (num_entries);\ 689 break;\ 690 case 6:\ 691 memState[(table6)].index_max = (num_entries);\ 692 break;\ 693 default: \ 694 /* nothing. All are set to 0 anyway at init */\ 695 break;\ 696 }\ 697 } while (0) 698 699 #define ROUND_UP_M(x, y) ((x)%(y) ? (x) + (y) - (x)%(y) : (x)) 700 701 extern int wcmod_esm_serdes_control_set(int unit, int lane, soc_phy_control_t type, 702 uint32 *value); 703 extern int wcmod_esm_serdes_control_get(int unit, int lane, soc_phy_control_t type, 704 uint32 *value); 705 extern int wcmod_esm_serdes_init(int unit); 706 extern int wcmod_esm_serdes_fifo_reset(int unit); 707 extern int wcmod_esm_serdes_decouple_prbs_set(int unit, int lane, int tx, int rx, 708 int poly, int invert); 709 extern int soc_tr3_esmif_init(int unit); 710 extern uint32 tr3_tcam_partition_order[]; 711 extern uint32 tr3_tcam_partition_order_num_entries; 712 extern uint32 tr3_tcam_dup_part_order[]; 713 extern uint32 tr3_dup_part_count; 714 715 /* 716 * block to first physical port array - used in HX4 and TR3 717 */ 718 extern int _soc_tr3_b2pp[SOC_MAX_NUM_BLKS]; 719 extern int _soc_tr3_mmu_buffer_cells[SOC_MAX_NUM_DEVICES]; 720 extern uint32 _soc_tr3_tdm_arr[]; 721 extern int _soc_tr3_tdm_size; 722 /* extern _soc_tr3_flex_tdm_inf_t _soc_tr3_flex_tdm; */ 723 724 extern int16 _tr3_wc_flex_port_speeds_1[]; 725 extern int16 _tr3_wc_flex_port_lanes_1[]; 726 extern int16 _tr3_wc_def_flex_port_speeds_1[]; 727 extern int16 _tr3_wc_flex_port_speeds_2[]; 728 extern int16 _tr3_wc_flex_port_lanes_2[]; 729 extern int16 _tr3_wc_def_flex_port_speeds_2[]; 730 extern int16 _tr3_wc_flex_port_speeds_3[]; 731 extern int16 _tr3_wc_flex_port_lanes_3[]; 732 extern int16 _tr3_wc_def_flex_port_speeds_3[]; 733 extern int16 _tr3_xc_flex_port_speeds[]; 734 extern int16 _tr3_xc_flex_port_lanes[]; 735 extern int16 _tr3_xc_def_flex_port_speeds[]; 736 737 extern int _tr3_port_config_id[SOC_MAX_NUM_DEVICES]; 738 extern int _tr3_tdm_opp_spacing[SOC_MAX_NUM_DEVICES]; 739 #define _MAX_TR3_FLEX_PORT_GROUPS 20 /* Total num of XC, WC -1 */ 740 typedef struct { 741 uint16 dev_id; 742 int16 port_groups; 743 int16 ports[_MAX_TR3_FLEX_PORT_GROUPS]; 744 } _soc_tr3_flex_port_data_t; 745 extern _soc_tr3_flex_port_data_t _tr3_flex_port_data[SOC_MAX_NUM_DEVICES]; 746 747 extern int _soc_tr3_mmu_init(int unit); 748 extern int _soc_tr3_misc_init(int unit); 749 750 typedef struct { 751 uint8 valid; 752 int16 flex_port_groups[_MAX_TR3_FLEX_PORT_GROUPS]; 753 int16 *flex_port_speeds[_MAX_TR3_FLEX_PORT_GROUPS]; 754 int16 *def_flex_port_speeds[_MAX_TR3_FLEX_PORT_GROUPS]; 755 int16 *flex_port_lanes[_MAX_TR3_FLEX_PORT_GROUPS]; 756 } _soc_tr3_flex_port_inf_t; 757 758 typedef struct { 759 uint8 valid; 760 uint16 cells_per_row[_MAX_TR3_FLEX_PORT_GROUPS]; /* Represents one cycle (of repetitions) */ 761 uint16 base_slot[_MAX_TR3_FLEX_PORT_GROUPS]; /* First slot's location in a cycle */ 762 uint16 cell_offset[_MAX_TR3_FLEX_PORT_GROUPS]; /* Offset between slots in a cycle */ 763 } _soc_tr3_flex_tdm_inf_t; 764 765 extern _soc_tr3_flex_tdm_inf_t _soc_tr3_flex_tdm; 766 extern _soc_tr3_flex_port_inf_t _tr3_flex_port_inf[SOC_MAX_NUM_DEVICES]; 767 extern int _soc_tr3_port_speed_max[]; 768 769 extern char *_soc_hx4_ser_hwmem_base_info[]; 770 771 /* defines for bits in the ppa_info data word */ 772 #define _SOC_TR3_L2E_VP 0x80000000 /* Used for virtual-ports */ 773 #define _SOC_TR3_L2E_VALID 0x40000000 774 #define _SOC_TR3_L2E_STATIC 0x20000000 775 #define _SOC_TR3_L2E_T 0x10000000 776 777 #define _SOC_TR3_L2E_VLAN_MASK 0xfff 778 #define _SOC_TR3_L2E_VLAN_SHIFT 16 779 #define _SOC_TR3_L2E_TRUNK_MASK 0xffff 780 #define _SOC_TR3_L2E_TRUNK_SHIFT 0 781 #define _SOC_TR3_L2E_MOD_MASK 0xff 782 #define _SOC_TR3_L2E_MOD_SHIFT 8 783 #define _SOC_TR3_L2E_PORT_MASK 0xff 784 #define _SOC_TR3_L2E_PORT_SHIFT 0 785 #define _SOC_TR3_L2E_DESTINATION_MASK 0xff /* Used for virtual-ports */ 786 #define _SOC_TR3_L2E_DESTINATION_SHIFT 0 /* Used for virtual-ports */ 787 788 789 typedef struct _soc_tr3_l2e_ppa_info_s { 790 uint32 data; 791 sal_mac_addr_t mac; 792 } _soc_tr3_l2e_ppa_info_t; 793 794 typedef struct _soc_tr3_l2e_ppa_vlan_s { 795 int vlan_min[VLAN_ID_MAX + 1]; 796 int vlan_max[VLAN_ID_MAX + 1]; 797 } _soc_tr3_l2e_ppa_vlan_t; 798 799 typedef enum soc_tr3_drop_limit_alpha_value_e { 800 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 801 dynamic threshold */ 802 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 803 dynamic threshold */ 804 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 805 dynamic threshold */ 806 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 807 dynamic threshold */ 808 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 809 dynamic threshold */ 810 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 811 dynamic threshold */ 812 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 813 threshold */ 814 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 815 threshold */ 816 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 817 threshold */ 818 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 819 threshold */ 820 SOC_TR3_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 821 } soc_tr3_drop_limit_alpha_value_t; 822 823 extern int soc_triumph3_ext_l2_entry_update(int unit, soc_mem_t mem, int index, 824 void *entry); 825 826 #define _SOC_TR3_MGMT_PHY_PORT 37 827 #define _SOC_HX4_MGMT_PHY_PORT 49 828 #define _SOC_HX4_XMAC_FIFO_CHK_PKT_SZ 9216 829 #define _SOC_HX4_FIFO_CHK_MAX_PORTS 86 830 831 extern 832 int _soc_tr3_ur_port_reset(int unit, int num_ports, soc_port_t port, 833 soc_block_type_t pbt); 834 extern 835 int _soc_hx4_xmac_cclk_config(int unit); 836 837 extern int soc_tr3_esm_recovery_start(int unit); 838 extern int soc_tr3_esm_recovery_stop(int unit); 839 extern int 840 soc_tr3_mmu_config_shared_buf_recalc(int unit, uint32 spid, int shared_size, 841 int flags); 842 int soc_tr3_mmu_get_shared_size(int unit, int *shared_size); 843 844 #if defined(SER_TR_TEST_SUPPORT) 845 extern soc_error_t 846 soc_tr3_ser_error_injection_support (int unit, soc_mem_t mem, 847 int pipe); 848 extern soc_error_t 849 soc_tr3_ser_inject_error (int unit, uint32 flags, soc_mem_t mem, 850 int pipe_target, int block, int index); 851 extern soc_error_t 852 soc_tr3_ser_test_mem(int unit, soc_mem_t mem, _soc_ser_test_t test_type, 853 int cmd); 854 extern soc_error_t 855 soc_tr3_ser_test (int unit, _soc_ser_test_t test_type); 856 857 #endif /*defined(SER_TR_TEST_SUPPORT*/ 858 859 extern int soc_tr3_lls_sched_init(int unit); 860 extern int soc_tr3_mmu_register_store(int unit); 861 extern int soc_tr3_mmu_register_restore(int unit); 862 extern int soc_tr3_mmu_store_alloc(int unit); 863 extern void soc_tr3_mmu_store_free(int unit); 864 extern int soc_tr3_mmu_memory_store(int unit); 865 extern int soc_tr3_mmu_memory_restore(int unit); 866 extern int soc_tr3_mmu_init_restore(int unit); 867 868 extern soc_pbmp_t 869 soc_tr3_get_control_port_bitmap(int unit); 870 #endif /* !_SOC_TRIUMPH3_H_ */