trident3.h (53052B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: trident3.h 8 */ 9 10 #ifndef _SOC_TRIDENT3_H_ 11 #define _SOC_TRIDENT3_H_ 12 13 #include <soc/drv.h> 14 #include <soc/tomahawk.h> 15 #include <soc/trident3_tdm.h> 16 17 /* **************** TDM-related Macors and structs adopted from Tomahawk ---start************ */ 18 /* Device port */ 19 /* 64 General device port + 1 CPU/Mng + 1 Loopback*/ 20 #define _TD3_TDM_GDEV_PORTS_PER_PIPE 64 21 #define _TD3_TDM_DEV_PORTS_PER_PIPE (_TD3_TDM_GDEV_PORTS_PER_PIPE + 2) 22 #define _TD3_TDM_DEV_PORTS_PER_DEV \ 23 (_TD3_TDM_DEV_PORTS_PER_PIPE * TRIDENT3_TDM_PIPES_PER_DEV) 24 /* MMU port */ 25 #define _TD3_TDM_MMU_PORTS_OFFSET_PER_PIPE 64 26 #define _TD3_TDM_MMU_PORTS_PER_DEV (64 * 2) 27 /* ------------------------------------------------- */ 28 #define _TD3_TDM_LENGTH 512 29 #define _TD3_PKT_SCH_LENGTH 160 30 #define _TD3_TDM_LR_SPEED_CLASS_MAX 4 31 #define _TD3_TDM_OS_SPEED_CLASS_MAX 5 32 33 /* **************** TDM-related Macors and structs adopted from Tomahawk ---end************ */ 34 35 extern int soc_td3_mmu_config_shared_buf_recalc(int unit, int res, int thdi_shd, 36 int thdo_db_shd, int thdo_qe_shd, 37 int post_update); 38 #define SOC_TD3_MMU_BASE_TYPE_IPORT 0 39 #define SOC_TD3_MMU_BASE_TYPE_EPORT 1 40 #define SOC_TD3_MMU_BASE_TYPE_IPIPE 2 41 #define SOC_TD3_MMU_BASE_TYPE_EPIPE 3 42 #define SOC_TD3_MMU_BASE_TYPE_CHIP 4 43 #define SOC_TD3_MMU_BASE_TYPE_XPE 5 44 #define SOC_TD3_MMU_BASE_TYPE_SLICE 6 45 #define SOC_TD3_MMU_BASE_TYPE_LAYER 7 46 47 #define SOC_TD3_MEM_CHK_TCAM_GLOBAL_UNIQUE_MODE(mem) \ 48 (mem == SRC_COMPRESSIONm || mem == DST_COMPRESSIONm || \ 49 mem == FP_UDF_TCAMm || mem == VFP_TCAMm || \ 50 mem == IFP_LOGICAL_TABLE_SELECTm || \ 51 mem == EXACT_MATCH_LOGICAL_TABLE_SELECTm || \ 52 mem == EFP_TCAMm || mem == IFP_TCAMm || mem == IFP_TCAM_WIDEm) \ 53 54 #define CCLK_FREQ_1700MHZ 1700 55 #define CCLK_FREQ_1525MHZ 1525 56 #define CCLK_FREQ_1012MHZ 1012 57 58 #define SOC_TD3_FP_SLICE_ENTRY_NARROW_VIEW 1536 59 #define SOC_TD3_FP_SLICE_ENTRY_WIDE_VIEW 768 60 61 extern int soc_td3_rx_etype_niv[]; 62 extern int soc_td3_rx_etype_pe[]; 63 extern uint32 soc_td3_ip_pipe_fifo_bmask[SOC_MAX_NUM_DEVICES][2]; 64 extern uint32 soc_td3_temp_mon_mask[SOC_MAX_NUM_DEVICES]; 65 66 extern soc_functions_t soc_trident3_drv_funs; 67 extern int soc_trident3_tcam_mode_set(int unit, int stage, int mode); 68 extern int soc_trident3_tcam_mode_get(int unit, soc_mem_t mem, int *mode); 69 extern int soc_td3_ifp_slice_mode_check(int unit, soc_mem_t mem, int slice, int *slice_skip); 70 71 extern void soc_td3_hgoe_feature_update(int unit); 72 73 extern int soc_trident3_check_cache_skip(int unit, soc_mem_t mem); 74 extern void soc_trident3_pipe_map_get(int unit, uint32 *pipe_map); 75 extern int soc_trident3_pipe_select(int unit, int egress, int pipe); 76 extern void soc_trident3_vlan_xlate_mem_remap(soc_mem_t *mem, int *index); 77 extern int soc_trident3_l3_memwr_parity_check(int unit, soc_mem_t mem, 78 int disable); 79 extern int soc_td3_parity_bit_enable(int unit, soc_reg_t enreg, 80 soc_mem_t enmem, soc_field_t enfld, 81 int enfld_position, int enable); 82 extern int soc_trident3_check_cache_skip(int unit, soc_mem_t mem); 83 extern int soc_trident3_ser_enable_parity_table_all(int unit, int enable); 84 extern int 85 soc_trident3_ser_enable_parity_table(int unit, int type, void *info, int enable); 86 extern int soc_trident3_tcam_ser_init(int unit); 87 extern int soc_trident3_ser_enable_all(int unit, int enable); 88 extern void soc_trident3_ser_fail(int unit); 89 extern void soc_trident3_ser_error(void *unit_vp, void *d1, void *d2, 90 void *d3, void *d4); 91 extern int soc_trident3_mem_ser_control(int unit, soc_mem_t mem, 92 int copyno, int enable); 93 extern int soc_trident3_ifp_slice_mode_hw_get(int unit, int pipe, int slice_num, 94 int *slice_type, int *slice_enabled); 95 extern int soc_trident3_mem_cpu_write_control(int unit, soc_mem_t mem, int copyno, 96 int enable, int *orig_enable); 97 extern int soc_trident3_reg_cpu_write_control(int unit, int enable); 98 extern int soc_trident3_ser_mem_clear(int unit, soc_mem_t mem); 99 extern void soc_trident3_ser_register(int unit); 100 extern int soc_trident3_mem_config(int unit); 101 extern int soc_trident3_num_cosq_init(int unit); 102 extern int soc_trident3_num_cosq_init_port(int unit, int port); 103 extern int soc_trident3_port_map_validity_check(int unit, int port, int phy_port); 104 extern int soc_trident3_port_config_init(int unit, uint16 dev_id); 105 extern int soc_trident3_chip_reset(int unit); 106 extern int soc_trident3_port_reset(int unit); 107 extern int soc_trident3_xpe_base_index_check(int unit, int base_type, int xpe, 108 int base_index, char *msg); 109 extern int soc_trident3_xpe_reg32_set(int unit, soc_reg_t reg, int xpe, 110 int base_index, int index, uint32 data); 111 extern int soc_trident3_xpe_reg32_get(int unit, soc_reg_t reg, int xpe, 112 int base_index, int index, uint32 *data); 113 extern int soc_trident3_xpe_reg_set(int unit, soc_reg_t reg, int xpe, 114 int base_index, int index, uint64 data); 115 extern int soc_trident3_xpe_reg_get(int unit, soc_reg_t reg, int xpe, 116 int base_index, int index, uint64 *data); 117 #if 0 118 extern int soc_trident3_xpe_mem_write(int unit, soc_mem_t mem, int xpe, 119 int base_index, int copyno, 120 int offset_in_section, void *entry_data); 121 extern int soc_trident3_xpe_mem_read(int unit, soc_mem_t mem, int xpe, 122 int base_index, int copyno, 123 int offset_in_section, void *entry_data); 124 #endif 125 extern int soc_trident3_mem_xpe_pipe_check(int unit, soc_mem_t mem, 126 int xpe, int pipe); 127 extern int soc_trident3_mem_basetype_get(int unit, soc_mem_t mem); 128 extern int soc_trident3_mem_is_xpe(int unit, soc_mem_t mem); 129 extern int soc_trident3_sc_base_index_check(int unit, int base_type, int sc, 130 int base_index, char *msg); 131 extern int soc_trident3_sc_reg32_set(int unit, soc_reg_t reg, int sc, 132 int base_index, int index, uint32 data); 133 extern int soc_trident3_sc_reg32_get(int unit, soc_reg_t reg, int sc, 134 int base_index, int index, uint32 *data); 135 extern int soc_trident3_sc_reg_set(int unit, soc_reg_t reg, int sc, 136 int base_index, int index, uint64 data); 137 extern int soc_trident3_sc_reg_get(int unit, soc_reg_t reg, int sc, 138 int base_index, int index, uint64 *data); 139 extern int soc_trident3_sed_reg32_set(int unit, soc_reg_t reg, int sed, 140 int base_index, int index, uint32 data); 141 extern int soc_trident3_sed_reg32_get(int unit, soc_reg_t reg, int sed, 142 int base_index, int index, uint32 *data); 143 extern int soc_trident3_sed_reg_set(int unit, soc_reg_t reg, int sed, 144 int base_index, int index, uint64 data); 145 extern int soc_trident3_sed_reg_get(int unit, soc_reg_t reg, int sed, 146 int base_index, int index, uint64 *data); 147 #if 0 148 extern int soc_trident3_sc_mem_write(int unit, soc_mem_t mem, int sc, 149 int base_index, int copyno, 150 int offset_in_section, void *entry_data); 151 extern int soc_trident3_sc_mem_read(int unit, soc_mem_t mem, int sc, 152 int base_index, int copyno, 153 int offset_in_section, void *entry_data); 154 #endif 155 extern uint32 _soc_td3_piped_mem_index(int unit, soc_port_t port, 156 soc_mem_t mem, int arr_off); 157 extern soc_mem_t 158 _soc_trident3_pmem(int unit, int port, soc_mem_t mema, soc_mem_t memb); 159 160 extern int soc_td3_l2_bulk_age_start(int unit, int interval); 161 extern int soc_td3_l2_bulk_age_stop(int unit); 162 extern int soc_trident3_port_obm_info_get(int unit, soc_port_t port, 163 int *obm_id, int *lane); 164 165 extern int soc_trident3_show_ring_osc(int unit); 166 167 extern soc_error_t 168 soc_td3_subsidiary_ports_get(int unit, soc_port_t port, soc_pbmp_t *pbmp); 169 170 /* Counter */ 171 extern int soc_counter_trident3_status_enable(int unit, int enable); 172 extern int soc_counter_trident3_non_dma_init(int unit, int nports, 173 int non_dma_start_index, 174 int *non_dma_entries); 175 extern int soc_counter_trident3_get_info(int unit, soc_port_t port, 176 soc_reg_t id, int *base_index, 177 int *num_entries); 178 extern int soc_counter_trident3_eviction_init(int unit); 179 extern int soc_counter_trident3_eviction_enable(int unit, int enable); 180 extern void soc_counter_trident3_eviction_flags_update(int unit, 181 uint32 flags, 182 int enable); 183 extern int soc_counter_trident3_generic_get_info(int unit, soc_ctr_control_info_t ctrl_info, 184 soc_reg_t id, int *base_index, int *num_entries); 185 extern int 186 soc_counter_trident3_get_child_dma_by_idx(int unit, 187 soc_counter_non_dma_t *parent, int idx, soc_counter_non_dma_t **child); 188 extern int 189 soc_counter_trident3_get_child_dma(int unit, soc_reg_t id, 190 soc_ctr_control_info_t ctrl_info, 191 soc_counter_non_dma_t **child_dma); 192 extern int 193 soc_counter_trident3_dma_flags_update(int unit, soc_counter_non_dma_t *ctr_dma, 194 uint32 flags, int val); 195 extern int 196 soc_counter_td3_extra_sflow_ctrs_init(int unit, 197 soc_counter_non_dma_t *non_dma_parent, 198 soc_counter_non_dma_t *non_dma_extra, 199 uint32 extra_ctr_ct, 200 int *total_entries); 201 extern int 202 soc_counter_trident3_extra_ctrs_init(int unit, soc_reg_t id, 203 soc_counter_non_dma_t *non_dma_parent, 204 soc_counter_non_dma_t *non_dma_extra, 205 uint32 extra_ctr_ct, 206 int *total_entries); 207 208 extern int soc_td3_flow_based_udf_enable(int unit); 209 210 typedef struct _soc_trident3_tdm_pblk_info_s { 211 int pblk_hpipe_num; /* half pipeline info */ 212 int pblk_cal_idx; /* index to 8 HPIPEx_PBLK_CALENDARr */ 213 }_soc_trident3_tdm_pblk_info_t; 214 215 typedef struct _soc_trident3_tdm_pipe_s { 216 int idb_tdm[_TD3_TDM_LENGTH]; 217 int mmu_tdm[_TD3_TDM_LENGTH]; 218 int ovs_tdm[TRIDENT3_OVS_HPIPE_COUNT_PER_PIPE][TRIDENT3_TDM_OVS_GROUPS_PER_HPIPE][TRIDENT3_TDM_OVS_GROUP_LENGTH]; 219 int pkt_shaper_tdm[TRIDENT3_OVS_HPIPE_COUNT_PER_PIPE][_TD3_PKT_SCH_LENGTH]; 220 } _soc_trident3_tdm_pipe_t; 221 222 typedef struct _soc_trident3_tdm_temp_s { 223 _soc_trident3_tdm_pipe_t tdm_pipe[TRIDENT3_TDM_PIPES_PER_DEV]; 224 _soc_trident3_tdm_pblk_info_t pblk_info[TRIDENT3_TDM_PHY_PORTS_PER_DEV]; 225 int port_ratio[TRIDENT3_TDM_PBLKS_PER_DEV]; 226 int ovs_ratio_x1000[TRIDENT3_TDM_PIPES_PER_DEV][TRIDENT3_OVS_HPIPE_COUNT_PER_PIPE]; 227 228 } _soc_trident3_tdm_temp_t; 229 230 typedef struct soc_td3_port_lanes_s { 231 int port_base; /* Base port number */ 232 int lanes; /* New number of lanes */ 233 int cur_lanes; /* Current number of lanes */ 234 int mode; /* New mode */ 235 int cur_mode; /* Current mode */ 236 int class; /* Speed class for new group */ 237 int cur_class; /* Speed class for current group */ 238 int idb_group; /* New IDB oversub group number */ 239 int cur_idb_group; /* Current IDB oversub group number */ 240 int idb_slots[4]; /* New IDB oversub group slot number */ 241 int cur_idb_slots[4]; /* Current IDB oversub group slot number */ 242 int cur_idb_empty; /* Current IDB oversub group become empty after flex */ 243 int mmu_group; /* New MMU oversub group number */ 244 int cur_mmu_group; /* Current MMU oversub group number */ 245 int mmu_slots[4]; /* New MMU oversub group slot number */ 246 int cur_mmu_slots[4]; /* Current MMU oversub group slot number */ 247 int cur_mmu_empty; /* Current MMU oversub group become empty after flex */ 248 int bindex; /* Base port subport index */ 249 int oversub; /* Oversub status for the ports */ 250 int phy_ports_len; /* Length of valid entries in phy_ports array */ 251 int phy_ports[3]; /* Array of added/removed physical port number */ 252 } soc_td3_port_lanes_t; 253 254 extern void soc_trident3_port_ratio_get(int unit, int clport, int *mode); 255 256 extern int soc_trident3_port_lanes_validate(int unit, 257 soc_td3_port_lanes_t *lanes_ctrl); 258 extern int soc_trident3_port_lanes_set(int unit, 259 soc_td3_port_lanes_t *lanes_ctrl); 260 extern int soc_trident3_port_lanes_get(int unit, soc_port_t port_base, 261 int *cur_lanes); 262 extern int soc_trident3_port_speed_update(int unit, soc_port_t port, int speed); 263 264 typedef int (*_soc_td3_bst_hw_cb)(int unit); 265 extern int soc_td3_set_bst_callback(int unit, _soc_td3_bst_hw_cb cb); 266 extern int _soc_td3_process_mmu_bst(int unit, int xpe, soc_field_t field); 267 268 269 #define SOC_TD3_MMU_PORT(u, p) _soc_td3_mmu_port((u),(p)) 270 #define SOC_TD3_MMU_PIPED_MEM_INDEX(u,p,m,off) \ 271 _soc_td3_piped_mem_index((u),(p),(m),(off)) 272 #define SOC_TD3_PMEM(u, p, m1, m2) _soc_trident3_pmem((u), (p), (m1), (m2)) 273 274 typedef enum { 275 SOC_TD3_TS_PLL, 276 SOC_TD3_BS_PLL0, 277 SOC_TD3_BS_PLL1, 278 SOC_TD3_PLL_INVALID 279 } soc_td3_plls_e; 280 281 enum soc_td3_port_ratio_e { 282 SOC_TD3_PORT_RATIO_SINGLE, 283 SOC_TD3_PORT_RATIO_DUAL_1_1, 284 SOC_TD3_PORT_RATIO_DUAL_2_1, 285 SOC_TD3_PORT_RATIO_DUAL_1_2, 286 SOC_TD3_PORT_RATIO_TRI_023_2_1_1, 287 SOC_TD3_PORT_RATIO_TRI_023_4_1_1, 288 SOC_TD3_PORT_RATIO_TRI_012_1_1_2, 289 SOC_TD3_PORT_RATIO_TRI_012_1_1_4, 290 SOC_TD3_PORT_RATIO_QUAD, 291 SOC_TD3_PORT_RATIO_COUNT 292 }; 293 294 enum soc_td3_port_mode_e { 295 /* WARNING: values given match hardware register; do not modify */ 296 SOC_TD3_PORT_MODE_QUAD = 0, 297 SOC_TD3_PORT_MODE_TRI_012 = 1, 298 SOC_TD3_PORT_MODE_TRI_023 = 2, 299 SOC_TD3_PORT_MODE_DUAL = 3, 300 SOC_TD3_PORT_MODE_SINGLE = 4 301 }; 302 303 extern int soc_trident3_hash_init(int unit); 304 305 enum td3_l2_hash_key_type_e { 306 /* WARNING: values given match hardware register; do not modify */ 307 TD3_L2_HASH_KEY_TYPE_BRIDGE = 0, 308 TD3_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 309 TD3_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 310 TD3_L2_HASH_KEY_TYPE_VFI = 3, 311 TD3_L2_HASH_KEY_TYPE_VIF = 4, 312 TD3_L2_HASH_KEY_TYPE_TRILL_NONUC_ACCESS = 5, 313 TD3_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_LONG = 6, 314 TD3_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_SHORT = 7, 315 TD3_L2_HASH_KEY_TYPE_BFD = 8, 316 TD3_L2_HASH_KEY_TYPE_PE_VID = 9, 317 TD3_L2_HASH_KEY_TYPE_FCOE_ZONE = 10, 318 TD3_L2_HASH_KEY_TYPE_COUNT 319 }; 320 321 enum td3_l3_hash_key_type_e { 322 /* WARNING: values given match hardware register; do not modify */ 323 TD3_L3_HASH_KEY_TYPE_V4UC = 0, 324 TD3_L3_HASH_KEY_TYPE_V4UC_EXT = 0, 325 TD3_L3_HASH_KEY_TYPE_V6UC = 2, 326 TD3_L3_HASH_KEY_TYPE_V6UC_EXT = 2, 327 TD3_L3_HASH_KEY_TYPE_V4MC = 4, 328 TD3_L3_HASH_KEY_TYPE_V6MC = 5, 329 TD3_L3_HASH_KEY_TYPE_TRILL = 8, 330 TD3_L3_HASH_KEY_TYPE_FCOE_DOMAIN = 12, 331 TD3_L3_HASH_KEY_TYPE_FCOE_DOMAIN_EXT = 12, 332 TD3_L3_HASH_KEY_TYPE_FCOE_HOST = 14, 333 TD3_L3_HASH_KEY_TYPE_FCOE_HOST_EXT = 14, 334 TD3_L3_HASH_KEY_TYPE_FCOE_SOURCE_MAP = 16, 335 TD3_L3_HASH_KEY_TYPE_FCOE_SOURCE_MAP_EXT = 16, 336 TD3_L3_HASH_KEY_TYPE_DST_NAT = 18, 337 TD3_L3_HASH_KEY_TYPE_DST_NAPT = 19, 338 TD3_L3_HASH_KEY_TYPE_L2_IPV4_MULTICAST = 20, 339 TD3_L3_HASH_KEY_TYPE_L2VP_IPV4_MULTICAST = 21, 340 TD3_L3_HASH_KEY_TYPE_L2_IPV6_MULTICAST = 22, 341 TD3_L3_HASH_KEY_TYPE_L2VP_IPV6_MULTICAST = 23, 342 TD3_L3_HASH_KEY_TYPE_COUNT 343 }; 344 345 enum td3_fpem_hash_key_type_e { 346 /* WARNING: values given match hardware register; do not modify */ 347 TD3_FPEM_HASH_KEY_TYPE_128B = 0, 348 TD3_FPEM_HASH_KEY_TYPE_160B = 1, 349 TD3_FPEM_HASH_KEY_TYPE_320B = 2, 350 TD3_FPEM_HASH_KEY_TYPE_COUNT 351 }; 352 353 enum td3_mpls_hash_key_type_e { 354 /* WARNING: values given match hardware register; do not modify */ 355 TD3_MPLS_HASH_KEY_TYPE_MPLS = 0, 356 TD3_MPLS_HASH_KEY_TYPE_MIM_NVP = 1, 357 TD3_MPLS_HASH_KEY_TYPE_MIM_ISID = 2, 358 TD3_MPLS_HASH_KEY_TYPE_MIM_ISID_SVP = 3, 359 TD3_MPLS_HASH_KEY_TYPE_L2GRE_VPNID_SIP = 4, 360 TD3_MPLS_HASH_KEY_TYPE_TRILL = 5, 361 TD3_MPLS_HASH_KEY_TYPE_L2GRE_SIP = 6, 362 TD3_MPLS_HASH_KEY_TYPE_L2GRE_VPNID = 7, 363 TD3_MPLS_HASH_KEY_TYPE_VXLAN_SIP = 8, 364 TD3_MPLS_HASH_KEY_TYPE_VXLAN_VPNID = 9, 365 TD3_MPLS_HASH_KEY_TYPE_VXLAN_VPNID_SIP = 10, 366 TD3_MPLS_HASH_KEY_TYPE_VXLAN_FLEX_IPV4_DIP = 12, 367 TD3_MPLS_HASH_KEY_TYPE_COUNT 368 }; 369 370 enum td3_vlxlt_hash_key_type_e { 371 /* WARNING: values given match hardware register; do not modify */ 372 TD3_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 373 TD3_VLXLT_HASH_KEY_TYPE_OTAG = 1, 374 TD3_VLXLT_HASH_KEY_TYPE_ITAG = 2, 375 TD3_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 376 TD3_VLXLT_HASH_KEY_TYPE_OVID = 4, 377 TD3_VLXLT_HASH_KEY_TYPE_IVID = 5, 378 TD3_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 379 TD3_VLXLT_HASH_KEY_TYPE_HPAE = 7, 380 TD3_VLXLT_HASH_KEY_TYPE_VIF = 8, 381 TD3_VLXLT_HASH_KEY_TYPE_VIF_VLAN = 9, 382 TD3_VLXLT_HASH_KEY_TYPE_VIF_CVLAN = 10, 383 TD3_VLXLT_HASH_KEY_TYPE_VIF_OTAG = 11, 384 TD3_VLXLT_HASH_KEY_TYPE_VIF_ITAG = 12, 385 TD3_VLXLT_HASH_KEY_TYPE_L2GRE_DIP = 13, 386 TD3_VLXLT_HASH_KEY_TYPE_VLAN_MAC_PORT = 14, 387 TD3_VLXLT_HASH_KEY_TYPE_IVID_OVID_VSAN = 15, 388 TD3_VLXLT_HASH_KEY_TYPE_IVID_VSAN = 16, 389 TD3_VLXLT_HASH_KEY_TYPE_OVID_VSAN = 17, 390 TD3_VLXLT_HASH_KEY_TYPE_VXLAN_DIP = 18, 391 TD3_VLXLT_HASH_KEY_TYPE_VXLAN_FLEX_VNID = 19, 392 TD3_VLXLT_HASH_KEY_TYPE_VXLAN_FLEX_SIP_VNID = 28, 393 TD3_VLXLT_HASH_KEY_TYPE_COUNT 394 }; 395 396 enum td3_evlxlt_hash_key_type_e { 397 /* WARNING: values given match hardware register; do not modify */ 398 TD3_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE = 0, 399 TD3_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE_DVP = 1, 400 TD3_EVLXLT_HASH_KEY_TYPE_FCOE_XLATE = 2, 401 TD3_EVLXLT_HASH_KEY_TYPE_ISID_XLATE = 3, 402 TD3_EVLXLT_HASH_KEY_TYPE_ISID_DVP_XLATE = 4, 403 TD3_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI = 5, 404 TD3_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI_DVP = 6, 405 TD3_EVLXLT_HASH_KEY_TYPE_FCOE_XLATE_DVP = 7, 406 TD3_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI = 8, 407 TD3_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI_DVP = 9, 408 TD3_ELVXLT_HASH_KEY_TYPE_VFI_DVP_GROUP = 10, 409 TD3_ELVXLT_HASH_KEY_TYPE_VRF_MAPPING = 11, 410 TD3_ELVXLT_HASH_KEY_TYPE_VLAN_XLATE_VFI = 12, 411 TD3_VELXLT_HASH_KEY_TYPE_COUNT 412 }; 413 414 enum td3_l3_hash_data_type_e { 415 /* WARNING: values given match hardware register; do not modify */ 416 TD3_L3_HASH_DATA_TYPE_V4UC = 0, 417 TD3_L3_HASH_DATA_TYPE_V4UC_EXT = 1, 418 TD3_L3_HASH_DATA_TYPE_V6UC = 2, 419 TD3_L3_HASH_DATA_TYPE_V6UC_EXT = 3, 420 TD3_L3_HASH_DATA_TYPE_V4MC = 4, 421 TD3_L3_HASH_DATA_TYPE_V6MC = 5, 422 TD3_L3_HASH_DATA_TYPE_TRILL = 8, 423 TD3_L3_HASH_DATA_TYPE_FCOE_DOMAIN = 12, 424 TD3_L3_HASH_DATA_TYPE_FCOE_DOMAIN_EXT = 13, 425 TD3_L3_HASH_DATA_TYPE_FCOE_HOST = 14, 426 TD3_L3_HASH_DATA_TYPE_FCOE_HOST_EXT = 15, 427 TD3_L3_HASH_DATA_TYPE_FCOE_SOURCE_MAP = 16, 428 TD3_L3_HASH_DATA_TYPE_FCOE_SOURCE_MAP_EXT = 17, 429 TD3_L3_HASH_DATA_TYPE_DST_NAT = 18, 430 TD3_L3_HASH_DATA_TYPE_DST_NAPT = 19, 431 TD3_L3_HASH_DATA_TYPE_V4L2MC = 20, 432 TD3_L3_HASH_DATA_TYPE_V4L2VPMC = 21, 433 TD3_L3_HASH_DATA_TYPE_V6L2MC = 22, 434 TD3_L3_HASH_KEY_TYPE_V6L2VPMC = 23, 435 TD3_L3_HASH_DATA_TYPE_COUNT 436 }; 437 438 typedef int (*_soc_td3_tcb_hw_cb)(int unit); 439 extern int soc_td3_set_tcb_callback(int unit, _soc_td3_tcb_hw_cb cb); 440 extern int _soc_td3_process_mmu_tcb(int unit, int xpe, soc_field_t field); 441 442 /* Maximum Flex Key Width for each hash table in TD3 */ 443 444 #define SOC_TD3_L2_MAX_KEY_WIDTH 100 445 #define SOC_TD3_L3_MAX_KEY_WIDTH 415 446 #define SOC_TD3_EXACT_MATCH_MAX_KEY_WIDTH 322 447 #define SOC_TD3_MPLS_MAX_KEY_WIDTH 199 448 #define SOC_TD3_VLAN_XLATE_MAX_KEY_WIDTH 199 449 #define SOC_TD3_EGR_VLAN_XLATE_MAX_KEY_WIDTH 199 450 #define SOC_TD3_ING_DNAT_ADDRESS_TYPE_MAX_KEY_WIDTH 48 451 #define SOC_TD3_SUBPORT_ID_SGPP_MAP_MAX_KEY_WIDTH 24 452 #define SOC_TD3_ING_VP_VLAN_MEMBERSHIP_MAX_KEY_WIDTH 37 453 #define SOC_TD3_EGR_VP_VLAN_MEMBERSHIP_MAX_KEY_WIDTH 37 454 455 extern int soc_trident3_uft_uat_config(int unit); 456 457 extern int soc_td3_shared_hash_mem_bucket_read(int unit, int ent, 458 int key_type, int *width, 459 soc_mem_t base_mem, soc_mem_t *mem, 460 void *bkt_entry, void *entry); 461 extern int soc_td3_hash_mem_status_get(int unit, soc_mem_t mem, 462 void* entry, uint32 *valid); 463 extern int soc_trident3_iuat_sizing(int unit, int iuat_entries, 464 int *iuat_16k, int *iuat_8k); 465 extern int soc_trident3_hash_bank_count_get(int unit, soc_mem_t mem, 466 int *num_banks); 467 extern int soc_trident3_hash_bank_bitmap_get(int unit, soc_mem_t mem, 468 uint32 *bitmap); 469 extern int soc_td3_hash_bank_phy_bitmap_get(int unit, soc_mem_t mem, 470 uint32 *bitmap); 471 extern int soc_td3_hash_bank_number_get(int unit, soc_mem_t mem, 472 int seq_num, int *bank_num); 473 extern int soc_td3_hash_seq_number_get(int unit, soc_mem_t mem, 474 int bank_num, int *seq_num); 475 extern int soc_td3_hash_bank_info_get(int unit, soc_mem_t mem, 476 int bank, 477 int *entries_per_bank, 478 int *entries_per_row, 479 int *entries_per_bucket, 480 int *bank_base, 481 int *bucket_offset); 482 extern int soc_td3_hash_bucket_get(int unit, int mem, int bank, 483 uint32 *entry, uint32 *bucket); 484 extern int soc_td3_hash_index_get(int unit, int mem, int bank, int bucket); 485 extern int soc_td3_hash_offset_get(int unit, soc_mem_t mem, int bank, 486 int *hash_offset, int *use_lsb); 487 extern int soc_td3_hash_offset_set(int unit, soc_mem_t mem, int bank, 488 int hash_offset, int use_lsb); 489 extern uint32 soc_td3_l2x_hash(int unit, int bank, int hash_offset, 490 int use_lsb, int key_nbits, void *base_entry, 491 uint8 *key1, uint8 *key2); 492 extern int soc_td3_l2x_base_entry_to_key(int unit, int bank, uint32 *entry, 493 uint8 *key); 494 extern uint32 soc_td3_l2x_entry_hash(int unit, int bank, int hash_offset, 495 int use_lsb, uint32 *entry); 496 extern uint32 soc_td3_l2x_bank_entry_hash(int unit, int bank, uint32 *entry); 497 extern uint32 soc_td3_l3x_hash(int unit, int bank, int hash_offset, 498 int use_lsb, int key_nbits, void *base_entry, 499 uint8 *key1, uint8 *key2); 500 extern int soc_td3_l3x_base_entry_to_key(int unit, int bank, uint32 *entry, 501 uint8 *key); 502 extern uint32 soc_td3_l3x_entry_hash(int unit, int bank, int hash_offset, 503 int use_lsb, uint32 *entry); 504 extern uint32 soc_td3_l3x_bank_entry_hash(int unit, int bank, uint32 *entry); 505 extern uint32 soc_td3_exact_match_hash(int unit, int bank, int hash_offset, 506 int use_lsb, int key_nbits, 507 void *base_entry, uint8 *key1, 508 uint8 *key2); 509 extern int soc_td3_exact_match_base_entry_to_key(int unit, int bank, uint32 *entry, 510 uint8 *key); 511 extern uint32 soc_td3_exact_match_entry_hash(int unit, int bank, 512 int hash_offset, int use_lsb, 513 uint32 *entry); 514 extern uint32 soc_td3_exact_match_bank_entry_hash(int unit, int bank, 515 uint32 *entry); 516 extern uint32 soc_td3_mpls_hash(int unit, soc_mem_t mem, int bank, int hash_offset, int use_lsb, 517 int key_nbits, void *base_entry, uint8 *key1, uint8 *key2); 518 extern int soc_td3_mpls_base_entry_to_key(int unit, soc_mem_t mem, int bank, void *entry, 519 uint8 *key); 520 extern uint32 soc_td3_mpls_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 521 int use_lsb, uint32 *entry); 522 extern uint32 soc_td3_mpls_bank_entry_hash(int unit, soc_mem_t mem, int bank, uint32 *entry); 523 extern uint32 soc_td3_vlan_xlate_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 524 int use_lsb, int key_nbits, void *base_entry, 525 uint8 *key1, uint8 *key2); 526 extern int soc_td3_vlan_xlate_base_entry_to_key(int unit, soc_mem_t mem, int bank, 527 void *entry, uint8 *key); 528 extern uint32 soc_td3_vlan_xlate_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 529 int use_lsb, uint32 *entry); 530 extern uint32 soc_td3_vlan_xlate_bank_entry_hash(int unit, soc_mem_t mem, int bank, 531 uint32 *entry); 532 extern uint32 soc_td3_egr_vlan_xlate_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 533 int use_lsb, int key_nbits, void *base_entry, 534 uint8 *key1, uint8 *key2); 535 extern int soc_td3_egr_vlan_xlate_base_entry_to_key(int unit, soc_mem_t mem, 536 int bank, void *entry, uint8 *key); 537 extern uint32 soc_td3_egr_vlan_xlate_entry_hash(int unit, soc_mem_t mem, int bank, int hash_offset, 538 int use_lsb, uint32 *entry); 539 extern uint32 soc_td3_egr_vlan_xlate_bank_entry_hash(int unit, soc_mem_t mem, 540 int bank, uint32 *entry); 541 extern uint32 soc_td3_ing_vp_vlan_member_hash(int unit, int bank, int hash_offset, 542 int use_lsb, int key_nbits, void *base_entry, 543 uint8 *key1, uint8 *key2); 544 extern int soc_td3_ing_vp_vlan_member_base_entry_to_key(int unit, 545 int bank, 546 void *entry, 547 uint8 *key); 548 extern uint32 soc_td3_ing_vp_vlan_member_entry_hash(int unit, int bank, int hash_offset, 549 int use_lsb, uint32 *entry); 550 extern uint32 soc_td3_ing_vp_vlan_member_bank_entry_hash(int unit, int bank, 551 uint32 *entry); 552 extern uint32 soc_td3_egr_vp_vlan_member_hash(int unit, int bank, int hash_offset, 553 int use_lsb, int key_nbits, void *base_entry, 554 uint8 *key1, uint8 *key2); 555 extern int soc_td3_egr_vp_vlan_member_base_entry_to_key(int unit, 556 int bank, 557 void *entry, 558 uint8 *key); 559 extern uint32 soc_td3_egr_vp_vlan_member_entry_hash(int unit, int bank, int hash_offset, 560 int use_lsb, uint32 *entry); 561 extern uint32 soc_td3_egr_vp_vlan_member_bank_entry_hash(int unit, int bank, 562 uint32 *entry); 563 extern uint32 soc_td3_ing_dnat_address_type_hash(int unit, int bank, int hash_offset, 564 int use_lsb, int key_nbits, 565 void *base_entry, uint8 *key1, uint8 *key2); 566 extern int soc_td3_ing_dnat_address_type_base_entry_to_key(int unit, 567 int bank, 568 void *entry, 569 uint8 *key); 570 extern uint32 soc_td3_ing_dnat_address_type_entry_hash(int unit, int bank, int hash_offset, 571 int use_lsb, uint32 *entry); 572 extern uint32 soc_td3_ing_dnat_address_type_bank_entry_hash(int unit, int bank, uint32 *entry); 573 extern uint32 soc_td3_subport_id_to_sgpp_map_hash(int unit, int bank, int hash_offset, 574 int use_lsb, int key_nbits, 575 void *base_entry, uint8 *key1, uint8 *key2); 576 extern int soc_td3_subport_id_to_sgpp_map_base_entry_to_key(int unit, int bank, 577 void *entry, uint8 *key); 578 extern uint32 soc_td3_subport_id_to_sgpp_map_entry_hash(int unit, int bank, int hash_offset, 579 int use_lsb, uint32 *entry); 580 extern uint32 soc_td3_subport_id_to_sgpp_map_bank_entry_hash(int unit, int bank, 581 uint32 *entry); 582 583 extern int soc_td3_port_schedule_tdm_init(int unit, 584 soc_port_schedule_state_t *port_schedule_state); 585 extern int soc_td3_soc_tdm_update(int unit, 586 soc_port_schedule_state_t *port_schedule_state); 587 extern soc_error_t 588 soc_trident3_edb_buf_reset(int unit, soc_port_t port, int reset); 589 590 extern soc_error_t 591 soc_trident3_idb_buf_reset(int unit, soc_port_t port, int reset); 592 593 extern int soc_trident3_bond_info_init(int unit); 594 extern int soc_trident3_init_idb_memory(int unit); 595 596 /* ALPM support */ 597 extern int soc_trident3_get_alpm_banks(int unit); 598 extern int soc_trident3_set_alpm_banks(int unit, int banks); 599 extern int soc_trident3_alpm_mode_get(int unit); 600 extern void _soc_trident3_alpm_bkt_view_set(int unit, int index, soc_mem_t view); 601 extern soc_mem_t _soc_trident3_alpm_bkt_view_get(int unit, int index); 602 603 extern void _soc_trident3_alpm2_bnk_fmt_set(int unit, int index, int8 fmt); 604 extern int8 _soc_trident3_alpm2_bnk_fmt_get(int unit, int index); 605 extern int soc_trident3_init_alpm2_memory(int unit); 606 607 extern int _soc_trident3_init_hash_control_reset(int unit); 608 609 610 /* Special port number used by H/W */ 611 #define _SOC_TD3_TDM_OVERSUB_TOKEN 0x22 612 #define _SOC_TD3_TDM_NULL_TOKEN 0x23 613 #define _SOC_TD3_TDM_IDL1_TOKEN 0x24 614 #define _SOC_TD3_TDM_IDL2_TOKEN 0x25 615 #define _SOC_TD3_TDM_UNUSED_TOKEN 0x3f 616 617 typedef enum { 618 SOC_TD3_SCHED_MODE_UNKNOWN = 0, 619 SOC_TD3_SCHED_MODE_STRICT, 620 SOC_TD3_SCHED_MODE_WRR, 621 SOC_TD3_SCHED_MODE_WERR 622 } soc_td3_sched_mode_e; 623 624 typedef enum { 625 SOC_TD3_NODE_LVL_ROOT = 0, 626 SOC_TD3_NODE_LVL_L0, 627 SOC_TD3_NODE_LVL_L1, 628 SOC_TD3_NODE_LVL_L2, 629 SOC_TD3_NODE_LVL_MAX 630 } soc_td3_node_lvl_e; 631 632 typedef enum { 633 _SOC_TD3_INDEX_STYLE_BUCKET, 634 _SOC_TD3_INDEX_STYLE_BUCKET_MODE, 635 _SOC_TD3_INDEX_STYLE_WRED, 636 _SOC_TD3_INDEX_STYLE_WRED_DROP_THRESH, 637 _SOC_TD3_INDEX_STYLE_SCHEDULER, 638 _SOC_TD3_INDEX_STYLE_PERQ_XMT, 639 _SOC_TD3_INDEX_STYLE_UCAST_DROP, 640 _SOC_TD3_INDEX_STYLE_UCAST_QUEUE, 641 _SOC_TD3_INDEX_STYLE_MCAST_QUEUE, 642 _SOC_TD3_INDEX_STYLE_EXT_UCAST_QUEUE, 643 _SOC_TD3_INDEX_STYLE_EGR_POOL, 644 _SOC_TD3_INDEX_STYLE_COUNT 645 } soc_td3_index_style_t; 646 647 typedef enum soc_td3_drop_limit_alpha_value_e { 648 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_128, /* Use 1/128 as the alpha value for 649 dynamic threshold */ 650 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 651 dynamic threshold */ 652 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 653 dynamic threshold */ 654 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 655 dynamic threshold */ 656 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 657 dynamic threshold */ 658 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 659 dynamic threshold */ 660 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 661 dynamic threshold */ 662 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 663 threshold */ 664 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 665 threshold */ 666 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 667 threshold */ 668 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 669 threshold */ 670 SOC_TD3_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 671 } soc_td3_drop_limit_alpha_value_t; 672 673 #define _TD3_PORTS_PER_PBLK 4 674 #define _TD3_PBLKS_PER_PIPE 16 675 #define _TD3_PIPES_PER_DEV 2 676 #define _TD3_XPES_PER_DEV 1 677 678 #define _TD3_PBLKS_PER_DEV(unit) (_TD3_PBLKS_PER_PIPE * NUM_PIPE(unit)) 679 680 #define _TD3_PORTS_PER_PIPE (_TD3_PORTS_PER_PBLK * _TD3_PBLKS_PER_PIPE) 681 #define _TD3_PORTS_PER_DEV(unit) (_TD3_PORTS_PER_PIPE * NUM_PIPE(unit)) 682 683 #define _TD3_SECTION_SIZE 32768 684 685 #define _TD3_MMU_MAX_PACKET_BYTES 9416 /* bytes */ 686 #define _TD3_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 687 #define _TD3_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 688 #define _TD3_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 689 690 #define _TD3_MMU_PHYSICAL_CELLS_PER_XPE 131072 /* Total Physical cells per XPE */ 691 #define _TD3_MMU_TOTAL_CELLS_PER_XPE 129024 /* 31.5MB/XPE = 129024 cells/XPE */ 692 #define _TD3_MMU_RSVD_CELLS_CFAP_PER_XPE 556 /* Reserved CFAP cells per XPE */ 693 #define _TD3_MMU_CFAP_BANK_FULL_LIMIT 2047 /* CFAP Bank Full limit */ 694 695 #define _TD3_MMU_TOTAL_CELLS (_TD3_MMU_TOTAL_CELLS_PER_XPE * _TD3_XPES_PER_DEV) 696 #define _TD3_MMU_PHYSICAL_CELLS (_TD3_MMU_PHYSICAL_CELLS_PER_XPE * _TD3_XPES_PER_DEV) 697 698 #define _TD3_MMU_BYTES_PER_CELL 256 /* bytes (2048 bits) */ 699 #define _TD3_MMU_NUM_PG 8 700 #define _TD3_MMU_NUM_POOL 4 701 #define _TD3_MMU_NUM_RQE_QUEUES 11 702 #define _TD3_MMU_NUM_INT_PRI 16 703 #define _TD3_MMU_PORTS_PER_PIPE 66 704 705 #define SOC_TD3_MMU_CFG_QGROUP_MAX 66 706 707 #define SOC_TD3_MMU_PORT_STRIDE 0x7f /* MMU Port number space per pipe */ 708 #define SOC_TD3_MMU_PORT_PER_PIPE 128 709 710 #define SOC_TD3_NUM_CPU_QUEUES 48 /* CPU port has 48 MC Queues */ 711 #define SOC_TD3_NUM_UC_QUEUES_PER_PIPE 650 /* (64 General Ports + 1 Management Port) * 10 */ 712 #define SOC_TD3_NUM_MC_QUEUES_PER_PIPE 698 /* (64 General Ports + 1 CPU Port/Management Port +*/ 713 /* 1 Loop-back Port) * 10 */ 714 #define SOC_TD3_CPU_MCQ_BASE 650 /* CPU port MC queue base index */ 715 #define SOC_TD3_LB_MCQ_BASE 640 /* LB ports MC queue base index */ 716 #define SOC_TD3_MGMT_UCQ_BASE 640 /* Mgmt ports UC queue base index */ 717 #define SOC_TD3_MGMT_MCQ_BASE 650 /* Mgmt ports MC queue base index */ 718 #define SOC_TD3_SECOND_MGMT_BASE 630 /* Second Mgmt ports UC/MC queue base index */ 719 720 /* Number of Unicast Queues per Port */ 721 #define SOC_TD3_NUM_UCAST_QUEUE_PER_PORT 10 722 /* Number of Multicast Queues per Port */ 723 #define SOC_TD3_NUM_MCAST_QUEUE_PER_PORT 10 724 /* Number of Scheduler Nodes(L0) per Port */ 725 #define SOC_TD3_NUM_SCHEDULER_PER_PORT 10 726 727 #define SOC_TD3_MMU_MCQ_ENTRY_PER_XPE 24576 728 #define SOC_TD3_MMU_RQE_ENTRY_PER_XPE 2048 729 #define _TD3_MMU_RQE_ENTRY_RSVD_PER_XPE 242 /* Reserved RQE QE per XPE */ 730 731 #define _TD3_MMU_TOTAL_MCQ_ENTRY(unit) SOC_TD3_MMU_MCQ_ENTRY_PER_XPE 732 #define _TD3_MMU_TOTAL_RQE_ENTRY(unit) SOC_TD3_MMU_RQE_ENTRY_PER_XPE 733 734 #define _TD3_MMU_CFAP_BANK_FULL_LIMIT 2047 /* CFAP Bank Full limit */ 735 #define _TD3_TDM_MCQE_RSVD_OVERSHOOT 12 /* Reserved MC egress queue entry 736 for TDM overshoot */ 737 #define _TD3_MCQE_RSVD_PER_MCQ 6 /* Reserved MC egress queue entry 738 per MC queue */ 739 /* MMU pktstats control flags */ 740 #define _TD3_MMU_PSTATS_ENABLE 0x0001 /* Packetized/OOB Stat mode is enabled */ 741 #define _TD3_MMU_PSTATS_PKT_MOD 0x0002 /* Packetized mode is enabled. OOB Stat mode is disabled */ 742 #define _TD3_MMU_PSTATS_HWM_MOD 0x0004 /* Report High Watermark values */ 743 #define _TD3_MMU_PSTATS_RESET_ON_READ 0x0008 /* Enable Hardware clear-on read */ 744 #define _TD3_MMU_PSTATS_MOR_EN 0x0010 /* Enable MOR capability */ 745 #define _TD3_MMU_PSTATS_SYNC 0x8000 /* Read from device else the buffer */ 746 747 /* Per pipe WRED config memory base index */ 748 #define _TD3_WRED_PER_PIPE_UC_QUEUES_BASE 0 /* (64 General Ports + 1 Management Port) * 10 */ 749 #define _TD3_WRED_PER_PIPE_PORT_SP_BASE 650 /* (64 General Ports + 1 Management Port) * 4 */ 750 #define _TD3_WRED_PER_PIPE_GLOBAL_SP_BASE 910 /* (4 global service pools) */ 751 752 extern void soc_trident3_mmu_pstats_tbl_config(int unit); 753 extern int soc_trident3_mmu_pstats_mode_set(int unit, uint32 flags); 754 extern int soc_trident3_mmu_pstats_mode_get(int unit, uint32 *flags); 755 extern int soc_trident3_mmu_pstats_mor_enable(int unit); 756 extern int soc_trident3_mmu_pstats_mor_disable(int unit); 757 extern int soc_trident3_mmu_splitter_reset(int unit); 758 759 typedef struct _soc_td3_mmu_sw_config_info_s { 760 uint32 mmu_egr_queue_min; /* For CPU and loopback port */ 761 uint32 mmu_egr_qgrp_min; 762 uint32 mmu_total_pri_groups; 763 uint32 mmu_active_pri_groups; 764 uint32 mmu_pg_min; 765 uint32 mmu_port_min; 766 uint32 mmu_mc_egr_qentry_min; 767 uint32 mmu_rqe_qentry_min; 768 uint32 mmu_rqe_queue_min; 769 int ing_shared_total; 770 int egr_shared_total; 771 } _soc_td3_mmu_sw_config_info_t; 772 773 #define SOC_TD3_STAT_ING_FLEX_POOL_MAX 20 774 775 /* Num of evict memories is 26, 1 is added for reserved mem */ 776 #define SOC_TD3_NUM_EVICT_MEM 27 777 778 extern int 779 soc_trident3_mem_sram_info_get(int unit, soc_mem_t mem, int index, 780 _soc_ser_sram_info_t *sram_info); 781 782 #define SOC_TD3_NUM_EL_VLAN_XLATE 4 783 784 #define SOC_TD3_NUM_EL_EGR_VLAN_XLATE 4 785 #define SOC_TD3_NUM_EL_MPLS_ENTRY 4 786 787 #define SOC_TD3_NUM_EL_ING_L3_NEXT_HOP 4 788 #define SOC_TD3_RAM_OFFSET_ING_L3_NEXT_HOP 8192 789 790 #define SOC_TD3_NUM_ENTRIES_L2_BANK 32768 791 #define SOC_TD3_NUM_ENTRIES_L2_DEDICATE_RAM 1024 792 #define SOC_TD3_NUM_ENTRIES_L2_SHARE_RAM 2048 793 #define SOC_TD3_NUM_ENTRIES_L3_BANK 16384 794 795 #define SOC_TD3_NUM_EL_SHARED 4 796 #define SOC_TD3_NUM_ENTRIES_XOR_BANK 8192 797 #define SOC_TD3_LP_ENTRIES_IN_XOR_BANK 2048 798 #define SOC_TD3_LP_ENTRIES_IN_UFT_BANK 8192 799 800 #define SOC_TD3_ALPM_MAX_BKTS(u) (SOC_IS_TRIDENT3X(u) ? 8192 : 16384) 801 #define SOC_TD3_ALPM_BKT_MASK(u) (SOC_IS_TRIDENT3X(u) ? 0x1FFF : 0x3FFF) 802 #define SOC_TD3_ALPM_BKT_OFFFSET 2048 803 #define SOC_TD3_ALPM_MODE0_BKT_MASK 0x70007 804 #define SOC_TD3_ALPM_MODE1_BKT_MASK SOC_TD3_ALPM_MODE0_BKT_MASK >> 1 805 806 /* SUBPORT */ 807 #define TD3_SUBPORT_COE_GROUP_MAX (512) 808 #define TD3_SUBPORT_COE_PORT_MAX (512) 809 #define TD3_MAX_SUBPORT_COE_PORT_PER_CASPORT (80) 810 #define TD3_MAX_SUBPORT_COE_PORT_PER_MOD (128) 811 #define TD3_MAX_COE_MODULES (5) 812 813 extern int 814 soc_trident3_clear_all_memory(int unit); 815 816 extern int 817 soc_trident3_temperature_monitor_get(int unit, int temperature_max, 818 soc_switch_temperature_monitor_t *temperature_array, 819 int *temperature_count); 820 extern void 821 soc_trident3_temperature_intr(void *unit_vp, void *d1, void *d2, 822 void *d3, void *d4); 823 #if defined(SER_TR_TEST_SUPPORT) 824 extern int ser_test_td3_mem_index_remap(int unit, ser_test_data_t *test_data, 825 int *mem_has_ecc); 826 extern soc_error_t 827 soc_td3_ser_parity_control_reg_set(int unit, ser_test_data_t *test_data, int enable); 828 829 extern soc_error_t 830 soc_td3_ser_error_injection_support(int unit, soc_mem_t mem, int pipe_target); 831 832 extern soc_error_t 833 soc_td3_ser_inject_or_test_mem(int unit, soc_mem_t mem, int pipe_target, 834 int block, int index, _soc_ser_test_t test_type, 835 int inject_only, int cmd, uint32 flags); 836 837 838 extern soc_error_t 839 soc_td3_ser_correction_info_get(int unit, ser_correction_info_t *corr_info); 840 841 extern soc_error_t 842 soc_td3_ser_test(int unit, _soc_ser_test_t test_type); 843 844 #endif /*defined(SER_TR_TEST_SUPPORT*/ 845 846 typedef enum { 847 _SOC_TD3_PARITY_TYPE_NONE, 848 _SOC_TD3_PARITY_TYPE_ECC, 849 _SOC_TD3_PARITY_TYPE_PARITY, 850 _SOC_TD3_PARITY_TYPE_MMU_SER, 851 _SOC_TD3_PARITY_TYPE_MMU_GLB, 852 _SOC_TD3_PARITY_TYPE_MMU_XPE, 853 _SOC_TD3_PARITY_TYPE_MMU_SC, 854 _SOC_TD3_PARITY_TYPE_MMU_SED, 855 _SOC_TD3_PARITY_TYPE_CLMAC, 856 _SOC_TD3_PARITY_TYPE_XLMAC, 857 _SOC_TD3_PARITY_TYPE_SER 858 } _soc_td3_ser_info_type_t; 859 860 typedef struct _soc_td3_ser_reg_s { 861 soc_reg_t reg; 862 char *mem_str; 863 } _soc_td3_ser_reg_t; 864 865 typedef struct _soc_td3_ser_info_s { 866 _soc_td3_ser_info_type_t type; 867 struct _soc_td3_ser_info_s *info; 868 int id; 869 soc_field_t group_reg_enable_field; 870 soc_field_t group_reg_status_field; 871 soc_mem_t mem; 872 char *mem_str; 873 soc_reg_t enable_reg; 874 soc_field_t enable_field; 875 soc_field_t *enable_field_list; 876 soc_reg_t intr_enable_reg; 877 soc_field_t intr_enable_field; 878 soc_field_t *intr_enable_field_list; 879 soc_reg_t intr_status_reg; 880 _soc_td3_ser_reg_t *intr_status_reg_list; 881 soc_reg_t intr_status_field; 882 soc_field_t *intr_status_field_list; 883 soc_reg_t intr_clr_reg; 884 soc_field_t intr_clr_field; 885 soc_field_t *intr_clr_field_list; 886 } _soc_td3_ser_info_t; 887 888 extern int 889 soc_td3_ser_enable_info(int unit, int block_info_idx, int inst, int port, 890 soc_reg_t group_reg, uint64 *group_rval, 891 _soc_td3_ser_info_t *info_list, 892 soc_mem_t mem, int enable); 893 extern int 894 soc_td3_ser_process(int unit, int block_info_idx, int inst, int pipe, 895 int port, soc_reg_t group_reg, uint64 group_rval, 896 const _soc_td3_ser_info_t *info_list, 897 soc_block_t blocktype, 898 char *prefix_str); 899 extern soc_error_t 900 soc_td3_ser_tcam_wrapper_enable(int unit, int enable); 901 902 extern void 903 soc_td3_ser_test_register(int unit); 904 extern int 905 soc_trident3_process_ser_fifo(int unit, soc_block_t blk, int pipe, 906 char *prefix_str, int l2_mgmt_ser_fifo); 907 extern int soc_td3_ser_reg_field32_modify(int unit, soc_reg_t reg, 908 soc_port_t port, soc_field_t field, 909 uint32 value, int index, 910 int mmu_base_index); 911 extern int 912 soc_td3_mem_parity_control(int unit, soc_mem_t mem, int copyno, 913 int en, int en_1b); 914 extern void 915 soc_trident3_process_func_intr(void *unit_vp, void *d1, void *d2, 916 void *d3, void *d4); 917 extern int 918 soc_td3_mmu_non_ser_intr_handler(int unit, soc_block_t blocktype, 919 int mmu_base_index, 920 uint32 rval_intr_status_reg); 921 extern int 922 soc_td3_ser_mem_mode_get(int unit, soc_mem_t mem, int *mode); 923 extern int 924 soc_trident3_clear_mmu_memory(int unit); 925 extern int 926 soc_td3_check_scrub_skip(int unit, soc_mem_t mem, int check_hw_global_mode); 927 extern int 928 soc_td3_check_scrub_info(int unit, soc_mem_t mem, int blk, int copyno, 929 int *num_inst_to_scrub, int *acc_type_list); 930 extern int 931 soc_td3_check_hw_global_mode(int unit, soc_mem_t mem, int *mem_mode); 932 extern int 933 soc_td3_get_alpm_banks(int unit); 934 extern int 935 soc_trident3_alpm_mode_get(int unit); 936 extern int 937 soc_td3_tcam_engine_enable(int unit, int enable); 938 extern void 939 soc_td3_mem_scan_info_get(int unit, soc_mem_t mem, int block, 940 int *num_pipe, int *ser_flags); 941 extern int 942 soc_td3_mmu_bmp_reg_pos_get(int unit, soc_port_t port, 943 int *pipe, int *split, int *pos); 944 extern int 945 soc_trident3_mmu_port_flush_hw(int unit, soc_port_t port, uint32 drain_timeout); 946 extern int 947 soc_td3_port_traffic_egr_enable_set(int unit, soc_port_t port, int enable); 948 extern int 949 soc_td3_port_mmu_tx_enable_set(int unit, soc_port_t port, int enable); 950 extern int 951 soc_td3_port_mmu_tx_enable_get(int unit, soc_port_t port, int *enable); 952 extern int 953 soc_td3_port_mmu_rx_enable_set(int unit, soc_port_t port, int enable); 954 extern int 955 soc_td3_port_mmu_rx_enable_get(int unit, soc_port_t port, int *enable); 956 extern int 957 soc_td3_mmu_traffic_ctrl_size(int unit, int *req_scache_size); 958 extern int 959 soc_td3_mmu_traffic_ctrl_wb_sync(int unit, uint8 **scache_ptr); 960 extern int 961 soc_td3_mmu_traffic_ctrl_wb_restore(int unit, uint8 **scache_ptr); 962 extern void soc_td3_subport_init(int unit); 963 964 /************ FlexPort Start ********************/ 965 extern int soc_td3_mmu_config_init_port(int unit, int port); 966 #ifdef BCM_WARM_BOOT_SUPPORT 967 extern int soc_td3_flexport_scache_allocate(int unit); 968 extern int soc_td3_flexport_scache_sync(int unit); 969 extern int soc_td3_flexport_scache_recovery(int unit); 970 extern int soc_td3_tdm_scache_allocate(int unit); 971 extern int soc_td3_tdm_scache_sync(int unit); 972 extern int soc_td3_tdm_scache_recovery(int unit); 973 #endif /* BCM_WARM_BOOT_SUPPORT */ 974 /************ FlexPort End ********************/ 975 976 int 977 soc_td3_max_lr_bandwidth(int unit, uint32 *max_lr_bw); 978 int 979 soc_td3_max_lr_cal_len(int unit, uint32 *max_lr_cal, int eth); 980 int 981 soc_td3_support_speeds(int unit, int lanes, uint32 *speed_mask); 982 uint32 _soc_td3_mmu_port(int unit, int port); 983 984 extern int 985 soc_td3_speed_mix_validate(int unit, uint32 speed_mask); 986 extern int 987 soc_td3_port_mode_get(int unit, int logical_port, int *mode); 988 989 990 #if !defined(BCM_TD3_ASF_EXCLUDE) 991 /* 992 ============================= 993 TD3 ASF (cut-thru forwarding) 994 ============================= 995 */ 996 #define OUT 997 #define IN_OUT 998 999 /* ASF Modes */ 1000 typedef enum { 1001 _SOC_TD3_ASF_MODE_SAF = 0, /* store-and-forward */ 1002 _SOC_TD3_ASF_MODE_SAME_SPEED = 1, /* same speed CT */ 1003 _SOC_TD3_ASF_MODE_SLOW_TO_FAST = 2, /* slow to fast CT */ 1004 _SOC_TD3_ASF_MODE_FAST_TO_SLOW = 3, /* fast to slow CT */ 1005 _SOC_TD3_ASF_MODE_CFG_UPDATE = 4, /* internal cfg updates */ 1006 _SOC_TD3_ASF_MODE_INIT = 5, /* init */ 1007 _SOC_TD3_ASF_MODE_UNSUPPORTED = 6 1008 } soc_td3_asf_mode_e; 1009 1010 /* ASF MMU Cell Buffer Allocation Profiles */ 1011 typedef enum { 1012 _SOC_TD3_ASF_MEM_PROFILE_NONE = 0, /* No cut-through support */ 1013 _SOC_TD3_ASF_MEM_PROFILE_SIMILAR = 1, /* Similar Speed Alloc Profile */ 1014 _SOC_TD3_ASF_MEM_PROFILE_EXTREME = 2 /* Extreme Speed Alloc Profile */ 1015 } soc_td3_asf_mem_profile_e; 1016 1017 /* Latency modes */ 1018 typedef enum { 1019 _SOC_TD3_L2_LATENCY = 0, 1020 _SOC_TD3_L3_LATENCY = 1, 1021 _SOC_TD3_FULL_LATENCY = 2 1022 } _soc_td3_latency_mode_e; 1023 1024 extern int 1025 soc_td3_port_oversub_ratio_get( 1026 int unit, 1027 soc_port_t port, 1028 int* const ratio); 1029 1030 extern int 1031 soc_td3_asf_init_start(int unit); 1032 1033 extern int 1034 soc_td3_asf_init_done(int unit); 1035 1036 extern int 1037 soc_td3_port_asf_init( 1038 int unit, 1039 soc_port_t port, 1040 int port_speed, 1041 soc_td3_asf_mode_e mode); 1042 1043 extern int 1044 soc_td3_asf_deinit(int unit); 1045 1046 extern int 1047 soc_td3_port_asf_xmit_start_count_set( 1048 int unit, 1049 soc_port_t port, 1050 int port_speed, 1051 soc_td3_asf_mode_e mode, 1052 uint8 extra_cells); 1053 1054 extern int 1055 soc_td3_port_asf_mode_get( 1056 int unit, 1057 soc_port_t port, 1058 int port_speed, 1059 OUT soc_td3_asf_mode_e* const mode); 1060 1061 extern int 1062 soc_td3_port_asf_mode_set( 1063 int unit, 1064 soc_port_t port, 1065 int port_speed, 1066 soc_td3_asf_mode_e mode); 1067 1068 extern int 1069 soc_td3_port_asf_params_set( 1070 int unit, 1071 soc_port_t port, 1072 int port_speed, 1073 soc_td3_asf_mode_e mode); 1074 1075 extern int 1076 soc_td3_port_asf_speed_to_mmu_cell_credit( 1077 int unit, 1078 soc_port_t port, 1079 int port_speed, 1080 OUT uint32 *mmu_cell_credit); 1081 1082 extern int 1083 soc_td3_port_asf_mmu_cell_credit_to_speed( 1084 int unit, 1085 soc_port_t port, 1086 uint8 mmu_cell_credit, 1087 OUT int *port_speed); 1088 1089 extern pbmp_t * 1090 soc_td3_port_asf_pause_bpmp_get(int unit); 1091 1092 #ifdef BCM_WARM_BOOT_SUPPORT 1093 extern int 1094 soc_td3_asf_wb_memsz_get( 1095 int unit, 1096 OUT uint32* const wb_mem_sz, 1097 uint16 scache_ver); 1098 1099 extern int 1100 soc_td3_asf_wb_sync( 1101 int unit, 1102 IN_OUT uint8* const wb_data); 1103 1104 extern int 1105 soc_td3_asf_wb_recover( 1106 int unit, 1107 uint8* const wb_data, 1108 uint16 scache_ver); 1109 #endif 1110 1111 extern int 1112 soc_td3_asf_pbmp_get(int unit); 1113 1114 extern int 1115 soc_td3_port_asf_show( 1116 int unit, 1117 soc_port_t port, 1118 int port_speed); 1119 1120 extern int 1121 soc_td3_asf_config_dump(int unit); 1122 1123 extern int 1124 soc_td3_port_asf_config_dump( 1125 int unit, 1126 soc_port_t port, 1127 int port_speed); 1128 1129 extern int 1130 soc_td3_port_asf_detach( 1131 int unit, 1132 soc_port_t port); 1133 #endif 1134 1135 extern soc_error_t 1136 soc_td3_granular_speed_get(int unit, soc_port_t port, int *speed); 1137 1138 extern int 1139 soc_td3_lpm_flex_ip4entry0_to_1( 1140 int u, 1141 void *src, 1142 void *dst, 1143 uint32 key_type, 1144 int copy_hit); 1145 1146 extern int 1147 soc_td3_lpm_flex_ip4entry0_to_0( 1148 int u, 1149 void *src, 1150 void *dst, 1151 uint32 key_type, 1152 int copy_hit); 1153 1154 extern int 1155 soc_td3_lpm_flex_prefix_length_get( 1156 int u, 1157 void *entry, 1158 int *ipv6, 1159 int *vrf_id, 1160 int *pfx, 1161 uint32 key_type); 1162 extern int soc_td3_post_mmu_init_update(int unit); 1163 1164 extern int 1165 soc_td3_mpls_hash_control_set(int *hash_entry); 1166 1167 extern int 1168 _soc_trident3_init_mmu_memory(int unit); 1169 extern int soc_td3_frequency_init(int unit); 1170 1171 extern int 1172 _soc_trident3_pll_dco_code_get(int unit, soc_td3_plls_e pll, uint32 *dco_code); 1173 1174 extern int 1175 _soc_td3_pll_dco_normalize(uint32 *dco_code, uint32 ref_freq, uint32 ndiv); 1176 1177 1178 extern int 1179 soc_trident3_age_timer_get(int unit, int *age_seconds, int *enabled); 1180 1181 extern int 1182 soc_trident3_age_timer_max_get(int unit, int *max_seconds); 1183 1184 extern int 1185 soc_trident3_age_timer_set(int unit, int age_seconds, int enable); 1186 1187 extern int 1188 soc_trident3_tscx_firmware_set(int unit, int port, uint8 *array, int datalen); 1189 1190 extern int 1191 soc_trident3_latency_config(int unit); 1192 1193 extern int 1194 soc_td3_set_idb_dpp_ctrl(int unit); 1195 1196 extern int 1197 soc_flex_hash_mem_view_get(int unit, soc_mem_t mem,uint32 *entry, 1198 soc_mem_t *mem_view, soc_field_t *field_list); 1199 1200 #ifdef INCLUDE_AVS 1201 extern soc_error_t 1202 soc_td3_avs_init(int unit); 1203 #endif /* INCLUDE_AVS */ 1204 1205 #endif /* !_SOC_TRIDENT3_H_ */