trident2.h (41439B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: trident2.h 8 */ 9 10 #ifndef _SOC_TRIDENT2_H_ 11 #define _SOC_TRIDENT2_H_ 12 13 #include <soc/drv.h> 14 #include <soc/mem.h> 15 #include <soc/error.h> 16 #include <soc/mmu_config.h> 17 18 #define SOC_TD2_NUM_EL_L2 4 19 #define SOC_TD2_NUM_EL_SHARED 8 20 #define SOC_TD2_NUM_EL_ALPM 4 21 #define SOC_TD2_NUM_EL_VLAN_XLATE 4 22 #define SOC_TD2_NUM_EL_EGR_VLAN_XLATE 4 23 #define SOC_TD2_NUM_EL_ING_L3_NEXT_HOP 6 24 #define SOC_TD2_NUM_EL_L3_IPMC 4 25 26 #ifdef BCM_TRIDENT2PLUS_SUPPORT 27 #define SOC_TD2P_NUM_EL_SHARED 16 28 #define SOC_TD2P_ALPM_MODE0_BKT_MASK 0x70003 29 #define SOC_TD2P_NUM_EL_L3 3 30 #define SOC_TD2P_NUM_EL_L3_IPMC 8 31 #endif 32 33 #define SOC_TD2_RAM_OFFSET_L2_BANK 4096 34 #define SOC_TD2_RAM_OFFSET_L2MC 4096 /* size of every ram */ 35 #define SOC_TD2_NUM_EL_L2MC(unit) \ 36 ((soc_mem_index_max(unit, L2MCm) + 1) / SOC_TD2_RAM_OFFSET_L2MC) /* Number of L2MC RAM*/ 37 38 #define SOC_TD2_RAM_OFFSET_L2_SHARED_BANK 8192 39 40 #define SOC_TD2_RAM_OFFSET_L3_NARROW 8192 41 #define SOC_TD2_RAM_OFFSET_L3_WIDE 4096 42 #define SOC_TD2_RAM_OFFSET_L3_DOUBLE_WIDE 2048 43 44 #define SOC_TD2_RAM_OFFSET_ING_L3_NEXT_HOP 8192 45 #define SOC_TD2_RAM_OFFSET_L3_IPMC 2048 46 47 #define SOC_TD2_L3_DEFIP_ALPM_PER_BKT_COUNT 1 48 #define SOC_TD2_L3_DEFIP_ALPM_IPV6_128_PER_BKT_COUNT 2 49 #define SOC_TD2_L3_DEFIP_ALPM_IPV6_64_1_PER_BKT_COUNT 3 50 #define SOC_TD2_L3_DEFIP_ALPM_IPV6_64_PER_BKT_COUNT 4 51 #define SOC_TD2_L3_DEFIP_ALPM_IPV4_1_PER_BKT_COUNT 4 52 #define SOC_TD2_L3_DEFIP_ALPM_IPV4_PER_BKT_COUNT 6 53 54 #define SOC_TD2_NUM_ENTRIES_PER_L2_BANK 16384 55 #define SOC_TD2_NUM_ENTRIES_L2_BANK 32768 56 #define SOC_TD2_NUM_ENTRIES_L3_BANK 16384 57 #define SOC_TD2_NUM_ENTRIES_L3_BANK_WIDE 8192 58 #define SOC_TD2_NUM_ENTRIES_L3_BANK_DOUBLE_WIDE 4096 59 60 #define SOC_TD2_ALPM_MAX_BKTS 16384 61 #define SOC_TD2_ALPM_BKT_OFFFSET 2048 62 #define SOC_TD2_ALPM_BKT_MASK 0x3FFF 63 64 #define _SOC_TD2_L2LU_INTR_MASK 0x01000 65 #define _SOC_TD2_FUNC_INTR_MASK _SOC_TD2_L2LU_INTR_MASK 66 67 #define SOC_TD2_PORT_CT_SPEED_NONE 0x0 68 #define SOC_TD2_PORT_CT_SPEED_10M_HALF 0x2 69 #define SOC_TD2_PORT_CT_SPEED_10M_FULL 0x3 70 #define SOC_TD2_PORT_CT_SPEED_100M_HALF 0x4 71 #define SOC_TD2_PORT_CT_SPEED_100M_FULL 0x5 72 #define SOC_TD2_PORT_CT_SPEED_1000M_HALF 0x6 73 #define SOC_TD2_PORT_CT_SPEED_1000M_FULL 0x7 74 #define SOC_TD2_PORT_CT_SPEED_2500M_HALF 0x8 75 #define SOC_TD2_PORT_CT_SPEED_2500M_FULL 0x9 76 #define SOC_TD2_PORT_CT_SPEED_5000M_FULL 0xa 77 #define SOC_TD2_PORT_CT_SPEED_10000M_FULL 0xc 78 #define SOC_TD2_PORT_CT_SPEED_11000M_FULL 0xb 79 #define SOC_TD2_PORT_CT_SPEED_12000M_FULL 0xd 80 #define SOC_TD2_PORT_CT_SPEED_13000M_FULL 0xe 81 #define SOC_TD2_PORT_CT_SPEED_15000M_FULL 0xf 82 #define SOC_TD2_PORT_CT_SPEED_16000M_FULL 0x10 83 #define SOC_TD2_PORT_CT_SPEED_20000M_FULL 0x12 84 #define SOC_TD2_PORT_CT_SPEED_21000M_FULL 0x13 85 #define SOC_TD2_PORT_CT_SPEED_24000M_FULL 0x14 86 #define SOC_TD2_PORT_CT_SPEED_30000M_FULL 0x18 87 #define SOC_TD2_PORT_CT_SPEED_32000M_FULL 0x19 88 #define SOC_TD2_PORT_CT_SPEED_40000M_FULL 0x1c 89 #define SOC_TD2_PORT_CT_SPEED_42000M_FULL 0x1d 90 #define SOC_TD2_PORT_CT_SPEED_100000M_FULL 0x1e 91 #define SOC_TD2_PORT_CT_SPEED_120000M_FULL 0x1f 92 93 #define SOC_TD2_NUM_MMU_PORTS_PER_PIPE 53 94 95 #define SOC_TD2_NUM_HSP_MMU_PORTS_PER_PIPE 16 96 97 #define _TD2_COSQ_NUM_CPU_L0_NODES 4 98 #define _TD2PLUS_COSQ_NUM_CPU_L0_NODES 6 99 100 #define SOC_TD2_COSQ_NUM_CPU_L0_NODES(unit) \ 101 (SOC_IS_TD2P_TT2P(unit) ? _TD2PLUS_COSQ_NUM_CPU_L0_NODES : _TD2_COSQ_NUM_CPU_L0_NODES) 102 #define SOC_TD2_COSQ_CPU_RESERVED_L0_NUM(unit) \ 103 (SOC_IS_TD2P_TT2P(unit) ? 0 : _TD2_COSQ_NUM_CPU_L0_NODES) 104 105 #define SOC_TD2_COSQ_CPU_RESERVED_L0_BASE(unit) \ 106 (SOC_IS_TD2P_TT2P(unit) ? 259 : 261) 107 108 #define _TD2_PORTS_PER_XLP 4 109 #define _TD2_XLPS_PER_PGW 4 110 #define _TD2_PGWS_PER_QUAD 2 111 #define _TD2_QUADS_PER_PIPE 2 112 #define _TD2_PIPES_PER_DEV 2 113 114 #define _TD2_QUADS_PER_DEV (_TD2_QUADS_PER_PIPE * _TD2_PIPES_PER_DEV) 115 116 #define _TD2_PGWS_PER_PIPE (_TD2_PGWS_PER_QUAD * _TD2_QUADS_PER_PIPE) 117 #define _TD2_PGWS_PER_DEV (_TD2_PGWS_PER_PIPE * _TD2_PIPES_PER_DEV) 118 119 #define _TD2_PORTS_PER_PGW (_TD2_PORTS_PER_XLP * _TD2_XLPS_PER_PGW) 120 #define _TD2_PORTS_PER_QUAD (_TD2_PORTS_PER_PGW * _TD2_PGWS_PER_QUAD) 121 #define _TD2_PORTS_PER_PIPE (_TD2_PORTS_PER_QUAD * _TD2_QUADS_PER_PIPE) 122 123 #define _TD2_BYTES_PER_OBM_CELL 16 124 125 #define _TD2_LOG_PORTS_PER_PIPE 53 126 #define _TD2_MMU_PORTS_PER_PIPE 53 127 #define _TD2_NUM_LOG_PORTS_PER_DEV (_TD2_LOG_PORTS_PER_PIPE * _TD2_PIPES_PER_DEV) 128 129 #define SOC_FIELD_RANGE_CHECK(val, min, max) \ 130 (((val) > (min)) && ((val) <= (max))) 131 132 typedef enum { 133 SOC_TD2_SCHED_MODE_UNKNOWN = 0, 134 SOC_TD2_SCHED_MODE_STRICT, 135 SOC_TD2_SCHED_MODE_WRR, 136 SOC_TD2_SCHED_MODE_WDRR 137 } soc_td2_sched_mode_e; 138 139 typedef enum { 140 SOC_TD2_NODE_LVL_ROOT = 0, 141 SOC_TD2_NODE_LVL_L0, 142 SOC_TD2_NODE_LVL_L1, 143 SOC_TD2_NODE_LVL_L2, 144 SOC_TD2_NODE_LVL_MAX 145 } soc_td2_node_lvl_e; 146 147 typedef enum { 148 _SOC_TD2_INDEX_STYLE_BUCKET, 149 _SOC_TD2_INDEX_STYLE_BUCKET_MODE, 150 _SOC_TD2_INDEX_STYLE_WRED, 151 _SOC_TD2_INDEX_STYLE_WRED_DROP_THRESH, 152 _SOC_TD2_INDEX_STYLE_SCHEDULER, 153 _SOC_TD2_INDEX_STYLE_PERQ_XMT, 154 _SOC_TD2_INDEX_STYLE_UCAST_DROP, 155 _SOC_TD2_INDEX_STYLE_UCAST_QUEUE, 156 _SOC_TD2_INDEX_STYLE_MCAST_QUEUE, 157 _SOC_TD2_INDEX_STYLE_EXT_UCAST_QUEUE, 158 _SOC_TD2_INDEX_STYLE_EGR_POOL, 159 _SOC_TD2_INDEX_STYLE_COUNT 160 } soc_td2_index_style_t; 161 162 typedef enum soc_td2_drop_limit_alpha_value_e { 163 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_128, /* Use 1/128 as the alpha value for 164 dynamic threshold */ 165 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_64, /* Use 1/64 as the alpha value for 166 dynamic threshold */ 167 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_32, /* Use 1/32 as the alpha value for 168 dynamic threshold */ 169 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_16, /* Use 1/16 as the alpha value for 170 dynamic threshold */ 171 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_8, /* Use 1/8 as the alpha value for 172 dynamic threshold */ 173 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_4, /* Use 1/4 as the alpha value for 174 dynamic threshold */ 175 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1_2, /* Use 1/2 as the alpha value for 176 dynamic threshold */ 177 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_1, /* Use 1 as the alpha value for dynamic 178 threshold */ 179 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_2, /* Use 2 as the alpha value for dynamic 180 threshold */ 181 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_4, /* Use 4 as the alpha value for dynamic 182 threshold */ 183 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_8, /* Use 8 as the alpha value for dynamic 184 threshold */ 185 SOC_TD2_COSQ_DROP_LIMIT_ALPHA_COUNT /* Must be the last entry! */ 186 } soc_td2_drop_limit_alpha_value_t; 187 188 extern uint8 _soc_alpm_mode[SOC_MAX_NUM_DEVICES]; 189 190 extern uint32* soc_td2_mmu_params_arr_get (uint16 dev_id, uint8 rev_id); 191 192 extern soc_functions_t soc_trident2_drv_funs; 193 extern int _soc_trident2_mem_ser_control(int unit, soc_mem_t mem, 194 int copyno, int enable); 195 extern int _soc_trident2_mem_cpu_write_control(int unit, soc_mem_t mem, 196 int copyno, int enable, 197 int *orig_enable); 198 extern int soc_trident2_ser_mem_clear(int unit, soc_mem_t mem); 199 extern int soc_trident2_alpm_scrub(int unit); 200 extern void _soc_trident2_alpm_bkt_view_set(int unit, int index, soc_mem_t view); 201 extern soc_mem_t _soc_trident2_alpm_bkt_view_get(int unit, int index); 202 extern int soc_trident2_mem_config(int unit); 203 extern int soc_trident2_alpm_mode_get(int unit); 204 extern int soc_trident2_l3_defip_index_map(int unit, soc_mem_t mem, int index); 205 extern int soc_trident2_l3_defip_index_remap(int unit, soc_mem_t mem, int index); 206 extern int soc_trident2_l3_defip_mem_index_get(int unit, int pindex, soc_mem_t *mem); 207 extern int _soc_trident2_mem_sram_info_get(int unit, soc_mem_t mem, int index, 208 _soc_ser_sram_info_t *sram_info); 209 extern int soc_trident2_pipe_select(int unit, int egress, int pipe); 210 extern int soc_trident2_num_cosq_init(int unit); 211 extern int soc_trident2_tsc_map_get(int unit, uint32 *tsc_map); 212 extern int soc_trident2_port_config_init(int unit, uint16 dev_id, uint8 rev_id); 213 extern int soc_trident2_lls_bmap_alloc(int unit); 214 extern int soc_trident2_lls_bmap_alloc_port(int unit, int port, int ets_mode); 215 extern int soc_trident2_chip_reset(int unit); 216 extern int soc_trident2_tsc_reset(int unit); 217 extern void trident2p_ovstb_toggle(int unit); 218 extern int soc_trident2_l3_memwr_parity_check(int unit, soc_mem_t mem, int disable); 219 220 int soc_td2_mmu_traffic_ctrl_size(int unit, int *req_scache_size); 221 222 int soc_td2_mmu_traffic_ctrl_wb_sync(int unit, uint8 **scache_ptr); 223 224 int soc_td2_mmu_traffic_ctrl_wb_restore(int unit, uint8 **scache_ptr); 225 226 227 typedef struct soc_td2_port_lanes_s { 228 int port_base; /* Base port number */ 229 int lanes; /* New number of lanes */ 230 int cur_lanes; /* Current number of lanes */ 231 int mode; /* New mode */ 232 int cur_mode; /* Current mode */ 233 int weight; /* Weight for new group */ 234 int cur_weight; /* Weight for current group */ 235 int group; /* New MMU oversub group number */ 236 int cur_group; /* Current MMU oversub group number */ 237 int slot; /* New MMU oversub group slot number */ 238 int cur_slot; /* Current MMU oversub group slot number */ 239 int cur_empty; /* Current MMU oversub group become empty after flex */ 240 int bindex; /* Base port subport index */ 241 int oversub; /* Oversub status for the ports */ 242 int phy_ports_len; /* Length of valid entries in phy_ports array */ 243 int phy_ports[3]; /* Array of added/removed physical port number */ 244 } soc_td2_port_lanes_t; 245 extern int soc_trident2_port_lanes_validate(int unit, 246 soc_td2_port_lanes_t *lanes_ctrl); 247 extern int soc_trident2_port_lanes_set(int unit, 248 soc_td2_port_lanes_t *lanes_ctrl); 249 extern int soc_trident2_port_lanes_get(int unit, soc_port_t port_base, 250 int *cur_lanes); 251 extern int soc_trident2_temperature_monitor_get(int unit, 252 int temperature_max, 253 soc_switch_temperature_monitor_t *temperature_array, 254 int *temperature_count); 255 extern int soc_trident2_show_material_process(int unit); 256 extern int soc_trident2_show_ring_osc(int unit); 257 258 enum soc_td2_port_mode_e { 259 /* WARNING: values given match hardware register; do not modify */ 260 SOC_TD2_PORT_MODE_QUAD = 0, 261 SOC_TD2_PORT_MODE_TRI_012 = 1, 262 SOC_TD2_PORT_MODE_TRI_023 = 2, 263 SOC_TD2_PORT_MODE_DUAL = 3, 264 SOC_TD2_PORT_MODE_SINGLE = 4 265 }; 266 267 /* 268 * Miscellaneous SOC port data used for validation 269 * 270 * Most fields are equivalent to the fields in the SOC_INFO data 271 * structure. Use same field names. 272 */ 273 typedef struct soc_info_misc_s { 274 int port_l2p_mapping[SOC_MAX_NUM_PORTS]; /* Logic to phys */ 275 int port_p2l_mapping[SOC_MAX_NUM_PORTS]; /* Phys to logic */ 276 int port_speed_max[SOC_MAX_NUM_PORTS]; /* Max speed */ 277 int port_speed[SOC_MAX_NUM_PORTS]; /* Current speed */ 278 int port_num_lanes[SOC_MAX_NUM_PORTS]; /* Number of lanes */ 279 soc_encap_mode_t port_encap[SOC_MAX_NUM_PORTS]; /* Encap mode */ 280 int bandwidth; /* Bandwidth */ 281 pbmp_t oversub_pbm; /* Oversubscription */ 282 pbmp_t disabled_bitmap; /* Disabled ports */ 283 pbmp_t management_pbm; /* Management ports */ 284 } soc_info_misc_t; 285 286 typedef struct soc_pmap_info_s { 287 int port; 288 int phy_port; 289 int port_bandwidth; 290 int lane_config; 291 int fallback_lane; 292 int pipe; 293 char *option; 294 soc_pbmp_t oversub_pbm; 295 } soc_pmap_info_t; 296 297 extern void 298 soc_trident2_soc_info_misc_t_init(int unit, soc_info_misc_t *si_m); 299 extern int 300 soc_trident2_port_bandwidth_validate(int unit, soc_info_misc_t *si_m); 301 extern int 302 soc_trident2_port_portmap_parse(int unit, soc_port_t port, 303 soc_pmap_info_t *pmap); 304 305 enum td2_l2_hash_key_type_e { 306 /* WARNING: values given match hardware register; do not modify */ 307 TD2_L2_HASH_KEY_TYPE_BRIDGE = 0, 308 TD2_L2_HASH_KEY_TYPE_SINGLE_CROSS_CONNECT = 1, 309 TD2_L2_HASH_KEY_TYPE_DOUBLE_CROSS_CONNECT = 2, 310 TD2_L2_HASH_KEY_TYPE_VFI = 3, 311 TD2_L2_HASH_KEY_TYPE_VIF = 4, 312 TD2_L2_HASH_KEY_TYPE_TRILL_NONUC_ACCESS = 5, 313 TD2_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_LONG = 6, 314 TD2_L2_HASH_KEY_TYPE_TRILL_NONUC_NETWORK_SHORT = 7, 315 TD2_L2_HASH_KEY_TYPE_BFD = 8, 316 TD2_L2_HASH_KEY_TYPE_PE_VID = 9, 317 TD2_L2_HASH_KEY_TYPE_FCOE_ZONE = 10, 318 TD2_L2_HASH_KEY_TYPE_COUNT 319 }; 320 321 enum td2_l3_hash_key_type_e { 322 /* WARNING: values given match hardware register; do not modify */ 323 TD2_L3_HASH_KEY_TYPE_V4UC = 0, 324 TD2_L3_HASH_KEY_TYPE_V4UC_EXT = 1, 325 TD2_L3_HASH_KEY_TYPE_V6UC = 2, 326 TD2_L3_HASH_KEY_TYPE_V6UC_EXT = 3, 327 TD2_L3_HASH_KEY_TYPE_V4MC = 4, 328 TD2_L3_HASH_KEY_TYPE_V6MC = 5, 329 /* 6,7 are not used */ 330 TD2_L3_HASH_KEY_TYPE_TRILL = 8, 331 /* 9,10,11 is not used */ 332 TD2_L3_HASH_KEY_TYPE_FCOE_DOMAIN = 12, 333 TD2_L3_HASH_KEY_TYPE_FCOE_DOMAIN_EXT = 13, 334 TD2_L3_HASH_KEY_TYPE_FCOE_HOST = 14, 335 TD2_L3_HASH_KEY_TYPE_FCOE_HOST_EXT = 15, 336 TD2_L3_HASH_KEY_TYPE_FCOE_SRC_MAP = 16, 337 TD2_L3_HASH_KEY_TYPE_FCOE_SRC_MAP_EXT = 17, 338 TD2_L3_HASH_KEY_TYPE_DST_NAT = 18, 339 TD2_L3_HASH_KEY_TYPE_DST_NAPT = 19, 340 TD2_L3_HASH_KEY_TYPE_V4L2MC = 20, 341 TD2_L3_HASH_KEY_TYPE_V4L2VPMC = 21, 342 TD2_L3_HASH_KEY_TYPE_V6L2MC = 22, 343 TD2_L3_HASH_KEY_TYPE_V6L2VPMC = 23, 344 TD2_L3_HASH_KEY_TYPE_COUNT 345 }; 346 347 enum td2_mpls_hash_key_type_e { 348 /* WARNING: values given match hardware register; do not modify */ 349 TD2_MPLS_HASH_KEY_TYPE_MPLS = 0, 350 TD2_MPLS_HASH_KEY_TYPE_MIM_NVP = 1, 351 TD2_MPLS_HASH_KEY_TYPE_MIM_ISID = 2, 352 TD2_MPLS_HASH_KEY_TYPE_MIM_ISID_SVP = 3, 353 TD2_MPLS_HASH_KEY_TYPE_L2GRE_VPNID_SIP = 4, 354 TD2_MPLS_HASH_KEY_TYPE_TRILL = 5, 355 TD2_MPLS_HASH_KEY_TYPE_L2GRE_SIP = 6, 356 TD2_MPLS_HASH_KEY_TYPE_L2GRE_VPNID = 7, 357 TD2_MPLS_HASH_KEY_TYPE_VXLAN_SIP = 8, 358 TD2_MPLS_HASH_KEY_TYPE_VXLAN_VPNID = 9, 359 TD2_MPLS_HASH_KEY_TYPE_VXLAN_VPNID_SIP = 10, 360 TD2_MPLS_HASH_KEY_TYPE_COUNT 361 }; 362 363 enum td2_vlxlt_hash_key_type_e { 364 /* WARNING: values given match hardware register; do not modify */ 365 TD2_VLXLT_HASH_KEY_TYPE_IVID_OVID = 0, 366 TD2_VLXLT_HASH_KEY_TYPE_OTAG = 1, 367 TD2_VLXLT_HASH_KEY_TYPE_ITAG = 2, 368 TD2_VLXLT_HASH_KEY_TYPE_VLAN_MAC = 3, 369 TD2_VLXLT_HASH_KEY_TYPE_OVID = 4, 370 TD2_VLXLT_HASH_KEY_TYPE_IVID = 5, 371 TD2_VLXLT_HASH_KEY_TYPE_PRI_CFI = 6, 372 TD2_VLXLT_HASH_KEY_TYPE_HPAE = 7, 373 TD2_VLXLT_HASH_KEY_TYPE_VIF = 8, 374 TD2_VLXLT_HASH_KEY_TYPE_VIF_VLAN = 9, 375 TD2_VLXLT_HASH_KEY_TYPE_VIF_CVLAN = 10, 376 TD2_VLXLT_HASH_KEY_TYPE_VIF_OTAG = 11, 377 TD2_VLXLT_HASH_KEY_TYPE_VIF_ITAG = 12, 378 TD2_VLXLT_HASH_KEY_TYPE_L2GRE_DIP = 13, 379 TD2_VLXLT_HASH_KEY_TYPE_VLAN_MAC_PORT = 14, 380 TD2_VLXLT_HASH_KEY_TYPE_IVID_OVID_VSAN = 15, 381 TD2_VLXLT_HASH_KEY_TYPE_IVID_VSAN = 16, 382 TD2_VLXLT_HASH_KEY_TYPE_OVID_VSAN = 17, 383 TD2_VLXLT_HASH_KEY_TYPE_VXLAN_DIP = 18, 384 TD2_VLXLT_HASH_KEY_TYPE_COUNT 385 }; 386 387 enum td2_evlxlt_hash_key_type_e { 388 /* WARNING: values given match hardware register; do not modify */ 389 TD2_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE = 0, 390 TD2_EVLXLT_HASH_KEY_TYPE_VLAN_XLATE_DVP = 1, 391 TD2_EVLXLT_HASH_KEY_TYPE_FCOE_XLATE = 2, 392 TD2_EVLXLT_HASH_KEY_TYPE_ISID_XLATE = 3, 393 TD2_EVLXLT_HASH_KEY_TYPE_ISID_DVP_XLATE = 4, 394 TD2_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI = 5, 395 TD2_EVLXLT_HASH_KEY_TYPE_L2GRE_VFI_DVP = 6, 396 TD2_EVLXLT_HASH_KEY_TYPE_FCOE_XLATE_DVP = 7, 397 TD2_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI = 8, 398 TD2_EVLXLT_HASH_KEY_TYPE_VXLAN_VFI_DVP = 9, 399 TD2_VELXLT_HASH_KEY_TYPE_COUNT 400 }; 401 402 extern void 403 _soc_trident2_quad_bandwidth_calculate(int unit, int quad, 404 int *max_quad_core_bandwidth, 405 int *quad_linerate_bandwidth, 406 int *quad_oversub_bandwidth); 407 extern int 408 soc_trident2_get_prio_map(int unit, int port, uint16 *pri_mask); 409 410 extern int soc_trident2_hash_bank_count_get(int unit, soc_mem_t mem, 411 int *num_banks); 412 extern int soc_trident2_hash_bank_bitmap_get(int unit, soc_mem_t mem, 413 uint32 *bitmap); 414 extern int soc_trident2_hash_bank_number_get(int unit, soc_mem_t mem, 415 int seq_num, int *bank_num); 416 extern int soc_trident2_hash_seq_number_get(int unit, soc_mem_t mem, 417 int bank_num, int *seq_num); 418 extern int soc_trident2_hash_bank_info_get(int unit, soc_mem_t mem, 419 int bank, 420 int *entries_per_bank, 421 int *entries_per_row, 422 int *entries_per_bucket, 423 int *bank_base, 424 int *bucket_offset); 425 extern int soc_td2_hash_offset_get(int unit, soc_mem_t mem, int bank, 426 int *hash_offset, int *use_lsb); 427 extern uint32 soc_td2_l2x_hash(int unit, int bank, int hash_offset, 428 int use_lsb, int key_nbits, void *base_entry, 429 uint8 *key); 430 extern int soc_td2_l2x_base_entry_to_key(int unit, int bank, uint32 *entry, 431 uint8 *key); 432 extern uint32 soc_td2_l2x_entry_hash(int unit, int bank, int hash_offset, 433 int use_lsb, uint32 *entry); 434 extern uint32 soc_td2_l2x_bank_entry_hash(int unit, int bank, uint32 *entry); 435 extern uint32 soc_td2_l3x_hash(int unit, int bank, int hash_offset, 436 int use_lsb, int key_nbits, void *base_entry, 437 uint8 *key); 438 extern int soc_td2_l3x_base_entry_to_key(int unit, int bank, uint32 *entry, 439 uint8 *key); 440 extern uint32 soc_td2_l3x_entry_hash(int unit, int bank, int hash_offset, 441 int use_lsb, uint32 *entry); 442 extern uint32 soc_td2_l3x_bank_entry_hash(int unit, int bank, uint32 *entry); 443 extern uint32 soc_td2_mpls_hash(int unit, int hash_sel, int key_nbits, 444 void *base_entry, uint8 *key); 445 extern int soc_td2_mpls_base_entry_to_key(int unit, int bank, void *entry, 446 uint8 *key); 447 extern uint32 soc_td2_mpls_entry_hash(int unit, int hash_sel, 448 int bank, uint32 *entry); 449 extern uint32 soc_td2_mpls_bank_entry_hash(int unit, int bank, uint32 *entry); 450 extern uint32 soc_td2_vlan_xlate_hash(int unit, int hash_sel, int key_nbits, 451 void *base_entry, uint8 *key); 452 extern int soc_td2_vlan_xlate_base_entry_to_key(int unit, int bank, 453 void *entry, 454 uint8 *key); 455 extern uint32 soc_td2_vlan_xlate_entry_hash(int unit, int hash_sel, int bank, 456 uint32 *entry); 457 extern uint32 soc_td2_vlan_xlate_bank_entry_hash(int unit, int bank, 458 uint32 *entry); 459 extern uint32 soc_td2_egr_vlan_xlate_hash(int unit, int hash_sel, 460 int key_nbits, void *base_entry, 461 uint8 *key); 462 extern int soc_td2_egr_vlan_xlate_base_entry_to_key(int unit, int bank, 463 void *entry, 464 uint8 *key); 465 extern uint32 soc_td2_egr_vlan_xlate_entry_hash(int unit, 466 int hash_sel, 467 int bank, 468 uint32 *entry); 469 extern uint32 soc_td2_egr_vlan_xlate_bank_entry_hash(int unit, int bank, 470 uint32 *entry); 471 extern uint32 soc_td2_ing_vp_vlan_member_hash(int unit, int hash_sel, 472 int key_nbits, 473 void *base_entry, uint8 *key); 474 extern int soc_td2_ing_vp_vlan_member_base_entry_to_key(int unit, int bank, 475 void *entry, 476 uint8 *key); 477 extern uint32 soc_td2_ing_vp_vlan_member_entry_hash(int unit, int hash_sel, 478 int bank, 479 uint32 *entry); 480 extern uint32 soc_td2_egr_vp_vlan_member_hash(int unit, int hash_sel, 481 int key_nbits, 482 void *base_entry, uint8 *key); 483 extern int soc_td2_egr_vp_vlan_member_base_entry_to_key(int unit, int bank, 484 void *entry, 485 uint8 *key); 486 extern uint32 soc_td2_egr_vp_vlan_member_entry_hash(int unit, int hash_sel, 487 int bank, 488 uint32 *entry); 489 extern uint32 soc_td2_ing_dnat_address_type_hash(int unit, int hash_sel, 490 int key_nbits, 491 void *base_entry, 492 uint8 *key); 493 extern int soc_td2_ing_dnat_address_type_base_entry_to_key(int unit, 494 int bank, 495 void *entry, 496 uint8 *key); 497 extern uint32 soc_td2_ing_dnat_address_type_entry_hash(int unit, 498 int hash_sel, 499 int bank, 500 uint32 *entry); 501 extern uint32 soc_td2_l2_endpoint_id_hash(int unit, int hash_sel, 502 int key_nbits, void *base_entry, 503 uint8 *key); 504 extern int soc_td2_l2_endpoint_id_base_entry_to_key(int unit, int bank, 505 void *entry, 506 uint8 *key); 507 extern uint32 soc_td2_l2_endpoint_id_entry_hash(int unit, 508 int hash_sel, 509 int bank, 510 uint32 *entry); 511 extern uint32 soc_td2_endpoint_queue_map_hash(int unit, int hash_sel, 512 int key_nbits, 513 void *base_entry, 514 uint8 *key); 515 extern int soc_td2_endpoint_queue_map_base_entry_to_key(int unit, 516 int bank, 517 void *entry, 518 uint8 *key); 519 extern uint32 soc_td2_endpoint_queue_map_entry_hash(int unit, 520 int hash_sel, 521 int bank, 522 uint32 *entry); 523 extern int soc_hash_bucket_get(int unit, int mem, int bank, 524 uint32 *entry, uint32 *bucket); 525 extern int soc_hash_index_get(int unit, int mem, int bank, int bucket); 526 527 extern void 528 soc_cm_get_id_otp(int unit, uint16 *dev_id, uint8 *rev_id); 529 530 /* TDM algorithm */ 531 extern int set_tdm_tbl 532 (int speed[130], int tdm_bw, 533 int pgw_tdm_tbl_x0[32], int ovs_tdm_tbl_x0[32], int ovs_spacing_x0[32], 534 int pgw_tdm_tbl_x1[32], int ovs_tdm_tbl_x1[32], int ovs_spacing_x1[32], 535 int pgw_tdm_tbl_y0[32], int ovs_tdm_tbl_y0[32], int ovs_spacing_y0[32], 536 int pgw_tdm_tbl_y1[32], int ovs_tdm_tbl_y1[32], int ovs_spacing_y1[32], 537 int mmu_tdm_tbl_x[256], int mmu_tdm_ovs_x_1[16], int mmu_tdm_ovs_x_2[16], 538 int mmu_tdm_ovs_x_3[16], int mmu_tdm_ovs_x_4[16], 539 int mmu_tdm_tbl_y[256], int mmu_tdm_ovs_y_1[16], int mmu_tdm_ovs_y_2[16], 540 int mmu_tdm_ovs_y_3[16], int mmu_tdm_ovs_y_4[16], 541 int port_state_map[128], 542 int iarb_tdm_tbl_x[512], int iarb_tdm_tbl_y[512]); 543 extern int set_iarb_tdm_table(int core_bw, int is_x_ovs, int is_y_ovs, 544 int mgm4x1, int mgm4x2p5, int mgm1x10, 545 int *iarb_tdm_wrap_ptr_x, 546 int *iarb_tdm_wrap_ptr_y, 547 int iarb_tdm_tbl_x[512], 548 int iarb_tdm_tbl_y[512]); 549 extern int 550 soc_td2_get_def_qbase(int unit, soc_port_t inport, int qtype, 551 int *pbase, int *pnumq); 552 553 #define SOC_TD2_PORT_PIPE(u, p) \ 554 (SOC_PBMP_MEMBER(SOC_INFO(u).xpipe_pbm,(p)) ? 0 : 1) 555 556 extern soc_mem_t 557 _soc_trident2_pmem(int unit, int port, soc_mem_t memx, soc_mem_t memy); 558 559 #define SOC_TD2_PMEM(u,p,m1,m2) _soc_trident2_pmem((u),(p),(m1),(m2)) 560 561 extern soc_reg_t 562 _soc_trident2_preg(int unit, int port, soc_reg_t reg_x, soc_reg_t reg_y); 563 564 #define SOC_TD2_PREG(u,p,m1,m2) _soc_trident2_preg((u),(p),(m1),(m2)) 565 566 extern uint32 _soc_trident2_mmu_port(int unit, int port); 567 568 #define SOC_TD2_MMU_PORT(u, p) _soc_trident2_mmu_port((u),(p)) 569 570 extern uint32 _soc_trident2_piped_mem_index(int unit, soc_port_t port, 571 soc_mem_t mem, int arr_off); 572 573 #define SOC_TD2_MMU_PIPED_MEM_INDEX(u,p,m,off) \ 574 _soc_trident2_piped_mem_index((u),(p),(m),(off)) 575 576 #define _SOC_TD2_NODE_CONFIG_MEM(u,p,n) \ 577 (((n)==SOC_TD2_NODE_LVL_ROOT) ? \ 578 SOC_TD2_PMEM((u),(p),ES_PIPE0_LLS_PORT_MEMA_CONFIGm, \ 579 ES_PIPE1_LLS_PORT_MEMA_CONFIGm) : \ 580 (((n) == SOC_TD2_NODE_LVL_L0) ? \ 581 SOC_TD2_PMEM((u),(p),ES_PIPE0_LLS_L0_MEMA_CONFIGm, \ 582 ES_PIPE1_LLS_L0_MEMA_CONFIGm) : \ 583 ((n) == SOC_TD2_NODE_LVL_L1 ? \ 584 SOC_TD2_PMEM((u),(p),ES_PIPE0_LLS_L1_MEMA_CONFIGm, \ 585 ES_PIPE1_LLS_L1_MEMA_CONFIGm) : -1 ))) 586 587 #define _SOC_TD2_NODE_CONFIG_MEM2(u,p,n) \ 588 (((n)==SOC_TD2_NODE_LVL_ROOT) ? \ 589 SOC_TD2_PMEM((u),(p),ES_PIPE0_LLS_PORT_MEMB_CONFIGm, \ 590 ES_PIPE1_LLS_PORT_MEMB_CONFIGm) : \ 591 (((n) == SOC_TD2_NODE_LVL_L0) ? \ 592 SOC_TD2_PMEM((u),(p),ES_PIPE0_LLS_L0_MEMB_CONFIGm, \ 593 ES_PIPE1_LLS_L0_MEMB_CONFIGm) : \ 594 ((n) == SOC_TD2_NODE_LVL_L1 ? \ 595 SOC_TD2_PMEM((u),(p),ES_PIPE0_LLS_L1_MEMB_CONFIGm, \ 596 ES_PIPE1_LLS_L1_MEMB_CONFIGm) : -1 ))) 597 598 #define _SOC_TD2_NODE_PARENT_MEM(u,p,n) \ 599 (((n)==SOC_TD2_NODE_LVL_L2) ? \ 600 SOC_TD2_PMEM((u),(p), ES_PIPE0_LLS_L2_PARENTm, \ 601 ES_PIPE1_LLS_L2_PARENTm) : \ 602 (((n) == SOC_TD2_NODE_LVL_L1) ? \ 603 SOC_TD2_PMEM((u),(p), ES_PIPE0_LLS_L1_PARENTm, \ 604 ES_PIPE1_LLS_L1_PARENTm) : \ 605 (((n) == SOC_TD2_NODE_LVL_L0) ? \ 606 SOC_TD2_PMEM((u),(p), ES_PIPE0_LLS_L0_PARENTm, \ 607 ES_PIPE1_LLS_L0_PARENTm) : -1 ))) 608 609 #define _SOC_TD2_PIPED_NODE_PARENT_MEM(u,p,n) \ 610 (((n) == SOC_TD2_NODE_LVL_L2) ? \ 611 (p ? ES_PIPE1_LLS_L2_PARENTm: \ 612 ES_PIPE0_LLS_L2_PARENTm) : \ 613 (((n) == SOC_TD2_NODE_LVL_L1) ? \ 614 (p ? ES_PIPE1_LLS_L1_PARENTm: \ 615 ES_PIPE0_LLS_L1_PARENTm) : \ 616 (((n) == SOC_TD2_NODE_LVL_L0) ? \ 617 (p ? ES_PIPE1_LLS_L0_PARENTm: \ 618 ES_PIPE0_LLS_L0_PARENTm) : -1 ))) \ 619 620 #define _SOC_TD2_NODE_WIEGHT_MEM(u,p,n) \ 621 (((n)==SOC_TD2_NODE_LVL_L0) ? \ 622 SOC_TD2_PMEM((u),(p), ES_PIPE0_LLS_L0_CHILD_WEIGHT_CFGm , \ 623 ES_PIPE1_LLS_L0_CHILD_WEIGHT_CFGm) : \ 624 (((n) == SOC_TD2_NODE_LVL_L1) ? \ 625 SOC_TD2_PMEM((u),(p), ES_PIPE0_LLS_L1_CHILD_WEIGHT_CFGm , \ 626 ES_PIPE1_LLS_L1_CHILD_WEIGHT_CFGm) : \ 627 (((n) == SOC_TD2_NODE_LVL_L2) ? \ 628 SOC_TD2_PMEM((u),(p), ES_PIPE0_LLS_L2_CHILD_WEIGHT_CFGm , \ 629 ES_PIPE1_LLS_L2_CHILD_WEIGHT_CFGm) : -1 ))) 630 631 632 typedef enum { 633 SOC_TD2_SCHED_UNKNOWN = 0, 634 SOC_TD2_SCHED_LLS, 635 SOC_TD2_SCHED_HSP 636 } soc_trident2_sched_type_t; 637 638 #ifdef BCM_TRIDENT2PLUS_SUPPORT 639 #define MAX_MMU_OVS_GROUP_COUNT 8 640 #else 641 #define MAX_MMU_OVS_GROUP_COUNT 4 642 #endif /* BCM_TRIDENT2PUS_SUPPORT */ 643 644 #ifdef BCM_TRIDENT2PLUS_SUPPORT 645 typedef soc_reg_t (*mmu_ovs_group_wt_select_regs_t); 646 typedef soc_reg_t (*pgw_ovs_tdm_regs_t); 647 typedef const soc_reg_t (*mmu_ovs_group_regs_t)[MAX_MMU_OVS_GROUP_COUNT]; 648 typedef const soc_reg_t (*pgw_ovs_spacing_regs_t); 649 typedef const soc_reg_t (*pgw_obm_threshold_regs_t); 650 typedef const soc_field_t (*pgw_tdm_fields_t); 651 typedef const soc_field_t (*pgw_spacing_fields_t); 652 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 653 654 655 #if defined BCM_TRIDENT2PLUS_SUPPORT 656 /* logical to IFP port mapping structure */ 657 typedef struct soc_logical_to_ifp_port_mapping_s { 658 int ifp_x_port[_TD2_NUM_LOG_PORTS_PER_DEV]; 659 int ifp_y_port[_TD2_NUM_LOG_PORTS_PER_DEV]; 660 char valid_x[_TD2_NUM_LOG_PORTS_PER_DEV]; 661 char valid_y[_TD2_NUM_LOG_PORTS_PER_DEV]; 662 int last_valid_x_port; 663 int last_valid_y_port; 664 } soc_logical_to_ifp_port_mapping_t; 665 666 extern soc_logical_to_ifp_port_mapping_t soc_td2p_log_to_ifp_port[SOC_MAX_NUM_DEVICES]; 667 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 668 669 extern soc_trident2_sched_type_t 670 _soc_trident2_port_sched_type_get(int unit, soc_port_t port); 671 672 extern int 673 soc_td2_port_common_attributes_get(int unit, int port, int *pipe, 674 int *mmu_port, int *phy_port); 675 extern int 676 _soc_td2_invalid_parent_index(int unit, int level); 677 678 extern int 679 soc_td2_sched_hw_index_get(int unit, int port, int lvl, int offset, 680 int *hw_index); 681 682 extern int soc_td2_l2_hw_index(int unit, int qnum, int uc); 683 extern int soc_td2_hw_index_logical_num(int unit, int port, 684 int index, int uc); 685 extern int 686 soc_td2_cosq_set_sched_child_config(int unit, soc_port_t port, 687 int level, int index, 688 int num_spri, int first_sp_child, 689 int first_sp_mc_child, uint32 ucmap, uint32 spmap); 690 691 extern int 692 soc_td2_cosq_set_sched_mode(int unit, soc_port_t port, int level, int index, 693 soc_td2_sched_mode_e mode, int weight); 694 695 extern int 696 soc_td2_cosq_set_sched_config(int unit, soc_port_t port, 697 int level, int index, int child_index, 698 int num_psri, int first_sp_child, 699 int first_sp_mc_child, uint32 ucmap, uint32 spmap, 700 soc_td2_sched_mode_e mode, int weight); 701 702 extern int 703 soc_td2_cosq_get_sched_child_config(int unit, soc_port_t port, 704 int level, int index, 705 int *pnum_spri, int *pfirst_sp_child, 706 int *pfirst_sp_mc_child, uint32 *pucmap, 707 uint32 *pspmap); 708 709 extern int 710 soc_td2_cosq_get_sched_mode(int unit, soc_port_t port, int level, 711 int index, soc_td2_sched_mode_e *pmode, int *weight); 712 713 extern int 714 soc_td2_cosq_get_sched_config(int unit, soc_port_t port, 715 int level, int index, int child_index, 716 int *num_spri, int *first_sp_child, 717 int *first_sp_mc_child, uint32 *ucmap, 718 uint32 *pspmap, 719 soc_td2_sched_mode_e *mode, int *weight); 720 721 extern int 722 soc_td2_get_child_type(int unit, soc_port_t port, int level, int *child_type); 723 724 extern int 725 soc_td2_sched_weight_get(int unit, int port, int level, int index, int *weight); 726 727 extern int 728 soc_td2_sched_weight_set(int unit, int port, int level, int index, int weight); 729 730 extern int soc_td2_get_pipe_queue_count(int unit, int uc, int xpipe); 731 732 extern int soc_td2_dump_port_lls(int unit, int port); 733 734 extern int soc_td2_dump_port_hsp(int unit, int port); 735 736 extern int soc_td2_lls_init(int unit); 737 738 extern int soc_td2_lls_port_uninit(int unit, soc_port_t port); 739 740 extern int soc_td2_lls_reset(int unit); 741 742 extern int soc_td2_lls_reset_port(int unit, int port); 743 744 extern int soc_td2_cosq_set_sched_parent(int unit, soc_port_t port, 745 int level, int hw_index, 746 int parent_hw_idx); 747 748 extern int soc_td2_logical_qnum_hw_qnum(int unit, int port, int lqnum, int uc); 749 750 extern int soc_td2_mmu_get_shared_size(int unit, int *shared_size); 751 extern int soc_td2_mmu_config_shared_buf_recalc(int unit, 752 uint32 spid, 753 int shared_size, 754 int flags); 755 extern int soc_td2_mmu_config_res_limits_update(int unit, 756 uint32 spid, 757 uint32 shared_size, 758 int flags); 759 760 extern void soc_td2_process_func_intr(void *unit_vp, void *d1, void *d2, 761 void *d3, void *d4); 762 763 typedef int (*_soc_td2_bst_hw_cb)(int unit); 764 extern int soc_td2_set_bst_callback(int unit, _soc_td2_bst_hw_cb cb); 765 typedef int (*soc_bst_intr_check_cb)(int unit); 766 extern int soc_td2_set_bst_intr_check_callback(int unit, soc_bst_intr_check_cb cb); 767 768 extern int soc_td2_port_asf_para_set(int unit, soc_port_t port, int speed, 769 int enable); 770 extern int soc_trident2_port_speed_update(int unit, soc_port_t port, 771 int speed); 772 extern int soc_td2_port_asf_set(int unit, soc_port_t port, 773 int speed); 774 extern int soc_trident2_port_thdo_rx_enable_set(int unit, soc_port_t port, 775 int enable); 776 777 extern int soc_trident2_fc_map_shadow_create(int unit); 778 extern void soc_trident2_fc_map_shadow_free(int unit); 779 extern int 780 soc_trident2_fc_map_shadow_entry_set (int unit, soc_mem_t mem, int index, 781 void* entry_data); 782 extern int 783 soc_trident2_fc_map_shadow_entry_get (int unit, soc_mem_t mem, int index, 784 void* entry_data); 785 extern int soc_trident2_fc_map_shadow_clear (int unit, soc_mem_t mem); 786 extern int soc_td2_port_traffic_egr_enable_set(int unit, int port, int enable); 787 extern int soc_td2_port_mmu_tx_enable_set(int unit, int port, int enable); 788 extern int soc_td2_is_skip_default_lls_creation(int unit); 789 790 extern int soc_td2_mmu_rx_enable_set(int unit, soc_port_t port, int enable); 791 792 extern int soc_td2_qcn_counter_hw_index_get(int unit, soc_port_t port, 793 int index, int *qindex); 794 extern void soc_td2p_subport_init(int unit); 795 796 #ifdef BCM_WARM_BOOT_SUPPORT 797 extern int soc_trident2_fc_map_shadow_size_get (int unit, uint32* size); 798 extern int soc_trident2_fc_map_shadow_sync(int unit, uint32 **sync_addr); 799 extern int soc_trident2_fc_map_shadow_load(int unit, uint32 **load_addr); 800 #endif 801 802 #if defined(SER_TR_TEST_SUPPORT) 803 extern soc_error_t soc_td2_ser_inject_error(int unit, uint32 flags, 804 soc_mem_t mem, int pipe_target, 805 int block, int index); 806 extern soc_error_t soc_td2_ser_test_mem(int unit, soc_mem_t mem, 807 _soc_ser_test_t test_type, int cmd); 808 extern soc_error_t soc_td2_ser_test(int unit, _soc_ser_test_t test_type); 809 extern soc_error_t soc_td2_ser_error_injection_support(int unit, 810 soc_mem_t mem, int pipe); 811 extern int soc_td2_ser_test_overlay (int unit, _soc_ser_test_t test_type); 812 #endif /*#if defined(SER_TR_TEST_SUPPORT)*/ 813 extern int soc_td2_reg_cpu_write_control(int unit, int enable); 814 extern int soc_td2_is_blk_valid(int unit, int blk); 815 extern int 816 soc_trident2_mem_parity_control(int unit, soc_mem_t mem, int copyno, 817 int enable); 818 819 typedef int (*_soc_td2_lls_traverse_cb)(int unit, int port, int level, 820 int hw_index, void *cookie); 821 extern int soc_td2_port_lls_traverse(int unit, soc_port_t port, 822 _soc_td2_lls_traverse_cb cb, void *cookie); 823 int 824 extern soc_td2_cosq_set_sched_child_config_dynamic(int unit, soc_port_t port, 825 int level, int index, 826 int num_spri, int first_child, 827 int first_mc_child, uint32 ucmap, 828 uint32 spmap, int child_index); 829 830 extern int 831 soc_trident2_port_sched_set(int unit, soc_port_t port); 832 833 extern int 834 soc_td2_obm_ctrl_reg_default_set (int unit, int xlp, int port_index, int obm_inst, 835 int oversub, int default_flag); 836 extern int 837 soc_td2_obm_use_counter_reg_default_set (int unit, int xlp, int port_index, 838 int obm_inst); 839 extern int 840 soc_td2_obm_shared_config_reg_default_set (int unit, int xlp, int port_index, 841 int obm_inst, int default_flag); 842 extern int 843 soc_td2_obm_max_usage_reg_default_set (int unit, int xlp, int port_index, 844 int obm_inst); 845 extern int 846 soc_td2_obm_fc_config_reg_default_set (int unit, int xlp, int port_index, 847 int obm_inst, int logical_port, 848 int oversub, int default_flag); 849 extern int 850 soc_td2_obm_counters_reset(int unit, soc_port_t port); 851 #ifdef BCM_TRIDENT2PLUS_SUPPORT 852 extern mmu_ovs_group_regs_t 853 soc_trident2_mmu_ovs_group_regs_get (int unit); 854 855 extern mmu_ovs_group_wt_select_regs_t 856 soc_trident2_mmu_ovs_group_wt_select_regs_get (int unit); 857 858 extern pgw_ovs_tdm_regs_t 859 soc_trident2_pgw_ovs_tdm_regs_get (int unit); 860 861 extern pgw_ovs_spacing_regs_t 862 soc_trident2_pgw_ovs_spacing_regs_get (int unit); 863 864 extern pgw_obm_threshold_regs_t 865 soc_trident2_pgw_obm_threshold_regs_get (int unit); 866 867 extern pgw_tdm_fields_t 868 soc_trident2_pgw_tdm_fields_get (int unit); 869 870 extern pgw_spacing_fields_t 871 soc_trident2_pgw_spacing_fields_get (int unit); 872 873 extern int 874 ser_test_trident2p_mem_index_remap(int unit, ser_test_data_t *test_data, 875 int *mem_has_ecc); 876 extern int 877 soc_trident2p_mem_is_eligible_for_scan(int unit, soc_mem_t mem); 878 #endif /* BCM_TRIDENT2PLUS_SUPPORT */ 879 880 extern int 881 soc_trident2_port_icc_width_set(int unit, soc_port_t port); 882 883 extern int 884 soc_trident2_ser_test_skip_check(int unit, soc_mem_t mem, 885 soc_acc_type_t acc_type); 886 extern int 887 soc_td2x_ser_single_bit_error_enable_set(int unit, int enable); 888 889 extern int 890 soc_td2x_ser_single_bit_error_enable_get(int unit, int *enable); 891 892 extern int 893 soc_td2p_ledup_port_update(int unit, soc_port_t port, uint8 attach); 894 #endif /* !_SOC_TRIDENT2_H_ */